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###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor             : Xilinx
## \   \   \/     Version            : 2.3
##  \   \         Application        : MIG
##  /   /         Filename           : vcs_run.sh
## /___/   /\     Date Last Modified : $Date: 2011/06/02 08:31:17 $
## \   \  /  \    Date Created       : Tue Oct 29 2013
##  \___\/\___\
##
## Device           : 7 Series
## Purpose          :
##                   Sample vcs_run.sh file to compile and simulate memory interface
##                   design and run the simulation for specified period of time.
##                   Display the waveforms that are listed with "add wave" command.
## Assumptions      :
##                   Simulation takes place in \sim folder of MIG output directory.
## Reference        :
## Revision History :
###############################################################################

#echo Simulation Tool: VCS

#Compile the required libraries here#
#libraries path#

#Compile all modules#
vhdlan ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.vhd > vcs_sim.log
vhdlan ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.vhd >> vcs_sim.log
vhdlan ../../../sources_1/imports/rtl/*.vhd >> vcs_sim.log
vlogan -sverilog ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/clocking/*.v >> vcs_sim.log
vlogan -sverilog ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/*.v >> vcs_sim.log
vlogan -sverilog ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ecc/*.v >> vcs_sim.log
vlogan -sverilog ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ip_top/*.v >> vcs_sim.log
vlogan -sverilog ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/*.v >> vcs_sim.log
vlogan -sverilog ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ui/*.v >> vcs_sim.log
vlogan -sverilog ../../../sources_1/imports/rtl/traffic_gen/*.v >> vcs_sim.log


vhdlan ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/*.vhd >> vcs_sim.log

#Compile files in sim folder (excluding model parameter file)#
#$XILINX variable must be set
vlogan $XILINX_VIVADO/data/verilog/src/glbl.v >> vcs_sim.log
vlogan -sverilog wiredly.v >> vcs_sim.log
vlogan -sverilog sim_tb_top.v >> vcs_sim.log

#Pass the parameters for memory model parameter file#
vlogan -Xcheck_p1800_2009=char -sverilog +define+x1Gb +define+sg15E +define+x8 ddr3_model.sv >> vcs_sim.log 

#Simulate the design with sim_tb_top as the top module
vcs -R -debug_pp -lca sim_tb_top glbl >> vcs_sim.log
#echo done
