// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date        : Tue Jan 30 11:58:23 2018
// Host        : L1 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim {C:/Users/Alain/Documents/1VHDL/com1800template
//               003a/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_7series_0_funcsim.v}
// Design      : mig_7series_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a100tfgg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* NotValidForBitStream *)
module mig_7series_0
   (ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    ddr3_addr,
    ddr3_ba,
    ddr3_ras_n,
    ddr3_cas_n,
    ddr3_we_n,
    ddr3_reset_n,
    ddr3_ck_p,
    ddr3_ck_n,
    ddr3_cke,
    ddr3_cs_n,
    ddr3_dm,
    ddr3_odt,
    app_addr,
    app_cmd,
    app_en,
    app_wdf_data,
    app_wdf_end,
    app_wdf_mask,
    app_wdf_wren,
    app_rd_data,
    app_rd_data_end,
    app_rd_data_valid,
    app_rdy,
    app_wdf_rdy,
    app_sr_req,
    app_ref_req,
    app_zq_req,
    app_sr_active,
    app_ref_ack,
    app_zq_ack,
    ui_clk,
    ui_clk_sync_rst,
    init_calib_complete,
    sys_clk_i,
    clk_ref_i,
    sys_rst);
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output ddr3_ras_n;
  output ddr3_cas_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [0:0]ddr3_ck_p;
  output [0:0]ddr3_ck_n;
  output [0:0]ddr3_cke;
  output [0:0]ddr3_cs_n;
  output [7:0]ddr3_dm;
  output [0:0]ddr3_odt;
  input [27:0]app_addr;
  input [2:0]app_cmd;
  input app_en;
  input [511:0]app_wdf_data;
  input app_wdf_end;
  input [63:0]app_wdf_mask;
  input app_wdf_wren;
  output [511:0]app_rd_data;
  output app_rd_data_end;
  output app_rd_data_valid;
  output app_rdy;
  output app_wdf_rdy;
  input app_sr_req;
  input app_ref_req;
  input app_zq_req;
  output app_sr_active;
  output app_ref_ack;
  output app_zq_ack;
  output ui_clk;
  output ui_clk_sync_rst;
  output init_calib_complete;
  input sys_clk_i;
  input clk_ref_i;
  input sys_rst;

  wire [27:0]app_addr;
  wire [2:0]app_cmd;
  wire app_en;
  wire [511:0]app_rd_data;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_rdy;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire clk_ref_i;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_ck_n;
  wire [0:0]ddr3_ck_p;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  (* IBUF_LOW_PWR = 0 *) wire [63:0]ddr3_dq;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [7:0]ddr3_dqs_n;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  (* DRIVE = "12" *) wire ddr3_reset_n;
  wire ddr3_we_n;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 ;
  wire init_calib_complete;
  wire sys_clk_i;
  wire sys_rst;
  wire [49:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address ;
  wire [11:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank ;
  wire [2:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n ;
  wire [3:3]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ;
  wire [2:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n ;
  wire [0:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n ;
  wire [2:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n ;
  wire [511:32]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata ;
  wire [63:4]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask ;
  (* RTL_KEEP = "true" *) wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_complete_r_timing ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ;
  wire [63:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [65:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ;
  wire [59:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [79:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ;
  wire [63:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [65:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ;
  wire [79:8]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [79:6]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ;
  wire [71:8]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [71:6]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ;
  wire u_mig_7series_0_mig_n_14;
  wire u_mig_7series_0_mig_n_15;
  wire u_mig_7series_0_mig_n_17;
  wire u_mig_7series_0_mig_n_18;
  wire u_mig_7series_0_mig_n_20;
  wire u_mig_7series_0_mig_n_21;
  wire u_mig_7series_0_mig_n_7;
  wire u_mig_7series_0_mig_n_8;
  wire ui_clk;
  wire ui_clk_sync_rst;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED ;

  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [1:0]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [3:2]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [5:4]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:2]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [5:4]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [13:12]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [15:14]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [13:12]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:14]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [17:16]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [19:18]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [21:20]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [19:18]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [21:20]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [25:24]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [27:26]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [29:28]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [31:30]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [33:32]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [31:30]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [35:34]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [37:36]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [39:38]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [39:38]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [41:40]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [43:42]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [45:44]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [47:46]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [49:48]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [51:50]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [53:52]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [55:54]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [57:56]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [59:58]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [61:60]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [63:62]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [61:60]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [63:62]),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [7:6]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [9:8]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [11:10]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [7:6]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [11:10]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [103],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [39]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [231],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [167]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [359],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [295]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [358],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [294]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [486],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [422]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [101],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [37]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [229],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [165]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [357],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [293]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [485],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [421]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [100],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [36]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [228],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [164]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [356],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [292]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [484],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [420]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [99],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [35]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [227],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [163]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [355],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [291]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [483],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [419]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [98],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [34]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [226],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [162]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [354],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [290]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [482],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [418]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [97],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [33]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [225],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [161]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [353],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [289]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [481],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [417]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [96],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [32]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [224],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [160]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [352],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [288]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [480],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [416]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [487],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [423]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [102],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [38]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [230],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [166]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [12],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [4]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [28],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [20]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [44],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [36]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 }),
        .DOB({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 }),
        .DOC({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 }),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [60],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [52]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 }),
        .DOB(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [3:2]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:4]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke }),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke }),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [29:28]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [39:38]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [41:40]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b1,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n [1:0]),
        .DIC({1'b1,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n [2]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [47:46]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n [1:0]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [53:52]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b1,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n [2]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:58]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt }),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt }),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [11:10]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n ),
        .DIB({1'b1,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [3:2]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:4]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [1]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [13:12]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [15:14]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [17:16]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [10],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [7]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [19:18]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [21:20]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [23:22]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [2]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [11],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [8]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [29:28]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [14],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [0]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [42],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [28]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [31:30]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:34]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [15],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [1]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [39:38]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [41:40]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [43],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [29]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [16],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [2]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [44],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [30]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:46]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [18],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [4]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [46],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [32]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [3]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [53:52]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [45],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [31]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [19],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [5]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [47],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [33]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [59:58]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [20],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [6]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [61:60]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:62]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [65:64]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [48],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [34]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:66]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [69:68]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [71:70]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [0]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [9],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [6]}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [11:10]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [21],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [7]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [49],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [35]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [73:72]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:74]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:76]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [79:78]),
        .DOB(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [1:0]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [3:2]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [5:4]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:2]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [5:4]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [13:12]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [15:14]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [13:12]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:14]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [17:16]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [19:18]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [21:20]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [19:18]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [21:20]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [25:24]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [27:26]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [29:28]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [31:30]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [33:32]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [31:30]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [35:34]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [37:36]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [39:38]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [39:38]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [41:40]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [43:42]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [45:44]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [47:46]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [49:48]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [51:50]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [53:52]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [55:54]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [57:56]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [59:58]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [61:60]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [63:62]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [61:60]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [63:62]),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [7:6]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [9:8]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r [11:10]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [7:6]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [11:10]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [127],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [63]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [255],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [191]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [383],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [319]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [382],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [318]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [510],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [446]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [125],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [61]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [253],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [189]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [381],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [317]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [509],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [445]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [124],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [60]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [252],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [188]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [380],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [316]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [508],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [444]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [123],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [59]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [251],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [187]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [379],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [315]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [507],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [443]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [122],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [58]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [250],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [186]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [378],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [314]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [506],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [442]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [121],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [57]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [249],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [185]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [377],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [313]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [505],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [441]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [120],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [56]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [248],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [184]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [376],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [312]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [504],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [440]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [511],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [447]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [126],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [62]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [254],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [190]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [15],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [7]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [31],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [23]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [47],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [39]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [63],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [55]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 }),
        .DOB(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [13:12]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [15:14]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [13:12]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [15:14]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [17:16]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [19:18]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [21:20]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [19:18]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [21:20]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [23:22]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [25:24]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [27:26]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [29:28]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [31:30]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [33:32]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [31:30]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:34]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [37:36]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [39:38]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [39:38]),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [49:48]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [51:50]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [53:52]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [55:54]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [57:56]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:58]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [61:60]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [63:62]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [61:60]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [63:62]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [65:64]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [67:66]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [69:68]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [71:70]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [67:66]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [69:68]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [71:70]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [7:6]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [9:8]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [11:10]),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1 }),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [11:10]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [73:72]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [75:74]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [77:76]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [73:72]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [75:74]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [77:76]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [79:78]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [79:78]),
        .DOB(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [375],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [311]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [503],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [439]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [118],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [54]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [246],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [182]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [374],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [310]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [502],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [438]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [117],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [53]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [245],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [181]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [373],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [309]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [501],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [437]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [116],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [52]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [244],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [180]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [372],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [308]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [500],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [436]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [14],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [6]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [30],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [22]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [46],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [38]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [62],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [54]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [115],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [51]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [243],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [179]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [371],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [307]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [499],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [435]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [114],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [50]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [242],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [178]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [370],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [306]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [498],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [434]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [113],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [49]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [241],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [177]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [369],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [305]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [497],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [433]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [119],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [55]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [247],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [183]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [112],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [48]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [240],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [176]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [368],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [304]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [496],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [432]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 }),
        .DOB(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [13:12]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [15:14]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [13:12]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [15:14]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [17:16]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [19:18]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [21:20]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [19:18]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [21:20]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [23:22]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [25:24]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [27:26]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [29:28]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [31:30]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [33:32]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [31:30]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:34]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [37:36]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [39:38]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [39:38]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [41:40]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [43:42]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [45:44]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:46]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [49:48]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [51:50]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [53:52]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [55:54]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [57:56]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [59:58]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [61:60]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [63:62]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [61:60]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:62]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [65:64]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [67:66]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [69:68]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [71:70]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:66]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [69:68]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [71:70]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11 
       (.ADDRA({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRB({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRC({1'b0,1'b0,1'b0,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [7:6]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [9:8]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [11:10]),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1 }),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [11:10]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [367],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [303]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [495],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [431]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [110],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [46]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [238],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [174]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [366],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [302]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [494],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [430]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [109],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [45]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [237],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [173]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [365],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [301]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [493],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [429]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [108],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [44]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [236],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [172]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [364],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [300]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [492],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [428]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [107],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [43]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [235],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [171]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [363],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [299]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [491],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [427]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [106],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [42]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [234],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [170]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [362],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [298]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [490],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [426]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [105],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [41]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [233],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [169]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [361],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [297]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [489],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [425]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [104],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [40]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [232],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [168]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [360],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [296]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [488],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [424]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [111],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [47]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [239],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [175]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [13],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [5]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [29],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [21]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [45],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [37]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 }),
        .DOB({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 }),
        .DOC({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 }),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  RAM32M \ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [61],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [53]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 }),
        .DOB(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  mig_7series_0_mig_7series_0_mig u_mig_7series_0_mig
       (.A_rst_primitives_reg(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .A_rst_primitives_reg_0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .A_rst_primitives_reg_1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .A_rst_primitives_reg_2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .A_rst_primitives_reg_3(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .A_rst_primitives_reg_4(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .A_rst_primitives_reg_5(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .A_rst_primitives_reg_6(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .Q(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ),
        .app_addr(app_addr[26:0]),
        .app_cmd(app_cmd[1:0]),
        .app_en(app_en),
        .app_rd_data(app_rd_data),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rdy(app_rdy),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .clk_ref_i(clk_ref_i),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out({ddr3_ck_n,ddr3_ck_p}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [79:48],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [39:8]}),
        .init_calib_complete(init_calib_complete),
        .init_complete_r_timing(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_complete_r_timing ),
        .init_complete_r_timing_reg(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_complete_r_timing ),
        .iserdes_clk(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .iserdes_clk_0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .iserdes_clk_1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .iserdes_clk_2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .iserdes_clk_3(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .iserdes_clk_4(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .iserdes_clk_5(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .iserdes_clk_6(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .mem_out(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ),
        .\my_empty_reg[7] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ),
        .\my_empty_reg[7]_0 ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [511:480],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [447:416],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [383:352],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [319:288],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [255:224],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [191:160],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [127:96],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [63:32]}),
        .\my_empty_reg[7]_1 ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [63:60],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [55:52],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [47:44],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [39:36],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [31:28],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [23:20],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [15:12],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata_mask [7:4]}),
        .\my_empty_reg[7]_2 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ),
        .\my_empty_reg[7]_3 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ),
        .\my_empty_reg[7]_4 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ),
        .\not_strict_mode.app_rd_data_reg[232] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ),
        .\not_strict_mode.app_rd_data_reg[376] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ),
        .\not_strict_mode.app_rd_data_reg[488] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ),
        .\not_strict_mode.app_rd_data_reg[496] ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [79:48],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r [41:6]}),
        .\not_strict_mode.app_rd_data_reg[496]_0 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ),
        .out({u_mig_7series_0_mig_n_7,u_mig_7series_0_mig_n_8}),
        .p_0_in1_in(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ),
        .phy_dout({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt }),
        .\rd_ptr_reg_rep[3] ({\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ,\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 }),
        .\rd_ptr_reg_rep[3]_0 ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:36],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [29:24],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [11:0]}),
        .\rd_ptr_reg_rep[3]_1 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ),
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,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ,\ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 }),
        .\rd_ptr_timing_reg[1] ({u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_15}),
        .\rd_ptr_timing_reg[1]_0 ({u_mig_7series_0_mig_n_17,u_mig_7series_0_mig_n_18}),
        .\rd_ptr_timing_reg[1]_1 ({u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_21}),
        .sys_clk_i(sys_clk_i),
        .sys_rst(sys_rst),
        .ui_clk(ui_clk),
        .ui_clk_sync_rst(ui_clk_sync_rst),
        .wr_en(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_en_10(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_en_11(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_en_12(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_en_13(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_en_14(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_ptr(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ),
        .wr_ptr_7(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ),
        .wr_ptr_8(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ),
        .wr_ptr_9(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ),
        .\wr_ptr_timing_reg[0] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ),
        .\wr_ptr_timing_reg[0]_0 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr ),
        .\wr_ptr_timing_reg[0]_1 ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [49],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [35],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [21],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [7],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [48],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [34],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [20],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [6],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [47],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [33],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [19],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [5],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [45],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [31],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [3],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [46],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [32],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [18],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [4],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [44],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [30],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [16],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [2],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [43],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [29],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [15],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [1],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [42],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [28],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [14],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [0],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [11],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [8],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [2],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [10],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [7],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [1],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [9],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [6],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [0],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n }),
        .\wr_ptr_timing_reg[3] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .\wr_ptr_timing_reg[3]_0 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .\wr_ptr_timing_reg[3]_1 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .\wr_ptr_timing_reg[3]_2 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .\wr_ptr_timing_reg[3]_3 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .\wr_ptr_timing_reg[3]_4 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ));
endmodule

(* ORIG_REF_NAME = "mig_7series_0_mig" *) 
module mig_7series_0_mig_7series_0_mig
   (ui_clk,
    app_ref_ack,
    app_zq_ack,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_reset_n,
    out,
    iserdes_clk,
    iserdes_clk_0,
    iserdes_clk_1,
    iserdes_clk_2,
    iserdes_clk_3,
    \rd_ptr_timing_reg[1] ,
    iserdes_clk_4,
    \rd_ptr_timing_reg[1]_0 ,
    iserdes_clk_5,
    \rd_ptr_timing_reg[1]_1 ,
    iserdes_clk_6,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    init_complete_r_timing,
    init_calib_complete,
    app_sr_active,
    app_rdy,
    app_wdf_rdy,
    app_rd_data_valid,
    app_rd_data_end,
    ui_clk_sync_rst,
    Q,
    \not_strict_mode.app_rd_data_reg[488] ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \not_strict_mode.app_rd_data_reg[376] ,
    wr_ptr,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7] ,
    \wr_ptr_timing_reg[3]_0 ,
    \wr_ptr_timing_reg[0] ,
    \wr_ptr_timing_reg[3]_1 ,
    \wr_ptr_timing_reg[0]_0 ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    wr_ptr_7,
    \wr_ptr_timing_reg[3]_2 ,
    \my_empty_reg[7]_2 ,
    wr_ptr_8,
    \wr_ptr_timing_reg[3]_3 ,
    \my_empty_reg[7]_3 ,
    wr_ptr_9,
    \wr_ptr_timing_reg[3]_4 ,
    \my_empty_reg[7]_4 ,
    app_rd_data,
    p_0_in1_in,
    \not_strict_mode.app_rd_data_reg[232] ,
    \not_strict_mode.app_rd_data_reg[496]_0 ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    phy_dout,
    \wr_ptr_timing_reg[0]_1 ,
    wr_en,
    wr_en_10,
    wr_en_11,
    wr_en_12,
    wr_en_13,
    wr_en_14,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    init_complete_r_timing_reg,
    app_en,
    clk_ref_i,
    app_wdf_end,
    app_wdf_wren,
    app_ref_req,
    app_zq_req,
    app_sr_req,
    mem_out,
    sys_rst,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    app_addr,
    app_cmd,
    app_wdf_data,
    app_wdf_mask,
    sys_clk_i,
    \rd_ptr_reg_rep[3] ,
    \rd_ptr_reg_rep[3]_0 ,
    \rd_ptr_reg_rep[3]_1 ,
    \rd_ptr_reg_rep[3]_2 ,
    \rd_ptr_reg_rep[3]_3 ,
    \rd_ptr_reg_rep[3]_4 );
  output ui_clk;
  output app_ref_ack;
  output app_zq_ack;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [1:0]out;
  output iserdes_clk;
  output iserdes_clk_0;
  output iserdes_clk_1;
  output iserdes_clk_2;
  output iserdes_clk_3;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output iserdes_clk_4;
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output iserdes_clk_5;
  output [1:0]\rd_ptr_timing_reg[1]_1 ;
  output iserdes_clk_6;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output init_complete_r_timing;
  output init_calib_complete;
  output app_sr_active;
  output app_rdy;
  output app_wdf_rdy;
  output app_rd_data_valid;
  output app_rd_data_end;
  output ui_clk_sync_rst;
  output [65:0]Q;
  output [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  output [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output [1:0]wr_ptr;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7] ;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\wr_ptr_timing_reg[0] ;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  output [255:0]\my_empty_reg[7]_0 ;
  output [31:0]\my_empty_reg[7]_1 ;
  output [1:0]wr_ptr_7;
  output [3:0]\wr_ptr_timing_reg[3]_2 ;
  output [3:0]\my_empty_reg[7]_2 ;
  output [1:0]wr_ptr_8;
  output [3:0]\wr_ptr_timing_reg[3]_3 ;
  output [3:0]\my_empty_reg[7]_3 ;
  output [1:0]wr_ptr_9;
  output [3:0]\wr_ptr_timing_reg[3]_4 ;
  output [3:0]\my_empty_reg[7]_4 ;
  output [511:0]app_rd_data;
  output p_0_in1_in;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \not_strict_mode.app_rd_data_reg[496]_0 ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output [10:0]phy_dout;
  output [45:0]\wr_ptr_timing_reg[0]_1 ;
  output wr_en;
  output wr_en_10;
  output wr_en_11;
  output wr_en_12;
  output wr_en_13;
  output wr_en_14;
  output [1:0]ddr_ck_out;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input A_rst_primitives_reg_1;
  input A_rst_primitives_reg_2;
  input A_rst_primitives_reg_3;
  input A_rst_primitives_reg_4;
  input A_rst_primitives_reg_5;
  input A_rst_primitives_reg_6;
  input init_complete_r_timing_reg;
  input app_en;
  input clk_ref_i;
  input app_wdf_end;
  input app_wdf_wren;
  input app_ref_req;
  input app_zq_req;
  input app_sr_req;
  input [63:0]mem_out;
  input sys_rst;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input [26:0]app_addr;
  input [1:0]app_cmd;
  input [511:0]app_wdf_data;
  input [63:0]app_wdf_mask;
  input sys_clk_i;
  input [79:0]\rd_ptr_reg_rep[3] ;
  input [41:0]\rd_ptr_reg_rep[3]_0 ;
  input [79:0]\rd_ptr_reg_rep[3]_1 ;
  input [79:0]\rd_ptr_reg_rep[3]_2 ;
  input [79:0]\rd_ptr_reg_rep[3]_3 ;
  input [79:0]\rd_ptr_reg_rep[3]_4 ;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire [65:0]Q;
  wire [26:0]app_addr;
  wire [1:0]app_cmd;
  wire app_en;
  wire [511:0]app_rd_data;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_rdy;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire clk_ref_i;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire freq_refclk;
  wire init_calib_complete;
  wire init_complete_r_timing;
  wire init_complete_r_timing_reg;
  wire [0:0]iodelay_ctrl_rdy;
  wire iserdes_clk;
  wire iserdes_clk_0;
  wire iserdes_clk_1;
  wire iserdes_clk_2;
  wire iserdes_clk_3;
  wire iserdes_clk_4;
  wire iserdes_clk_5;
  wire iserdes_clk_6;
  wire [11:0]\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row0_rd_done1 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cnt_shift_r0 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/idelay_tap_limit_r0 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pi_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire mmcm_clk;
  wire [3:0]\my_empty_reg[7] ;
  wire [255:0]\my_empty_reg[7]_0 ;
  wire [31:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_2 ;
  wire [3:0]\my_empty_reg[7]_3 ;
  wire [3:0]\my_empty_reg[7]_4 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  wire [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  wire \not_strict_mode.app_rd_data_reg[496]_0 ;
  wire [1:0]out;
  wire p_0_in1_in;
  wire [10:0]phy_dout;
  wire pll_lock;
  wire [79:0]\rd_ptr_reg_rep[3] ;
  wire [41:0]\rd_ptr_reg_rep[3]_0 ;
  wire [79:0]\rd_ptr_reg_rep[3]_1 ;
  wire [79:0]\rd_ptr_reg_rep[3]_2 ;
  wire [79:0]\rd_ptr_reg_rep[3]_3 ;
  wire [79:0]\rd_ptr_reg_rep[3]_4 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rd_ptr_timing_reg[1]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1]_1 ;
  wire rstdiv0_sync_r1;
  wire sync_pulse;
  wire sys_clk_i;
  wire sys_rst;
  wire sys_rst_act_hi;
  wire u_ddr3_infrastructure_n_10;
  wire u_ddr3_infrastructure_n_11;
  wire u_ddr3_infrastructure_n_12;
  wire u_ddr3_infrastructure_n_13;
  wire u_ddr3_infrastructure_n_14;
  wire u_ddr3_infrastructure_n_15;
  wire u_ddr3_infrastructure_n_16;
  wire u_ddr3_infrastructure_n_17;
  wire u_ddr3_infrastructure_n_18;
  wire u_ddr3_infrastructure_n_19;
  wire u_ddr3_infrastructure_n_20;
  wire u_ddr3_infrastructure_n_21;
  wire u_ddr3_infrastructure_n_22;
  wire u_ddr3_infrastructure_n_23;
  wire u_ddr3_infrastructure_n_24;
  wire u_ddr3_infrastructure_n_25;
  wire u_ddr3_infrastructure_n_26;
  wire u_ddr3_infrastructure_n_27;
  wire u_ddr3_infrastructure_n_28;
  wire u_ddr3_infrastructure_n_29;
  wire u_ddr3_infrastructure_n_30;
  wire u_ddr3_infrastructure_n_31;
  wire u_ddr3_infrastructure_n_32;
  wire u_ddr3_infrastructure_n_33;
  wire u_ddr3_infrastructure_n_34;
  wire u_ddr3_infrastructure_n_35;
  wire u_ddr3_infrastructure_n_37;
  wire u_ddr3_infrastructure_n_38;
  wire u_ddr3_infrastructure_n_39;
  wire u_ddr3_infrastructure_n_4;
  wire u_ddr3_infrastructure_n_40;
  wire u_ddr3_infrastructure_n_42;
  wire u_ddr3_infrastructure_n_44;
  wire u_ddr3_infrastructure_n_45;
  wire u_ddr3_infrastructure_n_7;
  wire u_ddr3_infrastructure_n_8;
  wire u_ddr3_infrastructure_n_9;
  wire u_memc_ui_top_std_n_134;
  wire u_memc_ui_top_std_n_335;
  wire u_memc_ui_top_std_n_56;
  wire u_memc_ui_top_std_n_64;
  wire u_memc_ui_top_std_n_67;
  wire ui_clk;
  wire ui_clk_sync_rst;
  wire wr_en;
  wire wr_en_10;
  wire wr_en_11;
  wire wr_en_12;
  wire wr_en_13;
  wire wr_en_14;
  wire [1:0]wr_ptr;
  wire [1:0]wr_ptr_7;
  wire [1:0]wr_ptr_8;
  wire [1:0]wr_ptr_9;
  wire [3:0]\wr_ptr_timing_reg[0] ;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;
  wire [45:0]\wr_ptr_timing_reg[0]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3]_3 ;
  wire [3:0]\wr_ptr_timing_reg[3]_4 ;

  mig_7series_0_mig_7series_v2_3_tempmon \temp_mon_enabled.u_tempmon 
       (.CLK(ui_clk),
        .D(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),
        .clk_ref_i(clk_ref_i),
        .rstdiv0_sync_r1(rstdiv0_sync_r1));
  mig_7series_0_mig_7series_v2_3_clk_ibuf u_ddr3_clk_ibuf
       (.mmcm_clk(mmcm_clk),
        .sys_clk_i(sys_clk_i));
  mig_7series_0_mig_7series_v2_3_infrastructure u_ddr3_infrastructure
       (.ADDRA(u_ddr3_infrastructure_n_34),
        .AS(sys_rst_act_hi),
        .CLK(ui_clk),
        .D(u_ddr3_infrastructure_n_35),
        .SR(u_ddr3_infrastructure_n_10),
        .SS(u_ddr3_infrastructure_n_42),
        .act_wait_r_lcl_reg(u_ddr3_infrastructure_n_37),
        .act_wait_r_lcl_reg_0(u_ddr3_infrastructure_n_38),
        .act_wait_r_lcl_reg_1(u_ddr3_infrastructure_n_39),
        .act_wait_r_lcl_reg_2(u_ddr3_infrastructure_n_40),
        .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_2(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),
        .cal2_if_reset_reg(u_ddr3_infrastructure_n_11),
        .\cnt_shift_r_reg[0] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cnt_shift_r0 ),
        .\complex_address_reg[0] (u_ddr3_infrastructure_n_12),
        .\complex_num_writes_dec_reg[0] (u_ddr3_infrastructure_n_30),
        .complex_row0_rd_done1(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row0_rd_done1 ),
        .\corse_cnt_reg[0][1] (u_ddr3_infrastructure_n_16),
        .\corse_inc_reg[7][1] (u_ddr3_infrastructure_n_15),
        .\device_temp_init_reg[0] (u_ddr3_infrastructure_n_23),
        .\fine_inc_reg[7][4] ({u_ddr3_infrastructure_n_13,u_ddr3_infrastructure_n_14}),
        .freq_refclk(freq_refclk),
        .\idelay_tap_cnt_slice_r_reg[2] (u_memc_ui_top_std_n_335),
        .\last_master_r_reg[0] (u_ddr3_infrastructure_n_29),
        .\maint_controller.maint_wip_r_lcl_reg (u_ddr3_infrastructure_n_28),
        .\maintenance_request.maint_sre_r_lcl_reg (u_ddr3_infrastructure_n_27),
        .\maintenance_request.maint_zq_r_lcl_reg (u_ddr3_infrastructure_n_26),
        .mem_refclk(mem_refclk),
        .mmcm_clk(mmcm_clk),
        .\neutral_min_limit_reg[0] (u_ddr3_infrastructure_n_22),
        .new_cnt_cpt_r_reg(u_memc_ui_top_std_n_64),
        .\one_dec_max_limit_reg[11] (u_ddr3_infrastructure_n_25),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg (u_ddr3_infrastructure_n_9),
        .\periodic_read_request.periodic_rd_r_cnt_reg (u_ddr3_infrastructure_n_8),
        .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pi_cnt_dec ),
        .pll_lock(pll_lock),
        .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),
        .prbs_rdlvl_done_pulse(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ({u_ddr3_infrastructure_n_19,u_ddr3_infrastructure_n_20}),
        .rdlvl_stg1_start_reg(u_memc_ui_top_std_n_56),
        .\read_fifo.head_r_reg[0] (u_ddr3_infrastructure_n_7),
        .\read_fifo.tail_r_reg[2] (u_memc_ui_top_std_n_67),
        .reset_reg(u_ddr3_infrastructure_n_32),
        .\rst_ref_sync_r_reg[0][14] (u_memc_ui_top_std_n_134),
        .rst_sync_r1_reg_0(u_ddr3_infrastructure_n_4),
        .rst_sync_r1_reg_1(u_ddr3_infrastructure_n_33),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),
        .\samp_edge_cnt0_r_reg[0] (u_ddr3_infrastructure_n_44),
        .\smallest_reg[7][2] ({u_ddr3_infrastructure_n_17,u_ddr3_infrastructure_n_18}),
        .\stable_pass_cnt_reg[0] (u_ddr3_infrastructure_n_21),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/idelay_tap_limit_r0 ),
        .\three_inc_min_limit_reg[11] (u_ddr3_infrastructure_n_24),
        .ui_clk_sync_rst(ui_clk_sync_rst),
        .\wait_cnt_r_reg[0] (u_ddr3_infrastructure_n_45),
        .\wait_cnt_reg[0] (u_ddr3_infrastructure_n_31));
  mig_7series_0_mig_7series_v2_3_iodelay_ctrl u_iodelay_ctrl
       (.AS(sys_rst_act_hi),
        .clk_ref_i(clk_ref_i),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .sys_rst(sys_rst));
  (* CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v2_3,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=3000, PHY_RATIO=4, CLKIN_PERIOD=3000, VCCAUX_IO=1.8V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8jsf12864hz-1g4, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=NO_BUFFER}" *) 
  (* X_CORE_INFO = "mig_7series_v2_3_ddr3_7Series, 2013.4" *) 
  mig_7series_0_mig_7series_v2_3_memc_ui_top_std u_memc_ui_top_std
       (.ADDRA(u_ddr3_infrastructure_n_34),
        .A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .CLK(ui_clk),
        .D(u_ddr3_infrastructure_n_35),
        .E(app_rdy),
        .Q(Q),
        .SR(u_ddr3_infrastructure_n_16),
        .SS(u_ddr3_infrastructure_n_42),
        .app_addr(app_addr),
        .app_cmd(app_cmd),
        .app_en(app_en),
        .app_rd_data(app_rd_data),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_2(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),
        .complex_row0_rd_done1(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row0_rd_done1 ),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\device_temp_r_reg[11] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (iserdes_clk),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (iserdes_clk_0),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (iserdes_clk_1),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (iserdes_clk_2),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (iserdes_clk_3),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (iserdes_clk_4),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (iserdes_clk_5),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (iserdes_clk_6),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .freq_refclk(freq_refclk),
        .\idelay_tap_cnt_r_reg[0][7][3] (u_memc_ui_top_std_n_335),
        .idelay_tap_limit_r_reg(u_memc_ui_top_std_n_64),
        .init_calib_complete(init_calib_complete),
        .init_complete_r_timing(init_complete_r_timing),
        .init_complete_r_timing_reg(init_complete_r_timing_reg),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_1 ),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376] ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[488] (\not_strict_mode.app_rd_data_reg[488] ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496] ),
        .\not_strict_mode.app_rd_data_reg[496]_0 (\not_strict_mode.app_rd_data_reg[496]_0 ),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .phy_dout(phy_dout),
        .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pi_cnt_dec ),
        .pll_lock(pll_lock),
        .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),
        .prbs_rdlvl_done_pulse(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] ),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3]_0 ),
        .\rd_ptr_reg_rep[3]_1 (\rd_ptr_reg_rep[3]_1 ),
        .\rd_ptr_reg_rep[3]_2 (\rd_ptr_reg_rep[3]_2 ),
        .\rd_ptr_reg_rep[3]_3 (\rd_ptr_reg_rep[3]_3 ),
        .\rd_ptr_reg_rep[3]_4 (\rd_ptr_reg_rep[3]_4 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1]_0 ),
        .\rd_ptr_timing_reg[1]_1 (\rd_ptr_timing_reg[1]_1 ),
        .rdlvl_stg1_start_r_reg(u_memc_ui_top_std_n_56),
        .\read_fifo.fifo_out_data_r_reg[5] (u_memc_ui_top_std_n_67),
        .rst_sync_r1_reg(u_memc_ui_top_std_n_134),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep(u_ddr3_infrastructure_n_7),
        .rstdiv0_sync_r1_reg_rep__0(u_ddr3_infrastructure_n_8),
        .rstdiv0_sync_r1_reg_rep__1(u_ddr3_infrastructure_n_9),
        .rstdiv0_sync_r1_reg_rep__10({u_ddr3_infrastructure_n_18,u_ddr3_infrastructure_n_20}),
        .rstdiv0_sync_r1_reg_rep__12(u_ddr3_infrastructure_n_19),
        .rstdiv0_sync_r1_reg_rep__13(u_ddr3_infrastructure_n_21),
        .rstdiv0_sync_r1_reg_rep__14(u_ddr3_infrastructure_n_22),
        .rstdiv0_sync_r1_reg_rep__15(u_ddr3_infrastructure_n_23),
        .rstdiv0_sync_r1_reg_rep__16(u_ddr3_infrastructure_n_24),
        .rstdiv0_sync_r1_reg_rep__17(u_ddr3_infrastructure_n_25),
        .rstdiv0_sync_r1_reg_rep__18(u_ddr3_infrastructure_n_26),
        .rstdiv0_sync_r1_reg_rep__19(u_ddr3_infrastructure_n_27),
        .rstdiv0_sync_r1_reg_rep__2(u_ddr3_infrastructure_n_10),
        .rstdiv0_sync_r1_reg_rep__20(u_ddr3_infrastructure_n_28),
        .rstdiv0_sync_r1_reg_rep__20_0(u_ddr3_infrastructure_n_38),
        .rstdiv0_sync_r1_reg_rep__20_1(u_ddr3_infrastructure_n_37),
        .rstdiv0_sync_r1_reg_rep__20_2(u_ddr3_infrastructure_n_39),
        .rstdiv0_sync_r1_reg_rep__20_3(u_ddr3_infrastructure_n_40),
        .rstdiv0_sync_r1_reg_rep__21(u_ddr3_infrastructure_n_29),
        .rstdiv0_sync_r1_reg_rep__22(u_ddr3_infrastructure_n_30),
        .rstdiv0_sync_r1_reg_rep__23(u_ddr3_infrastructure_n_31),
        .rstdiv0_sync_r1_reg_rep__24(u_ddr3_infrastructure_n_32),
        .rstdiv0_sync_r1_reg_rep__24_0(u_ddr3_infrastructure_n_44),
        .rstdiv0_sync_r1_reg_rep__24_1(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/idelay_tap_limit_r0 ),
        .rstdiv0_sync_r1_reg_rep__24_2(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cnt_shift_r0 ),
        .rstdiv0_sync_r1_reg_rep__24_3(u_ddr3_infrastructure_n_45),
        .rstdiv0_sync_r1_reg_rep__3(u_ddr3_infrastructure_n_11),
        .rstdiv0_sync_r1_reg_rep__4(u_ddr3_infrastructure_n_12),
        .rstdiv0_sync_r1_reg_rep__6(u_ddr3_infrastructure_n_15),
        .rstdiv0_sync_r1_reg_rep__7({u_ddr3_infrastructure_n_13,u_ddr3_infrastructure_n_14}),
        .rstdiv0_sync_r1_reg_rep__9(u_ddr3_infrastructure_n_17),
        .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst),
        .sys_rst_0(u_ddr3_infrastructure_n_33),
        .sys_rst_1(u_ddr3_infrastructure_n_4),
        .wr_en(wr_en),
        .wr_en_10(wr_en_10),
        .wr_en_11(wr_en_11),
        .wr_en_12(wr_en_12),
        .wr_en_13(wr_en_13),
        .wr_en_14(wr_en_14),
        .\wr_ptr_reg[0] (wr_ptr_7[0]),
        .\wr_ptr_reg[0]_0 (wr_ptr_8[0]),
        .\wr_ptr_reg[0]_1 (wr_ptr_9[0]),
        .\wr_ptr_reg[1] (wr_ptr[0]),
        .\wr_ptr_reg[1]_0 (wr_ptr[1]),
        .\wr_ptr_reg[1]_1 (wr_ptr_7[1]),
        .\wr_ptr_reg[1]_2 (wr_ptr_8[1]),
        .\wr_ptr_reg[1]_3 (wr_ptr_9[1]),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_1 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3]_0 ),
        .\wr_ptr_timing_reg[3]_1 (\wr_ptr_timing_reg[3]_1 ),
        .\wr_ptr_timing_reg[3]_2 (\wr_ptr_timing_reg[3]_2 ),
        .\wr_ptr_timing_reg[3]_3 (\wr_ptr_timing_reg[3]_3 ),
        .\wr_ptr_timing_reg[3]_4 (\wr_ptr_timing_reg[3]_4 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_arb_mux" *) 
module mig_7series_0_mig_7series_v2_3_arb_mux
   (\cmd_pipe_plus.mc_cmd_reg[0] ,
    \cmd_pipe_plus.mc_cs_n_reg[0] ,
    cs_en2,
    DIC,
    col_rd_wr_r,
    \col_mux.col_rd_wr_r_reg ,
    cke_r,
    \rnk_config_r_reg[0] ,
    \cmd_pipe_plus.mc_ras_n_reg[1] ,
    Q,
    granted_col_r_reg,
    granted_col_r_reg_0,
    override_demand_ns,
    \grant_r_reg[2] ,
    \grant_r_reg[1] ,
    E,
    D,
    \grant_r_reg[0] ,
    \grant_r_reg[0]_0 ,
    granted_col_r_reg_1,
    \last_master_r_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[0] ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    \cmd_pipe_plus.wr_data_en_reg ,
    \wtr_timer.wtr_cnt_r_reg[0] ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[1]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    read_this_rank,
    int_read_this_rank,
    granted_col_r_reg_2,
    mc_odt_ns,
    col_data_buf_addr,
    sre_clears_sre_request,
    \last_master_r_reg[2] ,
    \last_master_r_reg[0] ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    mc_cas_n_ns,
    mc_ras_n_ns,
    act_this_rank,
    \grant_r_reg[1]_2 ,
    mc_cs_n_ns,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    granted_row_ns,
    CLK,
    rnk_config_strobe_ns,
    granted_col_ns,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    granted_pre_ns,
    rstdiv0_sync_r1_reg_rep__1,
    mc_cke_ns,
    rstdiv0_sync_r1_reg_rep__18,
    p_14_out,
    demand_priority_r_reg,
    \order_q_r_reg[0] ,
    ofs_rdy_r,
    demand_priority_r_reg_0,
    col_wait_r,
    col_wait_r_reg,
    col_wait_r_reg_0,
    demand_priority_r_reg_1,
    col_wait_r_0,
    \order_q_r_reg[0]_0 ,
    p_92_out,
    rd_wr_r_lcl_reg,
    idle_r_lcl_reg,
    p_131_out,
    ofs_rdy_r_1,
    ofs_rdy_r_2,
    \grant_r_reg[3] ,
    ofs_rdy_r_3,
    rstdiv0_sync_r1_reg_rep__20,
    rstdiv0_sync_r1_reg_rep__21,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_row_r_lcl_reg[13] ,
    \req_row_r_lcl_reg[13]_0 ,
    mc_cmd,
    rstdiv0_sync_r1_reg_rep__24,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    col_wait_r_reg_1,
    col_wait_r_reg_2,
    demand_act_priority_r_reg,
    rd_this_rank_r,
    read_this_rank_r,
    rd_wr_r_lcl_reg_0,
    rd_wr_r_lcl_reg_1,
    col_wait_r_reg_3,
    rd_wr_r_lcl_reg_2,
    col_wait_r_reg_4,
    rstdiv0_sync_r1_reg_rep__19,
    col_wait_r_reg_5,
    p_53_out,
    p_71_out,
    p_32_out,
    p_110_out,
    p_149_out,
    \req_data_buf_addr_r_reg[4] ,
    \req_data_buf_addr_r_reg[4]_0 ,
    maint_sre_r,
    auto_pre_r_lcl_reg,
    auto_pre_r_lcl_reg_0,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    auto_pre_r_lcl_reg_1,
    ras_timer_zero_r_reg_2,
    auto_pre_r_lcl_reg_2,
    p_115_out,
    maint_zq_r,
    p_154_out,
    act_wait_r_lcl_reg,
    demand_act_priority_r_reg_0,
    demand_act_priority_r,
    head_r_lcl_reg,
    act_wait_r_lcl_reg_0,
    demand_act_priority_r_4,
    head_r_lcl_reg_0,
    act_wait_r_lcl_reg_1,
    inhbt_act_faw_r,
    demand_act_priority_r_5,
    \grant_r_reg[0]_1 ,
    head_r_lcl_reg_1,
    p_76_out,
    p_37_out,
    wr_this_rank_r,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \req_col_r_reg[9] ,
    \req_col_r_reg[9]_0 ,
    \req_col_r_reg[9]_1 ,
    \req_col_r_reg[9]_2 ,
    auto_pre_r,
    auto_pre_r_6,
    auto_pre_r_7,
    auto_pre_r_8,
    \req_data_buf_addr_r_reg[4]_1 ,
    \req_data_buf_addr_r_reg[4]_2 ,
    col_wr_data_buf_addr_r,
    maint_srx_r,
    act_this_rank_r,
    demand_act_priority_r_9,
    maint_rank_r,
    \req_row_r_lcl_reg[13]_1 ,
    \req_row_r_lcl_reg[13]_2 );
  output \cmd_pipe_plus.mc_cmd_reg[0] ;
  output \cmd_pipe_plus.mc_cs_n_reg[0] ;
  output cs_en2;
  output [0:0]DIC;
  output col_rd_wr_r;
  output \col_mux.col_rd_wr_r_reg ;
  output cke_r;
  output \rnk_config_r_reg[0] ;
  output \cmd_pipe_plus.mc_ras_n_reg[1] ;
  output [3:0]Q;
  output granted_col_r_reg;
  output granted_col_r_reg_0;
  output override_demand_ns;
  output \grant_r_reg[2] ;
  output \grant_r_reg[1] ;
  output [0:0]E;
  output [2:0]D;
  output \grant_r_reg[0] ;
  output \grant_r_reg[0]_0 ;
  output granted_col_r_reg_1;
  output [3:0]\last_master_r_reg[3] ;
  output [3:0]\cmd_pipe_plus.mc_we_n_reg[0] ;
  output [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  output \cmd_pipe_plus.wr_data_en_reg ;
  output \wtr_timer.wtr_cnt_r_reg[0] ;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[1]_1 ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  output read_this_rank;
  output int_read_this_rank;
  output granted_col_r_reg_2;
  output [0:0]mc_odt_ns;
  output [4:0]col_data_buf_addr;
  output sre_clears_sre_request;
  output \last_master_r_reg[2] ;
  output \last_master_r_reg[0] ;
  output [37:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [0:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output act_this_rank;
  output \grant_r_reg[1]_2 ;
  output [0:0]mc_cs_n_ns;
  output \cmd_pipe_plus.mc_bank_reg[2] ;
  input granted_row_ns;
  input CLK;
  input rnk_config_strobe_ns;
  input granted_col_ns;
  input \generate_maint_cmds.insert_maint_r_lcl_reg ;
  input granted_pre_ns;
  input rstdiv0_sync_r1_reg_rep__1;
  input [0:0]mc_cke_ns;
  input rstdiv0_sync_r1_reg_rep__18;
  input p_14_out;
  input demand_priority_r_reg;
  input \order_q_r_reg[0] ;
  input ofs_rdy_r;
  input demand_priority_r_reg_0;
  input col_wait_r;
  input col_wait_r_reg;
  input col_wait_r_reg_0;
  input demand_priority_r_reg_1;
  input col_wait_r_0;
  input \order_q_r_reg[0]_0 ;
  input p_92_out;
  input rd_wr_r_lcl_reg;
  input idle_r_lcl_reg;
  input p_131_out;
  input ofs_rdy_r_1;
  input ofs_rdy_r_2;
  input \grant_r_reg[3] ;
  input ofs_rdy_r_3;
  input rstdiv0_sync_r1_reg_rep__20;
  input rstdiv0_sync_r1_reg_rep__21;
  input [2:0]\req_bank_r_lcl_reg[2] ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [13:0]\req_row_r_lcl_reg[13] ;
  input [12:0]\req_row_r_lcl_reg[13]_0 ;
  input [0:0]mc_cmd;
  input rstdiv0_sync_r1_reg_rep__24;
  input [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;
  input col_wait_r_reg_1;
  input col_wait_r_reg_2;
  input demand_act_priority_r_reg;
  input [3:0]rd_this_rank_r;
  input read_this_rank_r;
  input rd_wr_r_lcl_reg_0;
  input rd_wr_r_lcl_reg_1;
  input col_wait_r_reg_3;
  input rd_wr_r_lcl_reg_2;
  input col_wait_r_reg_4;
  input rstdiv0_sync_r1_reg_rep__19;
  input col_wait_r_reg_5;
  input p_53_out;
  input p_71_out;
  input p_32_out;
  input p_110_out;
  input p_149_out;
  input [4:0]\req_data_buf_addr_r_reg[4] ;
  input [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  input maint_sre_r;
  input auto_pre_r_lcl_reg;
  input auto_pre_r_lcl_reg_0;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input auto_pre_r_lcl_reg_1;
  input ras_timer_zero_r_reg_2;
  input auto_pre_r_lcl_reg_2;
  input p_115_out;
  input maint_zq_r;
  input p_154_out;
  input act_wait_r_lcl_reg;
  input demand_act_priority_r_reg_0;
  input demand_act_priority_r;
  input head_r_lcl_reg;
  input act_wait_r_lcl_reg_0;
  input demand_act_priority_r_4;
  input head_r_lcl_reg_0;
  input act_wait_r_lcl_reg_1;
  input inhbt_act_faw_r;
  input demand_act_priority_r_5;
  input \grant_r_reg[0]_1 ;
  input head_r_lcl_reg_1;
  input p_76_out;
  input p_37_out;
  input [3:0]wr_this_rank_r;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [2:0]\req_bank_r_lcl_reg[2]_2 ;
  input [9:0]\req_col_r_reg[9] ;
  input [9:0]\req_col_r_reg[9]_0 ;
  input [9:0]\req_col_r_reg[9]_1 ;
  input [9:0]\req_col_r_reg[9]_2 ;
  input auto_pre_r;
  input auto_pre_r_6;
  input auto_pre_r_7;
  input auto_pre_r_8;
  input [4:0]\req_data_buf_addr_r_reg[4]_1 ;
  input [4:0]\req_data_buf_addr_r_reg[4]_2 ;
  input [4:0]col_wr_data_buf_addr_r;
  input maint_srx_r;
  input [3:0]act_this_rank_r;
  input demand_act_priority_r_9;
  input maint_rank_r;
  input [13:0]\req_row_r_lcl_reg[13]_1 ;
  input [12:0]\req_row_r_lcl_reg[13]_2 ;

  wire CLK;
  wire [2:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [3:0]Q;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r;
  wire auto_pre_r_6;
  wire auto_pre_r_7;
  wire auto_pre_r_8;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire cke_r;
  wire [37:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire \cmd_pipe_plus.mc_bank_reg[2] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire \cmd_pipe_plus.mc_cmd_reg[0] ;
  wire \cmd_pipe_plus.mc_cs_n_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_ras_n_reg[1] ;
  wire [3:0]\cmd_pipe_plus.mc_we_n_reg[0] ;
  wire \cmd_pipe_plus.wr_data_en_reg ;
  wire [4:0]col_data_buf_addr;
  wire \col_mux.col_rd_wr_r_reg ;
  wire col_periodic_rd_r;
  wire col_rd_wr_r;
  wire col_wait_r;
  wire col_wait_r_0;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire col_wait_r_reg_2;
  wire col_wait_r_reg_3;
  wire col_wait_r_reg_4;
  wire col_wait_r_reg_5;
  wire [4:0]col_wr_data_buf_addr_r;
  wire cs_en2;
  wire demand_act_priority_r;
  wire demand_act_priority_r_4;
  wire demand_act_priority_r_5;
  wire demand_act_priority_r_9;
  wire demand_act_priority_r_reg;
  wire demand_act_priority_r_reg_0;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[3] ;
  wire granted_col_ns;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire granted_pre_ns;
  wire granted_row_ns;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire idle_r_lcl_reg;
  wire inhbt_act_faw_r;
  wire int_read_this_rank;
  wire \last_master_r_reg[0] ;
  wire \last_master_r_reg[2] ;
  wire [3:0]\last_master_r_reg[3] ;
  wire maint_rank_r;
  wire maint_sre_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire mc_aux_out_r;
  wire mc_aux_out_r0;
  wire [0:0]mc_cas_n_ns;
  wire [0:0]mc_cke_ns;
  wire [0:0]mc_cmd;
  wire [0:0]mc_cs_n_ns;
  wire [0:0]mc_odt_ns;
  wire [1:0]mc_ras_n_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_1;
  wire ofs_rdy_r_2;
  wire ofs_rdy_r_3;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[0]_0 ;
  wire override_demand_ns;
  wire p_110_out;
  wire p_115_out;
  wire p_131_out;
  wire p_149_out;
  wire p_14_out;
  wire p_154_out;
  wire p_32_out;
  wire p_37_out;
  wire p_53_out;
  wire p_71_out;
  wire p_76_out;
  wire p_92_out;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire [3:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire read_this_rank;
  wire read_this_rank_r;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [9:0]\req_col_r_reg[9]_2 ;
  wire [4:0]\req_data_buf_addr_r_reg[4] ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_1 ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_2 ;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [12:0]\req_row_r_lcl_reg[13]_0 ;
  wire [13:0]\req_row_r_lcl_reg[13]_1 ;
  wire [12:0]\req_row_r_lcl_reg[13]_2 ;
  wire rnk_config_r;
  wire \rnk_config_r_reg[0] ;
  wire rnk_config_strobe_ns;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire sre_clears_sre_request;
  wire [3:0]wr_this_rank_r;
  wire \wtr_timer.wtr_cnt_r_reg[0] ;
  wire [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;

  mig_7series_0_mig_7series_v2_3_arb_row_col arb_row_col0
       (.CLK(CLK),
        .D(D),
        .DIC(DIC),
        .E(E),
        .Q(Q),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .auto_pre_r(auto_pre_r),
        .auto_pre_r_6(auto_pre_r_6),
        .auto_pre_r_7(auto_pre_r_7),
        .auto_pre_r_8(auto_pre_r_8),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2] ),
        .\cmd_pipe_plus.mc_cmd_reg[0] (\cmd_pipe_plus.mc_cmd_reg[0] ),
        .\cmd_pipe_plus.mc_cs_n_reg[0] (\cmd_pipe_plus.mc_cs_n_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[1] (\cmd_pipe_plus.mc_ras_n_reg[1] ),
        .\cmd_pipe_plus.mc_we_n_reg[0] (\cmd_pipe_plus.mc_we_n_reg[0] ),
        .col_data_buf_addr(col_data_buf_addr),
        .\col_mux.col_rd_wr_r_reg (\col_mux.col_rd_wr_r_reg ),
        .col_periodic_rd_r(col_periodic_rd_r),
        .col_rd_wr_r(col_rd_wr_r),
        .col_wait_r(col_wait_r),
        .col_wait_r_0(col_wait_r_0),
        .col_wait_r_reg(col_wait_r_reg),
        .col_wait_r_reg_0(col_wait_r_reg_0),
        .col_wait_r_reg_1(col_wait_r_reg_1),
        .col_wait_r_reg_2(col_wait_r_reg_2),
        .col_wait_r_reg_3(col_wait_r_reg_3),
        .col_wait_r_reg_4(col_wait_r_reg_4),
        .col_wait_r_reg_5(col_wait_r_reg_5),
        .col_wr_data_buf_addr_r(col_wr_data_buf_addr_r),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_4(demand_act_priority_r_4),
        .demand_act_priority_r_5(demand_act_priority_r_5),
        .demand_act_priority_r_9(demand_act_priority_r_9),
        .demand_act_priority_r_reg(demand_act_priority_r_reg),
        .demand_act_priority_r_reg_0(demand_act_priority_r_reg_0),
        .demand_priority_r_reg(demand_priority_r_reg),
        .demand_priority_r_reg_0(demand_priority_r_reg_0),
        .demand_priority_r_reg_1(demand_priority_r_reg_1),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ),
        .\grant_r_reg[1]_2 (\grant_r_reg[1]_2 ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[3] (\grant_r_reg[3] ),
        .granted_col_ns(granted_col_ns),
        .granted_col_r_reg_0(granted_col_r_reg),
        .granted_col_r_reg_1(granted_col_r_reg_0),
        .granted_col_r_reg_2(granted_col_r_reg_1),
        .granted_col_r_reg_3(granted_col_r_reg_2),
        .granted_pre_ns(granted_pre_ns),
        .granted_row_ns(granted_row_ns),
        .head_r_lcl_reg(head_r_lcl_reg),
        .head_r_lcl_reg_0(head_r_lcl_reg_0),
        .head_r_lcl_reg_1(head_r_lcl_reg_1),
        .idle_r_lcl_reg(idle_r_lcl_reg),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .int_read_this_rank(int_read_this_rank),
        .\last_master_r_reg[0] (cs_en2),
        .\last_master_r_reg[2] ({\last_master_r_reg[2] ,\last_master_r_reg[0] }),
        .\last_master_r_reg[3] (\last_master_r_reg[3] ),
        .maint_rank_r(maint_rank_r),
        .maint_sre_r(maint_sre_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_aux_out_r(mc_aux_out_r),
        .mc_aux_out_r0(mc_aux_out_r0),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_cs_n_ns(mc_cs_n_ns),
        .mc_odt_ns(mc_odt_ns),
        .mc_ras_n_ns(mc_ras_n_ns),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r_1(ofs_rdy_r_1),
        .ofs_rdy_r_2(ofs_rdy_r_2),
        .ofs_rdy_r_3(ofs_rdy_r_3),
        .\order_q_r_reg[0] (\order_q_r_reg[0] ),
        .\order_q_r_reg[0]_0 (\order_q_r_reg[0]_0 ),
        .override_demand_ns(override_demand_ns),
        .p_110_out(p_110_out),
        .p_115_out(p_115_out),
        .p_131_out(p_131_out),
        .p_149_out(p_149_out),
        .p_14_out(p_14_out),
        .p_154_out(p_154_out),
        .p_32_out(p_32_out),
        .p_37_out(p_37_out),
        .p_53_out(p_53_out),
        .p_71_out(p_71_out),
        .p_76_out(p_76_out),
        .p_92_out(p_92_out),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_2),
        .read_this_rank(read_this_rank),
        .read_this_rank_r(read_this_rank_r),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ),
        .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ),
        .\req_col_r_reg[9] (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9]_0 ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_1 ),
        .\req_col_r_reg[9]_2 (\req_col_r_reg[9]_2 ),
        .\req_data_buf_addr_r_reg[4] (\req_data_buf_addr_r_reg[4] ),
        .\req_data_buf_addr_r_reg[4]_0 (\req_data_buf_addr_r_reg[4]_0 ),
        .\req_data_buf_addr_r_reg[4]_1 (\req_data_buf_addr_r_reg[4]_1 ),
        .\req_data_buf_addr_r_reg[4]_2 (\req_data_buf_addr_r_reg[4]_2 ),
        .\req_row_r_lcl_reg[13] (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13]_0 ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_1 ),
        .\req_row_r_lcl_reg[13]_2 (\req_row_r_lcl_reg[13]_2 ),
        .rnk_config_r(rnk_config_r),
        .\rnk_config_r_reg[0] (\rnk_config_r_reg[0] ),
        .rnk_config_strobe_ns(rnk_config_strobe_ns),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .sre_clears_sre_request(sre_clears_sre_request),
        .wr_this_rank_r(wr_this_rank_r),
        .\wtr_timer.wtr_cnt_r_reg[0] (\wtr_timer.wtr_cnt_r_reg[0] ),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ));
  mig_7series_0_mig_7series_v2_3_arb_select arb_select0
       (.CLK(CLK),
        .DIC(DIC),
        .cke_r(cke_r),
        .\cmd_pipe_plus.wr_data_en_reg (\cmd_pipe_plus.wr_data_en_reg ),
        .col_periodic_rd_r(col_periodic_rd_r),
        .col_rd_wr_r(col_rd_wr_r),
        .\grant_r_reg[2] (\rnk_config_r_reg[0] ),
        .\grant_r_reg[3] (\col_mux.col_rd_wr_r_reg ),
        .mc_aux_out_r(mc_aux_out_r),
        .mc_aux_out_r0(mc_aux_out_r0),
        .mc_cke_ns(mc_cke_ns),
        .mc_cmd(mc_cmd),
        .rnk_config_r(rnk_config_r),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_arb_row_col" *) 
module mig_7series_0_mig_7series_v2_3_arb_row_col
   (\cmd_pipe_plus.mc_cmd_reg[0] ,
    \cmd_pipe_plus.mc_cs_n_reg[0] ,
    \last_master_r_reg[0] ,
    \cmd_pipe_plus.mc_ras_n_reg[1] ,
    Q,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    \rnk_config_r_reg[0] ,
    override_demand_ns,
    \grant_r_reg[2] ,
    \grant_r_reg[1] ,
    E,
    \col_mux.col_rd_wr_r_reg ,
    D,
    \grant_r_reg[0] ,
    \grant_r_reg[0]_0 ,
    granted_col_r_reg_2,
    \last_master_r_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[0] ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    \wtr_timer.wtr_cnt_r_reg[0] ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[1]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    read_this_rank,
    int_read_this_rank,
    granted_col_r_reg_3,
    mc_odt_ns,
    mc_aux_out_r0,
    DIC,
    col_data_buf_addr,
    sre_clears_sre_request,
    \last_master_r_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    mc_cas_n_ns,
    mc_ras_n_ns,
    act_this_rank,
    \grant_r_reg[1]_2 ,
    mc_cs_n_ns,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    granted_row_ns,
    CLK,
    rnk_config_strobe_ns,
    granted_col_ns,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    granted_pre_ns,
    rstdiv0_sync_r1_reg_rep__18,
    p_14_out,
    demand_priority_r_reg,
    \order_q_r_reg[0] ,
    ofs_rdy_r,
    demand_priority_r_reg_0,
    col_wait_r,
    col_wait_r_reg,
    col_wait_r_reg_0,
    demand_priority_r_reg_1,
    col_wait_r_0,
    \order_q_r_reg[0]_0 ,
    p_92_out,
    rd_wr_r_lcl_reg,
    idle_r_lcl_reg,
    p_131_out,
    col_rd_wr_r,
    ofs_rdy_r_1,
    ofs_rdy_r_2,
    \grant_r_reg[3] ,
    ofs_rdy_r_3,
    rstdiv0_sync_r1_reg_rep__20,
    rstdiv0_sync_r1_reg_rep__21,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_row_r_lcl_reg[13] ,
    \req_row_r_lcl_reg[13]_0 ,
    rnk_config_r,
    rstdiv0_sync_r1_reg_rep__24,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    col_wait_r_reg_1,
    col_wait_r_reg_2,
    demand_act_priority_r_reg,
    rd_this_rank_r,
    read_this_rank_r,
    rd_wr_r_lcl_reg_0,
    rd_wr_r_lcl_reg_1,
    col_wait_r_reg_3,
    rd_wr_r_lcl_reg_2,
    col_wait_r_reg_4,
    rstdiv0_sync_r1_reg_rep__19,
    col_wait_r_reg_5,
    mc_aux_out_r,
    p_53_out,
    p_71_out,
    p_32_out,
    p_110_out,
    col_periodic_rd_r,
    p_149_out,
    \req_data_buf_addr_r_reg[4] ,
    \req_data_buf_addr_r_reg[4]_0 ,
    maint_sre_r,
    auto_pre_r_lcl_reg,
    auto_pre_r_lcl_reg_0,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    auto_pre_r_lcl_reg_1,
    ras_timer_zero_r_reg_2,
    auto_pre_r_lcl_reg_2,
    p_115_out,
    maint_zq_r,
    p_154_out,
    act_wait_r_lcl_reg,
    demand_act_priority_r_reg_0,
    demand_act_priority_r,
    head_r_lcl_reg,
    act_wait_r_lcl_reg_0,
    demand_act_priority_r_4,
    head_r_lcl_reg_0,
    act_wait_r_lcl_reg_1,
    inhbt_act_faw_r,
    demand_act_priority_r_5,
    \grant_r_reg[0]_1 ,
    head_r_lcl_reg_1,
    p_76_out,
    p_37_out,
    wr_this_rank_r,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \req_col_r_reg[9] ,
    \req_col_r_reg[9]_0 ,
    \req_col_r_reg[9]_1 ,
    \req_col_r_reg[9]_2 ,
    auto_pre_r,
    auto_pre_r_6,
    auto_pre_r_7,
    auto_pre_r_8,
    \req_data_buf_addr_r_reg[4]_1 ,
    \req_data_buf_addr_r_reg[4]_2 ,
    col_wr_data_buf_addr_r,
    maint_srx_r,
    act_this_rank_r,
    demand_act_priority_r_9,
    maint_rank_r,
    \req_row_r_lcl_reg[13]_1 ,
    \req_row_r_lcl_reg[13]_2 );
  output \cmd_pipe_plus.mc_cmd_reg[0] ;
  output \cmd_pipe_plus.mc_cs_n_reg[0] ;
  output \last_master_r_reg[0] ;
  output \cmd_pipe_plus.mc_ras_n_reg[1] ;
  output [3:0]Q;
  output granted_col_r_reg_0;
  output granted_col_r_reg_1;
  output \rnk_config_r_reg[0] ;
  output override_demand_ns;
  output \grant_r_reg[2] ;
  output \grant_r_reg[1] ;
  output [0:0]E;
  output \col_mux.col_rd_wr_r_reg ;
  output [2:0]D;
  output \grant_r_reg[0] ;
  output \grant_r_reg[0]_0 ;
  output granted_col_r_reg_2;
  output [3:0]\last_master_r_reg[3] ;
  output [3:0]\cmd_pipe_plus.mc_we_n_reg[0] ;
  output [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  output \wtr_timer.wtr_cnt_r_reg[0] ;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[1]_1 ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  output read_this_rank;
  output int_read_this_rank;
  output granted_col_r_reg_3;
  output [0:0]mc_odt_ns;
  output mc_aux_out_r0;
  output [0:0]DIC;
  output [4:0]col_data_buf_addr;
  output sre_clears_sre_request;
  output [1:0]\last_master_r_reg[2] ;
  output [37:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [0:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output act_this_rank;
  output \grant_r_reg[1]_2 ;
  output [0:0]mc_cs_n_ns;
  output \cmd_pipe_plus.mc_bank_reg[2] ;
  input granted_row_ns;
  input CLK;
  input rnk_config_strobe_ns;
  input granted_col_ns;
  input \generate_maint_cmds.insert_maint_r_lcl_reg ;
  input granted_pre_ns;
  input rstdiv0_sync_r1_reg_rep__18;
  input p_14_out;
  input demand_priority_r_reg;
  input \order_q_r_reg[0] ;
  input ofs_rdy_r;
  input demand_priority_r_reg_0;
  input col_wait_r;
  input col_wait_r_reg;
  input col_wait_r_reg_0;
  input demand_priority_r_reg_1;
  input col_wait_r_0;
  input \order_q_r_reg[0]_0 ;
  input p_92_out;
  input rd_wr_r_lcl_reg;
  input idle_r_lcl_reg;
  input p_131_out;
  input col_rd_wr_r;
  input ofs_rdy_r_1;
  input ofs_rdy_r_2;
  input \grant_r_reg[3] ;
  input ofs_rdy_r_3;
  input rstdiv0_sync_r1_reg_rep__20;
  input rstdiv0_sync_r1_reg_rep__21;
  input [2:0]\req_bank_r_lcl_reg[2] ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [13:0]\req_row_r_lcl_reg[13] ;
  input [12:0]\req_row_r_lcl_reg[13]_0 ;
  input rnk_config_r;
  input rstdiv0_sync_r1_reg_rep__24;
  input [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;
  input col_wait_r_reg_1;
  input col_wait_r_reg_2;
  input demand_act_priority_r_reg;
  input [3:0]rd_this_rank_r;
  input read_this_rank_r;
  input rd_wr_r_lcl_reg_0;
  input rd_wr_r_lcl_reg_1;
  input col_wait_r_reg_3;
  input rd_wr_r_lcl_reg_2;
  input col_wait_r_reg_4;
  input rstdiv0_sync_r1_reg_rep__19;
  input col_wait_r_reg_5;
  input mc_aux_out_r;
  input p_53_out;
  input p_71_out;
  input p_32_out;
  input p_110_out;
  input col_periodic_rd_r;
  input p_149_out;
  input [4:0]\req_data_buf_addr_r_reg[4] ;
  input [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  input maint_sre_r;
  input auto_pre_r_lcl_reg;
  input auto_pre_r_lcl_reg_0;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input auto_pre_r_lcl_reg_1;
  input ras_timer_zero_r_reg_2;
  input auto_pre_r_lcl_reg_2;
  input p_115_out;
  input maint_zq_r;
  input p_154_out;
  input act_wait_r_lcl_reg;
  input demand_act_priority_r_reg_0;
  input demand_act_priority_r;
  input head_r_lcl_reg;
  input act_wait_r_lcl_reg_0;
  input demand_act_priority_r_4;
  input head_r_lcl_reg_0;
  input act_wait_r_lcl_reg_1;
  input inhbt_act_faw_r;
  input demand_act_priority_r_5;
  input \grant_r_reg[0]_1 ;
  input head_r_lcl_reg_1;
  input p_76_out;
  input p_37_out;
  input [3:0]wr_this_rank_r;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [2:0]\req_bank_r_lcl_reg[2]_2 ;
  input [9:0]\req_col_r_reg[9] ;
  input [9:0]\req_col_r_reg[9]_0 ;
  input [9:0]\req_col_r_reg[9]_1 ;
  input [9:0]\req_col_r_reg[9]_2 ;
  input auto_pre_r;
  input auto_pre_r_6;
  input auto_pre_r_7;
  input auto_pre_r_8;
  input [4:0]\req_data_buf_addr_r_reg[4]_1 ;
  input [4:0]\req_data_buf_addr_r_reg[4]_2 ;
  input [4:0]col_wr_data_buf_addr_r;
  input maint_srx_r;
  input [3:0]act_this_rank_r;
  input demand_act_priority_r_9;
  input maint_rank_r;
  input [13:0]\req_row_r_lcl_reg[13]_1 ;
  input [12:0]\req_row_r_lcl_reg[13]_2 ;

  wire CLK;
  wire [2:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [3:0]Q;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r;
  wire auto_pre_r_6;
  wire auto_pre_r_7;
  wire auto_pre_r_8;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire [37:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire \cmd_pipe_plus.mc_bank_reg[2] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire \cmd_pipe_plus.mc_cmd_reg[0] ;
  wire \cmd_pipe_plus.mc_cs_n_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_ras_n_reg[1] ;
  wire [3:0]\cmd_pipe_plus.mc_we_n_reg[0] ;
  wire [4:0]col_data_buf_addr;
  wire \col_mux.col_rd_wr_r_reg ;
  wire col_periodic_rd_r;
  wire col_rd_wr_r;
  wire col_wait_r;
  wire col_wait_r_0;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire col_wait_r_reg_2;
  wire col_wait_r_reg_3;
  wire col_wait_r_reg_4;
  wire col_wait_r_reg_5;
  wire [4:0]col_wr_data_buf_addr_r;
  wire demand_act_priority_r;
  wire demand_act_priority_r_4;
  wire demand_act_priority_r_5;
  wire demand_act_priority_r_9;
  wire demand_act_priority_r_reg;
  wire demand_act_priority_r_reg_0;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[3] ;
  wire granted_col_ns;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire granted_col_r_reg_3;
  wire granted_pre_ns;
  wire granted_row_ns;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire idle_r_lcl_reg;
  wire inhbt_act_faw_r;
  wire int_read_this_rank;
  wire \last_master_r_reg[0] ;
  wire [1:0]\last_master_r_reg[2] ;
  wire [3:0]\last_master_r_reg[3] ;
  wire maint_rank_r;
  wire maint_sre_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire mc_aux_out_r;
  wire mc_aux_out_r0;
  wire [0:0]mc_cas_n_ns;
  wire [0:0]mc_cs_n_ns;
  wire [0:0]mc_odt_ns;
  wire [1:0]mc_ras_n_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_1;
  wire ofs_rdy_r_2;
  wire ofs_rdy_r_3;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[0]_0 ;
  wire override_demand_ns;
  wire p_110_out;
  wire p_115_out;
  wire p_131_out;
  wire p_149_out;
  wire p_14_out;
  wire p_154_out;
  wire p_32_out;
  wire p_37_out;
  wire p_53_out;
  wire p_71_out;
  wire p_76_out;
  wire p_92_out;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire [3:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire read_this_rank;
  wire read_this_rank_r;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [9:0]\req_col_r_reg[9]_2 ;
  wire [4:0]\req_data_buf_addr_r_reg[4] ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_1 ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_2 ;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [12:0]\req_row_r_lcl_reg[13]_0 ;
  wire [13:0]\req_row_r_lcl_reg[13]_1 ;
  wire [12:0]\req_row_r_lcl_reg[13]_2 ;
  wire rnk_config_r;
  wire \rnk_config_r_reg[0] ;
  wire rnk_config_strobe;
  wire [2:1]rnk_config_strobe_0;
  wire rnk_config_strobe_ns;
  wire rnk_config_valid_r;
  wire rnk_config_valid_r_lcl_i_1_n_0;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire sent_row;
  wire sre_clears_sre_request;
  wire [3:0]wr_this_rank_r;
  wire \wtr_timer.wtr_cnt_r_reg[0] ;
  wire [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;

  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_cas_n[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_cmd_reg[0] ),
        .O(mc_cas_n_ns));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_ras_n[2]_i_1 
       (.I0(\last_master_r_reg[0] ),
        .O(mc_ras_n_ns[1]));
  mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized4 col_arb0
       (.CLK(CLK),
        .D(D[1]),
        .DIC(DIC),
        .E(E),
        .Q(Q),
        .auto_pre_r(auto_pre_r),
        .auto_pre_r_6(auto_pre_r_6),
        .auto_pre_r_7(auto_pre_r_7),
        .auto_pre_r_8(auto_pre_r_8),
        .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[41] [24:14]),
        .\cmd_pipe_plus.mc_bank_reg[5] (\cmd_pipe_plus.mc_bank_reg[8] [5:3]),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[1] (\cmd_pipe_plus.mc_ras_n_reg[1] ),
        .col_data_buf_addr(col_data_buf_addr),
        .\col_mux.col_rd_wr_r_reg (\col_mux.col_rd_wr_r_reg ),
        .col_periodic_rd_r(col_periodic_rd_r),
        .col_rd_wr_r(col_rd_wr_r),
        .col_wait_r_reg(col_wait_r_reg_3),
        .col_wr_data_buf_addr_r(col_wr_data_buf_addr_r),
        .demand_priority_r_reg(demand_priority_r_reg),
        .\grant_r_reg[0]_0 (\grant_r_reg[0] ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1] ),
        .\grant_r_reg[2]_0 (\rnk_config_r_reg[0] ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3] ),
        .granted_col_r_reg(granted_col_r_reg_0),
        .granted_col_r_reg_0(granted_col_r_reg_1),
        .granted_col_r_reg_1(granted_col_r_reg_2),
        .granted_col_r_reg_2(granted_col_r_reg_3),
        .granted_col_r_reg_3(\cmd_pipe_plus.mc_cmd_reg[0] ),
        .idle_r_lcl_reg(idle_r_lcl_reg),
        .int_read_this_rank(int_read_this_rank),
        .mc_aux_out_r(mc_aux_out_r),
        .mc_aux_out_r0(mc_aux_out_r0),
        .mc_odt_ns(mc_odt_ns),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r_1(ofs_rdy_r_1),
        .ofs_rdy_r_2(ofs_rdy_r_2),
        .ofs_rdy_r_3(ofs_rdy_r_3),
        .\order_q_r_reg[0] (\order_q_r_reg[0] ),
        .override_demand_ns(override_demand_ns),
        .p_110_out(p_110_out),
        .p_131_out(p_131_out),
        .p_149_out(p_149_out),
        .p_14_out(p_14_out),
        .p_32_out(p_32_out),
        .p_53_out(p_53_out),
        .p_71_out(p_71_out),
        .p_92_out(p_92_out),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_2),
        .read_this_rank(read_this_rank),
        .read_this_rank_r(read_this_rank_r),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_1 ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ),
        .\req_col_r_reg[9] (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9]_0 ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_1 ),
        .\req_col_r_reg[9]_2 (\req_col_r_reg[9]_2 ),
        .\req_data_buf_addr_r_reg[4] (\req_data_buf_addr_r_reg[4] ),
        .\req_data_buf_addr_r_reg[4]_0 (\req_data_buf_addr_r_reg[4]_0 ),
        .\req_data_buf_addr_r_reg[4]_1 (\req_data_buf_addr_r_reg[4]_1 ),
        .\req_data_buf_addr_r_reg[4]_2 (\req_data_buf_addr_r_reg[4]_2 ),
        .rnk_config_strobe(rnk_config_strobe),
        .rnk_config_strobe_0(rnk_config_strobe_0),
        .rnk_config_valid_r(rnk_config_valid_r),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .wr_this_rank_r(wr_this_rank_r),
        .\wtr_timer.wtr_cnt_r_reg[0] (\wtr_timer.wtr_cnt_r_reg[0] ),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ));
  mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized3 config_arb0
       (.CLK(CLK),
        .col_wait_r(col_wait_r),
        .col_wait_r_0(col_wait_r_0),
        .col_wait_r_reg(col_wait_r_reg_1),
        .col_wait_r_reg_0(col_wait_r_reg),
        .col_wait_r_reg_1(col_wait_r_reg_0),
        .col_wait_r_reg_2(col_wait_r_reg_2),
        .col_wait_r_reg_3(col_wait_r_reg_4),
        .col_wait_r_reg_4(col_wait_r_reg_5),
        .demand_priority_r_reg(demand_priority_r_reg_0),
        .demand_priority_r_reg_0(demand_priority_r_reg_1),
        .\grant_r_reg[2]_0 (\grant_r_reg[2] ),
        .\order_q_r_reg[0] (\order_q_r_reg[0] ),
        .\order_q_r_reg[0]_0 (\order_q_r_reg[0]_0 ),
        .rnk_config_r(rnk_config_r),
        .\rnk_config_r_reg[0] (\rnk_config_r_reg[0] ),
        .rnk_config_strobe(rnk_config_strobe),
        .rnk_config_strobe_0(rnk_config_strobe_0),
        .rnk_config_valid_r(rnk_config_valid_r),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24));
  FDRE \genblk3[1].rnk_config_strobe_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_strobe),
        .Q(rnk_config_strobe_0[1]),
        .R(1'b0));
  FDRE \genblk3[2].rnk_config_strobe_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_strobe_0[1]),
        .Q(rnk_config_strobe_0[2]),
        .R(1'b0));
  FDRE granted_col_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(granted_col_ns),
        .Q(\cmd_pipe_plus.mc_cmd_reg[0] ),
        .R(1'b0));
  FDRE granted_row_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(granted_row_ns),
        .Q(sent_row),
        .R(1'b0));
  FDRE insert_maint_r1_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .Q(\cmd_pipe_plus.mc_cs_n_reg[0] ),
        .R(1'b0));
  FDRE \pre_4_1_1T_arb.granted_pre_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(granted_pre_ns),
        .Q(\last_master_r_reg[0] ),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized2 \pre_4_1_1T_arb.pre_arb0 
       (.CLK(CLK),
        .D(\last_master_r_reg[2] ),
        .Q(\last_master_r_reg[3] ),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] [37:25]),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] [8:6]),
        .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2] [1]),
        .\cmd_pipe_plus.mc_we_n_reg[2] (D[2]),
        .p_115_out(p_115_out),
        .p_154_out(p_154_out),
        .p_37_out(p_37_out),
        .p_76_out(p_76_out),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\last_master_r_reg[0] ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ),
        .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [13:11],\req_row_r_lcl_reg[13] [9:0]}),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13]_0 ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_2 ),
        .\req_row_r_lcl_reg[13]_2 ({\req_row_r_lcl_reg[13]_1 [13:11],\req_row_r_lcl_reg[13]_1 [9:0]}),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21));
  FDRE \rnk_config_strobe_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_strobe_ns),
        .Q(rnk_config_strobe),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFB)) 
    rnk_config_valid_r_lcl_i_1
       (.I0(rnk_config_valid_r),
        .I1(col_wait_r_reg),
        .I2(col_wait_r_reg_0),
        .O(rnk_config_valid_r_lcl_i_1_n_0));
  FDRE rnk_config_valid_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_valid_r_lcl_i_1_n_0),
        .Q(rnk_config_valid_r),
        .R(rstdiv0_sync_r1_reg_rep__18));
  mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1 row_arb0
       (.CLK(CLK),
        .D(D[0]),
        .Q(\cmd_pipe_plus.mc_we_n_reg[0] ),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .\cmd_pipe_plus.mc_address_reg[13] (\cmd_pipe_plus.mc_address_reg[41] [13:0]),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[8] [2:0]),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_cas_n_reg[0] (\cmd_pipe_plus.mc_cas_n_reg[2] [0]),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_4(demand_act_priority_r_4),
        .demand_act_priority_r_5(demand_act_priority_r_5),
        .demand_act_priority_r_9(demand_act_priority_r_9),
        .demand_act_priority_r_reg(demand_act_priority_r_reg),
        .demand_act_priority_r_reg_0(demand_act_priority_r_reg_0),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ),
        .\grant_r_reg[1]_2 (\grant_r_reg[1]_2 ),
        .head_r_lcl_reg(head_r_lcl_reg),
        .head_r_lcl_reg_0(head_r_lcl_reg_0),
        .head_r_lcl_reg_1(head_r_lcl_reg_1),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1_lcl_reg(\cmd_pipe_plus.mc_cs_n_reg[0] ),
        .maint_rank_r(maint_rank_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cs_n_ns(mc_cs_n_ns),
        .mc_ras_n_ns(mc_ras_n_ns[0]),
        .p_115_out(p_115_out),
        .p_154_out(p_154_out),
        .p_37_out(p_37_out),
        .p_76_out(p_76_out),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_2 ),
        .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_1 ),
        .\req_row_r_lcl_reg[13] (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13]_0 ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_1 ),
        .\req_row_r_lcl_reg[13]_2 (\req_row_r_lcl_reg[13]_2 ),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sent_row(sent_row));
  LUT2 #(
    .INIT(4'h8)) 
    \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_cs_n_reg[0] ),
        .I1(maint_sre_r),
        .O(sre_clears_sre_request));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_arb_select" *) 
module mig_7series_0_mig_7series_v2_3_arb_select
   (col_periodic_rd_r,
    col_rd_wr_r,
    mc_aux_out_r,
    cke_r,
    rnk_config_r,
    \cmd_pipe_plus.wr_data_en_reg ,
    DIC,
    CLK,
    \grant_r_reg[3] ,
    mc_aux_out_r0,
    rstdiv0_sync_r1_reg_rep__1,
    mc_cke_ns,
    \grant_r_reg[2] ,
    mc_cmd);
  output col_periodic_rd_r;
  output col_rd_wr_r;
  output mc_aux_out_r;
  output cke_r;
  output rnk_config_r;
  output \cmd_pipe_plus.wr_data_en_reg ;
  input [0:0]DIC;
  input CLK;
  input \grant_r_reg[3] ;
  input mc_aux_out_r0;
  input rstdiv0_sync_r1_reg_rep__1;
  input [0:0]mc_cke_ns;
  input \grant_r_reg[2] ;
  input [0:0]mc_cmd;

  wire CLK;
  wire [0:0]DIC;
  wire cke_r;
  wire \cmd_pipe_plus.wr_data_en_reg ;
  wire col_periodic_rd_r;
  wire col_rd_wr_r;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[3] ;
  wire mc_aux_out_r;
  wire mc_aux_out_r0;
  wire [0:0]mc_cke_ns;
  wire [0:0]mc_cmd;
  wire rnk_config_r;
  wire rstdiv0_sync_r1_reg_rep__1;

  FDSE cke_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cke_ns),
        .Q(cke_r),
        .S(rstdiv0_sync_r1_reg_rep__1));
  LUT2 #(
    .INIT(4'h2)) 
    \cmd_pipe_plus.wr_data_en_i_1 
       (.I0(mc_cmd),
        .I1(col_rd_wr_r),
        .O(\cmd_pipe_plus.wr_data_en_reg ));
  FDRE \col_mux.col_periodic_rd_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(DIC),
        .Q(col_periodic_rd_r),
        .R(1'b0));
  FDRE \col_mux.col_rd_wr_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r_reg[3] ),
        .Q(col_rd_wr_r),
        .R(1'b0));
  FDRE \mc_aux_out_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_aux_out_r0),
        .Q(mc_aux_out_r),
        .R(1'b0));
  FDRE \rnk_config_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r_reg[2] ),
        .Q(rnk_config_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_cntrl" *) 
module mig_7series_0_mig_7series_v2_3_bank_cntrl
   (p_129_out,
    p_149_out,
    p_131_out,
    p_132_out,
    p_126_out,
    bm_end_r1,
    p_130_out,
    p_154_out,
    demand_act_priority_r,
    act_this_rank_r,
    demand_priority_r,
    demanded_prior_r,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    auto_pre_r_lcl_reg,
    tail_r,
    p_128_out,
    \grant_r_reg[0] ,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    head_r_lcl_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg ,
    ras_timer_zero_r_reg,
    clear_req,
    \grant_r_reg[2] ,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[1] ,
    granted_col_ns,
    granted_col_r_reg,
    rnk_config_strobe_ns,
    \rnk_config_strobe_r_reg[0] ,
    \grant_r_reg[1] ,
    demand_priority_r_reg,
    \q_entry_r_reg[1] ,
    \q_entry_r_reg[1]_0 ,
    q_entry_ns,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[1]_2 ,
    q_entry_ns_0,
    \q_entry_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_0 ,
    auto_pre_r,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \cmd_pipe_plus.mc_address_reg[13] ,
    \grant_r_reg[1]_0 ,
    demanded_prior_r_reg,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    p_142_out,
    CLK,
    periodic_rd_insert,
    hi_priority,
    p_145_out,
    rstdiv0_sync_r1_reg_rep__0,
    ofs_rdy_r0,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__19,
    app_en_r2_reg,
    pre_bm_end_r_reg,
    idle_r_lcl_reg,
    demand_priority_r_reg_0,
    \grant_r_reg[1]_1 ,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    rnk_config_valid_r_lcl_reg,
    req_wr_r_lcl_reg,
    Q,
    pre_bm_end_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    req_wr_r_lcl_reg_0,
    p_91_out,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    idle_r_lcl_reg_0,
    pre_bm_end_r_reg_1,
    periodic_rd_ack_r_lcl_reg,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[2]_0 ,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    periodic_rd_ack_r_lcl_reg_0,
    was_priority,
    rstdiv0_sync_r1_reg_rep__20_0,
    demanded_prior_r_reg_0,
    S,
    \ras_timer_r_reg[1]_0 ,
    rd_wr_r_lcl_reg,
    \ras_timer_r_reg[0]_1 ,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    rd_wr_r_lcl_reg_0,
    col_wait_r_reg,
    col_wait_r_reg_0,
    rd_wr_r_lcl_reg_1,
    demanded_prior_r_reg_1,
    \rnk_config_strobe_r_reg[0]_0 ,
    p_90_out,
    p_51_out,
    p_12_out,
    periodic_rd_ack_r_lcl_reg_1,
    q_entry_r,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[0]_2 ,
    rstdiv0_sync_r1_reg_rep__20_1,
    pre_passing_open_bank_r_reg,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    p_106_out,
    clear_req_1,
    p_67_out,
    \grant_r_reg[2]_1 ,
    p_28_out,
    \grant_r_reg[3] ,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    \grant_r_reg[0]_1 ,
    periodic_rd_ack_r_lcl_reg_2,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    accept_r_reg,
    row,
    demanded_prior_r_2,
    demand_priority_r_3,
    granted_col_r_reg_0,
    p_9_out,
    p_48_out,
    p_87_out,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] ,
    rstdiv0_sync_r1_reg_rep__24,
    rstdiv0_sync_r1_reg_rep__1,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    ordered_r_lcl_reg,
    ordered_r_lcl_reg_0);
  output p_129_out;
  output p_149_out;
  output p_131_out;
  output p_132_out;
  output p_126_out;
  output bm_end_r1;
  output p_130_out;
  output p_154_out;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demand_priority_r;
  output demanded_prior_r;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output auto_pre_r_lcl_reg;
  output tail_r;
  output p_128_out;
  output \grant_r_reg[0] ;
  output \q_entry_r_reg[0] ;
  output \q_entry_r_reg[0]_0 ;
  output head_r_lcl_reg;
  output head_r_lcl_reg_0;
  output head_r_lcl_reg_1;
  output \compute_tail.tail_r_lcl_reg ;
  output ras_timer_zero_r_reg;
  output clear_req;
  output \grant_r_reg[2] ;
  output \ras_timer_r_reg[0] ;
  output \ras_timer_r_reg[1] ;
  output granted_col_ns;
  output granted_col_r_reg;
  output rnk_config_strobe_ns;
  output \rnk_config_strobe_r_reg[0] ;
  output \grant_r_reg[1] ;
  output demand_priority_r_reg;
  output \q_entry_r_reg[1] ;
  output \q_entry_r_reg[1]_0 ;
  output [0:0]q_entry_ns;
  output \q_entry_r_reg[1]_1 ;
  output \q_entry_r_reg[1]_2 ;
  output [0:0]q_entry_ns_0;
  output \q_entry_r_reg[0]_1 ;
  output \ras_timer_r_reg[0]_0 ;
  output auto_pre_r;
  output \pre_4_1_1T_arb.granted_pre_r_reg ;
  output [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  output \grant_r_reg[1]_0 ;
  output demanded_prior_r_reg;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  output p_142_out;
  input CLK;
  input periodic_rd_insert;
  input hi_priority;
  input p_145_out;
  input rstdiv0_sync_r1_reg_rep__0;
  input ofs_rdy_r0;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__19;
  input app_en_r2_reg;
  input pre_bm_end_r_reg;
  input idle_r_lcl_reg;
  input demand_priority_r_reg_0;
  input \grant_r_reg[1]_1 ;
  input \wtr_timer.wtr_cnt_r_reg[1] ;
  input rnk_config_valid_r_lcl_reg;
  input req_wr_r_lcl_reg;
  input [1:0]Q;
  input pre_bm_end_r_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input req_wr_r_lcl_reg_0;
  input p_91_out;
  input [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input idle_r_lcl_reg_0;
  input pre_bm_end_r_reg_1;
  input periodic_rd_ack_r_lcl_reg;
  input [0:0]\grant_r_reg[0]_0 ;
  input [1:0]\grant_r_reg[2]_0 ;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input periodic_rd_ack_r_lcl_reg_0;
  input was_priority;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input demanded_prior_r_reg_0;
  input [0:0]S;
  input \ras_timer_r_reg[1]_0 ;
  input rd_wr_r_lcl_reg;
  input \ras_timer_r_reg[0]_1 ;
  input bm_end_r1_reg;
  input bm_end_r1_reg_0;
  input bm_end_r1_reg_1;
  input rd_wr_r_lcl_reg_0;
  input col_wait_r_reg;
  input col_wait_r_reg_0;
  input rd_wr_r_lcl_reg_1;
  input demanded_prior_r_reg_1;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input p_90_out;
  input p_51_out;
  input p_12_out;
  input periodic_rd_ack_r_lcl_reg_1;
  input [0:0]q_entry_r;
  input \q_entry_r_reg[1]_3 ;
  input \q_entry_r_reg[0]_2 ;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input pre_passing_open_bank_r_reg;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input p_106_out;
  input clear_req_1;
  input p_67_out;
  input \grant_r_reg[2]_1 ;
  input p_28_out;
  input \grant_r_reg[3] ;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input [0:0]\grant_r_reg[0]_1 ;
  input periodic_rd_ack_r_lcl_reg_2;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input accept_r_reg;
  input [13:0]row;
  input demanded_prior_r_2;
  input demand_priority_r_3;
  input granted_col_r_reg_0;
  input p_9_out;
  input p_48_out;
  input p_87_out;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;
  input rstdiv0_sync_r1_reg_rep__24;
  input rstdiv0_sync_r1_reg_rep__1;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input ordered_r_lcl_reg;
  input ordered_r_lcl_reg_0;

  wire CLK;
  wire [1:0]Q;
  wire [0:0]S;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_en_r2_reg;
  wire app_rdy_r_reg;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire bank_compare0_n_12;
  wire bank_compare0_n_13;
  wire bank_queue0_n_12;
  wire bank_queue0_n_20;
  wire bank_queue0_n_24;
  wire bank_state0_n_22;
  wire bank_state0_n_25;
  wire bank_state0_n_5;
  wire bm_end_r1;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire clear_req;
  wire clear_req_1;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire col_wait_r;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg ;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire demand_act_priority_r;
  wire demand_priority_ns;
  wire demand_priority_r;
  wire demand_priority_r_3;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demanded_prior_r;
  wire demanded_prior_r_2;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire \grant_r_reg[0] ;
  wire [0:0]\grant_r_reg[0]_0 ;
  wire [0:0]\grant_r_reg[0]_1 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[2] ;
  wire [1:0]\grant_r_reg[2]_0 ;
  wire \grant_r_reg[2]_1 ;
  wire \grant_r_reg[3] ;
  wire granted_col_ns;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire p_106_out;
  wire p_126_out;
  wire p_128_out;
  wire p_129_out;
  wire p_12_out;
  wire p_130_out;
  wire p_131_out;
  wire p_132_out;
  wire p_133_out;
  wire p_142_out;
  wire p_145_out;
  wire p_149_out;
  wire p_154_out;
  wire p_28_out;
  wire p_48_out;
  wire p_51_out;
  wire p_67_out;
  wire p_87_out;
  wire p_90_out;
  wire p_91_out;
  wire p_9_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_ack_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire [0:0]q_entry_ns_0;
  wire [0:0]q_entry_r;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg[1]_3 ;
  wire q_has_rd;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire req_bank_rdy_ns;
  wire req_priority_r;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire rnk_config_valid_r_lcl_reg;
  wire [13:0]row;
  wire row_hit_r;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire set_order_q;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;

  mig_7series_0_mig_7series_v2_3_bank_compare_2 bank_compare0
       (.CLK(CLK),
        .E(p_133_out),
        .Q(Q),
        .S(S),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_rdy_r_reg(app_rdy_r_reg),
        .bm_end_r1_reg(p_132_out),
        .\cmd_pipe_plus.mc_address_reg[13] (\cmd_pipe_plus.mc_address_reg[13] ),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ),
        .\grant_r_reg[0] (\grant_r_reg[2]_0 [0]),
        .head_r_lcl_reg(head_r_lcl_reg),
        .head_r_lcl_reg_0(head_r_lcl_reg_1),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(demand_priority_r_reg),
        .idle_r_lcl_reg_0(p_129_out),
        .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .p_145_out(p_145_out),
        .p_149_out(p_149_out),
        .p_48_out(p_48_out),
        .p_87_out(p_87_out),
        .p_91_out(p_91_out),
        .p_9_out(p_9_out),
        .pass_open_bank_r_lcl_reg(bank_compare0_n_13),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),
        .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r_reg(p_130_out),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg_1),
        .pre_bm_end_r_reg_2(bank_queue0_n_24),
        .q_entry_ns(q_entry_ns),
        .q_entry_r(q_entry_r),
        .\q_entry_r_reg[0] (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_0 ),
        .q_has_priority_r_reg(p_126_out),
        .ras_timer_zero_r_reg(bank_compare0_n_12),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rd_this_rank_r_reg[0] (p_131_out),
        .req_priority_r(req_priority_r),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),
        .row(row),
        .row_hit_r(row_hit_r),
        .set_order_q(set_order_q),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r0(wr_this_rank_r0));
  mig_7series_0_mig_7series_v2_3_bank_queue bank_queue0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .E(p_133_out),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(ras_timer_zero_r_reg),
        .act_wait_r_lcl_reg_0(p_154_out),
        .app_en_r2_reg(app_en_r2_reg),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r),
        .bm_end_r1_reg(p_130_out),
        .bm_end_r1_reg_0(\ras_timer_r_reg[1] ),
        .bm_end_r1_reg_1(bm_end_r1_reg),
        .bm_end_r1_reg_2(bm_end_r1_reg_0),
        .bm_end_r1_reg_3(bm_end_r1_reg_1),
        .clear_req_1(clear_req_1),
        .col_wait_r(col_wait_r),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_reg(demand_priority_r_reg),
        .demand_priority_r_reg_0(bank_queue0_n_20),
        .demand_priority_r_reg_1(demand_priority_r_reg_0),
        .demand_priority_r_reg_2(bank_state0_n_25),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[0]_0 (\grant_r_reg[2]_0 [0]),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[1] (\grant_r_reg[1]_0 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_1 ),
        .\grant_r_reg[2] (\grant_r_reg[2]_1 ),
        .\grant_r_reg[3] (\grant_r_reg[3] ),
        .granted_col_ns(granted_col_ns),
        .granted_col_r_reg(granted_col_r_reg),
        .head_r_lcl_reg_0(p_128_out),
        .head_r_lcl_reg_1(head_r_lcl_reg_0),
        .idle_r_lcl_reg_0(idle_r_lcl_reg),
        .idle_r_lcl_reg_1(idle_r_lcl_reg_0),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),
        .p_106_out(p_106_out),
        .p_126_out(p_126_out),
        .p_12_out(p_12_out),
        .p_142_out(p_142_out),
        .p_28_out(p_28_out),
        .p_51_out(p_51_out),
        .p_67_out(p_67_out),
        .p_90_out(p_90_out),
        .p_91_out(p_91_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(clear_req),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),
        .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_2),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0),
        .pre_passing_open_bank_r_reg_2(pre_passing_open_bank_r_reg_1),
        .pre_wait_r(pre_wait_r),
        .q_entry_ns_0(q_entry_ns_0),
        .\q_entry_r_reg[0]_0 (bank_queue0_n_24),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_2 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ),
        .\q_entry_r_reg[1]_3 (\q_entry_r_reg[1]_2 ),
        .\q_entry_r_reg[1]_4 (\q_entry_r_reg[1]_3 ),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0] (bank_queue0_n_12),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[1] (\ras_timer_r_reg[1]_0 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .rb_hit_busy_r_reg(\q_entry_r_reg[0]_0 ),
        .rb_hit_busy_r_reg_0(head_r_lcl_reg_1),
        .rb_hit_busy_r_reg_1(bank_state0_n_22),
        .rd_wr_r_lcl_reg(p_131_out),
        .rd_wr_r_lcl_reg_0(\ras_timer_r_reg[0] ),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_0),
        .rd_wr_r_lcl_reg_3(rd_wr_r_lcl_reg_1),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .\req_data_buf_addr_r_reg[0] (p_129_out),
        .req_priority_r(req_priority_r),
        .req_wr_r_lcl_reg(req_wr_r_lcl_reg),
        .req_wr_r_lcl_reg_0(p_132_out),
        .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),
        .row_hit_r(row_hit_r),
        .row_hit_r_reg(bank_compare0_n_13),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__19_0(bank_state0_n_5),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_1),
        .set_order_q(set_order_q),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ));
  mig_7series_0_mig_7series_v2_3_bank_state bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .accept_r_reg(accept_r_reg),
        .act_this_rank_r(act_this_rank_r),
        .\act_this_rank_r_reg[0]_0 (p_154_out),
        .act_wait_ns(act_wait_ns),
        .auto_pre_r_lcl_reg(bank_state0_n_22),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .bm_end_r1(bm_end_r1),
        .col_wait_r(col_wait_r),
        .col_wait_r_reg_0(bank_state0_n_5),
        .col_wait_r_reg_1(col_wait_r_reg),
        .col_wait_r_reg_2(col_wait_r_reg_0),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_3(demand_priority_r_3),
        .demand_priority_r_reg_0(bank_state0_n_25),
        .demanded_prior_r_2(demanded_prior_r_2),
        .demanded_prior_r_reg_0(demand_priority_r),
        .demanded_prior_r_reg_1(demanded_prior_r),
        .demanded_prior_r_reg_2(demanded_prior_r_reg),
        .demanded_prior_r_reg_3(demanded_prior_r_reg_0),
        .demanded_prior_r_reg_4(demanded_prior_r_reg_1),
        .\grant_r_reg[0] (\grant_r_reg[0]_0 ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .granted_col_r_reg(granted_col_r_reg_0),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .\order_q_r_reg[0] (bank_queue0_n_20),
        .p_126_out(p_126_out),
        .p_128_out(p_128_out),
        .p_129_out(p_129_out),
        .p_130_out(p_130_out),
        .p_132_out(p_132_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[1] (bank_queue0_n_12),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r_lcl_reg(p_131_out),
        .rd_wr_r_lcl_reg_0(bank_compare0_n_12),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .rnk_config_strobe_ns(rnk_config_strobe_ns),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_0 ),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_1),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r(wr_this_rank_r),
        .wr_this_rank_r0(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_cntrl" *) 
module mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized0
   (p_90_out,
    p_110_out,
    p_92_out,
    p_87_out,
    bm_end_r1_0,
    p_91_out,
    p_115_out,
    col_wait_r,
    demand_act_priority_r,
    act_this_rank_r,
    demand_priority_r,
    demanded_prior_r,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    auto_pre_r_lcl_reg,
    tail_r,
    p_89_out,
    \grant_r_reg[1] ,
    demand_priority_r_reg,
    \compute_tail.tail_r_lcl_reg ,
    head_r_lcl_reg,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    clear_req,
    \grant_r_reg[1]_0 ,
    ras_timer_zero_r_reg,
    granted_col_r_reg,
    \grant_r_reg[3] ,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0] ,
    \grant_r_reg[1]_1 ,
    demand_priority_r_reg_0,
    \ras_timer_r_reg[0]_0 ,
    p_7_in,
    auto_pre_r,
    \q_entry_r_reg[1] ,
    req_bank_rdy_r_reg,
    granted_pre_ns,
    \grant_r_reg[2] ,
    granted_row_ns,
    granted_row_r_reg,
    \grant_r_reg[1]_2 ,
    \grant_r_reg[2]_0 ,
    \grant_r_reg[1]_3 ,
    \cmd_pipe_plus.mc_address_reg[13] ,
    \grant_r_reg[2]_1 ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    p_103_out,
    CLK,
    periodic_rd_insert,
    hi_priority,
    p_106_out,
    rstdiv0_sync_r1_reg_rep__0,
    ofs_rdy_r0,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__19,
    idle_r_lcl_reg,
    p_130_out,
    req_wr_r_lcl_reg,
    \grant_r_reg[2]_2 ,
    pre_bm_end_r_reg,
    Q,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    p_129_out,
    p_51_out,
    p_12_out,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    app_en_r2_reg,
    periodic_rd_ack_r_lcl_reg,
    was_priority,
    rstdiv0_sync_r1_reg_rep__20_0,
    periodic_rd_ack_r_lcl_reg_0,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    \grant_r_reg[3]_0 ,
    demanded_prior_r_reg,
    override_demand_r,
    demand_priority_r_0,
    rstdiv0_sync_r1_reg_rep__20_1,
    \app_addr_r1_reg[22] ,
    rd_wr_r_lcl_reg,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[1]_0 ,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    demand_priority_r_reg_1,
    \rnk_config_strobe_r_reg[0] ,
    periodic_rd_ack_r_lcl_reg_1,
    p_67_out,
    \grant_r_reg[2]_3 ,
    p_28_out,
    \grant_r_reg[3]_1 ,
    p_145_out,
    clear_req_1,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    init_calib_complete_reg_rep,
    idle_r_lcl_reg_0,
    idle_r_lcl_reg_1,
    idle_r_lcl_reg_2,
    \grant_r_reg[1]_4 ,
    rstdiv0_sync_r1_reg_rep__19_0,
    periodic_rd_ack_r_lcl_reg_2,
    pre_bm_end_r_reg_0,
    pre_passing_open_bank_r_reg,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    p_131_out,
    p_132_out,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    accept_r_reg,
    auto_pre_r_lcl_reg_0,
    ras_timer_zero_r_reg_0,
    demand_act_priority_r_reg,
    \grant_r_reg[2]_4 ,
    demand_act_priority_r_2,
    demand_act_priority_r_reg_0,
    \grant_r_reg[1]_5 ,
    \last_master_r_reg[0] ,
    row,
    demanded_prior_r_3,
    p_154_out,
    \req_row_r_lcl_reg[10] ,
    granted_col_r_reg_0,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] ,
    rstdiv0_sync_r1_reg_rep__24,
    q_entry_ns,
    idle_r_lcl_reg_3,
    rstdiv0_sync_r1_reg_rep__1,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    ordered_r_lcl_reg,
    ordered_r_lcl_reg_0);
  output p_90_out;
  output p_110_out;
  output p_92_out;
  output p_87_out;
  output bm_end_r1_0;
  output p_91_out;
  output p_115_out;
  output col_wait_r;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demand_priority_r;
  output demanded_prior_r;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output auto_pre_r_lcl_reg;
  output tail_r;
  output p_89_out;
  output \grant_r_reg[1] ;
  output demand_priority_r_reg;
  output \compute_tail.tail_r_lcl_reg ;
  output head_r_lcl_reg;
  output \q_entry_r_reg[0] ;
  output \q_entry_r_reg[0]_0 ;
  output clear_req;
  output \grant_r_reg[1]_0 ;
  output ras_timer_zero_r_reg;
  output granted_col_r_reg;
  output \grant_r_reg[3] ;
  output \ras_timer_r_reg[1] ;
  output \ras_timer_r_reg[0] ;
  output \grant_r_reg[1]_1 ;
  output demand_priority_r_reg_0;
  output \ras_timer_r_reg[0]_0 ;
  output p_7_in;
  output auto_pre_r;
  output \q_entry_r_reg[1] ;
  output req_bank_rdy_r_reg;
  output granted_pre_ns;
  output \grant_r_reg[2] ;
  output granted_row_ns;
  output granted_row_r_reg;
  output \grant_r_reg[1]_2 ;
  output \grant_r_reg[2]_0 ;
  output \grant_r_reg[1]_3 ;
  output [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  output \grant_r_reg[2]_1 ;
  output \cmd_pipe_plus.mc_address_reg[38] ;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  output p_103_out;
  input CLK;
  input periodic_rd_insert;
  input hi_priority;
  input p_106_out;
  input rstdiv0_sync_r1_reg_rep__0;
  input ofs_rdy_r0;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__19;
  input idle_r_lcl_reg;
  input p_130_out;
  input req_wr_r_lcl_reg;
  input \grant_r_reg[2]_2 ;
  input pre_bm_end_r_reg;
  input [2:0]Q;
  input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input p_129_out;
  input p_51_out;
  input p_12_out;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input app_en_r2_reg;
  input periodic_rd_ack_r_lcl_reg;
  input was_priority;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input periodic_rd_ack_r_lcl_reg_0;
  input rb_hit_busy_r_reg;
  input rb_hit_busy_r_reg_0;
  input [1:0]\grant_r_reg[3]_0 ;
  input demanded_prior_r_reg;
  input override_demand_r;
  input demand_priority_r_0;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input [0:0]\app_addr_r1_reg[22] ;
  input rd_wr_r_lcl_reg;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[1]_0 ;
  input bm_end_r1_reg;
  input bm_end_r1_reg_0;
  input bm_end_r1_reg_1;
  input demand_priority_r_reg_1;
  input \rnk_config_strobe_r_reg[0] ;
  input periodic_rd_ack_r_lcl_reg_1;
  input p_67_out;
  input \grant_r_reg[2]_3 ;
  input p_28_out;
  input \grant_r_reg[3]_1 ;
  input p_145_out;
  input clear_req_1;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input init_calib_complete_reg_rep;
  input idle_r_lcl_reg_0;
  input idle_r_lcl_reg_1;
  input idle_r_lcl_reg_2;
  input [1:0]\grant_r_reg[1]_4 ;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input periodic_rd_ack_r_lcl_reg_2;
  input pre_bm_end_r_reg_0;
  input pre_passing_open_bank_r_reg;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input p_131_out;
  input p_132_out;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input accept_r_reg;
  input auto_pre_r_lcl_reg_0;
  input ras_timer_zero_r_reg_0;
  input demand_act_priority_r_reg;
  input \grant_r_reg[2]_4 ;
  input demand_act_priority_r_2;
  input demand_act_priority_r_reg_0;
  input \grant_r_reg[1]_5 ;
  input \last_master_r_reg[0] ;
  input [13:0]row;
  input demanded_prior_r_3;
  input p_154_out;
  input [0:0]\req_row_r_lcl_reg[10] ;
  input granted_col_r_reg_0;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;
  input rstdiv0_sync_r1_reg_rep__24;
  input [0:0]q_entry_ns;
  input idle_r_lcl_reg_3;
  input rstdiv0_sync_r1_reg_rep__1;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input ordered_r_lcl_reg;
  input ordered_r_lcl_reg_0;

  wire CLK;
  wire [2:0]Q;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_en_r2_reg;
  wire app_rdy_r_reg;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire bank_compare0_n_10;
  wire bank_compare0_n_11;
  wire bank_queue0_n_16;
  wire bank_queue0_n_27;
  wire bank_state0_n_20;
  wire bank_state0_n_29;
  wire bank_state0_n_5;
  wire bm_end_r1_0;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire clear_req;
  wire clear_req_1;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire \cmd_pipe_plus.mc_address_reg[38] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire col_wait_r;
  wire \compute_tail.tail_r_lcl_reg ;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire demand_act_priority_r;
  wire demand_act_priority_r_2;
  wire demand_act_priority_r_reg;
  wire demand_act_priority_r_reg_0;
  wire demand_priority_ns;
  wire demand_priority_r;
  wire demand_priority_r_0;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demanded_prior_r;
  wire demanded_prior_r_3;
  wire demanded_prior_r_reg;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[1]_3 ;
  wire [1:0]\grant_r_reg[1]_4 ;
  wire \grant_r_reg[1]_5 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[2]_1 ;
  wire \grant_r_reg[2]_2 ;
  wire \grant_r_reg[2]_3 ;
  wire \grant_r_reg[2]_4 ;
  wire \grant_r_reg[3] ;
  wire [1:0]\grant_r_reg[3]_0 ;
  wire \grant_r_reg[3]_1 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_pre_ns;
  wire granted_row_ns;
  wire granted_row_r_reg;
  wire head_r_lcl_reg;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire init_calib_complete_reg_rep;
  wire \last_master_r_reg[0] ;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire override_demand_r;
  wire p_103_out;
  wire p_106_out;
  wire p_110_out;
  wire p_115_out;
  wire p_129_out;
  wire p_12_out;
  wire p_130_out;
  wire p_131_out;
  wire p_132_out;
  wire p_145_out;
  wire p_154_out;
  wire p_28_out;
  wire p_51_out;
  wire p_67_out;
  wire p_7_in;
  wire p_87_out;
  wire p_89_out;
  wire p_90_out;
  wire p_91_out;
  wire p_92_out;
  wire p_93_out;
  wire p_94_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_ack_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[1] ;
  wire q_has_rd;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_priority_r;
  wire [0:0]\req_row_r_lcl_reg[10] ;
  wire req_wr_r_lcl_reg;
  wire \rnk_config_strobe_r_reg[0] ;
  wire [13:0]row;
  wire row_hit_r;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire set_order_q;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;

  mig_7series_0_mig_7series_v2_3_bank_compare_1 bank_compare0
       (.CLK(CLK),
        .E(p_94_out),
        .Q(Q[1:0]),
        .act_wait_r_lcl_reg(p_115_out),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_rdy_r_reg(app_rdy_r_reg),
        .\cmd_pipe_plus.mc_address_reg[13] (\cmd_pipe_plus.mc_address_reg[13] ),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ),
        .\grant_r_reg[1] (\grant_r_reg[1]_4 ),
        .head_r_lcl_reg(head_r_lcl_reg),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(demand_priority_r_reg_0),
        .idle_r_lcl_reg_0(p_90_out),
        .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .p_106_out(p_106_out),
        .p_110_out(p_110_out),
        .p_130_out(p_130_out),
        .p_131_out(p_131_out),
        .p_132_out(p_132_out),
        .p_154_out(p_154_out),
        .p_87_out(p_87_out),
        .p_93_out(p_93_out),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg(bank_compare0_n_11),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r(pre_bm_end_r),
        .\q_entry_r_reg[0] (\q_entry_r_reg[0] ),
        .ras_timer_zero_r_reg(bank_compare0_n_10),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rd_this_rank_r_reg[0] (p_92_out),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ),
        .row(row),
        .row_hit_r(row_hit_r),
        .set_order_q(set_order_q),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r0(wr_this_rank_r0));
  mig_7series_0_mig_7series_v2_3_bank_queue__parameterized0 bank_queue0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .E(p_94_out),
        .Q(Q[1]),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(bank_queue0_n_16),
        .act_wait_r_lcl_reg_0(ras_timer_zero_r_reg),
        .act_wait_r_lcl_reg_1(p_115_out),
        .app_en_r2_reg(app_en_r2_reg),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r),
        .bm_end_r1_reg(p_91_out),
        .bm_end_r1_reg_0(\ras_timer_r_reg[1] ),
        .bm_end_r1_reg_1(bm_end_r1_reg),
        .bm_end_r1_reg_2(bm_end_r1_reg_0),
        .bm_end_r1_reg_3(bm_end_r1_reg_1),
        .clear_req_1(clear_req_1),
        .col_wait_r_reg(col_wait_r),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_reg(demand_priority_r_reg),
        .demand_priority_r_reg_0(demand_priority_r_reg_0),
        .demand_priority_r_reg_1(demand_priority_r_reg_1),
        .demand_priority_r_reg_2(bank_state0_n_29),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ),
        .\grant_r_reg[1]_2 (bank_queue0_n_27),
        .\grant_r_reg[1]_3 (\grant_r_reg[3]_0 [0]),
        .\grant_r_reg[2] (\grant_r_reg[2]_2 ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_3 ),
        .\grant_r_reg[3] (\grant_r_reg[3]_1 ),
        .head_r_lcl_reg_0(p_89_out),
        .idle_r_lcl_reg_0(idle_r_lcl_reg),
        .idle_r_lcl_reg_1(idle_r_lcl_reg_0),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_3(idle_r_lcl_reg_2),
        .idle_r_lcl_reg_4(idle_r_lcl_reg_3),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),
        .p_103_out(p_103_out),
        .p_129_out(p_129_out),
        .p_12_out(p_12_out),
        .p_130_out(p_130_out),
        .p_145_out(p_145_out),
        .p_28_out(p_28_out),
        .p_51_out(p_51_out),
        .p_67_out(p_67_out),
        .p_7_in(p_7_in),
        .p_87_out(p_87_out),
        .p_93_out(p_93_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(clear_req),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),
        .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),
        .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg_2),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r(pre_bm_end_r),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0),
        .pre_passing_open_bank_r_reg_2(pre_passing_open_bank_r_reg_1),
        .pre_wait_r(pre_wait_r),
        .q_entry_ns(q_entry_ns),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0] (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[1] (\ras_timer_r_reg[1]_0 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_1(bank_state0_n_20),
        .rd_wr_r_lcl_reg(p_92_out),
        .rd_wr_r_lcl_reg_0(\ras_timer_r_reg[0] ),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .\req_data_buf_addr_r_reg[0] (p_90_out),
        .req_priority_r(req_priority_r),
        .req_wr_r_lcl_reg(req_wr_r_lcl_reg),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .row_hit_r(row_hit_r),
        .row_hit_r_reg(bank_compare0_n_11),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__19_0(rstdiv0_sync_r1_reg_rep__19_0),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_1),
        .rstdiv0_sync_r1_reg_rep__20_2(bank_state0_n_5),
        .set_order_q(set_order_q),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .was_priority(was_priority),
        .was_wr(was_wr));
  mig_7series_0_mig_7series_v2_3_bank_state__parameterized0 bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .Q(Q[2:1]),
        .accept_r_reg(accept_r_reg),
        .act_this_rank_r(act_this_rank_r),
        .\act_this_rank_r_reg[0]_0 (p_115_out),
        .act_wait_ns(act_wait_ns),
        .auto_pre_r_lcl_reg(bank_state0_n_20),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_0),
        .bm_end_r1_0(bm_end_r1_0),
        .col_wait_r_reg_0(col_wait_r),
        .col_wait_r_reg_1(bank_state0_n_5),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_2(demand_act_priority_r_2),
        .demand_act_priority_r_reg_0(demand_act_priority_r_reg),
        .demand_act_priority_r_reg_1(demand_act_priority_r_reg_0),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_0(demand_priority_r_0),
        .demand_priority_r_reg_0(bank_state0_n_29),
        .demanded_prior_r_3(demanded_prior_r_3),
        .demanded_prior_r_reg_0(demand_priority_r),
        .demanded_prior_r_reg_1(demanded_prior_r),
        .demanded_prior_r_reg_2(demanded_prior_r_reg),
        .\grant_r_reg[1] (\grant_r_reg[1]_2 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_3 ),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_4 [1]),
        .\grant_r_reg[1]_2 (\grant_r_reg[1]_5 ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .\grant_r_reg[2]_1 (\grant_r_reg[2]_1 ),
        .\grant_r_reg[2]_2 (\grant_r_reg[2]_4 ),
        .\grant_r_reg[3] (\grant_r_reg[3] ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 ),
        .granted_col_r_reg(granted_col_r_reg),
        .granted_col_r_reg_0(granted_col_r_reg_0),
        .granted_pre_ns(granted_pre_ns),
        .granted_row_ns(granted_row_ns),
        .granted_row_r_reg(granted_row_r_reg),
        .head_r_lcl_reg(bank_queue0_n_27),
        .\last_master_r_reg[0] (\last_master_r_reg[0] ),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .override_demand_r(override_demand_r),
        .p_87_out(p_87_out),
        .p_89_out(p_89_out),
        .p_90_out(p_90_out),
        .p_91_out(p_91_out),
        .p_93_out(p_93_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[1] (bank_queue0_n_16),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r_lcl_reg(p_92_out),
        .rd_wr_r_lcl_reg_0(bank_compare0_n_10),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19_0),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_1),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r(wr_this_rank_r),
        .wr_this_rank_r0(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_cntrl" *) 
module mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized1
   (p_51_out,
    p_71_out,
    p_53_out,
    p_48_out,
    ras_timer_zero_r_reg,
    p_76_out,
    demand_act_priority_r,
    act_this_rank_r,
    demand_priority_r,
    demanded_prior_r,
    override_demand_r,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    auto_pre_r_lcl_reg,
    tail_r,
    p_50_out,
    act_wait_r_lcl_reg,
    \grant_r_reg[0] ,
    req_bank_rdy_r_reg,
    head_r_lcl_reg,
    Q,
    ras_timer_zero_r_reg_0,
    accept_ns,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    pass_open_bank_r_lcl_reg,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[1] ,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[1] ,
    \order_q_r_reg[0] ,
    \order_q_r_reg[1] ,
    \grant_r_reg[2] ,
    \q_entry_r_reg[1] ,
    periodic_rd_ack_ns,
    \compute_tail.tail_r_lcl_reg ,
    \ras_timer_r_reg[0]_0 ,
    auto_pre_r,
    \grant_r_reg[2]_0 ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \grant_r_reg[2]_1 ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    ofs_rdy_r0,
    ofs_rdy_r0_0,
    ofs_rdy_r0_1,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[0]_0 ,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    CLK,
    periodic_rd_insert,
    hi_priority,
    p_67_out,
    override_demand_ns,
    rstdiv0_sync_r1_reg_rep__0,
    phy_mc_ctl_full,
    rstdiv0_sync_r1_reg_rep__1,
    of_ctl_full_v,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__19,
    req_wr_r_lcl_reg,
    idle_r_lcl_reg,
    \grant_r_reg[1]_0 ,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    idle_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    rb_hit_busy_r_reg,
    pre_bm_end_r_reg,
    p_91_out,
    p_130_out,
    rstdiv0_sync_r1_reg_rep__19_0,
    \grant_r_reg[2]_2 ,
    \grant_r_reg[3] ,
    \rnk_config_strobe_r_reg[0] ,
    idle_r_lcl_reg_1,
    idle_r_lcl_reg_2,
    idle_r_lcl_reg_3,
    init_calib_complete_reg_rep,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    app_en_r2_reg,
    periodic_rd_ack_r_lcl_reg,
    was_priority,
    rstdiv0_sync_r1_reg_rep__20_0,
    \grant_r_reg[2]_3 ,
    demanded_prior_r_reg,
    demand_priority_r_2,
    demanded_prior_r_reg_0,
    \app_addr_r1_reg[22] ,
    p_25_out,
    p_103_out,
    p_142_out,
    \rnk_config_strobe_r_reg[0]_0 ,
    p_14_out,
    p_15_out,
    rd_wr_r_lcl_reg,
    rd_wr_r_lcl_reg_0,
    \ras_timer_r_reg[1]_0 ,
    rd_wr_r_lcl_reg_1,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    idle_r_lcl_reg_4,
    periodic_rd_ack_r_lcl_reg_0,
    rb_hit_busy_r_reg_0,
    rstdiv0_sync_r1_reg_rep__20_1,
    pre_passing_open_bank_r_reg,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    p_106_out,
    clear_req,
    p_145_out,
    clear_req_3,
    p_28_out,
    \grant_r_reg[3]_0 ,
    \grant_r_reg[3]_1 ,
    periodic_rd_ack_r_lcl_reg_1,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    accept_r_reg,
    row,
    demanded_prior_r_4,
    \req_row_r_lcl_reg[10] ,
    act_wait_r_lcl_reg_0,
    p_131_out,
    phy_mc_data_full,
    p_92_out,
    granted_col_r_reg,
    order_q_r,
    req_wr_r_lcl_reg_0,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] ,
    rstdiv0_sync_r1_reg_rep__24,
    idle_r_lcl_reg_5,
    \q_entry_r_reg[1]_0 ,
    \maintenance_request.maint_zq_r_lcl_reg_0 );
  output p_51_out;
  output p_71_out;
  output p_53_out;
  output p_48_out;
  output ras_timer_zero_r_reg;
  output p_76_out;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demand_priority_r;
  output demanded_prior_r;
  output override_demand_r;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output auto_pre_r_lcl_reg;
  output tail_r;
  output p_50_out;
  output act_wait_r_lcl_reg;
  output \grant_r_reg[0] ;
  output req_bank_rdy_r_reg;
  output head_r_lcl_reg;
  output [2:0]Q;
  output ras_timer_zero_r_reg_0;
  output accept_ns;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output pass_open_bank_r_lcl_reg;
  output \grant_r_reg[0]_0 ;
  output \grant_r_reg[1] ;
  output \ras_timer_r_reg[0] ;
  output \ras_timer_r_reg[1] ;
  output \order_q_r_reg[0] ;
  output \order_q_r_reg[1] ;
  output \grant_r_reg[2] ;
  output \q_entry_r_reg[1] ;
  output periodic_rd_ack_ns;
  output \compute_tail.tail_r_lcl_reg ;
  output \ras_timer_r_reg[0]_0 ;
  output auto_pre_r;
  output \grant_r_reg[2]_0 ;
  output [13:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output \grant_r_reg[2]_1 ;
  output [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  output ofs_rdy_r0;
  output ofs_rdy_r0_0;
  output ofs_rdy_r0_1;
  output \order_q_r_reg[1]_0 ;
  output \order_q_r_reg[0]_0 ;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input CLK;
  input periodic_rd_insert;
  input hi_priority;
  input p_67_out;
  input override_demand_ns;
  input rstdiv0_sync_r1_reg_rep__0;
  input phy_mc_ctl_full;
  input rstdiv0_sync_r1_reg_rep__1;
  input [0:0]of_ctl_full_v;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__19;
  input req_wr_r_lcl_reg;
  input idle_r_lcl_reg;
  input \grant_r_reg[1]_0 ;
  input \wtr_timer.wtr_cnt_r_reg[1] ;
  input idle_r_lcl_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input rb_hit_busy_r_reg;
  input pre_bm_end_r_reg;
  input p_91_out;
  input p_130_out;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input [0:0]\grant_r_reg[2]_2 ;
  input [2:0]\grant_r_reg[3] ;
  input \rnk_config_strobe_r_reg[0] ;
  input idle_r_lcl_reg_1;
  input idle_r_lcl_reg_2;
  input idle_r_lcl_reg_3;
  input init_calib_complete_reg_rep;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input app_en_r2_reg;
  input periodic_rd_ack_r_lcl_reg;
  input was_priority;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input \grant_r_reg[2]_3 ;
  input demanded_prior_r_reg;
  input demand_priority_r_2;
  input demanded_prior_r_reg_0;
  input [0:0]\app_addr_r1_reg[22] ;
  input p_25_out;
  input p_103_out;
  input p_142_out;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input p_14_out;
  input p_15_out;
  input rd_wr_r_lcl_reg;
  input rd_wr_r_lcl_reg_0;
  input \ras_timer_r_reg[1]_0 ;
  input rd_wr_r_lcl_reg_1;
  input bm_end_r1_reg;
  input bm_end_r1_reg_0;
  input bm_end_r1_reg_1;
  input idle_r_lcl_reg_4;
  input periodic_rd_ack_r_lcl_reg_0;
  input rb_hit_busy_r_reg_0;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input pre_passing_open_bank_r_reg;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input p_106_out;
  input clear_req;
  input p_145_out;
  input clear_req_3;
  input p_28_out;
  input \grant_r_reg[3]_0 ;
  input [1:0]\grant_r_reg[3]_1 ;
  input periodic_rd_ack_r_lcl_reg_1;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input accept_r_reg;
  input [13:0]row;
  input demanded_prior_r_4;
  input \req_row_r_lcl_reg[10] ;
  input act_wait_r_lcl_reg_0;
  input p_131_out;
  input phy_mc_data_full;
  input p_92_out;
  input granted_col_r_reg;
  input [1:0]order_q_r;
  input req_wr_r_lcl_reg_0;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;
  input rstdiv0_sync_r1_reg_rep__24;
  input idle_r_lcl_reg_5;
  input \q_entry_r_reg[1]_0 ;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;

  wire CLK;
  wire [2:0]Q;
  wire accept_ns;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_en_r2_reg;
  wire app_rdy_r_reg;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire bank_compare0_n_12;
  wire bank_compare0_n_15;
  wire bank_compare0_n_7;
  wire bank_queue0_n_17;
  wire bank_queue0_n_18;
  wire bank_state0_n_13;
  wire bank_state0_n_22;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire clear_req;
  wire clear_req_3;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire col_wait_r;
  wire \compute_tail.tail_r_lcl_reg ;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire demand_act_priority_r;
  wire demand_priority_r;
  wire demand_priority_r_2;
  wire demanded_prior_r;
  wire demanded_prior_r_4;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[2]_1 ;
  wire [0:0]\grant_r_reg[2]_2 ;
  wire \grant_r_reg[2]_3 ;
  wire [2:0]\grant_r_reg[3] ;
  wire \grant_r_reg[3]_0 ;
  wire [1:0]\grant_r_reg[3]_1 ;
  wire granted_col_r_reg;
  wire head_r_lcl_reg;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire idle_r_lcl_reg_5;
  wire init_calib_complete_reg_rep;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire [0:0]of_ctl_full_v;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r0_0;
  wire ofs_rdy_r0_1;
  wire [1:0]order_q_r;
  wire [1:0]order_q_r_0;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire override_demand_ns;
  wire override_demand_r;
  wire p_103_out;
  wire p_106_out;
  wire p_130_out;
  wire p_131_out;
  wire p_142_out;
  wire p_145_out;
  wire p_14_out;
  wire p_15_out;
  wire p_25_out;
  wire p_28_out;
  wire p_48_out;
  wire p_50_out;
  wire p_51_out;
  wire p_52_out;
  wire p_53_out;
  wire p_54_out;
  wire p_55_out;
  wire p_64_out;
  wire p_67_out;
  wire p_71_out;
  wire p_76_out;
  wire p_91_out;
  wire p_92_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_ns;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_insert;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_wait_r;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire q_has_priority;
  wire q_has_rd;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_priority_r;
  wire \req_row_r_lcl_reg[10] ;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire [13:0]row;
  wire row_hit_r;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire set_order_q;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;

  mig_7series_0_mig_7series_v2_3_bank_compare_0 bank_compare0
       (.CLK(CLK),
        .E(p_55_out),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0),
        .act_wait_r_lcl_reg_0(p_76_out),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_rdy_r_reg(app_rdy_r_reg),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .col_wait_r(col_wait_r),
        .col_wait_r_reg(bank_queue0_n_17),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ),
        .demand_priority_r_reg(bank_compare0_n_7),
        .demand_priority_r_reg_0(bank_state0_n_13),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[1] (\grant_r_reg[1]_0 ),
        .\grant_r_reg[3] (\grant_r_reg[3] [2:1]),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_1 ),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .idle_r_lcl_reg_0(p_51_out),
        .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .order_q_r(order_q_r_0),
        .\order_q_r_reg[0] (\order_q_r_reg[0] ),
        .\order_q_r_reg[1] (\order_q_r_reg[1] ),
        .p_103_out(p_103_out),
        .p_142_out(p_142_out),
        .p_14_out(p_14_out),
        .p_15_out(p_15_out),
        .p_25_out(p_25_out),
        .p_48_out(p_48_out),
        .p_52_out(p_52_out),
        .p_54_out(p_54_out),
        .p_64_out(p_64_out),
        .p_67_out(p_67_out),
        .p_71_out(p_71_out),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg(bank_compare0_n_15),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_0),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r(pre_bm_end_r),
        .ras_timer_zero_r_reg(bank_compare0_n_12),
        .\rd_this_rank_r_reg[0] (p_53_out),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ),
        .row(row),
        .row_hit_r(row_hit_r),
        .set_order_q(set_order_q),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r0(wr_this_rank_r0),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ));
  mig_7series_0_mig_7series_v2_3_bank_queue__parameterized1 bank_queue0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .E(p_55_out),
        .Q(Q),
        .accept_ns(accept_ns),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_0(ras_timer_zero_r_reg_0),
        .act_wait_r_lcl_reg_1(p_76_out),
        .app_en_r2_reg(app_en_r2_reg),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r),
        .bm_end_r1_reg(\ras_timer_r_reg[1] ),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .bm_end_r1_reg_1(bm_end_r1_reg_0),
        .bm_end_r1_reg_2(bm_end_r1_reg_1),
        .clear_req(clear_req),
        .clear_req_3(clear_req_3),
        .col_wait_r(col_wait_r),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .\grant_r_reg[0] (bank_queue0_n_17),
        .\grant_r_reg[2] (\grant_r_reg[2]_1 ),
        .\grant_r_reg[2]_0 (\grant_r_reg[3] [1]),
        .\grant_r_reg[2]_1 (\grant_r_reg[2]_2 ),
        .\grant_r_reg[3] (\grant_r_reg[3]_0 ),
        .head_r_lcl_reg_0(p_50_out),
        .head_r_lcl_reg_1(head_r_lcl_reg),
        .idle_r_lcl_reg_0(idle_r_lcl_reg),
        .idle_r_lcl_reg_1(idle_r_lcl_reg_0),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_3(idle_r_lcl_reg_2),
        .idle_r_lcl_reg_4(idle_r_lcl_reg_3),
        .idle_r_lcl_reg_5(idle_r_lcl_reg_4),
        .idle_r_lcl_reg_6(idle_r_lcl_reg_5),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .order_q_r(order_q_r),
        .order_q_r_0(order_q_r_0),
        .\order_q_r_reg[0]_0 (\order_q_r_reg[0]_0 ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[1]_0 ),
        .ordered_r_lcl_reg_0(\order_q_r_reg[1] ),
        .ordered_r_lcl_reg_1(\order_q_r_reg[0] ),
        .p_106_out(p_106_out),
        .p_130_out(p_130_out),
        .p_145_out(p_145_out),
        .p_28_out(p_28_out),
        .p_48_out(p_48_out),
        .p_54_out(p_54_out),
        .p_64_out(p_64_out),
        .p_91_out(p_91_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .periodic_rd_ack_ns(periodic_rd_ack_ns),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),
        .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r(pre_bm_end_r),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0),
        .pre_passing_open_bank_r_reg_2(pre_passing_open_bank_r_reg_1),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .q_has_priority(q_has_priority),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0] (bank_queue0_n_18),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[1] (\ras_timer_r_reg[1]_0 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_1(bank_state0_n_22),
        .rd_wr_r_lcl_reg(p_53_out),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1),
        .\req_data_buf_addr_r_reg[0] (p_51_out),
        .req_wr_r_lcl_reg(req_bank_rdy_r_reg),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),
        .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .row_hit_r(row_hit_r),
        .row_hit_r_reg(bank_compare0_n_15),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__19_0(rstdiv0_sync_r1_reg_rep__19_0),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_1),
        .set_order_q(set_order_q),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .was_priority(was_priority),
        .was_wr(was_wr));
  mig_7series_0_mig_7series_v2_3_bank_state__parameterized1 bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .accept_r_reg(accept_r_reg),
        .act_this_rank_r(act_this_rank_r),
        .\act_this_rank_r_reg[0]_0 (p_76_out),
        .act_wait_ns(act_wait_ns),
        .auto_pre_r_lcl_reg(bank_state0_n_22),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .col_wait_r(col_wait_r),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_priority_r_2(demand_priority_r_2),
        .demanded_prior_r(demanded_prior_r),
        .demanded_prior_r_4(demanded_prior_r_4),
        .demanded_prior_r_reg_0(demand_priority_r),
        .demanded_prior_r_reg_1(demanded_prior_r_reg),
        .demanded_prior_r_reg_2(demanded_prior_r_reg_0),
        .\grant_r_reg[0] (bank_state0_n_13),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .\grant_r_reg[2]_1 (\grant_r_reg[2]_2 ),
        .\grant_r_reg[2]_2 (\grant_r_reg[3] [1:0]),
        .\grant_r_reg[2]_3 (\grant_r_reg[2]_3 ),
        .\grant_r_reg[2]_4 (\grant_r_reg[3]_1 [0]),
        .granted_col_r_reg(granted_col_r_reg),
        .idle_r_lcl_reg(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .of_ctl_full_v(of_ctl_full_v),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .ofs_rdy_r0_0(ofs_rdy_r0_0),
        .ofs_rdy_r0_1(ofs_rdy_r0_1),
        .\order_q_r_reg[0] (bank_compare0_n_7),
        .override_demand_ns(override_demand_ns),
        .override_demand_r(override_demand_r),
        .p_131_out(p_131_out),
        .p_14_out(p_14_out),
        .p_48_out(p_48_out),
        .p_50_out(p_50_out),
        .p_51_out(p_51_out),
        .p_52_out(p_52_out),
        .p_54_out(p_54_out),
        .p_92_out(p_92_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[1] (bank_queue0_n_18),
        .q_has_priority(q_has_priority),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r_lcl_reg(p_53_out),
        .rd_wr_r_lcl_reg_0(bank_compare0_n_12),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_priority_r(req_priority_r),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0]_0 ),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19_0),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r(wr_this_rank_r),
        .wr_this_rank_r0(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_cntrl" *) 
module mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized2
   (p_12_out,
    p_32_out,
    p_14_out,
    p_15_out,
    p_9_out,
    ras_timer_zero_r_reg,
    p_37_out,
    col_wait_r,
    demand_act_priority_r,
    act_this_rank_r,
    demand_priority_r,
    demanded_prior_r,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    auto_pre_r_lcl_reg,
    tail_r,
    p_11_out,
    order_q_r,
    act_wait_r_lcl_reg,
    granted_col_r_reg,
    ras_timer_zero_r_reg_0,
    demand_priority_r_reg,
    \q_entry_r_reg[0] ,
    \grant_r_reg[3] ,
    pass_open_bank_r_lcl_reg,
    \grant_r_reg[1] ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \ras_timer_r_reg[0] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    \ras_timer_r_reg[1] ,
    demand_priority_r_reg_0,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    head_r_lcl_reg,
    \compute_tail.tail_r_lcl_reg ,
    head_r_lcl_reg_0,
    \ras_timer_r_reg[0]_0 ,
    auto_pre_r,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[1]_1 ,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \grant_r_reg[0] ,
    \grant_r_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[10] ,
    \grant_r_reg[3]_0 ,
    demanded_prior_r_reg,
    \grant_r_reg[1]_2 ,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    p_25_out,
    CLK,
    periodic_rd_insert,
    hi_priority,
    p_28_out,
    rstdiv0_sync_r1_reg_rep__0,
    ofs_rdy_r0,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__19,
    \order_q_r_reg[0] ,
    \order_q_r_reg[0]_0 ,
    pre_bm_end_r_reg,
    idle_r_lcl_reg,
    \grant_r_reg[1]_3 ,
    \rnk_config_strobe_r_reg[0]_1 ,
    idle_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    rb_hit_busy_r_reg,
    rstdiv0_sync_r1_reg_rep__19_0,
    \grant_r_reg[3]_1 ,
    Q,
    override_demand_r,
    demanded_prior_r_reg_0,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    app_en_r2_reg,
    periodic_rd_ack_r_lcl_reg,
    was_priority,
    rstdiv0_sync_r1_reg_rep__20_0,
    demanded_prior_r_reg_1,
    demand_priority_r_0,
    \grant_r_reg[3]_2 ,
    cs_en2,
    \app_addr_r1_reg[22] ,
    \ras_timer_r_reg[0]_1 ,
    rd_wr_r_lcl_reg,
    rd_wr_r_lcl_reg_0,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    col_wait_r_reg,
    demand_priority_r_reg_1,
    \rnk_config_strobe_r_reg[0]_2 ,
    req_wr_r_lcl_reg,
    periodic_rd_ack_r_lcl_reg_0,
    idle_r_lcl_reg_1,
    p_126_out,
    p_87_out,
    p_48_out,
    p_130_out,
    pre_bm_end_r_reg_0,
    p_91_out,
    rstdiv0_sync_r1_reg_rep__20_1,
    pre_passing_open_bank_r_reg,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    p_106_out,
    clear_req,
    p_145_out,
    clear_req_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    periodic_rd_ack_r_lcl_reg_1,
    p_67_out,
    \grant_r_reg[2]_0 ,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    accept_r_reg,
    act_wait_r_lcl_reg_0,
    act_wait_r_lcl_reg_1,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    inhbt_act_faw_r,
    act_wait_r_lcl_reg_2,
    auto_pre_r_lcl_reg_0,
    \last_master_r_reg[2] ,
    row,
    \req_row_r_lcl_reg[10] ,
    p_115_out,
    \grant_r_reg[3]_3 ,
    demanded_prior_r_2,
    granted_col_r_reg_0,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] ,
    rstdiv0_sync_r1_reg_rep__24,
    idle_r_lcl_reg_2,
    q_entry_ns,
    \maintenance_request.maint_zq_r_lcl_reg_0 );
  output p_12_out;
  output p_32_out;
  output p_14_out;
  output p_15_out;
  output p_9_out;
  output ras_timer_zero_r_reg;
  output p_37_out;
  output col_wait_r;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demand_priority_r;
  output demanded_prior_r;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output auto_pre_r_lcl_reg;
  output tail_r;
  output p_11_out;
  output [1:0]order_q_r;
  output act_wait_r_lcl_reg;
  output granted_col_r_reg;
  output ras_timer_zero_r_reg_0;
  output demand_priority_r_reg;
  output [0:0]\q_entry_r_reg[0] ;
  output \grant_r_reg[3] ;
  output pass_open_bank_r_lcl_reg;
  output \grant_r_reg[1] ;
  output \cmd_pipe_plus.mc_address_reg[38] ;
  output [12:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output \ras_timer_r_reg[0] ;
  output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  output \ras_timer_r_reg[1] ;
  output demand_priority_r_reg_0;
  output \rnk_config_strobe_r_reg[0] ;
  output \rnk_config_strobe_r_reg[0]_0 ;
  output head_r_lcl_reg;
  output \compute_tail.tail_r_lcl_reg ;
  output head_r_lcl_reg_0;
  output \ras_timer_r_reg[0]_0 ;
  output auto_pre_r;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[1]_1 ;
  output \pre_4_1_1T_arb.granted_pre_r_reg ;
  output \grant_r_reg[0] ;
  output \grant_r_reg[2] ;
  output \cmd_pipe_plus.mc_address_reg[10] ;
  output \grant_r_reg[3]_0 ;
  output demanded_prior_r_reg;
  output \grant_r_reg[1]_2 ;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  output p_25_out;
  input CLK;
  input periodic_rd_insert;
  input hi_priority;
  input p_28_out;
  input rstdiv0_sync_r1_reg_rep__0;
  input ofs_rdy_r0;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__19;
  input \order_q_r_reg[0] ;
  input \order_q_r_reg[0]_0 ;
  input pre_bm_end_r_reg;
  input idle_r_lcl_reg;
  input \grant_r_reg[1]_3 ;
  input \rnk_config_strobe_r_reg[0]_1 ;
  input idle_r_lcl_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input rb_hit_busy_r_reg;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input [2:0]\grant_r_reg[3]_1 ;
  input [1:0]Q;
  input override_demand_r;
  input demanded_prior_r_reg_0;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input app_en_r2_reg;
  input periodic_rd_ack_r_lcl_reg;
  input was_priority;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input demanded_prior_r_reg_1;
  input demand_priority_r_0;
  input [0:0]\grant_r_reg[3]_2 ;
  input cs_en2;
  input [0:0]\app_addr_r1_reg[22] ;
  input \ras_timer_r_reg[0]_1 ;
  input rd_wr_r_lcl_reg;
  input rd_wr_r_lcl_reg_0;
  input bm_end_r1_reg;
  input bm_end_r1_reg_0;
  input bm_end_r1_reg_1;
  input col_wait_r_reg;
  input demand_priority_r_reg_1;
  input \rnk_config_strobe_r_reg[0]_2 ;
  input req_wr_r_lcl_reg;
  input periodic_rd_ack_r_lcl_reg_0;
  input idle_r_lcl_reg_1;
  input p_126_out;
  input p_87_out;
  input p_48_out;
  input p_130_out;
  input pre_bm_end_r_reg_0;
  input p_91_out;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input pre_passing_open_bank_r_reg;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input p_106_out;
  input clear_req;
  input p_145_out;
  input clear_req_1;
  input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  input periodic_rd_ack_r_lcl_reg_1;
  input p_67_out;
  input \grant_r_reg[2]_0 ;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input accept_r_reg;
  input act_wait_r_lcl_reg_0;
  input act_wait_r_lcl_reg_1;
  input \generate_maint_cmds.insert_maint_r_lcl_reg ;
  input inhbt_act_faw_r;
  input act_wait_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_0;
  input \last_master_r_reg[2] ;
  input [13:0]row;
  input [0:0]\req_row_r_lcl_reg[10] ;
  input p_115_out;
  input \grant_r_reg[3]_3 ;
  input demanded_prior_r_2;
  input granted_col_r_reg_0;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;
  input rstdiv0_sync_r1_reg_rep__24;
  input idle_r_lcl_reg_2;
  input [0:0]q_entry_ns;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;

  wire CLK;
  wire [1:0]Q;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire act_wait_r_lcl_reg_2;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_en_r2_reg;
  wire app_rdy_r_reg;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire bank_compare0_n_6;
  wire bank_compare0_n_9;
  wire bank_queue0_n_13;
  wire bank_state0_n_21;
  wire bank_state0_n_30;
  wire bank_state0_n_5;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire clear_req;
  wire clear_req_1;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire \cmd_pipe_plus.mc_address_reg[38] ;
  wire [12:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire col_wait_r;
  wire col_wait_r_reg;
  wire \compute_tail.tail_r_lcl_reg ;
  wire cs_en2;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire demand_act_priority_r;
  wire demand_priority_ns;
  wire demand_priority_r;
  wire demand_priority_r_0;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demanded_prior_r;
  wire demanded_prior_r_2;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[1]_3 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[3] ;
  wire \grant_r_reg[3]_0 ;
  wire [2:0]\grant_r_reg[3]_1 ;
  wire [0:0]\grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire inhbt_act_faw_r;
  wire \last_master_r_reg[2] ;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire [1:0]order_q_r;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[0]_0 ;
  wire override_demand_r;
  wire p_106_out;
  wire p_115_out;
  wire p_11_out;
  wire p_126_out;
  wire p_12_out;
  wire p_130_out;
  wire p_13_out;
  wire p_145_out;
  wire p_14_out;
  wire p_15_out;
  wire p_16_out;
  wire p_25_out;
  wire p_28_out;
  wire p_32_out;
  wire [10:10]p_34_out;
  wire p_37_out;
  wire p_48_out;
  wire p_67_out;
  wire p_87_out;
  wire p_91_out;
  wire p_9_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_insert;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire [0:0]\q_entry_r_reg[0] ;
  wire q_has_rd;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[1] ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire rb_hit_busy_r_reg;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire req_bank_rdy_ns;
  wire req_priority_r;
  wire [0:0]\req_row_r_lcl_reg[10] ;
  wire req_wr_r_lcl_reg;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire \rnk_config_strobe_r_reg[0]_1 ;
  wire \rnk_config_strobe_r_reg[0]_2 ;
  wire [13:0]row;
  wire row_hit_r;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;

  mig_7series_0_mig_7series_v2_3_bank_compare bank_compare0
       (.CLK(CLK),
        .E(p_16_out),
        .Q(Q[1]),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_rdy_r_reg(app_rdy_r_reg),
        .bm_end_r1_reg(p_15_out),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_address_reg[41] ({\cmd_pipe_plus.mc_address_reg[41] [12:10],p_34_out,\cmd_pipe_plus.mc_address_reg[41] [9:0]}),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ),
        .head_r_lcl_reg(head_r_lcl_reg_0),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(demand_priority_r_reg_0),
        .idle_r_lcl_reg_0(p_12_out),
        .\maint_controller.maint_wip_r_lcl_reg (\maint_controller.maint_wip_r_lcl_reg ),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .p_13_out(p_13_out),
        .p_28_out(p_28_out),
        .p_32_out(p_32_out),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg(bank_compare0_n_9),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r(pre_bm_end_r),
        .q_has_priority_r_reg(p_9_out),
        .ras_timer_zero_r_reg(bank_compare0_n_6),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rd_this_rank_r_reg[0] (p_14_out),
        .req_priority_r(req_priority_r),
        .row(row),
        .row_hit_r(row_hit_r),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r0(wr_this_rank_r0));
  mig_7series_0_mig_7series_v2_3_bank_queue__parameterized2 bank_queue0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .E(p_16_out),
        .Q(Q[1]),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_0(ras_timer_zero_r_reg_0),
        .act_wait_r_lcl_reg_1(p_37_out),
        .app_en_r2_reg(app_en_r2_reg),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r),
        .bm_end_r1_reg(\ras_timer_r_reg[1] ),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .bm_end_r1_reg_1(bm_end_r1_reg_0),
        .bm_end_r1_reg_2(bm_end_r1_reg_1),
        .clear_req(clear_req),
        .clear_req_1(clear_req_1),
        .col_wait_r_reg(col_wait_r),
        .col_wait_r_reg_0(col_wait_r_reg),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_reg(demand_priority_r_reg),
        .demand_priority_r_reg_0(demand_priority_r_reg_0),
        .demand_priority_r_reg_1(bank_state0_n_30),
        .demand_priority_r_reg_2(demand_priority_r_reg_1),
        .\grant_r_reg[1] (\grant_r_reg[1]_3 ),
        .\grant_r_reg[2] (\grant_r_reg[2]_0 ),
        .\grant_r_reg[3] (\grant_r_reg[3]_0 ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_1 [2]),
        .granted_col_r_reg(granted_col_r_reg),
        .head_r_lcl_reg_0(p_11_out),
        .head_r_lcl_reg_1(head_r_lcl_reg),
        .idle_r_lcl_reg_0(idle_r_lcl_reg),
        .idle_r_lcl_reg_1(idle_r_lcl_reg_0),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_3(idle_r_lcl_reg_2),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .order_q_r(order_q_r),
        .\order_q_r_reg[0]_0 (\order_q_r_reg[0] ),
        .\order_q_r_reg[0]_1 (\order_q_r_reg[0]_0 ),
        .p_106_out(p_106_out),
        .p_126_out(p_126_out),
        .p_130_out(p_130_out),
        .p_145_out(p_145_out),
        .p_25_out(p_25_out),
        .p_48_out(p_48_out),
        .p_67_out(p_67_out),
        .p_87_out(p_87_out),
        .p_91_out(p_91_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),
        .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r(pre_bm_end_r),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0),
        .pre_passing_open_bank_r_reg_2(pre_passing_open_bank_r_reg_1),
        .pre_wait_r(pre_wait_r),
        .q_entry_ns(q_entry_ns),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0] (bank_queue0_n_13),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[1] (\ras_timer_r_reg[0] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_0(p_9_out),
        .rb_hit_busy_r_reg_1(bank_state0_n_21),
        .rd_wr_r_lcl_reg(p_14_out),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .\req_data_buf_addr_r_reg[0] (p_12_out),
        .req_priority_r(req_priority_r),
        .req_wr_r_lcl_reg(p_15_out),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_0 ),
        .\rnk_config_strobe_r_reg[0]_1 (\rnk_config_strobe_r_reg[0]_1 ),
        .\rnk_config_strobe_r_reg[0]_2 (\rnk_config_strobe_r_reg[0]_2 ),
        .row_hit_r(row_hit_r),
        .row_hit_r_reg(bank_compare0_n_9),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__19_0(bank_state0_n_5),
        .rstdiv0_sync_r1_reg_rep__19_1(rstdiv0_sync_r1_reg_rep__19_0),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_1),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .was_priority(was_priority),
        .was_wr(was_wr));
  mig_7series_0_mig_7series_v2_3_bank_state__parameterized2 bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .Q(Q),
        .accept_r_reg(accept_r_reg),
        .act_this_rank_r(act_this_rank_r),
        .\act_this_rank_r_reg[0]_0 (p_37_out),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2),
        .auto_pre_r_lcl_reg(bank_state0_n_21),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_0),
        .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ),
        .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ),
        .col_wait_r_reg_0(col_wait_r),
        .col_wait_r_reg_1(bank_state0_n_5),
        .cs_en2(cs_en2),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_0(demand_priority_r_0),
        .demand_priority_r_reg_0(bank_state0_n_30),
        .demanded_prior_r_2(demanded_prior_r_2),
        .demanded_prior_r_reg_0(demand_priority_r),
        .demanded_prior_r_reg_1(demanded_prior_r),
        .demanded_prior_r_reg_2(demanded_prior_r_reg),
        .demanded_prior_r_reg_3(demanded_prior_r_reg_0),
        .demanded_prior_r_reg_4(demanded_prior_r_reg_1),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ),
        .\grant_r_reg[1]_2 (\grant_r_reg[1]_2 ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[3] (\grant_r_reg[3] ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_1 ),
        .\grant_r_reg[3]_1 (\grant_r_reg[3]_2 ),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_3 ),
        .granted_col_r_reg(granted_col_r_reg_0),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .\last_master_r_reg[2] (\last_master_r_reg[2] ),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .override_demand_r(override_demand_r),
        .p_115_out(p_115_out),
        .p_11_out(p_11_out),
        .p_12_out(p_12_out),
        .p_13_out(p_13_out),
        .p_15_out(p_15_out),
        .p_9_out(p_9_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[1] (bank_queue0_n_13),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r_lcl_reg(p_14_out),
        .rd_wr_r_lcl_reg_0(bank_compare0_n_6),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .\req_row_r_lcl_reg[10] (p_34_out),
        .\req_row_r_lcl_reg[10]_0 (\req_row_r_lcl_reg[10] ),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19_0),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg(auto_pre_r_lcl_reg),
        .wr_this_rank_r(wr_this_rank_r),
        .wr_this_rank_r0(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_common" *) 
module mig_7series_0_mig_7series_v2_3_bank_common
   (req_periodic_rd_r_lcl_reg,
    was_wr,
    insert_maint_r1_lcl_reg,
    \maint_controller.maint_rdy_r1_reg_0 ,
    periodic_rd_cntr_r,
    was_priority,
    hi_priority,
    \compute_tail.tail_r_lcl_reg ,
    \compute_tail.tail_r_lcl_reg_0 ,
    \compute_tail.tail_r_lcl_reg_1 ,
    \compute_tail.tail_r_lcl_reg_2 ,
    \compute_tail.tail_r_lcl_reg_3 ,
    \compute_tail.tail_r_lcl_reg_4 ,
    \maint_controller.maint_hit_busies_r_reg[2]_0 ,
    head_r_lcl_reg,
    \maint_controller.maint_hit_busies_r_reg[3]_0 ,
    q_has_priority_r_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    \maint_controller.maint_hit_busies_r_reg[0]_0 ,
    \maint_controller.maint_hit_busies_r_reg[1]_0 ,
    \order_q_r_reg[0] ,
    pass_open_bank_r_lcl_reg,
    pass_open_bank_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    auto_pre_r_lcl_reg,
    q_has_rd_r_reg,
    head_r_lcl_reg_2,
    periodic_rd_insert,
    \maintenance_request.upd_last_master_r_reg ,
    head_r_lcl_reg_3,
    E,
    p_7_in,
    CLK,
    periodic_rd_ack_ns,
    accept_ns,
    was_wr0,
    maint_srx_r,
    rstdiv0_sync_r1_reg_rep__20,
    rstdiv0_sync_r1_reg_rep__1,
    rstdiv0_sync_r1_reg_rep__19,
    p_90_out,
    pre_bm_end_r_reg,
    tail_r,
    p_51_out,
    pre_bm_end_r_reg_0,
    tail_r_0,
    p_12_out,
    pre_bm_end_r_reg_1,
    tail_r_1,
    \periodic_read_request.periodic_rd_r_lcl_reg ,
    pre_bm_end_r_reg_2,
    p_91_out,
    p_130_out,
    pre_bm_end_r_reg_3,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    p_129_out,
    \maintenance_request.maint_zq_r_lcl_reg ,
    clear_req,
    app_rdy_r_reg,
    app_en_r2,
    p_89_out,
    clear_req_2,
    p_128_out,
    \grant_r_reg[3] ,
    p_15_out,
    p_11_out,
    \grant_r_reg[2] ,
    p_50_out,
    tail_r_3,
    p_126_out,
    p_87_out,
    p_48_out,
    p_9_out,
    rstdiv0_sync_r1_reg_rep__21,
    rstdiv0_sync_r1_reg_rep__19_0,
    maint_req_r,
    maint_zq_r,
    \maintenance_request.maint_sre_r_lcl_reg );
  output req_periodic_rd_r_lcl_reg;
  output was_wr;
  output insert_maint_r1_lcl_reg;
  output \maint_controller.maint_rdy_r1_reg_0 ;
  output periodic_rd_cntr_r;
  output was_priority;
  output hi_priority;
  output \compute_tail.tail_r_lcl_reg ;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output \compute_tail.tail_r_lcl_reg_1 ;
  output \compute_tail.tail_r_lcl_reg_2 ;
  output \compute_tail.tail_r_lcl_reg_3 ;
  output \compute_tail.tail_r_lcl_reg_4 ;
  output \maint_controller.maint_hit_busies_r_reg[2]_0 ;
  output head_r_lcl_reg;
  output \maint_controller.maint_hit_busies_r_reg[3]_0 ;
  output q_has_priority_r_reg;
  output head_r_lcl_reg_0;
  output head_r_lcl_reg_1;
  output \maint_controller.maint_hit_busies_r_reg[0]_0 ;
  output \maint_controller.maint_hit_busies_r_reg[1]_0 ;
  output \order_q_r_reg[0] ;
  output pass_open_bank_r_lcl_reg;
  output pass_open_bank_r_lcl_reg_0;
  output pass_open_bank_r_lcl_reg_1;
  output pass_open_bank_r_lcl_reg_2;
  output auto_pre_r_lcl_reg;
  output q_has_rd_r_reg;
  output head_r_lcl_reg_2;
  output periodic_rd_insert;
  output \maintenance_request.upd_last_master_r_reg ;
  output head_r_lcl_reg_3;
  output [0:0]E;
  input p_7_in;
  input CLK;
  input periodic_rd_ack_ns;
  input accept_ns;
  input was_wr0;
  input maint_srx_r;
  input rstdiv0_sync_r1_reg_rep__20;
  input rstdiv0_sync_r1_reg_rep__1;
  input rstdiv0_sync_r1_reg_rep__19;
  input p_90_out;
  input pre_bm_end_r_reg;
  input tail_r;
  input p_51_out;
  input pre_bm_end_r_reg_0;
  input tail_r_0;
  input p_12_out;
  input pre_bm_end_r_reg_1;
  input tail_r_1;
  input \periodic_read_request.periodic_rd_r_lcl_reg ;
  input pre_bm_end_r_reg_2;
  input p_91_out;
  input p_130_out;
  input pre_bm_end_r_reg_3;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  input p_129_out;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input clear_req;
  input app_rdy_r_reg;
  input app_en_r2;
  input p_89_out;
  input clear_req_2;
  input p_128_out;
  input \grant_r_reg[3] ;
  input p_15_out;
  input p_11_out;
  input \grant_r_reg[2] ;
  input p_50_out;
  input tail_r_3;
  input p_126_out;
  input p_87_out;
  input p_48_out;
  input p_9_out;
  input rstdiv0_sync_r1_reg_rep__21;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input maint_req_r;
  input maint_zq_r;
  input \maintenance_request.maint_sre_r_lcl_reg ;

  wire CLK;
  wire [0:0]E;
  wire accept_internal_r;
  wire accept_ns;
  wire accept_r_reg_n_0;
  wire app_en_r2;
  wire app_rdy_r_reg;
  wire auto_pre_r_lcl_reg;
  wire clear_req;
  wire clear_req_2;
  wire \compute_tail.tail_r_lcl_i_2__0_n_0 ;
  wire \compute_tail.tail_r_lcl_i_2__1_n_0 ;
  wire \compute_tail.tail_r_lcl_i_2_n_0 ;
  wire \compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \compute_tail.tail_r_lcl_reg_2 ;
  wire \compute_tail.tail_r_lcl_reg_3 ;
  wire \compute_tail.tail_r_lcl_reg_4 ;
  wire \generate_maint_cmds.insert_maint_r_lcl_i_2_n_0 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[3] ;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire hi_priority;
  wire insert_maint_ns;
  wire insert_maint_r1_lcl_reg;
  wire \maint_controller.maint_hit_busies_r[0]_i_1_n_0 ;
  wire \maint_controller.maint_hit_busies_r[1]_i_1_n_0 ;
  wire \maint_controller.maint_hit_busies_r[2]_i_1_n_0 ;
  wire \maint_controller.maint_hit_busies_r[3]_i_1_n_0 ;
  wire \maint_controller.maint_hit_busies_r_reg[0]_0 ;
  wire \maint_controller.maint_hit_busies_r_reg[1]_0 ;
  wire \maint_controller.maint_hit_busies_r_reg[2]_0 ;
  wire \maint_controller.maint_hit_busies_r_reg[3]_0 ;
  wire \maint_controller.maint_rdy_r1_i_2_n_0 ;
  wire \maint_controller.maint_rdy_r1_reg_0 ;
  wire \maint_controller.maint_wip_r_lcl_i_2_n_0 ;
  wire [3:0]maint_hit_busies_r;
  wire maint_rdy;
  wire maint_rdy_r1;
  wire maint_req_r;
  wire maint_srx_r;
  wire maint_srx_r1;
  wire maint_zq_r;
  wire \maintenance_request.maint_sre_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.upd_last_master_r_reg ;
  wire \order_q_r_reg[0] ;
  wire p_11_out;
  wire p_126_out;
  wire p_128_out;
  wire p_129_out;
  wire p_12_out;
  wire p_130_out;
  wire p_15_out;
  wire p_48_out;
  wire p_50_out;
  wire p_51_out;
  wire p_7_in;
  wire p_87_out;
  wire p_89_out;
  wire p_90_out;
  wire p_91_out;
  wire p_9_out;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_ack_ns;
  wire periodic_rd_cntr_r;
  wire periodic_rd_cntr_r_i_1_n_0;
  wire periodic_rd_insert;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_bm_end_r_reg_2;
  wire pre_bm_end_r_reg_3;
  wire q_has_priority_r_reg;
  wire q_has_rd_r_reg;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire req_periodic_rd_r_lcl_reg;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ;
  wire [7:0]rfc_zq_xsdll_timer_ns;
  wire [7:0]rfc_zq_xsdll_timer_r;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire tail_r;
  wire tail_r_0;
  wire tail_r_1;
  wire tail_r_3;
  wire was_priority;
  wire was_wr;
  wire was_wr0;

  FDRE accept_internal_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_7_in),
        .Q(accept_internal_r),
        .R(1'b0));
  FDRE accept_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(accept_ns),
        .Q(accept_r_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair796" *) 
  LUT4 #(
    .INIT(16'h007F)) 
    auto_pre_r_lcl_i_4
       (.I0(accept_r_reg_n_0),
        .I1(app_rdy_r_reg),
        .I2(app_en_r2),
        .I3(req_periodic_rd_r_lcl_reg),
        .O(auto_pre_r_lcl_reg));
  LUT6 #(
    .INIT(64'h3232223222222222)) 
    \compute_tail.tail_r_lcl_i_1__0 
       (.I0(\compute_tail.tail_r_lcl_i_2_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(\compute_tail.tail_r_lcl_reg_0 ),
        .I3(p_90_out),
        .I4(pre_bm_end_r_reg),
        .I5(tail_r),
        .O(\compute_tail.tail_r_lcl_reg ));
  LUT6 #(
    .INIT(64'h3131113111111111)) 
    \compute_tail.tail_r_lcl_i_1__1 
       (.I0(\compute_tail.tail_r_lcl_i_2__1_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(\compute_tail.tail_r_lcl_reg_2 ),
        .I3(p_51_out),
        .I4(pre_bm_end_r_reg_0),
        .I5(tail_r_0),
        .O(\compute_tail.tail_r_lcl_reg_1 ));
  LUT6 #(
    .INIT(64'h3131113111111111)) 
    \compute_tail.tail_r_lcl_i_1__2 
       (.I0(\compute_tail.tail_r_lcl_i_2__0_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(\compute_tail.tail_r_lcl_reg_4 ),
        .I3(p_12_out),
        .I4(pre_bm_end_r_reg_1),
        .I5(tail_r_1),
        .O(\compute_tail.tail_r_lcl_reg_3 ));
  LUT5 #(
    .INIT(32'hAAAAEAAA)) 
    \compute_tail.tail_r_lcl_i_2 
       (.I0(\maint_controller.maint_hit_busies_r_reg[1]_0 ),
        .I1(p_91_out),
        .I2(pre_bm_end_r_reg_2),
        .I3(pre_bm_end_r_reg_3),
        .I4(p_130_out),
        .O(\compute_tail.tail_r_lcl_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h55555455)) 
    \compute_tail.tail_r_lcl_i_2__0 
       (.I0(\maint_controller.maint_hit_busies_r_reg[3]_0 ),
        .I1(pre_bm_end_r_reg_3),
        .I2(p_130_out),
        .I3(pre_bm_end_r_reg_2),
        .I4(p_91_out),
        .O(\compute_tail.tail_r_lcl_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h55545555)) 
    \compute_tail.tail_r_lcl_i_2__1 
       (.I0(\maint_controller.maint_hit_busies_r_reg[2]_0 ),
        .I1(pre_bm_end_r_reg_2),
        .I2(p_91_out),
        .I3(p_130_out),
        .I4(pre_bm_end_r_reg_3),
        .O(\compute_tail.tail_r_lcl_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h4444444444444F44)) 
    \generate_maint_cmds.insert_maint_r_lcl_i_1 
       (.I0(maint_srx_r1),
        .I1(maint_srx_r),
        .I2(\maint_controller.maint_rdy_r1_i_2_n_0 ),
        .I3(\generate_maint_cmds.insert_maint_r_lcl_i_2_n_0 ),
        .I4(maint_rdy_r1),
        .I5(\maint_controller.maint_hit_busies_r[3]_i_1_n_0 ),
        .O(insert_maint_ns));
  LUT3 #(
    .INIT(8'h8C)) 
    \generate_maint_cmds.insert_maint_r_lcl_i_2 
       (.I0(\grant_r_reg[2] ),
        .I1(\maintenance_request.upd_last_master_r_reg ),
        .I2(maint_hit_busies_r[2]),
        .O(\generate_maint_cmds.insert_maint_r_lcl_i_2_n_0 ));
  FDRE \generate_maint_cmds.insert_maint_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(insert_maint_ns),
        .Q(insert_maint_r1_lcl_reg),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80010116)) 
    head_r_lcl_i_2
       (.I0(q_has_priority_r_reg),
        .I1(p_90_out),
        .I2(p_51_out),
        .I3(p_12_out),
        .I4(p_129_out),
        .O(head_r_lcl_reg_3));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT4 #(
    .INIT(16'h110F)) 
    head_r_lcl_i_3__1
       (.I0(\maint_controller.maint_hit_busies_r_reg[3]_0 ),
        .I1(q_has_priority_r_reg),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .I3(p_12_out),
        .O(head_r_lcl_reg));
  LUT6 #(
    .INIT(64'h00000000EAAA0000)) 
    head_r_lcl_i_4
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(accept_r_reg_n_0),
        .I2(app_rdy_r_reg),
        .I3(app_en_r2),
        .I4(p_90_out),
        .I5(\maint_controller.maint_hit_busies_r_reg[1]_0 ),
        .O(head_r_lcl_reg_2));
  LUT4 #(
    .INIT(16'h110F)) 
    head_r_lcl_i_4__0
       (.I0(\maint_controller.maint_hit_busies_r_reg[2]_0 ),
        .I1(q_has_priority_r_reg),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .I3(p_51_out),
        .O(head_r_lcl_reg_0));
  LUT4 #(
    .INIT(16'h110F)) 
    head_r_lcl_i_4__1
       (.I0(\maint_controller.maint_hit_busies_r_reg[0]_0 ),
        .I1(q_has_priority_r_reg),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),
        .I3(p_129_out),
        .O(head_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'h0000AAEF)) 
    \maint_controller.maint_hit_busies_r[0]_i_1 
       (.I0(maint_hit_busies_r[0]),
        .I1(\maint_controller.maint_hit_busies_r_reg[0]_0 ),
        .I2(p_129_out),
        .I3(\maintenance_request.maint_zq_r_lcl_reg ),
        .I4(clear_req_2),
        .O(\maint_controller.maint_hit_busies_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEA00000000000000)) 
    \maint_controller.maint_hit_busies_r[0]_i_2 
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_rdy_r_reg),
        .I2(app_en_r2),
        .I3(accept_internal_r),
        .I4(p_129_out),
        .I5(p_128_out),
        .O(\maint_controller.maint_hit_busies_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h0000AAEF)) 
    \maint_controller.maint_hit_busies_r[1]_i_1 
       (.I0(maint_hit_busies_r[1]),
        .I1(\maint_controller.maint_hit_busies_r_reg[1]_0 ),
        .I2(p_90_out),
        .I3(\maintenance_request.maint_zq_r_lcl_reg ),
        .I4(clear_req),
        .O(\maint_controller.maint_hit_busies_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEA00000000000000)) 
    \maint_controller.maint_hit_busies_r[1]_i_2 
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_rdy_r_reg),
        .I2(app_en_r2),
        .I3(accept_internal_r),
        .I4(p_90_out),
        .I5(p_89_out),
        .O(\maint_controller.maint_hit_busies_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'h0000AAEF)) 
    \maint_controller.maint_hit_busies_r[2]_i_1 
       (.I0(maint_hit_busies_r[2]),
        .I1(\maint_controller.maint_hit_busies_r_reg[2]_0 ),
        .I2(p_51_out),
        .I3(\maintenance_request.maint_zq_r_lcl_reg ),
        .I4(\grant_r_reg[2] ),
        .O(\maint_controller.maint_hit_busies_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEA00000000000000)) 
    \maint_controller.maint_hit_busies_r[2]_i_2 
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_rdy_r_reg),
        .I2(app_en_r2),
        .I3(accept_internal_r),
        .I4(p_51_out),
        .I5(p_50_out),
        .O(\maint_controller.maint_hit_busies_r_reg[2]_0 ));
  LUT5 #(
    .INIT(32'h0000AAEF)) 
    \maint_controller.maint_hit_busies_r[3]_i_1 
       (.I0(maint_hit_busies_r[3]),
        .I1(\maint_controller.maint_hit_busies_r_reg[3]_0 ),
        .I2(p_12_out),
        .I3(\maintenance_request.maint_zq_r_lcl_reg ),
        .I4(\grant_r_reg[3] ),
        .O(\maint_controller.maint_hit_busies_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEA00000000000000)) 
    \maint_controller.maint_hit_busies_r[3]_i_2 
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_rdy_r_reg),
        .I2(app_en_r2),
        .I3(accept_internal_r),
        .I4(p_12_out),
        .I5(p_11_out),
        .O(\maint_controller.maint_hit_busies_r_reg[3]_0 ));
  FDRE \maint_controller.maint_hit_busies_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r[0]_i_1_n_0 ),
        .Q(maint_hit_busies_r[0]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r[1]_i_1_n_0 ),
        .Q(maint_hit_busies_r[1]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r[2]_i_1_n_0 ),
        .Q(maint_hit_busies_r[2]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r[3]_i_1_n_0 ),
        .Q(maint_hit_busies_r[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair799" *) 
  LUT5 #(
    .INIT(32'h00000054)) 
    \maint_controller.maint_rdy_r1_i_1 
       (.I0(\maint_controller.maint_hit_busies_r[2]_i_1_n_0 ),
        .I1(\maint_controller.maint_rdy_r1_reg_0 ),
        .I2(maint_req_r),
        .I3(\maint_controller.maint_rdy_r1_i_2_n_0 ),
        .I4(\maint_controller.maint_hit_busies_r[3]_i_1_n_0 ),
        .O(maint_rdy));
  LUT6 #(
    .INIT(64'hFFFFFFFF55551101)) 
    \maint_controller.maint_rdy_r1_i_2 
       (.I0(clear_req),
        .I1(\maintenance_request.maint_zq_r_lcl_reg ),
        .I2(p_90_out),
        .I3(\maint_controller.maint_hit_busies_r_reg[1]_0 ),
        .I4(maint_hit_busies_r[1]),
        .I5(\maint_controller.maint_hit_busies_r[0]_i_1_n_0 ),
        .O(\maint_controller.maint_rdy_r1_i_2_n_0 ));
  FDRE \maint_controller.maint_rdy_r1_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(maint_rdy),
        .Q(maint_rdy_r1),
        .R(1'b0));
  FDRE \maint_controller.maint_srx_r1_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(maint_srx_r),
        .Q(maint_srx_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT4 #(
    .INIT(16'hF7FF)) 
    \maint_controller.maint_wip_r_lcl_i_2 
       (.I0(rfc_zq_xsdll_timer_r[0]),
        .I1(rfc_zq_xsdll_timer_r[1]),
        .I2(rfc_zq_xsdll_timer_r[2]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ),
        .O(\maint_controller.maint_wip_r_lcl_i_2_n_0 ));
  FDRE \maint_controller.maint_wip_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_controller.maint_wip_r_lcl_i_2_n_0 ),
        .Q(\maint_controller.maint_rdy_r1_reg_0 ),
        .R(rstdiv0_sync_r1_reg_rep__20));
  (* SOFT_HLUTNM = "soft_lutpair799" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \maintenance_request.upd_last_master_r_i_3 
       (.I0(\maint_controller.maint_rdy_r1_reg_0 ),
        .I1(maint_req_r),
        .O(\maintenance_request.upd_last_master_r_reg ));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \order_q_r[1]_i_2__2 
       (.I0(\maint_controller.maint_hit_busies_r_reg[3]_0 ),
        .I1(p_15_out),
        .O(\order_q_r_reg[0] ));
  LUT6 #(
    .INIT(64'h1555FFFFFFFFFFFF)) 
    pass_open_bank_r_lcl_i_2
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_en_r2),
        .I2(app_rdy_r_reg),
        .I3(accept_r_reg_n_0),
        .I4(tail_r_3),
        .I5(p_126_out),
        .O(pass_open_bank_r_lcl_reg));
  LUT6 #(
    .INIT(64'h1555FFFFFFFFFFFF)) 
    pass_open_bank_r_lcl_i_2__0
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_en_r2),
        .I2(app_rdy_r_reg),
        .I3(accept_r_reg_n_0),
        .I4(tail_r),
        .I5(p_87_out),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h1555FFFFFFFFFFFF)) 
    pass_open_bank_r_lcl_i_2__1
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_en_r2),
        .I2(app_rdy_r_reg),
        .I3(accept_r_reg_n_0),
        .I4(tail_r_0),
        .I5(p_48_out),
        .O(pass_open_bank_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h1555FFFFFFFFFFFF)) 
    pass_open_bank_r_lcl_i_2__2
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(app_en_r2),
        .I2(app_rdy_r_reg),
        .I3(accept_r_reg_n_0),
        .I4(tail_r_1),
        .I5(p_9_out),
        .O(pass_open_bank_r_lcl_reg_2));
  FDRE periodic_rd_ack_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(periodic_rd_ack_ns),
        .Q(req_periodic_rd_r_lcl_reg),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT3 #(
    .INIT(8'h78)) 
    periodic_rd_cntr_r_i_1
       (.I0(\periodic_read_request.periodic_rd_r_lcl_reg ),
        .I1(req_periodic_rd_r_lcl_reg),
        .I2(periodic_rd_cntr_r),
        .O(periodic_rd_cntr_r_i_1_n_0));
  FDRE periodic_rd_cntr_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(periodic_rd_cntr_r_i_1_n_0),
        .Q(periodic_rd_cntr_r),
        .R(rstdiv0_sync_r1_reg_rep__1));
  (* SOFT_HLUTNM = "soft_lutpair798" *) 
  LUT4 #(
    .INIT(16'h1555)) 
    \q_entry_r[0]_i_2__2 
       (.I0(req_periodic_rd_r_lcl_reg),
        .I1(accept_r_reg_n_0),
        .I2(app_rdy_r_reg),
        .I3(app_en_r2),
        .O(q_has_priority_r_reg));
  LUT5 #(
    .INIT(32'h007FFFFF)) 
    q_has_rd_r_i_2__0
       (.I0(app_en_r2),
        .I1(app_rdy_r_reg),
        .I2(accept_r_reg_n_0),
        .I3(req_periodic_rd_r_lcl_reg),
        .I4(p_9_out),
        .O(\compute_tail.tail_r_lcl_reg_4 ));
  LUT5 #(
    .INIT(32'h007FFFFF)) 
    q_has_rd_r_i_2__1
       (.I0(app_en_r2),
        .I1(app_rdy_r_reg),
        .I2(accept_r_reg_n_0),
        .I3(req_periodic_rd_r_lcl_reg),
        .I4(p_48_out),
        .O(\compute_tail.tail_r_lcl_reg_2 ));
  (* SOFT_HLUTNM = "soft_lutpair798" *) 
  LUT5 #(
    .INIT(32'h007FFFFF)) 
    q_has_rd_r_i_2__2
       (.I0(app_en_r2),
        .I1(app_rdy_r_reg),
        .I2(accept_r_reg_n_0),
        .I3(req_periodic_rd_r_lcl_reg),
        .I4(p_87_out),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair796" *) 
  LUT5 #(
    .INIT(32'h007FFFFF)) 
    q_has_rd_r_i_3
       (.I0(app_en_r2),
        .I1(app_rdy_r_reg),
        .I2(accept_r_reg_n_0),
        .I3(req_periodic_rd_r_lcl_reg),
        .I4(p_126_out),
        .O(q_has_rd_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    req_periodic_rd_r_lcl_i_1
       (.I0(\periodic_read_request.periodic_rd_r_lcl_reg ),
        .I1(periodic_rd_cntr_r),
        .I2(req_periodic_rd_r_lcl_reg),
        .O(periodic_rd_insert));
  LUT2 #(
    .INIT(4'h2)) 
    req_priority_r_i_1
       (.I0(was_priority),
        .I1(app_rdy_r_reg),
        .O(hi_priority));
  LUT3 #(
    .INIT(8'h01)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(insert_maint_r1_lcl_reg),
        .I2(rfc_zq_xsdll_timer_r[0]),
        .O(rfc_zq_xsdll_timer_ns[0]));
  LUT6 #(
    .INIT(64'h0000AAAAF909AAAA)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1 
       (.I0(rfc_zq_xsdll_timer_r[1]),
        .I1(rfc_zq_xsdll_timer_r[0]),
        .I2(insert_maint_r1_lcl_reg),
        .I3(\maintenance_request.maint_sre_r_lcl_reg ),
        .I4(E),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair797" *) 
  LUT5 #(
    .INIT(32'h000000E1)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1 
       (.I0(rfc_zq_xsdll_timer_r[0]),
        .I1(rfc_zq_xsdll_timer_r[1]),
        .I2(rfc_zq_xsdll_timer_r[2]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .I4(insert_maint_r1_lcl_reg),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAAAF606AAAA)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1 
       (.I0(rfc_zq_xsdll_timer_r[3]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ),
        .I2(insert_maint_r1_lcl_reg),
        .I3(\maintenance_request.maint_sre_r_lcl_reg ),
        .I4(E),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair797" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2 
       (.I0(rfc_zq_xsdll_timer_r[1]),
        .I1(rfc_zq_xsdll_timer_r[0]),
        .I2(rfc_zq_xsdll_timer_r[2]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000F909)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_1 
       (.I0(rfc_zq_xsdll_timer_r[4]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ),
        .I2(insert_maint_r1_lcl_reg),
        .I3(maint_zq_r),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .O(rfc_zq_xsdll_timer_ns[4]));
  LUT5 #(
    .INIT(32'h11100001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(insert_maint_r1_lcl_reg),
        .I2(rfc_zq_xsdll_timer_r[4]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ),
        .I4(rfc_zq_xsdll_timer_r[5]),
        .O(rfc_zq_xsdll_timer_ns[5]));
  LUT6 #(
    .INIT(64'h000000000000FE01)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1 
       (.I0(rfc_zq_xsdll_timer_r[4]),
        .I1(rfc_zq_xsdll_timer_r[5]),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ),
        .I3(rfc_zq_xsdll_timer_r[6]),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .I5(insert_maint_r1_lcl_reg),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2 
       (.I0(rfc_zq_xsdll_timer_r[3]),
        .I1(rfc_zq_xsdll_timer_r[2]),
        .I2(rfc_zq_xsdll_timer_r[0]),
        .I3(rfc_zq_xsdll_timer_r[1]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ),
        .I1(insert_maint_r1_lcl_reg),
        .I2(rstdiv0_sync_r1_reg_rep__21),
        .I3(rfc_zq_xsdll_timer_r[1]),
        .I4(rfc_zq_xsdll_timer_r[0]),
        .I5(rfc_zq_xsdll_timer_r[2]),
        .O(E));
  LUT6 #(
    .INIT(64'h02020002FFFFFFFF)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2 
       (.I0(rfc_zq_xsdll_timer_r[7]),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(insert_maint_r1_lcl_reg),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ),
        .I4(rfc_zq_xsdll_timer_r[6]),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(rfc_zq_xsdll_timer_ns[7]));
  LUT5 #(
    .INIT(32'h00000001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3 
       (.I0(rfc_zq_xsdll_timer_r[4]),
        .I1(rfc_zq_xsdll_timer_r[5]),
        .I2(rfc_zq_xsdll_timer_r[7]),
        .I3(rfc_zq_xsdll_timer_r[3]),
        .I4(rfc_zq_xsdll_timer_r[6]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4 
       (.I0(rfc_zq_xsdll_timer_r[4]),
        .I1(rfc_zq_xsdll_timer_r[5]),
        .I2(rfc_zq_xsdll_timer_r[1]),
        .I3(rfc_zq_xsdll_timer_r[0]),
        .I4(rfc_zq_xsdll_timer_r[2]),
        .I5(rfc_zq_xsdll_timer_r[3]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(rfc_zq_xsdll_timer_ns[0]),
        .Q(rfc_zq_xsdll_timer_r[0]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0 ),
        .Q(rfc_zq_xsdll_timer_r[1]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0 ),
        .Q(rfc_zq_xsdll_timer_r[2]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0 ),
        .Q(rfc_zq_xsdll_timer_r[3]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(rfc_zq_xsdll_timer_ns[4]),
        .Q(rfc_zq_xsdll_timer_r[4]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(rfc_zq_xsdll_timer_ns[5]),
        .Q(rfc_zq_xsdll_timer_r[5]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1_n_0 ),
        .Q(rfc_zq_xsdll_timer_r[6]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(rfc_zq_xsdll_timer_ns[7]),
        .Q(rfc_zq_xsdll_timer_r[7]),
        .R(1'b0));
  FDRE was_priority_reg
       (.C(CLK),
        .CE(1'b1),
        .D(hi_priority),
        .Q(was_priority),
        .R(1'b0));
  FDRE was_wr_reg
       (.C(CLK),
        .CE(1'b1),
        .D(was_wr0),
        .Q(was_wr),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_compare" *) 
module mig_7series_0_mig_7series_v2_3_bank_compare
   (p_32_out,
    \rd_this_rank_r_reg[0] ,
    bm_end_r1_reg,
    req_priority_r,
    q_has_priority_r_reg,
    row_hit_r,
    ras_timer_zero_r_reg,
    head_r_lcl_reg,
    p_13_out,
    pass_open_bank_r_lcl_reg,
    wr_this_rank_r0,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    E,
    periodic_rd_insert,
    CLK,
    hi_priority,
    p_28_out,
    \app_addr_r1_reg[22] ,
    Q,
    pass_open_bank_r,
    pre_bm_end_r,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    idle_r_lcl_reg,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    wait_for_maint_r_lcl_reg,
    row,
    idle_r_lcl_reg_0,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] );
  output p_32_out;
  output \rd_this_rank_r_reg[0] ;
  output bm_end_r1_reg;
  output req_priority_r;
  output q_has_priority_r_reg;
  output row_hit_r;
  output ras_timer_zero_r_reg;
  output head_r_lcl_reg;
  output p_13_out;
  output pass_open_bank_r_lcl_reg;
  output wr_this_rank_r0;
  output [13:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input hi_priority;
  input p_28_out;
  input [0:0]\app_addr_r1_reg[22] ;
  input [0:0]Q;
  input pass_open_bank_r;
  input pre_bm_end_r;
  input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input idle_r_lcl_reg;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input wait_for_maint_r_lcl_reg;
  input [13:0]row;
  input [0:0]idle_r_lcl_reg_0;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;

  wire CLK;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_rdy_r_reg;
  wire bm_end_r1_reg;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire head_r_lcl_reg;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire [0:0]idle_r_lcl_reg_0;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire p_13_out;
  wire p_28_out;
  wire p_32_out;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_insert;
  wire pre_bm_end_r;
  wire q_has_priority_r_reg;
  wire ras_timer_zero_r_reg;
  wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rd_this_rank_r_reg[0] ;
  wire rd_wr_ns;
  wire [1:0]req_cmd_r;
  wire \req_cmd_r[0]_i_1__1_n_0 ;
  wire \req_cmd_r[1]_i_1__1_n_0 ;
  wire req_priority_r;
  wire req_wr_r_lcl0;
  wire [13:0]row;
  wire row_hit_ns;
  wire row_hit_r;
  wire row_hit_r_i_4__2_n_0;
  wire row_hit_r_i_5__2_n_0;
  wire row_hit_r_i_6__2_n_0;
  wire row_hit_r_i_7__2_n_0;
  wire row_hit_r_reg_i_2__2_n_0;
  wire row_hit_r_reg_i_2__2_n_1;
  wire row_hit_r_reg_i_2__2_n_2;
  wire row_hit_r_reg_i_2__2_n_3;
  wire wait_for_maint_r_lcl_reg;
  wire wr_this_rank_r0;
  wire [3:1]NLW_row_hit_r_reg_i_1__2_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_1__2_O_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_2__2_O_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair788" *) 
  LUT5 #(
    .INIT(32'hFFFF7000)) 
    bm_end_r1_i_1__1
       (.I0(bm_end_r1_reg),
        .I1(\rd_this_rank_r_reg[0] ),
        .I2(pass_open_bank_r),
        .I3(Q),
        .I4(pre_bm_end_r),
        .O(p_13_out));
  LUT5 #(
    .INIT(32'hAAAA888A)) 
    pass_open_bank_r_lcl_i_3
       (.I0(row_hit_r),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .I2(maint_req_r),
        .I3(\maint_controller.maint_wip_r_lcl_reg ),
        .I4(wait_for_maint_r_lcl_reg),
        .O(pass_open_bank_r_lcl_reg));
  LUT6 #(
    .INIT(64'h00008FFFFFFFFFFF)) 
    \q_entry_r[0]_i_5 
       (.I0(bm_end_r1_reg),
        .I1(\rd_this_rank_r_reg[0] ),
        .I2(pass_open_bank_r),
        .I3(Q),
        .I4(pre_bm_end_r),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .O(head_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair788" *) 
  LUT2 #(
    .INIT(4'hB)) 
    ras_timer_zero_r_i_3__0
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(Q),
        .O(ras_timer_zero_r_reg));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_28_out),
        .Q(q_has_priority_r_reg),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair789" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__1
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(Q),
        .I2(idle_r_lcl_reg),
        .I3(\app_cmd_r2_reg[0] ),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(\rd_this_rank_r_reg[0] ),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [0]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8] [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [1]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8] [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [2]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8] [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair789" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_cmd_r[0]_i_1__1 
       (.I0(req_cmd_r[0]),
        .I1(idle_r_lcl_reg),
        .I2(\app_cmd_r2_reg[0] ),
        .O(\req_cmd_r[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \req_cmd_r[1]_i_1__1 
       (.I0(req_cmd_r[1]),
        .I1(idle_r_lcl_reg),
        .I2(app_cmd_r2),
        .I3(app_rdy_r_reg),
        .I4(\app_cmd_r1_reg[1] ),
        .I5(periodic_rd_insert),
        .O(\req_cmd_r[1]_i_1__1_n_0 ));
  FDRE \req_cmd_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[0]_i_1__1_n_0 ),
        .Q(req_cmd_r[0]),
        .R(1'b0));
  FDRE \req_cmd_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[1]_i_1__1_n_0 ),
        .Q(req_cmd_r[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [0]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [1]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [2]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [3]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [4]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [5]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [6]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [7]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [8]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [9]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [3]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[4] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [4]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(p_32_out),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hCCAFFFAF)) 
    req_wr_r_lcl_i_1__1
       (.I0(\app_cmd_r2_reg[1] ),
        .I1(req_cmd_r[1]),
        .I2(\app_cmd_r2_reg[0] ),
        .I3(idle_r_lcl_reg),
        .I4(req_cmd_r[0]),
        .O(req_wr_r_lcl0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(bm_end_r1_reg),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_4__2
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [11]),
        .I1(row[11]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [10]),
        .I3(row[10]),
        .I4(row[9]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [9]),
        .O(row_hit_r_i_4__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_5__2
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [8]),
        .I1(row[8]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [7]),
        .I3(row[7]),
        .I4(row[6]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [6]),
        .O(row_hit_r_i_5__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_6__2
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [5]),
        .I1(row[5]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [3]),
        .I3(row[3]),
        .I4(row[4]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [4]),
        .O(row_hit_r_i_6__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_7__2
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [2]),
        .I1(row[2]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [1]),
        .I3(row[1]),
        .I4(row[0]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [0]),
        .O(row_hit_r_i_7__2_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns),
        .Q(row_hit_r),
        .R(1'b0));
  CARRY4 row_hit_r_reg_i_1__2
       (.CI(row_hit_r_reg_i_2__2_n_0),
        .CO({NLW_row_hit_r_reg_i_1__2_CO_UNCONNECTED[3:1],row_hit_ns}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_1__2_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,\app_addr_r1_reg[22] }));
  CARRY4 row_hit_r_reg_i_2__2
       (.CI(1'b0),
        .CO({row_hit_r_reg_i_2__2_n_0,row_hit_r_reg_i_2__2_n_1,row_hit_r_reg_i_2__2_n_2,row_hit_r_reg_i_2__2_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_2__2_O_UNCONNECTED[3:0]),
        .S({row_hit_r_i_4__2_n_0,row_hit_r_i_5__2_n_0,row_hit_r_i_6__2_n_0,row_hit_r_i_7__2_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__2 
       (.I0(\rd_this_rank_r_reg[0] ),
        .O(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_compare" *) 
module mig_7series_0_mig_7series_v2_3_bank_compare_0
   (p_71_out,
    \rd_this_rank_r_reg[0] ,
    p_54_out,
    req_priority_r,
    p_48_out,
    row_hit_r,
    \grant_r_reg[0] ,
    demand_priority_r_reg,
    req_bank_rdy_r_reg,
    \order_q_r_reg[0] ,
    \order_q_r_reg[1] ,
    req_bank_rdy_ns,
    ras_timer_zero_r_reg,
    p_52_out,
    set_order_q,
    pass_open_bank_r_lcl_reg,
    wr_this_rank_r0,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    E,
    periodic_rd_insert,
    CLK,
    hi_priority,
    p_67_out,
    \grant_r_reg[1] ,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    demand_priority_r_reg_0,
    col_wait_r_reg,
    order_q_r,
    \app_addr_r1_reg[22] ,
    p_25_out,
    p_64_out,
    p_103_out,
    p_142_out,
    col_wait_r,
    \grant_r_reg[3] ,
    p_14_out,
    p_15_out,
    rd_wr_r_lcl_reg_0,
    pass_open_bank_r,
    pre_bm_end_r,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    idle_r_lcl_reg,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    periodic_rd_ack_r_lcl_reg,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    wait_for_maint_r_lcl_reg,
    row,
    \req_row_r_lcl_reg[10]_0 ,
    act_wait_r_lcl_reg,
    \grant_r_reg[3]_0 ,
    act_wait_r_lcl_reg_0,
    idle_r_lcl_reg_0,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] );
  output p_71_out;
  output \rd_this_rank_r_reg[0] ;
  output p_54_out;
  output req_priority_r;
  output p_48_out;
  output row_hit_r;
  output \grant_r_reg[0] ;
  output demand_priority_r_reg;
  output req_bank_rdy_r_reg;
  output \order_q_r_reg[0] ;
  output \order_q_r_reg[1] ;
  output req_bank_rdy_ns;
  output ras_timer_zero_r_reg;
  output p_52_out;
  output set_order_q;
  output pass_open_bank_r_lcl_reg;
  output wr_this_rank_r0;
  output [13:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input hi_priority;
  input p_67_out;
  input \grant_r_reg[1] ;
  input \wtr_timer.wtr_cnt_r_reg[1] ;
  input demand_priority_r_reg_0;
  input col_wait_r_reg;
  input [1:0]order_q_r;
  input [0:0]\app_addr_r1_reg[22] ;
  input p_25_out;
  input p_64_out;
  input p_103_out;
  input p_142_out;
  input col_wait_r;
  input [1:0]\grant_r_reg[3] ;
  input p_14_out;
  input p_15_out;
  input rd_wr_r_lcl_reg_0;
  input pass_open_bank_r;
  input pre_bm_end_r;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input idle_r_lcl_reg;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input periodic_rd_ack_r_lcl_reg;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input wait_for_maint_r_lcl_reg;
  input [13:0]row;
  input \req_row_r_lcl_reg[10]_0 ;
  input act_wait_r_lcl_reg;
  input [1:0]\grant_r_reg[3]_0 ;
  input act_wait_r_lcl_reg_0;
  input [0:0]idle_r_lcl_reg_0;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;

  wire CLK;
  wire [0:0]E;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_rdy_r_reg;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire col_wait_r;
  wire col_wait_r_reg;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[1] ;
  wire [1:0]\grant_r_reg[3] ;
  wire [1:0]\grant_r_reg[3]_0 ;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire [0:0]idle_r_lcl_reg_0;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire [1:0]order_q_r;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[1] ;
  wire p_103_out;
  wire p_142_out;
  wire p_14_out;
  wire p_15_out;
  wire p_25_out;
  wire p_48_out;
  wire p_52_out;
  wire p_54_out;
  wire p_64_out;
  wire p_67_out;
  wire p_71_out;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_insert;
  wire pre_bm_end_r;
  wire ras_timer_zero_r_reg;
  wire \rd_this_rank_r_reg[0] ;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire [1:0]req_cmd_r;
  wire \req_cmd_r[0]_i_1__2_n_0 ;
  wire \req_cmd_r[1]_i_1__2_n_0 ;
  wire req_priority_r;
  wire \req_row_r_lcl_reg[10]_0 ;
  wire req_wr_r_lcl0;
  wire [13:0]row;
  wire row_hit_ns;
  wire row_hit_r;
  wire row_hit_r_i_4__1_n_0;
  wire row_hit_r_i_5__1_n_0;
  wire row_hit_r_i_6__1_n_0;
  wire row_hit_r_i_7__1_n_0;
  wire row_hit_r_reg_i_2__1_n_0;
  wire row_hit_r_reg_i_2__1_n_1;
  wire row_hit_r_reg_i_2__1_n_2;
  wire row_hit_r_reg_i_2__1_n_3;
  wire set_order_q;
  wire wait_for_maint_r_lcl_reg;
  wire wr_this_rank_r0;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;
  wire [3:1]NLW_row_hit_r_reg_i_1__1_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_1__1_O_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_2__1_O_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair779" *) 
  LUT5 #(
    .INIT(32'hFFFF7000)) 
    bm_end_r1_i_1__2
       (.I0(p_54_out),
        .I1(\rd_this_rank_r_reg[0] ),
        .I2(pass_open_bank_r),
        .I3(\grant_r_reg[3] [0]),
        .I4(pre_bm_end_r),
        .O(p_52_out));
  LUT6 #(
    .INIT(64'hCCFCCCDDCCCCCCDD)) 
    \cmd_pipe_plus.mc_address[38]_i_1 
       (.I0(\req_row_r_lcl_reg[10]_0 ),
        .I1(act_wait_r_lcl_reg),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [10]),
        .I3(\grant_r_reg[3]_0 [1]),
        .I4(\grant_r_reg[3]_0 [0]),
        .I5(act_wait_r_lcl_reg_0),
        .O(\cmd_pipe_plus.mc_address_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair778" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    demand_priority_r_i_2__1
       (.I0(req_bank_rdy_r_reg),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(\rd_this_rank_r_reg[0] ),
        .O(demand_priority_r_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFE2)) 
    \grant_r[3]_i_6__0 
       (.I0(\grant_r_reg[1] ),
        .I1(\rd_this_rank_r_reg[0] ),
        .I2(\wtr_timer.wtr_cnt_r_reg[1] ),
        .I3(demand_priority_r_reg_0),
        .I4(col_wait_r_reg),
        .I5(demand_priority_r_reg),
        .O(\grant_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair777" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    \order_q_r[0]_i_2 
       (.I0(req_bank_rdy_r_reg),
        .I1(p_25_out),
        .I2(p_64_out),
        .I3(p_103_out),
        .I4(p_142_out),
        .O(\order_q_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair777" *) 
  LUT5 #(
    .INIT(32'h7EE8E881)) 
    \order_q_r[1]_i_2 
       (.I0(req_bank_rdy_r_reg),
        .I1(p_142_out),
        .I2(p_103_out),
        .I3(p_64_out),
        .I4(p_25_out),
        .O(\order_q_r_reg[1] ));
  LUT2 #(
    .INIT(4'h8)) 
    \order_q_r[1]_i_2__1 
       (.I0(p_54_out),
        .I1(periodic_rd_ack_r_lcl_reg),
        .O(set_order_q));
  LUT5 #(
    .INIT(32'hAAAA888A)) 
    pass_open_bank_r_lcl_i_3__0
       (.I0(row_hit_r),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .I2(maint_req_r),
        .I3(\maint_controller.maint_wip_r_lcl_reg ),
        .I4(wait_for_maint_r_lcl_reg),
        .O(pass_open_bank_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair779" *) 
  LUT2 #(
    .INIT(4'hB)) 
    ras_timer_zero_r_i_3
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(\grant_r_reg[3] [0]),
        .O(ras_timer_zero_r_reg));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_67_out),
        .Q(p_48_out),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair780" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__2
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(\grant_r_reg[3] [0]),
        .I2(idle_r_lcl_reg),
        .I3(\app_cmd_r2_reg[0] ),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(\rd_this_rank_r_reg[0] ),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [0]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8] [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [1]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8] [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [2]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8] [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair778" *) 
  LUT5 #(
    .INIT(32'h888A8A8A)) 
    req_bank_rdy_r_i_1__0
       (.I0(col_wait_r),
        .I1(\rd_this_rank_r_reg[0] ),
        .I2(order_q_r[1]),
        .I3(order_q_r[0]),
        .I4(req_bank_rdy_r_reg),
        .O(req_bank_rdy_ns));
  LUT6 #(
    .INIT(64'h00000000DD0DDDDD)) 
    req_bank_rdy_r_i_2
       (.I0(p_54_out),
        .I1(ras_timer_zero_r_reg),
        .I2(\grant_r_reg[3] [1]),
        .I3(p_14_out),
        .I4(p_15_out),
        .I5(rd_wr_r_lcl_reg_0),
        .O(req_bank_rdy_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair780" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_cmd_r[0]_i_1__2 
       (.I0(req_cmd_r[0]),
        .I1(idle_r_lcl_reg),
        .I2(\app_cmd_r2_reg[0] ),
        .O(\req_cmd_r[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \req_cmd_r[1]_i_1__2 
       (.I0(req_cmd_r[1]),
        .I1(idle_r_lcl_reg),
        .I2(app_cmd_r2),
        .I3(app_rdy_r_reg),
        .I4(\app_cmd_r1_reg[1] ),
        .I5(periodic_rd_insert),
        .O(\req_cmd_r[1]_i_1__2_n_0 ));
  FDRE \req_cmd_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[0]_i_1__2_n_0 ),
        .Q(req_cmd_r[0]),
        .R(1'b0));
  FDRE \req_cmd_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[1]_i_1__2_n_0 ),
        .Q(req_cmd_r[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [0]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [1]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [2]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [3]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [4]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [5]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [6]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [7]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [8]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [9]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [3]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[4] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [4]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(p_71_out),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\cmd_pipe_plus.mc_address_reg[41] [9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hCCAFFFAF)) 
    req_wr_r_lcl_i_1__2
       (.I0(\app_cmd_r2_reg[1] ),
        .I1(req_cmd_r[1]),
        .I2(\app_cmd_r2_reg[0] ),
        .I3(idle_r_lcl_reg),
        .I4(req_cmd_r[0]),
        .O(req_wr_r_lcl0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(p_54_out),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_4__1
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [11]),
        .I1(row[11]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [9]),
        .I3(row[9]),
        .I4(row[10]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [10]),
        .O(row_hit_r_i_4__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_5__1
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [8]),
        .I1(row[8]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [6]),
        .I3(row[6]),
        .I4(row[7]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [7]),
        .O(row_hit_r_i_5__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_6__1
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [5]),
        .I1(row[5]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [3]),
        .I3(row[3]),
        .I4(row[4]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [4]),
        .O(row_hit_r_i_6__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_7__1
       (.I0(\cmd_pipe_plus.mc_address_reg[41] [2]),
        .I1(row[2]),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [0]),
        .I3(row[0]),
        .I4(row[1]),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [1]),
        .O(row_hit_r_i_7__1_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns),
        .Q(row_hit_r),
        .R(1'b0));
  CARRY4 row_hit_r_reg_i_1__1
       (.CI(row_hit_r_reg_i_2__1_n_0),
        .CO({NLW_row_hit_r_reg_i_1__1_CO_UNCONNECTED[3:1],row_hit_ns}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_1__1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,\app_addr_r1_reg[22] }));
  CARRY4 row_hit_r_reg_i_2__1
       (.CI(1'b0),
        .CO({row_hit_r_reg_i_2__1_n_0,row_hit_r_reg_i_2__1_n_1,row_hit_r_reg_i_2__1_n_2,row_hit_r_reg_i_2__1_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_2__1_O_UNCONNECTED[3:0]),
        .S({row_hit_r_i_4__1_n_0,row_hit_r_i_5__1_n_0,row_hit_r_i_6__1_n_0,row_hit_r_i_7__1_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__1 
       (.I0(\rd_this_rank_r_reg[0] ),
        .O(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_compare" *) 
module mig_7series_0_mig_7series_v2_3_bank_compare_1
   (p_110_out,
    \rd_this_rank_r_reg[0] ,
    p_93_out,
    req_priority_r,
    p_87_out,
    row_hit_r,
    head_r_lcl_reg,
    \q_entry_r_reg[0] ,
    set_order_q,
    req_bank_rdy_r_reg,
    ras_timer_zero_r_reg,
    pass_open_bank_r_lcl_reg,
    wr_this_rank_r0,
    \cmd_pipe_plus.mc_address_reg[13] ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    E,
    periodic_rd_insert,
    CLK,
    hi_priority,
    p_106_out,
    p_130_out,
    pass_open_bank_r,
    Q,
    pre_bm_end_r,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    \app_addr_r1_reg[22] ,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    idle_r_lcl_reg,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    periodic_rd_ack_r_lcl_reg,
    p_131_out,
    p_132_out,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    wait_for_maint_r_lcl_reg,
    row,
    act_wait_r_lcl_reg,
    \grant_r_reg[1] ,
    p_154_out,
    \req_row_r_lcl_reg[10]_0 ,
    idle_r_lcl_reg_0,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] );
  output p_110_out;
  output \rd_this_rank_r_reg[0] ;
  output p_93_out;
  output req_priority_r;
  output p_87_out;
  output row_hit_r;
  output head_r_lcl_reg;
  output \q_entry_r_reg[0] ;
  output set_order_q;
  output req_bank_rdy_r_reg;
  output ras_timer_zero_r_reg;
  output pass_open_bank_r_lcl_reg;
  output wr_this_rank_r0;
  output [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  output \cmd_pipe_plus.mc_address_reg[38] ;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input hi_priority;
  input p_106_out;
  input p_130_out;
  input pass_open_bank_r;
  input [1:0]Q;
  input pre_bm_end_r;
  input [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input [0:0]\app_addr_r1_reg[22] ;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input idle_r_lcl_reg;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input periodic_rd_ack_r_lcl_reg;
  input p_131_out;
  input p_132_out;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input wait_for_maint_r_lcl_reg;
  input [13:0]row;
  input act_wait_r_lcl_reg;
  input [1:0]\grant_r_reg[1] ;
  input p_154_out;
  input [0:0]\req_row_r_lcl_reg[10]_0 ;
  input [0:0]idle_r_lcl_reg_0;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;

  wire CLK;
  wire [0:0]E;
  wire [1:0]Q;
  wire act_wait_r_lcl_reg;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_rdy_r_reg;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire \cmd_pipe_plus.mc_address_reg[38] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire [1:0]\grant_r_reg[1] ;
  wire head_r_lcl_reg;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire [0:0]idle_r_lcl_reg_0;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire p_106_out;
  wire p_110_out;
  wire p_130_out;
  wire p_131_out;
  wire p_132_out;
  wire p_154_out;
  wire p_87_out;
  wire p_93_out;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_insert;
  wire pre_bm_end_r;
  wire \q_entry_r_reg[0] ;
  wire ras_timer_zero_r_reg;
  wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rd_this_rank_r_reg[0] ;
  wire rd_wr_ns;
  wire req_bank_rdy_r_reg;
  wire [1:0]req_cmd_r;
  wire \req_cmd_r[0]_i_1_n_0 ;
  wire \req_cmd_r[1]_i_1_n_0 ;
  wire req_priority_r;
  wire [0:0]\req_row_r_lcl_reg[10]_0 ;
  wire req_wr_r_lcl0;
  wire [13:0]row;
  wire row_hit_ns;
  wire row_hit_r;
  wire row_hit_r_i_4__0_n_0;
  wire row_hit_r_i_5__0_n_0;
  wire row_hit_r_i_6__0_n_0;
  wire row_hit_r_i_7__0_n_0;
  wire row_hit_r_reg_i_2__0_n_0;
  wire row_hit_r_reg_i_2__0_n_1;
  wire row_hit_r_reg_i_2__0_n_2;
  wire row_hit_r_reg_i_2__0_n_3;
  wire set_order_q;
  wire wait_for_maint_r_lcl_reg;
  wire wr_this_rank_r0;
  wire [3:1]NLW_row_hit_r_reg_i_1__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_1__0_O_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_2__0_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h707F7F7F7F7F7F7F)) 
    \cmd_pipe_plus.mc_address[38]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [10]),
        .I1(act_wait_r_lcl_reg),
        .I2(\grant_r_reg[1] [1]),
        .I3(\grant_r_reg[1] [0]),
        .I4(p_154_out),
        .I5(\req_row_r_lcl_reg[10]_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[38] ));
  LUT6 #(
    .INIT(64'h0000000040555555)) 
    head_r_lcl_i_3__0
       (.I0(p_130_out),
        .I1(p_93_out),
        .I2(\rd_this_rank_r_reg[0] ),
        .I3(pass_open_bank_r),
        .I4(Q[1]),
        .I5(pre_bm_end_r),
        .O(head_r_lcl_reg));
  LUT2 #(
    .INIT(4'h8)) 
    \order_q_r[1]_i_2__0 
       (.I0(p_93_out),
        .I1(periodic_rd_ack_r_lcl_reg),
        .O(set_order_q));
  LUT5 #(
    .INIT(32'hAAAA888A)) 
    pass_open_bank_r_lcl_i_3__1
       (.I0(row_hit_r),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .I2(maint_req_r),
        .I3(\maint_controller.maint_wip_r_lcl_reg ),
        .I4(wait_for_maint_r_lcl_reg),
        .O(pass_open_bank_r_lcl_reg));
  LUT6 #(
    .INIT(64'hAAAAAAAA2A000000)) 
    \q_entry_r[0]_i_5__1 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .I1(p_93_out),
        .I2(\rd_this_rank_r_reg[0] ),
        .I3(pass_open_bank_r),
        .I4(Q[1]),
        .I5(pre_bm_end_r),
        .O(\q_entry_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair769" *) 
  LUT2 #(
    .INIT(4'hB)) 
    ras_timer_zero_r_i_3__2
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(Q[1]),
        .O(ras_timer_zero_r_reg));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_106_out),
        .Q(p_87_out),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair769" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(Q[1]),
        .I2(idle_r_lcl_reg),
        .I3(\app_cmd_r2_reg[0] ),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(\rd_this_rank_r_reg[0] ),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [0]),
        .Q(\cmd_pipe_plus.mc_bank_reg[2] [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [1]),
        .Q(\cmd_pipe_plus.mc_bank_reg[2] [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [2]),
        .Q(\cmd_pipe_plus.mc_bank_reg[2] [2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h40FF404040404040)) 
    req_bank_rdy_r_i_3
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(Q[1]),
        .I2(p_93_out),
        .I3(p_131_out),
        .I4(Q[0]),
        .I5(p_132_out),
        .O(req_bank_rdy_r_reg));
  LUT3 #(
    .INIT(8'hB8)) 
    \req_cmd_r[0]_i_1 
       (.I0(req_cmd_r[0]),
        .I1(idle_r_lcl_reg),
        .I2(\app_cmd_r2_reg[0] ),
        .O(\req_cmd_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \req_cmd_r[1]_i_1 
       (.I0(req_cmd_r[1]),
        .I1(idle_r_lcl_reg),
        .I2(app_cmd_r2),
        .I3(app_rdy_r_reg),
        .I4(\app_cmd_r1_reg[1] ),
        .I5(periodic_rd_insert),
        .O(\req_cmd_r[1]_i_1_n_0 ));
  FDRE \req_cmd_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[0]_i_1_n_0 ),
        .Q(req_cmd_r[0]),
        .R(1'b0));
  FDRE \req_cmd_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[1]_i_1_n_0 ),
        .Q(req_cmd_r[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [0]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [1]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [2]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [3]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [4]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [5]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [6]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [7]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [8]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [9]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [3]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[4] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [4]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(p_110_out),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hCCAFFFAF)) 
    req_wr_r_lcl_i_1
       (.I0(\app_cmd_r2_reg[1] ),
        .I1(req_cmd_r[1]),
        .I2(\app_cmd_r2_reg[0] ),
        .I3(idle_r_lcl_reg),
        .I4(req_cmd_r[0]),
        .O(req_wr_r_lcl0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(p_93_out),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_4__0
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [11]),
        .I1(row[11]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [10]),
        .I3(row[10]),
        .I4(row[9]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [9]),
        .O(row_hit_r_i_4__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_5__0
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [8]),
        .I1(row[8]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [6]),
        .I3(row[6]),
        .I4(row[7]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [7]),
        .O(row_hit_r_i_5__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_6__0
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [5]),
        .I1(row[5]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [3]),
        .I3(row[3]),
        .I4(row[4]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [4]),
        .O(row_hit_r_i_6__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_7__0
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [2]),
        .I1(row[2]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [1]),
        .I3(row[1]),
        .I4(row[0]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [0]),
        .O(row_hit_r_i_7__0_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns),
        .Q(row_hit_r),
        .R(1'b0));
  CARRY4 row_hit_r_reg_i_1__0
       (.CI(row_hit_r_reg_i_2__0_n_0),
        .CO({NLW_row_hit_r_reg_i_1__0_CO_UNCONNECTED[3:1],row_hit_ns}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_1__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,\app_addr_r1_reg[22] }));
  CARRY4 row_hit_r_reg_i_2__0
       (.CI(1'b0),
        .CO({row_hit_r_reg_i_2__0_n_0,row_hit_r_reg_i_2__0_n_1,row_hit_r_reg_i_2__0_n_2,row_hit_r_reg_i_2__0_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_2__0_O_UNCONNECTED[3:0]),
        .S({row_hit_r_i_4__0_n_0,row_hit_r_i_5__0_n_0,row_hit_r_i_6__0_n_0,row_hit_r_i_7__0_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__0 
       (.I0(\rd_this_rank_r_reg[0] ),
        .O(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_compare" *) 
module mig_7series_0_mig_7series_v2_3_bank_compare_2
   (p_149_out,
    \rd_this_rank_r_reg[0] ,
    bm_end_r1_reg,
    req_priority_r,
    q_has_priority_r_reg,
    row_hit_r,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    head_r_lcl_reg,
    q_entry_ns,
    set_order_q,
    wr_this_rank_r0,
    ras_timer_zero_r_reg,
    pass_open_bank_r_lcl_reg,
    \cmd_pipe_plus.mc_address_reg[13] ,
    head_r_lcl_reg_0,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    E,
    periodic_rd_insert,
    CLK,
    hi_priority,
    p_145_out,
    Q,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    req_wr_r_lcl_reg_0,
    p_91_out,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    S,
    periodic_rd_ack_r_lcl_reg,
    q_entry_r,
    pre_bm_end_r_reg_1,
    pre_bm_end_r_reg_2,
    periodic_rd_ack_r_lcl_reg_0,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    idle_r_lcl_reg,
    app_cmd_r2,
    app_rdy_r_reg,
    \app_cmd_r1_reg[1] ,
    \grant_r_reg[0] ,
    periodic_rd_ack_r_lcl_reg_1,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_req_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    wait_for_maint_r_lcl_reg,
    row,
    p_9_out,
    p_48_out,
    p_87_out,
    idle_r_lcl_reg_0,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] );
  output p_149_out;
  output \rd_this_rank_r_reg[0] ;
  output bm_end_r1_reg;
  output req_priority_r;
  output q_has_priority_r_reg;
  output row_hit_r;
  output \q_entry_r_reg[0] ;
  output \q_entry_r_reg[0]_0 ;
  output head_r_lcl_reg;
  output [0:0]q_entry_ns;
  output set_order_q;
  output wr_this_rank_r0;
  output ras_timer_zero_r_reg;
  output pass_open_bank_r_lcl_reg;
  output [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  output head_r_lcl_reg_0;
  output [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  output [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input hi_priority;
  input p_145_out;
  input [1:0]Q;
  input pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input req_wr_r_lcl_reg_0;
  input p_91_out;
  input [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input [0:0]S;
  input periodic_rd_ack_r_lcl_reg;
  input [0:0]q_entry_r;
  input pre_bm_end_r_reg_1;
  input pre_bm_end_r_reg_2;
  input periodic_rd_ack_r_lcl_reg_0;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input idle_r_lcl_reg;
  input [0:0]app_cmd_r2;
  input app_rdy_r_reg;
  input [0:0]\app_cmd_r1_reg[1] ;
  input [0:0]\grant_r_reg[0] ;
  input periodic_rd_ack_r_lcl_reg_1;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input maint_req_r;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input wait_for_maint_r_lcl_reg;
  input [13:0]row;
  input p_9_out;
  input p_48_out;
  input p_87_out;
  input [0:0]idle_r_lcl_reg_0;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;

  wire CLK;
  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]S;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_rdy_r_reg;
  wire bm_end_r1_reg;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [4:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] ;
  wire [0:0]\grant_r_reg[0] ;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire hi_priority;
  wire idle_r_lcl_reg;
  wire [0:0]idle_r_lcl_reg_0;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire maint_req_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire p_145_out;
  wire p_149_out;
  wire p_48_out;
  wire p_87_out;
  wire p_91_out;
  wire p_9_out;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_insert;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_bm_end_r_reg_2;
  wire [0:0]q_entry_ns;
  wire [0:0]q_entry_r;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire q_has_priority_r_reg;
  wire ras_timer_zero_r_reg;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rd_this_rank_r_reg[0] ;
  wire rd_wr_ns;
  wire [1:0]req_cmd_r;
  wire \req_cmd_r[0]_i_1__0_n_0 ;
  wire \req_cmd_r[1]_i_1__0_n_0 ;
  wire req_priority_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire [13:0]row;
  wire row_hit_ns;
  wire row_hit_r;
  wire row_hit_r_i_4_n_0;
  wire row_hit_r_i_5_n_0;
  wire row_hit_r_i_6_n_0;
  wire row_hit_r_i_7_n_0;
  wire row_hit_r_reg_i_2_n_0;
  wire row_hit_r_reg_i_2_n_1;
  wire row_hit_r_reg_i_2_n_2;
  wire row_hit_r_reg_i_2_n_3;
  wire set_order_q;
  wire wait_for_maint_r_lcl_reg;
  wire wr_this_rank_r0;
  wire [3:1]NLW_row_hit_r_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_row_hit_r_reg_i_2_O_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair760" *) 
  LUT4 #(
    .INIT(16'h7EE8)) 
    head_r_lcl_i_5
       (.I0(q_has_priority_r_reg),
        .I1(p_9_out),
        .I2(p_48_out),
        .I3(p_87_out),
        .O(head_r_lcl_reg_0));
  LUT2 #(
    .INIT(4'h8)) 
    \order_q_r[1]_i_3 
       (.I0(bm_end_r1_reg),
        .I1(periodic_rd_ack_r_lcl_reg_1),
        .O(set_order_q));
  LUT5 #(
    .INIT(32'hAAAA888A)) 
    pass_open_bank_r_lcl_i_3__2
       (.I0(row_hit_r),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .I2(maint_req_r),
        .I3(\maint_controller.maint_wip_r_lcl_reg ),
        .I4(wait_for_maint_r_lcl_reg),
        .O(pass_open_bank_r_lcl_reg));
  LUT6 #(
    .INIT(64'h8BFF8B008B008BFF)) 
    \q_entry_r[0]_i_2 
       (.I0(\q_entry_r_reg[0] ),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(q_entry_r),
        .I3(pre_bm_end_r_reg_1),
        .I4(pre_bm_end_r_reg_2),
        .I5(periodic_rd_ack_r_lcl_reg_0),
        .O(q_entry_ns));
  LUT6 #(
    .INIT(64'h555555556A556A6A)) 
    \q_entry_r[0]_i_3__1 
       (.I0(\q_entry_r_reg[0]_0 ),
        .I1(Q[0]),
        .I2(pre_bm_end_r_reg),
        .I3(pre_bm_end_r_reg_0),
        .I4(Q[1]),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .O(\q_entry_r_reg[0] ));
  LUT6 #(
    .INIT(64'h5555599959995999)) 
    \q_entry_r[0]_i_4__1 
       (.I0(\q_entry_r_reg[0]_0 ),
        .I1(req_wr_r_lcl_reg_0),
        .I2(p_91_out),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]),
        .I4(pre_bm_end_r_reg),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]),
        .O(head_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair760" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \q_entry_r[0]_i_5__0 
       (.I0(q_has_priority_r_reg),
        .I1(p_87_out),
        .I2(p_48_out),
        .I3(p_9_out),
        .O(\q_entry_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair759" *) 
  LUT2 #(
    .INIT(4'hB)) 
    ras_timer_zero_r_i_3__1
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(\grant_r_reg[0] ),
        .O(ras_timer_zero_r_reg));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_145_out),
        .Q(q_has_priority_r_reg),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair759" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__0
       (.I0(\rd_this_rank_r_reg[0] ),
        .I1(\grant_r_reg[0] ),
        .I2(idle_r_lcl_reg),
        .I3(\app_cmd_r2_reg[0] ),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(\rd_this_rank_r_reg[0] ),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [0]),
        .Q(\cmd_pipe_plus.mc_bank_reg[2] [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [1]),
        .Q(\cmd_pipe_plus.mc_bank_reg[2] [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[26] [2]),
        .Q(\cmd_pipe_plus.mc_bank_reg[2] [2]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    \req_cmd_r[0]_i_1__0 
       (.I0(req_cmd_r[0]),
        .I1(idle_r_lcl_reg),
        .I2(\app_cmd_r2_reg[0] ),
        .O(\req_cmd_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \req_cmd_r[1]_i_1__0 
       (.I0(req_cmd_r[1]),
        .I1(idle_r_lcl_reg),
        .I2(app_cmd_r2),
        .I3(app_rdy_r_reg),
        .I4(\app_cmd_r1_reg[1] ),
        .I5(periodic_rd_insert),
        .O(\req_cmd_r[1]_i_1__0_n_0 ));
  FDRE \req_cmd_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[0]_i_1__0_n_0 ),
        .Q(req_cmd_r[0]),
        .R(1'b0));
  FDRE \req_cmd_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\req_cmd_r[1]_i_1__0_n_0 ),
        .Q(req_cmd_r[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [0]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [1]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [2]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [3]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [4]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [5]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [6]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [7]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [8]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg[9] [9]),
        .Q(\cmd_pipe_plus.mc_address_reg[23] [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [3]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[4] 
       (.C(CLK),
        .CE(idle_r_lcl_reg_0),
        .D(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),
        .Q(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] [4]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(p_149_out),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\cmd_pipe_plus.mc_address_reg[13] [9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hCCAFFFAF)) 
    req_wr_r_lcl_i_1__0
       (.I0(\app_cmd_r2_reg[1] ),
        .I1(req_cmd_r[1]),
        .I2(\app_cmd_r2_reg[0] ),
        .I3(idle_r_lcl_reg),
        .I4(req_cmd_r[0]),
        .O(req_wr_r_lcl0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(bm_end_r1_reg),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_4
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [11]),
        .I1(row[11]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [10]),
        .I3(row[10]),
        .I4(row[9]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [9]),
        .O(row_hit_r_i_4_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_5
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [8]),
        .I1(row[8]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [6]),
        .I3(row[6]),
        .I4(row[7]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [7]),
        .O(row_hit_r_i_5_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_6
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [5]),
        .I1(row[5]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [4]),
        .I3(row[4]),
        .I4(row[3]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [3]),
        .O(row_hit_r_i_6_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_r_i_7
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [2]),
        .I1(row[2]),
        .I2(\cmd_pipe_plus.mc_address_reg[13] [1]),
        .I3(row[1]),
        .I4(row[0]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [0]),
        .O(row_hit_r_i_7_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns),
        .Q(row_hit_r),
        .R(1'b0));
  CARRY4 row_hit_r_reg_i_1
       (.CI(row_hit_r_reg_i_2_n_0),
        .CO({NLW_row_hit_r_reg_i_1_CO_UNCONNECTED[3:1],row_hit_ns}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,S}));
  CARRY4 row_hit_r_reg_i_2
       (.CI(1'b0),
        .CO({row_hit_r_reg_i_2_n_0,row_hit_r_reg_i_2_n_1,row_hit_r_reg_i_2_n_2,row_hit_r_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_r_reg_i_2_O_UNCONNECTED[3:0]),
        .S({row_hit_r_i_4_n_0,row_hit_r_i_5_n_0,row_hit_r_i_6_n_0,row_hit_r_i_7_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1 
       (.I0(\rd_this_rank_r_reg[0] ),
        .O(wr_this_rank_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_mach" *) 
module mig_7series_0_mig_7series_v2_3_bank_mach
   (req_periodic_rd_r_lcl_reg,
    accept_ns,
    insert_maint_r,
    \cmd_pipe_plus.mc_cmd_reg[0] ,
    insert_maint_r1,
    DIC,
    col_rd_wr_r,
    \col_mux.col_rd_wr_r_reg ,
    cke_r,
    bm_end_r1,
    bm_end_r1_0,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    maint_wip_r,
    wait_for_maint_r,
    wait_for_maint_r_0,
    wait_for_maint_r_1,
    wait_for_maint_r_2,
    periodic_rd_cntr_r,
    \cmd_pipe_plus.mc_ras_n_reg[1] ,
    E,
    D,
    \maint_controller.maint_hit_busies_r_reg[2] ,
    \maint_controller.maint_hit_busies_r_reg[3] ,
    \maint_controller.maint_hit_busies_r_reg[0] ,
    \maint_controller.maint_hit_busies_r_reg[1] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    demand_priority_r_reg,
    demand_priority_r_reg_0,
    demand_priority_r_reg_1,
    Q,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[13] ,
    \cmd_pipe_plus.mc_address_reg[13]_0 ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    \cmd_pipe_plus.wr_data_en_reg ,
    \wtr_timer.wtr_cnt_r_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    read_this_rank,
    int_read_this_rank,
    mc_odt_ns,
    col_data_buf_addr,
    sre_clears_sre_request,
    \maintenance_request.upd_last_master_r_reg ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_bank_reg[8]_0 ,
    mc_cas_n_ns,
    \cmd_pipe_plus.mc_bank_reg[8]_1 ,
    mc_ras_n_ns,
    act_this_rank,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,
    mc_cs_n_ns,
    \cmd_pipe_plus.mc_address_reg[41]_0 ,
    \cmd_pipe_plus.mc_address_reg[41]_1 ,
    CLK,
    was_wr0,
    maint_srx_r,
    rstdiv0_sync_r1_reg_rep__1,
    mc_cke_ns,
    p_145_out,
    rstdiv0_sync_r1_reg_rep__0,
    p_106_out,
    p_67_out,
    phy_mc_ctl_full,
    of_ctl_full_v,
    p_28_out,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    rstdiv0_sync_r1_reg_rep__18,
    rstdiv0_sync_r1_reg_rep__19,
    \periodic_read_request.periodic_rd_r_lcl_reg ,
    \maintenance_request.maint_zq_r_lcl_reg ,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    init_calib_complete_reg_rep,
    rstdiv0_sync_r1_reg_rep__20_0,
    app_rdy_r_reg,
    app_en_r2,
    rstdiv0_sync_r1_reg_rep__21,
    mc_cmd,
    rstdiv0_sync_r1_reg_rep__24,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    rstdiv0_sync_r1_reg_rep__20_1,
    S,
    \app_addr_r1_reg[22] ,
    \app_addr_r1_reg[22]_0 ,
    \app_addr_r1_reg[22]_1 ,
    rstdiv0_sync_r1_reg_rep__19_0,
    read_this_rank_r,
    rstdiv0_sync_r1_reg_rep__20_2,
    rstdiv0_sync_r1_reg_rep__20_3,
    rstdiv0_sync_r1_reg_rep__20_4,
    maint_req_r,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    app_cmd_r2,
    \app_cmd_r1_reg[1] ,
    maint_sre_r,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    row,
    maint_zq_r,
    inhbt_act_faw_r,
    col_wr_data_buf_addr_r,
    maint_rank_r,
    phy_mc_data_full,
    \maintenance_request.maint_sre_r_lcl_reg ,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] ,
    \maintenance_request.maint_zq_r_lcl_reg_1 );
  output req_periodic_rd_r_lcl_reg;
  output accept_ns;
  output insert_maint_r;
  output \cmd_pipe_plus.mc_cmd_reg[0] ;
  output insert_maint_r1;
  output [0:0]DIC;
  output col_rd_wr_r;
  output \col_mux.col_rd_wr_r_reg ;
  output cke_r;
  output bm_end_r1;
  output bm_end_r1_0;
  output ras_timer_zero_r_reg;
  output ras_timer_zero_r_reg_0;
  output maint_wip_r;
  output wait_for_maint_r;
  output wait_for_maint_r_0;
  output wait_for_maint_r_1;
  output wait_for_maint_r_2;
  output periodic_rd_cntr_r;
  output \cmd_pipe_plus.mc_ras_n_reg[1] ;
  output [0:0]E;
  output [2:0]D;
  output \maint_controller.maint_hit_busies_r_reg[2] ;
  output \maint_controller.maint_hit_busies_r_reg[3] ;
  output \maint_controller.maint_hit_busies_r_reg[0] ;
  output \maint_controller.maint_hit_busies_r_reg[1] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output demand_priority_r_reg;
  output demand_priority_r_reg_0;
  output demand_priority_r_reg_1;
  output [2:0]Q;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[13] ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[13]_0 ;
  output [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  output \cmd_pipe_plus.wr_data_en_reg ;
  output \wtr_timer.wtr_cnt_r_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  output read_this_rank;
  output int_read_this_rank;
  output [0:0]mc_odt_ns;
  output [4:0]col_data_buf_addr;
  output sre_clears_sre_request;
  output \maintenance_request.upd_last_master_r_reg ;
  output [38:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  output [0:0]mc_cas_n_ns;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  output [1:0]mc_ras_n_ns;
  output act_this_rank;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  output [0:0]mc_cs_n_ns;
  output [1:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[41]_1 ;
  input CLK;
  input was_wr0;
  input maint_srx_r;
  input rstdiv0_sync_r1_reg_rep__1;
  input [0:0]mc_cke_ns;
  input p_145_out;
  input rstdiv0_sync_r1_reg_rep__0;
  input p_106_out;
  input p_67_out;
  input phy_mc_ctl_full;
  input [0:0]of_ctl_full_v;
  input p_28_out;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input wait_for_maint_r_lcl_reg_2;
  input rstdiv0_sync_r1_reg_rep__18;
  input rstdiv0_sync_r1_reg_rep__19;
  input \periodic_read_request.periodic_rd_r_lcl_reg ;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input init_calib_complete_reg_rep;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input app_rdy_r_reg;
  input app_en_r2;
  input rstdiv0_sync_r1_reg_rep__21;
  input [0:0]mc_cmd;
  input rstdiv0_sync_r1_reg_rep__24;
  input [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input [0:0]S;
  input [0:0]\app_addr_r1_reg[22] ;
  input [0:0]\app_addr_r1_reg[22]_0 ;
  input [0:0]\app_addr_r1_reg[22]_1 ;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input read_this_rank_r;
  input rstdiv0_sync_r1_reg_rep__20_2;
  input rstdiv0_sync_r1_reg_rep__20_3;
  input rstdiv0_sync_r1_reg_rep__20_4;
  input maint_req_r;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input [0:0]app_cmd_r2;
  input [0:0]\app_cmd_r1_reg[1] ;
  input maint_sre_r;
  input \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input [13:0]row;
  input maint_zq_r;
  input inhbt_act_faw_r;
  input [4:0]col_wr_data_buf_addr_r;
  input maint_rank_r;
  input phy_mc_data_full;
  input \maintenance_request.maint_sre_r_lcl_reg ;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;
  input \maintenance_request.maint_zq_r_lcl_reg_1 ;

  wire CLK;
  wire [2:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [2:0]Q;
  wire [0:0]S;
  wire accept_ns;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [0:0]\app_addr_r1_reg[22]_0 ;
  wire [0:0]\app_addr_r1_reg[22]_1 ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_en_r2;
  wire app_rdy_r_reg;
  wire arb_mux0_n_103;
  wire arb_mux0_n_105;
  wire arb_mux0_n_13;
  wire arb_mux0_n_14;
  wire arb_mux0_n_16;
  wire arb_mux0_n_17;
  wire arb_mux0_n_22;
  wire arb_mux0_n_23;
  wire arb_mux0_n_24;
  wire arb_mux0_n_37;
  wire arb_mux0_n_38;
  wire arb_mux0_n_42;
  wire arb_mux0_n_50;
  wire arb_mux0_n_51;
  wire arb_mux0_n_7;
  wire \arb_row_col0/granted_col_ns ;
  wire \arb_row_col0/rnk_config_strobe_ns ;
  wire auto_pre_r;
  wire auto_pre_r_12;
  wire auto_pre_r_19;
  wire auto_pre_r_2;
  wire \bank_cntrl[0].bank0_n_18 ;
  wire \bank_cntrl[0].bank0_n_19 ;
  wire \bank_cntrl[0].bank0_n_20 ;
  wire \bank_cntrl[0].bank0_n_21 ;
  wire \bank_cntrl[0].bank0_n_22 ;
  wire \bank_cntrl[0].bank0_n_23 ;
  wire \bank_cntrl[0].bank0_n_24 ;
  wire \bank_cntrl[0].bank0_n_25 ;
  wire \bank_cntrl[0].bank0_n_27 ;
  wire \bank_cntrl[0].bank0_n_28 ;
  wire \bank_cntrl[0].bank0_n_29 ;
  wire \bank_cntrl[0].bank0_n_31 ;
  wire \bank_cntrl[0].bank0_n_33 ;
  wire \bank_cntrl[0].bank0_n_34 ;
  wire \bank_cntrl[0].bank0_n_36 ;
  wire \bank_cntrl[0].bank0_n_37 ;
  wire \bank_cntrl[0].bank0_n_39 ;
  wire \bank_cntrl[0].bank0_n_40 ;
  wire \bank_cntrl[0].bank0_n_42 ;
  wire \bank_cntrl[0].bank0_n_43 ;
  wire \bank_cntrl[0].bank0_n_45 ;
  wire \bank_cntrl[0].bank0_n_60 ;
  wire \bank_cntrl[0].bank0_n_61 ;
  wire \bank_cntrl[1].bank0_n_18 ;
  wire \bank_cntrl[1].bank0_n_19 ;
  wire \bank_cntrl[1].bank0_n_20 ;
  wire \bank_cntrl[1].bank0_n_21 ;
  wire \bank_cntrl[1].bank0_n_22 ;
  wire \bank_cntrl[1].bank0_n_23 ;
  wire \bank_cntrl[1].bank0_n_25 ;
  wire \bank_cntrl[1].bank0_n_26 ;
  wire \bank_cntrl[1].bank0_n_27 ;
  wire \bank_cntrl[1].bank0_n_28 ;
  wire \bank_cntrl[1].bank0_n_29 ;
  wire \bank_cntrl[1].bank0_n_30 ;
  wire \bank_cntrl[1].bank0_n_31 ;
  wire \bank_cntrl[1].bank0_n_33 ;
  wire \bank_cntrl[1].bank0_n_36 ;
  wire \bank_cntrl[1].bank0_n_37 ;
  wire \bank_cntrl[1].bank0_n_39 ;
  wire \bank_cntrl[1].bank0_n_41 ;
  wire \bank_cntrl[1].bank0_n_42 ;
  wire \bank_cntrl[1].bank0_n_43 ;
  wire \bank_cntrl[1].bank0_n_44 ;
  wire \bank_cntrl[1].bank0_n_59 ;
  wire \bank_cntrl[1].bank0_n_60 ;
  wire \bank_cntrl[2].bank0_n_17 ;
  wire \bank_cntrl[2].bank0_n_18 ;
  wire \bank_cntrl[2].bank0_n_19 ;
  wire \bank_cntrl[2].bank0_n_20 ;
  wire \bank_cntrl[2].bank0_n_24 ;
  wire \bank_cntrl[2].bank0_n_27 ;
  wire \bank_cntrl[2].bank0_n_28 ;
  wire \bank_cntrl[2].bank0_n_29 ;
  wire \bank_cntrl[2].bank0_n_30 ;
  wire \bank_cntrl[2].bank0_n_31 ;
  wire \bank_cntrl[2].bank0_n_32 ;
  wire \bank_cntrl[2].bank0_n_33 ;
  wire \bank_cntrl[2].bank0_n_34 ;
  wire \bank_cntrl[2].bank0_n_35 ;
  wire \bank_cntrl[2].bank0_n_37 ;
  wire \bank_cntrl[2].bank0_n_38 ;
  wire \bank_cntrl[2].bank0_n_40 ;
  wire \bank_cntrl[2].bank0_n_55 ;
  wire \bank_cntrl[2].bank0_n_60 ;
  wire \bank_cntrl[2].bank0_n_61 ;
  wire \bank_cntrl[3].bank0_n_20 ;
  wire \bank_cntrl[3].bank0_n_21 ;
  wire \bank_cntrl[3].bank0_n_22 ;
  wire \bank_cntrl[3].bank0_n_23 ;
  wire \bank_cntrl[3].bank0_n_25 ;
  wire \bank_cntrl[3].bank0_n_26 ;
  wire \bank_cntrl[3].bank0_n_27 ;
  wire \bank_cntrl[3].bank0_n_28 ;
  wire \bank_cntrl[3].bank0_n_42 ;
  wire \bank_cntrl[3].bank0_n_46 ;
  wire \bank_cntrl[3].bank0_n_48 ;
  wire \bank_cntrl[3].bank0_n_49 ;
  wire \bank_cntrl[3].bank0_n_50 ;
  wire \bank_cntrl[3].bank0_n_51 ;
  wire \bank_cntrl[3].bank0_n_52 ;
  wire \bank_cntrl[3].bank0_n_53 ;
  wire \bank_cntrl[3].bank0_n_55 ;
  wire \bank_cntrl[3].bank0_n_56 ;
  wire \bank_cntrl[3].bank0_n_57 ;
  wire \bank_cntrl[3].bank0_n_58 ;
  wire \bank_cntrl[3].bank0_n_59 ;
  wire \bank_cntrl[3].bank0_n_60 ;
  wire \bank_cntrl[3].bank0_n_61 ;
  wire \bank_cntrl[3].bank0_n_62 ;
  wire \bank_cntrl[3].bank0_n_63 ;
  wire bank_common0_n_10;
  wire bank_common0_n_11;
  wire bank_common0_n_12;
  wire bank_common0_n_14;
  wire bank_common0_n_16;
  wire bank_common0_n_17;
  wire bank_common0_n_18;
  wire bank_common0_n_21;
  wire bank_common0_n_22;
  wire bank_common0_n_23;
  wire bank_common0_n_24;
  wire bank_common0_n_25;
  wire bank_common0_n_26;
  wire bank_common0_n_27;
  wire bank_common0_n_28;
  wire bank_common0_n_31;
  wire bank_common0_n_7;
  wire bank_common0_n_8;
  wire bank_common0_n_9;
  wire [9:0]\bank_compare0/req_col_r ;
  wire [9:0]\bank_compare0/req_col_r_1 ;
  wire [9:0]\bank_compare0/req_col_r_18 ;
  wire [9:0]\bank_compare0/req_col_r_9 ;
  wire \bank_queue0/clear_req ;
  wire \bank_queue0/clear_req_3 ;
  wire [1:0]\bank_queue0/order_q_r ;
  wire [1:1]\bank_queue0/q_entry_ns ;
  wire [0:0]\bank_queue0/q_entry_ns_0 ;
  wire \bank_state0/col_wait_r ;
  wire \bank_state0/col_wait_r_26 ;
  wire \bank_state0/demand_act_priority_r ;
  wire \bank_state0/demand_act_priority_r_17 ;
  wire \bank_state0/demand_act_priority_r_25 ;
  wire \bank_state0/demand_act_priority_r_8 ;
  wire \bank_state0/demand_priority_r ;
  wire \bank_state0/demand_priority_r_16 ;
  wire \bank_state0/demand_priority_r_24 ;
  wire \bank_state0/demand_priority_r_7 ;
  wire \bank_state0/demanded_prior_r ;
  wire \bank_state0/demanded_prior_r_15 ;
  wire \bank_state0/demanded_prior_r_23 ;
  wire \bank_state0/demanded_prior_r_6 ;
  wire \bank_state0/ofs_rdy_r ;
  wire \bank_state0/ofs_rdy_r0 ;
  wire \bank_state0/ofs_rdy_r0_10 ;
  wire \bank_state0/ofs_rdy_r0_11 ;
  wire \bank_state0/ofs_rdy_r_14 ;
  wire \bank_state0/ofs_rdy_r_22 ;
  wire \bank_state0/ofs_rdy_r_5 ;
  wire \bank_state0/override_demand_ns ;
  wire \bank_state0/override_demand_r ;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire cke_r;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[13]_0 ;
  wire [38:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[41]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  wire [1:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire \cmd_pipe_plus.mc_cmd_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_ras_n_reg[1] ;
  wire \cmd_pipe_plus.wr_data_en_reg ;
  wire [4:0]col_data_buf_addr;
  wire \col_mux.col_rd_wr_r_reg ;
  wire col_rd_wr_r;
  wire [4:0]col_wr_data_buf_addr_r;
  wire cs_en2;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire granted_pre_ns;
  wire granted_row_ns;
  wire hi_priority;
  wire inhbt_act_faw_r;
  wire init_calib_complete_reg_rep;
  wire insert_maint_r;
  wire insert_maint_r1;
  wire int_read_this_rank;
  wire \maint_controller.maint_hit_busies_r_reg[0] ;
  wire \maint_controller.maint_hit_busies_r_reg[1] ;
  wire \maint_controller.maint_hit_busies_r_reg[2] ;
  wire \maint_controller.maint_hit_busies_r_reg[3] ;
  wire maint_rank_r;
  wire maint_req_r;
  wire maint_sre_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_sre_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire \maintenance_request.maint_zq_r_lcl_reg_1 ;
  wire \maintenance_request.upd_last_master_r_reg ;
  wire [0:0]mc_cas_n_ns;
  wire [0:0]mc_cke_ns;
  wire [0:0]mc_cmd;
  wire [0:0]mc_cs_n_ns;
  wire [0:0]mc_odt_ns;
  wire [1:0]mc_ras_n_ns;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire [0:0]of_ctl_full_v;
  wire p_103_out;
  wire p_106_out;
  wire p_110_out;
  wire [11:0]p_112_out;
  wire p_115_out;
  wire p_11_out;
  wire [4:0]p_123_out;
  wire p_126_out;
  wire p_128_out;
  wire p_129_out;
  wire p_12_out;
  wire p_130_out;
  wire p_131_out;
  wire p_132_out;
  wire p_142_out;
  wire p_145_out;
  wire p_149_out;
  wire p_14_out;
  wire [11:0]p_151_out;
  wire p_154_out;
  wire p_15_out;
  wire p_25_out;
  wire p_28_out;
  wire p_32_out;
  wire [11:0]p_34_out;
  wire p_37_out;
  wire [4:0]p_45_out;
  wire p_48_out;
  wire p_50_out;
  wire p_51_out;
  wire p_53_out;
  wire p_67_out;
  wire [4:0]p_6_out;
  wire p_71_out;
  wire [11:0]p_73_out;
  wire p_76_out;
  wire p_7_in;
  wire [4:0]p_84_out;
  wire p_87_out;
  wire p_89_out;
  wire p_90_out;
  wire p_91_out;
  wire p_92_out;
  wire p_9_out;
  wire periodic_rd_ack_ns;
  wire periodic_rd_cntr_r;
  wire periodic_rd_insert;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire [0:0]q_entry_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire [5:3]rb_hit_busies_r;
  wire [6:4]rb_hit_busies_r_20;
  wire [3:0]rd_this_rank_r;
  wire read_this_rank;
  wire read_this_rank_r;
  wire req_periodic_rd_r_lcl_reg;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  wire [13:0]row;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__20_2;
  wire rstdiv0_sync_r1_reg_rep__20_3;
  wire rstdiv0_sync_r1_reg_rep__20_4;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire [3:0]sending_col;
  wire [3:0]sending_pre;
  wire [3:0]sending_row;
  wire sre_clears_sre_request;
  wire tail_r;
  wire tail_r_13;
  wire tail_r_21;
  wire tail_r_4;
  wire wait_for_maint_r;
  wire wait_for_maint_r_0;
  wire wait_for_maint_r_1;
  wire wait_for_maint_r_2;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire was_priority;
  wire was_wr;
  wire was_wr0;
  wire [3:0]wr_this_rank_r;
  wire \wtr_timer.wtr_cnt_r_reg[0] ;
  wire [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;

  mig_7series_0_mig_7series_v2_3_arb_mux arb_mux0
       (.CLK(CLK),
        .D(D),
        .DIC(DIC),
        .E(E),
        .Q(sending_col),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_r_lcl_reg(\bank_cntrl[3].bank0_n_60 ),
        .act_wait_r_lcl_reg_0(\bank_cntrl[3].bank0_n_22 ),
        .act_wait_r_lcl_reg_1(\bank_cntrl[2].bank0_n_24 ),
        .auto_pre_r(auto_pre_r_19),
        .auto_pre_r_6(auto_pre_r),
        .auto_pre_r_7(auto_pre_r_2),
        .auto_pre_r_8(auto_pre_r_12),
        .auto_pre_r_lcl_reg(\bank_cntrl[0].bank0_n_45 ),
        .auto_pre_r_lcl_reg_0(\bank_cntrl[1].bank0_n_44 ),
        .auto_pre_r_lcl_reg_1(\bank_cntrl[2].bank0_n_40 ),
        .auto_pre_r_lcl_reg_2(\bank_cntrl[3].bank0_n_59 ),
        .cke_r(cke_r),
        .\cmd_pipe_plus.mc_address_reg[41] ({\cmd_pipe_plus.mc_address_reg[41] [38:36],\cmd_pipe_plus.mc_address_reg[41] [34:0]}),
        .\cmd_pipe_plus.mc_bank_reg[2] (arb_mux0_n_105),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2] ),
        .\cmd_pipe_plus.mc_cmd_reg[0] (\cmd_pipe_plus.mc_cmd_reg[0] ),
        .\cmd_pipe_plus.mc_cs_n_reg[0] (insert_maint_r1),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[1] (\cmd_pipe_plus.mc_ras_n_reg[1] ),
        .\cmd_pipe_plus.mc_we_n_reg[0] (sending_row),
        .\cmd_pipe_plus.wr_data_en_reg (\cmd_pipe_plus.wr_data_en_reg ),
        .col_data_buf_addr(col_data_buf_addr),
        .\col_mux.col_rd_wr_r_reg (\col_mux.col_rd_wr_r_reg ),
        .col_rd_wr_r(col_rd_wr_r),
        .col_wait_r(\bank_state0/col_wait_r_26 ),
        .col_wait_r_0(\bank_state0/col_wait_r ),
        .col_wait_r_reg(\bank_cntrl[3].bank0_n_48 ),
        .col_wait_r_reg_0(\bank_cntrl[0].bank0_n_33 ),
        .col_wait_r_reg_1(\bank_cntrl[0].bank0_n_34 ),
        .col_wait_r_reg_2(\bank_cntrl[2].bank0_n_34 ),
        .col_wait_r_reg_3(\bank_cntrl[3].bank0_n_21 ),
        .col_wait_r_reg_4(\bank_cntrl[1].bank0_n_31 ),
        .col_wait_r_reg_5(\bank_cntrl[3].bank0_n_49 ),
        .col_wr_data_buf_addr_r(col_wr_data_buf_addr_r),
        .cs_en2(cs_en2),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r_17 ),
        .demand_act_priority_r_4(\bank_state0/demand_act_priority_r_25 ),
        .demand_act_priority_r_5(\bank_state0/demand_act_priority_r ),
        .demand_act_priority_r_9(\bank_state0/demand_act_priority_r_8 ),
        .demand_act_priority_r_reg(\bank_cntrl[1].bank0_n_41 ),
        .demand_act_priority_r_reg_0(\bank_cntrl[1].bank0_n_42 ),
        .demand_priority_r_reg(\bank_cntrl[3].bank0_n_25 ),
        .demand_priority_r_reg_0(\bank_cntrl[1].bank0_n_59 ),
        .demand_priority_r_reg_1(\bank_cntrl[3].bank0_n_63 ),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r),
        .\grant_r_reg[0] (arb_mux0_n_22),
        .\grant_r_reg[0]_0 (arb_mux0_n_23),
        .\grant_r_reg[0]_1 (\bank_cntrl[3].bank0_n_56 ),
        .\grant_r_reg[1] (arb_mux0_n_17),
        .\grant_r_reg[1]_0 (arb_mux0_n_37),
        .\grant_r_reg[1]_1 (arb_mux0_n_38),
        .\grant_r_reg[1]_2 (arb_mux0_n_103),
        .\grant_r_reg[2] (arb_mux0_n_16),
        .\grant_r_reg[3] (\bank_cntrl[3].bank0_n_27 ),
        .granted_col_ns(\arb_row_col0/granted_col_ns ),
        .granted_col_r_reg(arb_mux0_n_13),
        .granted_col_r_reg_0(arb_mux0_n_14),
        .granted_col_r_reg_1(arb_mux0_n_24),
        .granted_col_r_reg_2(arb_mux0_n_42),
        .granted_pre_ns(granted_pre_ns),
        .granted_row_ns(granted_row_ns),
        .head_r_lcl_reg(\bank_cntrl[2].bank0_n_55 ),
        .head_r_lcl_reg_0(\bank_cntrl[3].bank0_n_61 ),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_60 ),
        .idle_r_lcl_reg(\bank_cntrl[1].bank0_n_25 ),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .int_read_this_rank(int_read_this_rank),
        .\last_master_r_reg[0] (arb_mux0_n_51),
        .\last_master_r_reg[2] (arb_mux0_n_50),
        .\last_master_r_reg[3] (sending_pre),
        .maint_rank_r(maint_rank_r),
        .maint_sre_r(maint_sre_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_cke_ns(mc_cke_ns),
        .mc_cmd(mc_cmd),
        .mc_cs_n_ns(mc_cs_n_ns),
        .mc_odt_ns(mc_odt_ns),
        .mc_ras_n_ns(mc_ras_n_ns),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_22 ),
        .ofs_rdy_r_1(\bank_state0/ofs_rdy_r ),
        .ofs_rdy_r_2(\bank_state0/ofs_rdy_r_14 ),
        .ofs_rdy_r_3(\bank_state0/ofs_rdy_r_5 ),
        .\order_q_r_reg[0] (\bank_cntrl[3].bank0_n_23 ),
        .\order_q_r_reg[0]_0 (\bank_cntrl[1].bank0_n_19 ),
        .override_demand_ns(\bank_state0/override_demand_ns ),
        .p_110_out(p_110_out),
        .p_115_out(p_115_out),
        .p_131_out(p_131_out),
        .p_149_out(p_149_out),
        .p_14_out(p_14_out),
        .p_154_out(p_154_out),
        .p_32_out(p_32_out),
        .p_37_out(p_37_out),
        .p_53_out(p_53_out),
        .p_71_out(p_71_out),
        .p_76_out(p_76_out),
        .p_92_out(p_92_out),
        .ras_timer_zero_r_reg(\bank_cntrl[3].bank0_n_58 ),
        .ras_timer_zero_r_reg_0(\bank_cntrl[3].bank0_n_57 ),
        .ras_timer_zero_r_reg_1(\bank_cntrl[1].bank0_n_43 ),
        .ras_timer_zero_r_reg_2(\bank_cntrl[1].bank0_n_39 ),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r_lcl_reg(\bank_cntrl[1].bank0_n_18 ),
        .rd_wr_r_lcl_reg_0(\bank_cntrl[0].bank0_n_18 ),
        .rd_wr_r_lcl_reg_1(\bank_cntrl[2].bank0_n_18 ),
        .rd_wr_r_lcl_reg_2(\bank_cntrl[0].bank0_n_31 ),
        .read_this_rank(read_this_rank),
        .read_this_rank_r(read_this_rank_r),
        .\req_bank_r_lcl_reg[2] (Q),
        .\req_bank_r_lcl_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\req_bank_r_lcl_reg[2]_1 (\cmd_pipe_plus.mc_bank_reg[8]_0 ),
        .\req_bank_r_lcl_reg[2]_2 (\cmd_pipe_plus.mc_bank_reg[8]_1 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r_18 ),
        .\req_col_r_reg[9]_0 (\bank_compare0/req_col_r ),
        .\req_col_r_reg[9]_1 (\bank_compare0/req_col_r_1 ),
        .\req_col_r_reg[9]_2 (\bank_compare0/req_col_r_9 ),
        .\req_data_buf_addr_r_reg[4] (p_45_out),
        .\req_data_buf_addr_r_reg[4]_0 (p_6_out),
        .\req_data_buf_addr_r_reg[4]_1 (p_84_out),
        .\req_data_buf_addr_r_reg[4]_2 (p_123_out),
        .\req_row_r_lcl_reg[13] ({\cmd_pipe_plus.mc_address_reg[13] ,p_151_out}),
        .\req_row_r_lcl_reg[13]_0 ({\cmd_pipe_plus.mc_address_reg[13]_0 ,p_112_out[11],p_112_out[9:0]}),
        .\req_row_r_lcl_reg[13]_1 ({\cmd_pipe_plus.mc_address_reg[41]_0 ,p_73_out}),
        .\req_row_r_lcl_reg[13]_2 ({\cmd_pipe_plus.mc_address_reg[41]_1 ,p_34_out[11],p_34_out[9:0]}),
        .\rnk_config_r_reg[0] (arb_mux0_n_7),
        .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .sre_clears_sre_request(sre_clears_sre_request),
        .wr_this_rank_r(wr_this_rank_r),
        .\wtr_timer.wtr_cnt_r_reg[0] (\wtr_timer.wtr_cnt_r_reg[0] ),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ));
  mig_7series_0_mig_7series_v2_3_bank_cntrl \bank_cntrl[0].bank0 
       (.CLK(CLK),
        .Q({rb_hit_busies_r_20[6],rb_hit_busies_r_20[4]}),
        .S(S),
        .accept_r_reg(bank_common0_n_26),
        .act_this_rank_r(act_this_rank_r[0]),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_en_r2_reg(bank_common0_n_27),
        .app_rdy_r_reg(app_rdy_r_reg),
        .auto_pre_r(auto_pre_r),
        .auto_pre_r_lcl_reg(wait_for_maint_r),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_reg(\bank_cntrl[3].bank0_n_46 ),
        .bm_end_r1_reg_0(\bank_cntrl[2].bank0_n_31 ),
        .bm_end_r1_reg_1(\bank_cntrl[1].bank0_n_29 ),
        .clear_req(\bank_queue0/clear_req ),
        .clear_req_1(\bank_queue0/clear_req_3 ),
        .\cmd_pipe_plus.mc_address_reg[13] ({\cmd_pipe_plus.mc_address_reg[13] ,p_151_out}),
        .\cmd_pipe_plus.mc_address_reg[23] (\bank_compare0/req_col_r ),
        .\cmd_pipe_plus.mc_bank_reg[2] (Q),
        .col_wait_r_reg(\bank_cntrl[3].bank0_n_48 ),
        .col_wait_r_reg_0(\bank_cntrl[1].bank0_n_31 ),
        .\compute_tail.tail_r_lcl_reg (\bank_cntrl[0].bank0_n_24 ),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (p_123_out),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r ),
        .demand_priority_r(\bank_state0/demand_priority_r ),
        .demand_priority_r_3(\bank_state0/demand_priority_r_16 ),
        .demand_priority_r_reg(demand_priority_r_reg_0),
        .demand_priority_r_reg_0(\bank_cntrl[2].bank0_n_28 ),
        .demanded_prior_r(\bank_state0/demanded_prior_r ),
        .demanded_prior_r_2(\bank_state0/demanded_prior_r_15 ),
        .demanded_prior_r_reg(\bank_cntrl[0].bank0_n_61 ),
        .demanded_prior_r_reg_0(\bank_cntrl[3].bank0_n_62 ),
        .demanded_prior_r_reg_1(\bank_cntrl[2].bank0_n_29 ),
        .\grant_r_reg[0] (\bank_cntrl[0].bank0_n_18 ),
        .\grant_r_reg[0]_0 (sending_row[0]),
        .\grant_r_reg[0]_1 (sending_pre[0]),
        .\grant_r_reg[1] (\bank_cntrl[0].bank0_n_34 ),
        .\grant_r_reg[1]_0 (\bank_cntrl[0].bank0_n_60 ),
        .\grant_r_reg[1]_1 (arb_mux0_n_13),
        .\grant_r_reg[2] (\bank_cntrl[0].bank0_n_27 ),
        .\grant_r_reg[2]_0 ({sending_col[2],sending_col[0]}),
        .\grant_r_reg[2]_1 (\bank_cntrl[2].bank0_n_27 ),
        .\grant_r_reg[3] (\bank_cntrl[3].bank0_n_26 ),
        .granted_col_ns(\arb_row_col0/granted_col_ns ),
        .granted_col_r_reg(\bank_cntrl[0].bank0_n_31 ),
        .granted_col_r_reg_0(\cmd_pipe_plus.mc_cmd_reg[0] ),
        .head_r_lcl_reg(\bank_cntrl[0].bank0_n_21 ),
        .head_r_lcl_reg_0(\bank_cntrl[0].bank0_n_22 ),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_23 ),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(bank_common0_n_31),
        .idle_r_lcl_reg_0(bank_common0_n_18),
        .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_1 ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_11 ),
        .ordered_r_lcl_reg(\bank_cntrl[2].bank0_n_33 ),
        .ordered_r_lcl_reg_0(\bank_cntrl[2].bank0_n_32 ),
        .p_106_out(p_106_out),
        .p_126_out(p_126_out),
        .p_128_out(p_128_out),
        .p_129_out(p_129_out),
        .p_12_out(p_12_out),
        .p_130_out(p_130_out),
        .p_131_out(p_131_out),
        .p_132_out(p_132_out),
        .p_142_out(p_142_out),
        .p_145_out(p_145_out),
        .p_149_out(p_149_out),
        .p_154_out(p_154_out),
        .p_28_out(p_28_out),
        .p_48_out(p_48_out),
        .p_51_out(p_51_out),
        .p_67_out(p_67_out),
        .p_87_out(p_87_out),
        .p_90_out(p_90_out),
        .p_91_out(p_91_out),
        .p_9_out(p_9_out),
        .periodic_rd_ack_r_lcl_reg(\maint_controller.maint_hit_busies_r_reg[0] ),
        .periodic_rd_ack_r_lcl_reg_0(bank_common0_n_16),
        .periodic_rd_ack_r_lcl_reg_1(\maint_controller.maint_hit_busies_r_reg[3] ),
        .periodic_rd_ack_r_lcl_reg_2(bank_common0_n_22),
        .periodic_rd_insert(periodic_rd_insert),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[0].bank0_n_45 ),
        .pre_bm_end_r_reg(\bank_cntrl[3].bank0_n_51 ),
        .pre_bm_end_r_reg_0(\bank_cntrl[2].bank0_n_17 ),
        .pre_bm_end_r_reg_1(\bank_cntrl[3].bank0_n_20 ),
        .pre_passing_open_bank_r_reg(\bank_cntrl[2].bank0_n_38 ),
        .pre_passing_open_bank_r_reg_0(\bank_cntrl[1].bank0_n_33 ),
        .pre_passing_open_bank_r_reg_1(\bank_cntrl[3].bank0_n_53 ),
        .q_entry_ns(\bank_queue0/q_entry_ns_0 ),
        .q_entry_ns_0(\bank_queue0/q_entry_ns ),
        .q_entry_r(q_entry_r),
        .\q_entry_r_reg[0] (\bank_cntrl[0].bank0_n_19 ),
        .\q_entry_r_reg[0]_0 (\bank_cntrl[0].bank0_n_20 ),
        .\q_entry_r_reg[0]_1 (\bank_cntrl[0].bank0_n_42 ),
        .\q_entry_r_reg[0]_2 (\bank_cntrl[1].bank0_n_36 ),
        .\q_entry_r_reg[1] (\bank_cntrl[0].bank0_n_36 ),
        .\q_entry_r_reg[1]_0 (\bank_cntrl[0].bank0_n_37 ),
        .\q_entry_r_reg[1]_1 (\bank_cntrl[0].bank0_n_39 ),
        .\q_entry_r_reg[1]_2 (\bank_cntrl[0].bank0_n_40 ),
        .\q_entry_r_reg[1]_3 (\bank_cntrl[2].bank0_n_35 ),
        .\ras_timer_r_reg[0] (\bank_cntrl[0].bank0_n_28 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[0].bank0_n_43 ),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[0].bank0_n_29 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[3].bank0_n_42 ),
        .ras_timer_zero_r_reg(\bank_cntrl[0].bank0_n_25 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\bank_cntrl[1].bank0_n_22 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (rb_hit_busies_r[5:4]),
        .rd_this_rank_r(rd_this_rank_r[0]),
        .rd_wr_r_lcl_reg(\bank_cntrl[1].bank0_n_30 ),
        .rd_wr_r_lcl_reg_0(arb_mux0_n_42),
        .rd_wr_r_lcl_reg_1(arb_mux0_n_17),
        .req_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_19 ),
        .req_wr_r_lcl_reg_0(\bank_cntrl[3].bank0_n_52 ),
        .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ),
        .\rnk_config_strobe_r_reg[0] (\bank_cntrl[0].bank0_n_33 ),
        .\rnk_config_strobe_r_reg[0]_0 (arb_mux0_n_16),
        .rnk_config_valid_r_lcl_reg(arb_mux0_n_22),
        .row(row),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_2),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[0]),
        .\wtr_timer.wtr_cnt_r_reg[1] (arb_mux0_n_14));
  mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized0 \bank_cntrl[1].bank0 
       (.CLK(CLK),
        .Q({sending_col[3],sending_col[1:0]}),
        .accept_r_reg(bank_common0_n_26),
        .act_this_rank_r(act_this_rank_r[1]),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_en_r2_reg(bank_common0_n_8),
        .app_rdy_r_reg(app_rdy_r_reg),
        .auto_pre_r(auto_pre_r_2),
        .auto_pre_r_lcl_reg(wait_for_maint_r_0),
        .auto_pre_r_lcl_reg_0(\bank_cntrl[0].bank0_n_45 ),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_reg(\bank_cntrl[0].bank0_n_29 ),
        .bm_end_r1_reg_0(\bank_cntrl[3].bank0_n_46 ),
        .bm_end_r1_reg_1(\bank_cntrl[2].bank0_n_31 ),
        .clear_req(\bank_queue0/clear_req_3 ),
        .clear_req_1(\bank_queue0/clear_req ),
        .\cmd_pipe_plus.mc_address_reg[13] ({\cmd_pipe_plus.mc_address_reg[13]_0 ,p_112_out}),
        .\cmd_pipe_plus.mc_address_reg[23] (\bank_compare0/req_col_r_1 ),
        .\cmd_pipe_plus.mc_address_reg[38] (\bank_cntrl[1].bank0_n_60 ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .col_wait_r(\bank_state0/col_wait_r ),
        .\compute_tail.tail_r_lcl_reg (\bank_cntrl[1].bank0_n_20 ),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (p_84_out),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r_8 ),
        .demand_act_priority_r_2(\bank_state0/demand_act_priority_r_25 ),
        .demand_act_priority_r_reg(arb_mux0_n_37),
        .demand_act_priority_r_reg_0(arb_mux0_n_103),
        .demand_priority_r(\bank_state0/demand_priority_r_7 ),
        .demand_priority_r_0(\bank_state0/demand_priority_r_24 ),
        .demand_priority_r_reg(\bank_cntrl[1].bank0_n_19 ),
        .demand_priority_r_reg_0(demand_priority_r_reg_1),
        .demand_priority_r_reg_1(\bank_cntrl[3].bank0_n_63 ),
        .demanded_prior_r(\bank_state0/demanded_prior_r_6 ),
        .demanded_prior_r_3(\bank_state0/demanded_prior_r_23 ),
        .demanded_prior_r_reg(\bank_cntrl[0].bank0_n_61 ),
        .\grant_r_reg[1] (\bank_cntrl[1].bank0_n_18 ),
        .\grant_r_reg[1]_0 (\bank_cntrl[1].bank0_n_25 ),
        .\grant_r_reg[1]_1 (\bank_cntrl[1].bank0_n_31 ),
        .\grant_r_reg[1]_2 (\bank_cntrl[1].bank0_n_42 ),
        .\grant_r_reg[1]_3 (\bank_cntrl[1].bank0_n_44 ),
        .\grant_r_reg[1]_4 (sending_pre[1:0]),
        .\grant_r_reg[1]_5 (\bank_cntrl[3].bank0_n_55 ),
        .\grant_r_reg[2] (\bank_cntrl[1].bank0_n_39 ),
        .\grant_r_reg[2]_0 (\bank_cntrl[1].bank0_n_43 ),
        .\grant_r_reg[2]_1 (\bank_cntrl[1].bank0_n_59 ),
        .\grant_r_reg[2]_2 (arb_mux0_n_7),
        .\grant_r_reg[2]_3 (\bank_cntrl[2].bank0_n_27 ),
        .\grant_r_reg[2]_4 (arb_mux0_n_38),
        .\grant_r_reg[3] (\bank_cntrl[1].bank0_n_28 ),
        .\grant_r_reg[3]_0 ({sending_row[3],sending_row[1]}),
        .\grant_r_reg[3]_1 (\bank_cntrl[3].bank0_n_26 ),
        .granted_col_r_reg(\bank_cntrl[1].bank0_n_27 ),
        .granted_col_r_reg_0(\cmd_pipe_plus.mc_cmd_reg[0] ),
        .granted_pre_ns(granted_pre_ns),
        .granted_row_ns(granted_row_ns),
        .granted_row_r_reg(\bank_cntrl[1].bank0_n_41 ),
        .head_r_lcl_reg(\bank_cntrl[1].bank0_n_21 ),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(bank_common0_n_31),
        .idle_r_lcl_reg_0(demand_priority_r_reg_0),
        .idle_r_lcl_reg_1(demand_priority_r_reg),
        .idle_r_lcl_reg_2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .idle_r_lcl_reg_3(\bank_cntrl[0].bank0_n_42 ),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .\last_master_r_reg[0] (arb_mux0_n_51),
        .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_1 ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_5 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0 ),
        .ordered_r_lcl_reg(\bank_cntrl[2].bank0_n_33 ),
        .ordered_r_lcl_reg_0(\bank_cntrl[2].bank0_n_32 ),
        .override_demand_r(\bank_state0/override_demand_r ),
        .p_103_out(p_103_out),
        .p_106_out(p_106_out),
        .p_110_out(p_110_out),
        .p_115_out(p_115_out),
        .p_129_out(p_129_out),
        .p_12_out(p_12_out),
        .p_130_out(p_130_out),
        .p_131_out(p_131_out),
        .p_132_out(p_132_out),
        .p_145_out(p_145_out),
        .p_154_out(p_154_out),
        .p_28_out(p_28_out),
        .p_51_out(p_51_out),
        .p_67_out(p_67_out),
        .p_7_in(p_7_in),
        .p_87_out(p_87_out),
        .p_89_out(p_89_out),
        .p_90_out(p_90_out),
        .p_91_out(p_91_out),
        .p_92_out(p_92_out),
        .periodic_rd_ack_r_lcl_reg(bank_common0_n_16),
        .periodic_rd_ack_r_lcl_reg_0(bank_common0_n_28),
        .periodic_rd_ack_r_lcl_reg_1(\maint_controller.maint_hit_busies_r_reg[1] ),
        .periodic_rd_ack_r_lcl_reg_2(bank_common0_n_23),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r_reg(\bank_cntrl[3].bank0_n_20 ),
        .pre_bm_end_r_reg_0(\bank_cntrl[2].bank0_n_17 ),
        .pre_passing_open_bank_r_reg(\bank_cntrl[2].bank0_n_38 ),
        .pre_passing_open_bank_r_reg_0(\bank_cntrl[0].bank0_n_43 ),
        .pre_passing_open_bank_r_reg_1(\bank_cntrl[3].bank0_n_53 ),
        .q_entry_ns(\bank_queue0/q_entry_ns ),
        .\q_entry_r_reg[0] (\bank_cntrl[1].bank0_n_22 ),
        .\q_entry_r_reg[0]_0 (\bank_cntrl[1].bank0_n_23 ),
        .\q_entry_r_reg[1] (\bank_cntrl[1].bank0_n_36 ),
        .\ras_timer_r_reg[0] (\bank_cntrl[1].bank0_n_30 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[1].bank0_n_33 ),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[1].bank0_n_29 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[3].bank0_n_42 ),
        .ras_timer_zero_r_reg(\bank_cntrl[1].bank0_n_26 ),
        .ras_timer_zero_r_reg_0(\bank_cntrl[3].bank0_n_57 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (rb_hit_busies_r_20[5]),
        .rb_hit_busy_r_reg(\bank_cntrl[0].bank0_n_20 ),
        .rb_hit_busy_r_reg_0(\bank_cntrl[0].bank0_n_23 ),
        .rd_this_rank_r(rd_this_rank_r[1]),
        .rd_wr_r_lcl_reg(\bank_cntrl[0].bank0_n_28 ),
        .req_bank_rdy_r_reg(\bank_cntrl[1].bank0_n_37 ),
        .\req_row_r_lcl_reg[10] (p_151_out[10]),
        .req_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_19 ),
        .\rnk_config_strobe_r_reg[0] (arb_mux0_n_16),
        .row(row),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(bank_common0_n_7),
        .rstdiv0_sync_r1_reg_rep__19_0(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_1),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r_4),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg_0),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[1]));
  mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized1 \bank_cntrl[2].bank0 
       (.CLK(CLK),
        .Q(rb_hit_busies_r),
        .accept_ns(accept_ns),
        .accept_r_reg(bank_common0_n_26),
        .act_this_rank_r(act_this_rank_r[2]),
        .act_wait_r_lcl_reg(\bank_cntrl[2].bank0_n_17 ),
        .act_wait_r_lcl_reg_0(\bank_cntrl[3].bank0_n_28 ),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22]_0 ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_en_r2_reg(bank_common0_n_10),
        .app_rdy_r_reg(app_rdy_r_reg),
        .auto_pre_r(auto_pre_r_12),
        .auto_pre_r_lcl_reg(wait_for_maint_r_1),
        .bm_end_r1_reg(\bank_cntrl[1].bank0_n_29 ),
        .bm_end_r1_reg_0(\bank_cntrl[0].bank0_n_29 ),
        .bm_end_r1_reg_1(\bank_cntrl[3].bank0_n_46 ),
        .clear_req(\bank_queue0/clear_req_3 ),
        .clear_req_3(\bank_queue0/clear_req ),
        .\cmd_pipe_plus.mc_address_reg[23] (\bank_compare0/req_col_r_9 ),
        .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[41] [35]),
        .\cmd_pipe_plus.mc_address_reg[41] ({\cmd_pipe_plus.mc_address_reg[41]_0 ,p_73_out}),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8]_1 ),
        .\compute_tail.tail_r_lcl_reg (\bank_cntrl[2].bank0_n_37 ),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (p_45_out),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r_17 ),
        .demand_priority_r(\bank_state0/demand_priority_r_16 ),
        .demand_priority_r_2(\bank_state0/demand_priority_r ),
        .demanded_prior_r(\bank_state0/demanded_prior_r_15 ),
        .demanded_prior_r_4(\bank_state0/demanded_prior_r ),
        .demanded_prior_r_reg(\bank_cntrl[0].bank0_n_27 ),
        .demanded_prior_r_reg_0(\bank_cntrl[3].bank0_n_62 ),
        .\grant_r_reg[0] (\bank_cntrl[2].bank0_n_18 ),
        .\grant_r_reg[0]_0 (\bank_cntrl[2].bank0_n_28 ),
        .\grant_r_reg[1] (\bank_cntrl[2].bank0_n_29 ),
        .\grant_r_reg[1]_0 (arb_mux0_n_13),
        .\grant_r_reg[2] (\bank_cntrl[2].bank0_n_34 ),
        .\grant_r_reg[2]_0 (\bank_cntrl[2].bank0_n_40 ),
        .\grant_r_reg[2]_1 (\bank_cntrl[2].bank0_n_55 ),
        .\grant_r_reg[2]_2 (sending_row[2]),
        .\grant_r_reg[2]_3 (arb_mux0_n_7),
        .\grant_r_reg[3] ({sending_col[3:2],sending_col[0]}),
        .\grant_r_reg[3]_0 (\bank_cntrl[3].bank0_n_26 ),
        .\grant_r_reg[3]_1 (sending_pre[3:2]),
        .granted_col_r_reg(\cmd_pipe_plus.mc_cmd_reg[0] ),
        .head_r_lcl_reg(\bank_cntrl[2].bank0_n_20 ),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(bank_common0_n_31),
        .idle_r_lcl_reg_0(bank_common0_n_17),
        .idle_r_lcl_reg_1(demand_priority_r_reg),
        .idle_r_lcl_reg_2(demand_priority_r_reg_0),
        .idle_r_lcl_reg_3(demand_priority_r_reg_1),
        .idle_r_lcl_reg_4(\bank_cntrl[1].bank0_n_23 ),
        .idle_r_lcl_reg_5(\bank_cntrl[0].bank0_n_36 ),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_1 ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .of_ctl_full_v(of_ctl_full_v),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_14 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_11 ),
        .ofs_rdy_r0_0(\bank_state0/ofs_rdy_r0_10 ),
        .ofs_rdy_r0_1(\bank_state0/ofs_rdy_r0 ),
        .order_q_r(\bank_queue0/order_q_r ),
        .\order_q_r_reg[0] (\bank_cntrl[2].bank0_n_32 ),
        .\order_q_r_reg[0]_0 (\bank_cntrl[2].bank0_n_61 ),
        .\order_q_r_reg[1] (\bank_cntrl[2].bank0_n_33 ),
        .\order_q_r_reg[1]_0 (\bank_cntrl[2].bank0_n_60 ),
        .override_demand_ns(\bank_state0/override_demand_ns ),
        .override_demand_r(\bank_state0/override_demand_r ),
        .p_103_out(p_103_out),
        .p_106_out(p_106_out),
        .p_130_out(p_130_out),
        .p_131_out(p_131_out),
        .p_142_out(p_142_out),
        .p_145_out(p_145_out),
        .p_14_out(p_14_out),
        .p_15_out(p_15_out),
        .p_25_out(p_25_out),
        .p_28_out(p_28_out),
        .p_48_out(p_48_out),
        .p_50_out(p_50_out),
        .p_51_out(p_51_out),
        .p_53_out(p_53_out),
        .p_67_out(p_67_out),
        .p_71_out(p_71_out),
        .p_76_out(p_76_out),
        .p_91_out(p_91_out),
        .p_92_out(p_92_out),
        .pass_open_bank_r_lcl_reg(\bank_cntrl[2].bank0_n_27 ),
        .periodic_rd_ack_ns(periodic_rd_ack_ns),
        .periodic_rd_ack_r_lcl_reg(bank_common0_n_16),
        .periodic_rd_ack_r_lcl_reg_0(\maint_controller.maint_hit_busies_r_reg[2] ),
        .periodic_rd_ack_r_lcl_reg_1(bank_common0_n_24),
        .periodic_rd_insert(periodic_rd_insert),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .pre_bm_end_r_reg(\bank_cntrl[3].bank0_n_20 ),
        .pre_passing_open_bank_r_reg(\bank_cntrl[3].bank0_n_53 ),
        .pre_passing_open_bank_r_reg_0(\bank_cntrl[1].bank0_n_33 ),
        .pre_passing_open_bank_r_reg_1(\bank_cntrl[0].bank0_n_43 ),
        .\q_entry_r_reg[1] (\bank_cntrl[2].bank0_n_35 ),
        .\q_entry_r_reg[1]_0 (\bank_cntrl[0].bank0_n_39 ),
        .\ras_timer_r_reg[0] (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[2].bank0_n_38 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[2].bank0_n_31 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[3].bank0_n_42 ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(\bank_cntrl[2].bank0_n_24 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\bank_cntrl[0].bank0_n_21 ),
        .rb_hit_busy_r_reg(\bank_cntrl[0].bank0_n_23 ),
        .rb_hit_busy_r_reg_0(\bank_cntrl[0].bank0_n_20 ),
        .rd_this_rank_r(rd_this_rank_r[2]),
        .rd_wr_r_lcl_reg(\bank_cntrl[1].bank0_n_37 ),
        .rd_wr_r_lcl_reg_0(\bank_cntrl[1].bank0_n_30 ),
        .rd_wr_r_lcl_reg_1(\bank_cntrl[0].bank0_n_28 ),
        .req_bank_rdy_r_reg(\bank_cntrl[2].bank0_n_19 ),
        .\req_row_r_lcl_reg[10] (\bank_cntrl[1].bank0_n_60 ),
        .req_wr_r_lcl_reg(\bank_cntrl[1].bank0_n_21 ),
        .req_wr_r_lcl_reg_0(bank_common0_n_21),
        .\rnk_config_strobe_r_reg[0] (arb_mux0_n_23),
        .\rnk_config_strobe_r_reg[0]_0 (arb_mux0_n_16),
        .row(row),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(bank_common0_n_9),
        .rstdiv0_sync_r1_reg_rep__19_0(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_3),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r_13),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg_1),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[2]),
        .\wtr_timer.wtr_cnt_r_reg[1] (arb_mux0_n_14));
  mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized2 \bank_cntrl[3].bank0 
       (.CLK(CLK),
        .Q({sending_col[3],sending_col[1]}),
        .accept_r_reg(bank_common0_n_26),
        .act_this_rank_r(act_this_rank_r[3]),
        .act_wait_r_lcl_reg(\bank_cntrl[3].bank0_n_20 ),
        .act_wait_r_lcl_reg_0(\bank_cntrl[2].bank0_n_24 ),
        .act_wait_r_lcl_reg_1(\bank_cntrl[0].bank0_n_25 ),
        .act_wait_r_lcl_reg_2(\bank_cntrl[1].bank0_n_26 ),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22]_1 ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_en_r2_reg(bank_common0_n_12),
        .app_rdy_r_reg(app_rdy_r_reg),
        .auto_pre_r(auto_pre_r_19),
        .auto_pre_r_lcl_reg(wait_for_maint_r_2),
        .auto_pre_r_lcl_reg_0(\bank_cntrl[2].bank0_n_40 ),
        .bm_end_r1_reg(\bank_cntrl[2].bank0_n_31 ),
        .bm_end_r1_reg_0(\bank_cntrl[1].bank0_n_29 ),
        .bm_end_r1_reg_1(\bank_cntrl[0].bank0_n_29 ),
        .clear_req(\bank_queue0/clear_req_3 ),
        .clear_req_1(\bank_queue0/clear_req ),
        .\cmd_pipe_plus.mc_address_reg[10] (\bank_cntrl[3].bank0_n_60 ),
        .\cmd_pipe_plus.mc_address_reg[23] (\bank_compare0/req_col_r_18 ),
        .\cmd_pipe_plus.mc_address_reg[38] (\bank_cntrl[3].bank0_n_28 ),
        .\cmd_pipe_plus.mc_address_reg[41] ({\cmd_pipe_plus.mc_address_reg[41]_1 ,p_34_out[11],p_34_out[9:0]}),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8]_0 ),
        .col_wait_r(\bank_state0/col_wait_r_26 ),
        .col_wait_r_reg(\bank_cntrl[2].bank0_n_34 ),
        .\compute_tail.tail_r_lcl_reg (\bank_cntrl[3].bank0_n_51 ),
        .cs_en2(cs_en2),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] (p_6_out),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r_25 ),
        .demand_priority_r(\bank_state0/demand_priority_r_24 ),
        .demand_priority_r_0(\bank_state0/demand_priority_r_7 ),
        .demand_priority_r_reg(\bank_cntrl[3].bank0_n_23 ),
        .demand_priority_r_reg_0(demand_priority_r_reg),
        .demand_priority_r_reg_1(\bank_cntrl[1].bank0_n_59 ),
        .demanded_prior_r(\bank_state0/demanded_prior_r_23 ),
        .demanded_prior_r_2(\bank_state0/demanded_prior_r_6 ),
        .demanded_prior_r_reg(\bank_cntrl[3].bank0_n_62 ),
        .demanded_prior_r_reg_0(\bank_cntrl[1].bank0_n_28 ),
        .demanded_prior_r_reg_1(\bank_cntrl[0].bank0_n_61 ),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r),
        .\grant_r_reg[0] (\bank_cntrl[3].bank0_n_58 ),
        .\grant_r_reg[1] (\bank_cntrl[3].bank0_n_27 ),
        .\grant_r_reg[1]_0 (\bank_cntrl[3].bank0_n_55 ),
        .\grant_r_reg[1]_1 (\bank_cntrl[3].bank0_n_56 ),
        .\grant_r_reg[1]_2 (\bank_cntrl[3].bank0_n_63 ),
        .\grant_r_reg[1]_3 (\bank_cntrl[1].bank0_n_27 ),
        .\grant_r_reg[2] (\bank_cntrl[3].bank0_n_59 ),
        .\grant_r_reg[2]_0 (\bank_cntrl[2].bank0_n_27 ),
        .\grant_r_reg[3] (\bank_cntrl[3].bank0_n_25 ),
        .\grant_r_reg[3]_0 (\bank_cntrl[3].bank0_n_61 ),
        .\grant_r_reg[3]_1 ({sending_row[3],sending_row[1:0]}),
        .\grant_r_reg[3]_2 (sending_pre[3]),
        .\grant_r_reg[3]_3 (arb_mux0_n_105),
        .granted_col_r_reg(\bank_cntrl[3].bank0_n_21 ),
        .granted_col_r_reg_0(\cmd_pipe_plus.mc_cmd_reg[0] ),
        .head_r_lcl_reg(\bank_cntrl[3].bank0_n_50 ),
        .head_r_lcl_reg_0(\bank_cntrl[3].bank0_n_52 ),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(bank_common0_n_31),
        .idle_r_lcl_reg_0(bank_common0_n_14),
        .idle_r_lcl_reg_1(\bank_cntrl[0].bank0_n_37 ),
        .idle_r_lcl_reg_2(\bank_cntrl[0].bank0_n_40 ),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .\last_master_r_reg[2] (arb_mux0_n_50),
        .\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_1 ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_22 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_10 ),
        .order_q_r(\bank_queue0/order_q_r ),
        .\order_q_r_reg[0] (\bank_cntrl[2].bank0_n_60 ),
        .\order_q_r_reg[0]_0 (\bank_cntrl[2].bank0_n_61 ),
        .override_demand_r(\bank_state0/override_demand_r ),
        .p_106_out(p_106_out),
        .p_115_out(p_115_out),
        .p_11_out(p_11_out),
        .p_126_out(p_126_out),
        .p_12_out(p_12_out),
        .p_130_out(p_130_out),
        .p_145_out(p_145_out),
        .p_14_out(p_14_out),
        .p_15_out(p_15_out),
        .p_25_out(p_25_out),
        .p_28_out(p_28_out),
        .p_32_out(p_32_out),
        .p_37_out(p_37_out),
        .p_48_out(p_48_out),
        .p_67_out(p_67_out),
        .p_87_out(p_87_out),
        .p_91_out(p_91_out),
        .p_9_out(p_9_out),
        .pass_open_bank_r_lcl_reg(\bank_cntrl[3].bank0_n_26 ),
        .periodic_rd_ack_r_lcl_reg(bank_common0_n_16),
        .periodic_rd_ack_r_lcl_reg_0(\maint_controller.maint_hit_busies_r_reg[3] ),
        .periodic_rd_ack_r_lcl_reg_1(bank_common0_n_25),
        .periodic_rd_insert(periodic_rd_insert),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[3].bank0_n_57 ),
        .pre_bm_end_r_reg(\bank_cntrl[0].bank0_n_24 ),
        .pre_bm_end_r_reg_0(\bank_cntrl[2].bank0_n_17 ),
        .pre_passing_open_bank_r_reg(\bank_cntrl[1].bank0_n_33 ),
        .pre_passing_open_bank_r_reg_0(\bank_cntrl[0].bank0_n_43 ),
        .pre_passing_open_bank_r_reg_1(\bank_cntrl[2].bank0_n_38 ),
        .q_entry_ns(\bank_queue0/q_entry_ns_0 ),
        .\q_entry_r_reg[0] (q_entry_r),
        .\ras_timer_r_reg[0] (\bank_cntrl[3].bank0_n_42 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[3].bank0_n_53 ),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[3].bank0_n_46 ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_0(\bank_cntrl[3].bank0_n_22 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (rb_hit_busies_r[3]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\bank_cntrl[0].bank0_n_19 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (rb_hit_busies_r_20),
        .rb_hit_busy_r_reg(\bank_cntrl[0].bank0_n_23 ),
        .rd_this_rank_r(rd_this_rank_r[3]),
        .rd_wr_r_lcl_reg(\bank_cntrl[0].bank0_n_28 ),
        .rd_wr_r_lcl_reg_0(\bank_cntrl[1].bank0_n_30 ),
        .\req_row_r_lcl_reg[10] (p_112_out[10]),
        .req_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_19 ),
        .\rnk_config_strobe_r_reg[0] (\bank_cntrl[3].bank0_n_48 ),
        .\rnk_config_strobe_r_reg[0]_0 (\bank_cntrl[3].bank0_n_49 ),
        .\rnk_config_strobe_r_reg[0]_1 (arb_mux0_n_24),
        .\rnk_config_strobe_r_reg[0]_2 (arb_mux0_n_16),
        .row(row),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__19(bank_common0_n_11),
        .rstdiv0_sync_r1_reg_rep__19_0(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_4),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .tail_r(tail_r_21),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg_2),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[3]));
  mig_7series_0_mig_7series_v2_3_bank_common bank_common0
       (.CLK(CLK),
        .E(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .accept_ns(accept_ns),
        .app_en_r2(app_en_r2),
        .app_rdy_r_reg(app_rdy_r_reg),
        .auto_pre_r_lcl_reg(bank_common0_n_26),
        .clear_req(\bank_queue0/clear_req_3 ),
        .clear_req_2(\bank_queue0/clear_req ),
        .\compute_tail.tail_r_lcl_reg (bank_common0_n_7),
        .\compute_tail.tail_r_lcl_reg_0 (bank_common0_n_8),
        .\compute_tail.tail_r_lcl_reg_1 (bank_common0_n_9),
        .\compute_tail.tail_r_lcl_reg_2 (bank_common0_n_10),
        .\compute_tail.tail_r_lcl_reg_3 (bank_common0_n_11),
        .\compute_tail.tail_r_lcl_reg_4 (bank_common0_n_12),
        .\grant_r_reg[2] (\bank_cntrl[2].bank0_n_27 ),
        .\grant_r_reg[3] (\bank_cntrl[3].bank0_n_26 ),
        .head_r_lcl_reg(bank_common0_n_14),
        .head_r_lcl_reg_0(bank_common0_n_17),
        .head_r_lcl_reg_1(bank_common0_n_18),
        .head_r_lcl_reg_2(bank_common0_n_28),
        .head_r_lcl_reg_3(bank_common0_n_31),
        .hi_priority(hi_priority),
        .insert_maint_r1_lcl_reg(insert_maint_r),
        .\maint_controller.maint_hit_busies_r_reg[0]_0 (\maint_controller.maint_hit_busies_r_reg[0] ),
        .\maint_controller.maint_hit_busies_r_reg[1]_0 (\maint_controller.maint_hit_busies_r_reg[1] ),
        .\maint_controller.maint_hit_busies_r_reg[2]_0 (\maint_controller.maint_hit_busies_r_reg[2] ),
        .\maint_controller.maint_hit_busies_r_reg[3]_0 (\maint_controller.maint_hit_busies_r_reg[3] ),
        .\maint_controller.maint_rdy_r1_reg_0 (maint_wip_r),
        .maint_req_r(maint_req_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .\maintenance_request.maint_sre_r_lcl_reg (\maintenance_request.maint_sre_r_lcl_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_zq_r_lcl_reg ),
        .\maintenance_request.upd_last_master_r_reg (\maintenance_request.upd_last_master_r_reg ),
        .\order_q_r_reg[0] (bank_common0_n_21),
        .p_11_out(p_11_out),
        .p_126_out(p_126_out),
        .p_128_out(p_128_out),
        .p_129_out(p_129_out),
        .p_12_out(p_12_out),
        .p_130_out(p_130_out),
        .p_15_out(p_15_out),
        .p_48_out(p_48_out),
        .p_50_out(p_50_out),
        .p_51_out(p_51_out),
        .p_7_in(p_7_in),
        .p_87_out(p_87_out),
        .p_89_out(p_89_out),
        .p_90_out(p_90_out),
        .p_91_out(p_91_out),
        .p_9_out(p_9_out),
        .pass_open_bank_r_lcl_reg(bank_common0_n_22),
        .pass_open_bank_r_lcl_reg_0(bank_common0_n_23),
        .pass_open_bank_r_lcl_reg_1(bank_common0_n_24),
        .pass_open_bank_r_lcl_reg_2(bank_common0_n_25),
        .periodic_rd_ack_ns(periodic_rd_ack_ns),
        .periodic_rd_cntr_r(periodic_rd_cntr_r),
        .periodic_rd_insert(periodic_rd_insert),
        .\periodic_read_request.periodic_rd_r_lcl_reg (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .pre_bm_end_r_reg(\bank_cntrl[2].bank0_n_37 ),
        .pre_bm_end_r_reg_0(\bank_cntrl[1].bank0_n_20 ),
        .pre_bm_end_r_reg_1(\bank_cntrl[0].bank0_n_24 ),
        .pre_bm_end_r_reg_2(\bank_cntrl[2].bank0_n_17 ),
        .pre_bm_end_r_reg_3(\bank_cntrl[3].bank0_n_20 ),
        .q_has_priority_r_reg(bank_common0_n_16),
        .q_has_rd_r_reg(bank_common0_n_27),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\bank_cntrl[0].bank0_n_22 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\bank_cntrl[2].bank0_n_20 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\bank_cntrl[3].bank0_n_50 ),
        .req_periodic_rd_r_lcl_reg(req_periodic_rd_r_lcl_reg),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__19_0(rstdiv0_sync_r1_reg_rep__19_0),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .tail_r(tail_r_4),
        .tail_r_0(tail_r_13),
        .tail_r_1(tail_r_21),
        .tail_r_3(tail_r),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .was_wr0(was_wr0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_queue" *) 
module mig_7series_0_mig_7series_v2_3_bank_queue
   (\req_data_buf_addr_r_reg[0] ,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    q_has_rd,
    auto_pre_r_lcl_reg_0,
    tail_r,
    head_r_lcl_reg_0,
    bm_end_r1_reg,
    \grant_r_reg[0] ,
    head_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_0 ,
    \ras_timer_r_reg[0] ,
    pass_open_bank_r_lcl_reg_0,
    D,
    granted_col_ns,
    granted_col_r_reg,
    demand_priority_ns,
    demand_priority_r_reg,
    demand_priority_r_reg_0,
    req_bank_rdy_ns,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[0]_0 ,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[1]_3 ,
    q_entry_ns_0,
    act_wait_ns,
    \q_entry_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_0 ,
    \grant_r_reg[1] ,
    auto_pre_r_lcl_reg_1,
    p_142_out,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__0,
    rstdiv0_sync_r1_reg_rep__19,
    app_en_r2_reg,
    pre_bm_end_r_reg_0,
    idle_r_lcl_reg_0,
    demand_priority_r_reg_1,
    \grant_r_reg[1]_0 ,
    rd_wr_r_lcl_reg,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    rnk_config_valid_r_lcl_reg,
    req_wr_r_lcl_reg,
    idle_r_lcl_reg_1,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    pre_bm_end_r_reg_1,
    p_91_out,
    pre_bm_end_r_reg_2,
    periodic_rd_ack_r_lcl_reg,
    col_wait_r,
    act_wait_r_lcl_reg,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    p_126_out,
    periodic_rd_ack_r_lcl_reg_0,
    was_priority,
    \grant_r_reg[0]_0 ,
    req_wr_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__20_0,
    rd_wr_r_lcl_reg_0,
    \ras_timer_r_reg[1] ,
    rd_wr_r_lcl_reg_1,
    \ras_timer_r_reg[0]_1 ,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    bm_end_r1_reg_2,
    bm_end_r1_reg_3,
    rd_wr_r_lcl_reg_2,
    rd_wr_r_lcl_reg_3,
    rstdiv0_sync_r1_reg_rep__19_0,
    req_priority_r,
    demand_priority_r_reg_2,
    p_90_out,
    p_51_out,
    p_12_out,
    \q_entry_r_reg[1]_4 ,
    \q_entry_r_reg[0]_2 ,
    \grant_r_reg[0]_1 ,
    act_wait_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__20_1,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    pre_passing_open_bank_r_reg_2,
    p_106_out,
    clear_req_1,
    p_67_out,
    \grant_r_reg[2] ,
    p_28_out,
    \grant_r_reg[3] ,
    periodic_rd_ack_r_lcl_reg_1,
    pre_wait_r,
    row_hit_r_reg,
    ras_timer_zero_r,
    rstdiv0_sync_r1_reg_rep__1,
    rb_hit_busy_r_reg_1,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    row_hit_r,
    ordered_r_lcl_reg_0,
    set_order_q,
    ordered_r_lcl_reg_1);
  output [0:0]\req_data_buf_addr_r_reg[0] ;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output q_has_rd;
  output auto_pre_r_lcl_reg_0;
  output tail_r;
  output head_r_lcl_reg_0;
  output bm_end_r1_reg;
  output \grant_r_reg[0] ;
  output head_r_lcl_reg_1;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output \ras_timer_r_reg[0] ;
  output pass_open_bank_r_lcl_reg_0;
  output [1:0]D;
  output granted_col_ns;
  output granted_col_r_reg;
  output demand_priority_ns;
  output demand_priority_r_reg;
  output demand_priority_r_reg_0;
  output req_bank_rdy_ns;
  output \q_entry_r_reg[1]_0 ;
  output \q_entry_r_reg[1]_1 ;
  output \q_entry_r_reg[0]_0 ;
  output \q_entry_r_reg[1]_2 ;
  output \q_entry_r_reg[1]_3 ;
  output [0:0]q_entry_ns_0;
  output act_wait_ns;
  output \q_entry_r_reg[0]_1 ;
  output \ras_timer_r_reg[0]_0 ;
  output \grant_r_reg[1] ;
  output auto_pre_r_lcl_reg_1;
  output p_142_out;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__0;
  input rstdiv0_sync_r1_reg_rep__19;
  input app_en_r2_reg;
  input pre_bm_end_r_reg_0;
  input idle_r_lcl_reg_0;
  input demand_priority_r_reg_1;
  input \grant_r_reg[1]_0 ;
  input rd_wr_r_lcl_reg;
  input \wtr_timer.wtr_cnt_r_reg[1] ;
  input rnk_config_valid_r_lcl_reg;
  input req_wr_r_lcl_reg;
  input idle_r_lcl_reg_1;
  input rb_hit_busy_r_reg;
  input rb_hit_busy_r_reg_0;
  input pre_bm_end_r_reg_1;
  input p_91_out;
  input pre_bm_end_r_reg_2;
  input periodic_rd_ack_r_lcl_reg;
  input col_wait_r;
  input act_wait_r_lcl_reg;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input p_126_out;
  input periodic_rd_ack_r_lcl_reg_0;
  input was_priority;
  input [0:0]\grant_r_reg[0]_0 ;
  input req_wr_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input rd_wr_r_lcl_reg_0;
  input \ras_timer_r_reg[1] ;
  input rd_wr_r_lcl_reg_1;
  input \ras_timer_r_reg[0]_1 ;
  input bm_end_r1_reg_0;
  input bm_end_r1_reg_1;
  input bm_end_r1_reg_2;
  input bm_end_r1_reg_3;
  input rd_wr_r_lcl_reg_2;
  input rd_wr_r_lcl_reg_3;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input req_priority_r;
  input demand_priority_r_reg_2;
  input p_90_out;
  input p_51_out;
  input p_12_out;
  input \q_entry_r_reg[1]_4 ;
  input \q_entry_r_reg[0]_2 ;
  input [0:0]\grant_r_reg[0]_1 ;
  input act_wait_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input pre_passing_open_bank_r_reg_2;
  input p_106_out;
  input clear_req_1;
  input p_67_out;
  input \grant_r_reg[2] ;
  input p_28_out;
  input \grant_r_reg[3] ;
  input periodic_rd_ack_r_lcl_reg_1;
  input pre_wait_r;
  input row_hit_r_reg;
  input ras_timer_zero_r;
  input rstdiv0_sync_r1_reg_rep__1;
  input rb_hit_busy_r_reg_1;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input row_hit_r;
  input ordered_r_lcl_reg_0;
  input set_order_q;
  input ordered_r_lcl_reg_1;

  wire CLK;
  wire [1:0]D;
  wire [0:0]E;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_4_n_0;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire app_en_r2_reg;
  wire auto_pre_r_lcl_i_1_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire bm_end_r1_reg_2;
  wire bm_end_r1_reg_3;
  wire clear_req_1;
  wire col_wait_r;
  wire \compute_tail.tail_r_lcl_i_1_n_0 ;
  wire \compute_tail.tail_r_lcl_i_2__2_n_0 ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_priority_ns;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire \grant_r[0]_i_5_n_0 ;
  wire \grant_r[0]_i_6_n_0 ;
  wire \grant_r_reg[0] ;
  wire [0:0]\grant_r_reg[0]_0 ;
  wire [0:0]\grant_r_reg[0]_1 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[3] ;
  wire granted_col_ns;
  wire granted_col_r_reg;
  wire head_r_lcl_i_1_n_0;
  wire head_r_lcl_i_3__2_n_0;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire ordered_r_lcl_i_1_n_0;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_106_out;
  wire p_126_out;
  wire p_12_out;
  wire p_142_out;
  wire p_28_out;
  wire [3:1]p_2_out;
  wire p_51_out;
  wire p_67_out;
  wire p_90_out;
  wire p_91_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_bm_end_r_reg_2;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_passing_open_bank_r_reg_2;
  wire pre_wait_r;
  wire [1:1]q_entry_ns;
  wire [0:0]q_entry_ns_0;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[0]_i_3__0_n_0 ;
  wire \q_entry_r[0]_i_4__0_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r[1]_i_3__1_n_0 ;
  wire \q_entry_r[1]_i_4__2_n_0 ;
  wire \q_entry_r[1]_i_5__1_n_0 ;
  wire [1:0]q_entry_r_0;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg[1]_3 ;
  wire \q_entry_r_reg[1]_4 ;
  wire q_has_priority;
  wire q_has_priority_r_i_1__0_n_0;
  wire q_has_rd;
  wire q_has_rd_r_i_1__0_n_0;
  wire \ras_timer_r[0]_i_2_n_0 ;
  wire \ras_timer_r[1]_i_2_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[1] ;
  wire ras_timer_zero_r;
  wire [3:1]rb_hit_busies_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire rd_wr_r_lcl_reg_3;
  wire req_bank_rdy_ns;
  wire [0:0]\req_data_buf_addr_r_reg[0] ;
  wire req_priority_r;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire rnk_config_valid_r_lcl_reg;
  wire row_hit_r;
  wire row_hit_r_reg;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire set_order_q;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire was_priority;
  wire was_wr;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;

  LUT3 #(
    .INIT(8'h0D)) 
    accept_internal_r_i_3
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(pass_open_bank_r_lcl_reg_0),
        .O(demand_priority_r_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF040404)) 
    act_wait_r_lcl_i_1
       (.I0(\grant_r_reg[0]_1 ),
        .I1(act_wait_r_lcl_reg_0),
        .I2(\ras_timer_r_reg[0] ),
        .I3(pass_open_bank_r),
        .I4(bm_end_r1_reg),
        .I5(rstdiv0_sync_r1_reg_rep__20_1),
        .O(act_wait_ns));
  LUT4 #(
    .INIT(16'h0020)) 
    act_wait_r_lcl_i_2
       (.I0(act_wait_r_lcl_i_4_n_0),
        .I1(q_entry_r_0[1]),
        .I2(q_entry_r_0[0]),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .O(\ras_timer_r_reg[0] ));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    act_wait_r_lcl_i_4
       (.I0(pre_passing_open_bank_r_reg_0),
        .I1(rb_hit_busies_r[2]),
        .I2(rb_hit_busies_r[1]),
        .I3(pre_passing_open_bank_r_reg_1),
        .I4(rb_hit_busies_r[3]),
        .I5(pre_passing_open_bank_r_reg_2),
        .O(act_wait_r_lcl_i_4_n_0));
  LUT5 #(
    .INIT(32'h55151515)) 
    act_wait_r_lcl_i_5__1
       (.I0(pre_passing_open_bank_r),
        .I1(\grant_r_reg[0]_0 ),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(req_wr_r_lcl_reg_0),
        .O(\ras_timer_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAEEEEE)) 
    auto_pre_r_lcl_i_1
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg_1),
        .I2(auto_pre_r_lcl_reg_0),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(row_hit_r),
        .I5(pass_open_bank_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1_n_0),
        .Q(auto_pre_r_lcl_reg_1),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAAEAEAEA)) 
    bm_end_r1_i_1__0
       (.I0(pre_bm_end_r),
        .I1(\grant_r_reg[0]_0 ),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(req_wr_r_lcl_reg_0),
        .O(bm_end_r1_reg));
  LUT6 #(
    .INIT(64'h3232223222222222)) 
    \compute_tail.tail_r_lcl_i_1 
       (.I0(\compute_tail.tail_r_lcl_i_2__2_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(app_en_r2_reg),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(pre_bm_end_r_reg_0),
        .I5(tail_r),
        .O(\compute_tail.tail_r_lcl_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair762" *) 
  LUT5 #(
    .INIT(32'hFFFF0080)) 
    \compute_tail.tail_r_lcl_i_2__2 
       (.I0(bm_end_r1_reg),
        .I1(pre_bm_end_r_reg_2),
        .I2(pre_bm_end_r_reg_1),
        .I3(p_91_out),
        .I4(periodic_rd_ack_r_lcl_reg),
        .O(\compute_tail.tail_r_lcl_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair762" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \compute_tail.tail_r_lcl_i_3__2 
       (.I0(bm_end_r1_reg),
        .I1(pre_bm_end_r_reg_1),
        .I2(p_91_out),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  FDRE \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_i_1_n_0 ),
        .Q(tail_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8888888800008880)) 
    demand_priority_r_i_1__2
       (.I0(rstdiv0_sync_r1_reg_rep__19_0),
        .I1(demand_priority_r_reg),
        .I2(req_priority_r),
        .I3(q_has_priority),
        .I4(demand_priority_r_reg_0),
        .I5(demand_priority_r_reg_2),
        .O(demand_priority_ns));
  (* SOFT_HLUTNM = "soft_lutpair763" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    demand_priority_r_i_2__0
       (.I0(req_wr_r_lcl_reg),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(rd_wr_r_lcl_reg),
        .O(demand_priority_r_reg_0));
  LUT6 #(
    .INIT(64'h0000008080800080)) 
    \grant_r[0]_i_2__0 
       (.I0(demand_priority_r_reg_1),
        .I1(\grant_r[0]_i_5_n_0 ),
        .I2(\grant_r[0]_i_6_n_0 ),
        .I3(\grant_r_reg[1]_0 ),
        .I4(rd_wr_r_lcl_reg),
        .I5(\wtr_timer.wtr_cnt_r_reg[1] ),
        .O(\grant_r_reg[0] ));
  LUT5 #(
    .INIT(32'h888A8A8A)) 
    \grant_r[0]_i_5 
       (.I0(rnk_config_valid_r_lcl_reg),
        .I1(rd_wr_r_lcl_reg),
        .I2(order_q_r[1]),
        .I3(order_q_r[0]),
        .I4(req_wr_r_lcl_reg),
        .O(\grant_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0400)) 
    \grant_r[0]_i_6 
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(q_entry_r_0[0]),
        .I2(q_entry_r_0[1]),
        .I3(act_wait_r_lcl_i_4_n_0),
        .I4(col_wait_r),
        .I5(act_wait_r_lcl_reg),
        .O(\grant_r[0]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF7F)) 
    \grant_r[1]_i_10 
       (.I0(head_r_lcl_reg_0),
        .I1(ras_timer_zero_r),
        .I2(act_wait_r_lcl_reg_0),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(\grant_r_reg[1] ));
  LUT2 #(
    .INIT(4'hB)) 
    \grant_r[3]_i_2__0 
       (.I0(\grant_r_reg[0] ),
        .I1(rd_wr_r_lcl_reg_3),
        .O(granted_col_r_reg));
  LUT2 #(
    .INIT(4'hB)) 
    granted_col_r_i_1
       (.I0(granted_col_r_reg),
        .I1(rd_wr_r_lcl_reg_2),
        .O(granted_col_ns));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    head_r_lcl_i_1
       (.I0(idle_r_lcl_reg_0),
        .I1(bm_end_r1_reg),
        .I2(head_r_lcl_i_3__2_n_0),
        .I3(\q_entry_r[1]_i_3__1_n_0 ),
        .I4(head_r_lcl_reg_0),
        .O(head_r_lcl_i_1_n_0));
  LUT6 #(
    .INIT(64'h20202020202F2F20)) 
    head_r_lcl_i_3__2
       (.I0(q_entry_r_0[0]),
        .I1(q_entry_r_0[1]),
        .I2(idle_r_lcl_reg_1),
        .I3(rb_hit_busy_r_reg),
        .I4(head_r_lcl_reg_1),
        .I5(rb_hit_busy_r_reg_0),
        .O(head_r_lcl_i_3__2_n_0));
  FDSE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1_n_0),
        .Q(head_r_lcl_reg_0),
        .S(rstdiv0_sync_r1_reg_rep__0));
  (* SOFT_HLUTNM = "soft_lutpair765" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__0
       (.I0(demand_priority_r_reg),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(\req_data_buf_addr_r_reg[0] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0888)) 
    \maint_controller.maint_hit_busies_r[0]_i_3 
       (.I0(\grant_r_reg[0]_0 ),
        .I1(pass_open_bank_r),
        .I2(rd_wr_r_lcl_reg),
        .I3(req_wr_r_lcl_reg_0),
        .I4(rstdiv0_sync_r1_reg_rep__20_0),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h553100305531CC30)) 
    \order_q_r[0]_i_1 
       (.I0(ordered_r_lcl_reg_1),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(set_order_q),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAC200C0AAC2F0C0)) 
    \order_q_r[1]_i_1 
       (.I0(ordered_r_lcl_reg_0),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(set_order_q),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000EAEA0AEA)) 
    ordered_r_lcl_i_1
       (.I0(p_142_out),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(req_wr_r_lcl_reg_0),
        .I3(\grant_r_reg[0]_0 ),
        .I4(rd_wr_r_lcl_reg),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(ordered_r_lcl_i_1_n_0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_i_1_n_0),
        .Q(p_142_out),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44454444)) 
    pass_open_bank_r_lcl_i_1__0
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(periodic_rd_ack_r_lcl_reg_1),
        .I3(pre_wait_r),
        .I4(row_hit_r_reg),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h82D7FFFF82D70000)) 
    \q_entry_r[0]_i_1 
       (.I0(bm_end_r1_reg),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(\q_entry_r[0]_i_3__0_n_0 ),
        .I3(\q_entry_r[0]_i_4__0_n_0 ),
        .I4(\q_entry_r[1]_i_3__1_n_0 ),
        .I5(q_entry_r_0[0]),
        .O(\q_entry_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair764" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    \q_entry_r[0]_i_2__1 
       (.I0(bm_end_r1_reg),
        .I1(p_12_out),
        .I2(p_51_out),
        .I3(p_90_out),
        .I4(\req_data_buf_addr_r_reg[0] ),
        .O(\q_entry_r_reg[0]_1 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \q_entry_r[0]_i_3__0 
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(p_90_out),
        .I2(p_51_out),
        .I3(p_12_out),
        .O(\q_entry_r[0]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'h9669)) 
    \q_entry_r[0]_i_4 
       (.I0(pre_bm_end_r_reg_1),
        .I1(bm_end_r1_reg),
        .I2(\q_entry_r[0]_i_3__0_n_0 ),
        .I3(p_91_out),
        .O(\q_entry_r_reg[0]_0 ));
  LUT4 #(
    .INIT(16'h6F60)) 
    \q_entry_r[0]_i_4__0 
       (.I0(head_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg),
        .I2(periodic_rd_ack_r_lcl_reg),
        .I3(q_entry_r_0[0]),
        .O(\q_entry_r[0]_i_4__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \q_entry_r[1]_i_1 
       (.I0(q_entry_ns),
        .I1(\q_entry_r[1]_i_3__1_n_0 ),
        .I2(q_entry_r_0[1]),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h177E7EE87EE8E881)) 
    \q_entry_r[1]_i_2 
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(p_90_out),
        .I2(p_51_out),
        .I3(p_12_out),
        .I4(bm_end_r1_reg),
        .I5(p_91_out),
        .O(\q_entry_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hC0CF909F)) 
    \q_entry_r[1]_i_2__0 
       (.I0(\q_entry_r[0]_i_3__0_n_0 ),
        .I1(\q_entry_r[1]_i_4__2_n_0 ),
        .I2(bm_end_r1_reg),
        .I3(\q_entry_r[1]_i_5__1_n_0 ),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .O(q_entry_ns));
  (* SOFT_HLUTNM = "soft_lutpair761" *) 
  LUT5 #(
    .INIT(32'h6A56A96A)) 
    \q_entry_r[1]_i_2__1 
       (.I0(\q_entry_r[1]_i_4__2_n_0 ),
        .I1(bm_end_r1_reg),
        .I2(\q_entry_r[0]_i_3__0_n_0 ),
        .I3(pre_bm_end_r_reg_1),
        .I4(p_91_out),
        .O(\q_entry_r_reg[1]_3 ));
  LUT6 #(
    .INIT(64'h7DF5F5D728A0A082)) 
    \q_entry_r[1]_i_2__2 
       (.I0(p_91_out),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(\q_entry_r[1]_i_4__2_n_0 ),
        .I3(bm_end_r1_reg),
        .I4(\q_entry_r[0]_i_3__0_n_0 ),
        .I5(\q_entry_r_reg[0]_2 ),
        .O(q_entry_ns_0));
  LUT6 #(
    .INIT(64'h55555555333C3CCC)) 
    \q_entry_r[1]_i_3__0 
       (.I0(\q_entry_r_reg[1]_4 ),
        .I1(\q_entry_r[1]_i_4__2_n_0 ),
        .I2(p_91_out),
        .I3(\q_entry_r[0]_i_3__0_n_0 ),
        .I4(bm_end_r1_reg),
        .I5(pre_bm_end_r_reg_1),
        .O(\q_entry_r_reg[1]_2 ));
  LUT5 #(
    .INIT(32'hFFFFFF1D)) 
    \q_entry_r[1]_i_3__1 
       (.I0(head_r_lcl_reg_1),
        .I1(\req_data_buf_addr_r_reg[0] ),
        .I2(periodic_rd_ack_r_lcl_reg_0),
        .I3(bm_end_r1_reg),
        .I4(periodic_rd_ack_r_lcl_reg),
        .O(\q_entry_r[1]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair764" *) 
  LUT4 #(
    .INIT(16'h7EE8)) 
    \q_entry_r[1]_i_4__2 
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(p_12_out),
        .I2(p_51_out),
        .I3(p_90_out),
        .O(\q_entry_r[1]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'h1E001EFF1EFF1E00)) 
    \q_entry_r[1]_i_5__1 
       (.I0(rb_hit_busy_r_reg),
        .I1(head_r_lcl_reg_1),
        .I2(rb_hit_busy_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg),
        .I4(q_entry_r_0[1]),
        .I5(q_entry_r_0[0]),
        .O(\q_entry_r[1]_i_5__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair761" *) 
  LUT5 #(
    .INIT(32'h366C9336)) 
    \q_entry_r[1]_i_6 
       (.I0(\q_entry_r[0]_i_3__0_n_0 ),
        .I1(\q_entry_r[1]_i_4__2_n_0 ),
        .I2(bm_end_r1_reg),
        .I3(p_91_out),
        .I4(pre_bm_end_r_reg_1),
        .O(\q_entry_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h0000DD0DDD0DDD0D)) 
    \q_entry_r[1]_i_6__0 
       (.I0(rb_hit_busies_r[2]),
        .I1(pre_bm_end_r_reg_1),
        .I2(rb_hit_busies_r[3]),
        .I3(pre_bm_end_r_reg_2),
        .I4(rb_hit_busies_r[1]),
        .I5(p_91_out),
        .O(head_r_lcl_reg_1));
  FDRE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(q_entry_r_0[0]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(q_entry_r_0[1]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT5 #(
    .INIT(32'h44544444)) 
    q_has_priority_r_i_1__0
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_priority),
        .I2(p_126_out),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .I4(was_priority),
        .O(q_has_priority_r_i_1__0_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1__0_n_0),
        .Q(q_has_priority),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4445444544455555)) 
    q_has_rd_r_i_1__0
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(\maintenance_request.maint_zq_r_lcl_reg ),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(was_wr),
        .I5(app_en_r2_reg),
        .O(q_has_rd_r_i_1__0_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1__0_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair766" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1 
       (.I0(\ras_timer_r[0]_i_2_n_0 ),
        .I1(\ras_timer_r_reg[0] ),
        .I2(rd_wr_r_lcl_reg_0),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hBBBBB8888888B888)) 
    \ras_timer_r[0]_i_2 
       (.I0(\ras_timer_r_reg[1] ),
        .I1(rb_hit_busies_r[3]),
        .I2(rb_hit_busies_r[1]),
        .I3(rd_wr_r_lcl_reg_1),
        .I4(rb_hit_busies_r[2]),
        .I5(\ras_timer_r_reg[0]_1 ),
        .O(\ras_timer_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair766" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1 
       (.I0(\ras_timer_r[1]_i_2_n_0 ),
        .I1(\ras_timer_r_reg[0] ),
        .I2(bm_end_r1_reg_0),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2 
       (.I0(bm_end_r1_reg_1),
        .I1(rb_hit_busies_r[3]),
        .I2(bm_end_r1_reg_2),
        .I3(rb_hit_busies_r[2]),
        .I4(rb_hit_busies_r[1]),
        .I5(bm_end_r1_reg_3),
        .O(\ras_timer_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair765" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1 
       (.I0(p_106_out),
        .I1(demand_priority_r_reg),
        .I2(rb_hit_busies_r[1]),
        .I3(clear_req_1),
        .O(p_2_out[1]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0 
       (.I0(p_67_out),
        .I1(demand_priority_r_reg),
        .I2(rb_hit_busies_r[2]),
        .I3(\grant_r_reg[2] ),
        .O(p_2_out[2]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0 
       (.I0(p_28_out),
        .I1(demand_priority_r_reg),
        .I2(rb_hit_busies_r[3]),
        .I3(\grant_r_reg[3] ),
        .O(p_2_out[3]));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[1]),
        .Q(rb_hit_busies_r[1]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[2]),
        .Q(rb_hit_busies_r[2]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[3]),
        .Q(rb_hit_busies_r[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair763" *) 
  LUT5 #(
    .INIT(32'h888A8A8A)) 
    req_bank_rdy_r_i_1__2
       (.I0(col_wait_r),
        .I1(rd_wr_r_lcl_reg),
        .I2(order_q_r[1]),
        .I3(order_q_r[0]),
        .I4(req_wr_r_lcl_reg),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__20));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_queue" *) 
module mig_7series_0_mig_7series_v2_3_bank_queue__parameterized0
   (\req_data_buf_addr_r_reg[0] ,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    pre_bm_end_r,
    q_has_rd,
    auto_pre_r_lcl_reg_0,
    tail_r,
    head_r_lcl_reg_0,
    bm_end_r1_reg,
    \grant_r_reg[1] ,
    demand_priority_r_reg,
    \compute_tail.tail_r_lcl_reg_0 ,
    \q_entry_r_reg[0]_0 ,
    pass_open_bank_r_lcl_reg_0,
    \grant_r_reg[1]_0 ,
    act_wait_r_lcl_reg,
    act_wait_ns,
    D,
    \grant_r_reg[1]_1 ,
    req_bank_rdy_ns,
    demand_priority_ns,
    demand_priority_r_reg_0,
    \ras_timer_r_reg[0] ,
    p_7_in,
    \q_entry_r_reg[1]_0 ,
    \grant_r_reg[1]_2 ,
    auto_pre_r_lcl_reg_1,
    p_103_out,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__19,
    rstdiv0_sync_r1_reg_rep__0,
    idle_r_lcl_reg_0,
    p_130_out,
    rd_wr_r_lcl_reg,
    req_wr_r_lcl_reg,
    \grant_r_reg[2] ,
    pre_bm_end_r_reg_0,
    p_129_out,
    p_51_out,
    p_12_out,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    app_en_r2_reg,
    p_87_out,
    periodic_rd_ack_r_lcl_reg,
    was_priority,
    Q,
    p_93_out,
    rstdiv0_sync_r1_reg_rep__20_0,
    periodic_rd_ack_r_lcl_reg_0,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    col_wait_r_reg,
    act_wait_r_lcl_reg_0,
    \grant_r_reg[1]_3 ,
    act_wait_r_lcl_reg_1,
    rstdiv0_sync_r1_reg_rep__20_1,
    bm_end_r1_reg_0,
    rd_wr_r_lcl_reg_0,
    rd_wr_r_lcl_reg_1,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[1] ,
    bm_end_r1_reg_1,
    bm_end_r1_reg_2,
    bm_end_r1_reg_3,
    demand_priority_r_reg_1,
    \rnk_config_strobe_r_reg[0] ,
    rstdiv0_sync_r1_reg_rep__20_2,
    req_priority_r,
    demand_priority_r_reg_2,
    periodic_rd_ack_r_lcl_reg_1,
    p_67_out,
    \grant_r_reg[2]_0 ,
    p_28_out,
    \grant_r_reg[3] ,
    p_145_out,
    clear_req_1,
    init_calib_complete_reg_rep,
    idle_r_lcl_reg_1,
    idle_r_lcl_reg_2,
    idle_r_lcl_reg_3,
    periodic_rd_ack_r_lcl_reg_2,
    pre_wait_r,
    row_hit_r_reg,
    pre_bm_end_r_reg_1,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    pre_passing_open_bank_r_reg_2,
    ras_timer_zero_r,
    q_entry_ns,
    idle_r_lcl_reg_4,
    rstdiv0_sync_r1_reg_rep__1,
    rb_hit_busy_r_reg_1,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    row_hit_r,
    rstdiv0_sync_r1_reg_rep__19_0,
    ordered_r_lcl_reg_0,
    set_order_q,
    ordered_r_lcl_reg_1);
  output [0:0]\req_data_buf_addr_r_reg[0] ;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output pre_bm_end_r;
  output q_has_rd;
  output auto_pre_r_lcl_reg_0;
  output tail_r;
  output head_r_lcl_reg_0;
  output bm_end_r1_reg;
  output \grant_r_reg[1] ;
  output demand_priority_r_reg;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output \q_entry_r_reg[0]_0 ;
  output pass_open_bank_r_lcl_reg_0;
  output \grant_r_reg[1]_0 ;
  output act_wait_r_lcl_reg;
  output act_wait_ns;
  output [1:0]D;
  output \grant_r_reg[1]_1 ;
  output req_bank_rdy_ns;
  output demand_priority_ns;
  output demand_priority_r_reg_0;
  output \ras_timer_r_reg[0] ;
  output p_7_in;
  output \q_entry_r_reg[1]_0 ;
  output \grant_r_reg[1]_2 ;
  output auto_pre_r_lcl_reg_1;
  output p_103_out;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__19;
  input rstdiv0_sync_r1_reg_rep__0;
  input idle_r_lcl_reg_0;
  input p_130_out;
  input rd_wr_r_lcl_reg;
  input req_wr_r_lcl_reg;
  input \grant_r_reg[2] ;
  input pre_bm_end_r_reg_0;
  input p_129_out;
  input p_51_out;
  input p_12_out;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input app_en_r2_reg;
  input p_87_out;
  input periodic_rd_ack_r_lcl_reg;
  input was_priority;
  input [0:0]Q;
  input p_93_out;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input periodic_rd_ack_r_lcl_reg_0;
  input rb_hit_busy_r_reg;
  input rb_hit_busy_r_reg_0;
  input col_wait_r_reg;
  input act_wait_r_lcl_reg_0;
  input [0:0]\grant_r_reg[1]_3 ;
  input act_wait_r_lcl_reg_1;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input bm_end_r1_reg_0;
  input rd_wr_r_lcl_reg_0;
  input rd_wr_r_lcl_reg_1;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[1] ;
  input bm_end_r1_reg_1;
  input bm_end_r1_reg_2;
  input bm_end_r1_reg_3;
  input demand_priority_r_reg_1;
  input \rnk_config_strobe_r_reg[0] ;
  input rstdiv0_sync_r1_reg_rep__20_2;
  input req_priority_r;
  input demand_priority_r_reg_2;
  input periodic_rd_ack_r_lcl_reg_1;
  input p_67_out;
  input \grant_r_reg[2]_0 ;
  input p_28_out;
  input \grant_r_reg[3] ;
  input p_145_out;
  input clear_req_1;
  input init_calib_complete_reg_rep;
  input idle_r_lcl_reg_1;
  input idle_r_lcl_reg_2;
  input idle_r_lcl_reg_3;
  input periodic_rd_ack_r_lcl_reg_2;
  input pre_wait_r;
  input row_hit_r_reg;
  input pre_bm_end_r_reg_1;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input pre_passing_open_bank_r_reg_2;
  input ras_timer_zero_r;
  input [0:0]q_entry_ns;
  input idle_r_lcl_reg_4;
  input rstdiv0_sync_r1_reg_rep__1;
  input rb_hit_busy_r_reg_1;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input row_hit_r;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input ordered_r_lcl_reg_0;
  input set_order_q;
  input ordered_r_lcl_reg_1;

  wire CLK;
  wire [1:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_4__0_n_0;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire app_en_r2_reg;
  wire auto_pre_r_lcl_i_1__0_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire bm_end_r1_reg_2;
  wire bm_end_r1_reg_3;
  wire clear_req_1;
  wire col_wait_r_reg;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_priority_ns;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire [0:0]\grant_r_reg[1]_3 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[3] ;
  wire head_r_lcl_i_1__0_n_0;
  wire head_r_lcl_i_2__2_n_0;
  wire head_r_lcl_i_3_n_0;
  wire head_r_lcl_reg_0;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire init_calib_complete_reg_rep;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1__0_n_0 ;
  wire \order_q_r[1]_i_1__0_n_0 ;
  wire ordered_r_lcl_i_1__0_n_0;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_103_out;
  wire p_129_out;
  wire p_12_out;
  wire p_130_out;
  wire p_145_out;
  wire p_28_out;
  wire [4:2]p_2_out;
  wire p_51_out;
  wire p_67_out;
  wire p_7_in;
  wire p_87_out;
  wire p_93_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_ack_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_passing_open_bank_r_reg_2;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire [1:0]q_entry_r;
  wire \q_entry_r[0]_i_1__0_n_0 ;
  wire \q_entry_r[0]_i_3_n_0 ;
  wire \q_entry_r[1]_i_1__0_n_0 ;
  wire \q_entry_r[1]_i_3__2_n_0 ;
  wire \q_entry_r[1]_i_5__2_n_0 ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[1]_0 ;
  wire q_has_priority;
  wire q_has_priority_r_i_1_n_0;
  wire q_has_rd;
  wire q_has_rd_r_i_1_n_0;
  wire \ras_timer_r[0]_i_2__1_n_0 ;
  wire \ras_timer_r[1]_i_2__1_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[1] ;
  wire ras_timer_zero_r;
  wire [4:2]rb_hit_busies_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire req_bank_rdy_ns;
  wire [0:0]\req_data_buf_addr_r_reg[0] ;
  wire req_priority_r;
  wire req_wr_r_lcl_reg;
  wire \rnk_config_strobe_r_reg[0] ;
  wire row_hit_r;
  wire row_hit_r_reg;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__20_2;
  wire set_order_q;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire was_priority;
  wire was_wr;

  (* SOFT_HLUTNM = "soft_lutpair771" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    accept_internal_r_i_1
       (.I0(init_calib_complete_reg_rep),
        .I1(demand_priority_r_reg_0),
        .I2(idle_r_lcl_reg_1),
        .I3(idle_r_lcl_reg_2),
        .I4(idle_r_lcl_reg_3),
        .O(p_7_in));
  LUT3 #(
    .INIT(8'h0D)) 
    accept_internal_r_i_2
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(periodic_rd_ack_r_lcl_reg_1),
        .I2(pass_open_bank_r_lcl_reg_0),
        .O(demand_priority_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF202020)) 
    act_wait_r_lcl_i_1__2
       (.I0(act_wait_r_lcl_reg),
        .I1(\grant_r_reg[1]_3 ),
        .I2(act_wait_r_lcl_reg_1),
        .I3(pass_open_bank_r),
        .I4(bm_end_r1_reg),
        .I5(rstdiv0_sync_r1_reg_rep__20_1),
        .O(act_wait_ns));
  LUT4 #(
    .INIT(16'hFBFF)) 
    act_wait_r_lcl_i_2__2
       (.I0(q_entry_r[1]),
        .I1(q_entry_r[0]),
        .I2(\req_data_buf_addr_r_reg[0] ),
        .I3(act_wait_r_lcl_i_4__0_n_0),
        .O(act_wait_r_lcl_reg));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    act_wait_r_lcl_i_4__0
       (.I0(pre_passing_open_bank_r_reg_0),
        .I1(rb_hit_busies_r[2]),
        .I2(rb_hit_busies_r[4]),
        .I3(pre_passing_open_bank_r_reg_1),
        .I4(rb_hit_busies_r[3]),
        .I5(pre_passing_open_bank_r_reg_2),
        .O(act_wait_r_lcl_i_4__0_n_0));
  LUT5 #(
    .INIT(32'h55151515)) 
    act_wait_r_lcl_i_6
       (.I0(pre_passing_open_bank_r),
        .I1(Q),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(p_93_out),
        .O(\ras_timer_r_reg[0] ));
  LUT6 #(
    .INIT(64'h00000000AAAEEEEE)) 
    auto_pre_r_lcl_i_1__0
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg_1),
        .I2(auto_pre_r_lcl_reg_0),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(row_hit_r),
        .I5(pass_open_bank_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1__0_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1__0_n_0),
        .Q(auto_pre_r_lcl_reg_1),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAAEAEAEA)) 
    bm_end_r1_i_1
       (.I0(pre_bm_end_r),
        .I1(Q),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(p_93_out),
        .O(bm_end_r1_reg));
  LUT3 #(
    .INIT(8'h10)) 
    \compute_tail.tail_r_lcl_i_3__1 
       (.I0(bm_end_r1_reg),
        .I1(p_130_out),
        .I2(pre_bm_end_r_reg_0),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  FDRE \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r1_reg_rep__19),
        .Q(tail_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8888888800008880)) 
    demand_priority_r_i_1__1
       (.I0(rstdiv0_sync_r1_reg_rep__20_2),
        .I1(demand_priority_r_reg_0),
        .I2(req_priority_r),
        .I3(q_has_priority),
        .I4(demand_priority_r_reg),
        .I5(demand_priority_r_reg_2),
        .O(demand_priority_ns));
  (* SOFT_HLUTNM = "soft_lutpair770" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    demand_priority_r_i_2__2
       (.I0(req_wr_r_lcl_reg),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(rd_wr_r_lcl_reg),
        .O(demand_priority_r_reg));
  LUT4 #(
    .INIT(16'hFDFF)) 
    \grant_r[1]_i_2 
       (.I0(demand_priority_r_reg_1),
        .I1(\rnk_config_strobe_r_reg[0] ),
        .I2(demand_priority_r_reg),
        .I3(col_wait_r_reg),
        .O(\grant_r_reg[1]_1 ));
  LUT5 #(
    .INIT(32'hFFFF5444)) 
    \grant_r[1]_i_4__2 
       (.I0(rd_wr_r_lcl_reg),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_wr_r_lcl_reg),
        .I4(\grant_r_reg[2] ),
        .O(\grant_r_reg[1] ));
  LUT6 #(
    .INIT(64'h000000000000FFDF)) 
    \grant_r[1]_i_6__0 
       (.I0(act_wait_r_lcl_i_4__0_n_0),
        .I1(\req_data_buf_addr_r_reg[0] ),
        .I2(q_entry_r[0]),
        .I3(q_entry_r[1]),
        .I4(col_wait_r_reg),
        .I5(act_wait_r_lcl_reg_0),
        .O(\grant_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF7F)) 
    \grant_r[1]_i_7__0 
       (.I0(head_r_lcl_reg_0),
        .I1(ras_timer_zero_r),
        .I2(act_wait_r_lcl_reg_1),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(\grant_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    head_r_lcl_i_1__0
       (.I0(idle_r_lcl_reg_0),
        .I1(p_130_out),
        .I2(bm_end_r1_reg),
        .I3(head_r_lcl_i_2__2_n_0),
        .I4(\q_entry_r[1]_i_3__2_n_0 ),
        .I5(head_r_lcl_reg_0),
        .O(head_r_lcl_i_1__0_n_0));
  LUT6 #(
    .INIT(64'h4445444547457475)) 
    head_r_lcl_i_2__2
       (.I0(head_r_lcl_i_3_n_0),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(\q_entry_r[1]_i_5__2_n_0 ),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(rb_hit_busy_r_reg),
        .I5(rb_hit_busy_r_reg_0),
        .O(head_r_lcl_i_2__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair772" *) 
  LUT2 #(
    .INIT(4'hB)) 
    head_r_lcl_i_3
       (.I0(q_entry_r[1]),
        .I1(q_entry_r[0]),
        .O(head_r_lcl_i_3_n_0));
  FDRE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1__0_n_0),
        .Q(head_r_lcl_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* SOFT_HLUTNM = "soft_lutpair771" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1
       (.I0(demand_priority_r_reg_0),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(\req_data_buf_addr_r_reg[0] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0888)) 
    \maint_controller.maint_hit_busies_r[1]_i_3 
       (.I0(Q),
        .I1(pass_open_bank_r),
        .I2(rd_wr_r_lcl_reg),
        .I3(p_93_out),
        .I4(rstdiv0_sync_r1_reg_rep__20_0),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h553100305531CC30)) 
    \order_q_r[0]_i_1__0 
       (.I0(ordered_r_lcl_reg_1),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(set_order_q),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(\order_q_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAC200C0AAC2F0C0)) 
    \order_q_r[1]_i_1__0 
       (.I0(ordered_r_lcl_reg_0),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(set_order_q),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(\order_q_r[1]_i_1__0_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1__0_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1__0_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000EAEA0AEA)) 
    ordered_r_lcl_i_1__0
       (.I0(p_103_out),
        .I1(periodic_rd_ack_r_lcl_reg_1),
        .I2(p_93_out),
        .I3(Q),
        .I4(rd_wr_r_lcl_reg),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(ordered_r_lcl_i_1__0_n_0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_i_1__0_n_0),
        .Q(p_103_out),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44454444)) 
    pass_open_bank_r_lcl_i_1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(periodic_rd_ack_r_lcl_reg_2),
        .I3(pre_wait_r),
        .I4(row_hit_r_reg),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h84B7FFFF84B70000)) 
    \q_entry_r[0]_i_1__0 
       (.I0(periodic_rd_ack_r_lcl_reg),
        .I1(bm_end_r1_reg),
        .I2(idle_r_lcl_reg_4),
        .I3(\q_entry_r[0]_i_3_n_0 ),
        .I4(\q_entry_r[1]_i_3__2_n_0 ),
        .I5(q_entry_r[0]),
        .O(\q_entry_r[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair772" *) 
  LUT4 #(
    .INIT(16'h6F60)) 
    \q_entry_r[0]_i_3 
       (.I0(rb_hit_busy_r_reg),
        .I1(\q_entry_r[1]_i_5__2_n_0 ),
        .I2(periodic_rd_ack_r_lcl_reg_1),
        .I3(q_entry_r[0]),
        .O(\q_entry_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    \q_entry_r[0]_i_3__2 
       (.I0(bm_end_r1_reg),
        .I1(p_129_out),
        .I2(\req_data_buf_addr_r_reg[0] ),
        .I3(p_51_out),
        .I4(p_12_out),
        .I5(p_130_out),
        .O(\q_entry_r_reg[0]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \q_entry_r[1]_i_1__0 
       (.I0(q_entry_ns),
        .I1(\q_entry_r[1]_i_3__2_n_0 ),
        .I2(q_entry_r[1]),
        .O(\q_entry_r[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF1D)) 
    \q_entry_r[1]_i_3__2 
       (.I0(\q_entry_r[1]_i_5__2_n_0 ),
        .I1(\req_data_buf_addr_r_reg[0] ),
        .I2(periodic_rd_ack_r_lcl_reg),
        .I3(periodic_rd_ack_r_lcl_reg_1),
        .I4(bm_end_r1_reg),
        .O(\q_entry_r[1]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hA9FFA900A900A9FF)) 
    \q_entry_r[1]_i_4__1 
       (.I0(rb_hit_busy_r_reg_0),
        .I1(\q_entry_r[1]_i_5__2_n_0 ),
        .I2(rb_hit_busy_r_reg),
        .I3(periodic_rd_ack_r_lcl_reg_1),
        .I4(q_entry_r[0]),
        .I5(q_entry_r[1]),
        .O(\q_entry_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h7707770700007707)) 
    \q_entry_r[1]_i_5__2 
       (.I0(p_130_out),
        .I1(rb_hit_busies_r[4]),
        .I2(rb_hit_busies_r[3]),
        .I3(pre_bm_end_r_reg_0),
        .I4(rb_hit_busies_r[2]),
        .I5(pre_bm_end_r_reg_1),
        .O(\q_entry_r[1]_i_5__2_n_0 ));
  FDSE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1__0_n_0 ),
        .Q(q_entry_r[0]),
        .S(rstdiv0_sync_r1_reg_rep__0));
  FDRE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1__0_n_0 ),
        .Q(q_entry_r[1]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT5 #(
    .INIT(32'h44544444)) 
    q_has_priority_r_i_1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_priority),
        .I2(p_87_out),
        .I3(periodic_rd_ack_r_lcl_reg),
        .I4(was_priority),
        .O(q_has_priority_r_i_1_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1_n_0),
        .Q(q_has_priority),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4445444544455555)) 
    q_has_rd_r_i_1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(\maintenance_request.maint_zq_r_lcl_reg ),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(was_wr),
        .I5(app_en_r2_reg),
        .O(q_has_rd_r_i_1_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair773" *) 
  LUT3 #(
    .INIT(8'hE4)) 
    \ras_timer_r[0]_i_1__2 
       (.I0(act_wait_r_lcl_reg),
        .I1(\ras_timer_r[0]_i_2__1_n_0 ),
        .I2(rd_wr_r_lcl_reg_0),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[0]_i_2__1 
       (.I0(rd_wr_r_lcl_reg_1),
        .I1(rb_hit_busies_r[4]),
        .I2(rb_hit_busies_r[2]),
        .I3(\ras_timer_r_reg[0]_0 ),
        .I4(\ras_timer_r_reg[1] ),
        .I5(rb_hit_busies_r[3]),
        .O(\ras_timer_r[0]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair773" *) 
  LUT3 #(
    .INIT(8'hE4)) 
    \ras_timer_r[1]_i_1__2 
       (.I0(act_wait_r_lcl_reg),
        .I1(\ras_timer_r[1]_i_2__1_n_0 ),
        .I2(bm_end_r1_reg_0),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2__1 
       (.I0(bm_end_r1_reg_1),
        .I1(rb_hit_busies_r[4]),
        .I2(bm_end_r1_reg_2),
        .I3(rb_hit_busies_r[3]),
        .I4(rb_hit_busies_r[2]),
        .I5(bm_end_r1_reg_3),
        .O(\ras_timer_r[1]_i_2__1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1 
       (.I0(p_67_out),
        .I1(demand_priority_r_reg_0),
        .I2(rb_hit_busies_r[2]),
        .I3(\grant_r_reg[2]_0 ),
        .O(p_2_out[2]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1 
       (.I0(p_28_out),
        .I1(demand_priority_r_reg_0),
        .I2(rb_hit_busies_r[3]),
        .I3(\grant_r_reg[3] ),
        .O(p_2_out[3]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1 
       (.I0(p_145_out),
        .I1(demand_priority_r_reg_0),
        .I2(rb_hit_busies_r[4]),
        .I3(clear_req_1),
        .O(p_2_out[4]));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[2]),
        .Q(rb_hit_busies_r[2]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[3]),
        .Q(rb_hit_busies_r[3]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[4]),
        .Q(rb_hit_busies_r[4]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair770" *) 
  LUT5 #(
    .INIT(32'h888A8A8A)) 
    req_bank_rdy_r_i_1__1
       (.I0(col_wait_r_reg),
        .I1(rd_wr_r_lcl_reg),
        .I2(order_q_r[1]),
        .I3(order_q_r[0]),
        .I4(req_wr_r_lcl_reg),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__20));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_queue" *) 
module mig_7series_0_mig_7series_v2_3_bank_queue__parameterized1
   (\req_data_buf_addr_r_reg[0] ,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    pre_bm_end_r,
    q_has_rd,
    q_has_priority,
    auto_pre_r_lcl_reg_0,
    tail_r,
    head_r_lcl_reg_0,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[0]_0 ,
    act_wait_r_lcl_reg,
    head_r_lcl_reg_1,
    Q,
    \grant_r_reg[0] ,
    \ras_timer_r_reg[0] ,
    accept_ns,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    pass_open_bank_r_lcl_reg_0,
    D,
    \q_entry_r_reg[1]_0 ,
    act_wait_ns,
    periodic_rd_ack_ns,
    \compute_tail.tail_r_lcl_reg_0 ,
    \ras_timer_r_reg[0]_0 ,
    \grant_r_reg[2] ,
    auto_pre_r_lcl_reg_1,
    p_64_out,
    order_q_r_0,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__19,
    rstdiv0_sync_r1_reg_rep__0,
    ordered_r_lcl_reg_0,
    order_q_r,
    req_wr_r_lcl_reg,
    req_wr_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__19_0,
    ordered_r_lcl_reg_1,
    req_wr_r_lcl_reg_1,
    idle_r_lcl_reg_0,
    idle_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    rb_hit_busy_r_reg,
    pre_bm_end_r_reg_0,
    p_91_out,
    p_130_out,
    \rnk_config_strobe_r_reg[0] ,
    act_wait_r_lcl_reg_0,
    col_wait_r,
    idle_r_lcl_reg_2,
    idle_r_lcl_reg_3,
    idle_r_lcl_reg_4,
    init_calib_complete_reg_rep,
    periodic_rd_insert,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    app_en_r2_reg,
    p_48_out,
    periodic_rd_ack_r_lcl_reg,
    was_priority,
    \grant_r_reg[2]_0 ,
    rd_wr_r_lcl_reg,
    p_54_out,
    rstdiv0_sync_r1_reg_rep__20_0,
    \ras_timer_r_reg[0]_1 ,
    bm_end_r1_reg,
    rd_wr_r_lcl_reg_0,
    \ras_timer_r_reg[1] ,
    rd_wr_r_lcl_reg_1,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    bm_end_r1_reg_2,
    idle_r_lcl_reg_5,
    periodic_rd_ack_r_lcl_reg_0,
    rb_hit_busy_r_reg_0,
    \grant_r_reg[2]_1 ,
    act_wait_r_lcl_reg_1,
    rstdiv0_sync_r1_reg_rep__20_1,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    pre_passing_open_bank_r_reg_2,
    p_106_out,
    clear_req,
    p_145_out,
    clear_req_3,
    p_28_out,
    \grant_r_reg[3] ,
    periodic_rd_ack_r_lcl_reg_1,
    pre_wait_r,
    row_hit_r_reg,
    ras_timer_zero_r,
    idle_r_lcl_reg_6,
    \q_entry_r_reg[1]_1 ,
    rstdiv0_sync_r1_reg_rep__1,
    rb_hit_busy_r_reg_1,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    row_hit_r,
    set_order_q);
  output [0:0]\req_data_buf_addr_r_reg[0] ;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output pre_bm_end_r;
  output q_has_rd;
  output q_has_priority;
  output auto_pre_r_lcl_reg_0;
  output tail_r;
  output head_r_lcl_reg_0;
  output \order_q_r_reg[1]_0 ;
  output \order_q_r_reg[0]_0 ;
  output act_wait_r_lcl_reg;
  output head_r_lcl_reg_1;
  output [2:0]Q;
  output \grant_r_reg[0] ;
  output \ras_timer_r_reg[0] ;
  output accept_ns;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  output pass_open_bank_r_lcl_reg_0;
  output [1:0]D;
  output \q_entry_r_reg[1]_0 ;
  output act_wait_ns;
  output periodic_rd_ack_ns;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output \ras_timer_r_reg[0]_0 ;
  output \grant_r_reg[2] ;
  output auto_pre_r_lcl_reg_1;
  output p_64_out;
  output [1:0]order_q_r_0;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__19;
  input rstdiv0_sync_r1_reg_rep__0;
  input ordered_r_lcl_reg_0;
  input [1:0]order_q_r;
  input req_wr_r_lcl_reg;
  input req_wr_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input ordered_r_lcl_reg_1;
  input req_wr_r_lcl_reg_1;
  input idle_r_lcl_reg_0;
  input idle_r_lcl_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  input rb_hit_busy_r_reg;
  input pre_bm_end_r_reg_0;
  input p_91_out;
  input p_130_out;
  input \rnk_config_strobe_r_reg[0] ;
  input act_wait_r_lcl_reg_0;
  input col_wait_r;
  input idle_r_lcl_reg_2;
  input idle_r_lcl_reg_3;
  input idle_r_lcl_reg_4;
  input init_calib_complete_reg_rep;
  input periodic_rd_insert;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input app_en_r2_reg;
  input p_48_out;
  input periodic_rd_ack_r_lcl_reg;
  input was_priority;
  input [0:0]\grant_r_reg[2]_0 ;
  input rd_wr_r_lcl_reg;
  input p_54_out;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input \ras_timer_r_reg[0]_1 ;
  input bm_end_r1_reg;
  input rd_wr_r_lcl_reg_0;
  input \ras_timer_r_reg[1] ;
  input rd_wr_r_lcl_reg_1;
  input bm_end_r1_reg_0;
  input bm_end_r1_reg_1;
  input bm_end_r1_reg_2;
  input idle_r_lcl_reg_5;
  input periodic_rd_ack_r_lcl_reg_0;
  input rb_hit_busy_r_reg_0;
  input [0:0]\grant_r_reg[2]_1 ;
  input act_wait_r_lcl_reg_1;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input pre_passing_open_bank_r_reg_2;
  input p_106_out;
  input clear_req;
  input p_145_out;
  input clear_req_3;
  input p_28_out;
  input \grant_r_reg[3] ;
  input periodic_rd_ack_r_lcl_reg_1;
  input pre_wait_r;
  input row_hit_r_reg;
  input ras_timer_zero_r;
  input idle_r_lcl_reg_6;
  input \q_entry_r_reg[1]_1 ;
  input rstdiv0_sync_r1_reg_rep__1;
  input rb_hit_busy_r_reg_1;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input row_hit_r;
  input set_order_q;

  wire CLK;
  wire [1:0]D;
  wire [0:0]E;
  wire [2:0]Q;
  wire accept_ns;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_5_n_0;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire app_en_r2_reg;
  wire auto_pre_r_lcl_i_1__1_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire bm_end_r1_reg_2;
  wire clear_req;
  wire clear_req_3;
  wire col_wait_r;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \grant_r[3]_i_15_n_0 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[2] ;
  wire [0:0]\grant_r_reg[2]_0 ;
  wire [0:0]\grant_r_reg[2]_1 ;
  wire \grant_r_reg[3] ;
  wire head_r_lcl_i_1__1_n_0;
  wire head_r_lcl_i_2__1_n_0;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire idle_r_lcl_reg_5;
  wire idle_r_lcl_reg_6;
  wire init_calib_complete_reg_rep;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1__1_n_0 ;
  wire \order_q_r[1]_i_1__1_n_0 ;
  wire [1:0]order_q_r_0;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[1]_0 ;
  wire ordered_r_lcl_i_1__1_n_0;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_106_out;
  wire p_130_out;
  wire p_145_out;
  wire p_28_out;
  wire [5:3]p_2_out;
  wire p_48_out;
  wire p_54_out;
  wire p_64_out;
  wire p_91_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_ack_ns;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_insert;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_passing_open_bank_r_reg_2;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire [1:0]q_entry_r;
  wire \q_entry_r[0]_i_1__1_n_0 ;
  wire \q_entry_r[1]_i_1__1_n_0 ;
  wire \q_entry_r[1]_i_4__0_n_0 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire q_has_priority;
  wire q_has_priority_r_i_1__2_n_0;
  wire q_has_rd;
  wire q_has_rd_r_i_1__2_n_0;
  wire \ras_timer_r[0]_i_2__2_n_0 ;
  wire \ras_timer_r[1]_i_2__2_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[1] ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire [0:0]\req_data_buf_addr_r_reg[0] ;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire req_wr_r_lcl_reg_1;
  wire \rnk_config_strobe_r_reg[0] ;
  wire row_hit_r;
  wire row_hit_r_reg;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire set_order_q;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire was_priority;
  wire was_wr;

  LUT3 #(
    .INIT(8'h0D)) 
    accept_internal_r_i_5
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(pass_open_bank_r_lcl_reg_0),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF0000)) 
    accept_r_i_1
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I1(idle_r_lcl_reg_2),
        .I2(idle_r_lcl_reg_3),
        .I3(idle_r_lcl_reg_4),
        .I4(init_calib_complete_reg_rep),
        .I5(periodic_rd_insert),
        .O(accept_ns));
  LUT6 #(
    .INIT(64'hFFFFFFFF0404FF04)) 
    act_wait_r_lcl_i_1__0
       (.I0(\grant_r_reg[2]_1 ),
        .I1(act_wait_r_lcl_reg_1),
        .I2(\ras_timer_r_reg[0] ),
        .I3(pass_open_bank_r),
        .I4(act_wait_r_lcl_reg),
        .I5(rstdiv0_sync_r1_reg_rep__20_1),
        .O(act_wait_ns));
  LUT4 #(
    .INIT(16'h0020)) 
    act_wait_r_lcl_i_2__0
       (.I0(act_wait_r_lcl_i_5_n_0),
        .I1(q_entry_r[1]),
        .I2(q_entry_r[0]),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .O(\ras_timer_r_reg[0] ));
  LUT5 #(
    .INIT(32'h55151515)) 
    act_wait_r_lcl_i_3__0
       (.I0(pre_bm_end_r),
        .I1(\grant_r_reg[2]_0 ),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(p_54_out),
        .O(act_wait_r_lcl_reg));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    act_wait_r_lcl_i_5
       (.I0(pre_passing_open_bank_r_reg_0),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(pre_passing_open_bank_r_reg_1),
        .I4(Q[1]),
        .I5(pre_passing_open_bank_r_reg_2),
        .O(act_wait_r_lcl_i_5_n_0));
  LUT5 #(
    .INIT(32'h55151515)) 
    act_wait_r_lcl_i_5__2
       (.I0(pre_passing_open_bank_r),
        .I1(\grant_r_reg[2]_0 ),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(p_54_out),
        .O(\ras_timer_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAEEEEE)) 
    auto_pre_r_lcl_i_1__1
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg_1),
        .I2(auto_pre_r_lcl_reg_0),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(row_hit_r),
        .I5(pass_open_bank_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1__1_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1__1_n_0),
        .Q(auto_pre_r_lcl_reg_1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h08)) 
    \compute_tail.tail_r_lcl_i_3__0 
       (.I0(act_wait_r_lcl_reg),
        .I1(pre_bm_end_r_reg_0),
        .I2(p_130_out),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  FDRE \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r1_reg_rep__19),
        .Q(tail_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFFF7F)) 
    \grant_r[3]_i_11 
       (.I0(head_r_lcl_reg_0),
        .I1(ras_timer_zero_r),
        .I2(act_wait_r_lcl_reg_1),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(\grant_r_reg[2] ));
  LUT6 #(
    .INIT(64'hABABABABABABAAAB)) 
    \grant_r[3]_i_12 
       (.I0(\rnk_config_strobe_r_reg[0] ),
        .I1(act_wait_r_lcl_reg_0),
        .I2(col_wait_r),
        .I3(act_wait_r_lcl_i_5_n_0),
        .I4(\grant_r[3]_i_15_n_0 ),
        .I5(\req_data_buf_addr_r_reg[0] ),
        .O(\grant_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair781" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \grant_r[3]_i_15 
       (.I0(q_entry_r[1]),
        .I1(q_entry_r[0]),
        .O(\grant_r[3]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hB888FFFFB8880000)) 
    head_r_lcl_i_1__1
       (.I0(head_r_lcl_i_2__1_n_0),
        .I1(act_wait_r_lcl_reg),
        .I2(req_wr_r_lcl_reg_1),
        .I3(idle_r_lcl_reg_0),
        .I4(\q_entry_r[1]_i_4__0_n_0 ),
        .I5(head_r_lcl_reg_0),
        .O(head_r_lcl_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair781" *) 
  LUT5 #(
    .INIT(32'h2020202F)) 
    head_r_lcl_i_2__1
       (.I0(q_entry_r[0]),
        .I1(q_entry_r[1]),
        .I2(idle_r_lcl_reg_1),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .I4(rb_hit_busy_r_reg),
        .O(head_r_lcl_i_2__1_n_0));
  FDRE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1__1_n_0),
        .Q(head_r_lcl_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* SOFT_HLUTNM = "soft_lutpair782" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__2
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(\req_data_buf_addr_r_reg[0] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0888)) 
    \maint_controller.maint_hit_busies_r[2]_i_3 
       (.I0(\grant_r_reg[2]_0 ),
        .I1(pass_open_bank_r),
        .I2(rd_wr_r_lcl_reg),
        .I3(p_54_out),
        .I4(rstdiv0_sync_r1_reg_rep__20_0),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h553100305531CC30)) 
    \order_q_r[0]_i_1__1 
       (.I0(ordered_r_lcl_reg_1),
        .I1(order_q_r_0[0]),
        .I2(order_q_r_0[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(set_order_q),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(\order_q_r[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h553100305531CC30)) 
    \order_q_r[0]_i_1__2 
       (.I0(ordered_r_lcl_reg_1),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(req_wr_r_lcl_reg_0),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(\order_q_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAAC200C0AAC2F0C0)) 
    \order_q_r[1]_i_1__1 
       (.I0(ordered_r_lcl_reg_0),
        .I1(order_q_r_0[0]),
        .I2(order_q_r_0[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(set_order_q),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(\order_q_r[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAC200C0AAC2F0C0)) 
    \order_q_r[1]_i_1__2 
       (.I0(ordered_r_lcl_reg_0),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_wr_r_lcl_reg),
        .I4(req_wr_r_lcl_reg_0),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(\order_q_r_reg[1]_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1__1_n_0 ),
        .Q(order_q_r_0[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1__1_n_0 ),
        .Q(order_q_r_0[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000EAEA0AEA)) 
    ordered_r_lcl_i_1__1
       (.I0(p_64_out),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(p_54_out),
        .I3(\grant_r_reg[2]_0 ),
        .I4(rd_wr_r_lcl_reg),
        .I5(rstdiv0_sync_r1_reg_rep__19_0),
        .O(ordered_r_lcl_i_1__1_n_0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_i_1__1_n_0),
        .Q(p_64_out),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44454444)) 
    pass_open_bank_r_lcl_i_1__2
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(periodic_rd_ack_r_lcl_reg_1),
        .I3(pre_wait_r),
        .I4(row_hit_r_reg),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h7FFF000000000000)) 
    periodic_rd_ack_r_lcl_i_1
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I1(idle_r_lcl_reg_2),
        .I2(idle_r_lcl_reg_3),
        .I3(idle_r_lcl_reg_4),
        .I4(init_calib_complete_reg_rep),
        .I5(periodic_rd_insert),
        .O(periodic_rd_ack_ns));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    \q_entry_r[0]_i_1__1 
       (.I0(q_entry_ns),
        .I1(\q_entry_r[1]_i_4__0_n_0 ),
        .I2(q_entry_r[0]),
        .O(\q_entry_r[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hBE14BEBE141414BE)) 
    \q_entry_r[0]_i_2__0 
       (.I0(act_wait_r_lcl_reg),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(idle_r_lcl_reg_5),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .I4(q_entry_r[0]),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .O(q_entry_ns));
  LUT6 #(
    .INIT(64'hFE02FFFFFE020000)) 
    \q_entry_r[1]_i_1__1 
       (.I0(idle_r_lcl_reg_6),
        .I1(act_wait_r_lcl_reg),
        .I2(periodic_rd_ack_r_lcl_reg),
        .I3(\q_entry_r_reg[1]_1 ),
        .I4(\q_entry_r[1]_i_4__0_n_0 ),
        .I5(q_entry_r[1]),
        .O(\q_entry_r[1]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hF3FFF7F7)) 
    \q_entry_r[1]_i_4__0 
       (.I0(head_r_lcl_reg_1),
        .I1(act_wait_r_lcl_reg),
        .I2(periodic_rd_ack_r_lcl_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg),
        .I4(\req_data_buf_addr_r_reg[0] ),
        .O(\q_entry_r[1]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h560056FF56FF5600)) 
    \q_entry_r[1]_i_5__0 
       (.I0(rb_hit_busy_r_reg),
        .I1(head_r_lcl_reg_1),
        .I2(rb_hit_busy_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .I4(q_entry_r[1]),
        .I5(q_entry_r[0]),
        .O(\q_entry_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h00000DDD0DDD0DDD)) 
    \q_entry_r[1]_i_6__1 
       (.I0(Q[0]),
        .I1(pre_bm_end_r_reg_0),
        .I2(Q[2]),
        .I3(p_91_out),
        .I4(Q[1]),
        .I5(p_130_out),
        .O(head_r_lcl_reg_1));
  FDRE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1__1_n_0 ),
        .Q(q_entry_r[0]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDSE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1__1_n_0 ),
        .Q(q_entry_r[1]),
        .S(rstdiv0_sync_r1_reg_rep__0));
  LUT5 #(
    .INIT(32'h44544444)) 
    q_has_priority_r_i_1__2
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_priority),
        .I2(p_48_out),
        .I3(periodic_rd_ack_r_lcl_reg),
        .I4(was_priority),
        .O(q_has_priority_r_i_1__2_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1__2_n_0),
        .Q(q_has_priority),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4445444544455555)) 
    q_has_rd_r_i_1__2
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(\maintenance_request.maint_zq_r_lcl_reg ),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(was_wr),
        .I5(app_en_r2_reg),
        .O(q_has_rd_r_i_1__2_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1__2_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair783" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1__1 
       (.I0(\ras_timer_r[0]_i_2__2_n_0 ),
        .I1(\ras_timer_r_reg[0] ),
        .I2(\ras_timer_r_reg[0]_1 ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[0]_i_2__2 
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(\ras_timer_r_reg[1] ),
        .I4(rd_wr_r_lcl_reg_1),
        .I5(Q[1]),
        .O(\ras_timer_r[0]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair783" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1__1 
       (.I0(\ras_timer_r[1]_i_2__2_n_0 ),
        .I1(\ras_timer_r_reg[0] ),
        .I2(bm_end_r1_reg),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2__2 
       (.I0(bm_end_r1_reg_0),
        .I1(Q[2]),
        .I2(bm_end_r1_reg_1),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(bm_end_r1_reg_2),
        .O(\ras_timer_r[1]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair782" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1 
       (.I0(p_28_out),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I2(Q[0]),
        .I3(\grant_r_reg[3] ),
        .O(p_2_out[3]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0 
       (.I0(p_145_out),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I2(Q[1]),
        .I3(clear_req_3),
        .O(p_2_out[4]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1 
       (.I0(p_106_out),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I2(Q[2]),
        .I3(clear_req),
        .O(p_2_out[5]));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[3]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[4]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[5]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__20));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_queue" *) 
module mig_7series_0_mig_7series_v2_3_bank_queue__parameterized2
   (\req_data_buf_addr_r_reg[0] ,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    pre_bm_end_r,
    q_has_rd,
    auto_pre_r_lcl_reg_0,
    tail_r,
    head_r_lcl_reg_0,
    order_q_r,
    act_wait_r_lcl_reg,
    granted_col_r_reg,
    \ras_timer_r_reg[0] ,
    demand_priority_r_reg,
    \q_entry_r_reg[0]_0 ,
    pass_open_bank_r_lcl_reg_0,
    D,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ,
    demand_priority_ns,
    demand_priority_r_reg_0,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    req_bank_rdy_ns,
    head_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_0 ,
    act_wait_ns,
    \ras_timer_r_reg[0]_0 ,
    \grant_r_reg[3] ,
    auto_pre_r_lcl_reg_1,
    p_25_out,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    rstdiv0_sync_r1_reg_rep__20,
    wait_for_maint_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__19,
    rstdiv0_sync_r1_reg_rep__0,
    \order_q_r_reg[0]_0 ,
    \order_q_r_reg[0]_1 ,
    pre_bm_end_r_reg_0,
    idle_r_lcl_reg_0,
    col_wait_r_reg,
    act_wait_r_lcl_reg_0,
    \grant_r_reg[1] ,
    \rnk_config_strobe_r_reg[0]_1 ,
    idle_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    rb_hit_busy_r_reg,
    \maintenance_request.maint_zq_r_lcl_reg ,
    was_wr,
    app_en_r2_reg,
    rb_hit_busy_r_reg_0,
    periodic_rd_ack_r_lcl_reg,
    was_priority,
    Q,
    rd_wr_r_lcl_reg,
    req_wr_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__20_0,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0]_1 ,
    rd_wr_r_lcl_reg_0,
    rd_wr_r_lcl_reg_1,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    bm_end_r1_reg_2,
    rstdiv0_sync_r1_reg_rep__19_0,
    req_priority_r,
    demand_priority_r_reg_1,
    col_wait_r_reg_0,
    demand_priority_r_reg_2,
    \rnk_config_strobe_r_reg[0]_2 ,
    req_wr_r_lcl_reg_0,
    periodic_rd_ack_r_lcl_reg_0,
    idle_r_lcl_reg_2,
    p_126_out,
    p_87_out,
    p_48_out,
    p_130_out,
    pre_bm_end_r_reg_1,
    p_91_out,
    \grant_r_reg[3]_0 ,
    act_wait_r_lcl_reg_1,
    rstdiv0_sync_r1_reg_rep__20_1,
    pre_passing_open_bank_r_reg_0,
    pre_passing_open_bank_r_reg_1,
    pre_passing_open_bank_r_reg_2,
    p_106_out,
    clear_req,
    p_145_out,
    clear_req_1,
    periodic_rd_ack_r_lcl_reg_1,
    pre_wait_r,
    row_hit_r_reg,
    p_67_out,
    \grant_r_reg[2] ,
    ras_timer_zero_r,
    idle_r_lcl_reg_3,
    q_entry_ns,
    rb_hit_busy_r_reg_1,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    row_hit_r,
    rstdiv0_sync_r1_reg_rep__19_1);
  output [0:0]\req_data_buf_addr_r_reg[0] ;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output pre_bm_end_r;
  output q_has_rd;
  output auto_pre_r_lcl_reg_0;
  output tail_r;
  output head_r_lcl_reg_0;
  output [1:0]order_q_r;
  output act_wait_r_lcl_reg;
  output granted_col_r_reg;
  output \ras_timer_r_reg[0] ;
  output demand_priority_r_reg;
  output \q_entry_r_reg[0]_0 ;
  output pass_open_bank_r_lcl_reg_0;
  output [1:0]D;
  output [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  output demand_priority_ns;
  output demand_priority_r_reg_0;
  output \rnk_config_strobe_r_reg[0] ;
  output \rnk_config_strobe_r_reg[0]_0 ;
  output req_bank_rdy_ns;
  output head_r_lcl_reg_1;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output act_wait_ns;
  output \ras_timer_r_reg[0]_0 ;
  output \grant_r_reg[3] ;
  output auto_pre_r_lcl_reg_1;
  output p_25_out;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input rstdiv0_sync_r1_reg_rep__20;
  input wait_for_maint_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__19;
  input rstdiv0_sync_r1_reg_rep__0;
  input \order_q_r_reg[0]_0 ;
  input \order_q_r_reg[0]_1 ;
  input pre_bm_end_r_reg_0;
  input idle_r_lcl_reg_0;
  input col_wait_r_reg;
  input act_wait_r_lcl_reg_0;
  input \grant_r_reg[1] ;
  input \rnk_config_strobe_r_reg[0]_1 ;
  input idle_r_lcl_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input rb_hit_busy_r_reg;
  input \maintenance_request.maint_zq_r_lcl_reg ;
  input was_wr;
  input app_en_r2_reg;
  input rb_hit_busy_r_reg_0;
  input periodic_rd_ack_r_lcl_reg;
  input was_priority;
  input [0:0]Q;
  input rd_wr_r_lcl_reg;
  input req_wr_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[0]_1 ;
  input rd_wr_r_lcl_reg_0;
  input rd_wr_r_lcl_reg_1;
  input bm_end_r1_reg;
  input bm_end_r1_reg_0;
  input bm_end_r1_reg_1;
  input bm_end_r1_reg_2;
  input rstdiv0_sync_r1_reg_rep__19_0;
  input req_priority_r;
  input demand_priority_r_reg_1;
  input col_wait_r_reg_0;
  input demand_priority_r_reg_2;
  input \rnk_config_strobe_r_reg[0]_2 ;
  input req_wr_r_lcl_reg_0;
  input periodic_rd_ack_r_lcl_reg_0;
  input idle_r_lcl_reg_2;
  input p_126_out;
  input p_87_out;
  input p_48_out;
  input p_130_out;
  input pre_bm_end_r_reg_1;
  input p_91_out;
  input [0:0]\grant_r_reg[3]_0 ;
  input act_wait_r_lcl_reg_1;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input pre_passing_open_bank_r_reg_0;
  input pre_passing_open_bank_r_reg_1;
  input pre_passing_open_bank_r_reg_2;
  input p_106_out;
  input clear_req;
  input p_145_out;
  input clear_req_1;
  input periodic_rd_ack_r_lcl_reg_1;
  input pre_wait_r;
  input row_hit_r_reg;
  input p_67_out;
  input \grant_r_reg[2] ;
  input ras_timer_zero_r;
  input idle_r_lcl_reg_3;
  input [0:0]q_entry_ns;
  input rb_hit_busy_r_reg_1;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input row_hit_r;
  input rstdiv0_sync_r1_reg_rep__19_1;

  wire CLK;
  wire [1:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_5__0_n_0;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire app_en_r2_reg;
  wire auto_pre_r_lcl_i_1__2_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire bm_end_r1_reg_2;
  wire clear_req;
  wire clear_req_1;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_priority_ns;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[3] ;
  wire [0:0]\grant_r_reg[3]_0 ;
  wire granted_col_r_reg;
  wire head_r_lcl_i_1__2_n_0;
  wire head_r_lcl_i_2__0_n_0;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire ordered_r_lcl_i_1__2_n_0;
  wire p_106_out;
  wire p_126_out;
  wire p_130_out;
  wire p_145_out;
  wire p_25_out;
  wire [6:4]p_2_out;
  wire p_48_out;
  wire p_67_out;
  wire p_87_out;
  wire p_91_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_passing_open_bank_r_reg_1;
  wire pre_passing_open_bank_r_reg_2;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire [1:1]q_entry_r;
  wire \q_entry_r[0]_i_1__2_n_0 ;
  wire \q_entry_r[1]_i_1__2_n_0 ;
  wire \q_entry_r[1]_i_3_n_0 ;
  wire \q_entry_r[1]_i_4_n_0 ;
  wire \q_entry_r[1]_i_5_n_0 ;
  wire \q_entry_r_reg[0]_0 ;
  wire q_has_priority;
  wire q_has_priority_r_i_1__1_n_0;
  wire q_has_rd;
  wire q_has_rd_r_i_1__1_n_0;
  wire \ras_timer_r[0]_i_2__0_n_0 ;
  wire \ras_timer_r[1]_i_2__0_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[1] ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire [2:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire req_bank_rdy_ns;
  wire [0:0]\req_data_buf_addr_r_reg[0] ;
  wire req_priority_r;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire \rnk_config_strobe_r_reg[0]_1 ;
  wire \rnk_config_strobe_r_reg[0]_2 ;
  wire row_hit_r;
  wire row_hit_r_reg;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__19_1;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire was_priority;
  wire was_wr;

  LUT3 #(
    .INIT(8'h0D)) 
    accept_internal_r_i_4
       (.I0(\req_data_buf_addr_r_reg[0] ),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(pass_open_bank_r_lcl_reg_0),
        .O(demand_priority_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF0404FF04)) 
    act_wait_r_lcl_i_1__1
       (.I0(\grant_r_reg[3]_0 ),
        .I1(act_wait_r_lcl_reg_1),
        .I2(\ras_timer_r_reg[0] ),
        .I3(pass_open_bank_r),
        .I4(act_wait_r_lcl_reg),
        .I5(rstdiv0_sync_r1_reg_rep__20_1),
        .O(act_wait_ns));
  LUT4 #(
    .INIT(16'h0020)) 
    act_wait_r_lcl_i_2__1
       (.I0(act_wait_r_lcl_i_5__0_n_0),
        .I1(q_entry_r),
        .I2(\q_entry_r_reg[0]_0 ),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .O(\ras_timer_r_reg[0] ));
  LUT5 #(
    .INIT(32'h55151515)) 
    act_wait_r_lcl_i_3
       (.I0(pre_bm_end_r),
        .I1(Q),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(req_wr_r_lcl_reg),
        .O(act_wait_r_lcl_reg));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    act_wait_r_lcl_i_5__0
       (.I0(pre_passing_open_bank_r_reg_0),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]),
        .I3(pre_passing_open_bank_r_reg_1),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]),
        .I5(pre_passing_open_bank_r_reg_2),
        .O(act_wait_r_lcl_i_5__0_n_0));
  LUT5 #(
    .INIT(32'h55151515)) 
    act_wait_r_lcl_i_7
       (.I0(pre_passing_open_bank_r),
        .I1(Q),
        .I2(pass_open_bank_r),
        .I3(rd_wr_r_lcl_reg),
        .I4(req_wr_r_lcl_reg),
        .O(\ras_timer_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAEEEEE)) 
    auto_pre_r_lcl_i_1__2
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg_1),
        .I2(auto_pre_r_lcl_reg_0),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(row_hit_r),
        .I5(pass_open_bank_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1__2_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1__2_n_0),
        .Q(auto_pre_r_lcl_reg_1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h08)) 
    \compute_tail.tail_r_lcl_i_3 
       (.I0(act_wait_r_lcl_reg),
        .I1(pre_bm_end_r_reg_1),
        .I2(p_91_out),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  FDRE \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r1_reg_rep__19),
        .Q(tail_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8888888800008880)) 
    demand_priority_r_i_1
       (.I0(rstdiv0_sync_r1_reg_rep__19_0),
        .I1(demand_priority_r_reg_0),
        .I2(req_priority_r),
        .I3(q_has_priority),
        .I4(demand_priority_r_reg),
        .I5(demand_priority_r_reg_1),
        .O(demand_priority_ns));
  (* SOFT_HLUTNM = "soft_lutpair790" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    demand_priority_r_i_2
       (.I0(req_wr_r_lcl_reg_0),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(rd_wr_r_lcl_reg),
        .O(demand_priority_r_reg));
  LUT2 #(
    .INIT(4'h2)) 
    \grant_r[1]_i_4 
       (.I0(\rnk_config_strobe_r_reg[0]_0 ),
        .I1(col_wait_r_reg_0),
        .O(\rnk_config_strobe_r_reg[0] ));
  LUT4 #(
    .INIT(16'hFDFF)) 
    \grant_r[3]_i_5 
       (.I0(demand_priority_r_reg_2),
        .I1(\rnk_config_strobe_r_reg[0]_2 ),
        .I2(demand_priority_r_reg),
        .I3(col_wait_r_reg),
        .O(\rnk_config_strobe_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF7F)) 
    \grant_r[3]_i_8 
       (.I0(head_r_lcl_reg_0),
        .I1(ras_timer_zero_r),
        .I2(act_wait_r_lcl_reg_1),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(\grant_r_reg[3] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF01)) 
    granted_col_r_i_3
       (.I0(\ras_timer_r_reg[0] ),
        .I1(col_wait_r_reg),
        .I2(act_wait_r_lcl_reg_0),
        .I3(\grant_r_reg[1] ),
        .I4(\rnk_config_strobe_r_reg[0]_1 ),
        .I5(demand_priority_r_reg),
        .O(granted_col_r_reg));
  LUT6 #(
    .INIT(64'hB888FFFFB8880000)) 
    head_r_lcl_i_1__2
       (.I0(head_r_lcl_i_2__0_n_0),
        .I1(act_wait_r_lcl_reg),
        .I2(pre_bm_end_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(\q_entry_r[1]_i_4_n_0 ),
        .I5(head_r_lcl_reg_0),
        .O(head_r_lcl_i_1__2_n_0));
  LUT5 #(
    .INIT(32'h2020202F)) 
    head_r_lcl_i_2__0
       (.I0(\q_entry_r_reg[0]_0 ),
        .I1(q_entry_r),
        .I2(idle_r_lcl_reg_1),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I4(rb_hit_busy_r_reg),
        .O(head_r_lcl_i_2__0_n_0));
  FDRE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1__2_n_0),
        .Q(head_r_lcl_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* SOFT_HLUTNM = "soft_lutpair791" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__1
       (.I0(demand_priority_r_reg_0),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(\req_data_buf_addr_r_reg[0] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0888)) 
    \maint_controller.maint_hit_busies_r[3]_i_4 
       (.I0(Q),
        .I1(pass_open_bank_r),
        .I2(rd_wr_r_lcl_reg),
        .I3(req_wr_r_lcl_reg),
        .I4(rstdiv0_sync_r1_reg_rep__20_0),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r_reg[0]_1 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r_reg[0]_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000EE0EAAAA)) 
    ordered_r_lcl_i_1__2
       (.I0(p_25_out),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(Q),
        .I3(rd_wr_r_lcl_reg),
        .I4(req_wr_r_lcl_reg),
        .I5(rstdiv0_sync_r1_reg_rep__19_1),
        .O(ordered_r_lcl_i_1__2_n_0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_i_1__2_n_0),
        .Q(p_25_out),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44454444)) 
    pass_open_bank_r_lcl_i_1__1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(periodic_rd_ack_r_lcl_reg_1),
        .I3(pre_wait_r),
        .I4(row_hit_r_reg),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    \q_entry_r[0]_i_1__2 
       (.I0(q_entry_ns),
        .I1(\q_entry_r[1]_i_4_n_0 ),
        .I2(\q_entry_r_reg[0]_0 ),
        .O(\q_entry_r[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFE02FFFFFE020000)) 
    \q_entry_r[1]_i_1__2 
       (.I0(idle_r_lcl_reg_3),
        .I1(act_wait_r_lcl_reg),
        .I2(periodic_rd_ack_r_lcl_reg),
        .I3(\q_entry_r[1]_i_3_n_0 ),
        .I4(\q_entry_r[1]_i_4_n_0 ),
        .I5(q_entry_r),
        .O(\q_entry_r[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB88BFFFFB88B0000)) 
    \q_entry_r[1]_i_3 
       (.I0(\q_entry_r[1]_i_5_n_0 ),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(q_entry_r),
        .I3(\q_entry_r_reg[0]_0 ),
        .I4(act_wait_r_lcl_reg),
        .I5(idle_r_lcl_reg_2),
        .O(\q_entry_r[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF35FF)) 
    \q_entry_r[1]_i_4 
       (.I0(head_r_lcl_reg_1),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(\req_data_buf_addr_r_reg[0] ),
        .I3(act_wait_r_lcl_reg),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .O(\q_entry_r[1]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h7EE8E881)) 
    \q_entry_r[1]_i_5 
       (.I0(head_r_lcl_reg_1),
        .I1(p_126_out),
        .I2(p_87_out),
        .I3(p_48_out),
        .I4(rb_hit_busy_r_reg_0),
        .O(\q_entry_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000770777077707)) 
    \q_entry_r[1]_i_7 
       (.I0(p_130_out),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]),
        .I3(pre_bm_end_r_reg_1),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]),
        .I5(p_91_out),
        .O(head_r_lcl_reg_1));
  FDSE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1__2_n_0 ),
        .Q(\q_entry_r_reg[0]_0 ),
        .S(rstdiv0_sync_r1_reg_rep__0));
  FDSE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1__2_n_0 ),
        .Q(q_entry_r),
        .S(rstdiv0_sync_r1_reg_rep__0));
  LUT5 #(
    .INIT(32'h44544444)) 
    q_has_priority_r_i_1__1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_priority),
        .I2(rb_hit_busy_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg),
        .I4(was_priority),
        .O(q_has_priority_r_i_1__1_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1__1_n_0),
        .Q(q_has_priority),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4445444544455555)) 
    q_has_rd_r_i_1__1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(\maintenance_request.maint_zq_r_lcl_reg ),
        .I3(\req_data_buf_addr_r_reg[0] ),
        .I4(was_wr),
        .I5(app_en_r2_reg),
        .O(q_has_rd_r_i_1__1_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1__1_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair792" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1__0 
       (.I0(\ras_timer_r[0]_i_2__0_n_0 ),
        .I1(\ras_timer_r_reg[0] ),
        .I2(\ras_timer_r_reg[1] ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[0]_i_2__0 
       (.I0(\ras_timer_r_reg[0]_1 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]),
        .I3(rd_wr_r_lcl_reg_0),
        .I4(rd_wr_r_lcl_reg_1),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]),
        .O(\ras_timer_r[0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair792" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1__0 
       (.I0(\ras_timer_r[1]_i_2__0_n_0 ),
        .I1(\ras_timer_r_reg[0] ),
        .I2(bm_end_r1_reg),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2__0 
       (.I0(bm_end_r1_reg_0),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]),
        .I2(bm_end_r1_reg_1),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]),
        .I5(bm_end_r1_reg_2),
        .O(\ras_timer_r[1]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair791" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1 
       (.I0(p_145_out),
        .I1(demand_priority_r_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]),
        .I3(clear_req_1),
        .O(p_2_out[4]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0 
       (.I0(p_106_out),
        .I1(demand_priority_r_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]),
        .I3(clear_req),
        .O(p_2_out[5]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1 
       (.I0(p_67_out),
        .I1(demand_priority_r_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]),
        .I3(\grant_r_reg[2] ),
        .O(p_2_out[6]));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[4]),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[5]),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]),
        .R(1'b0));
  FDRE \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_2_out[6]),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair790" *) 
  LUT5 #(
    .INIT(32'h888A8A8A)) 
    req_bank_rdy_r_i_1
       (.I0(col_wait_r_reg),
        .I1(rd_wr_r_lcl_reg),
        .I2(order_q_r[1]),
        .I3(order_q_r[0]),
        .I4(req_wr_r_lcl_reg_0),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__20));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_state" *) 
module mig_7series_0_mig_7series_v2_3_bank_state
   (bm_end_r1,
    \act_this_rank_r_reg[0]_0 ,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r,
    col_wait_r_reg_0,
    demand_act_priority_r,
    act_this_rank_r,
    demanded_prior_r_reg_0,
    demanded_prior_r_reg_1,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    \grant_r_reg[2] ,
    rnk_config_strobe_ns,
    \rnk_config_strobe_r_reg[0] ,
    \grant_r_reg[1] ,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    ras_timer_zero_r_reg_0,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[1]_0 ,
    auto_pre_r_lcl_reg,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    demanded_prior_r_reg_2,
    demand_priority_r_reg_0,
    p_130_out,
    CLK,
    act_wait_ns,
    req_bank_rdy_ns,
    demand_priority_ns,
    rstdiv0_sync_r1_reg_rep__0,
    ofs_rdy_r0,
    wr_this_rank_r0,
    rd_wr_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__19,
    \grant_r_reg[0] ,
    \grant_r_reg[2]_0 ,
    \q_entry_r_reg[1] ,
    demanded_prior_r_reg_3,
    col_wait_r_reg_1,
    col_wait_r_reg_2,
    \order_q_r_reg[0] ,
    demanded_prior_r_reg_4,
    \rnk_config_strobe_r_reg[0]_0 ,
    \grant_r_reg[0]_0 ,
    auto_pre_r_lcl_reg_0,
    pass_open_bank_ns,
    pass_open_bank_r,
    rstdiv0_sync_r1_reg_rep__20,
    rd_wr_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__20_0,
    p_126_out,
    tail_r,
    accept_r_reg,
    wait_for_maint_r_lcl_reg,
    p_129_out,
    p_128_out,
    demanded_prior_r_2,
    demand_priority_r_3,
    granted_col_r_reg,
    q_has_rd,
    p_132_out,
    D,
    rstdiv0_sync_r1_reg_rep__24);
  output bm_end_r1;
  output \act_this_rank_r_reg[0]_0 ;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r;
  output col_wait_r_reg_0;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demanded_prior_r_reg_0;
  output demanded_prior_r_reg_1;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output \grant_r_reg[2] ;
  output rnk_config_strobe_ns;
  output \rnk_config_strobe_r_reg[0] ;
  output \grant_r_reg[1] ;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output ras_timer_zero_r_reg_0;
  output \ras_timer_r_reg[0]_0 ;
  output \ras_timer_r_reg[1]_0 ;
  output auto_pre_r_lcl_reg;
  output \pre_4_1_1T_arb.granted_pre_r_reg ;
  output demanded_prior_r_reg_2;
  output demand_priority_r_reg_0;
  input p_130_out;
  input CLK;
  input act_wait_ns;
  input req_bank_rdy_ns;
  input demand_priority_ns;
  input rstdiv0_sync_r1_reg_rep__0;
  input ofs_rdy_r0;
  input wr_this_rank_r0;
  input rd_wr_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__19;
  input [0:0]\grant_r_reg[0] ;
  input [1:0]\grant_r_reg[2]_0 ;
  input \q_entry_r_reg[1] ;
  input demanded_prior_r_reg_3;
  input col_wait_r_reg_1;
  input col_wait_r_reg_2;
  input \order_q_r_reg[0] ;
  input demanded_prior_r_reg_4;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input [0:0]\grant_r_reg[0]_0 ;
  input auto_pre_r_lcl_reg_0;
  input pass_open_bank_ns;
  input pass_open_bank_r;
  input rstdiv0_sync_r1_reg_rep__20;
  input rd_wr_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input p_126_out;
  input tail_r;
  input accept_r_reg;
  input wait_for_maint_r_lcl_reg;
  input p_129_out;
  input p_128_out;
  input demanded_prior_r_2;
  input demand_priority_r_3;
  input granted_col_r_reg;
  input q_has_rd;
  input p_132_out;
  input [1:0]D;
  input rstdiv0_sync_r1_reg_rep__24;

  wire CLK;
  wire [1:0]D;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire \act_this_rank_r_reg[0]_0 ;
  wire act_wait_ns;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire bm_end_r1;
  wire col_wait_r;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire col_wait_r_reg_2;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_priority_ns;
  wire demand_priority_r_3;
  wire demand_priority_r_i_4_n_0;
  wire demand_priority_r_reg_0;
  wire demanded_prior_ns;
  wire demanded_prior_r_2;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire demanded_prior_r_reg_3;
  wire demanded_prior_r_reg_4;
  wire [0:0]\grant_r_reg[0] ;
  wire [0:0]\grant_r_reg[0]_0 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[2] ;
  wire [1:0]\grant_r_reg[2]_0 ;
  wire granted_col_r_reg;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire \order_q_r_reg[0] ;
  wire p_126_out;
  wire p_128_out;
  wire p_129_out;
  wire p_130_out;
  wire p_132_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2_n_0;
  wire \q_entry_r_reg[1] ;
  wire q_has_rd;
  wire [1:0]ras_timer_r;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_ns;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1_n_0 ;
  wire \rtp_timer_r[1]_i_1_n_0 ;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\act_this_rank_r_reg[0]_0 ),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(\act_this_rank_r_reg[0]_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0808080800000800)) 
    auto_pre_r_lcl_i_2
       (.I0(p_126_out),
        .I1(tail_r),
        .I2(accept_r_reg),
        .I3(col_wait_r),
        .I4(\grant_r_reg[2]_0 [0]),
        .I5(\act_this_rank_r_reg[0]_0 ),
        .O(auto_pre_r_lcl_reg));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_130_out),
        .Q(bm_end_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h5555555540554040)) 
    col_wait_r_i_1
       (.I0(rstdiv0_sync_r1_reg_rep__19),
        .I1(\grant_r_reg[0] ),
        .I2(\act_this_rank_r_reg[0]_0 ),
        .I3(\grant_r_reg[2]_0 [0]),
        .I4(col_wait_r),
        .I5(\q_entry_r_reg[1] ),
        .O(col_wait_r_reg_0));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_reg_0),
        .Q(col_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0200000000000000)) 
    demand_act_priority_r_i_1__2
       (.I0(demand_act_priority_r),
        .I1(wait_for_maint_r_lcl_reg),
        .I2(p_129_out),
        .I3(\act_this_rank_r_reg[0]_0 ),
        .I4(ras_timer_zero_r),
        .I5(p_128_out),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hBAAAAAAA)) 
    demand_priority_r_i_3
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_i_4_n_0),
        .I2(starve_limit_cntr_r[2]),
        .I3(starve_limit_cntr_r[1]),
        .I4(starve_limit_cntr_r[0]),
        .O(demand_priority_r_reg_0));
  LUT5 #(
    .INIT(32'hDFFFDFDF)) 
    demand_priority_r_i_4
       (.I0(granted_col_r_reg),
        .I1(\grant_r_reg[2]_0 [0]),
        .I2(req_bank_rdy_r),
        .I3(q_has_rd),
        .I4(p_132_out),
        .O(demand_priority_r_i_4_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0DDD0D0)) 
    demanded_prior_r_i_1__1
       (.I0(demanded_prior_r_reg_0),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_reg_3),
        .I3(demanded_prior_r_2),
        .I4(demand_priority_r_3),
        .I5(\grant_r_reg[2]_0 [1]),
        .O(demanded_prior_ns));
  LUT6 #(
    .INIT(64'hFBFBFBFBFB00FBFB)) 
    demanded_prior_r_i_2__0
       (.I0(demanded_prior_r_reg_1),
        .I1(demanded_prior_r_reg_0),
        .I2(\grant_r_reg[2]_0 [0]),
        .I3(demanded_prior_r_2),
        .I4(demand_priority_r_3),
        .I5(\grant_r_reg[2]_0 [1]),
        .O(demanded_prior_r_reg_2));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_1),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00004044)) 
    \grant_r[1]_i_3__0 
       (.I0(\order_q_r_reg[0] ),
        .I1(col_wait_r),
        .I2(demanded_prior_r_reg_0),
        .I3(demanded_prior_r_reg_4),
        .I4(\rnk_config_strobe_r_reg[0]_0 ),
        .O(\grant_r_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair767" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[1]_i_3__1 
       (.I0(auto_pre_r_lcl_reg_0),
        .I1(\grant_r_reg[0]_0 ),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg ));
  LUT4 #(
    .INIT(16'hAABA)) 
    \grant_r[2]_i_9 
       (.I0(demanded_prior_r_reg_3),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_reg_0),
        .I3(\grant_r_reg[2]_0 [0]),
        .O(\grant_r_reg[2] ));
  LUT2 #(
    .INIT(4'hB)) 
    \grant_r[3]_i_2 
       (.I0(\grant_r_reg[1] ),
        .I1(col_wait_r_reg_2),
        .O(\rnk_config_strobe_r_reg[0] ));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* SOFT_HLUTNM = "soft_lutpair767" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__0
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[0]_0 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__0
       (.I0(pass_open_bank_ns),
        .I1(\grant_r_reg[2]_0 [0]),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__0
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2_n_0),
        .I2(pass_open_bank_r),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[0]_0 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_wait_r_i_2_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000004444FFF4)) 
    \ras_timer_r[0]_i_3__1 
       (.I0(rd_wr_r_lcl_reg),
        .I1(\grant_r_reg[2]_0 [0]),
        .I2(ras_timer_zero_r_reg_0),
        .I3(ras_timer_r[1]),
        .I4(ras_timer_r[0]),
        .I5(rstdiv0_sync_r1_reg_rep__20_0),
        .O(\ras_timer_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_3__1 
       (.I0(bm_end_r1),
        .I1(rstdiv0_sync_r1_reg_rep__20),
        .I2(ras_timer_r[0]),
        .I3(ras_timer_r[1]),
        .I4(rd_wr_r_lcl_reg),
        .I5(\grant_r_reg[2]_0 [0]),
        .O(\ras_timer_r_reg[1]_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(ras_timer_r[0]),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(ras_timer_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0C04)) 
    ras_timer_zero_r_i_1__1
       (.I0(ras_timer_zero_r_reg_0),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(ras_timer_r[1]),
        .I3(ras_timer_r[0]),
        .I4(rstdiv0_sync_r1_reg_rep__20),
        .I5(bm_end_r1),
        .O(ras_timer_zero_ns));
  LUT2 #(
    .INIT(4'h8)) 
    ras_timer_zero_r_i_2
       (.I0(\act_this_rank_r_reg[0]_0 ),
        .I1(\grant_r_reg[0] ),
        .O(ras_timer_zero_r_reg_0));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_ns),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_r_lcl_reg),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    \rnk_config_strobe_r[0]_i_1 
       (.I0(\rnk_config_strobe_r_reg[0] ),
        .I1(col_wait_r_reg_1),
        .O(rnk_config_strobe_ns));
  LUT4 #(
    .INIT(16'h0002)) 
    \rtp_timer_r[0]_i_1 
       (.I0(rtp_timer_r[1]),
        .I1(rtp_timer_r[0]),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .I3(pass_open_bank_r),
        .O(\rtp_timer_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1 
       (.I0(\grant_r_reg[2]_0 [0]),
        .I1(rtp_timer_r[1]),
        .I2(rtp_timer_r[0]),
        .I3(pass_open_bank_r),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .O(\rtp_timer_r[1]_i_1_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair768" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair768" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00007F0000000000)) 
    \starve_limit_cntr_r[2]_i_2 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(granted_col_r_reg),
        .I4(\grant_r_reg[2]_0 [0]),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_this_rank_r0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_state" *) 
module mig_7series_0_mig_7series_v2_3_bank_state__parameterized0
   (bm_end_r1_0,
    \act_this_rank_r_reg[0]_0 ,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    col_wait_r_reg_1,
    demand_act_priority_r,
    act_this_rank_r,
    demanded_prior_r_reg_0,
    demanded_prior_r_reg_1,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    granted_col_r_reg,
    \grant_r_reg[3] ,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    ras_timer_zero_r_reg_0,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[1]_0 ,
    auto_pre_r_lcl_reg,
    granted_pre_ns,
    \grant_r_reg[2] ,
    granted_row_ns,
    granted_row_r_reg,
    \grant_r_reg[1] ,
    \grant_r_reg[2]_0 ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[2]_1 ,
    demand_priority_r_reg_0,
    p_91_out,
    CLK,
    act_wait_ns,
    req_bank_rdy_ns,
    demand_priority_ns,
    rstdiv0_sync_r1_reg_rep__0,
    ofs_rdy_r0,
    wr_this_rank_r0,
    rd_wr_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__20,
    \grant_r_reg[3]_0 ,
    Q,
    \q_entry_r_reg[1] ,
    demanded_prior_r_reg_2,
    override_demand_r,
    demand_priority_r_0,
    \grant_r_reg[1]_1 ,
    auto_pre_r_lcl_reg_0,
    pass_open_bank_ns,
    pass_open_bank_r,
    rstdiv0_sync_r1_reg_rep__19,
    rd_wr_r_lcl_reg_0,
    rstdiv0_sync_r1_reg_rep__20_0,
    p_87_out,
    tail_r,
    accept_r_reg,
    auto_pre_r_lcl_reg_1,
    ras_timer_zero_r_reg_1,
    demand_act_priority_r_reg_0,
    \grant_r_reg[2]_2 ,
    demand_act_priority_r_2,
    demand_act_priority_r_reg_1,
    \grant_r_reg[1]_2 ,
    head_r_lcl_reg,
    \last_master_r_reg[0] ,
    wait_for_maint_r_lcl_reg,
    p_90_out,
    p_89_out,
    demanded_prior_r_3,
    granted_col_r_reg_0,
    q_has_rd,
    p_93_out,
    D,
    rstdiv0_sync_r1_reg_rep__24);
  output bm_end_r1_0;
  output \act_this_rank_r_reg[0]_0 ;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output col_wait_r_reg_1;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demanded_prior_r_reg_0;
  output demanded_prior_r_reg_1;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output granted_col_r_reg;
  output \grant_r_reg[3] ;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output ras_timer_zero_r_reg_0;
  output \ras_timer_r_reg[0]_0 ;
  output \ras_timer_r_reg[1]_0 ;
  output auto_pre_r_lcl_reg;
  output granted_pre_ns;
  output \grant_r_reg[2] ;
  output granted_row_ns;
  output granted_row_r_reg;
  output \grant_r_reg[1] ;
  output \grant_r_reg[2]_0 ;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[2]_1 ;
  output demand_priority_r_reg_0;
  input p_91_out;
  input CLK;
  input act_wait_ns;
  input req_bank_rdy_ns;
  input demand_priority_ns;
  input rstdiv0_sync_r1_reg_rep__0;
  input ofs_rdy_r0;
  input wr_this_rank_r0;
  input rd_wr_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__20;
  input [1:0]\grant_r_reg[3]_0 ;
  input [1:0]Q;
  input \q_entry_r_reg[1] ;
  input demanded_prior_r_reg_2;
  input override_demand_r;
  input demand_priority_r_0;
  input [0:0]\grant_r_reg[1]_1 ;
  input auto_pre_r_lcl_reg_0;
  input pass_open_bank_ns;
  input pass_open_bank_r;
  input rstdiv0_sync_r1_reg_rep__19;
  input rd_wr_r_lcl_reg_0;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input p_87_out;
  input tail_r;
  input accept_r_reg;
  input auto_pre_r_lcl_reg_1;
  input ras_timer_zero_r_reg_1;
  input demand_act_priority_r_reg_0;
  input \grant_r_reg[2]_2 ;
  input demand_act_priority_r_2;
  input demand_act_priority_r_reg_1;
  input \grant_r_reg[1]_2 ;
  input head_r_lcl_reg;
  input \last_master_r_reg[0] ;
  input wait_for_maint_r_lcl_reg;
  input p_90_out;
  input p_89_out;
  input demanded_prior_r_3;
  input granted_col_r_reg_0;
  input q_has_rd;
  input p_93_out;
  input [1:0]D;
  input rstdiv0_sync_r1_reg_rep__24;

  wire CLK;
  wire [1:0]D;
  wire [1:0]Q;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire \act_this_rank_r_reg[0]_0 ;
  wire act_wait_ns;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire bm_end_r1_0;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_act_priority_r_2;
  wire demand_act_priority_r_reg_0;
  wire demand_act_priority_r_reg_1;
  wire demand_priority_ns;
  wire demand_priority_r_0;
  wire demand_priority_r_i_4__0_n_0;
  wire demand_priority_r_reg_0;
  wire demanded_prior_ns;
  wire demanded_prior_r_3;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire [0:0]\grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[2]_1 ;
  wire \grant_r_reg[2]_2 ;
  wire \grant_r_reg[3] ;
  wire [1:0]\grant_r_reg[3]_0 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_pre_ns;
  wire granted_row_ns;
  wire granted_row_r_reg;
  wire head_r_lcl_reg;
  wire \last_master_r_reg[0] ;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire override_demand_r;
  wire p_87_out;
  wire p_89_out;
  wire p_90_out;
  wire p_91_out;
  wire p_93_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pre_bm_end_ns;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__0_n_0;
  wire \q_entry_r_reg[1] ;
  wire q_has_rd;
  wire [1:0]ras_timer_r;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_ns;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__0_n_0 ;
  wire \rtp_timer_r[1]_i_1__0_n_0 ;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1__0_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1__0_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1__0_n_0 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\act_this_rank_r_reg[0]_0 ),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(\act_this_rank_r_reg[0]_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0808080800000800)) 
    auto_pre_r_lcl_i_2__0
       (.I0(p_87_out),
        .I1(tail_r),
        .I2(accept_r_reg),
        .I3(col_wait_r_reg_0),
        .I4(Q[0]),
        .I5(\act_this_rank_r_reg[0]_0 ),
        .O(auto_pre_r_lcl_reg));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_91_out),
        .Q(bm_end_r1_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4055404055555555)) 
    col_wait_r_i_1__2
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(\grant_r_reg[3]_0 [0]),
        .I2(\act_this_rank_r_reg[0]_0 ),
        .I3(Q[0]),
        .I4(col_wait_r_reg_0),
        .I5(\q_entry_r_reg[1] ),
        .O(col_wait_r_reg_1));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_reg_1),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0200000000000000)) 
    demand_act_priority_r_i_1__0
       (.I0(demand_act_priority_r),
        .I1(wait_for_maint_r_lcl_reg),
        .I2(p_90_out),
        .I3(\act_this_rank_r_reg[0]_0 ),
        .I4(ras_timer_zero_r),
        .I5(p_89_out),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hBAAAAAAA)) 
    demand_priority_r_i_3__0
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_i_4__0_n_0),
        .I2(starve_limit_cntr_r[2]),
        .I3(starve_limit_cntr_r[1]),
        .I4(starve_limit_cntr_r[0]),
        .O(demand_priority_r_reg_0));
  LUT5 #(
    .INIT(32'hDFFFDFDF)) 
    demand_priority_r_i_4__0
       (.I0(granted_col_r_reg_0),
        .I1(Q[0]),
        .I2(req_bank_rdy_r),
        .I3(q_has_rd),
        .I4(p_93_out),
        .O(demand_priority_r_i_4__0_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000D00DDDDDDDD)) 
    demanded_prior_r_i_1
       (.I0(demanded_prior_r_reg_0),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_3),
        .I3(demand_priority_r_0),
        .I4(Q[1]),
        .I5(demanded_prior_r_reg_2),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF1055)) 
    \grant_r[1]_i_2__0 
       (.I0(demand_act_priority_r),
        .I1(\grant_r_reg[3]_0 [1]),
        .I2(demand_act_priority_r_2),
        .I3(demand_act_priority_r_reg_1),
        .I4(\grant_r_reg[1]_2 ),
        .I5(head_r_lcl_reg),
        .O(\grant_r_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair774" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[1]_i_4__1 
       (.I0(auto_pre_r_lcl_reg_0),
        .I1(\grant_r_reg[1]_1 ),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(\grant_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \grant_r[2]_i_2__0 
       (.I0(\last_master_r_reg[0] ),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[1]_1 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(\grant_r_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair774" *) 
  LUT5 #(
    .INIT(32'h0000FFF7)) 
    \grant_r[2]_i_3 
       (.I0(ras_timer_zero_r),
        .I1(pre_wait_r),
        .I2(\grant_r_reg[1]_1 ),
        .I3(auto_pre_r_lcl_reg_0),
        .I4(auto_pre_r_lcl_reg_1),
        .O(\grant_r_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair776" *) 
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \grant_r[2]_i_8 
       (.I0(demand_priority_r_0),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_reg_0),
        .I3(Q[0]),
        .I4(demanded_prior_r_reg_2),
        .O(\grant_r_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair776" *) 
  LUT4 #(
    .INIT(16'h04FF)) 
    \grant_r[3]_i_13 
       (.I0(demanded_prior_r_reg_1),
        .I1(demanded_prior_r_reg_0),
        .I2(Q[0]),
        .I3(demanded_prior_r_reg_2),
        .O(\grant_r_reg[3] ));
  LUT2 #(
    .INIT(4'h2)) 
    \grant_r[3]_i_2__2 
       (.I0(\grant_r_reg[1] ),
        .I1(\grant_r_reg[2]_2 ),
        .O(granted_row_r_reg));
  LUT6 #(
    .INIT(64'h0000000000005575)) 
    granted_col_r_i_4
       (.I0(demanded_prior_r_reg_2),
        .I1(Q[0]),
        .I2(demanded_prior_r_reg_0),
        .I3(demanded_prior_r_reg_1),
        .I4(override_demand_r),
        .I5(demand_priority_r_0),
        .O(granted_col_r_reg));
  LUT2 #(
    .INIT(4'h7)) 
    granted_row_r_i_1
       (.I0(granted_row_r_reg),
        .I1(demand_act_priority_r_reg_0),
        .O(granted_row_ns));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(rstdiv0_sync_r1_reg_rep__0));
  LUT6 #(
    .INIT(64'hABAAAAAAFFFFFFFF)) 
    \pre_4_1_1T_arb.granted_pre_r_i_1 
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(auto_pre_r_lcl_reg_0),
        .I2(\grant_r_reg[1]_1 ),
        .I3(pre_wait_r),
        .I4(ras_timer_zero_r),
        .I5(ras_timer_zero_r_reg_1),
        .O(granted_pre_ns));
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[1]_1 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1
       (.I0(pass_open_bank_ns),
        .I1(Q[0]),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__0_n_0),
        .I2(pass_open_bank_r),
        .I3(rstdiv0_sync_r1_reg_rep__19),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__0
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[1]_1 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_wait_r_i_2__0_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000004444FFF4)) 
    \ras_timer_r[0]_i_3__2 
       (.I0(rd_wr_r_lcl_reg),
        .I1(Q[0]),
        .I2(ras_timer_zero_r_reg_0),
        .I3(ras_timer_r[1]),
        .I4(ras_timer_r[0]),
        .I5(rstdiv0_sync_r1_reg_rep__20_0),
        .O(\ras_timer_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_3__2 
       (.I0(bm_end_r1_0),
        .I1(rstdiv0_sync_r1_reg_rep__20),
        .I2(ras_timer_r[0]),
        .I3(ras_timer_r[1]),
        .I4(rd_wr_r_lcl_reg),
        .I5(Q[0]),
        .O(\ras_timer_r_reg[1]_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(ras_timer_r[0]),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(ras_timer_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0C04)) 
    ras_timer_zero_r_i_1__2
       (.I0(ras_timer_zero_r_reg_0),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(ras_timer_r[1]),
        .I3(ras_timer_r[0]),
        .I4(rstdiv0_sync_r1_reg_rep__20),
        .I5(bm_end_r1_0),
        .O(ras_timer_zero_ns));
  LUT2 #(
    .INIT(4'h8)) 
    ras_timer_zero_r_i_2__0
       (.I0(\act_this_rank_r_reg[0]_0 ),
        .I1(\grant_r_reg[3]_0 [0]),
        .O(ras_timer_zero_r_reg_0));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_ns),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_r_lcl_reg),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0002)) 
    \rtp_timer_r[0]_i_1__0 
       (.I0(rtp_timer_r[1]),
        .I1(rtp_timer_r[0]),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .I3(pass_open_bank_r),
        .O(\rtp_timer_r[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__0 
       (.I0(Q[0]),
        .I1(rtp_timer_r[1]),
        .I2(rtp_timer_r[0]),
        .I3(pass_open_bank_r),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .O(\rtp_timer_r[1]_i_1__0_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__0_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__0_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1__0 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair775" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1__0 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair775" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1__0 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00007F0000000000)) 
    \starve_limit_cntr_r[2]_i_2__0 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(granted_col_r_reg_0),
        .I4(Q[0]),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1__0_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1__0_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1__0_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_this_rank_r0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_state" *) 
module mig_7series_0_mig_7series_v2_3_bank_state__parameterized1
   (ras_timer_zero_r_reg_0,
    \act_this_rank_r_reg[0]_0 ,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r,
    demand_act_priority_r,
    act_this_rank_r,
    demanded_prior_r_reg_0,
    demanded_prior_r,
    override_demand_r,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    \grant_r_reg[0] ,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[1] ,
    ras_timer_zero_r_reg_1,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[1]_0 ,
    \grant_r_reg[2] ,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    auto_pre_r_lcl_reg,
    \grant_r_reg[2]_0 ,
    ofs_rdy_r0,
    ofs_rdy_r0_0,
    ofs_rdy_r0_1,
    p_52_out,
    CLK,
    act_wait_ns,
    req_bank_rdy_ns,
    override_demand_ns,
    rstdiv0_sync_r1_reg_rep__0,
    phy_mc_ctl_full,
    rstdiv0_sync_r1_reg_rep__1,
    of_ctl_full_v,
    wr_this_rank_r0,
    rd_wr_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__19,
    \grant_r_reg[2]_1 ,
    \grant_r_reg[2]_2 ,
    \q_entry_r_reg[1] ,
    \grant_r_reg[2]_3 ,
    demanded_prior_r_reg_1,
    demand_priority_r_2,
    demanded_prior_r_reg_2,
    rd_wr_r_lcl_reg_0,
    \order_q_r_reg[0] ,
    \rnk_config_strobe_r_reg[0] ,
    idle_r_lcl_reg,
    req_priority_r,
    q_has_priority,
    \grant_r_reg[2]_4 ,
    auto_pre_r_lcl_reg_0,
    pass_open_bank_ns,
    pass_open_bank_r,
    rstdiv0_sync_r1_reg_rep__20,
    p_48_out,
    tail_r,
    accept_r_reg,
    wait_for_maint_r_lcl_reg,
    p_51_out,
    p_50_out,
    demanded_prior_r_4,
    p_131_out,
    phy_mc_data_full,
    p_14_out,
    p_92_out,
    granted_col_r_reg,
    q_has_rd,
    p_54_out,
    D,
    rstdiv0_sync_r1_reg_rep__24);
  output ras_timer_zero_r_reg_0;
  output \act_this_rank_r_reg[0]_0 ;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demanded_prior_r_reg_0;
  output demanded_prior_r;
  output override_demand_r;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output \grant_r_reg[0] ;
  output \grant_r_reg[0]_0 ;
  output \grant_r_reg[1] ;
  output ras_timer_zero_r_reg_1;
  output \ras_timer_r_reg[0]_0 ;
  output \ras_timer_r_reg[1]_0 ;
  output \grant_r_reg[2] ;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output auto_pre_r_lcl_reg;
  output \grant_r_reg[2]_0 ;
  output ofs_rdy_r0;
  output ofs_rdy_r0_0;
  output ofs_rdy_r0_1;
  input p_52_out;
  input CLK;
  input act_wait_ns;
  input req_bank_rdy_ns;
  input override_demand_ns;
  input rstdiv0_sync_r1_reg_rep__0;
  input phy_mc_ctl_full;
  input rstdiv0_sync_r1_reg_rep__1;
  input [0:0]of_ctl_full_v;
  input wr_this_rank_r0;
  input rd_wr_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__19;
  input [0:0]\grant_r_reg[2]_1 ;
  input [1:0]\grant_r_reg[2]_2 ;
  input \q_entry_r_reg[1] ;
  input \grant_r_reg[2]_3 ;
  input demanded_prior_r_reg_1;
  input demand_priority_r_2;
  input demanded_prior_r_reg_2;
  input rd_wr_r_lcl_reg_0;
  input \order_q_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0] ;
  input idle_r_lcl_reg;
  input req_priority_r;
  input q_has_priority;
  input [0:0]\grant_r_reg[2]_4 ;
  input auto_pre_r_lcl_reg_0;
  input pass_open_bank_ns;
  input pass_open_bank_r;
  input rstdiv0_sync_r1_reg_rep__20;
  input p_48_out;
  input tail_r;
  input accept_r_reg;
  input wait_for_maint_r_lcl_reg;
  input p_51_out;
  input p_50_out;
  input demanded_prior_r_4;
  input p_131_out;
  input phy_mc_data_full;
  input p_14_out;
  input p_92_out;
  input granted_col_r_reg;
  input q_has_rd;
  input p_54_out;
  input [1:0]D;
  input rstdiv0_sync_r1_reg_rep__24;

  wire CLK;
  wire [1:0]D;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire \act_this_rank_r_reg[0]_0 ;
  wire act_wait_ns;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire col_wait_r;
  wire col_wait_r_i_1__0_n_0;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_priority_ns;
  wire demand_priority_r_2;
  wire demand_priority_r_i_3__1_n_0;
  wire demand_priority_r_i_4__1_n_0;
  wire demanded_prior_ns;
  wire demanded_prior_r;
  wire demanded_prior_r_4;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire [0:0]\grant_r_reg[2]_1 ;
  wire [1:0]\grant_r_reg[2]_2 ;
  wire \grant_r_reg[2]_3 ;
  wire [0:0]\grant_r_reg[2]_4 ;
  wire granted_col_r_reg;
  wire idle_r_lcl_reg;
  wire [0:0]of_ctl_full_v;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r0_0;
  wire ofs_rdy_r0_1;
  wire ofs_rdy_r0_2;
  wire \order_q_r_reg[0] ;
  wire override_demand_ns;
  wire override_demand_r;
  wire p_131_out;
  wire p_14_out;
  wire p_48_out;
  wire p_50_out;
  wire p_51_out;
  wire p_52_out;
  wire p_54_out;
  wire p_92_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire phy_mc_cmd_full_r;
  wire phy_mc_ctl_full;
  wire phy_mc_ctl_full_r;
  wire phy_mc_data_full;
  wire pre_bm_end_ns;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__1_n_0;
  wire \q_entry_r_reg[1] ;
  wire q_has_priority;
  wire q_has_rd;
  wire [1:0]ras_timer_r;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_ns;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire req_priority_r;
  wire \rnk_config_strobe_r_reg[0] ;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__1_n_0 ;
  wire \rtp_timer_r[1]_i_1__1_n_0 ;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1__1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1__1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1__1_n_0 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\act_this_rank_r_reg[0]_0 ),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(\act_this_rank_r_reg[0]_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0808080800000800)) 
    auto_pre_r_lcl_i_2__1
       (.I0(p_48_out),
        .I1(tail_r),
        .I2(accept_r_reg),
        .I3(col_wait_r),
        .I4(\grant_r_reg[2]_2 [1]),
        .I5(\act_this_rank_r_reg[0]_0 ),
        .O(auto_pre_r_lcl_reg));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_52_out),
        .Q(ras_timer_zero_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h5555555540554040)) 
    col_wait_r_i_1__0
       (.I0(rstdiv0_sync_r1_reg_rep__19),
        .I1(\grant_r_reg[2]_1 ),
        .I2(\act_this_rank_r_reg[0]_0 ),
        .I3(\grant_r_reg[2]_2 [1]),
        .I4(col_wait_r),
        .I5(\q_entry_r_reg[1] ),
        .O(col_wait_r_i_1__0_n_0));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_i_1__0_n_0),
        .Q(col_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0200000000000000)) 
    demand_act_priority_r_i_1__1
       (.I0(demand_act_priority_r),
        .I1(wait_for_maint_r_lcl_reg),
        .I2(p_51_out),
        .I3(\act_this_rank_r_reg[0]_0 ),
        .I4(ras_timer_zero_r),
        .I5(p_50_out),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8888888800008880)) 
    demand_priority_r_i_1__0
       (.I0(col_wait_r_i_1__0_n_0),
        .I1(idle_r_lcl_reg),
        .I2(req_priority_r),
        .I3(q_has_priority),
        .I4(\order_q_r_reg[0] ),
        .I5(demand_priority_r_i_3__1_n_0),
        .O(demand_priority_ns));
  LUT5 #(
    .INIT(32'hBAAAAAAA)) 
    demand_priority_r_i_3__1
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_i_4__1_n_0),
        .I2(starve_limit_cntr_r[2]),
        .I3(starve_limit_cntr_r[1]),
        .I4(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_3__1_n_0));
  LUT5 #(
    .INIT(32'hDFFFDFDF)) 
    demand_priority_r_i_4__1
       (.I0(granted_col_r_reg),
        .I1(\grant_r_reg[2]_2 [1]),
        .I2(req_bank_rdy_r),
        .I3(q_has_rd),
        .I4(p_54_out),
        .O(demand_priority_r_i_4__1_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0DDD0D0)) 
    demanded_prior_r_i_1__2
       (.I0(demanded_prior_r_reg_0),
        .I1(demanded_prior_r),
        .I2(demanded_prior_r_reg_2),
        .I3(demanded_prior_r_4),
        .I4(demand_priority_r_2),
        .I5(\grant_r_reg[2]_2 [0]),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h5455)) 
    \grant_r[0]_i_4 
       (.I0(\grant_r_reg[2]_3 ),
        .I1(demand_priority_r_2),
        .I2(override_demand_r),
        .I3(\grant_r_reg[1] ),
        .O(\grant_r_reg[0]_0 ));
  LUT4 #(
    .INIT(16'hAABA)) 
    \grant_r[1]_i_5__1 
       (.I0(demanded_prior_r_reg_2),
        .I1(demanded_prior_r),
        .I2(demanded_prior_r_reg_0),
        .I3(\grant_r_reg[2]_2 [1]),
        .O(\grant_r_reg[1] ));
  LUT5 #(
    .INIT(32'h00004044)) 
    \grant_r[2]_i_5 
       (.I0(\order_q_r_reg[0] ),
        .I1(col_wait_r),
        .I2(demanded_prior_r_reg_0),
        .I3(demanded_prior_r_reg_1),
        .I4(\rnk_config_strobe_r_reg[0] ),
        .O(\grant_r_reg[2] ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \grant_r[3]_i_11__0 
       (.I0(\grant_r_reg[2]_3 ),
        .I1(demanded_prior_r_reg_0),
        .I2(override_demand_r),
        .I3(demanded_prior_r_reg_1),
        .O(\grant_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair784" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_4__2 
       (.I0(auto_pre_r_lcl_reg_0),
        .I1(\grant_r_reg[2]_4 ),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(\grant_r_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair786" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1
       (.I0(phy_mc_ctl_full_r),
        .I1(phy_mc_cmd_full_r),
        .I2(p_131_out),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0));
  (* SOFT_HLUTNM = "soft_lutpair786" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__0
       (.I0(phy_mc_ctl_full_r),
        .I1(phy_mc_cmd_full_r),
        .I2(p_14_out),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_0));
  (* SOFT_HLUTNM = "soft_lutpair787" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__1
       (.I0(phy_mc_ctl_full_r),
        .I1(phy_mc_cmd_full_r),
        .I2(rd_wr_r_lcl_reg),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_2));
  (* SOFT_HLUTNM = "soft_lutpair787" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__2
       (.I0(phy_mc_ctl_full_r),
        .I1(phy_mc_cmd_full_r),
        .I2(p_92_out),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_1));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0_2),
        .Q(ofs_rdy_r),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE override_demand_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(override_demand_ns),
        .Q(override_demand_r),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    phy_mc_cmd_full_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(of_ctl_full_v),
        .Q(phy_mc_cmd_full_r),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE #(
    .INIT(1'b0)) 
    phy_mc_ctl_full_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_mc_ctl_full),
        .Q(phy_mc_ctl_full_r),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* SOFT_HLUTNM = "soft_lutpair784" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__2
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[2]_4 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__2
       (.I0(pass_open_bank_ns),
        .I1(\grant_r_reg[2]_2 [1]),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__2
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__1_n_0),
        .I2(pass_open_bank_r),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__1
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[2]_4 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_wait_r_i_2__1_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000000054FF)) 
    \ras_timer_r[0]_i_3 
       (.I0(ras_timer_r[0]),
        .I1(ras_timer_zero_r_reg_1),
        .I2(ras_timer_r[1]),
        .I3(rd_wr_r_lcl_reg_0),
        .I4(ras_timer_zero_r_reg_0),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(\ras_timer_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_3 
       (.I0(ras_timer_zero_r_reg_0),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(ras_timer_r[0]),
        .I3(ras_timer_r[1]),
        .I4(rd_wr_r_lcl_reg),
        .I5(\grant_r_reg[2]_2 [1]),
        .O(\ras_timer_r_reg[1]_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(ras_timer_r[0]),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(ras_timer_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0C04)) 
    ras_timer_zero_r_i_1
       (.I0(ras_timer_zero_r_reg_1),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(ras_timer_r[1]),
        .I3(ras_timer_r[0]),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .I5(ras_timer_zero_r_reg_0),
        .O(ras_timer_zero_ns));
  LUT2 #(
    .INIT(4'h8)) 
    ras_timer_zero_r_i_2__1
       (.I0(\act_this_rank_r_reg[0]_0 ),
        .I1(\grant_r_reg[2]_1 ),
        .O(ras_timer_zero_r_reg_1));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_ns),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_r_lcl_reg),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0002)) 
    \rtp_timer_r[0]_i_1__1 
       (.I0(rtp_timer_r[1]),
        .I1(rtp_timer_r[0]),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .I3(pass_open_bank_r),
        .O(\rtp_timer_r[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__1 
       (.I0(\grant_r_reg[2]_2 [1]),
        .I1(rtp_timer_r[1]),
        .I2(rtp_timer_r[0]),
        .I3(pass_open_bank_r),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .O(\rtp_timer_r[1]_i_1__1_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__1_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__1_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1__1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r),
        .O(\starve_limit_cntr_r[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair785" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1__1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r),
        .O(\starve_limit_cntr_r[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair785" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1__1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r),
        .O(\starve_limit_cntr_r[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00007F0000000000)) 
    \starve_limit_cntr_r[2]_i_2__1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(granted_col_r_reg),
        .I4(\grant_r_reg[2]_2 [1]),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1__1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1__1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1__1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_this_rank_r0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_bank_state" *) 
module mig_7series_0_mig_7series_v2_3_bank_state__parameterized2
   (ras_timer_zero_r_reg_0,
    \act_this_rank_r_reg[0]_0 ,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    col_wait_r_reg_1,
    demand_act_priority_r,
    act_this_rank_r,
    demanded_prior_r_reg_0,
    demanded_prior_r_reg_1,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    \grant_r_reg[3] ,
    ras_timer_zero_r_reg_1,
    \grant_r_reg[1] ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[1]_0 ,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    auto_pre_r_lcl_reg,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[1]_1 ,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \grant_r_reg[0] ,
    \grant_r_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[10] ,
    demanded_prior_r_reg_2,
    \grant_r_reg[1]_2 ,
    demand_priority_r_reg_0,
    p_13_out,
    CLK,
    act_wait_ns,
    req_bank_rdy_ns,
    demand_priority_ns,
    rstdiv0_sync_r1_reg_rep__0,
    ofs_rdy_r0,
    wr_this_rank_r0,
    rd_wr_r_lcl_reg,
    rstdiv0_sync_r1_reg_rep__19,
    \grant_r_reg[3]_0 ,
    Q,
    \q_entry_r_reg[1] ,
    override_demand_r,
    demanded_prior_r_reg_3,
    demanded_prior_r_reg_4,
    demand_priority_r_0,
    \grant_r_reg[3]_1 ,
    \req_row_r_lcl_reg[10] ,
    cs_en2,
    rd_wr_r_lcl_reg_0,
    auto_pre_r_lcl_reg_0,
    pass_open_bank_ns,
    pass_open_bank_r,
    rstdiv0_sync_r1_reg_rep__20,
    p_9_out,
    tail_r,
    accept_r_reg,
    act_wait_r_lcl_reg_0,
    act_wait_r_lcl_reg_1,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    inhbt_act_faw_r,
    act_wait_r_lcl_reg_2,
    auto_pre_r_lcl_reg_1,
    \last_master_r_reg[2] ,
    \req_row_r_lcl_reg[10]_0 ,
    p_115_out,
    \grant_r_reg[3]_2 ,
    wait_for_maint_r_lcl_reg,
    p_12_out,
    p_11_out,
    demanded_prior_r_2,
    granted_col_r_reg,
    q_has_rd,
    p_15_out,
    D,
    rstdiv0_sync_r1_reg_rep__24);
  output ras_timer_zero_r_reg_0;
  output \act_this_rank_r_reg[0]_0 ;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output col_wait_r_reg_1;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demanded_prior_r_reg_0;
  output demanded_prior_r_reg_1;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output \grant_r_reg[3] ;
  output ras_timer_zero_r_reg_1;
  output \grant_r_reg[1] ;
  output \cmd_pipe_plus.mc_address_reg[38] ;
  output \ras_timer_r_reg[0]_0 ;
  output \ras_timer_r_reg[1]_0 ;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output auto_pre_r_lcl_reg;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[1]_1 ;
  output \pre_4_1_1T_arb.granted_pre_r_reg ;
  output \grant_r_reg[0] ;
  output \grant_r_reg[2] ;
  output \cmd_pipe_plus.mc_address_reg[10] ;
  output demanded_prior_r_reg_2;
  output \grant_r_reg[1]_2 ;
  output demand_priority_r_reg_0;
  input p_13_out;
  input CLK;
  input act_wait_ns;
  input req_bank_rdy_ns;
  input demand_priority_ns;
  input rstdiv0_sync_r1_reg_rep__0;
  input ofs_rdy_r0;
  input wr_this_rank_r0;
  input rd_wr_r_lcl_reg;
  input rstdiv0_sync_r1_reg_rep__19;
  input [2:0]\grant_r_reg[3]_0 ;
  input [1:0]Q;
  input \q_entry_r_reg[1] ;
  input override_demand_r;
  input demanded_prior_r_reg_3;
  input demanded_prior_r_reg_4;
  input demand_priority_r_0;
  input [0:0]\grant_r_reg[3]_1 ;
  input [0:0]\req_row_r_lcl_reg[10] ;
  input cs_en2;
  input rd_wr_r_lcl_reg_0;
  input auto_pre_r_lcl_reg_0;
  input pass_open_bank_ns;
  input pass_open_bank_r;
  input rstdiv0_sync_r1_reg_rep__20;
  input p_9_out;
  input tail_r;
  input accept_r_reg;
  input act_wait_r_lcl_reg_0;
  input act_wait_r_lcl_reg_1;
  input \generate_maint_cmds.insert_maint_r_lcl_reg ;
  input inhbt_act_faw_r;
  input act_wait_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_1;
  input \last_master_r_reg[2] ;
  input [0:0]\req_row_r_lcl_reg[10]_0 ;
  input p_115_out;
  input \grant_r_reg[3]_2 ;
  input wait_for_maint_r_lcl_reg;
  input p_12_out;
  input p_11_out;
  input demanded_prior_r_2;
  input granted_col_r_reg;
  input q_has_rd;
  input p_15_out;
  input [1:0]D;
  input rstdiv0_sync_r1_reg_rep__24;

  wire CLK;
  wire [1:0]D;
  wire [1:0]Q;
  wire accept_r_reg;
  wire [0:0]act_this_rank_r;
  wire \act_this_rank_r_reg[0]_0 ;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire act_wait_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire \cmd_pipe_plus.mc_address_reg[38] ;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire cs_en2;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_priority_ns;
  wire demand_priority_r_0;
  wire demand_priority_r_i_4__2_n_0;
  wire demand_priority_r_reg_0;
  wire demanded_prior_ns;
  wire demanded_prior_r_2;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire demanded_prior_r_reg_3;
  wire demanded_prior_r_reg_4;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[3] ;
  wire [2:0]\grant_r_reg[3]_0 ;
  wire [0:0]\grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_2 ;
  wire granted_col_r_reg;
  wire inhbt_act_faw_r;
  wire \last_master_r_reg[2] ;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire override_demand_r;
  wire p_115_out;
  wire p_11_out;
  wire p_12_out;
  wire p_13_out;
  wire p_15_out;
  wire p_9_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__2_n_0;
  wire \q_entry_r_reg[1] ;
  wire q_has_rd;
  wire [1:0]ras_timer_r;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_ns;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire [0:0]\req_row_r_lcl_reg[10] ;
  wire [0:0]\req_row_r_lcl_reg[10]_0 ;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__2_n_0 ;
  wire \rtp_timer_r[1]_i_1__2_n_0 ;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1__2_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1__2_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1__2_n_0 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg;
  wire [0:0]wr_this_rank_r;
  wire wr_this_rank_r0;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\act_this_rank_r_reg[0]_0 ),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(\act_this_rank_r_reg[0]_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0808080800000800)) 
    auto_pre_r_lcl_i_2__2
       (.I0(p_9_out),
        .I1(tail_r),
        .I2(accept_r_reg),
        .I3(col_wait_r_reg_0),
        .I4(Q[1]),
        .I5(\act_this_rank_r_reg[0]_0 ),
        .O(auto_pre_r_lcl_reg));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_13_out),
        .Q(ras_timer_zero_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h7F7F7F7F007F7F7F)) 
    \cmd_pipe_plus.mc_address[10]_i_3 
       (.I0(\act_this_rank_r_reg[0]_0 ),
        .I1(\grant_r_reg[3]_0 [2]),
        .I2(\req_row_r_lcl_reg[10] ),
        .I3(\req_row_r_lcl_reg[10]_0 ),
        .I4(p_115_out),
        .I5(\grant_r_reg[3]_2 ),
        .O(\cmd_pipe_plus.mc_address_reg[10] ));
  (* SOFT_HLUTNM = "soft_lutpair795" *) 
  LUT4 #(
    .INIT(16'h80FF)) 
    \cmd_pipe_plus.mc_address[38]_i_3 
       (.I0(\act_this_rank_r_reg[0]_0 ),
        .I1(\grant_r_reg[3]_1 ),
        .I2(\req_row_r_lcl_reg[10] ),
        .I3(cs_en2),
        .O(\cmd_pipe_plus.mc_address_reg[38] ));
  LUT6 #(
    .INIT(64'h5555555540554040)) 
    col_wait_r_i_1__1
       (.I0(rstdiv0_sync_r1_reg_rep__19),
        .I1(\grant_r_reg[3]_0 [2]),
        .I2(\act_this_rank_r_reg[0]_0 ),
        .I3(Q[1]),
        .I4(col_wait_r_reg_0),
        .I5(\q_entry_r_reg[1] ),
        .O(col_wait_r_reg_1));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_reg_1),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0200000000000000)) 
    demand_act_priority_r_i_1
       (.I0(demand_act_priority_r),
        .I1(wait_for_maint_r_lcl_reg),
        .I2(p_12_out),
        .I3(\act_this_rank_r_reg[0]_0 ),
        .I4(ras_timer_zero_r),
        .I5(p_11_out),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hBAAAAAAA)) 
    demand_priority_r_i_3__2
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_i_4__2_n_0),
        .I2(starve_limit_cntr_r[2]),
        .I3(starve_limit_cntr_r[1]),
        .I4(starve_limit_cntr_r[0]),
        .O(demand_priority_r_reg_0));
  LUT5 #(
    .INIT(32'hDFFFDFDF)) 
    demand_priority_r_i_4__2
       (.I0(granted_col_r_reg),
        .I1(Q[1]),
        .I2(req_bank_rdy_r),
        .I3(q_has_rd),
        .I4(p_15_out),
        .O(demand_priority_r_i_4__2_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000D00DDDDDDDD)) 
    demanded_prior_r_i_1__0
       (.I0(demanded_prior_r_reg_0),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_2),
        .I3(demand_priority_r_0),
        .I4(Q[0]),
        .I5(demanded_prior_r_reg_4),
        .O(demanded_prior_ns));
  LUT6 #(
    .INIT(64'h0404040404FF0404)) 
    demanded_prior_r_i_2
       (.I0(demanded_prior_r_reg_1),
        .I1(demanded_prior_r_reg_0),
        .I2(Q[1]),
        .I3(demanded_prior_r_2),
        .I4(demand_priority_r_0),
        .I5(Q[0]),
        .O(demanded_prior_r_reg_2));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_1),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00000080)) 
    \grant_r[0]_i_2 
       (.I0(\last_master_r_reg[2] ),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[3]_1 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(\grant_r_reg[0] ));
  LUT5 #(
    .INIT(32'h0000FFF7)) 
    \grant_r[0]_i_3 
       (.I0(ras_timer_zero_r),
        .I1(pre_wait_r),
        .I2(\grant_r_reg[3]_1 ),
        .I3(auto_pre_r_lcl_reg_0),
        .I4(auto_pre_r_lcl_reg_1),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \grant_r[1]_i_6 
       (.I0(ras_timer_zero_r_reg_1),
        .I1(act_wait_r_lcl_reg_0),
        .I2(\grant_r_reg[3]_0 [1]),
        .I3(act_wait_r_lcl_reg_1),
        .I4(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .I5(inhbt_act_faw_r),
        .O(\grant_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0000000000005575)) 
    \grant_r[1]_i_8__0 
       (.I0(demanded_prior_r_reg_4),
        .I1(Q[1]),
        .I2(demanded_prior_r_reg_0),
        .I3(demanded_prior_r_reg_1),
        .I4(override_demand_r),
        .I5(demand_priority_r_0),
        .O(\grant_r_reg[1] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \grant_r[1]_i_9 
       (.I0(ras_timer_zero_r_reg_1),
        .I1(act_wait_r_lcl_reg_0),
        .I2(\grant_r_reg[3]_0 [0]),
        .I3(act_wait_r_lcl_reg_2),
        .I4(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .I5(inhbt_act_faw_r),
        .O(\grant_r_reg[1]_1 ));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \grant_r[2]_i_6 
       (.I0(demand_priority_r_0),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_reg_0),
        .I3(Q[1]),
        .I4(demanded_prior_r_reg_4),
        .O(\grant_r_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair793" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_5__0 
       (.I0(auto_pre_r_lcl_reg_0),
        .I1(\grant_r_reg[3]_1 ),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(\grant_r_reg[2] ));
  LUT6 #(
    .INIT(64'h10101010101010FF)) 
    \grant_r[3]_i_9__0 
       (.I0(demanded_prior_r_reg_0),
        .I1(override_demand_r),
        .I2(demanded_prior_r_reg_3),
        .I3(ras_timer_zero_r_reg_1),
        .I4(col_wait_r_reg_0),
        .I5(\q_entry_r_reg[1] ),
        .O(\grant_r_reg[3] ));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(rstdiv0_sync_r1_reg_rep__0));
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__1
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[3]_1 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__1
       (.I0(pass_open_bank_ns),
        .I1(Q[1]),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__1
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__2_n_0),
        .I2(pass_open_bank_r),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  (* SOFT_HLUTNM = "soft_lutpair793" *) 
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__2
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\grant_r_reg[3]_1 ),
        .I4(auto_pre_r_lcl_reg_0),
        .O(pre_wait_r_i_2__2_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000000055FD)) 
    \ras_timer_r[0]_i_3__0 
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(ras_timer_zero_r_reg_1),
        .I2(ras_timer_r[1]),
        .I3(ras_timer_r[0]),
        .I4(ras_timer_zero_r_reg_0),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(\ras_timer_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_3__0 
       (.I0(ras_timer_zero_r_reg_0),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(ras_timer_r[0]),
        .I3(ras_timer_r[1]),
        .I4(rd_wr_r_lcl_reg),
        .I5(Q[1]),
        .O(\ras_timer_r_reg[1]_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(ras_timer_r[0]),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(ras_timer_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0C04)) 
    ras_timer_zero_r_i_1__0
       (.I0(ras_timer_zero_r_reg_1),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(ras_timer_r[1]),
        .I3(ras_timer_r[0]),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .I5(ras_timer_zero_r_reg_0),
        .O(ras_timer_zero_ns));
  (* SOFT_HLUTNM = "soft_lutpair795" *) 
  LUT2 #(
    .INIT(4'h8)) 
    ras_timer_zero_r_i_2__2
       (.I0(\act_this_rank_r_reg[0]_0 ),
        .I1(\grant_r_reg[3]_0 [2]),
        .O(ras_timer_zero_r_reg_1));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_ns),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_r_lcl_reg),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0002)) 
    \rtp_timer_r[0]_i_1__2 
       (.I0(rtp_timer_r[1]),
        .I1(rtp_timer_r[0]),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .I3(pass_open_bank_r),
        .O(\rtp_timer_r[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__2 
       (.I0(Q[1]),
        .I1(rtp_timer_r[1]),
        .I2(rtp_timer_r[0]),
        .I3(pass_open_bank_r),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .O(\rtp_timer_r[1]_i_1__2_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__2_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__2_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1__2 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair794" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1__2 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair794" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1__2 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00007F0000000000)) 
    \starve_limit_cntr_r[2]_i_2__2 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(granted_col_r_reg),
        .I4(Q[1]),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1__2_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1__2_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1__2_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_this_rank_r0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_clk_ibuf" *) 
module mig_7series_0_mig_7series_v2_3_clk_ibuf
   (mmcm_clk,
    sys_clk_i);
  output mmcm_clk;
  input sys_clk_i;

  (* RTL_KEEP = "true" *) (* syn_keep = "1" *) wire sys_clk_ibufg;

  assign mmcm_clk = sys_clk_ibufg;
  assign sys_clk_ibufg = sys_clk_i;
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_col_mach" *) 
module mig_7series_0_mig_7series_v2_3_col_mach
   (col_wr_data_buf_addr_r,
    \read_fifo.tail_r_reg[3]_0 ,
    \read_fifo.fifo_out_data_r_reg[5]_0 ,
    \read_fifo.tail_r_reg[2]_0 ,
    \read_fifo.tail_r_reg[2]_1 ,
    \read_fifo.tail_r_reg[2]_2 ,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    mc_read_idle_r_reg,
    mc_ref_zq_wip_ns,
    app_rd_data_end_ns,
    \not_strict_mode.app_rd_data_end_reg ,
    CLK,
    col_data_buf_addr,
    ADDRC,
    DIC,
    col_rd_wr_r,
    mc_cmd,
    rstdiv0_sync_r1_reg_rep__21,
    \read_fifo.tail_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    init_complete_r1_timing_reg,
    maint_ref_zq_wip,
    \read_fifo.fifo_out_data_r_reg[4]_0 ,
    \not_strict_mode.status_ram.rd_buf_we_r1_reg ,
    rstdiv0_sync_r1_reg_rep__18,
    init_complete_r1_timing_reg_0,
    init_complete_r1_timing_reg_1,
    rstdiv0_sync_r1_reg_rep,
    E);
  output [4:0]col_wr_data_buf_addr_r;
  output \read_fifo.tail_r_reg[3]_0 ;
  output \read_fifo.fifo_out_data_r_reg[5]_0 ;
  output \read_fifo.tail_r_reg[2]_0 ;
  output \read_fifo.tail_r_reg[2]_1 ;
  output \read_fifo.tail_r_reg[2]_2 ;
  output \cmd_pipe_plus.mc_wrdata_en_reg ;
  output mc_read_idle_r_reg;
  output mc_ref_zq_wip_ns;
  output app_rd_data_end_ns;
  output [7:0]\not_strict_mode.app_rd_data_end_reg ;
  input CLK;
  input [4:0]col_data_buf_addr;
  input [3:0]ADDRC;
  input [0:0]DIC;
  input col_rd_wr_r;
  input [0:0]mc_cmd;
  input rstdiv0_sync_r1_reg_rep__21;
  input \read_fifo.tail_r_reg[1]_0 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input init_complete_r1_timing_reg;
  input maint_ref_zq_wip;
  input \read_fifo.fifo_out_data_r_reg[4]_0 ;
  input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ;
  input rstdiv0_sync_r1_reg_rep__18;
  input init_complete_r1_timing_reg_0;
  input init_complete_r1_timing_reg_1;
  input rstdiv0_sync_r1_reg_rep;
  input [0:0]E;

  wire [3:0]ADDRC;
  wire CLK;
  wire [0:0]DIC;
  wire [0:0]E;
  wire app_rd_data_end_ns;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire [4:0]col_data_buf_addr;
  wire col_rd_wr_r;
  wire col_rd_wr_r2;
  wire [4:0]col_wr_data_buf_addr_r;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire init_complete_r1_timing_reg;
  wire init_complete_r1_timing_reg_0;
  wire init_complete_r1_timing_reg_1;
  wire maint_ref_zq_wip;
  wire [0:0]mc_cmd;
  wire mc_read_idle_r_reg;
  wire mc_ref_zq_wip_ns;
  wire mc_ref_zq_wip_r_i_2_n_0;
  wire [7:0]\not_strict_mode.app_rd_data_end_reg ;
  wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ;
  wire [4:0]p_0_in;
  wire [1:0]p_0_out;
  wire [1:0]p_3_out;
  wire [1:0]p_4_out;
  wire [1:0]p_5_out;
  wire \read_fifo.fifo_out_data_r_reg[4]_0 ;
  wire \read_fifo.fifo_out_data_r_reg[5]_0 ;
  wire \read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ;
  wire [4:0]\read_fifo.head_r_reg__0 ;
  wire \read_fifo.tail_r[2]_i_1_n_0 ;
  wire \read_fifo.tail_r[3]_i_1_n_0 ;
  wire \read_fifo.tail_r[4]_i_1_n_0 ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire \read_fifo.tail_r_reg[2]_0 ;
  wire \read_fifo.tail_r_reg[2]_1 ;
  wire \read_fifo.tail_r_reg[2]_2 ;
  wire \read_fifo.tail_r_reg[3]_0 ;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sent_col_r2;
  wire [4:4]tail_r;
  wire [1:0]\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED ;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED ;

  LUT2 #(
    .INIT(4'h2)) 
    \cmd_pipe_plus.mc_wrdata_en_i_1 
       (.I0(sent_col_r2),
        .I1(col_rd_wr_r2),
        .O(\cmd_pipe_plus.mc_wrdata_en_reg ));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_data_buf_addr[0]),
        .Q(col_wr_data_buf_addr_r[0]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_data_buf_addr[1]),
        .Q(col_wr_data_buf_addr_r[1]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_data_buf_addr[2]),
        .Q(col_wr_data_buf_addr_r[2]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_data_buf_addr[3]),
        .Q(col_wr_data_buf_addr_r[3]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_data_buf_addr[4]),
        .Q(col_wr_data_buf_addr_r[4]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h09000009)) 
    mc_read_idle_r_i_1
       (.I0(tail_r),
        .I1(\read_fifo.head_r_reg__0 [4]),
        .I2(mc_ref_zq_wip_r_i_2_n_0),
        .I3(\read_fifo.head_r_reg__0 [3]),
        .I4(\read_fifo.tail_r_reg[3]_0 ),
        .O(mc_read_idle_r_reg));
  LUT6 #(
    .INIT(64'h0082000000000082)) 
    mc_ref_zq_wip_r_i_1
       (.I0(maint_ref_zq_wip),
        .I1(tail_r),
        .I2(\read_fifo.head_r_reg__0 [4]),
        .I3(mc_ref_zq_wip_r_i_2_n_0),
        .I4(\read_fifo.head_r_reg__0 [3]),
        .I5(\read_fifo.tail_r_reg[3]_0 ),
        .O(mc_ref_zq_wip_ns));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    mc_ref_zq_wip_r_i_2
       (.I0(\read_fifo.head_r_reg__0 [1]),
        .I1(\read_fifo.tail_r_reg[2]_1 ),
        .I2(\read_fifo.head_r_reg__0 [2]),
        .I3(\read_fifo.tail_r_reg[2]_0 ),
        .I4(\read_fifo.tail_r_reg[2]_2 ),
        .I5(\read_fifo.head_r_reg__0 [0]),
        .O(mc_ref_zq_wip_r_i_2_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.app_rd_data_end_i_1 
       (.I0(\not_strict_mode.app_rd_data_end_reg [7]),
        .I1(\read_fifo.fifo_out_data_r_reg[4]_0 ),
        .I2(\not_strict_mode.status_ram.rd_buf_we_r1_reg ),
        .O(app_rd_data_end_ns));
  FDRE \offset_pipe_1.col_rd_wr_r2_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(col_rd_wr_r),
        .Q(col_rd_wr_r2),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_3_out[0]),
        .Q(\not_strict_mode.app_rd_data_end_reg [0]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_3_out[1]),
        .Q(\not_strict_mode.app_rd_data_end_reg [1]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_4_out[0]),
        .Q(\not_strict_mode.app_rd_data_end_reg [2]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_4_out[1]),
        .Q(\not_strict_mode.app_rd_data_end_reg [3]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_5_out[0]),
        .Q(\not_strict_mode.app_rd_data_end_reg [4]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_5_out[1]),
        .Q(\not_strict_mode.app_rd_data_end_reg [5]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_out[0]),
        .Q(\not_strict_mode.app_rd_data_end_reg [6]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_out[1]),
        .Q(\not_strict_mode.app_rd_data_end_reg [7]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \read_fifo.fifo_ram[0].RAM32M0 
       (.ADDRA({\read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ,ADDRC}),
        .ADDRB({\read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ,ADDRC}),
        .ADDRC({\read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ,ADDRC}),
        .ADDRD(\read_fifo.head_r_reg__0 ),
        .DIA(col_data_buf_addr[4:3]),
        .DIB(col_data_buf_addr[2:1]),
        .DIC({col_data_buf_addr[0],1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(p_5_out),
        .DOB(p_4_out),
        .DOC(p_3_out),
        .DOD(\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(1'b1));
  LUT6 #(
    .INIT(64'h5655555555555555)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_17 
       (.I0(\read_fifo.tail_r_reg[2]_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I3(\read_fifo.tail_r_reg[2]_1 ),
        .I4(init_complete_r1_timing_reg),
        .I5(\read_fifo.tail_r_reg[2]_2 ),
        .O(\read_fifo.fifo_out_data_r_reg[5]_0 ));
  LUT4 #(
    .INIT(16'h1540)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_6 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(\read_fifo.tail_r_reg[3]_0 ),
        .I2(\read_fifo.tail_r_reg[1]_0 ),
        .I3(tail_r),
        .O(\read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \read_fifo.fifo_ram[1].RAM32M0 
       (.ADDRA({\read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ,ADDRC}),
        .ADDRB({\read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ,ADDRC}),
        .ADDRC({\read_fifo.fifo_ram[0].RAM32M0_i_6_n_0 ,ADDRC}),
        .ADDRD(\read_fifo.head_r_reg__0 ),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b1,DIC}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED [1:0]),
        .DOC(p_0_out),
        .DOD(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(1'b1));
  LUT1 #(
    .INIT(2'h1)) 
    \read_fifo.head_r[0]_i_1 
       (.I0(\read_fifo.head_r_reg__0 [0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_fifo.head_r[1]_i_1 
       (.I0(\read_fifo.head_r_reg__0 [0]),
        .I1(\read_fifo.head_r_reg__0 [1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \read_fifo.head_r[2]_i_1 
       (.I0(\read_fifo.head_r_reg__0 [2]),
        .I1(\read_fifo.head_r_reg__0 [1]),
        .I2(\read_fifo.head_r_reg__0 [0]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \read_fifo.head_r[3]_i_1 
       (.I0(\read_fifo.head_r_reg__0 [3]),
        .I1(\read_fifo.head_r_reg__0 [0]),
        .I2(\read_fifo.head_r_reg__0 [1]),
        .I3(\read_fifo.head_r_reg__0 [2]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \read_fifo.head_r[4]_i_1 
       (.I0(\read_fifo.head_r_reg__0 [4]),
        .I1(\read_fifo.head_r_reg__0 [2]),
        .I2(\read_fifo.head_r_reg__0 [1]),
        .I3(\read_fifo.head_r_reg__0 [0]),
        .I4(\read_fifo.head_r_reg__0 [3]),
        .O(p_0_in[4]));
  FDRE \read_fifo.head_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[0]),
        .Q(\read_fifo.head_r_reg__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \read_fifo.head_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[1]),
        .Q(\read_fifo.head_r_reg__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \read_fifo.head_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[2]),
        .Q(\read_fifo.head_r_reg__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \read_fifo.head_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[3]),
        .Q(\read_fifo.head_r_reg__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \read_fifo.head_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[4]),
        .Q(\read_fifo.head_r_reg__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep));
  LUT6 #(
    .INIT(64'hFFFFFF7F00000080)) 
    \read_fifo.tail_r[2]_i_1 
       (.I0(\read_fifo.tail_r_reg[2]_2 ),
        .I1(init_complete_r1_timing_reg),
        .I2(\read_fifo.tail_r_reg[2]_1 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I5(\read_fifo.tail_r_reg[2]_0 ),
        .O(\read_fifo.tail_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_fifo.tail_r[3]_i_1 
       (.I0(\read_fifo.tail_r_reg[3]_0 ),
        .I1(\read_fifo.tail_r_reg[1]_0 ),
        .O(\read_fifo.tail_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \read_fifo.tail_r[4]_i_1 
       (.I0(\read_fifo.tail_r_reg[3]_0 ),
        .I1(\read_fifo.tail_r_reg[1]_0 ),
        .I2(tail_r),
        .O(\read_fifo.tail_r[4]_i_1_n_0 ));
  FDRE \read_fifo.tail_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r1_timing_reg_0),
        .Q(\read_fifo.tail_r_reg[2]_2 ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \read_fifo.tail_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r1_timing_reg_1),
        .Q(\read_fifo.tail_r_reg[2]_1 ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \read_fifo.tail_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r[2]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg[2]_0 ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \read_fifo.tail_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r[3]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg[3]_0 ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \read_fifo.tail_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r[4]_i_1_n_0 ),
        .Q(tail_r),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE sent_col_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cmd),
        .Q(sent_col_r2),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io
   (\pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    D0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    p_5_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ,
    p_17_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ,
    p_25_in,
    p_30_in,
    p_29_in,
    p_1_in,
    \ddr3_dm[7] ,
    idelay_ld_rst_3,
    rst_r4,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    mc_read_idle_r_reg,
    CLK,
    A_idelay_ce10_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives,
    mc_read_idle_r_reg_0,
    mc_read_idle_r_reg_1,
    mc_read_idle_r_reg_2,
    mc_read_idle_r_reg_3,
    mc_read_idle_r_reg_4,
    mc_read_idle_r_reg_5,
    p_31_out,
    Q0,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q9);
  output \pi_dqs_found_lanes_r1_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[8]_0 ;
  output [3:0]D0;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output p_5_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  output p_17_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  output p_25_in;
  output p_30_in;
  output p_29_in;
  output p_1_in;
  output \ddr3_dm[7] ;
  output idelay_ld_rst_3;
  output rst_r4;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input mc_read_idle_r_reg;
  input CLK;
  input A_idelay_ce10_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives;
  input mc_read_idle_r_reg_0;
  input mc_read_idle_r_reg_1;
  input mc_read_idle_r_reg_2;
  input mc_read_idle_r_reg_3;
  input mc_read_idle_r_reg_4;
  input mc_read_idle_r_reg_5;
  input p_31_out;
  input [3:0]Q0;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q9;

  wire A_idelay_ce10_out;
  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire [0:0]CTSBUS;
  wire [3:0]D0;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire [3:0]Q0;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q9;
  wire \ddr3_dm[7] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_i_1__5_n_0;
  wire \input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire mc_read_idle_r_reg;
  wire mc_read_idle_r_reg_0;
  wire mc_read_idle_r_reg_1;
  wire mc_read_idle_r_reg_2;
  wire mc_read_idle_r_reg_3;
  wire mc_read_idle_r_reg_4;
  wire mc_read_idle_r_reg_5;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_17_in;
  wire p_1_in;
  wire p_25_in;
  wire p_29_in;
  wire p_30_in;
  wire p_31_out;
  wire p_5_in;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire po_oserdes_rst;
  wire rst_r3_reg_srl3_n_0;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(\pi_dqs_found_lanes_r1_reg[8] ),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__5
       (.I0(idelay_ld_rst_3),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__5_n_0));
  FDSE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__5_n_0),
        .Q(idelay_ld_rst_3),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(mc_read_idle_r_reg),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[0].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mc_read_idle_r_reg),
        .DDLY(\input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D0[3]),
        .Q2(D0[2]),
        .Q3(D0[1]),
        .Q4(D0[0]),
        .Q5(\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(mc_read_idle_r_reg_0),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mc_read_idle_r_reg_0),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(mc_read_idle_r_reg_1),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mc_read_idle_r_reg_1),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(mc_read_idle_r_reg_2),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mc_read_idle_r_reg_2),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(mc_read_idle_r_reg_3),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mc_read_idle_r_reg_3),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(mc_read_idle_r_reg_4),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mc_read_idle_r_reg_4),
        .DDLY(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(mc_read_idle_r_reg_5),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mc_read_idle_r_reg_5),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce10_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_31_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_31_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[0].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q0[0]),
        .D2(Q0[1]),
        .D3(Q0[2]),
        .D4(Q0[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_5_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_17_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_25_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_30_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_29_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_1_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\ddr3_dm[7] ));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 " *) 
  SRL16E rst_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(A_rst_primitives),
        .Q(rst_r3_reg_srl3_n_0));
  FDRE rst_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_r3_reg_srl3_n_0),
        .Q(rst_r4),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_11
   (\pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    D0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    p_134_in,
    p_133_in,
    p_138_in,
    p_137_in,
    p_142_in,
    p_141_in,
    p_146_in,
    p_145_in,
    p_150_in,
    p_149_in,
    p_154_in,
    p_153_in,
    p_158_in,
    p_157_in,
    p_13_in,
    \ddr3_dm[3] ,
    idelay_ld_rst,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    p_131_out,
    CLK,
    A_idelay_ce13_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives,
    p_135_out,
    p_139_out,
    p_143_out,
    p_147_out,
    p_151_out,
    p_155_out,
    p_159_out,
    Q0,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q9,
    rst_r4);
  output \pi_dqs_found_lanes_r1_reg[0] ;
  output \pi_dqs_found_lanes_r1_reg[0]_0 ;
  output [3:0]D0;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output p_134_in;
  output p_133_in;
  output p_138_in;
  output p_137_in;
  output p_142_in;
  output p_141_in;
  output p_146_in;
  output p_145_in;
  output p_150_in;
  output p_149_in;
  output p_154_in;
  output p_153_in;
  output p_158_in;
  output p_157_in;
  output p_13_in;
  output \ddr3_dm[3] ;
  output idelay_ld_rst;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input p_131_out;
  input CLK;
  input A_idelay_ce13_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives;
  input p_135_out;
  input p_139_out;
  input p_143_out;
  input p_147_out;
  input p_151_out;
  input p_155_out;
  input p_159_out;
  input [3:0]Q0;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q9;
  input rst_r4;

  wire A_idelay_ce13_out;
  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire [0:0]CTSBUS;
  wire [3:0]D0;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire [3:0]Q0;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q9;
  wire \ddr3_dm[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_i_1_n_0;
  wire \input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_131_out;
  wire p_133_in;
  wire p_134_in;
  wire p_135_out;
  wire p_137_in;
  wire p_138_in;
  wire p_139_out;
  wire p_13_in;
  wire p_141_in;
  wire p_142_in;
  wire p_143_out;
  wire p_145_in;
  wire p_146_in;
  wire p_147_out;
  wire p_149_in;
  wire p_150_in;
  wire p_151_out;
  wire p_153_in;
  wire p_154_in;
  wire p_155_out;
  wire p_157_in;
  wire p_158_in;
  wire p_159_out;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(\pi_dqs_found_lanes_r1_reg[0] ),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1
       (.I0(idelay_ld_rst),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1_n_0));
  FDSE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1_n_0),
        .Q(idelay_ld_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_131_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[0].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_131_out),
        .DDLY(\input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D0[3]),
        .Q2(D0[2]),
        .Q3(D0[1]),
        .Q4(D0[0]),
        .Q5(\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_135_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_135_out),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_139_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_139_out),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_143_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_143_out),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_147_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_147_out),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_151_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_151_out),
        .DDLY(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_155_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_155_out),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce13_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_159_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_159_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[0].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q0[0]),
        .D2(Q0[1]),
        .D3(Q0[2]),
        .D4(Q0[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_134_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_133_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_138_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_137_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_142_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_141_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_146_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_145_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_150_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_149_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_154_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_153_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_158_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_157_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_13_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\ddr3_dm[3] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_5
   (\pi_dqs_found_lanes_r1_reg[4] ,
    \pi_dqs_found_lanes_r1_reg[4]_0 ,
    D0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    p_98_in,
    p_97_in,
    p_102_in,
    p_101_in,
    p_106_in,
    p_105_in,
    p_110_in,
    p_109_in,
    p_114_in,
    p_113_in,
    p_118_in,
    p_117_in,
    p_122_in,
    p_121_in,
    p_126_in,
    p_125_in,
    \ddr3_dm[4] ,
    p_9_in,
    idelay_ld_rst_6,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    p_99_out,
    CLK,
    A_idelay_ce19_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives_reg_1,
    p_103_out,
    p_107_out,
    p_111_out,
    p_115_out,
    p_119_out,
    p_123_out,
    p_127_out,
    Q0,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q9);
  output \pi_dqs_found_lanes_r1_reg[4] ;
  output \pi_dqs_found_lanes_r1_reg[4]_0 ;
  output [3:0]D0;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output p_98_in;
  output p_97_in;
  output p_102_in;
  output p_101_in;
  output p_106_in;
  output p_105_in;
  output p_110_in;
  output p_109_in;
  output p_114_in;
  output p_113_in;
  output p_118_in;
  output p_117_in;
  output p_122_in;
  output p_121_in;
  output p_126_in;
  output p_125_in;
  output \ddr3_dm[4] ;
  output p_9_in;
  output idelay_ld_rst_6;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input p_99_out;
  input CLK;
  input A_idelay_ce19_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives_reg_1;
  input p_103_out;
  input p_107_out;
  input p_111_out;
  input p_115_out;
  input p_119_out;
  input p_123_out;
  input p_127_out;
  input [3:0]Q0;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q9;

  wire A_idelay_ce19_out;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire CLK;
  wire [0:0]CTSBUS;
  wire [3:0]D0;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire [3:0]Q0;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q9;
  wire \ddr3_dm[4] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst_6;
  wire idelay_ld_rst_i_1_n_0;
  wire \input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_101_in;
  wire p_102_in;
  wire p_103_out;
  wire p_105_in;
  wire p_106_in;
  wire p_107_out;
  wire p_109_in;
  wire p_110_in;
  wire p_111_out;
  wire p_113_in;
  wire p_114_in;
  wire p_115_out;
  wire p_117_in;
  wire p_118_in;
  wire p_119_out;
  wire p_121_in;
  wire p_122_in;
  wire p_123_out;
  wire p_125_in;
  wire p_126_in;
  wire p_127_out;
  wire p_97_in;
  wire p_98_in;
  wire p_99_out;
  wire p_9_in;
  wire \pi_dqs_found_lanes_r1_reg[4] ;
  wire \pi_dqs_found_lanes_r1_reg[4]_0 ;
  wire po_oserdes_rst;
  wire rst_r3_reg_srl3_n_0;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(\pi_dqs_found_lanes_r1_reg[4] ),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(\pi_dqs_found_lanes_r1_reg[4]_0 ),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT3 #(
    .INIT(8'hF4)) 
    idelay_ld_rst_i_1
       (.I0(rst_r4),
        .I1(idelay_ld_rst_6),
        .I2(A_rst_primitives_reg_1),
        .O(idelay_ld_rst_i_1_n_0));
  FDRE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1_n_0),
        .Q(idelay_ld_rst_6),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_99_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[0].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_99_out),
        .DDLY(\input_[0].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D0[3]),
        .Q2(D0[2]),
        .Q3(D0[1]),
        .Q4(D0[0]),
        .Q5(\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_103_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_103_out),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_107_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_107_out),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_111_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_111_out),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_115_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_115_out),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_119_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_119_out),
        .DDLY(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_123_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_123_out),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(A_idelay_ce19_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_127_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives_reg_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_127_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[0].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q0[0]),
        .D2(Q0[1]),
        .D3(Q0[2]),
        .D4(Q0[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_98_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_97_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_102_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_101_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_106_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_105_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_110_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_109_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_114_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_113_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_118_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_117_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_122_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_121_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_126_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_125_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_dm[4] ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_9_in));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 " *) 
  SRL16E rst_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(A_rst_primitives_reg_1),
        .Q(rst_r3_reg_srl3_n_0));
  FDRE rst_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_r3_reg_srl3_n_0),
        .Q(rst_r4),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0
   (p_28_in,
    p_27_in,
    D1,
    D2,
    D3,
    D4,
    D6,
    D7,
    D8,
    D9,
    p_162_in,
    p_161_in,
    p_166_in,
    p_165_in,
    p_170_in,
    p_169_in,
    p_174_in,
    p_173_in,
    \ddr3_dm[2] ,
    p_15_in,
    p_178_in,
    p_177_in,
    p_182_in,
    p_181_in,
    p_186_in,
    p_185_in,
    p_190_in,
    p_189_in,
    idelay_ld_rst_0,
    rst_r4,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    p_163_out,
    CLK,
    B_idelay_ce9_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives,
    p_167_out,
    p_171_out,
    p_175_out,
    p_179_out,
    p_183_out,
    p_187_out,
    p_191_out,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q8,
    Q9);
  output p_28_in;
  output p_27_in;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output p_162_in;
  output p_161_in;
  output p_166_in;
  output p_165_in;
  output p_170_in;
  output p_169_in;
  output p_174_in;
  output p_173_in;
  output \ddr3_dm[2] ;
  output p_15_in;
  output p_178_in;
  output p_177_in;
  output p_182_in;
  output p_181_in;
  output p_186_in;
  output p_185_in;
  output p_190_in;
  output p_189_in;
  output idelay_ld_rst_0;
  output rst_r4;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input p_163_out;
  input CLK;
  input B_idelay_ce9_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives;
  input p_167_out;
  input p_171_out;
  input p_175_out;
  input p_179_out;
  input p_183_out;
  input p_187_out;
  input p_191_out;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q8;
  input [3:0]Q9;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire B_idelay_ce9_out;
  wire CLK;
  wire [0:0]CTSBUS;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q8;
  wire [3:0]Q9;
  wire \ddr3_dm[2] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_i_1__0_n_0;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[9].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_15_in;
  wire p_161_in;
  wire p_162_in;
  wire p_163_out;
  wire p_165_in;
  wire p_166_in;
  wire p_167_out;
  wire p_169_in;
  wire p_170_in;
  wire p_171_out;
  wire p_173_in;
  wire p_174_in;
  wire p_175_out;
  wire p_177_in;
  wire p_178_in;
  wire p_179_out;
  wire p_181_in;
  wire p_182_in;
  wire p_183_out;
  wire p_185_in;
  wire p_186_in;
  wire p_187_out;
  wire p_189_in;
  wire p_190_in;
  wire p_191_out;
  wire p_27_in;
  wire p_28_in;
  wire po_oserdes_rst;
  wire rst_r3_reg_srl3_n_0;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(p_28_in),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(p_27_in),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__0
       (.I0(idelay_ld_rst_0),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__0_n_0));
  FDSE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__0_n_0),
        .Q(idelay_ld_rst_0),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_163_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_163_out),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_167_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_167_out),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_171_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_171_out),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_175_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_175_out),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_179_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_179_out),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_183_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_183_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_187_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_187_out),
        .DDLY(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce9_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[9].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_191_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_191_out),
        .DDLY(\input_[9].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_162_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_161_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_166_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_165_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_170_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_169_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_174_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_173_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_dm[2] ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_15_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_178_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_177_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_182_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_181_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q8[0]),
        .D2(Q8[1]),
        .D3(Q8[2]),
        .D4(Q8[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_186_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_185_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_190_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_189_in));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/rst_r3_reg_srl3 " *) 
  SRL16E rst_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(A_rst_primitives),
        .Q(rst_r3_reg_srl3_n_0));
  FDRE rst_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_r3_reg_srl3_n_0),
        .Q(rst_r4),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1
   (\pi_dqs_found_lanes_r1_reg[2] ,
    p_32_in,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    p_194_in,
    p_193_in,
    p_198_in,
    p_197_in,
    p_202_in,
    p_201_in,
    p_206_in,
    p_205_in,
    p_210_in,
    p_209_in,
    p_214_in,
    p_213_in,
    p_218_in,
    p_217_in,
    p_222_in,
    p_221_in,
    p_19_in,
    \ddr3_dm[1] ,
    idelay_ld_rst_1,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    p_195_out,
    CLK,
    C_idelay_ce5_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives,
    p_199_out,
    p_203_out,
    p_207_out,
    p_211_out,
    p_215_out,
    p_219_out,
    p_223_out,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q8,
    Q9,
    rst_r4);
  output \pi_dqs_found_lanes_r1_reg[2] ;
  output p_32_in;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output p_194_in;
  output p_193_in;
  output p_198_in;
  output p_197_in;
  output p_202_in;
  output p_201_in;
  output p_206_in;
  output p_205_in;
  output p_210_in;
  output p_209_in;
  output p_214_in;
  output p_213_in;
  output p_218_in;
  output p_217_in;
  output p_222_in;
  output p_221_in;
  output p_19_in;
  output \ddr3_dm[1] ;
  output idelay_ld_rst_1;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input p_195_out;
  input CLK;
  input C_idelay_ce5_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives;
  input p_199_out;
  input p_203_out;
  input p_207_out;
  input p_211_out;
  input p_215_out;
  input p_219_out;
  input p_223_out;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q8;
  input [3:0]Q9;
  input rst_r4;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire [0:0]CTSBUS;
  wire C_idelay_ce5_out;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q8;
  wire [3:0]Q9;
  wire \ddr3_dm[1] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_i_1__1_n_0;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_193_in;
  wire p_194_in;
  wire p_195_out;
  wire p_197_in;
  wire p_198_in;
  wire p_199_out;
  wire p_19_in;
  wire p_201_in;
  wire p_202_in;
  wire p_203_out;
  wire p_205_in;
  wire p_206_in;
  wire p_207_out;
  wire p_209_in;
  wire p_210_in;
  wire p_211_out;
  wire p_213_in;
  wire p_214_in;
  wire p_215_out;
  wire p_217_in;
  wire p_218_in;
  wire p_219_out;
  wire p_221_in;
  wire p_222_in;
  wire p_223_out;
  wire p_32_in;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(\pi_dqs_found_lanes_r1_reg[2] ),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(p_32_in),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__1
       (.I0(idelay_ld_rst_1),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__1_n_0));
  FDSE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__1_n_0),
        .Q(idelay_ld_rst_1),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_195_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_195_out),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_199_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_199_out),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_203_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_203_out),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_207_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_207_out),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_211_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_211_out),
        .DDLY(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_215_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_215_out),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_219_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_219_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce5_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_223_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_223_out),
        .DDLY(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_194_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_193_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_198_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_197_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_202_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_201_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_206_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_205_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_210_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_209_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_214_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_213_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_218_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_217_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q8[0]),
        .D2(Q8[1]),
        .D3(Q8[2]),
        .D4(Q8[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_222_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_221_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_19_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\ddr3_dm[1] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized2
   (\pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    p_226_in,
    p_225_in,
    p_230_in,
    p_229_in,
    p_234_in,
    p_233_in,
    p_238_in,
    p_237_in,
    p_242_in,
    p_241_in,
    p_246_in,
    p_245_in,
    p_250_in,
    p_249_in,
    p_254_in,
    p_253_in,
    \ddr3_dm[0] ,
    p_21_in,
    idelay_ld_rst_2,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    p_227_out,
    CLK,
    D_idelay_ce1_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives,
    p_231_out,
    p_235_out,
    p_239_out,
    p_243_out,
    p_247_out,
    p_251_out,
    p_255_out,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q8,
    Q9,
    rst_r4);
  output \pi_dqs_found_lanes_r1_reg[3] ;
  output \pi_dqs_found_lanes_r1_reg[3]_0 ;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output p_226_in;
  output p_225_in;
  output p_230_in;
  output p_229_in;
  output p_234_in;
  output p_233_in;
  output p_238_in;
  output p_237_in;
  output p_242_in;
  output p_241_in;
  output p_246_in;
  output p_245_in;
  output p_250_in;
  output p_249_in;
  output p_254_in;
  output p_253_in;
  output \ddr3_dm[0] ;
  output p_21_in;
  output idelay_ld_rst_2;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input p_227_out;
  input CLK;
  input D_idelay_ce1_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives;
  input p_231_out;
  input p_235_out;
  input p_239_out;
  input p_243_out;
  input p_247_out;
  input p_251_out;
  input p_255_out;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q8;
  input [3:0]Q9;
  input rst_r4;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire [0:0]CTSBUS;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire D_idelay_ce1_out;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q8;
  wire [3:0]Q9;
  wire \ddr3_dm[0] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_i_1__2_n_0;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_21_in;
  wire p_225_in;
  wire p_226_in;
  wire p_227_out;
  wire p_229_in;
  wire p_230_in;
  wire p_231_out;
  wire p_233_in;
  wire p_234_in;
  wire p_235_out;
  wire p_237_in;
  wire p_238_in;
  wire p_239_out;
  wire p_241_in;
  wire p_242_in;
  wire p_243_out;
  wire p_245_in;
  wire p_246_in;
  wire p_247_out;
  wire p_249_in;
  wire p_250_in;
  wire p_251_out;
  wire p_253_in;
  wire p_254_in;
  wire p_255_out;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(\pi_dqs_found_lanes_r1_reg[3] ),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__2
       (.I0(idelay_ld_rst_2),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__2_n_0));
  FDSE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__2_n_0),
        .Q(idelay_ld_rst_2),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_227_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_227_out),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_231_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_231_out),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_235_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_235_out),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_239_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_239_out),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_243_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_243_out),
        .DDLY(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_247_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_247_out),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_251_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_251_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(D_idelay_ce1_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_255_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_255_out),
        .DDLY(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_226_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_225_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_230_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_229_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_234_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_233_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_238_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_237_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_242_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_241_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_246_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_245_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_250_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_249_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q8[0]),
        .D2(Q8[1]),
        .D3(Q8[2]),
        .D4(Q8[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_254_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_253_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_dm[0] ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_21_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized3
   (mem_dq_out,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [4:0]mem_dq_out;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [19:0]oserdes_dq;
  input po_oserdes_rst;

  wire [4:0]mem_dq_out;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [19:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[10].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[11].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[1].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[3].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized4
   (\ddr3_addr[3] ,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [11:0]\ddr3_addr[3] ;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [47:0]oserdes_dq;
  input po_oserdes_rst;

  wire [11:0]\ddr3_addr[3] ;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [47:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[0].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[10].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[40]),
        .D2(oserdes_dq[41]),
        .D3(oserdes_dq[42]),
        .D4(oserdes_dq[43]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [10]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[11].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[44]),
        .D2(oserdes_dq[45]),
        .D3(oserdes_dq[46]),
        .D4(oserdes_dq[47]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [11]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[1].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[2].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[3].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[4].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[20]),
        .D2(oserdes_dq[21]),
        .D3(oserdes_dq[22]),
        .D4(oserdes_dq[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[6].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[24]),
        .D2(oserdes_dq[25]),
        .D3(oserdes_dq[26]),
        .D4(oserdes_dq[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[7].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[28]),
        .D2(oserdes_dq[29]),
        .D3(oserdes_dq[30]),
        .D4(oserdes_dq[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[8].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[32]),
        .D2(oserdes_dq[33]),
        .D3(oserdes_dq[34]),
        .D4(oserdes_dq[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[9].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[36]),
        .D2(oserdes_dq[37]),
        .D3(oserdes_dq[38]),
        .D4(oserdes_dq[39]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[3] [9]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized5
   (\ddr3_addr[13] ,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [5:0]\ddr3_addr[13] ;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [23:0]oserdes_dq;
  input po_oserdes_rst;

  wire [5:0]\ddr3_addr[13] ;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [23:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[10].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[20]),
        .D2(oserdes_dq[21]),
        .D3(oserdes_dq[22]),
        .D4(oserdes_dq[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[13] [5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[1].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[13] [0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[2].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[13] [1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[3].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[13] [2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[4].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[13] [3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_addr[13] [4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized6
   (\pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    D1,
    D2,
    D3,
    D4,
    D6,
    D7,
    D8,
    D9,
    p_34_in,
    p_33_in,
    p_38_in,
    p_37_in,
    p_42_in,
    p_41_in,
    p_46_in,
    p_45_in,
    \ddr3_dm[6] ,
    p_3_in,
    p_50_in,
    p_49_in,
    p_54_in,
    p_53_in,
    p_58_in,
    p_57_in,
    p_62_in,
    p_61_in,
    idelay_ld_rst_4,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    p_35_out,
    CLK,
    B_idelay_ce6_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives,
    p_39_out,
    p_43_out,
    p_47_out,
    p_51_out,
    p_55_out,
    p_59_out,
    p_63_out,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q8,
    Q9,
    rst_r4);
  output \pi_dqs_found_lanes_r1_reg[9] ;
  output \pi_dqs_found_lanes_r1_reg[9]_0 ;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output p_34_in;
  output p_33_in;
  output p_38_in;
  output p_37_in;
  output p_42_in;
  output p_41_in;
  output p_46_in;
  output p_45_in;
  output \ddr3_dm[6] ;
  output p_3_in;
  output p_50_in;
  output p_49_in;
  output p_54_in;
  output p_53_in;
  output p_58_in;
  output p_57_in;
  output p_62_in;
  output p_61_in;
  output idelay_ld_rst_4;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input p_35_out;
  input CLK;
  input B_idelay_ce6_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives;
  input p_39_out;
  input p_43_out;
  input p_47_out;
  input p_51_out;
  input p_55_out;
  input p_59_out;
  input p_63_out;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q8;
  input [3:0]Q9;
  input rst_r4;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire B_idelay_ce6_out;
  wire CLK;
  wire [0:0]CTSBUS;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q8;
  wire [3:0]Q9;
  wire \ddr3_dm[6] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_i_1__4_n_0;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[9].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_33_in;
  wire p_34_in;
  wire p_35_out;
  wire p_37_in;
  wire p_38_in;
  wire p_39_out;
  wire p_3_in;
  wire p_41_in;
  wire p_42_in;
  wire p_43_out;
  wire p_45_in;
  wire p_46_in;
  wire p_47_out;
  wire p_49_in;
  wire p_50_in;
  wire p_51_out;
  wire p_53_in;
  wire p_54_in;
  wire p_55_out;
  wire p_57_in;
  wire p_58_in;
  wire p_59_out;
  wire p_61_in;
  wire p_62_in;
  wire p_63_out;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(\pi_dqs_found_lanes_r1_reg[9] ),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__4
       (.I0(idelay_ld_rst_4),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__4_n_0));
  FDSE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__4_n_0),
        .Q(idelay_ld_rst_4),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_35_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_35_out),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_39_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_39_out),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_43_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_43_out),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_47_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_47_out),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_51_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_51_out),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_55_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_55_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_59_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_59_out),
        .DDLY(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(B_idelay_ce6_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[9].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_63_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_63_out),
        .DDLY(\input_[9].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_34_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_33_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_38_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_37_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_42_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_41_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_46_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_45_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(\ddr3_dm[6] ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_3_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_50_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_49_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_54_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_53_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q8[0]),
        .D2(Q8[1]),
        .D3(Q8[2]),
        .D4(Q8[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_58_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_57_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_62_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_61_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_group_io" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized7
   (\pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    p_66_in,
    p_65_in,
    p_70_in,
    p_69_in,
    p_74_in,
    p_73_in,
    p_78_in,
    p_77_in,
    p_82_in,
    p_81_in,
    p_86_in,
    p_85_in,
    p_90_in,
    p_89_in,
    p_94_in,
    p_93_in,
    p_7_in,
    \ddr3_dm[5] ,
    idelay_ld_rst_5,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    iserdes_clkdiv,
    p_67_out,
    CLK,
    C_idelay_ce2_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    A_rst_primitives,
    p_71_out,
    p_75_out,
    p_79_out,
    p_83_out,
    p_87_out,
    p_91_out,
    p_95_out,
    Q1,
    Q2,
    Q3,
    Q4,
    Q5,
    Q6,
    Q7,
    Q8,
    Q9,
    rst_r4);
  output \pi_dqs_found_lanes_r1_reg[10] ;
  output \pi_dqs_found_lanes_r1_reg[10]_0 ;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output p_66_in;
  output p_65_in;
  output p_70_in;
  output p_69_in;
  output p_74_in;
  output p_73_in;
  output p_78_in;
  output p_77_in;
  output p_82_in;
  output p_81_in;
  output p_86_in;
  output p_85_in;
  output p_90_in;
  output p_89_in;
  output p_94_in;
  output p_93_in;
  output p_7_in;
  output \ddr3_dm[5] ;
  output idelay_ld_rst_5;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input A_rst_primitives_reg;
  input A_rst_primitives_reg_0;
  input iserdes_clkdiv;
  input p_67_out;
  input CLK;
  input C_idelay_ce2_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input A_rst_primitives;
  input p_71_out;
  input p_75_out;
  input p_79_out;
  input p_83_out;
  input p_87_out;
  input p_91_out;
  input p_95_out;
  input [3:0]Q1;
  input [3:0]Q2;
  input [3:0]Q3;
  input [3:0]Q4;
  input [3:0]Q5;
  input [3:0]Q6;
  input [3:0]Q7;
  input [3:0]Q8;
  input [3:0]Q9;
  input rst_r4;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire [0:0]CTSBUS;
  wire C_idelay_ce2_out;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire [3:0]Q1;
  wire [3:0]Q2;
  wire [3:0]Q3;
  wire [3:0]Q4;
  wire [3:0]Q5;
  wire [3:0]Q6;
  wire [3:0]Q7;
  wire [3:0]Q8;
  wire [3:0]Q9;
  wire \ddr3_dm[5] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire idelay_inc;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_i_1__3_n_0;
  wire \input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire \input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ;
  wire iserdes_clkdiv;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire p_65_in;
  wire p_66_in;
  wire p_67_out;
  wire p_69_in;
  wire p_70_in;
  wire p_71_out;
  wire p_73_in;
  wire p_74_in;
  wire p_75_out;
  wire p_77_in;
  wire p_78_in;
  wire p_79_out;
  wire p_7_in;
  wire p_81_in;
  wire p_82_in;
  wire p_83_out;
  wire p_85_in;
  wire p_86_in;
  wire p_87_out;
  wire p_89_in;
  wire p_90_in;
  wire p_91_out;
  wire p_93_in;
  wire p_94_in;
  wire p_95_out;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(\pi_dqs_found_lanes_r1_reg[10] ),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__3
       (.I0(idelay_ld_rst_5),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__3_n_0));
  FDSE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__3_n_0),
        .Q(idelay_ld_rst_5),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_67_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_67_out),
        .DDLY(\input_[1].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_71_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_71_out),
        .DDLY(\input_[2].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_75_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_75_out),
        .DDLY(\input_[3].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_79_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_79_out),
        .DDLY(\input_[4].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_83_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_83_out),
        .DDLY(\input_[5].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_87_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_87_out),
        .DDLY(\input_[6].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_91_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_91_out),
        .DDLY(\input_[7].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(C_idelay_ce2_out),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .IDATAIN(p_95_out),
        .INC(idelay_inc),
        .LD(\gen_byte_sel_div2.calib_in_common_reg ),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(A_rst_primitives_reg),
        .CLKB(A_rst_primitives_reg_0),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(p_95_out),
        .DDLY(\input_[8].iserdes_dq_.idelay_dq.idelaye2_n_0 ),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q1[0]),
        .D2(Q1[1]),
        .D3(Q1[2]),
        .D4(Q1[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_66_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_65_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q2[0]),
        .D2(Q2[1]),
        .D3(Q2[2]),
        .D4(Q2[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_70_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_69_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q3[0]),
        .D2(Q3[1]),
        .D3(Q3[2]),
        .D4(Q3[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_74_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_73_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q4[0]),
        .D2(Q4[1]),
        .D3(Q4[2]),
        .D4(Q4[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_78_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_77_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q5[0]),
        .D2(Q5[1]),
        .D3(Q5[2]),
        .D4(Q5[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_82_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_81_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q6[0]),
        .D2(Q6[1]),
        .D3(Q6[2]),
        .D4(Q6[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_86_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_85_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q7[0]),
        .D2(Q7[1]),
        .D3(Q7[2]),
        .D4(Q7[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_90_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_89_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q8[0]),
        .D2(Q8[1]),
        .D3(Q8[2]),
        .D4(Q8[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_94_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(p_93_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(Q9[0]),
        .D2(Q9[1]),
        .D3(Q9[2]),
        .D4(Q9[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(p_7_in),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\ddr3_dm[5] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane
   (\rd_ptr_timing_reg[1] ,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    pi_phase_locked_all_r1_reg,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    p_5_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ,
    p_17_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ,
    p_25_in,
    p_30_in,
    p_29_in,
    p_1_in,
    \ddr3_dm[7] ,
    if_empty_r,
    idelay_ld_rst_3,
    rst_r4,
    phy_rddata_en,
    rd_active_r_reg,
    ififo_rd_en_in,
    Q,
    \my_empty_reg[4]_rep__1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \my_empty_reg[1] ,
    ADDRA,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[511] ,
    wr_en_12,
    \entry_cnt_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7] ,
    phaser_ctl_bus,
    A_pi_counter_load_en87_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable83_out,
    A_pi_fine_inc85_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_rst_primitives,
    A_pi_rst_dqs_find81_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    \calib_zero_inputs_reg[2] ,
    A_po_coarse_enable69_out,
    A_po_fine_enable67_out,
    A_po_fine_inc71_out,
    \write_buffer.wr_buf_out_data_reg[511] ,
    \write_buffer.wr_buf_out_data_reg[510] ,
    \write_buffer.wr_buf_out_data_reg[509] ,
    init_calib_complete_reg_rep__10,
    \write_buffer.wr_buf_out_data_reg[507] ,
    \write_buffer.wr_buf_out_data_reg[506] ,
    \write_buffer.wr_buf_out_data_reg[505] ,
    init_calib_complete_reg_rep__10_0,
    init_calib_complete_reg_rep__9,
    A_rst_primitives_reg,
    mc_read_idle_r_reg_0,
    A_idelay_ce10_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    mc_read_idle_r_reg_1,
    mc_read_idle_r_reg_2,
    mc_read_idle_r_reg_3,
    mc_read_idle_r_reg_4,
    mc_read_idle_r_reg_5,
    mc_read_idle_r_reg_6,
    p_31_out,
    phy_if_reset,
    phy_data_wr_en,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ,
    \my_empty_reg[3] ,
    if_empty_r_1,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ,
    \my_empty_reg[4]_rep__1_0 ,
    if_empty_r_0,
    \my_empty_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ,
    \my_empty_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    tail_r,
    init_complete_r1_timing_reg,
    rstdiv0_sync_r1_reg_rep__21,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \rd_mux_sel_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__9_0,
    mc_wrdata_en,
    \rd_ptr_reg_rep[3] ,
    \po_stg2_wrcal_cnt_reg[2] );
  output [1:0]\rd_ptr_timing_reg[1] ;
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output pi_phase_locked_all_r1_reg;
  output [5:0]COUNTERREADVAL;
  output [8:0]\po_counter_read_val_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output p_5_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  output p_17_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ;
  output p_25_in;
  output p_30_in;
  output p_29_in;
  output p_1_in;
  output \ddr3_dm[7] ;
  output [0:0]if_empty_r;
  output idelay_ld_rst_3;
  output rst_r4;
  output phy_rddata_en;
  output rd_active_r_reg;
  output ififo_rd_en_in;
  output [0:0]Q;
  output \my_empty_reg[4]_rep__1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \my_empty_reg[1] ;
  output [0:0]ADDRA;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [63:0]\not_strict_mode.app_rd_data_reg[511] ;
  output wr_en_12;
  output [2:0]\entry_cnt_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7] ;
  input [3:0]phaser_ctl_bus;
  input A_pi_counter_load_en87_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable83_out;
  input A_pi_fine_inc85_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_rst_primitives;
  input A_pi_rst_dqs_find81_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [5:0]\calib_zero_inputs_reg[2] ;
  input A_po_coarse_enable69_out;
  input A_po_fine_enable67_out;
  input A_po_fine_inc71_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  input [7:0]init_calib_complete_reg_rep__10;
  input [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  input [7:0]init_calib_complete_reg_rep__10_0;
  input [7:0]init_calib_complete_reg_rep__9;
  input A_rst_primitives_reg;
  input mc_read_idle_r_reg_0;
  input A_idelay_ce10_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input mc_read_idle_r_reg_1;
  input mc_read_idle_r_reg_2;
  input mc_read_idle_r_reg_3;
  input mc_read_idle_r_reg_4;
  input mc_read_idle_r_reg_5;
  input mc_read_idle_r_reg_6;
  input p_31_out;
  input phy_if_reset;
  input phy_data_wr_en;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ;
  input [0:0]\my_empty_reg[3] ;
  input [0:0]if_empty_r_1;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ;
  input [0:0]\my_empty_reg[4]_rep__1_0 ;
  input [0:0]if_empty_r_0;
  input \my_empty_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ;
  input [0:0]\my_empty_reg[3]_0 ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  input [0:0]tail_r;
  input init_complete_r1_timing_reg;
  input rstdiv0_sync_r1_reg_rep__21;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  input [1:0]\rd_mux_sel_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__9_0;
  input mc_wrdata_en;
  input [7:0]\rd_ptr_reg_rep[3] ;
  input [1:0]\po_stg2_wrcal_cnt_reg[2] ;

  wire [0:0]ADDRA;
  wire A_idelay_ce10_out;
  wire A_if_a_empty;
  wire A_of_data_a_full;
  wire A_of_data_full;
  wire A_pi_counter_load_en87_out;
  wire A_pi_dqs_out_of_range;
  wire A_pi_fine_enable83_out;
  wire A_pi_fine_inc85_out;
  wire A_pi_fine_overflow;
  wire A_pi_rst_dqs_find81_out;
  wire A_po_coarse_enable69_out;
  wire A_po_coarse_overflow;
  wire A_po_fine_enable67_out;
  wire A_po_fine_inc71_out;
  wire A_po_fine_overflow;
  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire [1:0]PCENABLECALIB;
  wire [0:0]Q;
  wire \calib_sel_reg[0] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[2] ;
  wire \ddr3_dm[7] ;
  wire ddr_byte_group_io_n_2;
  wire ddr_byte_group_io_n_3;
  wire ddr_byte_group_io_n_4;
  wire ddr_byte_group_io_n_5;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  wire [2:0]\entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  wire idelay_inc;
  wire idelay_ld_rst_3;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_r_1;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rd_en_in;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire [7:0]init_calib_complete_reg_rep__10;
  wire [7:0]init_calib_complete_reg_rep__10_0;
  wire [7:0]init_calib_complete_reg_rep__9;
  wire init_calib_complete_reg_rep__9_0;
  wire init_complete_r1_timing_reg;
  wire iserdes_clkdiv;
  wire mc_read_idle_r_reg;
  wire mc_read_idle_r_reg_0;
  wire mc_read_idle_r_reg_1;
  wire mc_read_idle_r_reg_2;
  wire mc_read_idle_r_reg_3;
  wire mc_read_idle_r_reg_4;
  wire mc_read_idle_r_reg_5;
  wire mc_read_idle_r_reg_6;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[1] ;
  wire [0:0]\my_empty_reg[3] ;
  wire [0:0]\my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_rep__1 ;
  wire [0:0]\my_empty_reg[4]_rep__1_0 ;
  wire [3:0]\my_empty_reg[7] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[511] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [7:0]of_d8;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_17_in;
  wire p_1_in;
  wire p_25_in;
  wire p_29_in;
  wire p_30_in;
  wire p_31_out;
  wire p_5_in;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire phy_rddata_en;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [1:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire rd_active_r_reg;
  wire [1:0]\rd_mux_sel_r_reg[2] ;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire rst_r4;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sync_pulse;
  wire [0:0]tail_r;
  wire wr_en_12;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[1] ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io ddr_byte_group_io
       (.A_idelay_ce10_out(A_idelay_ce10_out),
        .A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D0({ddr_byte_group_io_n_2,ddr_byte_group_io_n_3,ddr_byte_group_io_n_4,ddr_byte_group_io_n_5}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q9(of_q9),
        .\ddr3_dm[7] (\ddr3_dm[7] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mc_read_idle_r_reg(mc_read_idle_r_reg_0),
        .mc_read_idle_r_reg_0(mc_read_idle_r_reg_1),
        .mc_read_idle_r_reg_1(mc_read_idle_r_reg_2),
        .mc_read_idle_r_reg_2(mc_read_idle_r_reg_3),
        .mc_read_idle_r_reg_3(mc_read_idle_r_reg_4),
        .mc_read_idle_r_reg_4(mc_read_idle_r_reg_5),
        .mc_read_idle_r_reg_5(mc_read_idle_r_reg_6),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_17_in(p_17_in),
        .p_1_in(p_1_in),
        .p_25_in(p_25_in),
        .p_29_in(p_29_in),
        .p_30_in(p_30_in),
        .p_31_out(p_31_out),
        .p_5_in(p_5_in),
        .\pi_dqs_found_lanes_r1_reg[8] (\pi_dqs_found_lanes_r1_reg[8] ),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [0]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [1]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [2]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [3]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [4]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [5]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(\not_strict_mode.app_rd_data_reg[376] [9]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_4 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.ADDRA(ADDRA),
        .CLK(CLK),
        .Q(Q),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (if_empty_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\not_strict_mode.app_rd_data_reg[376] [63:0]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (\gen_rd[7].rd_data_rise_wl_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .if_empty_r_0(if_empty_r_0),
        .if_empty_r_1(if_empty_r_1),
        .ififo_rst(ififo_rst),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .\my_empty_reg[0]_0 (\my_empty_reg[0] ),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\my_empty_reg[3]_1 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[4]_rep__1_0 (ififo_rd_en_in),
        .\my_empty_reg[4]_rep__1_1 (\my_empty_reg[4]_rep__1 ),
        .\my_empty_reg[4]_rep__1_2 (\my_empty_reg[4]_rep__1_0 ),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[511] (\not_strict_mode.app_rd_data_reg[511] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .phy_rddata_en(phy_rddata_en),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .rd_active_r_reg(rd_active_r_reg),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .tail_r(tail_r),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(A_pi_rst_dqs_find81_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(A_if_a_empty),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({ddr_byte_group_io_n_2,ddr_byte_group_io_n_3,ddr_byte_group_io_n_4,ddr_byte_group_io_n_5}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8({1'b0,1'b0,1'b0,1'b0}),
        .D9({1'b0,1'b0,1'b0,1'b0}),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized2 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.A_of_data_full(A_of_data_full),
        .CLK(CLK),
        .D8(of_d8),
        .Q(\entry_cnt_reg[4] ),
        .calib_wrdata_en(calib_wrdata_en),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_0),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7] ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3] ),
        .wr_en_12(wr_en_12),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(A_pi_rst_dqs_find81_out),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(A_of_data_a_full),
        .D0(\write_buffer.wr_buf_out_data_reg[511] ),
        .D1(\write_buffer.wr_buf_out_data_reg[510] ),
        .D2(\write_buffer.wr_buf_out_data_reg[509] ),
        .D3(init_calib_complete_reg_rep__10),
        .D4(\write_buffer.wr_buf_out_data_reg[507] ),
        .D5(\write_buffer.wr_buf_out_data_reg[506] ),
        .D6(\write_buffer.wr_buf_out_data_reg[505] ),
        .D7(init_calib_complete_reg_rep__10_0),
        .D8(of_d8),
        .D9(init_calib_complete_reg_rep__9),
        .EMPTY(out_fifo_n_2),
        .FULL(A_of_data_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(A_pi_counter_load_en87_out),
        .COUNTERLOADVAL(\calib_zero_inputs_reg[2] ),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(A_pi_dqs_out_of_range),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(A_pi_fine_enable83_out),
        .FINEINC(A_pi_fine_inc85_out),
        .FINEOVERFLOW(A_pi_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(pi_phase_locked_all_r1_reg),
        .PHASEREFCLK(mc_read_idle_r_reg),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(A_pi_rst_dqs_find81_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(A_po_coarse_enable69_out),
        .COARSEINC(A_po_coarse_enable69_out),
        .COARSEOVERFLOW(A_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(\po_counter_read_val_reg[8] ),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(A_po_fine_enable67_out),
        .FINEINC(A_po_fine_inc71_out),
        .FINEOVERFLOW(A_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane_7
   (pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    pi_phase_locked_all_r1_reg,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    p_134_in,
    p_133_in,
    p_138_in,
    p_137_in,
    p_142_in,
    p_141_in,
    p_146_in,
    p_145_in,
    p_150_in,
    p_149_in,
    p_154_in,
    p_153_in,
    p_158_in,
    p_157_in,
    p_13_in,
    \ddr3_dm[3] ,
    if_empty_r,
    idelay_ld_rst,
    rd_buf_we,
    Q,
    \read_fifo.tail_r_reg[1] ,
    \read_fifo.tail_r_reg[3] ,
    ADDRA,
    \my_empty_reg[4]_rep__1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ,
    \my_empty_reg[1] ,
    \entry_cnt_reg[4] ,
    ofs_rdy_r_reg,
    \read_fifo.tail_r_reg[0] ,
    \read_fifo.tail_r_reg[1]_0 ,
    \not_strict_mode.app_rd_data_reg[479] ,
    \not_strict_mode.app_rd_data_reg[24] ,
    \my_empty_reg[7] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    phaser_ctl_bus,
    A_pi_counter_load_en116_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable112_out,
    A_pi_fine_inc114_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_rst_primitives,
    A_pi_rst_dqs_find110_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    COUNTERLOADVAL,
    A_po_coarse_enable98_out,
    A_po_fine_enable96_out,
    A_po_fine_inc100_out,
    \write_buffer.wr_buf_out_data_reg[479] ,
    \write_buffer.wr_buf_out_data_reg[478] ,
    \write_buffer.wr_buf_out_data_reg[477] ,
    \write_buffer.wr_buf_out_data_reg[412] ,
    \write_buffer.wr_buf_out_data_reg[475] ,
    \write_buffer.wr_buf_out_data_reg[474] ,
    \write_buffer.wr_buf_out_data_reg[473] ,
    \write_buffer.wr_buf_out_data_reg[408] ,
    A_rst_primitives_reg,
    p_131_out,
    A_idelay_ce13_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_135_out,
    p_139_out,
    p_143_out,
    p_147_out,
    p_151_out,
    p_155_out,
    p_159_out,
    phy_if_reset,
    phy_data_wr_en,
    ram_init_done_r,
    if_empty_r_1,
    my_empty,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \my_empty_reg[3] ,
    \read_fifo.fifo_out_data_r_reg[6] ,
    init_complete_r1_timing_reg,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    tail_r,
    rstdiv0_sync_r1_reg_rep__21,
    if_empty_r_0,
    \my_empty_reg[0] ,
    \my_empty_reg[0]_0 ,
    \my_empty_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ,
    \my_empty_reg[3]_1 ,
    rst_r4,
    \entry_cnt_reg[4]_0 ,
    \entry_cnt_reg[4]_1 ,
    \entry_cnt_reg[4]_2 ,
    \entry_cnt_reg[4]_3 ,
    \entry_cnt_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    ram_init_addr,
    calib_wrdata_en,
    init_calib_complete_reg_rep__3,
    mc_wrdata_en,
    \write_buffer.wr_buf_out_data_reg[571] ,
    init_calib_complete_reg_rep__4,
    phy_dout);
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output pi_phase_locked_all_r1_reg;
  output [5:0]COUNTERREADVAL;
  output [8:0]\po_counter_read_val_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[0] ;
  output \pi_dqs_found_lanes_r1_reg[0]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output p_134_in;
  output p_133_in;
  output p_138_in;
  output p_137_in;
  output p_142_in;
  output p_141_in;
  output p_146_in;
  output p_145_in;
  output p_150_in;
  output p_149_in;
  output p_154_in;
  output p_153_in;
  output p_158_in;
  output p_157_in;
  output p_13_in;
  output \ddr3_dm[3] ;
  output [0:0]if_empty_r;
  output idelay_ld_rst;
  output rd_buf_we;
  output [0:0]Q;
  output \read_fifo.tail_r_reg[1] ;
  output \read_fifo.tail_r_reg[3] ;
  output [1:0]ADDRA;
  output \my_empty_reg[4]_rep__1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  output \my_empty_reg[1] ;
  output [1:0]\entry_cnt_reg[4] ;
  output ofs_rdy_r_reg;
  output \read_fifo.tail_r_reg[0] ;
  output \read_fifo.tail_r_reg[1]_0 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[479] ;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output [43:0]\my_empty_reg[7] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input [3:0]phaser_ctl_bus;
  input A_pi_counter_load_en116_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable112_out;
  input A_pi_fine_inc114_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_rst_primitives;
  input A_pi_rst_dqs_find110_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [5:0]COUNTERLOADVAL;
  input A_po_coarse_enable98_out;
  input A_po_fine_enable96_out;
  input A_po_fine_inc100_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  input A_rst_primitives_reg;
  input p_131_out;
  input A_idelay_ce13_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_135_out;
  input p_139_out;
  input p_143_out;
  input p_147_out;
  input p_151_out;
  input p_155_out;
  input p_159_out;
  input phy_if_reset;
  input phy_data_wr_en;
  input ram_init_done_r;
  input [0:0]if_empty_r_1;
  input [0:0]my_empty;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  input \my_empty_reg[3] ;
  input [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  input init_complete_r1_timing_reg;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  input [3:0]tail_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input [0:0]if_empty_r_0;
  input [0:0]\my_empty_reg[0] ;
  input \my_empty_reg[0]_0 ;
  input [0:0]\my_empty_reg[3]_0 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  input [0:0]\my_empty_reg[3]_1 ;
  input rst_r4;
  input [0:0]\entry_cnt_reg[4]_0 ;
  input [0:0]\entry_cnt_reg[4]_1 ;
  input [0:0]\entry_cnt_reg[4]_2 ;
  input [0:0]\entry_cnt_reg[4]_3 ;
  input [0:0]\entry_cnt_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input \read_fifo.fifo_out_data_r_reg[5] ;
  input [0:0]ram_init_addr;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__3;
  input mc_wrdata_en;
  input [27:0]\write_buffer.wr_buf_out_data_reg[571] ;
  input init_calib_complete_reg_rep__4;
  input [71:0]phy_dout;

  wire [1:0]ADDRA;
  wire A_idelay_ce13_out;
  wire A_pi_counter_load_en116_out;
  wire A_pi_fine_enable112_out;
  wire A_pi_fine_inc114_out;
  wire A_pi_rst_dqs_find110_out;
  wire A_po_coarse_enable98_out;
  wire A_po_fine_enable96_out;
  wire A_po_fine_inc100_out;
  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire [5:0]COUNTERREADVAL;
  wire [1:0]PCENABLECALIB;
  wire [0:0]Q;
  wire \calib_sel_reg[0] ;
  wire calib_wrdata_en;
  wire \ddr3_dm[3] ;
  wire ddr_byte_group_io_n_2;
  wire ddr_byte_group_io_n_3;
  wire ddr_byte_group_io_n_4;
  wire ddr_byte_group_io_n_5;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  wire [1:0]\entry_cnt_reg[4] ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire [0:0]\entry_cnt_reg[4]_1 ;
  wire [0:0]\entry_cnt_reg[4]_2 ;
  wire [0:0]\entry_cnt_reg[4]_3 ;
  wire [0:0]\entry_cnt_reg[4]_4 ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_r_1;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire init_calib_complete_reg_rep__3;
  wire init_calib_complete_reg_rep__4;
  wire init_complete_r1_timing_reg;
  wire iserdes_clkdiv;
  wire mc_read_idle_r_reg;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire [0:0]my_empty;
  wire [0:0]\my_empty_reg[0] ;
  wire \my_empty_reg[0]_0 ;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[3] ;
  wire [0:0]\my_empty_reg[3]_0 ;
  wire [0:0]\my_empty_reg[3]_1 ;
  wire \my_empty_reg[4]_rep__1 ;
  wire [43:0]\my_empty_reg[7] ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[479] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [4:1]of_d1;
  wire [4:2]of_d2;
  wire [7:0]of_d3;
  wire [5:0]of_d4;
  wire [4:1]of_d5;
  wire [4:2]of_d6;
  wire [7:0]of_d7;
  wire [7:0]of_d8;
  wire [7:0]of_d9;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofs_rdy_r_reg;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_131_out;
  wire p_133_in;
  wire p_134_in;
  wire p_135_out;
  wire p_137_in;
  wire p_138_in;
  wire p_139_out;
  wire p_13_in;
  wire p_141_in;
  wire p_142_in;
  wire p_143_out;
  wire p_145_in;
  wire p_146_in;
  wire p_147_out;
  wire p_149_in;
  wire p_150_in;
  wire p_151_out;
  wire p_153_in;
  wire p_154_in;
  wire p_155_out;
  wire p_157_in;
  wire p_158_in;
  wire p_159_out;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_if_reset;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [0:0]ram_init_addr;
  wire ram_init_done_r;
  wire rd_buf_we;
  wire [65:0]rd_data_r;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  wire \read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire \read_fifo.tail_r_reg[3] ;
  wire rst_r4;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sync_pulse;
  wire [3:0]tail_r;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[571] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_11 ddr_byte_group_io
       (.A_idelay_ce13_out(A_idelay_ce13_out),
        .A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D0({ddr_byte_group_io_n_2,ddr_byte_group_io_n_3,ddr_byte_group_io_n_4,ddr_byte_group_io_n_5}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q9(of_q9),
        .\ddr3_dm[3] (\ddr3_dm[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .iserdes_clkdiv(iserdes_clkdiv),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_131_out(p_131_out),
        .p_133_in(p_133_in),
        .p_134_in(p_134_in),
        .p_135_out(p_135_out),
        .p_137_in(p_137_in),
        .p_138_in(p_138_in),
        .p_139_out(p_139_out),
        .p_13_in(p_13_in),
        .p_141_in(p_141_in),
        .p_142_in(p_142_in),
        .p_143_out(p_143_out),
        .p_145_in(p_145_in),
        .p_146_in(p_146_in),
        .p_147_out(p_147_out),
        .p_149_in(p_149_in),
        .p_150_in(p_150_in),
        .p_151_out(p_151_out),
        .p_153_in(p_153_in),
        .p_154_in(p_154_in),
        .p_155_out(p_155_out),
        .p_157_in(p_157_in),
        .p_158_in(p_158_in),
        .p_159_out(p_159_out),
        .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0] ),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[0]),
        .Q(rd_data_r[0]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(rd_data_r[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(rd_data_r[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[1]),
        .Q(rd_data_r[1]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[2]),
        .Q(rd_data_r[2]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[3]),
        .Q(rd_data_r[3]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[2]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[3]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[4]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[5]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[6]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[7]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[4]),
        .Q(rd_data_r[4]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[5]),
        .Q(rd_data_r[5]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(rd_data_r[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(rd_data_r[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(rd_data_r[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(rd_data_r[9]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_12 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.ADDRA(ADDRA),
        .CLK(CLK),
        .Q(Q),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (rd_data_r),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (\gen_rd[3].rd_data_rise_wl_r_reg[3] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .if_empty_r_0(if_empty_r_0),
        .if_empty_r_1(if_empty_r_1),
        .ififo_rst(ififo_rst),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .my_empty(my_empty),
        .\my_empty_reg[0]_0 (\my_empty_reg[0] ),
        .\my_empty_reg[0]_1 (\my_empty_reg[0]_0 ),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\my_empty_reg[3]_1 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[3]_2 (\my_empty_reg[3]_1 ),
        .\my_empty_reg[4]_rep__1_0 (\my_empty_reg[4]_rep__1 ),
        .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ),
        .\not_strict_mode.app_rd_data_reg[479] (\not_strict_mode.app_rd_data_reg[479] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .ram_init_addr(ram_init_addr),
        .ram_init_done_r(ram_init_done_r),
        .rd_buf_we(rd_buf_we),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ),
        .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1]_0 ),
        .\read_fifo.tail_r_reg[3] (\read_fifo.tail_r_reg[3] ),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .tail_r(tail_r));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(A_pi_rst_dqs_find110_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({ddr_byte_group_io_n_2,ddr_byte_group_io_n_3,ddr_byte_group_io_n_4,ddr_byte_group_io_n_5}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8({1'b0,1'b0,1'b0,1'b0}),
        .D9({1'b0,1'b0,1'b0,1'b0}),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized2_13 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }),
        .D1({of_d1[4:3],of_d1[1]}),
        .D2({of_d2[4],of_d2[2]}),
        .D3({of_d3[7],of_d3[0]}),
        .D4({of_d4[5],of_d4[1:0]}),
        .D5({of_d5[4:3],of_d5[1]}),
        .D6({of_d6[4],of_d6[2]}),
        .D7({of_d7[7],of_d7[0]}),
        .D8(of_d8),
        .D9(of_d9),
        .calib_wrdata_en(calib_wrdata_en),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .\entry_cnt_reg[4]_1 (\entry_cnt_reg[4]_0 ),
        .\entry_cnt_reg[4]_2 (\entry_cnt_reg[4]_1 ),
        .\entry_cnt_reg[4]_3 (\entry_cnt_reg[4]_2 ),
        .\entry_cnt_reg[4]_4 (\entry_cnt_reg[4]_3 ),
        .\entry_cnt_reg[4]_5 (\entry_cnt_reg[4]_4 ),
        .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3),
        .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7] ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(out_fifo_n_3),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .\write_buffer.wr_buf_out_data_reg[571] (\write_buffer.wr_buf_out_data_reg[571] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(A_pi_rst_dqs_find110_out),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\write_buffer.wr_buf_out_data_reg[479] [4:3],\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\write_buffer.wr_buf_out_data_reg[479] [2:0],\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }),
        .D1({\write_buffer.wr_buf_out_data_reg[478] [4:2],of_d1[4:3],\write_buffer.wr_buf_out_data_reg[478] [1],of_d1[1],\write_buffer.wr_buf_out_data_reg[478] [0]}),
        .D2({\write_buffer.wr_buf_out_data_reg[477] [5:3],of_d2[4],\write_buffer.wr_buf_out_data_reg[477] [2],of_d2[2],\write_buffer.wr_buf_out_data_reg[477] [1:0]}),
        .D3({of_d3[7],\write_buffer.wr_buf_out_data_reg[412] ,of_d3[0]}),
        .D4({\write_buffer.wr_buf_out_data_reg[475] [4:3],of_d4[5],\write_buffer.wr_buf_out_data_reg[475] [2:0],of_d4[1:0]}),
        .D5({\write_buffer.wr_buf_out_data_reg[474] [4:2],of_d5[4:3],\write_buffer.wr_buf_out_data_reg[474] [1],of_d5[1],\write_buffer.wr_buf_out_data_reg[474] [0]}),
        .D6({\write_buffer.wr_buf_out_data_reg[473] [5:3],of_d6[4],\write_buffer.wr_buf_out_data_reg[473] [2],of_d6[2],\write_buffer.wr_buf_out_data_reg[473] [1:0]}),
        .D7({of_d7[7],\write_buffer.wr_buf_out_data_reg[408] ,of_d7[0]}),
        .D8(of_d8),
        .D9(of_d9),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(A_pi_counter_load_en116_out),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(A_pi_fine_enable112_out),
        .FINEINC(A_pi_fine_inc114_out),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(pi_phase_locked_all_r1_reg),
        .PHASEREFCLK(mc_read_idle_r_reg),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(A_pi_rst_dqs_find110_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(A_po_coarse_enable98_out),
        .COARSEINC(A_po_coarse_enable98_out),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(\po_counter_read_val_reg[8] ),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(A_po_fine_enable96_out),
        .FINEINC(A_po_fine_inc100_out),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0
   (pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    pi_phase_locked_all_r1_reg,
    rclk_,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8] ,
    p_28_in,
    p_27_in,
    p_162_in,
    p_161_in,
    p_166_in,
    p_165_in,
    p_170_in,
    p_169_in,
    p_174_in,
    p_173_in,
    \ddr3_dm[2] ,
    p_15_in,
    p_178_in,
    p_177_in,
    p_182_in,
    p_181_in,
    p_186_in,
    p_185_in,
    p_190_in,
    p_189_in,
    \my_full_reg[0] ,
    idelay_ld_rst_0,
    rst_r4,
    Q,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \my_empty_reg[1] ,
    \entry_cnt_reg[4] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    DIB,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[471] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    p_0_out,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \my_empty_reg[7] ,
    B_byte_rd_en,
    phaser_ctl_bus,
    B_pi_counter_load_en38_out,
    \calib_sel_reg[0] ,
    B_pi_fine_enable34_out,
    B_pi_fine_inc36_out,
    freq_refclk,
    mem_refclk,
    p_29_out,
    A_rst_primitives,
    B_pi_rst_dqs_find32_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    \calib_zero_inputs_reg[0] ,
    B_po_coarse_enable20_out,
    B_po_fine_enable18_out,
    B_po_fine_inc22_out,
    \write_buffer.wr_buf_out_data_reg[471] ,
    \write_buffer.wr_buf_out_data_reg[470] ,
    \write_buffer.wr_buf_out_data_reg[469] ,
    \write_buffer.wr_buf_out_data_reg[404] ,
    \write_buffer.wr_buf_out_data_reg[467] ,
    \write_buffer.wr_buf_out_data_reg[466] ,
    \write_buffer.wr_buf_out_data_reg[465] ,
    \write_buffer.wr_buf_out_data_reg[400] ,
    A_rst_primitives_reg,
    p_163_out,
    B_idelay_ce9_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_167_out,
    p_171_out,
    p_175_out,
    p_179_out,
    p_183_out,
    p_187_out,
    p_191_out,
    phy_if_reset,
    phy_data_wr_en,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    C_byte_rd_en,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[1] ,
    DIA,
    DIC,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \rd_mux_sel_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \rd_mux_sel_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \rd_mux_sel_r_reg[1]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \rd_mux_sel_r_reg[1]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \rd_mux_sel_r_reg[1]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \rd_mux_sel_r_reg[1]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \rd_mux_sel_r_reg[1]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \rd_mux_sel_r_reg[1]_7 ,
    \rd_mux_sel_r_reg[1]_8 ,
    \rd_mux_sel_r_reg[1]_9 ,
    \rd_mux_sel_r_reg[1]_10 ,
    \rd_mux_sel_r_reg[1]_11 ,
    \rd_mux_sel_r_reg[1]_12 ,
    \rd_mux_sel_r_reg[1]_13 ,
    \rd_mux_sel_r_reg[1]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \rd_mux_sel_r_reg[1]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \rd_mux_sel_r_reg[1]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \rd_mux_sel_r_reg[1]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \rd_mux_sel_r_reg[1]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \rd_mux_sel_r_reg[1]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \rd_mux_sel_r_reg[1]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \rd_mux_sel_r_reg[1]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \rd_mux_sel_r_reg[1]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \rd_mux_sel_r_reg[1]_23 ,
    \rd_mux_sel_r_reg[1]_24 ,
    \rd_mux_sel_r_reg[1]_25 ,
    \rd_mux_sel_r_reg[1]_26 ,
    \rd_mux_sel_r_reg[1]_27 ,
    \rd_mux_sel_r_reg[1]_28 ,
    \rd_mux_sel_r_reg[1]_29 ,
    \rd_mux_sel_r_reg[1]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \rd_mux_sel_r_reg[1]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \rd_mux_sel_r_reg[1]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \rd_mux_sel_r_reg[1]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \rd_mux_sel_r_reg[1]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \rd_mux_sel_r_reg[1]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \rd_mux_sel_r_reg[1]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \rd_mux_sel_r_reg[1]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \rd_mux_sel_r_reg[1]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \rd_mux_sel_r_reg[1]_39 ,
    \rd_mux_sel_r_reg[1]_40 ,
    \rd_mux_sel_r_reg[1]_41 ,
    \rd_mux_sel_r_reg[1]_42 ,
    \rd_mux_sel_r_reg[1]_43 ,
    \rd_mux_sel_r_reg[1]_44 ,
    \rd_mux_sel_r_reg[1]_45 ,
    \rd_mux_sel_r_reg[1]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \rd_mux_sel_r_reg[1]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,
    \rd_mux_sel_r_reg[1]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,
    \rd_mux_sel_r_reg[1]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,
    \rd_mux_sel_r_reg[1]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,
    \rd_mux_sel_r_reg[1]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,
    \rd_mux_sel_r_reg[1]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,
    \rd_mux_sel_r_reg[1]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,
    \rd_mux_sel_r_reg[1]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \rd_mux_sel_r_reg[1]_55 ,
    \rd_mux_sel_r_reg[1]_56 ,
    \rd_mux_sel_r_reg[1]_57 ,
    \rd_mux_sel_r_reg[1]_58 ,
    \rd_mux_sel_r_reg[1]_59 ,
    \rd_mux_sel_r_reg[1]_60 ,
    \rd_mux_sel_r_reg[1]_61 ,
    \rd_mux_sel_r_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__4,
    mc_wrdata_en,
    \write_buffer.wr_buf_out_data_reg[570] ,
    init_calib_complete_reg_rep__5,
    init_calib_complete_reg_rep__6,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[1]_0 ,
    \po_stg2_wrcal_cnt_reg[1]_1 ,
    \po_stg2_wrcal_cnt_reg[1]_2 ,
    \po_stg2_wrcal_cnt_reg[1]_3 ,
    \po_stg2_wrcal_cnt_reg[1]_4 ,
    \po_stg2_wrcal_cnt_reg[1]_5 ,
    \po_stg2_wrcal_cnt_reg[1]_6 ,
    \po_stg2_wrcal_cnt_reg[1]_7 ,
    \po_stg2_wrcal_cnt_reg[1]_8 ,
    \po_stg2_wrcal_cnt_reg[1]_9 ,
    \po_stg2_wrcal_cnt_reg[1]_10 ,
    \po_stg2_wrcal_cnt_reg[1]_11 ,
    \po_stg2_wrcal_cnt_reg[1]_12 ,
    \po_stg2_wrcal_cnt_reg[1]_13 ,
    \po_stg2_wrcal_cnt_reg[1]_14 ,
    \po_stg2_wrcal_cnt_reg[1]_15 ,
    \po_stg2_wrcal_cnt_reg[1]_16 ,
    \po_stg2_wrcal_cnt_reg[1]_17 ,
    \po_stg2_wrcal_cnt_reg[1]_18 ,
    \po_stg2_wrcal_cnt_reg[1]_19 ,
    \po_stg2_wrcal_cnt_reg[1]_20 ,
    \po_stg2_wrcal_cnt_reg[1]_21 ,
    \po_stg2_wrcal_cnt_reg[1]_22 ,
    \po_stg2_wrcal_cnt_reg[1]_23 ,
    \po_stg2_wrcal_cnt_reg[1]_24 ,
    \po_stg2_wrcal_cnt_reg[1]_25 ,
    \po_stg2_wrcal_cnt_reg[1]_26 ,
    \po_stg2_wrcal_cnt_reg[1]_27 ,
    \po_stg2_wrcal_cnt_reg[1]_28 ,
    \po_stg2_wrcal_cnt_reg[1]_29 ,
    \po_stg2_wrcal_cnt_reg[1]_30 ,
    \po_stg2_wrcal_cnt_reg[1]_31 ,
    \po_stg2_wrcal_cnt_reg[1]_32 ,
    \po_stg2_wrcal_cnt_reg[1]_33 ,
    \po_stg2_wrcal_cnt_reg[1]_34 ,
    \po_stg2_wrcal_cnt_reg[1]_35 ,
    \po_stg2_wrcal_cnt_reg[1]_36 ,
    \po_stg2_wrcal_cnt_reg[1]_37 ,
    \po_stg2_wrcal_cnt_reg[1]_38 ,
    \po_stg2_wrcal_cnt_reg[1]_39 ,
    \po_stg2_wrcal_cnt_reg[1]_40 ,
    \po_stg2_wrcal_cnt_reg[1]_41 ,
    \po_stg2_wrcal_cnt_reg[1]_42 ,
    \po_stg2_wrcal_cnt_reg[1]_43 ,
    \po_stg2_wrcal_cnt_reg[1]_44 ,
    \po_stg2_wrcal_cnt_reg[1]_45 ,
    \po_stg2_wrcal_cnt_reg[1]_46 ,
    \po_stg2_wrcal_cnt_reg[1]_47 ,
    \po_stg2_wrcal_cnt_reg[1]_48 ,
    \po_stg2_wrcal_cnt_reg[1]_49 ,
    \po_stg2_wrcal_cnt_reg[1]_50 ,
    \po_stg2_wrcal_cnt_reg[1]_51 ,
    \po_stg2_wrcal_cnt_reg[1]_52 ,
    \po_stg2_wrcal_cnt_reg[1]_53 ,
    \po_stg2_wrcal_cnt_reg[1]_54 ,
    \po_stg2_wrcal_cnt_reg[1]_55 ,
    \po_stg2_wrcal_cnt_reg[1]_56 ,
    \po_stg2_wrcal_cnt_reg[1]_57 ,
    \po_stg2_wrcal_cnt_reg[1]_58 ,
    \po_stg2_wrcal_cnt_reg[1]_59 ,
    \po_stg2_wrcal_cnt_reg[1]_60 ,
    \po_stg2_wrcal_cnt_reg[1]_61 ,
    \po_stg2_wrcal_cnt_reg[1]_62 ,
    phy_dout);
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output pi_phase_locked_all_r1_reg;
  output rclk_;
  output [5:0]COUNTERREADVAL;
  output [8:0]\po_counter_read_val_reg[8] ;
  output p_28_in;
  output p_27_in;
  output p_162_in;
  output p_161_in;
  output p_166_in;
  output p_165_in;
  output p_170_in;
  output p_169_in;
  output p_174_in;
  output p_173_in;
  output \ddr3_dm[2] ;
  output p_15_in;
  output p_178_in;
  output p_177_in;
  output p_182_in;
  output p_181_in;
  output p_186_in;
  output p_185_in;
  output p_190_in;
  output p_189_in;
  output \my_full_reg[0] ;
  output idelay_ld_rst_0;
  output rst_r4;
  output [1:0]Q;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \my_empty_reg[1] ;
  output [2:0]\entry_cnt_reg[4] ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]DIB;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [63:0]\not_strict_mode.app_rd_data_reg[471] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output p_0_out;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [43:0]\my_empty_reg[7] ;
  output B_byte_rd_en;
  input [3:0]phaser_ctl_bus;
  input B_pi_counter_load_en38_out;
  input \calib_sel_reg[0] ;
  input B_pi_fine_enable34_out;
  input B_pi_fine_inc36_out;
  input freq_refclk;
  input mem_refclk;
  input p_29_out;
  input A_rst_primitives;
  input B_pi_rst_dqs_find32_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [5:0]\calib_zero_inputs_reg[0] ;
  input B_po_coarse_enable20_out;
  input B_po_fine_enable18_out;
  input B_po_fine_inc22_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  input A_rst_primitives_reg;
  input p_163_out;
  input B_idelay_ce9_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_167_out;
  input p_171_out;
  input p_175_out;
  input p_179_out;
  input p_183_out;
  input p_187_out;
  input p_191_out;
  input phy_if_reset;
  input phy_data_wr_en;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  input C_byte_rd_en;
  input [2:0]\rd_mux_sel_r_reg[2] ;
  input \rd_mux_sel_r_reg[1] ;
  input [1:0]DIA;
  input [1:0]DIC;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  input \rd_mux_sel_r_reg[1]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  input \rd_mux_sel_r_reg[1]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  input \rd_mux_sel_r_reg[1]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  input \rd_mux_sel_r_reg[1]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  input \rd_mux_sel_r_reg[1]_4 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  input \rd_mux_sel_r_reg[1]_5 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  input \rd_mux_sel_r_reg[1]_6 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  input \rd_mux_sel_r_reg[1]_7 ;
  input \rd_mux_sel_r_reg[1]_8 ;
  input \rd_mux_sel_r_reg[1]_9 ;
  input \rd_mux_sel_r_reg[1]_10 ;
  input \rd_mux_sel_r_reg[1]_11 ;
  input \rd_mux_sel_r_reg[1]_12 ;
  input \rd_mux_sel_r_reg[1]_13 ;
  input \rd_mux_sel_r_reg[1]_14 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  input \rd_mux_sel_r_reg[1]_15 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  input \rd_mux_sel_r_reg[1]_16 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  input \rd_mux_sel_r_reg[1]_17 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  input \rd_mux_sel_r_reg[1]_18 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  input \rd_mux_sel_r_reg[1]_19 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  input \rd_mux_sel_r_reg[1]_20 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  input \rd_mux_sel_r_reg[1]_21 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  input \rd_mux_sel_r_reg[1]_22 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  input \rd_mux_sel_r_reg[1]_23 ;
  input \rd_mux_sel_r_reg[1]_24 ;
  input \rd_mux_sel_r_reg[1]_25 ;
  input \rd_mux_sel_r_reg[1]_26 ;
  input \rd_mux_sel_r_reg[1]_27 ;
  input \rd_mux_sel_r_reg[1]_28 ;
  input \rd_mux_sel_r_reg[1]_29 ;
  input \rd_mux_sel_r_reg[1]_30 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  input \rd_mux_sel_r_reg[1]_31 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  input \rd_mux_sel_r_reg[1]_32 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  input \rd_mux_sel_r_reg[1]_33 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  input \rd_mux_sel_r_reg[1]_34 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  input \rd_mux_sel_r_reg[1]_35 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  input \rd_mux_sel_r_reg[1]_36 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  input \rd_mux_sel_r_reg[1]_37 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  input \rd_mux_sel_r_reg[1]_38 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  input \rd_mux_sel_r_reg[1]_39 ;
  input \rd_mux_sel_r_reg[1]_40 ;
  input \rd_mux_sel_r_reg[1]_41 ;
  input \rd_mux_sel_r_reg[1]_42 ;
  input \rd_mux_sel_r_reg[1]_43 ;
  input \rd_mux_sel_r_reg[1]_44 ;
  input \rd_mux_sel_r_reg[1]_45 ;
  input \rd_mux_sel_r_reg[1]_46 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  input \rd_mux_sel_r_reg[1]_47 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  input \rd_mux_sel_r_reg[1]_48 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  input \rd_mux_sel_r_reg[1]_49 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  input \rd_mux_sel_r_reg[1]_50 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  input \rd_mux_sel_r_reg[1]_51 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  input \rd_mux_sel_r_reg[1]_52 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  input \rd_mux_sel_r_reg[1]_53 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  input \rd_mux_sel_r_reg[1]_54 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  input \rd_mux_sel_r_reg[1]_55 ;
  input \rd_mux_sel_r_reg[1]_56 ;
  input \rd_mux_sel_r_reg[1]_57 ;
  input \rd_mux_sel_r_reg[1]_58 ;
  input \rd_mux_sel_r_reg[1]_59 ;
  input \rd_mux_sel_r_reg[1]_60 ;
  input \rd_mux_sel_r_reg[1]_61 ;
  input \rd_mux_sel_r_reg[1]_62 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__4;
  input mc_wrdata_en;
  input [27:0]\write_buffer.wr_buf_out_data_reg[570] ;
  input init_calib_complete_reg_rep__5;
  input init_calib_complete_reg_rep__6;
  input [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  input \po_stg2_wrcal_cnt_reg[1] ;
  input \po_stg2_wrcal_cnt_reg[1]_0 ;
  input \po_stg2_wrcal_cnt_reg[1]_1 ;
  input \po_stg2_wrcal_cnt_reg[1]_2 ;
  input \po_stg2_wrcal_cnt_reg[1]_3 ;
  input \po_stg2_wrcal_cnt_reg[1]_4 ;
  input \po_stg2_wrcal_cnt_reg[1]_5 ;
  input \po_stg2_wrcal_cnt_reg[1]_6 ;
  input \po_stg2_wrcal_cnt_reg[1]_7 ;
  input \po_stg2_wrcal_cnt_reg[1]_8 ;
  input \po_stg2_wrcal_cnt_reg[1]_9 ;
  input \po_stg2_wrcal_cnt_reg[1]_10 ;
  input \po_stg2_wrcal_cnt_reg[1]_11 ;
  input \po_stg2_wrcal_cnt_reg[1]_12 ;
  input \po_stg2_wrcal_cnt_reg[1]_13 ;
  input \po_stg2_wrcal_cnt_reg[1]_14 ;
  input \po_stg2_wrcal_cnt_reg[1]_15 ;
  input \po_stg2_wrcal_cnt_reg[1]_16 ;
  input \po_stg2_wrcal_cnt_reg[1]_17 ;
  input \po_stg2_wrcal_cnt_reg[1]_18 ;
  input \po_stg2_wrcal_cnt_reg[1]_19 ;
  input \po_stg2_wrcal_cnt_reg[1]_20 ;
  input \po_stg2_wrcal_cnt_reg[1]_21 ;
  input \po_stg2_wrcal_cnt_reg[1]_22 ;
  input \po_stg2_wrcal_cnt_reg[1]_23 ;
  input \po_stg2_wrcal_cnt_reg[1]_24 ;
  input \po_stg2_wrcal_cnt_reg[1]_25 ;
  input \po_stg2_wrcal_cnt_reg[1]_26 ;
  input \po_stg2_wrcal_cnt_reg[1]_27 ;
  input \po_stg2_wrcal_cnt_reg[1]_28 ;
  input \po_stg2_wrcal_cnt_reg[1]_29 ;
  input \po_stg2_wrcal_cnt_reg[1]_30 ;
  input \po_stg2_wrcal_cnt_reg[1]_31 ;
  input \po_stg2_wrcal_cnt_reg[1]_32 ;
  input \po_stg2_wrcal_cnt_reg[1]_33 ;
  input \po_stg2_wrcal_cnt_reg[1]_34 ;
  input \po_stg2_wrcal_cnt_reg[1]_35 ;
  input \po_stg2_wrcal_cnt_reg[1]_36 ;
  input \po_stg2_wrcal_cnt_reg[1]_37 ;
  input \po_stg2_wrcal_cnt_reg[1]_38 ;
  input \po_stg2_wrcal_cnt_reg[1]_39 ;
  input \po_stg2_wrcal_cnt_reg[1]_40 ;
  input \po_stg2_wrcal_cnt_reg[1]_41 ;
  input \po_stg2_wrcal_cnt_reg[1]_42 ;
  input \po_stg2_wrcal_cnt_reg[1]_43 ;
  input \po_stg2_wrcal_cnt_reg[1]_44 ;
  input \po_stg2_wrcal_cnt_reg[1]_45 ;
  input \po_stg2_wrcal_cnt_reg[1]_46 ;
  input \po_stg2_wrcal_cnt_reg[1]_47 ;
  input \po_stg2_wrcal_cnt_reg[1]_48 ;
  input \po_stg2_wrcal_cnt_reg[1]_49 ;
  input \po_stg2_wrcal_cnt_reg[1]_50 ;
  input \po_stg2_wrcal_cnt_reg[1]_51 ;
  input \po_stg2_wrcal_cnt_reg[1]_52 ;
  input \po_stg2_wrcal_cnt_reg[1]_53 ;
  input \po_stg2_wrcal_cnt_reg[1]_54 ;
  input \po_stg2_wrcal_cnt_reg[1]_55 ;
  input \po_stg2_wrcal_cnt_reg[1]_56 ;
  input \po_stg2_wrcal_cnt_reg[1]_57 ;
  input \po_stg2_wrcal_cnt_reg[1]_58 ;
  input \po_stg2_wrcal_cnt_reg[1]_59 ;
  input \po_stg2_wrcal_cnt_reg[1]_60 ;
  input \po_stg2_wrcal_cnt_reg[1]_61 ;
  input \po_stg2_wrcal_cnt_reg[1]_62 ;
  input [71:0]phy_dout;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire B_byte_rd_en;
  wire B_idelay_ce9_out;
  wire B_pi_counter_load_en38_out;
  wire B_pi_fine_enable34_out;
  wire B_pi_fine_inc36_out;
  wire B_pi_rst_dqs_find32_out;
  wire B_po_coarse_enable20_out;
  wire B_po_fine_enable18_out;
  wire B_po_fine_inc22_out;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire C_byte_rd_en;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]PCENABLECALIB;
  wire [1:0]Q;
  wire \calib_sel_reg[0] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[0] ;
  wire \ddr3_dm[2] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  wire [2:0]\entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  wire idelay_inc;
  wire idelay_ld_rst_0;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire init_calib_complete_reg_rep__4;
  wire init_calib_complete_reg_rep__5;
  wire init_calib_complete_reg_rep__6;
  wire iserdes_clkdiv;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [43:0]\my_empty_reg[7] ;
  wire \my_full_reg[0] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[471] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [5:0]of_d1;
  wire [4:1]of_d2;
  wire [4:2]of_d3;
  wire [7:0]of_d4;
  wire [7:0]of_d5;
  wire [5:0]of_d6;
  wire [4:1]of_d7;
  wire [4:2]of_d8;
  wire [7:0]of_d9;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_0_out;
  wire p_15_in;
  wire p_161_in;
  wire p_162_in;
  wire p_163_out;
  wire p_165_in;
  wire p_166_in;
  wire p_167_out;
  wire p_169_in;
  wire p_170_in;
  wire p_171_out;
  wire p_173_in;
  wire p_174_in;
  wire p_175_out;
  wire p_177_in;
  wire p_178_in;
  wire p_179_out;
  wire p_181_in;
  wire p_182_in;
  wire p_183_out;
  wire p_185_in;
  wire p_186_in;
  wire p_187_out;
  wire p_189_in;
  wire p_190_in;
  wire p_191_out;
  wire p_27_in;
  wire p_28_in;
  wire p_29_out;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_if_reset;
  wire [0:0]pi_dqs_found_lanes;
  wire pi_phase_locked_all_r1_reg;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[1]_0 ;
  wire \po_stg2_wrcal_cnt_reg[1]_1 ;
  wire \po_stg2_wrcal_cnt_reg[1]_10 ;
  wire \po_stg2_wrcal_cnt_reg[1]_11 ;
  wire \po_stg2_wrcal_cnt_reg[1]_12 ;
  wire \po_stg2_wrcal_cnt_reg[1]_13 ;
  wire \po_stg2_wrcal_cnt_reg[1]_14 ;
  wire \po_stg2_wrcal_cnt_reg[1]_15 ;
  wire \po_stg2_wrcal_cnt_reg[1]_16 ;
  wire \po_stg2_wrcal_cnt_reg[1]_17 ;
  wire \po_stg2_wrcal_cnt_reg[1]_18 ;
  wire \po_stg2_wrcal_cnt_reg[1]_19 ;
  wire \po_stg2_wrcal_cnt_reg[1]_2 ;
  wire \po_stg2_wrcal_cnt_reg[1]_20 ;
  wire \po_stg2_wrcal_cnt_reg[1]_21 ;
  wire \po_stg2_wrcal_cnt_reg[1]_22 ;
  wire \po_stg2_wrcal_cnt_reg[1]_23 ;
  wire \po_stg2_wrcal_cnt_reg[1]_24 ;
  wire \po_stg2_wrcal_cnt_reg[1]_25 ;
  wire \po_stg2_wrcal_cnt_reg[1]_26 ;
  wire \po_stg2_wrcal_cnt_reg[1]_27 ;
  wire \po_stg2_wrcal_cnt_reg[1]_28 ;
  wire \po_stg2_wrcal_cnt_reg[1]_29 ;
  wire \po_stg2_wrcal_cnt_reg[1]_3 ;
  wire \po_stg2_wrcal_cnt_reg[1]_30 ;
  wire \po_stg2_wrcal_cnt_reg[1]_31 ;
  wire \po_stg2_wrcal_cnt_reg[1]_32 ;
  wire \po_stg2_wrcal_cnt_reg[1]_33 ;
  wire \po_stg2_wrcal_cnt_reg[1]_34 ;
  wire \po_stg2_wrcal_cnt_reg[1]_35 ;
  wire \po_stg2_wrcal_cnt_reg[1]_36 ;
  wire \po_stg2_wrcal_cnt_reg[1]_37 ;
  wire \po_stg2_wrcal_cnt_reg[1]_38 ;
  wire \po_stg2_wrcal_cnt_reg[1]_39 ;
  wire \po_stg2_wrcal_cnt_reg[1]_4 ;
  wire \po_stg2_wrcal_cnt_reg[1]_40 ;
  wire \po_stg2_wrcal_cnt_reg[1]_41 ;
  wire \po_stg2_wrcal_cnt_reg[1]_42 ;
  wire \po_stg2_wrcal_cnt_reg[1]_43 ;
  wire \po_stg2_wrcal_cnt_reg[1]_44 ;
  wire \po_stg2_wrcal_cnt_reg[1]_45 ;
  wire \po_stg2_wrcal_cnt_reg[1]_46 ;
  wire \po_stg2_wrcal_cnt_reg[1]_47 ;
  wire \po_stg2_wrcal_cnt_reg[1]_48 ;
  wire \po_stg2_wrcal_cnt_reg[1]_49 ;
  wire \po_stg2_wrcal_cnt_reg[1]_5 ;
  wire \po_stg2_wrcal_cnt_reg[1]_50 ;
  wire \po_stg2_wrcal_cnt_reg[1]_51 ;
  wire \po_stg2_wrcal_cnt_reg[1]_52 ;
  wire \po_stg2_wrcal_cnt_reg[1]_53 ;
  wire \po_stg2_wrcal_cnt_reg[1]_54 ;
  wire \po_stg2_wrcal_cnt_reg[1]_55 ;
  wire \po_stg2_wrcal_cnt_reg[1]_56 ;
  wire \po_stg2_wrcal_cnt_reg[1]_57 ;
  wire \po_stg2_wrcal_cnt_reg[1]_58 ;
  wire \po_stg2_wrcal_cnt_reg[1]_59 ;
  wire \po_stg2_wrcal_cnt_reg[1]_6 ;
  wire \po_stg2_wrcal_cnt_reg[1]_60 ;
  wire \po_stg2_wrcal_cnt_reg[1]_61 ;
  wire \po_stg2_wrcal_cnt_reg[1]_62 ;
  wire \po_stg2_wrcal_cnt_reg[1]_7 ;
  wire \po_stg2_wrcal_cnt_reg[1]_8 ;
  wire \po_stg2_wrcal_cnt_reg[1]_9 ;
  wire [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire rclk_;
  wire [79:6]rd_data_r;
  wire \rd_mux_sel_r_reg[1] ;
  wire \rd_mux_sel_r_reg[1]_0 ;
  wire \rd_mux_sel_r_reg[1]_1 ;
  wire \rd_mux_sel_r_reg[1]_10 ;
  wire \rd_mux_sel_r_reg[1]_11 ;
  wire \rd_mux_sel_r_reg[1]_12 ;
  wire \rd_mux_sel_r_reg[1]_13 ;
  wire \rd_mux_sel_r_reg[1]_14 ;
  wire \rd_mux_sel_r_reg[1]_15 ;
  wire \rd_mux_sel_r_reg[1]_16 ;
  wire \rd_mux_sel_r_reg[1]_17 ;
  wire \rd_mux_sel_r_reg[1]_18 ;
  wire \rd_mux_sel_r_reg[1]_19 ;
  wire \rd_mux_sel_r_reg[1]_2 ;
  wire \rd_mux_sel_r_reg[1]_20 ;
  wire \rd_mux_sel_r_reg[1]_21 ;
  wire \rd_mux_sel_r_reg[1]_22 ;
  wire \rd_mux_sel_r_reg[1]_23 ;
  wire \rd_mux_sel_r_reg[1]_24 ;
  wire \rd_mux_sel_r_reg[1]_25 ;
  wire \rd_mux_sel_r_reg[1]_26 ;
  wire \rd_mux_sel_r_reg[1]_27 ;
  wire \rd_mux_sel_r_reg[1]_28 ;
  wire \rd_mux_sel_r_reg[1]_29 ;
  wire \rd_mux_sel_r_reg[1]_3 ;
  wire \rd_mux_sel_r_reg[1]_30 ;
  wire \rd_mux_sel_r_reg[1]_31 ;
  wire \rd_mux_sel_r_reg[1]_32 ;
  wire \rd_mux_sel_r_reg[1]_33 ;
  wire \rd_mux_sel_r_reg[1]_34 ;
  wire \rd_mux_sel_r_reg[1]_35 ;
  wire \rd_mux_sel_r_reg[1]_36 ;
  wire \rd_mux_sel_r_reg[1]_37 ;
  wire \rd_mux_sel_r_reg[1]_38 ;
  wire \rd_mux_sel_r_reg[1]_39 ;
  wire \rd_mux_sel_r_reg[1]_4 ;
  wire \rd_mux_sel_r_reg[1]_40 ;
  wire \rd_mux_sel_r_reg[1]_41 ;
  wire \rd_mux_sel_r_reg[1]_42 ;
  wire \rd_mux_sel_r_reg[1]_43 ;
  wire \rd_mux_sel_r_reg[1]_44 ;
  wire \rd_mux_sel_r_reg[1]_45 ;
  wire \rd_mux_sel_r_reg[1]_46 ;
  wire \rd_mux_sel_r_reg[1]_47 ;
  wire \rd_mux_sel_r_reg[1]_48 ;
  wire \rd_mux_sel_r_reg[1]_49 ;
  wire \rd_mux_sel_r_reg[1]_5 ;
  wire \rd_mux_sel_r_reg[1]_50 ;
  wire \rd_mux_sel_r_reg[1]_51 ;
  wire \rd_mux_sel_r_reg[1]_52 ;
  wire \rd_mux_sel_r_reg[1]_53 ;
  wire \rd_mux_sel_r_reg[1]_54 ;
  wire \rd_mux_sel_r_reg[1]_55 ;
  wire \rd_mux_sel_r_reg[1]_56 ;
  wire \rd_mux_sel_r_reg[1]_57 ;
  wire \rd_mux_sel_r_reg[1]_58 ;
  wire \rd_mux_sel_r_reg[1]_59 ;
  wire \rd_mux_sel_r_reg[1]_6 ;
  wire \rd_mux_sel_r_reg[1]_60 ;
  wire \rd_mux_sel_r_reg[1]_61 ;
  wire \rd_mux_sel_r_reg[1]_62 ;
  wire \rd_mux_sel_r_reg[1]_7 ;
  wire \rd_mux_sel_r_reg[1]_8 ;
  wire \rd_mux_sel_r_reg[1]_9 ;
  wire [2:0]\rd_mux_sel_r_reg[2] ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire rst_r4;
  wire sync_pulse;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[570] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .B_idelay_ce9_out(B_idelay_ce9_out),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .\ddr3_dm[2] (\ddr3_dm[2] ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .iserdes_clkdiv(iserdes_clkdiv),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_15_in(p_15_in),
        .p_161_in(p_161_in),
        .p_162_in(p_162_in),
        .p_163_out(p_163_out),
        .p_165_in(p_165_in),
        .p_166_in(p_166_in),
        .p_167_out(p_167_out),
        .p_169_in(p_169_in),
        .p_170_in(p_170_in),
        .p_171_out(p_171_out),
        .p_173_in(p_173_in),
        .p_174_in(p_174_in),
        .p_175_out(p_175_out),
        .p_177_in(p_177_in),
        .p_178_in(p_178_in),
        .p_179_out(p_179_out),
        .p_181_in(p_181_in),
        .p_182_in(p_182_in),
        .p_183_out(p_183_out),
        .p_185_in(p_185_in),
        .p_186_in(p_186_in),
        .p_187_out(p_187_out),
        .p_189_in(p_189_in),
        .p_190_in(p_190_in),
        .p_191_out(p_191_out),
        .p_27_in(p_27_in),
        .p_28_in(p_28_in),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(\my_full_reg[0] ),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(rd_data_r[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(rd_data_r[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[2]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[3]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[4]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[5]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(rd_data_r[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[6]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[7]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[0]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[1]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[2]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[3]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[4]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[5]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[6]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[7]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(rd_data_r[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(rd_data_r[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(rd_data_r[9]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_10 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.B_byte_rd_en(B_byte_rd_en),
        .CLK(CLK),
        .C_byte_rd_en(C_byte_rd_en),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .Q(Q),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\my_full_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ({rd_data_r[79:48],rd_data_r[41:6]}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (\gen_rd[2].rd_data_rise_wl_r_reg[2] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .ififo_rst(ififo_rst),
        .\not_strict_mode.app_rd_data_reg[471] (\not_strict_mode.app_rd_data_reg[471] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .p_0_out(p_0_out),
        .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ),
        .\po_stg2_wrcal_cnt_reg[1]_0 (\po_stg2_wrcal_cnt_reg[1]_0 ),
        .\po_stg2_wrcal_cnt_reg[1]_1 (\po_stg2_wrcal_cnt_reg[1]_1 ),
        .\po_stg2_wrcal_cnt_reg[1]_10 (\po_stg2_wrcal_cnt_reg[1]_10 ),
        .\po_stg2_wrcal_cnt_reg[1]_11 (\po_stg2_wrcal_cnt_reg[1]_11 ),
        .\po_stg2_wrcal_cnt_reg[1]_12 (\po_stg2_wrcal_cnt_reg[1]_12 ),
        .\po_stg2_wrcal_cnt_reg[1]_13 (\po_stg2_wrcal_cnt_reg[1]_13 ),
        .\po_stg2_wrcal_cnt_reg[1]_14 (\po_stg2_wrcal_cnt_reg[1]_14 ),
        .\po_stg2_wrcal_cnt_reg[1]_15 (\po_stg2_wrcal_cnt_reg[1]_15 ),
        .\po_stg2_wrcal_cnt_reg[1]_16 (\po_stg2_wrcal_cnt_reg[1]_16 ),
        .\po_stg2_wrcal_cnt_reg[1]_17 (\po_stg2_wrcal_cnt_reg[1]_17 ),
        .\po_stg2_wrcal_cnt_reg[1]_18 (\po_stg2_wrcal_cnt_reg[1]_18 ),
        .\po_stg2_wrcal_cnt_reg[1]_19 (\po_stg2_wrcal_cnt_reg[1]_19 ),
        .\po_stg2_wrcal_cnt_reg[1]_2 (\po_stg2_wrcal_cnt_reg[1]_2 ),
        .\po_stg2_wrcal_cnt_reg[1]_20 (\po_stg2_wrcal_cnt_reg[1]_20 ),
        .\po_stg2_wrcal_cnt_reg[1]_21 (\po_stg2_wrcal_cnt_reg[1]_21 ),
        .\po_stg2_wrcal_cnt_reg[1]_22 (\po_stg2_wrcal_cnt_reg[1]_22 ),
        .\po_stg2_wrcal_cnt_reg[1]_23 (\po_stg2_wrcal_cnt_reg[1]_23 ),
        .\po_stg2_wrcal_cnt_reg[1]_24 (\po_stg2_wrcal_cnt_reg[1]_24 ),
        .\po_stg2_wrcal_cnt_reg[1]_25 (\po_stg2_wrcal_cnt_reg[1]_25 ),
        .\po_stg2_wrcal_cnt_reg[1]_26 (\po_stg2_wrcal_cnt_reg[1]_26 ),
        .\po_stg2_wrcal_cnt_reg[1]_27 (\po_stg2_wrcal_cnt_reg[1]_27 ),
        .\po_stg2_wrcal_cnt_reg[1]_28 (\po_stg2_wrcal_cnt_reg[1]_28 ),
        .\po_stg2_wrcal_cnt_reg[1]_29 (\po_stg2_wrcal_cnt_reg[1]_29 ),
        .\po_stg2_wrcal_cnt_reg[1]_3 (\po_stg2_wrcal_cnt_reg[1]_3 ),
        .\po_stg2_wrcal_cnt_reg[1]_30 (\po_stg2_wrcal_cnt_reg[1]_30 ),
        .\po_stg2_wrcal_cnt_reg[1]_31 (\po_stg2_wrcal_cnt_reg[1]_31 ),
        .\po_stg2_wrcal_cnt_reg[1]_32 (\po_stg2_wrcal_cnt_reg[1]_32 ),
        .\po_stg2_wrcal_cnt_reg[1]_33 (\po_stg2_wrcal_cnt_reg[1]_33 ),
        .\po_stg2_wrcal_cnt_reg[1]_34 (\po_stg2_wrcal_cnt_reg[1]_34 ),
        .\po_stg2_wrcal_cnt_reg[1]_35 (\po_stg2_wrcal_cnt_reg[1]_35 ),
        .\po_stg2_wrcal_cnt_reg[1]_36 (\po_stg2_wrcal_cnt_reg[1]_36 ),
        .\po_stg2_wrcal_cnt_reg[1]_37 (\po_stg2_wrcal_cnt_reg[1]_37 ),
        .\po_stg2_wrcal_cnt_reg[1]_38 (\po_stg2_wrcal_cnt_reg[1]_38 ),
        .\po_stg2_wrcal_cnt_reg[1]_39 (\po_stg2_wrcal_cnt_reg[1]_39 ),
        .\po_stg2_wrcal_cnt_reg[1]_4 (\po_stg2_wrcal_cnt_reg[1]_4 ),
        .\po_stg2_wrcal_cnt_reg[1]_40 (\po_stg2_wrcal_cnt_reg[1]_40 ),
        .\po_stg2_wrcal_cnt_reg[1]_41 (\po_stg2_wrcal_cnt_reg[1]_41 ),
        .\po_stg2_wrcal_cnt_reg[1]_42 (\po_stg2_wrcal_cnt_reg[1]_42 ),
        .\po_stg2_wrcal_cnt_reg[1]_43 (\po_stg2_wrcal_cnt_reg[1]_43 ),
        .\po_stg2_wrcal_cnt_reg[1]_44 (\po_stg2_wrcal_cnt_reg[1]_44 ),
        .\po_stg2_wrcal_cnt_reg[1]_45 (\po_stg2_wrcal_cnt_reg[1]_45 ),
        .\po_stg2_wrcal_cnt_reg[1]_46 (\po_stg2_wrcal_cnt_reg[1]_46 ),
        .\po_stg2_wrcal_cnt_reg[1]_47 (\po_stg2_wrcal_cnt_reg[1]_47 ),
        .\po_stg2_wrcal_cnt_reg[1]_48 (\po_stg2_wrcal_cnt_reg[1]_48 ),
        .\po_stg2_wrcal_cnt_reg[1]_49 (\po_stg2_wrcal_cnt_reg[1]_49 ),
        .\po_stg2_wrcal_cnt_reg[1]_5 (\po_stg2_wrcal_cnt_reg[1]_5 ),
        .\po_stg2_wrcal_cnt_reg[1]_50 (\po_stg2_wrcal_cnt_reg[1]_50 ),
        .\po_stg2_wrcal_cnt_reg[1]_51 (\po_stg2_wrcal_cnt_reg[1]_51 ),
        .\po_stg2_wrcal_cnt_reg[1]_52 (\po_stg2_wrcal_cnt_reg[1]_52 ),
        .\po_stg2_wrcal_cnt_reg[1]_53 (\po_stg2_wrcal_cnt_reg[1]_53 ),
        .\po_stg2_wrcal_cnt_reg[1]_54 (\po_stg2_wrcal_cnt_reg[1]_54 ),
        .\po_stg2_wrcal_cnt_reg[1]_55 (\po_stg2_wrcal_cnt_reg[1]_55 ),
        .\po_stg2_wrcal_cnt_reg[1]_56 (\po_stg2_wrcal_cnt_reg[1]_56 ),
        .\po_stg2_wrcal_cnt_reg[1]_57 (\po_stg2_wrcal_cnt_reg[1]_57 ),
        .\po_stg2_wrcal_cnt_reg[1]_58 (\po_stg2_wrcal_cnt_reg[1]_58 ),
        .\po_stg2_wrcal_cnt_reg[1]_59 (\po_stg2_wrcal_cnt_reg[1]_59 ),
        .\po_stg2_wrcal_cnt_reg[1]_6 (\po_stg2_wrcal_cnt_reg[1]_6 ),
        .\po_stg2_wrcal_cnt_reg[1]_60 (\po_stg2_wrcal_cnt_reg[1]_60 ),
        .\po_stg2_wrcal_cnt_reg[1]_61 (\po_stg2_wrcal_cnt_reg[1]_61 ),
        .\po_stg2_wrcal_cnt_reg[1]_62 (\po_stg2_wrcal_cnt_reg[1]_62 ),
        .\po_stg2_wrcal_cnt_reg[1]_7 (\po_stg2_wrcal_cnt_reg[1]_7 ),
        .\po_stg2_wrcal_cnt_reg[1]_8 (\po_stg2_wrcal_cnt_reg[1]_8 ),
        .\po_stg2_wrcal_cnt_reg[1]_9 (\po_stg2_wrcal_cnt_reg[1]_9 ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ),
        .\rd_mux_sel_r_reg[1]_0 (\rd_mux_sel_r_reg[1]_0 ),
        .\rd_mux_sel_r_reg[1]_1 (\rd_mux_sel_r_reg[1]_1 ),
        .\rd_mux_sel_r_reg[1]_10 (\rd_mux_sel_r_reg[1]_10 ),
        .\rd_mux_sel_r_reg[1]_11 (\rd_mux_sel_r_reg[1]_11 ),
        .\rd_mux_sel_r_reg[1]_12 (\rd_mux_sel_r_reg[1]_12 ),
        .\rd_mux_sel_r_reg[1]_13 (\rd_mux_sel_r_reg[1]_13 ),
        .\rd_mux_sel_r_reg[1]_14 (\rd_mux_sel_r_reg[1]_14 ),
        .\rd_mux_sel_r_reg[1]_15 (\rd_mux_sel_r_reg[1]_15 ),
        .\rd_mux_sel_r_reg[1]_16 (\rd_mux_sel_r_reg[1]_16 ),
        .\rd_mux_sel_r_reg[1]_17 (\rd_mux_sel_r_reg[1]_17 ),
        .\rd_mux_sel_r_reg[1]_18 (\rd_mux_sel_r_reg[1]_18 ),
        .\rd_mux_sel_r_reg[1]_19 (\rd_mux_sel_r_reg[1]_19 ),
        .\rd_mux_sel_r_reg[1]_2 (\rd_mux_sel_r_reg[1]_2 ),
        .\rd_mux_sel_r_reg[1]_20 (\rd_mux_sel_r_reg[1]_20 ),
        .\rd_mux_sel_r_reg[1]_21 (\rd_mux_sel_r_reg[1]_21 ),
        .\rd_mux_sel_r_reg[1]_22 (\rd_mux_sel_r_reg[1]_22 ),
        .\rd_mux_sel_r_reg[1]_23 (\rd_mux_sel_r_reg[1]_23 ),
        .\rd_mux_sel_r_reg[1]_24 (\rd_mux_sel_r_reg[1]_24 ),
        .\rd_mux_sel_r_reg[1]_25 (\rd_mux_sel_r_reg[1]_25 ),
        .\rd_mux_sel_r_reg[1]_26 (\rd_mux_sel_r_reg[1]_26 ),
        .\rd_mux_sel_r_reg[1]_27 (\rd_mux_sel_r_reg[1]_27 ),
        .\rd_mux_sel_r_reg[1]_28 (\rd_mux_sel_r_reg[1]_28 ),
        .\rd_mux_sel_r_reg[1]_29 (\rd_mux_sel_r_reg[1]_29 ),
        .\rd_mux_sel_r_reg[1]_3 (\rd_mux_sel_r_reg[1]_3 ),
        .\rd_mux_sel_r_reg[1]_30 (\rd_mux_sel_r_reg[1]_30 ),
        .\rd_mux_sel_r_reg[1]_31 (\rd_mux_sel_r_reg[1]_31 ),
        .\rd_mux_sel_r_reg[1]_32 (\rd_mux_sel_r_reg[1]_32 ),
        .\rd_mux_sel_r_reg[1]_33 (\rd_mux_sel_r_reg[1]_33 ),
        .\rd_mux_sel_r_reg[1]_34 (\rd_mux_sel_r_reg[1]_34 ),
        .\rd_mux_sel_r_reg[1]_35 (\rd_mux_sel_r_reg[1]_35 ),
        .\rd_mux_sel_r_reg[1]_36 (\rd_mux_sel_r_reg[1]_36 ),
        .\rd_mux_sel_r_reg[1]_37 (\rd_mux_sel_r_reg[1]_37 ),
        .\rd_mux_sel_r_reg[1]_38 (\rd_mux_sel_r_reg[1]_38 ),
        .\rd_mux_sel_r_reg[1]_39 (\rd_mux_sel_r_reg[1]_39 ),
        .\rd_mux_sel_r_reg[1]_4 (\rd_mux_sel_r_reg[1]_4 ),
        .\rd_mux_sel_r_reg[1]_40 (\rd_mux_sel_r_reg[1]_40 ),
        .\rd_mux_sel_r_reg[1]_41 (\rd_mux_sel_r_reg[1]_41 ),
        .\rd_mux_sel_r_reg[1]_42 (\rd_mux_sel_r_reg[1]_42 ),
        .\rd_mux_sel_r_reg[1]_43 (\rd_mux_sel_r_reg[1]_43 ),
        .\rd_mux_sel_r_reg[1]_44 (\rd_mux_sel_r_reg[1]_44 ),
        .\rd_mux_sel_r_reg[1]_45 (\rd_mux_sel_r_reg[1]_45 ),
        .\rd_mux_sel_r_reg[1]_46 (\rd_mux_sel_r_reg[1]_46 ),
        .\rd_mux_sel_r_reg[1]_47 (\rd_mux_sel_r_reg[1]_47 ),
        .\rd_mux_sel_r_reg[1]_48 (\rd_mux_sel_r_reg[1]_48 ),
        .\rd_mux_sel_r_reg[1]_49 (\rd_mux_sel_r_reg[1]_49 ),
        .\rd_mux_sel_r_reg[1]_5 (\rd_mux_sel_r_reg[1]_5 ),
        .\rd_mux_sel_r_reg[1]_50 (\rd_mux_sel_r_reg[1]_50 ),
        .\rd_mux_sel_r_reg[1]_51 (\rd_mux_sel_r_reg[1]_51 ),
        .\rd_mux_sel_r_reg[1]_52 (\rd_mux_sel_r_reg[1]_52 ),
        .\rd_mux_sel_r_reg[1]_53 (\rd_mux_sel_r_reg[1]_53 ),
        .\rd_mux_sel_r_reg[1]_54 (\rd_mux_sel_r_reg[1]_54 ),
        .\rd_mux_sel_r_reg[1]_55 (\rd_mux_sel_r_reg[1]_55 ),
        .\rd_mux_sel_r_reg[1]_56 (\rd_mux_sel_r_reg[1]_56 ),
        .\rd_mux_sel_r_reg[1]_57 (\rd_mux_sel_r_reg[1]_57 ),
        .\rd_mux_sel_r_reg[1]_58 (\rd_mux_sel_r_reg[1]_58 ),
        .\rd_mux_sel_r_reg[1]_59 (\rd_mux_sel_r_reg[1]_59 ),
        .\rd_mux_sel_r_reg[1]_6 (\rd_mux_sel_r_reg[1]_6 ),
        .\rd_mux_sel_r_reg[1]_60 (\rd_mux_sel_r_reg[1]_60 ),
        .\rd_mux_sel_r_reg[1]_61 (\rd_mux_sel_r_reg[1]_61 ),
        .\rd_mux_sel_r_reg[1]_62 (\rd_mux_sel_r_reg[1]_62 ),
        .\rd_mux_sel_r_reg[1]_7 (\rd_mux_sel_r_reg[1]_7 ),
        .\rd_mux_sel_r_reg[1]_8 (\rd_mux_sel_r_reg[1]_8 ),
        .\rd_mux_sel_r_reg[1]_9 (\rd_mux_sel_r_reg[1]_9 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(B_pi_rst_dqs_find32_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],1'b0,1'b0,1'b0,1'b0}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized3 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }),
        .D1({of_d1[5],of_d1[1:0]}),
        .D2({of_d2[4:3],of_d2[1]}),
        .D3({of_d3[4],of_d3[2]}),
        .D4({of_d4[7],of_d4[0]}),
        .D5(of_d5),
        .D6({of_d6[5],of_d6[1:0]}),
        .D7({of_d7[4:3],of_d7[1]}),
        .D8({of_d8[4],of_d8[2]}),
        .D9({of_d9[7],of_d9[0]}),
        .calib_wrdata_en(calib_wrdata_en),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4),
        .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),
        .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7] ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(out_fifo_n_3),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .\write_buffer.wr_buf_out_data_reg[570] (\write_buffer.wr_buf_out_data_reg[570] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(B_pi_rst_dqs_find32_out),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }),
        .D1({\write_buffer.wr_buf_out_data_reg[471] [4:3],of_d1[5],\write_buffer.wr_buf_out_data_reg[471] [2:0],of_d1[1:0]}),
        .D2({\write_buffer.wr_buf_out_data_reg[470] [4:2],of_d2[4:3],\write_buffer.wr_buf_out_data_reg[470] [1],of_d2[1],\write_buffer.wr_buf_out_data_reg[470] [0]}),
        .D3({\write_buffer.wr_buf_out_data_reg[469] [5:3],of_d3[4],\write_buffer.wr_buf_out_data_reg[469] [2],of_d3[2],\write_buffer.wr_buf_out_data_reg[469] [1:0]}),
        .D4({of_d4[7],\write_buffer.wr_buf_out_data_reg[404] ,of_d4[0]}),
        .D5(of_d5),
        .D6({\write_buffer.wr_buf_out_data_reg[467] [4:3],of_d6[5],\write_buffer.wr_buf_out_data_reg[467] [2:0],of_d6[1:0]}),
        .D7({\write_buffer.wr_buf_out_data_reg[466] [4:2],of_d7[4:3],\write_buffer.wr_buf_out_data_reg[466] [1],of_d7[1],\write_buffer.wr_buf_out_data_reg[466] [0]}),
        .D8({\write_buffer.wr_buf_out_data_reg[465] [5:3],of_d8[4],\write_buffer.wr_buf_out_data_reg[465] [2],of_d8[2],\write_buffer.wr_buf_out_data_reg[465] [1:0]}),
        .D9({of_d9[7],\write_buffer.wr_buf_out_data_reg[400] ,of_d9[0]}),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(B_pi_counter_load_en38_out),
        .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(B_pi_fine_enable34_out),
        .FINEINC(B_pi_fine_inc36_out),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(pi_phase_locked_all_r1_reg),
        .PHASEREFCLK(p_29_out),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(rclk_),
        .RST(A_rst_primitives),
        .RSTDQSFIND(B_pi_rst_dqs_find32_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(B_po_coarse_enable20_out),
        .COARSEINC(B_po_coarse_enable20_out),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(\po_counter_read_val_reg[8] ),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(B_po_fine_enable18_out),
        .FINEINC(B_po_fine_inc22_out),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1
   (pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[2] ,
    p_32_in,
    p_194_in,
    p_193_in,
    p_198_in,
    p_197_in,
    p_202_in,
    p_201_in,
    p_206_in,
    p_205_in,
    p_210_in,
    p_209_in,
    p_214_in,
    p_213_in,
    p_218_in,
    p_217_in,
    p_222_in,
    p_221_in,
    p_19_in,
    \ddr3_dm[1] ,
    \my_full_reg[0] ,
    idelay_ld_rst_1,
    Q,
    \my_empty_reg[4]_rep__1 ,
    ofs_rdy_r_reg,
    \entry_cnt_reg[4] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ,
    \my_empty_reg[1] ,
    pi_phase_locked_all_r1_reg,
    \not_strict_mode.app_rd_data_reg[463] ,
    \wr_ptr_reg[1] ,
    \my_empty_reg[7] ,
    C_byte_rd_en,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    phaser_ctl_bus,
    C_pi_counter_load_en64_out,
    \calib_sel_reg[1] ,
    C_pi_fine_enable60_out,
    C_pi_fine_inc62_out,
    freq_refclk,
    mem_refclk,
    p_34_out,
    A_rst_primitives,
    C_pi_rst_dqs_find58_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    \calib_zero_inputs_reg[0] ,
    C_po_coarse_enable46_out,
    C_po_fine_enable44_out,
    C_po_fine_inc48_out,
    \write_buffer.wr_buf_out_data_reg[463] ,
    \write_buffer.wr_buf_out_data_reg[462] ,
    \write_buffer.wr_buf_out_data_reg[461] ,
    \write_buffer.wr_buf_out_data_reg[396] ,
    \write_buffer.wr_buf_out_data_reg[459] ,
    \write_buffer.wr_buf_out_data_reg[458] ,
    \write_buffer.wr_buf_out_data_reg[457] ,
    \write_buffer.wr_buf_out_data_reg[392] ,
    A_rst_primitives_reg,
    p_195_out,
    C_idelay_ce5_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_199_out,
    p_203_out,
    p_207_out,
    p_211_out,
    p_215_out,
    p_219_out,
    p_223_out,
    phy_if_reset,
    phy_data_wr_en,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    B_byte_rd_en,
    if_empty_r_2,
    \my_empty_reg[3] ,
    \entry_cnt_reg[3] ,
    \entry_cnt_reg[3]_0 ,
    rst_r4,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__6,
    mc_wrdata_en,
    \write_buffer.wr_buf_out_data_reg[569] ,
    init_calib_complete_reg_rep__7,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    phy_dout);
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output [5:0]COUNTERREADVAL;
  output [8:0]\po_counter_read_val_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[2] ;
  output p_32_in;
  output p_194_in;
  output p_193_in;
  output p_198_in;
  output p_197_in;
  output p_202_in;
  output p_201_in;
  output p_206_in;
  output p_205_in;
  output p_210_in;
  output p_209_in;
  output p_214_in;
  output p_213_in;
  output p_218_in;
  output p_217_in;
  output p_222_in;
  output p_221_in;
  output p_19_in;
  output \ddr3_dm[1] ;
  output \my_full_reg[0] ;
  output idelay_ld_rst_1;
  output [1:0]Q;
  output \my_empty_reg[4]_rep__1 ;
  output ofs_rdy_r_reg;
  output [0:0]\entry_cnt_reg[4] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  output \my_empty_reg[1] ;
  output pi_phase_locked_all_r1_reg;
  output [63:0]\not_strict_mode.app_rd_data_reg[463] ;
  output \wr_ptr_reg[1] ;
  output [43:0]\my_empty_reg[7] ;
  output C_byte_rd_en;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input [3:0]phaser_ctl_bus;
  input C_pi_counter_load_en64_out;
  input \calib_sel_reg[1] ;
  input C_pi_fine_enable60_out;
  input C_pi_fine_inc62_out;
  input freq_refclk;
  input mem_refclk;
  input p_34_out;
  input A_rst_primitives;
  input C_pi_rst_dqs_find58_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [5:0]\calib_zero_inputs_reg[0] ;
  input C_po_coarse_enable46_out;
  input C_po_fine_enable44_out;
  input C_po_fine_inc48_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  input A_rst_primitives_reg;
  input p_195_out;
  input C_idelay_ce5_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_199_out;
  input p_203_out;
  input p_207_out;
  input p_211_out;
  input p_215_out;
  input p_219_out;
  input p_223_out;
  input phy_if_reset;
  input phy_data_wr_en;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  input B_byte_rd_en;
  input [0:0]if_empty_r_2;
  input [0:0]\my_empty_reg[3] ;
  input [1:0]\entry_cnt_reg[3] ;
  input [1:0]\entry_cnt_reg[3]_0 ;
  input rst_r4;
  input A_rst_primitives_reg_0;
  input A_rst_primitives_reg_1;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__6;
  input mc_wrdata_en;
  input [27:0]\write_buffer.wr_buf_out_data_reg[569] ;
  input init_calib_complete_reg_rep__7;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  input [71:0]phy_dout;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire B_byte_rd_en;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire C_byte_rd_en;
  wire C_idelay_ce5_out;
  wire C_pi_counter_load_en64_out;
  wire C_pi_fine_enable60_out;
  wire C_pi_fine_inc62_out;
  wire C_pi_rst_dqs_find58_out;
  wire C_po_coarse_enable46_out;
  wire C_po_fine_enable44_out;
  wire C_po_fine_inc48_out;
  wire [1:0]PCENABLECALIB;
  wire [1:0]Q;
  wire \calib_sel_reg[1] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[0] ;
  wire \ddr3_dm[1] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire [1:0]\entry_cnt_reg[3] ;
  wire [1:0]\entry_cnt_reg[3]_0 ;
  wire [0:0]\entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst_1;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire if_empty_;
  wire [0:0]if_empty_r_2;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire init_calib_complete_reg_rep__6;
  wire init_calib_complete_reg_rep__7;
  wire iserdes_clkdiv;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [0:0]\my_empty_reg[3] ;
  wire \my_empty_reg[4]_rep__1 ;
  wire [43:0]\my_empty_reg[7] ;
  wire \my_full_reg[0] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[463] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [5:0]of_d1;
  wire [4:1]of_d2;
  wire [4:2]of_d3;
  wire [7:0]of_d4;
  wire [5:0]of_d5;
  wire [4:1]of_d6;
  wire [4:2]of_d7;
  wire [7:0]of_d8;
  wire [7:0]of_d9;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofs_rdy_r_reg;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_193_in;
  wire p_194_in;
  wire p_195_out;
  wire p_197_in;
  wire p_198_in;
  wire p_199_out;
  wire p_19_in;
  wire p_201_in;
  wire p_202_in;
  wire p_203_out;
  wire p_205_in;
  wire p_206_in;
  wire p_207_out;
  wire p_209_in;
  wire p_210_in;
  wire p_211_out;
  wire p_213_in;
  wire p_214_in;
  wire p_215_out;
  wire p_217_in;
  wire p_218_in;
  wire p_219_out;
  wire p_221_in;
  wire p_222_in;
  wire p_223_out;
  wire p_32_in;
  wire p_34_out;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_6 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_if_reset;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire pi_phase_locked_all_r1_reg;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [71:6]rd_data_r;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire rst_r4;
  wire sync_pulse;
  wire \wr_ptr_reg[1] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[569] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .C_idelay_ce5_out(C_idelay_ce5_out),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .\ddr3_dm[1] (\ddr3_dm[1] ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .iserdes_clkdiv(iserdes_clkdiv),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_193_in(p_193_in),
        .p_194_in(p_194_in),
        .p_195_out(p_195_out),
        .p_197_in(p_197_in),
        .p_198_in(p_198_in),
        .p_199_out(p_199_out),
        .p_19_in(p_19_in),
        .p_201_in(p_201_in),
        .p_202_in(p_202_in),
        .p_203_out(p_203_out),
        .p_205_in(p_205_in),
        .p_206_in(p_206_in),
        .p_207_out(p_207_out),
        .p_209_in(p_209_in),
        .p_210_in(p_210_in),
        .p_211_out(p_211_out),
        .p_213_in(p_213_in),
        .p_214_in(p_214_in),
        .p_215_out(p_215_out),
        .p_217_in(p_217_in),
        .p_218_in(p_218_in),
        .p_219_out(p_219_out),
        .p_221_in(p_221_in),
        .p_222_in(p_222_in),
        .p_223_out(p_223_out),
        .p_32_in(p_32_in),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(\my_full_reg[0] ),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(rd_data_r[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(rd_data_r[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[2]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[3]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[4]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[5]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[6]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[7]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[2]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[3]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[4]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[5]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(rd_data_r[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[6]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[7]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(rd_data_r[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(rd_data_r[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(rd_data_r[9]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_9 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.B_byte_rd_en(B_byte_rd_en),
        .CLK(CLK),
        .C_byte_rd_en(C_byte_rd_en),
        .Q(Q),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\my_full_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (rd_data_r),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .if_empty_r_2(if_empty_r_2),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\my_empty_reg[4]_rep__1_0 (\my_empty_reg[4]_rep__1 ),
        .\not_strict_mode.app_rd_data_reg[463] (\not_strict_mode.app_rd_data_reg[463] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(C_pi_rst_dqs_find58_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9({1'b0,1'b0,1'b0,1'b0}),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized4 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }),
        .D1({of_d1[5],of_d1[1:0]}),
        .D2({of_d2[4:3],of_d2[1]}),
        .D3({of_d3[4],of_d3[2]}),
        .D4({of_d4[7],of_d4[0]}),
        .D5({of_d5[5],of_d5[1:0]}),
        .D6({of_d6[4:3],of_d6[1]}),
        .D7({of_d7[4],of_d7[2]}),
        .D8({of_d8[7],of_d8[0]}),
        .D9(of_d9),
        .calib_wrdata_en(calib_wrdata_en),
        .\entry_cnt_reg[3]_0 (\entry_cnt_reg[3] ),
        .\entry_cnt_reg[3]_1 (\entry_cnt_reg[3]_0 ),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),
        .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7] ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(out_fifo_n_3),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .\write_buffer.wr_buf_out_data_reg[569] (\write_buffer.wr_buf_out_data_reg[569] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(C_pi_rst_dqs_find58_out),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }),
        .D1({\write_buffer.wr_buf_out_data_reg[463] [4:3],of_d1[5],\write_buffer.wr_buf_out_data_reg[463] [2:0],of_d1[1:0]}),
        .D2({\write_buffer.wr_buf_out_data_reg[462] [4:2],of_d2[4:3],\write_buffer.wr_buf_out_data_reg[462] [1],of_d2[1],\write_buffer.wr_buf_out_data_reg[462] [0]}),
        .D3({\write_buffer.wr_buf_out_data_reg[461] [5:3],of_d3[4],\write_buffer.wr_buf_out_data_reg[461] [2],of_d3[2],\write_buffer.wr_buf_out_data_reg[461] [1:0]}),
        .D4({of_d4[7],\write_buffer.wr_buf_out_data_reg[396] ,of_d4[0]}),
        .D5({\write_buffer.wr_buf_out_data_reg[459] [4:3],of_d5[5],\write_buffer.wr_buf_out_data_reg[459] [2:0],of_d5[1:0]}),
        .D6({\write_buffer.wr_buf_out_data_reg[458] [4:2],of_d6[4:3],\write_buffer.wr_buf_out_data_reg[458] [1],of_d6[1],\write_buffer.wr_buf_out_data_reg[458] [0]}),
        .D7({\write_buffer.wr_buf_out_data_reg[457] [5:3],of_d7[4],\write_buffer.wr_buf_out_data_reg[457] [2],of_d7[2],\write_buffer.wr_buf_out_data_reg[457] [1:0]}),
        .D8({of_d8[7],\write_buffer.wr_buf_out_data_reg[392] ,of_d8[0]}),
        .D9(of_d9),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(C_pi_counter_load_en64_out),
        .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ),
        .COUNTERREADEN(\calib_sel_reg[1] ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(C_pi_fine_enable60_out),
        .FINEINC(C_pi_fine_inc62_out),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(\phaser_in_gen.phaser_in_n_6 ),
        .PHASEREFCLK(p_34_out),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(C_pi_rst_dqs_find58_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(C_po_coarse_enable46_out),
        .COARSEINC(C_po_coarse_enable46_out),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[1] ),
        .COUNTERREADVAL(\po_counter_read_val_reg[8] ),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(C_po_fine_enable44_out),
        .FINEINC(C_po_fine_inc48_out),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
  LUT3 #(
    .INIT(8'h80)) 
    pi_phase_locked_all_inferred_i_1
       (.I0(\phaser_in_gen.phaser_in_n_6 ),
        .I1(A_rst_primitives_reg_0),
        .I2(A_rst_primitives_reg_1),
        .O(pi_phase_locked_all_r1_reg));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized2
   (pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    p_226_in,
    p_225_in,
    p_230_in,
    p_229_in,
    p_234_in,
    p_233_in,
    p_238_in,
    p_237_in,
    p_242_in,
    p_241_in,
    p_246_in,
    p_245_in,
    p_250_in,
    p_249_in,
    p_254_in,
    p_253_in,
    \ddr3_dm[0] ,
    p_21_in,
    if_empty_r_2,
    idelay_ld_rst_2,
    Q,
    phy_mc_data_full,
    \wr_ptr_reg[1] ,
    \my_empty_reg[4]_rep__1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ,
    \my_empty_reg[1] ,
    \entry_cnt_reg[4] ,
    pi_phase_locked_all_r1_reg,
    \not_strict_mode.app_rd_data_reg[455] ,
    \my_empty_reg[7] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    D,
    \po_counter_read_val_reg[8] ,
    phaser_ctl_bus,
    D_pi_counter_load_en90_out,
    \calib_sel_reg[0] ,
    D_pi_fine_enable86_out,
    D_pi_fine_inc88_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_rst_primitives,
    D_pi_rst_dqs_find84_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    \calib_zero_inputs_reg[0] ,
    D_po_coarse_enable72_out,
    D_po_fine_enable70_out,
    D_po_fine_inc74_out,
    \write_buffer.wr_buf_out_data_reg[455] ,
    \write_buffer.wr_buf_out_data_reg[454] ,
    \write_buffer.wr_buf_out_data_reg[453] ,
    \write_buffer.wr_buf_out_data_reg[388] ,
    \write_buffer.wr_buf_out_data_reg[451] ,
    \write_buffer.wr_buf_out_data_reg[450] ,
    \write_buffer.wr_buf_out_data_reg[449] ,
    \write_buffer.wr_buf_out_data_reg[384] ,
    A_rst_primitives_reg,
    p_227_out,
    D_idelay_ce1_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_231_out,
    p_235_out,
    p_239_out,
    p_243_out,
    p_247_out,
    p_251_out,
    p_255_out,
    phy_if_reset,
    phy_data_wr_en,
    if_empty_r_1,
    my_empty,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \my_empty_reg[3] ,
    \entry_cnt_reg[3] ,
    \entry_cnt_reg[2] ,
    \entry_cnt_reg[3]_0 ,
    \entry_cnt_reg[3]_1 ,
    if_empty_r_3,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[3]_1 ,
    if_empty_r,
    if_empty_r_0,
    \my_empty_reg[3]_2 ,
    rst_r4,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    \read_fifo.fifo_out_data_r_reg[4] ,
    DOC,
    DOB,
    DOA,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__7,
    mc_wrdata_en,
    init_calib_complete_reg_rep__8,
    \write_buffer.wr_buf_out_data_reg[568] ,
    init_calib_complete_reg_rep__9,
    phy_dout,
    COUNTERREADVAL,
    \calib_sel_reg[1] ,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    A_rst_primitives_reg_7,
    A_rst_primitives_reg_8,
    A_rst_primitives_reg_9);
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \pi_dqs_found_lanes_r1_reg[3] ;
  output \pi_dqs_found_lanes_r1_reg[3]_0 ;
  output p_226_in;
  output p_225_in;
  output p_230_in;
  output p_229_in;
  output p_234_in;
  output p_233_in;
  output p_238_in;
  output p_237_in;
  output p_242_in;
  output p_241_in;
  output p_246_in;
  output p_245_in;
  output p_250_in;
  output p_249_in;
  output p_254_in;
  output p_253_in;
  output \ddr3_dm[0] ;
  output p_21_in;
  output [0:0]if_empty_r_2;
  output idelay_ld_rst_2;
  output [0:0]Q;
  output phy_mc_data_full;
  output \wr_ptr_reg[1] ;
  output \my_empty_reg[4]_rep__1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  output \my_empty_reg[1] ;
  output [0:0]\entry_cnt_reg[4] ;
  output pi_phase_locked_all_r1_reg;
  output [63:0]\not_strict_mode.app_rd_data_reg[455] ;
  output [43:0]\my_empty_reg[7] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [5:0]D;
  output [8:0]\po_counter_read_val_reg[8] ;
  input [3:0]phaser_ctl_bus;
  input D_pi_counter_load_en90_out;
  input \calib_sel_reg[0] ;
  input D_pi_fine_enable86_out;
  input D_pi_fine_inc88_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_rst_primitives;
  input D_pi_rst_dqs_find84_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [5:0]\calib_zero_inputs_reg[0] ;
  input D_po_coarse_enable72_out;
  input D_po_fine_enable70_out;
  input D_po_fine_inc74_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  input A_rst_primitives_reg;
  input p_227_out;
  input D_idelay_ce1_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_231_out;
  input p_235_out;
  input p_239_out;
  input p_243_out;
  input p_247_out;
  input p_251_out;
  input p_255_out;
  input phy_if_reset;
  input phy_data_wr_en;
  input [0:0]if_empty_r_1;
  input [0:0]my_empty;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  input \my_empty_reg[3] ;
  input \entry_cnt_reg[3] ;
  input \entry_cnt_reg[2] ;
  input \entry_cnt_reg[3]_0 ;
  input \entry_cnt_reg[3]_1 ;
  input [0:0]if_empty_r_3;
  input [0:0]\my_empty_reg[3]_0 ;
  input [0:0]\my_empty_reg[3]_1 ;
  input [0:0]if_empty_r;
  input [0:0]if_empty_r_0;
  input [0:0]\my_empty_reg[3]_2 ;
  input rst_r4;
  input A_rst_primitives_reg_0;
  input A_rst_primitives_reg_1;
  input A_rst_primitives_reg_2;
  input A_rst_primitives_reg_3;
  input A_rst_primitives_reg_4;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]DOA;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__7;
  input mc_wrdata_en;
  input init_calib_complete_reg_rep__8;
  input [27:0]\write_buffer.wr_buf_out_data_reg[568] ;
  input init_calib_complete_reg_rep__9;
  input [71:0]phy_dout;
  input [5:0]COUNTERREADVAL;
  input [1:0]\calib_sel_reg[1] ;
  input [5:0]A_rst_primitives_reg_5;
  input [5:0]A_rst_primitives_reg_6;
  input [8:0]A_rst_primitives_reg_7;
  input [8:0]A_rst_primitives_reg_8;
  input [8:0]A_rst_primitives_reg_9;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire [5:0]A_rst_primitives_reg_5;
  wire [5:0]A_rst_primitives_reg_6;
  wire [8:0]A_rst_primitives_reg_7;
  wire [8:0]A_rst_primitives_reg_8;
  wire [8:0]A_rst_primitives_reg_9;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire [5:0]D;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire D_idelay_ce1_out;
  wire D_pi_counter_load_en90_out;
  wire [5:0]D_pi_counter_read_val;
  wire D_pi_fine_enable86_out;
  wire D_pi_fine_inc88_out;
  wire D_pi_rst_dqs_find84_out;
  wire D_po_coarse_enable72_out;
  wire [8:0]D_po_counter_read_val;
  wire D_po_fine_enable70_out;
  wire D_po_fine_inc74_out;
  wire [1:0]PCENABLECALIB;
  wire [0:0]Q;
  wire \calib_sel_reg[0] ;
  wire [1:0]\calib_sel_reg[1] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[0] ;
  wire \ddr3_dm[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \entry_cnt_reg[2] ;
  wire \entry_cnt_reg[3] ;
  wire \entry_cnt_reg[3]_0 ;
  wire \entry_cnt_reg[3]_1 ;
  wire [0:0]\entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst_2;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_r_1;
  wire [0:0]if_empty_r_2;
  wire [0:0]if_empty_r_3;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire init_calib_complete_reg_rep__7;
  wire init_calib_complete_reg_rep__8;
  wire init_calib_complete_reg_rep__9;
  wire iserdes_clkdiv;
  wire mc_read_idle_r_reg;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire [0:0]my_empty;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[3] ;
  wire [0:0]\my_empty_reg[3]_0 ;
  wire [0:0]\my_empty_reg[3]_1 ;
  wire [0:0]\my_empty_reg[3]_2 ;
  wire \my_empty_reg[4]_rep__1 ;
  wire [43:0]\my_empty_reg[7] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[455] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [5:0]of_d1;
  wire [4:1]of_d2;
  wire [4:2]of_d3;
  wire [7:0]of_d4;
  wire [5:0]of_d5;
  wire [4:1]of_d6;
  wire [4:2]of_d7;
  wire [7:0]of_d8;
  wire [7:0]of_d9;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_21_in;
  wire p_225_in;
  wire p_226_in;
  wire p_227_out;
  wire p_229_in;
  wire p_230_in;
  wire p_231_out;
  wire p_233_in;
  wire p_234_in;
  wire p_235_out;
  wire p_237_in;
  wire p_238_in;
  wire p_239_out;
  wire p_241_in;
  wire p_242_in;
  wire p_243_out;
  wire p_245_in;
  wire p_246_in;
  wire p_247_out;
  wire p_249_in;
  wire p_250_in;
  wire p_251_out;
  wire p_253_in;
  wire p_254_in;
  wire p_255_out;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_6 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_if_reset;
  wire phy_mc_data_full;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [71:6]rd_data_r;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire rst_r4;
  wire sync_pulse;
  wire \wr_ptr_reg[1] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[568] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized2 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .D_idelay_ce1_out(D_idelay_ce1_out),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .\ddr3_dm[0] (\ddr3_dm[0] ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .iserdes_clkdiv(iserdes_clkdiv),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_21_in(p_21_in),
        .p_225_in(p_225_in),
        .p_226_in(p_226_in),
        .p_227_out(p_227_out),
        .p_229_in(p_229_in),
        .p_230_in(p_230_in),
        .p_231_out(p_231_out),
        .p_233_in(p_233_in),
        .p_234_in(p_234_in),
        .p_235_out(p_235_out),
        .p_237_in(p_237_in),
        .p_238_in(p_238_in),
        .p_239_out(p_239_out),
        .p_241_in(p_241_in),
        .p_242_in(p_242_in),
        .p_243_out(p_243_out),
        .p_245_in(p_245_in),
        .p_246_in(p_246_in),
        .p_247_out(p_247_out),
        .p_249_in(p_249_in),
        .p_250_in(p_250_in),
        .p_251_out(p_251_out),
        .p_253_in(p_253_in),
        .p_254_in(p_254_in),
        .p_255_out(p_255_out),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r_2),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(rd_data_r[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(rd_data_r[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[2]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[3]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[4]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[5]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[6]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[7]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[2]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[3]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[4]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[5]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(rd_data_r[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[6]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[7]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(rd_data_r[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(rd_data_r[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(rd_data_r[9]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_8 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.CLK(CLK),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .Q(rd_data_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r_2),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_0),
        .if_empty_r_1(if_empty_r_1),
        .if_empty_r_3(if_empty_r_3),
        .ififo_rst(ififo_rst),
        .my_empty(my_empty),
        .\my_empty_reg[0]_0 (Q),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\my_empty_reg[3]_1 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[3]_2 (\my_empty_reg[3]_1 ),
        .\my_empty_reg[3]_3 (\my_empty_reg[3]_2 ),
        .\my_empty_reg[4]_rep__1_0 (\my_empty_reg[4]_rep__1 ),
        .\not_strict_mode.app_rd_data_reg[455] (\not_strict_mode.app_rd_data_reg[455] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(D_pi_rst_dqs_find84_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9({1'b0,1'b0,1'b0,1'b0}),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized5 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }),
        .D1({of_d1[5],of_d1[1:0]}),
        .D2({of_d2[4:3],of_d2[1]}),
        .D3({of_d3[4],of_d3[2]}),
        .D4({of_d4[7],of_d4[0]}),
        .D5({of_d5[5],of_d5[1:0]}),
        .D6({of_d6[4:3],of_d6[1]}),
        .D7({of_d7[4],of_d7[2]}),
        .D8({of_d8[7],of_d8[0]}),
        .D9(of_d9),
        .calib_wrdata_en(calib_wrdata_en),
        .\entry_cnt_reg[2]_0 (\entry_cnt_reg[2] ),
        .\entry_cnt_reg[3]_0 (\entry_cnt_reg[3] ),
        .\entry_cnt_reg[3]_1 (\entry_cnt_reg[3]_0 ),
        .\entry_cnt_reg[3]_2 (\entry_cnt_reg[3]_1 ),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),
        .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7] ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(out_fifo_n_3),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .phy_mc_data_full(phy_mc_data_full),
        .\write_buffer.wr_buf_out_data_reg[568] (\write_buffer.wr_buf_out_data_reg[568] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(D_pi_rst_dqs_find84_out),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }),
        .D1({\write_buffer.wr_buf_out_data_reg[455] [4:3],of_d1[5],\write_buffer.wr_buf_out_data_reg[455] [2:0],of_d1[1:0]}),
        .D2({\write_buffer.wr_buf_out_data_reg[454] [4:2],of_d2[4:3],\write_buffer.wr_buf_out_data_reg[454] [1],of_d2[1],\write_buffer.wr_buf_out_data_reg[454] [0]}),
        .D3({\write_buffer.wr_buf_out_data_reg[453] [5:3],of_d3[4],\write_buffer.wr_buf_out_data_reg[453] [2],of_d3[2],\write_buffer.wr_buf_out_data_reg[453] [1:0]}),
        .D4({of_d4[7],\write_buffer.wr_buf_out_data_reg[388] ,of_d4[0]}),
        .D5({\write_buffer.wr_buf_out_data_reg[451] [4:3],of_d5[5],\write_buffer.wr_buf_out_data_reg[451] [2:0],of_d5[1:0]}),
        .D6({\write_buffer.wr_buf_out_data_reg[450] [4:2],of_d6[4:3],\write_buffer.wr_buf_out_data_reg[450] [1],of_d6[1],\write_buffer.wr_buf_out_data_reg[450] [0]}),
        .D7({\write_buffer.wr_buf_out_data_reg[449] [5:3],of_d7[4],\write_buffer.wr_buf_out_data_reg[449] [2],of_d7[2],\write_buffer.wr_buf_out_data_reg[449] [1:0]}),
        .D8({of_d8[7],\write_buffer.wr_buf_out_data_reg[384] ,of_d8[0]}),
        .D9(of_d9),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(D_pi_counter_load_en90_out),
        .COUNTERLOADVAL(\calib_zero_inputs_reg[0] ),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(D_pi_counter_read_val),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(D_pi_fine_enable86_out),
        .FINEINC(D_pi_fine_inc88_out),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(\phaser_in_gen.phaser_in_n_6 ),
        .PHASEREFCLK(mc_read_idle_r_reg),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(D_pi_rst_dqs_find84_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(D_po_coarse_enable72_out),
        .COARSEINC(D_po_coarse_enable72_out),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(D_po_counter_read_val),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(D_po_fine_enable70_out),
        .FINEINC(D_po_fine_inc74_out),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_counter_read_val[0]_i_1 
       (.I0(D_pi_counter_read_val[0]),
        .I1(COUNTERREADVAL[0]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(A_rst_primitives_reg_5[0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(A_rst_primitives_reg_6[0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_counter_read_val[1]_i_1 
       (.I0(D_pi_counter_read_val[1]),
        .I1(COUNTERREADVAL[1]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(A_rst_primitives_reg_5[1]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(A_rst_primitives_reg_6[1]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_counter_read_val[2]_i_1 
       (.I0(D_pi_counter_read_val[2]),
        .I1(COUNTERREADVAL[2]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(A_rst_primitives_reg_5[2]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(A_rst_primitives_reg_6[2]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_counter_read_val[3]_i_1 
       (.I0(D_pi_counter_read_val[3]),
        .I1(COUNTERREADVAL[3]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(A_rst_primitives_reg_5[3]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(A_rst_primitives_reg_6[3]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_counter_read_val[4]_i_1 
       (.I0(D_pi_counter_read_val[4]),
        .I1(COUNTERREADVAL[4]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(A_rst_primitives_reg_5[4]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(A_rst_primitives_reg_6[4]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_counter_read_val[5]_i_1 
       (.I0(D_pi_counter_read_val[5]),
        .I1(COUNTERREADVAL[5]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(A_rst_primitives_reg_5[5]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(A_rst_primitives_reg_6[5]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    pi_phase_locked_all_inferred_i_2
       (.I0(\phaser_in_gen.phaser_in_n_6 ),
        .I1(A_rst_primitives_reg_0),
        .I2(A_rst_primitives_reg_1),
        .I3(A_rst_primitives_reg_2),
        .I4(A_rst_primitives_reg_3),
        .I5(A_rst_primitives_reg_4),
        .O(pi_phase_locked_all_r1_reg));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[0]_i_1__0 
       (.I0(D_po_counter_read_val[0]),
        .I1(A_rst_primitives_reg_7[0]),
        .I2(A_rst_primitives_reg_8[0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[0]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [0]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[1]_i_1__0 
       (.I0(D_po_counter_read_val[1]),
        .I1(A_rst_primitives_reg_7[1]),
        .I2(A_rst_primitives_reg_8[1]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[1]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [1]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[2]_i_1__0 
       (.I0(D_po_counter_read_val[2]),
        .I1(A_rst_primitives_reg_7[2]),
        .I2(A_rst_primitives_reg_8[2]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[2]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [2]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[3]_i_1__0 
       (.I0(D_po_counter_read_val[3]),
        .I1(A_rst_primitives_reg_7[3]),
        .I2(A_rst_primitives_reg_8[3]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[3]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [3]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[4]_i_1__0 
       (.I0(D_po_counter_read_val[4]),
        .I1(A_rst_primitives_reg_7[4]),
        .I2(A_rst_primitives_reg_8[4]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[4]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [4]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[5]_i_1__0 
       (.I0(D_po_counter_read_val[5]),
        .I1(A_rst_primitives_reg_7[5]),
        .I2(A_rst_primitives_reg_8[5]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[5]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [5]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[6]_i_1__0 
       (.I0(D_po_counter_read_val[6]),
        .I1(A_rst_primitives_reg_7[6]),
        .I2(A_rst_primitives_reg_8[6]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[6]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [6]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[7]_i_1__0 
       (.I0(D_po_counter_read_val[7]),
        .I1(A_rst_primitives_reg_7[7]),
        .I2(A_rst_primitives_reg_8[7]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[7]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [7]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[8]_i_1__0 
       (.I0(D_po_counter_read_val[8]),
        .I1(A_rst_primitives_reg_7[8]),
        .I2(A_rst_primitives_reg_8[8]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_9[8]),
        .I5(\calib_sel_reg[1] [0]),
        .O(\po_counter_read_val_reg[8] [8]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized3
   (out,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0]_0 ,
    pi_phase_locked_all_r1_reg,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[4] ,
    \pi_dqs_found_lanes_r1_reg[4]_0 ,
    p_98_in,
    p_97_in,
    p_102_in,
    p_101_in,
    p_106_in,
    p_105_in,
    p_110_in,
    p_109_in,
    p_114_in,
    p_113_in,
    p_118_in,
    p_117_in,
    p_122_in,
    p_121_in,
    p_126_in,
    p_125_in,
    \ddr3_dm[4] ,
    p_9_in,
    \wr_ptr_reg[1] ,
    \my_empty_reg[4]_rep__1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    Q,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ,
    \my_empty_reg[1] ,
    \entry_cnt_reg[4] ,
    ofs_rdy_r_reg,
    \not_strict_mode.app_rd_data_reg[487] ,
    wr_en,
    p_0_in1_in,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_reg[1]_2 ,
    DIC,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7] ,
    idelay_ld_rst_6,
    INBURSTPENDING,
    A_pi_counter_load_en161_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable157_out,
    A_pi_fine_inc159_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_rst_primitives_reg,
    A_pi_rst_dqs_find155_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    INRANKA,
    \pi_stg2_reg_l_reg[5] ,
    OUTBURSTPENDING,
    A_po_coarse_enable143_out,
    A_po_fine_enable141_out,
    A_po_fine_inc145_out,
    D0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    A_rst_primitives_reg_0,
    p_99_out,
    A_idelay_ce19_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_103_out,
    p_107_out,
    p_111_out,
    p_115_out,
    p_119_out,
    p_123_out,
    p_127_out,
    ofifo_rst0,
    phy_if_reset,
    phy_data_wr_en,
    \my_empty_reg[3] ,
    mem_out,
    \entry_cnt_reg[4]_0 ,
    \entry_cnt_reg[3] ,
    \entry_cnt_reg[4]_1 ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__0,
    mc_wrdata_en,
    \rd_ptr_reg_rep[3] );
  output [1:0]out;
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0]_0 ;
  output pi_phase_locked_all_r1_reg;
  output [5:0]COUNTERREADVAL;
  output [8:0]\po_counter_read_val_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[4] ;
  output \pi_dqs_found_lanes_r1_reg[4]_0 ;
  output p_98_in;
  output p_97_in;
  output p_102_in;
  output p_101_in;
  output p_106_in;
  output p_105_in;
  output p_110_in;
  output p_109_in;
  output p_114_in;
  output p_113_in;
  output p_118_in;
  output p_117_in;
  output p_122_in;
  output p_121_in;
  output p_126_in;
  output p_125_in;
  output \ddr3_dm[4] ;
  output p_9_in;
  output \wr_ptr_reg[1] ;
  output [1:0]\my_empty_reg[4]_rep__1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  output [65:0]Q;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  output \my_empty_reg[1] ;
  output [0:0]\entry_cnt_reg[4] ;
  output ofs_rdy_r_reg;
  output [63:0]\not_strict_mode.app_rd_data_reg[487] ;
  output wr_en;
  output p_0_in1_in;
  output \wr_ptr_reg[1]_0 ;
  output \wr_ptr_reg[1]_1 ;
  output \wr_ptr_reg[1]_2 ;
  output [1:0]DIC;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7] ;
  output idelay_ld_rst_6;
  input [0:0]INBURSTPENDING;
  input A_pi_counter_load_en161_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable157_out;
  input A_pi_fine_inc159_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_rst_primitives_reg;
  input A_pi_rst_dqs_find155_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [1:0]INRANKA;
  input [5:0]\pi_stg2_reg_l_reg[5] ;
  input [0:0]OUTBURSTPENDING;
  input A_po_coarse_enable143_out;
  input A_po_fine_enable141_out;
  input A_po_fine_inc145_out;
  input [7:0]D0;
  input [7:0]D1;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D9;
  input A_rst_primitives_reg_0;
  input p_99_out;
  input A_idelay_ce19_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_103_out;
  input p_107_out;
  input p_111_out;
  input p_115_out;
  input p_119_out;
  input p_123_out;
  input p_127_out;
  input ofifo_rst0;
  input phy_if_reset;
  input phy_data_wr_en;
  input \my_empty_reg[3] ;
  input [63:0]mem_out;
  input [0:0]\entry_cnt_reg[4]_0 ;
  input [1:0]\entry_cnt_reg[3] ;
  input \entry_cnt_reg[4]_1 ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__0;
  input mc_wrdata_en;
  input [7:0]\rd_ptr_reg_rep[3] ;

  wire A_idelay_ce19_out;
  wire A_pi_counter_load_en161_out;
  wire A_pi_dqs_out_of_range;
  wire A_pi_fine_enable157_out;
  wire A_pi_fine_inc159_out;
  wire A_pi_fine_overflow;
  wire A_pi_rst_dqs_find155_out;
  wire A_po_coarse_enable143_out;
  wire A_po_coarse_overflow;
  wire A_po_fine_enable141_out;
  wire A_po_fine_inc145_out;
  wire A_po_fine_overflow;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [7:0]D9;
  wire [1:0]DIC;
  wire [0:0]INBURSTPENDING;
  wire [1:0]INRANKA;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [65:0]Q;
  wire \calib_sel_reg[0] ;
  wire calib_wrdata_en;
  wire \ddr3_dm[4] ;
  wire ddr_byte_group_io_n_2;
  wire ddr_byte_group_io_n_3;
  wire ddr_byte_group_io_n_4;
  wire ddr_byte_group_io_n_5;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0]_0 ;
  wire [1:0]\entry_cnt_reg[3] ;
  wire [0:0]\entry_cnt_reg[4] ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire \entry_cnt_reg[4]_1 ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst_6;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire if_empty_;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire init_calib_complete_reg_rep__0;
  wire iserdes_clkdiv;
  wire mc_read_idle_r_reg;
  wire mc_wrdata_en;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[3] ;
  wire [1:0]\my_empty_reg[4]_rep__1 ;
  wire [3:0]\my_empty_reg[7] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[487] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [7:0]of_d8;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst0;
  wire ofs_rdy_r_reg;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire [1:0]out;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_0_in1_in;
  wire p_101_in;
  wire p_102_in;
  wire p_103_out;
  wire p_105_in;
  wire p_106_in;
  wire p_107_out;
  wire p_109_in;
  wire p_110_in;
  wire p_111_out;
  wire p_113_in;
  wire p_114_in;
  wire p_115_out;
  wire p_117_in;
  wire p_118_in;
  wire p_119_out;
  wire p_121_in;
  wire p_122_in;
  wire p_123_out;
  wire p_125_in;
  wire p_126_in;
  wire p_127_out;
  wire p_97_in;
  wire p_98_in;
  wire p_99_out;
  wire p_9_in;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[4] ;
  wire \pi_dqs_found_lanes_r1_reg[4]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire [5:0]\pi_stg2_reg_l_reg[5] ;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire sync_pulse;
  wire wr_en;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_5 ddr_byte_group_io
       (.A_idelay_ce19_out(A_idelay_ce19_out),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D0({ddr_byte_group_io_n_2,ddr_byte_group_io_n_3,ddr_byte_group_io_n_4,ddr_byte_group_io_n_5}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q9(of_q9),
        .\ddr3_dm[4] (\ddr3_dm[4] ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .iserdes_clkdiv(iserdes_clkdiv),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_101_in(p_101_in),
        .p_102_in(p_102_in),
        .p_103_out(p_103_out),
        .p_105_in(p_105_in),
        .p_106_in(p_106_in),
        .p_107_out(p_107_out),
        .p_109_in(p_109_in),
        .p_110_in(p_110_in),
        .p_111_out(p_111_out),
        .p_113_in(p_113_in),
        .p_114_in(p_114_in),
        .p_115_out(p_115_out),
        .p_117_in(p_117_in),
        .p_118_in(p_118_in),
        .p_119_out(p_119_out),
        .p_121_in(p_121_in),
        .p_122_in(p_122_in),
        .p_123_out(p_123_out),
        .p_125_in(p_125_in),
        .p_126_in(p_126_in),
        .p_127_out(p_127_out),
        .p_97_in(p_97_in),
        .p_98_in(p_98_in),
        .p_99_out(p_99_out),
        .p_9_in(p_9_in),
        .\pi_dqs_found_lanes_r1_reg[4] (\pi_dqs_found_lanes_r1_reg[4] ),
        .\pi_dqs_found_lanes_r1_reg[4]_0 (\pi_dqs_found_lanes_r1_reg[4]_0 ),
        .po_oserdes_rst(po_oserdes_rst));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(\wr_ptr_reg[1] ),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(Q[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(Q[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(Q[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(Q[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(Q[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(Q[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(Q[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(Q[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(Q[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(Q[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(Q[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(Q[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(Q[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(Q[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(Q[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(Q[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(Q[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(Q[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(Q[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(Q[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[2]),
        .Q(Q[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[3]),
        .Q(Q[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[4]),
        .Q(Q[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[5]),
        .Q(Q[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[6]),
        .Q(Q[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[7]),
        .Q(Q[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(Q[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(Q[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(Q[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(Q[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(Q[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(Q[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(Q[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(Q[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(Q[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(Q[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(Q[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(Q[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(Q[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(Q[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(Q[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(Q[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(Q[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(Q[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(Q[9]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_6 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.CLK(CLK),
        .DIC(DIC),
        .Q(Q[63:0]),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\wr_ptr_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (\gen_rd[4].rd_data_rise_wl_r_reg[4] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .ififo_rst(ififo_rst),
        .mem_out(mem_out),
        .\my_empty_reg[3] (\my_empty_reg[3] ),
        .\my_empty_reg[4]_rep__1_0 (\my_empty_reg[4]_rep__1 ),
        .\not_strict_mode.app_rd_data_reg[487] (\not_strict_mode.app_rd_data_reg[487] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_reg[1]_2 (\wr_ptr_reg[1]_2 ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(A_pi_rst_dqs_find155_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({ddr_byte_group_io_n_2,ddr_byte_group_io_n_3,ddr_byte_group_io_n_4,ddr_byte_group_io_n_5}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8({1'b0,1'b0,1'b0,1'b0}),
        .D9({1'b0,1'b0,1'b0,1'b0}),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized6 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D8(of_d8),
        .Q(\wr_ptr_timing_reg[3] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\entry_cnt_reg[3]_0 (\entry_cnt_reg[3] ),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .\entry_cnt_reg[4]_1 (\entry_cnt_reg[4]_0 ),
        .\entry_cnt_reg[4]_2 (\entry_cnt_reg[4]_1 ),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7] ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(out_fifo_n_3),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3] ),
        .wr_en(wr_en));
  FDRE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofifo_rst0),
        .Q(ofifo_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0(D0),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(of_d8),
        .D9(D9),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(INBURSTPENDING),
        .COUNTERLOADEN(A_pi_counter_load_en161_out),
        .COUNTERLOADVAL(\pi_stg2_reg_l_reg[5] ),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(A_pi_dqs_out_of_range),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(A_pi_fine_enable157_out),
        .FINEINC(A_pi_fine_inc159_out),
        .FINEOVERFLOW(A_pi_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(pi_phase_locked_all_r1_reg),
        .PHASEREFCLK(mc_read_idle_r_reg),
        .RANKSELPHY(INRANKA),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives_reg),
        .RSTDQSFIND(A_pi_rst_dqs_find155_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(A_po_coarse_enable143_out),
        .COARSEINC(A_po_coarse_enable143_out),
        .COARSEOVERFLOW(A_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(\po_counter_read_val_reg[8] ),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(A_po_fine_enable141_out),
        .FINEINC(A_po_fine_inc145_out),
        .FINEOVERFLOW(A_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives_reg),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized4
   (COUNTERREADVAL,
    B_of_ctl_full,
    \my_empty_reg[1] ,
    wr_en_10,
    Q,
    \wr_ptr_timing_reg[0] ,
    mem_dq_out,
    OUTBURSTPENDING,
    B_po_coarse_enable27_out,
    \gen_byte_sel_div2.calib_in_common_reg ,
    B_po_fine_enable24_out,
    B_po_fine_inc30_out,
    freq_refclk,
    mem_refclk,
    A_rst_primitives_reg,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    ofifo_rst,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    phy_cmd_wr_en,
    calib_cmd_wren,
    init_calib_complete_reg_rep__1,
    \rd_ptr_reg_rep[3] ,
    init_calib_complete_reg_rep__0);
  output [8:0]COUNTERREADVAL;
  output B_of_ctl_full;
  output \my_empty_reg[1] ;
  output wr_en_10;
  output [3:0]Q;
  output [3:0]\wr_ptr_timing_reg[0] ;
  output [4:0]mem_dq_out;
  input [0:0]OUTBURSTPENDING;
  input B_po_coarse_enable27_out;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input B_po_fine_enable24_out;
  input B_po_fine_inc30_out;
  input freq_refclk;
  input mem_refclk;
  input A_rst_primitives_reg;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input ofifo_rst;
  input [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  input [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  input [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  input [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  input phy_cmd_wr_en;
  input calib_cmd_wren;
  input init_calib_complete_reg_rep__1;
  input [24:0]\rd_ptr_reg_rep[3] ;
  input init_calib_complete_reg_rep__0;

  wire A_rst_primitives_reg;
  wire B_of_ctl_a_full;
  wire B_of_ctl_full;
  wire B_po_coarse_enable27_out;
  wire B_po_coarse_overflow;
  wire B_po_fine_enable24_out;
  wire B_po_fine_inc30_out;
  wire B_po_fine_overflow;
  wire CLK;
  wire [8:0]COUNTERREADVAL;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [3:0]Q;
  wire calib_cmd_wren;
  wire [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__1;
  wire [4:0]mem_dq_out;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [5:4]of_d3;
  wire [7:4]of_d4;
  wire [7:3]of_d5;
  wire [7:0]of_d6;
  wire [3:0]of_d7;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire phy_cmd_wr_en;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [24:0]\rd_ptr_reg_rep[3] ;
  wire sync_pulse;
  wire wr_en_10;
  wire [3:0]\wr_ptr_timing_reg[0] ;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized3 ddr_byte_group_io
       (.mem_dq_out(mem_dq_out),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q6[7:4],of_q5,of_q3,of_q1}),
        .po_oserdes_rst(po_oserdes_rst));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized7 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 }),
        .D3(of_d3),
        .D4({of_d4,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .D5({of_d5[7],of_d5[3]}),
        .D6({of_d6[7],of_d6[3:0]}),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,of_d7}),
        .Q(Q),
        .calib_cmd_wren(calib_cmd_wren),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(B_of_ctl_full),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3] ),
        .wr_en_10(wr_en_10),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(B_of_ctl_a_full),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 }),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\cmd_pipe_plus.mc_odt_reg[0] }),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,of_d3,\cmd_pipe_plus.mc_cke_reg[3] }),
        .D4({of_d4,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 }),
        .D5({of_d5[7],\cmd_pipe_plus.mc_we_n_reg[2] [5:3],of_d5[3],\cmd_pipe_plus.mc_we_n_reg[2] [2:0]}),
        .D6({of_d6[7],\cmd_pipe_plus.mc_cas_n_reg[2] ,of_d6[3:0]}),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,of_d7}),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 }),
        .EMPTY(out_fifo_n_2),
        .FULL(B_of_ctl_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(B_po_coarse_enable27_out),
        .COARSEINC(B_po_coarse_enable27_out),
        .COARSEOVERFLOW(B_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\gen_byte_sel_div2.calib_in_common_reg ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(B_po_fine_enable24_out),
        .FINEINC(B_po_fine_inc30_out),
        .FINEOVERFLOW(B_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives_reg),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized5
   (COUNTERREADVAL,
    C_of_ctl_full,
    \my_empty_reg[1] ,
    wr_en_11,
    Q,
    \wr_ptr_timing_reg[0] ,
    \ddr3_addr[3] ,
    OUTBURSTPENDING,
    C_po_coarse_enable66_out,
    \gen_byte_sel_div2.calib_in_common_reg ,
    C_po_fine_enable63_out,
    C_po_fine_inc69_out,
    freq_refclk,
    mem_refclk,
    A_rst_primitives_reg,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    ofifo_rst,
    \cmd_pipe_plus.mc_ras_n_reg[2] ,
    init_calib_complete_reg_rep__3,
    init_calib_complete_reg_rep__2,
    init_calib_complete_reg_rep__2_0,
    init_calib_complete_reg_rep__2_1,
    init_calib_complete_reg_rep__2_2,
    init_calib_complete_reg_rep__2_3,
    init_calib_complete_reg_rep__2_4,
    D8,
    init_calib_complete_reg_rep__2_5,
    phy_cmd_wr_en,
    init_calib_complete_reg_rep__2_6,
    calib_cmd_wren,
    \rd_ptr_reg_rep[3] ,
    init_calib_complete_reg_rep__0);
  output [8:0]COUNTERREADVAL;
  output C_of_ctl_full;
  output \my_empty_reg[1] ;
  output wr_en_11;
  output [3:0]Q;
  output [3:0]\wr_ptr_timing_reg[0] ;
  output [11:0]\ddr3_addr[3] ;
  input [0:0]OUTBURSTPENDING;
  input C_po_coarse_enable66_out;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input C_po_fine_enable63_out;
  input C_po_fine_inc69_out;
  input freq_refclk;
  input mem_refclk;
  input A_rst_primitives_reg;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input ofifo_rst;
  input [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  input [3:0]init_calib_complete_reg_rep__3;
  input [3:0]init_calib_complete_reg_rep__2;
  input [3:0]init_calib_complete_reg_rep__2_0;
  input [3:0]init_calib_complete_reg_rep__2_1;
  input [7:0]init_calib_complete_reg_rep__2_2;
  input [7:0]init_calib_complete_reg_rep__2_3;
  input [3:0]init_calib_complete_reg_rep__2_4;
  input [3:0]D8;
  input [3:0]init_calib_complete_reg_rep__2_5;
  input phy_cmd_wr_en;
  input init_calib_complete_reg_rep__2_6;
  input calib_cmd_wren;
  input [32:0]\rd_ptr_reg_rep[3] ;
  input init_calib_complete_reg_rep__0;

  wire A_rst_primitives_reg;
  wire CLK;
  wire [8:0]COUNTERREADVAL;
  wire C_of_ctl_a_full;
  wire C_of_ctl_full;
  wire C_po_coarse_enable66_out;
  wire C_po_coarse_overflow;
  wire C_po_fine_enable63_out;
  wire C_po_fine_inc69_out;
  wire C_po_fine_overflow;
  wire [3:0]D8;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [3:0]Q;
  wire calib_cmd_wren;
  wire [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  wire [11:0]\ddr3_addr[3] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire init_calib_complete_reg_rep__0;
  wire [3:0]init_calib_complete_reg_rep__2;
  wire [3:0]init_calib_complete_reg_rep__2_0;
  wire [3:0]init_calib_complete_reg_rep__2_1;
  wire [7:0]init_calib_complete_reg_rep__2_2;
  wire [7:0]init_calib_complete_reg_rep__2_3;
  wire [3:0]init_calib_complete_reg_rep__2_4;
  wire [3:0]init_calib_complete_reg_rep__2_5;
  wire init_calib_complete_reg_rep__2_6;
  wire [3:0]init_calib_complete_reg_rep__3;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [7:4]of_d1;
  wire [7:4]of_d2;
  wire [7:4]of_d3;
  wire [7:4]of_d4;
  wire [7:4]of_d7;
  wire [7:4]of_d8;
  wire [7:4]of_d9;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire phy_cmd_wr_en;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [32:0]\rd_ptr_reg_rep[3] ;
  wire sync_pulse;
  wire wr_en_11;
  wire [3:0]\wr_ptr_timing_reg[0] ;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized4 ddr_byte_group_io
       (.\ddr3_addr[3] (\ddr3_addr[3] ),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1,of_q0}),
        .po_oserdes_rst(po_oserdes_rst));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized8 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 }),
        .D1(of_d1),
        .D2(of_d2),
        .D3(of_d3),
        .D4(of_d4),
        .D7(of_d7),
        .D8(of_d8),
        .D9(of_d9),
        .Q(Q),
        .calib_cmd_wren(calib_cmd_wren),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2_6),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(C_of_ctl_full),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3] ),
        .wr_en_11(wr_en_11),
        .\wr_ptr_timing_reg[0]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(C_of_ctl_a_full),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\cmd_pipe_plus.mc_ras_n_reg[2] }),
        .D1({of_d1,init_calib_complete_reg_rep__3}),
        .D2({of_d2,init_calib_complete_reg_rep__2}),
        .D3({of_d3,init_calib_complete_reg_rep__2_0}),
        .D4({of_d4,init_calib_complete_reg_rep__2_1}),
        .D5(init_calib_complete_reg_rep__2_2),
        .D6(init_calib_complete_reg_rep__2_3),
        .D7({of_d7,init_calib_complete_reg_rep__2_4}),
        .D8({of_d8,D8}),
        .D9({of_d9,init_calib_complete_reg_rep__2_5}),
        .EMPTY(out_fifo_n_2),
        .FULL(C_of_ctl_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(C_po_coarse_enable66_out),
        .COARSEINC(C_po_coarse_enable66_out),
        .COARSEOVERFLOW(C_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\gen_byte_sel_div2.calib_in_common_reg ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(C_po_fine_enable63_out),
        .FINEINC(C_po_fine_inc69_out),
        .FINEOVERFLOW(C_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives_reg),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized6
   (ofifo_rst,
    ddr_ck_out,
    \my_empty_reg[1] ,
    of_ctl_full_v,
    \ddr3_addr[13] ,
    \my_empty_reg[6] ,
    D,
    A_rst_primitives_reg,
    CLK,
    OUTBURSTPENDING,
    D_po_coarse_enable105_out,
    \gen_byte_sel_div2.calib_in_common_reg ,
    D_po_fine_enable102_out,
    D_po_fine_inc108_out,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    PCENABLECALIB,
    init_calib_complete_reg_rep,
    init_calib_complete_reg_rep_0,
    init_calib_complete_reg_rep_1,
    init_calib_complete_reg_rep_2,
    init_calib_complete_reg_rep_3,
    calib_cmd_wren,
    init_calib_complete_reg_rep__14,
    C_of_ctl_full,
    B_of_ctl_full,
    phy_cmd_wr_en,
    \cmd_pipe_plus.mc_address_reg[41] ,
    mc_cas_n,
    init_calib_complete_reg_rep__0,
    phy_dout,
    COUNTERREADVAL,
    A_rst_primitives_reg_0,
    \calib_sel_reg[1] ,
    A_rst_primitives_reg_1);
  output ofifo_rst;
  output [1:0]ddr_ck_out;
  output \my_empty_reg[1] ;
  output [0:0]of_ctl_full_v;
  output [5:0]\ddr3_addr[13] ;
  output [15:0]\my_empty_reg[6] ;
  output [8:0]D;
  input A_rst_primitives_reg;
  input CLK;
  input [0:0]OUTBURSTPENDING;
  input D_po_coarse_enable105_out;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input D_po_fine_enable102_out;
  input D_po_fine_inc108_out;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [3:0]init_calib_complete_reg_rep;
  input [3:0]init_calib_complete_reg_rep_0;
  input [3:0]init_calib_complete_reg_rep_1;
  input [3:0]init_calib_complete_reg_rep_2;
  input init_calib_complete_reg_rep_3;
  input calib_cmd_wren;
  input init_calib_complete_reg_rep__14;
  input C_of_ctl_full;
  input B_of_ctl_full;
  input phy_cmd_wr_en;
  input [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [0:0]mc_cas_n;
  input init_calib_complete_reg_rep__0;
  input [21:0]phy_dout;
  input [8:0]COUNTERREADVAL;
  input [8:0]A_rst_primitives_reg_0;
  input [1:0]\calib_sel_reg[1] ;
  input [8:0]A_rst_primitives_reg_1;

  wire A_rst_primitives_reg;
  wire [8:0]A_rst_primitives_reg_0;
  wire [8:0]A_rst_primitives_reg_1;
  wire B_of_ctl_full;
  wire CLK;
  wire [8:0]COUNTERREADVAL;
  wire C_of_ctl_full;
  wire [8:0]D;
  wire D_of_ctl_full;
  wire D_po_coarse_enable105_out;
  wire [8:0]D_po_counter_read_val;
  wire D_po_fine_enable102_out;
  wire D_po_fine_inc108_out;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire calib_cmd_wren;
  wire [1:0]\calib_sel_reg[1] ;
  wire [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [5:0]\ddr3_addr[13] ;
  wire [1:0]ddr_ck_out;
  wire [0:0]ddr_ck_out_q;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire [3:0]init_calib_complete_reg_rep;
  wire [3:0]init_calib_complete_reg_rep_0;
  wire [3:0]init_calib_complete_reg_rep_1;
  wire [3:0]init_calib_complete_reg_rep_2;
  wire init_calib_complete_reg_rep_3;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__14;
  wire [0:0]mc_cas_n;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [15:0]\my_empty_reg[6] ;
  wire [0:0]of_ctl_full_v;
  wire [3:0]of_d4;
  wire [7:4]of_d5;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_cmd_wr_en;
  wire [21:0]phy_dout;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire sync_pulse;
  wire \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized5 ddr_byte_group_io
       (.\ddr3_addr[13] (\ddr3_addr[13] ),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q5,of_q4,of_q3,of_q2,of_q1}),
        .po_oserdes_rst(po_oserdes_rst));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck 
       (.C(oserdes_clk),
        .CE(1'b1),
        .D1(1'b0),
        .D2(1'b1),
        .Q(ddr_ck_out_q),
        .R(1'b0),
        .S(\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  (* XILINX_LEGACY_PRIM = "OBUFDS" *) 
  OBUFDS #(
    .IOSTANDARD("DEFAULT")) 
    \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf 
       (.I(ddr_ck_out_q),
        .O(ddr_ck_out[0]),
        .OB(ddr_ck_out[1]));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized9 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 }),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 }),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 }),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d4}),
        .D5(of_d5),
        .D_of_ctl_full(D_of_ctl_full),
        .SR(ofifo_rst),
        .calib_cmd_wren(calib_cmd_wren),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep_3),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__14(init_calib_complete_reg_rep__14),
        .mc_cas_n(mc_cas_n),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[6]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ),
        .\my_empty_reg[6]_1 (\my_empty_reg[6] ),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_dout(phy_dout));
  FDRE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(A_rst_primitives_reg),
        .Q(ofifo_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,init_calib_complete_reg_rep}),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,init_calib_complete_reg_rep_0}),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,init_calib_complete_reg_rep_1}),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d4}),
        .D5({of_d5,init_calib_complete_reg_rep_2}),
        .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 }),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 }),
        .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .EMPTY(out_fifo_n_2),
        .FULL(D_of_ctl_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(D_po_coarse_enable105_out),
        .COARSEINC(D_po_coarse_enable105_out),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\gen_byte_sel_div2.calib_in_common_reg ),
        .COUNTERREADVAL(D_po_counter_read_val),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(D_po_fine_enable102_out),
        .FINEINC(D_po_fine_inc108_out),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives_reg),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
  LUT3 #(
    .INIT(8'hFE)) 
    phy_mc_cmd_full_r_i_1
       (.I0(D_of_ctl_full),
        .I1(C_of_ctl_full),
        .I2(B_of_ctl_full),
        .O(of_ctl_full_v));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[0]_i_1 
       (.I0(D_po_counter_read_val[0]),
        .I1(COUNTERREADVAL[0]),
        .I2(A_rst_primitives_reg_0[0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[0]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[1]_i_1 
       (.I0(D_po_counter_read_val[1]),
        .I1(COUNTERREADVAL[1]),
        .I2(A_rst_primitives_reg_0[1]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[1]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[2]_i_1 
       (.I0(D_po_counter_read_val[2]),
        .I1(COUNTERREADVAL[2]),
        .I2(A_rst_primitives_reg_0[2]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[2]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[3]_i_1 
       (.I0(D_po_counter_read_val[3]),
        .I1(COUNTERREADVAL[3]),
        .I2(A_rst_primitives_reg_0[3]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[3]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[4]_i_1 
       (.I0(D_po_counter_read_val[4]),
        .I1(COUNTERREADVAL[4]),
        .I2(A_rst_primitives_reg_0[4]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[4]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[5]_i_1 
       (.I0(D_po_counter_read_val[5]),
        .I1(COUNTERREADVAL[5]),
        .I2(A_rst_primitives_reg_0[5]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[5]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[6]_i_1 
       (.I0(D_po_counter_read_val[6]),
        .I1(COUNTERREADVAL[6]),
        .I2(A_rst_primitives_reg_0[6]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[6]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[6]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[7]_i_1 
       (.I0(D_po_counter_read_val[7]),
        .I1(COUNTERREADVAL[7]),
        .I2(A_rst_primitives_reg_0[7]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[7]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[7]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \po_counter_read_val[8]_i_1 
       (.I0(D_po_counter_read_val[8]),
        .I1(COUNTERREADVAL[8]),
        .I2(A_rst_primitives_reg_0[8]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(A_rst_primitives_reg_1[8]),
        .I5(\calib_sel_reg[1] [0]),
        .O(D[8]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized7
   (\rd_ptr_timing_reg[1] ,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    pi_phase_locked_all_r1_reg,
    rclk_,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8] ,
    \my_empty_reg[7] ,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    p_34_in,
    p_33_in,
    p_38_in,
    p_37_in,
    p_42_in,
    p_41_in,
    p_46_in,
    p_45_in,
    \ddr3_dm[6] ,
    p_3_in,
    p_50_in,
    p_49_in,
    p_54_in,
    p_53_in,
    p_58_in,
    p_57_in,
    p_62_in,
    p_61_in,
    \my_empty_reg[0] ,
    \my_empty_reg[7]_0 ,
    idelay_ld_rst_4,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    Q,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ,
    \my_empty_reg[1] ,
    \not_strict_mode.app_rd_data_reg[503] ,
    wr_en_13,
    \entry_cnt_reg[4] ,
    ofs_rdy_r_reg,
    \not_strict_mode.app_rd_data_reg[496] ,
    \my_empty_reg[3] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[1]_0 ,
    \read_fifo.tail_r_reg[1] ,
    DIA,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7]_1 ,
    phaser_ctl_bus,
    B_pi_counter_load_en35_out,
    \calib_sel_reg[0] ,
    B_pi_fine_enable31_out,
    B_pi_fine_inc33_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_rst_primitives,
    B_pi_rst_dqs_find29_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    \calib_zero_inputs_reg[2] ,
    B_po_coarse_enable17_out,
    B_po_fine_enable15_out,
    B_po_fine_inc19_out,
    \write_buffer.wr_buf_out_data_reg[503] ,
    \write_buffer.wr_buf_out_data_reg[502] ,
    \write_buffer.wr_buf_out_data_reg[501] ,
    init_calib_complete_reg_rep__12,
    init_calib_complete_reg_rep__11,
    \write_buffer.wr_buf_out_data_reg[499] ,
    \write_buffer.wr_buf_out_data_reg[498] ,
    \write_buffer.wr_buf_out_data_reg[497] ,
    init_calib_complete_reg_rep__11_0,
    A_rst_primitives_reg,
    p_35_out,
    B_idelay_ce6_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_39_out,
    p_43_out,
    p_47_out,
    p_51_out,
    p_55_out,
    p_59_out,
    p_63_out,
    phy_if_reset,
    phy_data_wr_en,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    rst_r4,
    ififo_rd_en_in,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__9,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    init_calib_complete_reg_rep__11_1,
    \rd_ptr_reg_rep[3] ,
    if_empty_r,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[3]_1 ,
    if_empty_r_0);
  output [1:0]\rd_ptr_timing_reg[1] ;
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output pi_phase_locked_all_r1_reg;
  output rclk_;
  output [5:0]COUNTERREADVAL;
  output [8:0]\po_counter_read_val_reg[8] ;
  output \my_empty_reg[7] ;
  output \pi_dqs_found_lanes_r1_reg[9] ;
  output \pi_dqs_found_lanes_r1_reg[9]_0 ;
  output p_34_in;
  output p_33_in;
  output p_38_in;
  output p_37_in;
  output p_42_in;
  output p_41_in;
  output p_46_in;
  output p_45_in;
  output \ddr3_dm[6] ;
  output p_3_in;
  output p_50_in;
  output p_49_in;
  output p_54_in;
  output p_53_in;
  output p_58_in;
  output p_57_in;
  output p_62_in;
  output p_61_in;
  output \my_empty_reg[0] ;
  output \my_empty_reg[7]_0 ;
  output idelay_ld_rst_4;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  output [67:0]Q;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  output \my_empty_reg[1] ;
  output [63:0]\not_strict_mode.app_rd_data_reg[503] ;
  output wr_en_13;
  output [0:0]\entry_cnt_reg[4] ;
  output ofs_rdy_r_reg;
  output \not_strict_mode.app_rd_data_reg[496] ;
  output [0:0]\my_empty_reg[3] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[1]_0 ;
  output \read_fifo.tail_r_reg[1] ;
  output [1:0]DIA;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7]_1 ;
  input [3:0]phaser_ctl_bus;
  input B_pi_counter_load_en35_out;
  input \calib_sel_reg[0] ;
  input B_pi_fine_enable31_out;
  input B_pi_fine_inc33_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_rst_primitives;
  input B_pi_rst_dqs_find29_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [5:0]\calib_zero_inputs_reg[2] ;
  input B_po_coarse_enable17_out;
  input B_po_fine_enable15_out;
  input B_po_fine_inc19_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  input [7:0]init_calib_complete_reg_rep__12;
  input [7:0]init_calib_complete_reg_rep__11;
  input [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  input [7:0]init_calib_complete_reg_rep__11_0;
  input A_rst_primitives_reg;
  input p_35_out;
  input B_idelay_ce6_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_39_out;
  input p_43_out;
  input p_47_out;
  input p_51_out;
  input p_55_out;
  input p_59_out;
  input p_63_out;
  input phy_if_reset;
  input phy_data_wr_en;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  input rst_r4;
  input ififo_rd_en_in;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__9;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_wrdata_en_reg ;
  input init_calib_complete_reg_rep__11_1;
  input [7:0]\rd_ptr_reg_rep[3] ;
  input [0:0]if_empty_r;
  input [1:0]\my_empty_reg[3]_0 ;
  input [0:0]\my_empty_reg[3]_1 ;
  input [0:0]if_empty_r_0;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire B_idelay_ce6_out;
  wire B_if_a_empty;
  wire B_of_data_a_full;
  wire B_pi_counter_load_en35_out;
  wire B_pi_dqs_out_of_range;
  wire B_pi_fine_enable31_out;
  wire B_pi_fine_inc33_out;
  wire B_pi_fine_overflow;
  wire B_pi_rst_dqs_find29_out;
  wire B_po_coarse_enable17_out;
  wire B_po_coarse_overflow;
  wire B_po_fine_enable15_out;
  wire B_po_fine_inc19_out;
  wire B_po_fine_overflow;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire [1:0]DIA;
  wire [1:0]PCENABLECALIB;
  wire [67:0]Q;
  wire \calib_sel_reg[0] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[2] ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire \ddr3_dm[6] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire [0:0]\entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst_4;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rd_en_in;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire [7:0]init_calib_complete_reg_rep__11;
  wire [7:0]init_calib_complete_reg_rep__11_0;
  wire init_calib_complete_reg_rep__11_1;
  wire [7:0]init_calib_complete_reg_rep__12;
  wire init_calib_complete_reg_rep__9;
  wire iserdes_clkdiv;
  wire mc_read_idle_r_reg;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[1] ;
  wire [0:0]\my_empty_reg[3] ;
  wire [1:0]\my_empty_reg[3]_0 ;
  wire [0:0]\my_empty_reg[3]_1 ;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire \not_strict_mode.app_rd_data_reg[496] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[503] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofs_rdy_r_reg;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_33_in;
  wire p_34_in;
  wire p_35_out;
  wire p_37_in;
  wire p_38_in;
  wire p_39_out;
  wire p_3_in;
  wire p_41_in;
  wire p_42_in;
  wire p_43_out;
  wire p_45_in;
  wire p_46_in;
  wire p_47_out;
  wire p_49_in;
  wire p_50_in;
  wire p_51_out;
  wire p_53_in;
  wire p_54_in;
  wire p_55_out;
  wire p_57_in;
  wire p_58_in;
  wire p_59_out;
  wire p_61_in;
  wire p_62_in;
  wire p_63_out;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire rclk_;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire rst_r4;
  wire sync_pulse;
  wire wr_en_13;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized6 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .B_idelay_ce6_out(B_idelay_ce6_out),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .\ddr3_dm[6] (\ddr3_dm[6] ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .iserdes_clkdiv(iserdes_clkdiv),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_33_in(p_33_in),
        .p_34_in(p_34_in),
        .p_35_out(p_35_out),
        .p_37_in(p_37_in),
        .p_38_in(p_38_in),
        .p_39_out(p_39_out),
        .p_3_in(p_3_in),
        .p_41_in(p_41_in),
        .p_42_in(p_42_in),
        .p_43_out(p_43_out),
        .p_45_in(p_45_in),
        .p_46_in(p_46_in),
        .p_47_out(p_47_out),
        .p_49_in(p_49_in),
        .p_50_in(p_50_in),
        .p_51_out(p_51_out),
        .p_53_in(p_53_in),
        .p_54_in(p_54_in),
        .p_55_out(p_55_out),
        .p_57_in(p_57_in),
        .p_58_in(p_58_in),
        .p_59_out(p_59_out),
        .p_61_in(p_61_in),
        .p_62_in(p_62_in),
        .p_63_out(p_63_out),
        .\pi_dqs_found_lanes_r1_reg[9] (\pi_dqs_found_lanes_r1_reg[9] ),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(\my_empty_reg[0] ),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(Q[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(Q[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(Q[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(Q[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(Q[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(Q[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(Q[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(Q[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(Q[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(Q[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(Q[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(Q[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(Q[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(Q[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(Q[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(Q[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(Q[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(Q[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(Q[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(Q[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(Q[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(Q[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(Q[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(Q[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(Q[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(Q[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(Q[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(Q[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(Q[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(Q[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(Q[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(Q[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[2]),
        .Q(Q[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[3]),
        .Q(Q[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[4]),
        .Q(Q[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[5]),
        .Q(Q[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[6]),
        .Q(Q[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[7]),
        .Q(Q[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[0]),
        .Q(Q[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[1]),
        .Q(Q[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[2]),
        .Q(Q[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[3]),
        .Q(Q[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[4]),
        .Q(Q[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[5]),
        .Q(Q[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[6]),
        .Q(Q[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q9[7]),
        .Q(Q[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(Q[3]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_3 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.CLK(CLK),
        .DIA(DIA),
        .Q({Q[67:36],Q[33:2]}),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\my_empty_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (\gen_rd[6].rd_data_rise_wl_r_reg[6] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_0),
        .ififo_rd_en_in(ififo_rd_en_in),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\my_empty_reg[3]_1 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[3]_2 (\my_empty_reg[3]_1 ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496] ),
        .\not_strict_mode.app_rd_data_reg[503] (\not_strict_mode.app_rd_data_reg[503] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_0 ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(B_pi_rst_dqs_find29_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(B_if_a_empty),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],1'b0,1'b0,1'b0,1'b0}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized10 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 }),
        .Q(\wr_ptr_timing_reg[3] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\cmd_pipe_plus.mc_wrdata_en_reg (\cmd_pipe_plus.mc_wrdata_en_reg ),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11_1),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(\my_empty_reg[7] ),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3] ),
        .wr_en_13(wr_en_13));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(B_pi_rst_dqs_find29_out),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(B_of_data_a_full),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 }),
        .D1(\write_buffer.wr_buf_out_data_reg[503] ),
        .D2(\write_buffer.wr_buf_out_data_reg[502] ),
        .D3(\write_buffer.wr_buf_out_data_reg[501] ),
        .D4(init_calib_complete_reg_rep__12),
        .D5(init_calib_complete_reg_rep__11),
        .D6(\write_buffer.wr_buf_out_data_reg[499] ),
        .D7(\write_buffer.wr_buf_out_data_reg[498] ),
        .D8(\write_buffer.wr_buf_out_data_reg[497] ),
        .D9(init_calib_complete_reg_rep__11_0),
        .EMPTY(out_fifo_n_2),
        .FULL(\my_empty_reg[7] ),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(B_pi_counter_load_en35_out),
        .COUNTERLOADVAL(\calib_zero_inputs_reg[2] ),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(B_pi_dqs_out_of_range),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(B_pi_fine_enable31_out),
        .FINEINC(B_pi_fine_inc33_out),
        .FINEOVERFLOW(B_pi_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(pi_phase_locked_all_r1_reg),
        .PHASEREFCLK(mc_read_idle_r_reg),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(rclk_),
        .RST(A_rst_primitives),
        .RSTDQSFIND(B_pi_rst_dqs_find29_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(B_po_coarse_enable17_out),
        .COARSEINC(B_po_coarse_enable17_out),
        .COARSEOVERFLOW(B_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[0] ),
        .COUNTERREADVAL(\po_counter_read_val_reg[8] ),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(B_po_fine_enable15_out),
        .FINEINC(B_po_fine_inc19_out),
        .FINEOVERFLOW(B_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_byte_lane" *) 
module mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized8
   (\rd_ptr_timing_reg[1] ,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    pi_phase_locked_all_r1_reg,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8] ,
    \my_empty_reg[7] ,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    p_66_in,
    p_65_in,
    p_70_in,
    p_69_in,
    p_74_in,
    p_73_in,
    p_78_in,
    p_77_in,
    p_82_in,
    p_81_in,
    p_86_in,
    p_85_in,
    p_90_in,
    p_89_in,
    p_94_in,
    p_93_in,
    p_7_in,
    \ddr3_dm[5] ,
    if_empty_r,
    \my_empty_reg[7]_0 ,
    idelay_ld_rst_5,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    Q,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ,
    \my_empty_reg[1] ,
    \my_empty_reg[3] ,
    \not_strict_mode.app_rd_data_reg[495] ,
    wr_en_14,
    ofs_rdy_r_reg,
    \not_strict_mode.app_rd_data_reg[232] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7]_1 ,
    phaser_ctl_bus,
    C_pi_counter_load_en61_out,
    \calib_sel_reg[1] ,
    C_pi_fine_enable57_out,
    C_pi_fine_inc59_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_rst_primitives,
    C_pi_rst_dqs_find55_out,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    \calib_zero_inputs_reg[2] ,
    C_po_coarse_enable43_out,
    C_po_fine_enable41_out,
    C_po_fine_inc45_out,
    \write_buffer.wr_buf_out_data_reg[495] ,
    \write_buffer.wr_buf_out_data_reg[494] ,
    \write_buffer.wr_buf_out_data_reg[493] ,
    init_calib_complete_reg_rep__13,
    \write_buffer.wr_buf_out_data_reg[491] ,
    \write_buffer.wr_buf_out_data_reg[490] ,
    \write_buffer.wr_buf_out_data_reg[489] ,
    init_calib_complete_reg_rep__12,
    init_calib_complete_reg_rep__12_0,
    A_rst_primitives_reg,
    p_67_out,
    C_idelay_ce2_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_71_out,
    p_75_out,
    p_79_out,
    p_83_out,
    p_87_out,
    p_91_out,
    p_95_out,
    phy_if_reset,
    phy_data_wr_en,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    rst_r4,
    ififo_rd_en_in,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__9,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    init_calib_complete_reg_rep__12_1,
    \rd_ptr_reg_rep[3] );
  output [1:0]\rd_ptr_timing_reg[1] ;
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output pi_phase_locked_all_r1_reg;
  output [5:0]COUNTERREADVAL;
  output [8:0]\po_counter_read_val_reg[8] ;
  output \my_empty_reg[7] ;
  output \pi_dqs_found_lanes_r1_reg[10] ;
  output \pi_dqs_found_lanes_r1_reg[10]_0 ;
  output p_66_in;
  output p_65_in;
  output p_70_in;
  output p_69_in;
  output p_74_in;
  output p_73_in;
  output p_78_in;
  output p_77_in;
  output p_82_in;
  output p_81_in;
  output p_86_in;
  output p_85_in;
  output p_90_in;
  output p_89_in;
  output p_94_in;
  output p_93_in;
  output p_7_in;
  output \ddr3_dm[5] ;
  output [0:0]if_empty_r;
  output \my_empty_reg[7]_0 ;
  output idelay_ld_rst_5;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  output [65:0]Q;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  output \my_empty_reg[1] ;
  output [1:0]\my_empty_reg[3] ;
  output [63:0]\not_strict_mode.app_rd_data_reg[495] ;
  output wr_en_14;
  output ofs_rdy_r_reg;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7]_1 ;
  input [3:0]phaser_ctl_bus;
  input C_pi_counter_load_en61_out;
  input \calib_sel_reg[1] ;
  input C_pi_fine_enable57_out;
  input C_pi_fine_inc59_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_rst_primitives;
  input C_pi_rst_dqs_find55_out;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input [5:0]\calib_zero_inputs_reg[2] ;
  input C_po_coarse_enable43_out;
  input C_po_fine_enable41_out;
  input C_po_fine_inc45_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  input [7:0]init_calib_complete_reg_rep__13;
  input [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  input [7:0]init_calib_complete_reg_rep__12;
  input [7:0]init_calib_complete_reg_rep__12_0;
  input A_rst_primitives_reg;
  input p_67_out;
  input C_idelay_ce2_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_71_out;
  input p_75_out;
  input p_79_out;
  input p_83_out;
  input p_87_out;
  input p_91_out;
  input p_95_out;
  input phy_if_reset;
  input phy_data_wr_en;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  input rst_r4;
  input ififo_rd_en_in;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__9;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_wrdata_en_reg ;
  input init_calib_complete_reg_rep__12_1;
  input [7:0]\rd_ptr_reg_rep[3] ;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire C_idelay_ce2_out;
  wire C_if_a_empty;
  wire C_of_data_a_full;
  wire C_pi_counter_load_en61_out;
  wire C_pi_dqs_out_of_range;
  wire C_pi_fine_enable57_out;
  wire C_pi_fine_inc59_out;
  wire C_pi_fine_overflow;
  wire C_pi_rst_dqs_find55_out;
  wire C_po_coarse_enable43_out;
  wire C_po_coarse_overflow;
  wire C_po_fine_enable41_out;
  wire C_po_fine_inc45_out;
  wire C_po_fine_overflow;
  wire [1:0]PCENABLECALIB;
  wire [65:0]Q;
  wire \calib_sel_reg[1] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[2] ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire \ddr3_dm[5] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst_5;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [7:0]if_q0;
  wire [7:0]if_q1;
  wire [7:0]if_q2;
  wire [7:0]if_q3;
  wire [7:0]if_q4;
  wire [7:0]if_q5;
  wire [7:0]if_q6;
  wire [7:0]if_q7;
  wire [7:0]if_q8;
  wire [7:0]if_q9;
  wire ififo_rd_en_in;
  wire ififo_rst;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire [7:0]init_calib_complete_reg_rep__12;
  wire [7:0]init_calib_complete_reg_rep__12_0;
  wire init_calib_complete_reg_rep__12_1;
  wire [7:0]init_calib_complete_reg_rep__13;
  wire init_calib_complete_reg_rep__9;
  wire iserdes_clkdiv;
  wire mc_read_idle_r_reg;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [1:0]\my_empty_reg[3] ;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[495] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofs_rdy_r_reg;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire out_fifo_n_40;
  wire out_fifo_n_41;
  wire out_fifo_n_42;
  wire out_fifo_n_43;
  wire out_fifo_n_48;
  wire out_fifo_n_49;
  wire out_fifo_n_50;
  wire out_fifo_n_51;
  wire p_65_in;
  wire p_66_in;
  wire p_67_out;
  wire p_69_in;
  wire p_70_in;
  wire p_71_out;
  wire p_73_in;
  wire p_74_in;
  wire p_75_out;
  wire p_77_in;
  wire p_78_in;
  wire p_79_out;
  wire p_7_in;
  wire p_81_in;
  wire p_82_in;
  wire p_83_out;
  wire p_85_in;
  wire p_86_in;
  wire p_87_out;
  wire p_89_in;
  wire p_90_in;
  wire p_91_out;
  wire p_93_in;
  wire p_94_in;
  wire p_95_out;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire rst_r4;
  wire sync_pulse;
  wire wr_en_14;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[1] ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized7 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .CLK(CLK),
        .CTSBUS(oserdes_dqs_ts[0]),
        .C_idelay_ce2_out(C_idelay_ce2_out),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .\ddr3_dm[5] (\ddr3_dm[5] ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .iserdes_clkdiv(iserdes_clkdiv),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .p_65_in(p_65_in),
        .p_66_in(p_66_in),
        .p_67_out(p_67_out),
        .p_69_in(p_69_in),
        .p_70_in(p_70_in),
        .p_71_out(p_71_out),
        .p_73_in(p_73_in),
        .p_74_in(p_74_in),
        .p_75_out(p_75_out),
        .p_77_in(p_77_in),
        .p_78_in(p_78_in),
        .p_79_out(p_79_out),
        .p_7_in(p_7_in),
        .p_81_in(p_81_in),
        .p_82_in(p_82_in),
        .p_83_out(p_83_out),
        .p_85_in(p_85_in),
        .p_86_in(p_86_in),
        .p_87_out(p_87_out),
        .p_89_in(p_89_in),
        .p_90_in(p_90_in),
        .p_91_out(p_91_out),
        .p_93_in(p_93_in),
        .p_94_in(p_94_in),
        .p_95_out(p_95_out),
        .\pi_dqs_found_lanes_r1_reg[10] (\pi_dqs_found_lanes_r1_reg[10] ),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4));
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[6]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[7]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[0]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[1]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[2]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[3]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[4]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[5]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[6]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q2[7]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[0]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[1]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[2]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[3]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[4]),
        .Q(Q[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[5]),
        .Q(Q[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[6]),
        .Q(Q[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q3[7]),
        .Q(Q[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[0]),
        .Q(Q[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[1]),
        .Q(Q[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[2]),
        .Q(Q[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[3]),
        .Q(Q[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[4]),
        .Q(Q[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[5]),
        .Q(Q[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[6]),
        .Q(Q[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q4[7]),
        .Q(Q[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[0]),
        .Q(Q[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[1]),
        .Q(Q[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[2]),
        .Q(Q[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[3]),
        .Q(Q[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[4]),
        .Q(Q[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[5]),
        .Q(Q[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[6]),
        .Q(Q[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q5[7]),
        .Q(Q[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[0]),
        .Q(Q[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[1]),
        .Q(Q[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[2]),
        .Q(Q[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[3]),
        .Q(Q[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[4]),
        .Q(Q[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[5]),
        .Q(Q[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[6]),
        .Q(Q[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q6[7]),
        .Q(Q[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[0]),
        .Q(Q[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[1]),
        .Q(Q[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[2]),
        .Q(Q[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[3]),
        .Q(Q[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[4]),
        .Q(Q[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[5]),
        .Q(Q[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[6]),
        .Q(Q[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q7[7]),
        .Q(Q[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[0]),
        .Q(Q[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[1]),
        .Q(Q[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[2]),
        .Q(Q[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[3]),
        .Q(Q[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[4]),
        .Q(Q[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[5]),
        .Q(Q[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[6]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[6]),
        .Q(Q[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q8[7]),
        .Q(Q[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q0[7]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_q1[1]),
        .Q(Q[3]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.CLK(CLK),
        .Q(Q[65:2]),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (\gen_rd[5].rd_data_rise_wl_r_reg[5] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .ififo_rd_en_in(ififo_rd_en_in),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[495] (\not_strict_mode.app_rd_data_reg[495] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(C_pi_rst_dqs_find55_out),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(C_if_a_empty),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9({1'b0,1'b0,1'b0,1'b0}),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(if_q0),
        .Q1(if_q1),
        .Q2(if_q2),
        .Q3(if_q3),
        .Q4(if_q4),
        .Q5(if_q5),
        .Q6(if_q6),
        .Q7(if_q7),
        .Q8(if_q8),
        .Q9(if_q9),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized11 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),
        .Q(\wr_ptr_timing_reg[3] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\cmd_pipe_plus.mc_wrdata_en_reg (\cmd_pipe_plus.mc_wrdata_en_reg ),
        .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12_1),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .of_wren_pre(of_wren_pre),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg(\my_empty_reg[7] ),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3] ),
        .wr_en_14(wr_en_14));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(C_pi_rst_dqs_find55_out),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(C_of_data_a_full),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),
        .D1(\write_buffer.wr_buf_out_data_reg[495] ),
        .D2(\write_buffer.wr_buf_out_data_reg[494] ),
        .D3(\write_buffer.wr_buf_out_data_reg[493] ),
        .D4(init_calib_complete_reg_rep__13),
        .D5(\write_buffer.wr_buf_out_data_reg[491] ),
        .D6(\write_buffer.wr_buf_out_data_reg[490] ),
        .D7(\write_buffer.wr_buf_out_data_reg[489] ),
        .D8(init_calib_complete_reg_rep__12),
        .D9(init_calib_complete_reg_rep__12_0),
        .EMPTY(out_fifo_n_2),
        .FULL(\my_empty_reg[7] ),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],out_fifo_n_40,out_fifo_n_41,out_fifo_n_42,out_fifo_n_43}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],out_fifo_n_48,out_fifo_n_49,out_fifo_n_50,out_fifo_n_51}),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(of_wren_pre));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.000000),
    .REFCLK_PERIOD(1.500000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(C_pi_counter_load_en61_out),
        .COUNTERLOADVAL(\calib_zero_inputs_reg[2] ),
        .COUNTERREADEN(\calib_sel_reg[1] ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(C_pi_dqs_out_of_range),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(C_pi_fine_enable57_out),
        .FINEINC(C_pi_fine_inc59_out),
        .FINEOVERFLOW(C_pi_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .ICLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(pi_phase_locked_all_r1_reg),
        .PHASEREFCLK(mc_read_idle_r_reg),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(C_pi_rst_dqs_find55_out),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.000000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(8),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.500000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(C_po_coarse_enable43_out),
        .COARSEINC(C_po_coarse_enable43_out),
        .COARSEOVERFLOW(C_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\calib_sel_reg[1] ),
        .COUNTERREADVAL(\po_counter_read_val_reg[8] ),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(C_po_fine_enable41_out),
        .FINEINC(C_po_fine_inc45_out),
        .FINEOVERFLOW(C_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_calib_top" *) 
module mig_7series_0_mig_7series_v2_3_ddr_calib_top
   (init_complete_r_timing,
    \read_fifo.tail_r_reg[1] ,
    complex_row1_rd_done_reg,
    calib_cmd_wren,
    calib_wrdata_en,
    rdlvl_stg1_start_r_reg,
    init_calib_complete,
    phy_if_reset,
    tempmon_pi_f_inc,
    idelay_inc,
    calib_in_common,
    app_zq_r_reg,
    \my_empty_reg[6] ,
    \my_empty_reg[1] ,
    \my_empty_reg[6]_0 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \wr_ptr_timing_reg[0] ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    \data_offset_2_i1_reg[3] ,
    \data_offset_2_i1_reg[2] ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \my_empty_reg[7]_15 ,
    phy_dout,
    reset_if,
    dqs_po_en_stg2_f_reg,
    idelay_tap_limit_r_reg,
    samp_edge_cnt0_en_r,
    fine_dly_dec_done_r1_reg,
    tempmon_pi_f_dec,
    phy_if_reset_w,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    Q,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    phy_ctl_wr_i1_reg,
    \cmd_pipe_plus.mc_data_offset_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \po_counter_read_val_reg[8] ,
    COUNTERLOADVAL,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[4] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \pi_dqs_found_lanes_r1_reg[1] ,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 ,
    \idelay_tap_cnt_r_reg[0][7][3] ,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    wr_en,
    E,
    wr_en_0,
    \wr_ptr_reg[2] ,
    wr_en_1,
    \wr_ptr_reg[2]_0 ,
    D,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \rdlvl_dqs_tap_cnt_r_reg[0][4][0] ,
    maint_prescaler_r1,
    maint_ref_zq_wip_r_reg,
    \cmd_pipe_plus.mc_data_offset_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ,
    phy_data_wr_en,
    phy_cmd_wr_en,
    mux_reset_n,
    \data_offset_1_i1_reg[5] ,
    \data_offset_2_i1_reg[5] ,
    \wr_ptr_timing_reg[0]_0 ,
    \wr_ptr_timing_reg[0]_1 ,
    \phy_ctl_wd_i1_reg[24] ,
    \my_empty_reg[7]_16 ,
    mux_wrdata,
    \my_empty_reg[7]_17 ,
    mux_wrdata_mask,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    ofifo_rst0,
    D_po_coarse_enable105_out,
    C_po_coarse_enable66_out,
    B_po_coarse_enable27_out,
    A_po_coarse_enable143_out,
    A_idelay_ce19_out,
    A_po_fine_enable141_out,
    A_po_fine_inc145_out,
    A_pi_rst_dqs_find155_out,
    A_pi_fine_enable157_out,
    A_pi_fine_inc159_out,
    A_pi_counter_load_en161_out,
    B_po_fine_enable24_out,
    B_po_fine_inc30_out,
    C_po_fine_enable63_out,
    C_po_fine_inc69_out,
    D_po_fine_enable102_out,
    D_po_fine_inc108_out,
    D_idelay_ce1_out,
    D_po_fine_inc74_out,
    D_po_fine_enable70_out,
    D_po_coarse_enable72_out,
    D_pi_rst_dqs_find84_out,
    D_pi_fine_inc88_out,
    D_pi_fine_enable86_out,
    D_pi_counter_load_en90_out,
    C_po_coarse_enable46_out,
    B_po_coarse_enable20_out,
    A_po_coarse_enable98_out,
    A_idelay_ce13_out,
    A_po_fine_enable96_out,
    A_po_fine_inc100_out,
    A_pi_rst_dqs_find110_out,
    A_pi_fine_enable112_out,
    A_pi_fine_inc114_out,
    A_pi_counter_load_en116_out,
    B_idelay_ce9_out,
    B_po_fine_enable18_out,
    B_po_fine_inc22_out,
    B_pi_rst_dqs_find32_out,
    B_pi_fine_enable34_out,
    B_pi_fine_inc36_out,
    B_pi_counter_load_en38_out,
    C_idelay_ce5_out,
    C_po_fine_enable44_out,
    C_po_fine_inc48_out,
    C_pi_rst_dqs_find58_out,
    C_pi_fine_enable60_out,
    C_pi_fine_inc62_out,
    C_pi_counter_load_en64_out,
    D9,
    D7,
    D6,
    D5,
    D4,
    D3,
    D2,
    D1,
    D0,
    \wr_ptr_timing_reg[0]_2 ,
    \wr_ptr_timing_reg[0]_3 ,
    \wr_ptr_timing_reg[0]_4 ,
    \wr_ptr_timing_reg[0]_5 ,
    \wr_ptr_timing_reg[0]_6 ,
    D8,
    \wr_ptr_timing_reg[0]_7 ,
    \wr_ptr_timing_reg[0]_8 ,
    \wr_ptr_timing_reg[0]_9 ,
    \wr_ptr_timing_reg[0]_10 ,
    \wr_ptr_timing_reg[0]_11 ,
    \wr_ptr_timing_reg[0]_12 ,
    \wr_ptr_timing_reg[0]_13 ,
    \wr_ptr_timing_reg[0]_14 ,
    \my_empty_reg[7]_18 ,
    \my_empty_reg[7]_19 ,
    \my_empty_reg[7]_20 ,
    \my_empty_reg[7]_21 ,
    \my_empty_reg[7]_22 ,
    \my_empty_reg[7]_23 ,
    \my_empty_reg[7]_24 ,
    \my_empty_reg[7]_25 ,
    \my_empty_reg[7]_26 ,
    \my_empty_reg[7]_27 ,
    \my_empty_reg[7]_28 ,
    \my_empty_reg[7]_29 ,
    \my_empty_reg[7]_30 ,
    \my_empty_reg[7]_31 ,
    \my_empty_reg[7]_32 ,
    \my_empty_reg[7]_33 ,
    \my_empty_reg[7]_34 ,
    \my_empty_reg[7]_35 ,
    \my_empty_reg[7]_36 ,
    \my_empty_reg[7]_37 ,
    \my_empty_reg[7]_38 ,
    \my_empty_reg[7]_39 ,
    \my_empty_reg[7]_40 ,
    \my_empty_reg[7]_41 ,
    \my_empty_reg[7]_42 ,
    \my_empty_reg[7]_43 ,
    \my_empty_reg[7]_44 ,
    \my_empty_reg[7]_45 ,
    \my_empty_reg[7]_46 ,
    \my_empty_reg[7]_47 ,
    \my_empty_reg[7]_48 ,
    \my_empty_reg[7]_49 ,
    \entry_cnt_reg[3] ,
    \entry_cnt_reg[3]_0 ,
    \my_empty_reg[7]_50 ,
    \my_empty_reg[7]_51 ,
    \my_empty_reg[7]_52 ,
    \my_empty_reg[7]_53 ,
    \my_empty_reg[7]_54 ,
    \my_empty_reg[7]_55 ,
    \my_empty_reg[7]_56 ,
    \my_empty_reg[7]_57 ,
    \my_empty_reg[7]_58 ,
    \my_empty_reg[7]_59 ,
    \my_empty_reg[7]_60 ,
    \my_empty_reg[7]_61 ,
    \my_empty_reg[7]_62 ,
    \my_empty_reg[7]_63 ,
    \my_empty_reg[7]_64 ,
    \my_empty_reg[7]_65 ,
    \my_empty_reg[7]_66 ,
    \my_empty_reg[7]_67 ,
    \my_empty_reg[7]_68 ,
    \my_empty_reg[7]_69 ,
    \my_empty_reg[7]_70 ,
    \my_empty_reg[7]_71 ,
    \my_empty_reg[7]_72 ,
    \my_empty_reg[7]_73 ,
    \my_empty_reg[7]_74 ,
    \my_empty_reg[7]_75 ,
    \my_empty_reg[7]_76 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    C_po_coarse_enable43_out,
    B_po_coarse_enable17_out,
    A_po_coarse_enable69_out,
    A_idelay_ce10_out,
    A_po_fine_enable67_out,
    A_po_fine_inc71_out,
    A_pi_rst_dqs_find81_out,
    A_pi_fine_enable83_out,
    A_pi_fine_inc85_out,
    A_pi_counter_load_en87_out,
    B_idelay_ce6_out,
    B_po_fine_enable15_out,
    B_po_fine_inc19_out,
    B_pi_rst_dqs_find29_out,
    B_pi_fine_enable31_out,
    B_pi_fine_inc33_out,
    B_pi_counter_load_en35_out,
    C_idelay_ce2_out,
    C_po_fine_enable41_out,
    C_po_fine_inc45_out,
    C_pi_rst_dqs_find55_out,
    C_pi_fine_enable57_out,
    C_pi_fine_inc59_out,
    C_pi_counter_load_en61_out,
    \my_empty_reg[6]_1 ,
    \my_empty_reg[6]_2 ,
    \my_empty_reg[6]_3 ,
    \my_empty_reg[6]_4 ,
    wrlvl_final_if_rst,
    write_calib,
    read_calib,
    \pi_dqs_found_lanes_r1_reg[4]_0 ,
    \pi_dqs_found_lanes_r1_reg[1]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    A_rst_primitives_reg,
    rstdiv0_sync_r1_reg_rep__4,
    CLK,
    rstdiv0_sync_r1_reg_rep__3,
    rstdiv0_sync_r1_reg_rep__18,
    init_complete_r_timing_reg,
    phy_if_reset0,
    tempmon_sel_pi_incdec,
    phy_rddata_en,
    rstdiv0_sync_r1_reg_rep__24,
    phy_ctl_ready,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    SR,
    rstdiv0_sync_r1_reg_rep__10,
    rstdiv0_sync_r1_reg_rep__2,
    \rd_mux_sel_r_reg[0] ,
    \rd_mux_sel_r_reg[0]_0 ,
    \rd_mux_sel_r_reg[0]_1 ,
    \rd_mux_sel_r_reg[0]_2 ,
    \rd_mux_sel_r_reg[0]_3 ,
    \rd_mux_sel_r_reg[0]_4 ,
    \rd_mux_sel_r_reg[0]_5 ,
    \rd_mux_sel_r_reg[0]_6 ,
    \rd_mux_sel_r_reg[0]_7 ,
    \rd_mux_sel_r_reg[0]_8 ,
    \rd_mux_sel_r_reg[0]_9 ,
    \rd_mux_sel_r_reg[0]_10 ,
    \rd_mux_sel_r_reg[0]_11 ,
    \rd_mux_sel_r_reg[0]_12 ,
    \rd_mux_sel_r_reg[0]_13 ,
    \rd_mux_sel_r_reg[0]_14 ,
    \rd_mux_sel_r_reg[0]_15 ,
    \rd_mux_sel_r_reg[0]_16 ,
    \rd_mux_sel_r_reg[0]_17 ,
    \rd_mux_sel_r_reg[0]_18 ,
    \rd_mux_sel_r_reg[0]_19 ,
    \rd_mux_sel_r_reg[0]_20 ,
    \rd_mux_sel_r_reg[0]_21 ,
    \rd_mux_sel_r_reg[0]_22 ,
    \rd_mux_sel_r_reg[0]_23 ,
    \rd_mux_sel_r_reg[0]_24 ,
    \rd_mux_sel_r_reg[0]_25 ,
    \rd_mux_sel_r_reg[0]_26 ,
    \rd_mux_sel_r_reg[0]_27 ,
    \rd_mux_sel_r_reg[0]_28 ,
    \rd_mux_sel_r_reg[0]_29 ,
    \rd_mux_sel_r_reg[0]_30 ,
    \rd_mux_sel_r_reg[0]_31 ,
    \rd_mux_sel_r_reg[0]_32 ,
    \rd_mux_sel_r_reg[0]_33 ,
    \rd_mux_sel_r_reg[0]_34 ,
    \rd_mux_sel_r_reg[0]_35 ,
    \rd_mux_sel_r_reg[0]_36 ,
    \rd_mux_sel_r_reg[0]_37 ,
    \rd_mux_sel_r_reg[0]_38 ,
    \rd_mux_sel_r_reg[0]_39 ,
    \rd_mux_sel_r_reg[0]_40 ,
    \rd_mux_sel_r_reg[0]_41 ,
    \rd_mux_sel_r_reg[0]_42 ,
    \rd_mux_sel_r_reg[0]_43 ,
    \rd_mux_sel_r_reg[0]_44 ,
    \rd_mux_sel_r_reg[0]_45 ,
    \rd_mux_sel_r_reg[0]_46 ,
    \rd_mux_sel_r_reg[0]_47 ,
    \rd_mux_sel_r_reg[0]_48 ,
    \rd_mux_sel_r_reg[0]_49 ,
    \rd_mux_sel_r_reg[0]_50 ,
    \rd_mux_sel_r_reg[0]_51 ,
    \rd_mux_sel_r_reg[0]_52 ,
    \rd_mux_sel_r_reg[0]_53 ,
    \rd_mux_sel_r_reg[0]_54 ,
    \rd_mux_sel_r_reg[0]_55 ,
    \rd_mux_sel_r_reg[0]_56 ,
    \rd_mux_sel_r_reg[0]_57 ,
    \rd_mux_sel_r_reg[0]_58 ,
    \rd_mux_sel_r_reg[0]_59 ,
    \rd_mux_sel_r_reg[0]_60 ,
    \rd_mux_sel_r_reg[0]_61 ,
    \rd_mux_sel_r_reg[0]_62 ,
    rstdiv0_sync_r1_reg_rep__1,
    rstdiv0_sync_r1_reg_rep__24_0,
    rstdiv0_sync_r1_reg_rep__13,
    tempmon_sample_en,
    rstdiv0_sync_r1_reg_rep__15,
    p_0_out,
    \po_stg2_wrcal_cnt_reg[0] ,
    \po_stg2_wrcal_cnt_reg[0]_0 ,
    \po_stg2_wrcal_cnt_reg[0]_1 ,
    \po_stg2_wrcal_cnt_reg[0]_2 ,
    \po_stg2_wrcal_cnt_reg[0]_3 ,
    \po_stg2_wrcal_cnt_reg[0]_4 ,
    \po_stg2_wrcal_cnt_reg[0]_5 ,
    \po_stg2_wrcal_cnt_reg[0]_6 ,
    \po_stg2_wrcal_cnt_reg[0]_7 ,
    \po_stg2_wrcal_cnt_reg[0]_8 ,
    \po_stg2_wrcal_cnt_reg[0]_9 ,
    \po_stg2_wrcal_cnt_reg[0]_10 ,
    \po_stg2_wrcal_cnt_reg[0]_11 ,
    \po_stg2_wrcal_cnt_reg[0]_12 ,
    \po_stg2_wrcal_cnt_reg[0]_13 ,
    \po_stg2_wrcal_cnt_reg[0]_14 ,
    \po_stg2_wrcal_cnt_reg[0]_15 ,
    \po_stg2_wrcal_cnt_reg[0]_16 ,
    \po_stg2_wrcal_cnt_reg[0]_17 ,
    \po_stg2_wrcal_cnt_reg[0]_18 ,
    \po_stg2_wrcal_cnt_reg[0]_19 ,
    \po_stg2_wrcal_cnt_reg[0]_20 ,
    \po_stg2_wrcal_cnt_reg[0]_21 ,
    \po_stg2_wrcal_cnt_reg[0]_22 ,
    \po_stg2_wrcal_cnt_reg[0]_23 ,
    \po_stg2_wrcal_cnt_reg[0]_24 ,
    \po_stg2_wrcal_cnt_reg[0]_25 ,
    \po_stg2_wrcal_cnt_reg[0]_26 ,
    \po_stg2_wrcal_cnt_reg[0]_27 ,
    \po_stg2_wrcal_cnt_reg[0]_28 ,
    \po_stg2_wrcal_cnt_reg[0]_29 ,
    \po_stg2_wrcal_cnt_reg[0]_30 ,
    \po_stg2_wrcal_cnt_reg[0]_31 ,
    \po_stg2_wrcal_cnt_reg[0]_32 ,
    \po_stg2_wrcal_cnt_reg[0]_33 ,
    \po_stg2_wrcal_cnt_reg[0]_34 ,
    \po_stg2_wrcal_cnt_reg[0]_35 ,
    \po_stg2_wrcal_cnt_reg[0]_36 ,
    \po_stg2_wrcal_cnt_reg[0]_37 ,
    \po_stg2_wrcal_cnt_reg[0]_38 ,
    \po_stg2_wrcal_cnt_reg[0]_39 ,
    \po_stg2_wrcal_cnt_reg[0]_40 ,
    \po_stg2_wrcal_cnt_reg[0]_41 ,
    \po_stg2_wrcal_cnt_reg[0]_42 ,
    \po_stg2_wrcal_cnt_reg[0]_43 ,
    \po_stg2_wrcal_cnt_reg[0]_44 ,
    \po_stg2_wrcal_cnt_reg[0]_45 ,
    \po_stg2_wrcal_cnt_reg[0]_46 ,
    \po_stg2_wrcal_cnt_reg[0]_47 ,
    \po_stg2_wrcal_cnt_reg[0]_48 ,
    \po_stg2_wrcal_cnt_reg[0]_49 ,
    \po_stg2_wrcal_cnt_reg[0]_50 ,
    \po_stg2_wrcal_cnt_reg[0]_51 ,
    \po_stg2_wrcal_cnt_reg[0]_52 ,
    \po_stg2_wrcal_cnt_reg[0]_53 ,
    \po_stg2_wrcal_cnt_reg[0]_54 ,
    \po_stg2_wrcal_cnt_reg[0]_55 ,
    \po_stg2_wrcal_cnt_reg[0]_56 ,
    \po_stg2_wrcal_cnt_reg[0]_57 ,
    \po_stg2_wrcal_cnt_reg[0]_58 ,
    \po_stg2_wrcal_cnt_reg[0]_59 ,
    \po_stg2_wrcal_cnt_reg[0]_60 ,
    \po_stg2_wrcal_cnt_reg[0]_61 ,
    idelay_ld_rst,
    idelay_ld_rst_2,
    idelay_ld_rst_3,
    idelay_ld_rst_4,
    rstdiv0_sync_r1_reg_rep__22,
    \pi_counter_read_val_reg[0] ,
    \pi_counter_read_val_reg[1] ,
    \pi_counter_read_val_reg[0]_0 ,
    \pi_counter_read_val_reg[2] ,
    \pi_counter_read_val_reg[1]_0 ,
    \pi_counter_read_val_reg[2]_0 ,
    \pi_counter_read_val_reg[3] ,
    \pi_counter_read_val_reg[4] ,
    rstdiv0_sync_r1_reg_rep__24_1,
    \my_empty_reg[3] ,
    \my_empty_reg[5] ,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[5]_0 ,
    \my_empty_reg[3]_1 ,
    \my_empty_reg[5]_1 ,
    COUNTERREADVAL,
    refresh_bank_r,
    sent_col,
    col_rd_wr,
    complex_row0_rd_done1,
    \po_counter_read_val_reg[0] ,
    \po_counter_read_val_reg[1] ,
    \po_counter_read_val_reg[2] ,
    \po_counter_read_val_reg[3] ,
    \po_counter_read_val_reg[4] ,
    \po_counter_read_val_reg[5] ,
    \po_counter_read_val_reg[6] ,
    \po_counter_read_val_reg[7] ,
    \po_counter_read_val_reg[8]_2 ,
    rstdiv0_sync_r1_reg_rep__23,
    \pi_counter_read_val_reg[5] ,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ,
    mc_cas_n,
    mc_ras_n,
    mc_odt,
    mc_cke,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[0]_0 ,
    mc_cmd,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \write_buffer.wr_buf_out_data_reg[575] ,
    idelay_ld_rst_5,
    A_rst_primitives,
    \my_empty_reg[1]_0 ,
    \rd_ptr_reg_rep[3] ,
    \my_empty_reg[1]_1 ,
    \rd_ptr_reg_rep[3]_0 ,
    mc_cs_n,
    \my_empty_reg[1]_2 ,
    \rd_ptr_reg_rep[3]_1 ,
    \my_empty_reg[1]_3 ,
    mem_out,
    \my_empty_reg[1]_4 ,
    \rd_ptr_reg_rep[3]_2 ,
    \my_empty_reg[1]_5 ,
    \rd_ptr_reg_rep[3]_3 ,
    \my_empty_reg[1]_6 ,
    \rd_ptr_reg_rep[3]_4 ,
    B_of_data_full,
    \my_full_reg[4] ,
    C_of_data_full,
    \my_full_reg[4]_0 ,
    \my_empty_reg[1]_7 ,
    \rd_ptr_reg_rep[3]_5 ,
    \my_empty_reg[1]_8 ,
    \rd_ptr_reg_rep[3]_6 ,
    \my_empty_reg[1]_9 ,
    \rd_ptr_reg_rep[3]_7 ,
    idelay_ld_rst_6,
    idelay_ld_rst_7,
    idelay_ld_rst_8,
    init_calib_complete_reg_rep__28_0,
    \my_empty_reg[1]_10 ,
    rstdiv0_sync_r1_reg_rep__21,
    rstdiv0_sync_r1_reg_rep,
    rstdiv0_sync_r1,
    rstdiv0_sync_r1_reg_rep__9,
    rstdiv0_sync_r1_reg_rep__7,
    rstdiv0_sync_r1_reg_rep__6,
    SS,
    rstdiv0_sync_r1_reg_rep__24_2,
    rstdiv0_sync_r1_reg_rep__24_3,
    rstdiv0_sync_r1_reg_rep__24_4,
    rstdiv0_sync_r1_reg_rep__24_5,
    \device_temp_r_reg[11] ,
    rstdiv0_sync_r1_reg_rep__16,
    rstdiv0_sync_r1_reg_rep__14,
    rstdiv0_sync_r1_reg_rep__17,
    \pi_counter_read_val_reg[4]_0 ,
    pi_dqs_found_lanes,
    rstdiv0_sync_r1_reg_rep__12);
  output init_complete_r_timing;
  output \read_fifo.tail_r_reg[1] ;
  output complex_row1_rd_done_reg;
  output calib_cmd_wren;
  output calib_wrdata_en;
  output rdlvl_stg1_start_r_reg;
  output init_calib_complete;
  output phy_if_reset;
  output tempmon_pi_f_inc;
  output idelay_inc;
  output calib_in_common;
  output app_zq_r_reg;
  output \my_empty_reg[6] ;
  output \my_empty_reg[1] ;
  output \my_empty_reg[6]_0 ;
  output \my_empty_reg[7] ;
  output \my_empty_reg[7]_0 ;
  output \my_empty_reg[7]_1 ;
  output \my_empty_reg[7]_2 ;
  output \my_empty_reg[7]_3 ;
  output \wr_ptr_timing_reg[0] ;
  output \my_empty_reg[7]_4 ;
  output \my_empty_reg[7]_5 ;
  output \my_empty_reg[7]_6 ;
  output \data_offset_2_i1_reg[3] ;
  output \data_offset_2_i1_reg[2] ;
  output \my_empty_reg[7]_7 ;
  output \my_empty_reg[7]_8 ;
  output \my_empty_reg[7]_9 ;
  output \my_empty_reg[7]_10 ;
  output \my_empty_reg[7]_11 ;
  output \my_empty_reg[7]_12 ;
  output \my_empty_reg[7]_13 ;
  output \my_empty_reg[7]_14 ;
  output \my_empty_reg[7]_15 ;
  output [21:0]phy_dout;
  output reset_if;
  output dqs_po_en_stg2_f_reg;
  output idelay_tap_limit_r_reg;
  output samp_edge_cnt0_en_r;
  output fine_dly_dec_done_r1_reg;
  output tempmon_pi_f_dec;
  output phy_if_reset_w;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output [3:0]Q;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output phy_ctl_wr_i1_reg;
  output \cmd_pipe_plus.mc_data_offset_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_reg[5] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  output \pi_dqs_found_lanes_r1_reg[3] ;
  output \po_counter_read_val_reg[8] ;
  output [5:0]COUNTERLOADVAL;
  output [5:0]\pi_dqs_found_lanes_r1_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[0] ;
  output \pi_dqs_found_lanes_r1_reg[4] ;
  output \pi_dqs_found_lanes_r1_reg[8]_0 ;
  output \pi_dqs_found_lanes_r1_reg[1] ;
  output \pi_dqs_found_lanes_r1_reg[9] ;
  output \pi_dqs_found_lanes_r1_reg[2] ;
  output \pi_dqs_found_lanes_r1_reg[10] ;
  output [2:0]\gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 ;
  output \idelay_tap_cnt_r_reg[0][7][3] ;
  output \gen_byte_sel_div2.calib_in_common_reg_0 ;
  output wr_en;
  output [0:0]E;
  output wr_en_0;
  output [0:0]\wr_ptr_reg[2] ;
  output wr_en_1;
  output [0:0]\wr_ptr_reg[2]_0 ;
  output [5:0]D;
  output \po_counter_read_val_reg[8]_0 ;
  output \po_counter_read_val_reg[8]_1 ;
  output [2:0]\rdlvl_dqs_tap_cnt_r_reg[0][4][0] ;
  output maint_prescaler_r1;
  output maint_ref_zq_wip_r_reg;
  output [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  output \cmd_pipe_plus.mc_data_offset_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  output phy_data_wr_en;
  output phy_cmd_wr_en;
  output mux_reset_n;
  output [5:0]\data_offset_1_i1_reg[5] ;
  output [5:0]\data_offset_2_i1_reg[5] ;
  output [4:0]\wr_ptr_timing_reg[0]_0 ;
  output [44:0]\wr_ptr_timing_reg[0]_1 ;
  output [10:0]\phy_ctl_wd_i1_reg[24] ;
  output [207:0]\my_empty_reg[7]_16 ;
  output [207:0]mux_wrdata;
  output [31:0]\my_empty_reg[7]_17 ;
  output [31:0]mux_wrdata_mask;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output ofifo_rst0;
  output D_po_coarse_enable105_out;
  output C_po_coarse_enable66_out;
  output B_po_coarse_enable27_out;
  output A_po_coarse_enable143_out;
  output A_idelay_ce19_out;
  output A_po_fine_enable141_out;
  output A_po_fine_inc145_out;
  output A_pi_rst_dqs_find155_out;
  output A_pi_fine_enable157_out;
  output A_pi_fine_inc159_out;
  output A_pi_counter_load_en161_out;
  output B_po_fine_enable24_out;
  output B_po_fine_inc30_out;
  output C_po_fine_enable63_out;
  output C_po_fine_inc69_out;
  output D_po_fine_enable102_out;
  output D_po_fine_inc108_out;
  output D_idelay_ce1_out;
  output D_po_fine_inc74_out;
  output D_po_fine_enable70_out;
  output D_po_coarse_enable72_out;
  output D_pi_rst_dqs_find84_out;
  output D_pi_fine_inc88_out;
  output D_pi_fine_enable86_out;
  output D_pi_counter_load_en90_out;
  output C_po_coarse_enable46_out;
  output B_po_coarse_enable20_out;
  output A_po_coarse_enable98_out;
  output A_idelay_ce13_out;
  output A_po_fine_enable96_out;
  output A_po_fine_inc100_out;
  output A_pi_rst_dqs_find110_out;
  output A_pi_fine_enable112_out;
  output A_pi_fine_inc114_out;
  output A_pi_counter_load_en116_out;
  output B_idelay_ce9_out;
  output B_po_fine_enable18_out;
  output B_po_fine_inc22_out;
  output B_pi_rst_dqs_find32_out;
  output B_pi_fine_enable34_out;
  output B_pi_fine_inc36_out;
  output B_pi_counter_load_en38_out;
  output C_idelay_ce5_out;
  output C_po_fine_enable44_out;
  output C_po_fine_inc48_out;
  output C_pi_rst_dqs_find58_out;
  output C_pi_fine_enable60_out;
  output C_pi_fine_inc62_out;
  output C_pi_counter_load_en64_out;
  output [7:0]D9;
  output [7:0]D7;
  output [7:0]D6;
  output [7:0]D5;
  output [7:0]D4;
  output [7:0]D3;
  output [7:0]D2;
  output [7:0]D1;
  output [7:0]D0;
  output [2:0]\wr_ptr_timing_reg[0]_2 ;
  output [5:0]\wr_ptr_timing_reg[0]_3 ;
  output [3:0]\wr_ptr_timing_reg[0]_4 ;
  output [3:0]\wr_ptr_timing_reg[0]_5 ;
  output [3:0]\wr_ptr_timing_reg[0]_6 ;
  output [3:0]D8;
  output [3:0]\wr_ptr_timing_reg[0]_7 ;
  output [7:0]\wr_ptr_timing_reg[0]_8 ;
  output [7:0]\wr_ptr_timing_reg[0]_9 ;
  output [3:0]\wr_ptr_timing_reg[0]_10 ;
  output [3:0]\wr_ptr_timing_reg[0]_11 ;
  output [3:0]\wr_ptr_timing_reg[0]_12 ;
  output [3:0]\wr_ptr_timing_reg[0]_13 ;
  output [2:0]\wr_ptr_timing_reg[0]_14 ;
  output [5:0]\my_empty_reg[7]_18 ;
  output [5:0]\my_empty_reg[7]_19 ;
  output [4:0]\my_empty_reg[7]_20 ;
  output [4:0]\my_empty_reg[7]_21 ;
  output [5:0]\my_empty_reg[7]_22 ;
  output [5:0]\my_empty_reg[7]_23 ;
  output [4:0]\my_empty_reg[7]_24 ;
  output [4:0]\my_empty_reg[7]_25 ;
  output [5:0]\my_empty_reg[7]_26 ;
  output [5:0]\my_empty_reg[7]_27 ;
  output [4:0]\my_empty_reg[7]_28 ;
  output [4:0]\my_empty_reg[7]_29 ;
  output [5:0]\my_empty_reg[7]_30 ;
  output [5:0]\my_empty_reg[7]_31 ;
  output [4:0]\my_empty_reg[7]_32 ;
  output [4:0]\my_empty_reg[7]_33 ;
  output [5:0]\my_empty_reg[7]_34 ;
  output [5:0]\my_empty_reg[7]_35 ;
  output [4:0]\my_empty_reg[7]_36 ;
  output [4:0]\my_empty_reg[7]_37 ;
  output [5:0]\my_empty_reg[7]_38 ;
  output [5:0]\my_empty_reg[7]_39 ;
  output [4:0]\my_empty_reg[7]_40 ;
  output [4:0]\my_empty_reg[7]_41 ;
  output [5:0]\my_empty_reg[7]_42 ;
  output [5:0]\my_empty_reg[7]_43 ;
  output [4:0]\my_empty_reg[7]_44 ;
  output [4:0]\my_empty_reg[7]_45 ;
  output [5:0]\my_empty_reg[7]_46 ;
  output [5:0]\my_empty_reg[7]_47 ;
  output [4:0]\my_empty_reg[7]_48 ;
  output [4:0]\my_empty_reg[7]_49 ;
  output \entry_cnt_reg[3] ;
  output \entry_cnt_reg[3]_0 ;
  output [7:0]\my_empty_reg[7]_50 ;
  output [7:0]\my_empty_reg[7]_51 ;
  output [7:0]\my_empty_reg[7]_52 ;
  output [7:0]\my_empty_reg[7]_53 ;
  output [7:0]\my_empty_reg[7]_54 ;
  output [7:0]\my_empty_reg[7]_55 ;
  output [7:0]\my_empty_reg[7]_56 ;
  output [7:0]\my_empty_reg[7]_57 ;
  output [7:0]\my_empty_reg[7]_58 ;
  output [7:0]\my_empty_reg[7]_59 ;
  output [7:0]\my_empty_reg[7]_60 ;
  output [7:0]\my_empty_reg[7]_61 ;
  output [7:0]\my_empty_reg[7]_62 ;
  output [7:0]\my_empty_reg[7]_63 ;
  output [7:0]\my_empty_reg[7]_64 ;
  output [7:0]\my_empty_reg[7]_65 ;
  output [7:0]\my_empty_reg[7]_66 ;
  output [7:0]\my_empty_reg[7]_67 ;
  output [7:0]\my_empty_reg[7]_68 ;
  output [7:0]\my_empty_reg[7]_69 ;
  output [7:0]\my_empty_reg[7]_70 ;
  output [7:0]\my_empty_reg[7]_71 ;
  output [7:0]\my_empty_reg[7]_72 ;
  output [7:0]\my_empty_reg[7]_73 ;
  output [7:0]\my_empty_reg[7]_74 ;
  output [7:0]\my_empty_reg[7]_75 ;
  output [7:0]\my_empty_reg[7]_76 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output C_po_coarse_enable43_out;
  output B_po_coarse_enable17_out;
  output A_po_coarse_enable69_out;
  output A_idelay_ce10_out;
  output A_po_fine_enable67_out;
  output A_po_fine_inc71_out;
  output A_pi_rst_dqs_find81_out;
  output A_pi_fine_enable83_out;
  output A_pi_fine_inc85_out;
  output A_pi_counter_load_en87_out;
  output B_idelay_ce6_out;
  output B_po_fine_enable15_out;
  output B_po_fine_inc19_out;
  output B_pi_rst_dqs_find29_out;
  output B_pi_fine_enable31_out;
  output B_pi_fine_inc33_out;
  output B_pi_counter_load_en35_out;
  output C_idelay_ce2_out;
  output C_po_fine_enable41_out;
  output C_po_fine_inc45_out;
  output C_pi_rst_dqs_find55_out;
  output C_pi_fine_enable57_out;
  output C_pi_fine_inc59_out;
  output C_pi_counter_load_en61_out;
  output [3:0]\my_empty_reg[6]_1 ;
  output [3:0]\my_empty_reg[6]_2 ;
  output [3:0]\my_empty_reg[6]_3 ;
  output [3:0]\my_empty_reg[6]_4 ;
  output wrlvl_final_if_rst;
  output write_calib;
  output read_calib;
  output [5:0]\pi_dqs_found_lanes_r1_reg[4]_0 ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[1]_0 ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[2]_0 ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[3]_0 ;
  output \gen_byte_sel_div2.calib_in_common_reg_1 ;
  output \gen_byte_sel_div2.calib_in_common_reg_2 ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[9]_0 ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[10]_0 ;
  input A_rst_primitives_reg;
  input rstdiv0_sync_r1_reg_rep__4;
  input CLK;
  input rstdiv0_sync_r1_reg_rep__3;
  input rstdiv0_sync_r1_reg_rep__18;
  input init_complete_r_timing_reg;
  input phy_if_reset0;
  input tempmon_sel_pi_incdec;
  input phy_rddata_en;
  input rstdiv0_sync_r1_reg_rep__24;
  input phy_ctl_ready;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input [0:0]SR;
  input [1:0]rstdiv0_sync_r1_reg_rep__10;
  input [0:0]rstdiv0_sync_r1_reg_rep__2;
  input \rd_mux_sel_r_reg[0] ;
  input \rd_mux_sel_r_reg[0]_0 ;
  input \rd_mux_sel_r_reg[0]_1 ;
  input \rd_mux_sel_r_reg[0]_2 ;
  input \rd_mux_sel_r_reg[0]_3 ;
  input \rd_mux_sel_r_reg[0]_4 ;
  input \rd_mux_sel_r_reg[0]_5 ;
  input \rd_mux_sel_r_reg[0]_6 ;
  input \rd_mux_sel_r_reg[0]_7 ;
  input \rd_mux_sel_r_reg[0]_8 ;
  input \rd_mux_sel_r_reg[0]_9 ;
  input \rd_mux_sel_r_reg[0]_10 ;
  input \rd_mux_sel_r_reg[0]_11 ;
  input \rd_mux_sel_r_reg[0]_12 ;
  input \rd_mux_sel_r_reg[0]_13 ;
  input \rd_mux_sel_r_reg[0]_14 ;
  input \rd_mux_sel_r_reg[0]_15 ;
  input \rd_mux_sel_r_reg[0]_16 ;
  input \rd_mux_sel_r_reg[0]_17 ;
  input \rd_mux_sel_r_reg[0]_18 ;
  input \rd_mux_sel_r_reg[0]_19 ;
  input \rd_mux_sel_r_reg[0]_20 ;
  input \rd_mux_sel_r_reg[0]_21 ;
  input \rd_mux_sel_r_reg[0]_22 ;
  input \rd_mux_sel_r_reg[0]_23 ;
  input \rd_mux_sel_r_reg[0]_24 ;
  input \rd_mux_sel_r_reg[0]_25 ;
  input \rd_mux_sel_r_reg[0]_26 ;
  input \rd_mux_sel_r_reg[0]_27 ;
  input \rd_mux_sel_r_reg[0]_28 ;
  input \rd_mux_sel_r_reg[0]_29 ;
  input \rd_mux_sel_r_reg[0]_30 ;
  input \rd_mux_sel_r_reg[0]_31 ;
  input \rd_mux_sel_r_reg[0]_32 ;
  input \rd_mux_sel_r_reg[0]_33 ;
  input \rd_mux_sel_r_reg[0]_34 ;
  input \rd_mux_sel_r_reg[0]_35 ;
  input \rd_mux_sel_r_reg[0]_36 ;
  input \rd_mux_sel_r_reg[0]_37 ;
  input \rd_mux_sel_r_reg[0]_38 ;
  input \rd_mux_sel_r_reg[0]_39 ;
  input \rd_mux_sel_r_reg[0]_40 ;
  input \rd_mux_sel_r_reg[0]_41 ;
  input \rd_mux_sel_r_reg[0]_42 ;
  input \rd_mux_sel_r_reg[0]_43 ;
  input \rd_mux_sel_r_reg[0]_44 ;
  input \rd_mux_sel_r_reg[0]_45 ;
  input \rd_mux_sel_r_reg[0]_46 ;
  input \rd_mux_sel_r_reg[0]_47 ;
  input \rd_mux_sel_r_reg[0]_48 ;
  input \rd_mux_sel_r_reg[0]_49 ;
  input \rd_mux_sel_r_reg[0]_50 ;
  input \rd_mux_sel_r_reg[0]_51 ;
  input \rd_mux_sel_r_reg[0]_52 ;
  input \rd_mux_sel_r_reg[0]_53 ;
  input \rd_mux_sel_r_reg[0]_54 ;
  input \rd_mux_sel_r_reg[0]_55 ;
  input \rd_mux_sel_r_reg[0]_56 ;
  input \rd_mux_sel_r_reg[0]_57 ;
  input \rd_mux_sel_r_reg[0]_58 ;
  input \rd_mux_sel_r_reg[0]_59 ;
  input \rd_mux_sel_r_reg[0]_60 ;
  input \rd_mux_sel_r_reg[0]_61 ;
  input \rd_mux_sel_r_reg[0]_62 ;
  input rstdiv0_sync_r1_reg_rep__1;
  input rstdiv0_sync_r1_reg_rep__24_0;
  input [0:0]rstdiv0_sync_r1_reg_rep__13;
  input tempmon_sample_en;
  input [0:0]rstdiv0_sync_r1_reg_rep__15;
  input p_0_out;
  input \po_stg2_wrcal_cnt_reg[0] ;
  input \po_stg2_wrcal_cnt_reg[0]_0 ;
  input \po_stg2_wrcal_cnt_reg[0]_1 ;
  input \po_stg2_wrcal_cnt_reg[0]_2 ;
  input \po_stg2_wrcal_cnt_reg[0]_3 ;
  input \po_stg2_wrcal_cnt_reg[0]_4 ;
  input \po_stg2_wrcal_cnt_reg[0]_5 ;
  input \po_stg2_wrcal_cnt_reg[0]_6 ;
  input \po_stg2_wrcal_cnt_reg[0]_7 ;
  input \po_stg2_wrcal_cnt_reg[0]_8 ;
  input \po_stg2_wrcal_cnt_reg[0]_9 ;
  input \po_stg2_wrcal_cnt_reg[0]_10 ;
  input \po_stg2_wrcal_cnt_reg[0]_11 ;
  input \po_stg2_wrcal_cnt_reg[0]_12 ;
  input \po_stg2_wrcal_cnt_reg[0]_13 ;
  input \po_stg2_wrcal_cnt_reg[0]_14 ;
  input \po_stg2_wrcal_cnt_reg[0]_15 ;
  input \po_stg2_wrcal_cnt_reg[0]_16 ;
  input \po_stg2_wrcal_cnt_reg[0]_17 ;
  input \po_stg2_wrcal_cnt_reg[0]_18 ;
  input \po_stg2_wrcal_cnt_reg[0]_19 ;
  input \po_stg2_wrcal_cnt_reg[0]_20 ;
  input \po_stg2_wrcal_cnt_reg[0]_21 ;
  input \po_stg2_wrcal_cnt_reg[0]_22 ;
  input \po_stg2_wrcal_cnt_reg[0]_23 ;
  input \po_stg2_wrcal_cnt_reg[0]_24 ;
  input \po_stg2_wrcal_cnt_reg[0]_25 ;
  input \po_stg2_wrcal_cnt_reg[0]_26 ;
  input \po_stg2_wrcal_cnt_reg[0]_27 ;
  input \po_stg2_wrcal_cnt_reg[0]_28 ;
  input \po_stg2_wrcal_cnt_reg[0]_29 ;
  input \po_stg2_wrcal_cnt_reg[0]_30 ;
  input \po_stg2_wrcal_cnt_reg[0]_31 ;
  input \po_stg2_wrcal_cnt_reg[0]_32 ;
  input \po_stg2_wrcal_cnt_reg[0]_33 ;
  input \po_stg2_wrcal_cnt_reg[0]_34 ;
  input \po_stg2_wrcal_cnt_reg[0]_35 ;
  input \po_stg2_wrcal_cnt_reg[0]_36 ;
  input \po_stg2_wrcal_cnt_reg[0]_37 ;
  input \po_stg2_wrcal_cnt_reg[0]_38 ;
  input \po_stg2_wrcal_cnt_reg[0]_39 ;
  input \po_stg2_wrcal_cnt_reg[0]_40 ;
  input \po_stg2_wrcal_cnt_reg[0]_41 ;
  input \po_stg2_wrcal_cnt_reg[0]_42 ;
  input \po_stg2_wrcal_cnt_reg[0]_43 ;
  input \po_stg2_wrcal_cnt_reg[0]_44 ;
  input \po_stg2_wrcal_cnt_reg[0]_45 ;
  input \po_stg2_wrcal_cnt_reg[0]_46 ;
  input \po_stg2_wrcal_cnt_reg[0]_47 ;
  input \po_stg2_wrcal_cnt_reg[0]_48 ;
  input \po_stg2_wrcal_cnt_reg[0]_49 ;
  input \po_stg2_wrcal_cnt_reg[0]_50 ;
  input \po_stg2_wrcal_cnt_reg[0]_51 ;
  input \po_stg2_wrcal_cnt_reg[0]_52 ;
  input \po_stg2_wrcal_cnt_reg[0]_53 ;
  input \po_stg2_wrcal_cnt_reg[0]_54 ;
  input \po_stg2_wrcal_cnt_reg[0]_55 ;
  input \po_stg2_wrcal_cnt_reg[0]_56 ;
  input \po_stg2_wrcal_cnt_reg[0]_57 ;
  input \po_stg2_wrcal_cnt_reg[0]_58 ;
  input \po_stg2_wrcal_cnt_reg[0]_59 ;
  input \po_stg2_wrcal_cnt_reg[0]_60 ;
  input \po_stg2_wrcal_cnt_reg[0]_61 ;
  input idelay_ld_rst;
  input idelay_ld_rst_2;
  input idelay_ld_rst_3;
  input idelay_ld_rst_4;
  input rstdiv0_sync_r1_reg_rep__22;
  input \pi_counter_read_val_reg[0] ;
  input \pi_counter_read_val_reg[1] ;
  input \pi_counter_read_val_reg[0]_0 ;
  input \pi_counter_read_val_reg[2] ;
  input \pi_counter_read_val_reg[1]_0 ;
  input \pi_counter_read_val_reg[2]_0 ;
  input \pi_counter_read_val_reg[3] ;
  input \pi_counter_read_val_reg[4] ;
  input rstdiv0_sync_r1_reg_rep__24_1;
  input \my_empty_reg[3] ;
  input \my_empty_reg[5] ;
  input \my_empty_reg[3]_0 ;
  input \my_empty_reg[5]_0 ;
  input \my_empty_reg[3]_1 ;
  input \my_empty_reg[5]_1 ;
  input [5:0]COUNTERREADVAL;
  input refresh_bank_r;
  input sent_col;
  input col_rd_wr;
  input complex_row0_rd_done1;
  input \po_counter_read_val_reg[0] ;
  input \po_counter_read_val_reg[1] ;
  input \po_counter_read_val_reg[2] ;
  input \po_counter_read_val_reg[3] ;
  input \po_counter_read_val_reg[4] ;
  input \po_counter_read_val_reg[5] ;
  input \po_counter_read_val_reg[6] ;
  input \po_counter_read_val_reg[7] ;
  input \po_counter_read_val_reg[8]_2 ;
  input rstdiv0_sync_r1_reg_rep__23;
  input \pi_counter_read_val_reg[5] ;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  input [2:0]mc_cas_n;
  input [2:0]mc_ras_n;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [2:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  input \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  input [1:0]mc_cmd;
  input [38:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input [527:0]\write_buffer.wr_buf_out_data_reg[575] ;
  input idelay_ld_rst_5;
  input A_rst_primitives;
  input \my_empty_reg[1]_0 ;
  input [71:0]\rd_ptr_reg_rep[3] ;
  input \my_empty_reg[1]_1 ;
  input [16:0]\rd_ptr_reg_rep[3]_0 ;
  input [0:0]mc_cs_n;
  input \my_empty_reg[1]_2 ;
  input [46:0]\rd_ptr_reg_rep[3]_1 ;
  input \my_empty_reg[1]_3 ;
  input [43:0]mem_out;
  input \my_empty_reg[1]_4 ;
  input [43:0]\rd_ptr_reg_rep[3]_2 ;
  input \my_empty_reg[1]_5 ;
  input [43:0]\rd_ptr_reg_rep[3]_3 ;
  input \my_empty_reg[1]_6 ;
  input [43:0]\rd_ptr_reg_rep[3]_4 ;
  input B_of_data_full;
  input \my_full_reg[4] ;
  input C_of_data_full;
  input \my_full_reg[4]_0 ;
  input \my_empty_reg[1]_7 ;
  input [71:0]\rd_ptr_reg_rep[3]_5 ;
  input \my_empty_reg[1]_8 ;
  input [71:0]\rd_ptr_reg_rep[3]_6 ;
  input \my_empty_reg[1]_9 ;
  input [71:0]\rd_ptr_reg_rep[3]_7 ;
  input idelay_ld_rst_6;
  input idelay_ld_rst_7;
  input idelay_ld_rst_8;
  input [15:0]init_calib_complete_reg_rep__28_0;
  input \my_empty_reg[1]_10 ;
  input rstdiv0_sync_r1_reg_rep__21;
  input rstdiv0_sync_r1_reg_rep;
  input rstdiv0_sync_r1;
  input [0:0]rstdiv0_sync_r1_reg_rep__9;
  input [1:0]rstdiv0_sync_r1_reg_rep__7;
  input [0:0]rstdiv0_sync_r1_reg_rep__6;
  input [0:0]SS;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_5;
  input [11:0]\device_temp_r_reg[11] ;
  input [0:0]rstdiv0_sync_r1_reg_rep__16;
  input [0:0]rstdiv0_sync_r1_reg_rep__14;
  input [0:0]rstdiv0_sync_r1_reg_rep__17;
  input \pi_counter_read_val_reg[4]_0 ;
  input [7:0]pi_dqs_found_lanes;
  input [0:0]rstdiv0_sync_r1_reg_rep__12;

  wire A_idelay_ce10_out;
  wire A_idelay_ce13_out;
  wire A_idelay_ce19_out;
  wire A_pi_counter_load_en116_out;
  wire A_pi_counter_load_en161_out;
  wire A_pi_counter_load_en87_out;
  wire A_pi_fine_enable112_out;
  wire A_pi_fine_enable157_out;
  wire A_pi_fine_enable83_out;
  wire A_pi_fine_inc114_out;
  wire A_pi_fine_inc159_out;
  wire A_pi_fine_inc85_out;
  wire A_pi_rst_dqs_find110_out;
  wire A_pi_rst_dqs_find155_out;
  wire A_pi_rst_dqs_find81_out;
  wire A_po_coarse_enable143_out;
  wire A_po_coarse_enable69_out;
  wire A_po_coarse_enable98_out;
  wire A_po_fine_enable141_out;
  wire A_po_fine_enable67_out;
  wire A_po_fine_enable96_out;
  wire A_po_fine_inc100_out;
  wire A_po_fine_inc145_out;
  wire A_po_fine_inc71_out;
  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire B_idelay_ce6_out;
  wire B_idelay_ce9_out;
  wire B_of_data_full;
  wire B_pi_counter_load_en35_out;
  wire B_pi_counter_load_en38_out;
  wire B_pi_fine_enable31_out;
  wire B_pi_fine_enable34_out;
  wire B_pi_fine_inc33_out;
  wire B_pi_fine_inc36_out;
  wire B_pi_rst_dqs_find29_out;
  wire B_pi_rst_dqs_find32_out;
  wire B_po_coarse_enable17_out;
  wire B_po_coarse_enable20_out;
  wire B_po_coarse_enable27_out;
  wire B_po_fine_enable15_out;
  wire B_po_fine_enable18_out;
  wire B_po_fine_enable24_out;
  wire B_po_fine_inc19_out;
  wire B_po_fine_inc22_out;
  wire B_po_fine_inc30_out;
  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire [5:0]COUNTERREADVAL;
  wire C_idelay_ce2_out;
  wire C_idelay_ce5_out;
  wire C_of_data_full;
  wire C_pi_counter_load_en61_out;
  wire C_pi_counter_load_en64_out;
  wire C_pi_fine_enable57_out;
  wire C_pi_fine_enable60_out;
  wire C_pi_fine_inc59_out;
  wire C_pi_fine_inc62_out;
  wire C_pi_rst_dqs_find55_out;
  wire C_pi_rst_dqs_find58_out;
  wire C_po_coarse_enable43_out;
  wire C_po_coarse_enable46_out;
  wire C_po_coarse_enable66_out;
  wire C_po_fine_enable41_out;
  wire C_po_fine_enable44_out;
  wire C_po_fine_enable63_out;
  wire C_po_fine_inc45_out;
  wire C_po_fine_inc48_out;
  wire C_po_fine_inc69_out;
  wire [5:0]D;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [3:0]D8;
  wire [7:0]D9;
  wire D_idelay_ce1_out;
  wire D_pi_counter_load_en90_out;
  wire D_pi_fine_enable86_out;
  wire D_pi_fine_inc88_out;
  wire D_pi_rst_dqs_find84_out;
  wire D_po_coarse_enable105_out;
  wire D_po_coarse_enable72_out;
  wire D_po_fine_enable102_out;
  wire D_po_fine_enable70_out;
  wire D_po_fine_inc108_out;
  wire D_po_fine_inc74_out;
  wire [0:0]E;
  wire [3:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire app_zq_r_reg;
  wire calib_cmd_wren;
  wire calib_complete;
  wire calib_in_common;
  wire \calib_sel[0]_i_2_n_0 ;
  wire \calib_sel[1]_i_2_n_0 ;
  wire calib_wrdata_en;
  wire [2:0]calib_zero_inputs;
  wire ck_po_stg2_f_en;
  wire [38:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire cmd_po_en_stg2_f;
  wire cnt_shift_r1545_out;
  wire col_rd_wr;
  wire complex_row0_rd_done;
  wire complex_row0_rd_done1;
  wire complex_row1_rd_done_reg;
  wire [2:0]ctl_lane_cnt;
  wire [5:0]\data_offset_1_i1_reg[5] ;
  wire \data_offset_2_i1_reg[2] ;
  wire \data_offset_2_i1_reg[3] ;
  wire [5:0]\data_offset_2_i1_reg[5] ;
  wire ddr3_lm_done_r;
  wire ddr_phy_tempmon_0_n_2;
  wire ddr_phy_tempmon_0_n_3;
  wire ddr_phy_tempmon_0_n_4;
  wire ddr_phy_tempmon_0_n_5;
  wire ddr_phy_tempmon_0_n_7;
  wire ddr_phy_tempmon_0_n_8;
  wire ddr_phy_tempmon_0_n_9;
  wire detect_pi_found_dqs;
  wire [11:0]\device_temp_r_reg[11] ;
  wire done_dqs_tap_inc;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire [3:3]dqs_count_r;
  wire dqs_found_prech_req;
  wire dqs_po_dec_done;
  wire dqs_po_en_stg2_f;
  wire dqs_po_en_stg2_f_reg;
  wire dqs_po_stg2_f_incdec;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_0 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_24 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_25 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_26 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_27 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_33 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_60 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_63 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_67 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_69 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_7 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_70 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_71 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_74 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_75 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_8 ;
  wire early1_data;
  wire early2_data;
  wire \entry_cnt_reg[3] ;
  wire \entry_cnt_reg[3]_0 ;
  wire fine_adjust_done;
  wire fine_dly_dec_done_r1_reg;
  wire first_rdlvl_pat_r;
  wire first_wrcal_pat_r;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  wire [2:0]\gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2] ;
  wire idelay_ce;
  wire idelay_ce_int;
  wire idelay_ce_r1;
  wire idelay_inc;
  wire idelay_inc_int;
  wire idelay_inc_r1;
  wire idelay_ld_rst;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_6;
  wire idelay_ld_rst_7;
  wire idelay_ld_rst_8;
  wire \idelay_tap_cnt_r_reg[0][7][3] ;
  wire idelay_tap_limit_r_reg;
  (* MAX_FANOUT = "0'b" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete;
  wire init_calib_complete_reg_rep__10_n_0;
  wire init_calib_complete_reg_rep__13_n_0;
  wire init_calib_complete_reg_rep__16_n_0;
  wire init_calib_complete_reg_rep__17_n_0;
  wire init_calib_complete_reg_rep__18_n_0;
  wire [15:0]init_calib_complete_reg_rep__28_0;
  wire init_complete_r_timing;
  wire init_complete_r_timing_reg;
  wire maint_prescaler_r1;
  wire maint_ref_zq_wip_r_reg;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_13 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_14 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_15 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_19 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_6 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_9 ;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire mc_wrdata_en;
  wire mem_init_done_r;
  wire [43:0]mem_out;
  wire mux_reset_n;
  wire [207:0]mux_wrdata;
  wire [31:0]mux_wrdata_mask;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_10 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[1]_3 ;
  wire \my_empty_reg[1]_4 ;
  wire \my_empty_reg[1]_5 ;
  wire \my_empty_reg[1]_6 ;
  wire \my_empty_reg[1]_7 ;
  wire \my_empty_reg[1]_8 ;
  wire \my_empty_reg[1]_9 ;
  wire \my_empty_reg[3] ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[3]_1 ;
  wire \my_empty_reg[5] ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg[5]_1 ;
  wire \my_empty_reg[6] ;
  wire \my_empty_reg[6]_0 ;
  wire [3:0]\my_empty_reg[6]_1 ;
  wire [3:0]\my_empty_reg[6]_2 ;
  wire [3:0]\my_empty_reg[6]_3 ;
  wire [3:0]\my_empty_reg[6]_4 ;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg[7]_1 ;
  wire \my_empty_reg[7]_10 ;
  wire \my_empty_reg[7]_11 ;
  wire \my_empty_reg[7]_12 ;
  wire \my_empty_reg[7]_13 ;
  wire \my_empty_reg[7]_14 ;
  wire \my_empty_reg[7]_15 ;
  wire [207:0]\my_empty_reg[7]_16 ;
  wire [31:0]\my_empty_reg[7]_17 ;
  wire [5:0]\my_empty_reg[7]_18 ;
  wire [5:0]\my_empty_reg[7]_19 ;
  wire \my_empty_reg[7]_2 ;
  wire [4:0]\my_empty_reg[7]_20 ;
  wire [4:0]\my_empty_reg[7]_21 ;
  wire [5:0]\my_empty_reg[7]_22 ;
  wire [5:0]\my_empty_reg[7]_23 ;
  wire [4:0]\my_empty_reg[7]_24 ;
  wire [4:0]\my_empty_reg[7]_25 ;
  wire [5:0]\my_empty_reg[7]_26 ;
  wire [5:0]\my_empty_reg[7]_27 ;
  wire [4:0]\my_empty_reg[7]_28 ;
  wire [4:0]\my_empty_reg[7]_29 ;
  wire \my_empty_reg[7]_3 ;
  wire [5:0]\my_empty_reg[7]_30 ;
  wire [5:0]\my_empty_reg[7]_31 ;
  wire [4:0]\my_empty_reg[7]_32 ;
  wire [4:0]\my_empty_reg[7]_33 ;
  wire [5:0]\my_empty_reg[7]_34 ;
  wire [5:0]\my_empty_reg[7]_35 ;
  wire [4:0]\my_empty_reg[7]_36 ;
  wire [4:0]\my_empty_reg[7]_37 ;
  wire [5:0]\my_empty_reg[7]_38 ;
  wire [5:0]\my_empty_reg[7]_39 ;
  wire \my_empty_reg[7]_4 ;
  wire [4:0]\my_empty_reg[7]_40 ;
  wire [4:0]\my_empty_reg[7]_41 ;
  wire [5:0]\my_empty_reg[7]_42 ;
  wire [5:0]\my_empty_reg[7]_43 ;
  wire [4:0]\my_empty_reg[7]_44 ;
  wire [4:0]\my_empty_reg[7]_45 ;
  wire [5:0]\my_empty_reg[7]_46 ;
  wire [5:0]\my_empty_reg[7]_47 ;
  wire [4:0]\my_empty_reg[7]_48 ;
  wire [4:0]\my_empty_reg[7]_49 ;
  wire \my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_50 ;
  wire [7:0]\my_empty_reg[7]_51 ;
  wire [7:0]\my_empty_reg[7]_52 ;
  wire [7:0]\my_empty_reg[7]_53 ;
  wire [7:0]\my_empty_reg[7]_54 ;
  wire [7:0]\my_empty_reg[7]_55 ;
  wire [7:0]\my_empty_reg[7]_56 ;
  wire [7:0]\my_empty_reg[7]_57 ;
  wire [7:0]\my_empty_reg[7]_58 ;
  wire [7:0]\my_empty_reg[7]_59 ;
  wire \my_empty_reg[7]_6 ;
  wire [7:0]\my_empty_reg[7]_60 ;
  wire [7:0]\my_empty_reg[7]_61 ;
  wire [7:0]\my_empty_reg[7]_62 ;
  wire [7:0]\my_empty_reg[7]_63 ;
  wire [7:0]\my_empty_reg[7]_64 ;
  wire [7:0]\my_empty_reg[7]_65 ;
  wire [7:0]\my_empty_reg[7]_66 ;
  wire [7:0]\my_empty_reg[7]_67 ;
  wire [7:0]\my_empty_reg[7]_68 ;
  wire [7:0]\my_empty_reg[7]_69 ;
  wire \my_empty_reg[7]_7 ;
  wire [7:0]\my_empty_reg[7]_70 ;
  wire [7:0]\my_empty_reg[7]_71 ;
  wire [7:0]\my_empty_reg[7]_72 ;
  wire [7:0]\my_empty_reg[7]_73 ;
  wire [7:0]\my_empty_reg[7]_74 ;
  wire [7:0]\my_empty_reg[7]_75 ;
  wire [7:0]\my_empty_reg[7]_76 ;
  wire \my_empty_reg[7]_8 ;
  wire \my_empty_reg[7]_9 ;
  wire \my_full_reg[4] ;
  wire \my_full_reg[4]_0 ;
  wire ofifo_rst0;
  wire [3:3]p_0_in;
  wire p_0_out;
  wire phaser_out_i_4__2_n_0;
  wire phaser_out_i_4__3_n_0;
  wire phaser_out_i_4__4_n_0;
  wire phaser_out_i_4__5_n_0;
  wire phy_cmd_wr_en;
  wire phy_ctl_ready;
  wire [10:0]\phy_ctl_wd_i1_reg[24] ;
  wire phy_ctl_wr_i1_reg;
  wire phy_data_wr_en;
  wire [21:0]phy_dout;
  wire phy_if_reset;
  wire phy_if_reset0;
  wire phy_if_reset_w;
  wire phy_rddata_en;
  wire pi_calib_done;
  wire \pi_counter_read_val_reg[0] ;
  wire \pi_counter_read_val_reg[0]_0 ;
  wire \pi_counter_read_val_reg[1] ;
  wire \pi_counter_read_val_reg[1]_0 ;
  wire \pi_counter_read_val_reg[2] ;
  wire \pi_counter_read_val_reg[2]_0 ;
  wire \pi_counter_read_val_reg[3] ;
  wire \pi_counter_read_val_reg[4] ;
  wire \pi_counter_read_val_reg[4]_0 ;
  wire \pi_counter_read_val_reg[5] ;
  wire pi_dqs_found_done_r1;
  wire [7:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[1] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[4] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[4]_0 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire pi_dqs_found_rank_done;
  wire pi_fine_dly_dec_done;
  wire po_ck_addr_cmd_delay_done;
  wire \po_counter_read_val_reg[0] ;
  wire \po_counter_read_val_reg[1] ;
  wire \po_counter_read_val_reg[2] ;
  wire \po_counter_read_val_reg[3] ;
  wire \po_counter_read_val_reg[4] ;
  wire \po_counter_read_val_reg[5] ;
  wire \po_counter_read_val_reg[6] ;
  wire \po_counter_read_val_reg[7] ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire [3:3]po_stg2_wrcal_cnt;
  wire \po_stg2_wrcal_cnt_reg[0] ;
  wire \po_stg2_wrcal_cnt_reg[0]_0 ;
  wire \po_stg2_wrcal_cnt_reg[0]_1 ;
  wire \po_stg2_wrcal_cnt_reg[0]_10 ;
  wire \po_stg2_wrcal_cnt_reg[0]_11 ;
  wire \po_stg2_wrcal_cnt_reg[0]_12 ;
  wire \po_stg2_wrcal_cnt_reg[0]_13 ;
  wire \po_stg2_wrcal_cnt_reg[0]_14 ;
  wire \po_stg2_wrcal_cnt_reg[0]_15 ;
  wire \po_stg2_wrcal_cnt_reg[0]_16 ;
  wire \po_stg2_wrcal_cnt_reg[0]_17 ;
  wire \po_stg2_wrcal_cnt_reg[0]_18 ;
  wire \po_stg2_wrcal_cnt_reg[0]_19 ;
  wire \po_stg2_wrcal_cnt_reg[0]_2 ;
  wire \po_stg2_wrcal_cnt_reg[0]_20 ;
  wire \po_stg2_wrcal_cnt_reg[0]_21 ;
  wire \po_stg2_wrcal_cnt_reg[0]_22 ;
  wire \po_stg2_wrcal_cnt_reg[0]_23 ;
  wire \po_stg2_wrcal_cnt_reg[0]_24 ;
  wire \po_stg2_wrcal_cnt_reg[0]_25 ;
  wire \po_stg2_wrcal_cnt_reg[0]_26 ;
  wire \po_stg2_wrcal_cnt_reg[0]_27 ;
  wire \po_stg2_wrcal_cnt_reg[0]_28 ;
  wire \po_stg2_wrcal_cnt_reg[0]_29 ;
  wire \po_stg2_wrcal_cnt_reg[0]_3 ;
  wire \po_stg2_wrcal_cnt_reg[0]_30 ;
  wire \po_stg2_wrcal_cnt_reg[0]_31 ;
  wire \po_stg2_wrcal_cnt_reg[0]_32 ;
  wire \po_stg2_wrcal_cnt_reg[0]_33 ;
  wire \po_stg2_wrcal_cnt_reg[0]_34 ;
  wire \po_stg2_wrcal_cnt_reg[0]_35 ;
  wire \po_stg2_wrcal_cnt_reg[0]_36 ;
  wire \po_stg2_wrcal_cnt_reg[0]_37 ;
  wire \po_stg2_wrcal_cnt_reg[0]_38 ;
  wire \po_stg2_wrcal_cnt_reg[0]_39 ;
  wire \po_stg2_wrcal_cnt_reg[0]_4 ;
  wire \po_stg2_wrcal_cnt_reg[0]_40 ;
  wire \po_stg2_wrcal_cnt_reg[0]_41 ;
  wire \po_stg2_wrcal_cnt_reg[0]_42 ;
  wire \po_stg2_wrcal_cnt_reg[0]_43 ;
  wire \po_stg2_wrcal_cnt_reg[0]_44 ;
  wire \po_stg2_wrcal_cnt_reg[0]_45 ;
  wire \po_stg2_wrcal_cnt_reg[0]_46 ;
  wire \po_stg2_wrcal_cnt_reg[0]_47 ;
  wire \po_stg2_wrcal_cnt_reg[0]_48 ;
  wire \po_stg2_wrcal_cnt_reg[0]_49 ;
  wire \po_stg2_wrcal_cnt_reg[0]_5 ;
  wire \po_stg2_wrcal_cnt_reg[0]_50 ;
  wire \po_stg2_wrcal_cnt_reg[0]_51 ;
  wire \po_stg2_wrcal_cnt_reg[0]_52 ;
  wire \po_stg2_wrcal_cnt_reg[0]_53 ;
  wire \po_stg2_wrcal_cnt_reg[0]_54 ;
  wire \po_stg2_wrcal_cnt_reg[0]_55 ;
  wire \po_stg2_wrcal_cnt_reg[0]_56 ;
  wire \po_stg2_wrcal_cnt_reg[0]_57 ;
  wire \po_stg2_wrcal_cnt_reg[0]_58 ;
  wire \po_stg2_wrcal_cnt_reg[0]_59 ;
  wire \po_stg2_wrcal_cnt_reg[0]_6 ;
  wire \po_stg2_wrcal_cnt_reg[0]_60 ;
  wire \po_stg2_wrcal_cnt_reg[0]_61 ;
  wire \po_stg2_wrcal_cnt_reg[0]_7 ;
  wire \po_stg2_wrcal_cnt_reg[0]_8 ;
  wire \po_stg2_wrcal_cnt_reg[0]_9 ;
  wire prbs_last_byte_done_r;
  wire prech_done;
  wire prech_req;
  wire rd_active_r;
  wire rd_data_offset_cal_done;
  wire [3:3]rd_data_offset_ranks_0;
  wire [3:3]rd_data_offset_ranks_1;
  wire [3:3]rd_data_offset_ranks_2;
  wire \rd_mux_sel_r_reg[0] ;
  wire \rd_mux_sel_r_reg[0]_0 ;
  wire \rd_mux_sel_r_reg[0]_1 ;
  wire \rd_mux_sel_r_reg[0]_10 ;
  wire \rd_mux_sel_r_reg[0]_11 ;
  wire \rd_mux_sel_r_reg[0]_12 ;
  wire \rd_mux_sel_r_reg[0]_13 ;
  wire \rd_mux_sel_r_reg[0]_14 ;
  wire \rd_mux_sel_r_reg[0]_15 ;
  wire \rd_mux_sel_r_reg[0]_16 ;
  wire \rd_mux_sel_r_reg[0]_17 ;
  wire \rd_mux_sel_r_reg[0]_18 ;
  wire \rd_mux_sel_r_reg[0]_19 ;
  wire \rd_mux_sel_r_reg[0]_2 ;
  wire \rd_mux_sel_r_reg[0]_20 ;
  wire \rd_mux_sel_r_reg[0]_21 ;
  wire \rd_mux_sel_r_reg[0]_22 ;
  wire \rd_mux_sel_r_reg[0]_23 ;
  wire \rd_mux_sel_r_reg[0]_24 ;
  wire \rd_mux_sel_r_reg[0]_25 ;
  wire \rd_mux_sel_r_reg[0]_26 ;
  wire \rd_mux_sel_r_reg[0]_27 ;
  wire \rd_mux_sel_r_reg[0]_28 ;
  wire \rd_mux_sel_r_reg[0]_29 ;
  wire \rd_mux_sel_r_reg[0]_3 ;
  wire \rd_mux_sel_r_reg[0]_30 ;
  wire \rd_mux_sel_r_reg[0]_31 ;
  wire \rd_mux_sel_r_reg[0]_32 ;
  wire \rd_mux_sel_r_reg[0]_33 ;
  wire \rd_mux_sel_r_reg[0]_34 ;
  wire \rd_mux_sel_r_reg[0]_35 ;
  wire \rd_mux_sel_r_reg[0]_36 ;
  wire \rd_mux_sel_r_reg[0]_37 ;
  wire \rd_mux_sel_r_reg[0]_38 ;
  wire \rd_mux_sel_r_reg[0]_39 ;
  wire \rd_mux_sel_r_reg[0]_4 ;
  wire \rd_mux_sel_r_reg[0]_40 ;
  wire \rd_mux_sel_r_reg[0]_41 ;
  wire \rd_mux_sel_r_reg[0]_42 ;
  wire \rd_mux_sel_r_reg[0]_43 ;
  wire \rd_mux_sel_r_reg[0]_44 ;
  wire \rd_mux_sel_r_reg[0]_45 ;
  wire \rd_mux_sel_r_reg[0]_46 ;
  wire \rd_mux_sel_r_reg[0]_47 ;
  wire \rd_mux_sel_r_reg[0]_48 ;
  wire \rd_mux_sel_r_reg[0]_49 ;
  wire \rd_mux_sel_r_reg[0]_5 ;
  wire \rd_mux_sel_r_reg[0]_50 ;
  wire \rd_mux_sel_r_reg[0]_51 ;
  wire \rd_mux_sel_r_reg[0]_52 ;
  wire \rd_mux_sel_r_reg[0]_53 ;
  wire \rd_mux_sel_r_reg[0]_54 ;
  wire \rd_mux_sel_r_reg[0]_55 ;
  wire \rd_mux_sel_r_reg[0]_56 ;
  wire \rd_mux_sel_r_reg[0]_57 ;
  wire \rd_mux_sel_r_reg[0]_58 ;
  wire \rd_mux_sel_r_reg[0]_59 ;
  wire \rd_mux_sel_r_reg[0]_6 ;
  wire \rd_mux_sel_r_reg[0]_60 ;
  wire \rd_mux_sel_r_reg[0]_61 ;
  wire \rd_mux_sel_r_reg[0]_62 ;
  wire \rd_mux_sel_r_reg[0]_7 ;
  wire \rd_mux_sel_r_reg[0]_8 ;
  wire \rd_mux_sel_r_reg[0]_9 ;
  wire [71:0]\rd_ptr_reg_rep[3] ;
  wire [16:0]\rd_ptr_reg_rep[3]_0 ;
  wire [46:0]\rd_ptr_reg_rep[3]_1 ;
  wire [43:0]\rd_ptr_reg_rep[3]_2 ;
  wire [43:0]\rd_ptr_reg_rep[3]_3 ;
  wire [43:0]\rd_ptr_reg_rep[3]_4 ;
  wire [71:0]\rd_ptr_reg_rep[3]_5 ;
  wire [71:0]\rd_ptr_reg_rep[3]_6 ;
  wire [71:0]\rd_ptr_reg_rep[3]_7 ;
  wire [2:0]\rdlvl_dqs_tap_cnt_r_reg[0][4][0] ;
  wire rdlvl_last_byte_done;
  wire rdlvl_prech_req;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_r_reg;
  wire read_calib;
  wire \read_fifo.tail_r_reg[1] ;
  wire refresh_bank_r;
  wire reset_if;
  wire reset_if_r8_reg_srl8_n_0;
  wire reset_if_r9;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire [1:0]rstdiv0_sync_r1_reg_rep__10;
  wire [0:0]rstdiv0_sync_r1_reg_rep__12;
  wire [0:0]rstdiv0_sync_r1_reg_rep__13;
  wire [0:0]rstdiv0_sync_r1_reg_rep__14;
  wire [0:0]rstdiv0_sync_r1_reg_rep__15;
  wire [0:0]rstdiv0_sync_r1_reg_rep__16;
  wire [0:0]rstdiv0_sync_r1_reg_rep__17;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire [0:0]rstdiv0_sync_r1_reg_rep__2;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__22;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__24_0;
  wire rstdiv0_sync_r1_reg_rep__24_1;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_5;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire rstdiv0_sync_r1_reg_rep__4;
  wire [0:0]rstdiv0_sync_r1_reg_rep__6;
  wire [1:0]rstdiv0_sync_r1_reg_rep__7;
  wire [0:0]rstdiv0_sync_r1_reg_rep__9;
  wire samp_edge_cnt0_en_r;
  wire sent_col;
  wire stg1_wr_done;
  wire tempmon_pi_f_dec;
  wire tempmon_pi_f_en_r;
  wire tempmon_pi_f_inc;
  wire tempmon_pi_f_inc_r;
  wire tempmon_sample_en;
  wire tempmon_sel_pi_incdec;
  wire u_ddr_phy_init_n_14;
  wire u_ddr_phy_init_n_22;
  wire u_ddr_phy_init_n_4;
  wire u_ddr_phy_init_n_887;
  wire u_ddr_phy_init_n_888;
  wire u_ddr_phy_init_n_906;
  wire u_ddr_phy_init_n_907;
  wire u_ddr_phy_init_n_908;
  wire u_ddr_phy_init_n_909;
  wire u_ddr_phy_rdlvl_n_22;
  wire u_ddr_phy_rdlvl_n_23;
  wire u_ddr_phy_rdlvl_n_25;
  wire u_ddr_phy_rdlvl_n_26;
  wire u_ddr_phy_rdlvl_n_30;
  wire u_ddr_phy_rdlvl_n_31;
  wire u_ddr_phy_rdlvl_n_32;
  wire u_ddr_phy_rdlvl_n_33;
  wire u_ddr_phy_rdlvl_n_34;
  wire u_ddr_phy_rdlvl_n_35;
  wire u_ddr_phy_rdlvl_n_36;
  wire u_ddr_phy_rdlvl_n_37;
  wire u_ddr_phy_rdlvl_n_38;
  wire u_ddr_phy_rdlvl_n_39;
  wire u_ddr_phy_rdlvl_n_40;
  wire u_ddr_phy_rdlvl_n_41;
  wire u_ddr_phy_rdlvl_n_66;
  wire u_ddr_phy_rdlvl_n_67;
  wire u_ddr_phy_rdlvl_n_68;
  wire u_ddr_phy_rdlvl_n_69;
  wire u_ddr_phy_rdlvl_n_7;
  wire u_ddr_phy_rdlvl_n_70;
  wire u_ddr_phy_rdlvl_n_71;
  wire u_ddr_phy_wrcal_n_13;
  wire u_ddr_phy_wrcal_n_14;
  wire u_ddr_phy_wrcal_n_15;
  wire u_ddr_phy_wrcal_n_16;
  wire u_ddr_phy_wrcal_n_21;
  wire u_ddr_phy_wrcal_n_22;
  wire u_ddr_phy_wrcal_n_24;
  wire u_ddr_phy_wrcal_n_25;
  wire u_ddr_phy_wrcal_n_26;
  wire u_ddr_phy_wrcal_n_27;
  wire u_ddr_phy_wrcal_n_29;
  wire u_ddr_phy_wrcal_n_30;
  wire u_ddr_phy_wrcal_n_31;
  wire u_ddr_phy_wrcal_n_32;
  wire u_ddr_phy_wrcal_n_33;
  wire u_ddr_phy_wrcal_n_34;
  wire u_ddr_phy_wrcal_n_35;
  wire u_ddr_phy_wrcal_n_36;
  wire u_ddr_phy_wrcal_n_41;
  wire u_ddr_phy_wrcal_n_42;
  wire u_ddr_phy_wrcal_n_43;
  wire u_ddr_phy_wrcal_n_44;
  wire wl_sm_start;
  wire wr_en;
  wire wr_en_0;
  wire wr_en_1;
  wire wr_level_done0;
  wire wr_level_done_r5;
  wire [0:0]\wr_ptr_reg[2] ;
  wire [0:0]\wr_ptr_reg[2]_0 ;
  wire \wr_ptr_timing_reg[0] ;
  wire [4:0]\wr_ptr_timing_reg[0]_0 ;
  wire [44:0]\wr_ptr_timing_reg[0]_1 ;
  wire [3:0]\wr_ptr_timing_reg[0]_10 ;
  wire [3:0]\wr_ptr_timing_reg[0]_11 ;
  wire [3:0]\wr_ptr_timing_reg[0]_12 ;
  wire [3:0]\wr_ptr_timing_reg[0]_13 ;
  wire [2:0]\wr_ptr_timing_reg[0]_14 ;
  wire [2:0]\wr_ptr_timing_reg[0]_2 ;
  wire [5:0]\wr_ptr_timing_reg[0]_3 ;
  wire [3:0]\wr_ptr_timing_reg[0]_4 ;
  wire [3:0]\wr_ptr_timing_reg[0]_5 ;
  wire [3:0]\wr_ptr_timing_reg[0]_6 ;
  wire [3:0]\wr_ptr_timing_reg[0]_7 ;
  wire [7:0]\wr_ptr_timing_reg[0]_8 ;
  wire [7:0]\wr_ptr_timing_reg[0]_9 ;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire wrcal_sanity_chk_done;
  wire wrcal_sanity_chk_r;
  wire [527:0]\write_buffer.wr_buf_out_data_reg[575] ;
  wire write_calib;
  wire wrlvl_byte_done;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_r;
  wire wrlvl_done_r1;
  wire wrlvl_final_if_rst;
  wire wrlvl_rank_done;

  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT4 #(
    .INIT(16'hFFF4)) 
    \calib_sel[0]_i_2 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ),
        .O(\calib_sel[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT4 #(
    .INIT(16'hFFF4)) 
    \calib_sel[1]_i_2 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ),
        .O(\calib_sel[1]_i_2_n_0 ));
  FDRE \calib_sel_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_9),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \calib_sel_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_70 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \calib_sel_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_8),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \calib_sel_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_69 ),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \calib_zero_inputs_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_4),
        .Q(calib_zero_inputs[0]),
        .R(1'b0));
  FDRE \calib_zero_inputs_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_3),
        .Q(calib_zero_inputs[1]),
        .R(1'b0));
  FDRE \calib_zero_inputs_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_2),
        .Q(calib_zero_inputs[2]),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_phy_tempmon ddr_phy_tempmon_0
       (.CLK(CLK),
        .D({ddr_phy_tempmon_0_n_2,ddr_phy_tempmon_0_n_3,ddr_phy_tempmon_0_n_4}),
        .E(ddr_phy_tempmon_0_n_7),
        .Q({\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] }),
        .calib_complete(calib_complete),
        .\calib_sel_reg[3] ({ddr_phy_tempmon_0_n_8,ddr_phy_tempmon_0_n_9}),
        .\calib_zero_inputs_reg[0] (ddr_phy_tempmon_0_n_5),
        .delay_done_r4_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_71 ),
        .\device_temp_r_reg[11] (\device_temp_r_reg[11] ),
        .dqs_po_dec_done(dqs_po_dec_done),
        .dqs_po_dec_done_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_8 ),
        .fine_adjust_done(fine_adjust_done),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (tempmon_pi_f_dec),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1] (\calib_sel[0]_i_2_n_0 ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (calib_in_common),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[0] (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2] (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2] ),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .pi_fine_dly_dec_done_reg(u_ddr_phy_rdlvl_n_71),
        .\pi_rst_stg1_cal_reg[0] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61 ),
        .\pi_rst_stg1_cal_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_7 ),
        .po_ck_addr_cmd_delay_done(po_ck_addr_cmd_delay_done),
        .rd_data_offset_cal_done(rd_data_offset_cal_done),
        .rdlvl_stg1_done_reg(u_ddr_phy_rdlvl_n_7),
        .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),
        .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),
        .rstdiv0_sync_r1_reg_rep__15(rstdiv0_sync_r1_reg_rep__15),
        .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),
        .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24_1),
        .tempmon_pi_f_inc_r_reg(tempmon_pi_f_inc),
        .tempmon_sample_en(tempmon_sample_en),
        .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_6 ),
        .wrcal_done_reg(u_ddr_phy_wrcal_n_14));
  mig_7series_0_mig_7series_v2_3_ddr_phy_dqs_found_cal_hr \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr 
       (.A_pi_rst_dqs_find110_out(A_pi_rst_dqs_find110_out),
        .A_pi_rst_dqs_find155_out(A_pi_rst_dqs_find155_out),
        .A_pi_rst_dqs_find81_out(A_pi_rst_dqs_find81_out),
        .A_po_fine_inc100_out(A_po_fine_inc100_out),
        .A_po_fine_inc145_out(A_po_fine_inc145_out),
        .A_po_fine_inc71_out(A_po_fine_inc71_out),
        .A_rst_primitives(A_rst_primitives),
        .B_pi_rst_dqs_find29_out(B_pi_rst_dqs_find29_out),
        .B_pi_rst_dqs_find32_out(B_pi_rst_dqs_find32_out),
        .B_po_fine_inc19_out(B_po_fine_inc19_out),
        .B_po_fine_inc22_out(B_po_fine_inc22_out),
        .B_po_fine_inc30_out(B_po_fine_inc30_out),
        .CLK(CLK),
        .C_pi_rst_dqs_find55_out(C_pi_rst_dqs_find55_out),
        .C_pi_rst_dqs_find58_out(C_pi_rst_dqs_find58_out),
        .C_po_fine_inc45_out(C_po_fine_inc45_out),
        .C_po_fine_inc48_out(C_po_fine_inc48_out),
        .C_po_fine_inc69_out(C_po_fine_inc69_out),
        .D({\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_69 ,\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_70 }),
        .D_pi_rst_dqs_find84_out(D_pi_rst_dqs_find84_out),
        .D_po_fine_inc108_out(D_po_fine_inc108_out),
        .D_po_fine_inc74_out(D_po_fine_inc74_out),
        .Q(rd_data_offset_ranks_0),
        .SR(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_67 ),
        .\calib_data_offset_0_reg[0] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_26 ),
        .\calib_data_offset_0_reg[1] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_25 ),
        .\calib_data_offset_0_reg[2] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_24 ),
        .\calib_data_offset_0_reg[4] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23 ),
        .\calib_data_offset_0_reg[5] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_0 ),
        .\calib_data_offset_0_reg[5]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21 ),
        .\calib_data_offset_1_reg[0] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_33 ),
        .\calib_data_offset_1_reg[1] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32 ),
        .\calib_data_offset_1_reg[2] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31 ),
        .\calib_data_offset_1_reg[3] (rd_data_offset_ranks_1),
        .\calib_data_offset_1_reg[4] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30 ),
        .\calib_data_offset_1_reg[5] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_27 ),
        .\calib_data_offset_2_reg[0] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39 ),
        .\calib_data_offset_2_reg[1] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38 ),
        .\calib_data_offset_2_reg[2] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37 ),
        .\calib_data_offset_2_reg[3] (rd_data_offset_ranks_2),
        .\calib_data_offset_2_reg[4] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36 ),
        .\calib_data_offset_2_reg[5] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34 ),
        .\calib_sel_reg[1] (Q[1:0]),
        .\calib_zero_inputs_reg[2] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_7 ),
        .\calib_zero_inputs_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_71 ),
        .\calib_zero_inputs_reg[2]_1 (calib_zero_inputs),
        .ck_po_stg2_f_en(ck_po_stg2_f_en),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[1] (\cmd_pipe_plus.mc_data_offset_2_reg[1] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[2] (\cmd_pipe_plus.mc_data_offset_2_reg[2] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[3] (\cmd_pipe_plus.mc_data_offset_2_reg[3] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[4] (\cmd_pipe_plus.mc_data_offset_2_reg[4] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (\cmd_pipe_plus.mc_data_offset_2_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1] ),
        .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2] ),
        .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4] ),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ),
        .col_rd_wr(col_rd_wr),
        .ctl_lane_cnt(ctl_lane_cnt),
        .detect_pi_found_dqs(detect_pi_found_dqs),
        .dqs_found_prech_req(dqs_found_prech_req),
        .dqs_po_dec_done(dqs_po_dec_done),
        .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),
        .fine_adjust_done(fine_adjust_done),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 (\calib_sel[1]_i_2_n_0 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[3] ({\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] }),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (calib_in_common),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[0] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_63 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[1] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_8 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_60 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2]_2 (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2] ),
        .ofifo_rst0(ofifo_rst0),
        .pi_calib_done(pi_calib_done),
        .pi_calib_done_r1_reg(u_ddr_phy_init_n_887),
        .pi_dqs_found_done(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72 ),
        .pi_dqs_found_done_r1(pi_dqs_found_done_r1),
        .pi_dqs_found_lanes(pi_dqs_found_lanes),
        .pi_dqs_found_rank_done(pi_dqs_found_rank_done),
        .pi_dqs_found_start_reg(u_ddr_phy_init_n_908),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .pi_fine_dly_dec_done_reg(u_ddr_phy_rdlvl_n_71),
        .po_ck_addr_cmd_delay_done(po_ck_addr_cmd_delay_done),
        .prech_done(prech_done),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_74 ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 (p_0_in),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_75 ),
        .rd_data_offset_cal_done(rd_data_offset_cal_done),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__10[0]),
        .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),
        .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__24(ddr_phy_tempmon_0_n_5),
        .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_1),
        .sent_col(sent_col));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[0] 
       (.C(CLK),
        .CE(ddr_phy_tempmon_0_n_7),
        .D(u_ddr_phy_wrcal_n_44),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_67 ));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[1] 
       (.C(CLK),
        .CE(ddr_phy_tempmon_0_n_7),
        .D(u_ddr_phy_wrcal_n_43),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_67 ));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[2] 
       (.C(CLK),
        .CE(ddr_phy_tempmon_0_n_7),
        .D(u_ddr_phy_wrcal_n_42),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_67 ));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[3] 
       (.C(CLK),
        .CE(ddr_phy_tempmon_0_n_7),
        .D(u_ddr_phy_wrcal_n_41),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_67 ));
  FDRE \gen_byte_sel_div2.calib_in_common_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r1_reg_rep__24),
        .Q(calib_in_common),
        .R(1'b0));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_63 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_60 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE idelay_ce_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ce_int),
        .Q(idelay_ce_r1),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE idelay_ce_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ce_r1),
        .Q(idelay_ce),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE idelay_inc_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_inc_int),
        .Q(idelay_inc_r1),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE idelay_inc_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_inc_r1),
        .Q(idelay_inc),
        .R(rstdiv0_sync_r1_reg_rep__3));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(app_zq_r_reg),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__0
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[6] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__1
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[1] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__10
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__10_n_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__11
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_5 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__12
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_6 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__13
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__13_n_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__14
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\data_offset_2_i1_reg[3] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__15
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\data_offset_2_i1_reg[2] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__16
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__16_n_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__17
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__17_n_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__18
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__18_n_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__19
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_7 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__2
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[6]_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__20
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_8 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__21
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_9 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__22
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_10 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__23
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_11 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__24
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_12 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__25
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_13 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__26
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_14 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__27
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_15 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__28
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(phy_dout[15]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__3
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__4
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__5
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_1 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__6
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_2 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__7
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_3 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__8
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\wr_ptr_timing_reg[0] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__9
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(\my_empty_reg[7]_4 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1 
       (.I0(calib_zero_inputs[1]),
        .I1(idelay_ce),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(calib_in_common),
        .O(A_idelay_ce19_out));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1__0 
       (.I0(calib_zero_inputs[0]),
        .I1(idelay_ce),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(calib_in_common),
        .O(A_idelay_ce13_out));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1__1 
       (.I0(calib_zero_inputs[2]),
        .I1(idelay_ce),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(calib_in_common),
        .O(A_idelay_ce10_out));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1 
       (.I0(calib_zero_inputs[0]),
        .I1(idelay_ce),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(calib_in_common),
        .O(D_idelay_ce1_out));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__0 
       (.I0(calib_zero_inputs[0]),
        .I1(idelay_ce),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(calib_in_common),
        .O(B_idelay_ce9_out));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__1 
       (.I0(calib_zero_inputs[0]),
        .I1(idelay_ce),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(calib_in_common),
        .O(C_idelay_ce5_out));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__2 
       (.I0(calib_zero_inputs[2]),
        .I1(idelay_ce),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(calib_in_common),
        .O(B_idelay_ce6_out));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__3 
       (.I0(calib_zero_inputs[2]),
        .I1(idelay_ce),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(calib_in_common),
        .O(C_idelay_ce2_out));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT2 #(
    .INIT(4'h2)) 
    maint_ref_zq_wip_r_i_2
       (.I0(app_zq_r_reg),
        .I1(refresh_bank_r),
        .O(maint_ref_zq_wip_r_reg));
  mig_7series_0_mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay 
       (.A_po_fine_enable141_out(A_po_fine_enable141_out),
        .A_po_fine_enable67_out(A_po_fine_enable67_out),
        .A_po_fine_enable96_out(A_po_fine_enable96_out),
        .B_po_fine_enable15_out(B_po_fine_enable15_out),
        .B_po_fine_enable18_out(B_po_fine_enable18_out),
        .CLK(CLK),
        .C_po_fine_enable41_out(C_po_fine_enable41_out),
        .C_po_fine_enable44_out(C_po_fine_enable44_out),
        .D_po_fine_enable70_out(D_po_fine_enable70_out),
        .Q(calib_zero_inputs),
        .ck_po_stg2_f_en(ck_po_stg2_f_en),
        .ctl_lane_cnt(ctl_lane_cnt),
        .dqs_po_dec_done(dqs_po_dec_done),
        .dqs_po_dec_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_14 ),
        .dqs_po_en_stg2_f(dqs_po_en_stg2_f),
        .\gen_byte_sel_div2.calib_in_common_reg (phaser_out_i_4__3_n_0),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (phaser_out_i_4__2_n_0),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (phaser_out_i_4__4_n_0),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (phaser_out_i_4__5_n_0),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .pi_fine_dly_dec_done_reg(u_ddr_phy_rdlvl_n_71),
        .po_ck_addr_cmd_delay_done(po_ck_addr_cmd_delay_done),
        .po_en_stg2_f(cmd_po_en_stg2_f),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24_1),
        .rstdiv0_sync_r1_reg_rep__3(rstdiv0_sync_r1_reg_rep__3));
  mig_7series_0_mig_7series_v2_3_ddr_phy_wrlvl \mb_wrlvl_inst.u_ddr_phy_wrlvl 
       (.A_po_coarse_enable143_out(A_po_coarse_enable143_out),
        .A_po_coarse_enable69_out(A_po_coarse_enable69_out),
        .A_po_coarse_enable98_out(A_po_coarse_enable98_out),
        .B_po_coarse_enable17_out(B_po_coarse_enable17_out),
        .B_po_coarse_enable20_out(B_po_coarse_enable20_out),
        .B_po_coarse_enable27_out(B_po_coarse_enable27_out),
        .B_po_fine_enable24_out(B_po_fine_enable24_out),
        .CLK(CLK),
        .C_po_coarse_enable43_out(C_po_coarse_enable43_out),
        .C_po_coarse_enable46_out(C_po_coarse_enable46_out),
        .C_po_coarse_enable66_out(C_po_coarse_enable66_out),
        .C_po_fine_enable63_out(C_po_fine_enable63_out),
        .D_po_coarse_enable105_out(D_po_coarse_enable105_out),
        .D_po_coarse_enable72_out(D_po_coarse_enable72_out),
        .D_po_fine_enable102_out(D_po_fine_enable102_out),
        .Q({\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_9 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 }),
        .SR(SR),
        .SS(SS),
        .\calib_sel_reg[1] (Q[1:0]),
        .\calib_zero_inputs_reg[2] (calib_zero_inputs),
        .ck_po_stg2_f_en(ck_po_stg2_f_en),
        .cmd_po_en_stg2_f(cmd_po_en_stg2_f),
        .\corse_cnt_reg[2][0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17 ),
        .\corse_cnt_reg[3][0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_13 ),
        .\corse_dec_reg[2][0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16 ),
        .delay_dec_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_14 ),
        .done_dqs_tap_inc(done_dqs_tap_inc),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\dqs_count_r_reg[3]_0 (dqs_count_r),
        .dqs_po_dec_done(dqs_po_dec_done),
        .dqs_po_en_stg2_f(dqs_po_en_stg2_f),
        .dqs_po_en_stg2_f_reg_0(dqs_po_en_stg2_f_reg),
        .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),
        .early1_data(early1_data),
        .early2_data(early2_data),
        .\fine_inc_reg[6][0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (calib_in_common),
        .phy_ctl_ready(phy_ctl_ready),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .\po_counter_read_val_reg[0] (\po_counter_read_val_reg[0] ),
        .\po_counter_read_val_reg[1] (\po_counter_read_val_reg[1] ),
        .\po_counter_read_val_reg[2] (\po_counter_read_val_reg[2] ),
        .\po_counter_read_val_reg[3] (\po_counter_read_val_reg[3] ),
        .\po_counter_read_val_reg[4] (\po_counter_read_val_reg[4] ),
        .\po_counter_read_val_reg[5] (\po_counter_read_val_reg[5] ),
        .\po_counter_read_val_reg[6] (\po_counter_read_val_reg[6] ),
        .\po_counter_read_val_reg[7] (\po_counter_read_val_reg[7] ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_2 ),
        .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_35),
        .\po_stg2_wrcal_cnt_reg[0]_0 (u_ddr_phy_wrcal_n_25),
        .\po_stg2_wrcal_cnt_reg[0]_1 (u_ddr_phy_wrcal_n_32),
        .\po_stg2_wrcal_cnt_reg[0]_2 (u_ddr_phy_wrcal_n_34),
        .\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_33),
        .\po_stg2_wrcal_cnt_reg[2] (u_ddr_phy_wrcal_n_27),
        .\po_stg2_wrcal_cnt_reg[3] (u_ddr_phy_wrcal_n_16),
        .\po_stg2_wrcal_cnt_reg[3]_0 ({po_stg2_wrcal_cnt,\gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 }),
        .rdlvl_stg1_done_reg(u_ddr_phy_rdlvl_n_7),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24_1),
        .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),
        .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),
        .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),
        .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),
        .\smallest_reg[7][0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_15 ),
        .\wl_corse_cnt_reg[0][7][2]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18 ),
        .\wl_corse_cnt_reg[0][7][2]_1 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_19 ),
        .wl_sm_start(wl_sm_start),
        .wr_level_done0(wr_level_done0),
        .wr_level_done_r5(wr_level_done_r5),
        .wr_level_done_r5_reg_0(u_ddr_phy_wrcal_n_26),
        .wr_lvl_start_reg(u_ddr_phy_init_n_906),
        .wrcal_done_reg(u_ddr_phy_wrcal_n_14),
        .wrlvl_byte_done(wrlvl_byte_done),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_byte_redo_r(wrlvl_byte_redo_r),
        .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_30),
        .wrlvl_byte_redo_reg_0(u_ddr_phy_wrcal_n_29),
        .wrlvl_byte_redo_reg_1(u_ddr_phy_wrcal_n_31),
        .wrlvl_done_r_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_6 ),
        .wrlvl_rank_done(wrlvl_rank_done));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_2__0
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [111]),
        .O(\my_empty_reg[7]_16 [47]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_2__1
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [87]),
        .O(\my_empty_reg[7]_16 [23]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_2__2
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [79]),
        .O(mux_wrdata[47]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_5__0
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [102]),
        .O(\my_empty_reg[7]_16 [38]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_5__1
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [94]),
        .O(\my_empty_reg[7]_16 [30]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_5__4
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [70]),
        .O(mux_wrdata[38]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_5__5
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [62]),
        .O(mux_wrdata[30]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_5__6
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [54]),
        .O(mux_wrdata[22]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_18_23_i_4
       (.I0(\my_empty_reg[7]_8 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [277]),
        .O(\my_empty_reg[7]_16 [118]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_18_23_i_4__2
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [253]),
        .O(\my_empty_reg[7]_16 [100]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_18_23_i_4__3
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [246]),
        .O(mux_wrdata[118]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_6__0
       (.I0(\my_empty_reg[7]_8 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [269]),
        .O(\my_empty_reg[7]_16 [112]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_6__1
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [261]),
        .O(\my_empty_reg[7]_16 [106]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_6__4
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [240]),
        .O(mux_wrdata[112]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_6__5
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [234]),
        .O(mux_wrdata[106]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_6__6
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [228]),
        .O(mux_wrdata[100]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_1
       (.I0(init_calib_complete_reg_rep__16_n_0),
        .I1(mc_cas_n[1]),
        .O(phy_dout[13]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_1__1
       (.I0(init_calib_complete_reg_rep__16_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [460]),
        .O(\my_empty_reg[7]_16 [204]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_1__4
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [436]),
        .O(\my_empty_reg[7]_16 [180]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_1__5
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [428]),
        .O(mux_wrdata[204]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_2
       (.I0(init_calib_complete_reg_rep__16_n_0),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [11]),
        .O(phy_dout[12]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_3__0
       (.I0(\data_offset_2_i1_reg[2] ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [36]),
        .O(phy_dout[14]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_3__1
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [107]),
        .O(\my_empty_reg[7]_16 [43]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_3__4
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [83]),
        .O(\my_empty_reg[7]_16 [19]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_30_35_i_3__5
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [75]),
        .O(mux_wrdata[43]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_3__0
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [452]),
        .O(\my_empty_reg[7]_16 [196]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_3__1
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [444]),
        .O(\my_empty_reg[7]_16 [188]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_3__4
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [420]),
        .O(mux_wrdata[196]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_3__5
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [412]),
        .O(mux_wrdata[188]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_3__6
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [404]),
        .O(mux_wrdata[180]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [106]),
        .O(\my_empty_reg[7]_16 [42]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__0
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [91]),
        .O(\my_empty_reg[7]_16 [27]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__1
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [82]),
        .O(\my_empty_reg[7]_16 [18]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__2
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [74]),
        .O(mux_wrdata[42]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__3
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [59]),
        .O(mux_wrdata[27]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__4
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [51]),
        .O(mux_wrdata[19]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__5
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [478]),
        .O(\my_empty_reg[7]_17 [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__6
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [474]),
        .O(mux_wrdata_mask[6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_6__5
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [470]),
        .O(\my_empty_reg[7]_17 [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_6__6
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [466]),
        .O(mux_wrdata_mask[2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_1__8
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [494]),
        .O(\my_empty_reg[7]_17 [14]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_1__9
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [490]),
        .O(mux_wrdata_mask[14]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_2__8
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [486]),
        .O(\my_empty_reg[7]_17 [10]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_2__9
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [482]),
        .O(mux_wrdata_mask[10]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_3__1
       (.I0(init_calib_complete_reg_rep__16_n_0),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [13]),
        .O(phy_dout[20]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_3__8
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [510]),
        .O(\my_empty_reg[7]_17 [22]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_3__9
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [506]),
        .O(mux_wrdata_mask[22]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_4__0
       (.I0(\data_offset_2_i1_reg[2] ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [38]),
        .O(phy_dout[21]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_4__8
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [502]),
        .O(\my_empty_reg[7]_17 [18]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_4__9
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [498]),
        .O(mux_wrdata_mask[18]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_5__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [526]),
        .O(\my_empty_reg[7]_17 [30]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_5__7
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [522]),
        .O(mux_wrdata_mask[30]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_6__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [518]),
        .O(\my_empty_reg[7]_17 [26]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_6__7
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [514]),
        .O(mux_wrdata_mask[26]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_1__2
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [99]),
        .O(\my_empty_reg[7]_16 [35]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_1__3
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [90]),
        .O(\my_empty_reg[7]_16 [26]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_1__6
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [67]),
        .O(mux_wrdata[35]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_1__7
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [58]),
        .O(mux_wrdata[26]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_1__8
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [50]),
        .O(mux_wrdata[18]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_6__0
       (.I0(\my_empty_reg[7]_8 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [273]),
        .O(\my_empty_reg[7]_16 [115]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_6__3
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [249]),
        .O(\my_empty_reg[7]_16 [97]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_6__4
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [243]),
        .O(mux_wrdata[115]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_54_59_i_3__1
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [98]),
        .O(\my_empty_reg[7]_16 [34]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_54_59_i_3__5
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [66]),
        .O(mux_wrdata[34]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_2__2
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [257]),
        .O(\my_empty_reg[7]_16 [103]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_2__6
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [231]),
        .O(mux_wrdata[103]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_2__7
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [225]),
        .O(mux_wrdata[97]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_3
       (.I0(init_calib_complete_reg_rep__16_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [456]),
        .O(\my_empty_reg[7]_16 [200]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_3__2
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [432]),
        .O(\my_empty_reg[7]_16 [176]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_3__3
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [424]),
        .O(mux_wrdata[200]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_4
       (.I0(\my_empty_reg[7]_8 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [265]),
        .O(\my_empty_reg[7]_16 [109]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_4__1
       (.I0(\my_empty_reg[7]_9 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [237]),
        .O(mux_wrdata[109]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_5__0
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [440]),
        .O(\my_empty_reg[7]_16 [184]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_5__2
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [408]),
        .O(mux_wrdata[184]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_5__3
       (.I0(init_calib_complete_reg_rep__18_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [400]),
        .O(mux_wrdata[176]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__5
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [103]),
        .O(\my_empty_reg[7]_16 [39]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__6
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [95]),
        .O(\my_empty_reg[7]_16 [31]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__7
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [71]),
        .O(mux_wrdata[39]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__8
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [63]),
        .O(mux_wrdata[31]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__9
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [55]),
        .O(mux_wrdata[23]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__6
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [110]),
        .O(\my_empty_reg[7]_16 [46]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__7
       (.I0(\my_empty_reg[7]_12 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [86]),
        .O(\my_empty_reg[7]_16 [22]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__8
       (.I0(\my_empty_reg[7]_13 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [78]),
        .O(mux_wrdata[46]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_1__2
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [479]),
        .O(\my_empty_reg[7]_17 [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_1__3
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [477]),
        .O(\my_empty_reg[7]_17 [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_1__4
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [476]),
        .O(\my_empty_reg[7]_17 [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_1__5
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [475]),
        .O(mux_wrdata_mask[7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_1__6
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [473]),
        .O(mux_wrdata_mask[5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_1__7
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [472]),
        .O(mux_wrdata_mask[4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_2__2
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [471]),
        .O(\my_empty_reg[7]_17 [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_2__3
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [469]),
        .O(\my_empty_reg[7]_17 [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_2__4
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [468]),
        .O(\my_empty_reg[7]_17 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_2__5
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [467]),
        .O(mux_wrdata_mask[3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_2__6
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [465]),
        .O(mux_wrdata_mask[1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_2__7
       (.I0(phy_dout[15]),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [464]),
        .O(mux_wrdata_mask[0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_3__2
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [495]),
        .O(\my_empty_reg[7]_17 [15]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_3__3
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [493]),
        .O(\my_empty_reg[7]_17 [13]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_3__4
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [492]),
        .O(\my_empty_reg[7]_17 [12]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_3__5
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [491]),
        .O(mux_wrdata_mask[15]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_3__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [489]),
        .O(mux_wrdata_mask[13]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_3__7
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [488]),
        .O(mux_wrdata_mask[12]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_4__2
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [487]),
        .O(\my_empty_reg[7]_17 [11]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_4__3
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [485]),
        .O(\my_empty_reg[7]_17 [9]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_4__4
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [484]),
        .O(\my_empty_reg[7]_17 [8]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_4__5
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [483]),
        .O(mux_wrdata_mask[11]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_4__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [481]),
        .O(mux_wrdata_mask[9]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_4__7
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [480]),
        .O(mux_wrdata_mask[8]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_5__1
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [511]),
        .O(\my_empty_reg[7]_17 [23]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_5__2
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [509]),
        .O(\my_empty_reg[7]_17 [21]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_5__3
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [508]),
        .O(\my_empty_reg[7]_17 [20]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_5__4
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [507]),
        .O(mux_wrdata_mask[23]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_5__5
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [505]),
        .O(mux_wrdata_mask[21]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_5__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [504]),
        .O(mux_wrdata_mask[20]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_6__1
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [503]),
        .O(\my_empty_reg[7]_17 [19]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_6__2
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [501]),
        .O(\my_empty_reg[7]_17 [17]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_6__3
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [500]),
        .O(\my_empty_reg[7]_17 [16]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_6__4
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [499]),
        .O(mux_wrdata_mask[19]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_6__5
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [497]),
        .O(mux_wrdata_mask[17]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_6__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [496]),
        .O(mux_wrdata_mask[16]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [448]),
        .O(\my_empty_reg[7]_16 [192]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1__0
       (.I0(init_calib_complete_reg_rep__17_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [416]),
        .O(mux_wrdata[192]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1__1
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [527]),
        .O(\my_empty_reg[7]_17 [31]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1__2
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [525]),
        .O(\my_empty_reg[7]_17 [29]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1__3
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [524]),
        .O(\my_empty_reg[7]_17 [28]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1__4
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [523]),
        .O(mux_wrdata_mask[31]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1__5
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [521]),
        .O(mux_wrdata_mask[29]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [520]),
        .O(mux_wrdata_mask[28]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_2__1
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [519]),
        .O(\my_empty_reg[7]_17 [27]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_2__2
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [517]),
        .O(\my_empty_reg[7]_17 [25]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_2__3
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [516]),
        .O(\my_empty_reg[7]_17 [24]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_2__4
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [515]),
        .O(mux_wrdata_mask[27]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_2__5
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [513]),
        .O(mux_wrdata_mask[25]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_2__6
       (.I0(\my_empty_reg[7]_15 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [512]),
        .O(mux_wrdata_mask[24]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_12__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [327]),
        .I1(\my_empty_reg[7]_6 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [5]),
        .O(\my_empty_reg[7]_67 [5]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_12__8
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [319]),
        .I1(\data_offset_2_i1_reg[3] ),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [5]),
        .O(\my_empty_reg[7]_76 [5]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_13
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [254]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [12]),
        .O(D1[4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_13__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [278]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [12]),
        .O(\my_empty_reg[7]_57 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_14
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [198]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [11]),
        .O(D1[3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_14__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [222]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [11]),
        .O(\my_empty_reg[7]_57 [3]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16
       (.I0(\my_empty_reg[1] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [86]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [9]),
        .O(D1[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16__6
       (.I0(\my_empty_reg[7]_5 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [110]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [9]),
        .O(\my_empty_reg[7]_57 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [103]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [1]),
        .O(\my_empty_reg[7]_67 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16__8
       (.I0(\data_offset_2_i1_reg[3] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [95]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [1]),
        .O(\my_empty_reg[7]_76 [1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_17__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [39]),
        .I1(\my_empty_reg[7]_6 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [0]),
        .O(\my_empty_reg[7]_67 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_17__8
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [31]),
        .I1(\data_offset_2_i1_reg[3] ),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [0]),
        .O(\my_empty_reg[7]_76 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_21
       (.I0(\my_empty_reg[1] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [253]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [20]),
        .O(D2[4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_21__6
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [277]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [20]),
        .O(\my_empty_reg[7]_56 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_21__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [270]),
        .I1(\my_empty_reg[7]_6 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [12]),
        .O(\my_empty_reg[7]_66 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_21__8
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [262]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [12]),
        .O(\my_empty_reg[7]_75 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_22__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [214]),
        .I1(\my_empty_reg[7]_6 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [11]),
        .O(\my_empty_reg[7]_66 [3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_22__8
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [206]),
        .I1(\data_offset_2_i1_reg[3] ),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [11]),
        .O(\my_empty_reg[7]_75 [3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_23
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [141]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [18]),
        .O(D2[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_23__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [165]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [18]),
        .O(\my_empty_reg[7]_56 [2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_24__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [102]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [9]),
        .O(\my_empty_reg[7]_66 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_24__8
       (.I0(\data_offset_2_i1_reg[3] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [94]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [9]),
        .O(\my_empty_reg[7]_75 [1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_25__0
       (.I0(\cmd_pipe_plus.mc_we_n_reg[2] [2]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_0 [13]),
        .O(\wr_ptr_timing_reg[0]_3 [5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_26
       (.I0(\my_empty_reg[1] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [436]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [31]),
        .O(D3[7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_26__6
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [460]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [31]),
        .O(\my_empty_reg[7]_55 [7]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_27__0
       (.I0(\cmd_pipe_plus.mc_we_n_reg[2] [0]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_0 [11]),
        .O(\wr_ptr_timing_reg[0]_3 [3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_29__0
       (.I0(mc_ras_n[2]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_0 [10]),
        .O(\wr_ptr_timing_reg[0]_3 [2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_29__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [269]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [20]),
        .O(\my_empty_reg[7]_65 [4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_29__8
       (.I0(init_calib_complete_reg_rep__13_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [261]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [20]),
        .O(\my_empty_reg[7]_74 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_31__0
       (.I0(mc_cs_n),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_0 [8]),
        .O(\wr_ptr_timing_reg[0]_3 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_31__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [157]),
        .I1(\my_empty_reg[7]_6 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [18]),
        .O(\my_empty_reg[7]_65 [2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_31__8
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [149]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [18]),
        .O(\my_empty_reg[7]_74 [2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_33
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [20]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [24]),
        .O(D3[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_33__0
       (.I0(mc_cas_n[2]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_0 [16]),
        .O(\wr_ptr_timing_reg[0]_2 [2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_33__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [44]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [24]),
        .O(\my_empty_reg[7]_55 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_34__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [452]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [31]),
        .O(\my_empty_reg[7]_64 [7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_34__8
       (.I0(init_calib_complete_reg_rep__13_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [444]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [31]),
        .O(\my_empty_reg[7]_73 [7]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_35__0
       (.I0(mc_cas_n[0]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_0 [14]),
        .O(\wr_ptr_timing_reg[0]_2 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_36
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [307]),
        .I1(\my_empty_reg[6] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [37]),
        .O(D4[5]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_36__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [331]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [37]),
        .O(\my_empty_reg[7]_54 [5]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_4
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [311]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [5]),
        .O(D0[5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_40
       (.I0(\my_empty_reg[1] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [83]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [33]),
        .O(D4[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_40__6
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [107]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [33]),
        .O(\my_empty_reg[7]_54 [1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [19]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [32]),
        .O(D4[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [43]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [32]),
        .O(\my_empty_reg[7]_54 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [36]),
        .I1(\my_empty_reg[7]_6 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [24]),
        .O(\my_empty_reg[7]_64 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41__8
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [28]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [24]),
        .O(\my_empty_reg[7]_73 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_42__7
       (.I0(\my_empty_reg[7]_5 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [526]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [39]),
        .O(\my_empty_reg[7]_63 [7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_43__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [518]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [38]),
        .O(\my_empty_reg[7]_63 [6]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_44__6
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [510]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [37]),
        .O(\my_empty_reg[7]_63 [5]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_44__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [315]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [37]),
        .O(\my_empty_reg[7]_72 [5]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_45
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [250]),
        .I1(\my_empty_reg[6] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [44]),
        .O(D5[4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_45__5
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [274]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [44]),
        .O(\my_empty_reg[7]_53 [4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_45__6
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [502]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [36]),
        .O(\my_empty_reg[7]_63 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_46
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [194]),
        .I1(\my_empty_reg[6] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [43]),
        .O(D5[3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_46__5
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [218]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [43]),
        .O(\my_empty_reg[7]_53 [3]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_46__6
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [494]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [35]),
        .O(\my_empty_reg[7]_63 [3]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_47__6
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [486]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [34]),
        .O(\my_empty_reg[7]_63 [2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [82]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [41]),
        .O(D5[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48__5
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [106]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [41]),
        .O(\my_empty_reg[7]_53 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48__6
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [478]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [33]),
        .O(\my_empty_reg[7]_63 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48__7
       (.I0(init_calib_complete_reg_rep__13_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [91]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [33]),
        .O(\my_empty_reg[7]_72 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_49__6
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [470]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [32]),
        .O(\my_empty_reg[7]_63 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_49__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [27]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [32]),
        .O(\my_empty_reg[7]_72 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [335]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [5]),
        .O(\my_empty_reg[7]_58 [5]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_52__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [323]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [45]),
        .O(\my_empty_reg[7]_62 [5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_53
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [249]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [52]),
        .O(D6[4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_53__5
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [273]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [52]),
        .O(\my_empty_reg[7]_52 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_53__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [258]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [44]),
        .O(\my_empty_reg[7]_71 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_54__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [202]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [43]),
        .O(\my_empty_reg[7]_71 [3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_55
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [137]),
        .I1(\my_empty_reg[6] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [50]),
        .O(D6[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_55__5
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [161]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [50]),
        .O(\my_empty_reg[7]_52 [2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_56__6
       (.I0(\my_empty_reg[7]_5 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [99]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [41]),
        .O(\my_empty_reg[7]_62 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_56__7
       (.I0(init_calib_complete_reg_rep__13_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [90]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [41]),
        .O(\my_empty_reg[7]_71 [1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_57__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [35]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [40]),
        .O(\my_empty_reg[7]_62 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_58
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [432]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [63]),
        .O(D7[7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_58__5
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [456]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [63]),
        .O(\my_empty_reg[7]_51 [7]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_61__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [266]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [52]),
        .O(\my_empty_reg[7]_61 [4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_61__7
       (.I0(init_calib_complete_reg_rep__13_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [257]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [52]),
        .O(\my_empty_reg[7]_70 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_62__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [210]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [51]),
        .O(\my_empty_reg[7]_61 [3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_63__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [145]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [50]),
        .O(\my_empty_reg[7]_70 [2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_64__6
       (.I0(\my_empty_reg[7]_5 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [98]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [49]),
        .O(\my_empty_reg[7]_61 [1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_65
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [16]),
        .I1(\my_empty_reg[6] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [56]),
        .O(D7[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_65__5
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [40]),
        .I1(init_calib_complete_reg_rep__10_n_0),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [56]),
        .O(\my_empty_reg[7]_51 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_66__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [440]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [63]),
        .O(\my_empty_reg[7]_69 [7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_69__6
       (.I0(\my_empty_reg[7]_5 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [265]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [60]),
        .O(\my_empty_reg[7]_60 [4]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_71__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [153]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [58]),
        .O(\my_empty_reg[7]_60 [2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_73__7
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [24]),
        .I1(init_calib_complete_reg_rep__13_n_0),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [56]),
        .O(\my_empty_reg[7]_69 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [524]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [71]),
        .O(D9[7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74__5
       (.I0(\my_empty_reg[7]_4 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [527]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [71]),
        .O(\my_empty_reg[7]_50 [7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74__6
       (.I0(\my_empty_reg[7]_5 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [448]),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [71]),
        .O(\my_empty_reg[7]_59 [7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [525]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [71]),
        .O(\my_empty_reg[7]_68 [7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_75
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [516]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [70]),
        .O(D9[6]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_75__5
       (.I0(\my_empty_reg[7]_4 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [519]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [70]),
        .O(\my_empty_reg[7]_50 [6]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_75__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [517]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [70]),
        .O(\my_empty_reg[7]_68 [6]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_76
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [508]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [69]),
        .O(D9[5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_76__5
       (.I0(\my_empty_reg[7]_4 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [511]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [69]),
        .O(\my_empty_reg[7]_50 [5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_76__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [509]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [69]),
        .O(\my_empty_reg[7]_68 [5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_77
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [500]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [68]),
        .O(D9[4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_77__5
       (.I0(\my_empty_reg[7]_4 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [503]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [68]),
        .O(\my_empty_reg[7]_50 [4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_77__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [501]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [68]),
        .O(\my_empty_reg[7]_68 [4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_78
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [492]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [67]),
        .O(D9[3]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_78__5
       (.I0(\my_empty_reg[7]_4 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [495]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [67]),
        .O(\my_empty_reg[7]_50 [3]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_78__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [493]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [67]),
        .O(\my_empty_reg[7]_68 [3]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_79
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [484]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [66]),
        .O(D9[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_79__5
       (.I0(\my_empty_reg[7]_4 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [487]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [66]),
        .O(\my_empty_reg[7]_50 [2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_79__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [485]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [66]),
        .O(\my_empty_reg[7]_68 [2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_7__1
       (.I0(mc_ras_n[2]),
        .I1(\my_empty_reg[7] ),
        .I2(\my_empty_reg[1]_2 ),
        .I3(\rd_ptr_reg_rep[3]_1 [2]),
        .O(\wr_ptr_timing_reg[0]_14 [2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_8
       (.I0(\my_empty_reg[1] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [87]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [1]),
        .O(D0[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_80
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [476]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [65]),
        .O(D9[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_80__5
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [479]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [65]),
        .O(\my_empty_reg[7]_50 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_80__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [477]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [65]),
        .O(\my_empty_reg[7]_68 [1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_81
       (.I0(\my_empty_reg[6] ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [468]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [64]),
        .O(D9[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_81__5
       (.I0(init_calib_complete_reg_rep__10_n_0),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [471]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [64]),
        .O(\my_empty_reg[7]_50 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_81__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [32]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_8 ),
        .I3(\rd_ptr_reg_rep[3]_6 [64]),
        .O(\my_empty_reg[7]_59 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_81__7
       (.I0(\my_empty_reg[7]_6 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [469]),
        .I2(\my_empty_reg[1]_9 ),
        .I3(\rd_ptr_reg_rep[3]_7 [64]),
        .O(\my_empty_reg[7]_68 [0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_8__6
       (.I0(\my_empty_reg[7]_5 ),
        .I1(\write_buffer.wr_buf_out_data_reg[575] [111]),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [1]),
        .O(\my_empty_reg[7]_58 [1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_9
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [23]),
        .I1(\my_empty_reg[1] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(\rd_ptr_reg_rep[3] [0]),
        .O(D0[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_9__1
       (.I0(mc_ras_n[0]),
        .I1(\my_empty_reg[7] ),
        .I2(\my_empty_reg[1]_2 ),
        .I3(\rd_ptr_reg_rep[3]_1 [0]),
        .O(\wr_ptr_timing_reg[0]_14 [0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_9__6
       (.I0(\write_buffer.wr_buf_out_data_reg[575] [47]),
        .I1(\my_empty_reg[7]_5 ),
        .I2(\my_empty_reg[1]_7 ),
        .I3(\rd_ptr_reg_rep[3]_5 [0]),
        .O(\my_empty_reg[7]_58 [0]));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \periodic_rd_generation.periodic_rd_timer_r[2]_i_1 
       (.I0(app_zq_r_reg),
        .O(maint_prescaler_r1));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    \phaser_in_gen.phaser_in_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\pi_dqs_found_lanes_r1_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT4 #(
    .INIT(16'h00F1)) 
    \phaser_in_gen.phaser_in_i_2__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\pi_dqs_found_lanes_r1_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT4 #(
    .INIT(16'h00F1)) 
    \phaser_in_gen.phaser_in_i_2__1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[1]),
        .O(\pi_dqs_found_lanes_r1_reg[4] ));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT4 #(
    .INIT(16'h00F1)) 
    \phaser_in_gen.phaser_in_i_2__2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[2]),
        .O(\pi_dqs_found_lanes_r1_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\pi_dqs_found_lanes_r1_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__4 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[2]),
        .O(\pi_dqs_found_lanes_r1_reg[9] ));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__5 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\pi_dqs_found_lanes_r1_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__6 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[2]),
        .O(\pi_dqs_found_lanes_r1_reg[10] ));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    phaser_out_i_2__7
       (.I0(calib_in_common),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(calib_zero_inputs[1]),
        .O(\po_counter_read_val_reg[8] ));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    phaser_out_i_2__8
       (.I0(calib_in_common),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(calib_zero_inputs[1]),
        .O(\po_counter_read_val_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    phaser_out_i_2__9
       (.I0(calib_in_common),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(calib_zero_inputs[1]),
        .O(\po_counter_read_val_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    phaser_out_i_4__2
       (.I0(calib_in_common),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(phaser_out_i_4__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT3 #(
    .INIT(8'hAB)) 
    phaser_out_i_4__3
       (.I0(calib_in_common),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(phaser_out_i_4__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    phaser_out_i_4__4
       (.I0(calib_in_common),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(phaser_out_i_4__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    phaser_out_i_4__5
       (.I0(calib_in_common),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(phaser_out_i_4__5_n_0));
  FDRE phy_if_reset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_if_reset0),
        .Q(phy_if_reset),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \pi_counter_read_val[0]_i_1__0 
       (.I0(Q[1]),
        .I1(COUNTERREADVAL[0]),
        .I2(Q[0]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \pi_counter_read_val[1]_i_1__0 
       (.I0(Q[1]),
        .I1(COUNTERREADVAL[1]),
        .I2(Q[0]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \pi_counter_read_val[2]_i_1__0 
       (.I0(Q[1]),
        .I1(COUNTERREADVAL[2]),
        .I2(Q[0]),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \pi_counter_read_val[3]_i_1__0 
       (.I0(Q[1]),
        .I1(COUNTERREADVAL[3]),
        .I2(Q[0]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \pi_counter_read_val[4]_i_1__0 
       (.I0(Q[1]),
        .I1(COUNTERREADVAL[4]),
        .I2(Q[0]),
        .O(D[4]));
  LUT3 #(
    .INIT(8'h04)) 
    \pi_counter_read_val[5]_i_1__0 
       (.I0(Q[1]),
        .I1(COUNTERREADVAL[5]),
        .I2(Q[0]),
        .O(D[5]));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 " *) 
  SRL16E reset_if_r8_reg_srl8
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(reset_if),
        .Q(reset_if_r8_reg_srl8_n_0));
  FDRE reset_if_r9_reg
       (.C(CLK),
        .CE(1'b1),
        .D(reset_if_r8_reg_srl8_n_0),
        .Q(reset_if_r9),
        .R(1'b0));
  FDRE reset_if_reg
       (.C(CLK),
        .CE(1'b1),
        .D(u_ddr_phy_rdlvl_n_66),
        .Q(reset_if),
        .R(1'b0));
  FDRE tempmon_pi_f_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_sel_pi_incdec),
        .Q(tempmon_pi_f_en_r),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE tempmon_pi_f_inc_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_pi_f_inc),
        .Q(tempmon_pi_f_inc_r),
        .R(rstdiv0_sync_r1_reg_rep__3));
  mig_7series_0_mig_7series_v2_3_ddr_phy_init u_ddr_phy_init
       (.A_rst_primitives_reg(A_rst_primitives_reg),
        .B_of_data_full(B_of_data_full),
        .CLK(CLK),
        .C_of_data_full(C_of_data_full),
        .D({u_ddr_phy_rdlvl_n_37,u_ddr_phy_rdlvl_n_38,u_ddr_phy_rdlvl_n_39,u_ddr_phy_rdlvl_n_40}),
        .D0({D0[7:6],D0[4:2]}),
        .D1({D1[7:5],D1[2],D1[0]}),
        .D2({D2[7:5],D2[3],D2[1:0]}),
        .D3(D3[6:1]),
        .D4({D4[7:6],D4[4:2]}),
        .D5({D5[7:5],D5[2],D5[0]}),
        .D6({D6[7:5],D6[3],D6[1:0]}),
        .D7(D7[6:1]),
        .D8(D8),
        .E(E),
        .Q(rd_data_offset_ranks_0),
        .\back_to_back_reads_4_1.num_reads_reg[1]_0 (u_ddr_phy_init_n_22),
        .cal2_done_r_reg(u_ddr_phy_init_n_888),
        .calib_complete(calib_complete),
        .\cmd_pipe_plus.mc_address_reg[40] ({\cmd_pipe_plus.mc_address_reg[41] [37],\cmd_pipe_plus.mc_address_reg[41] [35:14],\cmd_pipe_plus.mc_address_reg[41] [12],\cmd_pipe_plus.mc_address_reg[41] [10:0]}),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[1] (\cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[2] (\cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[3] (\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[4] (\cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (\cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),
        .\cmd_pipe_plus.mc_we_n_reg[1] (\cmd_pipe_plus.mc_we_n_reg[2] [1]),
        .\cnt_shift_r_reg[3] (cnt_shift_r1545_out),
        .complex_row0_rd_done(complex_row0_rd_done),
        .complex_row0_rd_done1(complex_row0_rd_done1),
        .complex_row1_rd_done_reg_0(complex_row1_rd_done_reg),
        .\data_offset_1_i1_reg[5] (\data_offset_1_i1_reg[5] ),
        .\data_offset_2_i1_reg[5] (\data_offset_2_i1_reg[5] ),
        .ddr3_lm_done_r(ddr3_lm_done_r),
        .detect_pi_found_dqs(detect_pi_found_dqs),
        .done_dqs_tap_inc(done_dqs_tap_inc),
        .dqs_found_done_r_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72 ),
        .dqs_found_done_r_reg_0(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .dqs_found_prech_req(dqs_found_prech_req),
        .\entry_cnt_reg[3] (\entry_cnt_reg[3] ),
        .\entry_cnt_reg[3]_0 (\entry_cnt_reg[3]_0 ),
        .first_rdlvl_pat_r(first_rdlvl_pat_r),
        .first_wrcal_pat_r(first_wrcal_pat_r),
        .\gen_byte_sel_div2.calib_in_common_reg (u_ddr_phy_init_n_887),
        .init_calib_complete_reg_rep(app_zq_r_reg),
        .init_calib_complete_reg_rep__0(\my_empty_reg[6] ),
        .init_calib_complete_reg_rep__1(\my_empty_reg[1] ),
        .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10_n_0),
        .init_calib_complete_reg_rep__11(\my_empty_reg[7]_5 ),
        .init_calib_complete_reg_rep__12(\my_empty_reg[7]_6 ),
        .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13_n_0),
        .init_calib_complete_reg_rep__14(\data_offset_2_i1_reg[3] ),
        .init_calib_complete_reg_rep__15(\data_offset_2_i1_reg[2] ),
        .init_calib_complete_reg_rep__16(init_calib_complete_reg_rep__16_n_0),
        .init_calib_complete_reg_rep__17(init_calib_complete_reg_rep__17_n_0),
        .init_calib_complete_reg_rep__18(init_calib_complete_reg_rep__18_n_0),
        .init_calib_complete_reg_rep__19(\my_empty_reg[7]_7 ),
        .init_calib_complete_reg_rep__2(\my_empty_reg[6]_0 ),
        .init_calib_complete_reg_rep__20(\my_empty_reg[7]_8 ),
        .init_calib_complete_reg_rep__21(\my_empty_reg[7]_9 ),
        .init_calib_complete_reg_rep__22(\my_empty_reg[7]_10 ),
        .init_calib_complete_reg_rep__23(\my_empty_reg[7]_11 ),
        .init_calib_complete_reg_rep__24(\my_empty_reg[7]_12 ),
        .init_calib_complete_reg_rep__25(\my_empty_reg[7]_13 ),
        .init_calib_complete_reg_rep__26(\my_empty_reg[7]_14 ),
        .init_calib_complete_reg_rep__27(\my_empty_reg[7]_15 ),
        .init_calib_complete_reg_rep__28(init_calib_complete_reg_rep__28_0),
        .init_calib_complete_reg_rep__3(\my_empty_reg[7] ),
        .init_calib_complete_reg_rep__4(\my_empty_reg[7]_0 ),
        .init_calib_complete_reg_rep__5(\my_empty_reg[7]_1 ),
        .init_calib_complete_reg_rep__6(\my_empty_reg[7]_2 ),
        .init_calib_complete_reg_rep__7(\my_empty_reg[7]_3 ),
        .init_calib_complete_reg_rep__8(\wr_ptr_timing_reg[0] ),
        .init_calib_complete_reg_rep__9(\my_empty_reg[7]_4 ),
        .init_complete_r_timing(init_complete_r_timing),
        .init_complete_r_timing_reg_0(init_complete_r_timing_reg),
        .init_dqsfound_done_r2_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_0 ),
        .mc_cas_n(mc_cas_n[1]),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n[1]),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_init_done_r(mem_init_done_r),
        .mem_out(mem_out),
        .mpr_rdlvl_start_r_reg(u_ddr_phy_init_n_909),
        .mux_reset_n(mux_reset_n),
        .mux_wrdata({mux_wrdata[207:205],mux_wrdata[203:201],mux_wrdata[199:197],mux_wrdata[195:193],mux_wrdata[191:189],mux_wrdata[187:185],mux_wrdata[183:181],mux_wrdata[179:177],mux_wrdata[175:119],mux_wrdata[117:116],mux_wrdata[114:113],mux_wrdata[111:110],mux_wrdata[108:107],mux_wrdata[105:104],mux_wrdata[102:101],mux_wrdata[99:98],mux_wrdata[96:48],mux_wrdata[45:44],mux_wrdata[41:40],mux_wrdata[37:36],mux_wrdata[33:32],mux_wrdata[29:28],mux_wrdata[25:24],mux_wrdata[21:20],mux_wrdata[17:0]}),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_1 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_2 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_3 ),
        .\my_empty_reg[1]_3 (\my_empty_reg[1]_4 ),
        .\my_empty_reg[1]_4 (\my_empty_reg[1]_5 ),
        .\my_empty_reg[1]_5 (\my_empty_reg[1]_6 ),
        .\my_empty_reg[1]_6 (\my_empty_reg[1]_7 ),
        .\my_empty_reg[1]_7 (\my_empty_reg[1]_8 ),
        .\my_empty_reg[1]_8 (\my_empty_reg[1]_9 ),
        .\my_empty_reg[1]_9 (\my_empty_reg[1]_10 ),
        .\my_empty_reg[3] (\my_empty_reg[3] ),
        .\my_empty_reg[3]_0 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[3]_1 (\my_empty_reg[3]_1 ),
        .\my_empty_reg[5] (\my_empty_reg[5] ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5]_0 ),
        .\my_empty_reg[5]_1 (\my_empty_reg[5]_1 ),
        .\my_empty_reg[6] (\my_empty_reg[6]_1 ),
        .\my_empty_reg[6]_0 (\my_empty_reg[6]_2 ),
        .\my_empty_reg[6]_1 (\my_empty_reg[6]_3 ),
        .\my_empty_reg[6]_2 (\my_empty_reg[6]_4 ),
        .\my_empty_reg[7] (calib_wrdata_en),
        .\my_empty_reg[7]_0 ({\my_empty_reg[7]_16 [207:205],\my_empty_reg[7]_16 [203:201],\my_empty_reg[7]_16 [199:197],\my_empty_reg[7]_16 [195:193],\my_empty_reg[7]_16 [191:189],\my_empty_reg[7]_16 [187:185],\my_empty_reg[7]_16 [183:181],\my_empty_reg[7]_16 [179:177],\my_empty_reg[7]_16 [175:119],\my_empty_reg[7]_16 [117:116],\my_empty_reg[7]_16 [114:113],\my_empty_reg[7]_16 [111:110],\my_empty_reg[7]_16 [108:107],\my_empty_reg[7]_16 [105:104],\my_empty_reg[7]_16 [102:101],\my_empty_reg[7]_16 [99:98],\my_empty_reg[7]_16 [96:48],\my_empty_reg[7]_16 [45:44],\my_empty_reg[7]_16 [41:40],\my_empty_reg[7]_16 [37:36],\my_empty_reg[7]_16 [33:32],\my_empty_reg[7]_16 [29:28],\my_empty_reg[7]_16 [25:24],\my_empty_reg[7]_16 [21:20],\my_empty_reg[7]_16 [17:0]}),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_18 ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_27 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_28 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_29 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_30 ),
        .\my_empty_reg[7]_14 (\my_empty_reg[7]_31 ),
        .\my_empty_reg[7]_15 (\my_empty_reg[7]_32 ),
        .\my_empty_reg[7]_16 (\my_empty_reg[7]_33 ),
        .\my_empty_reg[7]_17 (\my_empty_reg[7]_34 ),
        .\my_empty_reg[7]_18 (\my_empty_reg[7]_35 ),
        .\my_empty_reg[7]_19 (\my_empty_reg[7]_36 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_19 ),
        .\my_empty_reg[7]_20 (\my_empty_reg[7]_37 ),
        .\my_empty_reg[7]_21 (\my_empty_reg[7]_38 ),
        .\my_empty_reg[7]_22 (\my_empty_reg[7]_39 ),
        .\my_empty_reg[7]_23 (\my_empty_reg[7]_40 ),
        .\my_empty_reg[7]_24 (\my_empty_reg[7]_41 ),
        .\my_empty_reg[7]_25 (\my_empty_reg[7]_42 ),
        .\my_empty_reg[7]_26 (\my_empty_reg[7]_43 ),
        .\my_empty_reg[7]_27 (\my_empty_reg[7]_44 ),
        .\my_empty_reg[7]_28 (\my_empty_reg[7]_45 ),
        .\my_empty_reg[7]_29 (\my_empty_reg[7]_46 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_20 ),
        .\my_empty_reg[7]_30 (\my_empty_reg[7]_47 ),
        .\my_empty_reg[7]_31 (\my_empty_reg[7]_48 ),
        .\my_empty_reg[7]_32 (\my_empty_reg[7]_49 ),
        .\my_empty_reg[7]_33 (\my_empty_reg[7]_51 [6:1]),
        .\my_empty_reg[7]_34 ({\my_empty_reg[7]_52 [7:5],\my_empty_reg[7]_52 [3],\my_empty_reg[7]_52 [1:0]}),
        .\my_empty_reg[7]_35 ({\my_empty_reg[7]_53 [7:5],\my_empty_reg[7]_53 [2],\my_empty_reg[7]_53 [0]}),
        .\my_empty_reg[7]_36 ({\my_empty_reg[7]_54 [7:6],\my_empty_reg[7]_54 [4:2]}),
        .\my_empty_reg[7]_37 (\my_empty_reg[7]_55 [6:1]),
        .\my_empty_reg[7]_38 ({\my_empty_reg[7]_56 [7:5],\my_empty_reg[7]_56 [3],\my_empty_reg[7]_56 [1:0]}),
        .\my_empty_reg[7]_39 ({\my_empty_reg[7]_57 [7:5],\my_empty_reg[7]_57 [2],\my_empty_reg[7]_57 [0]}),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_21 ),
        .\my_empty_reg[7]_40 ({\my_empty_reg[7]_58 [7:6],\my_empty_reg[7]_58 [4:2]}),
        .\my_empty_reg[7]_41 (\my_empty_reg[7]_59 [6:1]),
        .\my_empty_reg[7]_42 ({\my_empty_reg[7]_60 [7:5],\my_empty_reg[7]_60 [3],\my_empty_reg[7]_60 [1:0]}),
        .\my_empty_reg[7]_43 ({\my_empty_reg[7]_61 [7:5],\my_empty_reg[7]_61 [2],\my_empty_reg[7]_61 [0]}),
        .\my_empty_reg[7]_44 ({\my_empty_reg[7]_62 [7:6],\my_empty_reg[7]_62 [4:2]}),
        .\my_empty_reg[7]_45 (\my_empty_reg[7]_64 [6:1]),
        .\my_empty_reg[7]_46 ({\my_empty_reg[7]_65 [7:5],\my_empty_reg[7]_65 [3],\my_empty_reg[7]_65 [1:0]}),
        .\my_empty_reg[7]_47 ({\my_empty_reg[7]_66 [7:5],\my_empty_reg[7]_66 [2],\my_empty_reg[7]_66 [0]}),
        .\my_empty_reg[7]_48 ({\my_empty_reg[7]_67 [7:6],\my_empty_reg[7]_67 [4:2]}),
        .\my_empty_reg[7]_49 (\my_empty_reg[7]_69 [6:1]),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_22 ),
        .\my_empty_reg[7]_50 ({\my_empty_reg[7]_70 [7:5],\my_empty_reg[7]_70 [3],\my_empty_reg[7]_70 [1:0]}),
        .\my_empty_reg[7]_51 ({\my_empty_reg[7]_71 [7:5],\my_empty_reg[7]_71 [2],\my_empty_reg[7]_71 [0]}),
        .\my_empty_reg[7]_52 ({\my_empty_reg[7]_72 [7:6],\my_empty_reg[7]_72 [4:2]}),
        .\my_empty_reg[7]_53 (\my_empty_reg[7]_73 [6:1]),
        .\my_empty_reg[7]_54 ({\my_empty_reg[7]_74 [7:5],\my_empty_reg[7]_74 [3],\my_empty_reg[7]_74 [1:0]}),
        .\my_empty_reg[7]_55 ({\my_empty_reg[7]_75 [7:5],\my_empty_reg[7]_75 [2],\my_empty_reg[7]_75 [0]}),
        .\my_empty_reg[7]_56 ({\my_empty_reg[7]_76 [7:6],\my_empty_reg[7]_76 [4:2]}),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_23 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_24 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_25 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_26 ),
        .\my_full_reg[4] (\my_full_reg[4] ),
        .\my_full_reg[4]_0 (\my_full_reg[4]_0 ),
        .\one_rank.stg1_wr_done_reg_0 (u_ddr_phy_init_n_14),
        .\one_rank.stg1_wr_done_reg_1 (u_ddr_phy_rdlvl_n_35),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_ctl_ready(phy_ctl_ready),
        .\phy_ctl_wd_i1_reg[24] (\phy_ctl_wd_i1_reg[24] ),
        .phy_ctl_wr_i1_reg(phy_ctl_wr_i1_reg),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({phy_dout[19:16],phy_dout[11:0]}),
        .pi_calib_done(pi_calib_done),
        .\pi_dqs_found_any_bank_reg[0] (u_ddr_phy_init_n_908),
        .pi_dqs_found_done_r1(pi_dqs_found_done_r1),
        .pi_dqs_found_done_r1_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21 ),
        .pi_dqs_found_done_r1_reg_1(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23 ),
        .pi_dqs_found_done_r1_reg_10(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34 ),
        .pi_dqs_found_done_r1_reg_11(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36 ),
        .pi_dqs_found_done_r1_reg_12(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37 ),
        .pi_dqs_found_done_r1_reg_13(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38 ),
        .pi_dqs_found_done_r1_reg_14(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39 ),
        .pi_dqs_found_done_r1_reg_2(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_24 ),
        .pi_dqs_found_done_r1_reg_3(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_25 ),
        .pi_dqs_found_done_r1_reg_4(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_26 ),
        .pi_dqs_found_done_r1_reg_5(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_27 ),
        .pi_dqs_found_done_r1_reg_6(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30 ),
        .pi_dqs_found_done_r1_reg_7(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31 ),
        .pi_dqs_found_done_r1_reg_8(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32 ),
        .pi_dqs_found_done_r1_reg_9(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_33 ),
        .pi_dqs_found_rank_done(pi_dqs_found_rank_done),
        .po_ck_addr_cmd_delay_done(po_ck_addr_cmd_delay_done),
        .prbs_last_byte_done_r(prbs_last_byte_done_r),
        .prech_done(prech_done),
        .prech_pending_r_reg_0(u_ddr_phy_init_n_4),
        .prech_req(prech_req),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] (rd_data_offset_ranks_1),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] (rd_data_offset_ranks_2),
        .rd_active_r(rd_active_r),
        .\rd_byte_data_offset_reg[0][15] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_75 ),
        .\rd_byte_data_offset_reg[0][3] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_74 ),
        .\rd_byte_data_offset_reg[0][9] (p_0_in),
        .\rd_ptr_reg_rep[3] ({\rd_ptr_reg_rep[3] [62:57],\rd_ptr_reg_rep[3] [55:53],\rd_ptr_reg_rep[3] [51],\rd_ptr_reg_rep[3] [49:45],\rd_ptr_reg_rep[3] [42],\rd_ptr_reg_rep[3] [40:38],\rd_ptr_reg_rep[3] [36:34],\rd_ptr_reg_rep[3] [30:25],\rd_ptr_reg_rep[3] [23:21],\rd_ptr_reg_rep[3] [19],\rd_ptr_reg_rep[3] [17:13],\rd_ptr_reg_rep[3] [10],\rd_ptr_reg_rep[3] [8:6],\rd_ptr_reg_rep[3] [4:2]}),
        .\rd_ptr_reg_rep[3]_0 ({\rd_ptr_reg_rep[3]_0 [15],\rd_ptr_reg_rep[3]_0 [12],\rd_ptr_reg_rep[3]_0 [9],\rd_ptr_reg_rep[3]_0 [7:0]}),
        .\rd_ptr_reg_rep[3]_1 ({\rd_ptr_reg_rep[3]_1 [46:3],\rd_ptr_reg_rep[3]_1 [1]}),
        .\rd_ptr_reg_rep[3]_2 (\rd_ptr_reg_rep[3]_2 ),
        .\rd_ptr_reg_rep[3]_3 (\rd_ptr_reg_rep[3]_3 ),
        .\rd_ptr_reg_rep[3]_4 (\rd_ptr_reg_rep[3]_4 ),
        .\rd_ptr_reg_rep[3]_5 ({\rd_ptr_reg_rep[3]_5 [62:57],\rd_ptr_reg_rep[3]_5 [55:53],\rd_ptr_reg_rep[3]_5 [51],\rd_ptr_reg_rep[3]_5 [49:45],\rd_ptr_reg_rep[3]_5 [42],\rd_ptr_reg_rep[3]_5 [40:38],\rd_ptr_reg_rep[3]_5 [36:34],\rd_ptr_reg_rep[3]_5 [30:25],\rd_ptr_reg_rep[3]_5 [23:21],\rd_ptr_reg_rep[3]_5 [19],\rd_ptr_reg_rep[3]_5 [17:13],\rd_ptr_reg_rep[3]_5 [10],\rd_ptr_reg_rep[3]_5 [8:6],\rd_ptr_reg_rep[3]_5 [4:2]}),
        .\rd_ptr_reg_rep[3]_6 ({\rd_ptr_reg_rep[3]_6 [70:65],\rd_ptr_reg_rep[3]_6 [63:61],\rd_ptr_reg_rep[3]_6 [59],\rd_ptr_reg_rep[3]_6 [57:53],\rd_ptr_reg_rep[3]_6 [50],\rd_ptr_reg_rep[3]_6 [48:46],\rd_ptr_reg_rep[3]_6 [44:42],\rd_ptr_reg_rep[3]_6 [30:25],\rd_ptr_reg_rep[3]_6 [23:21],\rd_ptr_reg_rep[3]_6 [19],\rd_ptr_reg_rep[3]_6 [17:13],\rd_ptr_reg_rep[3]_6 [10],\rd_ptr_reg_rep[3]_6 [8:6],\rd_ptr_reg_rep[3]_6 [4:2]}),
        .\rd_ptr_reg_rep[3]_7 ({\rd_ptr_reg_rep[3]_7 [62:57],\rd_ptr_reg_rep[3]_7 [55:53],\rd_ptr_reg_rep[3]_7 [51],\rd_ptr_reg_rep[3]_7 [49:45],\rd_ptr_reg_rep[3]_7 [42],\rd_ptr_reg_rep[3]_7 [40:38],\rd_ptr_reg_rep[3]_7 [36:34],\rd_ptr_reg_rep[3]_7 [30:25],\rd_ptr_reg_rep[3]_7 [23:21],\rd_ptr_reg_rep[3]_7 [19],\rd_ptr_reg_rep[3]_7 [17:13],\rd_ptr_reg_rep[3]_7 [10],\rd_ptr_reg_rep[3]_7 [8:6],\rd_ptr_reg_rep[3]_7 [4:2]}),
        .rdlvl_last_byte_done(rdlvl_last_byte_done),
        .rdlvl_prech_req(rdlvl_prech_req),
        .rdlvl_stg1_done_reg(u_ddr_phy_rdlvl_n_26),
        .rdlvl_stg1_done_reg_0(u_ddr_phy_rdlvl_n_7),
        .rdlvl_stg1_done_reg_1(u_ddr_phy_rdlvl_n_34),
        .rdlvl_stg1_done_reg_2(u_ddr_phy_rdlvl_n_32),
        .rdlvl_stg1_done_reg_3(u_ddr_phy_rdlvl_n_30),
        .rdlvl_stg1_done_reg_4(u_ddr_phy_rdlvl_n_33),
        .rdlvl_stg1_done_reg_5(u_ddr_phy_rdlvl_n_31),
        .rdlvl_stg1_done_reg_6(u_ddr_phy_rdlvl_n_36),
        .rdlvl_stg1_done_reg_7(u_ddr_phy_rdlvl_n_41),
        .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),
        .rdlvl_stg1_start_r_reg(rdlvl_stg1_start_r_reg),
        .read_calib(read_calib),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),
        .rstdiv0_sync_r1_reg_rep__22_0(u_ddr_phy_rdlvl_n_22),
        .rstdiv0_sync_r1_reg_rep__3(rstdiv0_sync_r1_reg_rep__3),
        .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),
        .stg1_wr_done(stg1_wr_done),
        .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec),
        .wl_sm_start(wl_sm_start),
        .wr_en(wr_en),
        .wr_en_0(wr_en_0),
        .wr_en_1(wr_en_1),
        .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_6 ),
        .wr_level_start_r_reg(u_ddr_phy_init_n_906),
        .\wr_ptr_reg[2] (calib_cmd_wren),
        .\wr_ptr_reg[2]_0 (\wr_ptr_reg[2] ),
        .\wr_ptr_reg[2]_1 (\wr_ptr_reg[2]_0 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_1 ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_2 [1]),
        .\wr_ptr_timing_reg[0]_10 (\wr_ptr_timing_reg[0]_11 ),
        .\wr_ptr_timing_reg[0]_11 (\wr_ptr_timing_reg[0]_12 ),
        .\wr_ptr_timing_reg[0]_12 (\wr_ptr_timing_reg[0]_13 ),
        .\wr_ptr_timing_reg[0]_13 (\wr_ptr_timing_reg[0]_14 [1]),
        .\wr_ptr_timing_reg[0]_2 ({\wr_ptr_timing_reg[0]_3 [4],\wr_ptr_timing_reg[0]_3 [1]}),
        .\wr_ptr_timing_reg[0]_3 (\wr_ptr_timing_reg[0]_4 ),
        .\wr_ptr_timing_reg[0]_4 (\wr_ptr_timing_reg[0]_5 ),
        .\wr_ptr_timing_reg[0]_5 (\wr_ptr_timing_reg[0]_6 ),
        .\wr_ptr_timing_reg[0]_6 (\wr_ptr_timing_reg[0]_7 ),
        .\wr_ptr_timing_reg[0]_7 (\wr_ptr_timing_reg[0]_8 ),
        .\wr_ptr_timing_reg[0]_8 (\wr_ptr_timing_reg[0]_9 ),
        .\wr_ptr_timing_reg[0]_9 (\wr_ptr_timing_reg[0]_10 ),
        .wrcal_done_reg(u_ddr_phy_wrcal_n_14),
        .wrcal_done_reg_0(u_ddr_phy_wrcal_n_15),
        .wrcal_prech_req(wrcal_prech_req),
        .wrcal_rd_wait(wrcal_rd_wait),
        .wrcal_resume_w(wrcal_resume_w),
        .wrcal_sanity_chk(wrcal_sanity_chk),
        .wrcal_sanity_chk_done(wrcal_sanity_chk_done),
        .wrcal_sanity_chk_done_reg(u_ddr_phy_wrcal_n_13),
        .wrcal_sanity_chk_r(wrcal_sanity_chk_r),
        .wrcal_start_reg_0(u_ddr_phy_init_n_907),
        .\write_buffer.wr_buf_out_data_reg[511] ({\write_buffer.wr_buf_out_data_reg[575] [463:461],\write_buffer.wr_buf_out_data_reg[575] [459:457],\write_buffer.wr_buf_out_data_reg[575] [455:453],\write_buffer.wr_buf_out_data_reg[575] [451:449],\write_buffer.wr_buf_out_data_reg[575] [447:445],\write_buffer.wr_buf_out_data_reg[575] [443:441],\write_buffer.wr_buf_out_data_reg[575] [439:437],\write_buffer.wr_buf_out_data_reg[575] [435:433],\write_buffer.wr_buf_out_data_reg[575] [431:429],\write_buffer.wr_buf_out_data_reg[575] [427:425],\write_buffer.wr_buf_out_data_reg[575] [423:421],\write_buffer.wr_buf_out_data_reg[575] [419:417],\write_buffer.wr_buf_out_data_reg[575] [415:413],\write_buffer.wr_buf_out_data_reg[575] [411:409],\write_buffer.wr_buf_out_data_reg[575] [407:405],\write_buffer.wr_buf_out_data_reg[575] [403:401],\write_buffer.wr_buf_out_data_reg[575] [399:336],\write_buffer.wr_buf_out_data_reg[575] [334:332],\write_buffer.wr_buf_out_data_reg[575] [330:328],\write_buffer.wr_buf_out_data_reg[575] [326:324],\write_buffer.wr_buf_out_data_reg[575] [322:320],\write_buffer.wr_buf_out_data_reg[575] [318:316],\write_buffer.wr_buf_out_data_reg[575] [314:312],\write_buffer.wr_buf_out_data_reg[575] [310:308],\write_buffer.wr_buf_out_data_reg[575] [306:279],\write_buffer.wr_buf_out_data_reg[575] [276:275],\write_buffer.wr_buf_out_data_reg[575] [272:271],\write_buffer.wr_buf_out_data_reg[575] [268:267],\write_buffer.wr_buf_out_data_reg[575] [264:263],\write_buffer.wr_buf_out_data_reg[575] [260:259],\write_buffer.wr_buf_out_data_reg[575] [256:255],\write_buffer.wr_buf_out_data_reg[575] [252:251],\write_buffer.wr_buf_out_data_reg[575] [248:247],\write_buffer.wr_buf_out_data_reg[575] [245:244],\write_buffer.wr_buf_out_data_reg[575] [242:241],\write_buffer.wr_buf_out_data_reg[575] [239:238],\write_buffer.wr_buf_out_data_reg[575] [236:235],\write_buffer.wr_buf_out_data_reg[575] [233:232],\write_buffer.wr_buf_out_data_reg[575] [230:229],\write_buffer.wr_buf_out_data_reg[575] [227:226],\write_buffer.wr_buf_out_data_reg[575] [224:223],\write_buffer.wr_buf_out_data_reg[575] [221:219],\write_buffer.wr_buf_out_data_reg[575] [217:215],\write_buffer.wr_buf_out_data_reg[575] [213:211],\write_buffer.wr_buf_out_data_reg[575] [209:207],\write_buffer.wr_buf_out_data_reg[575] [205:203],\write_buffer.wr_buf_out_data_reg[575] [201:199],\write_buffer.wr_buf_out_data_reg[575] [197:195],\write_buffer.wr_buf_out_data_reg[575] [193:166],\write_buffer.wr_buf_out_data_reg[575] [164:162],\write_buffer.wr_buf_out_data_reg[575] [160:158],\write_buffer.wr_buf_out_data_reg[575] [156:154],\write_buffer.wr_buf_out_data_reg[575] [152:150],\write_buffer.wr_buf_out_data_reg[575] [148:146],\write_buffer.wr_buf_out_data_reg[575] [144:142],\write_buffer.wr_buf_out_data_reg[575] [140:138],\write_buffer.wr_buf_out_data_reg[575] [136:112],\write_buffer.wr_buf_out_data_reg[575] [109:108],\write_buffer.wr_buf_out_data_reg[575] [105:104],\write_buffer.wr_buf_out_data_reg[575] [101:100],\write_buffer.wr_buf_out_data_reg[575] [97:96],\write_buffer.wr_buf_out_data_reg[575] [93:92],\write_buffer.wr_buf_out_data_reg[575] [89:88],\write_buffer.wr_buf_out_data_reg[575] [85:84],\write_buffer.wr_buf_out_data_reg[575] [81:80],\write_buffer.wr_buf_out_data_reg[575] [77:76],\write_buffer.wr_buf_out_data_reg[575] [73:72],\write_buffer.wr_buf_out_data_reg[575] [69:68],\write_buffer.wr_buf_out_data_reg[575] [65:64],\write_buffer.wr_buf_out_data_reg[575] [61:60],\write_buffer.wr_buf_out_data_reg[575] [57:56],\write_buffer.wr_buf_out_data_reg[575] [53:52],\write_buffer.wr_buf_out_data_reg[575] [49:48],\write_buffer.wr_buf_out_data_reg[575] [46:45],\write_buffer.wr_buf_out_data_reg[575] [42:41],\write_buffer.wr_buf_out_data_reg[575] [38:37],\write_buffer.wr_buf_out_data_reg[575] [34:33],\write_buffer.wr_buf_out_data_reg[575] [30:29],\write_buffer.wr_buf_out_data_reg[575] [26:25],\write_buffer.wr_buf_out_data_reg[575] [22:21],\write_buffer.wr_buf_out_data_reg[575] [18:17],\write_buffer.wr_buf_out_data_reg[575] [15:0]}),
        .write_calib(write_calib),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_24),
        .wrlvl_done_r1(wrlvl_done_r1),
        .wrlvl_final_if_rst(wrlvl_final_if_rst),
        .wrlvl_rank_done(wrlvl_rank_done));
  mig_7series_0_mig_7series_v2_3_ddr_phy_rdlvl u_ddr_phy_rdlvl
       (.A_pi_counter_load_en116_out(A_pi_counter_load_en116_out),
        .A_pi_counter_load_en161_out(A_pi_counter_load_en161_out),
        .A_pi_counter_load_en87_out(A_pi_counter_load_en87_out),
        .A_pi_fine_enable112_out(A_pi_fine_enable112_out),
        .A_pi_fine_enable157_out(A_pi_fine_enable157_out),
        .A_pi_fine_enable83_out(A_pi_fine_enable83_out),
        .A_pi_fine_inc114_out(A_pi_fine_inc114_out),
        .A_pi_fine_inc159_out(A_pi_fine_inc159_out),
        .A_pi_fine_inc85_out(A_pi_fine_inc85_out),
        .B_pi_counter_load_en35_out(B_pi_counter_load_en35_out),
        .B_pi_counter_load_en38_out(B_pi_counter_load_en38_out),
        .B_pi_fine_enable31_out(B_pi_fine_enable31_out),
        .B_pi_fine_enable34_out(B_pi_fine_enable34_out),
        .B_pi_fine_inc33_out(B_pi_fine_inc33_out),
        .B_pi_fine_inc36_out(B_pi_fine_inc36_out),
        .CLK(CLK),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .C_pi_counter_load_en61_out(C_pi_counter_load_en61_out),
        .C_pi_counter_load_en64_out(C_pi_counter_load_en64_out),
        .C_pi_fine_enable57_out(C_pi_fine_enable57_out),
        .C_pi_fine_enable60_out(C_pi_fine_enable60_out),
        .C_pi_fine_inc59_out(C_pi_fine_inc59_out),
        .C_pi_fine_inc62_out(C_pi_fine_inc62_out),
        .D({u_ddr_phy_rdlvl_n_37,u_ddr_phy_rdlvl_n_38,u_ddr_phy_rdlvl_n_39,u_ddr_phy_rdlvl_n_40}),
        .D_pi_counter_load_en90_out(D_pi_counter_load_en90_out),
        .D_pi_fine_enable86_out(D_pi_fine_enable86_out),
        .D_pi_fine_inc88_out(D_pi_fine_inc88_out),
        .E(u_ddr_phy_wrcal_n_36),
        .\FSM_onehot_cal1_state_r_reg[0]_0 (u_ddr_phy_rdlvl_n_23),
        .Q(calib_zero_inputs),
        .\calib_sel_reg[1] (Q[1:0]),
        .complex_row0_rd_done(complex_row0_rd_done),
        .\ctl_lane_cnt_reg[1] (u_ddr_phy_rdlvl_n_71),
        .\dqs_count_r_reg[0]_rep (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_19 ),
        .\dqs_count_r_reg[1]_rep (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18 ),
        .\dqs_count_r_reg[2]_rep__0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),
        .\dqs_count_r_reg[3] (dqs_count_r),
        .dqs_found_done_r_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72 ),
        .dqs_po_dec_done(dqs_po_dec_done),
        .fine_dly_dec_done_r1_reg_0(fine_dly_dec_done_r1_reg),
        .first_rdlvl_pat_r(first_rdlvl_pat_r),
        .first_wrcal_pat_r(first_wrcal_pat_r),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (u_ddr_phy_rdlvl_n_70),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1] (u_ddr_phy_rdlvl_n_69),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[2] (u_ddr_phy_rdlvl_n_68),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[3] (u_ddr_phy_rdlvl_n_67),
        .\gen_byte_sel_div2.calib_in_common_reg (calib_in_common),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (u_ddr_phy_rdlvl_n_32),
        .idelay_ce_int(idelay_ce_int),
        .idelay_inc_int(idelay_inc_int),
        .\idelay_tap_cnt_r_reg[0][7][3]_0 (\idelay_tap_cnt_r_reg[0][7][3] ),
        .\idelay_tap_cnt_r_reg[0][7][4]_0 (u_ddr_phy_rdlvl_n_25),
        .idelay_tap_limit_r_reg_0(idelay_tap_limit_r_reg),
        .\init_state_r_reg[0] (u_ddr_phy_rdlvl_n_30),
        .\init_state_r_reg[0]_0 (u_ddr_phy_rdlvl_n_31),
        .\init_state_r_reg[2] (u_ddr_phy_rdlvl_n_35),
        .\init_state_r_reg[3] (u_ddr_phy_rdlvl_n_34),
        .\init_state_r_reg[4] (u_ddr_phy_rdlvl_n_33),
        .mpr_rdlvl_start_reg(u_ddr_phy_init_n_909),
        .\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_14),
        .\pi_counter_read_val_reg[0] (\pi_counter_read_val_reg[0] ),
        .\pi_counter_read_val_reg[0]_0 (\pi_counter_read_val_reg[0]_0 ),
        .\pi_counter_read_val_reg[1] (\pi_counter_read_val_reg[1] ),
        .\pi_counter_read_val_reg[1]_0 (\pi_counter_read_val_reg[1]_0 ),
        .\pi_counter_read_val_reg[2] (\pi_counter_read_val_reg[2] ),
        .\pi_counter_read_val_reg[2]_0 (\pi_counter_read_val_reg[2]_0 ),
        .\pi_counter_read_val_reg[3] (\pi_counter_read_val_reg[3] ),
        .\pi_counter_read_val_reg[4] (\pi_counter_read_val_reg[4] ),
        .\pi_counter_read_val_reg[4]_0 (\pi_counter_read_val_reg[4]_0 ),
        .\pi_counter_read_val_reg[5] (\pi_counter_read_val_reg[5] ),
        .\pi_dqs_found_lanes_r1_reg[10] (\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[1]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .\pi_dqs_found_lanes_r1_reg[4] (\pi_dqs_found_lanes_r1_reg[4]_0 ),
        .\pi_dqs_found_lanes_r1_reg[8] (\pi_dqs_found_lanes_r1_reg[8] ),
        .\pi_dqs_found_lanes_r1_reg[9] (\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_32),
        .\po_stg2_wrcal_cnt_reg[0]_0 (u_ddr_phy_wrcal_n_34),
        .\po_stg2_wrcal_cnt_reg[0]_1 (u_ddr_phy_wrcal_n_35),
        .\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_33),
        .\po_stg2_wrcal_cnt_reg[2] (u_ddr_phy_wrcal_n_22),
        .\po_stg2_wrcal_cnt_reg[3] (u_ddr_phy_wrcal_n_21),
        .prbs_last_byte_done_r(prbs_last_byte_done_r),
        .prbs_rdlvl_done_pulse_reg(u_ddr_phy_rdlvl_n_26),
        .prech_done(prech_done),
        .rd_active_r(rd_active_r),
        .\rd_mux_sel_r_reg[0]_0 (\rd_mux_sel_r_reg[0] ),
        .\rd_mux_sel_r_reg[0]_1 (\rd_mux_sel_r_reg[0]_0 ),
        .\rd_mux_sel_r_reg[0]_10 (\rd_mux_sel_r_reg[0]_9 ),
        .\rd_mux_sel_r_reg[0]_11 (\rd_mux_sel_r_reg[0]_10 ),
        .\rd_mux_sel_r_reg[0]_12 (\rd_mux_sel_r_reg[0]_11 ),
        .\rd_mux_sel_r_reg[0]_13 (\rd_mux_sel_r_reg[0]_12 ),
        .\rd_mux_sel_r_reg[0]_14 (\rd_mux_sel_r_reg[0]_13 ),
        .\rd_mux_sel_r_reg[0]_15 (\rd_mux_sel_r_reg[0]_14 ),
        .\rd_mux_sel_r_reg[0]_16 (\rd_mux_sel_r_reg[0]_15 ),
        .\rd_mux_sel_r_reg[0]_17 (\rd_mux_sel_r_reg[0]_16 ),
        .\rd_mux_sel_r_reg[0]_18 (\rd_mux_sel_r_reg[0]_17 ),
        .\rd_mux_sel_r_reg[0]_19 (\rd_mux_sel_r_reg[0]_18 ),
        .\rd_mux_sel_r_reg[0]_2 (\rd_mux_sel_r_reg[0]_1 ),
        .\rd_mux_sel_r_reg[0]_20 (\rd_mux_sel_r_reg[0]_19 ),
        .\rd_mux_sel_r_reg[0]_21 (\rd_mux_sel_r_reg[0]_20 ),
        .\rd_mux_sel_r_reg[0]_22 (\rd_mux_sel_r_reg[0]_21 ),
        .\rd_mux_sel_r_reg[0]_23 (\rd_mux_sel_r_reg[0]_22 ),
        .\rd_mux_sel_r_reg[0]_24 (\rd_mux_sel_r_reg[0]_23 ),
        .\rd_mux_sel_r_reg[0]_25 (\rd_mux_sel_r_reg[0]_24 ),
        .\rd_mux_sel_r_reg[0]_26 (\rd_mux_sel_r_reg[0]_25 ),
        .\rd_mux_sel_r_reg[0]_27 (\rd_mux_sel_r_reg[0]_26 ),
        .\rd_mux_sel_r_reg[0]_28 (\rd_mux_sel_r_reg[0]_27 ),
        .\rd_mux_sel_r_reg[0]_29 (\rd_mux_sel_r_reg[0]_28 ),
        .\rd_mux_sel_r_reg[0]_3 (\rd_mux_sel_r_reg[0]_2 ),
        .\rd_mux_sel_r_reg[0]_30 (\rd_mux_sel_r_reg[0]_29 ),
        .\rd_mux_sel_r_reg[0]_31 (\rd_mux_sel_r_reg[0]_30 ),
        .\rd_mux_sel_r_reg[0]_32 (\rd_mux_sel_r_reg[0]_31 ),
        .\rd_mux_sel_r_reg[0]_33 (\rd_mux_sel_r_reg[0]_32 ),
        .\rd_mux_sel_r_reg[0]_34 (\rd_mux_sel_r_reg[0]_33 ),
        .\rd_mux_sel_r_reg[0]_35 (\rd_mux_sel_r_reg[0]_34 ),
        .\rd_mux_sel_r_reg[0]_36 (\rd_mux_sel_r_reg[0]_35 ),
        .\rd_mux_sel_r_reg[0]_37 (\rd_mux_sel_r_reg[0]_36 ),
        .\rd_mux_sel_r_reg[0]_38 (\rd_mux_sel_r_reg[0]_37 ),
        .\rd_mux_sel_r_reg[0]_39 (\rd_mux_sel_r_reg[0]_38 ),
        .\rd_mux_sel_r_reg[0]_4 (\rd_mux_sel_r_reg[0]_3 ),
        .\rd_mux_sel_r_reg[0]_40 (\rd_mux_sel_r_reg[0]_39 ),
        .\rd_mux_sel_r_reg[0]_41 (\rd_mux_sel_r_reg[0]_40 ),
        .\rd_mux_sel_r_reg[0]_42 (\rd_mux_sel_r_reg[0]_41 ),
        .\rd_mux_sel_r_reg[0]_43 (\rd_mux_sel_r_reg[0]_42 ),
        .\rd_mux_sel_r_reg[0]_44 (\rd_mux_sel_r_reg[0]_43 ),
        .\rd_mux_sel_r_reg[0]_45 (\rd_mux_sel_r_reg[0]_44 ),
        .\rd_mux_sel_r_reg[0]_46 (\rd_mux_sel_r_reg[0]_45 ),
        .\rd_mux_sel_r_reg[0]_47 (\rd_mux_sel_r_reg[0]_46 ),
        .\rd_mux_sel_r_reg[0]_48 (\rd_mux_sel_r_reg[0]_47 ),
        .\rd_mux_sel_r_reg[0]_49 (\rd_mux_sel_r_reg[0]_48 ),
        .\rd_mux_sel_r_reg[0]_5 (\rd_mux_sel_r_reg[0]_4 ),
        .\rd_mux_sel_r_reg[0]_50 (\rd_mux_sel_r_reg[0]_49 ),
        .\rd_mux_sel_r_reg[0]_51 (\rd_mux_sel_r_reg[0]_50 ),
        .\rd_mux_sel_r_reg[0]_52 (\rd_mux_sel_r_reg[0]_51 ),
        .\rd_mux_sel_r_reg[0]_53 (\rd_mux_sel_r_reg[0]_52 ),
        .\rd_mux_sel_r_reg[0]_54 (\rd_mux_sel_r_reg[0]_53 ),
        .\rd_mux_sel_r_reg[0]_55 (\rd_mux_sel_r_reg[0]_54 ),
        .\rd_mux_sel_r_reg[0]_56 (\rd_mux_sel_r_reg[0]_55 ),
        .\rd_mux_sel_r_reg[0]_57 (\rd_mux_sel_r_reg[0]_56 ),
        .\rd_mux_sel_r_reg[0]_58 (\rd_mux_sel_r_reg[0]_57 ),
        .\rd_mux_sel_r_reg[0]_59 (\rd_mux_sel_r_reg[0]_58 ),
        .\rd_mux_sel_r_reg[0]_6 (\rd_mux_sel_r_reg[0]_5 ),
        .\rd_mux_sel_r_reg[0]_60 (\rd_mux_sel_r_reg[0]_59 ),
        .\rd_mux_sel_r_reg[0]_61 (\rd_mux_sel_r_reg[0]_60 ),
        .\rd_mux_sel_r_reg[0]_62 (\rd_mux_sel_r_reg[0]_61 ),
        .\rd_mux_sel_r_reg[0]_63 (\rd_mux_sel_r_reg[0]_62 ),
        .\rd_mux_sel_r_reg[0]_7 (\rd_mux_sel_r_reg[0]_6 ),
        .\rd_mux_sel_r_reg[0]_8 (\rd_mux_sel_r_reg[0]_7 ),
        .\rd_mux_sel_r_reg[0]_9 (\rd_mux_sel_r_reg[0]_8 ),
        .\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][4][0] ),
        .rdlvl_last_byte_done(rdlvl_last_byte_done),
        .rdlvl_prech_req(rdlvl_prech_req),
        .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),
        .rdlvl_stg1_start_reg(rdlvl_stg1_start_r_reg),
        .rdlvl_stg1_start_reg_0(cnt_shift_r1545_out),
        .reset_if(reset_if),
        .reset_if_r9(reset_if_r9),
        .reset_if_reg(u_ddr_phy_rdlvl_n_66),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),
        .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24_0),
        .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_1),
        .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_2),
        .rstdiv0_sync_r1_reg_rep__24_2(rstdiv0_sync_r1_reg_rep__24_3),
        .rstdiv0_sync_r1_reg_rep__24_3(rstdiv0_sync_r1_reg_rep__24_4),
        .rstdiv0_sync_r1_reg_rep__24_4(rstdiv0_sync_r1_reg_rep__24_5),
        .rstdiv0_sync_r1_reg_rep__3(rstdiv0_sync_r1_reg_rep__3),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .stg1_wr_done(stg1_wr_done),
        .\stg1_wr_rd_cnt_reg[3] (u_ddr_phy_rdlvl_n_22),
        .tempmon_pi_f_en_r(tempmon_pi_f_en_r),
        .tempmon_pi_f_inc_r(tempmon_pi_f_inc_r),
        .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_6 ),
        .wrcal_done_reg(u_ddr_phy_wrcal_n_14),
        .\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep (u_ddr_phy_rdlvl_n_41),
        .\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] (u_ddr_phy_rdlvl_n_7),
        .\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511] (u_ddr_phy_rdlvl_n_36),
        .wrlvl_done_r1(wrlvl_done_r1));
  mig_7series_0_mig_7series_v2_3_ddr_phy_wrcal u_ddr_phy_wrcal
       (.CLK(CLK),
        .D({u_ddr_phy_wrcal_n_41,u_ddr_phy_wrcal_n_42,u_ddr_phy_wrcal_n_43,u_ddr_phy_wrcal_n_44}),
        .E(u_ddr_phy_wrcal_n_36),
        .Q(Q[1:0]),
        .\cal1_cnt_cpt_r_reg[0] (u_ddr_phy_rdlvl_n_23),
        .\calib_zero_inputs_reg[2] (calib_zero_inputs),
        .\corse_cnt_reg[3][0] (u_ddr_phy_wrcal_n_26),
        .\corse_cnt_reg[3][0]_0 (u_ddr_phy_wrcal_n_27),
        .\corse_cnt_reg[6][0] (u_ddr_phy_wrcal_n_25),
        .\corse_cnt_reg[7][0] (u_ddr_phy_wrcal_n_16),
        .ddr3_lm_done_r(ddr3_lm_done_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dqs_count_r_reg[1] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16 ),
        .\dqs_count_r_reg[2]_rep (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_15 ),
        .\dqs_count_r_reg[2]_rep__0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_13 ),
        .\dqs_count_r_reg[2]_rep__0_0 (u_ddr_phy_rdlvl_n_68),
        .dqs_found_done_r_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72 ),
        .dqs_found_prech_req(dqs_found_prech_req),
        .early1_data(early1_data),
        .early2_data(early2_data),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[3] ({po_stg2_wrcal_cnt,\gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 }),
        .\gen_byte_sel_div2.calib_in_common_reg (calib_in_common),
        .idelay_ce_int(idelay_ce_int),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .idelay_ld_rst_7(idelay_ld_rst_7),
        .idelay_ld_rst_8(idelay_ld_rst_8),
        .\idelay_tap_cnt_r_reg[0][0][0] (u_ddr_phy_wrcal_n_22),
        .\idelay_tap_cnt_r_reg[0][0][0]_0 (u_ddr_phy_wrcal_n_32),
        .\idelay_tap_cnt_r_reg[0][1][0] (u_ddr_phy_wrcal_n_33),
        .\idelay_tap_cnt_r_reg[0][2][0] (u_ddr_phy_wrcal_n_34),
        .\idelay_tap_cnt_r_reg[0][3][0] (u_ddr_phy_wrcal_n_35),
        .\idelay_tap_cnt_r_reg[0][7][4] (u_ddr_phy_wrcal_n_21),
        .\init_state_r_reg[0] (u_ddr_phy_wrcal_n_13),
        .\init_state_r_reg[2] (u_ddr_phy_wrcal_n_15),
        .\init_state_r_reg[5] (u_ddr_phy_wrcal_n_24),
        .\init_state_r_reg[5]_0 (u_ddr_phy_init_n_22),
        .mem_init_done_r(mem_init_done_r),
        .p_0_out(p_0_out),
        .phy_if_reset_w(phy_if_reset_w),
        .phy_rddata_en(phy_rddata_en),
        .\po_stg2_wrcal_cnt_reg[0]_0 (\po_stg2_wrcal_cnt_reg[0] ),
        .\po_stg2_wrcal_cnt_reg[0]_1 (\po_stg2_wrcal_cnt_reg[0]_0 ),
        .\po_stg2_wrcal_cnt_reg[0]_10 (\po_stg2_wrcal_cnt_reg[0]_9 ),
        .\po_stg2_wrcal_cnt_reg[0]_11 (\po_stg2_wrcal_cnt_reg[0]_10 ),
        .\po_stg2_wrcal_cnt_reg[0]_12 (\po_stg2_wrcal_cnt_reg[0]_11 ),
        .\po_stg2_wrcal_cnt_reg[0]_13 (\po_stg2_wrcal_cnt_reg[0]_12 ),
        .\po_stg2_wrcal_cnt_reg[0]_14 (\po_stg2_wrcal_cnt_reg[0]_13 ),
        .\po_stg2_wrcal_cnt_reg[0]_15 (\po_stg2_wrcal_cnt_reg[0]_14 ),
        .\po_stg2_wrcal_cnt_reg[0]_16 (\po_stg2_wrcal_cnt_reg[0]_15 ),
        .\po_stg2_wrcal_cnt_reg[0]_17 (\po_stg2_wrcal_cnt_reg[0]_16 ),
        .\po_stg2_wrcal_cnt_reg[0]_18 (\po_stg2_wrcal_cnt_reg[0]_17 ),
        .\po_stg2_wrcal_cnt_reg[0]_19 (\po_stg2_wrcal_cnt_reg[0]_18 ),
        .\po_stg2_wrcal_cnt_reg[0]_2 (\po_stg2_wrcal_cnt_reg[0]_1 ),
        .\po_stg2_wrcal_cnt_reg[0]_20 (\po_stg2_wrcal_cnt_reg[0]_19 ),
        .\po_stg2_wrcal_cnt_reg[0]_21 (\po_stg2_wrcal_cnt_reg[0]_20 ),
        .\po_stg2_wrcal_cnt_reg[0]_22 (\po_stg2_wrcal_cnt_reg[0]_21 ),
        .\po_stg2_wrcal_cnt_reg[0]_23 (\po_stg2_wrcal_cnt_reg[0]_22 ),
        .\po_stg2_wrcal_cnt_reg[0]_24 (\po_stg2_wrcal_cnt_reg[0]_23 ),
        .\po_stg2_wrcal_cnt_reg[0]_25 (\po_stg2_wrcal_cnt_reg[0]_24 ),
        .\po_stg2_wrcal_cnt_reg[0]_26 (\po_stg2_wrcal_cnt_reg[0]_25 ),
        .\po_stg2_wrcal_cnt_reg[0]_27 (\po_stg2_wrcal_cnt_reg[0]_26 ),
        .\po_stg2_wrcal_cnt_reg[0]_28 (\po_stg2_wrcal_cnt_reg[0]_27 ),
        .\po_stg2_wrcal_cnt_reg[0]_29 (\po_stg2_wrcal_cnt_reg[0]_28 ),
        .\po_stg2_wrcal_cnt_reg[0]_3 (\po_stg2_wrcal_cnt_reg[0]_2 ),
        .\po_stg2_wrcal_cnt_reg[0]_30 (\po_stg2_wrcal_cnt_reg[0]_29 ),
        .\po_stg2_wrcal_cnt_reg[0]_31 (\po_stg2_wrcal_cnt_reg[0]_30 ),
        .\po_stg2_wrcal_cnt_reg[0]_32 (\po_stg2_wrcal_cnt_reg[0]_31 ),
        .\po_stg2_wrcal_cnt_reg[0]_33 (\po_stg2_wrcal_cnt_reg[0]_32 ),
        .\po_stg2_wrcal_cnt_reg[0]_34 (\po_stg2_wrcal_cnt_reg[0]_33 ),
        .\po_stg2_wrcal_cnt_reg[0]_35 (\po_stg2_wrcal_cnt_reg[0]_34 ),
        .\po_stg2_wrcal_cnt_reg[0]_36 (\po_stg2_wrcal_cnt_reg[0]_35 ),
        .\po_stg2_wrcal_cnt_reg[0]_37 (\po_stg2_wrcal_cnt_reg[0]_36 ),
        .\po_stg2_wrcal_cnt_reg[0]_38 (\po_stg2_wrcal_cnt_reg[0]_37 ),
        .\po_stg2_wrcal_cnt_reg[0]_39 (\po_stg2_wrcal_cnt_reg[0]_38 ),
        .\po_stg2_wrcal_cnt_reg[0]_4 (\po_stg2_wrcal_cnt_reg[0]_3 ),
        .\po_stg2_wrcal_cnt_reg[0]_40 (\po_stg2_wrcal_cnt_reg[0]_39 ),
        .\po_stg2_wrcal_cnt_reg[0]_41 (\po_stg2_wrcal_cnt_reg[0]_40 ),
        .\po_stg2_wrcal_cnt_reg[0]_42 (\po_stg2_wrcal_cnt_reg[0]_41 ),
        .\po_stg2_wrcal_cnt_reg[0]_43 (\po_stg2_wrcal_cnt_reg[0]_42 ),
        .\po_stg2_wrcal_cnt_reg[0]_44 (\po_stg2_wrcal_cnt_reg[0]_43 ),
        .\po_stg2_wrcal_cnt_reg[0]_45 (\po_stg2_wrcal_cnt_reg[0]_44 ),
        .\po_stg2_wrcal_cnt_reg[0]_46 (\po_stg2_wrcal_cnt_reg[0]_45 ),
        .\po_stg2_wrcal_cnt_reg[0]_47 (\po_stg2_wrcal_cnt_reg[0]_46 ),
        .\po_stg2_wrcal_cnt_reg[0]_48 (\po_stg2_wrcal_cnt_reg[0]_47 ),
        .\po_stg2_wrcal_cnt_reg[0]_49 (\po_stg2_wrcal_cnt_reg[0]_48 ),
        .\po_stg2_wrcal_cnt_reg[0]_5 (\po_stg2_wrcal_cnt_reg[0]_4 ),
        .\po_stg2_wrcal_cnt_reg[0]_50 (\po_stg2_wrcal_cnt_reg[0]_49 ),
        .\po_stg2_wrcal_cnt_reg[0]_51 (\po_stg2_wrcal_cnt_reg[0]_50 ),
        .\po_stg2_wrcal_cnt_reg[0]_52 (\po_stg2_wrcal_cnt_reg[0]_51 ),
        .\po_stg2_wrcal_cnt_reg[0]_53 (\po_stg2_wrcal_cnt_reg[0]_52 ),
        .\po_stg2_wrcal_cnt_reg[0]_54 (\po_stg2_wrcal_cnt_reg[0]_53 ),
        .\po_stg2_wrcal_cnt_reg[0]_55 (\po_stg2_wrcal_cnt_reg[0]_54 ),
        .\po_stg2_wrcal_cnt_reg[0]_56 (\po_stg2_wrcal_cnt_reg[0]_55 ),
        .\po_stg2_wrcal_cnt_reg[0]_57 (\po_stg2_wrcal_cnt_reg[0]_56 ),
        .\po_stg2_wrcal_cnt_reg[0]_58 (\po_stg2_wrcal_cnt_reg[0]_57 ),
        .\po_stg2_wrcal_cnt_reg[0]_59 (\po_stg2_wrcal_cnt_reg[0]_58 ),
        .\po_stg2_wrcal_cnt_reg[0]_6 (\po_stg2_wrcal_cnt_reg[0]_5 ),
        .\po_stg2_wrcal_cnt_reg[0]_60 (\po_stg2_wrcal_cnt_reg[0]_59 ),
        .\po_stg2_wrcal_cnt_reg[0]_61 (\po_stg2_wrcal_cnt_reg[0]_60 ),
        .\po_stg2_wrcal_cnt_reg[0]_62 (\po_stg2_wrcal_cnt_reg[0]_61 ),
        .\po_stg2_wrcal_cnt_reg[0]_7 (\po_stg2_wrcal_cnt_reg[0]_6 ),
        .\po_stg2_wrcal_cnt_reg[0]_8 (\po_stg2_wrcal_cnt_reg[0]_7 ),
        .\po_stg2_wrcal_cnt_reg[0]_9 (\po_stg2_wrcal_cnt_reg[0]_8 ),
        .prech_done(prech_done),
        .prech_req(prech_req),
        .prech_req_posedge_r_reg(u_ddr_phy_init_n_4),
        .rd_active_r(rd_active_r),
        .rdlvl_prech_req(rdlvl_prech_req),
        .rdlvl_stg1_done_reg(u_ddr_phy_rdlvl_n_7),
        .rdlvl_stg1_done_reg_0(u_ddr_phy_rdlvl_n_67),
        .rdlvl_stg1_done_reg_1(u_ddr_phy_rdlvl_n_69),
        .rdlvl_stg1_done_reg_2(u_ddr_phy_rdlvl_n_70),
        .\rnk_cnt_r_reg[0] (u_ddr_phy_rdlvl_n_25),
        .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__3(rstdiv0_sync_r1_reg_rep__3),
        .wl_sm_start(wl_sm_start),
        .\wl_state_r_reg[0] (u_ddr_phy_wrcal_n_29),
        .\wl_state_r_reg[2] (u_ddr_phy_wrcal_n_30),
        .\wl_state_r_reg[2]_0 (u_ddr_phy_wrcal_n_31),
        .\wl_state_r_reg[4] ({\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_9 ,\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 }),
        .wr_level_done0(wr_level_done0),
        .wr_level_done_r5(wr_level_done_r5),
        .wr_level_done_r5_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17 ),
        .wr_level_done_reg(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_6 ),
        .wrcal_done_reg_0(u_ddr_phy_wrcal_n_14),
        .wrcal_prech_req(wrcal_prech_req),
        .wrcal_rd_wait(wrcal_rd_wait),
        .wrcal_resume_w(wrcal_resume_w),
        .wrcal_sanity_chk(wrcal_sanity_chk),
        .wrcal_sanity_chk_done(wrcal_sanity_chk_done),
        .wrcal_sanity_chk_r(wrcal_sanity_chk_r),
        .wrcal_sanity_chk_reg(u_ddr_phy_init_n_888),
        .wrcal_start_reg(u_ddr_phy_init_n_907),
        .wrlvl_byte_done(wrlvl_byte_done),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_byte_redo_r(wrlvl_byte_redo_r),
        .wrlvl_done_r1(wrlvl_done_r1));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo
   (\rd_ptr_timing_reg[1]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ,
    \not_strict_mode.app_rd_data_reg[495] ,
    \not_strict_mode.app_rd_data_reg[232] ,
    \my_empty_reg[3]_0 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    Q,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    ififo_rd_en_in,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    ififo_rst,
    CLK);
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[495] ;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output [1:0]\my_empty_reg[3]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input [63:0]Q;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input ififo_rd_en_in;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input ififo_rst;
  input CLK;

  wire CLK;
  wire [63:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  wire ififo_rd_en_in;
  wire ififo_rst;
  wire [4:1]my_empty;
  wire my_empty0;
  wire \my_empty[0]_i_1_n_0 ;
  wire \my_empty[1]_i_1__4_n_0 ;
  wire \my_empty[2]_i_1_n_0 ;
  wire \my_empty[3]_i_1_n_0 ;
  wire \my_empty[4]_i_1_n_0 ;
  wire \my_empty[4]_i_2__4_n_0 ;
  wire \my_empty[4]_i_3_n_0 ;
  wire \my_empty[4]_rep__0_i_1__0_n_0 ;
  wire \my_empty[4]_rep__1_i_1__0_n_0 ;
  wire \my_empty[4]_rep_i_1__0_n_0 ;
  wire [1:0]\my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire my_full0;
  wire \my_full[0]_i_1__4_n_0 ;
  wire \my_full[1]_i_1__4_n_0 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[495] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__1_n_0 ;
  wire \rd_ptr[1]_i_1__1_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1_n_0 ;
  wire \rd_ptr_timing[1]_i_1__4_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire \wr_ptr[0]_i_1__14_n_0 ;
  wire \wr_ptr[1]_i_1__14_n_0 ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1]_0 ;

  assign \rd_ptr_timing_reg[1]_0 [1:0] = rd_ptr_timing;
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[5].rd_data_rise_wl_r[5]_i_1 
       (.I0(\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .I1(\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .I2(\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .I3(\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .I4(\gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0 ),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[5].rd_data_rise_wl_r[5]_i_2 
       (.I0(\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .I1(Q[32]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [32]),
        .I4(\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .I5(\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .O(\gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0407)) 
    mem_reg_0_3_6_11_i_1__2
       (.I0(my_empty[2]),
        .I1(ififo_rd_en_in),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[0]),
        .O(\not_strict_mode.app_rd_data_reg[232] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[0]_i_1 
       (.I0(\my_empty_reg[3]_0 [0]),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__4_n_0 ),
        .O(\my_empty[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair736" *) 
  LUT5 #(
    .INIT(32'hF2E0F0E0)) 
    \my_empty[1]_i_1__4 
       (.I0(ififo_rd_en_in),
        .I1(my_full[1]),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty0),
        .O(\my_empty[1]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair737" *) 
  LUT4 #(
    .INIT(16'h4218)) 
    \my_empty[1]_i_2__2 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(\wr_ptr_reg[1]_0 ),
        .O(my_empty0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBD0000)) 
    \my_empty[2]_i_1 
       (.I0(my_empty[1]),
        .I1(ififo_rd_en_in),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[1]),
        .I4(my_empty[2]),
        .I5(\my_empty[4]_i_2__4_n_0 ),
        .O(\my_empty[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[3]_i_1 
       (.I0(\my_empty_reg[3]_0 [1]),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__4_n_0 ),
        .O(\my_empty[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_i_1 
       (.I0(my_empty[4]),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__4_n_0 ),
        .O(\my_empty[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010040140)) 
    \my_empty[4]_i_2__4 
       (.I0(\my_empty[4]_i_3_n_0 ),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(\wr_ptr_reg[0]_0 ),
        .I4(\wr_ptr_reg[1]_0 ),
        .I5(my_empty[1]),
        .O(\my_empty[4]_i_2__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair736" *) 
  LUT4 #(
    .INIT(16'hFFBD)) 
    \my_empty[4]_i_3 
       (.I0(my_empty[1]),
        .I1(ififo_rd_en_in),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_rep__0_i_1__0 
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__4_n_0 ),
        .O(\my_empty[4]_rep__0_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_rep__1_i_1__0 
       (.I0(\my_empty_reg[4]_rep__1_n_0 ),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__4_n_0 ),
        .O(\my_empty[4]_rep__1_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_rep_i_1__0 
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__4_n_0 ),
        .O(\my_empty[4]_rep_i_1__0_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[0]_i_1_n_0 ),
        .Q(\my_empty_reg[3]_0 [0]),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__4_n_0 ),
        .Q(my_empty[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1_n_0 ),
        .Q(my_empty[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1_n_0 ),
        .Q(\my_empty_reg[3]_0 [1]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1_n_0 ),
        .Q(my_empty[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__0_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__1_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAA2AABAAAA2AA8)) 
    \my_full[0]_i_1__4 
       (.I0(my_full[0]),
        .I1(my_full[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty[1]),
        .I5(my_full0),
        .O(\my_full[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hFF007710)) 
    \my_full[1]_i_1__4 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I1(ififo_rd_en_in),
        .I2(my_full0),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .O(\my_full[1]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair737" *) 
  LUT4 #(
    .INIT(16'h2442)) 
    \my_full[1]_i_2__6 
       (.I0(rd_ptr[0]),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(\wr_ptr_reg[1]_0 ),
        .I3(rd_ptr[1]),
        .O(my_full0));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__4_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1__4_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[104]_i_1 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [57]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[105]_i_1 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [49]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[106]_i_1 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [41]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[107]_i_1 
       (.I0(Q[33]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [33]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [11]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[108]_i_1 
       (.I0(Q[25]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [25]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[109]_i_1 
       (.I0(Q[17]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [17]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[110]_i_1 
       (.I0(Q[9]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [9]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[111]_i_1 
       (.I0(Q[1]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [1]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [15]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[168]_i_1 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [58]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[169]_i_1 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [50]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[170]_i_1 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [42]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[171]_i_1 
       (.I0(Q[34]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [34]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[172]_i_1 
       (.I0(Q[26]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [26]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[173]_i_1 
       (.I0(Q[18]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [18]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[174]_i_1 
       (.I0(Q[10]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [10]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[175]_i_1 
       (.I0(Q[2]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [2]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[232]_i_1 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [59]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[233]_i_1 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [51]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[234]_i_1 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [43]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[235]_i_1 
       (.I0(Q[35]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [35]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[236]_i_1 
       (.I0(Q[27]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [27]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[237]_i_1 
       (.I0(Q[19]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [19]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[238]_i_1 
       (.I0(Q[11]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [11]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[239]_i_1 
       (.I0(Q[3]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [3]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[296]_i_1 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [60]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[297]_i_1 
       (.I0(Q[52]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [52]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[298]_i_1 
       (.I0(Q[44]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [44]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[299]_i_1 
       (.I0(Q[36]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [36]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[300]_i_1 
       (.I0(Q[28]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [28]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[301]_i_1 
       (.I0(Q[20]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [20]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[302]_i_1 
       (.I0(Q[12]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [12]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[303]_i_1 
       (.I0(Q[4]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [4]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[360]_i_1 
       (.I0(Q[61]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [61]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[361]_i_1 
       (.I0(Q[53]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [53]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[362]_i_1 
       (.I0(Q[45]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [45]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[363]_i_1 
       (.I0(Q[37]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [37]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[364]_i_1 
       (.I0(Q[29]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [29]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[365]_i_1 
       (.I0(Q[21]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [21]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[366]_i_1 
       (.I0(Q[13]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [13]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[367]_i_1 
       (.I0(Q[5]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [5]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[40]_i_1 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [56]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[41]_i_1 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [48]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[424]_i_1 
       (.I0(Q[62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [62]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[425]_i_1 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [54]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[426]_i_1 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [46]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[427]_i_1 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [38]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[428]_i_1 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [30]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[429]_i_1 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [22]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[42]_i_1 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [40]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[430]_i_1 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [14]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[431]_i_1 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [6]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[43]_i_1 
       (.I0(Q[32]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [32]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[44]_i_1 
       (.I0(Q[24]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [24]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[45]_i_1 
       (.I0(Q[16]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [16]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[46]_i_1 
       (.I0(Q[8]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [8]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[47]_i_1 
       (.I0(Q[0]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [0]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [7]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[488]_i_1 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [63]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[489]_i_1 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [55]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[490]_i_1 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [47]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[491]_i_1 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [39]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[492]_i_1 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [31]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[493]_i_1 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [23]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[494]_i_1 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [15]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),
        .O(\not_strict_mode.app_rd_data_reg[495] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[495]_i_1 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [7]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),
        .O(\not_strict_mode.app_rd_data_reg[495] [63]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1 
       (.I0(Q[33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [33]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2 
       (.I0(Q[41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [41]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3 
       (.I0(Q[49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [49]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4 
       (.I0(Q[57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [57]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3 
       (.I0(Q[1]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [1]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4 
       (.I0(Q[9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5 
       (.I0(Q[17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [17]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_6 
       (.I0(Q[25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1 
       (.I0(Q[18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [18]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2 
       (.I0(Q[26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3 
       (.I0(Q[34]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [34]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4 
       (.I0(Q[42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [42]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5 
       (.I0(Q[50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [50]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_6 
       (.I0(Q[58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [58]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5 
       (.I0(Q[2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [2]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_6 
       (.I0(Q[10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1 
       (.I0(Q[51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [51]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2 
       (.I0(Q[59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [59]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1 
       (.I0(Q[3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [3]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2 
       (.I0(Q[11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3 
       (.I0(Q[19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [19]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4 
       (.I0(Q[27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5 
       (.I0(Q[35]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [35]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_6 
       (.I0(Q[43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [43]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1 
       (.I0(Q[36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [36]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2 
       (.I0(Q[44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [44]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3 
       (.I0(Q[52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [52]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4 
       (.I0(Q[60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [60]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3 
       (.I0(Q[4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [4]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4 
       (.I0(Q[12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5 
       (.I0(Q[20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [20]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_6 
       (.I0(Q[28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1 
       (.I0(Q[21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [21]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2 
       (.I0(Q[29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3 
       (.I0(Q[37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [37]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4 
       (.I0(Q[45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [45]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5 
       (.I0(Q[53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [53]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_6 
       (.I0(Q[61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [61]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5 
       (.I0(Q[5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [5]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_6 
       (.I0(Q[13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1 
       (.I0(Q[48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [48]),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2 
       (.I0(Q[56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [56]),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [54]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2 
       (.I0(Q[62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [62]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [6]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [22]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [38]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_6 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [46]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1 
       (.I0(Q[0]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [0]),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2 
       (.I0(Q[8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [8]),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3 
       (.I0(Q[16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [16]),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4 
       (.I0(Q[24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [24]),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5 
       (.I0(Q[32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [32]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_6 
       (.I0(Q[40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [40]),
        .O(\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [39]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [47]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [55]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [63]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [7]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [23]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_6 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair738" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr[0]_i_1__1 
       (.I0(my_empty[1]),
        .I1(ififo_rd_en_in),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair738" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__1 
       (.I0(rd_ptr[0]),
        .I1(ififo_rd_en_in),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__1_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__1_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__1_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'h8ABA)) 
    \rd_ptr_timing[0]_i_1 
       (.I0(rd_ptr_timing[0]),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hD0F2F2D0)) 
    \rd_ptr_timing[1]_i_1__4 
       (.I0(ififo_rd_en_in),
        .I1(my_empty[1]),
        .I2(rd_ptr_timing[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[1]),
        .O(\rd_ptr_timing[1]_i_1__4_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__4_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFDF80207)) 
    \wr_ptr[0]_i_1__14 
       (.I0(ififo_rd_en_in),
        .I1(my_empty[1]),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[1]),
        .I4(\wr_ptr_reg[0]_0 ),
        .O(\wr_ptr[0]_i_1__14_n_0 ));
  LUT6 #(
    .INIT(64'hFFF5FDFD000A0202)) 
    \wr_ptr[1]_i_1__14 
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(my_full[1]),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_empty[1]),
        .I4(ififo_rd_en_in),
        .I5(\wr_ptr_reg[1]_0 ),
        .O(\wr_ptr[1]_i_1__14_n_0 ));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__14_n_0 ),
        .Q(\wr_ptr_reg[0]_0 ),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__14_n_0 ),
        .Q(\wr_ptr_reg[1]_0 ),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_10
   (Q,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    DIB,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[471] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    p_0_out,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    B_byte_rd_en,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    C_byte_rd_en,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[1] ,
    DIA,
    DIC,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \rd_mux_sel_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \rd_mux_sel_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \rd_mux_sel_r_reg[1]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \rd_mux_sel_r_reg[1]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \rd_mux_sel_r_reg[1]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \rd_mux_sel_r_reg[1]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \rd_mux_sel_r_reg[1]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \rd_mux_sel_r_reg[1]_7 ,
    \rd_mux_sel_r_reg[1]_8 ,
    \rd_mux_sel_r_reg[1]_9 ,
    \rd_mux_sel_r_reg[1]_10 ,
    \rd_mux_sel_r_reg[1]_11 ,
    \rd_mux_sel_r_reg[1]_12 ,
    \rd_mux_sel_r_reg[1]_13 ,
    \rd_mux_sel_r_reg[1]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \rd_mux_sel_r_reg[1]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \rd_mux_sel_r_reg[1]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \rd_mux_sel_r_reg[1]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \rd_mux_sel_r_reg[1]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \rd_mux_sel_r_reg[1]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \rd_mux_sel_r_reg[1]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \rd_mux_sel_r_reg[1]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \rd_mux_sel_r_reg[1]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \rd_mux_sel_r_reg[1]_23 ,
    \rd_mux_sel_r_reg[1]_24 ,
    \rd_mux_sel_r_reg[1]_25 ,
    \rd_mux_sel_r_reg[1]_26 ,
    \rd_mux_sel_r_reg[1]_27 ,
    \rd_mux_sel_r_reg[1]_28 ,
    \rd_mux_sel_r_reg[1]_29 ,
    \rd_mux_sel_r_reg[1]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \rd_mux_sel_r_reg[1]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \rd_mux_sel_r_reg[1]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \rd_mux_sel_r_reg[1]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \rd_mux_sel_r_reg[1]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \rd_mux_sel_r_reg[1]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \rd_mux_sel_r_reg[1]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \rd_mux_sel_r_reg[1]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \rd_mux_sel_r_reg[1]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \rd_mux_sel_r_reg[1]_39 ,
    \rd_mux_sel_r_reg[1]_40 ,
    \rd_mux_sel_r_reg[1]_41 ,
    \rd_mux_sel_r_reg[1]_42 ,
    \rd_mux_sel_r_reg[1]_43 ,
    \rd_mux_sel_r_reg[1]_44 ,
    \rd_mux_sel_r_reg[1]_45 ,
    \rd_mux_sel_r_reg[1]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \rd_mux_sel_r_reg[1]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \rd_mux_sel_r_reg[1]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \rd_mux_sel_r_reg[1]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \rd_mux_sel_r_reg[1]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \rd_mux_sel_r_reg[1]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \rd_mux_sel_r_reg[1]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \rd_mux_sel_r_reg[1]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \rd_mux_sel_r_reg[1]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \rd_mux_sel_r_reg[1]_55 ,
    \rd_mux_sel_r_reg[1]_56 ,
    \rd_mux_sel_r_reg[1]_57 ,
    \rd_mux_sel_r_reg[1]_58 ,
    \rd_mux_sel_r_reg[1]_59 ,
    \rd_mux_sel_r_reg[1]_60 ,
    \rd_mux_sel_r_reg[1]_61 ,
    \rd_mux_sel_r_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[1]_0 ,
    \po_stg2_wrcal_cnt_reg[1]_1 ,
    \po_stg2_wrcal_cnt_reg[1]_2 ,
    \po_stg2_wrcal_cnt_reg[1]_3 ,
    \po_stg2_wrcal_cnt_reg[1]_4 ,
    \po_stg2_wrcal_cnt_reg[1]_5 ,
    \po_stg2_wrcal_cnt_reg[1]_6 ,
    \po_stg2_wrcal_cnt_reg[1]_7 ,
    \po_stg2_wrcal_cnt_reg[1]_8 ,
    \po_stg2_wrcal_cnt_reg[1]_9 ,
    \po_stg2_wrcal_cnt_reg[1]_10 ,
    \po_stg2_wrcal_cnt_reg[1]_11 ,
    \po_stg2_wrcal_cnt_reg[1]_12 ,
    \po_stg2_wrcal_cnt_reg[1]_13 ,
    \po_stg2_wrcal_cnt_reg[1]_14 ,
    \po_stg2_wrcal_cnt_reg[1]_15 ,
    \po_stg2_wrcal_cnt_reg[1]_16 ,
    \po_stg2_wrcal_cnt_reg[1]_17 ,
    \po_stg2_wrcal_cnt_reg[1]_18 ,
    \po_stg2_wrcal_cnt_reg[1]_19 ,
    \po_stg2_wrcal_cnt_reg[1]_20 ,
    \po_stg2_wrcal_cnt_reg[1]_21 ,
    \po_stg2_wrcal_cnt_reg[1]_22 ,
    \po_stg2_wrcal_cnt_reg[1]_23 ,
    \po_stg2_wrcal_cnt_reg[1]_24 ,
    \po_stg2_wrcal_cnt_reg[1]_25 ,
    \po_stg2_wrcal_cnt_reg[1]_26 ,
    \po_stg2_wrcal_cnt_reg[1]_27 ,
    \po_stg2_wrcal_cnt_reg[1]_28 ,
    \po_stg2_wrcal_cnt_reg[1]_29 ,
    \po_stg2_wrcal_cnt_reg[1]_30 ,
    \po_stg2_wrcal_cnt_reg[1]_31 ,
    \po_stg2_wrcal_cnt_reg[1]_32 ,
    \po_stg2_wrcal_cnt_reg[1]_33 ,
    \po_stg2_wrcal_cnt_reg[1]_34 ,
    \po_stg2_wrcal_cnt_reg[1]_35 ,
    \po_stg2_wrcal_cnt_reg[1]_36 ,
    \po_stg2_wrcal_cnt_reg[1]_37 ,
    \po_stg2_wrcal_cnt_reg[1]_38 ,
    \po_stg2_wrcal_cnt_reg[1]_39 ,
    \po_stg2_wrcal_cnt_reg[1]_40 ,
    \po_stg2_wrcal_cnt_reg[1]_41 ,
    \po_stg2_wrcal_cnt_reg[1]_42 ,
    \po_stg2_wrcal_cnt_reg[1]_43 ,
    \po_stg2_wrcal_cnt_reg[1]_44 ,
    \po_stg2_wrcal_cnt_reg[1]_45 ,
    \po_stg2_wrcal_cnt_reg[1]_46 ,
    \po_stg2_wrcal_cnt_reg[1]_47 ,
    \po_stg2_wrcal_cnt_reg[1]_48 ,
    \po_stg2_wrcal_cnt_reg[1]_49 ,
    \po_stg2_wrcal_cnt_reg[1]_50 ,
    \po_stg2_wrcal_cnt_reg[1]_51 ,
    \po_stg2_wrcal_cnt_reg[1]_52 ,
    \po_stg2_wrcal_cnt_reg[1]_53 ,
    \po_stg2_wrcal_cnt_reg[1]_54 ,
    \po_stg2_wrcal_cnt_reg[1]_55 ,
    \po_stg2_wrcal_cnt_reg[1]_56 ,
    \po_stg2_wrcal_cnt_reg[1]_57 ,
    \po_stg2_wrcal_cnt_reg[1]_58 ,
    \po_stg2_wrcal_cnt_reg[1]_59 ,
    \po_stg2_wrcal_cnt_reg[1]_60 ,
    \po_stg2_wrcal_cnt_reg[1]_61 ,
    \po_stg2_wrcal_cnt_reg[1]_62 ,
    ififo_rst,
    CLK);
  output [1:0]Q;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]DIB;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [63:0]\not_strict_mode.app_rd_data_reg[471] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output p_0_out;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output B_byte_rd_en;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  input C_byte_rd_en;
  input [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [2:0]\rd_mux_sel_r_reg[2] ;
  input \rd_mux_sel_r_reg[1] ;
  input [1:0]DIA;
  input [1:0]DIC;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  input \rd_mux_sel_r_reg[1]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  input \rd_mux_sel_r_reg[1]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input \rd_mux_sel_r_reg[1]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  input \rd_mux_sel_r_reg[1]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  input \rd_mux_sel_r_reg[1]_4 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  input \rd_mux_sel_r_reg[1]_5 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  input \rd_mux_sel_r_reg[1]_6 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  input \rd_mux_sel_r_reg[1]_7 ;
  input \rd_mux_sel_r_reg[1]_8 ;
  input \rd_mux_sel_r_reg[1]_9 ;
  input \rd_mux_sel_r_reg[1]_10 ;
  input \rd_mux_sel_r_reg[1]_11 ;
  input \rd_mux_sel_r_reg[1]_12 ;
  input \rd_mux_sel_r_reg[1]_13 ;
  input \rd_mux_sel_r_reg[1]_14 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input \rd_mux_sel_r_reg[1]_15 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  input \rd_mux_sel_r_reg[1]_16 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  input \rd_mux_sel_r_reg[1]_17 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  input \rd_mux_sel_r_reg[1]_18 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  input \rd_mux_sel_r_reg[1]_19 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  input \rd_mux_sel_r_reg[1]_20 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  input \rd_mux_sel_r_reg[1]_21 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  input \rd_mux_sel_r_reg[1]_22 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input \rd_mux_sel_r_reg[1]_23 ;
  input \rd_mux_sel_r_reg[1]_24 ;
  input \rd_mux_sel_r_reg[1]_25 ;
  input \rd_mux_sel_r_reg[1]_26 ;
  input \rd_mux_sel_r_reg[1]_27 ;
  input \rd_mux_sel_r_reg[1]_28 ;
  input \rd_mux_sel_r_reg[1]_29 ;
  input \rd_mux_sel_r_reg[1]_30 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  input \rd_mux_sel_r_reg[1]_31 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  input \rd_mux_sel_r_reg[1]_32 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  input \rd_mux_sel_r_reg[1]_33 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  input \rd_mux_sel_r_reg[1]_34 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  input \rd_mux_sel_r_reg[1]_35 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  input \rd_mux_sel_r_reg[1]_36 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  input \rd_mux_sel_r_reg[1]_37 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  input \rd_mux_sel_r_reg[1]_38 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  input \rd_mux_sel_r_reg[1]_39 ;
  input \rd_mux_sel_r_reg[1]_40 ;
  input \rd_mux_sel_r_reg[1]_41 ;
  input \rd_mux_sel_r_reg[1]_42 ;
  input \rd_mux_sel_r_reg[1]_43 ;
  input \rd_mux_sel_r_reg[1]_44 ;
  input \rd_mux_sel_r_reg[1]_45 ;
  input \rd_mux_sel_r_reg[1]_46 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input \rd_mux_sel_r_reg[1]_47 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  input \rd_mux_sel_r_reg[1]_48 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  input \rd_mux_sel_r_reg[1]_49 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  input \rd_mux_sel_r_reg[1]_50 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  input \rd_mux_sel_r_reg[1]_51 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  input \rd_mux_sel_r_reg[1]_52 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  input \rd_mux_sel_r_reg[1]_53 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  input \rd_mux_sel_r_reg[1]_54 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input \rd_mux_sel_r_reg[1]_55 ;
  input \rd_mux_sel_r_reg[1]_56 ;
  input \rd_mux_sel_r_reg[1]_57 ;
  input \rd_mux_sel_r_reg[1]_58 ;
  input \rd_mux_sel_r_reg[1]_59 ;
  input \rd_mux_sel_r_reg[1]_60 ;
  input \rd_mux_sel_r_reg[1]_61 ;
  input \rd_mux_sel_r_reg[1]_62 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  input \po_stg2_wrcal_cnt_reg[1] ;
  input \po_stg2_wrcal_cnt_reg[1]_0 ;
  input \po_stg2_wrcal_cnt_reg[1]_1 ;
  input \po_stg2_wrcal_cnt_reg[1]_2 ;
  input \po_stg2_wrcal_cnt_reg[1]_3 ;
  input \po_stg2_wrcal_cnt_reg[1]_4 ;
  input \po_stg2_wrcal_cnt_reg[1]_5 ;
  input \po_stg2_wrcal_cnt_reg[1]_6 ;
  input \po_stg2_wrcal_cnt_reg[1]_7 ;
  input \po_stg2_wrcal_cnt_reg[1]_8 ;
  input \po_stg2_wrcal_cnt_reg[1]_9 ;
  input \po_stg2_wrcal_cnt_reg[1]_10 ;
  input \po_stg2_wrcal_cnt_reg[1]_11 ;
  input \po_stg2_wrcal_cnt_reg[1]_12 ;
  input \po_stg2_wrcal_cnt_reg[1]_13 ;
  input \po_stg2_wrcal_cnt_reg[1]_14 ;
  input \po_stg2_wrcal_cnt_reg[1]_15 ;
  input \po_stg2_wrcal_cnt_reg[1]_16 ;
  input \po_stg2_wrcal_cnt_reg[1]_17 ;
  input \po_stg2_wrcal_cnt_reg[1]_18 ;
  input \po_stg2_wrcal_cnt_reg[1]_19 ;
  input \po_stg2_wrcal_cnt_reg[1]_20 ;
  input \po_stg2_wrcal_cnt_reg[1]_21 ;
  input \po_stg2_wrcal_cnt_reg[1]_22 ;
  input \po_stg2_wrcal_cnt_reg[1]_23 ;
  input \po_stg2_wrcal_cnt_reg[1]_24 ;
  input \po_stg2_wrcal_cnt_reg[1]_25 ;
  input \po_stg2_wrcal_cnt_reg[1]_26 ;
  input \po_stg2_wrcal_cnt_reg[1]_27 ;
  input \po_stg2_wrcal_cnt_reg[1]_28 ;
  input \po_stg2_wrcal_cnt_reg[1]_29 ;
  input \po_stg2_wrcal_cnt_reg[1]_30 ;
  input \po_stg2_wrcal_cnt_reg[1]_31 ;
  input \po_stg2_wrcal_cnt_reg[1]_32 ;
  input \po_stg2_wrcal_cnt_reg[1]_33 ;
  input \po_stg2_wrcal_cnt_reg[1]_34 ;
  input \po_stg2_wrcal_cnt_reg[1]_35 ;
  input \po_stg2_wrcal_cnt_reg[1]_36 ;
  input \po_stg2_wrcal_cnt_reg[1]_37 ;
  input \po_stg2_wrcal_cnt_reg[1]_38 ;
  input \po_stg2_wrcal_cnt_reg[1]_39 ;
  input \po_stg2_wrcal_cnt_reg[1]_40 ;
  input \po_stg2_wrcal_cnt_reg[1]_41 ;
  input \po_stg2_wrcal_cnt_reg[1]_42 ;
  input \po_stg2_wrcal_cnt_reg[1]_43 ;
  input \po_stg2_wrcal_cnt_reg[1]_44 ;
  input \po_stg2_wrcal_cnt_reg[1]_45 ;
  input \po_stg2_wrcal_cnt_reg[1]_46 ;
  input \po_stg2_wrcal_cnt_reg[1]_47 ;
  input \po_stg2_wrcal_cnt_reg[1]_48 ;
  input \po_stg2_wrcal_cnt_reg[1]_49 ;
  input \po_stg2_wrcal_cnt_reg[1]_50 ;
  input \po_stg2_wrcal_cnt_reg[1]_51 ;
  input \po_stg2_wrcal_cnt_reg[1]_52 ;
  input \po_stg2_wrcal_cnt_reg[1]_53 ;
  input \po_stg2_wrcal_cnt_reg[1]_54 ;
  input \po_stg2_wrcal_cnt_reg[1]_55 ;
  input \po_stg2_wrcal_cnt_reg[1]_56 ;
  input \po_stg2_wrcal_cnt_reg[1]_57 ;
  input \po_stg2_wrcal_cnt_reg[1]_58 ;
  input \po_stg2_wrcal_cnt_reg[1]_59 ;
  input \po_stg2_wrcal_cnt_reg[1]_60 ;
  input \po_stg2_wrcal_cnt_reg[1]_61 ;
  input \po_stg2_wrcal_cnt_reg[1]_62 ;
  input ififo_rst;
  input CLK;

  wire B_byte_rd_en;
  wire CLK;
  wire C_byte_rd_en;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  wire ififo_rst;
  wire [79:8]mem_out;
  wire mem_reg_0_3_36_41_n_4;
  wire mem_reg_0_3_36_41_n_5;
  wire mem_reg_0_3_6_11_n_0;
  wire mem_reg_0_3_6_11_n_1;
  wire [4:1]my_empty;
  wire \my_empty[0]_i_1__3_n_0 ;
  wire \my_empty[1]_i_1__1_n_0 ;
  wire \my_empty[2]_i_1__6_n_0 ;
  wire \my_empty[3]_i_1__6_n_0 ;
  wire \my_empty[4]_i_1__7_n_0 ;
  wire \my_empty[4]_i_2__1_n_0 ;
  wire \my_empty[4]_rep__0_i_1__5_n_0 ;
  wire \my_empty[4]_rep__1_i_1__5_n_0 ;
  wire \my_empty[4]_rep_i_1__5_n_0 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__1_n_0 ;
  wire \my_full[1]_i_1__1_n_0 ;
  wire \my_full[1]_i_2__1_n_0 ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[471] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire p_0_out;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[1]_0 ;
  wire \po_stg2_wrcal_cnt_reg[1]_1 ;
  wire \po_stg2_wrcal_cnt_reg[1]_10 ;
  wire \po_stg2_wrcal_cnt_reg[1]_11 ;
  wire \po_stg2_wrcal_cnt_reg[1]_12 ;
  wire \po_stg2_wrcal_cnt_reg[1]_13 ;
  wire \po_stg2_wrcal_cnt_reg[1]_14 ;
  wire \po_stg2_wrcal_cnt_reg[1]_15 ;
  wire \po_stg2_wrcal_cnt_reg[1]_16 ;
  wire \po_stg2_wrcal_cnt_reg[1]_17 ;
  wire \po_stg2_wrcal_cnt_reg[1]_18 ;
  wire \po_stg2_wrcal_cnt_reg[1]_19 ;
  wire \po_stg2_wrcal_cnt_reg[1]_2 ;
  wire \po_stg2_wrcal_cnt_reg[1]_20 ;
  wire \po_stg2_wrcal_cnt_reg[1]_21 ;
  wire \po_stg2_wrcal_cnt_reg[1]_22 ;
  wire \po_stg2_wrcal_cnt_reg[1]_23 ;
  wire \po_stg2_wrcal_cnt_reg[1]_24 ;
  wire \po_stg2_wrcal_cnt_reg[1]_25 ;
  wire \po_stg2_wrcal_cnt_reg[1]_26 ;
  wire \po_stg2_wrcal_cnt_reg[1]_27 ;
  wire \po_stg2_wrcal_cnt_reg[1]_28 ;
  wire \po_stg2_wrcal_cnt_reg[1]_29 ;
  wire \po_stg2_wrcal_cnt_reg[1]_3 ;
  wire \po_stg2_wrcal_cnt_reg[1]_30 ;
  wire \po_stg2_wrcal_cnt_reg[1]_31 ;
  wire \po_stg2_wrcal_cnt_reg[1]_32 ;
  wire \po_stg2_wrcal_cnt_reg[1]_33 ;
  wire \po_stg2_wrcal_cnt_reg[1]_34 ;
  wire \po_stg2_wrcal_cnt_reg[1]_35 ;
  wire \po_stg2_wrcal_cnt_reg[1]_36 ;
  wire \po_stg2_wrcal_cnt_reg[1]_37 ;
  wire \po_stg2_wrcal_cnt_reg[1]_38 ;
  wire \po_stg2_wrcal_cnt_reg[1]_39 ;
  wire \po_stg2_wrcal_cnt_reg[1]_4 ;
  wire \po_stg2_wrcal_cnt_reg[1]_40 ;
  wire \po_stg2_wrcal_cnt_reg[1]_41 ;
  wire \po_stg2_wrcal_cnt_reg[1]_42 ;
  wire \po_stg2_wrcal_cnt_reg[1]_43 ;
  wire \po_stg2_wrcal_cnt_reg[1]_44 ;
  wire \po_stg2_wrcal_cnt_reg[1]_45 ;
  wire \po_stg2_wrcal_cnt_reg[1]_46 ;
  wire \po_stg2_wrcal_cnt_reg[1]_47 ;
  wire \po_stg2_wrcal_cnt_reg[1]_48 ;
  wire \po_stg2_wrcal_cnt_reg[1]_49 ;
  wire \po_stg2_wrcal_cnt_reg[1]_5 ;
  wire \po_stg2_wrcal_cnt_reg[1]_50 ;
  wire \po_stg2_wrcal_cnt_reg[1]_51 ;
  wire \po_stg2_wrcal_cnt_reg[1]_52 ;
  wire \po_stg2_wrcal_cnt_reg[1]_53 ;
  wire \po_stg2_wrcal_cnt_reg[1]_54 ;
  wire \po_stg2_wrcal_cnt_reg[1]_55 ;
  wire \po_stg2_wrcal_cnt_reg[1]_56 ;
  wire \po_stg2_wrcal_cnt_reg[1]_57 ;
  wire \po_stg2_wrcal_cnt_reg[1]_58 ;
  wire \po_stg2_wrcal_cnt_reg[1]_59 ;
  wire \po_stg2_wrcal_cnt_reg[1]_6 ;
  wire \po_stg2_wrcal_cnt_reg[1]_60 ;
  wire \po_stg2_wrcal_cnt_reg[1]_61 ;
  wire \po_stg2_wrcal_cnt_reg[1]_62 ;
  wire \po_stg2_wrcal_cnt_reg[1]_7 ;
  wire \po_stg2_wrcal_cnt_reg[1]_8 ;
  wire \po_stg2_wrcal_cnt_reg[1]_9 ;
  wire [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire \rd_mux_sel_r_reg[1] ;
  wire \rd_mux_sel_r_reg[1]_0 ;
  wire \rd_mux_sel_r_reg[1]_1 ;
  wire \rd_mux_sel_r_reg[1]_10 ;
  wire \rd_mux_sel_r_reg[1]_11 ;
  wire \rd_mux_sel_r_reg[1]_12 ;
  wire \rd_mux_sel_r_reg[1]_13 ;
  wire \rd_mux_sel_r_reg[1]_14 ;
  wire \rd_mux_sel_r_reg[1]_15 ;
  wire \rd_mux_sel_r_reg[1]_16 ;
  wire \rd_mux_sel_r_reg[1]_17 ;
  wire \rd_mux_sel_r_reg[1]_18 ;
  wire \rd_mux_sel_r_reg[1]_19 ;
  wire \rd_mux_sel_r_reg[1]_2 ;
  wire \rd_mux_sel_r_reg[1]_20 ;
  wire \rd_mux_sel_r_reg[1]_21 ;
  wire \rd_mux_sel_r_reg[1]_22 ;
  wire \rd_mux_sel_r_reg[1]_23 ;
  wire \rd_mux_sel_r_reg[1]_24 ;
  wire \rd_mux_sel_r_reg[1]_25 ;
  wire \rd_mux_sel_r_reg[1]_26 ;
  wire \rd_mux_sel_r_reg[1]_27 ;
  wire \rd_mux_sel_r_reg[1]_28 ;
  wire \rd_mux_sel_r_reg[1]_29 ;
  wire \rd_mux_sel_r_reg[1]_3 ;
  wire \rd_mux_sel_r_reg[1]_30 ;
  wire \rd_mux_sel_r_reg[1]_31 ;
  wire \rd_mux_sel_r_reg[1]_32 ;
  wire \rd_mux_sel_r_reg[1]_33 ;
  wire \rd_mux_sel_r_reg[1]_34 ;
  wire \rd_mux_sel_r_reg[1]_35 ;
  wire \rd_mux_sel_r_reg[1]_36 ;
  wire \rd_mux_sel_r_reg[1]_37 ;
  wire \rd_mux_sel_r_reg[1]_38 ;
  wire \rd_mux_sel_r_reg[1]_39 ;
  wire \rd_mux_sel_r_reg[1]_4 ;
  wire \rd_mux_sel_r_reg[1]_40 ;
  wire \rd_mux_sel_r_reg[1]_41 ;
  wire \rd_mux_sel_r_reg[1]_42 ;
  wire \rd_mux_sel_r_reg[1]_43 ;
  wire \rd_mux_sel_r_reg[1]_44 ;
  wire \rd_mux_sel_r_reg[1]_45 ;
  wire \rd_mux_sel_r_reg[1]_46 ;
  wire \rd_mux_sel_r_reg[1]_47 ;
  wire \rd_mux_sel_r_reg[1]_48 ;
  wire \rd_mux_sel_r_reg[1]_49 ;
  wire \rd_mux_sel_r_reg[1]_5 ;
  wire \rd_mux_sel_r_reg[1]_50 ;
  wire \rd_mux_sel_r_reg[1]_51 ;
  wire \rd_mux_sel_r_reg[1]_52 ;
  wire \rd_mux_sel_r_reg[1]_53 ;
  wire \rd_mux_sel_r_reg[1]_54 ;
  wire \rd_mux_sel_r_reg[1]_55 ;
  wire \rd_mux_sel_r_reg[1]_56 ;
  wire \rd_mux_sel_r_reg[1]_57 ;
  wire \rd_mux_sel_r_reg[1]_58 ;
  wire \rd_mux_sel_r_reg[1]_59 ;
  wire \rd_mux_sel_r_reg[1]_6 ;
  wire \rd_mux_sel_r_reg[1]_60 ;
  wire \rd_mux_sel_r_reg[1]_61 ;
  wire \rd_mux_sel_r_reg[1]_62 ;
  wire \rd_mux_sel_r_reg[1]_7 ;
  wire \rd_mux_sel_r_reg[1]_8 ;
  wire \rd_mux_sel_r_reg[1]_9 ;
  wire [2:0]\rd_mux_sel_r_reg[2] ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__1_n_0 ;
  wire \rd_ptr[1]_i_1__1_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__4_n_0 ;
  wire \rd_ptr_timing[1]_i_1__1_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__6_n_0 ;
  wire \wr_ptr[1]_i_1__6_n_0 ;
  wire \wr_ptr[1]_i_2__2_n_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [0]),
        .I1(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [0]),
        .O(\gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_5 ),
        .O(\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [0]),
        .I1(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [0]),
        .O(\gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_3 ),
        .O(\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] [0]),
        .I1(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [0]),
        .O(\gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2 
       (.I0(DIA[0]),
        .I1(DIB[0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(DIC[0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [0]),
        .O(\gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1] ),
        .O(\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise0_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .O(\gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_6 ),
        .O(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] [0]),
        .I1(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [0]),
        .O(\gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_4 ),
        .O(\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] [0]),
        .I1(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [0]),
        .O(\gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_2 ),
        .O(\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] [0]),
        .I1(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [0]),
        .O(\gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_0 ),
        .O(\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [1]),
        .I1(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [1]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_13 ),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [1]),
        .I1(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [1]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_11 ),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] [1]),
        .I1(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [1]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_9 ),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2 
       (.I0(DIA[1]),
        .I1(DIB[1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(DIC[1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [1]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_7 ),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .O(\gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_14 ),
        .O(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] [1]),
        .I1(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [1]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_12 ),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] [1]),
        .I1(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [1]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_10 ),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] [1]),
        .I1(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [1]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_8 ),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [0]),
        .O(\gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_21 ),
        .O(\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [0]),
        .O(\gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_19 ),
        .O(\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [0]),
        .O(\gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_17 ),
        .O(\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [0]),
        .O(\gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_15 ),
        .O(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .I1(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .O(\gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_22 ),
        .O(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [0]),
        .O(\gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_20 ),
        .O(\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [0]),
        .O(\gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_18 ),
        .O(\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [0]),
        .O(\gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_16 ),
        .O(\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [1]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_29 ),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [1]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_27 ),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [1]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_25 ),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [1]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_23 ),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .I1(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .O(\gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_30 ),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [1]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_28 ),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [1]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_26 ),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [1]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_24 ),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_37 ),
        .O(\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_35 ),
        .O(\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_33 ),
        .O(\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_31 ),
        .O(\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_38 ),
        .O(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [0]),
        .I1(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_36 ),
        .O(\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [0]),
        .I1(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_34 ),
        .O(\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [0]),
        .I1(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_32 ),
        .O(\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_45 ),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_43 ),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_41 ),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_39 ),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_46 ),
        .O(\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [1]),
        .I1(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_44 ),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [1]),
        .I1(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_42 ),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [1]),
        .I1(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_40 ),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_53 ),
        .O(\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_51 ),
        .O(\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_49 ),
        .O(\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_47 ),
        .O(\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_54 ),
        .O(\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [0]),
        .I1(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_52 ),
        .O(\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [0]),
        .I1(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_50 ),
        .O(\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [0]),
        .I1(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [0]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_48 ),
        .O(\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_61 ),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_59 ),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_57 ),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_55 ),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_62 ),
        .O(\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [1]),
        .I1(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_60 ),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [1]),
        .I1(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_58 ),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [1]),
        .I1(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [1]),
        .I4(\rd_mux_sel_r_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ),
        .I1(\rd_mux_sel_r_reg[1]_56 ),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .S(\rd_mux_sel_r_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [0]),
        .I1(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_5 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [0]),
        .I1(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_3 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] [0]),
        .I1(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2 
       (.I0(DIA[0]),
        .I1(DIB[0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(DIC[0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1] ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_6 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] [0]),
        .I1(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_4 ),
        .O(p_0_out),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] [0]),
        .I1(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_2 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] [0]),
        .I1(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_0 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [1]),
        .I1(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_13 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] [1]),
        .I1(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_11 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] [1]),
        .I1(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_9 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2 
       (.I0(DIA[1]),
        .I1(DIB[1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(DIC[1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_7 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_14 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] [1]),
        .I1(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_12 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] [1]),
        .I1(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_10 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] [1]),
        .I1(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_8 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_21 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_19 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_17 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [0]),
        .I1(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_15 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .I1(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_22 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_20 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_18 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 [0]),
        .I1(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_16 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_29 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_27 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_25 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [1]),
        .I1(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_23 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .I1(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_30 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_28 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_26 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 [1]),
        .I1(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_24 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_37 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_35 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_33 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [0]),
        .I1(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_31 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_38 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [0]),
        .I1(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_36 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [0]),
        .I1(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_34 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [0]),
        .I1(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_32 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_45 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_43 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_41 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [1]),
        .I1(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_39 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_46 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [1]),
        .I1(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_44 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [1]),
        .I1(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_42 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [1]),
        .I1(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_40 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_53 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_51 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_49 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [0]),
        .I1(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_47 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_54 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [0]),
        .I1(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_52 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [0]),
        .I1(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_50 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [0]),
        .I1(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_48 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_61 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_59 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_57 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [1]),
        .I1(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_55 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_62 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [1]),
        .I1(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_60 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [1]),
        .I1(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_58 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [1]),
        .I1(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [2]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[1]_56 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .S(\po_stg2_wrcal_cnt_reg[2] [0]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[2].rd_data_rise_wl_r[2]_i_1 
       (.I0(\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .I2(\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .I3(\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .I4(\gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ),
        .O(\gen_rd[2].rd_data_rise_wl_r_reg[2] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[2].rd_data_rise_wl_r[2]_i_2 
       (.I0(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [36]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(mem_out[48]),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I5(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .O(\gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ));
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [7:6]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [9:8]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[13:12]),
        .DOB(mem_out[15:14]),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [13:12]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [15:14]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [19:18]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [21:20]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [25:24]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [27:26]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [31:30]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [33:32]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC({mem_reg_0_3_36_41_n_4,mem_reg_0_3_36_41_n_5}),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [37:36]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [39:38]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [43:42]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [45:44]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [49:48]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [51:50]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [55:54]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [57:56]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [1:0]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [3:2]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0047)) 
    mem_reg_0_3_6_11_i_1
       (.I0(my_full[0]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[2]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(wr_en));
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [61:60]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [63:62]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[0]_i_1__3 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__1_n_0 ),
        .I5(Q[0]),
        .O(\my_empty[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hCDCCCD0C)) 
    \my_empty[1]_i_1__1 
       (.I0(\my_empty[4]_i_2__1_n_0 ),
        .I1(my_empty[1]),
        .I2(\wr_ptr[1]_i_2__2_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .O(\my_empty[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[2]_i_1__6 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__1_n_0 ),
        .I5(my_empty[2]),
        .O(\my_empty[2]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[3]_i_1__6 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__1_n_0 ),
        .I5(Q[1]),
        .O(\my_empty[3]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_i_1__7 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__1_n_0 ),
        .I5(my_empty[4]),
        .O(\my_empty[4]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT5 #(
    .INIT(32'hFDEFEFFD)) 
    \my_empty[4]_i_2__1 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(wr_ptr[1]),
        .O(\my_empty[4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__0_i_1__5 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__1_n_0 ),
        .I5(\my_empty_reg[4]_rep__0_n_0 ),
        .O(\my_empty[4]_rep__0_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__1_i_1__5 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__1_n_0 ),
        .I5(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\my_empty[4]_rep__1_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep_i_1__5 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__2_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__1_n_0 ),
        .I5(\my_empty_reg[4]_rep_n_0 ),
        .O(\my_empty[4]_rep_i_1__5_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[0]_i_1__3_n_0 ),
        .Q(Q[0]),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__1_n_0 ),
        .Q(my_empty[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__6_n_0 ),
        .Q(my_empty[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__6_n_0 ),
        .Q(Q[1]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__7_n_0 ),
        .Q(my_empty[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep_i_1__5_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__0_i_1__5_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__1_i_1__5_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hA8AAAA8AA8AAAABA)) 
    \my_full[0]_i_1__1 
       (.I0(my_full[0]),
        .I1(my_empty[1]),
        .I2(\wr_ptr[1]_i_2__2_n_0 ),
        .I3(my_full[1]),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I5(\my_full[1]_i_2__1_n_0 ),
        .O(\my_full[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAA0BA)) 
    \my_full[1]_i_1__1 
       (.I0(my_full[1]),
        .I1(\my_full[1]_i_2__1_n_0 ),
        .I2(\wr_ptr[1]_i_2__2_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty[1]),
        .O(\my_full[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT4 #(
    .INIT(16'hF96F)) 
    \my_full[1]_i_2__1 
       (.I0(wr_ptr[1]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(wr_ptr[0]),
        .O(\my_full[1]_i_2__1_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__1_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1__1_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[144]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [62]),
        .I1(my_empty[4]),
        .I2(mem_out[74]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[145]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [54]),
        .I1(my_empty[4]),
        .I2(mem_out[66]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[146]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [46]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[147]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [38]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[148]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [28]),
        .I1(my_empty[4]),
        .I2(mem_out[34]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[149]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [20]),
        .I1(my_empty[4]),
        .I2(mem_out[26]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[150]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [12]),
        .I1(my_empty[4]),
        .I2(mem_out[18]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[151]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [4]),
        .I1(my_empty[4]),
        .I2(mem_out[10]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[16]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [60]),
        .I1(my_empty[4]),
        .I2(mem_out[72]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[17]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [52]),
        .I1(my_empty[4]),
        .I2(mem_out[64]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[18]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [44]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[19]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [36]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[208]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [63]),
        .I1(my_empty[4]),
        .I2(mem_out[75]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[209]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [55]),
        .I1(my_empty[4]),
        .I2(mem_out[67]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[20]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [26]),
        .I1(my_empty[4]),
        .I2(mem_out[32]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[210]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [47]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[211]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [39]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[212]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [29]),
        .I1(my_empty[4]),
        .I2(mem_out[35]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[213]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [21]),
        .I1(my_empty[4]),
        .I2(mem_out[27]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[214]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [13]),
        .I1(my_empty[4]),
        .I2(mem_out[19]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[215]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [5]),
        .I1(my_empty[4]),
        .I2(mem_out[11]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[21]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [18]),
        .I1(my_empty[4]),
        .I2(mem_out[24]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[22]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [10]),
        .I1(my_empty[4]),
        .I2(mem_out[16]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[23]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [2]),
        .I1(my_empty[4]),
        .I2(mem_out[8]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [7]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[272]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [64]),
        .I1(my_empty[4]),
        .I2(mem_out[76]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[273]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [56]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[68]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[274]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [48]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[60]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[275]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [40]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[52]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[276]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[36]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[277]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[28]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[278]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[20]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[279]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[12]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[336]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [65]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[77]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[337]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [57]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[69]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[338]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [49]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[61]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[339]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [41]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[53]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[340]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[37]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[341]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[29]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[342]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[21]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[343]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[13]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[400]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [66]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[78]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[401]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [58]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[70]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[402]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [50]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[62]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[403]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [42]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[54]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[404]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [32]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[38]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[405]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [24]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[30]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[406]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [16]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[22]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[407]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [8]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[14]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[464]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [67]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[79]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[465]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [59]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[71]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[466]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [51]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[63]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[467]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [43]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[55]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[468]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [33]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[39]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[469]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [25]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[31]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[470]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [17]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[23]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[471]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [9]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[15]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [63]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[80]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [61]),
        .I1(my_empty[4]),
        .I2(mem_out[73]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[81]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [53]),
        .I1(my_empty[4]),
        .I2(mem_out[65]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[82]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [45]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[83]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [37]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [11]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[84]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [27]),
        .I1(my_empty[4]),
        .I2(mem_out[33]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[85]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [19]),
        .I1(my_empty[4]),
        .I2(mem_out[25]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[86]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [11]),
        .I1(my_empty[4]),
        .I2(mem_out[17]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[471] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[87]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [3]),
        .I1(my_empty[4]),
        .I2(mem_out[9]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[471] [15]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[49]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[57]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[65]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[73]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[17]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[33]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[34]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[50]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[58]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[66]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [62]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[74]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[18]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[64]),
        .O(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[72]),
        .O(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[67]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [63]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[75]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[19]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[35]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[51]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[59]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[8]),
        .O(\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[16]),
        .O(\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[24]),
        .O(\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[32]),
        .O(\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[48]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[56]),
        .O(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[52]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[60]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[68]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [64]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[76]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[20]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [30]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[36]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [31]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[37]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[53]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[61]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[69]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [65]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[77]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[21]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[70]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [66]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[78]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[22]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[38]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[54]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[62]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[55]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[63]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[71]),
        .O(DIB[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [67]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[79]),
        .O(DIB[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[23]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[39]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \rd_ptr[0]_i_1__1 
       (.I0(\wr_ptr[1]_i_2__2_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT4 #(
    .INIT(16'hEF10)) 
    \rd_ptr[1]_i_1__1 
       (.I0(\wr_ptr[1]_i_2__2_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__1_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__1_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__1_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hE0F1)) 
    \rd_ptr_timing[0]_i_1__4 
       (.I0(\wr_ptr[1]_i_2__2_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr_timing[0]),
        .I3(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hE0F1F1E0)) 
    \rd_ptr_timing[1]_i_1__1 
       (.I0(\wr_ptr[1]_i_2__2_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr_timing[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[1]),
        .O(\rd_ptr_timing[1]_i_1__1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__4_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__1_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFDEC0213)) 
    \wr_ptr[0]_i_1__6 
       (.I0(\wr_ptr[1]_i_2__2_n_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFF5FFDD000A0022)) 
    \wr_ptr[1]_i_1__6 
       (.I0(wr_ptr[0]),
        .I1(my_empty[1]),
        .I2(my_full[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\wr_ptr[1]_i_2__2_n_0 ),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFD5FFFFFFFF)) 
    \wr_ptr[1]_i_2__2 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(Q[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I5(C_byte_rd_en),
        .O(\wr_ptr[1]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \wr_ptr[1]_i_4 
       (.I0(Q[1]),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(B_byte_rd_en));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__6_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__6_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_12
   (rd_buf_we,
    Q,
    \read_fifo.tail_r_reg[1] ,
    \read_fifo.tail_r_reg[3] ,
    ADDRA,
    \my_empty_reg[4]_rep__1_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ,
    \read_fifo.tail_r_reg[0] ,
    \read_fifo.tail_r_reg[1]_0 ,
    \not_strict_mode.app_rd_data_reg[479] ,
    \not_strict_mode.app_rd_data_reg[24] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    ram_init_done_r,
    if_empty_r_1,
    my_empty,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \my_empty_reg[3]_0 ,
    \read_fifo.fifo_out_data_r_reg[6] ,
    init_complete_r1_timing_reg,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    tail_r,
    rstdiv0_sync_r1_reg_rep__21,
    if_empty_r_0,
    \my_empty_reg[0]_0 ,
    \my_empty_reg[0]_1 ,
    \my_empty_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \my_empty_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    ram_init_addr,
    ififo_rst,
    CLK);
  output rd_buf_we;
  output [0:0]Q;
  output \read_fifo.tail_r_reg[1] ;
  output \read_fifo.tail_r_reg[3] ;
  output [1:0]ADDRA;
  output \my_empty_reg[4]_rep__1_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  output \read_fifo.tail_r_reg[0] ;
  output \read_fifo.tail_r_reg[1]_0 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[479] ;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input ram_init_done_r;
  input [0:0]if_empty_r_1;
  input [0:0]my_empty;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input \my_empty_reg[3]_0 ;
  input [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  input init_complete_r1_timing_reg;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  input [3:0]tail_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input [0:0]if_empty_r_0;
  input [0:0]\my_empty_reg[0]_0 ;
  input \my_empty_reg[0]_1 ;
  input [0:0]\my_empty_reg[3]_1 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  input [0:0]\my_empty_reg[3]_2 ;
  input [65:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input \read_fifo.fifo_out_data_r_reg[5] ;
  input [0:0]ram_init_addr;
  input ififo_rst;
  input CLK;

  wire [1:0]ADDRA;
  wire CLK;
  wire [0:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire [65:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_r_1;
  wire ififo_rst;
  wire init_complete_r1_timing_reg;
  wire [63:0]mem_out;
  wire mem_reg_0_3_60_65_n_4;
  wire mem_reg_0_3_60_65_n_5;
  wire [0:0]my_empty;
  wire \my_empty[0]_i_1__2_n_0 ;
  wire \my_empty[1]_i_1__0_n_0 ;
  wire \my_empty[2]_i_1__5_n_0 ;
  wire \my_empty[3]_i_1__5_n_0 ;
  wire \my_empty[4]_i_1__6_n_0 ;
  wire \my_empty[4]_i_2__0_n_0 ;
  wire \my_empty[4]_rep__0_i_1__6_n_0 ;
  wire \my_empty[4]_rep__1_i_1__6_n_0 ;
  wire \my_empty[4]_rep_i_1__6_n_0 ;
  wire [4:0]my_empty_0;
  wire [0:0]\my_empty_reg[0]_0 ;
  wire \my_empty_reg[0]_1 ;
  wire \my_empty_reg[3]_0 ;
  wire [0:0]\my_empty_reg[3]_1 ;
  wire [0:0]\my_empty_reg[3]_2 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__0_n_0 ;
  wire \my_full[1]_i_1__0_n_0 ;
  wire \my_full[1]_i_2__0_n_0 ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[479] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [0:0]ram_init_addr;
  wire ram_init_done_r;
  wire rd_buf_we;
  wire rd_data_en;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__0_n_0 ;
  wire \rd_ptr[1]_i_1__0_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__3_n_0 ;
  wire \rd_ptr_timing[1]_i_1__0_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  wire \read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire \read_fifo.tail_r_reg[3] ;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire [3:0]tail_r;
  wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__4_n_0 ;
  wire \wr_ptr[1]_i_1__4_n_0 ;
  wire \wr_ptr[1]_i_2__3_n_0 ;
  wire [1:0]NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;

  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[3].rd_data_rise_wl_r[3]_i_1 
       (.I0(\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .I1(\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .I2(\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .I3(\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .I4(\gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[3].rd_data_rise_wl_r[3]_i_2 
       (.I0(\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [32]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(mem_out[32]),
        .I4(\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .I5(\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .O(\gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ));
  RAM32M mem_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [1:0]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [3:2]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [5:4]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[1:0]),
        .DOB(mem_out[3:2]),
        .DOC(mem_out[5:4]),
        .DOD(NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0047)) 
    mem_reg_0_3_0_5_i_1__0
       (.I0(my_full[0]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[2]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(wr_en));
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [13:12]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [15:14]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[13:12]),
        .DOB(mem_out[15:14]),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [19:18]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [21:20]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [25:24]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [27:26]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [31:30]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [33:32]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [37:36]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [39:38]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [43:42]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [45:44]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [49:48]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [51:50]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [55:54]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [57:56]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [61:60]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [63:62]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC({mem_reg_0_3_60_65_n_4,mem_reg_0_3_60_65_n_5}),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [7:6]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [9:8]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[7:6]),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[0]_i_1__2 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__0_n_0 ),
        .I5(my_empty_0[0]),
        .O(\my_empty[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hCDCCCD0C)) 
    \my_empty[1]_i_1__0 
       (.I0(\my_empty[4]_i_2__0_n_0 ),
        .I1(my_empty_0[1]),
        .I2(\wr_ptr[1]_i_2__3_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .O(\my_empty[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[2]_i_1__5 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__0_n_0 ),
        .I5(my_empty_0[2]),
        .O(\my_empty[2]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[3]_i_1__5 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__0_n_0 ),
        .I5(Q),
        .O(\my_empty[3]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_i_1__6 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__0_n_0 ),
        .I5(my_empty_0[4]),
        .O(\my_empty[4]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT5 #(
    .INIT(32'hFDEFEFFD)) 
    \my_empty[4]_i_2__0 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(wr_ptr[1]),
        .O(\my_empty[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__0_i_1__6 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__0_n_0 ),
        .I5(\my_empty_reg[4]_rep__0_n_0 ),
        .O(\my_empty[4]_rep__0_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__1_i_1__6 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__0_n_0 ),
        .I5(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\my_empty[4]_rep__1_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep_i_1__6 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__3_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__0_n_0 ),
        .I5(\my_empty_reg[4]_rep_n_0 ),
        .O(\my_empty[4]_rep_i_1__6_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[0]_i_1__2_n_0 ),
        .Q(my_empty_0[0]),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__0_n_0 ),
        .Q(my_empty_0[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__5_n_0 ),
        .Q(my_empty_0[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__5_n_0 ),
        .Q(Q),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__6_n_0 ),
        .Q(my_empty_0[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep_i_1__6_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__0_i_1__6_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__1_i_1__6_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hA8AAAA8AA8AAAABA)) 
    \my_full[0]_i_1__0 
       (.I0(my_full[0]),
        .I1(my_empty_0[1]),
        .I2(\wr_ptr[1]_i_2__3_n_0 ),
        .I3(my_full[1]),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I5(\my_full[1]_i_2__0_n_0 ),
        .O(\my_full[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAA0BA)) 
    \my_full[1]_i_1__0 
       (.I0(my_full[1]),
        .I1(\my_full[1]_i_2__0_n_0 ),
        .I2(\wr_ptr[1]_i_2__3_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty_0[1]),
        .O(\my_full[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT4 #(
    .INIT(16'hF96F)) 
    \my_full[1]_i_2__0 
       (.I0(wr_ptr[1]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(wr_ptr[0]),
        .O(\my_full[1]_i_2__0_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__0_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1__0_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[152]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [58]),
        .I1(my_empty_0[4]),
        .I2(mem_out[58]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[153]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [50]),
        .I1(my_empty_0[4]),
        .I2(mem_out[50]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[154]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [42]),
        .I1(my_empty_0[4]),
        .I2(mem_out[42]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[155]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [34]),
        .I1(my_empty_0[4]),
        .I2(mem_out[34]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[156]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [26]),
        .I1(my_empty_0[4]),
        .I2(mem_out[26]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[157]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [18]),
        .I1(my_empty_0[4]),
        .I2(mem_out[18]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[158]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [10]),
        .I1(my_empty_0[4]),
        .I2(mem_out[10]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[159]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [2]),
        .I1(my_empty_0[4]),
        .I2(mem_out[2]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[216]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [59]),
        .I1(my_empty_0[4]),
        .I2(mem_out[59]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[217]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [51]),
        .I1(my_empty_0[4]),
        .I2(mem_out[51]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[218]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [43]),
        .I1(my_empty_0[4]),
        .I2(mem_out[43]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[219]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [35]),
        .I1(my_empty_0[4]),
        .I2(mem_out[35]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[220]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [27]),
        .I1(my_empty_0[4]),
        .I2(mem_out[27]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[221]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [19]),
        .I1(my_empty_0[4]),
        .I2(mem_out[19]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[222]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [11]),
        .I1(my_empty_0[4]),
        .I2(mem_out[11]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[223]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [3]),
        .I1(my_empty_0[4]),
        .I2(mem_out[3]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[24]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [56]),
        .I1(my_empty_0[4]),
        .I2(mem_out[56]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[25]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [48]),
        .I1(my_empty_0[4]),
        .I2(mem_out[48]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[26]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [40]),
        .I1(my_empty_0[4]),
        .I2(mem_out[40]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[27]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [32]),
        .I1(my_empty_0[4]),
        .I2(mem_out[32]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[280]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [60]),
        .I1(my_empty_0[4]),
        .I2(mem_out[60]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[281]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [52]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[52]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[282]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [44]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[44]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[283]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [36]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[36]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[284]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [28]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[28]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[285]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [20]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[20]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[286]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [12]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[12]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[287]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [4]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[4]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[28]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [24]),
        .I1(my_empty_0[4]),
        .I2(mem_out[24]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[29]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [16]),
        .I1(my_empty_0[4]),
        .I2(mem_out[16]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[30]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [8]),
        .I1(my_empty_0[4]),
        .I2(mem_out[8]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[31]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [0]),
        .I1(my_empty_0[4]),
        .I2(mem_out[0]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [7]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[344]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [61]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[61]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[345]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [53]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[53]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[346]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [45]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[45]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[347]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [37]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[37]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[348]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [29]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[29]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[349]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [21]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[21]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[350]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [13]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[13]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[351]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [5]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[5]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[408]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[62]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[409]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [54]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[54]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[410]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [46]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[46]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[411]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [38]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[38]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[412]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[30]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[413]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[22]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[414]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[14]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[415]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[6]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[472]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[63]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[473]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [55]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[55]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[474]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [47]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[47]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[475]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [39]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[39]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[476]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[31]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[477]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[23]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[478]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[15]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[479]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[7]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [63]));
  LUT4 #(
    .INIT(16'h2002)) 
    \not_strict_mode.app_rd_data[511]_i_2 
       (.I0(rd_data_en),
        .I1(\read_fifo.fifo_out_data_r_reg[5] ),
        .I2(\read_fifo.fifo_out_data_r_reg[6] [0]),
        .I3(ram_init_addr),
        .O(\not_strict_mode.app_rd_data_reg[24] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[88]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [57]),
        .I1(my_empty_0[4]),
        .I2(mem_out[57]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[89]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [49]),
        .I1(my_empty_0[4]),
        .I2(mem_out[49]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[90]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [41]),
        .I1(my_empty_0[4]),
        .I2(mem_out[41]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[91]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [33]),
        .I1(my_empty_0[4]),
        .I2(mem_out[33]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [11]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[92]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [25]),
        .I1(my_empty_0[4]),
        .I2(mem_out[25]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[93]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [17]),
        .I1(my_empty_0[4]),
        .I2(mem_out[17]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[94]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [9]),
        .I1(my_empty_0[4]),
        .I2(mem_out[9]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[479] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[95]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [1]),
        .I1(my_empty_0[4]),
        .I2(mem_out[1]),
        .I3(\not_strict_mode.app_rd_data_reg[24] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[479] [15]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1 
       (.I0(rd_data_en),
        .I1(ram_init_done_r),
        .O(rd_buf_we));
  LUT4 #(
    .INIT(16'h0004)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_8 
       (.I0(\read_fifo.fifo_out_data_r_reg[6] [1]),
        .I1(init_complete_r1_timing_reg),
        .I2(\read_fifo.tail_r_reg[1] ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .O(rd_data_en));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[49]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[57]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [1]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[1]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[17]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[33]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[41]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [34]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[34]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[42]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[50]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[58]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[2]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[18]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[19]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [35]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[35]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[43]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[51]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[59]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[3]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[52]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[60]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[4]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[20]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[36]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[44]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[16]),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[24]),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[32]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[40]),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[48]),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[56]),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[37]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[45]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[53]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[61]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[5]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[21]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [0]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[0]),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[8]),
        .O(\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[22]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [30]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[38]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[46]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[54]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[62]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[6]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[55]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[63]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[7]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[23]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [31]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[39]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] [47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[47]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \rd_ptr[0]_i_1__0 
       (.I0(\wr_ptr[1]_i_2__3_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT4 #(
    .INIT(16'hEF10)) 
    \rd_ptr[1]_i_1__0 
       (.I0(\wr_ptr[1]_i_2__3_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__0_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__0_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__0_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hE0F1)) 
    \rd_ptr_timing[0]_i_1__3 
       (.I0(\wr_ptr[1]_i_2__3_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr_timing[0]),
        .I3(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hE0F1F1E0)) 
    \rd_ptr_timing[1]_i_1__0 
       (.I0(\wr_ptr[1]_i_2__3_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr_timing[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[1]),
        .O(\rd_ptr_timing[1]_i_1__0_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__3_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__0_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_16 
       (.I0(\read_fifo.tail_r_reg[1] ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I2(tail_r[1]),
        .I3(init_complete_r1_timing_reg),
        .I4(tail_r[0]),
        .I5(tail_r[2]),
        .O(\read_fifo.tail_r_reg[3] ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_18 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I1(my_empty_0[0]),
        .I2(if_empty_r_0),
        .I3(\my_empty_reg[0]_0 ),
        .I4(\my_empty_reg[0]_1 ),
        .O(\read_fifo.tail_r_reg[1] ));
  LUT3 #(
    .INIT(8'h06)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_7 
       (.I0(\read_fifo.tail_r_reg[3] ),
        .I1(tail_r[3]),
        .I2(rstdiv0_sync_r1_reg_rep__21),
        .O(ADDRA[1]));
  LUT6 #(
    .INIT(64'h5555551500000040)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_9 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(init_complete_r1_timing_reg),
        .I2(tail_r[0]),
        .I3(\read_fifo.tail_r_reg[1] ),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I5(tail_r[1]),
        .O(ADDRA[0]));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT4 #(
    .INIT(16'hEF10)) 
    \read_fifo.tail_r[0]_i_1 
       (.I0(\read_fifo.tail_r_reg[1] ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I2(init_complete_r1_timing_reg),
        .I3(tail_r[0]),
        .O(\read_fifo.tail_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT5 #(
    .INIT(32'hFFF70008)) 
    \read_fifo.tail_r[1]_i_1 
       (.I0(init_complete_r1_timing_reg),
        .I1(tail_r[0]),
        .I2(\read_fifo.tail_r_reg[1] ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I4(tail_r[1]),
        .O(\read_fifo.tail_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hFDEC0213)) 
    \wr_ptr[0]_i_1__4 
       (.I0(\wr_ptr[1]_i_2__3_n_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(my_full[1]),
        .I3(my_empty_0[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFF5FFDD000A0022)) 
    \wr_ptr[1]_i_1__4 
       (.I0(wr_ptr[0]),
        .I1(my_empty_0[1]),
        .I2(my_full[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\wr_ptr[1]_i_2__3_n_0 ),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \wr_ptr[1]_i_2__3 
       (.I0(if_empty_r_1),
        .I1(my_empty),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(Q),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I5(\my_empty_reg[3]_0 ),
        .O(\wr_ptr[1]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \wr_ptr[1]_i_3__3 
       (.I0(Q),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(\my_empty_reg[3]_1 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .I5(\my_empty_reg[3]_2 ),
        .O(\my_empty_reg[4]_rep__1_0 ));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__4_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__4_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_3
   (\rd_ptr_timing_reg[1]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ,
    \not_strict_mode.app_rd_data_reg[503] ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \my_empty_reg[3]_0 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[1]_1 ,
    \read_fifo.tail_r_reg[1] ,
    DIA,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    Q,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    ififo_rd_en_in,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    if_empty_r,
    \my_empty_reg[3]_1 ,
    \my_empty_reg[3]_2 ,
    if_empty_r_0,
    ififo_rst,
    CLK);
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[503] ;
  output \not_strict_mode.app_rd_data_reg[496] ;
  output [0:0]\my_empty_reg[3]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output \wr_ptr_reg[1]_1 ;
  output \read_fifo.tail_r_reg[1] ;
  output [1:0]DIA;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input [63:0]Q;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input ififo_rd_en_in;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input [0:0]if_empty_r;
  input [1:0]\my_empty_reg[3]_1 ;
  input [0:0]\my_empty_reg[3]_2 ;
  input [0:0]if_empty_r_0;
  input ififo_rst;
  input CLK;

  wire CLK;
  wire [1:0]DIA;
  wire [63:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire ififo_rd_en_in;
  wire ififo_rst;
  wire [4:0]my_empty;
  wire my_empty0;
  wire \my_empty[0]_i_1__0_n_0 ;
  wire \my_empty[1]_i_1__5_n_0 ;
  wire \my_empty[2]_i_1__0_n_0 ;
  wire \my_empty[3]_i_1__0_n_0 ;
  wire \my_empty[4]_i_1__0_n_0 ;
  wire \my_empty[4]_i_2__5_n_0 ;
  wire \my_empty[4]_i_3__0_n_0 ;
  wire \my_empty[4]_rep__0_i_1__1_n_0 ;
  wire \my_empty[4]_rep__1_i_1__1_n_0 ;
  wire \my_empty[4]_rep_i_1__1_n_0 ;
  wire [0:0]\my_empty_reg[3]_0 ;
  wire [1:0]\my_empty_reg[3]_1 ;
  wire [0:0]\my_empty_reg[3]_2 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire my_full0;
  wire \my_full[0]_i_1__5_n_0 ;
  wire \my_full[1]_i_1__5_n_0 ;
  wire \not_strict_mode.app_rd_data_reg[496] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[503] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__0_n_0 ;
  wire \rd_ptr[1]_i_1__0_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__0_n_0 ;
  wire \rd_ptr_timing[1]_i_1__5_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \wr_ptr[0]_i_1__13_n_0 ;
  wire \wr_ptr[1]_i_1__13_n_0 ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;

  assign \rd_ptr_timing_reg[1]_0 [1:0] = rd_ptr_timing;
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[6].rd_data_rise_wl_r[6]_i_1 
       (.I0(\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .I1(\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .I2(\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .I3(\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .I4(\gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0 ),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[6].rd_data_rise_wl_r[6]_i_2 
       (.I0(\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .I1(Q[32]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [32]),
        .I4(\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .I5(\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .O(\gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0407)) 
    mem_reg_0_3_6_11_i_1__3
       (.I0(my_empty[2]),
        .I1(ififo_rd_en_in),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[0]),
        .O(\not_strict_mode.app_rd_data_reg[496] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[0]_i_1__0 
       (.I0(my_empty[0]),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__5_n_0 ),
        .O(\my_empty[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair721" *) 
  LUT5 #(
    .INIT(32'hF2E0F0E0)) 
    \my_empty[1]_i_1__5 
       (.I0(ififo_rd_en_in),
        .I1(my_full[1]),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty0),
        .O(\my_empty[1]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair722" *) 
  LUT4 #(
    .INIT(16'h4218)) 
    \my_empty[1]_i_2__1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(\wr_ptr_reg[1]_0 ),
        .O(my_empty0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBD0000)) 
    \my_empty[2]_i_1__0 
       (.I0(my_empty[1]),
        .I1(ififo_rd_en_in),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[1]),
        .I4(my_empty[2]),
        .I5(\my_empty[4]_i_2__5_n_0 ),
        .O(\my_empty[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[3]_i_1__0 
       (.I0(\my_empty_reg[3]_0 ),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__5_n_0 ),
        .O(\my_empty[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_i_1__0 
       (.I0(my_empty[4]),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__5_n_0 ),
        .O(\my_empty[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010040140)) 
    \my_empty[4]_i_2__5 
       (.I0(\my_empty[4]_i_3__0_n_0 ),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(\wr_ptr_reg[0]_0 ),
        .I4(\wr_ptr_reg[1]_0 ),
        .I5(my_empty[1]),
        .O(\my_empty[4]_i_2__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair721" *) 
  LUT4 #(
    .INIT(16'hFFBD)) 
    \my_empty[4]_i_3__0 
       (.I0(my_empty[1]),
        .I1(ififo_rd_en_in),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_rep__0_i_1__1 
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__5_n_0 ),
        .O(\my_empty[4]_rep__0_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_rep__1_i_1__1 
       (.I0(\my_empty_reg[4]_rep__1_n_0 ),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__5_n_0 ),
        .O(\my_empty[4]_rep__1_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[4]_rep_i_1__1 
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__5_n_0 ),
        .O(\my_empty[4]_rep_i_1__1_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[0]_i_1__0_n_0 ),
        .Q(my_empty[0]),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__5_n_0 ),
        .Q(my_empty[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__0_n_0 ),
        .Q(my_empty[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__0_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__0_n_0 ),
        .Q(my_empty[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep_i_1__1_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__0_i_1__1_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__1_i_1__1_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAA2AABAAAA2AA8)) 
    \my_full[0]_i_1__5 
       (.I0(my_full[0]),
        .I1(my_full[1]),
        .I2(ififo_rd_en_in),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty[1]),
        .I5(my_full0),
        .O(\my_full[0]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hFF007710)) 
    \my_full[1]_i_1__5 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I1(ififo_rd_en_in),
        .I2(my_full0),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .O(\my_full[1]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair722" *) 
  LUT4 #(
    .INIT(16'h2442)) 
    \my_full[1]_i_2__5 
       (.I0(rd_ptr[0]),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(\wr_ptr_reg[1]_0 ),
        .I3(rd_ptr[1]),
        .O(my_full0));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__5_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1__5_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[112]_i_1 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [57]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[113]_i_1 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [49]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[114]_i_1 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [41]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[115]_i_1 
       (.I0(Q[33]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [33]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [11]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[116]_i_1 
       (.I0(Q[25]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [25]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[117]_i_1 
       (.I0(Q[17]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [17]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[118]_i_1 
       (.I0(Q[9]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [9]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[119]_i_1 
       (.I0(Q[1]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [1]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [15]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[176]_i_1 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [58]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[177]_i_1 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [50]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[178]_i_1 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [42]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[179]_i_1 
       (.I0(Q[34]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [34]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[180]_i_1 
       (.I0(Q[26]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [26]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[181]_i_1 
       (.I0(Q[18]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [18]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[182]_i_1 
       (.I0(Q[10]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [10]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[183]_i_1 
       (.I0(Q[2]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [2]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[240]_i_1 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [59]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[241]_i_1 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [51]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[242]_i_1 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [43]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[243]_i_1 
       (.I0(Q[35]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [35]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[244]_i_1 
       (.I0(Q[27]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [27]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[245]_i_1 
       (.I0(Q[19]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [19]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[246]_i_1 
       (.I0(Q[11]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [11]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[247]_i_1 
       (.I0(Q[3]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [3]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[304]_i_1 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [60]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[305]_i_1 
       (.I0(Q[52]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [52]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[306]_i_1 
       (.I0(Q[44]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [44]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[307]_i_1 
       (.I0(Q[36]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [36]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[308]_i_1 
       (.I0(Q[28]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [28]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[309]_i_1 
       (.I0(Q[20]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [20]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[310]_i_1 
       (.I0(Q[12]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [12]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[311]_i_1 
       (.I0(Q[4]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [4]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[368]_i_1 
       (.I0(Q[61]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [61]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[369]_i_1 
       (.I0(Q[53]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [53]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[370]_i_1 
       (.I0(Q[45]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [45]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[371]_i_1 
       (.I0(Q[37]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [37]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[372]_i_1 
       (.I0(Q[29]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [29]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[373]_i_1 
       (.I0(Q[21]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [21]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[374]_i_1 
       (.I0(Q[13]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [13]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[375]_i_1 
       (.I0(Q[5]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [5]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[432]_i_1 
       (.I0(Q[62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [62]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[433]_i_1 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [54]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[434]_i_1 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [46]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[435]_i_1 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [38]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[436]_i_1 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [30]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[437]_i_1 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [22]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[438]_i_1 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [14]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[439]_i_1 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [6]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[48]_i_1 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [56]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[496]_i_1 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [63]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[497]_i_1 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [55]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[498]_i_1 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [47]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[499]_i_1 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [39]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[49]_i_1 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [48]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[500]_i_1 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [31]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[501]_i_1 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [23]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[502]_i_1 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [15]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[503]_i_1 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [7]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [63]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[50]_i_1 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [40]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[51]_i_1 
       (.I0(Q[32]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [32]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[52]_i_1 
       (.I0(Q[24]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [24]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[53]_i_1 
       (.I0(Q[16]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [16]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[54]_i_1 
       (.I0(Q[8]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [8]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[503] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[55]_i_1 
       (.I0(Q[0]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [0]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[503] [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1 
       (.I0(Q[49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [49]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2 
       (.I0(Q[57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [57]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1 
       (.I0(Q[1]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [1]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2 
       (.I0(Q[9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3 
       (.I0(Q[17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [17]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4 
       (.I0(Q[25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5 
       (.I0(Q[33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [33]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_6 
       (.I0(Q[41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [41]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1 
       (.I0(Q[34]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [34]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2 
       (.I0(Q[42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [42]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3 
       (.I0(Q[50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [50]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4 
       (.I0(Q[58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [58]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3 
       (.I0(Q[2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [2]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4 
       (.I0(Q[10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5 
       (.I0(Q[18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [18]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_6 
       (.I0(Q[26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1 
       (.I0(Q[19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [19]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2 
       (.I0(Q[27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3 
       (.I0(Q[35]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [35]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4 
       (.I0(Q[43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [43]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5 
       (.I0(Q[51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [51]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_6 
       (.I0(Q[59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [59]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5 
       (.I0(Q[3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [3]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_6 
       (.I0(Q[11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1 
       (.I0(Q[52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [52]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2 
       (.I0(Q[60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [60]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1 
       (.I0(Q[4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [4]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2 
       (.I0(Q[12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3 
       (.I0(Q[20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [20]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4 
       (.I0(Q[28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5 
       (.I0(Q[36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [36]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_6 
       (.I0(Q[44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [44]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1 
       (.I0(Q[37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [37]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2 
       (.I0(Q[45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [45]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3 
       (.I0(Q[53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [53]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4 
       (.I0(Q[61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [61]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3 
       (.I0(Q[5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [5]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4 
       (.I0(Q[13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5 
       (.I0(Q[21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [21]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_6 
       (.I0(Q[29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [22]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [38]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [46]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [54]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_6 
       (.I0(Q[62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [62]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [6]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_6 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [55]),
        .O(DIA[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [63]),
        .O(DIA[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [7]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [23]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [39]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_6 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [47]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1 
       (.I0(Q[16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [16]),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2 
       (.I0(Q[24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [24]),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3 
       (.I0(Q[32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [32]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4 
       (.I0(Q[40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [40]),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5 
       (.I0(Q[48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [48]),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_6 
       (.I0(Q[56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [56]),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5 
       (.I0(Q[0]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [0]),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_6 
       (.I0(Q[8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [8]),
        .O(\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair723" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr[0]_i_1__0 
       (.I0(my_empty[1]),
        .I1(ififo_rd_en_in),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair723" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__0 
       (.I0(rd_ptr[0]),
        .I1(ififo_rd_en_in),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__0_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__0_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__0_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'h8ABA)) 
    \rd_ptr_timing[0]_i_1__0 
       (.I0(rd_ptr_timing[0]),
        .I1(my_empty[1]),
        .I2(ififo_rd_en_in),
        .I3(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hD0F2F2D0)) 
    \rd_ptr_timing[1]_i_1__5 
       (.I0(ififo_rd_en_in),
        .I1(my_empty[1]),
        .I2(rd_ptr_timing[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[1]),
        .O(\rd_ptr_timing[1]_i_1__5_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__0_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__5_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_20 
       (.I0(my_empty[0]),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(\my_empty_reg[3]_1 [0]),
        .I3(if_empty_r),
        .O(\read_fifo.tail_r_reg[1] ));
  LUT5 #(
    .INIT(32'hFDF80207)) 
    \wr_ptr[0]_i_1__13 
       (.I0(ififo_rd_en_in),
        .I1(my_empty[1]),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_full[1]),
        .I4(\wr_ptr_reg[0]_0 ),
        .O(\wr_ptr[0]_i_1__13_n_0 ));
  LUT6 #(
    .INIT(64'hFFF5FDFD000A0202)) 
    \wr_ptr[1]_i_1__13 
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(my_full[1]),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_empty[1]),
        .I4(ififo_rd_en_in),
        .I5(\wr_ptr_reg[1]_0 ),
        .O(\wr_ptr[1]_i_1__13_n_0 ));
  LUT6 #(
    .INIT(64'h0000077707770777)) 
    \wr_ptr[1]_i_3__1 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I1(\my_empty_reg[3]_0 ),
        .I2(if_empty_r),
        .I3(\my_empty_reg[3]_1 [1]),
        .I4(\my_empty_reg[3]_2 ),
        .I5(if_empty_r_0),
        .O(\wr_ptr_reg[1]_1 ));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__13_n_0 ),
        .Q(\wr_ptr_reg[0]_0 ),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__13_n_0 ),
        .Q(\wr_ptr_reg[1]_0 ),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_4
   (\rd_ptr_timing_reg[1]_0 ,
    phy_rddata_en,
    rd_active_r_reg,
    \my_empty_reg[4]_rep__1_0 ,
    Q,
    \my_empty_reg[4]_rep__1_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    ADDRA,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[511] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \my_empty_reg[3]_0 ,
    if_empty_r_1,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \my_empty_reg[4]_rep__1_2 ,
    if_empty_r_0,
    \my_empty_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \my_empty_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    tail_r,
    init_complete_r1_timing_reg,
    rstdiv0_sync_r1_reg_rep__21,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \rd_mux_sel_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \po_stg2_wrcal_cnt_reg[2] ,
    ififo_rst,
    CLK);
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output phy_rddata_en;
  output rd_active_r_reg;
  output \my_empty_reg[4]_rep__1_0 ;
  output [0:0]Q;
  output \my_empty_reg[4]_rep__1_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output [0:0]ADDRA;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [63:0]\not_strict_mode.app_rd_data_reg[511] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output \not_strict_mode.app_rd_data_reg[376] ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  input [0:0]\my_empty_reg[3]_0 ;
  input [0:0]if_empty_r_1;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  input [0:0]\my_empty_reg[4]_rep__1_2 ;
  input [0:0]if_empty_r_0;
  input \my_empty_reg[0]_0 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  input [0:0]\my_empty_reg[3]_1 ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input [0:0]tail_r;
  input init_complete_r1_timing_reg;
  input rstdiv0_sync_r1_reg_rep__21;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  input [1:0]\rd_mux_sel_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [1:0]\po_stg2_wrcal_cnt_reg[2] ;
  input ififo_rst;
  input CLK;

  wire [0:0]ADDRA;
  wire CLK;
  wire [0:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_r_1;
  wire ififo_rst;
  wire init_complete_r1_timing_reg;
  wire [4:0]my_empty;
  wire my_empty0;
  wire \my_empty[0]_i_1__1_n_0 ;
  wire \my_empty[1]_i_1__6_n_0 ;
  wire \my_empty[2]_i_1__1_n_0 ;
  wire \my_empty[3]_i_1__1_n_0 ;
  wire \my_empty[4]_i_1__1_n_0 ;
  wire \my_empty[4]_i_2__6_n_0 ;
  wire \my_empty[4]_i_3__1_n_0 ;
  wire \my_empty[4]_rep__0_i_1__2_n_0 ;
  wire \my_empty[4]_rep__1_i_1__2_n_0 ;
  wire \my_empty[4]_rep_i_1__2_n_0 ;
  wire \my_empty_reg[0]_0 ;
  wire [0:0]\my_empty_reg[3]_0 ;
  wire [0:0]\my_empty_reg[3]_1 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_0 ;
  wire \my_empty_reg[4]_rep__1_1 ;
  wire [0:0]\my_empty_reg[4]_rep__1_2 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire my_full0;
  wire \my_full[0]_i_1__6_n_0 ;
  wire \my_full[1]_i_1__6_n_0 ;
  wire \not_strict_mode.app_rd_data_reg[376] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[511] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire phy_rddata_en;
  wire [1:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire rd_active_r_reg;
  wire [1:0]\rd_mux_sel_r_reg[2] ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1_n_0 ;
  wire \rd_ptr[1]_i_1_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__1_n_0 ;
  wire \rd_ptr_timing[1]_i_1__6_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire [0:0]tail_r;
  wire \wr_ptr[0]_i_1__12_n_0 ;
  wire \wr_ptr[1]_i_1__12_n_0 ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1]_0 ;

  assign \rd_ptr_timing_reg[1]_0 [1:0] = rd_ptr_timing;
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall0_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 [0]),
        .O(\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall1_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 [0]),
        .O(\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall2_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 [0]),
        .O(\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall3_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 [0]),
        .O(\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .O(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise1_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 [0]),
        .O(\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise2_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 [0]),
        .O(\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise3_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 [0]),
        .O(\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall0_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 [1]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall1_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 [1]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall2_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 [1]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall3_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 [1]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise0_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise1_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 [1]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise2_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 [1]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise3_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 [1]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall0_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 [0]),
        .O(\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall1_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 [0]),
        .O(\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall2_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 [0]),
        .O(\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall3_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 [0]),
        .O(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise0_r[2]_i_3 
       (.I0(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise1_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 [0]),
        .O(\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise2_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 [0]),
        .O(\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise3_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 [0]),
        .O(\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall0_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 [1]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall1_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 [1]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall2_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 [1]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall3_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 [1]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise0_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise1_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 [1]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise2_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 [1]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise3_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 [1]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall0_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall1_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall2_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall3_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise0_r[4]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise1_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise2_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise3_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [0]),
        .O(\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall0_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall1_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall2_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall3_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise0_r[5]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise1_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise2_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise3_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [1]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall0_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall1_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall2_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall3_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise0_r[6]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise1_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise2_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise3_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [0]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [0]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [0]),
        .O(\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall0_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall1_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall2_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall3_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise0_r[7]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise1_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise2_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise3_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [1]),
        .I2(\rd_mux_sel_r_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [1]),
        .I4(\rd_mux_sel_r_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [1]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_3 
       (.I0(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_3 
       (.I0(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_3 
       (.I0(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_3 
       (.I0(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [0]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [0]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_3 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_3 
       (.I0(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] [1]),
        .I2(\po_stg2_wrcal_cnt_reg[2] [0]),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] [1]),
        .I4(\po_stg2_wrcal_cnt_reg[2] [1]),
        .I5(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[7].rd_data_rise_wl_r[7]_i_1 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .I1(\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .I2(\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .I3(\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .I4(\gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0 ),
        .O(\gen_rd[7].rd_data_rise_wl_r_reg[7] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[7].rd_data_rise_wl_r[7]_i_2 
       (.I0(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [32]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [32]),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I5(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .O(\gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0407)) 
    mem_reg_0_3_0_5_i_1__1
       (.I0(my_empty[2]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[0]),
        .O(\not_strict_mode.app_rd_data_reg[376] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[0]_i_1__1 
       (.I0(my_empty[0]),
        .I1(my_empty[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__6_n_0 ),
        .O(\my_empty[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair707" *) 
  LUT5 #(
    .INIT(32'hF2E0F0E0)) 
    \my_empty[1]_i_1__6 
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(my_full[1]),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I4(my_empty0),
        .O(\my_empty[1]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair708" *) 
  LUT4 #(
    .INIT(16'h4218)) 
    \my_empty[1]_i_2__0 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(\wr_ptr_reg[1]_0 ),
        .O(my_empty0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBD0000)) 
    \my_empty[2]_i_1__1 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[1]),
        .I4(my_empty[2]),
        .I5(\my_empty[4]_i_2__6_n_0 ),
        .O(\my_empty[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAA8AA2)) 
    \my_empty[3]_i_1__1 
       (.I0(Q),
        .I1(my_empty[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I4(my_full[1]),
        .I5(\my_empty[4]_i_2__6_n_0 ),
        .O(\my_empty[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBD0000)) 
    \my_empty[4]_i_1__1 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[1]),
        .I4(my_empty[4]),
        .I5(\my_empty[4]_i_2__6_n_0 ),
        .O(\my_empty[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010040140)) 
    \my_empty[4]_i_2__6 
       (.I0(\my_empty[4]_i_3__1_n_0 ),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(\wr_ptr_reg[0]_0 ),
        .I4(\wr_ptr_reg[1]_0 ),
        .I5(my_empty[1]),
        .O(\my_empty[4]_i_2__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair707" *) 
  LUT4 #(
    .INIT(16'hFFBD)) 
    \my_empty[4]_i_3__1 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBD0000)) 
    \my_empty[4]_rep__0_i_1__2 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[1]),
        .I4(\my_empty_reg[4]_rep__0_n_0 ),
        .I5(\my_empty[4]_i_2__6_n_0 ),
        .O(\my_empty[4]_rep__0_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBD0000)) 
    \my_empty[4]_rep__1_i_1__2 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[1]),
        .I4(\my_empty_reg[4]_rep__1_n_0 ),
        .I5(\my_empty[4]_i_2__6_n_0 ),
        .O(\my_empty[4]_rep__1_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBD0000)) 
    \my_empty[4]_rep_i_1__2 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[1]),
        .I4(\my_empty_reg[4]_rep_n_0 ),
        .I5(\my_empty[4]_i_2__6_n_0 ),
        .O(\my_empty[4]_rep_i_1__2_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[0]_i_1__1_n_0 ),
        .Q(my_empty[0]),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__6_n_0 ),
        .Q(my_empty[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__1_n_0 ),
        .Q(my_empty[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__1_n_0 ),
        .Q(Q),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__1_n_0 ),
        .Q(my_empty[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep_i_1__2_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__0_i_1__2_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__1_i_1__2_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAA2AABAAAA2AA8)) 
    \my_full[0]_i_1__6 
       (.I0(my_full[0]),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I4(my_empty[1]),
        .I5(my_full0),
        .O(\my_full[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hFF007710)) 
    \my_full[1]_i_1__6 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(my_full0),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .O(\my_full[1]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair708" *) 
  LUT4 #(
    .INIT(16'h2442)) 
    \my_full[1]_i_2__4 
       (.I0(rd_ptr[0]),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(\wr_ptr_reg[1]_0 ),
        .I3(rd_ptr[1]),
        .O(my_full0));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__6_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1__6_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[120]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [57]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [57]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[121]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [49]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [49]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[122]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [41]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [41]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[123]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [33]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [33]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [11]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[124]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [25]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [25]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[125]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [17]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [17]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[126]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [9]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [9]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[127]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [1]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [1]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [15]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[184]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [58]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [58]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[185]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [50]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [50]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[186]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [42]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [42]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[187]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [34]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [34]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[188]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [26]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [26]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[189]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [18]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [18]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[190]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [10]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [10]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[191]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [2]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [2]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[248]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [59]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [59]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[249]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [51]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [51]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[250]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [43]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [43]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[251]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [35]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [35]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[252]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [27]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [27]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[253]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [19]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [19]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[254]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [11]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [11]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[255]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [3]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [3]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[312]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [60]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [60]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[313]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [52]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [52]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[314]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [44]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [44]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[315]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [36]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [36]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[316]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [28]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [28]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[317]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [20]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [20]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[318]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [12]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [12]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[319]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [4]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [4]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[376]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [61]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [61]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[377]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [53]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [53]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[378]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [45]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [45]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[379]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [37]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [37]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[380]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [29]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [29]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[381]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [21]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [21]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[382]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [13]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [13]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[383]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [5]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [5]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[440]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [62]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[441]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [54]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [54]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[442]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [46]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [46]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[443]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [38]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [38]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[444]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [30]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[445]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [22]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[446]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [14]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[447]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [6]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[504]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [63]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[505]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [55]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [55]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[506]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [47]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [47]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[507]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [39]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [39]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[508]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [31]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[509]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [23]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[510]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [15]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[511]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [7]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [63]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[56]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [56]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [56]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[57]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [48]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [48]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[58]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [40]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [40]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[59]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [32]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [32]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[60]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [24]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [24]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[61]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [16]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [16]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[62]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [8]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [8]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[511] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[63]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [0]),
        .I1(my_empty[4]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [0]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[511] [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [0]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [0]),
        .O(\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [8]),
        .O(\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [16]),
        .O(\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [24]),
        .O(\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [17]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [33]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [41]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [49]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [57]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [1]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [1]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [50]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [58]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [2]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [18]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [34]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [34]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [42]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [35]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [35]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [43]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [51]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [59]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [3]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [19]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [20]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [36]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [44]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [52]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [60]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [4]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [53]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [61]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [5]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [21]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [37]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [45]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [38]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [46]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [54]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [62]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [6]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [22]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [30]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [23]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [31]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [39]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [47]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [55]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [63]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [7]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [32]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [40]),
        .O(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [48]),
        .O(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] [56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] [56]),
        .O(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ));
  LUT2 #(
    .INIT(4'h1)) 
    rd_active_r_i_1
       (.I0(rd_active_r_reg),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(phy_rddata_en));
  (* SOFT_HLUTNM = "soft_lutpair709" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr[0]_i_1 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair709" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'h8ABA)) 
    \rd_ptr_timing[0]_i_1__1 
       (.I0(rd_ptr_timing[0]),
        .I1(my_empty[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hD0F2F2D0)) 
    \rd_ptr_timing[1]_i_1__6 
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr_timing[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[1]),
        .O(\rd_ptr_timing[1]_i_1__6_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__1_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__6_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'h0000AAA6)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_10 
       (.I0(tail_r),
        .I1(init_complete_r1_timing_reg),
        .I2(rd_active_r_reg),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .O(ADDRA));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_19 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I1(my_empty[0]),
        .I2(\my_empty_reg[4]_rep__1_2 ),
        .I3(if_empty_r_0),
        .I4(\my_empty_reg[0]_0 ),
        .O(rd_active_r_reg));
  LUT5 #(
    .INIT(32'hFDF80207)) 
    \wr_ptr[0]_i_1__12 
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(my_empty[1]),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_full[1]),
        .I4(\wr_ptr_reg[0]_0 ),
        .O(\wr_ptr[0]_i_1__12_n_0 ));
  LUT6 #(
    .INIT(64'hFFF5FDFD000A0202)) 
    \wr_ptr[1]_i_1__12 
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(my_full[1]),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(my_empty[1]),
        .I4(\my_empty_reg[4]_rep__1_0 ),
        .I5(\wr_ptr_reg[1]_0 ),
        .O(\wr_ptr[1]_i_1__12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000151515)) 
    \wr_ptr[1]_i_2__4 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I1(Q),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I3(\my_empty_reg[3]_0 ),
        .I4(if_empty_r_1),
        .I5(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .O(\my_empty_reg[4]_rep__1_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \wr_ptr[1]_i_4__0 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I1(Q),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .I3(\my_empty_reg[3]_1 ),
        .I4(\my_empty_reg[3]_0 ),
        .I5(if_empty_r_1),
        .O(\my_empty_reg[4]_rep__1_1 ));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__12_n_0 ),
        .Q(\wr_ptr_reg[0]_0 ),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__12_n_0 ),
        .Q(\wr_ptr_reg[1]_0 ),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_6
   (out,
    \my_empty_reg[4]_rep__1_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ,
    \not_strict_mode.app_rd_data_reg[487] ,
    p_0_in1_in,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_reg[1]_2 ,
    DIC,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \my_empty_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    Q,
    mem_out,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    ififo_rst,
    CLK);
  output [1:0]out;
  output [1:0]\my_empty_reg[4]_rep__1_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[487] ;
  output p_0_in1_in;
  output \wr_ptr_reg[1]_0 ;
  output \wr_ptr_reg[1]_1 ;
  output \wr_ptr_reg[1]_2 ;
  output [1:0]DIC;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \my_empty_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  input [63:0]Q;
  input [63:0]mem_out;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input ififo_rst;
  input CLK;

  wire CLK;
  wire [1:0]DIC;
  wire [63:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  wire ififo_rst;
  wire [63:0]mem_out;
  wire [4:1]my_empty;
  wire \my_empty[1]_i_1_n_0 ;
  wire \my_empty[1]_i_2_n_0 ;
  wire \my_empty[4]_i_1__5_n_0 ;
  wire \my_empty[4]_i_2_n_0 ;
  wire \my_empty[4]_rep__0_i_1_n_0 ;
  wire \my_empty[4]_rep__1_i_1_n_0 ;
  wire \my_empty[4]_rep_i_1_n_0 ;
  wire \my_empty_reg[3] ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire [1:0]\my_empty_reg[4]_rep__1_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1_n_0 ;
  wire \my_full[1]_i_1_n_0 ;
  wire \my_full[1]_i_2_n_0 ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[487] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire p_0_in1_in;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1_n_0 ;
  wire \rd_ptr[1]_i_1_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__2_n_0 ;
  wire \rd_ptr_timing[1]_i_1_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire \wr_ptr[0]_i_1__0_n_0 ;
  wire \wr_ptr[1]_i_1__0_n_0 ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;

  assign out[1:0] = rd_ptr_timing;
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[4].rd_data_rise_wl_r[4]_i_1 
       (.I0(\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .I1(\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .I2(\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .I3(\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .I4(\gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0 ),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[4].rd_data_rise_wl_r[4]_i_2 
       (.I0(\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .I1(Q[32]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(mem_out[32]),
        .I4(\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .I5(\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .O(\gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0407)) 
    mem_reg_0_3_0_5_i_1
       (.I0(my_full[0]),
        .I1(\my_empty_reg[3] ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I3(my_empty[2]),
        .O(p_0_in1_in));
  LUT1 #(
    .INIT(2'h2)) 
    mem_reg_0_3_0_5_i_2
       (.I0(\my_empty_reg[4]_rep__1_n_0 ),
        .O(my_empty[2]));
  LUT5 #(
    .INIT(32'hFF01CF00)) 
    \my_empty[1]_i_1 
       (.I0(\my_empty[1]_i_2_n_0 ),
        .I1(my_full[1]),
        .I2(\my_empty_reg[3] ),
        .I3(my_empty[1]),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .O(\my_empty[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT4 #(
    .INIT(16'hF69F)) 
    \my_empty[1]_i_2 
       (.I0(rd_ptr[1]),
        .I1(\wr_ptr_reg[1]_2 ),
        .I2(rd_ptr[0]),
        .I3(\wr_ptr_reg[1]_1 ),
        .O(\my_empty[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0024)) 
    \my_empty[4]_i_1__5 
       (.I0(\my_empty_reg[3] ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I2(my_empty[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT5 #(
    .INIT(32'h00002442)) 
    \my_empty[4]_i_2 
       (.I0(\wr_ptr_reg[1]_1 ),
        .I1(rd_ptr[0]),
        .I2(\wr_ptr_reg[1]_2 ),
        .I3(rd_ptr[1]),
        .I4(my_empty[1]),
        .O(\my_empty[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT5 #(
    .INIT(32'h00002442)) 
    \my_empty[4]_rep__0_i_1 
       (.I0(\wr_ptr_reg[1]_1 ),
        .I1(rd_ptr[0]),
        .I2(\wr_ptr_reg[1]_2 ),
        .I3(rd_ptr[1]),
        .I4(my_empty[1]),
        .O(\my_empty[4]_rep__0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT5 #(
    .INIT(32'h00002442)) 
    \my_empty[4]_rep__1_i_1 
       (.I0(\wr_ptr_reg[1]_1 ),
        .I1(rd_ptr[0]),
        .I2(\wr_ptr_reg[1]_2 ),
        .I3(rd_ptr[1]),
        .I4(my_empty[1]),
        .O(\my_empty[4]_rep__1_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT5 #(
    .INIT(32'h00002442)) 
    \my_empty[4]_rep_i_1 
       (.I0(\wr_ptr_reg[1]_1 ),
        .I1(rd_ptr[0]),
        .I2(\wr_ptr_reg[1]_2 ),
        .I3(rd_ptr[1]),
        .I4(my_empty[1]),
        .O(\my_empty[4]_rep_i_1_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1_n_0 ),
        .Q(my_empty[1]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(\my_empty[4]_i_1__5_n_0 ),
        .D(\my_empty[4]_i_2_n_0 ),
        .Q(my_empty[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(\my_empty[4]_i_1__5_n_0 ),
        .D(\my_empty[4]_rep_i_1_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(\my_empty[4]_i_1__5_n_0 ),
        .D(\my_empty[4]_rep__0_i_1_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(\my_empty[4]_i_1__5_n_0 ),
        .D(\my_empty[4]_rep__1_i_1_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAA8AA2AAAABAA2A)) 
    \my_full[0]_i_1 
       (.I0(my_full[0]),
        .I1(my_full[1]),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I3(my_empty[1]),
        .I4(\my_empty_reg[3] ),
        .I5(\my_full[1]_i_2_n_0 ),
        .O(\my_full[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF0F0C0F4)) 
    \my_full[1]_i_1 
       (.I0(\my_full[1]_i_2_n_0 ),
        .I1(\my_empty_reg[3] ),
        .I2(my_full[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I4(my_empty[1]),
        .O(\my_full[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT4 #(
    .INIT(16'hF96F)) 
    \my_full[1]_i_2 
       (.I0(\wr_ptr_reg[1]_2 ),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(\wr_ptr_reg[1]_1 ),
        .O(\my_full[1]_i_2_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[100]_i_1 
       (.I0(Q[25]),
        .I1(my_empty[4]),
        .I2(mem_out[25]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[101]_i_1 
       (.I0(Q[17]),
        .I1(my_empty[4]),
        .I2(mem_out[17]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[102]_i_1 
       (.I0(Q[9]),
        .I1(my_empty[4]),
        .I2(mem_out[9]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[103]_i_1 
       (.I0(Q[1]),
        .I1(my_empty[4]),
        .I2(mem_out[1]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [15]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[160]_i_1 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[161]_i_1 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[162]_i_1 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(mem_out[42]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[163]_i_1 
       (.I0(Q[34]),
        .I1(my_empty[4]),
        .I2(mem_out[34]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[164]_i_1 
       (.I0(Q[26]),
        .I1(my_empty[4]),
        .I2(mem_out[26]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[165]_i_1 
       (.I0(Q[18]),
        .I1(my_empty[4]),
        .I2(mem_out[18]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[166]_i_1 
       (.I0(Q[10]),
        .I1(my_empty[4]),
        .I2(mem_out[10]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[167]_i_1 
       (.I0(Q[2]),
        .I1(my_empty[4]),
        .I2(mem_out[2]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[224]_i_1 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[225]_i_1 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[226]_i_1 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(mem_out[43]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[227]_i_1 
       (.I0(Q[35]),
        .I1(my_empty[4]),
        .I2(mem_out[35]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[228]_i_1 
       (.I0(Q[27]),
        .I1(my_empty[4]),
        .I2(mem_out[27]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[229]_i_1 
       (.I0(Q[19]),
        .I1(my_empty[4]),
        .I2(mem_out[19]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[230]_i_1 
       (.I0(Q[11]),
        .I1(my_empty[4]),
        .I2(mem_out[11]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[231]_i_1 
       (.I0(Q[3]),
        .I1(my_empty[4]),
        .I2(mem_out[3]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[288]_i_1 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(mem_out[60]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[289]_i_1 
       (.I0(Q[52]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[52]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[290]_i_1 
       (.I0(Q[44]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[44]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[291]_i_1 
       (.I0(Q[36]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[36]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[292]_i_1 
       (.I0(Q[28]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[28]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[293]_i_1 
       (.I0(Q[20]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[20]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[294]_i_1 
       (.I0(Q[12]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[12]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[295]_i_1 
       (.I0(Q[4]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[4]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[32]_i_1 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[33]_i_1 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[34]_i_1 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(mem_out[40]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[352]_i_1 
       (.I0(Q[61]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[61]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[353]_i_1 
       (.I0(Q[53]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[53]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[354]_i_1 
       (.I0(Q[45]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[45]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[355]_i_1 
       (.I0(Q[37]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[37]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[356]_i_1 
       (.I0(Q[29]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[29]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[357]_i_1 
       (.I0(Q[21]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[21]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[358]_i_1 
       (.I0(Q[13]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[13]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[359]_i_1 
       (.I0(Q[5]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[5]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[35]_i_1 
       (.I0(Q[32]),
        .I1(my_empty[4]),
        .I2(mem_out[32]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[36]_i_1 
       (.I0(Q[24]),
        .I1(my_empty[4]),
        .I2(mem_out[24]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[37]_i_1 
       (.I0(Q[16]),
        .I1(my_empty[4]),
        .I2(mem_out[16]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[38]_i_1 
       (.I0(Q[8]),
        .I1(my_empty[4]),
        .I2(mem_out[8]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[39]_i_1 
       (.I0(Q[0]),
        .I1(my_empty[4]),
        .I2(mem_out[0]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [7]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[416]_i_1 
       (.I0(Q[62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[62]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[417]_i_1 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[54]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[418]_i_1 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[46]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[419]_i_1 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[38]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[420]_i_1 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[30]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[421]_i_1 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[22]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[422]_i_1 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[14]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[423]_i_1 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[6]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[480]_i_1 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[63]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[481]_i_1 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[55]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[482]_i_1 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[47]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[483]_i_1 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[39]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[484]_i_1 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[31]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[485]_i_1 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[23]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[486]_i_1 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[15]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[487]_i_1 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[7]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [63]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[96]_i_1 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[97]_i_1 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[98]_i_1 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(mem_out[41]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[487] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[99]_i_1 
       (.I0(Q[33]),
        .I1(my_empty[4]),
        .I2(mem_out[33]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[487] [11]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1 
       (.I0(Q[17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[17]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2 
       (.I0(Q[25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3 
       (.I0(Q[33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[33]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4 
       (.I0(Q[41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[41]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5 
       (.I0(Q[49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[49]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_6 
       (.I0(Q[57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[57]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5 
       (.I0(Q[1]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[1]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_6 
       (.I0(Q[9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1 
       (.I0(Q[50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[50]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2 
       (.I0(Q[58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[58]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1 
       (.I0(Q[2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[2]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2 
       (.I0(Q[10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3 
       (.I0(Q[18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[18]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4 
       (.I0(Q[26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5 
       (.I0(Q[34]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[34]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_6 
       (.I0(Q[42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[42]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1 
       (.I0(Q[35]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[35]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2 
       (.I0(Q[43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[43]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3 
       (.I0(Q[51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[51]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4 
       (.I0(Q[59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[59]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3 
       (.I0(Q[3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[3]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4 
       (.I0(Q[11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5 
       (.I0(Q[19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[19]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_6 
       (.I0(Q[27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1 
       (.I0(Q[20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[20]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2 
       (.I0(Q[28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3 
       (.I0(Q[36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[36]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4 
       (.I0(Q[44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[44]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5 
       (.I0(Q[52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[52]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_6 
       (.I0(Q[60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[60]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5 
       (.I0(Q[4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[4]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_6 
       (.I0(Q[12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1 
       (.I0(Q[53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[53]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2 
       (.I0(Q[61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[61]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1 
       (.I0(Q[5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[5]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2 
       (.I0(Q[13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3 
       (.I0(Q[21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[21]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4 
       (.I0(Q[29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5 
       (.I0(Q[37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[37]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_6 
       (.I0(Q[45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[45]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1 
       (.I0(Q[32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[32]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2 
       (.I0(Q[40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[40]),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3 
       (.I0(Q[48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[48]),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4 
       (.I0(Q[56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[56]),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[38]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[46]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[54]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4 
       (.I0(Q[62]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[62]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3 
       (.I0(Q[0]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[0]),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4 
       (.I0(Q[8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[8]),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5 
       (.I0(Q[16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[16]),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_6 
       (.I0(Q[24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[24]),
        .O(\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[6]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[22]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_6 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[23]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[39]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[47]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[55]),
        .O(DIC[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_6 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[63]),
        .O(DIC[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[7]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_6 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \rd_ptr[0]_i_1 
       (.I0(\my_empty_reg[3] ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT4 #(
    .INIT(16'hEF10)) 
    \rd_ptr[1]_i_1 
       (.I0(\my_empty_reg[3] ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hEF01)) 
    \rd_ptr_timing[0]_i_1__2 
       (.I0(\my_empty_reg[3] ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hEFFE0110)) 
    \rd_ptr_timing[1]_i_1 
       (.I0(\my_empty_reg[3] ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__2_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT1 #(
    .INIT(2'h2)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_21 
       (.I0(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\my_empty_reg[4]_rep__1_0 [0]));
  LUT5 #(
    .INIT(32'hFFE4001B)) 
    \wr_ptr[0]_i_1__0 
       (.I0(\my_empty_reg[3] ),
        .I1(my_empty[1]),
        .I2(my_full[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I4(\wr_ptr_reg[1]_1 ),
        .O(\wr_ptr[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFFDD02020022)) 
    \wr_ptr[1]_i_1__0 
       (.I0(\wr_ptr_reg[1]_1 ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(\my_empty_reg[3] ),
        .I5(\wr_ptr_reg[1]_2 ),
        .O(\wr_ptr[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT1 #(
    .INIT(2'h2)) 
    \wr_ptr[1]_i_3 
       (.I0(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\my_empty_reg[4]_rep__1_0 [1]));
  LUT2 #(
    .INIT(4'h7)) 
    \wr_ptr[1]_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I1(\my_empty_reg[4]_rep__1_0 [1]),
        .O(\wr_ptr_reg[1]_0 ));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__0_n_0 ),
        .Q(\wr_ptr_reg[1]_1 ),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__0_n_0 ),
        .Q(\wr_ptr_reg[1]_2 ),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_8
   (\wr_ptr_reg[1]_0 ,
    \my_empty_reg[4]_rep__1_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ,
    \my_empty_reg[0]_0 ,
    \not_strict_mode.app_rd_data_reg[455] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    if_empty_r_1,
    my_empty,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \my_empty_reg[3]_0 ,
    if_empty_r_3,
    \my_empty_reg[3]_1 ,
    \my_empty_reg[3]_2 ,
    if_empty_r,
    if_empty_r_0,
    \my_empty_reg[3]_3 ,
    Q,
    \read_fifo.fifo_out_data_r_reg[4] ,
    DOC,
    DOB,
    DOA,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    ififo_rst,
    CLK);
  output \wr_ptr_reg[1]_0 ;
  output \my_empty_reg[4]_rep__1_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  output [0:0]\my_empty_reg[0]_0 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[455] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input [0:0]if_empty_r_1;
  input [0:0]my_empty;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input \my_empty_reg[3]_0 ;
  input [0:0]if_empty_r_3;
  input [0:0]\my_empty_reg[3]_1 ;
  input [0:0]\my_empty_reg[3]_2 ;
  input [0:0]if_empty_r;
  input [0:0]if_empty_r_0;
  input [0:0]\my_empty_reg[3]_3 ;
  input [65:0]Q;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]DOA;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input ififo_rst;
  input CLK;

  wire CLK;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [65:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_r_1;
  wire [0:0]if_empty_r_3;
  wire ififo_rst;
  wire [71:8]mem_out;
  wire mem_reg_0_3_6_11_n_0;
  wire mem_reg_0_3_6_11_n_1;
  wire [0:0]my_empty;
  wire \my_empty[0]_i_1__5_n_0 ;
  wire \my_empty[1]_i_1__3_n_0 ;
  wire \my_empty[2]_i_1__8_n_0 ;
  wire \my_empty[3]_i_1__8_n_0 ;
  wire \my_empty[4]_i_1__9_n_0 ;
  wire \my_empty[4]_i_2__3_n_0 ;
  wire \my_empty[4]_rep__0_i_1__3_n_0 ;
  wire \my_empty[4]_rep__1_i_1__3_n_0 ;
  wire \my_empty[4]_rep_i_1__3_n_0 ;
  wire [4:1]my_empty_0;
  wire [0:0]\my_empty_reg[0]_0 ;
  wire \my_empty_reg[3]_0 ;
  wire [0:0]\my_empty_reg[3]_1 ;
  wire [0:0]\my_empty_reg[3]_2 ;
  wire [0:0]\my_empty_reg[3]_3 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__3_n_0 ;
  wire \my_full[1]_i_1__3_n_0 ;
  wire \my_full[1]_i_2__3_n_0 ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[455] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__3_n_0 ;
  wire \rd_ptr[1]_i_1__3_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__6_n_0 ;
  wire \rd_ptr_timing[1]_i_1__3_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__10_n_0 ;
  wire \wr_ptr[1]_i_1__10_n_0 ;
  wire \wr_ptr[1]_i_2__0_n_0 ;
  wire \wr_ptr_reg[1]_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;

  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[0].rd_data_rise_wl_r[0]_i_1 
       (.I0(\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .I1(\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .I3(\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .I4(\gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[0].rd_data_rise_wl_r[0]_i_2 
       (.I0(\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .I1(Q[34]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(mem_out[40]),
        .I4(\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .I5(\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .O(\gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ));
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[13:12]),
        .DOB(mem_out[15:14]),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0047)) 
    mem_reg_0_3_6_11_i_1__1
       (.I0(my_full[0]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[2]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(wr_en));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[0]_i_1__5 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__3_n_0 ),
        .I5(\my_empty_reg[0]_0 ),
        .O(\my_empty[0]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hCDCCCD0C)) 
    \my_empty[1]_i_1__3 
       (.I0(\my_empty[4]_i_2__3_n_0 ),
        .I1(my_empty_0[1]),
        .I2(\wr_ptr[1]_i_2__0_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .O(\my_empty[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[2]_i_1__8 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__3_n_0 ),
        .I5(my_empty_0[2]),
        .O(\my_empty[2]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[3]_i_1__8 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__3_n_0 ),
        .I5(my_empty_0[3]),
        .O(\my_empty[3]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_i_1__9 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__3_n_0 ),
        .I5(my_empty_0[4]),
        .O(\my_empty[4]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT5 #(
    .INIT(32'hFDEFEFFD)) 
    \my_empty[4]_i_2__3 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(wr_ptr[1]),
        .O(\my_empty[4]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__0_i_1__3 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__3_n_0 ),
        .I5(\my_empty_reg[4]_rep__0_n_0 ),
        .O(\my_empty[4]_rep__0_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__1_i_1__3 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__3_n_0 ),
        .I5(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\my_empty[4]_rep__1_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep_i_1__3 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__3_n_0 ),
        .I5(\my_empty_reg[4]_rep_n_0 ),
        .O(\my_empty[4]_rep_i_1__3_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[0]_i_1__5_n_0 ),
        .Q(\my_empty_reg[0]_0 ),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__3_n_0 ),
        .Q(my_empty_0[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__8_n_0 ),
        .Q(my_empty_0[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__8_n_0 ),
        .Q(my_empty_0[3]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__9_n_0 ),
        .Q(my_empty_0[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep_i_1__3_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__0_i_1__3_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__1_i_1__3_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hA8AAAA8AA8AAAABA)) 
    \my_full[0]_i_1__3 
       (.I0(my_full[0]),
        .I1(my_empty_0[1]),
        .I2(\wr_ptr[1]_i_2__0_n_0 ),
        .I3(my_full[1]),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I5(\my_full[1]_i_2__3_n_0 ),
        .O(\my_full[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAA0BA)) 
    \my_full[1]_i_1__3 
       (.I0(my_full[1]),
        .I1(\my_full[1]_i_2__3_n_0 ),
        .I2(\wr_ptr[1]_i_2__0_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty_0[1]),
        .O(\my_full[1]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT4 #(
    .INIT(16'hF96F)) 
    \my_full[1]_i_2__3 
       (.I0(wr_ptr[1]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(wr_ptr[0]),
        .O(\my_full[1]_i_2__3_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__3_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1__3_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[0]_i_1 
       (.I0(Q[58]),
        .I1(my_empty_0[4]),
        .I2(mem_out[64]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(DOC[0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[128]_i_1 
       (.I0(Q[60]),
        .I1(my_empty_0[4]),
        .I2(mem_out[66]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[129]_i_1 
       (.I0(Q[52]),
        .I1(my_empty_0[4]),
        .I2(mem_out[58]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[130]_i_1 
       (.I0(Q[44]),
        .I1(my_empty_0[4]),
        .I2(mem_out[50]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[131]_i_1 
       (.I0(Q[36]),
        .I1(my_empty_0[4]),
        .I2(mem_out[42]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[132]_i_1 
       (.I0(Q[28]),
        .I1(my_empty_0[4]),
        .I2(mem_out[34]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[133]_i_1 
       (.I0(Q[20]),
        .I1(my_empty_0[4]),
        .I2(mem_out[26]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[134]_i_1 
       (.I0(Q[12]),
        .I1(my_empty_0[4]),
        .I2(mem_out[18]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[135]_i_1 
       (.I0(Q[4]),
        .I1(my_empty_0[4]),
        .I2(mem_out[10]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[192]_i_1 
       (.I0(Q[61]),
        .I1(my_empty_0[4]),
        .I2(mem_out[67]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[193]_i_1 
       (.I0(Q[53]),
        .I1(my_empty_0[4]),
        .I2(mem_out[59]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[194]_i_1 
       (.I0(Q[45]),
        .I1(my_empty_0[4]),
        .I2(mem_out[51]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[195]_i_1 
       (.I0(Q[37]),
        .I1(my_empty_0[4]),
        .I2(mem_out[43]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[196]_i_1 
       (.I0(Q[29]),
        .I1(my_empty_0[4]),
        .I2(mem_out[35]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[197]_i_1 
       (.I0(Q[21]),
        .I1(my_empty_0[4]),
        .I2(mem_out[27]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[198]_i_1 
       (.I0(Q[13]),
        .I1(my_empty_0[4]),
        .I2(mem_out[19]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[199]_i_1 
       (.I0(Q[5]),
        .I1(my_empty_0[4]),
        .I2(mem_out[11]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[1]_i_1 
       (.I0(Q[50]),
        .I1(my_empty_0[4]),
        .I2(mem_out[56]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(DOC[1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[256]_i_1 
       (.I0(Q[62]),
        .I1(my_empty_0[4]),
        .I2(mem_out[68]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[257]_i_1 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[60]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[258]_i_1 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[52]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[259]_i_1 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[44]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[260]_i_1 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[36]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[261]_i_1 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[28]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[262]_i_1 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[20]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[263]_i_1 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[12]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[2]_i_1 
       (.I0(Q[42]),
        .I1(my_empty_0[4]),
        .I2(mem_out[48]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(DOB[0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[320]_i_1 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[69]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[321]_i_1 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[61]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[322]_i_1 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[53]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[323]_i_1 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[45]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[324]_i_1 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[37]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[325]_i_1 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[29]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[326]_i_1 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[21]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[327]_i_1 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[13]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[384]_i_1 
       (.I0(Q[64]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[70]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[385]_i_1 
       (.I0(Q[56]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[62]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[386]_i_1 
       (.I0(Q[48]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[54]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[387]_i_1 
       (.I0(Q[40]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[46]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[388]_i_1 
       (.I0(Q[32]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[38]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[389]_i_1 
       (.I0(Q[24]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[30]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[390]_i_1 
       (.I0(Q[16]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[22]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[391]_i_1 
       (.I0(Q[8]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[14]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[3]_i_1 
       (.I0(Q[34]),
        .I1(my_empty_0[4]),
        .I2(mem_out[40]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(DOB[1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[448]_i_1 
       (.I0(Q[65]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[71]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[449]_i_1 
       (.I0(Q[57]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[63]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[450]_i_1 
       (.I0(Q[49]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[55]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[451]_i_1 
       (.I0(Q[41]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[47]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[452]_i_1 
       (.I0(Q[33]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[39]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[453]_i_1 
       (.I0(Q[25]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[31]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[454]_i_1 
       (.I0(Q[17]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[23]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[455]_i_1 
       (.I0(Q[9]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[15]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [63]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[4]_i_1 
       (.I0(Q[26]),
        .I1(my_empty_0[4]),
        .I2(mem_out[32]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(DOA[0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[5]_i_1 
       (.I0(Q[18]),
        .I1(my_empty_0[4]),
        .I2(mem_out[24]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(DOA[1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[64]_i_1 
       (.I0(Q[59]),
        .I1(my_empty_0[4]),
        .I2(mem_out[65]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[65]_i_1 
       (.I0(Q[51]),
        .I1(my_empty_0[4]),
        .I2(mem_out[57]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[66]_i_1 
       (.I0(Q[43]),
        .I1(my_empty_0[4]),
        .I2(mem_out[49]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[67]_i_1 
       (.I0(Q[35]),
        .I1(my_empty_0[4]),
        .I2(mem_out[41]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [11]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[68]_i_1 
       (.I0(Q[27]),
        .I1(my_empty_0[4]),
        .I2(mem_out[33]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[69]_i_1 
       (.I0(Q[19]),
        .I1(my_empty_0[4]),
        .I2(mem_out[25]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[6]_i_1 
       (.I0(Q[10]),
        .I1(my_empty_0[4]),
        .I2(mem_out[16]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[70]_i_1 
       (.I0(Q[11]),
        .I1(my_empty_0[4]),
        .I2(mem_out[17]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[455] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[71]_i_1 
       (.I0(Q[3]),
        .I1(my_empty_0[4]),
        .I2(mem_out[9]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [15]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[7]_i_1 
       (.I0(Q[2]),
        .I1(my_empty_0[4]),
        .I2(mem_out[8]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[455] [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2 
       (.I0(Q[18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[24]),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3 
       (.I0(Q[26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[32]),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4 
       (.I0(Q[34]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[40]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5 
       (.I0(Q[42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[48]),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_6 
       (.I0(Q[50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[56]),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_7 
       (.I0(Q[58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[64]),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1 
       (.I0(Q[51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[57]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2 
       (.I0(Q[59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[65]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1 
       (.I0(Q[3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2 
       (.I0(Q[11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[17]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3 
       (.I0(Q[19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4 
       (.I0(Q[27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[33]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5 
       (.I0(Q[35]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[41]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_6 
       (.I0(Q[43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[49]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5 
       (.I0(Q[2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[8]),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_6 
       (.I0(Q[10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[16]),
        .O(\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1 
       (.I0(Q[36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[42]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2 
       (.I0(Q[44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[50]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3 
       (.I0(Q[52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[58]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4 
       (.I0(Q[60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[66]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3 
       (.I0(Q[4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4 
       (.I0(Q[12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[18]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5 
       (.I0(Q[20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_6 
       (.I0(Q[28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[34]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1 
       (.I0(Q[21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2 
       (.I0(Q[29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[35]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3 
       (.I0(Q[37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[43]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4 
       (.I0(Q[45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[51]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5 
       (.I0(Q[53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[59]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_6 
       (.I0(Q[61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[67]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5 
       (.I0(Q[5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_6 
       (.I0(Q[13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[19]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1 
       (.I0(Q[54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[60]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2 
       (.I0(Q[62]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[68]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1 
       (.I0(Q[6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2 
       (.I0(Q[14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[20]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3 
       (.I0(Q[22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4 
       (.I0(Q[30]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[36]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5 
       (.I0(Q[38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[44]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_6 
       (.I0(Q[46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[52]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1 
       (.I0(Q[39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[45]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2 
       (.I0(Q[47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[53]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3 
       (.I0(Q[55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[61]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4 
       (.I0(Q[63]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[69]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3 
       (.I0(Q[7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4 
       (.I0(Q[15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[21]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5 
       (.I0(Q[23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_6 
       (.I0(Q[31]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[37]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1 
       (.I0(Q[24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2 
       (.I0(Q[32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[38]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3 
       (.I0(Q[40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[46]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4 
       (.I0(Q[48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[54]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5 
       (.I0(Q[56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[62]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_6 
       (.I0(Q[64]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[70]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5 
       (.I0(Q[8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_6 
       (.I0(Q[16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[22]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1 
       (.I0(Q[57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[63]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2 
       (.I0(Q[65]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[71]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1 
       (.I0(Q[9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2 
       (.I0(Q[17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[23]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3 
       (.I0(Q[25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4 
       (.I0(Q[33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[39]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5 
       (.I0(Q[41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[47]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_6 
       (.I0(Q[49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[55]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \rd_ptr[0]_i_1__3 
       (.I0(\wr_ptr[1]_i_2__0_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT4 #(
    .INIT(16'hEF10)) 
    \rd_ptr[1]_i_1__3 
       (.I0(\wr_ptr[1]_i_2__0_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__3_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__3_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__3_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hE0F1)) 
    \rd_ptr_timing[0]_i_1__6 
       (.I0(\wr_ptr[1]_i_2__0_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr_timing[0]),
        .I3(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hE0F1F1E0)) 
    \rd_ptr_timing[1]_i_1__3 
       (.I0(\wr_ptr[1]_i_2__0_n_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr_timing[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[1]),
        .O(\rd_ptr_timing[1]_i_1__3_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__6_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__3_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFDEC0213)) 
    \wr_ptr[0]_i_1__10 
       (.I0(\wr_ptr[1]_i_2__0_n_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(my_full[1]),
        .I3(my_empty_0[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__10_n_0 ));
  LUT6 #(
    .INIT(64'hFFF5FFDD000A0022)) 
    \wr_ptr[1]_i_1__10 
       (.I0(wr_ptr[0]),
        .I1(my_empty_0[1]),
        .I2(my_full[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\wr_ptr[1]_i_2__0_n_0 ),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \wr_ptr[1]_i_2__0 
       (.I0(if_empty_r_1),
        .I1(my_empty),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I3(my_empty_0[3]),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I5(\my_empty_reg[3]_0 ),
        .O(\wr_ptr[1]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \wr_ptr[1]_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I1(my_empty_0[3]),
        .I2(if_empty_r_3),
        .I3(\my_empty_reg[3]_1 ),
        .O(\wr_ptr_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \wr_ptr[1]_i_5__0 
       (.I0(my_empty_0[3]),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(\my_empty_reg[3]_2 ),
        .I3(if_empty_r),
        .I4(if_empty_r_0),
        .I5(\my_empty_reg[3]_3 ),
        .O(\my_empty_reg[4]_rep__1_0 ));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__10_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__10_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_if_post_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_9
   (Q,
    \my_empty_reg[4]_rep__1_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ,
    \not_strict_mode.app_rd_data_reg[463] ,
    \wr_ptr_reg[1]_0 ,
    C_byte_rd_en,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    B_byte_rd_en,
    if_empty_r_2,
    \my_empty_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    ififo_rst,
    CLK);
  output [1:0]Q;
  output \my_empty_reg[4]_rep__1_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[463] ;
  output \wr_ptr_reg[1]_0 ;
  output C_byte_rd_en;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  input B_byte_rd_en;
  input [0:0]if_empty_r_2;
  input [0:0]\my_empty_reg[3]_0 ;
  input [65:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  input ififo_rst;
  input CLK;

  wire B_byte_rd_en;
  wire CLK;
  wire C_byte_rd_en;
  wire [1:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire [65:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  wire [0:0]if_empty_r_2;
  wire ififo_rst;
  wire [71:8]mem_out;
  wire mem_reg_0_3_6_11_n_0;
  wire mem_reg_0_3_6_11_n_1;
  wire [4:1]my_empty;
  wire \my_empty[0]_i_1__4_n_0 ;
  wire \my_empty[1]_i_1__2_n_0 ;
  wire \my_empty[2]_i_1__7_n_0 ;
  wire \my_empty[3]_i_1__7_n_0 ;
  wire \my_empty[4]_i_1__8_n_0 ;
  wire \my_empty[4]_i_2__2_n_0 ;
  wire \my_empty[4]_rep__0_i_1__4_n_0 ;
  wire \my_empty[4]_rep__1_i_1__4_n_0 ;
  wire \my_empty[4]_rep_i_1__4_n_0 ;
  wire [0:0]\my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__2_n_0 ;
  wire \my_full[1]_i_1__2_n_0 ;
  wire \my_full[1]_i_2__2_n_0 ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[463] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__2_n_0 ;
  wire \rd_ptr[1]_i_1__2_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__5_n_0 ;
  wire \rd_ptr_timing[1]_i_1__2_n_0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__8_n_0 ;
  wire \wr_ptr[1]_i_1__8_n_0 ;
  wire \wr_ptr[1]_i_2__1_n_0 ;
  wire \wr_ptr_reg[1]_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;

  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[1].rd_data_rise_wl_r[1]_i_1 
       (.I0(\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .I1(\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .I2(\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .I3(\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .I4(\gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \gen_rd[1].rd_data_rise_wl_r[1]_i_2 
       (.I0(\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .I1(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [34]),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(mem_out[40]),
        .I4(\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .I5(\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .O(\gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ));
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [7:6]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [9:8]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[13:12]),
        .DOB(mem_out[15:14]),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [13:12]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [15:14]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [19:18]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [21:20]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [25:24]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [27:26]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [31:30]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [33:32]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [37:36]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [39:38]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [43:42]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [45:44]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [49:48]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [51:50]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [55:54]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [57:56]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [61:60]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [63:62]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [1:0]),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [3:2]),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0047)) 
    mem_reg_0_3_6_11_i_1__0
       (.I0(my_full[0]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[2]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(wr_en));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[0]_i_1__4 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__2_n_0 ),
        .I5(Q[0]),
        .O(\my_empty[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hCDCCCD0C)) 
    \my_empty[1]_i_1__2 
       (.I0(\my_empty[4]_i_2__2_n_0 ),
        .I1(my_empty[1]),
        .I2(\wr_ptr[1]_i_2__1_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_full[1]),
        .O(\my_empty[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[2]_i_1__7 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__2_n_0 ),
        .I5(my_empty[2]),
        .O(\my_empty[2]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[3]_i_1__7 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__2_n_0 ),
        .I5(Q[1]),
        .O(\my_empty[3]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_i_1__8 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__2_n_0 ),
        .I5(my_empty[4]),
        .O(\my_empty[4]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT5 #(
    .INIT(32'hFDEFEFFD)) 
    \my_empty[4]_i_2__2 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(wr_ptr[1]),
        .O(\my_empty[4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__0_i_1__4 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__2_n_0 ),
        .I5(\my_empty_reg[4]_rep__0_n_0 ),
        .O(\my_empty[4]_rep__0_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep__1_i_1__4 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__2_n_0 ),
        .I5(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\my_empty[4]_rep__1_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFEBFFFBF00000300)) 
    \my_empty[4]_rep_i_1__4 
       (.I0(my_full[1]),
        .I1(\wr_ptr[1]_i_2__1_n_0 ),
        .I2(my_empty[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\my_empty[4]_i_2__2_n_0 ),
        .I5(\my_empty_reg[4]_rep_n_0 ),
        .O(\my_empty[4]_rep_i_1__4_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[0]_i_1__4_n_0 ),
        .Q(Q[0]),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__2_n_0 ),
        .Q(my_empty[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__7_n_0 ),
        .Q(my_empty[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__7_n_0 ),
        .Q(Q[1]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__8_n_0 ),
        .Q(my_empty[4]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep_i_1__4_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__0_i_1__4_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_rep__1_i_1__4_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hA8AAAA8AA8AAAABA)) 
    \my_full[0]_i_1__2 
       (.I0(my_full[0]),
        .I1(my_empty[1]),
        .I2(\wr_ptr[1]_i_2__1_n_0 ),
        .I3(my_full[1]),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I5(\my_full[1]_i_2__2_n_0 ),
        .O(\my_full[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAA0BA)) 
    \my_full[1]_i_1__2 
       (.I0(my_full[1]),
        .I1(\my_full[1]_i_2__2_n_0 ),
        .I2(\wr_ptr[1]_i_2__1_n_0 ),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(my_empty[1]),
        .O(\my_full[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT4 #(
    .INIT(16'hF96F)) 
    \my_full[1]_i_2__2 
       (.I0(wr_ptr[1]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(wr_ptr[0]),
        .O(\my_full[1]_i_2__2_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__2_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[1]_i_1__2_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[10]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [42]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[11]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [34]),
        .I1(my_empty[4]),
        .I2(mem_out[40]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[12]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [26]),
        .I1(my_empty[4]),
        .I2(mem_out[32]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[136]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [60]),
        .I1(my_empty[4]),
        .I2(mem_out[66]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [16]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[137]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [52]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [17]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[138]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [44]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [18]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[139]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [36]),
        .I1(my_empty[4]),
        .I2(mem_out[42]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [19]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[13]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [18]),
        .I1(my_empty[4]),
        .I2(mem_out[24]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[140]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [28]),
        .I1(my_empty[4]),
        .I2(mem_out[34]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [20]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[141]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [20]),
        .I1(my_empty[4]),
        .I2(mem_out[26]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [21]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[142]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [12]),
        .I1(my_empty[4]),
        .I2(mem_out[18]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [22]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[143]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [4]),
        .I1(my_empty[4]),
        .I2(mem_out[10]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [23]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[14]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [10]),
        .I1(my_empty[4]),
        .I2(mem_out[16]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[15]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [2]),
        .I1(my_empty[4]),
        .I2(mem_out[8]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [7]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[200]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [61]),
        .I1(my_empty[4]),
        .I2(mem_out[67]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [24]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[201]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [53]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [25]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[202]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [45]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [26]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[203]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [37]),
        .I1(my_empty[4]),
        .I2(mem_out[43]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [27]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[204]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [29]),
        .I1(my_empty[4]),
        .I2(mem_out[35]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [28]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[205]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [21]),
        .I1(my_empty[4]),
        .I2(mem_out[27]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [29]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[206]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [13]),
        .I1(my_empty[4]),
        .I2(mem_out[19]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [30]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[207]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [5]),
        .I1(my_empty[4]),
        .I2(mem_out[11]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [31]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[264]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [62]),
        .I1(my_empty[4]),
        .I2(mem_out[68]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [32]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[265]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [54]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[60]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [33]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[266]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [46]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[52]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [34]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[267]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [38]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[44]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [35]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[268]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [30]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[36]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [36]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[269]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [22]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[28]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [37]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[270]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [14]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[20]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [38]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[271]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [6]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[12]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [39]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[328]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [63]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[69]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [40]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[329]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [55]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[61]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [41]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[330]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [47]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[53]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [42]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[331]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [39]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[45]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [43]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[332]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [31]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[37]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [44]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[333]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [23]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[29]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [45]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[334]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [15]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[21]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [46]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[335]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [7]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[13]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [47]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[392]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [64]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[70]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [48]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[393]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [56]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[62]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [49]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[394]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [48]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[54]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [50]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[395]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [40]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[46]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [51]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[396]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [32]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[38]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [52]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[397]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [24]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[30]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [53]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[398]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [16]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[22]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [54]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[399]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [8]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[14]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [55]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[456]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [65]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[71]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [56]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[457]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [57]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[63]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [57]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[458]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [49]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[55]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [58]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[459]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [41]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[47]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [59]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[460]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [33]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[39]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [60]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[461]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [25]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[31]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [61]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[462]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [17]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[23]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [62]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[463]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [9]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[15]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [63]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[72]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [59]),
        .I1(my_empty[4]),
        .I2(mem_out[65]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [8]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[73]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [51]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [9]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[74]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [43]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [10]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[75]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [35]),
        .I1(my_empty[4]),
        .I2(mem_out[41]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [11]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[76]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [27]),
        .I1(my_empty[4]),
        .I2(mem_out[33]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [12]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[77]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [19]),
        .I1(my_empty[4]),
        .I2(mem_out[25]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [13]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[78]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [11]),
        .I1(my_empty[4]),
        .I2(mem_out[17]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [14]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[79]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [3]),
        .I1(my_empty[4]),
        .I2(mem_out[9]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [15]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[8]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [58]),
        .I1(my_empty[4]),
        .I2(mem_out[64]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),
        .O(\not_strict_mode.app_rd_data_reg[463] [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \not_strict_mode.app_rd_data[9]_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [50]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .I3(\read_fifo.fifo_out_data_r_reg[4] ),
        .I4(\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),
        .O(\not_strict_mode.app_rd_data_reg[463] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [19]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[25]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [27]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[33]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [35]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[41]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [43]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[49]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [51]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[57]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [59]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[65]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [3]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[9]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [11]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[17]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [34]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[40]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [42]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[48]),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [50]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[56]),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [58]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[64]),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [52]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[58]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [60]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[66]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [4]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[10]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [12]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[18]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [20]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[26]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [28]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[34]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [36]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[42]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [44]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[50]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [2]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[8]),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [10]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[16]),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [18]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[24]),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [26]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[32]),
        .O(\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [37]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[43]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [45]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[51]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [53]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[59]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [61]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[67]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [5]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[11]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [13]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[19]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [21]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[27]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [29]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[35]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [22]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[28]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [30]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[36]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [38]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[44]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [46]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[52]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [54]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[60]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [62]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[68]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [6]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[12]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [14]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[20]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [55]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[61]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [63]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[69]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [7]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[13]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [15]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[21]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [23]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[29]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [31]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[37]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [39]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[45]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [47]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[53]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [40]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[46]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [48]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[54]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [56]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[62]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [64]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[70]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [8]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[14]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [16]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[22]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [24]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[30]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [32]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[38]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [25]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[31]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [33]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[39]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [41]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[47]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [49]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[55]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [57]),
        .I1(\my_empty_reg[4]_rep__0_n_0 ),
        .I2(mem_out[63]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [65]),
        .I1(\my_empty_reg[4]_rep_n_0 ),
        .I2(mem_out[71]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [9]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[15]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_6 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] [17]),
        .I1(\my_empty_reg[4]_rep__1_n_0 ),
        .I2(mem_out[23]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \rd_ptr[0]_i_1__2 
       (.I0(\wr_ptr[1]_i_2__1_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT4 #(
    .INIT(16'hEF10)) 
    \rd_ptr[1]_i_1__2 
       (.I0(\wr_ptr[1]_i_2__1_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__2_n_0 ));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__2_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__2_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hE0F1)) 
    \rd_ptr_timing[0]_i_1__5 
       (.I0(\wr_ptr[1]_i_2__1_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr_timing[0]),
        .I3(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hE0F1F1E0)) 
    \rd_ptr_timing[1]_i_1__2 
       (.I0(\wr_ptr[1]_i_2__1_n_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr_timing[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[1]),
        .O(\rd_ptr_timing[1]_i_1__2_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__5_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__2_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFDEC0213)) 
    \wr_ptr[0]_i_1__8 
       (.I0(\wr_ptr[1]_i_2__1_n_0 ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'hFFF5FFDD000A0022)) 
    \wr_ptr[1]_i_1__8 
       (.I0(wr_ptr[0]),
        .I1(my_empty[1]),
        .I2(my_full[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\wr_ptr[1]_i_2__1_n_0 ),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF777FFFFFFFF)) 
    \wr_ptr[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .I1(B_byte_rd_en),
        .I2(Q[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I5(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .O(\wr_ptr_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFD5FFFFFFFF)) 
    \wr_ptr[1]_i_2__1 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .I2(Q[1]),
        .I3(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I4(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .I5(B_byte_rd_en),
        .O(\wr_ptr[1]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \wr_ptr[1]_i_3__0 
       (.I0(Q[1]),
        .I1(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(C_byte_rd_en));
  LUT6 #(
    .INIT(64'hFFFF8FFF8FFF8FFF)) 
    \wr_ptr[1]_i_3__2 
       (.I0(if_empty_r_2),
        .I1(\my_empty_reg[3]_0 ),
        .I2(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .I3(B_byte_rd_en),
        .I4(Q[1]),
        .I5(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .O(\my_empty_reg[4]_rep__1_0 ));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__8_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__8_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_mc_phy" *) 
module mig_7series_0_mig_7series_v2_3_ddr_mc_phy
   (out,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    COUNTERREADVAL,
    ofifo_rst_reg,
    \pi_dqs_found_lanes_r1_reg[4] ,
    \pi_dqs_found_lanes_r1_reg[4]_0 ,
    p_98_in,
    p_97_in,
    p_102_in,
    p_101_in,
    p_106_in,
    p_105_in,
    p_110_in,
    p_109_in,
    p_114_in,
    p_113_in,
    p_118_in,
    p_117_in,
    p_122_in,
    p_121_in,
    p_126_in,
    p_125_in,
    \ddr3_dm[4] ,
    p_9_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    p_134_in,
    p_133_in,
    p_138_in,
    p_137_in,
    p_142_in,
    p_141_in,
    p_146_in,
    p_145_in,
    p_150_in,
    p_149_in,
    p_154_in,
    p_153_in,
    p_158_in,
    p_157_in,
    p_13_in,
    \ddr3_dm[3] ,
    idelay_ld_rst,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    p_28_in,
    p_27_in,
    p_162_in,
    p_161_in,
    p_166_in,
    p_165_in,
    p_170_in,
    p_169_in,
    p_174_in,
    p_173_in,
    \ddr3_dm[2] ,
    p_15_in,
    p_178_in,
    p_177_in,
    p_182_in,
    p_181_in,
    p_186_in,
    p_185_in,
    p_190_in,
    p_189_in,
    idelay_ld_rst_0,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \pi_dqs_found_lanes_r1_reg[2] ,
    p_32_in,
    p_194_in,
    p_193_in,
    p_198_in,
    p_197_in,
    p_202_in,
    p_201_in,
    p_206_in,
    p_205_in,
    p_210_in,
    p_209_in,
    p_214_in,
    p_213_in,
    p_218_in,
    p_217_in,
    p_222_in,
    p_221_in,
    p_19_in,
    \ddr3_dm[1] ,
    idelay_ld_rst_1,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    p_226_in,
    p_225_in,
    p_230_in,
    p_229_in,
    p_234_in,
    p_233_in,
    p_238_in,
    p_237_in,
    p_242_in,
    p_241_in,
    p_246_in,
    p_245_in,
    p_250_in,
    p_249_in,
    p_254_in,
    p_253_in,
    \ddr3_dm[0] ,
    p_21_in,
    idelay_ld_rst_2,
    \rd_ptr_timing_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ,
    p_5_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ,
    p_17_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_16 ,
    p_25_in,
    p_30_in,
    p_29_in,
    p_1_in,
    \ddr3_dm[7] ,
    \rd_ptr_timing_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_17 ,
    \my_empty_reg[7] ,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    p_34_in,
    p_33_in,
    p_38_in,
    p_37_in,
    p_42_in,
    p_41_in,
    p_46_in,
    p_45_in,
    \ddr3_dm[6] ,
    p_3_in,
    p_50_in,
    p_49_in,
    p_54_in,
    p_53_in,
    p_58_in,
    p_57_in,
    p_62_in,
    p_61_in,
    \rd_ptr_timing_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_18 ,
    \my_empty_reg[7]_0 ,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    p_66_in,
    p_65_in,
    p_70_in,
    p_69_in,
    p_74_in,
    p_73_in,
    p_78_in,
    p_77_in,
    p_82_in,
    p_81_in,
    p_86_in,
    p_85_in,
    p_90_in,
    p_89_in,
    p_94_in,
    p_93_in,
    p_7_in,
    \ddr3_dm[5] ,
    idelay_ld_rst_3,
    \my_empty_reg[7]_1 ,
    idelay_ld_rst_4,
    \my_empty_reg[7]_2 ,
    idelay_ld_rst_5,
    phy_ctl_ready,
    ddr_ck_out,
    phy_mc_ctl_full,
    phy_rddata_en,
    rd_active_r_reg,
    \read_fifo.tail_r_reg[1] ,
    rd_buf_we,
    \my_empty_reg[1] ,
    \read_fifo.tail_r_reg[3] ,
    ADDRA,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    \not_strict_mode.app_rd_data_reg[352] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ,
    \my_empty_reg[1]_0 ,
    phy_mc_data_full,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ,
    \my_empty_reg[1]_3 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \my_empty_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ,
    \my_empty_reg[1]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ,
    \my_empty_reg[1]_6 ,
    rst_sync_r1_reg,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \not_strict_mode.app_rd_data_reg[488] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \my_empty_reg[1]_7 ,
    \my_empty_reg[1]_8 ,
    \my_empty_reg[1]_9 ,
    pi_phase_locked_all_r1_reg,
    \read_fifo.tail_r_reg[0] ,
    \read_fifo.tail_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    DIA,
    DIB,
    DIC,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ,
    store_sr_req_r_reg,
    \pi_rdval_cnt_reg[4] ,
    \pi_rdval_cnt_reg[1] ,
    \pi_rdval_cnt_reg[2] ,
    \pi_rdval_cnt_reg[3] ,
    \pi_rdval_cnt_reg[0] ,
    \pi_rdval_cnt_reg[5] ,
    \FSM_onehot_cal1_state_r_reg[0] ,
    \FSM_onehot_cal1_state_r_reg[0]_0 ,
    \FSM_onehot_cal1_state_r_reg[0]_1 ,
    \not_strict_mode.app_rd_data_reg[511] ,
    \not_strict_mode.app_rd_data_reg[24] ,
    wr_en,
    wr_en_10,
    wr_en_11,
    of_ctl_full_v,
    wr_en_12,
    wr_en_13,
    wr_en_14,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7]_3 ,
    idelay_ld_rst_6,
    \wr_ptr_timing_reg[3]_0 ,
    \wr_ptr_timing_reg[0] ,
    mem_dq_out,
    \wr_ptr_timing_reg[3]_1 ,
    \wr_ptr_timing_reg[0]_0 ,
    \ddr3_addr[3] ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    \my_empty_reg[7]_7 ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_timing_reg[3]_2 ,
    \my_empty_reg[7]_8 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_2 ,
    \wr_ptr_timing_reg[3]_3 ,
    \my_empty_reg[7]_9 ,
    \wr_ptr_reg[0]_1 ,
    \wr_ptr_reg[1]_3 ,
    \wr_ptr_timing_reg[3]_4 ,
    \my_empty_reg[7]_10 ,
    \ddr3_addr[13] ,
    \my_empty_reg[6] ,
    p_0_in1_in,
    \not_strict_mode.app_rd_data_reg[232] ,
    \not_strict_mode.app_rd_data_reg[496]_0 ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    \po_rdval_cnt_reg[0] ,
    \po_rdval_cnt_reg[1] ,
    \po_rdval_cnt_reg[2] ,
    \po_rdval_cnt_reg[3] ,
    \po_rdval_cnt_reg[4] ,
    \po_rdval_cnt_reg[5] ,
    \po_rdval_cnt_reg[6] ,
    \po_rdval_cnt_reg[7] ,
    \po_rdval_cnt_reg[8] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    p_0_out,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    A_pi_counter_load_en161_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable157_out,
    A_pi_fine_inc159_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_pi_rst_dqs_find155_out,
    sync_pulse,
    CLK,
    \pi_stg2_reg_l_reg[5] ,
    A_po_coarse_enable143_out,
    A_po_fine_enable141_out,
    A_po_fine_inc145_out,
    D0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    A_rst_primitives_reg,
    p_99_out,
    A_idelay_ce19_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_103_out,
    p_107_out,
    p_111_out,
    p_115_out,
    p_119_out,
    p_123_out,
    p_127_out,
    ofifo_rst0,
    B_po_coarse_enable27_out,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    B_po_fine_enable24_out,
    B_po_fine_inc30_out,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    C_po_coarse_enable66_out,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    C_po_fine_enable63_out,
    C_po_fine_inc69_out,
    \cmd_pipe_plus.mc_ras_n_reg[2] ,
    init_calib_complete_reg_rep__3,
    init_calib_complete_reg_rep__2,
    init_calib_complete_reg_rep__2_0,
    init_calib_complete_reg_rep__2_1,
    init_calib_complete_reg_rep__2_2,
    init_calib_complete_reg_rep__2_3,
    init_calib_complete_reg_rep__2_4,
    D8,
    init_calib_complete_reg_rep__2_5,
    phy_ctl_wr_i2,
    pll_lock,
    read_calib,
    rstdiv0_sync_r1,
    write_calib,
    Q,
    \data_offset_1_i2_reg[5] ,
    sys_rst_0,
    phy_if_reset,
    rstdiv0_sync_r1_reg_rep__0,
    A_pi_counter_load_en116_out,
    \calib_sel_reg[0]_0 ,
    A_pi_fine_enable112_out,
    A_pi_fine_inc114_out,
    mc_read_idle_r_reg_0,
    A_pi_rst_dqs_find110_out,
    COUNTERLOADVAL,
    A_po_coarse_enable98_out,
    A_po_fine_enable96_out,
    A_po_fine_inc100_out,
    \write_buffer.wr_buf_out_data_reg[479] ,
    \write_buffer.wr_buf_out_data_reg[478] ,
    \write_buffer.wr_buf_out_data_reg[477] ,
    \write_buffer.wr_buf_out_data_reg[412] ,
    \write_buffer.wr_buf_out_data_reg[475] ,
    \write_buffer.wr_buf_out_data_reg[474] ,
    \write_buffer.wr_buf_out_data_reg[473] ,
    \write_buffer.wr_buf_out_data_reg[408] ,
    A_rst_primitives_reg_0,
    p_131_out,
    A_idelay_ce13_out,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    p_135_out,
    p_139_out,
    p_143_out,
    p_147_out,
    p_151_out,
    p_155_out,
    p_159_out,
    B_pi_counter_load_en38_out,
    \calib_sel_reg[0]_1 ,
    B_pi_fine_enable34_out,
    B_pi_fine_inc36_out,
    p_29_out,
    B_pi_rst_dqs_find32_out,
    \calib_zero_inputs_reg[0] ,
    B_po_coarse_enable20_out,
    B_po_fine_enable18_out,
    B_po_fine_inc22_out,
    \write_buffer.wr_buf_out_data_reg[471] ,
    \write_buffer.wr_buf_out_data_reg[470] ,
    \write_buffer.wr_buf_out_data_reg[469] ,
    \write_buffer.wr_buf_out_data_reg[404] ,
    \write_buffer.wr_buf_out_data_reg[467] ,
    \write_buffer.wr_buf_out_data_reg[466] ,
    \write_buffer.wr_buf_out_data_reg[465] ,
    \write_buffer.wr_buf_out_data_reg[400] ,
    A_rst_primitives_reg_1,
    p_163_out,
    B_idelay_ce9_out,
    \gen_byte_sel_div2.calib_in_common_reg_3 ,
    p_167_out,
    p_171_out,
    p_175_out,
    p_179_out,
    p_183_out,
    p_187_out,
    p_191_out,
    C_pi_counter_load_en64_out,
    \calib_sel_reg[1] ,
    C_pi_fine_enable60_out,
    C_pi_fine_inc62_out,
    p_34_out,
    C_pi_rst_dqs_find58_out,
    \calib_zero_inputs_reg[0]_0 ,
    C_po_coarse_enable46_out,
    C_po_fine_enable44_out,
    C_po_fine_inc48_out,
    \write_buffer.wr_buf_out_data_reg[463] ,
    \write_buffer.wr_buf_out_data_reg[462] ,
    \write_buffer.wr_buf_out_data_reg[461] ,
    \write_buffer.wr_buf_out_data_reg[396] ,
    \write_buffer.wr_buf_out_data_reg[459] ,
    \write_buffer.wr_buf_out_data_reg[458] ,
    \write_buffer.wr_buf_out_data_reg[457] ,
    \write_buffer.wr_buf_out_data_reg[392] ,
    A_rst_primitives_reg_2,
    p_195_out,
    C_idelay_ce5_out,
    \gen_byte_sel_div2.calib_in_common_reg_4 ,
    p_199_out,
    p_203_out,
    p_207_out,
    p_211_out,
    p_215_out,
    p_219_out,
    p_223_out,
    D_pi_counter_load_en90_out,
    \calib_sel_reg[0]_2 ,
    D_pi_fine_enable86_out,
    D_pi_fine_inc88_out,
    mc_read_idle_r_reg_1,
    D_pi_rst_dqs_find84_out,
    \calib_zero_inputs_reg[0]_1 ,
    D_po_coarse_enable72_out,
    D_po_fine_enable70_out,
    D_po_fine_inc74_out,
    \write_buffer.wr_buf_out_data_reg[455] ,
    \write_buffer.wr_buf_out_data_reg[454] ,
    \write_buffer.wr_buf_out_data_reg[453] ,
    \write_buffer.wr_buf_out_data_reg[388] ,
    \write_buffer.wr_buf_out_data_reg[451] ,
    \write_buffer.wr_buf_out_data_reg[450] ,
    \write_buffer.wr_buf_out_data_reg[449] ,
    \write_buffer.wr_buf_out_data_reg[384] ,
    A_rst_primitives_reg_3,
    p_227_out,
    D_idelay_ce1_out,
    \gen_byte_sel_div2.calib_in_common_reg_5 ,
    p_231_out,
    p_235_out,
    p_239_out,
    p_243_out,
    p_247_out,
    p_251_out,
    p_255_out,
    A_pi_counter_load_en87_out,
    \calib_sel_reg[0]_3 ,
    A_pi_fine_enable83_out,
    A_pi_fine_inc85_out,
    mc_read_idle_r_reg_2,
    A_pi_rst_dqs_find81_out,
    \calib_zero_inputs_reg[2] ,
    A_po_coarse_enable69_out,
    A_po_fine_enable67_out,
    A_po_fine_inc71_out,
    \write_buffer.wr_buf_out_data_reg[511] ,
    \write_buffer.wr_buf_out_data_reg[510] ,
    \write_buffer.wr_buf_out_data_reg[509] ,
    init_calib_complete_reg_rep__10,
    \write_buffer.wr_buf_out_data_reg[507] ,
    \write_buffer.wr_buf_out_data_reg[506] ,
    \write_buffer.wr_buf_out_data_reg[505] ,
    init_calib_complete_reg_rep__10_0,
    init_calib_complete_reg_rep__9,
    A_rst_primitives_reg_4,
    mc_read_idle_r_reg_3,
    A_idelay_ce10_out,
    \gen_byte_sel_div2.calib_in_common_reg_6 ,
    mc_read_idle_r_reg_4,
    mc_read_idle_r_reg_5,
    mc_read_idle_r_reg_6,
    mc_read_idle_r_reg_7,
    mc_read_idle_r_reg_8,
    mc_read_idle_r_reg_9,
    p_31_out,
    B_pi_counter_load_en35_out,
    \calib_sel_reg[0]_4 ,
    B_pi_fine_enable31_out,
    B_pi_fine_inc33_out,
    mc_read_idle_r_reg_10,
    B_pi_rst_dqs_find29_out,
    \calib_zero_inputs_reg[2]_0 ,
    B_po_coarse_enable17_out,
    B_po_fine_enable15_out,
    B_po_fine_inc19_out,
    \write_buffer.wr_buf_out_data_reg[503] ,
    \write_buffer.wr_buf_out_data_reg[502] ,
    \write_buffer.wr_buf_out_data_reg[501] ,
    init_calib_complete_reg_rep__12,
    init_calib_complete_reg_rep__11,
    \write_buffer.wr_buf_out_data_reg[499] ,
    \write_buffer.wr_buf_out_data_reg[498] ,
    \write_buffer.wr_buf_out_data_reg[497] ,
    init_calib_complete_reg_rep__11_0,
    A_rst_primitives_reg_5,
    p_35_out,
    B_idelay_ce6_out,
    \gen_byte_sel_div2.calib_in_common_reg_7 ,
    p_39_out,
    p_43_out,
    p_47_out,
    p_51_out,
    p_55_out,
    p_59_out,
    p_63_out,
    C_pi_counter_load_en61_out,
    \calib_sel_reg[1]_0 ,
    C_pi_fine_enable57_out,
    C_pi_fine_inc59_out,
    mc_read_idle_r_reg_11,
    C_pi_rst_dqs_find55_out,
    \calib_zero_inputs_reg[2]_1 ,
    C_po_coarse_enable43_out,
    C_po_fine_enable41_out,
    C_po_fine_inc45_out,
    \write_buffer.wr_buf_out_data_reg[495] ,
    \write_buffer.wr_buf_out_data_reg[494] ,
    \write_buffer.wr_buf_out_data_reg[493] ,
    init_calib_complete_reg_rep__13,
    \write_buffer.wr_buf_out_data_reg[491] ,
    \write_buffer.wr_buf_out_data_reg[490] ,
    \write_buffer.wr_buf_out_data_reg[489] ,
    init_calib_complete_reg_rep__12_0,
    init_calib_complete_reg_rep__12_1,
    A_rst_primitives_reg_6,
    p_67_out,
    C_idelay_ce2_out,
    \gen_byte_sel_div2.calib_in_common_reg_8 ,
    p_71_out,
    p_75_out,
    p_79_out,
    p_83_out,
    p_87_out,
    p_91_out,
    p_95_out,
    \data_offset_2_i2_reg[5] ,
    rstdiv0_sync_r1_reg_rep__1,
    rstdiv0_sync_r1_reg_rep__18,
    D_po_coarse_enable105_out,
    \gen_byte_sel_div2.calib_in_common_reg_9 ,
    D_po_fine_enable102_out,
    D_po_fine_inc108_out,
    init_calib_complete_reg_rep,
    init_calib_complete_reg_rep_0,
    init_calib_complete_reg_rep_1,
    init_calib_complete_reg_rep_2,
    phy_data_wr_en,
    phy_cmd_wr_en,
    ram_init_done_r,
    init_calib_complete_reg_rep_3,
    calib_cmd_wren,
    \read_fifo.fifo_out_data_r_reg[6] ,
    init_complete_r1_timing_reg,
    tail_r,
    rstdiv0_sync_r1_reg_rep__21,
    mem_out,
    init_calib_complete_reg_rep__1,
    init_calib_complete_reg_rep__2_6,
    sys_rst,
    iodelay_ctrl_rdy,
    sys_rst_1,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    init_calib_complete_reg_rep__14,
    \rd_mux_sel_r_reg[2] ,
    \calib_sel_reg[4] ,
    DOC,
    DOB,
    DOA,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,
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    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ,
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    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ,
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    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ,
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    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    ram_init_addr,
    calib_wrdata_en,
    init_calib_complete_reg_rep__0,
    mc_wrdata_en,
    \rd_ptr_reg_rep[3] ,
    \rd_ptr_reg_rep[3]_0 ,
    \rd_ptr_reg_rep[3]_1 ,
    init_calib_complete_reg_rep__3_0,
    \write_buffer.wr_buf_out_data_reg[571] ,
    init_calib_complete_reg_rep__4,
    init_calib_complete_reg_rep__5,
    init_calib_complete_reg_rep__6,
    init_calib_complete_reg_rep__7,
    init_calib_complete_reg_rep__8,
    init_calib_complete_reg_rep__9_0,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    \cmd_pipe_plus.mc_wrdata_en_reg_0 ,
    \rd_ptr_reg_rep[3]_2 ,
    init_calib_complete_reg_rep__11_1,
    \rd_ptr_reg_rep[3]_3 ,
    init_calib_complete_reg_rep__12_2,
    \rd_ptr_reg_rep[3]_4 ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    mc_cas_n,
    D,
    mux_wrdata,
    \write_buffer.wr_buf_out_data_reg[351] ,
    mux_wrdata_mask,
    phy_dout,
    \po_stg2_wrcal_cnt_reg[2] );
  output [1:0]out;
  output [7:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output [5:0]COUNTERREADVAL;
  output ofifo_rst_reg;
  output \pi_dqs_found_lanes_r1_reg[4] ;
  output \pi_dqs_found_lanes_r1_reg[4]_0 ;
  output p_98_in;
  output p_97_in;
  output p_102_in;
  output p_101_in;
  output p_106_in;
  output p_105_in;
  output p_110_in;
  output p_109_in;
  output p_114_in;
  output p_113_in;
  output p_118_in;
  output p_117_in;
  output p_122_in;
  output p_121_in;
  output p_126_in;
  output p_125_in;
  output \ddr3_dm[4] ;
  output p_9_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \pi_dqs_found_lanes_r1_reg[0] ;
  output \pi_dqs_found_lanes_r1_reg[0]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output p_134_in;
  output p_133_in;
  output p_138_in;
  output p_137_in;
  output p_142_in;
  output p_141_in;
  output p_146_in;
  output p_145_in;
  output p_150_in;
  output p_149_in;
  output p_154_in;
  output p_153_in;
  output p_158_in;
  output p_157_in;
  output p_13_in;
  output \ddr3_dm[3] ;
  output idelay_ld_rst;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output p_28_in;
  output p_27_in;
  output p_162_in;
  output p_161_in;
  output p_166_in;
  output p_165_in;
  output p_170_in;
  output p_169_in;
  output p_174_in;
  output p_173_in;
  output \ddr3_dm[2] ;
  output p_15_in;
  output p_178_in;
  output p_177_in;
  output p_182_in;
  output p_181_in;
  output p_186_in;
  output p_185_in;
  output p_190_in;
  output p_189_in;
  output idelay_ld_rst_0;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output \pi_dqs_found_lanes_r1_reg[2] ;
  output p_32_in;
  output p_194_in;
  output p_193_in;
  output p_198_in;
  output p_197_in;
  output p_202_in;
  output p_201_in;
  output p_206_in;
  output p_205_in;
  output p_210_in;
  output p_209_in;
  output p_214_in;
  output p_213_in;
  output p_218_in;
  output p_217_in;
  output p_222_in;
  output p_221_in;
  output p_19_in;
  output \ddr3_dm[1] ;
  output idelay_ld_rst_1;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output \pi_dqs_found_lanes_r1_reg[3] ;
  output \pi_dqs_found_lanes_r1_reg[3]_0 ;
  output p_226_in;
  output p_225_in;
  output p_230_in;
  output p_229_in;
  output p_234_in;
  output p_233_in;
  output p_238_in;
  output p_237_in;
  output p_242_in;
  output p_241_in;
  output p_246_in;
  output p_245_in;
  output p_250_in;
  output p_249_in;
  output p_254_in;
  output p_253_in;
  output \ddr3_dm[0] ;
  output p_21_in;
  output idelay_ld_rst_2;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output \pi_dqs_found_lanes_r1_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  output p_5_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ;
  output p_17_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_16 ;
  output p_25_in;
  output p_30_in;
  output p_29_in;
  output p_1_in;
  output \ddr3_dm[7] ;
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_17 ;
  output \my_empty_reg[7] ;
  output \pi_dqs_found_lanes_r1_reg[9] ;
  output \pi_dqs_found_lanes_r1_reg[9]_0 ;
  output p_34_in;
  output p_33_in;
  output p_38_in;
  output p_37_in;
  output p_42_in;
  output p_41_in;
  output p_46_in;
  output p_45_in;
  output \ddr3_dm[6] ;
  output p_3_in;
  output p_50_in;
  output p_49_in;
  output p_54_in;
  output p_53_in;
  output p_58_in;
  output p_57_in;
  output p_62_in;
  output p_61_in;
  output [1:0]\rd_ptr_timing_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_18 ;
  output \my_empty_reg[7]_0 ;
  output \pi_dqs_found_lanes_r1_reg[10] ;
  output \pi_dqs_found_lanes_r1_reg[10]_0 ;
  output p_66_in;
  output p_65_in;
  output p_70_in;
  output p_69_in;
  output p_74_in;
  output p_73_in;
  output p_78_in;
  output p_77_in;
  output p_82_in;
  output p_81_in;
  output p_86_in;
  output p_85_in;
  output p_90_in;
  output p_89_in;
  output p_94_in;
  output p_93_in;
  output p_7_in;
  output \ddr3_dm[5] ;
  output idelay_ld_rst_3;
  output \my_empty_reg[7]_1 ;
  output idelay_ld_rst_4;
  output \my_empty_reg[7]_2 ;
  output idelay_ld_rst_5;
  output phy_ctl_ready;
  output [1:0]ddr_ck_out;
  output phy_mc_ctl_full;
  output phy_rddata_en;
  output rd_active_r_reg;
  output \read_fifo.tail_r_reg[1] ;
  output rd_buf_we;
  output \my_empty_reg[1] ;
  output \read_fifo.tail_r_reg[3] ;
  output [2:0]ADDRA;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  output \my_empty_reg[1]_0 ;
  output phy_mc_data_full;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  output \my_empty_reg[1]_3 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \my_empty_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  output \my_empty_reg[1]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  output \my_empty_reg[1]_6 ;
  output rst_sync_r1_reg;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  output [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \my_empty_reg[1]_7 ;
  output \my_empty_reg[1]_8 ;
  output \my_empty_reg[1]_9 ;
  output pi_phase_locked_all_r1_reg;
  output \read_fifo.tail_r_reg[0] ;
  output \read_fifo.tail_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]DIA;
  output [1:0]DIB;
  output [1:0]DIC;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ;
  output store_sr_req_r_reg;
  output \pi_rdval_cnt_reg[4] ;
  output \pi_rdval_cnt_reg[1] ;
  output \pi_rdval_cnt_reg[2] ;
  output \pi_rdval_cnt_reg[3] ;
  output \pi_rdval_cnt_reg[0] ;
  output \pi_rdval_cnt_reg[5] ;
  output \FSM_onehot_cal1_state_r_reg[0] ;
  output \FSM_onehot_cal1_state_r_reg[0]_0 ;
  output \FSM_onehot_cal1_state_r_reg[0]_1 ;
  output [511:0]\not_strict_mode.app_rd_data_reg[511] ;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output wr_en;
  output wr_en_10;
  output wr_en_11;
  output [0:0]of_ctl_full_v;
  output wr_en_12;
  output wr_en_13;
  output wr_en_14;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7]_3 ;
  output idelay_ld_rst_6;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\wr_ptr_timing_reg[0] ;
  output [4:0]mem_dq_out;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  output [11:0]\ddr3_addr[3] ;
  output [43:0]\my_empty_reg[7]_4 ;
  output [43:0]\my_empty_reg[7]_5 ;
  output [43:0]\my_empty_reg[7]_6 ;
  output [43:0]\my_empty_reg[7]_7 ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1]_1 ;
  output [3:0]\wr_ptr_timing_reg[3]_2 ;
  output [3:0]\my_empty_reg[7]_8 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_2 ;
  output [3:0]\wr_ptr_timing_reg[3]_3 ;
  output [3:0]\my_empty_reg[7]_9 ;
  output \wr_ptr_reg[0]_1 ;
  output \wr_ptr_reg[1]_3 ;
  output [3:0]\wr_ptr_timing_reg[3]_4 ;
  output [3:0]\my_empty_reg[7]_10 ;
  output [5:0]\ddr3_addr[13] ;
  output [15:0]\my_empty_reg[6] ;
  output p_0_in1_in;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \not_strict_mode.app_rd_data_reg[496]_0 ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output \po_rdval_cnt_reg[0] ;
  output \po_rdval_cnt_reg[1] ;
  output \po_rdval_cnt_reg[2] ;
  output \po_rdval_cnt_reg[3] ;
  output \po_rdval_cnt_reg[4] ;
  output \po_rdval_cnt_reg[5] ;
  output \po_rdval_cnt_reg[6] ;
  output \po_rdval_cnt_reg[7] ;
  output \po_rdval_cnt_reg[8] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output p_0_out;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input A_pi_counter_load_en161_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable157_out;
  input A_pi_fine_inc159_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_pi_rst_dqs_find155_out;
  input sync_pulse;
  input CLK;
  input [5:0]\pi_stg2_reg_l_reg[5] ;
  input A_po_coarse_enable143_out;
  input A_po_fine_enable141_out;
  input A_po_fine_inc145_out;
  input [7:0]D0;
  input [7:0]D1;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D9;
  input A_rst_primitives_reg;
  input p_99_out;
  input A_idelay_ce19_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_103_out;
  input p_107_out;
  input p_111_out;
  input p_115_out;
  input p_119_out;
  input p_123_out;
  input p_127_out;
  input ofifo_rst0;
  input B_po_coarse_enable27_out;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input B_po_fine_enable24_out;
  input B_po_fine_inc30_out;
  input [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  input [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  input [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  input [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  input C_po_coarse_enable66_out;
  input \gen_byte_sel_div2.calib_in_common_reg_1 ;
  input C_po_fine_enable63_out;
  input C_po_fine_inc69_out;
  input [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  input [3:0]init_calib_complete_reg_rep__3;
  input [3:0]init_calib_complete_reg_rep__2;
  input [3:0]init_calib_complete_reg_rep__2_0;
  input [3:0]init_calib_complete_reg_rep__2_1;
  input [7:0]init_calib_complete_reg_rep__2_2;
  input [7:0]init_calib_complete_reg_rep__2_3;
  input [3:0]init_calib_complete_reg_rep__2_4;
  input [3:0]D8;
  input [3:0]init_calib_complete_reg_rep__2_5;
  input phy_ctl_wr_i2;
  input pll_lock;
  input read_calib;
  input rstdiv0_sync_r1;
  input write_calib;
  input [10:0]Q;
  input [5:0]\data_offset_1_i2_reg[5] ;
  input sys_rst_0;
  input phy_if_reset;
  input rstdiv0_sync_r1_reg_rep__0;
  input A_pi_counter_load_en116_out;
  input \calib_sel_reg[0]_0 ;
  input A_pi_fine_enable112_out;
  input A_pi_fine_inc114_out;
  input mc_read_idle_r_reg_0;
  input A_pi_rst_dqs_find110_out;
  input [5:0]COUNTERLOADVAL;
  input A_po_coarse_enable98_out;
  input A_po_fine_enable96_out;
  input A_po_fine_inc100_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  input A_rst_primitives_reg_0;
  input p_131_out;
  input A_idelay_ce13_out;
  input \gen_byte_sel_div2.calib_in_common_reg_2 ;
  input p_135_out;
  input p_139_out;
  input p_143_out;
  input p_147_out;
  input p_151_out;
  input p_155_out;
  input p_159_out;
  input B_pi_counter_load_en38_out;
  input \calib_sel_reg[0]_1 ;
  input B_pi_fine_enable34_out;
  input B_pi_fine_inc36_out;
  input p_29_out;
  input B_pi_rst_dqs_find32_out;
  input [5:0]\calib_zero_inputs_reg[0] ;
  input B_po_coarse_enable20_out;
  input B_po_fine_enable18_out;
  input B_po_fine_inc22_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  input A_rst_primitives_reg_1;
  input p_163_out;
  input B_idelay_ce9_out;
  input \gen_byte_sel_div2.calib_in_common_reg_3 ;
  input p_167_out;
  input p_171_out;
  input p_175_out;
  input p_179_out;
  input p_183_out;
  input p_187_out;
  input p_191_out;
  input C_pi_counter_load_en64_out;
  input \calib_sel_reg[1] ;
  input C_pi_fine_enable60_out;
  input C_pi_fine_inc62_out;
  input p_34_out;
  input C_pi_rst_dqs_find58_out;
  input [5:0]\calib_zero_inputs_reg[0]_0 ;
  input C_po_coarse_enable46_out;
  input C_po_fine_enable44_out;
  input C_po_fine_inc48_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  input A_rst_primitives_reg_2;
  input p_195_out;
  input C_idelay_ce5_out;
  input \gen_byte_sel_div2.calib_in_common_reg_4 ;
  input p_199_out;
  input p_203_out;
  input p_207_out;
  input p_211_out;
  input p_215_out;
  input p_219_out;
  input p_223_out;
  input D_pi_counter_load_en90_out;
  input \calib_sel_reg[0]_2 ;
  input D_pi_fine_enable86_out;
  input D_pi_fine_inc88_out;
  input mc_read_idle_r_reg_1;
  input D_pi_rst_dqs_find84_out;
  input [5:0]\calib_zero_inputs_reg[0]_1 ;
  input D_po_coarse_enable72_out;
  input D_po_fine_enable70_out;
  input D_po_fine_inc74_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  input A_rst_primitives_reg_3;
  input p_227_out;
  input D_idelay_ce1_out;
  input \gen_byte_sel_div2.calib_in_common_reg_5 ;
  input p_231_out;
  input p_235_out;
  input p_239_out;
  input p_243_out;
  input p_247_out;
  input p_251_out;
  input p_255_out;
  input A_pi_counter_load_en87_out;
  input \calib_sel_reg[0]_3 ;
  input A_pi_fine_enable83_out;
  input A_pi_fine_inc85_out;
  input mc_read_idle_r_reg_2;
  input A_pi_rst_dqs_find81_out;
  input [5:0]\calib_zero_inputs_reg[2] ;
  input A_po_coarse_enable69_out;
  input A_po_fine_enable67_out;
  input A_po_fine_inc71_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  input [7:0]init_calib_complete_reg_rep__10;
  input [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  input [7:0]init_calib_complete_reg_rep__10_0;
  input [7:0]init_calib_complete_reg_rep__9;
  input A_rst_primitives_reg_4;
  input mc_read_idle_r_reg_3;
  input A_idelay_ce10_out;
  input \gen_byte_sel_div2.calib_in_common_reg_6 ;
  input mc_read_idle_r_reg_4;
  input mc_read_idle_r_reg_5;
  input mc_read_idle_r_reg_6;
  input mc_read_idle_r_reg_7;
  input mc_read_idle_r_reg_8;
  input mc_read_idle_r_reg_9;
  input p_31_out;
  input B_pi_counter_load_en35_out;
  input \calib_sel_reg[0]_4 ;
  input B_pi_fine_enable31_out;
  input B_pi_fine_inc33_out;
  input mc_read_idle_r_reg_10;
  input B_pi_rst_dqs_find29_out;
  input [5:0]\calib_zero_inputs_reg[2]_0 ;
  input B_po_coarse_enable17_out;
  input B_po_fine_enable15_out;
  input B_po_fine_inc19_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  input [7:0]init_calib_complete_reg_rep__12;
  input [7:0]init_calib_complete_reg_rep__11;
  input [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  input [7:0]init_calib_complete_reg_rep__11_0;
  input A_rst_primitives_reg_5;
  input p_35_out;
  input B_idelay_ce6_out;
  input \gen_byte_sel_div2.calib_in_common_reg_7 ;
  input p_39_out;
  input p_43_out;
  input p_47_out;
  input p_51_out;
  input p_55_out;
  input p_59_out;
  input p_63_out;
  input C_pi_counter_load_en61_out;
  input \calib_sel_reg[1]_0 ;
  input C_pi_fine_enable57_out;
  input C_pi_fine_inc59_out;
  input mc_read_idle_r_reg_11;
  input C_pi_rst_dqs_find55_out;
  input [5:0]\calib_zero_inputs_reg[2]_1 ;
  input C_po_coarse_enable43_out;
  input C_po_fine_enable41_out;
  input C_po_fine_inc45_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  input [7:0]init_calib_complete_reg_rep__13;
  input [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  input [7:0]init_calib_complete_reg_rep__12_0;
  input [7:0]init_calib_complete_reg_rep__12_1;
  input A_rst_primitives_reg_6;
  input p_67_out;
  input C_idelay_ce2_out;
  input \gen_byte_sel_div2.calib_in_common_reg_8 ;
  input p_71_out;
  input p_75_out;
  input p_79_out;
  input p_83_out;
  input p_87_out;
  input p_91_out;
  input p_95_out;
  input [5:0]\data_offset_2_i2_reg[5] ;
  input rstdiv0_sync_r1_reg_rep__1;
  input rstdiv0_sync_r1_reg_rep__18;
  input D_po_coarse_enable105_out;
  input \gen_byte_sel_div2.calib_in_common_reg_9 ;
  input D_po_fine_enable102_out;
  input D_po_fine_inc108_out;
  input [3:0]init_calib_complete_reg_rep;
  input [3:0]init_calib_complete_reg_rep_0;
  input [3:0]init_calib_complete_reg_rep_1;
  input [3:0]init_calib_complete_reg_rep_2;
  input phy_data_wr_en;
  input phy_cmd_wr_en;
  input ram_init_done_r;
  input init_calib_complete_reg_rep_3;
  input calib_cmd_wren;
  input [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  input init_complete_r1_timing_reg;
  input [3:0]tail_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input [63:0]mem_out;
  input init_calib_complete_reg_rep__1;
  input init_calib_complete_reg_rep__2_6;
  input sys_rst;
  input [0:0]iodelay_ctrl_rdy;
  input sys_rst_1;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input init_calib_complete_reg_rep__14;
  input [2:0]\rd_mux_sel_r_reg[2] ;
  input [3:0]\calib_sel_reg[4] ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]DOA;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  input \read_fifo.fifo_out_data_r_reg[5] ;
  input [0:0]ram_init_addr;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__0;
  input mc_wrdata_en;
  input [7:0]\rd_ptr_reg_rep[3] ;
  input [24:0]\rd_ptr_reg_rep[3]_0 ;
  input [32:0]\rd_ptr_reg_rep[3]_1 ;
  input init_calib_complete_reg_rep__3_0;
  input [111:0]\write_buffer.wr_buf_out_data_reg[571] ;
  input init_calib_complete_reg_rep__4;
  input init_calib_complete_reg_rep__5;
  input init_calib_complete_reg_rep__6;
  input init_calib_complete_reg_rep__7;
  input init_calib_complete_reg_rep__8;
  input init_calib_complete_reg_rep__9_0;
  input \cmd_pipe_plus.mc_wrdata_en_reg ;
  input \cmd_pipe_plus.mc_wrdata_en_reg_0 ;
  input [7:0]\rd_ptr_reg_rep[3]_2 ;
  input init_calib_complete_reg_rep__11_1;
  input [7:0]\rd_ptr_reg_rep[3]_3 ;
  input init_calib_complete_reg_rep__12_2;
  input [7:0]\rd_ptr_reg_rep[3]_4 ;
  input [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [0:0]mc_cas_n;
  input [5:0]D;
  input [207:0]mux_wrdata;
  input [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  input [31:0]mux_wrdata_mask;
  input [21:0]phy_dout;
  input [2:0]\po_stg2_wrcal_cnt_reg[2] ;

  wire [2:0]ADDRA;
  wire A_idelay_ce10_out;
  wire A_idelay_ce13_out;
  wire A_idelay_ce19_out;
  wire A_pi_counter_load_en116_out;
  wire A_pi_counter_load_en161_out;
  wire A_pi_counter_load_en87_out;
  wire A_pi_fine_enable112_out;
  wire A_pi_fine_enable157_out;
  wire A_pi_fine_enable83_out;
  wire A_pi_fine_inc114_out;
  wire A_pi_fine_inc159_out;
  wire A_pi_fine_inc85_out;
  wire A_pi_rst_dqs_find110_out;
  wire A_pi_rst_dqs_find155_out;
  wire A_pi_rst_dqs_find81_out;
  wire A_po_coarse_enable143_out;
  wire A_po_coarse_enable69_out;
  wire A_po_coarse_enable98_out;
  wire A_po_fine_enable141_out;
  wire A_po_fine_enable67_out;
  wire A_po_fine_enable96_out;
  wire A_po_fine_inc100_out;
  wire A_po_fine_inc145_out;
  wire A_po_fine_inc71_out;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire B_idelay_ce6_out;
  wire B_idelay_ce9_out;
  wire B_pi_counter_load_en35_out;
  wire B_pi_counter_load_en38_out;
  wire B_pi_fine_enable31_out;
  wire B_pi_fine_enable34_out;
  wire B_pi_fine_inc33_out;
  wire B_pi_fine_inc36_out;
  wire B_pi_rst_dqs_find29_out;
  wire B_pi_rst_dqs_find32_out;
  wire B_po_coarse_enable17_out;
  wire B_po_coarse_enable20_out;
  wire B_po_coarse_enable27_out;
  wire B_po_fine_enable15_out;
  wire B_po_fine_enable18_out;
  wire B_po_fine_enable24_out;
  wire B_po_fine_inc19_out;
  wire B_po_fine_inc22_out;
  wire B_po_fine_inc30_out;
  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire [5:0]COUNTERREADVAL;
  wire C_idelay_ce2_out;
  wire C_idelay_ce5_out;
  wire C_pi_counter_load_en61_out;
  wire C_pi_counter_load_en64_out;
  wire C_pi_fine_enable57_out;
  wire C_pi_fine_enable60_out;
  wire C_pi_fine_inc59_out;
  wire C_pi_fine_inc62_out;
  wire C_pi_rst_dqs_find55_out;
  wire C_pi_rst_dqs_find58_out;
  wire C_po_coarse_enable43_out;
  wire C_po_coarse_enable46_out;
  wire C_po_coarse_enable66_out;
  wire C_po_fine_enable41_out;
  wire C_po_fine_enable44_out;
  wire C_po_fine_enable63_out;
  wire C_po_fine_inc45_out;
  wire C_po_fine_inc48_out;
  wire C_po_fine_inc69_out;
  wire [5:0]D;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [3:0]D8;
  wire [7:0]D9;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire D_idelay_ce1_out;
  wire D_pi_counter_load_en90_out;
  wire D_pi_fine_enable86_out;
  wire D_pi_fine_inc88_out;
  wire D_pi_rst_dqs_find84_out;
  wire D_po_coarse_enable105_out;
  wire D_po_coarse_enable72_out;
  wire D_po_fine_enable102_out;
  wire D_po_fine_enable70_out;
  wire D_po_fine_inc108_out;
  wire D_po_fine_inc74_out;
  wire \FSM_onehot_cal1_state_r_reg[0] ;
  wire \FSM_onehot_cal1_state_r_reg[0]_0 ;
  wire \FSM_onehot_cal1_state_r_reg[0]_1 ;
  wire [10:0]Q;
  wire [2:0]_phy_ctl_full_p__0;
  wire calib_cmd_wren;
  wire \calib_sel_reg[0] ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[0]_1 ;
  wire \calib_sel_reg[0]_2 ;
  wire \calib_sel_reg[0]_3 ;
  wire \calib_sel_reg[0]_4 ;
  wire \calib_sel_reg[1] ;
  wire \calib_sel_reg[1]_0 ;
  wire [3:0]\calib_sel_reg[4] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[0] ;
  wire [5:0]\calib_zero_inputs_reg[0]_0 ;
  wire [5:0]\calib_zero_inputs_reg[0]_1 ;
  wire [5:0]\calib_zero_inputs_reg[2] ;
  wire [5:0]\calib_zero_inputs_reg[2]_0 ;
  wire [5:0]\calib_zero_inputs_reg[2]_1 ;
  wire [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  wire [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg_0 ;
  wire [5:0]\data_offset_1_i2_reg[5] ;
  wire [5:0]\data_offset_2_i2_reg[5] ;
  wire [5:0]\ddr3_addr[13] ;
  wire [11:0]\ddr3_addr[3] ;
  wire \ddr3_dm[0] ;
  wire \ddr3_dm[1] ;
  wire \ddr3_dm[2] ;
  wire \ddr3_dm[3] ;
  wire \ddr3_dm[4] ;
  wire \ddr3_dm[5] ;
  wire \ddr3_dm[6] ;
  wire \ddr3_dm[7] ;
  wire [3:0]\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [0:0]\ddr_byte_lane_A.ddr_byte_lane_A/if_empty_r ;
  wire [4:4]\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ;
  wire [4:2]\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 ;
  wire [0:0]\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:3]\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ;
  wire [3:3]\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r ;
  wire [3:3]\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r_2 ;
  wire [4:4]\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ;
  wire [0:0]\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:3]\ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r ;
  wire [4:4]\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ;
  wire [1:0]ddr_ck_out;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_102 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_104 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_148 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_587 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_98 ;
  wire \ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_118 ;
  wire \ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_200 ;
  wire \ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_4 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_30 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_318 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_323 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_333 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_338 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_343 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_353 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_354 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_355 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_357 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_358 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_359 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_361 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_362 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_367 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_372 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_377 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_382 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_387 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_392 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_397 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_398 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_399 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_400 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_401 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_402 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_403 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_404 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_405 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_408 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_413 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_418 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_423 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_428 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_433 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_438 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_443 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_444 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_445 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_446 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_447 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_448 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_449 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_450 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_451 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_452 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_457 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_462 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_467 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_472 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_477 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_482 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_487 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_488 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_489 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_490 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_491 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_492 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_493 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_494 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_495 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_56 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_6 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_694 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_696 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_697 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_698 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_699 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_700 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_701 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_702 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_703 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_704 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_705 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_706 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_707 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_708 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_709 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_710 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_711 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_712 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_713 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_714 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_715 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_716 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_717 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_718 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_719 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_720 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_721 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_722 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_723 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_724 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_725 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_726 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_727 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_728 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_729 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_730 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_731 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_732 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_733 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_734 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_735 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_736 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_737 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_738 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_739 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_740 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_741 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_742 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_743 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_744 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_745 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_746 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_747 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_748 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_749 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_750 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_751 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_752 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_753 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_754 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_755 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_756 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_757 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_758 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_759 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_760 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_88 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_16 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_17 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_18 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_3 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_4 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_5 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_6 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_7 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_8 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_9 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_6;
  wire [3:0]init_calib_complete_reg_rep;
  wire [3:0]init_calib_complete_reg_rep_0;
  wire [3:0]init_calib_complete_reg_rep_1;
  wire [3:0]init_calib_complete_reg_rep_2;
  wire init_calib_complete_reg_rep_3;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__1;
  wire [7:0]init_calib_complete_reg_rep__10;
  wire [7:0]init_calib_complete_reg_rep__10_0;
  wire [7:0]init_calib_complete_reg_rep__11;
  wire [7:0]init_calib_complete_reg_rep__11_0;
  wire init_calib_complete_reg_rep__11_1;
  wire [7:0]init_calib_complete_reg_rep__12;
  wire [7:0]init_calib_complete_reg_rep__12_0;
  wire [7:0]init_calib_complete_reg_rep__12_1;
  wire init_calib_complete_reg_rep__12_2;
  wire [7:0]init_calib_complete_reg_rep__13;
  wire init_calib_complete_reg_rep__14;
  wire [3:0]init_calib_complete_reg_rep__2;
  wire [3:0]init_calib_complete_reg_rep__2_0;
  wire [3:0]init_calib_complete_reg_rep__2_1;
  wire [7:0]init_calib_complete_reg_rep__2_2;
  wire [7:0]init_calib_complete_reg_rep__2_3;
  wire [3:0]init_calib_complete_reg_rep__2_4;
  wire [3:0]init_calib_complete_reg_rep__2_5;
  wire init_calib_complete_reg_rep__2_6;
  wire [3:0]init_calib_complete_reg_rep__3;
  wire init_calib_complete_reg_rep__3_0;
  wire init_calib_complete_reg_rep__4;
  wire init_calib_complete_reg_rep__5;
  wire init_calib_complete_reg_rep__6;
  wire init_calib_complete_reg_rep__7;
  wire init_calib_complete_reg_rep__8;
  wire [7:0]init_calib_complete_reg_rep__9;
  wire init_calib_complete_reg_rep__9_0;
  wire init_complete_r1_timing_reg;
  wire [0:0]iodelay_ctrl_rdy;
  wire mcGo_r1;
  wire \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ;
  wire \mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ;
  wire mcGo_r_reg_gate_n_0;
  wire mcGo_r_reg_r_0_n_0;
  wire mcGo_r_reg_r_10_n_0;
  wire mcGo_r_reg_r_11_n_0;
  wire mcGo_r_reg_r_12_n_0;
  wire mcGo_r_reg_r_13_n_0;
  wire mcGo_r_reg_r_1_n_0;
  wire mcGo_r_reg_r_2_n_0;
  wire mcGo_r_reg_r_3_n_0;
  wire mcGo_r_reg_r_4_n_0;
  wire mcGo_r_reg_r_5_n_0;
  wire mcGo_r_reg_r_6_n_0;
  wire mcGo_r_reg_r_7_n_0;
  wire mcGo_r_reg_r_8_n_0;
  wire mcGo_r_reg_r_9_n_0;
  wire mcGo_r_reg_r_n_0;
  wire [2:0]mcGo_w__0;
  wire [0:0]mc_cas_n;
  wire mc_read_idle_r_reg;
  wire mc_read_idle_r_reg_0;
  wire mc_read_idle_r_reg_1;
  wire mc_read_idle_r_reg_10;
  wire mc_read_idle_r_reg_11;
  wire mc_read_idle_r_reg_2;
  wire mc_read_idle_r_reg_3;
  wire mc_read_idle_r_reg_4;
  wire mc_read_idle_r_reg_5;
  wire mc_read_idle_r_reg_6;
  wire mc_read_idle_r_reg_7;
  wire mc_read_idle_r_reg_8;
  wire mc_read_idle_r_reg_9;
  wire mc_wrdata_en;
  wire [4:0]mem_dq_out;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire [207:0]mux_wrdata;
  wire [31:0]mux_wrdata_mask;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[1]_3 ;
  wire \my_empty_reg[1]_4 ;
  wire \my_empty_reg[1]_5 ;
  wire \my_empty_reg[1]_6 ;
  wire \my_empty_reg[1]_7 ;
  wire \my_empty_reg[1]_8 ;
  wire \my_empty_reg[1]_9 ;
  wire [15:0]\my_empty_reg[6] ;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_10 ;
  wire \my_empty_reg[7]_2 ;
  wire [3:0]\my_empty_reg[7]_3 ;
  wire [43:0]\my_empty_reg[7]_4 ;
  wire [43:0]\my_empty_reg[7]_5 ;
  wire [43:0]\my_empty_reg[7]_6 ;
  wire [43:0]\my_empty_reg[7]_7 ;
  wire [3:0]\my_empty_reg[7]_8 ;
  wire [3:0]\my_empty_reg[7]_9 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  wire [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  wire \not_strict_mode.app_rd_data_reg[496]_0 ;
  wire [511:0]\not_strict_mode.app_rd_data_reg[511] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  wire [0:0]of_ctl_full_v;
  wire ofifo_rst0;
  wire ofifo_rst_reg;
  wire [1:0]out;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_0_out;
  wire p_101_in;
  wire p_102_in;
  wire p_103_out;
  wire p_105_in;
  wire p_106_in;
  wire p_107_out;
  wire p_109_in;
  wire p_110_in;
  wire p_111_out;
  wire p_113_in;
  wire p_114_in;
  wire p_115_out;
  wire p_117_in;
  wire p_118_in;
  wire p_119_out;
  wire p_121_in;
  wire p_122_in;
  wire p_123_out;
  wire p_125_in;
  wire p_126_in;
  wire p_127_out;
  wire p_131_out;
  wire p_133_in;
  wire p_134_in;
  wire p_135_out;
  wire p_137_in;
  wire p_138_in;
  wire p_139_out;
  wire p_13_in;
  wire p_141_in;
  wire p_142_in;
  wire p_143_out;
  wire p_145_in;
  wire p_146_in;
  wire p_147_out;
  wire p_149_in;
  wire p_150_in;
  wire p_151_out;
  wire p_153_in;
  wire p_154_in;
  wire p_155_out;
  wire p_157_in;
  wire p_158_in;
  wire p_159_out;
  wire p_15_in;
  wire p_161_in;
  wire p_162_in;
  wire p_163_out;
  wire p_165_in;
  wire p_166_in;
  wire p_167_out;
  wire p_169_in;
  wire p_170_in;
  wire p_171_out;
  wire p_173_in;
  wire p_174_in;
  wire p_175_out;
  wire p_177_in;
  wire p_178_in;
  wire p_179_out;
  wire p_17_in;
  wire p_181_in;
  wire p_182_in;
  wire p_183_out;
  wire p_185_in;
  wire p_186_in;
  wire p_187_out;
  wire p_189_in;
  wire p_190_in;
  wire p_191_out;
  wire p_193_in;
  wire p_194_in;
  wire p_195_out;
  wire p_197_in;
  wire p_198_in;
  wire p_199_out;
  wire p_19_in;
  wire p_1_in;
  wire p_201_in;
  wire p_202_in;
  wire p_203_out;
  wire p_205_in;
  wire p_206_in;
  wire p_207_out;
  wire p_209_in;
  wire p_210_in;
  wire p_211_out;
  wire p_213_in;
  wire p_214_in;
  wire p_215_out;
  wire p_217_in;
  wire p_218_in;
  wire p_219_out;
  wire p_21_in;
  wire p_221_in;
  wire p_222_in;
  wire p_223_out;
  wire p_225_in;
  wire p_226_in;
  wire p_227_out;
  wire p_229_in;
  wire p_230_in;
  wire p_231_out;
  wire p_233_in;
  wire p_234_in;
  wire p_235_out;
  wire p_237_in;
  wire p_238_in;
  wire p_239_out;
  wire p_241_in;
  wire p_242_in;
  wire p_243_out;
  wire p_245_in;
  wire p_246_in;
  wire p_247_out;
  wire p_249_in;
  wire p_250_in;
  wire p_251_out;
  wire p_253_in;
  wire p_254_in;
  wire p_255_out;
  wire p_25_in;
  wire p_27_in;
  wire p_28_in;
  wire p_29_in;
  wire p_29_out;
  wire p_30_in;
  wire p_31_out;
  wire p_32_in;
  wire p_33_in;
  wire p_34_in;
  wire p_34_out;
  wire p_35_out;
  wire p_37_in;
  wire p_38_in;
  wire p_39_out;
  wire p_3_in;
  wire p_41_in;
  wire p_42_in;
  wire p_43_out;
  wire p_45_in;
  wire p_46_in;
  wire p_47_out;
  wire p_49_in;
  wire p_50_in;
  wire p_51_out;
  wire p_53_in;
  wire p_54_in;
  wire p_55_out;
  wire p_57_in;
  wire p_58_in;
  wire p_59_out;
  wire p_5_in;
  wire p_61_in;
  wire p_62_in;
  wire p_63_out;
  wire p_65_in;
  wire p_66_in;
  wire p_67_out;
  wire p_69_in;
  wire p_70_in;
  wire p_71_out;
  wire p_73_in;
  wire p_74_in;
  wire p_75_out;
  wire p_77_in;
  wire p_78_in;
  wire p_79_out;
  wire p_7_in;
  wire p_81_in;
  wire p_82_in;
  wire p_83_out;
  wire p_85_in;
  wire p_86_in;
  wire p_87_out;
  wire p_89_in;
  wire p_90_in;
  wire p_91_out;
  wire p_93_in;
  wire p_94_in;
  wire p_95_out;
  wire p_97_in;
  wire p_98_in;
  wire p_99_out;
  wire p_9_in;
  wire phy_cmd_wr_en;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_ready;
  wire phy_ctl_wr_i2;
  wire phy_data_wr_en;
  wire [21:0]phy_dout;
  wire phy_if_reset;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire [5:0]\pi_counter_read_val_w[0]_4 ;
  wire [5:0]\pi_counter_read_val_w[2]_6 ;
  wire [7:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[4] ;
  wire \pi_dqs_found_lanes_r1_reg[4]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire \pi_rdval_cnt_reg[0] ;
  wire \pi_rdval_cnt_reg[1] ;
  wire \pi_rdval_cnt_reg[2] ;
  wire \pi_rdval_cnt_reg[3] ;
  wire \pi_rdval_cnt_reg[4] ;
  wire \pi_rdval_cnt_reg[5] ;
  wire [5:0]\pi_stg2_reg_l_reg[5] ;
  wire pll_lock;
  wire [8:0]\po_counter_read_val_w[0]_3 ;
  wire [8:0]\po_counter_read_val_w[2]_5 ;
  wire \po_rdval_cnt_reg[0] ;
  wire \po_rdval_cnt_reg[1] ;
  wire \po_rdval_cnt_reg[2] ;
  wire \po_rdval_cnt_reg[3] ;
  wire \po_rdval_cnt_reg[4] ;
  wire \po_rdval_cnt_reg[5] ;
  wire \po_rdval_cnt_reg[6] ;
  wire \po_rdval_cnt_reg[7] ;
  wire \po_rdval_cnt_reg[8] ;
  wire [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire [0:0]ram_init_addr;
  wire ram_init_done_r;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_i_1_n_0 ;
  wire rd_active_r_reg;
  wire rd_buf_we;
  wire [2:0]\rd_mux_sel_r_reg[2] ;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire [24:0]\rd_ptr_reg_rep[3]_0 ;
  wire [32:0]\rd_ptr_reg_rep[3]_1 ;
  wire [7:0]\rd_ptr_reg_rep[3]_2 ;
  wire [7:0]\rd_ptr_reg_rep[3]_3 ;
  wire [7:0]\rd_ptr_reg_rep[3]_4 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rd_ptr_timing_reg[1]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1]_1 ;
  wire read_calib;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  wire \read_fifo.fifo_ram[0].RAM32M0_i_22_n_0 ;
  wire \read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire \read_fifo.tail_r_reg[3] ;
  wire [1:1]ref_dll_lock_w;
  wire [2:2]ref_dll_lock_w__0;
  wire rst_out_i_1_n_0;
  wire rst_primitives;
  wire rst_sync_r1_reg;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire store_sr_req_r_reg;
  wire sync_pulse;
  wire sys_rst;
  wire sys_rst_0;
  wire sys_rst_1;
  wire [3:0]tail_r;
  wire wr_en;
  wire wr_en_10;
  wire wr_en_11;
  wire wr_en_12;
  wire wr_en_13;
  wire wr_en_14;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[0]_1 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;
  wire \wr_ptr_reg[1]_3 ;
  wire [3:0]\wr_ptr_timing_reg[0] ;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3]_3 ;
  wire [3:0]\wr_ptr_timing_reg[3]_4 ;
  wire [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  wire [111:0]\write_buffer.wr_buf_out_data_reg[571] ;
  wire write_calib;

  mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes \ddr_phy_4lanes_0.u_ddr_phy_4lanes 
       (.ADDRA(ADDRA[2:1]),
        .A_idelay_ce13_out(A_idelay_ce13_out),
        .A_pi_counter_load_en116_out(A_pi_counter_load_en116_out),
        .A_pi_fine_enable112_out(A_pi_fine_enable112_out),
        .A_pi_fine_inc114_out(A_pi_fine_inc114_out),
        .A_pi_rst_dqs_find110_out(A_pi_rst_dqs_find110_out),
        .A_po_coarse_enable98_out(A_po_coarse_enable98_out),
        .A_po_fine_enable96_out(A_po_fine_enable96_out),
        .A_po_fine_inc100_out(A_po_fine_inc100_out),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(\ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_4 ),
        .A_rst_primitives_reg_5(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_30 ),
        .A_rst_primitives_reg_6(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_6 ),
        .A_rst_primitives_reg_7(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_56 ),
        .B_idelay_ce9_out(B_idelay_ce9_out),
        .B_pi_counter_load_en38_out(B_pi_counter_load_en38_out),
        .B_pi_fine_enable34_out(B_pi_fine_enable34_out),
        .B_pi_fine_inc36_out(B_pi_fine_inc36_out),
        .B_pi_rst_dqs_find32_out(B_pi_rst_dqs_find32_out),
        .B_po_coarse_enable20_out(B_po_coarse_enable20_out),
        .B_po_fine_enable18_out(B_po_fine_enable18_out),
        .B_po_fine_inc22_out(B_po_fine_inc22_out),
        .CLK(CLK),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .C_idelay_ce5_out(C_idelay_ce5_out),
        .C_pi_counter_load_en64_out(C_pi_counter_load_en64_out),
        .C_pi_fine_enable60_out(C_pi_fine_enable60_out),
        .C_pi_fine_inc62_out(C_pi_fine_inc62_out),
        .C_pi_rst_dqs_find58_out(C_pi_rst_dqs_find58_out),
        .C_po_coarse_enable46_out(C_po_coarse_enable46_out),
        .C_po_fine_enable44_out(C_po_fine_enable44_out),
        .C_po_fine_inc48_out(C_po_fine_inc48_out),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .D_idelay_ce1_out(D_idelay_ce1_out),
        .D_pi_counter_load_en90_out(D_pi_counter_load_en90_out),
        .D_pi_fine_enable86_out(D_pi_fine_enable86_out),
        .D_pi_fine_inc88_out(D_pi_fine_inc88_out),
        .D_pi_rst_dqs_find84_out(D_pi_rst_dqs_find84_out),
        .D_po_coarse_enable72_out(D_po_coarse_enable72_out),
        .D_po_fine_enable70_out(D_po_fine_enable70_out),
        .D_po_fine_inc74_out(D_po_fine_inc74_out),
        .Q(Q),
        ._phy_ctl_full_p__0(_phy_ctl_full_p__0[0]),
        .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ),
        .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_1 ),
        .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_2 ),
        .\calib_sel_reg[1] (\calib_sel_reg[1] ),
        .\calib_sel_reg[1]_0 (\calib_sel_reg[4] [1:0]),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ),
        .\calib_zero_inputs_reg[0]_0 (\calib_zero_inputs_reg[0]_0 ),
        .\calib_zero_inputs_reg[0]_1 (\calib_zero_inputs_reg[0]_1 ),
        .\ddr3_dm[0] (\ddr3_dm[0] ),
        .\ddr3_dm[1] (\ddr3_dm[1] ),
        .\ddr3_dm[2] (\ddr3_dm[2] ),
        .\ddr3_dm[3] (\ddr3_dm[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_200 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_88 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 (rd_active_r_reg),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\entry_cnt_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_694 ),
        .\entry_cnt_reg[3] (\ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_118 ),
        .\entry_cnt_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_696 ),
        .\entry_cnt_reg[4] (\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ),
        .\entry_cnt_reg[4]_0 (\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [4]),
        .\entry_cnt_reg[4]_1 (\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .\entry_cnt_reg[4]_2 (\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (\gen_byte_sel_div2.calib_in_common_reg_3 ),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (\gen_byte_sel_div2.calib_in_common_reg_4 ),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (\gen_byte_sel_div2.calib_in_common_reg_5 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (\gen_rd[2].rd_data_rise_wl_r_reg[2] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (\gen_rd[3].rd_data_rise_wl_r_reg[3] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .if_empty_r(\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r ),
        .if_empty_r_0(\ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r ),
        .if_empty_r_1(\ddr_byte_lane_A.ddr_byte_lane_A/if_empty_r ),
        .if_empty_r_2(\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r_2 ),
        .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3_0),
        .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4),
        .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),
        .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),
        .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),
        .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .mcGo_reg_0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_98 ),
        .mcGo_w__0(mcGo_w__0[0]),
        .mc_read_idle_r_reg(mc_read_idle_r_reg_0),
        .mc_read_idle_r_reg_0(mc_read_idle_r_reg_1),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .mux_wrdata(mux_wrdata),
        .mux_wrdata_mask(mux_wrdata_mask),
        .my_empty(\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [3]),
        .\my_empty_reg[0] (\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[0]_0 (\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[0]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810 ),
        .\my_empty_reg[1] (\my_empty_reg[1]_3 ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_4 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_5 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_6 ),
        .\my_empty_reg[3] (\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),
        .\my_empty_reg[4]_rep__1 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_104 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_7 ),
        .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ),
        .\not_strict_mode.app_rd_data_reg[479] ({\not_strict_mode.app_rd_data_reg[511] [479:448],\not_strict_mode.app_rd_data_reg[511] [415:384],\not_strict_mode.app_rd_data_reg[511] [351:320],\not_strict_mode.app_rd_data_reg[511] [287:256],\not_strict_mode.app_rd_data_reg[511] [223:192],\not_strict_mode.app_rd_data_reg[511] [159:128],\not_strict_mode.app_rd_data_reg[511] [95:64],\not_strict_mode.app_rd_data_reg[511] [31:0]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ),
        .ofs_rdy_r_reg(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_148 ),
        .p_0_in(p_0_in),
        .p_0_out(p_0_out),
        .p_131_out(p_131_out),
        .p_133_in(p_133_in),
        .p_134_in(p_134_in),
        .p_135_out(p_135_out),
        .p_137_in(p_137_in),
        .p_138_in(p_138_in),
        .p_139_out(p_139_out),
        .p_13_in(p_13_in),
        .p_141_in(p_141_in),
        .p_142_in(p_142_in),
        .p_143_out(p_143_out),
        .p_145_in(p_145_in),
        .p_146_in(p_146_in),
        .p_147_out(p_147_out),
        .p_149_in(p_149_in),
        .p_150_in(p_150_in),
        .p_151_out(p_151_out),
        .p_153_in(p_153_in),
        .p_154_in(p_154_in),
        .p_155_out(p_155_out),
        .p_157_in(p_157_in),
        .p_158_in(p_158_in),
        .p_159_out(p_159_out),
        .p_15_in(p_15_in),
        .p_161_in(p_161_in),
        .p_162_in(p_162_in),
        .p_163_out(p_163_out),
        .p_165_in(p_165_in),
        .p_166_in(p_166_in),
        .p_167_out(p_167_out),
        .p_169_in(p_169_in),
        .p_170_in(p_170_in),
        .p_171_out(p_171_out),
        .p_173_in(p_173_in),
        .p_174_in(p_174_in),
        .p_175_out(p_175_out),
        .p_177_in(p_177_in),
        .p_178_in(p_178_in),
        .p_179_out(p_179_out),
        .p_181_in(p_181_in),
        .p_182_in(p_182_in),
        .p_183_out(p_183_out),
        .p_185_in(p_185_in),
        .p_186_in(p_186_in),
        .p_187_out(p_187_out),
        .p_189_in(p_189_in),
        .p_190_in(p_190_in),
        .p_191_out(p_191_out),
        .p_193_in(p_193_in),
        .p_194_in(p_194_in),
        .p_195_out(p_195_out),
        .p_197_in(p_197_in),
        .p_198_in(p_198_in),
        .p_199_out(p_199_out),
        .p_19_in(p_19_in),
        .p_201_in(p_201_in),
        .p_202_in(p_202_in),
        .p_203_out(p_203_out),
        .p_205_in(p_205_in),
        .p_206_in(p_206_in),
        .p_207_out(p_207_out),
        .p_209_in(p_209_in),
        .p_210_in(p_210_in),
        .p_211_out(p_211_out),
        .p_213_in(p_213_in),
        .p_214_in(p_214_in),
        .p_215_out(p_215_out),
        .p_217_in(p_217_in),
        .p_218_in(p_218_in),
        .p_219_out(p_219_out),
        .p_21_in(p_21_in),
        .p_221_in(p_221_in),
        .p_222_in(p_222_in),
        .p_223_out(p_223_out),
        .p_225_in(p_225_in),
        .p_226_in(p_226_in),
        .p_227_out(p_227_out),
        .p_229_in(p_229_in),
        .p_230_in(p_230_in),
        .p_231_out(p_231_out),
        .p_233_in(p_233_in),
        .p_234_in(p_234_in),
        .p_235_out(p_235_out),
        .p_237_in(p_237_in),
        .p_238_in(p_238_in),
        .p_239_out(p_239_out),
        .p_241_in(p_241_in),
        .p_242_in(p_242_in),
        .p_243_out(p_243_out),
        .p_245_in(p_245_in),
        .p_246_in(p_246_in),
        .p_247_out(p_247_out),
        .p_249_in(p_249_in),
        .p_250_in(p_250_in),
        .p_251_out(p_251_out),
        .p_253_in(p_253_in),
        .p_254_in(p_254_in),
        .p_255_out(p_255_out),
        .p_27_in(p_27_in),
        .p_28_in(p_28_in),
        .p_29_out(p_29_out),
        .p_32_in(p_32_in),
        .p_34_out(p_34_out),
        .phy_ctl_mstr_empty(phy_ctl_mstr_empty),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .phy_mc_data_full(phy_mc_data_full),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[3:0]),
        .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0] ),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),
        .\pi_rdval_cnt_reg[5] (\pi_counter_read_val_w[0]_4 ),
        .pll_lock(pll_lock),
        .\po_rdval_cnt_reg[8] (\po_counter_read_val_w[0]_3 ),
        .\po_stg2_wrcal_cnt_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_697 ),
        .\po_stg2_wrcal_cnt_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_698 ),
        .\po_stg2_wrcal_cnt_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_699 ),
        .\po_stg2_wrcal_cnt_reg[1]_10 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_708 ),
        .\po_stg2_wrcal_cnt_reg[1]_11 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_709 ),
        .\po_stg2_wrcal_cnt_reg[1]_12 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_710 ),
        .\po_stg2_wrcal_cnt_reg[1]_13 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_711 ),
        .\po_stg2_wrcal_cnt_reg[1]_14 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_712 ),
        .\po_stg2_wrcal_cnt_reg[1]_15 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_713 ),
        .\po_stg2_wrcal_cnt_reg[1]_16 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_714 ),
        .\po_stg2_wrcal_cnt_reg[1]_17 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_715 ),
        .\po_stg2_wrcal_cnt_reg[1]_18 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_716 ),
        .\po_stg2_wrcal_cnt_reg[1]_19 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_717 ),
        .\po_stg2_wrcal_cnt_reg[1]_2 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_700 ),
        .\po_stg2_wrcal_cnt_reg[1]_20 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_718 ),
        .\po_stg2_wrcal_cnt_reg[1]_21 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_719 ),
        .\po_stg2_wrcal_cnt_reg[1]_22 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_720 ),
        .\po_stg2_wrcal_cnt_reg[1]_23 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_721 ),
        .\po_stg2_wrcal_cnt_reg[1]_24 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_722 ),
        .\po_stg2_wrcal_cnt_reg[1]_25 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_723 ),
        .\po_stg2_wrcal_cnt_reg[1]_26 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_724 ),
        .\po_stg2_wrcal_cnt_reg[1]_27 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_725 ),
        .\po_stg2_wrcal_cnt_reg[1]_28 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_726 ),
        .\po_stg2_wrcal_cnt_reg[1]_29 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_727 ),
        .\po_stg2_wrcal_cnt_reg[1]_3 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_701 ),
        .\po_stg2_wrcal_cnt_reg[1]_30 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_728 ),
        .\po_stg2_wrcal_cnt_reg[1]_31 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_729 ),
        .\po_stg2_wrcal_cnt_reg[1]_32 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_730 ),
        .\po_stg2_wrcal_cnt_reg[1]_33 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_731 ),
        .\po_stg2_wrcal_cnt_reg[1]_34 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_732 ),
        .\po_stg2_wrcal_cnt_reg[1]_35 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_733 ),
        .\po_stg2_wrcal_cnt_reg[1]_36 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_734 ),
        .\po_stg2_wrcal_cnt_reg[1]_37 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_735 ),
        .\po_stg2_wrcal_cnt_reg[1]_38 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_736 ),
        .\po_stg2_wrcal_cnt_reg[1]_39 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_737 ),
        .\po_stg2_wrcal_cnt_reg[1]_4 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_702 ),
        .\po_stg2_wrcal_cnt_reg[1]_40 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_738 ),
        .\po_stg2_wrcal_cnt_reg[1]_41 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_739 ),
        .\po_stg2_wrcal_cnt_reg[1]_42 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_740 ),
        .\po_stg2_wrcal_cnt_reg[1]_43 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_741 ),
        .\po_stg2_wrcal_cnt_reg[1]_44 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_742 ),
        .\po_stg2_wrcal_cnt_reg[1]_45 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_743 ),
        .\po_stg2_wrcal_cnt_reg[1]_46 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_744 ),
        .\po_stg2_wrcal_cnt_reg[1]_47 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_745 ),
        .\po_stg2_wrcal_cnt_reg[1]_48 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_746 ),
        .\po_stg2_wrcal_cnt_reg[1]_49 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_747 ),
        .\po_stg2_wrcal_cnt_reg[1]_5 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_703 ),
        .\po_stg2_wrcal_cnt_reg[1]_50 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_748 ),
        .\po_stg2_wrcal_cnt_reg[1]_51 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_749 ),
        .\po_stg2_wrcal_cnt_reg[1]_52 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_750 ),
        .\po_stg2_wrcal_cnt_reg[1]_53 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_751 ),
        .\po_stg2_wrcal_cnt_reg[1]_54 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_752 ),
        .\po_stg2_wrcal_cnt_reg[1]_55 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_753 ),
        .\po_stg2_wrcal_cnt_reg[1]_56 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_754 ),
        .\po_stg2_wrcal_cnt_reg[1]_57 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_755 ),
        .\po_stg2_wrcal_cnt_reg[1]_58 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_756 ),
        .\po_stg2_wrcal_cnt_reg[1]_59 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_757 ),
        .\po_stg2_wrcal_cnt_reg[1]_6 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_704 ),
        .\po_stg2_wrcal_cnt_reg[1]_60 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_758 ),
        .\po_stg2_wrcal_cnt_reg[1]_61 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_759 ),
        .\po_stg2_wrcal_cnt_reg[1]_62 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_760 ),
        .\po_stg2_wrcal_cnt_reg[1]_7 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_705 ),
        .\po_stg2_wrcal_cnt_reg[1]_8 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_706 ),
        .\po_stg2_wrcal_cnt_reg[1]_9 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_707 ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .ram_init_addr(ram_init_addr),
        .ram_init_done_r(ram_init_done_r),
        .rclk_delay_11(rclk_delay_11),
        .\rclk_delay_reg[11]_0 (rst_out_i_1_n_0),
        .rd_buf_we(rd_buf_we),
        .\rd_mux_sel_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_318 ),
        .\rd_mux_sel_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_323 ),
        .\rd_mux_sel_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328 ),
        .\rd_mux_sel_r_reg[1]_10 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_357 ),
        .\rd_mux_sel_r_reg[1]_11 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_358 ),
        .\rd_mux_sel_r_reg[1]_12 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_359 ),
        .\rd_mux_sel_r_reg[1]_13 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360 ),
        .\rd_mux_sel_r_reg[1]_14 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_361 ),
        .\rd_mux_sel_r_reg[1]_15 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_362 ),
        .\rd_mux_sel_r_reg[1]_16 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_367 ),
        .\rd_mux_sel_r_reg[1]_17 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_372 ),
        .\rd_mux_sel_r_reg[1]_18 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_377 ),
        .\rd_mux_sel_r_reg[1]_19 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_382 ),
        .\rd_mux_sel_r_reg[1]_2 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_333 ),
        .\rd_mux_sel_r_reg[1]_20 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_387 ),
        .\rd_mux_sel_r_reg[1]_21 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_392 ),
        .\rd_mux_sel_r_reg[1]_22 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_397 ),
        .\rd_mux_sel_r_reg[1]_23 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_398 ),
        .\rd_mux_sel_r_reg[1]_24 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_399 ),
        .\rd_mux_sel_r_reg[1]_25 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_400 ),
        .\rd_mux_sel_r_reg[1]_26 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_401 ),
        .\rd_mux_sel_r_reg[1]_27 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_402 ),
        .\rd_mux_sel_r_reg[1]_28 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_403 ),
        .\rd_mux_sel_r_reg[1]_29 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_404 ),
        .\rd_mux_sel_r_reg[1]_3 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_338 ),
        .\rd_mux_sel_r_reg[1]_30 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_405 ),
        .\rd_mux_sel_r_reg[1]_31 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_408 ),
        .\rd_mux_sel_r_reg[1]_32 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_413 ),
        .\rd_mux_sel_r_reg[1]_33 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_418 ),
        .\rd_mux_sel_r_reg[1]_34 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_423 ),
        .\rd_mux_sel_r_reg[1]_35 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_428 ),
        .\rd_mux_sel_r_reg[1]_36 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_433 ),
        .\rd_mux_sel_r_reg[1]_37 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_438 ),
        .\rd_mux_sel_r_reg[1]_38 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_443 ),
        .\rd_mux_sel_r_reg[1]_39 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_444 ),
        .\rd_mux_sel_r_reg[1]_4 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_343 ),
        .\rd_mux_sel_r_reg[1]_40 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_445 ),
        .\rd_mux_sel_r_reg[1]_41 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_446 ),
        .\rd_mux_sel_r_reg[1]_42 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_447 ),
        .\rd_mux_sel_r_reg[1]_43 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_448 ),
        .\rd_mux_sel_r_reg[1]_44 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_449 ),
        .\rd_mux_sel_r_reg[1]_45 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_450 ),
        .\rd_mux_sel_r_reg[1]_46 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_451 ),
        .\rd_mux_sel_r_reg[1]_47 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_452 ),
        .\rd_mux_sel_r_reg[1]_48 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_457 ),
        .\rd_mux_sel_r_reg[1]_49 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_462 ),
        .\rd_mux_sel_r_reg[1]_5 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348 ),
        .\rd_mux_sel_r_reg[1]_50 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_467 ),
        .\rd_mux_sel_r_reg[1]_51 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_472 ),
        .\rd_mux_sel_r_reg[1]_52 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_477 ),
        .\rd_mux_sel_r_reg[1]_53 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_482 ),
        .\rd_mux_sel_r_reg[1]_54 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_487 ),
        .\rd_mux_sel_r_reg[1]_55 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_488 ),
        .\rd_mux_sel_r_reg[1]_56 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_489 ),
        .\rd_mux_sel_r_reg[1]_57 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_490 ),
        .\rd_mux_sel_r_reg[1]_58 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_491 ),
        .\rd_mux_sel_r_reg[1]_59 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_492 ),
        .\rd_mux_sel_r_reg[1]_6 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_353 ),
        .\rd_mux_sel_r_reg[1]_60 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_493 ),
        .\rd_mux_sel_r_reg[1]_61 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_494 ),
        .\rd_mux_sel_r_reg[1]_62 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_495 ),
        .\rd_mux_sel_r_reg[1]_7 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_354 ),
        .\rd_mux_sel_r_reg[1]_8 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_355 ),
        .\rd_mux_sel_r_reg[1]_9 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .read_calib(read_calib),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ),
        .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1]_0 ),
        .\read_fifo.tail_r_reg[3] (\read_fifo.tail_r_reg[3] ),
        .ref_dll_lock_w(ref_dll_lock_w),
        .rst_primitives(rst_primitives),
        .rst_primitives_reg_0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ),
        .rst_primitives_reg_1(\rclk_delay_reg[10]_srl11_i_1_n_0 ),
        .rst_sync_r1_reg(rst_sync_r1_reg),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst),
        .sys_rst_0(ref_dll_lock_w__0),
        .sys_rst_1(sys_rst_0),
        .sys_rst_2(sys_rst_1),
        .tail_r(tail_r),
        .\wr_ptr_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_102 ),
        .\wr_ptr_reg[1]_0 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_587 ),
        .\write_buffer.wr_buf_out_data_reg[351] (\write_buffer.wr_buf_out_data_reg[351] ),
        .\write_buffer.wr_buf_out_data_reg[384] (\write_buffer.wr_buf_out_data_reg[384] ),
        .\write_buffer.wr_buf_out_data_reg[388] (\write_buffer.wr_buf_out_data_reg[388] ),
        .\write_buffer.wr_buf_out_data_reg[392] (\write_buffer.wr_buf_out_data_reg[392] ),
        .\write_buffer.wr_buf_out_data_reg[396] (\write_buffer.wr_buf_out_data_reg[396] ),
        .\write_buffer.wr_buf_out_data_reg[400] (\write_buffer.wr_buf_out_data_reg[400] ),
        .\write_buffer.wr_buf_out_data_reg[404] (\write_buffer.wr_buf_out_data_reg[404] ),
        .\write_buffer.wr_buf_out_data_reg[408] (\write_buffer.wr_buf_out_data_reg[408] ),
        .\write_buffer.wr_buf_out_data_reg[412] (\write_buffer.wr_buf_out_data_reg[412] ),
        .\write_buffer.wr_buf_out_data_reg[449] (\write_buffer.wr_buf_out_data_reg[449] ),
        .\write_buffer.wr_buf_out_data_reg[450] (\write_buffer.wr_buf_out_data_reg[450] ),
        .\write_buffer.wr_buf_out_data_reg[451] (\write_buffer.wr_buf_out_data_reg[451] ),
        .\write_buffer.wr_buf_out_data_reg[453] (\write_buffer.wr_buf_out_data_reg[453] ),
        .\write_buffer.wr_buf_out_data_reg[454] (\write_buffer.wr_buf_out_data_reg[454] ),
        .\write_buffer.wr_buf_out_data_reg[455] (\write_buffer.wr_buf_out_data_reg[455] ),
        .\write_buffer.wr_buf_out_data_reg[457] (\write_buffer.wr_buf_out_data_reg[457] ),
        .\write_buffer.wr_buf_out_data_reg[458] (\write_buffer.wr_buf_out_data_reg[458] ),
        .\write_buffer.wr_buf_out_data_reg[459] (\write_buffer.wr_buf_out_data_reg[459] ),
        .\write_buffer.wr_buf_out_data_reg[461] (\write_buffer.wr_buf_out_data_reg[461] ),
        .\write_buffer.wr_buf_out_data_reg[462] (\write_buffer.wr_buf_out_data_reg[462] ),
        .\write_buffer.wr_buf_out_data_reg[463] (\write_buffer.wr_buf_out_data_reg[463] ),
        .\write_buffer.wr_buf_out_data_reg[465] (\write_buffer.wr_buf_out_data_reg[465] ),
        .\write_buffer.wr_buf_out_data_reg[466] (\write_buffer.wr_buf_out_data_reg[466] ),
        .\write_buffer.wr_buf_out_data_reg[467] (\write_buffer.wr_buf_out_data_reg[467] ),
        .\write_buffer.wr_buf_out_data_reg[469] (\write_buffer.wr_buf_out_data_reg[469] ),
        .\write_buffer.wr_buf_out_data_reg[470] (\write_buffer.wr_buf_out_data_reg[470] ),
        .\write_buffer.wr_buf_out_data_reg[471] (\write_buffer.wr_buf_out_data_reg[471] ),
        .\write_buffer.wr_buf_out_data_reg[473] (\write_buffer.wr_buf_out_data_reg[473] ),
        .\write_buffer.wr_buf_out_data_reg[474] (\write_buffer.wr_buf_out_data_reg[474] ),
        .\write_buffer.wr_buf_out_data_reg[475] (\write_buffer.wr_buf_out_data_reg[475] ),
        .\write_buffer.wr_buf_out_data_reg[477] (\write_buffer.wr_buf_out_data_reg[477] ),
        .\write_buffer.wr_buf_out_data_reg[478] (\write_buffer.wr_buf_out_data_reg[478] ),
        .\write_buffer.wr_buf_out_data_reg[479] (\write_buffer.wr_buf_out_data_reg[479] ),
        .\write_buffer.wr_buf_out_data_reg[571] (\write_buffer.wr_buf_out_data_reg[571] ),
        .write_calib(write_calib));
  mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized0 \ddr_phy_4lanes_1.u_ddr_phy_4lanes 
       (.A_idelay_ce19_out(A_idelay_ce19_out),
        .A_pi_counter_load_en161_out(A_pi_counter_load_en161_out),
        .A_pi_fine_enable157_out(A_pi_fine_enable157_out),
        .A_pi_fine_inc159_out(A_pi_fine_inc159_out),
        .A_pi_rst_dqs_find155_out(A_pi_rst_dqs_find155_out),
        .A_po_coarse_enable143_out(A_po_coarse_enable143_out),
        .A_po_fine_enable141_out(A_po_fine_enable141_out),
        .A_po_fine_inc145_out(A_po_fine_inc145_out),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .B_po_coarse_enable27_out(B_po_coarse_enable27_out),
        .B_po_fine_enable24_out(B_po_fine_enable24_out),
        .B_po_fine_inc30_out(B_po_fine_inc30_out),
        .CLK(CLK),
        .COUNTERREADVAL(COUNTERREADVAL),
        .C_po_coarse_enable66_out(C_po_coarse_enable66_out),
        .C_po_fine_enable63_out(C_po_fine_enable63_out),
        .C_po_fine_inc69_out(C_po_fine_inc69_out),
        .D(D),
        .D0(D0),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .DIC(DIC),
        .D_po_coarse_enable105_out(D_po_coarse_enable105_out),
        .D_po_fine_enable102_out(D_po_fine_enable102_out),
        .D_po_fine_inc108_out(D_po_fine_inc108_out),
        .\FSM_onehot_cal1_state_r_reg[0] (\FSM_onehot_cal1_state_r_reg[0] ),
        .\FSM_onehot_cal1_state_r_reg[0]_0 (\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .\FSM_onehot_cal1_state_r_reg[0]_1 (\FSM_onehot_cal1_state_r_reg[0]_1 ),
        .PHYCTLWD({Q[10:9],\data_offset_1_i2_reg[5] ,Q[2:0]}),
        .Q(\not_strict_mode.app_rd_data_reg[352] ),
        ._phy_ctl_full_p__0({_phy_ctl_full_p__0[2],_phy_ctl_full_p__0[0]}),
        .calib_cmd_wren(calib_cmd_wren),
        .\calib_sel_reg[0] (\calib_sel_reg[0] ),
        .\calib_sel_reg[4] (\calib_sel_reg[4] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2] ),
        .\cmd_pipe_plus.mc_cke_reg[3] (\cmd_pipe_plus.mc_cke_reg[3] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[2] (\cmd_pipe_plus.mc_ras_n_reg[2] ),
        .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ),
        .\ddr3_addr[13] (\ddr3_addr[13] ),
        .\ddr3_addr[3] (\ddr3_addr[3] ),
        .\ddr3_dm[4] (\ddr3_dm[4] ),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\entry_cnt_reg[3] (\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [3:2]),
        .\entry_cnt_reg[4] (\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .\entry_cnt_reg[4]_0 (\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ),
        .\entry_cnt_reg[4]_1 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_148 ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (\gen_byte_sel_div2.calib_in_common_reg_9 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (\gen_rd[4].rd_data_rise_wl_r_reg[4] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .if_empty_r(\ddr_byte_lane_A.ddr_byte_lane_A/if_empty_r ),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .init_calib_complete_reg_rep_0(init_calib_complete_reg_rep_0),
        .init_calib_complete_reg_rep_1(init_calib_complete_reg_rep_1),
        .init_calib_complete_reg_rep_2(init_calib_complete_reg_rep_2),
        .init_calib_complete_reg_rep_3(init_calib_complete_reg_rep_3),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1),
        .init_calib_complete_reg_rep__14(init_calib_complete_reg_rep__14),
        .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2),
        .init_calib_complete_reg_rep__2_0(init_calib_complete_reg_rep__2_0),
        .init_calib_complete_reg_rep__2_1(init_calib_complete_reg_rep__2_1),
        .init_calib_complete_reg_rep__2_2(init_calib_complete_reg_rep__2_2),
        .init_calib_complete_reg_rep__2_3(init_calib_complete_reg_rep__2_3),
        .init_calib_complete_reg_rep__2_4(init_calib_complete_reg_rep__2_4),
        .init_calib_complete_reg_rep__2_5(init_calib_complete_reg_rep__2_5),
        .init_calib_complete_reg_rep__2_6(init_calib_complete_reg_rep__2_6),
        .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3),
        .mcGo_r1(mcGo_r1),
        .mcGo_w__0({mcGo_w__0[2],mcGo_w__0[0]}),
        .mc_cas_n(mc_cas_n),
        .mc_read_idle_r_reg(mc_read_idle_r_reg),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_dq_out(mem_dq_out),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ),
        .\my_empty_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_587 ),
        .\my_empty_reg[4]_rep__1 ({\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [3],\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [0]}),
        .\my_empty_reg[6] (\my_empty_reg[6] ),
        .\my_empty_reg[7] (\my_empty_reg[7]_3 ),
        .\not_strict_mode.app_rd_data_reg[487] ({\not_strict_mode.app_rd_data_reg[511] [487:480],\not_strict_mode.app_rd_data_reg[511] [423:416],\not_strict_mode.app_rd_data_reg[511] [359:352],\not_strict_mode.app_rd_data_reg[511] [295:288],\not_strict_mode.app_rd_data_reg[511] [231:224],\not_strict_mode.app_rd_data_reg[511] [167:160],\not_strict_mode.app_rd_data_reg[511] [103:96],\not_strict_mode.app_rd_data_reg[511] [39:32]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),
        .of_ctl_full_v(of_ctl_full_v),
        .ofifo_rst0(ofifo_rst0),
        .ofifo_rst_reg(ofifo_rst_reg),
        .ofs_rdy_r_reg(\ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_118 ),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .p_101_in(p_101_in),
        .p_102_in(p_102_in),
        .p_103_out(p_103_out),
        .p_105_in(p_105_in),
        .p_106_in(p_106_in),
        .p_107_out(p_107_out),
        .p_109_in(p_109_in),
        .p_110_in(p_110_in),
        .p_111_out(p_111_out),
        .p_113_in(p_113_in),
        .p_114_in(p_114_in),
        .p_115_out(p_115_out),
        .p_117_in(p_117_in),
        .p_118_in(p_118_in),
        .p_119_out(p_119_out),
        .p_121_in(p_121_in),
        .p_122_in(p_122_in),
        .p_123_out(p_123_out),
        .p_125_in(p_125_in),
        .p_126_in(p_126_in),
        .p_127_out(p_127_out),
        .p_97_in(p_97_in),
        .p_98_in(p_98_in),
        .p_99_out(p_99_out),
        .p_9_in(p_9_in),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_ctl_mstr_empty(phy_ctl_mstr_empty),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .phy_if_reset(phy_if_reset),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .\pi_counter_read_val_reg[5]_0 (\pi_counter_read_val_w[0]_4 ),
        .\pi_counter_read_val_reg[5]_1 (\pi_counter_read_val_w[2]_6 ),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[4]),
        .\pi_dqs_found_lanes_r1_reg[4] (\pi_dqs_found_lanes_r1_reg[4] ),
        .\pi_dqs_found_lanes_r1_reg[4]_0 (\pi_dqs_found_lanes_r1_reg[4]_0 ),
        .pi_phase_locked_all_r1_reg(\ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_4 ),
        .\pi_rdval_cnt_reg[0] (\pi_rdval_cnt_reg[0] ),
        .\pi_rdval_cnt_reg[1] (\pi_rdval_cnt_reg[1] ),
        .\pi_rdval_cnt_reg[2] (\pi_rdval_cnt_reg[2] ),
        .\pi_rdval_cnt_reg[3] (\pi_rdval_cnt_reg[3] ),
        .\pi_rdval_cnt_reg[4] (\pi_rdval_cnt_reg[4] ),
        .\pi_rdval_cnt_reg[5] (\pi_rdval_cnt_reg[5] ),
        .\pi_stg2_reg_l_reg[5] (\pi_stg2_reg_l_reg[5] ),
        .pll_lock(pll_lock),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_w[2]_5 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_w[0]_3 ),
        .\po_rdval_cnt_reg[0] (\po_rdval_cnt_reg[0] ),
        .\po_rdval_cnt_reg[1] (\po_rdval_cnt_reg[1] ),
        .\po_rdval_cnt_reg[2] (\po_rdval_cnt_reg[2] ),
        .\po_rdval_cnt_reg[3] (\po_rdval_cnt_reg[3] ),
        .\po_rdval_cnt_reg[4] (\po_rdval_cnt_reg[4] ),
        .\po_rdval_cnt_reg[5] (\po_rdval_cnt_reg[5] ),
        .\po_rdval_cnt_reg[6] (\po_rdval_cnt_reg[6] ),
        .\po_rdval_cnt_reg[7] (\po_rdval_cnt_reg[7] ),
        .\po_rdval_cnt_reg[8] (\po_rdval_cnt_reg[8] ),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] ),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3]_0 ),
        .\rd_ptr_reg_rep[3]_1 (\rd_ptr_reg_rep[3]_1 ),
        .read_calib(read_calib),
        .\read_fifo.fifo_out_data_r_reg[4] (\not_strict_mode.app_rd_data_reg[24] ),
        .ref_dll_lock_w(ref_dll_lock_w),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .store_sr_req_r_reg(store_sr_req_r_reg),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst_0),
        .wr_en(wr_en),
        .wr_en_10(wr_en_10),
        .wr_en_11(wr_en_11),
        .\wr_ptr_reg[1] (\ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_200 ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3]_0 ),
        .\wr_ptr_timing_reg[3]_1 (\wr_ptr_timing_reg[3]_1 ),
        .write_calib(write_calib));
  mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized1 \ddr_phy_4lanes_2.u_ddr_phy_4lanes 
       (.ADDRA(ADDRA[0]),
        .A_idelay_ce10_out(A_idelay_ce10_out),
        .A_pi_counter_load_en87_out(A_pi_counter_load_en87_out),
        .A_pi_fine_enable83_out(A_pi_fine_enable83_out),
        .A_pi_fine_inc85_out(A_pi_fine_inc85_out),
        .A_pi_rst_dqs_find81_out(A_pi_rst_dqs_find81_out),
        .A_po_coarse_enable69_out(A_po_coarse_enable69_out),
        .A_po_fine_enable67_out(A_po_fine_enable67_out),
        .A_po_fine_inc71_out(A_po_fine_inc71_out),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_6),
        .B_idelay_ce6_out(B_idelay_ce6_out),
        .B_pi_counter_load_en35_out(B_pi_counter_load_en35_out),
        .B_pi_fine_enable31_out(B_pi_fine_enable31_out),
        .B_pi_fine_inc33_out(B_pi_fine_inc33_out),
        .B_pi_rst_dqs_find29_out(B_pi_rst_dqs_find29_out),
        .B_po_coarse_enable17_out(B_po_coarse_enable17_out),
        .B_po_fine_enable15_out(B_po_fine_enable15_out),
        .B_po_fine_inc19_out(B_po_fine_inc19_out),
        .CLK(CLK),
        .C_idelay_ce2_out(C_idelay_ce2_out),
        .C_pi_counter_load_en61_out(C_pi_counter_load_en61_out),
        .C_pi_fine_enable57_out(C_pi_fine_enable57_out),
        .C_pi_fine_inc59_out(C_pi_fine_inc59_out),
        .C_pi_rst_dqs_find55_out(C_pi_rst_dqs_find55_out),
        .C_po_coarse_enable43_out(C_po_coarse_enable43_out),
        .C_po_fine_enable41_out(C_po_fine_enable41_out),
        .C_po_fine_inc45_out(C_po_fine_inc45_out),
        .DIA(DIA),
        .PHYCTLWD({Q[10:9],\data_offset_2_i2_reg[5] ,Q[2:0]}),
        .Q(\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),
        ._phy_ctl_full_p__0(_phy_ctl_full_p__0[2]),
        .\calib_sel_reg[0] (\calib_sel_reg[0]_3 ),
        .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_4 ),
        .\calib_sel_reg[1] (\calib_sel_reg[1]_0 ),
        .\calib_sel_reg[1]_0 (\calib_sel_reg[4] [1:0]),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[2] (\calib_zero_inputs_reg[2] ),
        .\calib_zero_inputs_reg[2]_0 (\calib_zero_inputs_reg[2]_0 ),
        .\calib_zero_inputs_reg[2]_1 (\calib_zero_inputs_reg[2]_1 ),
        .\cmd_pipe_plus.mc_wrdata_en_reg (\cmd_pipe_plus.mc_wrdata_en_reg ),
        .\cmd_pipe_plus.mc_wrdata_en_reg_0 (\cmd_pipe_plus.mc_wrdata_en_reg_0 ),
        .\ddr3_dm[5] (\ddr3_dm[5] ),
        .\ddr3_dm[6] (\ddr3_dm[6] ),
        .\ddr3_dm[7] (\ddr3_dm[7] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_16 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_17 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_18 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 (\read_fifo.tail_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_102 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_104 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ),
        .\entry_cnt_reg[4] (\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 ),
        .\entry_cnt_reg[4]_0 (\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_6 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (\gen_byte_sel_div2.calib_in_common_reg_7 ),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (\gen_byte_sel_div2.calib_in_common_reg_8 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_338 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_318 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_353 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_343 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_333 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_323 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_358 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_354 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_361 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_359 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_357 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_355 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_392 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_382 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_372 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_362 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_397 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_387 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_377 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_367 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_404 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_402 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_400 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_398 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_405 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_403 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_401 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_399 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_438 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_428 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_418 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_408 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_443 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_433 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_423 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_413 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_450 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_448 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_446 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_444 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_451 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_449 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_447 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_445 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_482 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_472 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_462 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_452 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_487 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_477 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_467 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_457 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_494 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_492 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_490 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_488 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_495 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_493 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_491 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_489 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_703 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_701 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_699 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_697 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_704 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_702 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_700 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_698 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_711 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_709 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_707 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_705 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_712 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_710 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_708 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_706 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_719 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_717 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_715 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_713 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_720 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_718 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_716 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_714 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_727 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_725 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_723 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_721 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_728 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_726 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_724 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_722 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_735 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_733 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_731 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_729 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_736 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_734 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_732 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_730 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_743 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_741 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_739 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_737 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_744 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_742 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_740 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_738 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_751 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_749 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_747 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_745 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_752 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_750 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_748 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_746 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_759 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_757 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_755 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_753 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_760 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_758 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_756 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_754 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (\gen_rd[5].rd_data_rise_wl_r_reg[5] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (\gen_rd[6].rd_data_rise_wl_r_reg[6] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (\gen_rd[7].rd_data_rise_wl_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .if_empty_r(\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r_2 ),
        .if_empty_r_0(\ddr_byte_lane_A.ddr_byte_lane_A/if_empty_r ),
        .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10),
        .init_calib_complete_reg_rep__10_0(init_calib_complete_reg_rep__10_0),
        .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11),
        .init_calib_complete_reg_rep__11_0(init_calib_complete_reg_rep__11_0),
        .init_calib_complete_reg_rep__11_1(init_calib_complete_reg_rep__11_1),
        .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12),
        .init_calib_complete_reg_rep__12_0(init_calib_complete_reg_rep__12_0),
        .init_calib_complete_reg_rep__12_1(init_calib_complete_reg_rep__12_1),
        .init_calib_complete_reg_rep__12_2(init_calib_complete_reg_rep__12_2),
        .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9),
        .init_calib_complete_reg_rep__9_0(init_calib_complete_reg_rep__9_0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .mcGo_w__0(mcGo_w__0[2]),
        .mc_read_idle_r_reg(mc_read_idle_r_reg_2),
        .mc_read_idle_r_reg_0(mc_read_idle_r_reg_3),
        .mc_read_idle_r_reg_1(mc_read_idle_r_reg_4),
        .mc_read_idle_r_reg_2(mc_read_idle_r_reg_5),
        .mc_read_idle_r_reg_3(mc_read_idle_r_reg_6),
        .mc_read_idle_r_reg_4(mc_read_idle_r_reg_7),
        .mc_read_idle_r_reg_5(mc_read_idle_r_reg_8),
        .mc_read_idle_r_reg_6(mc_read_idle_r_reg_9),
        .mc_read_idle_r_reg_7(mc_read_idle_r_reg_10),
        .mc_read_idle_r_reg_8(mc_read_idle_r_reg_11),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[0] (\read_fifo.fifo_ram[0].RAM32M0_i_22_n_0 ),
        .\my_empty_reg[1] (\my_empty_reg[1]_7 ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_8 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_9 ),
        .\my_empty_reg[4]_rep__1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_88 ),
        .\my_empty_reg[4]_rep__1_0 (\ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [0]),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_9 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_10 ),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376] ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[488] (\not_strict_mode.app_rd_data_reg[488] ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496] ),
        .\not_strict_mode.app_rd_data_reg[496]_0 (\not_strict_mode.app_rd_data_reg[496]_0 ),
        .\not_strict_mode.app_rd_data_reg[511] ({\not_strict_mode.app_rd_data_reg[511] [511:488],\not_strict_mode.app_rd_data_reg[511] [447:424],\not_strict_mode.app_rd_data_reg[511] [383:360],\not_strict_mode.app_rd_data_reg[511] [319:296],\not_strict_mode.app_rd_data_reg[511] [255:232],\not_strict_mode.app_rd_data_reg[511] [191:168],\not_strict_mode.app_rd_data_reg[511] [127:104],\not_strict_mode.app_rd_data_reg[511] [63:40]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ),
        .ofs_rdy_r_reg(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_694 ),
        .ofs_rdy_r_reg_0(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_696 ),
        .p_17_in(p_17_in),
        .p_1_in(p_1_in),
        .p_25_in(p_25_in),
        .p_29_in(p_29_in),
        .p_30_in(p_30_in),
        .p_31_out(p_31_out),
        .p_33_in(p_33_in),
        .p_34_in(p_34_in),
        .p_35_out(p_35_out),
        .p_37_in(p_37_in),
        .p_38_in(p_38_in),
        .p_39_out(p_39_out),
        .p_3_in(p_3_in),
        .p_41_in(p_41_in),
        .p_42_in(p_42_in),
        .p_43_out(p_43_out),
        .p_45_in(p_45_in),
        .p_46_in(p_46_in),
        .p_47_out(p_47_out),
        .p_49_in(p_49_in),
        .p_50_in(p_50_in),
        .p_51_out(p_51_out),
        .p_53_in(p_53_in),
        .p_54_in(p_54_in),
        .p_55_out(p_55_out),
        .p_57_in(p_57_in),
        .p_58_in(p_58_in),
        .p_59_out(p_59_out),
        .p_5_in(p_5_in),
        .p_61_in(p_61_in),
        .p_62_in(p_62_in),
        .p_63_out(p_63_out),
        .p_65_in(p_65_in),
        .p_66_in(p_66_in),
        .p_67_out(p_67_out),
        .p_69_in(p_69_in),
        .p_70_in(p_70_in),
        .p_71_out(p_71_out),
        .p_73_in(p_73_in),
        .p_74_in(p_74_in),
        .p_75_out(p_75_out),
        .p_77_in(p_77_in),
        .p_78_in(p_78_in),
        .p_79_out(p_79_out),
        .p_7_in(p_7_in),
        .p_81_in(p_81_in),
        .p_82_in(p_82_in),
        .p_83_out(p_83_out),
        .p_85_in(p_85_in),
        .p_86_in(p_86_in),
        .p_87_out(p_87_out),
        .p_89_in(p_89_in),
        .p_90_in(p_90_in),
        .p_91_out(p_91_out),
        .p_93_in(p_93_in),
        .p_94_in(p_94_in),
        .p_95_out(p_95_out),
        .phy_ctl_mstr_empty(phy_ctl_mstr_empty),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .phy_rddata_en(phy_rddata_en),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[7:5]),
        .\pi_dqs_found_lanes_r1_reg[10] (\pi_dqs_found_lanes_r1_reg[10] ),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .\pi_dqs_found_lanes_r1_reg[8] (\pi_dqs_found_lanes_r1_reg[8] ),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .\pi_dqs_found_lanes_r1_reg[9] (\pi_dqs_found_lanes_r1_reg[9] ),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .pi_phase_locked_all_r1_reg(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_6 ),
        .pi_phase_locked_all_r1_reg_0(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_30 ),
        .pi_phase_locked_all_r1_reg_1(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_56 ),
        .\pi_rdval_cnt_reg[5] (\pi_counter_read_val_w[2]_6 ),
        .pll_lock(pll_lock),
        .\po_rdval_cnt_reg[8] (\po_counter_read_val_w[2]_5 ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] [2:1]),
        .rd_active_r_reg(rd_active_r_reg),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] [2:1]),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3]_2 ),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3]_3 ),
        .\rd_ptr_reg_rep[3]_1 (\rd_ptr_reg_rep[3]_4 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1]_0 ),
        .\rd_ptr_timing_reg[1]_1 (\rd_ptr_timing_reg[1]_1 ),
        .read_calib(read_calib),
        .\read_fifo.fifo_out_data_r_reg[4] (\not_strict_mode.app_rd_data_reg[24] ),
        .\read_fifo.tail_r_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810 ),
        .rst_sync_r1_reg(ref_dll_lock_w__0),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst_0),
        .tail_r(tail_r[0]),
        .wr_en_12(wr_en_12),
        .wr_en_13(wr_en_13),
        .wr_en_14(wr_en_14),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[0]_1 (\wr_ptr_reg[0]_1 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_2 ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_3 ),
        .\wr_ptr_reg[1]_2 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3]_2 ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3]_3 ),
        .\wr_ptr_timing_reg[3]_1 (\wr_ptr_timing_reg[3]_4 ),
        .\write_buffer.wr_buf_out_data_reg[489] (\write_buffer.wr_buf_out_data_reg[489] ),
        .\write_buffer.wr_buf_out_data_reg[490] (\write_buffer.wr_buf_out_data_reg[490] ),
        .\write_buffer.wr_buf_out_data_reg[491] (\write_buffer.wr_buf_out_data_reg[491] ),
        .\write_buffer.wr_buf_out_data_reg[493] (\write_buffer.wr_buf_out_data_reg[493] ),
        .\write_buffer.wr_buf_out_data_reg[494] (\write_buffer.wr_buf_out_data_reg[494] ),
        .\write_buffer.wr_buf_out_data_reg[495] (\write_buffer.wr_buf_out_data_reg[495] ),
        .\write_buffer.wr_buf_out_data_reg[497] (\write_buffer.wr_buf_out_data_reg[497] ),
        .\write_buffer.wr_buf_out_data_reg[498] (\write_buffer.wr_buf_out_data_reg[498] ),
        .\write_buffer.wr_buf_out_data_reg[499] (\write_buffer.wr_buf_out_data_reg[499] ),
        .\write_buffer.wr_buf_out_data_reg[501] (\write_buffer.wr_buf_out_data_reg[501] ),
        .\write_buffer.wr_buf_out_data_reg[502] (\write_buffer.wr_buf_out_data_reg[502] ),
        .\write_buffer.wr_buf_out_data_reg[503] (\write_buffer.wr_buf_out_data_reg[503] ),
        .\write_buffer.wr_buf_out_data_reg[505] (\write_buffer.wr_buf_out_data_reg[505] ),
        .\write_buffer.wr_buf_out_data_reg[506] (\write_buffer.wr_buf_out_data_reg[506] ),
        .\write_buffer.wr_buf_out_data_reg[507] (\write_buffer.wr_buf_out_data_reg[507] ),
        .\write_buffer.wr_buf_out_data_reg[509] (\write_buffer.wr_buf_out_data_reg[509] ),
        .\write_buffer.wr_buf_out_data_reg[510] (\write_buffer.wr_buf_out_data_reg[510] ),
        .\write_buffer.wr_buf_out_data_reg[511] (\write_buffer.wr_buf_out_data_reg[511] ),
        .write_calib(write_calib));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 " *) 
  SRL16E \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(mcGo_r1),
        .Q(\mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ));
  FDRE \mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 
       (.C(CLK),
        .CE(1'b1),
        .D(\mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ),
        .Q(\mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ),
        .R(1'b0));
  FDRE \mcGo_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_gate_n_0),
        .Q(phy_ctl_ready),
        .R(rstdiv0_sync_r1_reg_rep__18));
  LUT2 #(
    .INIT(4'h8)) 
    mcGo_r_reg_gate
       (.I0(\mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ),
        .I1(mcGo_r_reg_r_13_n_0),
        .O(mcGo_r_reg_gate_n_0));
  FDRE mcGo_r_reg_r
       (.C(CLK),
        .CE(1'b1),
        .D(1'b1),
        .Q(mcGo_r_reg_r_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_0
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_n_0),
        .Q(mcGo_r_reg_r_0_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_1
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_0_n_0),
        .Q(mcGo_r_reg_r_1_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_10
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_9_n_0),
        .Q(mcGo_r_reg_r_10_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_11
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_10_n_0),
        .Q(mcGo_r_reg_r_11_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_12
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_11_n_0),
        .Q(mcGo_r_reg_r_12_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_13
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_12_n_0),
        .Q(mcGo_r_reg_r_13_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_2
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_1_n_0),
        .Q(mcGo_r_reg_r_2_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_3
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_2_n_0),
        .Q(mcGo_r_reg_r_3_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_4
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_3_n_0),
        .Q(mcGo_r_reg_r_4_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_5
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_4_n_0),
        .Q(mcGo_r_reg_r_5_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_6
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_5_n_0),
        .Q(mcGo_r_reg_r_6_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_7
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_6_n_0),
        .Q(mcGo_r_reg_r_7_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_8
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_7_n_0),
        .Q(mcGo_r_reg_r_8_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE mcGo_r_reg_r_9
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_r_reg_r_8_n_0),
        .Q(mcGo_r_reg_r_9_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  LUT1 #(
    .INIT(2'h1)) 
    \rclk_delay_reg[10]_srl11_i_1 
       (.I0(rst_primitives),
        .O(\rclk_delay_reg[10]_srl11_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_22 
       (.I0(\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r ),
        .I2(\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .I3(\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r ),
        .O(\read_fifo.fifo_ram[0].RAM32M0_i_22_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    rst_out_i_1
       (.I0(rclk_delay_11),
        .I1(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_98 ),
        .O(rst_out_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    rst_primitives_i_1
       (.I0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ),
        .O(p_0_in));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_mc_phy_wrapper" *) 
module mig_7series_0_mig_7series_v2_3_ddr_mc_phy_wrapper
   (ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_reset_n,
    out,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    COUNTERREADVAL,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    idelay_ld_rst,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    idelay_ld_rst_0,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    idelay_ld_rst_1,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    idelay_ld_rst_2,
    \rd_ptr_timing_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \rd_ptr_timing_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    B_of_data_full,
    \rd_ptr_timing_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    C_of_data_full,
    idelay_ld_rst_3,
    \my_empty_reg[7] ,
    idelay_ld_rst_4,
    \my_empty_reg[7]_0 ,
    idelay_ld_rst_5,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    phy_ctl_ready,
    ddr_ck_out,
    phy_mc_ctl_full,
    phy_rddata_en,
    rd_active_r_reg,
    \read_fifo.tail_r_reg[1] ,
    rd_buf_we,
    \my_empty_reg[1] ,
    \read_fifo.tail_r_reg[3] ,
    ADDRA,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    \not_strict_mode.app_rd_data_reg[352] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ,
    \my_empty_reg[1]_0 ,
    phy_mc_data_full,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ,
    \my_empty_reg[1]_3 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \my_empty_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ,
    \my_empty_reg[1]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ,
    \my_empty_reg[1]_6 ,
    rst_sync_r1_reg,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \not_strict_mode.app_rd_data_reg[488] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \my_empty_reg[1]_7 ,
    \my_empty_reg[1]_8 ,
    \my_empty_reg[1]_9 ,
    \my_empty_reg[6] ,
    pi_phase_locked_all_r1_reg,
    \read_fifo.tail_r_reg[0] ,
    \read_fifo.tail_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    DIA,
    DIB,
    DIC,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ,
    store_sr_req_r_reg,
    \pi_rdval_cnt_reg[4] ,
    \pi_rdval_cnt_reg[1] ,
    \pi_rdval_cnt_reg[2] ,
    \pi_rdval_cnt_reg[3] ,
    \pi_rdval_cnt_reg[0] ,
    \pi_rdval_cnt_reg[5] ,
    \FSM_onehot_cal1_state_r_reg[0] ,
    \FSM_onehot_cal1_state_r_reg[0]_0 ,
    \FSM_onehot_cal1_state_r_reg[0]_1 ,
    \not_strict_mode.app_rd_data_reg[511] ,
    \not_strict_mode.app_rd_data_reg[24] ,
    wr_en,
    wr_en_10,
    wr_en_11,
    of_ctl_full_v,
    wr_en_12,
    wr_en_13,
    wr_en_14,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7]_1 ,
    idelay_ld_rst_6,
    \wr_ptr_timing_reg[3]_0 ,
    \wr_ptr_timing_reg[0] ,
    \wr_ptr_timing_reg[3]_1 ,
    \wr_ptr_timing_reg[0]_0 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_timing_reg[3]_2 ,
    \my_empty_reg[7]_6 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_2 ,
    \wr_ptr_timing_reg[3]_3 ,
    \my_empty_reg[7]_7 ,
    \wr_ptr_reg[0]_1 ,
    \wr_ptr_reg[1]_3 ,
    \wr_ptr_timing_reg[3]_4 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[5] ,
    \my_empty_reg[3] ,
    \my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[5]_1 ,
    \my_empty_reg[3]_1 ,
    p_0_in1_in,
    \not_strict_mode.app_rd_data_reg[232] ,
    \not_strict_mode.app_rd_data_reg[496]_0 ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    \po_rdval_cnt_reg[0] ,
    \po_rdval_cnt_reg[1] ,
    \po_rdval_cnt_reg[2] ,
    \po_rdval_cnt_reg[3] ,
    \po_rdval_cnt_reg[4] ,
    \po_rdval_cnt_reg[5] ,
    \po_rdval_cnt_reg[6] ,
    \po_rdval_cnt_reg[7] ,
    \po_rdval_cnt_reg[8] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    p_0_out,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    mux_reset_n,
    A_pi_counter_load_en161_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable157_out,
    A_pi_fine_inc159_out,
    freq_refclk,
    mem_refclk,
    A_pi_rst_dqs_find155_out,
    sync_pulse,
    CLK,
    \pi_stg2_reg_l_reg[5] ,
    A_po_coarse_enable143_out,
    A_po_fine_enable141_out,
    A_po_fine_inc145_out,
    D0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    A_rst_primitives_reg,
    A_idelay_ce19_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    ofifo_rst0,
    B_po_coarse_enable27_out,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    B_po_fine_enable24_out,
    B_po_fine_inc30_out,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    C_po_coarse_enable66_out,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    C_po_fine_enable63_out,
    C_po_fine_inc69_out,
    \cmd_pipe_plus.mc_ras_n_reg[2] ,
    init_calib_complete_reg_rep__3,
    init_calib_complete_reg_rep__2,
    init_calib_complete_reg_rep__2_0,
    init_calib_complete_reg_rep__2_1,
    init_calib_complete_reg_rep__2_2,
    init_calib_complete_reg_rep__2_3,
    init_calib_complete_reg_rep__2_4,
    D8,
    init_calib_complete_reg_rep__2_5,
    pll_lock,
    read_calib,
    rstdiv0_sync_r1,
    write_calib,
    sys_rst_0,
    phy_if_reset,
    rstdiv0_sync_r1_reg_rep__0,
    A_pi_counter_load_en116_out,
    \calib_sel_reg[0]_0 ,
    A_pi_fine_enable112_out,
    A_pi_fine_inc114_out,
    A_pi_rst_dqs_find110_out,
    COUNTERLOADVAL,
    A_po_coarse_enable98_out,
    A_po_fine_enable96_out,
    A_po_fine_inc100_out,
    \write_buffer.wr_buf_out_data_reg[479] ,
    \write_buffer.wr_buf_out_data_reg[478] ,
    \write_buffer.wr_buf_out_data_reg[477] ,
    \write_buffer.wr_buf_out_data_reg[412] ,
    \write_buffer.wr_buf_out_data_reg[475] ,
    \write_buffer.wr_buf_out_data_reg[474] ,
    \write_buffer.wr_buf_out_data_reg[473] ,
    \write_buffer.wr_buf_out_data_reg[408] ,
    A_rst_primitives_reg_0,
    A_idelay_ce13_out,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    B_pi_counter_load_en38_out,
    \calib_sel_reg[0]_1 ,
    B_pi_fine_enable34_out,
    B_pi_fine_inc36_out,
    B_pi_rst_dqs_find32_out,
    \calib_zero_inputs_reg[0] ,
    B_po_coarse_enable20_out,
    B_po_fine_enable18_out,
    B_po_fine_inc22_out,
    \write_buffer.wr_buf_out_data_reg[471] ,
    \write_buffer.wr_buf_out_data_reg[470] ,
    \write_buffer.wr_buf_out_data_reg[469] ,
    \write_buffer.wr_buf_out_data_reg[404] ,
    \write_buffer.wr_buf_out_data_reg[467] ,
    \write_buffer.wr_buf_out_data_reg[466] ,
    \write_buffer.wr_buf_out_data_reg[465] ,
    \write_buffer.wr_buf_out_data_reg[400] ,
    A_rst_primitives_reg_1,
    B_idelay_ce9_out,
    \gen_byte_sel_div2.calib_in_common_reg_3 ,
    C_pi_counter_load_en64_out,
    \calib_sel_reg[1] ,
    C_pi_fine_enable60_out,
    C_pi_fine_inc62_out,
    C_pi_rst_dqs_find58_out,
    \calib_zero_inputs_reg[0]_0 ,
    C_po_coarse_enable46_out,
    C_po_fine_enable44_out,
    C_po_fine_inc48_out,
    \write_buffer.wr_buf_out_data_reg[463] ,
    \write_buffer.wr_buf_out_data_reg[462] ,
    \write_buffer.wr_buf_out_data_reg[461] ,
    \write_buffer.wr_buf_out_data_reg[396] ,
    \write_buffer.wr_buf_out_data_reg[459] ,
    \write_buffer.wr_buf_out_data_reg[458] ,
    \write_buffer.wr_buf_out_data_reg[457] ,
    \write_buffer.wr_buf_out_data_reg[392] ,
    A_rst_primitives_reg_2,
    C_idelay_ce5_out,
    \gen_byte_sel_div2.calib_in_common_reg_4 ,
    D_pi_counter_load_en90_out,
    \calib_sel_reg[0]_2 ,
    D_pi_fine_enable86_out,
    D_pi_fine_inc88_out,
    D_pi_rst_dqs_find84_out,
    \calib_zero_inputs_reg[0]_1 ,
    D_po_coarse_enable72_out,
    D_po_fine_enable70_out,
    D_po_fine_inc74_out,
    \write_buffer.wr_buf_out_data_reg[455] ,
    \write_buffer.wr_buf_out_data_reg[454] ,
    \write_buffer.wr_buf_out_data_reg[453] ,
    \write_buffer.wr_buf_out_data_reg[388] ,
    \write_buffer.wr_buf_out_data_reg[451] ,
    \write_buffer.wr_buf_out_data_reg[450] ,
    \write_buffer.wr_buf_out_data_reg[449] ,
    \write_buffer.wr_buf_out_data_reg[384] ,
    A_rst_primitives_reg_3,
    D_idelay_ce1_out,
    \gen_byte_sel_div2.calib_in_common_reg_5 ,
    A_pi_counter_load_en87_out,
    \calib_sel_reg[0]_3 ,
    A_pi_fine_enable83_out,
    A_pi_fine_inc85_out,
    A_pi_rst_dqs_find81_out,
    \calib_zero_inputs_reg[2] ,
    A_po_coarse_enable69_out,
    A_po_fine_enable67_out,
    A_po_fine_inc71_out,
    \write_buffer.wr_buf_out_data_reg[511] ,
    \write_buffer.wr_buf_out_data_reg[510] ,
    \write_buffer.wr_buf_out_data_reg[509] ,
    init_calib_complete_reg_rep__10,
    \write_buffer.wr_buf_out_data_reg[507] ,
    \write_buffer.wr_buf_out_data_reg[506] ,
    \write_buffer.wr_buf_out_data_reg[505] ,
    init_calib_complete_reg_rep__10_0,
    init_calib_complete_reg_rep__9,
    A_rst_primitives_reg_4,
    A_idelay_ce10_out,
    \gen_byte_sel_div2.calib_in_common_reg_6 ,
    B_pi_counter_load_en35_out,
    \calib_sel_reg[0]_4 ,
    B_pi_fine_enable31_out,
    B_pi_fine_inc33_out,
    B_pi_rst_dqs_find29_out,
    \calib_zero_inputs_reg[2]_0 ,
    B_po_coarse_enable17_out,
    B_po_fine_enable15_out,
    B_po_fine_inc19_out,
    \write_buffer.wr_buf_out_data_reg[503] ,
    \write_buffer.wr_buf_out_data_reg[502] ,
    \write_buffer.wr_buf_out_data_reg[501] ,
    init_calib_complete_reg_rep__12,
    init_calib_complete_reg_rep__11,
    \write_buffer.wr_buf_out_data_reg[499] ,
    \write_buffer.wr_buf_out_data_reg[498] ,
    \write_buffer.wr_buf_out_data_reg[497] ,
    init_calib_complete_reg_rep__11_0,
    A_rst_primitives_reg_5,
    B_idelay_ce6_out,
    \gen_byte_sel_div2.calib_in_common_reg_7 ,
    C_pi_counter_load_en61_out,
    \calib_sel_reg[1]_0 ,
    C_pi_fine_enable57_out,
    C_pi_fine_inc59_out,
    C_pi_rst_dqs_find55_out,
    \calib_zero_inputs_reg[2]_1 ,
    C_po_coarse_enable43_out,
    C_po_fine_enable41_out,
    C_po_fine_inc45_out,
    \write_buffer.wr_buf_out_data_reg[495] ,
    \write_buffer.wr_buf_out_data_reg[494] ,
    \write_buffer.wr_buf_out_data_reg[493] ,
    init_calib_complete_reg_rep__13,
    \write_buffer.wr_buf_out_data_reg[491] ,
    \write_buffer.wr_buf_out_data_reg[490] ,
    \write_buffer.wr_buf_out_data_reg[489] ,
    init_calib_complete_reg_rep__12_0,
    init_calib_complete_reg_rep__12_1,
    A_rst_primitives_reg_6,
    C_idelay_ce2_out,
    \gen_byte_sel_div2.calib_in_common_reg_8 ,
    rstdiv0_sync_r1_reg_rep__1,
    idle,
    wr_en_7,
    wr_en_8,
    wr_en_9,
    calib_ctl_wren_reg,
    rstdiv0_sync_r1_reg_rep__18,
    D_po_coarse_enable105_out,
    \gen_byte_sel_div2.calib_in_common_reg_9 ,
    D_po_fine_enable102_out,
    D_po_fine_inc108_out,
    init_calib_complete_reg_rep,
    init_calib_complete_reg_rep_0,
    init_calib_complete_reg_rep_1,
    init_calib_complete_reg_rep_2,
    phy_data_wr_en,
    phy_cmd_wr_en,
    ram_init_done_r,
    init_calib_complete_reg_rep_3,
    calib_cmd_wren,
    Q,
    init_complete_r1_timing_reg,
    tail_r,
    rstdiv0_sync_r1_reg_rep__21,
    mem_out,
    init_calib_complete_reg_rep__1,
    init_calib_complete_reg_rep__2_6,
    sys_rst,
    iodelay_ctrl_rdy,
    sys_rst_1,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    init_calib_complete_reg_rep__14,
    phy_dout,
    rstdiv0_sync_r1_reg_rep__24,
    \rd_mux_sel_r_reg[2] ,
    \calib_sel_reg[4] ,
    DOC,
    DOB,
    DOA,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    ram_init_addr,
    calib_wrdata_en,
    init_calib_complete_reg_rep__0,
    mc_wrdata_en,
    \rd_ptr_reg_rep[3] ,
    \rd_ptr_reg_rep[3]_0 ,
    \rd_ptr_reg_rep[3]_1 ,
    init_calib_complete_reg_rep__3_0,
    \write_buffer.wr_buf_out_data_reg[571] ,
    init_calib_complete_reg_rep__4,
    init_calib_complete_reg_rep__5,
    init_calib_complete_reg_rep__6,
    init_calib_complete_reg_rep__7,
    init_calib_complete_reg_rep__8,
    init_calib_complete_reg_rep__9_0,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    \cmd_pipe_plus.mc_wrdata_en_reg_0 ,
    \rd_ptr_reg_rep[3]_2 ,
    init_calib_complete_reg_rep__11_1,
    \rd_ptr_reg_rep[3]_3 ,
    init_calib_complete_reg_rep__12_2,
    \rd_ptr_reg_rep[3]_4 ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    mc_cas_n,
    D,
    mux_wrdata,
    \write_buffer.wr_buf_out_data_reg[351] ,
    mux_wrdata_mask,
    E,
    rstdiv0_sync_r1_reg_rep,
    calib_ctl_wren_reg_0,
    calib_ctl_wren_reg_1,
    \calib_seq_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    \po_stg2_wrcal_cnt_reg[2] );
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [1:0]out;
  output [7:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output [5:0]COUNTERREADVAL;
  output A_rst_primitives;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output idelay_ld_rst;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output idelay_ld_rst_0;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output idelay_ld_rst_1;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output idelay_ld_rst_2;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output B_of_data_full;
  output [1:0]\rd_ptr_timing_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output C_of_data_full;
  output idelay_ld_rst_3;
  output \my_empty_reg[7] ;
  output idelay_ld_rst_4;
  output \my_empty_reg[7]_0 ;
  output idelay_ld_rst_5;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output phy_ctl_ready;
  output [1:0]ddr_ck_out;
  output phy_mc_ctl_full;
  output phy_rddata_en;
  output rd_active_r_reg;
  output \read_fifo.tail_r_reg[1] ;
  output rd_buf_we;
  output \my_empty_reg[1] ;
  output \read_fifo.tail_r_reg[3] ;
  output [2:0]ADDRA;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  output \my_empty_reg[1]_0 ;
  output phy_mc_data_full;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  output \my_empty_reg[1]_3 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \my_empty_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  output \my_empty_reg[1]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  output \my_empty_reg[1]_6 ;
  output rst_sync_r1_reg;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  output [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \my_empty_reg[1]_7 ;
  output \my_empty_reg[1]_8 ;
  output \my_empty_reg[1]_9 ;
  output [15:0]\my_empty_reg[6] ;
  output pi_phase_locked_all_r1_reg;
  output \read_fifo.tail_r_reg[0] ;
  output \read_fifo.tail_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]DIA;
  output [1:0]DIB;
  output [1:0]DIC;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ;
  output store_sr_req_r_reg;
  output \pi_rdval_cnt_reg[4] ;
  output \pi_rdval_cnt_reg[1] ;
  output \pi_rdval_cnt_reg[2] ;
  output \pi_rdval_cnt_reg[3] ;
  output \pi_rdval_cnt_reg[0] ;
  output \pi_rdval_cnt_reg[5] ;
  output \FSM_onehot_cal1_state_r_reg[0] ;
  output \FSM_onehot_cal1_state_r_reg[0]_0 ;
  output \FSM_onehot_cal1_state_r_reg[0]_1 ;
  output [511:0]\not_strict_mode.app_rd_data_reg[511] ;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output wr_en;
  output wr_en_10;
  output wr_en_11;
  output [0:0]of_ctl_full_v;
  output wr_en_12;
  output wr_en_13;
  output wr_en_14;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7]_1 ;
  output idelay_ld_rst_6;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\wr_ptr_timing_reg[0] ;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  output [43:0]\my_empty_reg[7]_2 ;
  output [43:0]\my_empty_reg[7]_3 ;
  output [43:0]\my_empty_reg[7]_4 ;
  output [43:0]\my_empty_reg[7]_5 ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1]_1 ;
  output [3:0]\wr_ptr_timing_reg[3]_2 ;
  output [3:0]\my_empty_reg[7]_6 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_2 ;
  output [3:0]\wr_ptr_timing_reg[3]_3 ;
  output [3:0]\my_empty_reg[7]_7 ;
  output \wr_ptr_reg[0]_1 ;
  output \wr_ptr_reg[1]_3 ;
  output [3:0]\wr_ptr_timing_reg[3]_4 ;
  output [3:0]\my_empty_reg[7]_8 ;
  output \my_empty_reg[5] ;
  output \my_empty_reg[3] ;
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  output \my_empty_reg[5]_1 ;
  output \my_empty_reg[3]_1 ;
  output p_0_in1_in;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \not_strict_mode.app_rd_data_reg[496]_0 ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output \po_rdval_cnt_reg[0] ;
  output \po_rdval_cnt_reg[1] ;
  output \po_rdval_cnt_reg[2] ;
  output \po_rdval_cnt_reg[3] ;
  output \po_rdval_cnt_reg[4] ;
  output \po_rdval_cnt_reg[5] ;
  output \po_rdval_cnt_reg[6] ;
  output \po_rdval_cnt_reg[7] ;
  output \po_rdval_cnt_reg[8] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output p_0_out;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input mux_reset_n;
  input A_pi_counter_load_en161_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable157_out;
  input A_pi_fine_inc159_out;
  input freq_refclk;
  input mem_refclk;
  input A_pi_rst_dqs_find155_out;
  input sync_pulse;
  input CLK;
  input [5:0]\pi_stg2_reg_l_reg[5] ;
  input A_po_coarse_enable143_out;
  input A_po_fine_enable141_out;
  input A_po_fine_inc145_out;
  input [7:0]D0;
  input [7:0]D1;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D9;
  input A_rst_primitives_reg;
  input A_idelay_ce19_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input ofifo_rst0;
  input B_po_coarse_enable27_out;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input B_po_fine_enable24_out;
  input B_po_fine_inc30_out;
  input [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  input [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  input [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  input [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  input C_po_coarse_enable66_out;
  input \gen_byte_sel_div2.calib_in_common_reg_1 ;
  input C_po_fine_enable63_out;
  input C_po_fine_inc69_out;
  input [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  input [3:0]init_calib_complete_reg_rep__3;
  input [3:0]init_calib_complete_reg_rep__2;
  input [3:0]init_calib_complete_reg_rep__2_0;
  input [3:0]init_calib_complete_reg_rep__2_1;
  input [7:0]init_calib_complete_reg_rep__2_2;
  input [7:0]init_calib_complete_reg_rep__2_3;
  input [3:0]init_calib_complete_reg_rep__2_4;
  input [3:0]D8;
  input [3:0]init_calib_complete_reg_rep__2_5;
  input pll_lock;
  input read_calib;
  input rstdiv0_sync_r1;
  input write_calib;
  input sys_rst_0;
  input phy_if_reset;
  input rstdiv0_sync_r1_reg_rep__0;
  input A_pi_counter_load_en116_out;
  input \calib_sel_reg[0]_0 ;
  input A_pi_fine_enable112_out;
  input A_pi_fine_inc114_out;
  input A_pi_rst_dqs_find110_out;
  input [5:0]COUNTERLOADVAL;
  input A_po_coarse_enable98_out;
  input A_po_fine_enable96_out;
  input A_po_fine_inc100_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  input A_rst_primitives_reg_0;
  input A_idelay_ce13_out;
  input \gen_byte_sel_div2.calib_in_common_reg_2 ;
  input B_pi_counter_load_en38_out;
  input \calib_sel_reg[0]_1 ;
  input B_pi_fine_enable34_out;
  input B_pi_fine_inc36_out;
  input B_pi_rst_dqs_find32_out;
  input [5:0]\calib_zero_inputs_reg[0] ;
  input B_po_coarse_enable20_out;
  input B_po_fine_enable18_out;
  input B_po_fine_inc22_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  input A_rst_primitives_reg_1;
  input B_idelay_ce9_out;
  input \gen_byte_sel_div2.calib_in_common_reg_3 ;
  input C_pi_counter_load_en64_out;
  input \calib_sel_reg[1] ;
  input C_pi_fine_enable60_out;
  input C_pi_fine_inc62_out;
  input C_pi_rst_dqs_find58_out;
  input [5:0]\calib_zero_inputs_reg[0]_0 ;
  input C_po_coarse_enable46_out;
  input C_po_fine_enable44_out;
  input C_po_fine_inc48_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  input A_rst_primitives_reg_2;
  input C_idelay_ce5_out;
  input \gen_byte_sel_div2.calib_in_common_reg_4 ;
  input D_pi_counter_load_en90_out;
  input \calib_sel_reg[0]_2 ;
  input D_pi_fine_enable86_out;
  input D_pi_fine_inc88_out;
  input D_pi_rst_dqs_find84_out;
  input [5:0]\calib_zero_inputs_reg[0]_1 ;
  input D_po_coarse_enable72_out;
  input D_po_fine_enable70_out;
  input D_po_fine_inc74_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  input A_rst_primitives_reg_3;
  input D_idelay_ce1_out;
  input \gen_byte_sel_div2.calib_in_common_reg_5 ;
  input A_pi_counter_load_en87_out;
  input \calib_sel_reg[0]_3 ;
  input A_pi_fine_enable83_out;
  input A_pi_fine_inc85_out;
  input A_pi_rst_dqs_find81_out;
  input [5:0]\calib_zero_inputs_reg[2] ;
  input A_po_coarse_enable69_out;
  input A_po_fine_enable67_out;
  input A_po_fine_inc71_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  input [7:0]init_calib_complete_reg_rep__10;
  input [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  input [7:0]init_calib_complete_reg_rep__10_0;
  input [7:0]init_calib_complete_reg_rep__9;
  input A_rst_primitives_reg_4;
  input A_idelay_ce10_out;
  input \gen_byte_sel_div2.calib_in_common_reg_6 ;
  input B_pi_counter_load_en35_out;
  input \calib_sel_reg[0]_4 ;
  input B_pi_fine_enable31_out;
  input B_pi_fine_inc33_out;
  input B_pi_rst_dqs_find29_out;
  input [5:0]\calib_zero_inputs_reg[2]_0 ;
  input B_po_coarse_enable17_out;
  input B_po_fine_enable15_out;
  input B_po_fine_inc19_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  input [7:0]init_calib_complete_reg_rep__12;
  input [7:0]init_calib_complete_reg_rep__11;
  input [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  input [7:0]init_calib_complete_reg_rep__11_0;
  input A_rst_primitives_reg_5;
  input B_idelay_ce6_out;
  input \gen_byte_sel_div2.calib_in_common_reg_7 ;
  input C_pi_counter_load_en61_out;
  input \calib_sel_reg[1]_0 ;
  input C_pi_fine_enable57_out;
  input C_pi_fine_inc59_out;
  input C_pi_rst_dqs_find55_out;
  input [5:0]\calib_zero_inputs_reg[2]_1 ;
  input C_po_coarse_enable43_out;
  input C_po_fine_enable41_out;
  input C_po_fine_inc45_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  input [7:0]init_calib_complete_reg_rep__13;
  input [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  input [7:0]init_calib_complete_reg_rep__12_0;
  input [7:0]init_calib_complete_reg_rep__12_1;
  input A_rst_primitives_reg_6;
  input C_idelay_ce2_out;
  input \gen_byte_sel_div2.calib_in_common_reg_8 ;
  input rstdiv0_sync_r1_reg_rep__1;
  input idle;
  input wr_en_7;
  input wr_en_8;
  input wr_en_9;
  input calib_ctl_wren_reg;
  input rstdiv0_sync_r1_reg_rep__18;
  input D_po_coarse_enable105_out;
  input \gen_byte_sel_div2.calib_in_common_reg_9 ;
  input D_po_fine_enable102_out;
  input D_po_fine_inc108_out;
  input [3:0]init_calib_complete_reg_rep;
  input [3:0]init_calib_complete_reg_rep_0;
  input [3:0]init_calib_complete_reg_rep_1;
  input [3:0]init_calib_complete_reg_rep_2;
  input phy_data_wr_en;
  input phy_cmd_wr_en;
  input ram_init_done_r;
  input init_calib_complete_reg_rep_3;
  input calib_cmd_wren;
  input [1:0]Q;
  input init_complete_r1_timing_reg;
  input [3:0]tail_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input [63:0]mem_out;
  input init_calib_complete_reg_rep__1;
  input init_calib_complete_reg_rep__2_6;
  input sys_rst;
  input [0:0]iodelay_ctrl_rdy;
  input sys_rst_1;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input init_calib_complete_reg_rep__14;
  input [21:0]phy_dout;
  input rstdiv0_sync_r1_reg_rep__24;
  input [2:0]\rd_mux_sel_r_reg[2] ;
  input [3:0]\calib_sel_reg[4] ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]DOA;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  input \read_fifo.fifo_out_data_r_reg[5] ;
  input [0:0]ram_init_addr;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__0;
  input mc_wrdata_en;
  input [7:0]\rd_ptr_reg_rep[3] ;
  input [24:0]\rd_ptr_reg_rep[3]_0 ;
  input [32:0]\rd_ptr_reg_rep[3]_1 ;
  input init_calib_complete_reg_rep__3_0;
  input [111:0]\write_buffer.wr_buf_out_data_reg[571] ;
  input init_calib_complete_reg_rep__4;
  input init_calib_complete_reg_rep__5;
  input init_calib_complete_reg_rep__6;
  input init_calib_complete_reg_rep__7;
  input init_calib_complete_reg_rep__8;
  input init_calib_complete_reg_rep__9_0;
  input \cmd_pipe_plus.mc_wrdata_en_reg ;
  input \cmd_pipe_plus.mc_wrdata_en_reg_0 ;
  input [7:0]\rd_ptr_reg_rep[3]_2 ;
  input init_calib_complete_reg_rep__11_1;
  input [7:0]\rd_ptr_reg_rep[3]_3 ;
  input init_calib_complete_reg_rep__12_2;
  input [7:0]\rd_ptr_reg_rep[3]_4 ;
  input [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [0:0]mc_cas_n;
  input [5:0]D;
  input [207:0]mux_wrdata;
  input [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  input [31:0]mux_wrdata_mask;
  input [0:0]E;
  input rstdiv0_sync_r1_reg_rep;
  input [0:0]calib_ctl_wren_reg_0;
  input [0:0]calib_ctl_wren_reg_1;
  input [10:0]\calib_seq_reg[1] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  input [2:0]\po_stg2_wrcal_cnt_reg[2] ;

  wire [2:0]ADDRA;
  wire A_idelay_ce10_out;
  wire A_idelay_ce13_out;
  wire A_idelay_ce19_out;
  wire A_pi_counter_load_en116_out;
  wire A_pi_counter_load_en161_out;
  wire A_pi_counter_load_en87_out;
  wire A_pi_fine_enable112_out;
  wire A_pi_fine_enable157_out;
  wire A_pi_fine_enable83_out;
  wire A_pi_fine_inc114_out;
  wire A_pi_fine_inc159_out;
  wire A_pi_fine_inc85_out;
  wire A_pi_rst_dqs_find110_out;
  wire A_pi_rst_dqs_find155_out;
  wire A_pi_rst_dqs_find81_out;
  wire A_po_coarse_enable143_out;
  wire A_po_coarse_enable69_out;
  wire A_po_coarse_enable98_out;
  wire A_po_fine_enable141_out;
  wire A_po_fine_enable67_out;
  wire A_po_fine_enable96_out;
  wire A_po_fine_inc100_out;
  wire A_po_fine_inc145_out;
  wire A_po_fine_inc71_out;
  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire B_idelay_ce6_out;
  wire B_idelay_ce9_out;
  wire B_of_data_full;
  wire B_pi_counter_load_en35_out;
  wire B_pi_counter_load_en38_out;
  wire B_pi_fine_enable31_out;
  wire B_pi_fine_enable34_out;
  wire B_pi_fine_inc33_out;
  wire B_pi_fine_inc36_out;
  wire B_pi_rst_dqs_find29_out;
  wire B_pi_rst_dqs_find32_out;
  wire B_po_coarse_enable17_out;
  wire B_po_coarse_enable20_out;
  wire B_po_coarse_enable27_out;
  wire B_po_fine_enable15_out;
  wire B_po_fine_enable18_out;
  wire B_po_fine_enable24_out;
  wire B_po_fine_inc19_out;
  wire B_po_fine_inc22_out;
  wire B_po_fine_inc30_out;
  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire [5:0]COUNTERREADVAL;
  wire C_idelay_ce2_out;
  wire C_idelay_ce5_out;
  wire C_of_data_full;
  wire C_pi_counter_load_en61_out;
  wire C_pi_counter_load_en64_out;
  wire C_pi_fine_enable57_out;
  wire C_pi_fine_enable60_out;
  wire C_pi_fine_inc59_out;
  wire C_pi_fine_inc62_out;
  wire C_pi_rst_dqs_find55_out;
  wire C_pi_rst_dqs_find58_out;
  wire C_po_coarse_enable43_out;
  wire C_po_coarse_enable46_out;
  wire C_po_coarse_enable66_out;
  wire C_po_fine_enable41_out;
  wire C_po_fine_enable44_out;
  wire C_po_fine_enable63_out;
  wire C_po_fine_inc45_out;
  wire C_po_fine_inc48_out;
  wire C_po_fine_inc69_out;
  wire [5:0]D;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [3:0]D8;
  wire [7:0]D9;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire D_idelay_ce1_out;
  wire D_pi_counter_load_en90_out;
  wire D_pi_fine_enable86_out;
  wire D_pi_fine_inc88_out;
  wire D_pi_rst_dqs_find84_out;
  wire D_po_coarse_enable105_out;
  wire D_po_coarse_enable72_out;
  wire D_po_fine_enable102_out;
  wire D_po_fine_enable70_out;
  wire D_po_fine_inc108_out;
  wire D_po_fine_inc74_out;
  wire [0:0]E;
  wire \FSM_onehot_cal1_state_r_reg[0] ;
  wire \FSM_onehot_cal1_state_r_reg[0]_0 ;
  wire \FSM_onehot_cal1_state_r_reg[0]_1 ;
  wire [1:0]Q;
  wire calib_cmd_wren;
  wire calib_ctl_wren_reg;
  wire [0:0]calib_ctl_wren_reg_0;
  wire [0:0]calib_ctl_wren_reg_1;
  wire \calib_sel_reg[0] ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[0]_1 ;
  wire \calib_sel_reg[0]_2 ;
  wire \calib_sel_reg[0]_3 ;
  wire \calib_sel_reg[0]_4 ;
  wire \calib_sel_reg[1] ;
  wire \calib_sel_reg[1]_0 ;
  wire [3:0]\calib_sel_reg[4] ;
  wire [10:0]\calib_seq_reg[1] ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[0] ;
  wire [5:0]\calib_zero_inputs_reg[0]_0 ;
  wire [5:0]\calib_zero_inputs_reg[0]_1 ;
  wire [5:0]\calib_zero_inputs_reg[2] ;
  wire [5:0]\calib_zero_inputs_reg[2]_0 ;
  wire [5:0]\calib_zero_inputs_reg[2]_1 ;
  wire [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  wire [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg_0 ;
  wire [5:0]data_offset_1_i1;
  wire [5:0]data_offset_1_i2;
  wire [5:0]data_offset_2_i1;
  wire [5:0]data_offset_2_i2;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_3 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_4 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_5 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_6 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_7 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_8 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_9 ;
  wire \gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq_n_0 ;
  wire \gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq_n_0 ;
  wire \gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq_n_0 ;
  wire \gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq_n_0 ;
  wire \gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq_n_0 ;
  wire \gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq_n_0 ;
  wire \gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq_n_0 ;
  wire \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ;
  wire \gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ;
  wire \gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ;
  wire \gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ;
  wire \gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ;
  wire \gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_6;
  wire idle;
  wire [3:0]init_calib_complete_reg_rep;
  wire [3:0]init_calib_complete_reg_rep_0;
  wire [3:0]init_calib_complete_reg_rep_1;
  wire [3:0]init_calib_complete_reg_rep_2;
  wire init_calib_complete_reg_rep_3;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__1;
  wire [7:0]init_calib_complete_reg_rep__10;
  wire [7:0]init_calib_complete_reg_rep__10_0;
  wire [7:0]init_calib_complete_reg_rep__11;
  wire [7:0]init_calib_complete_reg_rep__11_0;
  wire init_calib_complete_reg_rep__11_1;
  wire [7:0]init_calib_complete_reg_rep__12;
  wire [7:0]init_calib_complete_reg_rep__12_0;
  wire [7:0]init_calib_complete_reg_rep__12_1;
  wire init_calib_complete_reg_rep__12_2;
  wire [7:0]init_calib_complete_reg_rep__13;
  wire init_calib_complete_reg_rep__14;
  wire [3:0]init_calib_complete_reg_rep__2;
  wire [3:0]init_calib_complete_reg_rep__2_0;
  wire [3:0]init_calib_complete_reg_rep__2_1;
  wire [7:0]init_calib_complete_reg_rep__2_2;
  wire [7:0]init_calib_complete_reg_rep__2_3;
  wire [3:0]init_calib_complete_reg_rep__2_4;
  wire [3:0]init_calib_complete_reg_rep__2_5;
  wire init_calib_complete_reg_rep__2_6;
  wire [3:0]init_calib_complete_reg_rep__3;
  wire init_calib_complete_reg_rep__3_0;
  wire init_calib_complete_reg_rep__4;
  wire init_calib_complete_reg_rep__5;
  wire init_calib_complete_reg_rep__6;
  wire init_calib_complete_reg_rep__7;
  wire init_calib_complete_reg_rep__8;
  wire [7:0]init_calib_complete_reg_rep__9;
  wire init_calib_complete_reg_rep__9_0;
  wire init_complete_r1_timing_reg;
  wire [0:0]iodelay_ctrl_rdy;
  wire [0:0]mc_cas_n;
  wire mc_wrdata_en;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire mux_reset_n;
  wire [207:0]mux_wrdata;
  wire [31:0]mux_wrdata_mask;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[1]_3 ;
  wire \my_empty_reg[1]_4 ;
  wire \my_empty_reg[1]_5 ;
  wire \my_empty_reg[1]_6 ;
  wire \my_empty_reg[1]_7 ;
  wire \my_empty_reg[1]_8 ;
  wire \my_empty_reg[1]_9 ;
  wire \my_empty_reg[3] ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[3]_1 ;
  wire \my_empty_reg[5] ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg[5]_1 ;
  wire [15:0]\my_empty_reg[6] ;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire [43:0]\my_empty_reg[7]_2 ;
  wire [43:0]\my_empty_reg[7]_3 ;
  wire [43:0]\my_empty_reg[7]_4 ;
  wire [43:0]\my_empty_reg[7]_5 ;
  wire [3:0]\my_empty_reg[7]_6 ;
  wire [3:0]\my_empty_reg[7]_7 ;
  wire [3:0]\my_empty_reg[7]_8 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  wire [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  wire \not_strict_mode.app_rd_data_reg[496]_0 ;
  wire [511:0]\not_strict_mode.app_rd_data_reg[511] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  wire [0:0]of_ctl_full_v;
  wire ofifo_rst0;
  wire [1:0]out;
  wire out_cas_n;
  wire out_cke;
  wire out_cs_n;
  wire out_odt;
  wire out_ras_n;
  wire out_we_n;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_0_out;
  wire p_101_in;
  wire p_102_in;
  wire p_103_out;
  wire p_105_in;
  wire p_106_in;
  wire p_107_out;
  wire p_109_in;
  wire p_10_in;
  wire p_110_in;
  wire p_111_out;
  wire p_113_in;
  wire p_114_in;
  wire p_115_out;
  wire p_117_in;
  wire p_118_in;
  wire p_119_out;
  wire p_121_in;
  wire p_122_in;
  wire p_123_out;
  wire p_125_in;
  wire p_126_in;
  wire p_127_out;
  wire p_12_in;
  wire p_131_out;
  wire p_133_in;
  wire p_134_in;
  wire p_135_out;
  wire p_137_in;
  wire p_138_in;
  wire p_139_out;
  wire p_13_in;
  wire p_141_in;
  wire p_142_in;
  wire p_143_out;
  wire p_145_in;
  wire p_146_in;
  wire p_147_out;
  wire p_149_in;
  wire p_14_in;
  wire p_150_in;
  wire p_151_out;
  wire p_153_in;
  wire p_154_in;
  wire p_155_out;
  wire p_157_in;
  wire p_158_in;
  wire p_159_out;
  wire p_15_in;
  wire p_161_in;
  wire p_162_in;
  wire p_163_out;
  wire p_165_in;
  wire p_166_in;
  wire p_167_out;
  wire p_169_in;
  wire p_16_in;
  wire p_170_in;
  wire p_171_out;
  wire p_173_in;
  wire p_174_in;
  wire p_175_out;
  wire p_177_in;
  wire p_178_in;
  wire p_179_out;
  wire p_17_in;
  wire p_181_in;
  wire p_182_in;
  wire p_183_out;
  wire p_185_in;
  wire p_186_in;
  wire p_187_out;
  wire p_189_in;
  wire p_18_in;
  wire p_190_in;
  wire p_191_out;
  wire p_193_in;
  wire p_194_in;
  wire p_195_out;
  wire p_197_in;
  wire p_198_in;
  wire p_199_out;
  wire p_19_in;
  wire p_1_in;
  wire p_201_in;
  wire p_202_in;
  wire p_203_out;
  wire p_205_in;
  wire p_206_in;
  wire p_207_out;
  wire p_209_in;
  wire p_20_in;
  wire p_210_in;
  wire p_211_out;
  wire p_213_in;
  wire p_214_in;
  wire p_215_out;
  wire p_217_in;
  wire p_218_in;
  wire p_219_out;
  wire p_21_in;
  wire p_221_in;
  wire p_222_in;
  wire p_223_out;
  wire p_225_in;
  wire p_226_in;
  wire p_227_out;
  wire p_229_in;
  wire p_22_in;
  wire p_230_in;
  wire p_231_out;
  wire p_233_in;
  wire p_234_in;
  wire p_235_out;
  wire p_237_in;
  wire p_238_in;
  wire p_239_out;
  wire p_241_in;
  wire p_242_in;
  wire p_243_out;
  wire p_245_in;
  wire p_246_in;
  wire p_247_out;
  wire p_249_in;
  wire p_24_in;
  wire p_250_in;
  wire p_251_out;
  wire p_253_in;
  wire p_254_in;
  wire p_255_out;
  wire p_25_in;
  wire p_26_in;
  wire p_27_in;
  wire p_28_in;
  wire p_29_in;
  wire p_29_out;
  wire p_2_in;
  wire p_30_in;
  wire p_31_out;
  wire p_32_in;
  wire p_33_in;
  wire p_34_in;
  wire p_34_out;
  wire p_35_out;
  wire p_37_in;
  wire p_38_in;
  wire p_39_out;
  wire p_3_in;
  wire p_41_in;
  wire p_42_in;
  wire p_43_out;
  wire p_45_in;
  wire p_46_in;
  wire p_47_out;
  wire p_49_in;
  wire p_4_in;
  wire p_50_in;
  wire p_51_out;
  wire p_53_in;
  wire p_54_in;
  wire p_55_out;
  wire p_57_in;
  wire p_58_in;
  wire p_59_out;
  wire p_5_in;
  wire p_61_in;
  wire p_62_in;
  wire p_63_out;
  wire p_65_in;
  wire p_66_in;
  wire p_67_out;
  wire p_69_in;
  wire p_6_in;
  wire p_70_in;
  wire p_71_out;
  wire p_73_in;
  wire p_74_in;
  wire p_75_out;
  wire p_77_in;
  wire p_78_in;
  wire p_79_out;
  wire p_7_in;
  wire p_81_in;
  wire p_82_in;
  wire p_83_out;
  wire p_85_in;
  wire p_86_in;
  wire p_87_out;
  wire p_89_in;
  wire p_8_in;
  wire p_90_in;
  wire p_91_out;
  wire p_93_in;
  wire p_94_in;
  wire p_95_out;
  wire p_97_in;
  wire p_98_in;
  wire p_99_out;
  wire p_9_in;
  wire phy_cmd_wr_en;
  wire phy_ctl_ready;
  wire [24:0]phy_ctl_wd_i1;
  wire [24:0]phy_ctl_wd_i2;
  wire phy_ctl_wr_i1;
  wire phy_ctl_wr_i2;
  wire phy_data_wr_en;
  wire [21:0]phy_dout;
  wire phy_if_reset;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire [7:0]pi_dqs_found_lanes;
  wire pi_phase_locked_all_r1_reg;
  wire \pi_rdval_cnt_reg[0] ;
  wire \pi_rdval_cnt_reg[1] ;
  wire \pi_rdval_cnt_reg[2] ;
  wire \pi_rdval_cnt_reg[3] ;
  wire \pi_rdval_cnt_reg[4] ;
  wire \pi_rdval_cnt_reg[5] ;
  wire [5:0]\pi_stg2_reg_l_reg[5] ;
  wire pll_lock;
  wire \po_rdval_cnt_reg[0] ;
  wire \po_rdval_cnt_reg[1] ;
  wire \po_rdval_cnt_reg[2] ;
  wire \po_rdval_cnt_reg[3] ;
  wire \po_rdval_cnt_reg[4] ;
  wire \po_rdval_cnt_reg[5] ;
  wire \po_rdval_cnt_reg[6] ;
  wire \po_rdval_cnt_reg[7] ;
  wire \po_rdval_cnt_reg[8] ;
  wire [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire [0:0]ram_init_addr;
  wire ram_init_done_r;
  wire rd_active_r_reg;
  wire rd_buf_we;
  wire [2:0]\rd_mux_sel_r_reg[2] ;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire [24:0]\rd_ptr_reg_rep[3]_0 ;
  wire [32:0]\rd_ptr_reg_rep[3]_1 ;
  wire [7:0]\rd_ptr_reg_rep[3]_2 ;
  wire [7:0]\rd_ptr_reg_rep[3]_3 ;
  wire [7:0]\rd_ptr_reg_rep[3]_4 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rd_ptr_timing_reg[1]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1]_1 ;
  wire read_calib;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire \read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire \read_fifo.tail_r_reg[3] ;
  wire rst_sync_r1_reg;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire store_sr_req_r_reg;
  wire sync_pulse;
  wire sys_rst;
  wire sys_rst_0;
  wire sys_rst_1;
  wire [3:0]tail_r;
  wire u_ddr_mc_phy_n_102;
  wire u_ddr_mc_phy_n_105;
  wire u_ddr_mc_phy_n_106;
  wire u_ddr_mc_phy_n_123;
  wire u_ddr_mc_phy_n_129;
  wire u_ddr_mc_phy_n_130;
  wire u_ddr_mc_phy_n_131;
  wire u_ddr_mc_phy_n_132;
  wire u_ddr_mc_phy_n_133;
  wire u_ddr_mc_phy_n_135;
  wire u_ddr_mc_phy_n_136;
  wire u_ddr_mc_phy_n_137;
  wire u_ddr_mc_phy_n_138;
  wire u_ddr_mc_phy_n_139;
  wire u_ddr_mc_phy_n_141;
  wire u_ddr_mc_phy_n_142;
  wire u_ddr_mc_phy_n_143;
  wire u_ddr_mc_phy_n_148;
  wire u_ddr_mc_phy_n_153;
  wire u_ddr_mc_phy_n_154;
  wire u_ddr_mc_phy_n_163;
  wire u_ddr_mc_phy_n_1650;
  wire u_ddr_mc_phy_n_1651;
  wire u_ddr_mc_phy_n_1652;
  wire u_ddr_mc_phy_n_177;
  wire u_ddr_mc_phy_n_178;
  wire u_ddr_mc_phy_n_18;
  wire u_ddr_mc_phy_n_19;
  wire u_ddr_mc_phy_n_196;
  wire u_ddr_mc_phy_n_36;
  wire u_ddr_mc_phy_n_39;
  wire u_ddr_mc_phy_n_40;
  wire u_ddr_mc_phy_n_41;
  wire u_ddr_mc_phy_n_42;
  wire u_ddr_mc_phy_n_58;
  wire u_ddr_mc_phy_n_71;
  wire u_ddr_mc_phy_n_83;
  wire wr_en;
  wire wr_en_10;
  wire wr_en_11;
  wire wr_en_12;
  wire wr_en_13;
  wire wr_en_14;
  wire wr_en_7;
  wire wr_en_8;
  wire wr_en_9;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[0]_1 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;
  wire \wr_ptr_reg[1]_3 ;
  wire [3:0]\wr_ptr_timing_reg[0] ;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3]_3 ;
  wire [3:0]\wr_ptr_timing_reg[3]_4 ;
  wire [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  wire [111:0]\write_buffer.wr_buf_out_data_reg[571] ;
  wire write_calib;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf 
       (.I(out_cke),
        .O(ddr3_cke));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf 
       (.I(out_odt),
        .O(ddr3_odt));
  FDRE \data_offset_1_i1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),
        .Q(data_offset_1_i1[0]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),
        .Q(data_offset_1_i1[1]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),
        .Q(data_offset_1_i1[2]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),
        .Q(data_offset_1_i1[3]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]),
        .Q(data_offset_1_i1[4]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]),
        .Q(data_offset_1_i1[5]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_1_i1[0]),
        .Q(data_offset_1_i2[0]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_1_i1[1]),
        .Q(data_offset_1_i2[1]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_1_i1[2]),
        .Q(data_offset_1_i2[2]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_1_i1[3]),
        .Q(data_offset_1_i2[3]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_1_i1[4]),
        .Q(data_offset_1_i2[4]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_1_i1[5]),
        .Q(data_offset_1_i2[5]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_2_reg[5] [0]),
        .Q(data_offset_2_i1[0]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_2_reg[5] [1]),
        .Q(data_offset_2_i1[1]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_2_reg[5] [2]),
        .Q(data_offset_2_i1[2]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_2_reg[5] [3]),
        .Q(data_offset_2_i1[3]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_2_reg[5] [4]),
        .Q(data_offset_2_i1[4]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_2_reg[5] [5]),
        .Q(data_offset_2_i1[5]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_2_i1[0]),
        .Q(data_offset_2_i2[0]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_2_i1[1]),
        .Q(data_offset_2_i2[1]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_2_i1[2]),
        .Q(data_offset_2_i2[2]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_2_i1[3]),
        .Q(data_offset_2_i2[3]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_2_i1[4]),
        .Q(data_offset_2_i2[4]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(data_offset_2_i1[5]),
        .Q(data_offset_2_i2[5]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[0].u_addr_obuf 
       (.I(p_26_in),
        .O(ddr3_addr[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[10].u_addr_obuf 
       (.I(p_6_in),
        .O(ddr3_addr[10]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[11].u_addr_obuf 
       (.I(p_4_in),
        .O(ddr3_addr[11]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[12].u_addr_obuf 
       (.I(p_2_in),
        .O(ddr3_addr[12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[13].u_addr_obuf 
       (.I(p_0_in),
        .O(ddr3_addr[13]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[1].u_addr_obuf 
       (.I(p_24_in),
        .O(ddr3_addr[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[2].u_addr_obuf 
       (.I(p_22_in),
        .O(ddr3_addr[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[3].u_addr_obuf 
       (.I(p_20_in),
        .O(ddr3_addr[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[4].u_addr_obuf 
       (.I(p_18_in),
        .O(ddr3_addr[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[5].u_addr_obuf 
       (.I(p_16_in),
        .O(ddr3_addr[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[6].u_addr_obuf 
       (.I(p_14_in),
        .O(ddr3_addr[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[7].u_addr_obuf 
       (.I(p_12_in),
        .O(ddr3_addr[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[8].u_addr_obuf 
       (.I(p_10_in),
        .O(ddr3_addr[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[9].u_addr_obuf 
       (.I(p_8_in),
        .O(ddr3_addr[9]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[0].u_bank_obuf 
       (.I(u_ddr_mc_phy_n_1652),
        .O(ddr3_ba[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[1].u_bank_obuf 
       (.I(u_ddr_mc_phy_n_1651),
        .O(ddr3_ba[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[2].u_bank_obuf 
       (.I(u_ddr_mc_phy_n_1650),
        .O(ddr3_ba[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf 
       (.I(out_cs_n),
        .O(ddr3_cs_n));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[0].u_dm_obuf 
       (.I(u_ddr_mc_phy_n_123),
        .O(ddr3_dm[0]),
        .T(p_21_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[1].u_dm_obuf 
       (.I(p_19_in),
        .O(ddr3_dm[1]),
        .T(u_ddr_mc_phy_n_102));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[2].u_dm_obuf 
       (.I(u_ddr_mc_phy_n_71),
        .O(ddr3_dm[2]),
        .T(p_15_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[3].u_dm_obuf 
       (.I(p_13_in),
        .O(ddr3_dm[3]),
        .T(u_ddr_mc_phy_n_58));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[4].u_dm_obuf 
       (.I(u_ddr_mc_phy_n_36),
        .O(ddr3_dm[4]),
        .T(p_9_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[5].u_dm_obuf 
       (.I(p_7_in),
        .O(ddr3_dm[5]),
        .T(u_ddr_mc_phy_n_196));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[6].u_dm_obuf 
       (.I(u_ddr_mc_phy_n_163),
        .O(ddr3_dm[6]),
        .T(p_3_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[7].u_dm_obuf 
       (.I(p_1_in),
        .O(ddr3_dm[7]),
        .T(u_ddr_mc_phy_n_148));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq 
       (.I(p_254_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[0]),
        .O(p_255_out),
        .T(p_253_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq 
       (.I(p_214_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[10]),
        .O(p_215_out),
        .T(p_213_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq 
       (.I(p_210_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[11]),
        .O(p_211_out),
        .T(p_209_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq 
       (.I(p_206_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[12]),
        .O(p_207_out),
        .T(p_205_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq 
       (.I(p_202_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[13]),
        .O(p_203_out),
        .T(p_201_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq 
       (.I(p_198_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[14]),
        .O(p_199_out),
        .T(p_197_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq 
       (.I(p_194_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[15]),
        .O(p_195_out),
        .T(p_193_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[16].u_iobuf_dq 
       (.I(p_190_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[16]),
        .O(p_191_out),
        .T(p_189_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[17].u_iobuf_dq 
       (.I(p_186_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[17]),
        .O(p_187_out),
        .T(p_185_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[18].u_iobuf_dq 
       (.I(p_182_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[18]),
        .O(p_183_out),
        .T(p_181_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[19].u_iobuf_dq 
       (.I(p_178_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[19]),
        .O(p_179_out),
        .T(p_177_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq 
       (.I(p_250_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[1]),
        .O(p_251_out),
        .T(p_249_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[20].u_iobuf_dq 
       (.I(p_174_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[20]),
        .O(p_175_out),
        .T(p_173_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[21].u_iobuf_dq 
       (.I(p_170_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[21]),
        .O(p_171_out),
        .T(p_169_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[22].u_iobuf_dq 
       (.I(p_166_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[22]),
        .O(p_167_out),
        .T(p_165_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[23].u_iobuf_dq 
       (.I(p_162_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[23]),
        .O(p_163_out),
        .T(p_161_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[24].u_iobuf_dq 
       (.I(p_158_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[24]),
        .O(p_159_out),
        .T(p_157_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[25].u_iobuf_dq 
       (.I(p_154_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[25]),
        .O(p_155_out),
        .T(p_153_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[26].u_iobuf_dq 
       (.I(p_150_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[26]),
        .O(p_151_out),
        .T(p_149_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[27].u_iobuf_dq 
       (.I(p_146_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[27]),
        .O(p_147_out),
        .T(p_145_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[28].u_iobuf_dq 
       (.I(p_142_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[28]),
        .O(p_143_out),
        .T(p_141_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[29].u_iobuf_dq 
       (.I(p_138_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[29]),
        .O(p_139_out),
        .T(p_137_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq 
       (.I(p_246_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[2]),
        .O(p_247_out),
        .T(p_245_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[30].u_iobuf_dq 
       (.I(p_134_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[30]),
        .O(p_135_out),
        .T(p_133_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[31].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_41),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[31]),
        .O(p_131_out),
        .T(u_ddr_mc_phy_n_42));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[32].u_iobuf_dq 
       (.I(p_126_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[32]),
        .O(p_127_out),
        .T(p_125_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[33].u_iobuf_dq 
       (.I(p_122_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[33]),
        .O(p_123_out),
        .T(p_121_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[34].u_iobuf_dq 
       (.I(p_118_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[34]),
        .O(p_119_out),
        .T(p_117_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[35].u_iobuf_dq 
       (.I(p_114_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[35]),
        .O(p_115_out),
        .T(p_113_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[36].u_iobuf_dq 
       (.I(p_110_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[36]),
        .O(p_111_out),
        .T(p_109_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[37].u_iobuf_dq 
       (.I(p_106_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[37]),
        .O(p_107_out),
        .T(p_105_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[38].u_iobuf_dq 
       (.I(p_102_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[38]),
        .O(p_103_out),
        .T(p_101_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[39].u_iobuf_dq 
       (.I(p_98_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[39]),
        .O(p_99_out),
        .T(p_97_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq 
       (.I(p_242_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[3]),
        .O(p_243_out),
        .T(p_241_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[40].u_iobuf_dq 
       (.I(p_94_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[40]),
        .O(p_95_out),
        .T(p_93_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[41].u_iobuf_dq 
       (.I(p_90_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[41]),
        .O(p_91_out),
        .T(p_89_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[42].u_iobuf_dq 
       (.I(p_86_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[42]),
        .O(p_87_out),
        .T(p_85_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[43].u_iobuf_dq 
       (.I(p_82_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[43]),
        .O(p_83_out),
        .T(p_81_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[44].u_iobuf_dq 
       (.I(p_78_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[44]),
        .O(p_79_out),
        .T(p_77_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[45].u_iobuf_dq 
       (.I(p_74_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[45]),
        .O(p_75_out),
        .T(p_73_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[46].u_iobuf_dq 
       (.I(p_70_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[46]),
        .O(p_71_out),
        .T(p_69_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[47].u_iobuf_dq 
       (.I(p_66_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[47]),
        .O(p_67_out),
        .T(p_65_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[48].u_iobuf_dq 
       (.I(p_62_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[48]),
        .O(p_63_out),
        .T(p_61_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[49].u_iobuf_dq 
       (.I(p_58_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[49]),
        .O(p_59_out),
        .T(p_57_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq 
       (.I(p_238_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[4]),
        .O(p_239_out),
        .T(p_237_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[50].u_iobuf_dq 
       (.I(p_54_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[50]),
        .O(p_55_out),
        .T(p_53_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[51].u_iobuf_dq 
       (.I(p_50_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[51]),
        .O(p_51_out),
        .T(p_49_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[52].u_iobuf_dq 
       (.I(p_46_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[52]),
        .O(p_47_out),
        .T(p_45_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[53].u_iobuf_dq 
       (.I(p_42_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[53]),
        .O(p_43_out),
        .T(p_41_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[54].u_iobuf_dq 
       (.I(p_38_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[54]),
        .O(p_39_out),
        .T(p_37_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[55].u_iobuf_dq 
       (.I(p_34_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[55]),
        .O(p_35_out),
        .T(p_33_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[56].u_iobuf_dq 
       (.I(p_30_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[56]),
        .O(p_31_out),
        .T(p_29_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_143),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[57]),
        .O(\gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq_n_0 ),
        .T(p_25_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_141),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[58]),
        .O(\gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq_n_0 ),
        .T(u_ddr_mc_phy_n_142));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_139),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[59]),
        .O(\gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq_n_0 ),
        .T(p_17_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq 
       (.I(p_234_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[5]),
        .O(p_235_out),
        .T(p_233_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_137),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[60]),
        .O(\gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq_n_0 ),
        .T(u_ddr_mc_phy_n_138));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_135),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[61]),
        .O(\gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq_n_0 ),
        .T(u_ddr_mc_phy_n_136));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_133),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[62]),
        .O(\gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq_n_0 ),
        .T(p_5_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq 
       (.I(u_ddr_mc_phy_n_131),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[63]),
        .O(\gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq_n_0 ),
        .T(u_ddr_mc_phy_n_132));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq 
       (.I(p_230_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[6]),
        .O(p_231_out),
        .T(p_229_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq 
       (.I(p_226_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[7]),
        .O(p_227_out),
        .T(p_225_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq 
       (.I(p_222_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[8]),
        .O(p_223_out),
        .T(p_221_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq 
       (.I(p_218_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[9]),
        .O(p_219_out),
        .T(p_217_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(u_ddr_mc_phy_n_105),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[0]),
        .IOB(ddr3_dqs_n[0]),
        .O(\gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .T(u_ddr_mc_phy_n_106));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(u_ddr_mc_phy_n_83),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[1]),
        .IOB(ddr3_dqs_n[1]),
        .O(p_34_out),
        .T(p_32_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(p_28_in),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[2]),
        .IOB(ddr3_dqs_n[2]),
        .O(p_29_out),
        .T(p_27_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(u_ddr_mc_phy_n_39),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[3]),
        .IOB(ddr3_dqs_n[3]),
        .O(\gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .T(u_ddr_mc_phy_n_40));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(u_ddr_mc_phy_n_18),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[4]),
        .IOB(ddr3_dqs_n[4]),
        .O(\gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .T(u_ddr_mc_phy_n_19));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(u_ddr_mc_phy_n_177),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[5]),
        .IOB(ddr3_dqs_n[5]),
        .O(\gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .T(u_ddr_mc_phy_n_178));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(u_ddr_mc_phy_n_153),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[6]),
        .IOB(ddr3_dqs_n[6]),
        .O(\gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .T(u_ddr_mc_phy_n_154));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(u_ddr_mc_phy_n_129),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[7]),
        .IOB(ddr3_dqs_n[7]),
        .O(\gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .T(u_ddr_mc_phy_n_130));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_reset_obuf.u_reset_obuf 
       (.I(mux_reset_n),
        .O(ddr3_reset_n));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo \genblk24.phy_ctl_pre_fifo_0 
       (.CLK(CLK),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_ctl_wren_reg(calib_ctl_wren_reg_1),
        .init_calib_complete_reg_rep__14(init_calib_complete_reg_rep__14),
        .\my_empty_reg[3]_0 (\my_empty_reg[3]_1 ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5]_1 ),
        .phy_dout(phy_dout[15]),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .wr_en_9(wr_en_9));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0 \genblk24.phy_ctl_pre_fifo_1 
       (.CLK(CLK),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_ctl_wren_reg(calib_ctl_wren_reg_0),
        .init_calib_complete_reg_rep__14(init_calib_complete_reg_rep__14),
        .\my_empty_reg[3]_0 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5]_0 ),
        .phy_dout(phy_dout[15]),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .wr_en_8(wr_en_8));
  mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1 \genblk24.phy_ctl_pre_fifo_2 
       (.CLK(CLK),
        .E(E),
        .calib_cmd_wren(calib_cmd_wren),
        .init_calib_complete_reg_rep__14(init_calib_complete_reg_rep__14),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5] ),
        .phy_dout(phy_dout[15]),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .wr_en_7(wr_en_7));
  FDRE \phy_ctl_wd_i1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [0]),
        .Q(phy_ctl_wd_i1[0]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [3]),
        .Q(phy_ctl_wd_i1[17]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [4]),
        .Q(phy_ctl_wd_i1[18]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [5]),
        .Q(phy_ctl_wd_i1[19]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [1]),
        .Q(phy_ctl_wd_i1[1]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [6]),
        .Q(phy_ctl_wd_i1[20]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [7]),
        .Q(phy_ctl_wd_i1[21]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [8]),
        .Q(phy_ctl_wd_i1[22]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [9]),
        .Q(phy_ctl_wd_i1[23]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [10]),
        .Q(phy_ctl_wd_i1[24]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq_reg[1] [2]),
        .Q(phy_ctl_wd_i1[2]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[0]),
        .Q(phy_ctl_wd_i2[0]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[17]),
        .Q(phy_ctl_wd_i2[17]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[18]),
        .Q(phy_ctl_wd_i2[18]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[19]),
        .Q(phy_ctl_wd_i2[19]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[1]),
        .Q(phy_ctl_wd_i2[1]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[20]),
        .Q(phy_ctl_wd_i2[20]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[21]),
        .Q(phy_ctl_wd_i2[21]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[22]),
        .Q(phy_ctl_wd_i2[22]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[23]),
        .Q(phy_ctl_wd_i2[23]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[24]),
        .Q(phy_ctl_wd_i2[24]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[2]),
        .Q(phy_ctl_wd_i2[2]),
        .R(1'b0));
  FDRE phy_ctl_wr_i1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(calib_ctl_wren_reg),
        .Q(phy_ctl_wr_i1),
        .R(1'b0));
  FDRE phy_ctl_wr_i2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wr_i1),
        .Q(phy_ctl_wr_i2),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_cas_n_obuf
       (.I(out_cas_n),
        .O(ddr3_cas_n));
  mig_7series_0_mig_7series_v2_3_ddr_mc_phy u_ddr_mc_phy
       (.ADDRA(ADDRA),
        .A_idelay_ce10_out(A_idelay_ce10_out),
        .A_idelay_ce13_out(A_idelay_ce13_out),
        .A_idelay_ce19_out(A_idelay_ce19_out),
        .A_pi_counter_load_en116_out(A_pi_counter_load_en116_out),
        .A_pi_counter_load_en161_out(A_pi_counter_load_en161_out),
        .A_pi_counter_load_en87_out(A_pi_counter_load_en87_out),
        .A_pi_fine_enable112_out(A_pi_fine_enable112_out),
        .A_pi_fine_enable157_out(A_pi_fine_enable157_out),
        .A_pi_fine_enable83_out(A_pi_fine_enable83_out),
        .A_pi_fine_inc114_out(A_pi_fine_inc114_out),
        .A_pi_fine_inc159_out(A_pi_fine_inc159_out),
        .A_pi_fine_inc85_out(A_pi_fine_inc85_out),
        .A_pi_rst_dqs_find110_out(A_pi_rst_dqs_find110_out),
        .A_pi_rst_dqs_find155_out(A_pi_rst_dqs_find155_out),
        .A_pi_rst_dqs_find81_out(A_pi_rst_dqs_find81_out),
        .A_po_coarse_enable143_out(A_po_coarse_enable143_out),
        .A_po_coarse_enable69_out(A_po_coarse_enable69_out),
        .A_po_coarse_enable98_out(A_po_coarse_enable98_out),
        .A_po_fine_enable141_out(A_po_fine_enable141_out),
        .A_po_fine_enable67_out(A_po_fine_enable67_out),
        .A_po_fine_enable96_out(A_po_fine_enable96_out),
        .A_po_fine_inc100_out(A_po_fine_inc100_out),
        .A_po_fine_inc145_out(A_po_fine_inc145_out),
        .A_po_fine_inc71_out(A_po_fine_inc71_out),
        .A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .B_idelay_ce6_out(B_idelay_ce6_out),
        .B_idelay_ce9_out(B_idelay_ce9_out),
        .B_pi_counter_load_en35_out(B_pi_counter_load_en35_out),
        .B_pi_counter_load_en38_out(B_pi_counter_load_en38_out),
        .B_pi_fine_enable31_out(B_pi_fine_enable31_out),
        .B_pi_fine_enable34_out(B_pi_fine_enable34_out),
        .B_pi_fine_inc33_out(B_pi_fine_inc33_out),
        .B_pi_fine_inc36_out(B_pi_fine_inc36_out),
        .B_pi_rst_dqs_find29_out(B_pi_rst_dqs_find29_out),
        .B_pi_rst_dqs_find32_out(B_pi_rst_dqs_find32_out),
        .B_po_coarse_enable17_out(B_po_coarse_enable17_out),
        .B_po_coarse_enable20_out(B_po_coarse_enable20_out),
        .B_po_coarse_enable27_out(B_po_coarse_enable27_out),
        .B_po_fine_enable15_out(B_po_fine_enable15_out),
        .B_po_fine_enable18_out(B_po_fine_enable18_out),
        .B_po_fine_enable24_out(B_po_fine_enable24_out),
        .B_po_fine_inc19_out(B_po_fine_inc19_out),
        .B_po_fine_inc22_out(B_po_fine_inc22_out),
        .B_po_fine_inc30_out(B_po_fine_inc30_out),
        .CLK(CLK),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .COUNTERREADVAL(COUNTERREADVAL),
        .C_idelay_ce2_out(C_idelay_ce2_out),
        .C_idelay_ce5_out(C_idelay_ce5_out),
        .C_pi_counter_load_en61_out(C_pi_counter_load_en61_out),
        .C_pi_counter_load_en64_out(C_pi_counter_load_en64_out),
        .C_pi_fine_enable57_out(C_pi_fine_enable57_out),
        .C_pi_fine_enable60_out(C_pi_fine_enable60_out),
        .C_pi_fine_inc59_out(C_pi_fine_inc59_out),
        .C_pi_fine_inc62_out(C_pi_fine_inc62_out),
        .C_pi_rst_dqs_find55_out(C_pi_rst_dqs_find55_out),
        .C_pi_rst_dqs_find58_out(C_pi_rst_dqs_find58_out),
        .C_po_coarse_enable43_out(C_po_coarse_enable43_out),
        .C_po_coarse_enable46_out(C_po_coarse_enable46_out),
        .C_po_coarse_enable66_out(C_po_coarse_enable66_out),
        .C_po_fine_enable41_out(C_po_fine_enable41_out),
        .C_po_fine_enable44_out(C_po_fine_enable44_out),
        .C_po_fine_enable63_out(C_po_fine_enable63_out),
        .C_po_fine_inc45_out(C_po_fine_inc45_out),
        .C_po_fine_inc48_out(C_po_fine_inc48_out),
        .C_po_fine_inc69_out(C_po_fine_inc69_out),
        .D(D),
        .D0(D0),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .D_idelay_ce1_out(D_idelay_ce1_out),
        .D_pi_counter_load_en90_out(D_pi_counter_load_en90_out),
        .D_pi_fine_enable86_out(D_pi_fine_enable86_out),
        .D_pi_fine_inc88_out(D_pi_fine_inc88_out),
        .D_pi_rst_dqs_find84_out(D_pi_rst_dqs_find84_out),
        .D_po_coarse_enable105_out(D_po_coarse_enable105_out),
        .D_po_coarse_enable72_out(D_po_coarse_enable72_out),
        .D_po_fine_enable102_out(D_po_fine_enable102_out),
        .D_po_fine_enable70_out(D_po_fine_enable70_out),
        .D_po_fine_inc108_out(D_po_fine_inc108_out),
        .D_po_fine_inc74_out(D_po_fine_inc74_out),
        .\FSM_onehot_cal1_state_r_reg[0] (\FSM_onehot_cal1_state_r_reg[0] ),
        .\FSM_onehot_cal1_state_r_reg[0]_0 (\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .\FSM_onehot_cal1_state_r_reg[0]_1 (\FSM_onehot_cal1_state_r_reg[0]_1 ),
        .Q({phy_ctl_wd_i2[24:17],phy_ctl_wd_i2[2:0]}),
        .calib_cmd_wren(calib_cmd_wren),
        .\calib_sel_reg[0] (\calib_sel_reg[0] ),
        .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_0 ),
        .\calib_sel_reg[0]_1 (\calib_sel_reg[0]_1 ),
        .\calib_sel_reg[0]_2 (\calib_sel_reg[0]_2 ),
        .\calib_sel_reg[0]_3 (\calib_sel_reg[0]_3 ),
        .\calib_sel_reg[0]_4 (\calib_sel_reg[0]_4 ),
        .\calib_sel_reg[1] (\calib_sel_reg[1] ),
        .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_0 ),
        .\calib_sel_reg[4] (\calib_sel_reg[4] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ),
        .\calib_zero_inputs_reg[0]_0 (\calib_zero_inputs_reg[0]_0 ),
        .\calib_zero_inputs_reg[0]_1 (\calib_zero_inputs_reg[0]_1 ),
        .\calib_zero_inputs_reg[2] (\calib_zero_inputs_reg[2] ),
        .\calib_zero_inputs_reg[2]_0 (\calib_zero_inputs_reg[2]_0 ),
        .\calib_zero_inputs_reg[2]_1 (\calib_zero_inputs_reg[2]_1 ),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2] ),
        .\cmd_pipe_plus.mc_cke_reg[3] (\cmd_pipe_plus.mc_cke_reg[3] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[2] (\cmd_pipe_plus.mc_ras_n_reg[2] ),
        .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ),
        .\cmd_pipe_plus.mc_wrdata_en_reg (\cmd_pipe_plus.mc_wrdata_en_reg ),
        .\cmd_pipe_plus.mc_wrdata_en_reg_0 (\cmd_pipe_plus.mc_wrdata_en_reg_0 ),
        .\data_offset_1_i2_reg[5] (data_offset_1_i2),
        .\data_offset_2_i2_reg[5] (data_offset_2_i2),
        .\ddr3_addr[13] ({p_0_in,p_2_in,p_4_in,p_6_in,p_8_in,p_10_in}),
        .\ddr3_addr[3] ({p_20_in,p_22_in,p_12_in,p_14_in,p_16_in,p_18_in,p_24_in,p_26_in,u_ddr_mc_phy_n_1650,u_ddr_mc_phy_n_1651,u_ddr_mc_phy_n_1652,out_ras_n}),
        .\ddr3_dm[0] (u_ddr_mc_phy_n_123),
        .\ddr3_dm[1] (u_ddr_mc_phy_n_102),
        .\ddr3_dm[2] (u_ddr_mc_phy_n_71),
        .\ddr3_dm[3] (u_ddr_mc_phy_n_58),
        .\ddr3_dm[4] (u_ddr_mc_phy_n_36),
        .\ddr3_dm[5] (u_ddr_mc_phy_n_196),
        .\ddr3_dm[6] (u_ddr_mc_phy_n_163),
        .\ddr3_dm[7] (u_ddr_mc_phy_n_148),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (u_ddr_mc_phy_n_41),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (u_ddr_mc_phy_n_42),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 (u_ddr_mc_phy_n_136),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 (u_ddr_mc_phy_n_137),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 (u_ddr_mc_phy_n_138),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 (u_ddr_mc_phy_n_139),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 (u_ddr_mc_phy_n_141),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 (u_ddr_mc_phy_n_142),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_16 (u_ddr_mc_phy_n_143),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_17 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_18 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 (u_ddr_mc_phy_n_131),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 (u_ddr_mc_phy_n_132),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 (u_ddr_mc_phy_n_133),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 (u_ddr_mc_phy_n_135),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .\gen_byte_sel_div2.calib_in_common_reg_3 (\gen_byte_sel_div2.calib_in_common_reg_3 ),
        .\gen_byte_sel_div2.calib_in_common_reg_4 (\gen_byte_sel_div2.calib_in_common_reg_4 ),
        .\gen_byte_sel_div2.calib_in_common_reg_5 (\gen_byte_sel_div2.calib_in_common_reg_5 ),
        .\gen_byte_sel_div2.calib_in_common_reg_6 (\gen_byte_sel_div2.calib_in_common_reg_6 ),
        .\gen_byte_sel_div2.calib_in_common_reg_7 (\gen_byte_sel_div2.calib_in_common_reg_7 ),
        .\gen_byte_sel_div2.calib_in_common_reg_8 (\gen_byte_sel_div2.calib_in_common_reg_8 ),
        .\gen_byte_sel_div2.calib_in_common_reg_9 (\gen_byte_sel_div2.calib_in_common_reg_9 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (\gen_rd[2].rd_data_rise_wl_r_reg[2] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (\gen_rd[3].rd_data_rise_wl_r_reg[3] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (\gen_rd[4].rd_data_rise_wl_r_reg[4] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (\gen_rd[5].rd_data_rise_wl_r_reg[5] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (\gen_rd[6].rd_data_rise_wl_r_reg[6] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (\gen_rd[7].rd_data_rise_wl_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .init_calib_complete_reg_rep_0(init_calib_complete_reg_rep_0),
        .init_calib_complete_reg_rep_1(init_calib_complete_reg_rep_1),
        .init_calib_complete_reg_rep_2(init_calib_complete_reg_rep_2),
        .init_calib_complete_reg_rep_3(init_calib_complete_reg_rep_3),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1),
        .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10),
        .init_calib_complete_reg_rep__10_0(init_calib_complete_reg_rep__10_0),
        .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11),
        .init_calib_complete_reg_rep__11_0(init_calib_complete_reg_rep__11_0),
        .init_calib_complete_reg_rep__11_1(init_calib_complete_reg_rep__11_1),
        .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12),
        .init_calib_complete_reg_rep__12_0(init_calib_complete_reg_rep__12_0),
        .init_calib_complete_reg_rep__12_1(init_calib_complete_reg_rep__12_1),
        .init_calib_complete_reg_rep__12_2(init_calib_complete_reg_rep__12_2),
        .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13),
        .init_calib_complete_reg_rep__14(init_calib_complete_reg_rep__14),
        .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2),
        .init_calib_complete_reg_rep__2_0(init_calib_complete_reg_rep__2_0),
        .init_calib_complete_reg_rep__2_1(init_calib_complete_reg_rep__2_1),
        .init_calib_complete_reg_rep__2_2(init_calib_complete_reg_rep__2_2),
        .init_calib_complete_reg_rep__2_3(init_calib_complete_reg_rep__2_3),
        .init_calib_complete_reg_rep__2_4(init_calib_complete_reg_rep__2_4),
        .init_calib_complete_reg_rep__2_5(init_calib_complete_reg_rep__2_5),
        .init_calib_complete_reg_rep__2_6(init_calib_complete_reg_rep__2_6),
        .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3),
        .init_calib_complete_reg_rep__3_0(init_calib_complete_reg_rep__3_0),
        .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4),
        .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),
        .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),
        .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),
        .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9),
        .init_calib_complete_reg_rep__9_0(init_calib_complete_reg_rep__9_0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .mc_cas_n(mc_cas_n),
        .mc_read_idle_r_reg(\gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .mc_read_idle_r_reg_0(\gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .mc_read_idle_r_reg_1(\gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .mc_read_idle_r_reg_10(\gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .mc_read_idle_r_reg_11(\gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .mc_read_idle_r_reg_2(\gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs_n_0 ),
        .mc_read_idle_r_reg_3(\gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq_n_0 ),
        .mc_read_idle_r_reg_4(\gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq_n_0 ),
        .mc_read_idle_r_reg_5(\gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq_n_0 ),
        .mc_read_idle_r_reg_6(\gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq_n_0 ),
        .mc_read_idle_r_reg_7(\gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq_n_0 ),
        .mc_read_idle_r_reg_8(\gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq_n_0 ),
        .mc_read_idle_r_reg_9(\gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq_n_0 ),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_dq_out({out_cas_n,out_we_n,out_cs_n,out_cke,out_odt}),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .mux_wrdata(mux_wrdata),
        .mux_wrdata_mask(mux_wrdata_mask),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ),
        .\my_empty_reg[1]_3 (\my_empty_reg[1]_3 ),
        .\my_empty_reg[1]_4 (\my_empty_reg[1]_4 ),
        .\my_empty_reg[1]_5 (\my_empty_reg[1]_5 ),
        .\my_empty_reg[1]_6 (\my_empty_reg[1]_6 ),
        .\my_empty_reg[1]_7 (\my_empty_reg[1]_7 ),
        .\my_empty_reg[1]_8 (\my_empty_reg[1]_8 ),
        .\my_empty_reg[1]_9 (\my_empty_reg[1]_9 ),
        .\my_empty_reg[6] (\my_empty_reg[6] ),
        .\my_empty_reg[7] (B_of_data_full),
        .\my_empty_reg[7]_0 (C_of_data_full),
        .\my_empty_reg[7]_1 (\my_empty_reg[7] ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_7 ),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ),
        .\not_strict_mode.app_rd_data_reg[352] (\not_strict_mode.app_rd_data_reg[352] ),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376] ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[488] (\not_strict_mode.app_rd_data_reg[488] ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496] ),
        .\not_strict_mode.app_rd_data_reg[496]_0 (\not_strict_mode.app_rd_data_reg[496]_0 ),
        .\not_strict_mode.app_rd_data_reg[511] (\not_strict_mode.app_rd_data_reg[511] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),
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        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),
        .of_ctl_full_v(of_ctl_full_v),
        .ofifo_rst0(ofifo_rst0),
        .ofifo_rst_reg(A_rst_primitives),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .p_0_out(p_0_out),
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        .p_102_in(p_102_in),
        .p_103_out(p_103_out),
        .p_105_in(p_105_in),
        .p_106_in(p_106_in),
        .p_107_out(p_107_out),
        .p_109_in(p_109_in),
        .p_110_in(p_110_in),
        .p_111_out(p_111_out),
        .p_113_in(p_113_in),
        .p_114_in(p_114_in),
        .p_115_out(p_115_out),
        .p_117_in(p_117_in),
        .p_118_in(p_118_in),
        .p_119_out(p_119_out),
        .p_121_in(p_121_in),
        .p_122_in(p_122_in),
        .p_123_out(p_123_out),
        .p_125_in(p_125_in),
        .p_126_in(p_126_in),
        .p_127_out(p_127_out),
        .p_131_out(p_131_out),
        .p_133_in(p_133_in),
        .p_134_in(p_134_in),
        .p_135_out(p_135_out),
        .p_137_in(p_137_in),
        .p_138_in(p_138_in),
        .p_139_out(p_139_out),
        .p_13_in(p_13_in),
        .p_141_in(p_141_in),
        .p_142_in(p_142_in),
        .p_143_out(p_143_out),
        .p_145_in(p_145_in),
        .p_146_in(p_146_in),
        .p_147_out(p_147_out),
        .p_149_in(p_149_in),
        .p_150_in(p_150_in),
        .p_151_out(p_151_out),
        .p_153_in(p_153_in),
        .p_154_in(p_154_in),
        .p_155_out(p_155_out),
        .p_157_in(p_157_in),
        .p_158_in(p_158_in),
        .p_159_out(p_159_out),
        .p_15_in(p_15_in),
        .p_161_in(p_161_in),
        .p_162_in(p_162_in),
        .p_163_out(p_163_out),
        .p_165_in(p_165_in),
        .p_166_in(p_166_in),
        .p_167_out(p_167_out),
        .p_169_in(p_169_in),
        .p_170_in(p_170_in),
        .p_171_out(p_171_out),
        .p_173_in(p_173_in),
        .p_174_in(p_174_in),
        .p_175_out(p_175_out),
        .p_177_in(p_177_in),
        .p_178_in(p_178_in),
        .p_179_out(p_179_out),
        .p_17_in(p_17_in),
        .p_181_in(p_181_in),
        .p_182_in(p_182_in),
        .p_183_out(p_183_out),
        .p_185_in(p_185_in),
        .p_186_in(p_186_in),
        .p_187_out(p_187_out),
        .p_189_in(p_189_in),
        .p_190_in(p_190_in),
        .p_191_out(p_191_out),
        .p_193_in(p_193_in),
        .p_194_in(p_194_in),
        .p_195_out(p_195_out),
        .p_197_in(p_197_in),
        .p_198_in(p_198_in),
        .p_199_out(p_199_out),
        .p_19_in(p_19_in),
        .p_1_in(p_1_in),
        .p_201_in(p_201_in),
        .p_202_in(p_202_in),
        .p_203_out(p_203_out),
        .p_205_in(p_205_in),
        .p_206_in(p_206_in),
        .p_207_out(p_207_out),
        .p_209_in(p_209_in),
        .p_210_in(p_210_in),
        .p_211_out(p_211_out),
        .p_213_in(p_213_in),
        .p_214_in(p_214_in),
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        .p_217_in(p_217_in),
        .p_218_in(p_218_in),
        .p_219_out(p_219_out),
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        .p_221_in(p_221_in),
        .p_222_in(p_222_in),
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        .p_225_in(p_225_in),
        .p_226_in(p_226_in),
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        .p_230_in(p_230_in),
        .p_231_out(p_231_out),
        .p_233_in(p_233_in),
        .p_234_in(p_234_in),
        .p_235_out(p_235_out),
        .p_237_in(p_237_in),
        .p_238_in(p_238_in),
        .p_239_out(p_239_out),
        .p_241_in(p_241_in),
        .p_242_in(p_242_in),
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        .p_246_in(p_246_in),
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        .p_249_in(p_249_in),
        .p_250_in(p_250_in),
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        .p_254_in(p_254_in),
        .p_255_out(p_255_out),
        .p_25_in(p_25_in),
        .p_27_in(p_27_in),
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        .p_29_in(p_29_in),
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        .p_30_in(p_30_in),
        .p_31_out(p_31_out),
        .p_32_in(p_32_in),
        .p_33_in(p_33_in),
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        .p_35_out(p_35_out),
        .p_37_in(p_37_in),
        .p_38_in(p_38_in),
        .p_39_out(p_39_out),
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        .p_41_in(p_41_in),
        .p_42_in(p_42_in),
        .p_43_out(p_43_out),
        .p_45_in(p_45_in),
        .p_46_in(p_46_in),
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        .p_49_in(p_49_in),
        .p_50_in(p_50_in),
        .p_51_out(p_51_out),
        .p_53_in(p_53_in),
        .p_54_in(p_54_in),
        .p_55_out(p_55_out),
        .p_57_in(p_57_in),
        .p_58_in(p_58_in),
        .p_59_out(p_59_out),
        .p_5_in(p_5_in),
        .p_61_in(p_61_in),
        .p_62_in(p_62_in),
        .p_63_out(p_63_out),
        .p_65_in(p_65_in),
        .p_66_in(p_66_in),
        .p_67_out(p_67_out),
        .p_69_in(p_69_in),
        .p_70_in(p_70_in),
        .p_71_out(p_71_out),
        .p_73_in(p_73_in),
        .p_74_in(p_74_in),
        .p_75_out(p_75_out),
        .p_77_in(p_77_in),
        .p_78_in(p_78_in),
        .p_79_out(p_79_out),
        .p_7_in(p_7_in),
        .p_81_in(p_81_in),
        .p_82_in(p_82_in),
        .p_83_out(p_83_out),
        .p_85_in(p_85_in),
        .p_86_in(p_86_in),
        .p_87_out(p_87_out),
        .p_89_in(p_89_in),
        .p_90_in(p_90_in),
        .p_91_out(p_91_out),
        .p_93_in(p_93_in),
        .p_94_in(p_94_in),
        .p_95_out(p_95_out),
        .p_97_in(p_97_in),
        .p_98_in(p_98_in),
        .p_99_out(p_99_out),
        .p_9_in(p_9_in),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_ctl_ready(phy_ctl_ready),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .phy_if_reset(phy_if_reset),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .pi_dqs_found_lanes(pi_dqs_found_lanes),
        .\pi_dqs_found_lanes_r1_reg[0] (u_ddr_mc_phy_n_39),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (u_ddr_mc_phy_n_40),
        .\pi_dqs_found_lanes_r1_reg[10] (u_ddr_mc_phy_n_177),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (u_ddr_mc_phy_n_178),
        .\pi_dqs_found_lanes_r1_reg[2] (u_ddr_mc_phy_n_83),
        .\pi_dqs_found_lanes_r1_reg[3] (u_ddr_mc_phy_n_105),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (u_ddr_mc_phy_n_106),
        .\pi_dqs_found_lanes_r1_reg[4] (u_ddr_mc_phy_n_18),
        .\pi_dqs_found_lanes_r1_reg[4]_0 (u_ddr_mc_phy_n_19),
        .\pi_dqs_found_lanes_r1_reg[8] (u_ddr_mc_phy_n_129),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (u_ddr_mc_phy_n_130),
        .\pi_dqs_found_lanes_r1_reg[9] (u_ddr_mc_phy_n_153),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (u_ddr_mc_phy_n_154),
        .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),
        .\pi_rdval_cnt_reg[0] (\pi_rdval_cnt_reg[0] ),
        .\pi_rdval_cnt_reg[1] (\pi_rdval_cnt_reg[1] ),
        .\pi_rdval_cnt_reg[2] (\pi_rdval_cnt_reg[2] ),
        .\pi_rdval_cnt_reg[3] (\pi_rdval_cnt_reg[3] ),
        .\pi_rdval_cnt_reg[4] (\pi_rdval_cnt_reg[4] ),
        .\pi_rdval_cnt_reg[5] (\pi_rdval_cnt_reg[5] ),
        .\pi_stg2_reg_l_reg[5] (\pi_stg2_reg_l_reg[5] ),
        .pll_lock(pll_lock),
        .\po_rdval_cnt_reg[0] (\po_rdval_cnt_reg[0] ),
        .\po_rdval_cnt_reg[1] (\po_rdval_cnt_reg[1] ),
        .\po_rdval_cnt_reg[2] (\po_rdval_cnt_reg[2] ),
        .\po_rdval_cnt_reg[3] (\po_rdval_cnt_reg[3] ),
        .\po_rdval_cnt_reg[4] (\po_rdval_cnt_reg[4] ),
        .\po_rdval_cnt_reg[5] (\po_rdval_cnt_reg[5] ),
        .\po_rdval_cnt_reg[6] (\po_rdval_cnt_reg[6] ),
        .\po_rdval_cnt_reg[7] (\po_rdval_cnt_reg[7] ),
        .\po_rdval_cnt_reg[8] (\po_rdval_cnt_reg[8] ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .ram_init_addr(ram_init_addr),
        .ram_init_done_r(ram_init_done_r),
        .rd_active_r_reg(rd_active_r_reg),
        .rd_buf_we(rd_buf_we),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] ),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3]_0 ),
        .\rd_ptr_reg_rep[3]_1 (\rd_ptr_reg_rep[3]_1 ),
        .\rd_ptr_reg_rep[3]_2 (\rd_ptr_reg_rep[3]_2 ),
        .\rd_ptr_reg_rep[3]_3 (\rd_ptr_reg_rep[3]_3 ),
        .\rd_ptr_reg_rep[3]_4 (\rd_ptr_reg_rep[3]_4 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1]_0 ),
        .\rd_ptr_timing_reg[1]_1 (\rd_ptr_timing_reg[1]_1 ),
        .read_calib(read_calib),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.fifo_out_data_r_reg[6] (Q),
        .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1]_0 ),
        .\read_fifo.tail_r_reg[3] (\read_fifo.tail_r_reg[3] ),
        .rst_sync_r1_reg(rst_sync_r1_reg),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .store_sr_req_r_reg(store_sr_req_r_reg),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst),
        .sys_rst_0(sys_rst_0),
        .sys_rst_1(sys_rst_1),
        .tail_r(tail_r),
        .wr_en(wr_en),
        .wr_en_10(wr_en_10),
        .wr_en_11(wr_en_11),
        .wr_en_12(wr_en_12),
        .wr_en_13(wr_en_13),
        .wr_en_14(wr_en_14),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[0]_1 (\wr_ptr_reg[0]_1 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_reg[1]_2 (\wr_ptr_reg[1]_2 ),
        .\wr_ptr_reg[1]_3 (\wr_ptr_reg[1]_3 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3]_0 ),
        .\wr_ptr_timing_reg[3]_1 (\wr_ptr_timing_reg[3]_1 ),
        .\wr_ptr_timing_reg[3]_2 (\wr_ptr_timing_reg[3]_2 ),
        .\wr_ptr_timing_reg[3]_3 (\wr_ptr_timing_reg[3]_3 ),
        .\wr_ptr_timing_reg[3]_4 (\wr_ptr_timing_reg[3]_4 ),
        .\write_buffer.wr_buf_out_data_reg[351] (\write_buffer.wr_buf_out_data_reg[351] ),
        .\write_buffer.wr_buf_out_data_reg[384] (\write_buffer.wr_buf_out_data_reg[384] ),
        .\write_buffer.wr_buf_out_data_reg[388] (\write_buffer.wr_buf_out_data_reg[388] ),
        .\write_buffer.wr_buf_out_data_reg[392] (\write_buffer.wr_buf_out_data_reg[392] ),
        .\write_buffer.wr_buf_out_data_reg[396] (\write_buffer.wr_buf_out_data_reg[396] ),
        .\write_buffer.wr_buf_out_data_reg[400] (\write_buffer.wr_buf_out_data_reg[400] ),
        .\write_buffer.wr_buf_out_data_reg[404] (\write_buffer.wr_buf_out_data_reg[404] ),
        .\write_buffer.wr_buf_out_data_reg[408] (\write_buffer.wr_buf_out_data_reg[408] ),
        .\write_buffer.wr_buf_out_data_reg[412] (\write_buffer.wr_buf_out_data_reg[412] ),
        .\write_buffer.wr_buf_out_data_reg[449] (\write_buffer.wr_buf_out_data_reg[449] ),
        .\write_buffer.wr_buf_out_data_reg[450] (\write_buffer.wr_buf_out_data_reg[450] ),
        .\write_buffer.wr_buf_out_data_reg[451] (\write_buffer.wr_buf_out_data_reg[451] ),
        .\write_buffer.wr_buf_out_data_reg[453] (\write_buffer.wr_buf_out_data_reg[453] ),
        .\write_buffer.wr_buf_out_data_reg[454] (\write_buffer.wr_buf_out_data_reg[454] ),
        .\write_buffer.wr_buf_out_data_reg[455] (\write_buffer.wr_buf_out_data_reg[455] ),
        .\write_buffer.wr_buf_out_data_reg[457] (\write_buffer.wr_buf_out_data_reg[457] ),
        .\write_buffer.wr_buf_out_data_reg[458] (\write_buffer.wr_buf_out_data_reg[458] ),
        .\write_buffer.wr_buf_out_data_reg[459] (\write_buffer.wr_buf_out_data_reg[459] ),
        .\write_buffer.wr_buf_out_data_reg[461] (\write_buffer.wr_buf_out_data_reg[461] ),
        .\write_buffer.wr_buf_out_data_reg[462] (\write_buffer.wr_buf_out_data_reg[462] ),
        .\write_buffer.wr_buf_out_data_reg[463] (\write_buffer.wr_buf_out_data_reg[463] ),
        .\write_buffer.wr_buf_out_data_reg[465] (\write_buffer.wr_buf_out_data_reg[465] ),
        .\write_buffer.wr_buf_out_data_reg[466] (\write_buffer.wr_buf_out_data_reg[466] ),
        .\write_buffer.wr_buf_out_data_reg[467] (\write_buffer.wr_buf_out_data_reg[467] ),
        .\write_buffer.wr_buf_out_data_reg[469] (\write_buffer.wr_buf_out_data_reg[469] ),
        .\write_buffer.wr_buf_out_data_reg[470] (\write_buffer.wr_buf_out_data_reg[470] ),
        .\write_buffer.wr_buf_out_data_reg[471] (\write_buffer.wr_buf_out_data_reg[471] ),
        .\write_buffer.wr_buf_out_data_reg[473] (\write_buffer.wr_buf_out_data_reg[473] ),
        .\write_buffer.wr_buf_out_data_reg[474] (\write_buffer.wr_buf_out_data_reg[474] ),
        .\write_buffer.wr_buf_out_data_reg[475] (\write_buffer.wr_buf_out_data_reg[475] ),
        .\write_buffer.wr_buf_out_data_reg[477] (\write_buffer.wr_buf_out_data_reg[477] ),
        .\write_buffer.wr_buf_out_data_reg[478] (\write_buffer.wr_buf_out_data_reg[478] ),
        .\write_buffer.wr_buf_out_data_reg[479] (\write_buffer.wr_buf_out_data_reg[479] ),
        .\write_buffer.wr_buf_out_data_reg[489] (\write_buffer.wr_buf_out_data_reg[489] ),
        .\write_buffer.wr_buf_out_data_reg[490] (\write_buffer.wr_buf_out_data_reg[490] ),
        .\write_buffer.wr_buf_out_data_reg[491] (\write_buffer.wr_buf_out_data_reg[491] ),
        .\write_buffer.wr_buf_out_data_reg[493] (\write_buffer.wr_buf_out_data_reg[493] ),
        .\write_buffer.wr_buf_out_data_reg[494] (\write_buffer.wr_buf_out_data_reg[494] ),
        .\write_buffer.wr_buf_out_data_reg[495] (\write_buffer.wr_buf_out_data_reg[495] ),
        .\write_buffer.wr_buf_out_data_reg[497] (\write_buffer.wr_buf_out_data_reg[497] ),
        .\write_buffer.wr_buf_out_data_reg[498] (\write_buffer.wr_buf_out_data_reg[498] ),
        .\write_buffer.wr_buf_out_data_reg[499] (\write_buffer.wr_buf_out_data_reg[499] ),
        .\write_buffer.wr_buf_out_data_reg[501] (\write_buffer.wr_buf_out_data_reg[501] ),
        .\write_buffer.wr_buf_out_data_reg[502] (\write_buffer.wr_buf_out_data_reg[502] ),
        .\write_buffer.wr_buf_out_data_reg[503] (\write_buffer.wr_buf_out_data_reg[503] ),
        .\write_buffer.wr_buf_out_data_reg[505] (\write_buffer.wr_buf_out_data_reg[505] ),
        .\write_buffer.wr_buf_out_data_reg[506] (\write_buffer.wr_buf_out_data_reg[506] ),
        .\write_buffer.wr_buf_out_data_reg[507] (\write_buffer.wr_buf_out_data_reg[507] ),
        .\write_buffer.wr_buf_out_data_reg[509] (\write_buffer.wr_buf_out_data_reg[509] ),
        .\write_buffer.wr_buf_out_data_reg[510] (\write_buffer.wr_buf_out_data_reg[510] ),
        .\write_buffer.wr_buf_out_data_reg[511] (\write_buffer.wr_buf_out_data_reg[511] ),
        .\write_buffer.wr_buf_out_data_reg[571] (\write_buffer.wr_buf_out_data_reg[571] ),
        .write_calib(write_calib));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_ras_n_obuf
       (.I(out_ras_n),
        .O(ddr3_ras_n));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_we_n_obuf
       (.I(out_we_n),
        .O(ddr3_we_n));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo
   (\my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    wr_en_9,
    phy_dout,
    calib_cmd_wren,
    rstdiv0_sync_r1_reg_rep__24,
    rstdiv0_sync_r1_reg_rep__0,
    CLK,
    calib_ctl_wren_reg,
    init_calib_complete_reg_rep__14,
    rstdiv0_sync_r1_reg_rep);
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  input wr_en_9;
  input [0:0]phy_dout;
  input calib_cmd_wren;
  input rstdiv0_sync_r1_reg_rep__24;
  input rstdiv0_sync_r1_reg_rep__0;
  input CLK;
  input [0:0]calib_ctl_wren_reg;
  input init_calib_complete_reg_rep__14;
  input rstdiv0_sync_r1_reg_rep;

  wire CLK;
  wire calib_cmd_wren;
  wire [0:0]calib_ctl_wren_reg;
  wire init_calib_complete_reg_rep__14;
  wire my_empty0;
  wire \my_empty[2]_i_1__4_n_0 ;
  wire \my_empty[3]_i_1__4_n_0 ;
  wire \my_empty[4]_i_1__4_n_0 ;
  wire \my_empty[5]_i_1__1_n_0 ;
  wire \my_empty[6]_i_1__1_n_0 ;
  wire \my_empty[8]_i_1__1_n_0 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg_n_0_[4] ;
  wire \my_empty_reg_n_0_[6] ;
  wire \my_full[0]_i_1__9_n_0 ;
  wire \my_full[3]_i_1__4_n_0 ;
  wire \my_full[5]_i_1__1_n_0 ;
  wire \my_full_reg_n_0_[0] ;
  wire \my_full_reg_n_0_[3] ;
  wire \my_full_reg_n_0_[5] ;
  wire p_1_in;
  wire p_3_in;
  wire [0:0]phy_dout;
  wire [2:0]rd_ptr;
  wire [2:0]rd_ptr0;
  wire \rd_ptr[2]_i_1__1_n_0 ;
  (* MAX_FANOUT = "0'b" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__24;
  (* MAX_FANOUT = "0'b" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en_9;
  wire [2:0]wr_ptr;
  wire [2:0]wr_ptr0;
  wire [2:0]wr_ptr_timing;

  LUT5 #(
    .INIT(32'hCCCCCCCE)) 
    \my_empty[2]_i_1__4 
       (.I0(my_empty0),
        .I1(p_1_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[3] ),
        .O(\my_empty[2]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[3]_i_1__4 
       (.I0(my_empty0),
        .I1(p_1_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[3] ),
        .I5(\my_empty_reg[3]_0 ),
        .O(\my_empty[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[4]_i_1__4 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg_n_0_[4] ),
        .O(\my_empty[4]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[5]_i_1__1 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg[5]_0 ),
        .O(\my_empty[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[6]_i_1__1 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hCCCCCCCE)) 
    \my_empty[8]_i_1__1 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .O(\my_empty[8]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    \my_empty[8]_i_2__1 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__4_n_0 ),
        .Q(p_1_in),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__4_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__4_n_0 ),
        .Q(\my_empty_reg_n_0_[4] ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[5]_i_1__1_n_0 ),
        .Q(\my_empty_reg[5]_0 ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[6]_i_1__1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[8]_i_1__1_n_0 ),
        .Q(p_3_in),
        .S(rstdiv0_sync_r1_reg_rep));
  LUT5 #(
    .INIT(32'h0000AAA8)) 
    \my_full[0]_i_1__9 
       (.I0(\my_full_reg_n_0_[0] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_empty_reg_n_0_[6] ),
        .I4(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[0]_i_1__9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAA8AA)) 
    \my_full[3]_i_1__4 
       (.I0(\my_full_reg_n_0_[3] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAA8AA)) 
    \my_full[5]_i_1__1 
       (.I0(\my_full_reg_n_0_[5] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[5]_i_1__1_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__9_n_0 ),
        .Q(\my_full_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__4_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \my_full_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[5]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[5] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[0]_i_1 
       (.I0(rd_ptr[0]),
        .O(rd_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(rd_ptr0[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[2]_i_1__1 
       (.I0(\my_empty_reg_n_0_[4] ),
        .O(\rd_ptr[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_ptr[2]_i_2 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[2]),
        .O(rd_ptr0[2]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__1_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__1_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__1_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__1_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr_timing[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__1_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr_timing[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__1_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr_timing[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[0]),
        .O(wr_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .O(wr_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \wr_ptr[2]_i_2 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[2]),
        .O(wr_ptr0[2]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[0]),
        .Q(wr_ptr[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[1]),
        .Q(wr_ptr[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[2]),
        .Q(wr_ptr[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[0]),
        .Q(wr_ptr_timing[0]),
        .R(rstdiv0_sync_r1_reg_rep));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[1]),
        .Q(wr_ptr_timing[1]),
        .R(rstdiv0_sync_r1_reg_rep));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[2]),
        .Q(wr_ptr_timing[2]),
        .R(rstdiv0_sync_r1_reg_rep));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0
   (\my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    wr_en_8,
    phy_dout,
    calib_cmd_wren,
    rstdiv0_sync_r1_reg_rep__24,
    rstdiv0_sync_r1_reg_rep__0,
    CLK,
    calib_ctl_wren_reg,
    init_calib_complete_reg_rep__14,
    rstdiv0_sync_r1_reg_rep);
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  input wr_en_8;
  input [0:0]phy_dout;
  input calib_cmd_wren;
  input rstdiv0_sync_r1_reg_rep__24;
  input rstdiv0_sync_r1_reg_rep__0;
  input CLK;
  input [0:0]calib_ctl_wren_reg;
  input init_calib_complete_reg_rep__14;
  input rstdiv0_sync_r1_reg_rep;

  wire CLK;
  wire calib_cmd_wren;
  wire [0:0]calib_ctl_wren_reg;
  wire init_calib_complete_reg_rep__14;
  wire my_empty0;
  wire \my_empty[2]_i_1__3_n_0 ;
  wire \my_empty[3]_i_1__3_n_0 ;
  wire \my_empty[4]_i_1__3_n_0 ;
  wire \my_empty[5]_i_1__0_n_0 ;
  wire \my_empty[6]_i_1__0_n_0 ;
  wire \my_empty[8]_i_1__0_n_0 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg_n_0_[4] ;
  wire \my_empty_reg_n_0_[6] ;
  wire \my_full[0]_i_1__8_n_0 ;
  wire \my_full[3]_i_1__3_n_0 ;
  wire \my_full[5]_i_1__0_n_0 ;
  wire \my_full_reg_n_0_[0] ;
  wire \my_full_reg_n_0_[3] ;
  wire \my_full_reg_n_0_[5] ;
  wire p_1_in;
  wire p_3_in;
  wire [0:0]phy_dout;
  wire [2:0]rd_ptr;
  wire [2:0]rd_ptr0;
  wire \rd_ptr[2]_i_1__0_n_0 ;
  (* MAX_FANOUT = "0'b" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__24;
  (* MAX_FANOUT = "0'b" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en_8;
  wire [2:0]wr_ptr;
  wire [2:0]wr_ptr0;
  wire [2:0]wr_ptr_timing;

  LUT5 #(
    .INIT(32'hCCCCCCCE)) 
    \my_empty[2]_i_1__3 
       (.I0(my_empty0),
        .I1(p_1_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[3] ),
        .O(\my_empty[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[3]_i_1__3 
       (.I0(my_empty0),
        .I1(p_1_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[3] ),
        .I5(\my_empty_reg[3]_0 ),
        .O(\my_empty[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[4]_i_1__3 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg_n_0_[4] ),
        .O(\my_empty[4]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[5]_i_1__0 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg[5]_0 ),
        .O(\my_empty[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[6]_i_1__0 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hCCCCCCCE)) 
    \my_empty[8]_i_1__0 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .O(\my_empty[8]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    \my_empty[8]_i_2__0 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__3_n_0 ),
        .Q(p_1_in),
        .S(rstdiv0_sync_r1_reg_rep__0));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__3_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(rstdiv0_sync_r1_reg_rep__0));
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__3_n_0 ),
        .Q(\my_empty_reg_n_0_[4] ),
        .S(rstdiv0_sync_r1_reg_rep__0));
  FDSE \my_empty_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[5]_i_1__0_n_0 ),
        .Q(\my_empty_reg[5]_0 ),
        .S(rstdiv0_sync_r1_reg_rep__0));
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[6]_i_1__0_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(rstdiv0_sync_r1_reg_rep__0));
  FDSE \my_empty_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[8]_i_1__0_n_0 ),
        .Q(p_3_in),
        .S(rstdiv0_sync_r1_reg_rep__0));
  LUT5 #(
    .INIT(32'h0000AAA8)) 
    \my_full[0]_i_1__8 
       (.I0(\my_full_reg_n_0_[0] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_empty_reg_n_0_[6] ),
        .I4(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[0]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAA8AA)) 
    \my_full[3]_i_1__3 
       (.I0(\my_full_reg_n_0_[3] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAA8AA)) 
    \my_full[5]_i_1__0 
       (.I0(\my_full_reg_n_0_[5] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[5]_i_1__0_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__8_n_0 ),
        .Q(\my_full_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__3_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \my_full_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[5]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[5] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[0]_i_1 
       (.I0(rd_ptr[0]),
        .O(rd_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(rd_ptr0[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[2]_i_1__0 
       (.I0(\my_empty_reg_n_0_[4] ),
        .O(\rd_ptr[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_ptr[2]_i_2 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[2]),
        .O(rd_ptr0[2]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__0_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__0_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__0_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__0_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr_timing[0]),
        .R(rstdiv0_sync_r1_reg_rep));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__0_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr_timing[1]),
        .R(rstdiv0_sync_r1_reg_rep));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1__0_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr_timing[2]),
        .R(rstdiv0_sync_r1_reg_rep));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[0]),
        .O(wr_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .O(wr_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \wr_ptr[2]_i_2 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[2]),
        .O(wr_ptr0[2]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[0]),
        .Q(wr_ptr[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[1]),
        .Q(wr_ptr[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[2]),
        .Q(wr_ptr[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[0]),
        .Q(wr_ptr_timing[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[1]),
        .Q(wr_ptr_timing[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(calib_ctl_wren_reg),
        .D(wr_ptr0[2]),
        .Q(wr_ptr_timing[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1
   (\my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    wr_en_7,
    phy_dout,
    calib_cmd_wren,
    rstdiv0_sync_r1_reg_rep__24,
    rstdiv0_sync_r1_reg_rep__0,
    CLK,
    E,
    init_calib_complete_reg_rep__14,
    rstdiv0_sync_r1_reg_rep);
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  input wr_en_7;
  input [0:0]phy_dout;
  input calib_cmd_wren;
  input rstdiv0_sync_r1_reg_rep__24;
  input rstdiv0_sync_r1_reg_rep__0;
  input CLK;
  input [0:0]E;
  input init_calib_complete_reg_rep__14;
  input rstdiv0_sync_r1_reg_rep;

  wire CLK;
  wire [0:0]E;
  wire calib_cmd_wren;
  wire init_calib_complete_reg_rep__14;
  wire my_empty0;
  wire \my_empty[2]_i_1__2_n_0 ;
  wire \my_empty[3]_i_1__2_n_0 ;
  wire \my_empty[4]_i_1__2_n_0 ;
  wire \my_empty[5]_i_1_n_0 ;
  wire \my_empty[6]_i_1_n_0 ;
  wire \my_empty[8]_i_1_n_0 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg_n_0_[4] ;
  wire \my_empty_reg_n_0_[6] ;
  wire \my_full[0]_i_1__7_n_0 ;
  wire \my_full[3]_i_1__2_n_0 ;
  wire \my_full[5]_i_1_n_0 ;
  wire \my_full_reg_n_0_[0] ;
  wire \my_full_reg_n_0_[3] ;
  wire \my_full_reg_n_0_[5] ;
  wire p_1_in;
  wire p_3_in;
  wire [0:0]phy_dout;
  wire [2:0]rd_ptr;
  wire [2:0]rd_ptr0;
  wire \rd_ptr[2]_i_1_n_0 ;
  (* MAX_FANOUT = "0'b" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__24;
  (* MAX_FANOUT = "0'b" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en_7;
  wire [2:0]wr_ptr;
  wire [2:0]wr_ptr0;
  wire [2:0]wr_ptr_timing;

  LUT5 #(
    .INIT(32'hCCCCCCCE)) 
    \my_empty[2]_i_1__2 
       (.I0(my_empty0),
        .I1(p_1_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[3] ),
        .O(\my_empty[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[3]_i_1__2 
       (.I0(my_empty0),
        .I1(p_1_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[3] ),
        .I5(\my_empty_reg[3]_0 ),
        .O(\my_empty[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[4]_i_1__2 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg_n_0_[4] ),
        .O(\my_empty[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[5]_i_1 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg[5]_0 ),
        .O(\my_empty[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000002)) 
    \my_empty[6]_i_1 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .I5(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hCCCCCCCE)) 
    \my_empty[8]_i_1 
       (.I0(my_empty0),
        .I1(p_3_in),
        .I2(init_calib_complete_reg_rep__14),
        .I3(calib_cmd_wren),
        .I4(\my_full_reg_n_0_[5] ),
        .O(\my_empty[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    \my_empty[8]_i_2 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__2_n_0 ),
        .Q(p_1_in),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__2_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_i_1__2_n_0 ),
        .Q(\my_empty_reg_n_0_[4] ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[5]_i_1_n_0 ),
        .Q(\my_empty_reg[5]_0 ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[6]_i_1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(rstdiv0_sync_r1_reg_rep));
  FDSE \my_empty_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[8]_i_1_n_0 ),
        .Q(p_3_in),
        .S(rstdiv0_sync_r1_reg_rep));
  LUT5 #(
    .INIT(32'h0000AAA8)) 
    \my_full[0]_i_1__7 
       (.I0(\my_full_reg_n_0_[0] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_empty_reg_n_0_[6] ),
        .I4(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[0]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAA8AA)) 
    \my_full[3]_i_1__2 
       (.I0(\my_full_reg_n_0_[3] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAA8AA)) 
    \my_full[5]_i_1 
       (.I0(\my_full_reg_n_0_[5] ),
        .I1(phy_dout),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(rstdiv0_sync_r1_reg_rep__24),
        .O(\my_full[5]_i_1_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__7_n_0 ),
        .Q(\my_full_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__2_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \my_full_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[5]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[5] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[0]_i_1 
       (.I0(rd_ptr[0]),
        .O(rd_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(rd_ptr0[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[2]_i_1 
       (.I0(\my_empty_reg_n_0_[4] ),
        .O(\rd_ptr[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_ptr[2]_i_2 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[2]),
        .O(rd_ptr0[2]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr_timing[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr_timing[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr[2]_i_1_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr_timing[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[0]),
        .O(wr_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .O(wr_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \wr_ptr[2]_i_2 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[2]),
        .O(wr_ptr0[2]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[0]),
        .Q(wr_ptr[0]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[1]),
        .Q(wr_ptr[1]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[2]),
        .Q(wr_ptr[2]),
        .R(rstdiv0_sync_r1_reg_rep__0));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[0]),
        .Q(wr_ptr_timing[0]),
        .R(rstdiv0_sync_r1_reg_rep));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[1]),
        .Q(wr_ptr_timing[1]),
        .R(rstdiv0_sync_r1_reg_rep));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[2]),
        .Q(wr_ptr_timing[2]),
        .R(rstdiv0_sync_r1_reg_rep));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized10
   (\my_empty_reg[7]_0 ,
    \my_empty_reg[1]_0 ,
    wr_en_13,
    \entry_cnt_reg[4]_0 ,
    ofs_rdy_r_reg,
    of_wren_pre,
    D0,
    Q,
    \my_empty_reg[7]_1 ,
    CLK,
    ofifo_rst,
    phy_data_wr_en,
    ofifo_rst_reg,
    calib_wrdata_en,
    init_calib_complete_reg_rep__9,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    init_calib_complete_reg_rep__11,
    \rd_ptr_reg_rep[3]_0 );
  output \my_empty_reg[7]_0 ;
  output \my_empty_reg[1]_0 ;
  output wr_en_13;
  output [0:0]\entry_cnt_reg[4]_0 ;
  output ofs_rdy_r_reg;
  output of_wren_pre;
  output [7:0]D0;
  output [3:0]Q;
  output [3:0]\my_empty_reg[7]_1 ;
  input CLK;
  input ofifo_rst;
  input phy_data_wr_en;
  input ofifo_rst_reg;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__9;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_wrdata_en_reg ;
  input init_calib_complete_reg_rep__11;
  input [7:0]\rd_ptr_reg_rep[3]_0 ;

  wire CLK;
  wire [7:0]D0;
  wire [3:0]Q;
  wire calib_wrdata_en;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire \entry_cnt[0]_i_1__5_n_0 ;
  wire \entry_cnt[1]_i_1__0_n_0 ;
  wire \entry_cnt[2]_i_1__5_n_0 ;
  wire \entry_cnt[3]_i_1__5_n_0 ;
  wire \entry_cnt[4]_i_1__5_n_0 ;
  wire \entry_cnt[4]_i_2__0_n_0 ;
  wire [3:0]entry_cnt_reg;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire init_calib_complete_reg_rep__11;
  wire init_calib_complete_reg_rep__9;
  wire mc_wrdata_en;
  wire \my_empty[1]_i_1__8_n_0 ;
  wire \my_empty[1]_i_2__12_n_0 ;
  wire \my_empty[7]_i_1__5_n_0 ;
  wire \my_empty[7]_i_2__5_n_0 ;
  wire \my_empty[7]_i_3__5_n_0 ;
  wire \my_empty[7]_i_4__4_n_0 ;
  wire \my_empty[7]_i_5__5_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1__5_n_0 ;
  wire \my_full[4]_i_2__5_n_0 ;
  wire \my_full[4]_i_3__5_n_0 ;
  wire \my_full[4]_i_4__5_n_0 ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire ofs_rdy_r_reg;
  wire phy_data_wr_en;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [7:0]\rd_ptr_reg_rep[3]_0 ;
  wire \rd_ptr_rep[3]_i_1__8_n_0 ;
  wire [3:0]rd_ptr_timing;
  wire wr_en_13;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;

  (* SOFT_HLUTNM = "soft_lutpair724" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__5 
       (.I0(entry_cnt_reg[0]),
        .O(\entry_cnt[0]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair724" *) 
  LUT5 #(
    .INIT(32'h9AAA6555)) 
    \entry_cnt[1]_i_1__0 
       (.I0(entry_cnt_reg[0]),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(phy_data_wr_en),
        .I4(entry_cnt_reg[1]),
        .O(\entry_cnt[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1__5 
       (.I0(entry_cnt_reg[2]),
        .I1(entry_cnt_reg[0]),
        .I2(entry_cnt_reg[1]),
        .I3(phy_data_wr_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[7]_0 ),
        .O(\entry_cnt[2]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair725" *) 
  LUT5 #(
    .INIT(32'hCCC96CCC)) 
    \entry_cnt[3]_i_1__5 
       (.I0(entry_cnt_reg[2]),
        .I1(entry_cnt_reg[3]),
        .I2(entry_cnt_reg[0]),
        .I3(entry_cnt_reg[1]),
        .I4(\cmd_pipe_plus.mc_wrdata_en_reg ),
        .O(\entry_cnt[3]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h3030300505053005)) 
    \entry_cnt[4]_i_1__5 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(calib_wrdata_en),
        .I4(init_calib_complete_reg_rep__9),
        .I5(mc_wrdata_en),
        .O(\entry_cnt[4]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0E178F0F0F0)) 
    \entry_cnt[4]_i_2__0 
       (.I0(entry_cnt_reg[3]),
        .I1(entry_cnt_reg[2]),
        .I2(\entry_cnt_reg[4]_0 ),
        .I3(entry_cnt_reg[0]),
        .I4(entry_cnt_reg[1]),
        .I5(\cmd_pipe_plus.mc_wrdata_en_reg ),
        .O(\entry_cnt[4]_i_2__0_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[0]_i_1__5_n_0 ),
        .Q(entry_cnt_reg[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[1]_i_1__0_n_0 ),
        .Q(entry_cnt_reg[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[2]_i_1__5_n_0 ),
        .Q(entry_cnt_reg[2]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[3]_i_1__5_n_0 ),
        .Q(entry_cnt_reg[3]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[4]_i_2__0_n_0 ),
        .Q(\entry_cnt_reg[4]_0 ),
        .R(ofifo_rst));
  LUT6 #(
    .INIT(64'h3535350000003500)) 
    mem_reg_0_15_0_5_i_1__8
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(calib_wrdata_en),
        .I4(init_calib_complete_reg_rep__9),
        .I5(mc_wrdata_en),
        .O(wr_en_13));
  LUT6 #(
    .INIT(64'h0000B80000000047)) 
    \my_empty[1]_i_1__8 
       (.I0(mc_wrdata_en),
        .I1(init_calib_complete_reg_rep__9),
        .I2(calib_wrdata_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[7]_0 ),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__8_n_0 ));
  LUT5 #(
    .INIT(32'hAA2AAAAA)) 
    \my_empty[1]_i_2__12 
       (.I0(\my_empty[7]_i_3__5_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_empty_reg[7]_0 ),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__12_n_0 ));
  LUT6 #(
    .INIT(64'h0000B80000000047)) 
    \my_empty[7]_i_1__5 
       (.I0(mc_wrdata_en),
        .I1(init_calib_complete_reg_rep__9),
        .I2(calib_wrdata_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[7]_0 ),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hAA2AAAAA)) 
    \my_empty[7]_i_2__5 
       (.I0(\my_empty[7]_i_3__5_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_empty_reg[7]_0 ),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3__5 
       (.I0(\my_empty[7]_i_4__4_n_0 ),
        .I1(\my_empty[7]_i_5__5_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair727" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_4__4 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair727" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_5__5 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_5__5_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__8_n_0 ),
        .D(\my_empty[1]_i_2__12_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1__5_n_0 ),
        .D(\my_empty[7]_i_2__5_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h3302330033003000)) 
    \my_full[4]_i_1__5 
       (.I0(\my_full[4]_i_2__5_n_0 ),
        .I1(ofifo_rst),
        .I2(\my_empty_reg_n_0_[7] ),
        .I3(\my_empty_reg[7]_0 ),
        .I4(phy_data_wr_en),
        .I5(ofifo_rst_reg),
        .O(\my_full[4]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2__5 
       (.I0(\my_full[4]_i_3__5_n_0 ),
        .I1(\my_full[4]_i_4__5_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(Q[2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair726" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3__5 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\my_full[4]_i_3__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair726" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4__5 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4__5_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__5_n_0 ),
        .Q(\my_empty_reg[7]_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair725" *) 
  LUT2 #(
    .INIT(4'hE)) 
    ofs_rdy_r_i_4
       (.I0(entry_cnt_reg[2]),
        .I1(entry_cnt_reg[3]),
        .O(ofs_rdy_r_reg));
  LUT5 #(
    .INIT(32'h31333111)) 
    out_fifo_i_1__6
       (.I0(\my_empty_reg[1]_0 ),
        .I1(ofifo_rst_reg),
        .I2(mc_wrdata_en),
        .I3(init_calib_complete_reg_rep__11),
        .I4(calib_wrdata_en),
        .O(of_wren_pre));
  (* SOFT_HLUTNM = "soft_lutpair732" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__7
       (.I0(\rd_ptr_reg_rep[3]_0 [7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair733" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__7
       (.I0(\rd_ptr_reg_rep[3]_0 [6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair734" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__7
       (.I0(\rd_ptr_reg_rep[3]_0 [5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair734" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__7
       (.I0(\rd_ptr_reg_rep[3]_0 [4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair735" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__7
       (.I0(\rd_ptr_reg_rep[3]_0 [3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair732" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__7
       (.I0(\rd_ptr_reg_rep[3]_0 [2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair735" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__7
       (.I0(\rd_ptr_reg_rep[3]_0 [1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair733" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__7
       (.I0(\rd_ptr_reg_rep[3]_0 [0]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\my_empty_reg[7]_1 [0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\my_empty_reg[7]_1 [1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\my_empty_reg[7]_1 [2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\my_empty_reg[7]_1 [3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair731" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__8 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair731" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__8 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair729" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__8 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__8 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(ofifo_rst_reg),
        .O(\rd_ptr_rep[3]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair729" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__8 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__8_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair730" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__16 
       (.I0(Q[3]),
        .I1(Q[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair730" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__16 
       (.I0(Q[1]),
        .I1(Q[3]),
        .I2(Q[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair728" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__8 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h3535350000003500)) 
    \wr_ptr[3]_i_1__8 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(calib_wrdata_en),
        .I4(init_calib_complete_reg_rep__9),
        .I5(mc_wrdata_en),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair728" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__8 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(Q[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(Q[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized11
   (\my_empty_reg[7]_0 ,
    \my_empty_reg[1]_0 ,
    wr_en_14,
    ofs_rdy_r_reg,
    of_wren_pre,
    D0,
    Q,
    \my_empty_reg[7]_1 ,
    CLK,
    ofifo_rst,
    phy_data_wr_en,
    ofifo_rst_reg,
    calib_wrdata_en,
    init_calib_complete_reg_rep__9,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    init_calib_complete_reg_rep__12,
    \rd_ptr_reg_rep[3]_0 );
  output \my_empty_reg[7]_0 ;
  output \my_empty_reg[1]_0 ;
  output wr_en_14;
  output ofs_rdy_r_reg;
  output of_wren_pre;
  output [7:0]D0;
  output [3:0]Q;
  output [3:0]\my_empty_reg[7]_1 ;
  input CLK;
  input ofifo_rst;
  input phy_data_wr_en;
  input ofifo_rst_reg;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__9;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_wrdata_en_reg ;
  input init_calib_complete_reg_rep__12;
  input [7:0]\rd_ptr_reg_rep[3]_0 ;

  wire CLK;
  wire [7:0]D0;
  wire [3:0]Q;
  wire calib_wrdata_en;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire \entry_cnt[0]_i_1__6_n_0 ;
  wire \entry_cnt[1]_i_1__1_n_0 ;
  wire \entry_cnt[2]_i_1__6_n_0 ;
  wire \entry_cnt[3]_i_1__6_n_0 ;
  wire \entry_cnt[4]_i_1__6_n_0 ;
  wire \entry_cnt[4]_i_2__1_n_0 ;
  wire [4:0]entry_cnt_reg;
  wire init_calib_complete_reg_rep__12;
  wire init_calib_complete_reg_rep__9;
  wire mc_wrdata_en;
  wire \my_empty[1]_i_1__9_n_0 ;
  wire \my_empty[1]_i_2__13_n_0 ;
  wire \my_empty[7]_i_1__6_n_0 ;
  wire \my_empty[7]_i_2__6_n_0 ;
  wire \my_empty[7]_i_3__6_n_0 ;
  wire \my_empty[7]_i_4__5_n_0 ;
  wire \my_empty[7]_i_5__6_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1__6_n_0 ;
  wire \my_full[4]_i_2__6_n_0 ;
  wire \my_full[4]_i_3__6_n_0 ;
  wire \my_full[4]_i_4__6_n_0 ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire ofs_rdy_r_reg;
  wire phy_data_wr_en;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [7:0]\rd_ptr_reg_rep[3]_0 ;
  wire \rd_ptr_rep[3]_i_1__9_n_0 ;
  wire [3:0]rd_ptr_timing;
  wire wr_en_14;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;

  (* SOFT_HLUTNM = "soft_lutpair739" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__6 
       (.I0(entry_cnt_reg[0]),
        .O(\entry_cnt[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h9AAA6555)) 
    \entry_cnt[1]_i_1__1 
       (.I0(entry_cnt_reg[0]),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(phy_data_wr_en),
        .I4(entry_cnt_reg[1]),
        .O(\entry_cnt[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1__6 
       (.I0(entry_cnt_reg[2]),
        .I1(entry_cnt_reg[0]),
        .I2(entry_cnt_reg[1]),
        .I3(phy_data_wr_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[7]_0 ),
        .O(\entry_cnt[2]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair739" *) 
  LUT5 #(
    .INIT(32'hCCC96CCC)) 
    \entry_cnt[3]_i_1__6 
       (.I0(entry_cnt_reg[2]),
        .I1(entry_cnt_reg[3]),
        .I2(entry_cnt_reg[0]),
        .I3(entry_cnt_reg[1]),
        .I4(\cmd_pipe_plus.mc_wrdata_en_reg ),
        .O(\entry_cnt[3]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h3030300505053005)) 
    \entry_cnt[4]_i_1__6 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(calib_wrdata_en),
        .I4(init_calib_complete_reg_rep__9),
        .I5(mc_wrdata_en),
        .O(\entry_cnt[4]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0E178F0F0F0)) 
    \entry_cnt[4]_i_2__1 
       (.I0(entry_cnt_reg[3]),
        .I1(entry_cnt_reg[2]),
        .I2(entry_cnt_reg[4]),
        .I3(entry_cnt_reg[0]),
        .I4(entry_cnt_reg[1]),
        .I5(\cmd_pipe_plus.mc_wrdata_en_reg ),
        .O(\entry_cnt[4]_i_2__1_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[0]_i_1__6_n_0 ),
        .Q(entry_cnt_reg[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[1]_i_1__1_n_0 ),
        .Q(entry_cnt_reg[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[2]_i_1__6_n_0 ),
        .Q(entry_cnt_reg[2]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[3]_i_1__6_n_0 ),
        .Q(entry_cnt_reg[3]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[4]_i_2__1_n_0 ),
        .Q(entry_cnt_reg[4]),
        .R(ofifo_rst));
  LUT6 #(
    .INIT(64'h3535350000003500)) 
    mem_reg_0_15_0_5_i_1__9
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(calib_wrdata_en),
        .I4(init_calib_complete_reg_rep__9),
        .I5(mc_wrdata_en),
        .O(wr_en_14));
  LUT6 #(
    .INIT(64'h0000B80000000047)) 
    \my_empty[1]_i_1__9 
       (.I0(mc_wrdata_en),
        .I1(init_calib_complete_reg_rep__9),
        .I2(calib_wrdata_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[7]_0 ),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'hAA2AAAAA)) 
    \my_empty[1]_i_2__13 
       (.I0(\my_empty[7]_i_3__6_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_empty_reg[7]_0 ),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__13_n_0 ));
  LUT6 #(
    .INIT(64'h0000B80000000047)) 
    \my_empty[7]_i_1__6 
       (.I0(mc_wrdata_en),
        .I1(init_calib_complete_reg_rep__9),
        .I2(calib_wrdata_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[7]_0 ),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hAA2AAAAA)) 
    \my_empty[7]_i_2__6 
       (.I0(\my_empty[7]_i_3__6_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_empty_reg[7]_0 ),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3__6 
       (.I0(\my_empty[7]_i_4__5_n_0 ),
        .I1(\my_empty[7]_i_5__6_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair741" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_4__5 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair741" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_5__6 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_5__6_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__9_n_0 ),
        .D(\my_empty[1]_i_2__13_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1__6_n_0 ),
        .D(\my_empty[7]_i_2__6_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h3302330033003000)) 
    \my_full[4]_i_1__6 
       (.I0(\my_full[4]_i_2__6_n_0 ),
        .I1(ofifo_rst),
        .I2(\my_empty_reg_n_0_[7] ),
        .I3(\my_empty_reg[7]_0 ),
        .I4(phy_data_wr_en),
        .I5(ofifo_rst_reg),
        .O(\my_full[4]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2__6 
       (.I0(\my_full[4]_i_3__6_n_0 ),
        .I1(\my_full[4]_i_4__6_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(Q[2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair740" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3__6 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\my_full[4]_i_3__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair740" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4__6 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4__6_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__6_n_0 ),
        .Q(\my_empty_reg[7]_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    ofs_rdy_r_i_6
       (.I0(entry_cnt_reg[3]),
        .I1(entry_cnt_reg[2]),
        .I2(entry_cnt_reg[4]),
        .O(ofs_rdy_r_reg));
  LUT5 #(
    .INIT(32'h31333111)) 
    out_fifo_i_1__7
       (.I0(\my_empty_reg[1]_0 ),
        .I1(ofifo_rst_reg),
        .I2(mc_wrdata_en),
        .I3(init_calib_complete_reg_rep__12),
        .I4(calib_wrdata_en),
        .O(of_wren_pre));
  (* SOFT_HLUTNM = "soft_lutpair746" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__8
       (.I0(\rd_ptr_reg_rep[3]_0 [7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair747" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__8
       (.I0(\rd_ptr_reg_rep[3]_0 [6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair748" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__8
       (.I0(\rd_ptr_reg_rep[3]_0 [5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair748" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__8
       (.I0(\rd_ptr_reg_rep[3]_0 [4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair749" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__8
       (.I0(\rd_ptr_reg_rep[3]_0 [3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair747" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__8
       (.I0(\rd_ptr_reg_rep[3]_0 [2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair749" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__8
       (.I0(\rd_ptr_reg_rep[3]_0 [1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair746" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__8
       (.I0(\rd_ptr_reg_rep[3]_0 [0]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\my_empty_reg[7]_1 [0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\my_empty_reg[7]_1 [1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\my_empty_reg[7]_1 [2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\my_empty_reg[7]_1 [3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair745" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__9 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair745" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__9 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair743" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__9 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__9 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(ofifo_rst_reg),
        .O(\rd_ptr_rep[3]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair743" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__9 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__9_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair744" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__17 
       (.I0(Q[3]),
        .I1(Q[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair744" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__17 
       (.I0(Q[1]),
        .I1(Q[3]),
        .I2(Q[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair742" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__9 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h3535350000003500)) 
    \wr_ptr[3]_i_1__9 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(ofifo_rst_reg),
        .I3(calib_wrdata_en),
        .I4(init_calib_complete_reg_rep__9),
        .I5(mc_wrdata_en),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair742" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__9 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(Q[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(Q[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized2
   (\my_empty_reg[1]_0 ,
    wr_en_12,
    Q,
    of_wren_pre,
    D8,
    \wr_ptr_timing_reg[3]_0 ,
    \my_empty_reg[7]_0 ,
    CLK,
    ofifo_rst,
    A_of_data_full,
    phy_data_wr_en,
    calib_wrdata_en,
    init_calib_complete_reg_rep__9,
    mc_wrdata_en,
    \rd_ptr_reg_rep[3]_0 );
  output \my_empty_reg[1]_0 ;
  output wr_en_12;
  output [2:0]Q;
  output of_wren_pre;
  output [7:0]D8;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\my_empty_reg[7]_0 ;
  input CLK;
  input ofifo_rst;
  input A_of_data_full;
  input phy_data_wr_en;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__9;
  input mc_wrdata_en;
  input [7:0]\rd_ptr_reg_rep[3]_0 ;

  wire A_of_data_full;
  wire CLK;
  wire [7:0]D8;
  wire [2:0]Q;
  wire calib_wrdata_en;
  wire \entry_cnt[0]_i_1__4_n_0 ;
  wire \entry_cnt[1]_i_1_n_0 ;
  wire \entry_cnt[2]_i_1__4_n_0 ;
  wire \entry_cnt[3]_i_1__4_n_0 ;
  wire \entry_cnt[4]_i_1__4_n_0 ;
  wire \entry_cnt[4]_i_2_n_0 ;
  wire \entry_cnt[4]_i_3__4_n_0 ;
  wire [1:0]entry_cnt_reg;
  wire init_calib_complete_reg_rep__9;
  wire mc_wrdata_en;
  wire \my_empty[1]_i_1__7_n_0 ;
  wire \my_empty[1]_i_2__11_n_0 ;
  wire \my_empty[7]_i_1__4_n_0 ;
  wire \my_empty[7]_i_2__4_n_0 ;
  wire \my_empty[7]_i_3__4_n_0 ;
  wire \my_empty[7]_i_4__3_n_0 ;
  wire \my_empty[7]_i_5__4_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire [3:0]\my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1__4_n_0 ;
  wire \my_full[4]_i_2__4_n_0 ;
  wire \my_full[4]_i_3__4_n_0 ;
  wire \my_full[4]_i_4__4_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire phy_data_wr_en;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [7:0]\rd_ptr_reg_rep[3]_0 ;
  wire \rd_ptr_rep[3]_i_1__7_n_0 ;
  wire [3:0]rd_ptr_timing;
  wire wr_en_12;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair710" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__4 
       (.I0(entry_cnt_reg[0]),
        .O(\entry_cnt[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h9AAA6555)) 
    \entry_cnt[1]_i_1 
       (.I0(entry_cnt_reg[0]),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(A_of_data_full),
        .I4(entry_cnt_reg[1]),
        .O(\entry_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1__4 
       (.I0(Q[0]),
        .I1(entry_cnt_reg[0]),
        .I2(entry_cnt_reg[1]),
        .I3(A_of_data_full),
        .I4(phy_data_wr_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[2]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair710" *) 
  LUT5 #(
    .INIT(32'hCCC96CCC)) 
    \entry_cnt[3]_i_1__4 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(entry_cnt_reg[0]),
        .I3(entry_cnt_reg[1]),
        .I4(\entry_cnt[4]_i_3__4_n_0 ),
        .O(\entry_cnt[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h3330003000055505)) 
    \entry_cnt[4]_i_1__4 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__9),
        .I4(mc_wrdata_en),
        .I5(A_of_data_full),
        .O(\entry_cnt[4]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0E178F0F0F0)) 
    \entry_cnt[4]_i_2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(entry_cnt_reg[0]),
        .I4(entry_cnt_reg[1]),
        .I5(\entry_cnt[4]_i_3__4_n_0 ),
        .O(\entry_cnt[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF757F)) 
    \entry_cnt[4]_i_3__4 
       (.I0(A_of_data_full),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__9),
        .I3(calib_wrdata_en),
        .I4(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[4]_i_3__4_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[0]_i_1__4_n_0 ),
        .Q(entry_cnt_reg[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[1]_i_1_n_0 ),
        .Q(entry_cnt_reg[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[2]_i_1__4_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[3]_i_1__4_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[4]_i_2_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  LUT6 #(
    .INIT(64'h3330003055500050)) 
    mem_reg_0_15_0_5_i_1__7
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__9),
        .I4(mc_wrdata_en),
        .I5(A_of_data_full),
        .O(wr_en_12));
  LUT6 #(
    .INIT(64'h00008A8000001015)) 
    \my_empty[1]_i_1__7 
       (.I0(A_of_data_full),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__9),
        .I3(calib_wrdata_en),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__7_n_0 ));
  LUT5 #(
    .INIT(32'hAA2AAAAA)) 
    \my_empty[1]_i_2__11 
       (.I0(\my_empty[7]_i_3__4_n_0 ),
        .I1(A_of_data_full),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__11_n_0 ));
  LUT6 #(
    .INIT(64'h00008A8000001015)) 
    \my_empty[7]_i_1__4 
       (.I0(A_of_data_full),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__9),
        .I3(calib_wrdata_en),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hAA2AAAAA)) 
    \my_empty[7]_i_2__4 
       (.I0(\my_empty[7]_i_3__4_n_0 ),
        .I1(A_of_data_full),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3__4 
       (.I0(\my_empty[7]_i_4__3_n_0 ),
        .I1(\my_empty[7]_i_5__4_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair712" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_4__3 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair712" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_5__4 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_5__4_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__7_n_0 ),
        .D(\my_empty[1]_i_2__11_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1__4_n_0 ),
        .D(\my_empty[7]_i_2__4_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h3302330033003000)) 
    \my_full[4]_i_1__4 
       (.I0(\my_full[4]_i_2__4_n_0 ),
        .I1(ofifo_rst),
        .I2(\my_empty_reg_n_0_[7] ),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(A_of_data_full),
        .I5(phy_data_wr_en),
        .O(\my_full[4]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2__4 
       (.I0(\my_full[4]_i_3__4_n_0 ),
        .I1(\my_full[4]_i_4__4_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(\wr_ptr_timing_reg[3]_0 [2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair711" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3__4 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(\wr_ptr_timing_reg[3]_0 [1]),
        .I3(\wr_ptr_timing_reg[3]_0 [0]),
        .I4(\wr_ptr_timing_reg[3]_0 [3]),
        .O(\my_full[4]_i_3__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair711" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4__4 
       (.I0(\wr_ptr_timing_reg[3]_0 [1]),
        .I1(\wr_ptr_timing_reg[3]_0 [0]),
        .I2(\wr_ptr_timing_reg[3]_0 [3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4__4_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__4_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h31333111)) 
    out_fifo_i_1__5
       (.I0(\my_empty_reg[1]_0 ),
        .I1(A_of_data_full),
        .I2(mc_wrdata_en),
        .I3(init_calib_complete_reg_rep__9),
        .I4(calib_wrdata_en),
        .O(of_wren_pre));
  (* SOFT_HLUTNM = "soft_lutpair717" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_66__5
       (.I0(\rd_ptr_reg_rep[3]_0 [7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[7]));
  (* SOFT_HLUTNM = "soft_lutpair718" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_67__5
       (.I0(\rd_ptr_reg_rep[3]_0 [6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[6]));
  (* SOFT_HLUTNM = "soft_lutpair718" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_68__5
       (.I0(\rd_ptr_reg_rep[3]_0 [5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[5]));
  (* SOFT_HLUTNM = "soft_lutpair719" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_69__5
       (.I0(\rd_ptr_reg_rep[3]_0 [4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[4]));
  (* SOFT_HLUTNM = "soft_lutpair719" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_70__5
       (.I0(\rd_ptr_reg_rep[3]_0 [3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair720" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_71__5
       (.I0(\rd_ptr_reg_rep[3]_0 [2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair720" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_72__5
       (.I0(\rd_ptr_reg_rep[3]_0 [1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair717" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_73__5
       (.I0(\rd_ptr_reg_rep[3]_0 [0]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\my_empty_reg[7]_0 [0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\my_empty_reg[7]_0 [1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\my_empty_reg[7]_0 [2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\my_empty_reg[7]_0 [3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair716" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__7 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair716" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__7 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair713" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__7 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__7 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(A_of_data_full),
        .O(\rd_ptr_rep[3]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair713" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__7 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair715" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__15 
       (.I0(\wr_ptr_timing_reg[3]_0 [3]),
        .I1(\wr_ptr_timing_reg[3]_0 [0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair715" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__15 
       (.I0(\wr_ptr_timing_reg[3]_0 [1]),
        .I1(\wr_ptr_timing_reg[3]_0 [3]),
        .I2(\wr_ptr_timing_reg[3]_0 [0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair714" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__7 
       (.I0(\wr_ptr_timing_reg[3]_0 [2]),
        .I1(\wr_ptr_timing_reg[3]_0 [1]),
        .I2(\wr_ptr_timing_reg[3]_0 [0]),
        .I3(\wr_ptr_timing_reg[3]_0 [3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h3330003055500050)) 
    \wr_ptr[3]_i_1__7 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__9),
        .I4(mc_wrdata_en),
        .I5(A_of_data_full),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair714" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__7 
       (.I0(\wr_ptr_timing_reg[3]_0 [2]),
        .I1(\wr_ptr_timing_reg[3]_0 [1]),
        .I2(\wr_ptr_timing_reg[3]_0 [0]),
        .I3(\wr_ptr_timing_reg[3]_0 [3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(\wr_ptr_timing_reg[3]_0 [0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(\wr_ptr_timing_reg[3]_0 [1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(\wr_ptr_timing_reg[3]_0 [2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(\wr_ptr_timing_reg[3]_0 [3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized2_13
   (\my_empty_reg[1]_0 ,
    \entry_cnt_reg[4]_0 ,
    ofs_rdy_r_reg,
    of_wren_pre,
    D9,
    D8,
    D7,
    D6,
    D5,
    D4,
    D3,
    D2,
    D1,
    D0,
    \my_empty_reg[7]_0 ,
    CLK,
    phy_data_wr_en,
    ofifo_rst_reg,
    ofifo_rst,
    \entry_cnt_reg[4]_1 ,
    \entry_cnt_reg[4]_2 ,
    \entry_cnt_reg[4]_3 ,
    \entry_cnt_reg[4]_4 ,
    \entry_cnt_reg[4]_5 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__3,
    mc_wrdata_en,
    \write_buffer.wr_buf_out_data_reg[571] ,
    init_calib_complete_reg_rep__4,
    phy_dout);
  output \my_empty_reg[1]_0 ;
  output [1:0]\entry_cnt_reg[4]_0 ;
  output ofs_rdy_r_reg;
  output of_wren_pre;
  output [7:0]D9;
  output [7:0]D8;
  output [1:0]D7;
  output [1:0]D6;
  output [2:0]D5;
  output [2:0]D4;
  output [1:0]D3;
  output [1:0]D2;
  output [2:0]D1;
  output [2:0]D0;
  output [43:0]\my_empty_reg[7]_0 ;
  input CLK;
  input phy_data_wr_en;
  input ofifo_rst_reg;
  input ofifo_rst;
  input [0:0]\entry_cnt_reg[4]_1 ;
  input [0:0]\entry_cnt_reg[4]_2 ;
  input [0:0]\entry_cnt_reg[4]_3 ;
  input [0:0]\entry_cnt_reg[4]_4 ;
  input [0:0]\entry_cnt_reg[4]_5 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__3;
  input mc_wrdata_en;
  input [27:0]\write_buffer.wr_buf_out_data_reg[571] ;
  input init_calib_complete_reg_rep__4;
  input [71:0]phy_dout;

  wire CLK;
  wire [2:0]D0;
  wire [2:0]D1;
  wire [1:0]D2;
  wire [1:0]D3;
  wire [2:0]D4;
  wire [2:0]D5;
  wire [1:0]D6;
  wire [1:0]D7;
  wire [7:0]D8;
  wire [7:0]D9;
  wire calib_wrdata_en;
  wire \entry_cnt[0]_i_1__0_n_0 ;
  wire \entry_cnt[1]_i_1__3_n_0 ;
  wire \entry_cnt[2]_i_1__0_n_0 ;
  wire \entry_cnt[3]_i_1__0_n_0 ;
  wire \entry_cnt[4]_i_1__0_n_0 ;
  wire \entry_cnt[4]_i_2__3_n_0 ;
  wire \entry_cnt[4]_i_3__0_n_0 ;
  wire [1:0]\entry_cnt_reg[4]_0 ;
  wire [0:0]\entry_cnt_reg[4]_1 ;
  wire [0:0]\entry_cnt_reg[4]_2 ;
  wire [0:0]\entry_cnt_reg[4]_3 ;
  wire [0:0]\entry_cnt_reg[4]_4 ;
  wire [0:0]\entry_cnt_reg[4]_5 ;
  wire [4:0]entry_cnt_reg__0__0;
  wire init_calib_complete_reg_rep__3;
  wire init_calib_complete_reg_rep__4;
  wire mc_wrdata_en;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_18_23_n_1;
  wire mem_reg_0_15_18_23_n_3;
  wire mem_reg_0_15_24_29_n_1;
  wire mem_reg_0_15_30_35_n_0;
  wire mem_reg_0_15_30_35_n_2;
  wire mem_reg_0_15_30_35_n_3;
  wire mem_reg_0_15_36_41_n_0;
  wire mem_reg_0_15_36_41_n_4;
  wire mem_reg_0_15_42_47_n_0;
  wire mem_reg_0_15_42_47_n_3;
  wire mem_reg_0_15_48_53_n_3;
  wire mem_reg_0_15_48_53_n_5;
  wire mem_reg_0_15_54_59_n_3;
  wire mem_reg_0_15_60_65_n_2;
  wire mem_reg_0_15_60_65_n_4;
  wire mem_reg_0_15_60_65_n_5;
  wire mem_reg_0_15_66_71_n_0;
  wire mem_reg_0_15_66_71_n_1;
  wire mem_reg_0_15_66_71_n_2;
  wire mem_reg_0_15_66_71_n_3;
  wire mem_reg_0_15_66_71_n_4;
  wire mem_reg_0_15_66_71_n_5;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_4;
  wire mem_reg_0_15_72_77_n_0;
  wire mem_reg_0_15_72_77_n_1;
  wire mem_reg_0_15_72_77_n_2;
  wire mem_reg_0_15_72_77_n_3;
  wire mem_reg_0_15_72_77_n_4;
  wire mem_reg_0_15_72_77_n_5;
  wire mem_reg_0_15_78_79_n_0;
  wire mem_reg_0_15_78_79_n_1;
  wire \my_empty[1]_i_1__3_n_0 ;
  wire \my_empty[1]_i_2__7_n_0 ;
  wire \my_empty[7]_i_1__0_n_0 ;
  wire \my_empty[7]_i_2__0_n_0 ;
  wire \my_empty[7]_i_3__0_n_0 ;
  wire \my_empty[7]_i_4_n_0 ;
  wire \my_empty[7]_i_5__0_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire [43:0]\my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1__0_n_0 ;
  wire \my_full[4]_i_2__0_n_0 ;
  wire \my_full[4]_i_3__0_n_0 ;
  wire \my_full[4]_i_4__0_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire ofs_rdy_r_reg;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire [3:0]rd_ptr;
  wire rd_ptr0;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[571] ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__0 
       (.I0(entry_cnt_reg__0__0[0]),
        .O(\entry_cnt[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT5 #(
    .INIT(32'hF70808F7)) 
    \entry_cnt[1]_i_1__3 
       (.I0(ofifo_rst_reg),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(entry_cnt_reg__0__0[1]),
        .I4(entry_cnt_reg__0__0[0]),
        .O(\entry_cnt[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1__0 
       (.I0(\entry_cnt_reg[4]_0 [0]),
        .I1(entry_cnt_reg__0__0[1]),
        .I2(entry_cnt_reg__0__0[0]),
        .I3(ofifo_rst_reg),
        .I4(phy_data_wr_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__0 
       (.I0(entry_cnt_reg__0__0[1]),
        .I1(entry_cnt_reg__0__0[0]),
        .I2(\entry_cnt[4]_i_3__0_n_0 ),
        .I3(\entry_cnt_reg[4]_0 [1]),
        .I4(\entry_cnt_reg[4]_0 [0]),
        .O(\entry_cnt[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00011101CCC111C1)) 
    \entry_cnt[4]_i_1__0 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(ofifo_rst_reg),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__3),
        .I4(mc_wrdata_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \entry_cnt[4]_i_2__3 
       (.I0(entry_cnt_reg__0__0[4]),
        .I1(\entry_cnt_reg[4]_0 [1]),
        .I2(entry_cnt_reg__0__0[1]),
        .I3(entry_cnt_reg__0__0[0]),
        .I4(\entry_cnt[4]_i_3__0_n_0 ),
        .I5(\entry_cnt_reg[4]_0 [0]),
        .O(\entry_cnt[4]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h45400000)) 
    \entry_cnt[4]_i_3__0 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__3),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(\entry_cnt[4]_i_3__0_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[0]_i_1__0_n_0 ),
        .Q(entry_cnt_reg__0__0[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[1]_i_1__3_n_0 ),
        .Q(entry_cnt_reg__0__0[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[2]_i_1__0_n_0 ),
        .Q(\entry_cnt_reg[4]_0 [0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[3]_i_1__0_n_0 ),
        .Q(\entry_cnt_reg[4]_0 [1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[4]_i_2__3_n_0 ),
        .Q(entry_cnt_reg__0__0[4]),
        .R(ofifo_rst));
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[1:0]),
        .DIB(phy_dout[3:2]),
        .DIC(phy_dout[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB(\my_empty_reg[7]_0 [1:0]),
        .DOC({mem_reg_0_15_0_5_n_4,\my_empty_reg[7]_0 [2]}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    mem_reg_0_15_0_5_i_1__3
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__3),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg[1]_0 ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_en));
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[13:12]),
        .DIB(phy_dout[15:14]),
        .DIC(phy_dout[17:16]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [7],mem_reg_0_15_12_17_n_1}),
        .DOB(\my_empty_reg[7]_0 [9:8]),
        .DOC(\my_empty_reg[7]_0 [11:10]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[19:18]),
        .DIB(phy_dout[21:20]),
        .DIC(phy_dout[23:22]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [12],mem_reg_0_15_18_23_n_1}),
        .DOB({\my_empty_reg[7]_0 [13],mem_reg_0_15_18_23_n_3}),
        .DOC(\my_empty_reg[7]_0 [15:14]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[25:24]),
        .DIB(phy_dout[27:26]),
        .DIC(phy_dout[29:28]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [16],mem_reg_0_15_24_29_n_1}),
        .DOB(\my_empty_reg[7]_0 [18:17]),
        .DOC(\my_empty_reg[7]_0 [20:19]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[31:30]),
        .DIB(phy_dout[33:32]),
        .DIC(phy_dout[35:34]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_30_35_n_0,\my_empty_reg[7]_0 [21]}),
        .DOB({mem_reg_0_15_30_35_n_2,mem_reg_0_15_30_35_n_3}),
        .DOC(\my_empty_reg[7]_0 [23:22]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[37:36]),
        .DIB(phy_dout[39:38]),
        .DIC(phy_dout[41:40]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_36_41_n_0,\my_empty_reg[7]_0 [24]}),
        .DOB(\my_empty_reg[7]_0 [26:25]),
        .DOC({mem_reg_0_15_36_41_n_4,\my_empty_reg[7]_0 [27]}),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[43:42]),
        .DIB(phy_dout[45:44]),
        .DIC(phy_dout[47:46]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_42_47_n_0,\my_empty_reg[7]_0 [28]}),
        .DOB({\my_empty_reg[7]_0 [29],mem_reg_0_15_42_47_n_3}),
        .DOC(\my_empty_reg[7]_0 [31:30]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[49:48]),
        .DIB(phy_dout[51:50]),
        .DIC(phy_dout[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [33:32]),
        .DOB({\my_empty_reg[7]_0 [34],mem_reg_0_15_48_53_n_3}),
        .DOC({\my_empty_reg[7]_0 [35],mem_reg_0_15_48_53_n_5}),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[55:54]),
        .DIB(phy_dout[57:56]),
        .DIC(phy_dout[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [37:36]),
        .DOB({\my_empty_reg[7]_0 [38],mem_reg_0_15_54_59_n_3}),
        .DOC(\my_empty_reg[7]_0 [40:39]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[61:60]),
        .DIB(phy_dout[63:62]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [42:41]),
        .DOB({mem_reg_0_15_60_65_n_2,\my_empty_reg[7]_0 [43]}),
        .DOC({mem_reg_0_15_60_65_n_4,mem_reg_0_15_60_65_n_5}),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_66_71_n_0,mem_reg_0_15_66_71_n_1}),
        .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}),
        .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[7:6]),
        .DIB(phy_dout[9:8]),
        .DIC(phy_dout[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [4:3]),
        .DOB({mem_reg_0_15_6_11_n_2,\my_empty_reg[7]_0 [5]}),
        .DOC({mem_reg_0_15_6_11_n_4,\my_empty_reg[7]_0 [6]}),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[65:64]),
        .DIB(phy_dout[67:66]),
        .DIC(phy_dout[69:68]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),
        .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),
        .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[1]_i_1__3 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__3),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[1]_i_2__7 
       (.I0(\my_empty[7]_i_3__0_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__7_n_0 ));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[7]_i_1__0 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__3),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[7]_i_2__0 
       (.I0(\my_empty[7]_i_3__0_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3__0 
       (.I0(\my_empty[7]_i_4_n_0 ),
        .I1(\my_empty[7]_i_5__0_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_4 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_5__0 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_5__0_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__3_n_0 ),
        .D(\my_empty[1]_i_2__7_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1__0_n_0 ),
        .D(\my_empty[7]_i_2__0_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[4]_i_1__0 
       (.I0(\my_full[4]_i_2__0_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg_n_0_[7] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2__0 
       (.I0(\my_full[4]_i_3__0_n_0 ),
        .I1(\my_full[4]_i_4__0_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(wr_ptr[2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3__0 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4__0 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4__0_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_7
       (.I0(entry_cnt_reg__0__0[4]),
        .I1(\entry_cnt_reg[4]_1 ),
        .I2(\entry_cnt_reg[4]_2 ),
        .I3(\entry_cnt_reg[4]_3 ),
        .I4(\entry_cnt_reg[4]_4 ),
        .I5(\entry_cnt_reg[4]_5 ),
        .O(ofs_rdy_r_reg));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_13__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [15]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_12_17_n_1),
        .O(D1[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_14__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [11]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_4),
        .O(D1[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16__2
       (.I0(init_calib_complete_reg_rep__4),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [6]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_2),
        .O(D1[0]));
  LUT5 #(
    .INIT(32'h0000DFD5)) 
    out_fifo_i_1__1
       (.I0(\my_empty_reg[1]_0 ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__3),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(of_wren_pre));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_21__2
       (.I0(init_calib_complete_reg_rep__4),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [14]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_3),
        .O(D2[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_23__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [9]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_1),
        .O(D2[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_26__2
       (.I0(init_calib_complete_reg_rep__4),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [19]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_30_35_n_0),
        .O(D3[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_33__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [2]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_24_29_n_1),
        .O(D3[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_36__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [16]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_0),
        .O(D4[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_40__2
       (.I0(init_calib_complete_reg_rep__4),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [5]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_30_35_n_2),
        .O(D4[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [1]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_30_35_n_3),
        .O(D4[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_45__1
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [13]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_3),
        .O(D5[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_46__1
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [10]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_0),
        .O(D5[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [4]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_4),
        .O(D5[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [17]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_0_5_n_4),
        .O(D0[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_53__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [12]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_5),
        .O(D6[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_55__1
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [8]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_3),
        .O(D6[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_58__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [18]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_60_65_n_2),
        .O(D7[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_65__1
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [0]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_54_59_n_3),
        .O(D7[0]));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_66__1
       (.I0(mem_reg_0_15_66_71_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[7]));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_67__1
       (.I0(mem_reg_0_15_66_71_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[6]));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_68__1
       (.I0(mem_reg_0_15_66_71_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[5]));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_69__1
       (.I0(mem_reg_0_15_66_71_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[4]));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_70__1
       (.I0(mem_reg_0_15_66_71_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_71__1
       (.I0(mem_reg_0_15_66_71_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_72__1
       (.I0(mem_reg_0_15_60_65_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_73__1
       (.I0(mem_reg_0_15_60_65_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[0]));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [27]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_78_79_n_0),
        .O(D9[7]));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_75__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [26]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_78_79_n_1),
        .O(D9[6]));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_76__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [25]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_4),
        .O(D9[5]));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_77__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [24]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_5),
        .O(D9[4]));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_78__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [23]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_2),
        .O(D9[3]));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_79__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [22]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_3),
        .O(D9[2]));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_80__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [21]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_0),
        .O(D9[1]));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_81__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [20]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_1),
        .O(D9[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_8__2
       (.I0(init_calib_complete_reg_rep__4),
        .I1(\write_buffer.wr_buf_out_data_reg[571] [7]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_0_5_n_0),
        .O(D0[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_9__2
       (.I0(\write_buffer.wr_buf_out_data_reg[571] [3]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_0_5_n_1),
        .O(D0[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__3 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__3 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__3 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__2 
       (.I0(ofifo_rst_reg),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(rd_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__3 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__5 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__5 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[3]),
        .I2(wr_ptr[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__3 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    \wr_ptr[3]_i_1__3 
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__3),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__3 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized3
   (\my_empty_reg[1]_0 ,
    \entry_cnt_reg[4]_0 ,
    of_wren_pre,
    D9,
    D8,
    D7,
    D6,
    D5,
    D4,
    D3,
    D2,
    D1,
    D0,
    \my_empty_reg[7]_0 ,
    CLK,
    phy_data_wr_en,
    ofifo_rst_reg,
    ofifo_rst,
    calib_wrdata_en,
    init_calib_complete_reg_rep__4,
    mc_wrdata_en,
    \write_buffer.wr_buf_out_data_reg[570] ,
    init_calib_complete_reg_rep__5,
    init_calib_complete_reg_rep__6,
    phy_dout);
  output \my_empty_reg[1]_0 ;
  output [2:0]\entry_cnt_reg[4]_0 ;
  output of_wren_pre;
  output [1:0]D9;
  output [1:0]D8;
  output [2:0]D7;
  output [2:0]D6;
  output [7:0]D5;
  output [1:0]D4;
  output [1:0]D3;
  output [2:0]D2;
  output [2:0]D1;
  output [7:0]D0;
  output [43:0]\my_empty_reg[7]_0 ;
  input CLK;
  input phy_data_wr_en;
  input ofifo_rst_reg;
  input ofifo_rst;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__4;
  input mc_wrdata_en;
  input [27:0]\write_buffer.wr_buf_out_data_reg[570] ;
  input init_calib_complete_reg_rep__5;
  input init_calib_complete_reg_rep__6;
  input [71:0]phy_dout;

  wire CLK;
  wire [7:0]D0;
  wire [2:0]D1;
  wire [2:0]D2;
  wire [1:0]D3;
  wire [1:0]D4;
  wire [7:0]D5;
  wire [2:0]D6;
  wire [2:0]D7;
  wire [1:0]D8;
  wire [1:0]D9;
  wire calib_wrdata_en;
  wire \entry_cnt[0]_i_1__1_n_0 ;
  wire \entry_cnt[1]_i_1__4_n_0 ;
  wire \entry_cnt[2]_i_1__1_n_0 ;
  wire \entry_cnt[3]_i_1__1_n_0 ;
  wire \entry_cnt[4]_i_1__1_n_0 ;
  wire \entry_cnt[4]_i_2__4_n_0 ;
  wire \entry_cnt[4]_i_3__1_n_0 ;
  wire [2:0]\entry_cnt_reg[4]_0 ;
  wire [1:0]entry_cnt_reg__0;
  wire init_calib_complete_reg_rep__4;
  wire init_calib_complete_reg_rep__5;
  wire init_calib_complete_reg_rep__6;
  wire mc_wrdata_en;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_4;
  wire mem_reg_0_15_18_23_n_0;
  wire mem_reg_0_15_18_23_n_3;
  wire mem_reg_0_15_24_29_n_3;
  wire mem_reg_0_15_24_29_n_5;
  wire mem_reg_0_15_30_35_n_3;
  wire mem_reg_0_15_36_41_n_2;
  wire mem_reg_0_15_36_41_n_4;
  wire mem_reg_0_15_36_41_n_5;
  wire mem_reg_0_15_42_47_n_0;
  wire mem_reg_0_15_42_47_n_1;
  wire mem_reg_0_15_42_47_n_2;
  wire mem_reg_0_15_42_47_n_3;
  wire mem_reg_0_15_42_47_n_4;
  wire mem_reg_0_15_42_47_n_5;
  wire mem_reg_0_15_48_53_n_0;
  wire mem_reg_0_15_48_53_n_1;
  wire mem_reg_0_15_48_53_n_4;
  wire mem_reg_0_15_54_59_n_2;
  wire mem_reg_0_15_54_59_n_4;
  wire mem_reg_0_15_60_65_n_1;
  wire mem_reg_0_15_66_71_n_1;
  wire mem_reg_0_15_66_71_n_3;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_72_77_n_1;
  wire mem_reg_0_15_78_79_n_0;
  wire \my_empty[1]_i_1__4_n_0 ;
  wire \my_empty[1]_i_2__8_n_0 ;
  wire \my_empty[7]_i_1__1_n_0 ;
  wire \my_empty[7]_i_2__1_n_0 ;
  wire \my_empty[7]_i_3__1_n_0 ;
  wire \my_empty[7]_i_4__0_n_0 ;
  wire \my_empty[7]_i_5__1_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire [43:0]\my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1__1_n_0 ;
  wire \my_full[4]_i_2__1_n_0 ;
  wire \my_full[4]_i_3__1_n_0 ;
  wire \my_full[4]_i_4__1_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire [3:0]rd_ptr;
  wire rd_ptr0;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[570] ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__1 
       (.I0(entry_cnt_reg__0[0]),
        .O(\entry_cnt[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT5 #(
    .INIT(32'hF70808F7)) 
    \entry_cnt[1]_i_1__4 
       (.I0(ofifo_rst_reg),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(entry_cnt_reg__0[1]),
        .I4(entry_cnt_reg__0[0]),
        .O(\entry_cnt[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1__1 
       (.I0(\entry_cnt_reg[4]_0 [0]),
        .I1(entry_cnt_reg__0[1]),
        .I2(entry_cnt_reg__0[0]),
        .I3(ofifo_rst_reg),
        .I4(phy_data_wr_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__1 
       (.I0(entry_cnt_reg__0[1]),
        .I1(entry_cnt_reg__0[0]),
        .I2(\entry_cnt[4]_i_3__1_n_0 ),
        .I3(\entry_cnt_reg[4]_0 [1]),
        .I4(\entry_cnt_reg[4]_0 [0]),
        .O(\entry_cnt[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00011101CCC111C1)) 
    \entry_cnt[4]_i_1__1 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(ofifo_rst_reg),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__4),
        .I4(mc_wrdata_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \entry_cnt[4]_i_2__4 
       (.I0(\entry_cnt_reg[4]_0 [2]),
        .I1(\entry_cnt_reg[4]_0 [1]),
        .I2(entry_cnt_reg__0[1]),
        .I3(entry_cnt_reg__0[0]),
        .I4(\entry_cnt[4]_i_3__1_n_0 ),
        .I5(\entry_cnt_reg[4]_0 [0]),
        .O(\entry_cnt[4]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h45400000)) 
    \entry_cnt[4]_i_3__1 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__4),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(\entry_cnt[4]_i_3__1_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[0]_i_1__1_n_0 ),
        .Q(entry_cnt_reg__0[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[1]_i_1__4_n_0 ),
        .Q(entry_cnt_reg__0[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[2]_i_1__1_n_0 ),
        .Q(\entry_cnt_reg[4]_0 [0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[3]_i_1__1_n_0 ),
        .Q(\entry_cnt_reg[4]_0 [1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[4]_i_2__4_n_0 ),
        .Q(\entry_cnt_reg[4]_0 [2]),
        .R(ofifo_rst));
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    mem_reg_0_15_0_5_i_1__4
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__4),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg[1]_0 ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_en));
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[5:4]),
        .DIB(phy_dout[7:6]),
        .DIC(phy_dout[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,\my_empty_reg[7]_0 [2]}),
        .DOB(\my_empty_reg[7]_0 [4:3]),
        .DOC({mem_reg_0_15_12_17_n_4,\my_empty_reg[7]_0 [5]}),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[11:10]),
        .DIB(phy_dout[13:12]),
        .DIC(phy_dout[15:14]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_18_23_n_0,\my_empty_reg[7]_0 [6]}),
        .DOB({\my_empty_reg[7]_0 [7],mem_reg_0_15_18_23_n_3}),
        .DOC(\my_empty_reg[7]_0 [9:8]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[17:16]),
        .DIB(phy_dout[19:18]),
        .DIC(phy_dout[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [11:10]),
        .DOB({\my_empty_reg[7]_0 [12],mem_reg_0_15_24_29_n_3}),
        .DOC({\my_empty_reg[7]_0 [13],mem_reg_0_15_24_29_n_5}),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[23:22]),
        .DIB(phy_dout[25:24]),
        .DIC(phy_dout[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [15:14]),
        .DOB({\my_empty_reg[7]_0 [16],mem_reg_0_15_30_35_n_3}),
        .DOC(\my_empty_reg[7]_0 [18:17]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[29:28]),
        .DIB(phy_dout[31:30]),
        .DIC(phy_dout[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [20:19]),
        .DOB({mem_reg_0_15_36_41_n_2,\my_empty_reg[7]_0 [21]}),
        .DOC({mem_reg_0_15_36_41_n_4,mem_reg_0_15_36_41_n_5}),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[35:34]),
        .DIB(phy_dout[37:36]),
        .DIC(phy_dout[39:38]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_42_47_n_0,mem_reg_0_15_42_47_n_1}),
        .DOB({mem_reg_0_15_42_47_n_2,mem_reg_0_15_42_47_n_3}),
        .DOC({mem_reg_0_15_42_47_n_4,mem_reg_0_15_42_47_n_5}),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[41:40]),
        .DIB(phy_dout[43:42]),
        .DIC(phy_dout[45:44]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_48_53_n_0,mem_reg_0_15_48_53_n_1}),
        .DOB(\my_empty_reg[7]_0 [23:22]),
        .DOC({mem_reg_0_15_48_53_n_4,\my_empty_reg[7]_0 [24]}),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[47:46]),
        .DIB(phy_dout[49:48]),
        .DIC(phy_dout[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [26:25]),
        .DOB({mem_reg_0_15_54_59_n_2,\my_empty_reg[7]_0 [27]}),
        .DOC({mem_reg_0_15_54_59_n_4,\my_empty_reg[7]_0 [28]}),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[53:52]),
        .DIB(phy_dout[55:54]),
        .DIC(phy_dout[57:56]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [29],mem_reg_0_15_60_65_n_1}),
        .DOB(\my_empty_reg[7]_0 [31:30]),
        .DOC(\my_empty_reg[7]_0 [33:32]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[59:58]),
        .DIB(phy_dout[61:60]),
        .DIC(phy_dout[63:62]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [34],mem_reg_0_15_66_71_n_1}),
        .DOB({\my_empty_reg[7]_0 [35],mem_reg_0_15_66_71_n_3}),
        .DOC(\my_empty_reg[7]_0 [37:36]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(phy_dout[1:0]),
        .DIC(phy_dout[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC(\my_empty_reg[7]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[65:64]),
        .DIB(phy_dout[67:66]),
        .DIC(phy_dout[69:68]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [38],mem_reg_0_15_72_77_n_1}),
        .DOB(\my_empty_reg[7]_0 [40:39]),
        .DOC(\my_empty_reg[7]_0 [42:41]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_78_79_n_0,\my_empty_reg[7]_0 [43]}),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[1]_i_1__4 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__4),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[1]_i_2__8 
       (.I0(\my_empty[7]_i_3__1_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__8_n_0 ));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[7]_i_1__1 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__4),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[7]_i_2__1 
       (.I0(\my_empty[7]_i_3__1_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3__1 
       (.I0(\my_empty[7]_i_4__0_n_0 ),
        .I1(\my_empty[7]_i_5__1_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_4__0 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_5__1 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_5__1_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__4_n_0 ),
        .D(\my_empty[1]_i_2__8_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1__1_n_0 ),
        .D(\my_empty[7]_i_2__1_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[4]_i_1__1 
       (.I0(\my_full[4]_i_2__1_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg_n_0_[7] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2__1 
       (.I0(\my_full[4]_i_3__1_n_0 ),
        .I1(\my_full[4]_i_4__1_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(wr_ptr[2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3__1 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4__1 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4__1_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_12__3
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [17]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_12_17_n_0),
        .O(D1[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [7]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_2),
        .O(D1[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_17__3
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [3]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_3),
        .O(D1[0]));
  LUT5 #(
    .INIT(32'h0000DFD5)) 
    out_fifo_i_1__2
       (.I0(\my_empty_reg[1]_0 ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__4),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(of_wren_pre));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_21__3
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [15]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_3),
        .O(D2[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_22__3
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [11]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_0),
        .O(D2[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_24__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [6]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_12_17_n_4),
        .O(D2[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_29__3
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [14]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_24_29_n_5),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__3
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[7]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_31__3
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [9]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_24_29_n_3),
        .O(D3[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_34__3
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [19]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_2),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__3
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[6]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41__3
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [2]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_30_35_n_3),
        .O(D4[0]));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_42__3
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [27]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_4),
        .O(D5[7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_43__3
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [26]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_5),
        .O(D5[6]));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_44__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [25]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_2),
        .O(D5[5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_45__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [24]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_3),
        .O(D5[4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_46__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [23]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_0),
        .O(D5[3]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_47__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [22]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_1),
        .O(D5[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [21]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_4),
        .O(D5[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_49__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [20]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_5),
        .O(D5[0]));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__3
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_52__2
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [16]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_4),
        .O(D6[2]));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_56__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [5]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_0),
        .O(D6[1]));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_57__2
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [1]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_1),
        .O(D6[0]));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__3
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_61__2
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [13]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_60_65_n_1),
        .O(D7[2]));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_62__2
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [10]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_54_59_n_4),
        .O(D7[1]));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_64__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [4]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_54_59_n_2),
        .O(D7[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_69__2
       (.I0(init_calib_complete_reg_rep__5),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [12]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_66_71_n_3),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__3
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_71__2
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [8]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_66_71_n_1),
        .O(D8[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74__2
       (.I0(init_calib_complete_reg_rep__4),
        .I1(\write_buffer.wr_buf_out_data_reg[570] [18]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_78_79_n_0),
        .O(D9[1]));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__3
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_81__2
       (.I0(\write_buffer.wr_buf_out_data_reg[570] [0]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_1),
        .O(D9[0]));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__3
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__3
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__4 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__4 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__4 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__3 
       (.I0(ofifo_rst_reg),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(rd_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__4 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__7 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__7 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[3]),
        .I2(wr_ptr[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__4 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    \wr_ptr[3]_i_1__4 
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__4),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__4 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized4
   (ofs_rdy_r_reg,
    \my_empty_reg[1]_0 ,
    \entry_cnt_reg[4]_0 ,
    of_wren_pre,
    D9,
    D8,
    D7,
    D6,
    D5,
    D4,
    D3,
    D2,
    D1,
    D0,
    \my_empty_reg[7]_0 ,
    CLK,
    phy_data_wr_en,
    ofifo_rst_reg,
    ofifo_rst,
    \entry_cnt_reg[3]_0 ,
    \entry_cnt_reg[3]_1 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__6,
    mc_wrdata_en,
    \write_buffer.wr_buf_out_data_reg[569] ,
    init_calib_complete_reg_rep__7,
    phy_dout);
  output ofs_rdy_r_reg;
  output \my_empty_reg[1]_0 ;
  output [0:0]\entry_cnt_reg[4]_0 ;
  output of_wren_pre;
  output [7:0]D9;
  output [1:0]D8;
  output [1:0]D7;
  output [2:0]D6;
  output [2:0]D5;
  output [1:0]D4;
  output [1:0]D3;
  output [2:0]D2;
  output [2:0]D1;
  output [7:0]D0;
  output [43:0]\my_empty_reg[7]_0 ;
  input CLK;
  input phy_data_wr_en;
  input ofifo_rst_reg;
  input ofifo_rst;
  input [1:0]\entry_cnt_reg[3]_0 ;
  input [1:0]\entry_cnt_reg[3]_1 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__6;
  input mc_wrdata_en;
  input [27:0]\write_buffer.wr_buf_out_data_reg[569] ;
  input init_calib_complete_reg_rep__7;
  input [71:0]phy_dout;

  wire CLK;
  wire [7:0]D0;
  wire [2:0]D1;
  wire [2:0]D2;
  wire [1:0]D3;
  wire [1:0]D4;
  wire [2:0]D5;
  wire [2:0]D6;
  wire [1:0]D7;
  wire [1:0]D8;
  wire [7:0]D9;
  wire calib_wrdata_en;
  wire \entry_cnt[0]_i_1__2_n_0 ;
  wire \entry_cnt[1]_i_1__5_n_0 ;
  wire \entry_cnt[2]_i_1__2_n_0 ;
  wire \entry_cnt[3]_i_1__2_n_0 ;
  wire \entry_cnt[4]_i_1__2_n_0 ;
  wire \entry_cnt[4]_i_2__5_n_0 ;
  wire \entry_cnt[4]_i_3__2_n_0 ;
  wire [1:0]\entry_cnt_reg[3]_0 ;
  wire [1:0]\entry_cnt_reg[3]_1 ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire [3:0]entry_cnt_reg__0;
  wire init_calib_complete_reg_rep__6;
  wire init_calib_complete_reg_rep__7;
  wire mc_wrdata_en;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_4;
  wire mem_reg_0_15_18_23_n_0;
  wire mem_reg_0_15_18_23_n_3;
  wire mem_reg_0_15_24_29_n_3;
  wire mem_reg_0_15_24_29_n_5;
  wire mem_reg_0_15_30_35_n_3;
  wire mem_reg_0_15_36_41_n_2;
  wire mem_reg_0_15_36_41_n_4;
  wire mem_reg_0_15_36_41_n_5;
  wire mem_reg_0_15_42_47_n_2;
  wire mem_reg_0_15_48_53_n_0;
  wire mem_reg_0_15_48_53_n_2;
  wire mem_reg_0_15_48_53_n_5;
  wire mem_reg_0_15_54_59_n_5;
  wire mem_reg_0_15_60_65_n_1;
  wire mem_reg_0_15_60_65_n_5;
  wire mem_reg_0_15_66_71_n_4;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_72_77_n_0;
  wire mem_reg_0_15_72_77_n_1;
  wire mem_reg_0_15_72_77_n_2;
  wire mem_reg_0_15_72_77_n_3;
  wire mem_reg_0_15_72_77_n_4;
  wire mem_reg_0_15_72_77_n_5;
  wire mem_reg_0_15_78_79_n_0;
  wire mem_reg_0_15_78_79_n_1;
  wire \my_empty[1]_i_1__5_n_0 ;
  wire \my_empty[1]_i_2__9_n_0 ;
  wire \my_empty[7]_i_1__2_n_0 ;
  wire \my_empty[7]_i_2__2_n_0 ;
  wire \my_empty[7]_i_3__2_n_0 ;
  wire \my_empty[7]_i_4__1_n_0 ;
  wire \my_empty[7]_i_5__2_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire [43:0]\my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1__2_n_0 ;
  wire \my_full[4]_i_2__2_n_0 ;
  wire \my_full[4]_i_3__2_n_0 ;
  wire \my_full[4]_i_4__2_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire ofs_rdy_r_reg;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire [3:0]rd_ptr;
  wire rd_ptr0;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[569] ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__2 
       (.I0(entry_cnt_reg__0[0]),
        .O(\entry_cnt[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT5 #(
    .INIT(32'hF70808F7)) 
    \entry_cnt[1]_i_1__5 
       (.I0(ofifo_rst_reg),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(entry_cnt_reg__0[1]),
        .I4(entry_cnt_reg__0[0]),
        .O(\entry_cnt[1]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1__2 
       (.I0(entry_cnt_reg__0[2]),
        .I1(entry_cnt_reg__0[1]),
        .I2(entry_cnt_reg__0[0]),
        .I3(ofifo_rst_reg),
        .I4(phy_data_wr_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[2]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__2 
       (.I0(entry_cnt_reg__0[1]),
        .I1(entry_cnt_reg__0[0]),
        .I2(\entry_cnt[4]_i_3__2_n_0 ),
        .I3(entry_cnt_reg__0[3]),
        .I4(entry_cnt_reg__0[2]),
        .O(\entry_cnt[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00011101CCC111C1)) 
    \entry_cnt[4]_i_1__2 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(ofifo_rst_reg),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__6),
        .I4(mc_wrdata_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \entry_cnt[4]_i_2__5 
       (.I0(\entry_cnt_reg[4]_0 ),
        .I1(entry_cnt_reg__0[3]),
        .I2(entry_cnt_reg__0[1]),
        .I3(entry_cnt_reg__0[0]),
        .I4(\entry_cnt[4]_i_3__2_n_0 ),
        .I5(entry_cnt_reg__0[2]),
        .O(\entry_cnt[4]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h45400000)) 
    \entry_cnt[4]_i_3__2 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__6),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(\entry_cnt[4]_i_3__2_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[0]_i_1__2_n_0 ),
        .Q(entry_cnt_reg__0[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[1]_i_1__5_n_0 ),
        .Q(entry_cnt_reg__0[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[2]_i_1__2_n_0 ),
        .Q(entry_cnt_reg__0[2]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[3]_i_1__2_n_0 ),
        .Q(entry_cnt_reg__0[3]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[4]_i_2__5_n_0 ),
        .Q(\entry_cnt_reg[4]_0 ),
        .R(ofifo_rst));
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    mem_reg_0_15_0_5_i_1__5
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__6),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg[1]_0 ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_en));
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[5:4]),
        .DIB(phy_dout[7:6]),
        .DIC(phy_dout[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,\my_empty_reg[7]_0 [2]}),
        .DOB(\my_empty_reg[7]_0 [4:3]),
        .DOC({mem_reg_0_15_12_17_n_4,\my_empty_reg[7]_0 [5]}),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[11:10]),
        .DIB(phy_dout[13:12]),
        .DIC(phy_dout[15:14]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_18_23_n_0,\my_empty_reg[7]_0 [6]}),
        .DOB({\my_empty_reg[7]_0 [7],mem_reg_0_15_18_23_n_3}),
        .DOC(\my_empty_reg[7]_0 [9:8]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[17:16]),
        .DIB(phy_dout[19:18]),
        .DIC(phy_dout[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [11:10]),
        .DOB({\my_empty_reg[7]_0 [12],mem_reg_0_15_24_29_n_3}),
        .DOC({\my_empty_reg[7]_0 [13],mem_reg_0_15_24_29_n_5}),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[23:22]),
        .DIB(phy_dout[25:24]),
        .DIC(phy_dout[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [15:14]),
        .DOB({\my_empty_reg[7]_0 [16],mem_reg_0_15_30_35_n_3}),
        .DOC(\my_empty_reg[7]_0 [18:17]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[29:28]),
        .DIB(phy_dout[31:30]),
        .DIC(phy_dout[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [20:19]),
        .DOB({mem_reg_0_15_36_41_n_2,\my_empty_reg[7]_0 [21]}),
        .DOC({mem_reg_0_15_36_41_n_4,mem_reg_0_15_36_41_n_5}),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[35:34]),
        .DIB(phy_dout[37:36]),
        .DIC(phy_dout[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [23:22]),
        .DOB({mem_reg_0_15_42_47_n_2,\my_empty_reg[7]_0 [24]}),
        .DOC(\my_empty_reg[7]_0 [26:25]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[41:40]),
        .DIB(phy_dout[43:42]),
        .DIC(phy_dout[45:44]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_48_53_n_0,\my_empty_reg[7]_0 [27]}),
        .DOB({mem_reg_0_15_48_53_n_2,\my_empty_reg[7]_0 [28]}),
        .DOC({\my_empty_reg[7]_0 [29],mem_reg_0_15_48_53_n_5}),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[47:46]),
        .DIB(phy_dout[49:48]),
        .DIC(phy_dout[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [31:30]),
        .DOB(\my_empty_reg[7]_0 [33:32]),
        .DOC({\my_empty_reg[7]_0 [34],mem_reg_0_15_54_59_n_5}),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[53:52]),
        .DIB(phy_dout[55:54]),
        .DIC(phy_dout[57:56]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [35],mem_reg_0_15_60_65_n_1}),
        .DOB(\my_empty_reg[7]_0 [37:36]),
        .DOC({\my_empty_reg[7]_0 [38],mem_reg_0_15_60_65_n_5}),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[59:58]),
        .DIB(phy_dout[61:60]),
        .DIC(phy_dout[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [40:39]),
        .DOB(\my_empty_reg[7]_0 [42:41]),
        .DOC({mem_reg_0_15_66_71_n_4,\my_empty_reg[7]_0 [43]}),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(phy_dout[1:0]),
        .DIC(phy_dout[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC(\my_empty_reg[7]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[65:64]),
        .DIB(phy_dout[67:66]),
        .DIC(phy_dout[69:68]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),
        .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),
        .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[1]_i_1__5 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__6),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[1]_i_2__9 
       (.I0(\my_empty[7]_i_3__2_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__9_n_0 ));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[7]_i_1__2 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__6),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[7]_i_2__2 
       (.I0(\my_empty[7]_i_3__2_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3__2 
       (.I0(\my_empty[7]_i_4__1_n_0 ),
        .I1(\my_empty[7]_i_5__2_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_4__1 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_5__2 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_5__2_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__5_n_0 ),
        .D(\my_empty[1]_i_2__9_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1__2_n_0 ),
        .D(\my_empty[7]_i_2__2_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[4]_i_1__2 
       (.I0(\my_full[4]_i_2__2_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg_n_0_[7] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2__2 
       (.I0(\my_full[4]_i_3__2_n_0 ),
        .I1(\my_full[4]_i_4__2_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(wr_ptr[2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3__2 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_3__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4__2 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4__2_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__2_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_5
       (.I0(entry_cnt_reg__0[3]),
        .I1(entry_cnt_reg__0[2]),
        .I2(\entry_cnt_reg[3]_0 [0]),
        .I3(\entry_cnt_reg[3]_0 [1]),
        .I4(\entry_cnt_reg[3]_1 [0]),
        .I5(\entry_cnt_reg[3]_1 [1]),
        .O(ofs_rdy_r_reg));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_12__4
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [17]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_12_17_n_0),
        .O(D1[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16__4
       (.I0(init_calib_complete_reg_rep__7),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [7]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_2),
        .O(D1[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_17__4
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [3]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_3),
        .O(D1[0]));
  LUT5 #(
    .INIT(32'h0000DFD5)) 
    out_fifo_i_1__3
       (.I0(\my_empty_reg[1]_0 ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__6),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(of_wren_pre));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_21__4
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [15]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_3),
        .O(D2[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_22__4
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [11]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_0),
        .O(D2[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_24__4
       (.I0(init_calib_complete_reg_rep__7),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [6]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_12_17_n_4),
        .O(D2[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_29__4
       (.I0(init_calib_complete_reg_rep__7),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [14]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_24_29_n_5),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__4
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[7]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_31__4
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [9]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_24_29_n_3),
        .O(D3[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_34__4
       (.I0(init_calib_complete_reg_rep__7),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [19]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_2),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__4
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[6]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41__4
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [2]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_30_35_n_3),
        .O(D4[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_44__3
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [16]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_2),
        .O(D5[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48__3
       (.I0(init_calib_complete_reg_rep__7),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [5]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_4),
        .O(D5[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_49__3
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [1]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_5),
        .O(D5[0]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__4
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_53__3
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [13]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_5),
        .O(D6[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_54__3
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [10]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_2),
        .O(D6[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_56__3
       (.I0(init_calib_complete_reg_rep__7),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [4]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_0),
        .O(D6[0]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__4
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_61__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [12]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_60_65_n_1),
        .O(D7[1]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_63__3
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [8]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_54_59_n_5),
        .O(D7[0]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_66__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [18]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_66_71_n_4),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__4
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_73__3
       (.I0(\write_buffer.wr_buf_out_data_reg[569] [0]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_60_65_n_5),
        .O(D8[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [27]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_78_79_n_0),
        .O(D9[7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_75__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [26]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_78_79_n_1),
        .O(D9[6]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_76__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [25]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_4),
        .O(D9[5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_77__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [24]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_5),
        .O(D9[4]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_78__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [23]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_2),
        .O(D9[3]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_79__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [22]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_3),
        .O(D9[2]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__4
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_80__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [21]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_0),
        .O(D9[1]));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_81__3
       (.I0(init_calib_complete_reg_rep__6),
        .I1(\write_buffer.wr_buf_out_data_reg[569] [20]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_1),
        .O(D9[0]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__4
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__4
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__5 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__5 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__5 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__4 
       (.I0(ofifo_rst_reg),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(rd_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__5 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__9 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__9 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[3]),
        .I2(wr_ptr[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__5 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    \wr_ptr[3]_i_1__5 
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__6),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__5 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized5
   (phy_mc_data_full,
    \my_empty_reg[1]_0 ,
    \entry_cnt_reg[4]_0 ,
    of_wren_pre,
    D9,
    D8,
    D7,
    D6,
    D5,
    D4,
    D3,
    D2,
    D1,
    D0,
    \my_empty_reg[7]_0 ,
    CLK,
    phy_data_wr_en,
    ofifo_rst_reg,
    ofifo_rst,
    \entry_cnt_reg[3]_0 ,
    \entry_cnt_reg[2]_0 ,
    \entry_cnt_reg[3]_1 ,
    \entry_cnt_reg[3]_2 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__7,
    mc_wrdata_en,
    init_calib_complete_reg_rep__8,
    \write_buffer.wr_buf_out_data_reg[568] ,
    init_calib_complete_reg_rep__9,
    phy_dout);
  output phy_mc_data_full;
  output \my_empty_reg[1]_0 ;
  output [0:0]\entry_cnt_reg[4]_0 ;
  output of_wren_pre;
  output [7:0]D9;
  output [1:0]D8;
  output [1:0]D7;
  output [2:0]D6;
  output [2:0]D5;
  output [1:0]D4;
  output [1:0]D3;
  output [2:0]D2;
  output [2:0]D1;
  output [7:0]D0;
  output [43:0]\my_empty_reg[7]_0 ;
  input CLK;
  input phy_data_wr_en;
  input ofifo_rst_reg;
  input ofifo_rst;
  input \entry_cnt_reg[3]_0 ;
  input \entry_cnt_reg[2]_0 ;
  input \entry_cnt_reg[3]_1 ;
  input \entry_cnt_reg[3]_2 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__7;
  input mc_wrdata_en;
  input init_calib_complete_reg_rep__8;
  input [27:0]\write_buffer.wr_buf_out_data_reg[568] ;
  input init_calib_complete_reg_rep__9;
  input [71:0]phy_dout;

  wire CLK;
  wire [7:0]D0;
  wire [2:0]D1;
  wire [2:0]D2;
  wire [1:0]D3;
  wire [1:0]D4;
  wire [2:0]D5;
  wire [2:0]D6;
  wire [1:0]D7;
  wire [1:0]D8;
  wire [7:0]D9;
  wire calib_wrdata_en;
  wire \entry_cnt[0]_i_1__3_n_0 ;
  wire \entry_cnt[1]_i_1__6_n_0 ;
  wire \entry_cnt[2]_i_1__3_n_0 ;
  wire \entry_cnt[3]_i_1__3_n_0 ;
  wire \entry_cnt[4]_i_1__3_n_0 ;
  wire \entry_cnt[4]_i_2__6_n_0 ;
  wire \entry_cnt[4]_i_3__3_n_0 ;
  wire \entry_cnt_reg[2]_0 ;
  wire \entry_cnt_reg[3]_0 ;
  wire \entry_cnt_reg[3]_1 ;
  wire \entry_cnt_reg[3]_2 ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire [3:0]entry_cnt_reg__0;
  wire init_calib_complete_reg_rep__7;
  wire init_calib_complete_reg_rep__8;
  wire init_calib_complete_reg_rep__9;
  wire mc_wrdata_en;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_4;
  wire mem_reg_0_15_18_23_n_0;
  wire mem_reg_0_15_18_23_n_3;
  wire mem_reg_0_15_24_29_n_3;
  wire mem_reg_0_15_24_29_n_5;
  wire mem_reg_0_15_30_35_n_3;
  wire mem_reg_0_15_36_41_n_2;
  wire mem_reg_0_15_36_41_n_4;
  wire mem_reg_0_15_36_41_n_5;
  wire mem_reg_0_15_42_47_n_2;
  wire mem_reg_0_15_48_53_n_0;
  wire mem_reg_0_15_48_53_n_2;
  wire mem_reg_0_15_48_53_n_5;
  wire mem_reg_0_15_54_59_n_5;
  wire mem_reg_0_15_60_65_n_1;
  wire mem_reg_0_15_60_65_n_5;
  wire mem_reg_0_15_66_71_n_4;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_72_77_n_0;
  wire mem_reg_0_15_72_77_n_1;
  wire mem_reg_0_15_72_77_n_2;
  wire mem_reg_0_15_72_77_n_3;
  wire mem_reg_0_15_72_77_n_4;
  wire mem_reg_0_15_72_77_n_5;
  wire mem_reg_0_15_78_79_n_0;
  wire mem_reg_0_15_78_79_n_1;
  wire \my_empty[1]_i_1__6_n_0 ;
  wire \my_empty[1]_i_2__10_n_0 ;
  wire \my_empty[7]_i_1__3_n_0 ;
  wire \my_empty[7]_i_2__3_n_0 ;
  wire \my_empty[7]_i_3__3_n_0 ;
  wire \my_empty[7]_i_4__2_n_0 ;
  wire \my_empty[7]_i_5__3_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire [43:0]\my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1__3_n_0 ;
  wire \my_full[4]_i_2__3_n_0 ;
  wire \my_full[4]_i_3__3_n_0 ;
  wire \my_full[4]_i_4__3_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_mc_data_full;
  wire [3:0]rd_ptr;
  wire rd_ptr0;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [27:0]\write_buffer.wr_buf_out_data_reg[568] ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__3 
       (.I0(entry_cnt_reg__0[0]),
        .O(\entry_cnt[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT5 #(
    .INIT(32'hF70808F7)) 
    \entry_cnt[1]_i_1__6 
       (.I0(ofifo_rst_reg),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(entry_cnt_reg__0[1]),
        .I4(entry_cnt_reg__0[0]),
        .O(\entry_cnt[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1__3 
       (.I0(entry_cnt_reg__0[2]),
        .I1(entry_cnt_reg__0[1]),
        .I2(entry_cnt_reg__0[0]),
        .I3(ofifo_rst_reg),
        .I4(phy_data_wr_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[2]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__3 
       (.I0(entry_cnt_reg__0[1]),
        .I1(entry_cnt_reg__0[0]),
        .I2(\entry_cnt[4]_i_3__3_n_0 ),
        .I3(entry_cnt_reg__0[3]),
        .I4(entry_cnt_reg__0[2]),
        .O(\entry_cnt[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h00011101CCC111C1)) 
    \entry_cnt[4]_i_1__3 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(ofifo_rst_reg),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__7),
        .I4(mc_wrdata_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[4]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \entry_cnt[4]_i_2__6 
       (.I0(\entry_cnt_reg[4]_0 ),
        .I1(entry_cnt_reg__0[3]),
        .I2(entry_cnt_reg__0[1]),
        .I3(entry_cnt_reg__0[0]),
        .I4(\entry_cnt[4]_i_3__3_n_0 ),
        .I5(entry_cnt_reg__0[2]),
        .O(\entry_cnt[4]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h45400000)) 
    \entry_cnt[4]_i_3__3 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__7),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(\entry_cnt[4]_i_3__3_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[0]_i_1__3_n_0 ),
        .Q(entry_cnt_reg__0[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[1]_i_1__6_n_0 ),
        .Q(entry_cnt_reg__0[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[2]_i_1__3_n_0 ),
        .Q(entry_cnt_reg__0[2]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[3]_i_1__3_n_0 ),
        .Q(entry_cnt_reg__0[3]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[4]_i_2__6_n_0 ),
        .Q(\entry_cnt_reg[4]_0 ),
        .R(ofifo_rst));
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    mem_reg_0_15_0_5_i_1__6
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__8),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg[1]_0 ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_en));
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[5:4]),
        .DIB(phy_dout[7:6]),
        .DIC(phy_dout[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,\my_empty_reg[7]_0 [2]}),
        .DOB(\my_empty_reg[7]_0 [4:3]),
        .DOC({mem_reg_0_15_12_17_n_4,\my_empty_reg[7]_0 [5]}),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[11:10]),
        .DIB(phy_dout[13:12]),
        .DIC(phy_dout[15:14]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_18_23_n_0,\my_empty_reg[7]_0 [6]}),
        .DOB({\my_empty_reg[7]_0 [7],mem_reg_0_15_18_23_n_3}),
        .DOC(\my_empty_reg[7]_0 [9:8]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[17:16]),
        .DIB(phy_dout[19:18]),
        .DIC(phy_dout[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [11:10]),
        .DOB({\my_empty_reg[7]_0 [12],mem_reg_0_15_24_29_n_3}),
        .DOC({\my_empty_reg[7]_0 [13],mem_reg_0_15_24_29_n_5}),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[23:22]),
        .DIB(phy_dout[25:24]),
        .DIC(phy_dout[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [15:14]),
        .DOB({\my_empty_reg[7]_0 [16],mem_reg_0_15_30_35_n_3}),
        .DOC(\my_empty_reg[7]_0 [18:17]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[29:28]),
        .DIB(phy_dout[31:30]),
        .DIC(phy_dout[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [20:19]),
        .DOB({mem_reg_0_15_36_41_n_2,\my_empty_reg[7]_0 [21]}),
        .DOC({mem_reg_0_15_36_41_n_4,mem_reg_0_15_36_41_n_5}),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[35:34]),
        .DIB(phy_dout[37:36]),
        .DIC(phy_dout[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [23:22]),
        .DOB({mem_reg_0_15_42_47_n_2,\my_empty_reg[7]_0 [24]}),
        .DOC(\my_empty_reg[7]_0 [26:25]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[41:40]),
        .DIB(phy_dout[43:42]),
        .DIC(phy_dout[45:44]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_48_53_n_0,\my_empty_reg[7]_0 [27]}),
        .DOB({mem_reg_0_15_48_53_n_2,\my_empty_reg[7]_0 [28]}),
        .DOC({\my_empty_reg[7]_0 [29],mem_reg_0_15_48_53_n_5}),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[47:46]),
        .DIB(phy_dout[49:48]),
        .DIC(phy_dout[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [31:30]),
        .DOB(\my_empty_reg[7]_0 [33:32]),
        .DOC({\my_empty_reg[7]_0 [34],mem_reg_0_15_54_59_n_5}),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[53:52]),
        .DIB(phy_dout[55:54]),
        .DIC(phy_dout[57:56]),
        .DID({1'b0,1'b0}),
        .DOA({\my_empty_reg[7]_0 [35],mem_reg_0_15_60_65_n_1}),
        .DOB(\my_empty_reg[7]_0 [37:36]),
        .DOC({\my_empty_reg[7]_0 [38],mem_reg_0_15_60_65_n_5}),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[59:58]),
        .DIB(phy_dout[61:60]),
        .DIC(phy_dout[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[7]_0 [40:39]),
        .DOB(\my_empty_reg[7]_0 [42:41]),
        .DOC({mem_reg_0_15_66_71_n_4,\my_empty_reg[7]_0 [43]}),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(phy_dout[1:0]),
        .DIC(phy_dout[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC(\my_empty_reg[7]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[65:64]),
        .DIB(phy_dout[67:66]),
        .DIC(phy_dout[69:68]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),
        .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),
        .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[1]_i_1__6 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__7),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[1]_i_2__10 
       (.I0(\my_empty[7]_i_3__3_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__10_n_0 ));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[7]_i_1__3 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__7),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[7]_i_2__3 
       (.I0(\my_empty[7]_i_3__3_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3__3 
       (.I0(\my_empty[7]_i_4__2_n_0 ),
        .I1(\my_empty[7]_i_5__3_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_4__2 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_5__3 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_5__3_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__6_n_0 ),
        .D(\my_empty[1]_i_2__10_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1__3_n_0 ),
        .D(\my_empty[7]_i_2__3_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[4]_i_1__3 
       (.I0(\my_full[4]_i_2__3_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg_n_0_[7] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2__3 
       (.I0(\my_full[4]_i_3__3_n_0 ),
        .I1(\my_full[4]_i_4__3_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(wr_ptr[2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3__3 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_3__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4__3 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4__3_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__3_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_2
       (.I0(\entry_cnt_reg[3]_0 ),
        .I1(\entry_cnt_reg[2]_0 ),
        .I2(entry_cnt_reg__0[3]),
        .I3(entry_cnt_reg__0[2]),
        .I4(\entry_cnt_reg[3]_1 ),
        .I5(\entry_cnt_reg[3]_2 ),
        .O(phy_mc_data_full));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_12__5
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [17]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_12_17_n_0),
        .O(D1[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_16__5
       (.I0(init_calib_complete_reg_rep__9),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [7]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_2),
        .O(D1[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_17__5
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [3]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_6_11_n_3),
        .O(D1[0]));
  LUT5 #(
    .INIT(32'h0000DFD5)) 
    out_fifo_i_1__4
       (.I0(\my_empty_reg[1]_0 ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__8),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(of_wren_pre));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_21__5
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [15]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_3),
        .O(D2[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_22__5
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [11]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_18_23_n_0),
        .O(D2[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_24__5
       (.I0(init_calib_complete_reg_rep__9),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [6]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_12_17_n_4),
        .O(D2[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_29__5
       (.I0(init_calib_complete_reg_rep__9),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [14]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_24_29_n_5),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__5
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[7]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_31__5
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [9]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_24_29_n_3),
        .O(D3[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_34__5
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [19]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_2),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__5
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[6]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_41__5
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [2]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_30_35_n_3),
        .O(D4[0]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_44__4
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [16]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_42_47_n_2),
        .O(D5[2]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_48__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [5]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_4),
        .O(D5[1]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_49__4
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [1]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_36_41_n_5),
        .O(D5[0]));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__5
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_53__4
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [13]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_5),
        .O(D6[2]));
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_54__4
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [10]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_2),
        .O(D6[1]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_56__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [4]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_48_53_n_0),
        .O(D6[0]));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__5
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_61__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [12]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_60_65_n_1),
        .O(D7[1]));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_63__4
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [8]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_54_59_n_5),
        .O(D7[0]));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_66__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [18]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_66_71_n_4),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__5
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT4 #(
    .INIT(16'hBFB0)) 
    out_fifo_i_73__4
       (.I0(\write_buffer.wr_buf_out_data_reg[568] [0]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_60_65_n_5),
        .O(D8[0]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_74__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [27]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_78_79_n_0),
        .O(D9[7]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_75__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [26]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_78_79_n_1),
        .O(D9[6]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_76__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [25]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_4),
        .O(D9[5]));
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_77__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [24]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_5),
        .O(D9[4]));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_78__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [23]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_2),
        .O(D9[3]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_79__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [22]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_3),
        .O(D9[2]));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__5
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_80__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [21]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_0),
        .O(D9[1]));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT4 #(
    .INIT(16'h8F80)) 
    out_fifo_i_81__4
       (.I0(init_calib_complete_reg_rep__8),
        .I1(\write_buffer.wr_buf_out_data_reg[568] [20]),
        .I2(\my_empty_reg[1]_0 ),
        .I3(mem_reg_0_15_72_77_n_1),
        .O(D9[0]));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__5
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__5
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__6 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__6 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__6 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__5 
       (.I0(ofifo_rst_reg),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(rd_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__6 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__11 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__11 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[3]),
        .I2(wr_ptr[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__6 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    \wr_ptr[3]_i_1__6 
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__8),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__6 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized6
   (\my_empty_reg[1]_0 ,
    \entry_cnt_reg[4]_0 ,
    ofs_rdy_r_reg,
    of_wren_pre,
    wr_en,
    D8,
    Q,
    \my_empty_reg[7]_0 ,
    CLK,
    phy_data_wr_en,
    ofifo_rst_reg,
    ofifo_rst,
    \entry_cnt_reg[4]_1 ,
    \entry_cnt_reg[3]_0 ,
    \entry_cnt_reg[4]_2 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__0,
    mc_wrdata_en,
    \rd_ptr_reg_rep[3]_0 );
  output \my_empty_reg[1]_0 ;
  output [0:0]\entry_cnt_reg[4]_0 ;
  output ofs_rdy_r_reg;
  output of_wren_pre;
  output wr_en;
  output [7:0]D8;
  output [3:0]Q;
  output [3:0]\my_empty_reg[7]_0 ;
  input CLK;
  input phy_data_wr_en;
  input ofifo_rst_reg;
  input ofifo_rst;
  input [0:0]\entry_cnt_reg[4]_1 ;
  input [1:0]\entry_cnt_reg[3]_0 ;
  input \entry_cnt_reg[4]_2 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__0;
  input mc_wrdata_en;
  input [7:0]\rd_ptr_reg_rep[3]_0 ;

  wire CLK;
  wire [7:0]D8;
  wire [3:0]Q;
  wire calib_wrdata_en;
  wire \entry_cnt[0]_i_1_n_0 ;
  wire \entry_cnt[1]_i_1__2_n_0 ;
  wire \entry_cnt[2]_i_1_n_0 ;
  wire \entry_cnt[3]_i_1_n_0 ;
  wire \entry_cnt[4]_i_1_n_0 ;
  wire \entry_cnt[4]_i_2__2_n_0 ;
  wire \entry_cnt[4]_i_3_n_0 ;
  wire [1:0]\entry_cnt_reg[3]_0 ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire [0:0]\entry_cnt_reg[4]_1 ;
  wire \entry_cnt_reg[4]_2 ;
  wire [3:0]entry_cnt_reg__0;
  wire init_calib_complete_reg_rep__0;
  wire mc_wrdata_en;
  wire \my_empty[1]_i_1__0_n_0 ;
  wire \my_empty[1]_i_2__4_n_0 ;
  wire \my_empty[7]_i_1_n_0 ;
  wire \my_empty[7]_i_2_n_0 ;
  wire \my_empty[7]_i_3_n_0 ;
  wire \my_empty[7]_i_5_n_0 ;
  wire \my_empty[7]_i_6_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire [3:0]\my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire \my_full[4]_i_1_n_0 ;
  wire \my_full[4]_i_2_n_0 ;
  wire \my_full[4]_i_3_n_0 ;
  wire \my_full[4]_i_4_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire ofs_rdy_r_reg;
  wire phy_data_wr_en;
  wire rd_ptr0;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [7:0]\rd_ptr_reg_rep[3]_0 ;
  wire [3:0]rd_ptr_timing;
  wire wr_en;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;

  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1 
       (.I0(entry_cnt_reg__0[0]),
        .O(\entry_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT5 #(
    .INIT(32'hF70808F7)) 
    \entry_cnt[1]_i_1__2 
       (.I0(ofifo_rst_reg),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(entry_cnt_reg__0[1]),
        .I4(entry_cnt_reg__0[0]),
        .O(\entry_cnt[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A96AA9A9A9)) 
    \entry_cnt[2]_i_1 
       (.I0(entry_cnt_reg__0[2]),
        .I1(entry_cnt_reg__0[1]),
        .I2(entry_cnt_reg__0[0]),
        .I3(ofifo_rst_reg),
        .I4(phy_data_wr_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1 
       (.I0(entry_cnt_reg__0[1]),
        .I1(entry_cnt_reg__0[0]),
        .I2(\entry_cnt[4]_i_3_n_0 ),
        .I3(entry_cnt_reg__0[3]),
        .I4(entry_cnt_reg__0[2]),
        .O(\entry_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00011101CCC111C1)) 
    \entry_cnt[4]_i_1 
       (.I0(\my_empty_reg_n_0_[7] ),
        .I1(ofifo_rst_reg),
        .I2(calib_wrdata_en),
        .I3(init_calib_complete_reg_rep__0),
        .I4(mc_wrdata_en),
        .I5(\my_full_reg_n_0_[4] ),
        .O(\entry_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \entry_cnt[4]_i_2__2 
       (.I0(\entry_cnt_reg[4]_0 ),
        .I1(entry_cnt_reg__0[3]),
        .I2(entry_cnt_reg__0[1]),
        .I3(entry_cnt_reg__0[0]),
        .I4(\entry_cnt[4]_i_3_n_0 ),
        .I5(entry_cnt_reg__0[2]),
        .O(\entry_cnt[4]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h45400000)) 
    \entry_cnt[4]_i_3 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__0),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(\entry_cnt[4]_i_3_n_0 ));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[0]_i_1_n_0 ),
        .Q(entry_cnt_reg__0[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[1]_i_1__2_n_0 ),
        .Q(entry_cnt_reg__0[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[2]_i_1_n_0 ),
        .Q(entry_cnt_reg__0[2]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[3]_i_1_n_0 ),
        .Q(entry_cnt_reg__0[3]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[4]_i_2__2_n_0 ),
        .Q(\entry_cnt_reg[4]_0 ),
        .R(ofifo_rst));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    mem_reg_0_15_0_5_i_1__0
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__0),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg[1]_0 ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_en));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[1]_i_1__0 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__0),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[1]_i_2__4 
       (.I0(\my_empty[7]_i_3_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h4540000000001015)) 
    \my_empty[7]_i_1 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__0),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \my_empty[7]_i_2 
       (.I0(\my_empty[7]_i_3_n_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(phy_data_wr_en),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(\my_empty[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[7]_i_3 
       (.I0(\my_empty[7]_i_5_n_0 ),
        .I1(\my_empty[7]_i_6_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .I4(wr_ptr_timing[3]),
        .O(\my_empty[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[7]_i_5 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[0] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[7]_i_6 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[3] ),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[7]_i_6_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__0_n_0 ),
        .D(\my_empty[1]_i_2__4_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[7] 
       (.C(CLK),
        .CE(\my_empty[7]_i_1_n_0 ),
        .D(\my_empty[7]_i_2_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[4]_i_1 
       (.I0(\my_full[4]_i_2_n_0 ),
        .I1(phy_data_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg_n_0_[7] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[4]_i_2 
       (.I0(\my_full[4]_i_3_n_0 ),
        .I1(\my_full[4]_i_4_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(Q[2]),
        .I4(rd_ptr_timing[3]),
        .O(\my_full[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[4]_i_3 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\my_full[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[4]_i_4 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[4]_i_4_n_0 ));
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_3
       (.I0(entry_cnt_reg__0[3]),
        .I1(entry_cnt_reg__0[2]),
        .I2(\entry_cnt_reg[4]_1 ),
        .I3(\entry_cnt_reg[3]_0 [0]),
        .I4(\entry_cnt_reg[3]_0 [1]),
        .I5(\entry_cnt_reg[4]_2 ),
        .O(ofs_rdy_r_reg));
  LUT5 #(
    .INIT(32'h0000DFD5)) 
    out_fifo_i_1
       (.I0(\my_empty_reg[1]_0 ),
        .I1(mc_wrdata_en),
        .I2(init_calib_complete_reg_rep__0),
        .I3(calib_wrdata_en),
        .I4(ofifo_rst_reg),
        .O(of_wren_pre));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_66
       (.I0(\rd_ptr_reg_rep[3]_0 [7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[7]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_67
       (.I0(\rd_ptr_reg_rep[3]_0 [6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[6]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_68
       (.I0(\rd_ptr_reg_rep[3]_0 [5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[5]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_69
       (.I0(\rd_ptr_reg_rep[3]_0 [4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[4]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_70
       (.I0(\rd_ptr_reg_rep[3]_0 [3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_71
       (.I0(\rd_ptr_reg_rep[3]_0 [2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_72
       (.I0(\rd_ptr_reg_rep[3]_0 [1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_73
       (.I0(\rd_ptr_reg_rep[3]_0 [0]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\my_empty_reg[7]_0 [0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\my_empty_reg[7]_0 [1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\my_empty_reg[7]_0 [2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\my_empty_reg[7]_0 [3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__0 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__0 
       (.I0(\rd_ptr_reg_n_0_[1] ),
        .I1(\rd_ptr_reg_n_0_[3] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__0 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1 
       (.I0(ofifo_rst_reg),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(rd_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__0 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__1 
       (.I0(Q[3]),
        .I1(Q[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__1 
       (.I0(Q[1]),
        .I1(Q[3]),
        .I2(Q[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__0 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h000000E2E2E200E2)) 
    \wr_ptr[3]_i_1__0 
       (.I0(calib_wrdata_en),
        .I1(init_calib_complete_reg_rep__0),
        .I2(mc_wrdata_en),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(ofifo_rst_reg),
        .I5(\my_full_reg_n_0_[4] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__0 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(Q[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(Q[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized7
   (\my_empty_reg[1]_0 ,
    of_wren_pre,
    wr_en_10,
    D7,
    D6,
    D4,
    D3,
    D0,
    D5,
    Q,
    \wr_ptr_timing_reg[0]_0 ,
    CLK,
    phy_cmd_wr_en,
    ofifo_rst_reg,
    ofifo_rst,
    calib_cmd_wren,
    init_calib_complete_reg_rep__1,
    \rd_ptr_reg_rep[3]_0 ,
    init_calib_complete_reg_rep__0);
  output \my_empty_reg[1]_0 ;
  output of_wren_pre;
  output wr_en_10;
  output [7:0]D7;
  output [4:0]D6;
  output [5:0]D4;
  output [1:0]D3;
  output [1:0]D0;
  output [1:0]D5;
  output [3:0]Q;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  input CLK;
  input phy_cmd_wr_en;
  input ofifo_rst_reg;
  input ofifo_rst;
  input calib_cmd_wren;
  input init_calib_complete_reg_rep__1;
  input [24:0]\rd_ptr_reg_rep[3]_0 ;
  input init_calib_complete_reg_rep__0;

  wire CLK;
  wire [1:0]D0;
  wire [1:0]D3;
  wire [5:0]D4;
  wire [1:0]D5;
  wire [4:0]D6;
  wire [7:0]D7;
  wire [3:0]Q;
  wire calib_cmd_wren;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__1;
  wire my_empty0;
  wire \my_empty[1]_i_1__1_n_0 ;
  wire \my_empty[1]_i_2__5_n_0 ;
  wire \my_empty[6]_i_1__0_n_0 ;
  wire \my_empty[6]_i_2__0_n_0 ;
  wire \my_empty[6]_i_4__0_n_0 ;
  wire \my_empty[6]_i_5__0_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg_n_0_[6] ;
  wire my_full0;
  wire \my_full[3]_i_1__0_n_0 ;
  wire \my_full[3]_i_3_n_0 ;
  wire \my_full[3]_i_4__0_n_0 ;
  wire \my_full_reg_n_0_[3] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire of_wren_pre;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire phy_cmd_wr_en;
  wire [3:0]rd_ptr;
  wire rd_ptr0;
  wire [24:0]\rd_ptr_reg_rep[3]_0 ;
  wire [3:0]rd_ptr_timing;
  wire wr_en_10;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;

  LUT5 #(
    .INIT(32'h000EEE0E)) 
    mem_reg_0_15_0_5_i_1__1
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep__1),
        .I2(\my_empty_reg[1]_0 ),
        .I3(ofifo_rst_reg),
        .I4(\my_full_reg_n_0_[3] ),
        .O(wr_en_10));
  LUT5 #(
    .INIT(32'h0E000001)) 
    \my_empty[1]_i_1__1 
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep__0),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAA02AAAAAAAAAAAA)) 
    \my_empty[1]_i_2__5 
       (.I0(my_empty0),
        .I1(calib_cmd_wren),
        .I2(init_calib_complete_reg_rep__1),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h0E000001)) 
    \my_empty[6]_i_1__0 
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep__0),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAA02AAAAAAAAAAAA)) 
    \my_empty[6]_i_2__0 
       (.I0(my_empty0),
        .I1(calib_cmd_wren),
        .I2(init_calib_complete_reg_rep__1),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[6]_i_3__0 
       (.I0(\my_empty[6]_i_4__0_n_0 ),
        .I1(\my_empty[6]_i_5__0_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(rd_ptr[2]),
        .I4(wr_ptr_timing[3]),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[6]_i_4__0 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[3]),
        .O(\my_empty[6]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[6]_i_5__0 
       (.I0(rd_ptr[1]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[3]),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[6]_i_5__0_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__1_n_0 ),
        .D(\my_empty[1]_i_2__5_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(\my_empty[6]_i_1__0_n_0 ),
        .D(\my_empty[6]_i_2__0_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[3]_i_1__0 
       (.I0(my_full0),
        .I1(phy_cmd_wr_en),
        .I2(ofifo_rst_reg),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(ofifo_rst),
        .O(\my_full[3]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[3]_i_2__0 
       (.I0(\my_full[3]_i_3_n_0 ),
        .I1(\my_full[3]_i_4__0_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(Q[2]),
        .I4(rd_ptr_timing[3]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[3]_i_3 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\my_full[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[3]_i_4__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[3]_i_4__0_n_0 ));
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_14__0
       (.I0(\rd_ptr_reg_rep[3]_0 [9]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_15__0
       (.I0(\rd_ptr_reg_rep[3]_0 [8]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[0]));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT4 #(
    .INIT(16'h00FD)) 
    out_fifo_i_1__0
       (.I0(\my_empty_reg[1]_0 ),
        .I1(init_calib_complete_reg_rep__1),
        .I2(calib_cmd_wren),
        .I3(ofifo_rst_reg),
        .O(of_wren_pre));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_20__0
       (.I0(\rd_ptr_reg_rep[3]_0 [13]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[5]));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_21__0
       (.I0(\rd_ptr_reg_rep[3]_0 [12]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[4]));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_22__0
       (.I0(\rd_ptr_reg_rep[3]_0 [11]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[3]));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_23__0
       (.I0(\rd_ptr_reg_rep[3]_0 [10]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[2]));
  (* SOFT_HLUTNM = "soft_lutpair659" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_24__1
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\rd_ptr_reg_rep[3]_0 [15]),
        .O(D5[1]));
  (* SOFT_HLUTNM = "soft_lutpair661" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_28__1
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\rd_ptr_reg_rep[3]_0 [14]),
        .O(D5[0]));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__0
       (.I0(\rd_ptr_reg_rep[3]_0 [7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair661" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_32__1
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\rd_ptr_reg_rep[3]_0 [20]),
        .O(D6[4]));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_36__0
       (.I0(\rd_ptr_reg_rep[3]_0 [19]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[3]));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_37__0
       (.I0(\rd_ptr_reg_rep[3]_0 [18]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[2]));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_38__0
       (.I0(\rd_ptr_reg_rep[3]_0 [17]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[1]));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_39__0
       (.I0(\rd_ptr_reg_rep[3]_0 [16]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[0]));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__0
       (.I0(\rd_ptr_reg_rep[3]_0 [6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_40__0
       (.I0(\rd_ptr_reg_rep[3]_0 [24]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[3]));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_41__0
       (.I0(\rd_ptr_reg_rep[3]_0 [23]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[2]));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_42__0
       (.I0(\rd_ptr_reg_rep[3]_0 [22]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[1]));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_43__0
       (.I0(\rd_ptr_reg_rep[3]_0 [21]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[0]));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__0
       (.I0(\rd_ptr_reg_rep[3]_0 [5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair659" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__0
       (.I0(\rd_ptr_reg_rep[3]_0 [4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[0]));
  (* SOFT_HLUTNM = "soft_lutpair660" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__0
       (.I0(\rd_ptr_reg_rep[3]_0 [3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[7]));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__0
       (.I0(\rd_ptr_reg_rep[3]_0 [2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[6]));
  (* SOFT_HLUTNM = "soft_lutpair660" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__0
       (.I0(\rd_ptr_reg_rep[3]_0 [1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[5]));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__0
       (.I0(\rd_ptr_reg_rep[3]_0 [0]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[4]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\wr_ptr_timing_reg[0]_0 [0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\wr_ptr_timing_reg[0]_0 [1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\wr_ptr_timing_reg[0]_0 [2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\wr_ptr_timing_reg[0]_0 [3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__1 
       (.I0(rd_ptr[1]),
        .I1(rd_ptr[3]),
        .I2(rd_ptr[0]),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__1 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__0 
       (.I0(ofifo_rst_reg),
        .I1(\my_empty_reg_n_0_[6] ),
        .O(rd_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__1 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__2 
       (.I0(Q[3]),
        .I1(Q[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__2 
       (.I0(Q[1]),
        .I1(Q[3]),
        .I2(Q[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[2]));
  LUT5 #(
    .INIT(32'h000EEE0E)) 
    \wr_ptr[3]_i_1__1 
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep__1),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(ofifo_rst_reg),
        .I4(\my_full_reg_n_0_[3] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(Q[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(Q[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized8
   (\my_empty_reg[1]_0 ,
    \wr_ptr_timing_reg[0]_0 ,
    wr_en_11,
    D9,
    D8,
    D7,
    D4,
    D3,
    D2,
    D1,
    D0,
    Q,
    \wr_ptr_timing_reg[0]_1 ,
    CLK,
    ofifo_rst_reg,
    phy_cmd_wr_en,
    ofifo_rst,
    init_calib_complete_reg_rep__2,
    calib_cmd_wren,
    \rd_ptr_reg_rep[3]_0 ,
    init_calib_complete_reg_rep__0);
  output \my_empty_reg[1]_0 ;
  output \wr_ptr_timing_reg[0]_0 ;
  output wr_en_11;
  output [3:0]D9;
  output [3:0]D8;
  output [3:0]D7;
  output [3:0]D4;
  output [3:0]D3;
  output [3:0]D2;
  output [3:0]D1;
  output [4:0]D0;
  output [3:0]Q;
  output [3:0]\wr_ptr_timing_reg[0]_1 ;
  input CLK;
  input ofifo_rst_reg;
  input phy_cmd_wr_en;
  input ofifo_rst;
  input init_calib_complete_reg_rep__2;
  input calib_cmd_wren;
  input [32:0]\rd_ptr_reg_rep[3]_0 ;
  input init_calib_complete_reg_rep__0;

  wire CLK;
  wire [4:0]D0;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [3:0]Q;
  wire calib_cmd_wren;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__2;
  wire my_empty0;
  wire \my_empty[1]_i_1__2_n_0 ;
  wire \my_empty[1]_i_2__6_n_0 ;
  wire \my_empty[6]_i_1__1_n_0 ;
  wire \my_empty[6]_i_2__1_n_0 ;
  wire \my_empty[6]_i_4__1_n_0 ;
  wire \my_empty[6]_i_5__1_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg_n_0_[6] ;
  wire my_full0;
  wire \my_full[3]_i_1__1_n_0 ;
  wire \my_full[3]_i_3__0_n_0 ;
  wire \my_full[3]_i_4__1_n_0 ;
  wire \my_full_reg_n_0_[3] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire ofifo_rst_reg;
  wire phy_cmd_wr_en;
  wire [3:0]rd_ptr;
  wire rd_ptr0;
  wire [32:0]\rd_ptr_reg_rep[3]_0 ;
  wire [3:0]rd_ptr_timing;
  wire wr_en_11;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire [3:0]\wr_ptr_timing_reg[0]_1 ;

  LUT5 #(
    .INIT(32'h000EEE0E)) 
    mem_reg_0_15_0_5_i_1__2
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep__2),
        .I2(\my_empty_reg[1]_0 ),
        .I3(ofifo_rst_reg),
        .I4(\my_full_reg_n_0_[3] ),
        .O(wr_en_11));
  LUT5 #(
    .INIT(32'h0E000001)) 
    \my_empty[1]_i_1__2 
       (.I0(init_calib_complete_reg_rep__0),
        .I1(calib_cmd_wren),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hAA02AAAAAAAAAAAA)) 
    \my_empty[1]_i_2__6 
       (.I0(my_empty0),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg[1]_0 ),
        .O(\my_empty[1]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h0E000001)) 
    \my_empty[6]_i_1__1 
       (.I0(init_calib_complete_reg_rep__0),
        .I1(calib_cmd_wren),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(ofifo_rst_reg),
        .I4(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAA02AAAAAAAAAAAA)) 
    \my_empty[6]_i_2__1 
       (.I0(my_empty0),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_cmd_wren),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(ofifo_rst_reg),
        .I5(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[6]_i_3__1 
       (.I0(\my_empty[6]_i_4__1_n_0 ),
        .I1(\my_empty[6]_i_5__1_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(rd_ptr[2]),
        .I4(wr_ptr_timing[3]),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair663" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[6]_i_4__1 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[3]),
        .O(\my_empty[6]_i_4__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair663" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[6]_i_5__1 
       (.I0(rd_ptr[1]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[3]),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[6]_i_5__1_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1__2_n_0 ),
        .D(\my_empty[1]_i_2__6_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(ofifo_rst));
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(\my_empty[6]_i_1__1_n_0 ),
        .D(\my_empty[6]_i_2__1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(ofifo_rst));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[3]_i_1__1 
       (.I0(my_full0),
        .I1(ofifo_rst_reg),
        .I2(phy_cmd_wr_en),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(ofifo_rst),
        .O(\my_full[3]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[3]_i_2__1 
       (.I0(\my_full[3]_i_3__0_n_0 ),
        .I1(\my_full[3]_i_4__1_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(Q[2]),
        .I4(rd_ptr_timing[3]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair662" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[3]_i_3__0 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\my_full[3]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair662" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[3]_i_4__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[3]_i_4__1_n_0 ));
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair681" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_10__1
       (.I0(\rd_ptr_reg_rep[3]_0 [8]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair679" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_11__1
       (.I0(\rd_ptr_reg_rep[3]_0 [7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair680" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_12__1
       (.I0(\rd_ptr_reg_rep[3]_0 [6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair682" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_13__1
       (.I0(\rd_ptr_reg_rep[3]_0 [5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[0]));
  (* SOFT_HLUTNM = "soft_lutpair679" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_18__1
       (.I0(\rd_ptr_reg_rep[3]_0 [12]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[3]));
  (* SOFT_HLUTNM = "soft_lutpair680" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_19__1
       (.I0(\rd_ptr_reg_rep[3]_0 [11]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[2]));
  (* SOFT_HLUTNM = "soft_lutpair666" *) 
  LUT4 #(
    .INIT(16'h5455)) 
    out_fifo_i_1__8
       (.I0(ofifo_rst_reg),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_cmd_wren),
        .I3(\my_empty_reg[1]_0 ),
        .O(\wr_ptr_timing_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair681" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_20__1
       (.I0(\rd_ptr_reg_rep[3]_0 [10]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[1]));
  (* SOFT_HLUTNM = "soft_lutpair678" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_21__1
       (.I0(\rd_ptr_reg_rep[3]_0 [9]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[0]));
  (* SOFT_HLUTNM = "soft_lutpair673" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_26__1
       (.I0(\rd_ptr_reg_rep[3]_0 [16]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[3]));
  (* SOFT_HLUTNM = "soft_lutpair676" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_27__1
       (.I0(\rd_ptr_reg_rep[3]_0 [15]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[2]));
  (* SOFT_HLUTNM = "soft_lutpair675" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_28__0
       (.I0(\rd_ptr_reg_rep[3]_0 [14]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair678" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_29__1
       (.I0(\rd_ptr_reg_rep[3]_0 [13]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[0]));
  (* SOFT_HLUTNM = "soft_lutpair682" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__1
       (.I0(\rd_ptr_reg_rep[3]_0 [4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair670" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_34__1
       (.I0(\rd_ptr_reg_rep[3]_0 [20]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[3]));
  (* SOFT_HLUTNM = "soft_lutpair671" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_35__1
       (.I0(\rd_ptr_reg_rep[3]_0 [19]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[2]));
  (* SOFT_HLUTNM = "soft_lutpair672" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_36__1
       (.I0(\rd_ptr_reg_rep[3]_0 [18]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair674" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_37__1
       (.I0(\rd_ptr_reg_rep[3]_0 [17]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[0]));
  (* SOFT_HLUTNM = "soft_lutpair683" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__1
       (.I0(\rd_ptr_reg_rep[3]_0 [3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair683" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__1
       (.I0(\rd_ptr_reg_rep[3]_0 [2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair676" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_58__0
       (.I0(\rd_ptr_reg_rep[3]_0 [24]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[3]));
  (* SOFT_HLUTNM = "soft_lutpair677" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_59__0
       (.I0(\rd_ptr_reg_rep[3]_0 [23]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[2]));
  (* SOFT_HLUTNM = "soft_lutpair684" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__1
       (.I0(\rd_ptr_reg_rep[3]_0 [1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair677" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_60__0
       (.I0(\rd_ptr_reg_rep[3]_0 [22]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[1]));
  (* SOFT_HLUTNM = "soft_lutpair669" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_61__0
       (.I0(\rd_ptr_reg_rep[3]_0 [21]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[0]));
  (* SOFT_HLUTNM = "soft_lutpair672" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_66__0
       (.I0(\rd_ptr_reg_rep[3]_0 [28]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair673" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_67__0
       (.I0(\rd_ptr_reg_rep[3]_0 [27]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair674" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_68__0
       (.I0(\rd_ptr_reg_rep[3]_0 [26]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair675" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_69__0
       (.I0(\rd_ptr_reg_rep[3]_0 [25]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[0]));
  (* SOFT_HLUTNM = "soft_lutpair684" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_6__1
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\rd_ptr_reg_rep[3]_0 [0]),
        .O(D0[0]));
  (* SOFT_HLUTNM = "soft_lutpair666" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_74__0
       (.I0(\rd_ptr_reg_rep[3]_0 [32]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D9[3]));
  (* SOFT_HLUTNM = "soft_lutpair669" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_75__0
       (.I0(\rd_ptr_reg_rep[3]_0 [31]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D9[2]));
  (* SOFT_HLUTNM = "soft_lutpair670" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_76__0
       (.I0(\rd_ptr_reg_rep[3]_0 [30]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D9[1]));
  (* SOFT_HLUTNM = "soft_lutpair671" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_77__0
       (.I0(\rd_ptr_reg_rep[3]_0 [29]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D9[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(ofifo_rst));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(\wr_ptr_timing_reg[0]_1 [0]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(\wr_ptr_timing_reg[0]_1 [1]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(\wr_ptr_timing_reg[0]_1 [2]),
        .R(ofifo_rst));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(\wr_ptr_timing_reg[0]_1 [3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair668" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1__2 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair668" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1__2 
       (.I0(rd_ptr[1]),
        .I1(rd_ptr[3]),
        .I2(rd_ptr[0]),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair665" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1__2 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__1 
       (.I0(ofifo_rst_reg),
        .I1(\my_empty_reg_n_0_[6] ),
        .O(rd_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair665" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2__2 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(rd_ptr0),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair667" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__3 
       (.I0(Q[3]),
        .I1(Q[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair667" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1__3 
       (.I0(Q[1]),
        .I1(Q[3]),
        .I2(Q[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair664" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__2 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[2]));
  LUT5 #(
    .INIT(32'h000EEE0E)) 
    \wr_ptr[3]_i_1__2 
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep__2),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(ofifo_rst_reg),
        .I4(\my_full_reg_n_0_[3] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair664" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2__2 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(Q[2]),
        .R(ofifo_rst));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(Q[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_of_pre_fifo" *) 
module mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized9
   (D4,
    \my_empty_reg[1]_0 ,
    D5,
    \my_empty_reg[6]_0 ,
    D0,
    D1,
    D2,
    D3,
    \my_empty_reg[6]_1 ,
    CLK,
    init_calib_complete_reg_rep,
    \cmd_pipe_plus.mc_address_reg[41] ,
    mc_cas_n,
    init_calib_complete_reg_rep__0,
    D_of_ctl_full,
    calib_cmd_wren,
    init_calib_complete_reg_rep__14,
    phy_cmd_wr_en,
    SR,
    phy_dout);
  output [7:0]D4;
  output \my_empty_reg[1]_0 ;
  output [3:0]D5;
  output \my_empty_reg[6]_0 ;
  output [7:0]D0;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [15:0]\my_empty_reg[6]_1 ;
  input CLK;
  input init_calib_complete_reg_rep;
  input [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [0:0]mc_cas_n;
  input init_calib_complete_reg_rep__0;
  input D_of_ctl_full;
  input calib_cmd_wren;
  input init_calib_complete_reg_rep__14;
  input phy_cmd_wr_en;
  input [0:0]SR;
  input [21:0]phy_dout;

  wire CLK;
  wire [7:0]D0;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [7:0]D4;
  wire [3:0]D5;
  wire D_of_ctl_full;
  wire [0:0]SR;
  wire calib_cmd_wren;
  wire [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire init_calib_complete_reg_rep;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__14;
  wire [0:0]mc_cas_n;
  wire [47:0]mem_out;
  wire my_empty0;
  wire \my_empty[1]_i_1_n_0 ;
  wire \my_empty[1]_i_2__3_n_0 ;
  wire \my_empty[6]_i_1_n_0 ;
  wire \my_empty[6]_i_2_n_0 ;
  wire \my_empty[6]_i_4_n_0 ;
  wire \my_empty[6]_i_5_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[6]_0 ;
  wire [15:0]\my_empty_reg[6]_1 ;
  wire \my_empty_reg_n_0_[6] ;
  wire my_full0;
  wire \my_full[3]_i_1_n_0 ;
  wire \my_full[3]_i_4_n_0 ;
  wire \my_full[3]_i_5_n_0 ;
  wire \my_full_reg_n_0_[3] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire phy_cmd_wr_en;
  wire [21:0]phy_dout;
  wire [3:0]rd_ptr;
  wire [3:0]rd_ptr_0;
  wire \rd_ptr_rep[3]_i_1__6_n_0 ;
  wire [3:0]rd_ptr_timing;
  wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;

  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[1:0]),
        .DOB(mem_out[3:2]),
        .DOC(mem_out[5:4]),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT5 #(
    .INIT(32'h00E00EEE)) 
    mem_reg_0_15_0_5_i_1
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep),
        .I2(D_of_ctl_full),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(\my_empty_reg[1]_0 ),
        .O(wr_en));
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[13:12]),
        .DOB(mem_out[15:14]),
        .DOC(\my_empty_reg[6]_1 [5:4]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[7:6]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[6]_1 [7:6]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[9:8]),
        .DIB(phy_dout[11:10]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[6]_1 [9:8]),
        .DOB(\my_empty_reg[6]_1 [11:10]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(phy_dout[13:12]),
        .DIC(phy_dout[15:14]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(\my_empty_reg[6]_1 [13:12]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[19:18]),
        .DIB({phy_dout[13],phy_dout[20]}),
        .DIC({phy_dout[15],phy_dout[21]}),
        .DID({1'b0,1'b0}),
        .DOA(\my_empty_reg[6]_1 [15:14]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr_0}),
        .ADDRB({1'b0,rd_ptr_0}),
        .ADDRC({1'b0,rd_ptr_0}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(phy_dout[1:0]),
        .DIC(phy_dout[3:2]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[7:6]),
        .DOB(\my_empty_reg[6]_1 [1:0]),
        .DOC(\my_empty_reg[6]_1 [3:2]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT5 #(
    .INIT(32'h40404001)) 
    \my_empty[1]_i_1 
       (.I0(\my_full_reg_n_0_[3] ),
        .I1(\my_empty_reg[1]_0 ),
        .I2(D_of_ctl_full),
        .I3(init_calib_complete_reg_rep),
        .I4(calib_cmd_wren),
        .O(\my_empty[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAA8AAA8AAAAAAA)) 
    \my_empty[1]_i_2__3 
       (.I0(my_empty0),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(D_of_ctl_full),
        .I4(init_calib_complete_reg_rep),
        .I5(calib_cmd_wren),
        .O(\my_empty[1]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h40404001)) 
    \my_empty[6]_i_1 
       (.I0(\my_full_reg_n_0_[3] ),
        .I1(\my_empty_reg_n_0_[6] ),
        .I2(D_of_ctl_full),
        .I3(init_calib_complete_reg_rep),
        .I4(calib_cmd_wren),
        .O(\my_empty[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAA8AAA8AAAAAAA)) 
    \my_empty[6]_i_2 
       (.I0(my_empty0),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(D_of_ctl_full),
        .I4(init_calib_complete_reg_rep),
        .I5(calib_cmd_wren),
        .O(\my_empty[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_empty[6]_i_3 
       (.I0(\my_empty[6]_i_4_n_0 ),
        .I1(\my_empty[6]_i_5_n_0 ),
        .I2(wr_ptr_timing[2]),
        .I3(rd_ptr[2]),
        .I4(wr_ptr_timing[3]),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair686" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_empty[6]_i_4 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(rd_ptr[3]),
        .O(\my_empty[6]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair686" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_empty[6]_i_5 
       (.I0(rd_ptr[1]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[3]),
        .I3(wr_ptr_timing[0]),
        .I4(wr_ptr_timing[1]),
        .O(\my_empty[6]_i_5_n_0 ));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_empty[1]_i_1_n_0 ),
        .D(\my_empty[1]_i_2__3_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(SR));
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(\my_empty[6]_i_1_n_0 ),
        .D(\my_empty[6]_i_2_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(SR));
  LUT6 #(
    .INIT(64'h00000000FF00FC80)) 
    \my_full[3]_i_1 
       (.I0(my_full0),
        .I1(phy_cmd_wr_en),
        .I2(D_of_ctl_full),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .I5(SR),
        .O(\my_full[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0300A03A)) 
    \my_full[3]_i_2 
       (.I0(\my_full[3]_i_4_n_0 ),
        .I1(\my_full[3]_i_5_n_0 ),
        .I2(rd_ptr_timing[2]),
        .I3(wr_ptr[2]),
        .I4(rd_ptr_timing[3]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair685" *) 
  LUT5 #(
    .INIT(32'h82410482)) 
    \my_full[3]_i_4 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(wr_ptr[3]),
        .O(\my_full[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair685" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \my_full[3]_i_5 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[3]),
        .I3(rd_ptr_timing[0]),
        .I4(rd_ptr_timing[1]),
        .O(\my_full[3]_i_5_n_0 ));
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair701" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_10__9
       (.I0(mem_out[15]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair698" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_11__9
       (.I0(mem_out[14]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair702" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_12__9
       (.I0(mem_out[13]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair702" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_13__9
       (.I0(mem_out[12]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[0]));
  (* SOFT_HLUTNM = "soft_lutpair697" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_18__9
       (.I0(mem_out[23]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[3]));
  (* SOFT_HLUTNM = "soft_lutpair703" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_19__9
       (.I0(mem_out[22]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[2]));
  (* SOFT_HLUTNM = "soft_lutpair688" *) 
  LUT4 #(
    .INIT(16'h00FD)) 
    out_fifo_i_1__9
       (.I0(\my_empty_reg[1]_0 ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_cmd_wren),
        .I3(D_of_ctl_full),
        .O(\my_empty_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair704" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_20__9
       (.I0(mem_out[21]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[1]));
  (* SOFT_HLUTNM = "soft_lutpair699" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_21__9
       (.I0(mem_out[20]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[0]));
  (* SOFT_HLUTNM = "soft_lutpair703" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_26__9
       (.I0(mem_out[31]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[3]));
  (* SOFT_HLUTNM = "soft_lutpair700" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_27__9
       (.I0(mem_out[30]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[2]));
  (* SOFT_HLUTNM = "soft_lutpair705" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_28__9
       (.I0(mem_out[29]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair706" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_29__9
       (.I0(mem_out[28]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[0]));
  (* SOFT_HLUTNM = "soft_lutpair688" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__9
       (.I0(mem_out[7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair706" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_34__9
       (.I0(mem_out[39]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[7]));
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_35__9
       (.I0(mem_out[38]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[6]));
  (* SOFT_HLUTNM = "soft_lutpair704" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_36__9
       (.I0(mem_out[37]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[5]));
  (* SOFT_HLUTNM = "soft_lutpair705" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_37__9
       (.I0(mem_out[36]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[4]));
  (* SOFT_HLUTNM = "soft_lutpair690" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    out_fifo_i_38
       (.I0(init_calib_complete_reg_rep),
        .I1(mem_out[35]),
        .I2(\my_empty_reg[1]_0 ),
        .O(D4[3]));
  (* SOFT_HLUTNM = "soft_lutpair690" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_39
       (.I0(init_calib_complete_reg_rep),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [2]),
        .I2(mem_out[34]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D4[2]));
  (* SOFT_HLUTNM = "soft_lutpair689" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__9
       (.I0(mem_out[6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair687" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_40
       (.I0(init_calib_complete_reg_rep),
        .I1(mc_cas_n),
        .I2(mem_out[33]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair692" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_41
       (.I0(init_calib_complete_reg_rep),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [0]),
        .I2(mem_out[32]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D4[0]));
  (* SOFT_HLUTNM = "soft_lutpair692" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    out_fifo_i_42
       (.I0(init_calib_complete_reg_rep),
        .I1(mem_out[47]),
        .I2(\my_empty_reg[1]_0 ),
        .O(D5[3]));
  (* SOFT_HLUTNM = "soft_lutpair691" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_43
       (.I0(init_calib_complete_reg_rep__0),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [3]),
        .I2(mem_out[46]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[2]));
  (* SOFT_HLUTNM = "soft_lutpair687" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_44
       (.I0(init_calib_complete_reg_rep),
        .I1(mc_cas_n),
        .I2(mem_out[45]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[1]));
  (* SOFT_HLUTNM = "soft_lutpair689" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_45
       (.I0(init_calib_complete_reg_rep__0),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [1]),
        .I2(mem_out[44]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[0]));
  (* SOFT_HLUTNM = "soft_lutpair691" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__9
       (.I0(mem_out[5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair697" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__9
       (.I0(mem_out[4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair698" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__9
       (.I0(mem_out[3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair699" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__9
       (.I0(mem_out[2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair700" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__9
       (.I0(mem_out[1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair701" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__9
       (.I0(mem_out[0]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(SR));
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(SR));
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(SR));
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_0[0]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_0[1]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_0[2]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_ptr_reg_rep[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_0[3]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair696" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_rep[0]_i_1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair696" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \rd_ptr_rep[1]_i_1 
       (.I0(rd_ptr[1]),
        .I1(rd_ptr[3]),
        .I2(rd_ptr[0]),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair694" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_rep[2]_i_1 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_rep[3]_i_1__6 
       (.I0(\my_empty_reg_n_0_[6] ),
        .I1(D_of_ctl_full),
        .O(\rd_ptr_rep[3]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair694" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \rd_ptr_rep[3]_i_2 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_rep[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair695" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair695" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[1]),
        .I1(wr_ptr[3]),
        .I2(wr_ptr[0]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair693" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT5 #(
    .INIT(32'h00E00EEE)) 
    \wr_ptr[3]_i_1 
       (.I0(calib_cmd_wren),
        .I1(init_calib_complete_reg_rep),
        .I2(D_of_ctl_full),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair693" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \wr_ptr[3]_i_2 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[3]));
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(SR));
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(SR));
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(SR));
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_4lanes" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes
   (pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    p_134_in,
    p_133_in,
    p_138_in,
    p_137_in,
    p_142_in,
    p_141_in,
    p_146_in,
    p_145_in,
    p_150_in,
    p_149_in,
    p_154_in,
    p_153_in,
    p_158_in,
    p_157_in,
    p_13_in,
    \ddr3_dm[3] ,
    idelay_ld_rst,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    p_28_in,
    p_27_in,
    p_162_in,
    p_161_in,
    p_166_in,
    p_165_in,
    p_170_in,
    p_169_in,
    p_174_in,
    p_173_in,
    \ddr3_dm[2] ,
    p_15_in,
    p_178_in,
    p_177_in,
    p_182_in,
    p_181_in,
    p_186_in,
    p_185_in,
    p_190_in,
    p_189_in,
    if_empty_r,
    idelay_ld_rst_0,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \pi_dqs_found_lanes_r1_reg[2] ,
    p_32_in,
    p_194_in,
    p_193_in,
    p_198_in,
    p_197_in,
    p_202_in,
    p_201_in,
    p_206_in,
    p_205_in,
    p_210_in,
    p_209_in,
    p_214_in,
    p_213_in,
    p_218_in,
    p_217_in,
    p_222_in,
    p_221_in,
    p_19_in,
    \ddr3_dm[1] ,
    if_empty_r_0,
    idelay_ld_rst_1,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    p_226_in,
    p_225_in,
    p_230_in,
    p_229_in,
    p_234_in,
    p_233_in,
    p_238_in,
    p_237_in,
    p_242_in,
    p_241_in,
    p_246_in,
    p_245_in,
    p_250_in,
    p_249_in,
    p_254_in,
    p_253_in,
    \ddr3_dm[0] ,
    p_21_in,
    idelay_ld_rst_2,
    _phy_ctl_full_p__0,
    rst_primitives_reg_0,
    rst_primitives,
    mcGo_w__0,
    mcGo_reg_0,
    rclk_delay_11,
    rd_buf_we,
    \my_empty_reg[0] ,
    \wr_ptr_reg[1] ,
    \my_empty_reg[0]_0 ,
    \my_empty_reg[4]_rep__1 ,
    \read_fifo.tail_r_reg[1] ,
    \read_fifo.tail_r_reg[3] ,
    ADDRA,
    phy_mc_data_full,
    \entry_cnt_reg[4] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ,
    \my_empty_reg[1] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \my_empty_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ,
    \my_empty_reg[1]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ,
    \my_empty_reg[1]_2 ,
    rst_sync_r1_reg,
    ofs_rdy_r_reg,
    pi_phase_locked_all_r1_reg,
    \read_fifo.tail_r_reg[0] ,
    \read_fifo.tail_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    DIB,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[479] ,
    \not_strict_mode.app_rd_data_reg[24] ,
    \wr_ptr_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    p_0_out,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \po_rdval_cnt_reg[8] ,
    \pi_rdval_cnt_reg[5] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ,
    A_pi_counter_load_en116_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable112_out,
    A_pi_fine_inc114_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_pi_rst_dqs_find110_out,
    sync_pulse,
    CLK,
    COUNTERLOADVAL,
    A_po_coarse_enable98_out,
    A_po_fine_enable96_out,
    A_po_fine_inc100_out,
    \write_buffer.wr_buf_out_data_reg[479] ,
    \write_buffer.wr_buf_out_data_reg[478] ,
    \write_buffer.wr_buf_out_data_reg[477] ,
    \write_buffer.wr_buf_out_data_reg[412] ,
    \write_buffer.wr_buf_out_data_reg[475] ,
    \write_buffer.wr_buf_out_data_reg[474] ,
    \write_buffer.wr_buf_out_data_reg[473] ,
    \write_buffer.wr_buf_out_data_reg[408] ,
    A_rst_primitives_reg_0,
    p_131_out,
    A_idelay_ce13_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_135_out,
    p_139_out,
    p_143_out,
    p_147_out,
    p_151_out,
    p_155_out,
    p_159_out,
    phy_if_reset,
    B_pi_counter_load_en38_out,
    \calib_sel_reg[0]_0 ,
    B_pi_fine_enable34_out,
    B_pi_fine_inc36_out,
    p_29_out,
    B_pi_rst_dqs_find32_out,
    \calib_zero_inputs_reg[0] ,
    B_po_coarse_enable20_out,
    B_po_fine_enable18_out,
    B_po_fine_inc22_out,
    \write_buffer.wr_buf_out_data_reg[471] ,
    \write_buffer.wr_buf_out_data_reg[470] ,
    \write_buffer.wr_buf_out_data_reg[469] ,
    \write_buffer.wr_buf_out_data_reg[404] ,
    \write_buffer.wr_buf_out_data_reg[467] ,
    \write_buffer.wr_buf_out_data_reg[466] ,
    \write_buffer.wr_buf_out_data_reg[465] ,
    \write_buffer.wr_buf_out_data_reg[400] ,
    A_rst_primitives_reg_1,
    p_163_out,
    B_idelay_ce9_out,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    p_167_out,
    p_171_out,
    p_175_out,
    p_179_out,
    p_183_out,
    p_187_out,
    p_191_out,
    C_pi_counter_load_en64_out,
    \calib_sel_reg[1] ,
    C_pi_fine_enable60_out,
    C_pi_fine_inc62_out,
    p_34_out,
    C_pi_rst_dqs_find58_out,
    \calib_zero_inputs_reg[0]_0 ,
    C_po_coarse_enable46_out,
    C_po_fine_enable44_out,
    C_po_fine_inc48_out,
    \write_buffer.wr_buf_out_data_reg[463] ,
    \write_buffer.wr_buf_out_data_reg[462] ,
    \write_buffer.wr_buf_out_data_reg[461] ,
    \write_buffer.wr_buf_out_data_reg[396] ,
    \write_buffer.wr_buf_out_data_reg[459] ,
    \write_buffer.wr_buf_out_data_reg[458] ,
    \write_buffer.wr_buf_out_data_reg[457] ,
    \write_buffer.wr_buf_out_data_reg[392] ,
    A_rst_primitives_reg_2,
    p_195_out,
    C_idelay_ce5_out,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    p_199_out,
    p_203_out,
    p_207_out,
    p_211_out,
    p_215_out,
    p_219_out,
    p_223_out,
    D_pi_counter_load_en90_out,
    \calib_sel_reg[0]_1 ,
    D_pi_fine_enable86_out,
    D_pi_fine_inc88_out,
    mc_read_idle_r_reg_0,
    D_pi_rst_dqs_find84_out,
    \calib_zero_inputs_reg[0]_1 ,
    D_po_coarse_enable72_out,
    D_po_fine_enable70_out,
    D_po_fine_inc74_out,
    \write_buffer.wr_buf_out_data_reg[455] ,
    \write_buffer.wr_buf_out_data_reg[454] ,
    \write_buffer.wr_buf_out_data_reg[453] ,
    \write_buffer.wr_buf_out_data_reg[388] ,
    \write_buffer.wr_buf_out_data_reg[451] ,
    \write_buffer.wr_buf_out_data_reg[450] ,
    \write_buffer.wr_buf_out_data_reg[449] ,
    \write_buffer.wr_buf_out_data_reg[384] ,
    A_rst_primitives_reg_3,
    p_227_out,
    D_idelay_ce1_out,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    p_231_out,
    p_235_out,
    p_239_out,
    p_243_out,
    p_247_out,
    p_251_out,
    p_255_out,
    phy_ctl_mstr_empty,
    phy_ctl_wr_i2,
    pll_lock,
    read_calib,
    sys_rst_0,
    rstdiv0_sync_r1,
    write_calib,
    Q,
    sys_rst_1,
    p_0_in,
    \rclk_delay_reg[11]_0 ,
    rst_primitives_reg_1,
    phy_data_wr_en,
    ram_init_done_r,
    if_empty_r_1,
    my_empty,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    if_empty_r_2,
    \my_empty_reg[3] ,
    \read_fifo.fifo_out_data_r_reg[6] ,
    init_complete_r1_timing_reg,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ,
    tail_r,
    rstdiv0_sync_r1_reg_rep__21,
    \entry_cnt_reg[3] ,
    \entry_cnt_reg[2] ,
    \entry_cnt_reg[3]_0 ,
    \my_empty_reg[0]_1 ,
    sys_rst,
    iodelay_ctrl_rdy,
    sys_rst_2,
    ref_dll_lock_w,
    \entry_cnt_reg[4]_0 ,
    \entry_cnt_reg[4]_1 ,
    \entry_cnt_reg[4]_2 ,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    A_rst_primitives_reg_7,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[1] ,
    DIA,
    DIC,
    \rd_mux_sel_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \rd_mux_sel_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \rd_mux_sel_r_reg[1]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \rd_mux_sel_r_reg[1]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \rd_mux_sel_r_reg[1]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \rd_mux_sel_r_reg[1]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \rd_mux_sel_r_reg[1]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \rd_mux_sel_r_reg[1]_7 ,
    \rd_mux_sel_r_reg[1]_8 ,
    \rd_mux_sel_r_reg[1]_9 ,
    \rd_mux_sel_r_reg[1]_10 ,
    \rd_mux_sel_r_reg[1]_11 ,
    \rd_mux_sel_r_reg[1]_12 ,
    \rd_mux_sel_r_reg[1]_13 ,
    \rd_mux_sel_r_reg[1]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \rd_mux_sel_r_reg[1]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \rd_mux_sel_r_reg[1]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \rd_mux_sel_r_reg[1]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \rd_mux_sel_r_reg[1]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \rd_mux_sel_r_reg[1]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \rd_mux_sel_r_reg[1]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \rd_mux_sel_r_reg[1]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \rd_mux_sel_r_reg[1]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \rd_mux_sel_r_reg[1]_23 ,
    \rd_mux_sel_r_reg[1]_24 ,
    \rd_mux_sel_r_reg[1]_25 ,
    \rd_mux_sel_r_reg[1]_26 ,
    \rd_mux_sel_r_reg[1]_27 ,
    \rd_mux_sel_r_reg[1]_28 ,
    \rd_mux_sel_r_reg[1]_29 ,
    \rd_mux_sel_r_reg[1]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \rd_mux_sel_r_reg[1]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \rd_mux_sel_r_reg[1]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \rd_mux_sel_r_reg[1]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \rd_mux_sel_r_reg[1]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \rd_mux_sel_r_reg[1]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \rd_mux_sel_r_reg[1]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \rd_mux_sel_r_reg[1]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \rd_mux_sel_r_reg[1]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \rd_mux_sel_r_reg[1]_39 ,
    \rd_mux_sel_r_reg[1]_40 ,
    \rd_mux_sel_r_reg[1]_41 ,
    \rd_mux_sel_r_reg[1]_42 ,
    \rd_mux_sel_r_reg[1]_43 ,
    \rd_mux_sel_r_reg[1]_44 ,
    \rd_mux_sel_r_reg[1]_45 ,
    \rd_mux_sel_r_reg[1]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \rd_mux_sel_r_reg[1]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,
    \rd_mux_sel_r_reg[1]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,
    \rd_mux_sel_r_reg[1]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,
    \rd_mux_sel_r_reg[1]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,
    \rd_mux_sel_r_reg[1]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,
    \rd_mux_sel_r_reg[1]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,
    \rd_mux_sel_r_reg[1]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,
    \rd_mux_sel_r_reg[1]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \rd_mux_sel_r_reg[1]_55 ,
    \rd_mux_sel_r_reg[1]_56 ,
    \rd_mux_sel_r_reg[1]_57 ,
    \rd_mux_sel_r_reg[1]_58 ,
    \rd_mux_sel_r_reg[1]_59 ,
    \rd_mux_sel_r_reg[1]_60 ,
    \rd_mux_sel_r_reg[1]_61 ,
    \rd_mux_sel_r_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,
    DOC,
    DOB,
    DOA,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    ram_init_addr,
    calib_wrdata_en,
    init_calib_complete_reg_rep__3,
    mc_wrdata_en,
    \write_buffer.wr_buf_out_data_reg[571] ,
    init_calib_complete_reg_rep__4,
    init_calib_complete_reg_rep__5,
    init_calib_complete_reg_rep__6,
    init_calib_complete_reg_rep__7,
    init_calib_complete_reg_rep__8,
    init_calib_complete_reg_rep__9,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[1]_0 ,
    \po_stg2_wrcal_cnt_reg[1]_1 ,
    \po_stg2_wrcal_cnt_reg[1]_2 ,
    \po_stg2_wrcal_cnt_reg[1]_3 ,
    \po_stg2_wrcal_cnt_reg[1]_4 ,
    \po_stg2_wrcal_cnt_reg[1]_5 ,
    \po_stg2_wrcal_cnt_reg[1]_6 ,
    \po_stg2_wrcal_cnt_reg[1]_7 ,
    \po_stg2_wrcal_cnt_reg[1]_8 ,
    \po_stg2_wrcal_cnt_reg[1]_9 ,
    \po_stg2_wrcal_cnt_reg[1]_10 ,
    \po_stg2_wrcal_cnt_reg[1]_11 ,
    \po_stg2_wrcal_cnt_reg[1]_12 ,
    \po_stg2_wrcal_cnt_reg[1]_13 ,
    \po_stg2_wrcal_cnt_reg[1]_14 ,
    \po_stg2_wrcal_cnt_reg[1]_15 ,
    \po_stg2_wrcal_cnt_reg[1]_16 ,
    \po_stg2_wrcal_cnt_reg[1]_17 ,
    \po_stg2_wrcal_cnt_reg[1]_18 ,
    \po_stg2_wrcal_cnt_reg[1]_19 ,
    \po_stg2_wrcal_cnt_reg[1]_20 ,
    \po_stg2_wrcal_cnt_reg[1]_21 ,
    \po_stg2_wrcal_cnt_reg[1]_22 ,
    \po_stg2_wrcal_cnt_reg[1]_23 ,
    \po_stg2_wrcal_cnt_reg[1]_24 ,
    \po_stg2_wrcal_cnt_reg[1]_25 ,
    \po_stg2_wrcal_cnt_reg[1]_26 ,
    \po_stg2_wrcal_cnt_reg[1]_27 ,
    \po_stg2_wrcal_cnt_reg[1]_28 ,
    \po_stg2_wrcal_cnt_reg[1]_29 ,
    \po_stg2_wrcal_cnt_reg[1]_30 ,
    \po_stg2_wrcal_cnt_reg[1]_31 ,
    \po_stg2_wrcal_cnt_reg[1]_32 ,
    \po_stg2_wrcal_cnt_reg[1]_33 ,
    \po_stg2_wrcal_cnt_reg[1]_34 ,
    \po_stg2_wrcal_cnt_reg[1]_35 ,
    \po_stg2_wrcal_cnt_reg[1]_36 ,
    \po_stg2_wrcal_cnt_reg[1]_37 ,
    \po_stg2_wrcal_cnt_reg[1]_38 ,
    \po_stg2_wrcal_cnt_reg[1]_39 ,
    \po_stg2_wrcal_cnt_reg[1]_40 ,
    \po_stg2_wrcal_cnt_reg[1]_41 ,
    \po_stg2_wrcal_cnt_reg[1]_42 ,
    \po_stg2_wrcal_cnt_reg[1]_43 ,
    \po_stg2_wrcal_cnt_reg[1]_44 ,
    \po_stg2_wrcal_cnt_reg[1]_45 ,
    \po_stg2_wrcal_cnt_reg[1]_46 ,
    \po_stg2_wrcal_cnt_reg[1]_47 ,
    \po_stg2_wrcal_cnt_reg[1]_48 ,
    \po_stg2_wrcal_cnt_reg[1]_49 ,
    \po_stg2_wrcal_cnt_reg[1]_50 ,
    \po_stg2_wrcal_cnt_reg[1]_51 ,
    \po_stg2_wrcal_cnt_reg[1]_52 ,
    \po_stg2_wrcal_cnt_reg[1]_53 ,
    \po_stg2_wrcal_cnt_reg[1]_54 ,
    \po_stg2_wrcal_cnt_reg[1]_55 ,
    \po_stg2_wrcal_cnt_reg[1]_56 ,
    \po_stg2_wrcal_cnt_reg[1]_57 ,
    \po_stg2_wrcal_cnt_reg[1]_58 ,
    \po_stg2_wrcal_cnt_reg[1]_59 ,
    \po_stg2_wrcal_cnt_reg[1]_60 ,
    \po_stg2_wrcal_cnt_reg[1]_61 ,
    \po_stg2_wrcal_cnt_reg[1]_62 ,
    mux_wrdata,
    \write_buffer.wr_buf_out_data_reg[351] ,
    mux_wrdata_mask,
    \calib_sel_reg[1]_0 );
  output [3:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \pi_dqs_found_lanes_r1_reg[0] ;
  output \pi_dqs_found_lanes_r1_reg[0]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output p_134_in;
  output p_133_in;
  output p_138_in;
  output p_137_in;
  output p_142_in;
  output p_141_in;
  output p_146_in;
  output p_145_in;
  output p_150_in;
  output p_149_in;
  output p_154_in;
  output p_153_in;
  output p_158_in;
  output p_157_in;
  output p_13_in;
  output \ddr3_dm[3] ;
  output idelay_ld_rst;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output p_28_in;
  output p_27_in;
  output p_162_in;
  output p_161_in;
  output p_166_in;
  output p_165_in;
  output p_170_in;
  output p_169_in;
  output p_174_in;
  output p_173_in;
  output \ddr3_dm[2] ;
  output p_15_in;
  output p_178_in;
  output p_177_in;
  output p_182_in;
  output p_181_in;
  output p_186_in;
  output p_185_in;
  output p_190_in;
  output p_189_in;
  output [0:0]if_empty_r;
  output idelay_ld_rst_0;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output \pi_dqs_found_lanes_r1_reg[2] ;
  output p_32_in;
  output p_194_in;
  output p_193_in;
  output p_198_in;
  output p_197_in;
  output p_202_in;
  output p_201_in;
  output p_206_in;
  output p_205_in;
  output p_210_in;
  output p_209_in;
  output p_214_in;
  output p_213_in;
  output p_218_in;
  output p_217_in;
  output p_222_in;
  output p_221_in;
  output p_19_in;
  output \ddr3_dm[1] ;
  output [0:0]if_empty_r_0;
  output idelay_ld_rst_1;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output \pi_dqs_found_lanes_r1_reg[3] ;
  output \pi_dqs_found_lanes_r1_reg[3]_0 ;
  output p_226_in;
  output p_225_in;
  output p_230_in;
  output p_229_in;
  output p_234_in;
  output p_233_in;
  output p_238_in;
  output p_237_in;
  output p_242_in;
  output p_241_in;
  output p_246_in;
  output p_245_in;
  output p_250_in;
  output p_249_in;
  output p_254_in;
  output p_253_in;
  output \ddr3_dm[0] ;
  output p_21_in;
  output idelay_ld_rst_2;
  output [0:0]_phy_ctl_full_p__0;
  output rst_primitives_reg_0;
  output rst_primitives;
  output [0:0]mcGo_w__0;
  output mcGo_reg_0;
  output rclk_delay_11;
  output rd_buf_we;
  output [0:0]\my_empty_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [0:0]\my_empty_reg[0]_0 ;
  output \my_empty_reg[4]_rep__1 ;
  output \read_fifo.tail_r_reg[1] ;
  output \read_fifo.tail_r_reg[3] ;
  output [1:0]ADDRA;
  output phy_mc_data_full;
  output [0:0]\entry_cnt_reg[4] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  output \my_empty_reg[1] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \my_empty_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  output \my_empty_reg[1]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  output \my_empty_reg[1]_2 ;
  output rst_sync_r1_reg;
  output ofs_rdy_r_reg;
  output pi_phase_locked_all_r1_reg;
  output \read_fifo.tail_r_reg[0] ;
  output \read_fifo.tail_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]DIB;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [255:0]\not_strict_mode.app_rd_data_reg[479] ;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output \wr_ptr_reg[1]_0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output p_0_out;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [43:0]\my_empty_reg[7] ;
  output [43:0]\my_empty_reg[7]_0 ;
  output [43:0]\my_empty_reg[7]_1 ;
  output [43:0]\my_empty_reg[7]_2 ;
  output [8:0]\po_rdval_cnt_reg[8] ;
  output [5:0]\pi_rdval_cnt_reg[5] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  input A_pi_counter_load_en116_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable112_out;
  input A_pi_fine_inc114_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_pi_rst_dqs_find110_out;
  input sync_pulse;
  input CLK;
  input [5:0]COUNTERLOADVAL;
  input A_po_coarse_enable98_out;
  input A_po_fine_enable96_out;
  input A_po_fine_inc100_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  input A_rst_primitives_reg_0;
  input p_131_out;
  input A_idelay_ce13_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_135_out;
  input p_139_out;
  input p_143_out;
  input p_147_out;
  input p_151_out;
  input p_155_out;
  input p_159_out;
  input phy_if_reset;
  input B_pi_counter_load_en38_out;
  input \calib_sel_reg[0]_0 ;
  input B_pi_fine_enable34_out;
  input B_pi_fine_inc36_out;
  input p_29_out;
  input B_pi_rst_dqs_find32_out;
  input [5:0]\calib_zero_inputs_reg[0] ;
  input B_po_coarse_enable20_out;
  input B_po_fine_enable18_out;
  input B_po_fine_inc22_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  input A_rst_primitives_reg_1;
  input p_163_out;
  input B_idelay_ce9_out;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input p_167_out;
  input p_171_out;
  input p_175_out;
  input p_179_out;
  input p_183_out;
  input p_187_out;
  input p_191_out;
  input C_pi_counter_load_en64_out;
  input \calib_sel_reg[1] ;
  input C_pi_fine_enable60_out;
  input C_pi_fine_inc62_out;
  input p_34_out;
  input C_pi_rst_dqs_find58_out;
  input [5:0]\calib_zero_inputs_reg[0]_0 ;
  input C_po_coarse_enable46_out;
  input C_po_fine_enable44_out;
  input C_po_fine_inc48_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  input A_rst_primitives_reg_2;
  input p_195_out;
  input C_idelay_ce5_out;
  input \gen_byte_sel_div2.calib_in_common_reg_1 ;
  input p_199_out;
  input p_203_out;
  input p_207_out;
  input p_211_out;
  input p_215_out;
  input p_219_out;
  input p_223_out;
  input D_pi_counter_load_en90_out;
  input \calib_sel_reg[0]_1 ;
  input D_pi_fine_enable86_out;
  input D_pi_fine_inc88_out;
  input mc_read_idle_r_reg_0;
  input D_pi_rst_dqs_find84_out;
  input [5:0]\calib_zero_inputs_reg[0]_1 ;
  input D_po_coarse_enable72_out;
  input D_po_fine_enable70_out;
  input D_po_fine_inc74_out;
  input [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  input [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  input [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  input A_rst_primitives_reg_3;
  input p_227_out;
  input D_idelay_ce1_out;
  input \gen_byte_sel_div2.calib_in_common_reg_2 ;
  input p_231_out;
  input p_235_out;
  input p_239_out;
  input p_243_out;
  input p_247_out;
  input p_251_out;
  input p_255_out;
  input phy_ctl_mstr_empty;
  input phy_ctl_wr_i2;
  input pll_lock;
  input read_calib;
  input [0:0]sys_rst_0;
  input rstdiv0_sync_r1;
  input write_calib;
  input [10:0]Q;
  input sys_rst_1;
  input p_0_in;
  input \rclk_delay_reg[11]_0 ;
  input rst_primitives_reg_1;
  input phy_data_wr_en;
  input ram_init_done_r;
  input [0:0]if_empty_r_1;
  input [0:0]my_empty;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  input [0:0]if_empty_r_2;
  input [0:0]\my_empty_reg[3] ;
  input [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  input init_complete_r1_timing_reg;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  input [3:0]tail_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input \entry_cnt_reg[3] ;
  input \entry_cnt_reg[2] ;
  input \entry_cnt_reg[3]_0 ;
  input \my_empty_reg[0]_1 ;
  input sys_rst;
  input [0:0]iodelay_ctrl_rdy;
  input sys_rst_2;
  input [0:0]ref_dll_lock_w;
  input [0:0]\entry_cnt_reg[4]_0 ;
  input [0:0]\entry_cnt_reg[4]_1 ;
  input [0:0]\entry_cnt_reg[4]_2 ;
  input A_rst_primitives_reg_4;
  input A_rst_primitives_reg_5;
  input A_rst_primitives_reg_6;
  input A_rst_primitives_reg_7;
  input [2:0]\rd_mux_sel_r_reg[2] ;
  input \rd_mux_sel_r_reg[1] ;
  input [1:0]DIA;
  input [1:0]DIC;
  input \rd_mux_sel_r_reg[1]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  input \rd_mux_sel_r_reg[1]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  input \rd_mux_sel_r_reg[1]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  input \rd_mux_sel_r_reg[1]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  input \rd_mux_sel_r_reg[1]_4 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  input \rd_mux_sel_r_reg[1]_5 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  input \rd_mux_sel_r_reg[1]_6 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  input \rd_mux_sel_r_reg[1]_7 ;
  input \rd_mux_sel_r_reg[1]_8 ;
  input \rd_mux_sel_r_reg[1]_9 ;
  input \rd_mux_sel_r_reg[1]_10 ;
  input \rd_mux_sel_r_reg[1]_11 ;
  input \rd_mux_sel_r_reg[1]_12 ;
  input \rd_mux_sel_r_reg[1]_13 ;
  input \rd_mux_sel_r_reg[1]_14 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  input \rd_mux_sel_r_reg[1]_15 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  input \rd_mux_sel_r_reg[1]_16 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  input \rd_mux_sel_r_reg[1]_17 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  input \rd_mux_sel_r_reg[1]_18 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  input \rd_mux_sel_r_reg[1]_19 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  input \rd_mux_sel_r_reg[1]_20 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  input \rd_mux_sel_r_reg[1]_21 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  input \rd_mux_sel_r_reg[1]_22 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  input \rd_mux_sel_r_reg[1]_23 ;
  input \rd_mux_sel_r_reg[1]_24 ;
  input \rd_mux_sel_r_reg[1]_25 ;
  input \rd_mux_sel_r_reg[1]_26 ;
  input \rd_mux_sel_r_reg[1]_27 ;
  input \rd_mux_sel_r_reg[1]_28 ;
  input \rd_mux_sel_r_reg[1]_29 ;
  input \rd_mux_sel_r_reg[1]_30 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  input \rd_mux_sel_r_reg[1]_31 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  input \rd_mux_sel_r_reg[1]_32 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  input \rd_mux_sel_r_reg[1]_33 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  input \rd_mux_sel_r_reg[1]_34 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  input \rd_mux_sel_r_reg[1]_35 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  input \rd_mux_sel_r_reg[1]_36 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  input \rd_mux_sel_r_reg[1]_37 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  input \rd_mux_sel_r_reg[1]_38 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input \rd_mux_sel_r_reg[1]_39 ;
  input \rd_mux_sel_r_reg[1]_40 ;
  input \rd_mux_sel_r_reg[1]_41 ;
  input \rd_mux_sel_r_reg[1]_42 ;
  input \rd_mux_sel_r_reg[1]_43 ;
  input \rd_mux_sel_r_reg[1]_44 ;
  input \rd_mux_sel_r_reg[1]_45 ;
  input \rd_mux_sel_r_reg[1]_46 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input \rd_mux_sel_r_reg[1]_47 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  input \rd_mux_sel_r_reg[1]_48 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  input \rd_mux_sel_r_reg[1]_49 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  input \rd_mux_sel_r_reg[1]_50 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  input \rd_mux_sel_r_reg[1]_51 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  input \rd_mux_sel_r_reg[1]_52 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  input \rd_mux_sel_r_reg[1]_53 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  input \rd_mux_sel_r_reg[1]_54 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input \rd_mux_sel_r_reg[1]_55 ;
  input \rd_mux_sel_r_reg[1]_56 ;
  input \rd_mux_sel_r_reg[1]_57 ;
  input \rd_mux_sel_r_reg[1]_58 ;
  input \rd_mux_sel_r_reg[1]_59 ;
  input \rd_mux_sel_r_reg[1]_60 ;
  input \rd_mux_sel_r_reg[1]_61 ;
  input \rd_mux_sel_r_reg[1]_62 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]DOA;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  input \read_fifo.fifo_out_data_r_reg[5] ;
  input [0:0]ram_init_addr;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__3;
  input mc_wrdata_en;
  input [111:0]\write_buffer.wr_buf_out_data_reg[571] ;
  input init_calib_complete_reg_rep__4;
  input init_calib_complete_reg_rep__5;
  input init_calib_complete_reg_rep__6;
  input init_calib_complete_reg_rep__7;
  input init_calib_complete_reg_rep__8;
  input init_calib_complete_reg_rep__9;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  input [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  input \po_stg2_wrcal_cnt_reg[1] ;
  input \po_stg2_wrcal_cnt_reg[1]_0 ;
  input \po_stg2_wrcal_cnt_reg[1]_1 ;
  input \po_stg2_wrcal_cnt_reg[1]_2 ;
  input \po_stg2_wrcal_cnt_reg[1]_3 ;
  input \po_stg2_wrcal_cnt_reg[1]_4 ;
  input \po_stg2_wrcal_cnt_reg[1]_5 ;
  input \po_stg2_wrcal_cnt_reg[1]_6 ;
  input \po_stg2_wrcal_cnt_reg[1]_7 ;
  input \po_stg2_wrcal_cnt_reg[1]_8 ;
  input \po_stg2_wrcal_cnt_reg[1]_9 ;
  input \po_stg2_wrcal_cnt_reg[1]_10 ;
  input \po_stg2_wrcal_cnt_reg[1]_11 ;
  input \po_stg2_wrcal_cnt_reg[1]_12 ;
  input \po_stg2_wrcal_cnt_reg[1]_13 ;
  input \po_stg2_wrcal_cnt_reg[1]_14 ;
  input \po_stg2_wrcal_cnt_reg[1]_15 ;
  input \po_stg2_wrcal_cnt_reg[1]_16 ;
  input \po_stg2_wrcal_cnt_reg[1]_17 ;
  input \po_stg2_wrcal_cnt_reg[1]_18 ;
  input \po_stg2_wrcal_cnt_reg[1]_19 ;
  input \po_stg2_wrcal_cnt_reg[1]_20 ;
  input \po_stg2_wrcal_cnt_reg[1]_21 ;
  input \po_stg2_wrcal_cnt_reg[1]_22 ;
  input \po_stg2_wrcal_cnt_reg[1]_23 ;
  input \po_stg2_wrcal_cnt_reg[1]_24 ;
  input \po_stg2_wrcal_cnt_reg[1]_25 ;
  input \po_stg2_wrcal_cnt_reg[1]_26 ;
  input \po_stg2_wrcal_cnt_reg[1]_27 ;
  input \po_stg2_wrcal_cnt_reg[1]_28 ;
  input \po_stg2_wrcal_cnt_reg[1]_29 ;
  input \po_stg2_wrcal_cnt_reg[1]_30 ;
  input \po_stg2_wrcal_cnt_reg[1]_31 ;
  input \po_stg2_wrcal_cnt_reg[1]_32 ;
  input \po_stg2_wrcal_cnt_reg[1]_33 ;
  input \po_stg2_wrcal_cnt_reg[1]_34 ;
  input \po_stg2_wrcal_cnt_reg[1]_35 ;
  input \po_stg2_wrcal_cnt_reg[1]_36 ;
  input \po_stg2_wrcal_cnt_reg[1]_37 ;
  input \po_stg2_wrcal_cnt_reg[1]_38 ;
  input \po_stg2_wrcal_cnt_reg[1]_39 ;
  input \po_stg2_wrcal_cnt_reg[1]_40 ;
  input \po_stg2_wrcal_cnt_reg[1]_41 ;
  input \po_stg2_wrcal_cnt_reg[1]_42 ;
  input \po_stg2_wrcal_cnt_reg[1]_43 ;
  input \po_stg2_wrcal_cnt_reg[1]_44 ;
  input \po_stg2_wrcal_cnt_reg[1]_45 ;
  input \po_stg2_wrcal_cnt_reg[1]_46 ;
  input \po_stg2_wrcal_cnt_reg[1]_47 ;
  input \po_stg2_wrcal_cnt_reg[1]_48 ;
  input \po_stg2_wrcal_cnt_reg[1]_49 ;
  input \po_stg2_wrcal_cnt_reg[1]_50 ;
  input \po_stg2_wrcal_cnt_reg[1]_51 ;
  input \po_stg2_wrcal_cnt_reg[1]_52 ;
  input \po_stg2_wrcal_cnt_reg[1]_53 ;
  input \po_stg2_wrcal_cnt_reg[1]_54 ;
  input \po_stg2_wrcal_cnt_reg[1]_55 ;
  input \po_stg2_wrcal_cnt_reg[1]_56 ;
  input \po_stg2_wrcal_cnt_reg[1]_57 ;
  input \po_stg2_wrcal_cnt_reg[1]_58 ;
  input \po_stg2_wrcal_cnt_reg[1]_59 ;
  input \po_stg2_wrcal_cnt_reg[1]_60 ;
  input \po_stg2_wrcal_cnt_reg[1]_61 ;
  input \po_stg2_wrcal_cnt_reg[1]_62 ;
  input [207:0]mux_wrdata;
  input [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  input [31:0]mux_wrdata_mask;
  input [1:0]\calib_sel_reg[1]_0 ;

  wire [1:0]ADDRA;
  wire A_idelay_ce13_out;
  wire A_pi_counter_load_en116_out;
  wire [5:0]A_pi_counter_read_val;
  wire A_pi_fine_enable112_out;
  wire A_pi_fine_inc114_out;
  wire A_pi_rst_dqs_find110_out;
  wire A_po_coarse_enable98_out;
  wire [8:0]A_po_counter_read_val;
  wire A_po_fine_enable96_out;
  wire A_po_fine_inc100_out;
  wire A_rst_primitives;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire A_rst_primitives_reg_7;
  wire B_byte_rd_en;
  wire B_idelay_ce9_out;
  wire B_pi_counter_load_en38_out;
  wire [5:0]B_pi_counter_read_val;
  wire B_pi_fine_enable34_out;
  wire B_pi_fine_inc36_out;
  wire B_pi_rst_dqs_find32_out;
  wire B_po_coarse_enable20_out;
  wire [8:0]B_po_counter_read_val;
  wire B_po_fine_enable18_out;
  wire B_po_fine_inc22_out;
  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire C_byte_rd_en;
  wire C_idelay_ce5_out;
  wire C_pi_counter_load_en64_out;
  wire [5:0]C_pi_counter_read_val;
  wire C_pi_fine_enable60_out;
  wire C_pi_fine_inc62_out;
  wire C_pi_rst_dqs_find58_out;
  wire C_po_coarse_enable46_out;
  wire [8:0]C_po_counter_read_val;
  wire C_po_fine_enable44_out;
  wire C_po_fine_inc48_out;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire D_idelay_ce1_out;
  wire D_pi_counter_load_en90_out;
  wire D_pi_fine_enable86_out;
  wire D_pi_fine_inc88_out;
  wire D_pi_rst_dqs_find84_out;
  wire D_po_coarse_enable72_out;
  wire D_po_fine_enable70_out;
  wire D_po_fine_inc74_out;
  wire [10:0]Q;
  wire [0:0]_phy_ctl_full_p__0;
  wire \calib_sel_reg[0] ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[0]_1 ;
  wire \calib_sel_reg[1] ;
  wire [1:0]\calib_sel_reg[1]_0 ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[0] ;
  wire [5:0]\calib_zero_inputs_reg[0]_0 ;
  wire [5:0]\calib_zero_inputs_reg[0]_1 ;
  wire \ddr3_dm[0] ;
  wire \ddr3_dm[1] ;
  wire \ddr3_dm[2] ;
  wire \ddr3_dm[3] ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A_n_2 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A_n_46 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_42 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_204 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_205 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_206 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_207 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_208 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_209 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_210 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_211 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_212 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_213 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_214 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_215 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_216 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_217 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_218 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_27 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_38 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_5 ;
  wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_7 ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_8 ;
  wire \entry_cnt_reg[2] ;
  wire \entry_cnt_reg[3] ;
  wire \entry_cnt_reg[3]_0 ;
  wire [0:0]\entry_cnt_reg[4] ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire [0:0]\entry_cnt_reg[4]_1 ;
  wire [0:0]\entry_cnt_reg[4]_2 ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_2;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_r_1;
  wire [0:0]if_empty_r_2;
  wire [3:3]if_empty_r_3;
  wire [3:3]if_empty_r_9;
  wire init_calib_complete_reg_rep__3;
  wire init_calib_complete_reg_rep__4;
  wire init_calib_complete_reg_rep__5;
  wire init_calib_complete_reg_rep__6;
  wire init_calib_complete_reg_rep__7;
  wire init_calib_complete_reg_rep__8;
  wire init_calib_complete_reg_rep__9;
  wire init_complete_r1_timing_reg;
  wire [0:0]iodelay_ctrl_rdy;
  wire mcGo_reg_0;
  wire [0:0]mcGo_w__0;
  wire mc_read_idle_r_reg;
  wire mc_read_idle_r_reg_0;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire [207:0]mux_wrdata;
  wire [31:0]mux_wrdata_mask;
  wire [0:0]my_empty;
  wire [0:0]\my_empty_reg[0] ;
  wire [0:0]\my_empty_reg[0]_0 ;
  wire \my_empty_reg[0]_1 ;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire [0:0]\my_empty_reg[3] ;
  wire \my_empty_reg[4]_rep__1 ;
  wire [43:0]\my_empty_reg[7] ;
  wire [43:0]\my_empty_reg[7]_0 ;
  wire [43:0]\my_empty_reg[7]_1 ;
  wire [43:0]\my_empty_reg[7]_2 ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [255:0]\not_strict_mode.app_rd_data_reg[479] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  wire [3:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_4 ;
  wire [4:4]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ;
  wire ofs_rdy_r_reg;
  wire p_0_in;
  wire p_0_out;
  wire p_131_out;
  wire p_133_in;
  wire p_134_in;
  wire p_135_out;
  wire p_137_in;
  wire p_138_in;
  wire p_139_out;
  wire p_13_in;
  wire p_141_in;
  wire p_142_in;
  wire p_143_out;
  wire p_145_in;
  wire p_146_in;
  wire p_147_out;
  wire p_149_in;
  wire p_150_in;
  wire p_151_out;
  wire p_153_in;
  wire p_154_in;
  wire p_155_out;
  wire p_157_in;
  wire p_158_in;
  wire p_159_out;
  wire p_15_in;
  wire p_161_in;
  wire p_162_in;
  wire p_163_out;
  wire p_165_in;
  wire p_166_in;
  wire p_167_out;
  wire p_169_in;
  wire p_170_in;
  wire p_171_out;
  wire p_173_in;
  wire p_174_in;
  wire p_175_out;
  wire p_177_in;
  wire p_178_in;
  wire p_179_out;
  wire p_181_in;
  wire p_182_in;
  wire p_183_out;
  wire p_185_in;
  wire p_186_in;
  wire p_187_out;
  wire p_189_in;
  wire p_190_in;
  wire p_191_out;
  wire p_193_in;
  wire p_194_in;
  wire p_195_out;
  wire p_197_in;
  wire p_198_in;
  wire p_199_out;
  wire p_19_in;
  wire p_201_in;
  wire p_202_in;
  wire p_203_out;
  wire p_205_in;
  wire p_206_in;
  wire p_207_out;
  wire p_209_in;
  wire p_210_in;
  wire p_211_out;
  wire p_213_in;
  wire p_214_in;
  wire p_215_out;
  wire p_217_in;
  wire p_218_in;
  wire p_219_out;
  wire p_21_in;
  wire p_221_in;
  wire p_222_in;
  wire p_223_out;
  wire p_225_in;
  wire p_226_in;
  wire p_227_out;
  wire p_229_in;
  wire p_230_in;
  wire p_231_out;
  wire p_233_in;
  wire p_234_in;
  wire p_235_out;
  wire p_237_in;
  wire p_238_in;
  wire p_239_out;
  wire p_241_in;
  wire p_242_in;
  wire p_243_out;
  wire p_245_in;
  wire p_246_in;
  wire p_247_out;
  wire p_249_in;
  wire p_250_in;
  wire p_251_out;
  wire p_253_in;
  wire p_254_in;
  wire p_255_out;
  wire p_27_in;
  wire p_28_in;
  wire p_29_out;
  wire p_32_in;
  wire p_34_out;
  wire [15:0]phaser_ctl_bus;
  wire phy_control_i_n_0;
  wire phy_control_i_n_1;
  wire phy_control_i_n_14;
  wire phy_control_i_n_15;
  wire phy_control_i_n_16;
  wire phy_control_i_n_17;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_wr_i2;
  wire phy_data_wr_en;
  wire [1:0]phy_encalib;
  wire phy_if_reset;
  wire phy_mc_data_full;
  wire [3:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire [5:0]\pi_rdval_cnt_reg[5] ;
  wire pll_lock;
  wire [8:0]\po_rdval_cnt_reg[8] ;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[1]_0 ;
  wire \po_stg2_wrcal_cnt_reg[1]_1 ;
  wire \po_stg2_wrcal_cnt_reg[1]_10 ;
  wire \po_stg2_wrcal_cnt_reg[1]_11 ;
  wire \po_stg2_wrcal_cnt_reg[1]_12 ;
  wire \po_stg2_wrcal_cnt_reg[1]_13 ;
  wire \po_stg2_wrcal_cnt_reg[1]_14 ;
  wire \po_stg2_wrcal_cnt_reg[1]_15 ;
  wire \po_stg2_wrcal_cnt_reg[1]_16 ;
  wire \po_stg2_wrcal_cnt_reg[1]_17 ;
  wire \po_stg2_wrcal_cnt_reg[1]_18 ;
  wire \po_stg2_wrcal_cnt_reg[1]_19 ;
  wire \po_stg2_wrcal_cnt_reg[1]_2 ;
  wire \po_stg2_wrcal_cnt_reg[1]_20 ;
  wire \po_stg2_wrcal_cnt_reg[1]_21 ;
  wire \po_stg2_wrcal_cnt_reg[1]_22 ;
  wire \po_stg2_wrcal_cnt_reg[1]_23 ;
  wire \po_stg2_wrcal_cnt_reg[1]_24 ;
  wire \po_stg2_wrcal_cnt_reg[1]_25 ;
  wire \po_stg2_wrcal_cnt_reg[1]_26 ;
  wire \po_stg2_wrcal_cnt_reg[1]_27 ;
  wire \po_stg2_wrcal_cnt_reg[1]_28 ;
  wire \po_stg2_wrcal_cnt_reg[1]_29 ;
  wire \po_stg2_wrcal_cnt_reg[1]_3 ;
  wire \po_stg2_wrcal_cnt_reg[1]_30 ;
  wire \po_stg2_wrcal_cnt_reg[1]_31 ;
  wire \po_stg2_wrcal_cnt_reg[1]_32 ;
  wire \po_stg2_wrcal_cnt_reg[1]_33 ;
  wire \po_stg2_wrcal_cnt_reg[1]_34 ;
  wire \po_stg2_wrcal_cnt_reg[1]_35 ;
  wire \po_stg2_wrcal_cnt_reg[1]_36 ;
  wire \po_stg2_wrcal_cnt_reg[1]_37 ;
  wire \po_stg2_wrcal_cnt_reg[1]_38 ;
  wire \po_stg2_wrcal_cnt_reg[1]_39 ;
  wire \po_stg2_wrcal_cnt_reg[1]_4 ;
  wire \po_stg2_wrcal_cnt_reg[1]_40 ;
  wire \po_stg2_wrcal_cnt_reg[1]_41 ;
  wire \po_stg2_wrcal_cnt_reg[1]_42 ;
  wire \po_stg2_wrcal_cnt_reg[1]_43 ;
  wire \po_stg2_wrcal_cnt_reg[1]_44 ;
  wire \po_stg2_wrcal_cnt_reg[1]_45 ;
  wire \po_stg2_wrcal_cnt_reg[1]_46 ;
  wire \po_stg2_wrcal_cnt_reg[1]_47 ;
  wire \po_stg2_wrcal_cnt_reg[1]_48 ;
  wire \po_stg2_wrcal_cnt_reg[1]_49 ;
  wire \po_stg2_wrcal_cnt_reg[1]_5 ;
  wire \po_stg2_wrcal_cnt_reg[1]_50 ;
  wire \po_stg2_wrcal_cnt_reg[1]_51 ;
  wire \po_stg2_wrcal_cnt_reg[1]_52 ;
  wire \po_stg2_wrcal_cnt_reg[1]_53 ;
  wire \po_stg2_wrcal_cnt_reg[1]_54 ;
  wire \po_stg2_wrcal_cnt_reg[1]_55 ;
  wire \po_stg2_wrcal_cnt_reg[1]_56 ;
  wire \po_stg2_wrcal_cnt_reg[1]_57 ;
  wire \po_stg2_wrcal_cnt_reg[1]_58 ;
  wire \po_stg2_wrcal_cnt_reg[1]_59 ;
  wire \po_stg2_wrcal_cnt_reg[1]_6 ;
  wire \po_stg2_wrcal_cnt_reg[1]_60 ;
  wire \po_stg2_wrcal_cnt_reg[1]_61 ;
  wire \po_stg2_wrcal_cnt_reg[1]_62 ;
  wire \po_stg2_wrcal_cnt_reg[1]_7 ;
  wire \po_stg2_wrcal_cnt_reg[1]_8 ;
  wire \po_stg2_wrcal_cnt_reg[1]_9 ;
  wire [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire [0:0]ram_init_addr;
  wire ram_init_done_r;
  wire rclk_;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_n_0 ;
  wire \rclk_delay_reg[11]_0 ;
  wire rd_buf_we;
  wire \rd_mux_sel_r_reg[1] ;
  wire \rd_mux_sel_r_reg[1]_0 ;
  wire \rd_mux_sel_r_reg[1]_1 ;
  wire \rd_mux_sel_r_reg[1]_10 ;
  wire \rd_mux_sel_r_reg[1]_11 ;
  wire \rd_mux_sel_r_reg[1]_12 ;
  wire \rd_mux_sel_r_reg[1]_13 ;
  wire \rd_mux_sel_r_reg[1]_14 ;
  wire \rd_mux_sel_r_reg[1]_15 ;
  wire \rd_mux_sel_r_reg[1]_16 ;
  wire \rd_mux_sel_r_reg[1]_17 ;
  wire \rd_mux_sel_r_reg[1]_18 ;
  wire \rd_mux_sel_r_reg[1]_19 ;
  wire \rd_mux_sel_r_reg[1]_2 ;
  wire \rd_mux_sel_r_reg[1]_20 ;
  wire \rd_mux_sel_r_reg[1]_21 ;
  wire \rd_mux_sel_r_reg[1]_22 ;
  wire \rd_mux_sel_r_reg[1]_23 ;
  wire \rd_mux_sel_r_reg[1]_24 ;
  wire \rd_mux_sel_r_reg[1]_25 ;
  wire \rd_mux_sel_r_reg[1]_26 ;
  wire \rd_mux_sel_r_reg[1]_27 ;
  wire \rd_mux_sel_r_reg[1]_28 ;
  wire \rd_mux_sel_r_reg[1]_29 ;
  wire \rd_mux_sel_r_reg[1]_3 ;
  wire \rd_mux_sel_r_reg[1]_30 ;
  wire \rd_mux_sel_r_reg[1]_31 ;
  wire \rd_mux_sel_r_reg[1]_32 ;
  wire \rd_mux_sel_r_reg[1]_33 ;
  wire \rd_mux_sel_r_reg[1]_34 ;
  wire \rd_mux_sel_r_reg[1]_35 ;
  wire \rd_mux_sel_r_reg[1]_36 ;
  wire \rd_mux_sel_r_reg[1]_37 ;
  wire \rd_mux_sel_r_reg[1]_38 ;
  wire \rd_mux_sel_r_reg[1]_39 ;
  wire \rd_mux_sel_r_reg[1]_4 ;
  wire \rd_mux_sel_r_reg[1]_40 ;
  wire \rd_mux_sel_r_reg[1]_41 ;
  wire \rd_mux_sel_r_reg[1]_42 ;
  wire \rd_mux_sel_r_reg[1]_43 ;
  wire \rd_mux_sel_r_reg[1]_44 ;
  wire \rd_mux_sel_r_reg[1]_45 ;
  wire \rd_mux_sel_r_reg[1]_46 ;
  wire \rd_mux_sel_r_reg[1]_47 ;
  wire \rd_mux_sel_r_reg[1]_48 ;
  wire \rd_mux_sel_r_reg[1]_49 ;
  wire \rd_mux_sel_r_reg[1]_5 ;
  wire \rd_mux_sel_r_reg[1]_50 ;
  wire \rd_mux_sel_r_reg[1]_51 ;
  wire \rd_mux_sel_r_reg[1]_52 ;
  wire \rd_mux_sel_r_reg[1]_53 ;
  wire \rd_mux_sel_r_reg[1]_54 ;
  wire \rd_mux_sel_r_reg[1]_55 ;
  wire \rd_mux_sel_r_reg[1]_56 ;
  wire \rd_mux_sel_r_reg[1]_57 ;
  wire \rd_mux_sel_r_reg[1]_58 ;
  wire \rd_mux_sel_r_reg[1]_59 ;
  wire \rd_mux_sel_r_reg[1]_6 ;
  wire \rd_mux_sel_r_reg[1]_60 ;
  wire \rd_mux_sel_r_reg[1]_61 ;
  wire \rd_mux_sel_r_reg[1]_62 ;
  wire \rd_mux_sel_r_reg[1]_7 ;
  wire \rd_mux_sel_r_reg[1]_8 ;
  wire \rd_mux_sel_r_reg[1]_9 ;
  wire [2:0]\rd_mux_sel_r_reg[2] ;
  wire read_calib;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[6] ;
  wire \read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire \read_fifo.tail_r_reg[3] ;
  wire [0:0]ref_dll_lock_w;
  wire [0:0]ref_dll_lock_w__0;
  wire rst_primitives;
  wire rst_primitives_reg_0;
  wire rst_primitives_reg_1;
  wire rst_r4;
  wire rst_sync_r1_reg;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sync_pulse;
  wire sys_rst;
  wire [0:0]sys_rst_0;
  wire sys_rst_1;
  wire sys_rst_2;
  wire [3:0]tail_r;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[384] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[388] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[392] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[396] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[400] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[404] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[408] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[412] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[449] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[450] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[451] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[453] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[454] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[455] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[457] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[458] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[459] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[461] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[462] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[463] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[465] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[466] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[467] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[469] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[470] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[471] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[473] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[474] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[475] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[477] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[478] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[479] ;
  wire [111:0]\write_buffer.wr_buf_out_data_reg[571] ;
  wire write_calib;

  FDRE #(
    .INIT(1'b0)) 
    A_rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_primitives),
        .Q(A_rst_primitives),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane_7 \ddr_byte_lane_A.ddr_byte_lane_A 
       (.ADDRA(ADDRA),
        .A_idelay_ce13_out(A_idelay_ce13_out),
        .A_pi_counter_load_en116_out(A_pi_counter_load_en116_out),
        .A_pi_fine_enable112_out(A_pi_fine_enable112_out),
        .A_pi_fine_inc114_out(A_pi_fine_inc114_out),
        .A_pi_rst_dqs_find110_out(A_pi_rst_dqs_find110_out),
        .A_po_coarse_enable98_out(A_po_coarse_enable98_out),
        .A_po_fine_enable96_out(A_po_fine_enable96_out),
        .A_po_fine_inc100_out(A_po_fine_inc100_out),
        .A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_0),
        .CLK(CLK),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .COUNTERREADVAL(A_pi_counter_read_val),
        .PCENABLECALIB(phy_encalib),
        .Q(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\calib_sel_reg[0] (\calib_sel_reg[0] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\ddr3_dm[3] (\ddr3_dm[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (if_empty_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 (if_empty_r_0),
        .\entry_cnt_reg[4] (\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ),
        .\entry_cnt_reg[4]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_4 [4]),
        .\entry_cnt_reg[4]_1 (\entry_cnt_reg[4]_0 ),
        .\entry_cnt_reg[4]_2 (\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ),
        .\entry_cnt_reg[4]_3 (\entry_cnt_reg[4]_1 ),
        .\entry_cnt_reg[4]_4 (\entry_cnt_reg[4]_2 ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (\gen_rd[3].rd_data_rise_wl_r_reg[3] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .if_empty_r(if_empty_r_3),
        .if_empty_r_0(if_empty_r_9),
        .if_empty_r_1(if_empty_r_1),
        .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3),
        .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .mc_read_idle_r_reg(mc_read_idle_r_reg),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .my_empty(my_empty),
        .\my_empty_reg[0] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_8 ),
        .\my_empty_reg[0]_0 (\my_empty_reg[0]_1 ),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[3] (\ddr_byte_lane_D.ddr_byte_lane_D_n_27 ),
        .\my_empty_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_5 ),
        .\my_empty_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_7 ),
        .\my_empty_reg[4]_rep__1 (\ddr_byte_lane_A.ddr_byte_lane_A_n_46 ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ),
        .\not_strict_mode.app_rd_data_reg[479] ({\not_strict_mode.app_rd_data_reg[479] [255:248],\not_strict_mode.app_rd_data_reg[479] [223:216],\not_strict_mode.app_rd_data_reg[479] [191:184],\not_strict_mode.app_rd_data_reg[479] [159:152],\not_strict_mode.app_rd_data_reg[479] [127:120],\not_strict_mode.app_rd_data_reg[479] [95:88],\not_strict_mode.app_rd_data_reg[479] [63:56],\not_strict_mode.app_rd_data_reg[479] [31:24]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .p_131_out(p_131_out),
        .p_133_in(p_133_in),
        .p_134_in(p_134_in),
        .p_135_out(p_135_out),
        .p_137_in(p_137_in),
        .p_138_in(p_138_in),
        .p_139_out(p_139_out),
        .p_13_in(p_13_in),
        .p_141_in(p_141_in),
        .p_142_in(p_142_in),
        .p_143_out(p_143_out),
        .p_145_in(p_145_in),
        .p_146_in(p_146_in),
        .p_147_out(p_147_out),
        .p_149_in(p_149_in),
        .p_150_in(p_150_in),
        .p_151_out(p_151_out),
        .p_153_in(p_153_in),
        .p_154_in(p_154_in),
        .p_155_out(p_155_out),
        .p_157_in(p_157_in),
        .p_158_in(p_158_in),
        .p_159_out(p_159_out),
        .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[200],mux_wrdata[168],mux_wrdata[138],mux_wrdata[114],mux_wrdata[90],mux_wrdata[66],mux_wrdata[40],\write_buffer.wr_buf_out_data_reg[351] [12],mux_wrdata[201],mux_wrdata[169],mux_wrdata[139],mux_wrdata[115],mux_wrdata[91],\write_buffer.wr_buf_out_data_reg[351] [22],mux_wrdata[41],mux_wrdata[12],mux_wrdata[202],mux_wrdata[170],mux_wrdata[140],\write_buffer.wr_buf_out_data_reg[351] [38],\write_buffer.wr_buf_out_data_reg[351] [30],mux_wrdata[67],mux_wrdata[42],mux_wrdata[13],mux_wrdata[203],mux_wrdata[171],\write_buffer.wr_buf_out_data_reg[351] [46],mux_wrdata[116],mux_wrdata[92],mux_wrdata[68],mux_wrdata[43],\write_buffer.wr_buf_out_data_reg[351] [13],mux_wrdata[204],mux_wrdata[172],mux_wrdata[141],mux_wrdata[117],mux_wrdata[93],mux_wrdata[69],mux_wrdata[44],\write_buffer.wr_buf_out_data_reg[351] [14],mux_wrdata[205],mux_wrdata[173],mux_wrdata[142],mux_wrdata[118],mux_wrdata[94],\write_buffer.wr_buf_out_data_reg[351] [23],mux_wrdata[45],mux_wrdata[14],mux_wrdata[206],mux_wrdata[174],mux_wrdata[143],\write_buffer.wr_buf_out_data_reg[351] [39],\write_buffer.wr_buf_out_data_reg[351] [31],mux_wrdata[70],mux_wrdata[46],mux_wrdata[15],mux_wrdata[207],mux_wrdata[175],\write_buffer.wr_buf_out_data_reg[351] [47],mux_wrdata[119],mux_wrdata[95],mux_wrdata[71],mux_wrdata[47],\write_buffer.wr_buf_out_data_reg[351] [15]}),
        .phy_if_reset(phy_if_reset),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[0]),
        .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0] ),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .pi_phase_locked_all_r1_reg(\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ),
        .\po_counter_read_val_reg[8] (A_po_counter_read_val),
        .ram_init_addr(ram_init_addr),
        .ram_init_done_r(ram_init_done_r),
        .rd_buf_we(rd_buf_we),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.fifo_out_data_r_reg[6] (\read_fifo.fifo_out_data_r_reg[6] ),
        .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1]_0 ),
        .\read_fifo.tail_r_reg[3] (\read_fifo.tail_r_reg[3] ),
        .rst_r4(rst_r4),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sync_pulse(sync_pulse),
        .tail_r(tail_r),
        .\write_buffer.wr_buf_out_data_reg[408] (\write_buffer.wr_buf_out_data_reg[408] ),
        .\write_buffer.wr_buf_out_data_reg[412] (\write_buffer.wr_buf_out_data_reg[412] ),
        .\write_buffer.wr_buf_out_data_reg[473] (\write_buffer.wr_buf_out_data_reg[473] ),
        .\write_buffer.wr_buf_out_data_reg[474] (\write_buffer.wr_buf_out_data_reg[474] ),
        .\write_buffer.wr_buf_out_data_reg[475] (\write_buffer.wr_buf_out_data_reg[475] ),
        .\write_buffer.wr_buf_out_data_reg[477] (\write_buffer.wr_buf_out_data_reg[477] ),
        .\write_buffer.wr_buf_out_data_reg[478] (\write_buffer.wr_buf_out_data_reg[478] ),
        .\write_buffer.wr_buf_out_data_reg[479] (\write_buffer.wr_buf_out_data_reg[479] ),
        .\write_buffer.wr_buf_out_data_reg[571] ({\write_buffer.wr_buf_out_data_reg[571] [111],\write_buffer.wr_buf_out_data_reg[571] [107],\write_buffer.wr_buf_out_data_reg[571] [103],\write_buffer.wr_buf_out_data_reg[571] [99],\write_buffer.wr_buf_out_data_reg[571] [95],\write_buffer.wr_buf_out_data_reg[571] [91],\write_buffer.wr_buf_out_data_reg[571] [87],\write_buffer.wr_buf_out_data_reg[571] [83],\write_buffer.wr_buf_out_data_reg[571] [79:78],\write_buffer.wr_buf_out_data_reg[571] [71:70],\write_buffer.wr_buf_out_data_reg[571] [63:60],\write_buffer.wr_buf_out_data_reg[571] [47:46],\write_buffer.wr_buf_out_data_reg[571] [39:38],\write_buffer.wr_buf_out_data_reg[571] [31:28],\write_buffer.wr_buf_out_data_reg[571] [15:12]}));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0 \ddr_byte_lane_B.ddr_byte_lane_B 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_1),
        .B_byte_rd_en(B_byte_rd_en),
        .B_idelay_ce9_out(B_idelay_ce9_out),
        .B_pi_counter_load_en38_out(B_pi_counter_load_en38_out),
        .B_pi_fine_enable34_out(B_pi_fine_enable34_out),
        .B_pi_fine_inc36_out(B_pi_fine_inc36_out),
        .B_pi_rst_dqs_find32_out(B_pi_rst_dqs_find32_out),
        .B_po_coarse_enable20_out(B_po_coarse_enable20_out),
        .B_po_fine_enable18_out(B_po_fine_enable18_out),
        .B_po_fine_inc22_out(B_po_fine_inc22_out),
        .CLK(CLK),
        .COUNTERREADVAL(B_pi_counter_read_val),
        .C_byte_rd_en(C_byte_rd_en),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .PCENABLECALIB(phy_encalib),
        .Q({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_5 ,\my_empty_reg[0]_0 }),
        .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0] ),
        .\ddr3_dm[2] (\ddr3_dm[2] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\wr_ptr_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\entry_cnt_reg[4] (\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_4 ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (\gen_rd[2].rd_data_rise_wl_r_reg[2] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4),
        .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),
        .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_0 ),
        .\my_full_reg[0] (if_empty_r),
        .\not_strict_mode.app_rd_data_reg[471] ({\not_strict_mode.app_rd_data_reg[479] [247:240],\not_strict_mode.app_rd_data_reg[479] [215:208],\not_strict_mode.app_rd_data_reg[479] [183:176],\not_strict_mode.app_rd_data_reg[479] [151:144],\not_strict_mode.app_rd_data_reg[479] [119:112],\not_strict_mode.app_rd_data_reg[479] [87:80],\not_strict_mode.app_rd_data_reg[479] [55:48],\not_strict_mode.app_rd_data_reg[479] [23:16]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),
        .p_0_out(p_0_out),
        .p_15_in(p_15_in),
        .p_161_in(p_161_in),
        .p_162_in(p_162_in),
        .p_163_out(p_163_out),
        .p_165_in(p_165_in),
        .p_166_in(p_166_in),
        .p_167_out(p_167_out),
        .p_169_in(p_169_in),
        .p_170_in(p_170_in),
        .p_171_out(p_171_out),
        .p_173_in(p_173_in),
        .p_174_in(p_174_in),
        .p_175_out(p_175_out),
        .p_177_in(p_177_in),
        .p_178_in(p_178_in),
        .p_179_out(p_179_out),
        .p_181_in(p_181_in),
        .p_182_in(p_182_in),
        .p_183_out(p_183_out),
        .p_185_in(p_185_in),
        .p_186_in(p_186_in),
        .p_187_out(p_187_out),
        .p_189_in(p_189_in),
        .p_190_in(p_190_in),
        .p_191_out(p_191_out),
        .p_27_in(p_27_in),
        .p_28_in(p_28_in),
        .p_29_out(p_29_out),
        .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_wrdata[192],mux_wrdata[160],mux_wrdata[132],mux_wrdata[108],mux_wrdata[84],mux_wrdata[60],mux_wrdata[32],\write_buffer.wr_buf_out_data_reg[351] [8],mux_wrdata[193],mux_wrdata[161],mux_wrdata[133],mux_wrdata[109],mux_wrdata[85],\write_buffer.wr_buf_out_data_reg[351] [20],mux_wrdata[33],mux_wrdata[8],mux_wrdata[194],mux_wrdata[162],mux_wrdata[134],\write_buffer.wr_buf_out_data_reg[351] [36],\write_buffer.wr_buf_out_data_reg[351] [28],mux_wrdata[61],mux_wrdata[34],mux_wrdata[9],mux_wrdata[195],mux_wrdata[163],\write_buffer.wr_buf_out_data_reg[351] [44],mux_wrdata[110],mux_wrdata[86],mux_wrdata[62],mux_wrdata[35],\write_buffer.wr_buf_out_data_reg[351] [9],mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[196],mux_wrdata[164],mux_wrdata[135],mux_wrdata[111],mux_wrdata[87],mux_wrdata[63],mux_wrdata[36],\write_buffer.wr_buf_out_data_reg[351] [10],mux_wrdata[197],mux_wrdata[165],mux_wrdata[136],mux_wrdata[112],mux_wrdata[88],\write_buffer.wr_buf_out_data_reg[351] [21],mux_wrdata[37],mux_wrdata[10],mux_wrdata[198],mux_wrdata[166],mux_wrdata[137],\write_buffer.wr_buf_out_data_reg[351] [37],\write_buffer.wr_buf_out_data_reg[351] [29],mux_wrdata[64],mux_wrdata[38],mux_wrdata[11],mux_wrdata[199],mux_wrdata[167],\write_buffer.wr_buf_out_data_reg[351] [45],mux_wrdata[113],mux_wrdata[89],mux_wrdata[65],mux_wrdata[39],\write_buffer.wr_buf_out_data_reg[351] [11]}),
        .phy_if_reset(phy_if_reset),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[1]),
        .pi_phase_locked_all_r1_reg(\ddr_byte_lane_B.ddr_byte_lane_B_n_2 ),
        .\po_counter_read_val_reg[8] (B_po_counter_read_val),
        .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ),
        .\po_stg2_wrcal_cnt_reg[1]_0 (\po_stg2_wrcal_cnt_reg[1]_0 ),
        .\po_stg2_wrcal_cnt_reg[1]_1 (\po_stg2_wrcal_cnt_reg[1]_1 ),
        .\po_stg2_wrcal_cnt_reg[1]_10 (\po_stg2_wrcal_cnt_reg[1]_10 ),
        .\po_stg2_wrcal_cnt_reg[1]_11 (\po_stg2_wrcal_cnt_reg[1]_11 ),
        .\po_stg2_wrcal_cnt_reg[1]_12 (\po_stg2_wrcal_cnt_reg[1]_12 ),
        .\po_stg2_wrcal_cnt_reg[1]_13 (\po_stg2_wrcal_cnt_reg[1]_13 ),
        .\po_stg2_wrcal_cnt_reg[1]_14 (\po_stg2_wrcal_cnt_reg[1]_14 ),
        .\po_stg2_wrcal_cnt_reg[1]_15 (\po_stg2_wrcal_cnt_reg[1]_15 ),
        .\po_stg2_wrcal_cnt_reg[1]_16 (\po_stg2_wrcal_cnt_reg[1]_16 ),
        .\po_stg2_wrcal_cnt_reg[1]_17 (\po_stg2_wrcal_cnt_reg[1]_17 ),
        .\po_stg2_wrcal_cnt_reg[1]_18 (\po_stg2_wrcal_cnt_reg[1]_18 ),
        .\po_stg2_wrcal_cnt_reg[1]_19 (\po_stg2_wrcal_cnt_reg[1]_19 ),
        .\po_stg2_wrcal_cnt_reg[1]_2 (\po_stg2_wrcal_cnt_reg[1]_2 ),
        .\po_stg2_wrcal_cnt_reg[1]_20 (\po_stg2_wrcal_cnt_reg[1]_20 ),
        .\po_stg2_wrcal_cnt_reg[1]_21 (\po_stg2_wrcal_cnt_reg[1]_21 ),
        .\po_stg2_wrcal_cnt_reg[1]_22 (\po_stg2_wrcal_cnt_reg[1]_22 ),
        .\po_stg2_wrcal_cnt_reg[1]_23 (\po_stg2_wrcal_cnt_reg[1]_23 ),
        .\po_stg2_wrcal_cnt_reg[1]_24 (\po_stg2_wrcal_cnt_reg[1]_24 ),
        .\po_stg2_wrcal_cnt_reg[1]_25 (\po_stg2_wrcal_cnt_reg[1]_25 ),
        .\po_stg2_wrcal_cnt_reg[1]_26 (\po_stg2_wrcal_cnt_reg[1]_26 ),
        .\po_stg2_wrcal_cnt_reg[1]_27 (\po_stg2_wrcal_cnt_reg[1]_27 ),
        .\po_stg2_wrcal_cnt_reg[1]_28 (\po_stg2_wrcal_cnt_reg[1]_28 ),
        .\po_stg2_wrcal_cnt_reg[1]_29 (\po_stg2_wrcal_cnt_reg[1]_29 ),
        .\po_stg2_wrcal_cnt_reg[1]_3 (\po_stg2_wrcal_cnt_reg[1]_3 ),
        .\po_stg2_wrcal_cnt_reg[1]_30 (\po_stg2_wrcal_cnt_reg[1]_30 ),
        .\po_stg2_wrcal_cnt_reg[1]_31 (\po_stg2_wrcal_cnt_reg[1]_31 ),
        .\po_stg2_wrcal_cnt_reg[1]_32 (\po_stg2_wrcal_cnt_reg[1]_32 ),
        .\po_stg2_wrcal_cnt_reg[1]_33 (\po_stg2_wrcal_cnt_reg[1]_33 ),
        .\po_stg2_wrcal_cnt_reg[1]_34 (\po_stg2_wrcal_cnt_reg[1]_34 ),
        .\po_stg2_wrcal_cnt_reg[1]_35 (\po_stg2_wrcal_cnt_reg[1]_35 ),
        .\po_stg2_wrcal_cnt_reg[1]_36 (\po_stg2_wrcal_cnt_reg[1]_36 ),
        .\po_stg2_wrcal_cnt_reg[1]_37 (\po_stg2_wrcal_cnt_reg[1]_37 ),
        .\po_stg2_wrcal_cnt_reg[1]_38 (\po_stg2_wrcal_cnt_reg[1]_38 ),
        .\po_stg2_wrcal_cnt_reg[1]_39 (\po_stg2_wrcal_cnt_reg[1]_39 ),
        .\po_stg2_wrcal_cnt_reg[1]_4 (\po_stg2_wrcal_cnt_reg[1]_4 ),
        .\po_stg2_wrcal_cnt_reg[1]_40 (\po_stg2_wrcal_cnt_reg[1]_40 ),
        .\po_stg2_wrcal_cnt_reg[1]_41 (\po_stg2_wrcal_cnt_reg[1]_41 ),
        .\po_stg2_wrcal_cnt_reg[1]_42 (\po_stg2_wrcal_cnt_reg[1]_42 ),
        .\po_stg2_wrcal_cnt_reg[1]_43 (\po_stg2_wrcal_cnt_reg[1]_43 ),
        .\po_stg2_wrcal_cnt_reg[1]_44 (\po_stg2_wrcal_cnt_reg[1]_44 ),
        .\po_stg2_wrcal_cnt_reg[1]_45 (\po_stg2_wrcal_cnt_reg[1]_45 ),
        .\po_stg2_wrcal_cnt_reg[1]_46 (\po_stg2_wrcal_cnt_reg[1]_46 ),
        .\po_stg2_wrcal_cnt_reg[1]_47 (\po_stg2_wrcal_cnt_reg[1]_47 ),
        .\po_stg2_wrcal_cnt_reg[1]_48 (\po_stg2_wrcal_cnt_reg[1]_48 ),
        .\po_stg2_wrcal_cnt_reg[1]_49 (\po_stg2_wrcal_cnt_reg[1]_49 ),
        .\po_stg2_wrcal_cnt_reg[1]_5 (\po_stg2_wrcal_cnt_reg[1]_5 ),
        .\po_stg2_wrcal_cnt_reg[1]_50 (\po_stg2_wrcal_cnt_reg[1]_50 ),
        .\po_stg2_wrcal_cnt_reg[1]_51 (\po_stg2_wrcal_cnt_reg[1]_51 ),
        .\po_stg2_wrcal_cnt_reg[1]_52 (\po_stg2_wrcal_cnt_reg[1]_52 ),
        .\po_stg2_wrcal_cnt_reg[1]_53 (\po_stg2_wrcal_cnt_reg[1]_53 ),
        .\po_stg2_wrcal_cnt_reg[1]_54 (\po_stg2_wrcal_cnt_reg[1]_54 ),
        .\po_stg2_wrcal_cnt_reg[1]_55 (\po_stg2_wrcal_cnt_reg[1]_55 ),
        .\po_stg2_wrcal_cnt_reg[1]_56 (\po_stg2_wrcal_cnt_reg[1]_56 ),
        .\po_stg2_wrcal_cnt_reg[1]_57 (\po_stg2_wrcal_cnt_reg[1]_57 ),
        .\po_stg2_wrcal_cnt_reg[1]_58 (\po_stg2_wrcal_cnt_reg[1]_58 ),
        .\po_stg2_wrcal_cnt_reg[1]_59 (\po_stg2_wrcal_cnt_reg[1]_59 ),
        .\po_stg2_wrcal_cnt_reg[1]_6 (\po_stg2_wrcal_cnt_reg[1]_6 ),
        .\po_stg2_wrcal_cnt_reg[1]_60 (\po_stg2_wrcal_cnt_reg[1]_60 ),
        .\po_stg2_wrcal_cnt_reg[1]_61 (\po_stg2_wrcal_cnt_reg[1]_61 ),
        .\po_stg2_wrcal_cnt_reg[1]_62 (\po_stg2_wrcal_cnt_reg[1]_62 ),
        .\po_stg2_wrcal_cnt_reg[1]_7 (\po_stg2_wrcal_cnt_reg[1]_7 ),
        .\po_stg2_wrcal_cnt_reg[1]_8 (\po_stg2_wrcal_cnt_reg[1]_8 ),
        .\po_stg2_wrcal_cnt_reg[1]_9 (\po_stg2_wrcal_cnt_reg[1]_9 ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .rclk_(rclk_),
        .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ),
        .\rd_mux_sel_r_reg[1]_0 (\rd_mux_sel_r_reg[1]_0 ),
        .\rd_mux_sel_r_reg[1]_1 (\rd_mux_sel_r_reg[1]_1 ),
        .\rd_mux_sel_r_reg[1]_10 (\rd_mux_sel_r_reg[1]_10 ),
        .\rd_mux_sel_r_reg[1]_11 (\rd_mux_sel_r_reg[1]_11 ),
        .\rd_mux_sel_r_reg[1]_12 (\rd_mux_sel_r_reg[1]_12 ),
        .\rd_mux_sel_r_reg[1]_13 (\rd_mux_sel_r_reg[1]_13 ),
        .\rd_mux_sel_r_reg[1]_14 (\rd_mux_sel_r_reg[1]_14 ),
        .\rd_mux_sel_r_reg[1]_15 (\rd_mux_sel_r_reg[1]_15 ),
        .\rd_mux_sel_r_reg[1]_16 (\rd_mux_sel_r_reg[1]_16 ),
        .\rd_mux_sel_r_reg[1]_17 (\rd_mux_sel_r_reg[1]_17 ),
        .\rd_mux_sel_r_reg[1]_18 (\rd_mux_sel_r_reg[1]_18 ),
        .\rd_mux_sel_r_reg[1]_19 (\rd_mux_sel_r_reg[1]_19 ),
        .\rd_mux_sel_r_reg[1]_2 (\rd_mux_sel_r_reg[1]_2 ),
        .\rd_mux_sel_r_reg[1]_20 (\rd_mux_sel_r_reg[1]_20 ),
        .\rd_mux_sel_r_reg[1]_21 (\rd_mux_sel_r_reg[1]_21 ),
        .\rd_mux_sel_r_reg[1]_22 (\rd_mux_sel_r_reg[1]_22 ),
        .\rd_mux_sel_r_reg[1]_23 (\rd_mux_sel_r_reg[1]_23 ),
        .\rd_mux_sel_r_reg[1]_24 (\rd_mux_sel_r_reg[1]_24 ),
        .\rd_mux_sel_r_reg[1]_25 (\rd_mux_sel_r_reg[1]_25 ),
        .\rd_mux_sel_r_reg[1]_26 (\rd_mux_sel_r_reg[1]_26 ),
        .\rd_mux_sel_r_reg[1]_27 (\rd_mux_sel_r_reg[1]_27 ),
        .\rd_mux_sel_r_reg[1]_28 (\rd_mux_sel_r_reg[1]_28 ),
        .\rd_mux_sel_r_reg[1]_29 (\rd_mux_sel_r_reg[1]_29 ),
        .\rd_mux_sel_r_reg[1]_3 (\rd_mux_sel_r_reg[1]_3 ),
        .\rd_mux_sel_r_reg[1]_30 (\rd_mux_sel_r_reg[1]_30 ),
        .\rd_mux_sel_r_reg[1]_31 (\rd_mux_sel_r_reg[1]_31 ),
        .\rd_mux_sel_r_reg[1]_32 (\rd_mux_sel_r_reg[1]_32 ),
        .\rd_mux_sel_r_reg[1]_33 (\rd_mux_sel_r_reg[1]_33 ),
        .\rd_mux_sel_r_reg[1]_34 (\rd_mux_sel_r_reg[1]_34 ),
        .\rd_mux_sel_r_reg[1]_35 (\rd_mux_sel_r_reg[1]_35 ),
        .\rd_mux_sel_r_reg[1]_36 (\rd_mux_sel_r_reg[1]_36 ),
        .\rd_mux_sel_r_reg[1]_37 (\rd_mux_sel_r_reg[1]_37 ),
        .\rd_mux_sel_r_reg[1]_38 (\rd_mux_sel_r_reg[1]_38 ),
        .\rd_mux_sel_r_reg[1]_39 (\rd_mux_sel_r_reg[1]_39 ),
        .\rd_mux_sel_r_reg[1]_4 (\rd_mux_sel_r_reg[1]_4 ),
        .\rd_mux_sel_r_reg[1]_40 (\rd_mux_sel_r_reg[1]_40 ),
        .\rd_mux_sel_r_reg[1]_41 (\rd_mux_sel_r_reg[1]_41 ),
        .\rd_mux_sel_r_reg[1]_42 (\rd_mux_sel_r_reg[1]_42 ),
        .\rd_mux_sel_r_reg[1]_43 (\rd_mux_sel_r_reg[1]_43 ),
        .\rd_mux_sel_r_reg[1]_44 (\rd_mux_sel_r_reg[1]_44 ),
        .\rd_mux_sel_r_reg[1]_45 (\rd_mux_sel_r_reg[1]_45 ),
        .\rd_mux_sel_r_reg[1]_46 (\rd_mux_sel_r_reg[1]_46 ),
        .\rd_mux_sel_r_reg[1]_47 (\rd_mux_sel_r_reg[1]_47 ),
        .\rd_mux_sel_r_reg[1]_48 (\rd_mux_sel_r_reg[1]_48 ),
        .\rd_mux_sel_r_reg[1]_49 (\rd_mux_sel_r_reg[1]_49 ),
        .\rd_mux_sel_r_reg[1]_5 (\rd_mux_sel_r_reg[1]_5 ),
        .\rd_mux_sel_r_reg[1]_50 (\rd_mux_sel_r_reg[1]_50 ),
        .\rd_mux_sel_r_reg[1]_51 (\rd_mux_sel_r_reg[1]_51 ),
        .\rd_mux_sel_r_reg[1]_52 (\rd_mux_sel_r_reg[1]_52 ),
        .\rd_mux_sel_r_reg[1]_53 (\rd_mux_sel_r_reg[1]_53 ),
        .\rd_mux_sel_r_reg[1]_54 (\rd_mux_sel_r_reg[1]_54 ),
        .\rd_mux_sel_r_reg[1]_55 (\rd_mux_sel_r_reg[1]_55 ),
        .\rd_mux_sel_r_reg[1]_56 (\rd_mux_sel_r_reg[1]_56 ),
        .\rd_mux_sel_r_reg[1]_57 (\rd_mux_sel_r_reg[1]_57 ),
        .\rd_mux_sel_r_reg[1]_58 (\rd_mux_sel_r_reg[1]_58 ),
        .\rd_mux_sel_r_reg[1]_59 (\rd_mux_sel_r_reg[1]_59 ),
        .\rd_mux_sel_r_reg[1]_6 (\rd_mux_sel_r_reg[1]_6 ),
        .\rd_mux_sel_r_reg[1]_60 (\rd_mux_sel_r_reg[1]_60 ),
        .\rd_mux_sel_r_reg[1]_61 (\rd_mux_sel_r_reg[1]_61 ),
        .\rd_mux_sel_r_reg[1]_62 (\rd_mux_sel_r_reg[1]_62 ),
        .\rd_mux_sel_r_reg[1]_7 (\rd_mux_sel_r_reg[1]_7 ),
        .\rd_mux_sel_r_reg[1]_8 (\rd_mux_sel_r_reg[1]_8 ),
        .\rd_mux_sel_r_reg[1]_9 (\rd_mux_sel_r_reg[1]_9 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\not_strict_mode.app_rd_data_reg[24] ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .\write_buffer.wr_buf_out_data_reg[400] (\write_buffer.wr_buf_out_data_reg[400] ),
        .\write_buffer.wr_buf_out_data_reg[404] (\write_buffer.wr_buf_out_data_reg[404] ),
        .\write_buffer.wr_buf_out_data_reg[465] (\write_buffer.wr_buf_out_data_reg[465] ),
        .\write_buffer.wr_buf_out_data_reg[466] (\write_buffer.wr_buf_out_data_reg[466] ),
        .\write_buffer.wr_buf_out_data_reg[467] (\write_buffer.wr_buf_out_data_reg[467] ),
        .\write_buffer.wr_buf_out_data_reg[469] (\write_buffer.wr_buf_out_data_reg[469] ),
        .\write_buffer.wr_buf_out_data_reg[470] (\write_buffer.wr_buf_out_data_reg[470] ),
        .\write_buffer.wr_buf_out_data_reg[471] (\write_buffer.wr_buf_out_data_reg[471] ),
        .\write_buffer.wr_buf_out_data_reg[570] ({\write_buffer.wr_buf_out_data_reg[571] [110],\write_buffer.wr_buf_out_data_reg[571] [106],\write_buffer.wr_buf_out_data_reg[571] [102],\write_buffer.wr_buf_out_data_reg[571] [98],\write_buffer.wr_buf_out_data_reg[571] [94],\write_buffer.wr_buf_out_data_reg[571] [90],\write_buffer.wr_buf_out_data_reg[571] [86],\write_buffer.wr_buf_out_data_reg[571] [82],\write_buffer.wr_buf_out_data_reg[571] [77:76],\write_buffer.wr_buf_out_data_reg[571] [69:68],\write_buffer.wr_buf_out_data_reg[571] [59:56],\write_buffer.wr_buf_out_data_reg[571] [45:44],\write_buffer.wr_buf_out_data_reg[571] [37:36],\write_buffer.wr_buf_out_data_reg[571] [27:24],\write_buffer.wr_buf_out_data_reg[571] [11:8]}));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1 \ddr_byte_lane_C.ddr_byte_lane_C 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_1(\ddr_byte_lane_D.ddr_byte_lane_D_n_38 ),
        .B_byte_rd_en(B_byte_rd_en),
        .CLK(CLK),
        .COUNTERREADVAL(C_pi_counter_read_val),
        .C_byte_rd_en(C_byte_rd_en),
        .C_idelay_ce5_out(C_idelay_ce5_out),
        .C_pi_counter_load_en64_out(C_pi_counter_load_en64_out),
        .C_pi_fine_enable60_out(C_pi_fine_enable60_out),
        .C_pi_fine_inc62_out(C_pi_fine_inc62_out),
        .C_pi_rst_dqs_find58_out(C_pi_rst_dqs_find58_out),
        .C_po_coarse_enable46_out(C_po_coarse_enable46_out),
        .C_po_fine_enable44_out(C_po_fine_enable44_out),
        .C_po_fine_inc48_out(C_po_fine_inc48_out),
        .PCENABLECALIB(phy_encalib),
        .Q({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_7 ,\my_empty_reg[0] }),
        .\calib_sel_reg[1] (\calib_sel_reg[1] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0]_0 ),
        .\ddr3_dm[1] (\ddr3_dm[1] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\wr_ptr_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ),
        .\entry_cnt_reg[3] (\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_4 [3:2]),
        .\entry_cnt_reg[3]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ),
        .\entry_cnt_reg[4] (\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .if_empty_r_2(if_empty_r_2),
        .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),
        .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_1 ),
        .\my_empty_reg[3] (\my_empty_reg[3] ),
        .\my_empty_reg[4]_rep__1 (\my_empty_reg[4]_rep__1 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_1 ),
        .\my_full_reg[0] (if_empty_r_0),
        .\not_strict_mode.app_rd_data_reg[463] ({\not_strict_mode.app_rd_data_reg[479] [239:232],\not_strict_mode.app_rd_data_reg[479] [207:200],\not_strict_mode.app_rd_data_reg[479] [175:168],\not_strict_mode.app_rd_data_reg[479] [143:136],\not_strict_mode.app_rd_data_reg[479] [111:104],\not_strict_mode.app_rd_data_reg[479] [79:72],\not_strict_mode.app_rd_data_reg[479] [47:40],\not_strict_mode.app_rd_data_reg[479] [15:8]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),
        .ofs_rdy_r_reg(\ddr_byte_lane_C.ddr_byte_lane_C_n_42 ),
        .p_193_in(p_193_in),
        .p_194_in(p_194_in),
        .p_195_out(p_195_out),
        .p_197_in(p_197_in),
        .p_198_in(p_198_in),
        .p_199_out(p_199_out),
        .p_19_in(p_19_in),
        .p_201_in(p_201_in),
        .p_202_in(p_202_in),
        .p_203_out(p_203_out),
        .p_205_in(p_205_in),
        .p_206_in(p_206_in),
        .p_207_out(p_207_out),
        .p_209_in(p_209_in),
        .p_210_in(p_210_in),
        .p_211_out(p_211_out),
        .p_213_in(p_213_in),
        .p_214_in(p_214_in),
        .p_215_out(p_215_out),
        .p_217_in(p_217_in),
        .p_218_in(p_218_in),
        .p_219_out(p_219_out),
        .p_221_in(p_221_in),
        .p_222_in(p_222_in),
        .p_223_out(p_223_out),
        .p_32_in(p_32_in),
        .p_34_out(p_34_out),
        .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[184],mux_wrdata[152],mux_wrdata[126],mux_wrdata[102],mux_wrdata[78],mux_wrdata[54],mux_wrdata[24],\write_buffer.wr_buf_out_data_reg[351] [4],mux_wrdata[185],mux_wrdata[153],mux_wrdata[127],mux_wrdata[103],mux_wrdata[79],\write_buffer.wr_buf_out_data_reg[351] [18],mux_wrdata[25],mux_wrdata[4],mux_wrdata[186],mux_wrdata[154],mux_wrdata[128],\write_buffer.wr_buf_out_data_reg[351] [34],\write_buffer.wr_buf_out_data_reg[351] [26],mux_wrdata[55],mux_wrdata[26],mux_wrdata[5],mux_wrdata[187],mux_wrdata[155],\write_buffer.wr_buf_out_data_reg[351] [42],mux_wrdata[104],mux_wrdata[80],mux_wrdata[56],mux_wrdata[27],\write_buffer.wr_buf_out_data_reg[351] [5],mux_wrdata[188],mux_wrdata[156],mux_wrdata[129],mux_wrdata[105],mux_wrdata[81],mux_wrdata[57],mux_wrdata[28],\write_buffer.wr_buf_out_data_reg[351] [6],mux_wrdata[189],mux_wrdata[157],mux_wrdata[130],mux_wrdata[106],mux_wrdata[82],\write_buffer.wr_buf_out_data_reg[351] [19],mux_wrdata[29],mux_wrdata[6],mux_wrdata[190],mux_wrdata[158],mux_wrdata[131],\write_buffer.wr_buf_out_data_reg[351] [35],\write_buffer.wr_buf_out_data_reg[351] [27],mux_wrdata[58],mux_wrdata[30],mux_wrdata[7],mux_wrdata[191],mux_wrdata[159],\write_buffer.wr_buf_out_data_reg[351] [43],mux_wrdata[107],mux_wrdata[83],mux_wrdata[59],mux_wrdata[31],\write_buffer.wr_buf_out_data_reg[351] [7]}),
        .phy_if_reset(phy_if_reset),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[2]),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),
        .\po_counter_read_val_reg[8] (C_po_counter_read_val),
        .\read_fifo.fifo_out_data_r_reg[4] (\not_strict_mode.app_rd_data_reg[24] ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1]_0 ),
        .\write_buffer.wr_buf_out_data_reg[392] (\write_buffer.wr_buf_out_data_reg[392] ),
        .\write_buffer.wr_buf_out_data_reg[396] (\write_buffer.wr_buf_out_data_reg[396] ),
        .\write_buffer.wr_buf_out_data_reg[457] (\write_buffer.wr_buf_out_data_reg[457] ),
        .\write_buffer.wr_buf_out_data_reg[458] (\write_buffer.wr_buf_out_data_reg[458] ),
        .\write_buffer.wr_buf_out_data_reg[459] (\write_buffer.wr_buf_out_data_reg[459] ),
        .\write_buffer.wr_buf_out_data_reg[461] (\write_buffer.wr_buf_out_data_reg[461] ),
        .\write_buffer.wr_buf_out_data_reg[462] (\write_buffer.wr_buf_out_data_reg[462] ),
        .\write_buffer.wr_buf_out_data_reg[463] (\write_buffer.wr_buf_out_data_reg[463] ),
        .\write_buffer.wr_buf_out_data_reg[569] ({\write_buffer.wr_buf_out_data_reg[571] [109],\write_buffer.wr_buf_out_data_reg[571] [105],\write_buffer.wr_buf_out_data_reg[571] [101],\write_buffer.wr_buf_out_data_reg[571] [97],\write_buffer.wr_buf_out_data_reg[571] [93],\write_buffer.wr_buf_out_data_reg[571] [89],\write_buffer.wr_buf_out_data_reg[571] [85],\write_buffer.wr_buf_out_data_reg[571] [81],\write_buffer.wr_buf_out_data_reg[571] [75:74],\write_buffer.wr_buf_out_data_reg[571] [67:66],\write_buffer.wr_buf_out_data_reg[571] [55:52],\write_buffer.wr_buf_out_data_reg[571] [43:42],\write_buffer.wr_buf_out_data_reg[571] [35:34],\write_buffer.wr_buf_out_data_reg[571] [23:20],\write_buffer.wr_buf_out_data_reg[571] [7:4]}));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized2 \ddr_byte_lane_D.ddr_byte_lane_D 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_0(\ddr_byte_lane_B.ddr_byte_lane_B_n_2 ),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_6),
        .A_rst_primitives_reg_3(\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_7),
        .A_rst_primitives_reg_5(C_pi_counter_read_val),
        .A_rst_primitives_reg_6(A_pi_counter_read_val),
        .A_rst_primitives_reg_7(B_po_counter_read_val),
        .A_rst_primitives_reg_8(C_po_counter_read_val),
        .A_rst_primitives_reg_9(A_po_counter_read_val),
        .CLK(CLK),
        .COUNTERREADVAL(B_pi_counter_read_val),
        .D({\ddr_byte_lane_D.ddr_byte_lane_D_n_204 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_205 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_206 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_207 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_208 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_209 }),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .D_idelay_ce1_out(D_idelay_ce1_out),
        .D_pi_counter_load_en90_out(D_pi_counter_load_en90_out),
        .D_pi_fine_enable86_out(D_pi_fine_enable86_out),
        .D_pi_fine_inc88_out(D_pi_fine_inc88_out),
        .D_pi_rst_dqs_find84_out(D_pi_rst_dqs_find84_out),
        .D_po_coarse_enable72_out(D_po_coarse_enable72_out),
        .D_po_fine_enable70_out(D_po_fine_enable70_out),
        .D_po_fine_inc74_out(D_po_fine_inc74_out),
        .PCENABLECALIB(phy_encalib),
        .Q(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_8 ),
        .\calib_sel_reg[0] (\calib_sel_reg[0]_1 ),
        .\calib_sel_reg[1] (\calib_sel_reg[1]_0 ),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[0] (\calib_zero_inputs_reg[0]_1 ),
        .\ddr3_dm[0] (\ddr3_dm[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\entry_cnt_reg[2] (\entry_cnt_reg[2] ),
        .\entry_cnt_reg[3] (\entry_cnt_reg[3] ),
        .\entry_cnt_reg[3]_0 (\ddr_byte_lane_C.ddr_byte_lane_C_n_42 ),
        .\entry_cnt_reg[3]_1 (\entry_cnt_reg[3]_0 ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_0),
        .if_empty_r_1(if_empty_r_1),
        .if_empty_r_2(if_empty_r_9),
        .if_empty_r_3(if_empty_r_3),
        .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),
        .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9),
        .mc_read_idle_r_reg(mc_read_idle_r_reg_0),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .my_empty(my_empty),
        .\my_empty_reg[1] (\my_empty_reg[1]_2 ),
        .\my_empty_reg[3] (\ddr_byte_lane_A.ddr_byte_lane_A_n_46 ),
        .\my_empty_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_5 ),
        .\my_empty_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_7 ),
        .\my_empty_reg[4]_rep__1 (\ddr_byte_lane_D.ddr_byte_lane_D_n_27 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_2 ),
        .\not_strict_mode.app_rd_data_reg[455] ({\not_strict_mode.app_rd_data_reg[479] [231:224],\not_strict_mode.app_rd_data_reg[479] [199:192],\not_strict_mode.app_rd_data_reg[479] [167:160],\not_strict_mode.app_rd_data_reg[479] [135:128],\not_strict_mode.app_rd_data_reg[479] [103:96],\not_strict_mode.app_rd_data_reg[479] [71:64],\not_strict_mode.app_rd_data_reg[479] [39:32],\not_strict_mode.app_rd_data_reg[479] [7:0]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),
        .p_21_in(p_21_in),
        .p_225_in(p_225_in),
        .p_226_in(p_226_in),
        .p_227_out(p_227_out),
        .p_229_in(p_229_in),
        .p_230_in(p_230_in),
        .p_231_out(p_231_out),
        .p_233_in(p_233_in),
        .p_234_in(p_234_in),
        .p_235_out(p_235_out),
        .p_237_in(p_237_in),
        .p_238_in(p_238_in),
        .p_239_out(p_239_out),
        .p_241_in(p_241_in),
        .p_242_in(p_242_in),
        .p_243_out(p_243_out),
        .p_245_in(p_245_in),
        .p_246_in(p_246_in),
        .p_247_out(p_247_out),
        .p_249_in(p_249_in),
        .p_250_in(p_250_in),
        .p_251_out(p_251_out),
        .p_253_in(p_253_in),
        .p_254_in(p_254_in),
        .p_255_out(p_255_out),
        .phaser_ctl_bus({phaser_ctl_bus[15:14],phaser_ctl_bus[7],phaser_ctl_bus[3]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[176],mux_wrdata[144],mux_wrdata[120],mux_wrdata[96],mux_wrdata[72],mux_wrdata[48],mux_wrdata[16],\write_buffer.wr_buf_out_data_reg[351] [0],mux_wrdata[177],mux_wrdata[145],mux_wrdata[121],mux_wrdata[97],mux_wrdata[73],\write_buffer.wr_buf_out_data_reg[351] [16],mux_wrdata[17],mux_wrdata[0],mux_wrdata[178],mux_wrdata[146],mux_wrdata[122],\write_buffer.wr_buf_out_data_reg[351] [32],\write_buffer.wr_buf_out_data_reg[351] [24],mux_wrdata[49],mux_wrdata[18],mux_wrdata[1],mux_wrdata[179],mux_wrdata[147],\write_buffer.wr_buf_out_data_reg[351] [40],mux_wrdata[98],mux_wrdata[74],mux_wrdata[50],mux_wrdata[19],\write_buffer.wr_buf_out_data_reg[351] [1],mux_wrdata[180],mux_wrdata[148],mux_wrdata[123],mux_wrdata[99],mux_wrdata[75],mux_wrdata[51],mux_wrdata[20],\write_buffer.wr_buf_out_data_reg[351] [2],mux_wrdata[181],mux_wrdata[149],mux_wrdata[124],mux_wrdata[100],mux_wrdata[76],\write_buffer.wr_buf_out_data_reg[351] [17],mux_wrdata[21],mux_wrdata[2],mux_wrdata[182],mux_wrdata[150],mux_wrdata[125],\write_buffer.wr_buf_out_data_reg[351] [33],\write_buffer.wr_buf_out_data_reg[351] [25],mux_wrdata[52],mux_wrdata[22],mux_wrdata[3],mux_wrdata[183],mux_wrdata[151],\write_buffer.wr_buf_out_data_reg[351] [41],mux_wrdata[101],mux_wrdata[77],mux_wrdata[53],mux_wrdata[23],\write_buffer.wr_buf_out_data_reg[351] [3]}),
        .phy_if_reset(phy_if_reset),
        .phy_mc_data_full(phy_mc_data_full),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[3]),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .pi_phase_locked_all_r1_reg(\ddr_byte_lane_D.ddr_byte_lane_D_n_38 ),
        .\po_counter_read_val_reg[8] ({\ddr_byte_lane_D.ddr_byte_lane_D_n_210 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_211 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_212 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_213 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_214 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_215 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_216 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_217 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_218 }),
        .\read_fifo.fifo_out_data_r_reg[4] (\not_strict_mode.app_rd_data_reg[24] ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\write_buffer.wr_buf_out_data_reg[384] (\write_buffer.wr_buf_out_data_reg[384] ),
        .\write_buffer.wr_buf_out_data_reg[388] (\write_buffer.wr_buf_out_data_reg[388] ),
        .\write_buffer.wr_buf_out_data_reg[449] (\write_buffer.wr_buf_out_data_reg[449] ),
        .\write_buffer.wr_buf_out_data_reg[450] (\write_buffer.wr_buf_out_data_reg[450] ),
        .\write_buffer.wr_buf_out_data_reg[451] (\write_buffer.wr_buf_out_data_reg[451] ),
        .\write_buffer.wr_buf_out_data_reg[453] (\write_buffer.wr_buf_out_data_reg[453] ),
        .\write_buffer.wr_buf_out_data_reg[454] (\write_buffer.wr_buf_out_data_reg[454] ),
        .\write_buffer.wr_buf_out_data_reg[455] (\write_buffer.wr_buf_out_data_reg[455] ),
        .\write_buffer.wr_buf_out_data_reg[568] ({\write_buffer.wr_buf_out_data_reg[571] [108],\write_buffer.wr_buf_out_data_reg[571] [104],\write_buffer.wr_buf_out_data_reg[571] [100],\write_buffer.wr_buf_out_data_reg[571] [96],\write_buffer.wr_buf_out_data_reg[571] [92],\write_buffer.wr_buf_out_data_reg[571] [88],\write_buffer.wr_buf_out_data_reg[571] [84],\write_buffer.wr_buf_out_data_reg[571] [80],\write_buffer.wr_buf_out_data_reg[571] [73:72],\write_buffer.wr_buf_out_data_reg[571] [65:64],\write_buffer.wr_buf_out_data_reg[571] [51:48],\write_buffer.wr_buf_out_data_reg[571] [41:40],\write_buffer.wr_buf_out_data_reg[571] [33:32],\write_buffer.wr_buf_out_data_reg[571] [19:16],\write_buffer.wr_buf_out_data_reg[571] [3:0]}));
  FDRE #(
    .INIT(1'b0)) 
    mcGo_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_reg_0),
        .Q(mcGo_w__0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_REF #(
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0)) 
    phaser_ref_i
       (.CLKIN(freq_refclk),
        .LOCKED(ref_dll_lock_w__0),
        .PWRDWN(1'b0),
        .RST(sys_rst_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHY_CONTROL #(
    .AO_TOGGLE(1),
    .AO_WRLVL_EN(4'b0000),
    .BURST_MODE("TRUE"),
    .CLK_RATIO(4),
    .CMD_OFFSET(8),
    .CO_DURATION(1),
    .DATA_CTL_A_N("TRUE"),
    .DATA_CTL_B_N("TRUE"),
    .DATA_CTL_C_N("TRUE"),
    .DATA_CTL_D_N("TRUE"),
    .DISABLE_SEQ_MATCH("TRUE"),
    .DI_DURATION(1),
    .DO_DURATION(1),
    .EVENTS_DELAY(18),
    .FOUR_WINDOW_CLOCKS(63),
    .MULTI_REGION("TRUE"),
    .PHY_COUNT_ENABLE("FALSE"),
    .RD_CMD_OFFSET_0(10),
    .RD_CMD_OFFSET_1(10),
    .RD_CMD_OFFSET_2(10),
    .RD_CMD_OFFSET_3(10),
    .RD_DURATION_0(6),
    .RD_DURATION_1(6),
    .RD_DURATION_2(6),
    .RD_DURATION_3(6),
    .SYNC_MODE("FALSE"),
    .WR_CMD_OFFSET_0(8),
    .WR_CMD_OFFSET_1(8),
    .WR_CMD_OFFSET_2(8),
    .WR_CMD_OFFSET_3(8),
    .WR_DURATION_0(7),
    .WR_DURATION_1(7),
    .WR_DURATION_2(7),
    .WR_DURATION_3(7)) 
    phy_control_i
       (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),
        .INBURSTPENDING(phaser_ctl_bus[7:4]),
        .INRANKA(phaser_ctl_bus[9:8]),
        .INRANKB(phaser_ctl_bus[11:10]),
        .INRANKC(phaser_ctl_bus[13:12]),
        .INRANKD(phaser_ctl_bus[15:14]),
        .MEMREFCLK(mem_refclk),
        .OUTBURSTPENDING(phaser_ctl_bus[3:0]),
        .PCENABLECALIB(phy_encalib),
        .PHYCLK(CLK),
        .PHYCTLALMOSTFULL(phy_control_i_n_0),
        .PHYCTLEMPTY(phy_control_i_n_1),
        .PHYCTLFULL(_phy_ctl_full_p__0),
        .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),
        .PHYCTLREADY(rst_primitives_reg_0),
        .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[2:0]}),
        .PHYCTLWRENABLE(phy_ctl_wr_i2),
        .PLLLOCK(pll_lock),
        .READCALIBENABLE(read_calib),
        .REFDLLLOCK(ref_dll_lock_w__0),
        .RESET(rstdiv0_sync_r1),
        .SYNCIN(sync_pulse),
        .WRITECALIBENABLE(write_calib));
  FDRE \pi_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_209 ),
        .Q(\pi_rdval_cnt_reg[5] [0]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_208 ),
        .Q(\pi_rdval_cnt_reg[5] [1]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_207 ),
        .Q(\pi_rdval_cnt_reg[5] [2]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_206 ),
        .Q(\pi_rdval_cnt_reg[5] [3]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_205 ),
        .Q(\pi_rdval_cnt_reg[5] [4]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_204 ),
        .Q(\pi_rdval_cnt_reg[5] [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_218 ),
        .Q(\po_rdval_cnt_reg[8] [0]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_217 ),
        .Q(\po_rdval_cnt_reg[8] [1]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_216 ),
        .Q(\po_rdval_cnt_reg[8] [2]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_215 ),
        .Q(\po_rdval_cnt_reg[8] [3]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_214 ),
        .Q(\po_rdval_cnt_reg[8] [4]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_213 ),
        .Q(\po_rdval_cnt_reg[8] [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_212 ),
        .Q(\po_rdval_cnt_reg[8] [6]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_211 ),
        .Q(\po_rdval_cnt_reg[8] [7]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_210 ),
        .Q(\po_rdval_cnt_reg[8] [8]),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) 
  SRL16E \rclk_delay_reg[10]_srl11 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(rst_primitives_reg_1),
        .Q(\rclk_delay_reg[10]_srl11_n_0 ));
  FDRE \rclk_delay_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rclk_delay_reg[10]_srl11_n_0 ),
        .Q(rclk_delay_11),
        .R(1'b0));
  FDCE #(
    .INIT(1'b0)) 
    rst_out_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(rstdiv0_sync_r1),
        .D(\rclk_delay_reg[11]_0 ),
        .Q(mcGo_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in),
        .Q(rst_primitives),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \rstdiv0_sync_r[11]_i_1 
       (.I0(sys_rst),
        .I1(iodelay_ctrl_rdy),
        .I2(sys_rst_2),
        .I3(ref_dll_lock_w__0),
        .I4(sys_rst_0),
        .I5(ref_dll_lock_w),
        .O(rst_sync_r1_reg));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_4lanes" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized0
   (out,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    pi_phase_locked_all_r1_reg,
    COUNTERREADVAL,
    ofifo_rst_reg,
    \pi_dqs_found_lanes_r1_reg[4] ,
    \pi_dqs_found_lanes_r1_reg[4]_0 ,
    p_98_in,
    p_97_in,
    p_102_in,
    p_101_in,
    p_106_in,
    p_105_in,
    p_110_in,
    p_109_in,
    p_114_in,
    p_113_in,
    p_118_in,
    p_117_in,
    p_122_in,
    p_121_in,
    p_126_in,
    p_125_in,
    \ddr3_dm[4] ,
    p_9_in,
    if_empty_r,
    phy_ctl_mstr_empty,
    ref_dll_lock_w,
    ddr_ck_out,
    \my_empty_reg[4]_rep__1 ,
    phy_mc_ctl_full,
    mcGo_r1,
    \my_empty_reg[1] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    Q,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ,
    \my_empty_reg[1]_0 ,
    \entry_cnt_reg[4] ,
    ofs_rdy_r_reg,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    store_sr_req_r_reg,
    \pi_rdval_cnt_reg[4] ,
    \pi_rdval_cnt_reg[1] ,
    \pi_rdval_cnt_reg[2] ,
    \pi_rdval_cnt_reg[3] ,
    \pi_rdval_cnt_reg[0] ,
    \pi_rdval_cnt_reg[5] ,
    \FSM_onehot_cal1_state_r_reg[0] ,
    \FSM_onehot_cal1_state_r_reg[0]_0 ,
    \FSM_onehot_cal1_state_r_reg[0]_1 ,
    \not_strict_mode.app_rd_data_reg[487] ,
    wr_en,
    wr_en_10,
    wr_en_11,
    of_ctl_full_v,
    p_0_in1_in,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[1]_1 ,
    DIC,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7] ,
    idelay_ld_rst_6,
    \wr_ptr_timing_reg[3]_0 ,
    \wr_ptr_timing_reg[0] ,
    mem_dq_out,
    \wr_ptr_timing_reg[3]_1 ,
    \wr_ptr_timing_reg[0]_0 ,
    \ddr3_addr[3] ,
    \ddr3_addr[13] ,
    \my_empty_reg[6] ,
    \po_rdval_cnt_reg[0] ,
    \po_rdval_cnt_reg[1] ,
    \po_rdval_cnt_reg[2] ,
    \po_rdval_cnt_reg[3] ,
    \po_rdval_cnt_reg[4] ,
    \po_rdval_cnt_reg[5] ,
    \po_rdval_cnt_reg[6] ,
    \po_rdval_cnt_reg[7] ,
    \po_rdval_cnt_reg[8] ,
    A_pi_counter_load_en161_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable157_out,
    A_pi_fine_inc159_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_pi_rst_dqs_find155_out,
    sync_pulse,
    CLK,
    \pi_stg2_reg_l_reg[5] ,
    A_po_coarse_enable143_out,
    A_po_fine_enable141_out,
    A_po_fine_inc145_out,
    D0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    A_rst_primitives_reg_0,
    p_99_out,
    A_idelay_ce19_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    p_103_out,
    p_107_out,
    p_111_out,
    p_115_out,
    p_119_out,
    p_123_out,
    p_127_out,
    ofifo_rst0,
    B_po_coarse_enable27_out,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    B_po_fine_enable24_out,
    B_po_fine_inc30_out,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    C_po_coarse_enable66_out,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    C_po_fine_enable63_out,
    C_po_fine_inc69_out,
    \cmd_pipe_plus.mc_ras_n_reg[2] ,
    init_calib_complete_reg_rep__3,
    init_calib_complete_reg_rep__2,
    init_calib_complete_reg_rep__2_0,
    init_calib_complete_reg_rep__2_1,
    init_calib_complete_reg_rep__2_2,
    init_calib_complete_reg_rep__2_3,
    init_calib_complete_reg_rep__2_4,
    D8,
    init_calib_complete_reg_rep__2_5,
    phy_ctl_wr_i2,
    pll_lock,
    read_calib,
    rstdiv0_sync_r1,
    write_calib,
    PHYCTLWD,
    sys_rst,
    phy_if_reset,
    rstdiv0_sync_r1_reg_rep__0,
    D_po_coarse_enable105_out,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    D_po_fine_enable102_out,
    D_po_fine_inc108_out,
    init_calib_complete_reg_rep,
    init_calib_complete_reg_rep_0,
    init_calib_complete_reg_rep_1,
    init_calib_complete_reg_rep_2,
    phy_data_wr_en,
    phy_cmd_wr_en,
    _phy_ctl_full_p__0,
    mcGo_w__0,
    init_calib_complete_reg_rep_3,
    calib_cmd_wren,
    \my_empty_reg[3] ,
    mem_out,
    \entry_cnt_reg[4]_0 ,
    \entry_cnt_reg[3] ,
    \entry_cnt_reg[4]_1 ,
    init_calib_complete_reg_rep__1,
    init_calib_complete_reg_rep__2_6,
    init_calib_complete_reg_rep__14,
    \pi_counter_read_val_reg[5]_0 ,
    \calib_sel_reg[4] ,
    \pi_counter_read_val_reg[5]_1 ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__0,
    mc_wrdata_en,
    \rd_ptr_reg_rep[3] ,
    \rd_ptr_reg_rep[3]_0 ,
    \rd_ptr_reg_rep[3]_1 ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    mc_cas_n,
    D,
    phy_dout,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 );
  output [1:0]out;
  output [0:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output pi_phase_locked_all_r1_reg;
  output [5:0]COUNTERREADVAL;
  output ofifo_rst_reg;
  output \pi_dqs_found_lanes_r1_reg[4] ;
  output \pi_dqs_found_lanes_r1_reg[4]_0 ;
  output p_98_in;
  output p_97_in;
  output p_102_in;
  output p_101_in;
  output p_106_in;
  output p_105_in;
  output p_110_in;
  output p_109_in;
  output p_114_in;
  output p_113_in;
  output p_118_in;
  output p_117_in;
  output p_122_in;
  output p_121_in;
  output p_126_in;
  output p_125_in;
  output \ddr3_dm[4] ;
  output p_9_in;
  output [0:0]if_empty_r;
  output phy_ctl_mstr_empty;
  output [0:0]ref_dll_lock_w;
  output [1:0]ddr_ck_out;
  output [1:0]\my_empty_reg[4]_rep__1 ;
  output phy_mc_ctl_full;
  output mcGo_r1;
  output \my_empty_reg[1] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  output [65:0]Q;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  output \my_empty_reg[1]_0 ;
  output [0:0]\entry_cnt_reg[4] ;
  output ofs_rdy_r_reg;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output store_sr_req_r_reg;
  output \pi_rdval_cnt_reg[4] ;
  output \pi_rdval_cnt_reg[1] ;
  output \pi_rdval_cnt_reg[2] ;
  output \pi_rdval_cnt_reg[3] ;
  output \pi_rdval_cnt_reg[0] ;
  output \pi_rdval_cnt_reg[5] ;
  output \FSM_onehot_cal1_state_r_reg[0] ;
  output \FSM_onehot_cal1_state_r_reg[0]_0 ;
  output \FSM_onehot_cal1_state_r_reg[0]_1 ;
  output [63:0]\not_strict_mode.app_rd_data_reg[487] ;
  output wr_en;
  output wr_en_10;
  output wr_en_11;
  output [0:0]of_ctl_full_v;
  output p_0_in1_in;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[1]_0 ;
  output \wr_ptr_reg[1]_1 ;
  output [1:0]DIC;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7] ;
  output idelay_ld_rst_6;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\wr_ptr_timing_reg[0] ;
  output [4:0]mem_dq_out;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  output [11:0]\ddr3_addr[3] ;
  output [5:0]\ddr3_addr[13] ;
  output [15:0]\my_empty_reg[6] ;
  output \po_rdval_cnt_reg[0] ;
  output \po_rdval_cnt_reg[1] ;
  output \po_rdval_cnt_reg[2] ;
  output \po_rdval_cnt_reg[3] ;
  output \po_rdval_cnt_reg[4] ;
  output \po_rdval_cnt_reg[5] ;
  output \po_rdval_cnt_reg[6] ;
  output \po_rdval_cnt_reg[7] ;
  output \po_rdval_cnt_reg[8] ;
  input A_pi_counter_load_en161_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable157_out;
  input A_pi_fine_inc159_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_pi_rst_dqs_find155_out;
  input sync_pulse;
  input CLK;
  input [5:0]\pi_stg2_reg_l_reg[5] ;
  input A_po_coarse_enable143_out;
  input A_po_fine_enable141_out;
  input A_po_fine_inc145_out;
  input [7:0]D0;
  input [7:0]D1;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D9;
  input A_rst_primitives_reg_0;
  input p_99_out;
  input A_idelay_ce19_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input p_103_out;
  input p_107_out;
  input p_111_out;
  input p_115_out;
  input p_119_out;
  input p_123_out;
  input p_127_out;
  input ofifo_rst0;
  input B_po_coarse_enable27_out;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input B_po_fine_enable24_out;
  input B_po_fine_inc30_out;
  input [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  input [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  input [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  input [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  input C_po_coarse_enable66_out;
  input \gen_byte_sel_div2.calib_in_common_reg_1 ;
  input C_po_fine_enable63_out;
  input C_po_fine_inc69_out;
  input [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  input [3:0]init_calib_complete_reg_rep__3;
  input [3:0]init_calib_complete_reg_rep__2;
  input [3:0]init_calib_complete_reg_rep__2_0;
  input [3:0]init_calib_complete_reg_rep__2_1;
  input [7:0]init_calib_complete_reg_rep__2_2;
  input [7:0]init_calib_complete_reg_rep__2_3;
  input [3:0]init_calib_complete_reg_rep__2_4;
  input [3:0]D8;
  input [3:0]init_calib_complete_reg_rep__2_5;
  input phy_ctl_wr_i2;
  input pll_lock;
  input read_calib;
  input rstdiv0_sync_r1;
  input write_calib;
  input [10:0]PHYCTLWD;
  input sys_rst;
  input phy_if_reset;
  input rstdiv0_sync_r1_reg_rep__0;
  input D_po_coarse_enable105_out;
  input \gen_byte_sel_div2.calib_in_common_reg_2 ;
  input D_po_fine_enable102_out;
  input D_po_fine_inc108_out;
  input [3:0]init_calib_complete_reg_rep;
  input [3:0]init_calib_complete_reg_rep_0;
  input [3:0]init_calib_complete_reg_rep_1;
  input [3:0]init_calib_complete_reg_rep_2;
  input phy_data_wr_en;
  input phy_cmd_wr_en;
  input [1:0]_phy_ctl_full_p__0;
  input [1:0]mcGo_w__0;
  input init_calib_complete_reg_rep_3;
  input calib_cmd_wren;
  input \my_empty_reg[3] ;
  input [63:0]mem_out;
  input [0:0]\entry_cnt_reg[4]_0 ;
  input [1:0]\entry_cnt_reg[3] ;
  input \entry_cnt_reg[4]_1 ;
  input init_calib_complete_reg_rep__1;
  input init_calib_complete_reg_rep__2_6;
  input init_calib_complete_reg_rep__14;
  input [5:0]\pi_counter_read_val_reg[5]_0 ;
  input [3:0]\calib_sel_reg[4] ;
  input [5:0]\pi_counter_read_val_reg[5]_1 ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__0;
  input mc_wrdata_en;
  input [7:0]\rd_ptr_reg_rep[3] ;
  input [24:0]\rd_ptr_reg_rep[3]_0 ;
  input [32:0]\rd_ptr_reg_rep[3]_1 ;
  input [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [0:0]mc_cas_n;
  input [5:0]D;
  input [21:0]phy_dout;
  input [8:0]\po_counter_read_val_reg[8]_0 ;
  input [8:0]\po_counter_read_val_reg[8]_1 ;

  wire A_idelay_ce19_out;
  wire A_pi_counter_load_en161_out;
  wire A_pi_fine_enable157_out;
  wire A_pi_fine_inc159_out;
  wire A_pi_rst_dqs_find155_out;
  wire A_po_coarse_enable143_out;
  wire [8:0]A_po_counter_read_val;
  wire A_po_fine_enable141_out;
  wire A_po_fine_inc145_out;
  wire A_rst_primitives_reg_0;
  wire B_of_ctl_full;
  wire B_po_coarse_enable27_out;
  wire [8:0]B_po_counter_read_val;
  wire B_po_fine_enable24_out;
  wire B_po_fine_inc30_out;
  wire CLK;
  wire [5:0]COUNTERREADVAL;
  wire C_of_ctl_full;
  wire C_po_coarse_enable66_out;
  wire [8:0]C_po_counter_read_val;
  wire C_po_fine_enable63_out;
  wire C_po_fine_inc69_out;
  wire [5:0]D;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [3:0]D8;
  wire [7:0]D9;
  wire [1:0]DIC;
  wire D_po_coarse_enable105_out;
  wire D_po_fine_enable102_out;
  wire D_po_fine_inc108_out;
  wire \FSM_onehot_cal1_state_r_reg[0] ;
  wire \FSM_onehot_cal1_state_r_reg[0]_0 ;
  wire \FSM_onehot_cal1_state_r_reg[0]_1 ;
  wire [10:0]PHYCTLWD;
  wire [65:0]Q;
  wire [1:1]_phy_ctl_full_p;
  wire [1:0]_phy_ctl_full_p__0;
  wire calib_cmd_wren;
  wire \calib_sel_reg[0] ;
  wire [3:0]\calib_sel_reg[4] ;
  wire calib_wrdata_en;
  wire [3:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  wire [5:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire [5:0]\ddr3_addr[13] ;
  wire [11:0]\ddr3_addr[3] ;
  wire \ddr3_dm[4] ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_27 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_28 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_29 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_30 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_31 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_32 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_33 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_34 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_35 ;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire [1:0]\entry_cnt_reg[3] ;
  wire [0:0]\entry_cnt_reg[4] ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire \entry_cnt_reg[4]_1 ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  wire idelay_inc;
  wire idelay_ld_rst_6;
  wire [0:0]if_empty_r;
  wire [3:0]init_calib_complete_reg_rep;
  wire [3:0]init_calib_complete_reg_rep_0;
  wire [3:0]init_calib_complete_reg_rep_1;
  wire [3:0]init_calib_complete_reg_rep_2;
  wire init_calib_complete_reg_rep_3;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__1;
  wire init_calib_complete_reg_rep__14;
  wire [3:0]init_calib_complete_reg_rep__2;
  wire [3:0]init_calib_complete_reg_rep__2_0;
  wire [3:0]init_calib_complete_reg_rep__2_1;
  wire [7:0]init_calib_complete_reg_rep__2_2;
  wire [7:0]init_calib_complete_reg_rep__2_3;
  wire [3:0]init_calib_complete_reg_rep__2_4;
  wire [3:0]init_calib_complete_reg_rep__2_5;
  wire init_calib_complete_reg_rep__2_6;
  wire [3:0]init_calib_complete_reg_rep__3;
  wire mcGo_r1;
  wire [1:1]mcGo_w;
  wire [1:0]mcGo_w__0;
  wire [0:0]mc_cas_n;
  wire mc_read_idle_r_reg;
  wire mc_wrdata_en;
  wire [4:0]mem_dq_out;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[3] ;
  wire [1:0]\my_empty_reg[4]_rep__1 ;
  wire [15:0]\my_empty_reg[6] ;
  wire [3:0]\my_empty_reg[7] ;
  wire [63:0]\not_strict_mode.app_rd_data_reg[487] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [0:0]of_ctl_full_v;
  wire ofifo_rst;
  wire ofifo_rst0;
  wire ofifo_rst_reg;
  wire ofs_rdy_r_reg;
  wire [1:0]out;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_101_in;
  wire p_102_in;
  wire p_103_out;
  wire p_105_in;
  wire p_106_in;
  wire p_107_out;
  wire p_109_in;
  wire p_110_in;
  wire p_111_out;
  wire p_113_in;
  wire p_114_in;
  wire p_115_out;
  wire p_117_in;
  wire p_118_in;
  wire p_119_out;
  wire p_121_in;
  wire p_122_in;
  wire p_123_out;
  wire p_125_in;
  wire p_126_in;
  wire p_127_out;
  wire p_97_in;
  wire p_98_in;
  wire p_99_out;
  wire p_9_in;
  wire [3:3]phaser_ctl_bus;
  wire phy_cmd_wr_en;
  wire phy_control_i_n_0;
  wire phy_control_i_n_10;
  wire phy_control_i_n_11;
  wire phy_control_i_n_14;
  wire phy_control_i_n_15;
  wire phy_control_i_n_16;
  wire phy_control_i_n_17;
  wire phy_control_i_n_18;
  wire phy_control_i_n_19;
  wire phy_control_i_n_20;
  wire phy_control_i_n_21;
  wire phy_control_i_n_23;
  wire phy_control_i_n_24;
  wire phy_control_i_n_25;
  wire phy_control_i_n_3;
  wire phy_control_i_n_4;
  wire phy_control_i_n_5;
  wire phy_control_i_n_6;
  wire phy_control_i_n_7;
  wire phy_control_i_n_8;
  wire phy_control_i_n_9;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_wr_i2;
  wire phy_data_wr_en;
  wire [21:0]phy_dout;
  wire [1:0]phy_encalib;
  wire phy_if_reset;
  wire phy_mc_ctl_full;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire [5:0]\pi_counter_read_val_reg[5]_1 ;
  wire [5:0]\pi_counter_read_val_w[1]_2 ;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[4] ;
  wire \pi_dqs_found_lanes_r1_reg[4]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire \pi_rdval_cnt_reg[0] ;
  wire \pi_rdval_cnt_reg[1] ;
  wire \pi_rdval_cnt_reg[2] ;
  wire \pi_rdval_cnt_reg[3] ;
  wire \pi_rdval_cnt_reg[4] ;
  wire \pi_rdval_cnt_reg[5] ;
  wire [5:0]\pi_stg2_reg_l_reg[5] ;
  wire pll_lock;
  wire [8:0]\po_counter_read_val_reg[8]_0 ;
  wire [8:0]\po_counter_read_val_reg[8]_1 ;
  wire [8:0]\po_counter_read_val_w[1]_1 ;
  wire \po_rdval_cnt_reg[0] ;
  wire \po_rdval_cnt_reg[1] ;
  wire \po_rdval_cnt_reg[2] ;
  wire \po_rdval_cnt_reg[3] ;
  wire \po_rdval_cnt_reg[4] ;
  wire \po_rdval_cnt_reg[5] ;
  wire \po_rdval_cnt_reg[6] ;
  wire \po_rdval_cnt_reg[7] ;
  wire \po_rdval_cnt_reg[8] ;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_i_1__0_n_0 ;
  wire \rclk_delay_reg[10]_srl11_n_0 ;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire [24:0]\rd_ptr_reg_rep[3]_0 ;
  wire [32:0]\rd_ptr_reg_rep[3]_1 ;
  wire read_calib;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire [0:0]ref_dll_lock_w;
  wire rst_out_i_1__0_n_0;
  wire rst_out_reg_n_0;
  wire rst_primitives;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire store_sr_req_r_reg;
  wire sync_pulse;
  wire sys_rst;
  wire wr_en;
  wire wr_en_10;
  wire wr_en_11;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire [3:0]\wr_ptr_timing_reg[0] ;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire write_calib;

  FDRE #(
    .INIT(1'b0)) 
    A_rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_primitives),
        .Q(ofifo_rst_reg),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF33E200E2)) 
    \FSM_onehot_cal1_state_r[32]_i_3 
       (.I0(\pi_counter_read_val_reg[5]_0 [1]),
        .I1(\calib_sel_reg[4] [3]),
        .I2(\pi_counter_read_val_reg[5]_1 [1]),
        .I3(\calib_sel_reg[4] [2]),
        .I4(\pi_counter_read_val_w[1]_2 [1]),
        .I5(\pi_rdval_cnt_reg[4] ),
        .O(\FSM_onehot_cal1_state_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF33E200E2)) 
    \FSM_onehot_cal1_state_r[32]_i_4 
       (.I0(\pi_counter_read_val_reg[5]_0 [0]),
        .I1(\calib_sel_reg[4] [3]),
        .I2(\pi_counter_read_val_reg[5]_1 [0]),
        .I3(\calib_sel_reg[4] [2]),
        .I4(\pi_counter_read_val_w[1]_2 [0]),
        .I5(\pi_rdval_cnt_reg[5] ),
        .O(\FSM_onehot_cal1_state_r_reg[0] ));
  LUT6 #(
    .INIT(64'hFFFFFFFF33E200E2)) 
    \FSM_onehot_cal1_state_r[32]_i_5 
       (.I0(\pi_counter_read_val_reg[5]_0 [2]),
        .I1(\calib_sel_reg[4] [3]),
        .I2(\pi_counter_read_val_reg[5]_1 [2]),
        .I3(\calib_sel_reg[4] [2]),
        .I4(\pi_counter_read_val_w[1]_2 [2]),
        .I5(\pi_rdval_cnt_reg[3] ),
        .O(\FSM_onehot_cal1_state_r_reg[0]_1 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \cnt_idel_dec_cpt_r[4]_i_3 
       (.I0(\pi_counter_read_val_w[1]_2 [4]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\pi_counter_read_val_reg[5]_1 [4]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\pi_counter_read_val_reg[5]_0 [4]),
        .O(\pi_rdval_cnt_reg[4] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \cnt_idel_dec_cpt_r[5]_i_3 
       (.I0(\pi_counter_read_val_w[1]_2 [5]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\pi_counter_read_val_reg[5]_1 [5]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\pi_counter_read_val_reg[5]_0 [5]),
        .O(\pi_rdval_cnt_reg[5] ));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized3 \ddr_byte_lane_A.ddr_byte_lane_A 
       (.A_idelay_ce19_out(A_idelay_ce19_out),
        .A_pi_counter_load_en161_out(A_pi_counter_load_en161_out),
        .A_pi_fine_enable157_out(A_pi_fine_enable157_out),
        .A_pi_fine_inc159_out(A_pi_fine_inc159_out),
        .A_pi_rst_dqs_find155_out(A_pi_rst_dqs_find155_out),
        .A_po_coarse_enable143_out(A_po_coarse_enable143_out),
        .A_po_fine_enable141_out(A_po_fine_enable141_out),
        .A_po_fine_inc145_out(A_po_fine_inc145_out),
        .A_rst_primitives_reg(ofifo_rst_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .CLK(CLK),
        .COUNTERREADVAL(COUNTERREADVAL),
        .D0(D0),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D9(D9),
        .DIC(DIC),
        .INBURSTPENDING(phy_control_i_n_21),
        .INRANKA({phy_control_i_n_4,phy_control_i_n_5}),
        .OUTBURSTPENDING(phy_control_i_n_25),
        .PCENABLECALIB(phy_encalib),
        .Q(Q),
        .\calib_sel_reg[0] (\calib_sel_reg[0] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\ddr3_dm[4] (\ddr3_dm[4] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\entry_cnt_reg[3] (\entry_cnt_reg[3] ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4]_0 ),
        .\entry_cnt_reg[4]_1 (\entry_cnt_reg[4]_1 ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (\gen_rd[4].rd_data_rise_wl_r_reg[4] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .mc_read_idle_r_reg(mc_read_idle_r_reg),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .\my_empty_reg[3] (\my_empty_reg[3] ),
        .\my_empty_reg[4]_rep__1 (\my_empty_reg[4]_rep__1 ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\not_strict_mode.app_rd_data_reg[487] (\not_strict_mode.app_rd_data_reg[487] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .ofifo_rst0(ofifo_rst0),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .p_101_in(p_101_in),
        .p_102_in(p_102_in),
        .p_103_out(p_103_out),
        .p_105_in(p_105_in),
        .p_106_in(p_106_in),
        .p_107_out(p_107_out),
        .p_109_in(p_109_in),
        .p_110_in(p_110_in),
        .p_111_out(p_111_out),
        .p_113_in(p_113_in),
        .p_114_in(p_114_in),
        .p_115_out(p_115_out),
        .p_117_in(p_117_in),
        .p_118_in(p_118_in),
        .p_119_out(p_119_out),
        .p_121_in(p_121_in),
        .p_122_in(p_122_in),
        .p_123_out(p_123_out),
        .p_125_in(p_125_in),
        .p_126_in(p_126_in),
        .p_127_out(p_127_out),
        .p_97_in(p_97_in),
        .p_98_in(p_98_in),
        .p_99_out(p_99_out),
        .p_9_in(p_9_in),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .pi_dqs_found_lanes(pi_dqs_found_lanes),
        .\pi_dqs_found_lanes_r1_reg[4] (\pi_dqs_found_lanes_r1_reg[4] ),
        .\pi_dqs_found_lanes_r1_reg[4]_0 (\pi_dqs_found_lanes_r1_reg[4]_0 ),
        .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),
        .\pi_stg2_reg_l_reg[5] (\pi_stg2_reg_l_reg[5] ),
        .\po_counter_read_val_reg[8] (A_po_counter_read_val),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .sync_pulse(sync_pulse),
        .wr_en(wr_en),
        .\wr_ptr_reg[1] (if_empty_r),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[1]_2 (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized4 \ddr_byte_lane_B.ddr_byte_lane_B 
       (.A_rst_primitives_reg(ofifo_rst_reg),
        .B_of_ctl_full(B_of_ctl_full),
        .B_po_coarse_enable27_out(B_po_coarse_enable27_out),
        .B_po_fine_enable24_out(B_po_fine_enable24_out),
        .B_po_fine_inc30_out(B_po_fine_inc30_out),
        .CLK(CLK),
        .COUNTERREADVAL(B_po_counter_read_val),
        .OUTBURSTPENDING(phy_control_i_n_24),
        .PCENABLECALIB(phy_encalib),
        .Q(\wr_ptr_timing_reg[3]_0 ),
        .calib_cmd_wren(calib_cmd_wren),
        .\cmd_pipe_plus.mc_cas_n_reg[2] (\cmd_pipe_plus.mc_cas_n_reg[2] ),
        .\cmd_pipe_plus.mc_cke_reg[3] (\cmd_pipe_plus.mc_cke_reg[3] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1),
        .mem_dq_out(mem_dq_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_1 ),
        .ofifo_rst(ofifo_rst),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3]_0 ),
        .sync_pulse(sync_pulse),
        .wr_en_10(wr_en_10),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized5 \ddr_byte_lane_C.ddr_byte_lane_C 
       (.A_rst_primitives_reg(ofifo_rst_reg),
        .CLK(CLK),
        .COUNTERREADVAL(C_po_counter_read_val),
        .C_of_ctl_full(C_of_ctl_full),
        .C_po_coarse_enable66_out(C_po_coarse_enable66_out),
        .C_po_fine_enable63_out(C_po_fine_enable63_out),
        .C_po_fine_inc69_out(C_po_fine_inc69_out),
        .D8(D8),
        .OUTBURSTPENDING(phy_control_i_n_23),
        .PCENABLECALIB(phy_encalib),
        .Q(\wr_ptr_timing_reg[3]_1 ),
        .calib_cmd_wren(calib_cmd_wren),
        .\cmd_pipe_plus.mc_ras_n_reg[2] (\cmd_pipe_plus.mc_ras_n_reg[2] ),
        .\ddr3_addr[3] (\ddr3_addr[3] ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2),
        .init_calib_complete_reg_rep__2_0(init_calib_complete_reg_rep__2_0),
        .init_calib_complete_reg_rep__2_1(init_calib_complete_reg_rep__2_1),
        .init_calib_complete_reg_rep__2_2(init_calib_complete_reg_rep__2_2),
        .init_calib_complete_reg_rep__2_3(init_calib_complete_reg_rep__2_3),
        .init_calib_complete_reg_rep__2_4(init_calib_complete_reg_rep__2_4),
        .init_calib_complete_reg_rep__2_5(init_calib_complete_reg_rep__2_5),
        .init_calib_complete_reg_rep__2_6(init_calib_complete_reg_rep__2_6),
        .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_2 ),
        .ofifo_rst(ofifo_rst),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3]_1 ),
        .sync_pulse(sync_pulse),
        .wr_en_11(wr_en_11),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0]_0 ));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized6 \ddr_byte_lane_D.ddr_byte_lane_D 
       (.A_rst_primitives_reg(ofifo_rst_reg),
        .A_rst_primitives_reg_0(C_po_counter_read_val),
        .A_rst_primitives_reg_1(A_po_counter_read_val),
        .B_of_ctl_full(B_of_ctl_full),
        .CLK(CLK),
        .COUNTERREADVAL(B_po_counter_read_val),
        .C_of_ctl_full(C_of_ctl_full),
        .D({\ddr_byte_lane_D.ddr_byte_lane_D_n_27 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_28 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_29 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_30 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_31 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_32 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_33 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_34 ,\ddr_byte_lane_D.ddr_byte_lane_D_n_35 }),
        .D_po_coarse_enable105_out(D_po_coarse_enable105_out),
        .D_po_fine_enable102_out(D_po_fine_enable102_out),
        .D_po_fine_inc108_out(D_po_fine_inc108_out),
        .OUTBURSTPENDING(phaser_ctl_bus),
        .PCENABLECALIB(phy_encalib),
        .calib_cmd_wren(calib_cmd_wren),
        .\calib_sel_reg[1] (\calib_sel_reg[4] [1:0]),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\ddr3_addr[13] (\ddr3_addr[13] ),
        .ddr_ck_out(ddr_ck_out),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .init_calib_complete_reg_rep_0(init_calib_complete_reg_rep_0),
        .init_calib_complete_reg_rep_1(init_calib_complete_reg_rep_1),
        .init_calib_complete_reg_rep_2(init_calib_complete_reg_rep_2),
        .init_calib_complete_reg_rep_3(init_calib_complete_reg_rep_3),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__14(init_calib_complete_reg_rep__14),
        .mc_cas_n(mc_cas_n),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[6] (\my_empty_reg[6] ),
        .of_ctl_full_v(of_ctl_full_v),
        .ofifo_rst(ofifo_rst),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_dout(phy_dout),
        .sync_pulse(sync_pulse));
  LUT3 #(
    .INIT(8'h80)) 
    \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_i_1 
       (.I0(mcGo_w),
        .I1(mcGo_w__0[1]),
        .I2(mcGo_w__0[0]),
        .O(mcGo_r1));
  FDRE #(
    .INIT(1'b0)) 
    mcGo_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_out_reg_n_0),
        .Q(mcGo_w),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_REF #(
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0)) 
    phaser_ref_i
       (.CLKIN(freq_refclk),
        .LOCKED(ref_dll_lock_w),
        .PWRDWN(1'b0),
        .RST(sys_rst));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHY_CONTROL #(
    .AO_TOGGLE(1),
    .AO_WRLVL_EN(4'b0000),
    .BURST_MODE("TRUE"),
    .CLK_RATIO(4),
    .CMD_OFFSET(8),
    .CO_DURATION(1),
    .DATA_CTL_A_N("TRUE"),
    .DATA_CTL_B_N("FALSE"),
    .DATA_CTL_C_N("FALSE"),
    .DATA_CTL_D_N("FALSE"),
    .DISABLE_SEQ_MATCH("TRUE"),
    .DI_DURATION(1),
    .DO_DURATION(1),
    .EVENTS_DELAY(18),
    .FOUR_WINDOW_CLOCKS(63),
    .MULTI_REGION("TRUE"),
    .PHY_COUNT_ENABLE("FALSE"),
    .RD_CMD_OFFSET_0(10),
    .RD_CMD_OFFSET_1(10),
    .RD_CMD_OFFSET_2(10),
    .RD_CMD_OFFSET_3(10),
    .RD_DURATION_0(6),
    .RD_DURATION_1(6),
    .RD_DURATION_2(6),
    .RD_DURATION_3(6),
    .SYNC_MODE("FALSE"),
    .WR_CMD_OFFSET_0(8),
    .WR_CMD_OFFSET_1(8),
    .WR_CMD_OFFSET_2(8),
    .WR_CMD_OFFSET_3(8),
    .WR_DURATION_0(7),
    .WR_DURATION_1(7),
    .WR_DURATION_2(7),
    .WR_DURATION_3(7)) 
    phy_control_i
       (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),
        .INBURSTPENDING({phy_control_i_n_18,phy_control_i_n_19,phy_control_i_n_20,phy_control_i_n_21}),
        .INRANKA({phy_control_i_n_4,phy_control_i_n_5}),
        .INRANKB({phy_control_i_n_6,phy_control_i_n_7}),
        .INRANKC({phy_control_i_n_8,phy_control_i_n_9}),
        .INRANKD({phy_control_i_n_10,phy_control_i_n_11}),
        .MEMREFCLK(mem_refclk),
        .OUTBURSTPENDING({phaser_ctl_bus,phy_control_i_n_23,phy_control_i_n_24,phy_control_i_n_25}),
        .PCENABLECALIB(phy_encalib),
        .PHYCLK(CLK),
        .PHYCTLALMOSTFULL(phy_control_i_n_0),
        .PHYCTLEMPTY(phy_ctl_mstr_empty),
        .PHYCTLFULL(_phy_ctl_full_p),
        .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),
        .PHYCTLREADY(phy_control_i_n_3),
        .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}),
        .PHYCTLWRENABLE(phy_ctl_wr_i2),
        .PLLLOCK(pll_lock),
        .READCALIBENABLE(read_calib),
        .REFDLLLOCK(ref_dll_lock_w),
        .RESET(rstdiv0_sync_r1),
        .SYNCIN(sync_pulse),
        .WRITECALIBENABLE(write_calib));
  LUT3 #(
    .INIT(8'hFE)) 
    phy_mc_ctl_full_r_i_1
       (.I0(_phy_ctl_full_p),
        .I1(_phy_ctl_full_p__0[1]),
        .I2(_phy_ctl_full_p__0[0]),
        .O(phy_mc_ctl_full));
  FDRE \pi_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pi_counter_read_val_w[1]_2 [0]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pi_counter_read_val_w[1]_2 [1]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pi_counter_read_val_w[1]_2 [2]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\pi_counter_read_val_w[1]_2 [3]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[4]),
        .Q(\pi_counter_read_val_w[1]_2 [4]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[5]),
        .Q(\pi_counter_read_val_w[1]_2 [5]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_rdval_cnt[0]_i_2 
       (.I0(\pi_counter_read_val_w[1]_2 [0]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\pi_counter_read_val_reg[5]_1 [0]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\pi_counter_read_val_reg[5]_0 [0]),
        .O(\pi_rdval_cnt_reg[0] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_rdval_cnt[1]_i_2 
       (.I0(\pi_counter_read_val_w[1]_2 [1]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\pi_counter_read_val_reg[5]_1 [1]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\pi_counter_read_val_reg[5]_0 [1]),
        .O(\pi_rdval_cnt_reg[1] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_rdval_cnt[2]_i_2 
       (.I0(\pi_counter_read_val_w[1]_2 [2]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\pi_counter_read_val_reg[5]_1 [2]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\pi_counter_read_val_reg[5]_0 [2]),
        .O(\pi_rdval_cnt_reg[2] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_rdval_cnt[3]_i_2 
       (.I0(\pi_counter_read_val_w[1]_2 [3]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\pi_counter_read_val_reg[5]_1 [3]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\pi_counter_read_val_reg[5]_0 [3]),
        .O(\pi_rdval_cnt_reg[3] ));
  FDRE \po_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_35 ),
        .Q(\po_counter_read_val_w[1]_1 [0]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_34 ),
        .Q(\po_counter_read_val_w[1]_1 [1]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_33 ),
        .Q(\po_counter_read_val_w[1]_1 [2]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_32 ),
        .Q(\po_counter_read_val_w[1]_1 [3]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_31 ),
        .Q(\po_counter_read_val_w[1]_1 [4]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_30 ),
        .Q(\po_counter_read_val_w[1]_1 [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_29 ),
        .Q(\po_counter_read_val_w[1]_1 [6]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_28 ),
        .Q(\po_counter_read_val_w[1]_1 [7]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_D.ddr_byte_lane_D_n_27 ),
        .Q(\po_counter_read_val_w[1]_1 [8]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[0]_i_2 
       (.I0(\po_counter_read_val_w[1]_1 [0]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [0]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [0]),
        .O(\po_rdval_cnt_reg[0] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[1]_i_2 
       (.I0(\po_counter_read_val_w[1]_1 [1]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [1]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [1]),
        .O(\po_rdval_cnt_reg[1] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[2]_i_2 
       (.I0(\po_counter_read_val_w[1]_1 [2]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [2]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [2]),
        .O(\po_rdval_cnt_reg[2] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[3]_i_3 
       (.I0(\po_counter_read_val_w[1]_1 [3]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [3]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [3]),
        .O(\po_rdval_cnt_reg[3] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[4]_i_3 
       (.I0(\po_counter_read_val_w[1]_1 [4]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [4]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [4]),
        .O(\po_rdval_cnt_reg[4] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[5]_i_3 
       (.I0(\po_counter_read_val_w[1]_1 [5]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [5]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [5]),
        .O(\po_rdval_cnt_reg[5] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[6]_i_2 
       (.I0(\po_counter_read_val_w[1]_1 [6]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [6]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [6]),
        .O(\po_rdval_cnt_reg[6] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[7]_i_2 
       (.I0(\po_counter_read_val_w[1]_1 [7]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [7]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [7]),
        .O(\po_rdval_cnt_reg[7] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[8]_i_4 
       (.I0(\po_counter_read_val_w[1]_1 [8]),
        .I1(\calib_sel_reg[4] [2]),
        .I2(\po_counter_read_val_reg[8]_0 [8]),
        .I3(\calib_sel_reg[4] [3]),
        .I4(\po_counter_read_val_reg[8]_1 [8]),
        .O(\po_rdval_cnt_reg[8] ));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) 
  SRL16E \rclk_delay_reg[10]_srl11 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(\rclk_delay_reg[10]_srl11_i_1__0_n_0 ),
        .Q(\rclk_delay_reg[10]_srl11_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rclk_delay_reg[10]_srl11_i_1__0 
       (.I0(rst_primitives),
        .O(\rclk_delay_reg[10]_srl11_i_1__0_n_0 ));
  FDRE \rclk_delay_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rclk_delay_reg[10]_srl11_n_0 ),
        .Q(rclk_delay_11),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_out_i_1__0
       (.I0(rclk_delay_11),
        .I1(rst_out_reg_n_0),
        .O(rst_out_i_1__0_n_0));
  FDCE #(
    .INIT(1'b0)) 
    rst_out_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(rstdiv0_sync_r1_reg_rep__0),
        .D(rst_out_i_1__0_n_0),
        .Q(rst_out_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    rst_primitives_i_1__0
       (.I0(phy_control_i_n_3),
        .O(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in),
        .Q(rst_primitives),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    store_sr_req_r_i_2
       (.I0(\pi_rdval_cnt_reg[4] ),
        .I1(\pi_rdval_cnt_reg[1] ),
        .I2(\pi_rdval_cnt_reg[2] ),
        .I3(\pi_rdval_cnt_reg[3] ),
        .I4(\pi_rdval_cnt_reg[0] ),
        .I5(\pi_rdval_cnt_reg[5] ),
        .O(store_sr_req_r_reg));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_4lanes" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized1
   (\rd_ptr_timing_reg[1] ,
    pi_dqs_found_lanes,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    pi_phase_locked_all_r1_reg,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    p_5_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ,
    p_17_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ,
    p_25_in,
    p_30_in,
    p_29_in,
    p_1_in,
    \ddr3_dm[7] ,
    \rd_ptr_timing_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ,
    pi_phase_locked_all_r1_reg_0,
    \my_empty_reg[7] ,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    p_34_in,
    p_33_in,
    p_38_in,
    p_37_in,
    p_42_in,
    p_41_in,
    p_46_in,
    p_45_in,
    \ddr3_dm[6] ,
    p_3_in,
    p_50_in,
    p_49_in,
    p_54_in,
    p_53_in,
    p_58_in,
    p_57_in,
    p_62_in,
    p_61_in,
    if_empty_r,
    \rd_ptr_timing_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ,
    pi_phase_locked_all_r1_reg_1,
    \my_empty_reg[7]_0 ,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    p_66_in,
    p_65_in,
    p_70_in,
    p_69_in,
    p_74_in,
    p_73_in,
    p_78_in,
    p_77_in,
    p_82_in,
    p_81_in,
    p_86_in,
    p_85_in,
    p_90_in,
    p_89_in,
    p_94_in,
    p_93_in,
    p_7_in,
    \ddr3_dm[5] ,
    _phy_ctl_full_p__0,
    rst_sync_r1_reg,
    mcGo_w__0,
    idelay_ld_rst_3,
    \my_empty_reg[7]_1 ,
    idelay_ld_rst_4,
    \my_empty_reg[7]_2 ,
    idelay_ld_rst_5,
    phy_rddata_en,
    rd_active_r_reg,
    \my_empty_reg[4]_rep__1 ,
    Q,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \not_strict_mode.app_rd_data_reg[488] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \my_empty_reg[1] ,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    ADDRA,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \not_strict_mode.app_rd_data_reg[511] ,
    wr_en_12,
    \entry_cnt_reg[4] ,
    wr_en_13,
    \entry_cnt_reg[4]_0 ,
    ofs_rdy_r_reg,
    wr_en_14,
    ofs_rdy_r_reg_0,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7]_3 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_timing_reg[3]_0 ,
    \my_empty_reg[7]_4 ,
    \wr_ptr_reg[0]_1 ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_timing_reg[3]_1 ,
    \my_empty_reg[7]_5 ,
    \po_rdval_cnt_reg[8] ,
    \pi_rdval_cnt_reg[5] ,
    \not_strict_mode.app_rd_data_reg[232] ,
    \not_strict_mode.app_rd_data_reg[496]_0 ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    \wr_ptr_reg[1]_2 ,
    \read_fifo.tail_r_reg[1] ,
    DIA,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    A_pi_counter_load_en87_out,
    \calib_sel_reg[0] ,
    A_pi_fine_enable83_out,
    A_pi_fine_inc85_out,
    freq_refclk,
    mem_refclk,
    mc_read_idle_r_reg,
    A_pi_rst_dqs_find81_out,
    sync_pulse,
    CLK,
    \calib_zero_inputs_reg[2] ,
    A_po_coarse_enable69_out,
    A_po_fine_enable67_out,
    A_po_fine_inc71_out,
    \write_buffer.wr_buf_out_data_reg[511] ,
    \write_buffer.wr_buf_out_data_reg[510] ,
    \write_buffer.wr_buf_out_data_reg[509] ,
    init_calib_complete_reg_rep__10,
    \write_buffer.wr_buf_out_data_reg[507] ,
    \write_buffer.wr_buf_out_data_reg[506] ,
    \write_buffer.wr_buf_out_data_reg[505] ,
    init_calib_complete_reg_rep__10_0,
    init_calib_complete_reg_rep__9,
    A_rst_primitives_reg_0,
    mc_read_idle_r_reg_0,
    A_idelay_ce10_out,
    idelay_inc,
    \gen_byte_sel_div2.calib_in_common_reg ,
    mc_read_idle_r_reg_1,
    mc_read_idle_r_reg_2,
    mc_read_idle_r_reg_3,
    mc_read_idle_r_reg_4,
    mc_read_idle_r_reg_5,
    mc_read_idle_r_reg_6,
    p_31_out,
    B_pi_counter_load_en35_out,
    \calib_sel_reg[0]_0 ,
    B_pi_fine_enable31_out,
    B_pi_fine_inc33_out,
    mc_read_idle_r_reg_7,
    B_pi_rst_dqs_find29_out,
    \calib_zero_inputs_reg[2]_0 ,
    B_po_coarse_enable17_out,
    B_po_fine_enable15_out,
    B_po_fine_inc19_out,
    \write_buffer.wr_buf_out_data_reg[503] ,
    \write_buffer.wr_buf_out_data_reg[502] ,
    \write_buffer.wr_buf_out_data_reg[501] ,
    init_calib_complete_reg_rep__12,
    init_calib_complete_reg_rep__11,
    \write_buffer.wr_buf_out_data_reg[499] ,
    \write_buffer.wr_buf_out_data_reg[498] ,
    \write_buffer.wr_buf_out_data_reg[497] ,
    init_calib_complete_reg_rep__11_0,
    A_rst_primitives_reg_1,
    p_35_out,
    B_idelay_ce6_out,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    p_39_out,
    p_43_out,
    p_47_out,
    p_51_out,
    p_55_out,
    p_59_out,
    p_63_out,
    C_pi_counter_load_en61_out,
    \calib_sel_reg[1] ,
    C_pi_fine_enable57_out,
    C_pi_fine_inc59_out,
    mc_read_idle_r_reg_8,
    C_pi_rst_dqs_find55_out,
    \calib_zero_inputs_reg[2]_1 ,
    C_po_coarse_enable43_out,
    C_po_fine_enable41_out,
    C_po_fine_inc45_out,
    \write_buffer.wr_buf_out_data_reg[495] ,
    \write_buffer.wr_buf_out_data_reg[494] ,
    \write_buffer.wr_buf_out_data_reg[493] ,
    init_calib_complete_reg_rep__13,
    \write_buffer.wr_buf_out_data_reg[491] ,
    \write_buffer.wr_buf_out_data_reg[490] ,
    \write_buffer.wr_buf_out_data_reg[489] ,
    init_calib_complete_reg_rep__12_0,
    init_calib_complete_reg_rep__12_1,
    A_rst_primitives_reg_2,
    p_67_out,
    C_idelay_ce2_out,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    p_71_out,
    p_75_out,
    p_79_out,
    p_83_out,
    p_87_out,
    p_91_out,
    p_95_out,
    phy_ctl_mstr_empty,
    phy_ctl_wr_i2,
    pll_lock,
    read_calib,
    rstdiv0_sync_r1,
    write_calib,
    PHYCTLWD,
    sys_rst,
    phy_if_reset,
    rstdiv0_sync_r1_reg_rep__1,
    phy_data_wr_en,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ,
    \my_empty_reg[4]_rep__1_0 ,
    if_empty_r_0,
    \my_empty_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    tail_r,
    init_complete_r1_timing_reg,
    rstdiv0_sync_r1_reg_rep__21,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \rd_mux_sel_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,
    calib_wrdata_en,
    init_calib_complete_reg_rep__9_0,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_wrdata_en_reg ,
    \cmd_pipe_plus.mc_wrdata_en_reg_0 ,
    \rd_ptr_reg_rep[3] ,
    init_calib_complete_reg_rep__11_1,
    \rd_ptr_reg_rep[3]_0 ,
    init_calib_complete_reg_rep__12_2,
    \rd_ptr_reg_rep[3]_1 ,
    \po_stg2_wrcal_cnt_reg[2] ,
    \calib_sel_reg[1]_0 );
  output [1:0]\rd_ptr_timing_reg[1] ;
  output [2:0]pi_dqs_found_lanes;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output pi_phase_locked_all_r1_reg;
  output \pi_dqs_found_lanes_r1_reg[8] ;
  output \pi_dqs_found_lanes_r1_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output p_5_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  output p_17_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ;
  output p_25_in;
  output p_30_in;
  output p_29_in;
  output p_1_in;
  output \ddr3_dm[7] ;
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ;
  output pi_phase_locked_all_r1_reg_0;
  output \my_empty_reg[7] ;
  output \pi_dqs_found_lanes_r1_reg[9] ;
  output \pi_dqs_found_lanes_r1_reg[9]_0 ;
  output p_34_in;
  output p_33_in;
  output p_38_in;
  output p_37_in;
  output p_42_in;
  output p_41_in;
  output p_46_in;
  output p_45_in;
  output \ddr3_dm[6] ;
  output p_3_in;
  output p_50_in;
  output p_49_in;
  output p_54_in;
  output p_53_in;
  output p_58_in;
  output p_57_in;
  output p_62_in;
  output p_61_in;
  output [0:0]if_empty_r;
  output [1:0]\rd_ptr_timing_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ;
  output pi_phase_locked_all_r1_reg_1;
  output \my_empty_reg[7]_0 ;
  output \pi_dqs_found_lanes_r1_reg[10] ;
  output \pi_dqs_found_lanes_r1_reg[10]_0 ;
  output p_66_in;
  output p_65_in;
  output p_70_in;
  output p_69_in;
  output p_74_in;
  output p_73_in;
  output p_78_in;
  output p_77_in;
  output p_82_in;
  output p_81_in;
  output p_86_in;
  output p_85_in;
  output p_90_in;
  output p_89_in;
  output p_94_in;
  output p_93_in;
  output p_7_in;
  output \ddr3_dm[5] ;
  output [0:0]_phy_ctl_full_p__0;
  output [0:0]rst_sync_r1_reg;
  output [0:0]mcGo_w__0;
  output idelay_ld_rst_3;
  output \my_empty_reg[7]_1 ;
  output idelay_ld_rst_4;
  output \my_empty_reg[7]_2 ;
  output idelay_ld_rst_5;
  output phy_rddata_en;
  output rd_active_r_reg;
  output \my_empty_reg[4]_rep__1 ;
  output [0:0]Q;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  output [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \my_empty_reg[1] ;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [0:0]ADDRA;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output [191:0]\not_strict_mode.app_rd_data_reg[511] ;
  output wr_en_12;
  output [2:0]\entry_cnt_reg[4] ;
  output wr_en_13;
  output [0:0]\entry_cnt_reg[4]_0 ;
  output ofs_rdy_r_reg;
  output wr_en_14;
  output ofs_rdy_r_reg_0;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7]_3 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\my_empty_reg[7]_4 ;
  output \wr_ptr_reg[0]_1 ;
  output \wr_ptr_reg[1]_1 ;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\my_empty_reg[7]_5 ;
  output [8:0]\po_rdval_cnt_reg[8] ;
  output [5:0]\pi_rdval_cnt_reg[5] ;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \not_strict_mode.app_rd_data_reg[496]_0 ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output \wr_ptr_reg[1]_2 ;
  output \read_fifo.tail_r_reg[1] ;
  output [1:0]DIA;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  input A_pi_counter_load_en87_out;
  input \calib_sel_reg[0] ;
  input A_pi_fine_enable83_out;
  input A_pi_fine_inc85_out;
  input freq_refclk;
  input mem_refclk;
  input mc_read_idle_r_reg;
  input A_pi_rst_dqs_find81_out;
  input sync_pulse;
  input CLK;
  input [5:0]\calib_zero_inputs_reg[2] ;
  input A_po_coarse_enable69_out;
  input A_po_fine_enable67_out;
  input A_po_fine_inc71_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  input [7:0]init_calib_complete_reg_rep__10;
  input [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  input [7:0]init_calib_complete_reg_rep__10_0;
  input [7:0]init_calib_complete_reg_rep__9;
  input A_rst_primitives_reg_0;
  input mc_read_idle_r_reg_0;
  input A_idelay_ce10_out;
  input idelay_inc;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input mc_read_idle_r_reg_1;
  input mc_read_idle_r_reg_2;
  input mc_read_idle_r_reg_3;
  input mc_read_idle_r_reg_4;
  input mc_read_idle_r_reg_5;
  input mc_read_idle_r_reg_6;
  input p_31_out;
  input B_pi_counter_load_en35_out;
  input \calib_sel_reg[0]_0 ;
  input B_pi_fine_enable31_out;
  input B_pi_fine_inc33_out;
  input mc_read_idle_r_reg_7;
  input B_pi_rst_dqs_find29_out;
  input [5:0]\calib_zero_inputs_reg[2]_0 ;
  input B_po_coarse_enable17_out;
  input B_po_fine_enable15_out;
  input B_po_fine_inc19_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  input [7:0]init_calib_complete_reg_rep__12;
  input [7:0]init_calib_complete_reg_rep__11;
  input [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  input [7:0]init_calib_complete_reg_rep__11_0;
  input A_rst_primitives_reg_1;
  input p_35_out;
  input B_idelay_ce6_out;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input p_39_out;
  input p_43_out;
  input p_47_out;
  input p_51_out;
  input p_55_out;
  input p_59_out;
  input p_63_out;
  input C_pi_counter_load_en61_out;
  input \calib_sel_reg[1] ;
  input C_pi_fine_enable57_out;
  input C_pi_fine_inc59_out;
  input mc_read_idle_r_reg_8;
  input C_pi_rst_dqs_find55_out;
  input [5:0]\calib_zero_inputs_reg[2]_1 ;
  input C_po_coarse_enable43_out;
  input C_po_fine_enable41_out;
  input C_po_fine_inc45_out;
  input [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  input [7:0]init_calib_complete_reg_rep__13;
  input [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  input [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  input [7:0]init_calib_complete_reg_rep__12_0;
  input [7:0]init_calib_complete_reg_rep__12_1;
  input A_rst_primitives_reg_2;
  input p_67_out;
  input C_idelay_ce2_out;
  input \gen_byte_sel_div2.calib_in_common_reg_1 ;
  input p_71_out;
  input p_75_out;
  input p_79_out;
  input p_83_out;
  input p_87_out;
  input p_91_out;
  input p_95_out;
  input phy_ctl_mstr_empty;
  input phy_ctl_wr_i2;
  input pll_lock;
  input read_calib;
  input rstdiv0_sync_r1;
  input write_calib;
  input [10:0]PHYCTLWD;
  input sys_rst;
  input phy_if_reset;
  input rstdiv0_sync_r1_reg_rep__1;
  input phy_data_wr_en;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ;
  input [0:0]\my_empty_reg[4]_rep__1_0 ;
  input [0:0]if_empty_r_0;
  input \my_empty_reg[0] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input [0:0]tail_r;
  input init_complete_r1_timing_reg;
  input rstdiv0_sync_r1_reg_rep__21;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  input [1:0]\rd_mux_sel_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  input [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  input calib_wrdata_en;
  input init_calib_complete_reg_rep__9_0;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_wrdata_en_reg ;
  input \cmd_pipe_plus.mc_wrdata_en_reg_0 ;
  input [7:0]\rd_ptr_reg_rep[3] ;
  input init_calib_complete_reg_rep__11_1;
  input [7:0]\rd_ptr_reg_rep[3]_0 ;
  input init_calib_complete_reg_rep__12_2;
  input [7:0]\rd_ptr_reg_rep[3]_1 ;
  input [1:0]\po_stg2_wrcal_cnt_reg[2] ;
  input [1:0]\calib_sel_reg[1]_0 ;

  wire [0:0]ADDRA;
  wire A_idelay_ce10_out;
  wire A_pi_counter_load_en87_out;
  wire [5:0]A_pi_counter_read_val;
  wire A_pi_fine_enable83_out;
  wire A_pi_fine_inc85_out;
  wire A_pi_rst_dqs_find81_out;
  wire A_po_coarse_enable69_out;
  wire [8:0]A_po_counter_read_val;
  wire A_po_fine_enable67_out;
  wire A_po_fine_inc71_out;
  wire A_rst_primitives;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire B_idelay_ce6_out;
  wire B_pi_counter_load_en35_out;
  wire [5:0]B_pi_counter_read_val;
  wire B_pi_fine_enable31_out;
  wire B_pi_fine_inc33_out;
  wire B_pi_rst_dqs_find29_out;
  wire B_po_coarse_enable17_out;
  wire [8:0]B_po_counter_read_val;
  wire B_po_fine_enable15_out;
  wire B_po_fine_inc19_out;
  wire CLK;
  wire C_idelay_ce2_out;
  wire C_pi_counter_load_en61_out;
  wire [5:0]C_pi_counter_read_val;
  wire C_pi_fine_enable57_out;
  wire C_pi_fine_inc59_out;
  wire C_pi_rst_dqs_find55_out;
  wire C_po_coarse_enable43_out;
  wire [8:0]C_po_counter_read_val;
  wire C_po_fine_enable41_out;
  wire C_po_fine_inc45_out;
  wire [1:0]DIA;
  wire [10:0]PHYCTLWD;
  wire [0:0]Q;
  wire [2:2]_phy_ctl_a_full_p;
  wire [0:0]_phy_ctl_full_p__0;
  wire [11:8]aux_out_;
  wire \calib_sel_reg[0] ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[1] ;
  wire [1:0]\calib_sel_reg[1]_0 ;
  wire calib_wrdata_en;
  wire [5:0]\calib_zero_inputs_reg[2] ;
  wire [5:0]\calib_zero_inputs_reg[2]_0 ;
  wire [5:0]\calib_zero_inputs_reg[2]_1 ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg ;
  wire \cmd_pipe_plus.mc_wrdata_en_reg_0 ;
  wire \ddr3_dm[5] ;
  wire \ddr3_dm[6] ;
  wire \ddr3_dm[7] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 ;
  wire [2:0]\entry_cnt_reg[4] ;
  wire [0:0]\entry_cnt_reg[4]_0 ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  wire idelay_inc;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [3:3]if_empty_r_1;
  wire [3:3]if_empty_r_3;
  wire ififo_rd_en_in;
  wire [7:0]init_calib_complete_reg_rep__10;
  wire [7:0]init_calib_complete_reg_rep__10_0;
  wire [7:0]init_calib_complete_reg_rep__11;
  wire [7:0]init_calib_complete_reg_rep__11_0;
  wire init_calib_complete_reg_rep__11_1;
  wire [7:0]init_calib_complete_reg_rep__12;
  wire [7:0]init_calib_complete_reg_rep__12_0;
  wire [7:0]init_calib_complete_reg_rep__12_1;
  wire init_calib_complete_reg_rep__12_2;
  wire [7:0]init_calib_complete_reg_rep__13;
  wire [7:0]init_calib_complete_reg_rep__9;
  wire init_calib_complete_reg_rep__9_0;
  wire init_complete_r1_timing_reg;
  wire [0:0]mcGo_w__0;
  wire mc_read_idle_r_reg;
  wire mc_read_idle_r_reg_0;
  wire mc_read_idle_r_reg_1;
  wire mc_read_idle_r_reg_2;
  wire mc_read_idle_r_reg_3;
  wire mc_read_idle_r_reg_4;
  wire mc_read_idle_r_reg_5;
  wire mc_read_idle_r_reg_6;
  wire mc_read_idle_r_reg_7;
  wire mc_read_idle_r_reg_8;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[4]_rep__1 ;
  wire [0:0]\my_empty_reg[4]_rep__1_0 ;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg[7]_1 ;
  wire \my_empty_reg[7]_2 ;
  wire [3:0]\my_empty_reg[7]_3 ;
  wire [3:0]\my_empty_reg[7]_4 ;
  wire [3:0]\my_empty_reg[7]_5 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  wire [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  wire \not_strict_mode.app_rd_data_reg[496]_0 ;
  wire [191:0]\not_strict_mode.app_rd_data_reg[511] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  wire ofs_rdy_r_reg;
  wire ofs_rdy_r_reg_0;
  wire p_0_in;
  wire p_17_in;
  wire p_1_in;
  wire p_25_in;
  wire p_29_in;
  wire p_30_in;
  wire p_31_out;
  wire p_33_in;
  wire p_34_in;
  wire p_35_out;
  wire p_37_in;
  wire p_38_in;
  wire p_39_out;
  wire p_3_in;
  wire p_41_in;
  wire p_42_in;
  wire p_43_out;
  wire p_45_in;
  wire p_46_in;
  wire p_47_out;
  wire p_49_in;
  wire p_50_in;
  wire p_51_out;
  wire p_53_in;
  wire p_54_in;
  wire p_55_out;
  wire p_57_in;
  wire p_58_in;
  wire p_59_out;
  wire p_5_in;
  wire p_61_in;
  wire p_62_in;
  wire p_63_out;
  wire p_65_in;
  wire p_66_in;
  wire p_67_out;
  wire p_69_in;
  wire p_70_in;
  wire p_71_out;
  wire p_73_in;
  wire p_74_in;
  wire p_75_out;
  wire p_77_in;
  wire p_78_in;
  wire p_79_out;
  wire p_7_in;
  wire p_81_in;
  wire p_82_in;
  wire p_83_out;
  wire p_85_in;
  wire p_86_in;
  wire p_87_out;
  wire p_89_in;
  wire p_90_in;
  wire p_91_out;
  wire p_93_in;
  wire p_94_in;
  wire p_95_out;
  wire [15:0]phaser_ctl_bus;
  wire phy_control_i_n_1;
  wire phy_control_i_n_3;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_wr_i2;
  wire phy_data_wr_en;
  wire [1:0]phy_encalib;
  wire phy_if_reset;
  wire phy_rddata_en;
  wire \pi_counter_read_val[0]_i_1_n_0 ;
  wire \pi_counter_read_val[1]_i_1_n_0 ;
  wire \pi_counter_read_val[2]_i_1_n_0 ;
  wire \pi_counter_read_val[3]_i_1_n_0 ;
  wire \pi_counter_read_val[4]_i_1_n_0 ;
  wire \pi_counter_read_val[5]_i_1_n_0 ;
  wire [2:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire pi_phase_locked_all_r1_reg;
  wire pi_phase_locked_all_r1_reg_0;
  wire pi_phase_locked_all_r1_reg_1;
  wire [5:0]\pi_rdval_cnt_reg[5] ;
  wire pll_lock;
  wire \po_counter_read_val[0]_i_1_n_0 ;
  wire \po_counter_read_val[1]_i_1_n_0 ;
  wire \po_counter_read_val[2]_i_1_n_0 ;
  wire \po_counter_read_val[3]_i_1_n_0 ;
  wire \po_counter_read_val[4]_i_1_n_0 ;
  wire \po_counter_read_val[5]_i_1_n_0 ;
  wire \po_counter_read_val[6]_i_1_n_0 ;
  wire \po_counter_read_val[7]_i_1_n_0 ;
  wire \po_counter_read_val[8]_i_1_n_0 ;
  wire [8:0]\po_rdval_cnt_reg[8] ;
  wire [1:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire rclk_;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_i_1__0__0_n_0 ;
  wire \rclk_delay_reg[10]_srl11_n_0 ;
  wire rd_active_r_reg;
  wire [1:0]\rd_mux_sel_r_reg[2] ;
  wire [7:0]\rd_ptr_reg_rep[3] ;
  wire [7:0]\rd_ptr_reg_rep[3]_0 ;
  wire [7:0]\rd_ptr_reg_rep[3]_1 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rd_ptr_timing_reg[1]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1]_1 ;
  wire read_calib;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire rst_out_i_1__0__0_n_0;
  wire rst_out_reg_n_0;
  wire rst_primitives;
  wire rst_r4;
  wire [0:0]rst_sync_r1_reg;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sync_pulse;
  wire sys_rst;
  wire [0:0]tail_r;
  wire wr_en_12;
  wire wr_en_13;
  wire wr_en_14;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[0]_1 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  wire write_calib;

  FDRE #(
    .INIT(1'b0)) 
    A_rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_primitives),
        .Q(A_rst_primitives),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane \ddr_byte_lane_A.ddr_byte_lane_A 
       (.ADDRA(ADDRA),
        .A_idelay_ce10_out(A_idelay_ce10_out),
        .A_pi_counter_load_en87_out(A_pi_counter_load_en87_out),
        .A_pi_fine_enable83_out(A_pi_fine_enable83_out),
        .A_pi_fine_inc85_out(A_pi_fine_inc85_out),
        .A_pi_rst_dqs_find81_out(A_pi_rst_dqs_find81_out),
        .A_po_coarse_enable69_out(A_po_coarse_enable69_out),
        .A_po_fine_enable67_out(A_po_fine_enable67_out),
        .A_po_fine_inc71_out(A_po_fine_inc71_out),
        .A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_0),
        .CLK(CLK),
        .COUNTERREADVAL(A_pi_counter_read_val),
        .PCENABLECALIB(phy_encalib),
        .Q(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\calib_sel_reg[0] (\calib_sel_reg[0] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[2] (\calib_zero_inputs_reg[2] ),
        .\ddr3_dm[7] (\ddr3_dm[7] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_10 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_13 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_14 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_15 (if_empty_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_7 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_9 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_8 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (\gen_rd[7].rd_data_rise_wl_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .if_empty_r(if_empty_r_1),
        .if_empty_r_0(if_empty_r_0),
        .if_empty_r_1(if_empty_r_3),
        .ififo_rd_en_in(ififo_rd_en_in),
        .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10),
        .init_calib_complete_reg_rep__10_0(init_calib_complete_reg_rep__10_0),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9),
        .init_calib_complete_reg_rep__9_0(init_calib_complete_reg_rep__9_0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .mc_read_idle_r_reg(mc_read_idle_r_reg),
        .mc_read_idle_r_reg_0(mc_read_idle_r_reg_0),
        .mc_read_idle_r_reg_1(mc_read_idle_r_reg_1),
        .mc_read_idle_r_reg_2(mc_read_idle_r_reg_2),
        .mc_read_idle_r_reg_3(mc_read_idle_r_reg_3),
        .mc_read_idle_r_reg_4(mc_read_idle_r_reg_4),
        .mc_read_idle_r_reg_5(mc_read_idle_r_reg_5),
        .mc_read_idle_r_reg_6(mc_read_idle_r_reg_6),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[0] (\my_empty_reg[0] ),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[3] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 [3]),
        .\my_empty_reg[3]_0 (Q),
        .\my_empty_reg[4]_rep__1 (\my_empty_reg[4]_rep__1 ),
        .\my_empty_reg[4]_rep__1_0 (\my_empty_reg[4]_rep__1_0 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_3 ),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376] ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[511] ({\not_strict_mode.app_rd_data_reg[511] [191:184],\not_strict_mode.app_rd_data_reg[511] [167:160],\not_strict_mode.app_rd_data_reg[511] [143:136],\not_strict_mode.app_rd_data_reg[511] [119:112],\not_strict_mode.app_rd_data_reg[511] [95:88],\not_strict_mode.app_rd_data_reg[511] [71:64],\not_strict_mode.app_rd_data_reg[511] [47:40],\not_strict_mode.app_rd_data_reg[511] [23:16]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),
        .p_17_in(p_17_in),
        .p_1_in(p_1_in),
        .p_25_in(p_25_in),
        .p_29_in(p_29_in),
        .p_30_in(p_30_in),
        .p_31_out(p_31_out),
        .p_5_in(p_5_in),
        .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .phy_rddata_en(phy_rddata_en),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[0]),
        .\pi_dqs_found_lanes_r1_reg[8] (\pi_dqs_found_lanes_r1_reg[8] ),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),
        .\po_counter_read_val_reg[8] (A_po_counter_read_val),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .rd_active_r_reg(rd_active_r_reg),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .rst_r4(rst_r4),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sync_pulse(sync_pulse),
        .tail_r(tail_r),
        .wr_en_12(wr_en_12),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ),
        .\write_buffer.wr_buf_out_data_reg[505] (\write_buffer.wr_buf_out_data_reg[505] ),
        .\write_buffer.wr_buf_out_data_reg[506] (\write_buffer.wr_buf_out_data_reg[506] ),
        .\write_buffer.wr_buf_out_data_reg[507] (\write_buffer.wr_buf_out_data_reg[507] ),
        .\write_buffer.wr_buf_out_data_reg[509] (\write_buffer.wr_buf_out_data_reg[509] ),
        .\write_buffer.wr_buf_out_data_reg[510] (\write_buffer.wr_buf_out_data_reg[510] ),
        .\write_buffer.wr_buf_out_data_reg[511] (\write_buffer.wr_buf_out_data_reg[511] ));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized7 \ddr_byte_lane_B.ddr_byte_lane_B 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_1),
        .B_idelay_ce6_out(B_idelay_ce6_out),
        .B_pi_counter_load_en35_out(B_pi_counter_load_en35_out),
        .B_pi_fine_enable31_out(B_pi_fine_enable31_out),
        .B_pi_fine_inc33_out(B_pi_fine_inc33_out),
        .B_pi_rst_dqs_find29_out(B_pi_rst_dqs_find29_out),
        .B_po_coarse_enable17_out(B_po_coarse_enable17_out),
        .B_po_fine_enable15_out(B_po_fine_enable15_out),
        .B_po_fine_inc19_out(B_po_fine_inc19_out),
        .CLK(CLK),
        .COUNTERREADVAL(B_pi_counter_read_val),
        .DIA(DIA),
        .PCENABLECALIB(phy_encalib),
        .Q(\not_strict_mode.app_rd_data_reg[496] ),
        .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[2] (\calib_zero_inputs_reg[2]_0 ),
        .\cmd_pipe_plus.mc_wrdata_en_reg (\cmd_pipe_plus.mc_wrdata_en_reg ),
        .\ddr3_dm[6] (\ddr3_dm[6] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_11 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4]_0 ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (\gen_rd[6].rd_data_rise_wl_r_reg[6] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .if_empty_r(if_empty_r_3),
        .if_empty_r_0(if_empty_r_1),
        .ififo_rd_en_in(ififo_rd_en_in),
        .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11),
        .init_calib_complete_reg_rep__11_0(init_calib_complete_reg_rep__11_0),
        .init_calib_complete_reg_rep__11_1(init_calib_complete_reg_rep__11_1),
        .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_0),
        .mc_read_idle_r_reg(mc_read_idle_r_reg_7),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[0] (if_empty_r),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .\my_empty_reg[3] (Q),
        .\my_empty_reg[3]_0 ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 [0]}),
        .\my_empty_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_4 ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496]_0 ),
        .\not_strict_mode.app_rd_data_reg[503] ({\not_strict_mode.app_rd_data_reg[511] [183:176],\not_strict_mode.app_rd_data_reg[511] [159:152],\not_strict_mode.app_rd_data_reg[511] [135:128],\not_strict_mode.app_rd_data_reg[511] [111:104],\not_strict_mode.app_rd_data_reg[511] [87:80],\not_strict_mode.app_rd_data_reg[511] [63:56],\not_strict_mode.app_rd_data_reg[511] [39:32],\not_strict_mode.app_rd_data_reg[511] [15:8]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .p_33_in(p_33_in),
        .p_34_in(p_34_in),
        .p_35_out(p_35_out),
        .p_37_in(p_37_in),
        .p_38_in(p_38_in),
        .p_39_out(p_39_out),
        .p_3_in(p_3_in),
        .p_41_in(p_41_in),
        .p_42_in(p_42_in),
        .p_43_out(p_43_out),
        .p_45_in(p_45_in),
        .p_46_in(p_46_in),
        .p_47_out(p_47_out),
        .p_49_in(p_49_in),
        .p_50_in(p_50_in),
        .p_51_out(p_51_out),
        .p_53_in(p_53_in),
        .p_54_in(p_54_in),
        .p_55_out(p_55_out),
        .p_57_in(p_57_in),
        .p_58_in(p_58_in),
        .p_59_out(p_59_out),
        .p_61_in(p_61_in),
        .p_62_in(p_62_in),
        .p_63_out(p_63_out),
        .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[1]),
        .\pi_dqs_found_lanes_r1_reg[9] (\pi_dqs_found_lanes_r1_reg[9] ),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg_0),
        .\po_counter_read_val_reg[8] (B_po_counter_read_val),
        .rclk_(rclk_),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3]_0 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1]_0 ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .wr_en_13(wr_en_13),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_2 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3]_0 ),
        .\write_buffer.wr_buf_out_data_reg[497] (\write_buffer.wr_buf_out_data_reg[497] ),
        .\write_buffer.wr_buf_out_data_reg[498] (\write_buffer.wr_buf_out_data_reg[498] ),
        .\write_buffer.wr_buf_out_data_reg[499] (\write_buffer.wr_buf_out_data_reg[499] ),
        .\write_buffer.wr_buf_out_data_reg[501] (\write_buffer.wr_buf_out_data_reg[501] ),
        .\write_buffer.wr_buf_out_data_reg[502] (\write_buffer.wr_buf_out_data_reg[502] ),
        .\write_buffer.wr_buf_out_data_reg[503] (\write_buffer.wr_buf_out_data_reg[503] ));
  mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized8 \ddr_byte_lane_C.ddr_byte_lane_C 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_2),
        .CLK(CLK),
        .COUNTERREADVAL(C_pi_counter_read_val),
        .C_idelay_ce2_out(C_idelay_ce2_out),
        .C_pi_counter_load_en61_out(C_pi_counter_load_en61_out),
        .C_pi_fine_enable57_out(C_pi_fine_enable57_out),
        .C_pi_fine_inc59_out(C_pi_fine_inc59_out),
        .C_pi_rst_dqs_find55_out(C_pi_rst_dqs_find55_out),
        .C_po_coarse_enable43_out(C_po_coarse_enable43_out),
        .C_po_fine_enable41_out(C_po_fine_enable41_out),
        .C_po_fine_inc45_out(C_po_fine_inc45_out),
        .PCENABLECALIB(phy_encalib),
        .Q(\not_strict_mode.app_rd_data_reg[488] ),
        .\calib_sel_reg[1] (\calib_sel_reg[1] ),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[2] (\calib_zero_inputs_reg[2]_1 ),
        .\cmd_pipe_plus.mc_wrdata_en_reg (\cmd_pipe_plus.mc_wrdata_en_reg_0 ),
        .\ddr3_dm[5] (\ddr3_dm[5] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_12 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (\gen_rd[5].rd_data_rise_wl_r_reg[5] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .if_empty_r(if_empty_r_3),
        .ififo_rd_en_in(ififo_rd_en_in),
        .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12_0),
        .init_calib_complete_reg_rep__12_0(init_calib_complete_reg_rep__12_1),
        .init_calib_complete_reg_rep__12_1(init_calib_complete_reg_rep__12_2),
        .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13),
        .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_0),
        .mc_read_idle_r_reg(mc_read_idle_r_reg_8),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_1 ),
        .\my_empty_reg[3] ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 [0]}),
        .\my_empty_reg[7] (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_5 ),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[495] ({\not_strict_mode.app_rd_data_reg[511] [175:168],\not_strict_mode.app_rd_data_reg[511] [151:144],\not_strict_mode.app_rd_data_reg[511] [127:120],\not_strict_mode.app_rd_data_reg[511] [103:96],\not_strict_mode.app_rd_data_reg[511] [79:72],\not_strict_mode.app_rd_data_reg[511] [55:48],\not_strict_mode.app_rd_data_reg[511] [31:24],\not_strict_mode.app_rd_data_reg[511] [7:0]}),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .ofs_rdy_r_reg(ofs_rdy_r_reg_0),
        .p_65_in(p_65_in),
        .p_66_in(p_66_in),
        .p_67_out(p_67_out),
        .p_69_in(p_69_in),
        .p_70_in(p_70_in),
        .p_71_out(p_71_out),
        .p_73_in(p_73_in),
        .p_74_in(p_74_in),
        .p_75_out(p_75_out),
        .p_77_in(p_77_in),
        .p_78_in(p_78_in),
        .p_79_out(p_79_out),
        .p_7_in(p_7_in),
        .p_81_in(p_81_in),
        .p_82_in(p_82_in),
        .p_83_out(p_83_out),
        .p_85_in(p_85_in),
        .p_86_in(p_86_in),
        .p_87_out(p_87_out),
        .p_89_in(p_89_in),
        .p_90_in(p_90_in),
        .p_91_out(p_91_out),
        .p_93_in(p_93_in),
        .p_94_in(p_94_in),
        .p_95_out(p_95_out),
        .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[2]),
        .\pi_dqs_found_lanes_r1_reg[10] (\pi_dqs_found_lanes_r1_reg[10] ),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg_1),
        .\po_counter_read_val_reg[8] (C_po_counter_read_val),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3]_1 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1]_1 ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .wr_en_14(wr_en_14),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0]_1 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3]_1 ),
        .\write_buffer.wr_buf_out_data_reg[489] (\write_buffer.wr_buf_out_data_reg[489] ),
        .\write_buffer.wr_buf_out_data_reg[490] (\write_buffer.wr_buf_out_data_reg[490] ),
        .\write_buffer.wr_buf_out_data_reg[491] (\write_buffer.wr_buf_out_data_reg[491] ),
        .\write_buffer.wr_buf_out_data_reg[493] (\write_buffer.wr_buf_out_data_reg[493] ),
        .\write_buffer.wr_buf_out_data_reg[494] (\write_buffer.wr_buf_out_data_reg[494] ),
        .\write_buffer.wr_buf_out_data_reg[495] (\write_buffer.wr_buf_out_data_reg[495] ));
  FDRE #(
    .INIT(1'b0)) 
    mcGo_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_out_reg_n_0),
        .Q(mcGo_w__0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_REF #(
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0)) 
    phaser_ref_i
       (.CLKIN(freq_refclk),
        .LOCKED(rst_sync_r1_reg),
        .PWRDWN(1'b0),
        .RST(sys_rst));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHY_CONTROL #(
    .AO_TOGGLE(1),
    .AO_WRLVL_EN(4'b0000),
    .BURST_MODE("TRUE"),
    .CLK_RATIO(4),
    .CMD_OFFSET(8),
    .CO_DURATION(1),
    .DATA_CTL_A_N("TRUE"),
    .DATA_CTL_B_N("TRUE"),
    .DATA_CTL_C_N("TRUE"),
    .DATA_CTL_D_N("FALSE"),
    .DISABLE_SEQ_MATCH("TRUE"),
    .DI_DURATION(1),
    .DO_DURATION(1),
    .EVENTS_DELAY(18),
    .FOUR_WINDOW_CLOCKS(63),
    .MULTI_REGION("TRUE"),
    .PHY_COUNT_ENABLE("FALSE"),
    .RD_CMD_OFFSET_0(10),
    .RD_CMD_OFFSET_1(10),
    .RD_CMD_OFFSET_2(10),
    .RD_CMD_OFFSET_3(10),
    .RD_DURATION_0(6),
    .RD_DURATION_1(6),
    .RD_DURATION_2(6),
    .RD_DURATION_3(6),
    .SYNC_MODE("FALSE"),
    .WR_CMD_OFFSET_0(8),
    .WR_CMD_OFFSET_1(8),
    .WR_CMD_OFFSET_2(8),
    .WR_CMD_OFFSET_3(8),
    .WR_DURATION_0(7),
    .WR_DURATION_1(7),
    .WR_DURATION_2(7),
    .WR_DURATION_3(7)) 
    phy_control_i
       (.AUXOUTPUT(aux_out_),
        .INBURSTPENDING(phaser_ctl_bus[7:4]),
        .INRANKA(phaser_ctl_bus[9:8]),
        .INRANKB(phaser_ctl_bus[11:10]),
        .INRANKC(phaser_ctl_bus[13:12]),
        .INRANKD(phaser_ctl_bus[15:14]),
        .MEMREFCLK(mem_refclk),
        .OUTBURSTPENDING(phaser_ctl_bus[3:0]),
        .PCENABLECALIB(phy_encalib),
        .PHYCLK(CLK),
        .PHYCTLALMOSTFULL(_phy_ctl_a_full_p),
        .PHYCTLEMPTY(phy_control_i_n_1),
        .PHYCTLFULL(_phy_ctl_full_p__0),
        .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),
        .PHYCTLREADY(phy_control_i_n_3),
        .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}),
        .PHYCTLWRENABLE(phy_ctl_wr_i2),
        .PLLLOCK(pll_lock),
        .READCALIBENABLE(read_calib),
        .REFDLLLOCK(rst_sync_r1_reg),
        .RESET(rstdiv0_sync_r1),
        .SYNCIN(sync_pulse),
        .WRITECALIBENABLE(write_calib));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_counter_read_val[0]_i_1 
       (.I0(B_pi_counter_read_val[0]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_pi_counter_read_val[0]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_pi_counter_read_val[0]),
        .O(\pi_counter_read_val[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_counter_read_val[1]_i_1 
       (.I0(B_pi_counter_read_val[1]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_pi_counter_read_val[1]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_pi_counter_read_val[1]),
        .O(\pi_counter_read_val[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_counter_read_val[2]_i_1 
       (.I0(B_pi_counter_read_val[2]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_pi_counter_read_val[2]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_pi_counter_read_val[2]),
        .O(\pi_counter_read_val[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_counter_read_val[3]_i_1 
       (.I0(B_pi_counter_read_val[3]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_pi_counter_read_val[3]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_pi_counter_read_val[3]),
        .O(\pi_counter_read_val[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_counter_read_val[4]_i_1 
       (.I0(B_pi_counter_read_val[4]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_pi_counter_read_val[4]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_pi_counter_read_val[4]),
        .O(\pi_counter_read_val[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \pi_counter_read_val[5]_i_1 
       (.I0(B_pi_counter_read_val[5]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_pi_counter_read_val[5]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_pi_counter_read_val[5]),
        .O(\pi_counter_read_val[5]_i_1_n_0 ));
  FDRE \pi_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_counter_read_val[0]_i_1_n_0 ),
        .Q(\pi_rdval_cnt_reg[5] [0]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_counter_read_val[1]_i_1_n_0 ),
        .Q(\pi_rdval_cnt_reg[5] [1]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_counter_read_val[2]_i_1_n_0 ),
        .Q(\pi_rdval_cnt_reg[5] [2]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_counter_read_val[3]_i_1_n_0 ),
        .Q(\pi_rdval_cnt_reg[5] [3]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_counter_read_val[4]_i_1_n_0 ),
        .Q(\pi_rdval_cnt_reg[5] [4]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_counter_read_val[5]_i_1_n_0 ),
        .Q(\pi_rdval_cnt_reg[5] [5]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[0]_i_1 
       (.I0(B_po_counter_read_val[0]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[0]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[0]),
        .O(\po_counter_read_val[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[1]_i_1 
       (.I0(B_po_counter_read_val[1]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[1]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[1]),
        .O(\po_counter_read_val[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[2]_i_1 
       (.I0(B_po_counter_read_val[2]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[2]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[2]),
        .O(\po_counter_read_val[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[3]_i_1 
       (.I0(B_po_counter_read_val[3]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[3]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[3]),
        .O(\po_counter_read_val[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[4]_i_1 
       (.I0(B_po_counter_read_val[4]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[4]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[4]),
        .O(\po_counter_read_val[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[5]_i_1 
       (.I0(B_po_counter_read_val[5]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[5]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[5]),
        .O(\po_counter_read_val[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[6]_i_1 
       (.I0(B_po_counter_read_val[6]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[6]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[6]),
        .O(\po_counter_read_val[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[7]_i_1 
       (.I0(B_po_counter_read_val[7]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[7]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[7]),
        .O(\po_counter_read_val[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_counter_read_val[8]_i_1 
       (.I0(B_po_counter_read_val[8]),
        .I1(\calib_sel_reg[1]_0 [0]),
        .I2(C_po_counter_read_val[8]),
        .I3(\calib_sel_reg[1]_0 [1]),
        .I4(A_po_counter_read_val[8]),
        .O(\po_counter_read_val[8]_i_1_n_0 ));
  FDRE \po_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[0]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [0]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[1]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [1]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[2]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [2]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[3]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [3]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[4]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [4]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[5]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[6]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [6]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[7]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [7]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_counter_read_val[8]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg[8] [8]),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) 
  SRL16E \rclk_delay_reg[10]_srl11 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(\rclk_delay_reg[10]_srl11_i_1__0__0_n_0 ),
        .Q(\rclk_delay_reg[10]_srl11_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rclk_delay_reg[10]_srl11_i_1__0__0 
       (.I0(rst_primitives),
        .O(\rclk_delay_reg[10]_srl11_i_1__0__0_n_0 ));
  FDRE \rclk_delay_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rclk_delay_reg[10]_srl11_n_0 ),
        .Q(rclk_delay_11),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_out_i_1__0__0
       (.I0(rclk_delay_11),
        .I1(rst_out_reg_n_0),
        .O(rst_out_i_1__0__0_n_0));
  FDCE #(
    .INIT(1'b0)) 
    rst_out_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(rstdiv0_sync_r1_reg_rep__1),
        .D(rst_out_i_1__0__0_n_0),
        .Q(rst_out_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    rst_primitives_i_1__0__0
       (.I0(phy_control_i_n_3),
        .O(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in),
        .Q(rst_primitives),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay
   (po_ck_addr_cmd_delay_done,
    ctl_lane_cnt,
    A_po_fine_enable141_out,
    po_en_stg2_f,
    D_po_fine_enable70_out,
    A_po_fine_enable96_out,
    B_po_fine_enable18_out,
    C_po_fine_enable44_out,
    A_po_fine_enable67_out,
    B_po_fine_enable15_out,
    C_po_fine_enable41_out,
    CLK,
    dqs_po_dec_done,
    pi_fine_dly_dec_done,
    rstdiv0_sync_r1_reg_rep__24,
    Q,
    ck_po_stg2_f_en,
    dqs_po_en_stg2_f,
    \gen_byte_sel_div2.calib_in_common_reg ,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    rstdiv0_sync_r1_reg_rep__23,
    pi_fine_dly_dec_done_reg,
    dqs_po_dec_done_reg,
    rstdiv0_sync_r1_reg_rep__3);
  output po_ck_addr_cmd_delay_done;
  output [2:0]ctl_lane_cnt;
  output A_po_fine_enable141_out;
  output po_en_stg2_f;
  output D_po_fine_enable70_out;
  output A_po_fine_enable96_out;
  output B_po_fine_enable18_out;
  output C_po_fine_enable44_out;
  output A_po_fine_enable67_out;
  output B_po_fine_enable15_out;
  output C_po_fine_enable41_out;
  input CLK;
  input dqs_po_dec_done;
  input pi_fine_dly_dec_done;
  input rstdiv0_sync_r1_reg_rep__24;
  input [2:0]Q;
  input ck_po_stg2_f_en;
  input dqs_po_en_stg2_f;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input \gen_byte_sel_div2.calib_in_common_reg_1 ;
  input \gen_byte_sel_div2.calib_in_common_reg_2 ;
  input rstdiv0_sync_r1_reg_rep__23;
  input pi_fine_dly_dec_done_reg;
  input dqs_po_dec_done_reg;
  input rstdiv0_sync_r1_reg_rep__3;

  wire A_po_fine_enable141_out;
  wire A_po_fine_enable67_out;
  wire A_po_fine_enable96_out;
  wire B_po_fine_enable15_out;
  wire B_po_fine_enable18_out;
  wire CLK;
  wire C_po_fine_enable41_out;
  wire C_po_fine_enable44_out;
  wire D_po_fine_enable70_out;
  wire [2:0]Q;
  wire ck_po_stg2_f_en;
  wire [2:0]ctl_lane_cnt;
  wire ctl_lane_cnt1;
  wire \ctl_lane_cnt[0]_i_1_n_0 ;
  wire \ctl_lane_cnt[1]_i_1_n_0 ;
  wire \ctl_lane_cnt[1]_i_5_n_0 ;
  wire \ctl_lane_cnt[2]_i_1_n_0 ;
  wire \ctl_lane_cnt[2]_i_2_n_0 ;
  wire \ctl_lane_cnt[2]_i_3_n_0 ;
  wire delay_dec_done;
  wire delay_dec_done_i_1_n_0;
  wire delay_done_r3_reg_srl3_n_0;
  wire delaydec_cnt_r0;
  wire [5:1]delaydec_cnt_r0__0;
  wire delaydec_cnt_r10_in;
  wire \delaydec_cnt_r[0]_i_1_n_0 ;
  wire \delaydec_cnt_r[5]_i_1_n_0 ;
  wire [5:0]delaydec_cnt_r_reg__0;
  wire dqs_po_dec_done;
  wire dqs_po_dec_done_reg;
  wire dqs_po_en_stg2_f;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire pi_fine_dly_dec_done;
  wire pi_fine_dly_dec_done_reg;
  wire po_ck_addr_cmd_delay_done;
  wire po_cnt_dec;
  wire po_cnt_dec_i_1__0_n_0;
  wire po_cnt_dec_i_2__0_n_0;
  wire po_en_stg2_f;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire [3:0]wait_cnt_r0__0;
  wire \wait_cnt_r[3]_i_1_n_0 ;
  wire \wait_cnt_r[3]_i_2__0_n_0 ;
  wire [3:0]wait_cnt_r_reg__0;

  LUT6 #(
    .INIT(64'h0000000000006000)) 
    \ctl_lane_cnt[0]_i_1 
       (.I0(ctl_lane_cnt[0]),
        .I1(delaydec_cnt_r10_in),
        .I2(dqs_po_dec_done),
        .I3(pi_fine_dly_dec_done),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .I5(ctl_lane_cnt1),
        .O(\ctl_lane_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000DEEE)) 
    \ctl_lane_cnt[1]_i_1 
       (.I0(ctl_lane_cnt[1]),
        .I1(ctl_lane_cnt1),
        .I2(delaydec_cnt_r10_in),
        .I3(ctl_lane_cnt[0]),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .I5(pi_fine_dly_dec_done_reg),
        .O(\ctl_lane_cnt[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00040000)) 
    \ctl_lane_cnt[1]_i_2 
       (.I0(delay_dec_done),
        .I1(ctl_lane_cnt[1]),
        .I2(ctl_lane_cnt[2]),
        .I3(ctl_lane_cnt[0]),
        .I4(\ctl_lane_cnt[1]_i_5_n_0 ),
        .O(ctl_lane_cnt1));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'h00EF)) 
    \ctl_lane_cnt[1]_i_3 
       (.I0(ctl_lane_cnt[0]),
        .I1(ctl_lane_cnt[2]),
        .I2(ctl_lane_cnt[1]),
        .I3(\ctl_lane_cnt[2]_i_2_n_0 ),
        .O(delaydec_cnt_r10_in));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \ctl_lane_cnt[1]_i_5 
       (.I0(delaydec_cnt_r_reg__0[1]),
        .I1(delaydec_cnt_r_reg__0[0]),
        .I2(delaydec_cnt_r_reg__0[4]),
        .I3(delaydec_cnt_r_reg__0[5]),
        .I4(delaydec_cnt_r_reg__0[2]),
        .I5(delaydec_cnt_r_reg__0[3]),
        .O(\ctl_lane_cnt[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT5 #(
    .INIT(32'h0000B4F0)) 
    \ctl_lane_cnt[2]_i_1 
       (.I0(\ctl_lane_cnt[2]_i_2_n_0 ),
        .I1(ctl_lane_cnt[1]),
        .I2(ctl_lane_cnt[2]),
        .I3(ctl_lane_cnt[0]),
        .I4(\ctl_lane_cnt[2]_i_3_n_0 ),
        .O(\ctl_lane_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \ctl_lane_cnt[2]_i_2 
       (.I0(delaydec_cnt_r_reg__0[4]),
        .I1(delaydec_cnt_r_reg__0[2]),
        .I2(delaydec_cnt_r_reg__0[0]),
        .I3(delaydec_cnt_r_reg__0[1]),
        .I4(delaydec_cnt_r_reg__0[3]),
        .I5(delaydec_cnt_r_reg__0[5]),
        .O(\ctl_lane_cnt[2]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hEFFF)) 
    \ctl_lane_cnt[2]_i_3 
       (.I0(ctl_lane_cnt1),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(pi_fine_dly_dec_done),
        .I3(dqs_po_dec_done),
        .O(\ctl_lane_cnt[2]_i_3_n_0 ));
  FDRE \ctl_lane_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[0]_i_1_n_0 ),
        .Q(ctl_lane_cnt[0]),
        .R(1'b0));
  FDRE \ctl_lane_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[1]_i_1_n_0 ),
        .Q(ctl_lane_cnt[1]),
        .R(1'b0));
  FDRE \ctl_lane_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[2]_i_1_n_0 ),
        .Q(ctl_lane_cnt[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAAABAA)) 
    delay_dec_done_i_1
       (.I0(delay_dec_done),
        .I1(ctl_lane_cnt[0]),
        .I2(ctl_lane_cnt[2]),
        .I3(ctl_lane_cnt[1]),
        .I4(\ctl_lane_cnt[2]_i_2_n_0 ),
        .I5(dqs_po_dec_done_reg),
        .O(delay_dec_done_i_1_n_0));
  FDRE delay_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(delay_dec_done_i_1_n_0),
        .Q(delay_dec_done),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 " *) 
  SRL16E delay_done_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(delay_dec_done),
        .Q(delay_done_r3_reg_srl3_n_0));
  FDRE delay_done_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(delay_done_r3_reg_srl3_n_0),
        .Q(po_ck_addr_cmd_delay_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \delaydec_cnt_r[0]_i_1 
       (.I0(delaydec_cnt_r_reg__0[0]),
        .O(\delaydec_cnt_r[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \delaydec_cnt_r[1]_i_1 
       (.I0(delaydec_cnt_r_reg__0[1]),
        .I1(delaydec_cnt_r_reg__0[0]),
        .O(delaydec_cnt_r0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \delaydec_cnt_r[2]_i_1 
       (.I0(delaydec_cnt_r_reg__0[2]),
        .I1(delaydec_cnt_r_reg__0[0]),
        .I2(delaydec_cnt_r_reg__0[1]),
        .O(delaydec_cnt_r0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \delaydec_cnt_r[3]_i_1 
       (.I0(delaydec_cnt_r_reg__0[3]),
        .I1(delaydec_cnt_r_reg__0[1]),
        .I2(delaydec_cnt_r_reg__0[0]),
        .I3(delaydec_cnt_r_reg__0[2]),
        .O(delaydec_cnt_r0__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \delaydec_cnt_r[4]_i_1 
       (.I0(delaydec_cnt_r_reg__0[4]),
        .I1(delaydec_cnt_r_reg__0[2]),
        .I2(delaydec_cnt_r_reg__0[0]),
        .I3(delaydec_cnt_r_reg__0[1]),
        .I4(delaydec_cnt_r_reg__0[3]),
        .O(delaydec_cnt_r0__0[4]));
  LUT4 #(
    .INIT(16'hEFFF)) 
    \delaydec_cnt_r[5]_i_1 
       (.I0(delaydec_cnt_r10_in),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(pi_fine_dly_dec_done),
        .I3(dqs_po_dec_done),
        .O(\delaydec_cnt_r[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \delaydec_cnt_r[5]_i_2 
       (.I0(\ctl_lane_cnt[2]_i_2_n_0 ),
        .I1(po_cnt_dec),
        .O(delaydec_cnt_r0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \delaydec_cnt_r[5]_i_3 
       (.I0(delaydec_cnt_r_reg__0[5]),
        .I1(delaydec_cnt_r_reg__0[3]),
        .I2(delaydec_cnt_r_reg__0[1]),
        .I3(delaydec_cnt_r_reg__0[0]),
        .I4(delaydec_cnt_r_reg__0[2]),
        .I5(delaydec_cnt_r_reg__0[4]),
        .O(delaydec_cnt_r0__0[5]));
  FDSE \delaydec_cnt_r_reg[0] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[0]_i_1_n_0 ),
        .Q(delaydec_cnt_r_reg__0[0]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDRE \delaydec_cnt_r_reg[1] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[1]),
        .Q(delaydec_cnt_r_reg__0[1]),
        .R(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDSE \delaydec_cnt_r_reg[2] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[2]),
        .Q(delaydec_cnt_r_reg__0[2]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDSE \delaydec_cnt_r_reg[3] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[3]),
        .Q(delaydec_cnt_r_reg__0[3]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDSE \delaydec_cnt_r_reg[4] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[4]),
        .Q(delaydec_cnt_r_reg__0[4]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDRE \delaydec_cnt_r_reg[5] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[5]),
        .Q(delaydec_cnt_r_reg__0[5]),
        .R(\delaydec_cnt_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2
       (.I0(Q[1]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_po_fine_enable141_out));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2__0
       (.I0(Q[0]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(D_po_fine_enable70_out));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2__1
       (.I0(Q[0]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_po_fine_enable96_out));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2__2
       (.I0(Q[0]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .O(B_po_fine_enable18_out));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2__3
       (.I0(Q[0]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .O(C_po_fine_enable44_out));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2__4
       (.I0(Q[2]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_po_fine_enable67_out));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2__5
       (.I0(Q[2]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .O(B_po_fine_enable15_out));
  LUT5 #(
    .INIT(32'h55540000)) 
    phaser_out_i_2__6
       (.I0(Q[2]),
        .I1(po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .I3(dqs_po_en_stg2_f),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .O(C_po_fine_enable41_out));
  LUT4 #(
    .INIT(16'h8000)) 
    po_cnt_dec_i_1__0
       (.I0(po_cnt_dec_i_2__0_n_0),
        .I1(\ctl_lane_cnt[2]_i_2_n_0 ),
        .I2(dqs_po_dec_done),
        .I3(pi_fine_dly_dec_done),
        .O(po_cnt_dec_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    po_cnt_dec_i_2__0
       (.I0(wait_cnt_r_reg__0[0]),
        .I1(wait_cnt_r_reg__0[3]),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .I3(wait_cnt_r_reg__0[1]),
        .I4(wait_cnt_r_reg__0[2]),
        .O(po_cnt_dec_i_2__0_n_0));
  FDRE po_cnt_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_cnt_dec_i_1__0_n_0),
        .Q(po_cnt_dec),
        .R(1'b0));
  FDRE po_en_stg2_f_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_cnt_dec),
        .Q(po_en_stg2_f),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt_r[0]_i_1 
       (.I0(wait_cnt_r_reg__0[0]),
        .O(wait_cnt_r0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt_r[1]_i_1 
       (.I0(wait_cnt_r_reg__0[1]),
        .I1(wait_cnt_r_reg__0[0]),
        .O(wait_cnt_r0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt_r[2]_i_1 
       (.I0(wait_cnt_r_reg__0[2]),
        .I1(wait_cnt_r_reg__0[0]),
        .I2(wait_cnt_r_reg__0[1]),
        .O(wait_cnt_r0__0[2]));
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt_r[3]_i_1 
       (.I0(po_cnt_dec),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .O(\wait_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFE000000000000)) 
    \wait_cnt_r[3]_i_2__0 
       (.I0(wait_cnt_r_reg__0[3]),
        .I1(wait_cnt_r_reg__0[1]),
        .I2(wait_cnt_r_reg__0[0]),
        .I3(wait_cnt_r_reg__0[2]),
        .I4(dqs_po_dec_done),
        .I5(pi_fine_dly_dec_done),
        .O(\wait_cnt_r[3]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt_r[3]_i_3 
       (.I0(wait_cnt_r_reg__0[3]),
        .I1(wait_cnt_r_reg__0[1]),
        .I2(wait_cnt_r_reg__0[0]),
        .I3(wait_cnt_r_reg__0[2]),
        .O(wait_cnt_r0__0[3]));
  FDRE \wait_cnt_r_reg[0] 
       (.C(CLK),
        .CE(\wait_cnt_r[3]_i_2__0_n_0 ),
        .D(wait_cnt_r0__0[0]),
        .Q(wait_cnt_r_reg__0[0]),
        .R(\wait_cnt_r[3]_i_1_n_0 ));
  FDRE \wait_cnt_r_reg[1] 
       (.C(CLK),
        .CE(\wait_cnt_r[3]_i_2__0_n_0 ),
        .D(wait_cnt_r0__0[1]),
        .Q(wait_cnt_r_reg__0[1]),
        .R(\wait_cnt_r[3]_i_1_n_0 ));
  FDRE \wait_cnt_r_reg[2] 
       (.C(CLK),
        .CE(\wait_cnt_r[3]_i_2__0_n_0 ),
        .D(wait_cnt_r0__0[2]),
        .Q(wait_cnt_r_reg__0[2]),
        .R(\wait_cnt_r[3]_i_1_n_0 ));
  FDSE \wait_cnt_r_reg[3] 
       (.C(CLK),
        .CE(\wait_cnt_r[3]_i_2__0_n_0 ),
        .D(wait_cnt_r0__0[3]),
        .Q(wait_cnt_r_reg__0[3]),
        .S(\wait_cnt_r[3]_i_1_n_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_dqs_found_cal_hr" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_dqs_found_cal_hr
   (\calib_data_offset_0_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    \calib_zero_inputs_reg[2] ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    \calib_data_offset_0_reg[5]_0 ,
    Q,
    \calib_data_offset_0_reg[4] ,
    \calib_data_offset_0_reg[2] ,
    \calib_data_offset_0_reg[1] ,
    \calib_data_offset_0_reg[0] ,
    \calib_data_offset_1_reg[5] ,
    \calib_data_offset_1_reg[3] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ,
    \calib_data_offset_1_reg[4] ,
    \calib_data_offset_1_reg[2] ,
    \calib_data_offset_1_reg[1] ,
    \calib_data_offset_1_reg[0] ,
    \calib_data_offset_2_reg[5] ,
    \calib_data_offset_2_reg[3] ,
    \calib_data_offset_2_reg[4] ,
    \calib_data_offset_2_reg[2] ,
    \calib_data_offset_2_reg[1] ,
    \calib_data_offset_2_reg[0] ,
    ofifo_rst0,
    A_po_fine_inc145_out,
    A_pi_rst_dqs_find155_out,
    B_po_fine_inc30_out,
    C_po_fine_inc69_out,
    D_po_fine_inc108_out,
    D_po_fine_inc74_out,
    D_pi_rst_dqs_find84_out,
    A_po_fine_inc100_out,
    A_pi_rst_dqs_find110_out,
    B_po_fine_inc22_out,
    B_pi_rst_dqs_find32_out,
    C_po_fine_inc48_out,
    C_pi_rst_dqs_find58_out,
    A_po_fine_inc71_out,
    A_pi_rst_dqs_find81_out,
    B_po_fine_inc19_out,
    B_pi_rst_dqs_find29_out,
    C_po_fine_inc45_out,
    C_pi_rst_dqs_find55_out,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[1] ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[0] ,
    \gen_byte_sel_div2.calib_in_common_reg ,
    fine_adjust_done,
    rd_data_offset_cal_done,
    SR,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    D,
    \calib_zero_inputs_reg[2]_0 ,
    pi_dqs_found_done,
    pi_dqs_found_rank_done,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ,
    ck_po_stg2_f_en,
    dqs_found_prech_req,
    CLK,
    prech_done,
    detect_pi_found_dqs,
    rstdiv0_sync_r1_reg_rep__24,
    sent_col,
    col_rd_wr,
    pi_dqs_found_done_r1,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    \calib_sel_reg[1] ,
    \calib_zero_inputs_reg[2]_1 ,
    A_rst_primitives,
    dqs_po_stg2_f_incdec,
    po_ck_addr_cmd_delay_done,
    ctl_lane_cnt,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_2 ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ,
    pi_calib_done_r1_reg,
    pi_fine_dly_dec_done_reg,
    rstdiv0_sync_r1_reg_rep__24_0,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[3] ,
    dqs_po_dec_done,
    pi_fine_dly_dec_done,
    pi_calib_done,
    pi_dqs_found_lanes,
    rstdiv0_sync_r1,
    rstdiv0_sync_r1_reg_rep__12,
    pi_dqs_found_start_reg,
    rstdiv0_sync_r1_reg_rep__23,
    rstdiv0_sync_r1_reg_rep__11,
    rstdiv0_sync_r1_reg_rep__18,
    rstdiv0_sync_r1_reg_rep__13);
  output \calib_data_offset_0_reg[5] ;
  output \cmd_pipe_plus.mc_data_offset_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_reg[5] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  output \calib_zero_inputs_reg[2] ;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[2] ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  output \cmd_pipe_plus.mc_data_offset_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  output \calib_data_offset_0_reg[5]_0 ;
  output [0:0]Q;
  output \calib_data_offset_0_reg[4] ;
  output \calib_data_offset_0_reg[2] ;
  output \calib_data_offset_0_reg[1] ;
  output \calib_data_offset_0_reg[0] ;
  output \calib_data_offset_1_reg[5] ;
  output [0:0]\calib_data_offset_1_reg[3] ;
  output [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ;
  output \calib_data_offset_1_reg[4] ;
  output \calib_data_offset_1_reg[2] ;
  output \calib_data_offset_1_reg[1] ;
  output \calib_data_offset_1_reg[0] ;
  output \calib_data_offset_2_reg[5] ;
  output [0:0]\calib_data_offset_2_reg[3] ;
  output \calib_data_offset_2_reg[4] ;
  output \calib_data_offset_2_reg[2] ;
  output \calib_data_offset_2_reg[1] ;
  output \calib_data_offset_2_reg[0] ;
  output ofifo_rst0;
  output A_po_fine_inc145_out;
  output A_pi_rst_dqs_find155_out;
  output B_po_fine_inc30_out;
  output C_po_fine_inc69_out;
  output D_po_fine_inc108_out;
  output D_po_fine_inc74_out;
  output D_pi_rst_dqs_find84_out;
  output A_po_fine_inc100_out;
  output A_pi_rst_dqs_find110_out;
  output B_po_fine_inc22_out;
  output B_pi_rst_dqs_find32_out;
  output C_po_fine_inc48_out;
  output C_pi_rst_dqs_find58_out;
  output A_po_fine_inc71_out;
  output A_pi_rst_dqs_find81_out;
  output B_po_fine_inc19_out;
  output B_pi_rst_dqs_find29_out;
  output C_po_fine_inc45_out;
  output C_pi_rst_dqs_find55_out;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  output \gen_byte_sel_div2.calib_in_common_reg ;
  output fine_adjust_done;
  output rd_data_offset_cal_done;
  output [0:0]SR;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  output [1:0]D;
  output \calib_zero_inputs_reg[2]_0 ;
  output pi_dqs_found_done;
  output pi_dqs_found_rank_done;
  output [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;
  output [0:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ;
  output ck_po_stg2_f_en;
  output dqs_found_prech_req;
  input CLK;
  input prech_done;
  input detect_pi_found_dqs;
  input rstdiv0_sync_r1_reg_rep__24;
  input sent_col;
  input col_rd_wr;
  input pi_dqs_found_done_r1;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input [1:0]\calib_sel_reg[1] ;
  input [2:0]\calib_zero_inputs_reg[2]_1 ;
  input A_rst_primitives;
  input dqs_po_stg2_f_incdec;
  input po_ck_addr_cmd_delay_done;
  input [2:0]ctl_lane_cnt;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[2]_2 ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ;
  input pi_calib_done_r1_reg;
  input pi_fine_dly_dec_done_reg;
  input rstdiv0_sync_r1_reg_rep__24_0;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  input [3:0]\gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  input dqs_po_dec_done;
  input pi_fine_dly_dec_done;
  input pi_calib_done;
  input [7:0]pi_dqs_found_lanes;
  input rstdiv0_sync_r1;
  input [0:0]rstdiv0_sync_r1_reg_rep__12;
  input pi_dqs_found_start_reg;
  input rstdiv0_sync_r1_reg_rep__23;
  input [0:0]rstdiv0_sync_r1_reg_rep__11;
  input rstdiv0_sync_r1_reg_rep__18;
  input [0:0]rstdiv0_sync_r1_reg_rep__13;

  wire A_pi_rst_dqs_find110_out;
  wire A_pi_rst_dqs_find155_out;
  wire A_pi_rst_dqs_find81_out;
  wire A_po_fine_inc100_out;
  wire A_po_fine_inc145_out;
  wire A_po_fine_inc71_out;
  wire A_rst_primitives;
  wire B_pi_rst_dqs_find29_out;
  wire B_pi_rst_dqs_find32_out;
  wire B_po_fine_inc19_out;
  wire B_po_fine_inc22_out;
  wire B_po_fine_inc30_out;
  wire CLK;
  wire C_pi_rst_dqs_find55_out;
  wire C_pi_rst_dqs_find58_out;
  wire C_po_fine_inc45_out;
  wire C_po_fine_inc48_out;
  wire C_po_fine_inc69_out;
  wire [1:0]D;
  wire D_pi_rst_dqs_find84_out;
  wire D_po_fine_inc108_out;
  wire D_po_fine_inc74_out;
  wire \FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_10_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_11_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_12_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ;
  wire \FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r_reg[3]_i_1_n_0 ;
  wire [0:0]Q;
  wire [0:0]SR;
  wire \calib_data_offset_0_reg[0] ;
  wire \calib_data_offset_0_reg[1] ;
  wire \calib_data_offset_0_reg[2] ;
  wire \calib_data_offset_0_reg[4] ;
  wire \calib_data_offset_0_reg[5] ;
  wire \calib_data_offset_0_reg[5]_0 ;
  wire \calib_data_offset_1_reg[0] ;
  wire \calib_data_offset_1_reg[1] ;
  wire \calib_data_offset_1_reg[2] ;
  wire [0:0]\calib_data_offset_1_reg[3] ;
  wire \calib_data_offset_1_reg[4] ;
  wire \calib_data_offset_1_reg[5] ;
  wire \calib_data_offset_2_reg[0] ;
  wire \calib_data_offset_2_reg[1] ;
  wire \calib_data_offset_2_reg[2] ;
  wire [0:0]\calib_data_offset_2_reg[3] ;
  wire \calib_data_offset_2_reg[4] ;
  wire \calib_data_offset_2_reg[5] ;
  wire [1:0]\calib_sel_reg[1] ;
  wire \calib_zero_inputs_reg[2] ;
  wire \calib_zero_inputs_reg[2]_0 ;
  wire [2:0]\calib_zero_inputs_reg[2]_1 ;
  wire ck_po_stg2_f_en;
  wire ck_po_stg2_f_en_i_1_n_0;
  wire ck_po_stg2_f_indec;
  wire ck_po_stg2_f_indec_i_1_n_0;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire col_rd_wr;
  wire [2:0]ctl_lane_cnt;
  wire \ctl_lane_cnt[0]_i_1__0_n_0 ;
  wire \ctl_lane_cnt[1]_i_1__0_n_0 ;
  wire \ctl_lane_cnt[2]_i_1__0_n_0 ;
  wire \ctl_lane_cnt[2]_i_2__0_n_0 ;
  wire [5:0]dec_cnt;
  wire \dec_cnt[0]_i_2_n_0 ;
  wire \dec_cnt[1]_i_2_n_0 ;
  wire \dec_cnt[2]_i_2_n_0 ;
  wire \dec_cnt[2]_i_4_n_0 ;
  wire \dec_cnt[2]_i_5_n_0 ;
  wire \dec_cnt[2]_i_6_n_0 ;
  wire \dec_cnt[2]_i_7_n_0 ;
  wire \dec_cnt[2]_i_8_n_0 ;
  wire \dec_cnt[3]_i_2_n_0 ;
  wire \dec_cnt[3]_i_3_n_0 ;
  wire \dec_cnt[4]_i_10_n_0 ;
  wire \dec_cnt[4]_i_11_n_0 ;
  wire \dec_cnt[4]_i_2_n_0 ;
  wire \dec_cnt[4]_i_3_n_0 ;
  wire \dec_cnt[4]_i_5_n_0 ;
  wire \dec_cnt[4]_i_6_n_0 ;
  wire \dec_cnt[4]_i_7_n_0 ;
  wire \dec_cnt[4]_i_8_n_0 ;
  wire \dec_cnt[4]_i_9_n_0 ;
  wire \dec_cnt[5]_i_10_n_0 ;
  wire \dec_cnt[5]_i_11_n_0 ;
  wire \dec_cnt[5]_i_12_n_0 ;
  wire \dec_cnt[5]_i_1_n_0 ;
  wire \dec_cnt[5]_i_3_n_0 ;
  wire \dec_cnt[5]_i_4_n_0 ;
  wire \dec_cnt[5]_i_5_n_0 ;
  wire \dec_cnt[5]_i_6_n_0 ;
  wire \dec_cnt[5]_i_7_n_0 ;
  wire \dec_cnt[5]_i_9_n_0 ;
  wire \dec_cnt_reg[2]_i_3_n_0 ;
  wire \dec_cnt_reg[2]_i_3_n_1 ;
  wire \dec_cnt_reg[2]_i_3_n_2 ;
  wire \dec_cnt_reg[2]_i_3_n_3 ;
  wire \dec_cnt_reg[2]_i_3_n_4 ;
  wire \dec_cnt_reg[2]_i_3_n_5 ;
  wire \dec_cnt_reg[2]_i_3_n_6 ;
  wire \dec_cnt_reg[2]_i_3_n_7 ;
  wire \dec_cnt_reg[4]_i_4_n_3 ;
  wire \dec_cnt_reg[4]_i_4_n_6 ;
  wire \dec_cnt_reg[4]_i_4_n_7 ;
  wire \dec_cnt_reg_n_0_[0] ;
  wire \dec_cnt_reg_n_0_[1] ;
  wire \dec_cnt_reg_n_0_[2] ;
  wire \dec_cnt_reg_n_0_[3] ;
  wire \dec_cnt_reg_n_0_[4] ;
  wire \dec_cnt_reg_n_0_[5] ;
  wire detect_pi_found_dqs;
  wire detect_rd_cnt0;
  wire [3:2]detect_rd_cnt0__0;
  wire \detect_rd_cnt[0]_i_1_n_0 ;
  wire \detect_rd_cnt[1]_i_1_n_0 ;
  wire \detect_rd_cnt[3]_i_1_n_0 ;
  wire [3:0]detect_rd_cnt_reg__0;
  wire dqs_found_done_r0;
  wire dqs_found_done_r_i_2_n_0;
  wire dqs_found_done_r_i_3_n_0;
  wire dqs_found_done_r_i_4_n_0;
  wire dqs_found_prech_req;
  wire dqs_found_prech_req_i_1_n_0;
  wire dqs_found_prech_req_i_2_n_0;
  wire dqs_found_prech_req_i_3_n_0;
  wire dqs_found_prech_req_i_6_n_0;
  wire dqs_found_prech_req_i_7_n_0;
  wire dqs_found_prech_req_i_8_n_0;
  wire dqs_found_start_r;
  wire dqs_po_dec_done;
  wire dqs_po_stg2_f_incdec;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_0 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_1 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_2 ;
  wire final_dec_done_i_1_n_0;
  wire final_dec_done_reg_n_0;
  (* RTL_KEEP = "yes" *) wire [3:0]fine_adj_state_r;
  wire fine_adj_state_r1;
  wire fine_adj_state_r112_out;
  wire fine_adj_state_r114_out;
  wire fine_adj_state_r139_out;
  wire fine_adj_state_r146_out;
  wire fine_adj_state_r149_out;
  wire fine_adj_state_r187_out;
  wire fine_adj_state_r18_out;
  wire fine_adj_state_r19_out;
  wire fine_adj_state_r3;
  wire fine_adjust_done;
  wire fine_adjust_done_r_i_1_n_0;
  wire fine_adjust_i_1_n_0;
  wire [2:0]fine_adjust_lane_cnt;
  wire fine_adjust_reg_n_0;
  wire first_fail_detect;
  wire first_fail_detect_i_1_n_0;
  wire first_fail_detect_i_2_n_0;
  wire first_fail_detect_reg_n_0;
  wire \first_fail_taps[0]_i_1_n_0 ;
  wire \first_fail_taps[1]_i_1_n_0 ;
  wire \first_fail_taps[2]_i_1_n_0 ;
  wire \first_fail_taps[3]_i_1_n_0 ;
  wire \first_fail_taps[4]_i_1_n_0 ;
  wire \first_fail_taps[5]_i_10_n_0 ;
  wire \first_fail_taps[5]_i_11_n_0 ;
  wire \first_fail_taps[5]_i_2_n_0 ;
  wire \first_fail_taps[5]_i_3_n_0 ;
  wire \first_fail_taps[5]_i_4_n_0 ;
  wire \first_fail_taps[5]_i_5_n_0 ;
  wire \first_fail_taps[5]_i_7_n_0 ;
  wire \first_fail_taps[5]_i_8_n_0 ;
  wire \first_fail_taps_reg_n_0_[0] ;
  wire \first_fail_taps_reg_n_0_[1] ;
  wire \first_fail_taps_reg_n_0_[2] ;
  wire \first_fail_taps_reg_n_0_[3] ;
  wire \first_fail_taps_reg_n_0_[4] ;
  wire \first_fail_taps_reg_n_0_[5] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  wire [3:0]\gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2]_2 ;
  wire \inc_cnt[3]_i_1_n_0 ;
  wire \inc_cnt[5]_i_1_n_0 ;
  wire \inc_cnt_reg_n_0_[0] ;
  wire \inc_cnt_reg_n_0_[1] ;
  wire \inc_cnt_reg_n_0_[2] ;
  wire \inc_cnt_reg_n_0_[3] ;
  wire \inc_cnt_reg_n_0_[4] ;
  wire \inc_cnt_reg_n_0_[5] ;
  wire [5:2]init_dec_cnt0;
  wire \init_dec_cnt[0]_i_1_n_0 ;
  wire \init_dec_cnt[1]_i_1_n_0 ;
  wire \init_dec_cnt[5]_i_1_n_0 ;
  wire [5:0]init_dec_cnt_reg__0;
  wire init_dec_done_i_1_n_0;
  wire init_dec_done_i_2_n_0;
  wire init_dec_done_i_3_n_0;
  wire init_dec_done_reg_n_0;
  wire init_dqsfound_done_r;
  wire init_dqsfound_done_r1_reg_n_0;
  wire init_dqsfound_done_r4_reg_srl2_n_0;
  wire init_dqsfound_done_r5;
  wire init_dqsfound_done_r_i_1_n_0;
  wire init_dqsfound_done_r_i_3_n_0;
  wire ofifo_rst0;
  wire [5:0]p_0_in;
  wire p_0_in24_in;
  wire p_0_in29_in;
  wire [5:0]p_0_in__0;
  wire [5:0]p_0_in__0__0;
  wire [5:2]p_1_in;
  wire p_1_in60_in;
  wire p_1_in65_in;
  wire [5:2]p_1_in__0;
  wire [5:2]p_1_in__1;
  wire p_24_out;
  wire p_2_in81_in;
  wire p_2_in82_in;
  wire [2:0]p_8_out;
  wire pi_calib_done;
  wire pi_calib_done_r1_reg;
  wire [2:0]pi_dqs_found_all_bank;
  wire [2:0]pi_dqs_found_all_bank_r;
  wire [2:0]pi_dqs_found_any_bank;
  wire \pi_dqs_found_any_bank[0]_i_1_n_0 ;
  wire \pi_dqs_found_any_bank[2]_i_1_n_0 ;
  wire \pi_dqs_found_any_bank_r_reg_n_0_[0] ;
  wire pi_dqs_found_done;
  wire pi_dqs_found_done_r1;
  wire [7:0]pi_dqs_found_lanes;
  wire [10:0]pi_dqs_found_lanes_r1;
  wire [10:0]pi_dqs_found_lanes_r2;
  wire [10:0]pi_dqs_found_lanes_r3;
  wire pi_dqs_found_rank_done;
  wire pi_dqs_found_start_reg;
  wire pi_fine_dly_dec_done;
  wire pi_fine_dly_dec_done_reg;
  wire [2:0]pi_rst_stg1_cal;
  wire \pi_rst_stg1_cal[0]_i_1_n_0 ;
  wire \pi_rst_stg1_cal[1]_i_1_n_0 ;
  wire \pi_rst_stg1_cal[2]_i_1_n_0 ;
  wire pi_rst_stg1_cal_r1_reg0;
  wire pi_rst_stg1_cal_r1_reg019_out;
  wire pi_rst_stg1_cal_r1_reg022_out;
  wire \pi_rst_stg1_cal_r1_reg_n_0_[0] ;
  wire \pi_rst_stg1_cal_r[0]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r[0]_i_2_n_0 ;
  wire \pi_rst_stg1_cal_r[1]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r[1]_i_2_n_0 ;
  wire \pi_rst_stg1_cal_r[2]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r[2]_i_2_n_0 ;
  wire \pi_rst_stg1_cal_r_reg_n_0_[0] ;
  wire po_ck_addr_cmd_delay_done;
  wire prech_done;
  wire rank_done_r0;
  wire rank_done_r1;
  wire rank_done_r_i_1_n_0;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][1] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][2] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][3] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][4] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][5] ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][10] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][11] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][7] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][8] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][9] ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][13] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][14] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][15] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][16] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][17] ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ;
  wire \rd_byte_data_offset[0][11]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][11]_i_2_n_0 ;
  wire \rd_byte_data_offset[0][11]_i_4_n_0 ;
  wire \rd_byte_data_offset[0][13]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][17]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][17]_i_2_n_0 ;
  wire \rd_byte_data_offset[0][17]_i_4_n_0 ;
  wire \rd_byte_data_offset[0][1]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_2_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_4_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_6_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_7_n_0 ;
  wire \rd_byte_data_offset[0][7]_i_1_n_0 ;
  wire \rd_byte_data_offset_reg_n_0_[0][0] ;
  wire \rd_byte_data_offset_reg_n_0_[0][12] ;
  wire \rd_byte_data_offset_reg_n_0_[0][13] ;
  wire \rd_byte_data_offset_reg_n_0_[0][14] ;
  wire \rd_byte_data_offset_reg_n_0_[0][16] ;
  wire \rd_byte_data_offset_reg_n_0_[0][17] ;
  wire \rd_byte_data_offset_reg_n_0_[0][1] ;
  wire \rd_byte_data_offset_reg_n_0_[0][2] ;
  wire \rd_byte_data_offset_reg_n_0_[0][4] ;
  wire \rd_byte_data_offset_reg_n_0_[0][5] ;
  wire rd_data_offset_cal_done;
  wire [5:0]rd_data_offset_ranks_0;
  wire [5:0]rd_data_offset_ranks_1;
  wire [5:0]rd_data_offset_ranks_2;
  wire \rnk_cnt_r[0]_i_1_n_0 ;
  wire \rnk_cnt_r[1]_i_1_n_0 ;
  wire \rnk_cnt_r_reg_n_0_[0] ;
  wire \rnk_cnt_r_reg_n_0_[1] ;
  wire rst_dqs_find_i_1_n_0;
  wire rst_dqs_find_i_2_n_0;
  wire rst_dqs_find_i_3_n_0;
  wire rst_dqs_find_i_4_n_0;
  wire rst_dqs_find_i_5_n_0;
  wire rst_dqs_find_i_6_n_0;
  wire rst_dqs_find_i_7_n_0;
  wire rst_dqs_find_i_8_n_0;
  wire rst_dqs_find_r1;
  wire rst_dqs_find_r2;
  wire rst_dqs_find_reg_n_0;
  wire rstdiv0_sync_r1;
  wire [0:0]rstdiv0_sync_r1_reg_rep__11;
  wire [0:0]rstdiv0_sync_r1_reg_rep__12;
  wire [0:0]rstdiv0_sync_r1_reg_rep__13;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__24_0;
  wire sent_col;
  wire \stable_pass_cnt[5]_i_1_n_0 ;
  wire \stable_pass_cnt[5]_i_3_n_0 ;
  wire [5:0]stable_pass_cnt_reg__0;
  wire [3:1]\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hF730FFFFF7300000)) 
    \FSM_sequential_fine_adj_state_r[0]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(fine_adj_state_r[1]),
        .I5(\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fine_adj_state_r[0]_i_2 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(fine_adjust_lane_cnt[2]),
        .I2(fine_adjust_lane_cnt[0]),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA2FFFFFFFF)) 
    \FSM_sequential_fine_adj_state_r[0]_i_4 
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adjust_lane_cnt[1]),
        .I2(fine_adjust_lane_cnt[2]),
        .I3(fine_adjust_lane_cnt[0]),
        .I4(fine_adj_state_r1),
        .I5(fine_adj_state_r[3]),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hCCCC7477)) 
    \FSM_sequential_fine_adj_state_r[0]_i_5 
       (.I0(fine_adj_state_r187_out),
        .I1(fine_adj_state_r[3]),
        .I2(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I3(final_dec_done_reg_n_0),
        .I4(fine_adj_state_r[2]),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFAFF0AFF030F030)) 
    \FSM_sequential_fine_adj_state_r[1]_i_2 
       (.I0(fine_adj_state_r187_out),
        .I1(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I2(fine_adj_state_r[0]),
        .I3(fine_adj_state_r[2]),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ),
        .I5(fine_adj_state_r[3]),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000D0D3D0D)) 
    \FSM_sequential_fine_adj_state_r[1]_i_3 
       (.I0(dqs_found_done_r_i_4_n_0),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[3]),
        .I3(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ),
        .I5(fine_adj_state_r[0]),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \FSM_sequential_fine_adj_state_r[1]_i_4 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I1(init_dec_done_i_2_n_0),
        .I2(fine_adjust_lane_cnt[0]),
        .I3(fine_adjust_lane_cnt[2]),
        .I4(fine_adjust_lane_cnt[1]),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h003333FFCCBBFC00)) 
    \FSM_sequential_fine_adj_state_r[2]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ),
        .I1(fine_adj_state_r[1]),
        .I2(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I3(fine_adj_state_r[0]),
        .I4(fine_adj_state_r[3]),
        .I5(fine_adj_state_r[2]),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAFFFF2AAA0000)) 
    \FSM_sequential_fine_adj_state_r[2]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(pi_dqs_found_all_bank[2]),
        .I4(detect_pi_found_dqs),
        .I5(fine_adj_state_r18_out),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000B08000008080)) 
    \FSM_sequential_fine_adj_state_r[2]_i_3 
       (.I0(fine_adj_state_r112_out),
        .I1(fine_adj_state_r114_out),
        .I2(\dec_cnt[5]_i_9_n_0 ),
        .I3(fine_adj_state_r19_out),
        .I4(fine_adj_state_r146_out),
        .I5(fine_adj_state_r139_out),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008660)) 
    \FSM_sequential_fine_adj_state_r[2]_i_4 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[5] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[1] ),
        .I5(\inc_cnt_reg_n_0_[0] ),
        .O(fine_adj_state_r18_out));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    \FSM_sequential_fine_adj_state_r[2]_i_5 
       (.I0(\first_fail_taps[5]_i_8_n_0 ),
        .I1(\first_fail_taps[5]_i_10_n_0 ),
        .I2(first_fail_detect_reg_n_0),
        .O(fine_adj_state_r114_out));
  LUT6 #(
    .INIT(64'h00000000FF7F0000)) 
    \FSM_sequential_fine_adj_state_r[2]_i_6 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\dec_cnt[5]_i_12_n_0 ),
        .I4(\first_fail_taps[5]_i_8_n_0 ),
        .I5(\first_fail_taps[5]_i_10_n_0 ),
        .O(fine_adj_state_r139_out));
  LUT6 #(
    .INIT(64'h1001001000000000)) 
    \FSM_sequential_fine_adj_state_r[3]_i_10 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFB8FFFFFFBBFF)) 
    \FSM_sequential_fine_adj_state_r[3]_i_11 
       (.I0(fine_adj_state_r112_out),
        .I1(fine_adj_state_r114_out),
        .I2(fine_adj_state_r19_out),
        .I3(\dec_cnt[5]_i_9_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_12_n_0 ),
        .I5(fine_adj_state_r139_out),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_sequential_fine_adj_state_r[3]_i_12 
       (.I0(first_fail_detect_i_2_n_0),
        .I1(first_fail_detect_reg_n_0),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBB888888B888)) 
    \FSM_sequential_fine_adj_state_r[3]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .I1(fine_adj_state_r[1]),
        .I2(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I3(fine_adj_state_r[0]),
        .I4(fine_adj_state_r[2]),
        .I5(fine_adj_state_r[3]),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFBFFF8)) 
    \FSM_sequential_fine_adj_state_r[3]_i_3 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[3]),
        .I4(init_dqsfound_done_r5),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCFFFFAF0CFFFFAFF)) 
    \FSM_sequential_fine_adj_state_r[3]_i_4 
       (.I0(detect_pi_found_dqs),
        .I1(prech_done),
        .I2(fine_adj_state_r[0]),
        .I3(fine_adj_state_r[3]),
        .I4(fine_adj_state_r[2]),
        .I5(dqs_found_done_r_i_4_n_0),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h0DC00CC0)) 
    \FSM_sequential_fine_adj_state_r[3]_i_5 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[3]),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_fine_adj_state_r[3]_i_6 
       (.I0(init_dec_cnt_reg__0[4]),
        .I1(init_dec_cnt_reg__0[3]),
        .I2(init_dec_cnt_reg__0[2]),
        .I3(init_dec_cnt_reg__0[0]),
        .I4(init_dec_cnt_reg__0[1]),
        .I5(init_dec_cnt_reg__0[5]),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \FSM_sequential_fine_adj_state_r[3]_i_7 
       (.I0(rst_dqs_find_r2),
        .I1(pi_dqs_found_any_bank[0]),
        .I2(pi_dqs_found_any_bank[2]),
        .I3(pi_dqs_found_all_bank[1]),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h0100)) 
    \FSM_sequential_fine_adj_state_r[3]_i_8 
       (.I0(fine_adj_state_r149_out),
        .I1(\FSM_sequential_fine_adj_state_r[3]_i_10_n_0 ),
        .I2(fine_adj_state_r112_out),
        .I3(fine_adj_state_r3),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT5 #(
    .INIT(32'hFFFF80FF)) 
    \FSM_sequential_fine_adj_state_r[3]_i_9 
       (.I0(pi_dqs_found_all_bank[1]),
        .I1(pi_dqs_found_all_bank[0]),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(detect_pi_found_dqs),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_11_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[0] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r_reg[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ),
        .Q(fine_adj_state_r[0]),
        .R(rstdiv0_sync_r1));
  MUXF7 \FSM_sequential_fine_adj_state_r_reg[0]_i_3 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ),
        .S(fine_adj_state_r[0]));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[1] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r_reg[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ),
        .Q(fine_adj_state_r[1]),
        .R(rstdiv0_sync_r1));
  MUXF7 \FSM_sequential_fine_adj_state_r_reg[1]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ),
        .S(fine_adj_state_r[1]));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[2] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r_reg[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ),
        .Q(fine_adj_state_r[2]),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[3] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r_reg[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ),
        .Q(fine_adj_state_r[3]),
        .R(rstdiv0_sync_r1));
  MUXF7 \FSM_sequential_fine_adj_state_r_reg[3]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r_reg[3]_i_1_n_0 ),
        .S(fine_adj_state_r[1]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[0]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[0]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(\calib_data_offset_0_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[1]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[1]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(\calib_data_offset_0_reg[1] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[2]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[2]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .O(\calib_data_offset_0_reg[2] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[4]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[4]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .O(\calib_data_offset_0_reg[4] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[5]_i_2 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[5]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .O(\calib_data_offset_0_reg[5]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[0]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[0]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(p_0_in[0]),
        .O(\calib_data_offset_1_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[1]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[1]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(p_0_in[1]),
        .O(\calib_data_offset_1_reg[1] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[2]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[2]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(p_0_in[2]),
        .O(\calib_data_offset_1_reg[2] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[4]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[4]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(p_0_in[4]),
        .O(\calib_data_offset_1_reg[4] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[5]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[5]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(p_0_in[5]),
        .O(\calib_data_offset_1_reg[5] ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[0]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[0]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(\calib_data_offset_2_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[1]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[1]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(\calib_data_offset_2_reg[1] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[2]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[2]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .O(\calib_data_offset_2_reg[2] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[4]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[4]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .O(\calib_data_offset_2_reg[4] ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[5]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[5]),
        .I2(\calib_data_offset_0_reg[5] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .O(\calib_data_offset_2_reg[5] ));
  LUT6 #(
    .INIT(64'h4040404040707040)) 
    \calib_sel[1]_i_1 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .I3(\gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ),
        .I4(\gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_2 ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0000888000000000)) 
    \calib_sel[4]_i_1 
       (.I0(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ),
        .I1(rstdiv0_sync_r1_reg_rep__24),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [3]),
        .I5(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [2]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'h0001FFFF)) 
    \calib_zero_inputs[2]_i_3 
       (.I0(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ),
        .I1(pi_rst_stg1_cal[0]),
        .I2(pi_rst_stg1_cal[1]),
        .I3(pi_rst_stg1_cal[2]),
        .I4(rstdiv0_sync_r1_reg_rep__24),
        .O(\calib_zero_inputs_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hA2)) 
    \calib_zero_inputs[2]_i_4 
       (.I0(po_ck_addr_cmd_delay_done),
        .I1(rd_data_offset_cal_done),
        .I2(fine_adjust_done),
        .O(\calib_zero_inputs_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hDFBF0820)) 
    ck_po_stg2_f_en_i_1
       (.I0(fine_adj_state_r[1]),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[0]),
        .I4(ck_po_stg2_f_en),
        .O(ck_po_stg2_f_en_i_1_n_0));
  FDRE ck_po_stg2_f_en_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ck_po_stg2_f_en_i_1_n_0),
        .Q(ck_po_stg2_f_en),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT5 #(
    .INIT(32'hD7BF0020)) 
    ck_po_stg2_f_indec_i_1
       (.I0(fine_adj_state_r[1]),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[0]),
        .I4(ck_po_stg2_f_indec),
        .O(ck_po_stg2_f_indec_i_1_n_0));
  FDRE ck_po_stg2_f_indec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ck_po_stg2_f_indec_i_1_n_0),
        .Q(ck_po_stg2_f_indec),
        .R(rstdiv0_sync_r1_reg_rep__11));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_data_offset[0]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ),
        .O(\cmd_pipe_plus.mc_data_offset_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cmd_pipe_plus.mc_data_offset[1]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ),
        .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][1] ),
        .O(\cmd_pipe_plus.mc_data_offset_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cmd_pipe_plus.mc_data_offset[2]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][2] ),
        .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][1] ),
        .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ),
        .O(\cmd_pipe_plus.mc_data_offset_reg[2] ));
  LUT6 #(
    .INIT(64'h28888888AAAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset[3]_i_1 
       (.I0(sent_col),
        .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][3] ),
        .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][2] ),
        .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ),
        .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][1] ),
        .I5(col_rd_wr),
        .O(\cmd_pipe_plus.mc_data_offset_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset[4]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][4] ),
        .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][1] ),
        .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ),
        .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][2] ),
        .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][3] ),
        .O(\cmd_pipe_plus.mc_data_offset_reg[4] ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset[5]_i_2 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][5] ),
        .I1(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][3] ),
        .I2(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][2] ),
        .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ),
        .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][1] ),
        .I5(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][4] ),
        .O(\cmd_pipe_plus.mc_data_offset_reg[5] ));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_data_offset_1[0]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cmd_pipe_plus.mc_data_offset_1[1]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ),
        .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][7] ),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cmd_pipe_plus.mc_data_offset_1[2]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][8] ),
        .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][7] ),
        .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[2] ));
  LUT6 #(
    .INIT(64'h28888888AAAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset_1[3]_i_1 
       (.I0(sent_col),
        .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][9] ),
        .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][8] ),
        .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ),
        .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][7] ),
        .I5(col_rd_wr),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset_1[4]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][10] ),
        .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][7] ),
        .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ),
        .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][8] ),
        .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][9] ),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[4] ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset_1[5]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][11] ),
        .I1(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][9] ),
        .I2(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][8] ),
        .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ),
        .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][7] ),
        .I5(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][10] ),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[5] ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_data_offset_2[0]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cmd_pipe_plus.mc_data_offset_2[1]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ),
        .I1(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][13] ),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cmd_pipe_plus.mc_data_offset_2[2]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][14] ),
        .I1(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][13] ),
        .I2(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[2] ));
  LUT6 #(
    .INIT(64'h28888888AAAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset_2[3]_i_1 
       (.I0(sent_col),
        .I1(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][15] ),
        .I2(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][14] ),
        .I3(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ),
        .I4(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][13] ),
        .I5(col_rd_wr),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset_2[4]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][16] ),
        .I1(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][13] ),
        .I2(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ),
        .I3(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][14] ),
        .I4(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][15] ),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[4] ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cmd_pipe_plus.mc_data_offset_2[5]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][17] ),
        .I1(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][15] ),
        .I2(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][14] ),
        .I3(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ),
        .I4(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][13] ),
        .I5(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][16] ),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[5] ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT4 #(
    .INIT(16'h0FD0)) 
    \ctl_lane_cnt[0]_i_1__0 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(fine_adjust_lane_cnt[2]),
        .I2(\ctl_lane_cnt[2]_i_2__0_n_0 ),
        .I3(fine_adjust_lane_cnt[0]),
        .O(\ctl_lane_cnt[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT4 #(
    .INIT(16'h2FC0)) 
    \ctl_lane_cnt[1]_i_1__0 
       (.I0(fine_adjust_lane_cnt[2]),
        .I1(fine_adjust_lane_cnt[0]),
        .I2(\ctl_lane_cnt[2]_i_2__0_n_0 ),
        .I3(fine_adjust_lane_cnt[1]),
        .O(\ctl_lane_cnt[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \ctl_lane_cnt[2]_i_1__0 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(fine_adjust_lane_cnt[0]),
        .I2(\ctl_lane_cnt[2]_i_2__0_n_0 ),
        .I3(fine_adjust_lane_cnt[2]),
        .O(\ctl_lane_cnt[2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2040)) 
    \ctl_lane_cnt[2]_i_2__0 
       (.I0(fine_adj_state_r[1]),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[0]),
        .O(\ctl_lane_cnt[2]_i_2__0_n_0 ));
  FDRE \ctl_lane_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[0]_i_1__0_n_0 ),
        .Q(fine_adjust_lane_cnt[0]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \ctl_lane_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[1]_i_1__0_n_0 ),
        .Q(fine_adjust_lane_cnt[1]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \ctl_lane_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[2]_i_1__0_n_0 ),
        .Q(fine_adjust_lane_cnt[2]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT5 #(
    .INIT(32'h77777444)) 
    \dec_cnt[0]_i_1 
       (.I0(\dec_cnt_reg_n_0_[0] ),
        .I1(fine_adj_state_r[0]),
        .I2(\dec_cnt[4]_i_3_n_0 ),
        .I3(\dec_cnt_reg[2]_i_3_n_6 ),
        .I4(\dec_cnt[0]_i_2_n_0 ),
        .O(dec_cnt[0]));
  LUT6 #(
    .INIT(64'h00FF010100000000)) 
    \dec_cnt[0]_i_2 
       (.I0(\first_fail_taps_reg_n_0_[1] ),
        .I1(\first_fail_taps[5]_i_8_n_0 ),
        .I2(fine_adj_state_r3),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(fine_adj_state_r146_out),
        .I5(fine_adj_state_r149_out),
        .O(\dec_cnt[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9F9F9F9F9F909090)) 
    \dec_cnt[1]_i_1 
       (.I0(\dec_cnt_reg_n_0_[0] ),
        .I1(\dec_cnt_reg_n_0_[1] ),
        .I2(fine_adj_state_r[0]),
        .I3(\dec_cnt[4]_i_3_n_0 ),
        .I4(\dec_cnt_reg[2]_i_3_n_5 ),
        .I5(\dec_cnt[1]_i_2_n_0 ),
        .O(dec_cnt[1]));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h4FF44444)) 
    \dec_cnt[1]_i_2 
       (.I0(\first_fail_taps_reg_n_0_[2] ),
        .I1(\dec_cnt[4]_i_9_n_0 ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .I4(\first_fail_taps[5]_i_4_n_0 ),
        .O(\dec_cnt[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9F9F9F9F9F909090)) 
    \dec_cnt[2]_i_1 
       (.I0(\dec_cnt_reg_n_0_[2] ),
        .I1(\dec_cnt[2]_i_2_n_0 ),
        .I2(fine_adj_state_r[0]),
        .I3(\dec_cnt[4]_i_3_n_0 ),
        .I4(\dec_cnt_reg[2]_i_3_n_4 ),
        .I5(\dec_cnt[2]_i_4_n_0 ),
        .O(dec_cnt[2]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \dec_cnt[2]_i_2 
       (.I0(\dec_cnt_reg_n_0_[0] ),
        .I1(\dec_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h4FF4F4F444444444)) 
    \dec_cnt[2]_i_4 
       (.I0(\first_fail_taps_reg_n_0_[3] ),
        .I1(\dec_cnt[4]_i_9_n_0 ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .I4(\inc_cnt_reg_n_0_[1] ),
        .I5(\first_fail_taps[5]_i_4_n_0 ),
        .O(\dec_cnt[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_5 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\first_fail_taps_reg_n_0_[3] ),
        .O(\dec_cnt[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_6 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\first_fail_taps_reg_n_0_[2] ),
        .O(\dec_cnt[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_7 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\first_fail_taps_reg_n_0_[1] ),
        .O(\dec_cnt[2]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_8 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\first_fail_taps_reg_n_0_[0] ),
        .O(\dec_cnt[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FE01FFFF)) 
    \dec_cnt[3]_i_1 
       (.I0(\dec_cnt_reg_n_0_[1] ),
        .I1(\dec_cnt_reg_n_0_[0] ),
        .I2(\dec_cnt_reg_n_0_[2] ),
        .I3(\dec_cnt_reg_n_0_[3] ),
        .I4(fine_adj_state_r[0]),
        .I5(\dec_cnt[3]_i_2_n_0 ),
        .O(dec_cnt[3]));
  LUT6 #(
    .INIT(64'h0000000D000D000D)) 
    \dec_cnt[3]_i_2 
       (.I0(\dec_cnt[4]_i_9_n_0 ),
        .I1(\first_fail_taps_reg_n_0_[4] ),
        .I2(fine_adj_state_r[0]),
        .I3(\dec_cnt[3]_i_3_n_0 ),
        .I4(\dec_cnt_reg[4]_i_4_n_7 ),
        .I5(\dec_cnt[4]_i_3_n_0 ),
        .O(\dec_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h80080000)) 
    \dec_cnt[3]_i_3 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(fine_adj_state_r149_out),
        .I2(\dec_cnt[4]_i_10_n_0 ),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\dec_cnt[4]_i_11_n_0 ),
        .O(\dec_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h9F0000009F9F9F9F)) 
    \dec_cnt[4]_i_1 
       (.I0(\dec_cnt_reg_n_0_[4] ),
        .I1(\dec_cnt[4]_i_2_n_0 ),
        .I2(fine_adj_state_r[0]),
        .I3(\dec_cnt[4]_i_3_n_0 ),
        .I4(\dec_cnt_reg[4]_i_4_n_6 ),
        .I5(\dec_cnt[4]_i_5_n_0 ),
        .O(dec_cnt[4]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \dec_cnt[4]_i_10 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .O(\dec_cnt[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EAAAAAAA)) 
    \dec_cnt[4]_i_11 
       (.I0(stable_pass_cnt_reg__0[5]),
        .I1(stable_pass_cnt_reg__0[4]),
        .I2(stable_pass_cnt_reg__0[3]),
        .I3(stable_pass_cnt_reg__0[1]),
        .I4(stable_pass_cnt_reg__0[2]),
        .I5(first_fail_detect_reg_n_0),
        .O(\dec_cnt[4]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \dec_cnt[4]_i_2 
       (.I0(\dec_cnt_reg_n_0_[3] ),
        .I1(\dec_cnt_reg_n_0_[2] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .I3(\dec_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h404F)) 
    \dec_cnt[4]_i_3 
       (.I0(fine_adj_state_r146_out),
        .I1(fine_adj_state_r3),
        .I2(fine_adj_state_r149_out),
        .I3(\dec_cnt[5]_i_10_n_0 ),
        .O(\dec_cnt[4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h1011)) 
    \dec_cnt[4]_i_5 
       (.I0(\dec_cnt[4]_i_8_n_0 ),
        .I1(fine_adj_state_r[0]),
        .I2(\first_fail_taps_reg_n_0_[5] ),
        .I3(\dec_cnt[4]_i_9_n_0 ),
        .O(\dec_cnt[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[4]_i_6 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\first_fail_taps_reg_n_0_[5] ),
        .O(\dec_cnt[4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[4]_i_7 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\first_fail_taps_reg_n_0_[4] ),
        .O(\dec_cnt[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hC008CC0000000000)) 
    \dec_cnt[4]_i_8 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(fine_adj_state_r149_out),
        .I2(\dec_cnt[4]_i_10_n_0 ),
        .I3(\inc_cnt_reg_n_0_[5] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(\dec_cnt[4]_i_11_n_0 ),
        .O(\dec_cnt[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'h000B0000)) 
    \dec_cnt[4]_i_9 
       (.I0(first_fail_detect_reg_n_0),
        .I1(first_fail_detect_i_2_n_0),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .I3(fine_adj_state_r3),
        .I4(fine_adj_state_r149_out),
        .O(\dec_cnt[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0C08000800000000)) 
    \dec_cnt[5]_i_1 
       (.I0(\dec_cnt[5]_i_3_n_0 ),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[0]),
        .I4(\dec_cnt[5]_i_4_n_0 ),
        .I5(fine_adj_state_r[1]),
        .O(\dec_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFF0FFF0FEF0F)) 
    \dec_cnt[5]_i_10 
       (.I0(\first_fail_taps_reg_n_0_[3] ),
        .I1(\first_fail_taps_reg_n_0_[2] ),
        .I2(first_fail_detect_reg_n_0),
        .I3(\first_fail_taps_reg_n_0_[5] ),
        .I4(\first_fail_taps_reg_n_0_[1] ),
        .I5(\first_fail_taps_reg_n_0_[4] ),
        .O(\dec_cnt[5]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \dec_cnt[5]_i_11 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[5] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \dec_cnt[5]_i_12 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEFFAEFFAEFFAE)) 
    \dec_cnt[5]_i_3 
       (.I0(\first_fail_taps[5]_i_4_n_0 ),
        .I1(\dec_cnt[5]_i_7_n_0 ),
        .I2(fine_adj_state_r3),
        .I3(fine_adj_state_r149_out),
        .I4(\dec_cnt[5]_i_9_n_0 ),
        .I5(\first_fail_taps[5]_i_7_n_0 ),
        .O(\dec_cnt[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \dec_cnt[5]_i_4 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(fine_adjust_lane_cnt[2]),
        .I2(fine_adjust_lane_cnt[0]),
        .I3(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I4(init_dec_done_i_2_n_0),
        .O(\dec_cnt[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0003AAAAFF03AAAA)) 
    \dec_cnt[5]_i_5 
       (.I0(\dec_cnt[5]_i_10_n_0 ),
        .I1(\dec_cnt[5]_i_11_n_0 ),
        .I2(first_fail_detect_reg_n_0),
        .I3(\first_fail_taps[5]_i_8_n_0 ),
        .I4(fine_adj_state_r149_out),
        .I5(fine_adj_state_r3),
        .O(\dec_cnt[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \dec_cnt[5]_i_6 
       (.I0(\dec_cnt_reg_n_0_[5] ),
        .I1(\dec_cnt_reg_n_0_[1] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .I3(\dec_cnt_reg_n_0_[2] ),
        .I4(\dec_cnt_reg_n_0_[3] ),
        .I5(\dec_cnt_reg_n_0_[4] ),
        .O(\dec_cnt[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040000000)) 
    \dec_cnt[5]_i_7 
       (.I0(fine_adj_state_r112_out),
        .I1(detect_pi_found_dqs),
        .I2(pi_dqs_found_all_bank[1]),
        .I3(pi_dqs_found_all_bank[0]),
        .I4(pi_dqs_found_all_bank[2]),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_10_n_0 ),
        .O(\dec_cnt[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \dec_cnt[5]_i_8 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[0] ),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .I5(\inc_cnt_reg_n_0_[4] ),
        .O(fine_adj_state_r3));
  LUT6 #(
    .INIT(64'hEFFFFFFFFFFFFFFF)) 
    \dec_cnt[5]_i_9 
       (.I0(first_fail_detect_reg_n_0),
        .I1(\dec_cnt[5]_i_12_n_0 ),
        .I2(\inc_cnt_reg_n_0_[5] ),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .I5(\inc_cnt_reg_n_0_[0] ),
        .O(\dec_cnt[5]_i_9_n_0 ));
  FDRE \dec_cnt_reg[0] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[0]),
        .Q(\dec_cnt_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \dec_cnt_reg[1] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[1]),
        .Q(\dec_cnt_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \dec_cnt_reg[2] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[2]),
        .Q(\dec_cnt_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  CARRY4 \dec_cnt_reg[2]_i_3 
       (.CI(1'b0),
        .CO({\dec_cnt_reg[2]_i_3_n_0 ,\dec_cnt_reg[2]_i_3_n_1 ,\dec_cnt_reg[2]_i_3_n_2 ,\dec_cnt_reg[2]_i_3_n_3 }),
        .CYINIT(1'b1),
        .DI({\inc_cnt_reg_n_0_[3] ,\inc_cnt_reg_n_0_[2] ,\inc_cnt_reg_n_0_[1] ,\inc_cnt_reg_n_0_[0] }),
        .O({\dec_cnt_reg[2]_i_3_n_4 ,\dec_cnt_reg[2]_i_3_n_5 ,\dec_cnt_reg[2]_i_3_n_6 ,\dec_cnt_reg[2]_i_3_n_7 }),
        .S({\dec_cnt[2]_i_5_n_0 ,\dec_cnt[2]_i_6_n_0 ,\dec_cnt[2]_i_7_n_0 ,\dec_cnt[2]_i_8_n_0 }));
  FDRE \dec_cnt_reg[3] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[3]),
        .Q(\dec_cnt_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \dec_cnt_reg[4] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[4]),
        .Q(\dec_cnt_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  CARRY4 \dec_cnt_reg[4]_i_4 
       (.CI(\dec_cnt_reg[2]_i_3_n_0 ),
        .CO({\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED [3:1],\dec_cnt_reg[4]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\inc_cnt_reg_n_0_[4] }),
        .O({\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED [3:2],\dec_cnt_reg[4]_i_4_n_6 ,\dec_cnt_reg[4]_i_4_n_7 }),
        .S({1'b0,1'b0,\dec_cnt[4]_i_6_n_0 ,\dec_cnt[4]_i_7_n_0 }));
  FDRE \dec_cnt_reg[5] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[5]),
        .Q(\dec_cnt_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  MUXF7 \dec_cnt_reg[5]_i_2 
       (.I0(\dec_cnt[5]_i_5_n_0 ),
        .I1(\dec_cnt[5]_i_6_n_0 ),
        .O(dec_cnt[5]),
        .S(fine_adj_state_r[0]));
  LUT1 #(
    .INIT(2'h1)) 
    \detect_rd_cnt[0]_i_1 
       (.I0(detect_rd_cnt_reg__0[0]),
        .O(\detect_rd_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \detect_rd_cnt[1]_i_1 
       (.I0(detect_rd_cnt_reg__0[0]),
        .I1(detect_rd_cnt_reg__0[1]),
        .O(\detect_rd_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \detect_rd_cnt[2]_i_1 
       (.I0(detect_rd_cnt_reg__0[2]),
        .I1(detect_rd_cnt_reg__0[1]),
        .I2(detect_rd_cnt_reg__0[0]),
        .O(detect_rd_cnt0__0[2]));
  LUT5 #(
    .INIT(32'hFFFF0001)) 
    \detect_rd_cnt[3]_i_1 
       (.I0(detect_rd_cnt_reg__0[0]),
        .I1(detect_rd_cnt_reg__0[1]),
        .I2(detect_rd_cnt_reg__0[2]),
        .I3(detect_rd_cnt_reg__0[3]),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .O(\detect_rd_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0000)) 
    \detect_rd_cnt[3]_i_2 
       (.I0(detect_rd_cnt_reg__0[1]),
        .I1(detect_rd_cnt_reg__0[2]),
        .I2(detect_rd_cnt_reg__0[3]),
        .I3(detect_rd_cnt_reg__0[0]),
        .I4(detect_pi_found_dqs),
        .O(detect_rd_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \detect_rd_cnt[3]_i_3 
       (.I0(detect_rd_cnt_reg__0[3]),
        .I1(detect_rd_cnt_reg__0[0]),
        .I2(detect_rd_cnt_reg__0[2]),
        .I3(detect_rd_cnt_reg__0[1]),
        .O(detect_rd_cnt0__0[3]));
  FDSE \detect_rd_cnt_reg[0] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(\detect_rd_cnt[0]_i_1_n_0 ),
        .Q(detect_rd_cnt_reg__0[0]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDSE \detect_rd_cnt_reg[1] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(\detect_rd_cnt[1]_i_1_n_0 ),
        .Q(detect_rd_cnt_reg__0[1]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDSE \detect_rd_cnt_reg[2] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(detect_rd_cnt0__0[2]),
        .Q(detect_rd_cnt_reg__0[2]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDRE \detect_rd_cnt_reg[3] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(detect_rd_cnt0__0[3]),
        .Q(detect_rd_cnt_reg__0[3]),
        .R(\detect_rd_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    dqs_found_done_r_i_1
       (.I0(dqs_found_done_r_i_2_n_0),
        .I1(fine_adj_state_r[1]),
        .I2(dqs_found_done_r_i_3_n_0),
        .I3(fine_adj_state_r[0]),
        .I4(init_dqsfound_done_r1_reg_n_0),
        .I5(dqs_found_done_r_i_4_n_0),
        .O(dqs_found_done_r0));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'h1)) 
    dqs_found_done_r_i_2
       (.I0(\rnk_cnt_r_reg_n_0_[1] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .O(dqs_found_done_r_i_2_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    dqs_found_done_r_i_3
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[3]),
        .O(dqs_found_done_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    dqs_found_done_r_i_4
       (.I0(pi_dqs_found_all_bank[2]),
        .I1(pi_dqs_found_all_bank[0]),
        .I2(pi_dqs_found_all_bank[1]),
        .O(dqs_found_done_r_i_4_n_0));
  FDRE dqs_found_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_found_done_r0),
        .Q(pi_dqs_found_done),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT4 #(
    .INIT(16'h2F20)) 
    dqs_found_prech_req_i_1
       (.I0(dqs_found_prech_req_i_2_n_0),
        .I1(fine_adj_state_r[2]),
        .I2(dqs_found_prech_req_i_3_n_0),
        .I3(dqs_found_prech_req),
        .O(dqs_found_prech_req_i_1_n_0));
  LUT6 #(
    .INIT(64'hFDDD0888FFFFCCCC)) 
    dqs_found_prech_req_i_2
       (.I0(first_fail_detect_reg_n_0),
        .I1(fine_adj_state_r19_out),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .I3(\first_fail_taps[5]_i_10_n_0 ),
        .I4(fine_adj_state_r112_out),
        .I5(fine_adj_state_r149_out),
        .O(dqs_found_prech_req_i_2_n_0));
  LUT6 #(
    .INIT(64'hC008000800000000)) 
    dqs_found_prech_req_i_3
       (.I0(dqs_found_prech_req_i_6_n_0),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[0]),
        .I4(prech_done),
        .I5(fine_adj_state_r[1]),
        .O(dqs_found_prech_req_i_3_n_0));
  LUT6 #(
    .INIT(64'h1000010001000000)) 
    dqs_found_prech_req_i_4
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[5] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(\inc_cnt_reg_n_0_[4] ),
        .O(fine_adj_state_r19_out));
  LUT6 #(
    .INIT(64'h0000001000100000)) 
    dqs_found_prech_req_i_5
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[5] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(\inc_cnt_reg_n_0_[4] ),
        .O(fine_adj_state_r112_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF80AA80)) 
    dqs_found_prech_req_i_6
       (.I0(fine_adj_state_r112_out),
        .I1(fine_adj_state_r149_out),
        .I2(fine_adj_state_r114_out),
        .I3(dqs_found_prech_req_i_7_n_0),
        .I4(fine_adj_state_r19_out),
        .I5(dqs_found_prech_req_i_8_n_0),
        .O(dqs_found_prech_req_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    dqs_found_prech_req_i_7
       (.I0(detect_pi_found_dqs),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(pi_dqs_found_all_bank[2]),
        .O(dqs_found_prech_req_i_7_n_0));
  LUT6 #(
    .INIT(64'h0000000008000000)) 
    dqs_found_prech_req_i_8
       (.I0(fine_adj_state_r19_out),
        .I1(\first_fail_taps[5]_i_8_n_0 ),
        .I2(\first_fail_taps[5]_i_10_n_0 ),
        .I3(fine_adj_state_r149_out),
        .I4(first_fail_detect_reg_n_0),
        .I5(\first_fail_taps[5]_i_11_n_0 ),
        .O(dqs_found_prech_req_i_8_n_0));
  FDRE dqs_found_prech_req_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_found_prech_req_i_1_n_0),
        .Q(dqs_found_prech_req),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE dqs_found_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_start_reg),
        .Q(dqs_found_start_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hri_0 
       (.I0(1'b1),
        .O(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hri_1 
       (.I0(1'b1),
        .O(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_1 ));
  LUT1 #(
    .INIT(2'h2)) 
    \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hri_2 
       (.I0(1'b1),
        .O(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_2 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000400)) 
    final_dec_done_i_1
       (.I0(fine_adj_state_r[1]),
        .I1(init_dec_done_i_3_n_0),
        .I2(fine_adj_state_r1),
        .I3(init_dec_done_reg_n_0),
        .I4(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I5(final_dec_done_reg_n_0),
        .O(final_dec_done_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    final_dec_done_i_2
       (.I0(init_dec_done_i_2_n_0),
        .I1(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .O(fine_adj_state_r1));
  FDRE final_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(final_dec_done_i_1_n_0),
        .Q(final_dec_done_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010000)) 
    fine_adjust_done_r_i_1
       (.I0(fine_adj_state_r[0]),
        .I1(fine_adj_state_r[2]),
        .I2(dqs_found_done_r_i_4_n_0),
        .I3(fine_adj_state_r[3]),
        .I4(fine_adj_state_r[1]),
        .I5(fine_adjust_done),
        .O(fine_adjust_done_r_i_1_n_0));
  FDRE fine_adjust_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_adjust_done_r_i_1_n_0),
        .Q(fine_adjust_done),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000100)) 
    fine_adjust_i_1
       (.I0(fine_adj_state_r[0]),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(init_dqsfound_done_r5),
        .I4(fine_adj_state_r[1]),
        .I5(fine_adjust_reg_n_0),
        .O(fine_adjust_i_1_n_0));
  FDRE fine_adjust_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_adjust_i_1_n_0),
        .Q(fine_adjust_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__12));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT4 #(
    .INIT(16'hFAFE)) 
    first_fail_detect_i_1
       (.I0(\first_fail_taps[5]_i_7_n_0 ),
        .I1(first_fail_detect_i_2_n_0),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .I3(first_fail_detect_reg_n_0),
        .O(first_fail_detect_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    first_fail_detect_i_2
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[0] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(first_fail_detect_i_2_n_0));
  FDRE first_fail_detect_reg
       (.C(CLK),
        .CE(first_fail_detect),
        .D(first_fail_detect_i_1_n_0),
        .Q(first_fail_detect_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__13));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[0]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\first_fail_taps[5]_i_7_n_0 ),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .O(\first_fail_taps[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[1]_i_1 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\first_fail_taps[5]_i_7_n_0 ),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .O(\first_fail_taps[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[2]_i_1 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\first_fail_taps[5]_i_7_n_0 ),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .O(\first_fail_taps[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[3]_i_1 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\first_fail_taps[5]_i_7_n_0 ),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .O(\first_fail_taps[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[4]_i_1 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\first_fail_taps[5]_i_7_n_0 ),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .O(\first_fail_taps[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0808080008000800)) 
    \first_fail_taps[5]_i_1 
       (.I0(fine_adj_state_r[1]),
        .I1(\first_fail_taps[5]_i_3_n_0 ),
        .I2(fine_adj_state_r[0]),
        .I3(\first_fail_taps[5]_i_4_n_0 ),
        .I4(\first_fail_taps[5]_i_5_n_0 ),
        .I5(fine_adj_state_r149_out),
        .O(first_fail_detect));
  LUT6 #(
    .INIT(64'h00000001FFFFFFFF)) 
    \first_fail_taps[5]_i_10 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\first_fail_taps[5]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \first_fail_taps[5]_i_11 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .O(\first_fail_taps[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[5]_i_2 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\first_fail_taps[5]_i_7_n_0 ),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .O(\first_fail_taps[5]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \first_fail_taps[5]_i_3 
       (.I0(fine_adj_state_r[3]),
        .I1(fine_adj_state_r[2]),
        .O(\first_fail_taps[5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h08888888)) 
    \first_fail_taps[5]_i_4 
       (.I0(fine_adj_state_r146_out),
        .I1(detect_pi_found_dqs),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(pi_dqs_found_all_bank[0]),
        .I4(pi_dqs_found_all_bank[1]),
        .O(\first_fail_taps[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hABBBBBBBBBBBBBBB)) 
    \first_fail_taps[5]_i_5 
       (.I0(\first_fail_taps[5]_i_7_n_0 ),
        .I1(stable_pass_cnt_reg__0[5]),
        .I2(stable_pass_cnt_reg__0[4]),
        .I3(stable_pass_cnt_reg__0[3]),
        .I4(stable_pass_cnt_reg__0[1]),
        .I5(stable_pass_cnt_reg__0[2]),
        .O(\first_fail_taps[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h7F00)) 
    \first_fail_taps[5]_i_6 
       (.I0(pi_dqs_found_all_bank[1]),
        .I1(pi_dqs_found_all_bank[0]),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(detect_pi_found_dqs),
        .O(fine_adj_state_r149_out));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'hB3F3)) 
    \first_fail_taps[5]_i_7 
       (.I0(\first_fail_taps[5]_i_10_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(\first_fail_taps[5]_i_8_n_0 ),
        .I3(\first_fail_taps[5]_i_11_n_0 ),
        .O(\first_fail_taps[5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT5 #(
    .INIT(32'h00007FFF)) 
    \first_fail_taps[5]_i_8 
       (.I0(stable_pass_cnt_reg__0[2]),
        .I1(stable_pass_cnt_reg__0[1]),
        .I2(stable_pass_cnt_reg__0[3]),
        .I3(stable_pass_cnt_reg__0[4]),
        .I4(stable_pass_cnt_reg__0[5]),
        .O(\first_fail_taps[5]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \first_fail_taps[5]_i_9 
       (.I0(first_fail_detect_reg_n_0),
        .I1(\first_fail_taps[5]_i_8_n_0 ),
        .I2(first_fail_detect_i_2_n_0),
        .O(fine_adj_state_r146_out));
  FDRE \first_fail_taps_reg[0] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\first_fail_taps[0]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \first_fail_taps_reg[1] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\first_fail_taps[1]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \first_fail_taps_reg[2] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\first_fail_taps[2]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \first_fail_taps_reg[3] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\first_fail_taps[3]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \first_fail_taps_reg[4] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\first_fail_taps[4]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \first_fail_taps_reg[5] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\first_fail_taps[5]_i_2_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF40F0)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_1 
       (.I0(fine_adjust_done),
        .I1(rd_data_offset_cal_done),
        .I2(po_ck_addr_cmd_delay_done),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I4(rstdiv0_sync_r1_reg_rep__24_0),
        .I5(pi_fine_dly_dec_done_reg),
        .O(SR));
  LUT2 #(
    .INIT(4'h8)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_4 
       (.I0(pi_dqs_found_done),
        .I1(pi_calib_done),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ));
  LUT6 #(
    .INIT(64'h00000000BAFF8AFF)) 
    \gen_byte_sel_div2.calib_in_common_i_2 
       (.I0(pi_calib_done_r1_reg),
        .I1(fine_adjust_done),
        .I2(rd_data_offset_cal_done),
        .I3(po_ck_addr_cmd_delay_done),
        .I4(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ),
        .I5(pi_fine_dly_dec_done_reg),
        .O(\gen_byte_sel_div2.calib_in_common_reg ));
  LUT6 #(
    .INIT(64'hFFFF8F8000008F80)) 
    \gen_byte_sel_div2.ctl_lane_sel[0]_i_1 
       (.I0(fine_adjust_lane_cnt[0]),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ),
        .I2(po_ck_addr_cmd_delay_done),
        .I3(ctl_lane_cnt[0]),
        .I4(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[0] ));
  LUT6 #(
    .INIT(64'hFFFF8F8000008F80)) 
    \gen_byte_sel_div2.ctl_lane_sel[1]_i_1 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ),
        .I2(po_ck_addr_cmd_delay_done),
        .I3(ctl_lane_cnt[1]),
        .I4(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[1] ));
  LUT6 #(
    .INIT(64'hFFFF8F8000008F80)) 
    \gen_byte_sel_div2.ctl_lane_sel[2]_i_1 
       (.I0(fine_adjust_lane_cnt[2]),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ),
        .I2(po_ck_addr_cmd_delay_done),
        .I3(ctl_lane_cnt[2]),
        .I4(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_2 ),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gen_byte_sel_div2.ctl_lane_sel[2]_i_2 
       (.I0(pi_rst_stg1_cal[0]),
        .I1(pi_rst_stg1_cal[1]),
        .I2(pi_rst_stg1_cal[2]),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'hF7FF7777)) 
    \gen_byte_sel_div2.ctl_lane_sel[2]_i_3 
       (.I0(dqs_po_dec_done),
        .I1(pi_fine_dly_dec_done),
        .I2(fine_adjust_done),
        .I3(rd_data_offset_cal_done),
        .I4(po_ck_addr_cmd_delay_done),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \inc_cnt[0]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \inc_cnt[1]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \inc_cnt[2]_i_1 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \inc_cnt[3]_i_1 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .O(\inc_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \inc_cnt[4]_i_1 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[4]));
  LUT5 #(
    .INIT(32'h00100000)) 
    \inc_cnt[5]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[0]),
        .I4(fine_adj_state_r[1]),
        .O(\inc_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \inc_cnt[5]_i_2 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[0] ),
        .I5(\inc_cnt_reg_n_0_[4] ),
        .O(p_0_in__0[5]));
  FDRE \inc_cnt_reg[0] 
       (.C(CLK),
        .CE(\inc_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0[0]),
        .Q(\inc_cnt_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \inc_cnt_reg[1] 
       (.C(CLK),
        .CE(\inc_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0[1]),
        .Q(\inc_cnt_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \inc_cnt_reg[2] 
       (.C(CLK),
        .CE(\inc_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0[2]),
        .Q(\inc_cnt_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \inc_cnt_reg[3] 
       (.C(CLK),
        .CE(\inc_cnt[5]_i_1_n_0 ),
        .D(\inc_cnt[3]_i_1_n_0 ),
        .Q(\inc_cnt_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \inc_cnt_reg[4] 
       (.C(CLK),
        .CE(\inc_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0[4]),
        .Q(\inc_cnt_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \inc_cnt_reg[5] 
       (.C(CLK),
        .CE(\inc_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0[5]),
        .Q(\inc_cnt_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  LUT1 #(
    .INIT(2'h1)) 
    \init_dec_cnt[0]_i_1 
       (.I0(init_dec_cnt_reg__0[0]),
        .O(\init_dec_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \init_dec_cnt[1]_i_1 
       (.I0(init_dec_cnt_reg__0[0]),
        .I1(init_dec_cnt_reg__0[1]),
        .O(\init_dec_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \init_dec_cnt[2]_i_1 
       (.I0(init_dec_cnt_reg__0[2]),
        .I1(init_dec_cnt_reg__0[0]),
        .I2(init_dec_cnt_reg__0[1]),
        .O(init_dec_cnt0[2]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \init_dec_cnt[3]_i_1 
       (.I0(init_dec_cnt_reg__0[1]),
        .I1(init_dec_cnt_reg__0[0]),
        .I2(init_dec_cnt_reg__0[2]),
        .I3(init_dec_cnt_reg__0[3]),
        .O(init_dec_cnt0[3]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \init_dec_cnt[4]_i_1 
       (.I0(init_dec_cnt_reg__0[4]),
        .I1(init_dec_cnt_reg__0[3]),
        .I2(init_dec_cnt_reg__0[2]),
        .I3(init_dec_cnt_reg__0[0]),
        .I4(init_dec_cnt_reg__0[1]),
        .O(init_dec_cnt0[4]));
  LUT6 #(
    .INIT(64'h0020000000000000)) 
    \init_dec_cnt[5]_i_1 
       (.I0(fine_adj_state_r[0]),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[3]),
        .I3(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I5(fine_adj_state_r[1]),
        .O(\init_dec_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \init_dec_cnt[5]_i_2 
       (.I0(init_dec_cnt_reg__0[5]),
        .I1(init_dec_cnt_reg__0[1]),
        .I2(init_dec_cnt_reg__0[0]),
        .I3(init_dec_cnt_reg__0[2]),
        .I4(init_dec_cnt_reg__0[3]),
        .I5(init_dec_cnt_reg__0[4]),
        .O(init_dec_cnt0[5]));
  FDSE \init_dec_cnt_reg[0] 
       (.C(CLK),
        .CE(\init_dec_cnt[5]_i_1_n_0 ),
        .D(\init_dec_cnt[0]_i_1_n_0 ),
        .Q(init_dec_cnt_reg__0[0]),
        .S(rstdiv0_sync_r1_reg_rep__18));
  FDSE \init_dec_cnt_reg[1] 
       (.C(CLK),
        .CE(\init_dec_cnt[5]_i_1_n_0 ),
        .D(\init_dec_cnt[1]_i_1_n_0 ),
        .Q(init_dec_cnt_reg__0[1]),
        .S(rstdiv0_sync_r1_reg_rep__18));
  FDSE \init_dec_cnt_reg[2] 
       (.C(CLK),
        .CE(\init_dec_cnt[5]_i_1_n_0 ),
        .D(init_dec_cnt0[2]),
        .Q(init_dec_cnt_reg__0[2]),
        .S(rstdiv0_sync_r1_reg_rep__18));
  FDSE \init_dec_cnt_reg[3] 
       (.C(CLK),
        .CE(\init_dec_cnt[5]_i_1_n_0 ),
        .D(init_dec_cnt0[3]),
        .Q(init_dec_cnt_reg__0[3]),
        .S(rstdiv0_sync_r1_reg_rep__18));
  FDSE \init_dec_cnt_reg[4] 
       (.C(CLK),
        .CE(\init_dec_cnt[5]_i_1_n_0 ),
        .D(init_dec_cnt0[4]),
        .Q(init_dec_cnt_reg__0[4]),
        .S(rstdiv0_sync_r1_reg_rep__18));
  FDRE \init_dec_cnt_reg[5] 
       (.C(CLK),
        .CE(\init_dec_cnt[5]_i_1_n_0 ),
        .D(init_dec_cnt0[5]),
        .Q(init_dec_cnt_reg__0[5]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAABAAAA)) 
    init_dec_done_i_1
       (.I0(init_dec_done_reg_n_0),
        .I1(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I3(init_dec_done_i_2_n_0),
        .I4(init_dec_done_i_3_n_0),
        .I5(fine_adj_state_r[1]),
        .O(init_dec_done_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    init_dec_done_i_2
       (.I0(\dec_cnt_reg_n_0_[4] ),
        .I1(\dec_cnt_reg_n_0_[3] ),
        .I2(\dec_cnt_reg_n_0_[2] ),
        .I3(\dec_cnt_reg_n_0_[0] ),
        .I4(\dec_cnt_reg_n_0_[1] ),
        .I5(\dec_cnt_reg_n_0_[5] ),
        .O(init_dec_done_i_2_n_0));
  LUT3 #(
    .INIT(8'h08)) 
    init_dec_done_i_3
       (.I0(fine_adj_state_r[3]),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[0]),
        .O(init_dec_done_i_3_n_0));
  FDRE init_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dec_done_i_1_n_0),
        .Q(init_dec_done_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE init_dqsfound_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data_offset_cal_done),
        .Q(init_dqsfound_done_r1_reg_n_0),
        .R(1'b0));
  FDRE init_dqsfound_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dqsfound_done_r1_reg_n_0),
        .Q(\calib_data_offset_0_reg[5] ),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r4_reg_srl2 " *) 
  SRL16E init_dqsfound_done_r4_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(\calib_data_offset_0_reg[5] ),
        .Q(init_dqsfound_done_r4_reg_srl2_n_0));
  FDRE init_dqsfound_done_r5_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dqsfound_done_r4_reg_srl2_n_0),
        .Q(init_dqsfound_done_r5),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAAABAAA8)) 
    init_dqsfound_done_r_i_1
       (.I0(init_dqsfound_done_r),
        .I1(init_dqsfound_done_r_i_3_n_0),
        .I2(p_1_in60_in),
        .I3(p_1_in65_in),
        .I4(rd_data_offset_cal_done),
        .O(init_dqsfound_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    init_dqsfound_done_r_i_2
       (.I0(p_1_in60_in),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .I3(p_1_in65_in),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(init_dqsfound_done_r));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT5 #(
    .INIT(32'hFEEEEEEE)) 
    init_dqsfound_done_r_i_3
       (.I0(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(pi_dqs_found_all_bank[1]),
        .I3(pi_dqs_found_all_bank[0]),
        .I4(pi_dqs_found_all_bank[2]),
        .O(init_dqsfound_done_r_i_3_n_0));
  FDRE init_dqsfound_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dqsfound_done_r_i_1_n_0),
        .Q(rd_data_offset_cal_done),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000AB00)) 
    ofifo_rst_i_1
       (.I0(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I1(\calib_sel_reg[1] [1]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(pi_rst_stg1_cal[1]),
        .I4(\calib_zero_inputs_reg[2]_1 [1]),
        .I5(A_rst_primitives),
        .O(ofifo_rst0));
  LUT5 #(
    .INIT(32'h44440004)) 
    \phaser_in_gen.phaser_in_i_5 
       (.I0(\calib_zero_inputs_reg[2]_1 [1]),
        .I1(pi_rst_stg1_cal[1]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_pi_rst_dqs_find155_out));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_5__0 
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(pi_rst_stg1_cal[0]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(D_pi_rst_dqs_find84_out));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    \phaser_in_gen.phaser_in_i_5__1 
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(pi_rst_stg1_cal[0]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_pi_rst_dqs_find110_out));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_5__2 
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(pi_rst_stg1_cal[0]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(B_pi_rst_dqs_find32_out));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_5__3 
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(pi_rst_stg1_cal[0]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(C_pi_rst_dqs_find58_out));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    \phaser_in_gen.phaser_in_i_5__4 
       (.I0(\calib_zero_inputs_reg[2]_1 [2]),
        .I1(pi_rst_stg1_cal[2]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_pi_rst_dqs_find81_out));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_5__5 
       (.I0(\calib_zero_inputs_reg[2]_1 [2]),
        .I1(pi_rst_stg1_cal[2]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(B_pi_rst_dqs_find29_out));
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_5__6 
       (.I0(\calib_zero_inputs_reg[2]_1 [2]),
        .I1(pi_rst_stg1_cal[2]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(C_pi_rst_dqs_find55_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    phaser_out_i_3
       (.I0(\calib_zero_inputs_reg[2]_1 [1]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_po_fine_inc145_out));
  LUT6 #(
    .INIT(64'h5454545454000000)) 
    phaser_out_i_3__3
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(D_po_fine_inc74_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    phaser_out_i_3__4
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_po_fine_inc100_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    phaser_out_i_3__5
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(B_po_fine_inc22_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    phaser_out_i_3__6
       (.I0(\calib_zero_inputs_reg[2]_1 [0]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(C_po_fine_inc48_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    phaser_out_i_3__7
       (.I0(\calib_zero_inputs_reg[2]_1 [2]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_po_fine_inc71_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    phaser_out_i_3__8
       (.I0(\calib_zero_inputs_reg[2]_1 [2]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(B_po_fine_inc19_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    phaser_out_i_3__9
       (.I0(\calib_zero_inputs_reg[2]_1 [2]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(C_po_fine_inc45_out));
  LUT6 #(
    .INIT(64'h0000000000540000)) 
    phaser_out_i_4
       (.I0(\calib_zero_inputs_reg[2]_1 [1]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\calib_sel_reg[1] [1]),
        .O(B_po_fine_inc30_out));
  LUT6 #(
    .INIT(64'h0000000000540000)) 
    phaser_out_i_4__0
       (.I0(\calib_zero_inputs_reg[2]_1 [1]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\calib_sel_reg[1] [0]),
        .O(C_po_fine_inc69_out));
  LUT6 #(
    .INIT(64'h0054000000000000)) 
    phaser_out_i_4__1
       (.I0(\calib_zero_inputs_reg[2]_1 [1]),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\calib_sel_reg[1] [1]),
        .O(D_po_fine_inc108_out));
  LUT4 #(
    .INIT(16'h8000)) 
    \pi_dqs_found_all_bank[0]_i_1 
       (.I0(pi_dqs_found_lanes_r3[2]),
        .I1(pi_dqs_found_lanes_r3[3]),
        .I2(pi_dqs_found_lanes_r3[1]),
        .I3(pi_dqs_found_lanes_r3[0]),
        .O(p_8_out[0]));
  LUT3 #(
    .INIT(8'h80)) 
    \pi_dqs_found_all_bank[2]_i_1 
       (.I0(pi_dqs_found_lanes_r3[8]),
        .I1(pi_dqs_found_lanes_r3[10]),
        .I2(pi_dqs_found_lanes_r3[9]),
        .O(p_8_out[2]));
  FDRE \pi_dqs_found_all_bank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_all_bank[0]),
        .Q(pi_dqs_found_all_bank_r[0]),
        .R(1'b0));
  FDRE \pi_dqs_found_all_bank_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_all_bank[2]),
        .Q(pi_dqs_found_all_bank_r[2]),
        .R(1'b0));
  FDRE \pi_dqs_found_all_bank_reg[0] 
       (.C(CLK),
        .CE(pi_dqs_found_start_reg),
        .D(p_8_out[0]),
        .Q(pi_dqs_found_all_bank[0]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \pi_dqs_found_all_bank_reg[1] 
       (.C(CLK),
        .CE(pi_dqs_found_start_reg),
        .D(pi_dqs_found_lanes_r3[4]),
        .Q(pi_dqs_found_all_bank[1]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \pi_dqs_found_all_bank_reg[2] 
       (.C(CLK),
        .CE(pi_dqs_found_start_reg),
        .D(p_8_out[2]),
        .Q(pi_dqs_found_all_bank[2]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pi_dqs_found_any_bank[0]_i_1 
       (.I0(pi_dqs_found_lanes_r3[2]),
        .I1(pi_dqs_found_lanes_r3[0]),
        .I2(pi_dqs_found_lanes_r3[3]),
        .I3(pi_dqs_found_lanes_r3[1]),
        .O(\pi_dqs_found_any_bank[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \pi_dqs_found_any_bank[2]_i_1 
       (.I0(pi_dqs_found_lanes_r3[8]),
        .I1(pi_dqs_found_lanes_r3[10]),
        .I2(pi_dqs_found_lanes_r3[9]),
        .O(\pi_dqs_found_any_bank[2]_i_1_n_0 ));
  FDRE \pi_dqs_found_any_bank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_any_bank[0]),
        .Q(\pi_dqs_found_any_bank_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \pi_dqs_found_any_bank_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_all_bank[1]),
        .Q(p_2_in82_in),
        .R(1'b0));
  FDRE \pi_dqs_found_any_bank_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_any_bank[2]),
        .Q(p_2_in81_in),
        .R(1'b0));
  FDRE \pi_dqs_found_any_bank_reg[0] 
       (.C(CLK),
        .CE(pi_dqs_found_start_reg),
        .D(\pi_dqs_found_any_bank[0]_i_1_n_0 ),
        .Q(pi_dqs_found_any_bank[0]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \pi_dqs_found_any_bank_reg[2] 
       (.C(CLK),
        .CE(pi_dqs_found_start_reg),
        .D(\pi_dqs_found_any_bank[2]_i_1_n_0 ),
        .Q(pi_dqs_found_any_bank[2]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[0]),
        .Q(pi_dqs_found_lanes_r1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[7]),
        .Q(pi_dqs_found_lanes_r1[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[1]),
        .Q(pi_dqs_found_lanes_r1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[2]),
        .Q(pi_dqs_found_lanes_r1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[3]),
        .Q(pi_dqs_found_lanes_r1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[4]),
        .Q(pi_dqs_found_lanes_r1[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_2 ),
        .Q(pi_dqs_found_lanes_r1[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_1 ),
        .Q(pi_dqs_found_lanes_r1[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_0 ),
        .Q(pi_dqs_found_lanes_r1[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[5]),
        .Q(pi_dqs_found_lanes_r1[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[6]),
        .Q(pi_dqs_found_lanes_r1[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[0]),
        .Q(pi_dqs_found_lanes_r2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[10]),
        .Q(pi_dqs_found_lanes_r2[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[1]),
        .Q(pi_dqs_found_lanes_r2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[2]),
        .Q(pi_dqs_found_lanes_r2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[3]),
        .Q(pi_dqs_found_lanes_r2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[4]),
        .Q(pi_dqs_found_lanes_r2[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[5]),
        .Q(pi_dqs_found_lanes_r2[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[6]),
        .Q(pi_dqs_found_lanes_r2[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[7]),
        .Q(pi_dqs_found_lanes_r2[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[8]),
        .Q(pi_dqs_found_lanes_r2[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[9]),
        .Q(pi_dqs_found_lanes_r2[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[0]),
        .Q(pi_dqs_found_lanes_r3[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[10]),
        .Q(pi_dqs_found_lanes_r3[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[1]),
        .Q(pi_dqs_found_lanes_r3[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[2]),
        .Q(pi_dqs_found_lanes_r3[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[3]),
        .Q(pi_dqs_found_lanes_r3[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[4]),
        .Q(pi_dqs_found_lanes_r3[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[5]),
        .Q(pi_dqs_found_lanes_r3[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[6]),
        .Q(pi_dqs_found_lanes_r3[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[7]),
        .Q(pi_dqs_found_lanes_r3[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[8]),
        .Q(pi_dqs_found_lanes_r3[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[9]),
        .Q(pi_dqs_found_lanes_r3[9]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \pi_rst_stg1_cal[0]_i_1 
       (.I0(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .I1(rst_dqs_find_reg_n_0),
        .O(\pi_rst_stg1_cal[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \pi_rst_stg1_cal[1]_i_1 
       (.I0(p_1_in65_in),
        .I1(rst_dqs_find_reg_n_0),
        .O(\pi_rst_stg1_cal[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \pi_rst_stg1_cal[2]_i_1 
       (.I0(p_1_in60_in),
        .I1(rst_dqs_find_reg_n_0),
        .O(\pi_rst_stg1_cal[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000E0)) 
    \pi_rst_stg1_cal_r1[0]_i_1 
       (.I0(pi_dqs_found_all_bank[0]),
        .I1(\pi_dqs_found_any_bank_r_reg_n_0_[0] ),
        .I2(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .I3(fine_adjust_reg_n_0),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .I5(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .O(pi_rst_stg1_cal_r1_reg022_out));
  LUT6 #(
    .INIT(64'h000000FF000000E0)) 
    \pi_rst_stg1_cal_r1[1]_i_1 
       (.I0(pi_dqs_found_all_bank[1]),
        .I1(p_2_in82_in),
        .I2(p_0_in29_in),
        .I3(fine_adjust_reg_n_0),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .I5(p_1_in65_in),
        .O(pi_rst_stg1_cal_r1_reg019_out));
  LUT6 #(
    .INIT(64'h000000FF000000E0)) 
    \pi_rst_stg1_cal_r1[2]_i_1 
       (.I0(pi_dqs_found_all_bank[2]),
        .I1(p_2_in81_in),
        .I2(p_0_in24_in),
        .I3(fine_adjust_reg_n_0),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .I5(p_1_in60_in),
        .O(pi_rst_stg1_cal_r1_reg0));
  FDRE \pi_rst_stg1_cal_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_rst_stg1_cal_r1_reg022_out),
        .Q(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_rst_stg1_cal_r1_reg019_out),
        .Q(p_0_in29_in),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_rst_stg1_cal_r1_reg0),
        .Q(p_0_in24_in),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0002)) 
    \pi_rst_stg1_cal_r[0]_i_1 
       (.I0(\pi_rst_stg1_cal_r[0]_i_2_n_0 ),
        .I1(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .I2(fine_adjust_reg_n_0),
        .I3(rstdiv0_sync_r1_reg_rep__23),
        .O(\pi_rst_stg1_cal_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF2F22)) 
    \pi_rst_stg1_cal_r[0]_i_2 
       (.I0(\pi_dqs_found_any_bank_r_reg_n_0_[0] ),
        .I1(pi_dqs_found_all_bank[0]),
        .I2(dqs_found_start_r),
        .I3(pi_dqs_found_start_reg),
        .I4(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .I5(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .O(\pi_rst_stg1_cal_r[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \pi_rst_stg1_cal_r[1]_i_1 
       (.I0(\pi_rst_stg1_cal_r[1]_i_2_n_0 ),
        .I1(p_0_in29_in),
        .I2(fine_adjust_reg_n_0),
        .I3(rstdiv0_sync_r1_reg_rep__23),
        .O(\pi_rst_stg1_cal_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF2F22)) 
    \pi_rst_stg1_cal_r[1]_i_2 
       (.I0(p_2_in82_in),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(dqs_found_start_r),
        .I3(pi_dqs_found_start_reg),
        .I4(\rd_byte_data_offset[0][11]_i_4_n_0 ),
        .I5(p_1_in65_in),
        .O(\pi_rst_stg1_cal_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \pi_rst_stg1_cal_r[2]_i_1 
       (.I0(\pi_rst_stg1_cal_r[2]_i_2_n_0 ),
        .I1(p_0_in24_in),
        .I2(fine_adjust_reg_n_0),
        .I3(rstdiv0_sync_r1_reg_rep__23),
        .O(\pi_rst_stg1_cal_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF2F22)) 
    \pi_rst_stg1_cal_r[2]_i_2 
       (.I0(p_2_in81_in),
        .I1(pi_dqs_found_all_bank[2]),
        .I2(dqs_found_start_r),
        .I3(pi_dqs_found_start_reg),
        .I4(\rd_byte_data_offset[0][17]_i_4_n_0 ),
        .I5(p_1_in60_in),
        .O(\pi_rst_stg1_cal_r[2]_i_2_n_0 ));
  FDRE \pi_rst_stg1_cal_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r[0]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r[1]_i_1_n_0 ),
        .Q(p_1_in65_in),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r[2]_i_1_n_0 ),
        .Q(p_1_in60_in),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal[0]_i_1_n_0 ),
        .Q(pi_rst_stg1_cal[0]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \pi_rst_stg1_cal_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal[1]_i_1_n_0 ),
        .Q(pi_rst_stg1_cal[1]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \pi_rst_stg1_cal_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal[2]_i_1_n_0 ),
        .Q(pi_rst_stg1_cal[2]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE rank_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_rank_done),
        .Q(rank_done_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'h22202222)) 
    rank_done_r_i_1
       (.I0(rank_done_r0),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(rd_data_offset_cal_done),
        .O(rank_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h7F00000000000000)) 
    rank_done_r_i_2
       (.I0(pi_dqs_found_all_bank_r[0]),
        .I1(pi_dqs_found_all_bank_r[2]),
        .I2(p_2_in82_in),
        .I3(pi_dqs_found_all_bank[2]),
        .I4(pi_dqs_found_all_bank[0]),
        .I5(pi_dqs_found_all_bank[1]),
        .O(rank_done_r0));
  FDRE rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rank_done_r_i_1_n_0),
        .Q(pi_dqs_found_rank_done),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1 
       (.I0(rd_data_offset_cal_done),
        .I1(init_dqsfound_done_r1_reg_n_0),
        .O(p_24_out));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__23),
        .I1(rd_data_offset_cal_done),
        .I2(init_dqsfound_done_r1_reg_n_0),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][3] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][4] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg_n_0_[0][5] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .Q(rd_data_offset_ranks_0[0]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .Q(rd_data_offset_ranks_0[1]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .Q(rd_data_offset_ranks_0[2]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .Q(Q),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .Q(rd_data_offset_ranks_0[4]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .Q(rd_data_offset_ranks_0[5]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1 
       (.I0(p_0_in[4]),
        .I1(p_0_in[0]),
        .I2(p_0_in[2]),
        .I3(p_0_in[1]),
        .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1 
       (.I0(p_0_in[5]),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .I4(p_0_in[0]),
        .I5(p_0_in[4]),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1 
       (.I0(p_0_in[0]),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1 
       (.I0(p_0_in[1]),
        .I1(p_0_in[0]),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1 
       (.I0(p_0_in[2]),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .I1(p_0_in[0]),
        .I2(p_0_in[1]),
        .I3(p_0_in[2]),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1_n_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][10] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][11] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][6] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][7] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][8] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg_n_0_[0][9] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10] 
       (.C(CLK),
        .CE(p_24_out),
        .D(p_0_in[4]),
        .Q(rd_data_offset_ranks_1[4]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11] 
       (.C(CLK),
        .CE(p_24_out),
        .D(p_0_in[5]),
        .Q(rd_data_offset_ranks_1[5]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6] 
       (.C(CLK),
        .CE(p_24_out),
        .D(p_0_in[0]),
        .Q(rd_data_offset_ranks_1[0]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7] 
       (.C(CLK),
        .CE(p_24_out),
        .D(p_0_in[1]),
        .Q(rd_data_offset_ranks_1[1]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8] 
       (.C(CLK),
        .CE(p_24_out),
        .D(p_0_in[2]),
        .Q(rd_data_offset_ranks_1[2]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .Q(\calib_data_offset_1_reg[3] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I4(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I3(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][12] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][13] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][13] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][14] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][15] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][15] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][16] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] 
       (.C(CLK),
        .CE(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg_n_0_[0][17] ),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][12] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .Q(rd_data_offset_ranks_2[0]),
        .R(rstdiv0_sync_r1_reg_rep__11));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][13] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .Q(rd_data_offset_ranks_2[1]),
        .R(rstdiv0_sync_r1_reg_rep__11));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][14] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .Q(rd_data_offset_ranks_2[2]),
        .R(rstdiv0_sync_r1_reg_rep__11));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .Q(\calib_data_offset_2_reg[3] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][16] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .Q(rd_data_offset_ranks_2[4]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][17] 
       (.C(CLK),
        .CE(p_24_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .Q(rd_data_offset_ranks_2[5]),
        .R(rstdiv0_sync_r1_reg_rep__12));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rd_byte_data_offset[0][10]_i_1 
       (.I0(p_0_in[4]),
        .I1(p_0_in[0]),
        .I2(p_0_in[1]),
        .I3(p_0_in[2]),
        .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .O(p_1_in__0[4]));
  LUT6 #(
    .INIT(64'hCCCECCCECCCFCCCE)) 
    \rd_byte_data_offset[0][11]_i_1 
       (.I0(\rd_byte_data_offset[0][11]_i_4_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(rank_done_r1),
        .I5(rd_data_offset_cal_done),
        .O(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \rd_byte_data_offset[0][11]_i_2 
       (.I0(fine_adj_state_r187_out),
        .I1(\rd_byte_data_offset[0][5]_i_6_n_0 ),
        .I2(\rd_byte_data_offset[0][5]_i_7_n_0 ),
        .I3(dqs_found_start_r),
        .I4(pi_dqs_found_all_bank[1]),
        .I5(\rd_byte_data_offset[0][11]_i_4_n_0 ),
        .O(\rd_byte_data_offset[0][11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rd_byte_data_offset[0][11]_i_3 
       (.I0(p_0_in[5]),
        .I1(p_0_in[0]),
        .I2(p_0_in[1]),
        .I3(p_0_in[4]),
        .I4(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .I5(p_0_in[2]),
        .O(p_1_in__0[5]));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \rd_byte_data_offset[0][11]_i_4 
       (.I0(p_0_in[4]),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .I4(p_0_in[5]),
        .O(\rd_byte_data_offset[0][11]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_byte_data_offset[0][13]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(\rd_byte_data_offset[0][13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \rd_byte_data_offset[0][14]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(p_1_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rd_byte_data_offset[0][15]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(p_1_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rd_byte_data_offset[0][16]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I4(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .O(p_1_in__1[4]));
  LUT6 #(
    .INIT(64'hCCCECCCECCCFCCCE)) 
    \rd_byte_data_offset[0][17]_i_1 
       (.I0(\rd_byte_data_offset[0][17]_i_4_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(rank_done_r1),
        .I5(rd_data_offset_cal_done),
        .O(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \rd_byte_data_offset[0][17]_i_2 
       (.I0(fine_adj_state_r187_out),
        .I1(\rd_byte_data_offset[0][5]_i_6_n_0 ),
        .I2(\rd_byte_data_offset[0][5]_i_7_n_0 ),
        .I3(dqs_found_start_r),
        .I4(pi_dqs_found_all_bank[2]),
        .I5(\rd_byte_data_offset[0][17]_i_4_n_0 ),
        .O(\rd_byte_data_offset[0][17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rd_byte_data_offset[0][17]_i_3 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .I4(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .O(p_1_in__1[5]));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \rd_byte_data_offset[0][17]_i_4 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I3(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .O(\rd_byte_data_offset[0][17]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_byte_data_offset[0][1]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(\rd_byte_data_offset[0][1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \rd_byte_data_offset[0][2]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(p_1_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rd_byte_data_offset[0][3]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(p_1_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rd_byte_data_offset[0][4]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .O(p_1_in[4]));
  LUT6 #(
    .INIT(64'hCCCECCCECCCFCCCE)) 
    \rd_byte_data_offset[0][5]_i_1 
       (.I0(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(rank_done_r1),
        .I5(rd_data_offset_cal_done),
        .O(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \rd_byte_data_offset[0][5]_i_2 
       (.I0(fine_adj_state_r187_out),
        .I1(\rd_byte_data_offset[0][5]_i_6_n_0 ),
        .I2(\rd_byte_data_offset[0][5]_i_7_n_0 ),
        .I3(dqs_found_start_r),
        .I4(pi_dqs_found_all_bank[0]),
        .I5(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .O(\rd_byte_data_offset[0][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rd_byte_data_offset[0][5]_i_3 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .I4(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \rd_byte_data_offset[0][5]_i_4 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .O(\rd_byte_data_offset[0][5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT5 #(
    .INIT(32'h00000008)) 
    \rd_byte_data_offset[0][5]_i_5 
       (.I0(detect_rd_cnt_reg__0[0]),
        .I1(detect_pi_found_dqs),
        .I2(detect_rd_cnt_reg__0[3]),
        .I3(detect_rd_cnt_reg__0[2]),
        .I4(detect_rd_cnt_reg__0[1]),
        .O(fine_adj_state_r187_out));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'h000D)) 
    \rd_byte_data_offset[0][5]_i_6 
       (.I0(rank_done_r1),
        .I1(rd_data_offset_cal_done),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rd_byte_data_offset[0][5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \rd_byte_data_offset[0][5]_i_7 
       (.I0(fine_adjust_reg_n_0),
        .I1(rd_data_offset_cal_done),
        .O(\rd_byte_data_offset[0][5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_byte_data_offset[0][7]_i_1 
       (.I0(p_0_in[0]),
        .I1(p_0_in[1]),
        .O(\rd_byte_data_offset[0][7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \rd_byte_data_offset[0][8]_i_1 
       (.I0(p_0_in[2]),
        .I1(p_0_in[1]),
        .I2(p_0_in[0]),
        .O(p_1_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rd_byte_data_offset[0][9]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .I1(p_0_in[2]),
        .I2(p_0_in[0]),
        .I3(p_0_in[1]),
        .O(p_1_in__0[3]));
  FDSE \rd_byte_data_offset_reg[0][0] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][5]_i_2_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .S(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][10] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in__0[4]),
        .Q(p_0_in[4]),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][11] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in__0[5]),
        .Q(p_0_in[5]),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][12] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .S(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][13] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(\rd_byte_data_offset[0][13]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .S(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][14] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__1[2]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][15] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__1[3]),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][16] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__1[4]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][17] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__1[5]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][1] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][5]_i_2_n_0 ),
        .D(\rd_byte_data_offset[0][1]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .S(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][2] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][5]_i_2_n_0 ),
        .D(p_1_in[2]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][3] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][5]_i_2_n_0 ),
        .D(p_1_in[3]),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][4] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][5]_i_2_n_0 ),
        .D(p_1_in[4]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][5] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][5]_i_2_n_0 ),
        .D(p_1_in[5]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][6] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0 ),
        .Q(p_0_in[0]),
        .S(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][7] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(\rd_byte_data_offset[0][7]_i_1_n_0 ),
        .Q(p_0_in[1]),
        .S(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][8] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in__0[2]),
        .Q(p_0_in[2]),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][9] 
       (.C(CLK),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in__0[3]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \rnk_cnt_r[0]_i_1 
       (.I0(rd_data_offset_cal_done),
        .I1(pi_dqs_found_rank_done),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\rnk_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rnk_cnt_r[1]_i_1 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(pi_dqs_found_rank_done),
        .I2(rd_data_offset_cal_done),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rnk_cnt_r[1]_i_1_n_0 ));
  FDRE \rnk_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[0]_i_1_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  FDRE \rnk_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[1]_i_1_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__12));
  LUT6 #(
    .INIT(64'hAFCCAFFFA0CCA000)) 
    rst_dqs_find_i_1
       (.I0(rst_dqs_find_i_2_n_0),
        .I1(rst_dqs_find_i_3_n_0),
        .I2(rst_dqs_find_i_4_n_0),
        .I3(fine_adj_state_r[1]),
        .I4(rst_dqs_find_i_5_n_0),
        .I5(rst_dqs_find_reg_n_0),
        .O(rst_dqs_find_i_1_n_0));
  LUT5 #(
    .INIT(32'hECEC00EC)) 
    rst_dqs_find_i_2
       (.I0(rst_dqs_find_i_6_n_0),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[0]),
        .I4(prech_done),
        .O(rst_dqs_find_i_2_n_0));
  LUT5 #(
    .INIT(32'h0000FFEA)) 
    rst_dqs_find_i_3
       (.I0(init_dqsfound_done_r5),
        .I1(fine_adj_state_r[3]),
        .I2(rst_dqs_find_i_6_n_0),
        .I3(fine_adj_state_r[2]),
        .I4(fine_adj_state_r[0]),
        .O(rst_dqs_find_i_3_n_0));
  LUT6 #(
    .INIT(64'hBB33000388000000)) 
    rst_dqs_find_i_4
       (.I0(prech_done),
        .I1(fine_adj_state_r[0]),
        .I2(dqs_found_done_r_i_4_n_0),
        .I3(fine_adj_state_r[2]),
        .I4(fine_adj_state_r[3]),
        .I5(rst_dqs_find_i_7_n_0),
        .O(rst_dqs_find_i_4_n_0));
  LUT5 #(
    .INIT(32'h000B0008)) 
    rst_dqs_find_i_5
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(init_dqsfound_done_r5),
        .O(rst_dqs_find_i_5_n_0));
  LUT6 #(
    .INIT(64'hEAAAFFFF2AAA0000)) 
    rst_dqs_find_i_6
       (.I0(\first_fail_taps[5]_i_7_n_0 ),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(pi_dqs_found_all_bank[2]),
        .I4(detect_pi_found_dqs),
        .I5(fine_adj_state_r3),
        .O(rst_dqs_find_i_6_n_0));
  LUT5 #(
    .INIT(32'hFFFF0080)) 
    rst_dqs_find_i_7
       (.I0(\dec_cnt[5]_i_9_n_0 ),
        .I1(\first_fail_taps[5]_i_7_n_0 ),
        .I2(fine_adj_state_r149_out),
        .I3(fine_adj_state_r146_out),
        .I4(rst_dqs_find_i_8_n_0),
        .O(rst_dqs_find_i_7_n_0));
  LUT4 #(
    .INIT(16'hEAFF)) 
    rst_dqs_find_i_8
       (.I0(fine_adj_state_r[2]),
        .I1(\dec_cnt[5]_i_7_n_0 ),
        .I2(fine_adj_state_r3),
        .I3(fine_adj_state_r[3]),
        .O(rst_dqs_find_i_8_n_0));
  FDRE rst_dqs_find_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_dqs_find_reg_n_0),
        .Q(rst_dqs_find_r1),
        .R(1'b0));
  FDRE rst_dqs_find_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_dqs_find_r1),
        .Q(rst_dqs_find_r2),
        .R(1'b0));
  FDRE rst_dqs_find_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_dqs_find_i_1_n_0),
        .Q(rst_dqs_find_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__12));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT5 #(
    .INIT(32'h51111111)) 
    \stable_pass_cnt[0]_i_1 
       (.I0(stable_pass_cnt_reg__0[0]),
        .I1(detect_pi_found_dqs),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(pi_dqs_found_all_bank[0]),
        .I4(pi_dqs_found_all_bank[1]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h6606060606060606)) 
    \stable_pass_cnt[1]_i_1 
       (.I0(stable_pass_cnt_reg__0[1]),
        .I1(stable_pass_cnt_reg__0[0]),
        .I2(detect_pi_found_dqs),
        .I3(pi_dqs_found_all_bank[2]),
        .I4(pi_dqs_found_all_bank[0]),
        .I5(pi_dqs_found_all_bank[1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h0078)) 
    \stable_pass_cnt[2]_i_1 
       (.I0(stable_pass_cnt_reg__0[0]),
        .I1(stable_pass_cnt_reg__0[1]),
        .I2(stable_pass_cnt_reg__0[2]),
        .I3(fine_adj_state_r149_out),
        .O(p_0_in__0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT5 #(
    .INIT(32'h00007F80)) 
    \stable_pass_cnt[3]_i_1 
       (.I0(stable_pass_cnt_reg__0[2]),
        .I1(stable_pass_cnt_reg__0[1]),
        .I2(stable_pass_cnt_reg__0[0]),
        .I3(stable_pass_cnt_reg__0[3]),
        .I4(fine_adj_state_r149_out),
        .O(p_0_in__0__0[3]));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \stable_pass_cnt[4]_i_1 
       (.I0(stable_pass_cnt_reg__0[3]),
        .I1(stable_pass_cnt_reg__0[1]),
        .I2(stable_pass_cnt_reg__0[2]),
        .I3(stable_pass_cnt_reg__0[0]),
        .I4(stable_pass_cnt_reg__0[4]),
        .I5(fine_adj_state_r149_out),
        .O(p_0_in__0__0[4]));
  LUT5 #(
    .INIT(32'h00200000)) 
    \stable_pass_cnt[5]_i_1 
       (.I0(detect_pi_found_dqs),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[0]),
        .I4(fine_adj_state_r[1]),
        .O(\stable_pass_cnt[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h00D2)) 
    \stable_pass_cnt[5]_i_2 
       (.I0(stable_pass_cnt_reg__0[0]),
        .I1(\stable_pass_cnt[5]_i_3_n_0 ),
        .I2(stable_pass_cnt_reg__0[5]),
        .I3(fine_adj_state_r149_out),
        .O(p_0_in__0__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \stable_pass_cnt[5]_i_3 
       (.I0(stable_pass_cnt_reg__0[4]),
        .I1(stable_pass_cnt_reg__0[3]),
        .I2(stable_pass_cnt_reg__0[1]),
        .I3(stable_pass_cnt_reg__0[2]),
        .O(\stable_pass_cnt[5]_i_3_n_0 ));
  FDRE \stable_pass_cnt_reg[0] 
       (.C(CLK),
        .CE(\stable_pass_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0__0[0]),
        .Q(stable_pass_cnt_reg__0[0]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \stable_pass_cnt_reg[1] 
       (.C(CLK),
        .CE(\stable_pass_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0__0[1]),
        .Q(stable_pass_cnt_reg__0[1]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \stable_pass_cnt_reg[2] 
       (.C(CLK),
        .CE(\stable_pass_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0__0[2]),
        .Q(stable_pass_cnt_reg__0[2]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \stable_pass_cnt_reg[3] 
       (.C(CLK),
        .CE(\stable_pass_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0__0[3]),
        .Q(stable_pass_cnt_reg__0[3]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \stable_pass_cnt_reg[4] 
       (.C(CLK),
        .CE(\stable_pass_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0__0[4]),
        .Q(stable_pass_cnt_reg__0[4]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \stable_pass_cnt_reg[5] 
       (.C(CLK),
        .CE(\stable_pass_cnt[5]_i_1_n_0 ),
        .D(p_0_in__0__0[5]),
        .Q(stable_pass_cnt_reg__0[5]),
        .R(rstdiv0_sync_r1_reg_rep__13));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_init" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_init
   (init_complete_r_timing,
    \read_fifo.tail_r_reg[1] ,
    wrlvl_done_r1,
    complex_row1_rd_done_reg_0,
    prech_pending_r_reg_0,
    pi_calib_done,
    wl_sm_start,
    wrcal_sanity_chk,
    detect_pi_found_dqs,
    calib_complete,
    \wr_ptr_reg[2] ,
    pi_dqs_found_done_r1,
    \my_empty_reg[7] ,
    wrcal_rd_wait,
    \one_rank.stg1_wr_done_reg_0 ,
    rdlvl_stg1_start_r_reg,
    prbs_last_byte_done_r,
    prech_done,
    phy_ctl_wr_i1_reg,
    mem_init_done_r,
    stg1_wr_done,
    complex_row0_rd_done,
    \back_to_back_reads_4_1.num_reads_reg[1]_0 ,
    wr_en,
    E,
    wr_en_0,
    \wr_ptr_reg[2]_0 ,
    wr_en_1,
    \wr_ptr_reg[2]_1 ,
    ddr3_lm_done_r,
    first_rdlvl_pat_r,
    first_wrcal_pat_r,
    \cnt_shift_r_reg[3] ,
    phy_data_wr_en,
    phy_cmd_wr_en,
    mux_reset_n,
    \data_offset_1_i1_reg[5] ,
    \data_offset_2_i1_reg[5] ,
    \wr_ptr_timing_reg[0] ,
    \wr_ptr_timing_reg[0]_0 ,
    \phy_ctl_wd_i1_reg[24] ,
    phy_dout,
    \my_empty_reg[7]_0 ,
    mux_wrdata,
    D7,
    D6,
    D5,
    D4,
    D3,
    D2,
    D1,
    D0,
    \wr_ptr_timing_reg[0]_1 ,
    \wr_ptr_timing_reg[0]_2 ,
    \wr_ptr_timing_reg[0]_3 ,
    \wr_ptr_timing_reg[0]_4 ,
    \wr_ptr_timing_reg[0]_5 ,
    D8,
    \wr_ptr_timing_reg[0]_6 ,
    \wr_ptr_timing_reg[0]_7 ,
    \wr_ptr_timing_reg[0]_8 ,
    \wr_ptr_timing_reg[0]_9 ,
    \wr_ptr_timing_reg[0]_10 ,
    \wr_ptr_timing_reg[0]_11 ,
    \wr_ptr_timing_reg[0]_12 ,
    \wr_ptr_timing_reg[0]_13 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \my_empty_reg[7]_15 ,
    \my_empty_reg[7]_16 ,
    \my_empty_reg[7]_17 ,
    \my_empty_reg[7]_18 ,
    \my_empty_reg[7]_19 ,
    \my_empty_reg[7]_20 ,
    \my_empty_reg[7]_21 ,
    \my_empty_reg[7]_22 ,
    \my_empty_reg[7]_23 ,
    \my_empty_reg[7]_24 ,
    \my_empty_reg[7]_25 ,
    \my_empty_reg[7]_26 ,
    \my_empty_reg[7]_27 ,
    \my_empty_reg[7]_28 ,
    \my_empty_reg[7]_29 ,
    \my_empty_reg[7]_30 ,
    \my_empty_reg[7]_31 ,
    \my_empty_reg[7]_32 ,
    \entry_cnt_reg[3] ,
    \entry_cnt_reg[3]_0 ,
    \my_empty_reg[7]_33 ,
    \my_empty_reg[7]_34 ,
    \my_empty_reg[7]_35 ,
    \my_empty_reg[7]_36 ,
    \my_empty_reg[7]_37 ,
    \my_empty_reg[7]_38 ,
    \my_empty_reg[7]_39 ,
    \my_empty_reg[7]_40 ,
    \my_empty_reg[7]_41 ,
    \my_empty_reg[7]_42 ,
    \my_empty_reg[7]_43 ,
    \my_empty_reg[7]_44 ,
    \my_empty_reg[7]_45 ,
    \my_empty_reg[7]_46 ,
    \my_empty_reg[7]_47 ,
    \my_empty_reg[7]_48 ,
    \my_empty_reg[7]_49 ,
    \my_empty_reg[7]_50 ,
    \my_empty_reg[7]_51 ,
    \my_empty_reg[7]_52 ,
    \my_empty_reg[7]_53 ,
    \my_empty_reg[7]_54 ,
    \my_empty_reg[7]_55 ,
    \my_empty_reg[7]_56 ,
    \gen_byte_sel_div2.calib_in_common_reg ,
    cal2_done_r_reg,
    \my_empty_reg[6] ,
    \my_empty_reg[6]_0 ,
    \my_empty_reg[6]_1 ,
    \my_empty_reg[6]_2 ,
    wrlvl_final_if_rst,
    wr_level_start_r_reg,
    wrcal_start_reg_0,
    \pi_dqs_found_any_bank_reg[0] ,
    mpr_rdlvl_start_r_reg,
    write_calib,
    read_calib,
    A_rst_primitives_reg,
    rstdiv0_sync_r1_reg_rep__4,
    CLK,
    wr_level_done_reg,
    wrlvl_rank_done,
    rdlvl_stg1_done_reg,
    prech_req,
    wrcal_resume_w,
    rdlvl_stg1_done_reg_0,
    rdlvl_last_byte_done,
    rstdiv0_sync_r1_reg_rep__3,
    rstdiv0_sync_r1_reg_rep__18,
    dqs_found_done_r_reg,
    init_complete_r_timing_reg_0,
    init_calib_complete_reg_rep__14,
    rstdiv0_sync_r1_reg_rep__22,
    phy_ctl_ready,
    dqs_found_prech_req,
    rdlvl_stg1_done_reg_1,
    wrcal_done_reg,
    \one_rank.stg1_wr_done_reg_1 ,
    wrlvl_byte_redo_reg,
    wrcal_sanity_chk_done,
    rdlvl_stg1_done_reg_2,
    rdlvl_stg1_done_reg_3,
    wrlvl_byte_redo,
    \my_empty_reg[3] ,
    \my_empty_reg[5] ,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[5]_0 ,
    \my_empty_reg[3]_1 ,
    \my_empty_reg[5]_1 ,
    po_ck_addr_cmd_delay_done,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ,
    init_dqsfound_done_r2_reg,
    \rd_byte_data_offset_reg[0][15] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ,
    \rd_byte_data_offset_reg[0][9] ,
    Q,
    \rd_byte_data_offset_reg[0][3] ,
    complex_row0_rd_done1,
    rdlvl_stg1_done_reg_4,
    wrcal_prech_req,
    rdlvl_prech_req,
    rstdiv0_sync_r1_reg_rep__22_0,
    wrcal_sanity_chk_done_reg,
    pi_dqs_found_rank_done,
    rdlvl_stg1_done_reg_5,
    wrcal_done_reg_0,
    rdlvl_stg1_rank_done,
    dqs_found_done_r_reg_0,
    rd_active_r,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[2] ,
    init_calib_complete_reg_rep__15,
    \cmd_pipe_plus.mc_data_offset_2_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    mc_cas_n,
    mc_ras_n,
    mc_odt,
    mc_cke,
    \cmd_pipe_plus.mc_we_n_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_reg[0] ,
    mc_cmd,
    \cmd_pipe_plus.mc_address_reg[40] ,
    init_calib_complete_reg_rep__16,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \write_buffer.wr_buf_out_data_reg[511] ,
    init_calib_complete_reg_rep__17,
    init_calib_complete_reg_rep__18,
    init_calib_complete_reg_rep__19,
    init_calib_complete_reg_rep__20,
    init_calib_complete_reg_rep__21,
    init_calib_complete_reg_rep__22,
    init_calib_complete_reg_rep__23,
    init_calib_complete_reg_rep__24,
    init_calib_complete_reg_rep__25,
    init_calib_complete_reg_rep__26,
    init_calib_complete_reg_rep__27,
    init_calib_complete_reg_rep__0,
    \my_empty_reg[1] ,
    \rd_ptr_reg_rep[3] ,
    init_calib_complete_reg_rep__1,
    \my_empty_reg[1]_0 ,
    \rd_ptr_reg_rep[3]_0 ,
    init_calib_complete_reg_rep__2,
    \my_empty_reg[1]_1 ,
    \rd_ptr_reg_rep[3]_1 ,
    init_calib_complete_reg_rep__3,
    \my_empty_reg[1]_2 ,
    mem_out,
    init_calib_complete_reg_rep__4,
    \my_empty_reg[1]_3 ,
    \rd_ptr_reg_rep[3]_2 ,
    init_calib_complete_reg_rep__5,
    init_calib_complete_reg_rep__6,
    \my_empty_reg[1]_4 ,
    \rd_ptr_reg_rep[3]_3 ,
    init_calib_complete_reg_rep__7,
    init_calib_complete_reg_rep__8,
    \my_empty_reg[1]_5 ,
    \rd_ptr_reg_rep[3]_4 ,
    init_calib_complete_reg_rep__9,
    B_of_data_full,
    \my_full_reg[4] ,
    C_of_data_full,
    \my_full_reg[4]_0 ,
    init_calib_complete_reg_rep__10,
    \my_empty_reg[1]_6 ,
    \rd_ptr_reg_rep[3]_5 ,
    init_calib_complete_reg_rep__11,
    \my_empty_reg[1]_7 ,
    \rd_ptr_reg_rep[3]_6 ,
    init_calib_complete_reg_rep__12,
    \my_empty_reg[1]_8 ,
    \rd_ptr_reg_rep[3]_7 ,
    init_calib_complete_reg_rep__13,
    tempmon_sel_pi_incdec,
    wrcal_sanity_chk_r,
    init_calib_complete_reg_rep,
    init_calib_complete_reg_rep__28,
    \my_empty_reg[1]_9 ,
    rstdiv0_sync_r1_reg_rep__21,
    done_dqs_tap_inc,
    pi_dqs_found_done_r1_reg_0,
    pi_dqs_found_done_r1_reg_1,
    pi_dqs_found_done_r1_reg_2,
    pi_dqs_found_done_r1_reg_3,
    pi_dqs_found_done_r1_reg_4,
    pi_dqs_found_done_r1_reg_5,
    pi_dqs_found_done_r1_reg_6,
    pi_dqs_found_done_r1_reg_7,
    pi_dqs_found_done_r1_reg_8,
    pi_dqs_found_done_r1_reg_9,
    pi_dqs_found_done_r1_reg_10,
    pi_dqs_found_done_r1_reg_11,
    pi_dqs_found_done_r1_reg_12,
    pi_dqs_found_done_r1_reg_13,
    pi_dqs_found_done_r1_reg_14,
    rdlvl_stg1_done_reg_6,
    D,
    rdlvl_stg1_done_reg_7,
    rstdiv0_sync_r1_reg_rep,
    rstdiv0_sync_r1);
  output init_complete_r_timing;
  output \read_fifo.tail_r_reg[1] ;
  output wrlvl_done_r1;
  output complex_row1_rd_done_reg_0;
  output prech_pending_r_reg_0;
  output pi_calib_done;
  output wl_sm_start;
  output wrcal_sanity_chk;
  output detect_pi_found_dqs;
  output calib_complete;
  output \wr_ptr_reg[2] ;
  output pi_dqs_found_done_r1;
  output \my_empty_reg[7] ;
  output wrcal_rd_wait;
  output \one_rank.stg1_wr_done_reg_0 ;
  output rdlvl_stg1_start_r_reg;
  output prbs_last_byte_done_r;
  output prech_done;
  output phy_ctl_wr_i1_reg;
  output mem_init_done_r;
  output stg1_wr_done;
  output complex_row0_rd_done;
  output \back_to_back_reads_4_1.num_reads_reg[1]_0 ;
  output wr_en;
  output [0:0]E;
  output wr_en_0;
  output [0:0]\wr_ptr_reg[2]_0 ;
  output wr_en_1;
  output [0:0]\wr_ptr_reg[2]_1 ;
  output ddr3_lm_done_r;
  output first_rdlvl_pat_r;
  output first_wrcal_pat_r;
  output [0:0]\cnt_shift_r_reg[3] ;
  output phy_data_wr_en;
  output phy_cmd_wr_en;
  output mux_reset_n;
  output [5:0]\data_offset_1_i1_reg[5] ;
  output [5:0]\data_offset_2_i1_reg[5] ;
  output [4:0]\wr_ptr_timing_reg[0] ;
  output [44:0]\wr_ptr_timing_reg[0]_0 ;
  output [10:0]\phy_ctl_wd_i1_reg[24] ;
  output [15:0]phy_dout;
  output [175:0]\my_empty_reg[7]_0 ;
  output [175:0]mux_wrdata;
  output [5:0]D7;
  output [5:0]D6;
  output [4:0]D5;
  output [4:0]D4;
  output [5:0]D3;
  output [5:0]D2;
  output [4:0]D1;
  output [4:0]D0;
  output [0:0]\wr_ptr_timing_reg[0]_1 ;
  output [1:0]\wr_ptr_timing_reg[0]_2 ;
  output [3:0]\wr_ptr_timing_reg[0]_3 ;
  output [3:0]\wr_ptr_timing_reg[0]_4 ;
  output [3:0]\wr_ptr_timing_reg[0]_5 ;
  output [3:0]D8;
  output [3:0]\wr_ptr_timing_reg[0]_6 ;
  output [7:0]\wr_ptr_timing_reg[0]_7 ;
  output [7:0]\wr_ptr_timing_reg[0]_8 ;
  output [3:0]\wr_ptr_timing_reg[0]_9 ;
  output [3:0]\wr_ptr_timing_reg[0]_10 ;
  output [3:0]\wr_ptr_timing_reg[0]_11 ;
  output [3:0]\wr_ptr_timing_reg[0]_12 ;
  output [0:0]\wr_ptr_timing_reg[0]_13 ;
  output [5:0]\my_empty_reg[7]_1 ;
  output [5:0]\my_empty_reg[7]_2 ;
  output [4:0]\my_empty_reg[7]_3 ;
  output [4:0]\my_empty_reg[7]_4 ;
  output [5:0]\my_empty_reg[7]_5 ;
  output [5:0]\my_empty_reg[7]_6 ;
  output [4:0]\my_empty_reg[7]_7 ;
  output [4:0]\my_empty_reg[7]_8 ;
  output [5:0]\my_empty_reg[7]_9 ;
  output [5:0]\my_empty_reg[7]_10 ;
  output [4:0]\my_empty_reg[7]_11 ;
  output [4:0]\my_empty_reg[7]_12 ;
  output [5:0]\my_empty_reg[7]_13 ;
  output [5:0]\my_empty_reg[7]_14 ;
  output [4:0]\my_empty_reg[7]_15 ;
  output [4:0]\my_empty_reg[7]_16 ;
  output [5:0]\my_empty_reg[7]_17 ;
  output [5:0]\my_empty_reg[7]_18 ;
  output [4:0]\my_empty_reg[7]_19 ;
  output [4:0]\my_empty_reg[7]_20 ;
  output [5:0]\my_empty_reg[7]_21 ;
  output [5:0]\my_empty_reg[7]_22 ;
  output [4:0]\my_empty_reg[7]_23 ;
  output [4:0]\my_empty_reg[7]_24 ;
  output [5:0]\my_empty_reg[7]_25 ;
  output [5:0]\my_empty_reg[7]_26 ;
  output [4:0]\my_empty_reg[7]_27 ;
  output [4:0]\my_empty_reg[7]_28 ;
  output [5:0]\my_empty_reg[7]_29 ;
  output [5:0]\my_empty_reg[7]_30 ;
  output [4:0]\my_empty_reg[7]_31 ;
  output [4:0]\my_empty_reg[7]_32 ;
  output \entry_cnt_reg[3] ;
  output \entry_cnt_reg[3]_0 ;
  output [5:0]\my_empty_reg[7]_33 ;
  output [5:0]\my_empty_reg[7]_34 ;
  output [4:0]\my_empty_reg[7]_35 ;
  output [4:0]\my_empty_reg[7]_36 ;
  output [5:0]\my_empty_reg[7]_37 ;
  output [5:0]\my_empty_reg[7]_38 ;
  output [4:0]\my_empty_reg[7]_39 ;
  output [4:0]\my_empty_reg[7]_40 ;
  output [5:0]\my_empty_reg[7]_41 ;
  output [5:0]\my_empty_reg[7]_42 ;
  output [4:0]\my_empty_reg[7]_43 ;
  output [4:0]\my_empty_reg[7]_44 ;
  output [5:0]\my_empty_reg[7]_45 ;
  output [5:0]\my_empty_reg[7]_46 ;
  output [4:0]\my_empty_reg[7]_47 ;
  output [4:0]\my_empty_reg[7]_48 ;
  output [5:0]\my_empty_reg[7]_49 ;
  output [5:0]\my_empty_reg[7]_50 ;
  output [4:0]\my_empty_reg[7]_51 ;
  output [4:0]\my_empty_reg[7]_52 ;
  output [5:0]\my_empty_reg[7]_53 ;
  output [5:0]\my_empty_reg[7]_54 ;
  output [4:0]\my_empty_reg[7]_55 ;
  output [4:0]\my_empty_reg[7]_56 ;
  output \gen_byte_sel_div2.calib_in_common_reg ;
  output cal2_done_r_reg;
  output [3:0]\my_empty_reg[6] ;
  output [3:0]\my_empty_reg[6]_0 ;
  output [3:0]\my_empty_reg[6]_1 ;
  output [3:0]\my_empty_reg[6]_2 ;
  output wrlvl_final_if_rst;
  output wr_level_start_r_reg;
  output wrcal_start_reg_0;
  output \pi_dqs_found_any_bank_reg[0] ;
  output mpr_rdlvl_start_r_reg;
  output write_calib;
  output read_calib;
  input A_rst_primitives_reg;
  input rstdiv0_sync_r1_reg_rep__4;
  input CLK;
  input wr_level_done_reg;
  input wrlvl_rank_done;
  input rdlvl_stg1_done_reg;
  input prech_req;
  input wrcal_resume_w;
  input rdlvl_stg1_done_reg_0;
  input rdlvl_last_byte_done;
  input rstdiv0_sync_r1_reg_rep__3;
  input rstdiv0_sync_r1_reg_rep__18;
  input dqs_found_done_r_reg;
  input init_complete_r_timing_reg_0;
  input init_calib_complete_reg_rep__14;
  input rstdiv0_sync_r1_reg_rep__22;
  input phy_ctl_ready;
  input dqs_found_prech_req;
  input rdlvl_stg1_done_reg_1;
  input wrcal_done_reg;
  input \one_rank.stg1_wr_done_reg_1 ;
  input wrlvl_byte_redo_reg;
  input wrcal_sanity_chk_done;
  input rdlvl_stg1_done_reg_2;
  input rdlvl_stg1_done_reg_3;
  input wrlvl_byte_redo;
  input \my_empty_reg[3] ;
  input \my_empty_reg[5] ;
  input \my_empty_reg[3]_0 ;
  input \my_empty_reg[5]_0 ;
  input \my_empty_reg[3]_1 ;
  input \my_empty_reg[5]_1 ;
  input po_ck_addr_cmd_delay_done;
  input [0:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ;
  input init_dqsfound_done_r2_reg;
  input [0:0]\rd_byte_data_offset_reg[0][15] ;
  input [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ;
  input [0:0]\rd_byte_data_offset_reg[0][9] ;
  input [0:0]Q;
  input [0:0]\rd_byte_data_offset_reg[0][3] ;
  input complex_row0_rd_done1;
  input rdlvl_stg1_done_reg_4;
  input wrcal_prech_req;
  input rdlvl_prech_req;
  input rstdiv0_sync_r1_reg_rep__22_0;
  input wrcal_sanity_chk_done_reg;
  input pi_dqs_found_rank_done;
  input rdlvl_stg1_done_reg_5;
  input wrcal_done_reg_0;
  input rdlvl_stg1_rank_done;
  input dqs_found_done_r_reg_0;
  input rd_active_r;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  input init_calib_complete_reg_rep__15;
  input \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  input [0:0]mc_cas_n;
  input [0:0]mc_ras_n;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  input \cmd_pipe_plus.mc_data_offset_reg[5] ;
  input \cmd_pipe_plus.mc_data_offset_reg[4] ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  input \cmd_pipe_plus.mc_data_offset_reg[2] ;
  input \cmd_pipe_plus.mc_data_offset_reg[1] ;
  input \cmd_pipe_plus.mc_data_offset_reg[0] ;
  input [1:0]mc_cmd;
  input [34:0]\cmd_pipe_plus.mc_address_reg[40] ;
  input init_calib_complete_reg_rep__16;
  input [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input [351:0]\write_buffer.wr_buf_out_data_reg[511] ;
  input init_calib_complete_reg_rep__17;
  input init_calib_complete_reg_rep__18;
  input init_calib_complete_reg_rep__19;
  input init_calib_complete_reg_rep__20;
  input init_calib_complete_reg_rep__21;
  input init_calib_complete_reg_rep__22;
  input init_calib_complete_reg_rep__23;
  input init_calib_complete_reg_rep__24;
  input init_calib_complete_reg_rep__25;
  input init_calib_complete_reg_rep__26;
  input init_calib_complete_reg_rep__27;
  input init_calib_complete_reg_rep__0;
  input \my_empty_reg[1] ;
  input [43:0]\rd_ptr_reg_rep[3] ;
  input init_calib_complete_reg_rep__1;
  input \my_empty_reg[1]_0 ;
  input [10:0]\rd_ptr_reg_rep[3]_0 ;
  input init_calib_complete_reg_rep__2;
  input \my_empty_reg[1]_1 ;
  input [44:0]\rd_ptr_reg_rep[3]_1 ;
  input init_calib_complete_reg_rep__3;
  input \my_empty_reg[1]_2 ;
  input [43:0]mem_out;
  input init_calib_complete_reg_rep__4;
  input \my_empty_reg[1]_3 ;
  input [43:0]\rd_ptr_reg_rep[3]_2 ;
  input init_calib_complete_reg_rep__5;
  input init_calib_complete_reg_rep__6;
  input \my_empty_reg[1]_4 ;
  input [43:0]\rd_ptr_reg_rep[3]_3 ;
  input init_calib_complete_reg_rep__7;
  input init_calib_complete_reg_rep__8;
  input \my_empty_reg[1]_5 ;
  input [43:0]\rd_ptr_reg_rep[3]_4 ;
  input init_calib_complete_reg_rep__9;
  input B_of_data_full;
  input \my_full_reg[4] ;
  input C_of_data_full;
  input \my_full_reg[4]_0 ;
  input init_calib_complete_reg_rep__10;
  input \my_empty_reg[1]_6 ;
  input [43:0]\rd_ptr_reg_rep[3]_5 ;
  input init_calib_complete_reg_rep__11;
  input \my_empty_reg[1]_7 ;
  input [43:0]\rd_ptr_reg_rep[3]_6 ;
  input init_calib_complete_reg_rep__12;
  input \my_empty_reg[1]_8 ;
  input [43:0]\rd_ptr_reg_rep[3]_7 ;
  input init_calib_complete_reg_rep__13;
  input tempmon_sel_pi_incdec;
  input wrcal_sanity_chk_r;
  input init_calib_complete_reg_rep;
  input [15:0]init_calib_complete_reg_rep__28;
  input \my_empty_reg[1]_9 ;
  input rstdiv0_sync_r1_reg_rep__21;
  input done_dqs_tap_inc;
  input pi_dqs_found_done_r1_reg_0;
  input pi_dqs_found_done_r1_reg_1;
  input pi_dqs_found_done_r1_reg_2;
  input pi_dqs_found_done_r1_reg_3;
  input pi_dqs_found_done_r1_reg_4;
  input pi_dqs_found_done_r1_reg_5;
  input pi_dqs_found_done_r1_reg_6;
  input pi_dqs_found_done_r1_reg_7;
  input pi_dqs_found_done_r1_reg_8;
  input pi_dqs_found_done_r1_reg_9;
  input pi_dqs_found_done_r1_reg_10;
  input pi_dqs_found_done_r1_reg_11;
  input pi_dqs_found_done_r1_reg_12;
  input pi_dqs_found_done_r1_reg_13;
  input pi_dqs_found_done_r1_reg_14;
  input [0:0]rdlvl_stg1_done_reg_6;
  input [3:0]D;
  input rdlvl_stg1_done_reg_7;
  input rstdiv0_sync_r1_reg_rep;
  input rstdiv0_sync_r1;

  wire A_rst_primitives_reg;
  wire B_of_data_full;
  wire CLK;
  wire C_of_data_full;
  wire [3:0]D;
  wire [4:0]D0;
  wire [4:0]D1;
  wire [5:0]D2;
  wire [5:0]D3;
  wire [4:0]D4;
  wire [4:0]D5;
  wire [5:0]D6;
  wire [5:0]D7;
  wire [3:0]D8;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ;
  wire [0:0]E;
  wire [0:0]Q;
  wire \back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ;
  wire \back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ;
  wire \back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ;
  wire \back_to_back_reads_4_1.num_reads_reg[1]_0 ;
  wire [2:0]bank_w;
  wire burst_addr_r6_out;
  wire burst_addr_r_i_2_n_0;
  wire burst_addr_r_i_3_n_0;
  wire burst_addr_r_i_4_n_0;
  wire burst_addr_r_i_5_n_0;
  wire burst_addr_r_i_6_n_0;
  wire burst_addr_r_i_7_n_0;
  wire burst_addr_r_reg_n_0;
  wire cal2_done_r_reg;
  wire [3:3]calib_cke;
  wire [2:0]calib_cmd;
  wire \calib_cmd[0]_i_1_n_0 ;
  wire \calib_cmd[1]_i_1_n_0 ;
  wire \calib_cmd[1]_i_2_n_0 ;
  wire \calib_cmd[1]_i_3_n_0 ;
  wire \calib_cmd[1]_i_4_n_0 ;
  wire \calib_cmd[1]_i_5_n_0 ;
  wire \calib_cmd[2]_i_1_n_0 ;
  wire calib_complete;
  wire calib_ctl_wren0;
  wire [5:0]calib_data_offset_0;
  wire \calib_data_offset_0[3]_i_1_n_0 ;
  wire \calib_data_offset_0[3]_i_2_n_0 ;
  wire \calib_data_offset_0[5]_i_1_n_0 ;
  wire [5:0]calib_data_offset_1;
  wire \calib_data_offset_1[3]_i_1_n_0 ;
  wire [5:0]calib_data_offset_2;
  wire \calib_data_offset_2[3]_i_1_n_0 ;
  wire [0:0]calib_odt;
  wire \calib_odt[0]_i_1_n_0 ;
  wire \calib_odt[0]_i_2_n_0 ;
  wire \calib_odt[0]_i_3_n_0 ;
  wire \calib_seq[0]_i_1_n_0 ;
  wire \calib_seq[1]_i_1_n_0 ;
  wire calib_wrdata_en_i_2_n_0;
  wire clear;
  wire [34:0]\cmd_pipe_plus.mc_address_reg[40] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  wire cnt_cmd_done_m7_r;
  wire cnt_cmd_done_m7_r_i_1_n_0;
  wire cnt_cmd_done_m7_r_i_2_n_0;
  wire cnt_cmd_done_r;
  wire cnt_cmd_done_r_i_1_n_0;
  wire \cnt_cmd_r[0]_i_1_n_0 ;
  wire \cnt_cmd_r[1]_i_1_n_0 ;
  wire \cnt_cmd_r[2]_i_1_n_0 ;
  wire \cnt_cmd_r[2]_i_2_n_0 ;
  wire \cnt_cmd_r[2]_i_3_n_0 ;
  wire \cnt_cmd_r[2]_i_4_n_0 ;
  wire \cnt_cmd_r[3]_i_1_n_0 ;
  wire \cnt_cmd_r[4]_i_1_n_0 ;
  wire \cnt_cmd_r[5]_i_1_n_0 ;
  wire \cnt_cmd_r[5]_i_2_n_0 ;
  wire \cnt_cmd_r[5]_i_3_n_0 ;
  wire \cnt_cmd_r[5]_i_4_n_0 ;
  wire \cnt_cmd_r[6]_i_1_n_0 ;
  wire \cnt_cmd_r[6]_i_2_n_0 ;
  wire \cnt_cmd_r[6]_i_3_n_0 ;
  wire \cnt_cmd_r[6]_i_4_n_0 ;
  wire \cnt_cmd_r[6]_i_5_n_0 ;
  wire \cnt_cmd_r_reg_n_0_[0] ;
  wire \cnt_cmd_r_reg_n_0_[1] ;
  wire \cnt_cmd_r_reg_n_0_[2] ;
  wire \cnt_cmd_r_reg_n_0_[3] ;
  wire \cnt_cmd_r_reg_n_0_[4] ;
  wire \cnt_cmd_r_reg_n_0_[5] ;
  wire \cnt_cmd_r_reg_n_0_[6] ;
  wire cnt_dllk_zqinit_done_r;
  wire cnt_dllk_zqinit_done_r_i_1_n_0;
  wire \cnt_dllk_zqinit_r[7]_i_1_n_0 ;
  wire [7:0]cnt_dllk_zqinit_r_reg__0;
  wire cnt_init_af_done_r;
  wire cnt_init_af_done_r_i_1_n_0;
  wire \cnt_init_af_r[0]_i_1_n_0 ;
  wire \cnt_init_af_r[1]_i_1_n_0 ;
  wire \cnt_init_af_r_reg_n_0_[0] ;
  wire \cnt_init_af_r_reg_n_0_[1] ;
  wire cnt_init_mr_done_r;
  wire cnt_init_mr_done_r_i_1_n_0;
  wire [1:0]cnt_init_mr_r;
  wire cnt_init_mr_r0;
  wire cnt_init_mr_r1;
  wire \cnt_init_mr_r[0]_i_1_n_0 ;
  wire \cnt_init_mr_r[0]_i_2_n_0 ;
  wire \cnt_init_mr_r[1]_i_1_n_0 ;
  wire \cnt_init_mr_r[1]_i_2_n_0 ;
  wire \cnt_init_mr_r[1]_i_3_n_0 ;
  wire [9:0]cnt_pwron_ce_r_reg__0;
  wire cnt_pwron_cke_done_r;
  wire cnt_pwron_cke_done_r_i_1_n_0;
  wire cnt_pwron_cke_done_r_i_2_n_0;
  wire cnt_pwron_cke_done_r_i_3_n_0;
  wire \cnt_pwron_r[6]_i_2_n_0 ;
  wire \cnt_pwron_r[8]_i_2_n_0 ;
  wire [8:0]cnt_pwron_r_reg__0;
  wire cnt_pwron_reset_done_r;
  wire cnt_pwron_reset_done_r_i_1_n_0;
  wire cnt_pwron_reset_done_r_i_2_n_0;
  wire [0:0]\cnt_shift_r_reg[3] ;
  wire cnt_txpr_done_r;
  wire cnt_txpr_done_r_i_1_n_0;
  wire cnt_txpr_done_r_i_2_n_0;
  wire \cnt_txpr_r[7]_i_3_n_0 ;
  wire [7:0]cnt_txpr_r_reg__0;
  wire complex_address0;
  wire \complex_address[9]_i_2_n_0 ;
  wire \complex_address[9]_i_3_n_0 ;
  wire \complex_address[9]_i_4_n_0 ;
  wire \complex_address_reg_n_0_[0] ;
  wire \complex_address_reg_n_0_[1] ;
  wire \complex_address_reg_n_0_[2] ;
  wire \complex_address_reg_n_0_[3] ;
  wire \complex_address_reg_n_0_[4] ;
  wire \complex_address_reg_n_0_[5] ;
  wire \complex_address_reg_n_0_[6] ;
  wire \complex_address_reg_n_0_[7] ;
  wire \complex_address_reg_n_0_[8] ;
  wire \complex_address_reg_n_0_[9] ;
  wire complex_byte_rd_done;
  wire complex_byte_rd_done_i_1_n_0;
  wire complex_byte_rd_done_i_2_n_0;
  wire \complex_num_reads[0]_i_1_n_0 ;
  wire \complex_num_reads[0]_i_2_n_0 ;
  wire \complex_num_reads[1]_i_1_n_0 ;
  wire \complex_num_reads[1]_i_2_n_0 ;
  wire \complex_num_reads[1]_i_3_n_0 ;
  wire \complex_num_reads[1]_i_4_n_0 ;
  wire \complex_num_reads[1]_i_5_n_0 ;
  wire \complex_num_reads[1]_i_6_n_0 ;
  wire \complex_num_reads[1]_i_7_n_0 ;
  wire \complex_num_reads[1]_i_8_n_0 ;
  wire \complex_num_reads[2]_i_1_n_0 ;
  wire \complex_num_reads[2]_i_2_n_0 ;
  wire \complex_num_reads[3]_i_1_n_0 ;
  wire \complex_num_reads[3]_i_2_n_0 ;
  wire \complex_num_reads[3]_i_3_n_0 ;
  wire \complex_num_reads[3]_i_4_n_0 ;
  wire \complex_num_reads[3]_i_5_n_0 ;
  wire \complex_num_reads[3]_i_6_n_0 ;
  wire \complex_num_reads[3]_i_7_n_0 ;
  wire \complex_num_reads[3]_i_8_n_0 ;
  wire \complex_num_reads[3]_i_9_n_0 ;
  wire \complex_num_reads_dec[3]_i_1_n_0 ;
  wire \complex_num_reads_dec[3]_i_3_n_0 ;
  wire [3:0]complex_num_reads_dec_reg__0;
  wire \complex_num_reads_reg_n_0_[0] ;
  wire \complex_num_reads_reg_n_0_[1] ;
  wire \complex_num_reads_reg_n_0_[2] ;
  wire \complex_num_reads_reg_n_0_[3] ;
  wire \complex_num_writes[0]_i_1_n_0 ;
  wire \complex_num_writes[0]_i_2_n_0 ;
  wire \complex_num_writes[0]_i_3_n_0 ;
  wire \complex_num_writes[0]_i_4_n_0 ;
  wire \complex_num_writes[0]_i_5_n_0 ;
  wire \complex_num_writes[0]_i_6_n_0 ;
  wire \complex_num_writes[0]_i_7_n_0 ;
  wire \complex_num_writes[1]_i_1_n_0 ;
  wire \complex_num_writes[1]_i_2_n_0 ;
  wire \complex_num_writes[2]_i_1_n_0 ;
  wire \complex_num_writes[2]_i_2_n_0 ;
  wire \complex_num_writes[2]_i_3_n_0 ;
  wire \complex_num_writes[2]_i_4_n_0 ;
  wire \complex_num_writes[2]_i_5_n_0 ;
  wire \complex_num_writes[3]_i_1_n_0 ;
  wire \complex_num_writes[3]_i_2_n_0 ;
  wire \complex_num_writes[3]_i_3_n_0 ;
  wire \complex_num_writes[3]_i_4_n_0 ;
  wire \complex_num_writes[4]_i_10_n_0 ;
  wire \complex_num_writes[4]_i_11_n_0 ;
  wire \complex_num_writes[4]_i_12_n_0 ;
  wire \complex_num_writes[4]_i_13_n_0 ;
  wire \complex_num_writes[4]_i_14_n_0 ;
  wire \complex_num_writes[4]_i_15_n_0 ;
  wire \complex_num_writes[4]_i_16_n_0 ;
  wire \complex_num_writes[4]_i_17_n_0 ;
  wire \complex_num_writes[4]_i_18_n_0 ;
  wire \complex_num_writes[4]_i_1_n_0 ;
  wire \complex_num_writes[4]_i_2_n_0 ;
  wire \complex_num_writes[4]_i_3_n_0 ;
  wire \complex_num_writes[4]_i_5_n_0 ;
  wire \complex_num_writes[4]_i_6_n_0 ;
  wire \complex_num_writes[4]_i_7_n_0 ;
  wire \complex_num_writes[4]_i_8_n_0 ;
  wire \complex_num_writes[4]_i_9_n_0 ;
  wire \complex_num_writes_dec[4]_i_2_n_0 ;
  wire \complex_num_writes_dec[4]_i_4_n_0 ;
  wire \complex_num_writes_dec[4]_i_5_n_0 ;
  wire [4:0]complex_num_writes_dec_reg__0;
  wire \complex_num_writes_reg[4]_i_4_n_0 ;
  wire \complex_num_writes_reg_n_0_[0] ;
  wire \complex_num_writes_reg_n_0_[1] ;
  wire \complex_num_writes_reg_n_0_[2] ;
  wire \complex_num_writes_reg_n_0_[3] ;
  wire \complex_num_writes_reg_n_0_[4] ;
  wire complex_ocal_odt_ext;
  wire complex_ocal_odt_ext_i_1_n_0;
  wire complex_ocal_odt_ext_i_2_n_0;
  wire complex_ocal_odt_ext_i_3_n_0;
  wire complex_ocal_odt_ext_i_4_n_0;
  wire complex_ocal_reset_rd_addr0;
  wire complex_ocal_reset_rd_addr_i_2_n_0;
  wire complex_ocal_reset_rd_addr_reg_n_0;
  wire complex_oclkdelay_calib_done_r1;
  wire complex_oclkdelay_calib_start_int;
  wire complex_oclkdelay_calib_start_int_i_1_n_0;
  wire complex_oclkdelay_calib_start_int_i_2_n_0;
  wire complex_oclkdelay_calib_start_r1;
  wire complex_odt_ext;
  wire complex_odt_ext_i_1_n_0;
  wire complex_odt_ext_i_2_n_0;
  wire complex_row0_rd_done;
  wire complex_row0_rd_done1;
  wire complex_row0_rd_done_i_1_n_0;
  wire complex_row0_wr_done;
  wire complex_row0_wr_done0;
  wire [2:0]complex_row1_rd_cnt;
  wire \complex_row1_rd_cnt[0]_i_1_n_0 ;
  wire \complex_row1_rd_cnt[1]_i_1_n_0 ;
  wire \complex_row1_rd_cnt[2]_i_1_n_0 ;
  wire complex_row1_rd_done;
  wire complex_row1_rd_done_i_1_n_0;
  wire complex_row1_rd_done_i_2_n_0;
  wire complex_row1_rd_done_r1;
  wire complex_row1_rd_done_reg_0;
  wire complex_row1_wr_done;
  wire complex_row1_wr_done0;
  wire [0:0]complex_row_cnt0;
  wire complex_row_cnt_ocal0;
  wire \complex_row_cnt_ocal[7]_i_2_n_0 ;
  wire \complex_row_cnt_ocal[7]_i_4_n_0 ;
  wire \complex_row_cnt_ocal[7]_i_5_n_0 ;
  wire \complex_row_cnt_ocal[7]_i_6_n_0 ;
  wire \complex_row_cnt_ocal[7]_i_7_n_0 ;
  wire \complex_row_cnt_ocal[7]_i_8_n_0 ;
  wire \complex_row_cnt_ocal[7]_i_9_n_0 ;
  wire [7:0]complex_row_cnt_ocal_reg__0;
  wire complex_sample_cnt_inc0;
  wire complex_sample_cnt_inc_i_2_n_0;
  wire complex_sample_cnt_inc_i_3_n_0;
  wire complex_sample_cnt_inc_r1;
  wire complex_sample_cnt_inc_r2;
  wire complex_sample_cnt_inc_reg_n_0;
  wire \complex_wait_cnt[3]_i_1_n_0 ;
  wire \complex_wait_cnt[3]_i_3_n_0 ;
  wire \complex_wait_cnt[3]_i_4_n_0 ;
  wire \complex_wait_cnt[3]_i_5_n_0 ;
  wire \complex_wait_cnt[3]_i_6_n_0 ;
  wire [3:0]complex_wait_cnt_reg__0;
  wire [5:0]\data_offset_1_i1_reg[5] ;
  wire [5:0]\data_offset_2_i1_reg[5] ;
  wire ddr2_pre_flag_r_i_1_n_0;
  wire ddr2_pre_flag_r_i_2_n_0;
  wire ddr2_pre_flag_r_i_3_n_0;
  wire ddr2_pre_flag_r_reg_n_0;
  wire ddr2_refresh_flag_r_i_1_n_0;
  wire ddr2_refresh_flag_r_i_2_n_0;
  wire ddr2_refresh_flag_r_reg_n_0;
  wire ddr3_lm_done_r;
  wire ddr3_lm_done_r_i_1_n_0;
  wire detect_pi_found_dqs;
  wire detect_pi_found_dqs0;
  wire detect_pi_found_dqs_i_2_n_0;
  wire detect_pi_found_dqs_i_3_n_0;
  wire done_dqs_tap_inc;
  wire [1:0]dqs_asrt_cnt;
  wire \dqs_asrt_cnt[0]_i_1_n_0 ;
  wire \dqs_asrt_cnt[1]_i_1_n_0 ;
  wire dqs_found_done_r_reg;
  wire dqs_found_done_r_reg_0;
  wire dqs_found_prech_req;
  wire \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ;
  wire \en_cnt_div4.wrlvl_odt_i_1_n_0 ;
  wire \en_cnt_div4.wrlvl_odt_i_2_n_0 ;
  wire \entry_cnt_reg[3] ;
  wire \entry_cnt_reg[3]_0 ;
  wire first_rdlvl_pat_r;
  wire first_rdlvl_pat_r_i_1_n_0;
  wire first_wrcal_pat_r;
  wire first_wrcal_pat_r_i_1_n_0;
  wire first_wrcal_pat_r_i_2_n_0;
  wire first_wrcal_pat_r_i_3_n_0;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_4_n_0 ;
  wire [1:1]\gen_rnk[0].mr1_r_reg[0]_0 ;
  wire init_calib_complete_reg_rep;
  wire init_calib_complete_reg_rep__0;
  wire init_calib_complete_reg_rep__1;
  wire init_calib_complete_reg_rep__10;
  wire init_calib_complete_reg_rep__11;
  wire init_calib_complete_reg_rep__12;
  wire init_calib_complete_reg_rep__13;
  wire init_calib_complete_reg_rep__14;
  wire init_calib_complete_reg_rep__15;
  wire init_calib_complete_reg_rep__16;
  wire init_calib_complete_reg_rep__17;
  wire init_calib_complete_reg_rep__18;
  wire init_calib_complete_reg_rep__19;
  wire init_calib_complete_reg_rep__2;
  wire init_calib_complete_reg_rep__20;
  wire init_calib_complete_reg_rep__21;
  wire init_calib_complete_reg_rep__22;
  wire init_calib_complete_reg_rep__23;
  wire init_calib_complete_reg_rep__24;
  wire init_calib_complete_reg_rep__25;
  wire init_calib_complete_reg_rep__26;
  wire init_calib_complete_reg_rep__27;
  wire [15:0]init_calib_complete_reg_rep__28;
  wire init_calib_complete_reg_rep__3;
  wire init_calib_complete_reg_rep__4;
  wire init_calib_complete_reg_rep__5;
  wire init_calib_complete_reg_rep__6;
  wire init_calib_complete_reg_rep__7;
  wire init_calib_complete_reg_rep__8;
  wire init_calib_complete_reg_rep__9;
  wire init_complete_r1;
  (* RTL_KEEP = "true" *) wire init_complete_r1_timing;
  wire init_complete_r2;
  wire init_complete_r_i_1_n_0;
  wire init_complete_r_i_2_n_0;
  wire init_complete_r_i_3_n_0;
  wire init_complete_r_reg_n_0;
  wire init_complete_r_timing_i_1_n_0;
  (* RTL_KEEP = "true" *) wire init_complete_r_timing_orig;
  wire init_complete_r_timing_reg_0;
  wire init_dqsfound_done_r2_reg;
  wire init_next_state1110_out;
  wire [6:6]init_state_r;
  wire [6:0]init_state_r1;
  wire \init_state_r[0]_i_10_n_0 ;
  wire \init_state_r[0]_i_11_n_0 ;
  wire \init_state_r[0]_i_12_n_0 ;
  wire \init_state_r[0]_i_13_n_0 ;
  wire \init_state_r[0]_i_14_n_0 ;
  wire \init_state_r[0]_i_15_n_0 ;
  wire \init_state_r[0]_i_16_n_0 ;
  wire \init_state_r[0]_i_17_n_0 ;
  wire \init_state_r[0]_i_18_n_0 ;
  wire \init_state_r[0]_i_19_n_0 ;
  wire \init_state_r[0]_i_1_n_0 ;
  wire \init_state_r[0]_i_20_n_0 ;
  wire \init_state_r[0]_i_21_n_0 ;
  wire \init_state_r[0]_i_22_n_0 ;
  wire \init_state_r[0]_i_23_n_0 ;
  wire \init_state_r[0]_i_24_n_0 ;
  wire \init_state_r[0]_i_25_n_0 ;
  wire \init_state_r[0]_i_26_n_0 ;
  wire \init_state_r[0]_i_27_n_0 ;
  wire \init_state_r[0]_i_28_n_0 ;
  wire \init_state_r[0]_i_29_n_0 ;
  wire \init_state_r[0]_i_2_n_0 ;
  wire \init_state_r[0]_i_31_n_0 ;
  wire \init_state_r[0]_i_33_n_0 ;
  wire \init_state_r[0]_i_34_n_0 ;
  wire \init_state_r[0]_i_35_n_0 ;
  wire \init_state_r[0]_i_3_n_0 ;
  wire \init_state_r[0]_i_4_n_0 ;
  wire \init_state_r[0]_i_5_n_0 ;
  wire \init_state_r[0]_i_6_n_0 ;
  wire \init_state_r[0]_i_7_n_0 ;
  wire \init_state_r[0]_i_8_n_0 ;
  wire \init_state_r[0]_i_9_n_0 ;
  wire \init_state_r[1]_i_10_n_0 ;
  wire \init_state_r[1]_i_11_n_0 ;
  wire \init_state_r[1]_i_12_n_0 ;
  wire \init_state_r[1]_i_13_n_0 ;
  wire \init_state_r[1]_i_14_n_0 ;
  wire \init_state_r[1]_i_15_n_0 ;
  wire \init_state_r[1]_i_16_n_0 ;
  wire \init_state_r[1]_i_17_n_0 ;
  wire \init_state_r[1]_i_18_n_0 ;
  wire \init_state_r[1]_i_19_n_0 ;
  wire \init_state_r[1]_i_1_n_0 ;
  wire \init_state_r[1]_i_20_n_0 ;
  wire \init_state_r[1]_i_21_n_0 ;
  wire \init_state_r[1]_i_22_n_0 ;
  wire \init_state_r[1]_i_23_n_0 ;
  wire \init_state_r[1]_i_24_n_0 ;
  wire \init_state_r[1]_i_25_n_0 ;
  wire \init_state_r[1]_i_26_n_0 ;
  wire \init_state_r[1]_i_27_n_0 ;
  wire \init_state_r[1]_i_28_n_0 ;
  wire \init_state_r[1]_i_29_n_0 ;
  wire \init_state_r[1]_i_2_n_0 ;
  wire \init_state_r[1]_i_30_n_0 ;
  wire \init_state_r[1]_i_31_n_0 ;
  wire \init_state_r[1]_i_32_n_0 ;
  wire \init_state_r[1]_i_33_n_0 ;
  wire \init_state_r[1]_i_34_n_0 ;
  wire \init_state_r[1]_i_35_n_0 ;
  wire \init_state_r[1]_i_36_n_0 ;
  wire \init_state_r[1]_i_37_n_0 ;
  wire \init_state_r[1]_i_3_n_0 ;
  wire \init_state_r[1]_i_4_n_0 ;
  wire \init_state_r[1]_i_5_n_0 ;
  wire \init_state_r[1]_i_6_n_0 ;
  wire \init_state_r[1]_i_7_n_0 ;
  wire \init_state_r[1]_i_8_n_0 ;
  wire \init_state_r[1]_i_9_n_0 ;
  wire \init_state_r[2]_i_10_n_0 ;
  wire \init_state_r[2]_i_11_n_0 ;
  wire \init_state_r[2]_i_12_n_0 ;
  wire \init_state_r[2]_i_13_n_0 ;
  wire \init_state_r[2]_i_14_n_0 ;
  wire \init_state_r[2]_i_15_n_0 ;
  wire \init_state_r[2]_i_16_n_0 ;
  wire \init_state_r[2]_i_17_n_0 ;
  wire \init_state_r[2]_i_18_n_0 ;
  wire \init_state_r[2]_i_19_n_0 ;
  wire \init_state_r[2]_i_1_n_0 ;
  wire \init_state_r[2]_i_20_n_0 ;
  wire \init_state_r[2]_i_21_n_0 ;
  wire \init_state_r[2]_i_22_n_0 ;
  wire \init_state_r[2]_i_23_n_0 ;
  wire \init_state_r[2]_i_24_n_0 ;
  wire \init_state_r[2]_i_25_n_0 ;
  wire \init_state_r[2]_i_26_n_0 ;
  wire \init_state_r[2]_i_27_n_0 ;
  wire \init_state_r[2]_i_28_n_0 ;
  wire \init_state_r[2]_i_29_n_0 ;
  wire \init_state_r[2]_i_2_n_0 ;
  wire \init_state_r[2]_i_30_n_0 ;
  wire \init_state_r[2]_i_32_n_0 ;
  wire \init_state_r[2]_i_34_n_0 ;
  wire \init_state_r[2]_i_35_n_0 ;
  wire \init_state_r[2]_i_3_n_0 ;
  wire \init_state_r[2]_i_4_n_0 ;
  wire \init_state_r[2]_i_5_n_0 ;
  wire \init_state_r[2]_i_6_n_0 ;
  wire \init_state_r[2]_i_7_n_0 ;
  wire \init_state_r[2]_i_8_n_0 ;
  wire \init_state_r[2]_i_9_n_0 ;
  wire \init_state_r[3]_i_10_n_0 ;
  wire \init_state_r[3]_i_11_n_0 ;
  wire \init_state_r[3]_i_12_n_0 ;
  wire \init_state_r[3]_i_13_n_0 ;
  wire \init_state_r[3]_i_14_n_0 ;
  wire \init_state_r[3]_i_15_n_0 ;
  wire \init_state_r[3]_i_16_n_0 ;
  wire \init_state_r[3]_i_17_n_0 ;
  wire \init_state_r[3]_i_18_n_0 ;
  wire \init_state_r[3]_i_19_n_0 ;
  wire \init_state_r[3]_i_1_n_0 ;
  wire \init_state_r[3]_i_21_n_0 ;
  wire \init_state_r[3]_i_2_n_0 ;
  wire \init_state_r[3]_i_3_n_0 ;
  wire \init_state_r[3]_i_4_n_0 ;
  wire \init_state_r[3]_i_5_n_0 ;
  wire \init_state_r[3]_i_6_n_0 ;
  wire \init_state_r[3]_i_7_n_0 ;
  wire \init_state_r[3]_i_8_n_0 ;
  wire \init_state_r[3]_i_9_n_0 ;
  wire \init_state_r[4]_i_10_n_0 ;
  wire \init_state_r[4]_i_11_n_0 ;
  wire \init_state_r[4]_i_12_n_0 ;
  wire \init_state_r[4]_i_13_n_0 ;
  wire \init_state_r[4]_i_14_n_0 ;
  wire \init_state_r[4]_i_15_n_0 ;
  wire \init_state_r[4]_i_16_n_0 ;
  wire \init_state_r[4]_i_17_n_0 ;
  wire \init_state_r[4]_i_18_n_0 ;
  wire \init_state_r[4]_i_19_n_0 ;
  wire \init_state_r[4]_i_1_n_0 ;
  wire \init_state_r[4]_i_20_n_0 ;
  wire \init_state_r[4]_i_21_n_0 ;
  wire \init_state_r[4]_i_22_n_0 ;
  wire \init_state_r[4]_i_23_n_0 ;
  wire \init_state_r[4]_i_24_n_0 ;
  wire \init_state_r[4]_i_25_n_0 ;
  wire \init_state_r[4]_i_26_n_0 ;
  wire \init_state_r[4]_i_27_n_0 ;
  wire \init_state_r[4]_i_28_n_0 ;
  wire \init_state_r[4]_i_29_n_0 ;
  wire \init_state_r[4]_i_2_n_0 ;
  wire \init_state_r[4]_i_30_n_0 ;
  wire \init_state_r[4]_i_31_n_0 ;
  wire \init_state_r[4]_i_32_n_0 ;
  wire \init_state_r[4]_i_33_n_0 ;
  wire \init_state_r[4]_i_34_n_0 ;
  wire \init_state_r[4]_i_35_n_0 ;
  wire \init_state_r[4]_i_37_n_0 ;
  wire \init_state_r[4]_i_38_n_0 ;
  wire \init_state_r[4]_i_39_n_0 ;
  wire \init_state_r[4]_i_3_n_0 ;
  wire \init_state_r[4]_i_40_n_0 ;
  wire \init_state_r[4]_i_41_n_0 ;
  wire \init_state_r[4]_i_42_n_0 ;
  wire \init_state_r[4]_i_4_n_0 ;
  wire \init_state_r[4]_i_5_n_0 ;
  wire \init_state_r[4]_i_6_n_0 ;
  wire \init_state_r[4]_i_7_n_0 ;
  wire \init_state_r[4]_i_8_n_0 ;
  wire \init_state_r[4]_i_9_n_0 ;
  wire \init_state_r[5]_i_10_n_0 ;
  wire \init_state_r[5]_i_11_n_0 ;
  wire \init_state_r[5]_i_12_n_0 ;
  wire \init_state_r[5]_i_13_n_0 ;
  wire \init_state_r[5]_i_14_n_0 ;
  wire \init_state_r[5]_i_15_n_0 ;
  wire \init_state_r[5]_i_16_n_0 ;
  wire \init_state_r[5]_i_17_n_0 ;
  wire \init_state_r[5]_i_18_n_0 ;
  wire \init_state_r[5]_i_19_n_0 ;
  wire \init_state_r[5]_i_1_n_0 ;
  wire \init_state_r[5]_i_20_n_0 ;
  wire \init_state_r[5]_i_21_n_0 ;
  wire \init_state_r[5]_i_22_n_0 ;
  wire \init_state_r[5]_i_23_n_0 ;
  wire \init_state_r[5]_i_24_n_0 ;
  wire \init_state_r[5]_i_25_n_0 ;
  wire \init_state_r[5]_i_26_n_0 ;
  wire \init_state_r[5]_i_27_n_0 ;
  wire \init_state_r[5]_i_28_n_0 ;
  wire \init_state_r[5]_i_29_n_0 ;
  wire \init_state_r[5]_i_2_n_0 ;
  wire \init_state_r[5]_i_30_n_0 ;
  wire \init_state_r[5]_i_31_n_0 ;
  wire \init_state_r[5]_i_32_n_0 ;
  wire \init_state_r[5]_i_33_n_0 ;
  wire \init_state_r[5]_i_34_n_0 ;
  wire \init_state_r[5]_i_36_n_0 ;
  wire \init_state_r[5]_i_37_n_0 ;
  wire \init_state_r[5]_i_38_n_0 ;
  wire \init_state_r[5]_i_3_n_0 ;
  wire \init_state_r[5]_i_4_n_0 ;
  wire \init_state_r[5]_i_5_n_0 ;
  wire \init_state_r[5]_i_6_n_0 ;
  wire \init_state_r[5]_i_7_n_0 ;
  wire \init_state_r[5]_i_8_n_0 ;
  wire \init_state_r[5]_i_9_n_0 ;
  wire \init_state_r[6]_i_10_n_0 ;
  wire \init_state_r[6]_i_11_n_0 ;
  wire \init_state_r[6]_i_12_n_0 ;
  wire \init_state_r[6]_i_13_n_0 ;
  wire \init_state_r[6]_i_14_n_0 ;
  wire \init_state_r[6]_i_15_n_0 ;
  wire \init_state_r[6]_i_16_n_0 ;
  wire \init_state_r[6]_i_17_n_0 ;
  wire \init_state_r[6]_i_18_n_0 ;
  wire \init_state_r[6]_i_19_n_0 ;
  wire \init_state_r[6]_i_1_n_0 ;
  wire \init_state_r[6]_i_20_n_0 ;
  wire \init_state_r[6]_i_21_n_0 ;
  wire \init_state_r[6]_i_22_n_0 ;
  wire \init_state_r[6]_i_23_n_0 ;
  wire \init_state_r[6]_i_24_n_0 ;
  wire \init_state_r[6]_i_25_n_0 ;
  wire \init_state_r[6]_i_26_n_0 ;
  wire \init_state_r[6]_i_27_n_0 ;
  wire \init_state_r[6]_i_28_n_0 ;
  wire \init_state_r[6]_i_29_n_0 ;
  wire \init_state_r[6]_i_2_n_0 ;
  wire \init_state_r[6]_i_3_n_0 ;
  wire \init_state_r[6]_i_4_n_0 ;
  wire \init_state_r[6]_i_5_n_0 ;
  wire \init_state_r[6]_i_6_n_0 ;
  wire \init_state_r[6]_i_7_n_0 ;
  wire \init_state_r[6]_i_8_n_0 ;
  wire \init_state_r[6]_i_9_n_0 ;
  wire \init_state_r_reg_n_0_[0] ;
  wire \init_state_r_reg_n_0_[1] ;
  wire \init_state_r_reg_n_0_[2] ;
  wire \init_state_r_reg_n_0_[3] ;
  wire \init_state_r_reg_n_0_[4] ;
  wire \init_state_r_reg_n_0_[5] ;
  wire [0:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_odt;
  wire [0:0]mc_ras_n;
  wire mc_wrdata_en;
  wire mem_init_done_r;
  wire mem_init_done_r_i_1_n_0;
  wire mem_init_done_r_i_2_n_0;
  wire [43:0]mem_out;
  wire mpr_rdlvl_start_i_1_n_0;
  wire mpr_rdlvl_start_i_2_n_0;
  wire mpr_rdlvl_start_r_reg;
  wire mux_reset_n;
  wire [175:0]mux_wrdata;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[1]_3 ;
  wire \my_empty_reg[1]_4 ;
  wire \my_empty_reg[1]_5 ;
  wire \my_empty_reg[1]_6 ;
  wire \my_empty_reg[1]_7 ;
  wire \my_empty_reg[1]_8 ;
  wire \my_empty_reg[1]_9 ;
  wire \my_empty_reg[3] ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[3]_1 ;
  wire \my_empty_reg[5] ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg[5]_1 ;
  wire [3:0]\my_empty_reg[6] ;
  wire [3:0]\my_empty_reg[6]_0 ;
  wire [3:0]\my_empty_reg[6]_1 ;
  wire [3:0]\my_empty_reg[6]_2 ;
  wire \my_empty_reg[7] ;
  wire [175:0]\my_empty_reg[7]_0 ;
  wire [5:0]\my_empty_reg[7]_1 ;
  wire [5:0]\my_empty_reg[7]_10 ;
  wire [4:0]\my_empty_reg[7]_11 ;
  wire [4:0]\my_empty_reg[7]_12 ;
  wire [5:0]\my_empty_reg[7]_13 ;
  wire [5:0]\my_empty_reg[7]_14 ;
  wire [4:0]\my_empty_reg[7]_15 ;
  wire [4:0]\my_empty_reg[7]_16 ;
  wire [5:0]\my_empty_reg[7]_17 ;
  wire [5:0]\my_empty_reg[7]_18 ;
  wire [4:0]\my_empty_reg[7]_19 ;
  wire [5:0]\my_empty_reg[7]_2 ;
  wire [4:0]\my_empty_reg[7]_20 ;
  wire [5:0]\my_empty_reg[7]_21 ;
  wire [5:0]\my_empty_reg[7]_22 ;
  wire [4:0]\my_empty_reg[7]_23 ;
  wire [4:0]\my_empty_reg[7]_24 ;
  wire [5:0]\my_empty_reg[7]_25 ;
  wire [5:0]\my_empty_reg[7]_26 ;
  wire [4:0]\my_empty_reg[7]_27 ;
  wire [4:0]\my_empty_reg[7]_28 ;
  wire [5:0]\my_empty_reg[7]_29 ;
  wire [4:0]\my_empty_reg[7]_3 ;
  wire [5:0]\my_empty_reg[7]_30 ;
  wire [4:0]\my_empty_reg[7]_31 ;
  wire [4:0]\my_empty_reg[7]_32 ;
  wire [5:0]\my_empty_reg[7]_33 ;
  wire [5:0]\my_empty_reg[7]_34 ;
  wire [4:0]\my_empty_reg[7]_35 ;
  wire [4:0]\my_empty_reg[7]_36 ;
  wire [5:0]\my_empty_reg[7]_37 ;
  wire [5:0]\my_empty_reg[7]_38 ;
  wire [4:0]\my_empty_reg[7]_39 ;
  wire [4:0]\my_empty_reg[7]_4 ;
  wire [4:0]\my_empty_reg[7]_40 ;
  wire [5:0]\my_empty_reg[7]_41 ;
  wire [5:0]\my_empty_reg[7]_42 ;
  wire [4:0]\my_empty_reg[7]_43 ;
  wire [4:0]\my_empty_reg[7]_44 ;
  wire [5:0]\my_empty_reg[7]_45 ;
  wire [5:0]\my_empty_reg[7]_46 ;
  wire [4:0]\my_empty_reg[7]_47 ;
  wire [4:0]\my_empty_reg[7]_48 ;
  wire [5:0]\my_empty_reg[7]_49 ;
  wire [5:0]\my_empty_reg[7]_5 ;
  wire [5:0]\my_empty_reg[7]_50 ;
  wire [4:0]\my_empty_reg[7]_51 ;
  wire [4:0]\my_empty_reg[7]_52 ;
  wire [5:0]\my_empty_reg[7]_53 ;
  wire [5:0]\my_empty_reg[7]_54 ;
  wire [4:0]\my_empty_reg[7]_55 ;
  wire [4:0]\my_empty_reg[7]_56 ;
  wire [5:0]\my_empty_reg[7]_6 ;
  wire [4:0]\my_empty_reg[7]_7 ;
  wire [4:0]\my_empty_reg[7]_8 ;
  wire [5:0]\my_empty_reg[7]_9 ;
  wire \my_full_reg[4] ;
  wire \my_full_reg[4]_0 ;
  wire [1:0]num_reads;
  wire num_refresh0;
  wire \num_refresh[3]_i_1_n_0 ;
  wire \num_refresh[3]_i_4_n_0 ;
  wire \num_refresh[3]_i_5_n_0 ;
  wire \num_refresh[3]_i_6_n_0 ;
  wire \num_refresh[3]_i_7_n_0 ;
  wire [3:0]num_refresh_reg__0;
  wire \ocal_act_wait_cnt[3]_i_1_n_0 ;
  wire \ocal_act_wait_cnt[3]_i_3_n_0 ;
  wire [3:0]ocal_act_wait_cnt_reg__0;
  wire [3:2]oclk_wr_cnt0;
  wire \oclk_wr_cnt[0]_i_1_n_0 ;
  wire \oclk_wr_cnt[1]_i_1_n_0 ;
  wire \oclk_wr_cnt[3]_i_1_n_0 ;
  wire \oclk_wr_cnt[3]_i_4_n_0 ;
  wire [3:0]oclk_wr_cnt_reg__0;
  wire \odd_cwl.phy_cas_n[1]_i_1_n_0 ;
  wire \odd_cwl.phy_ras_n[1]_i_1_n_0 ;
  wire \odd_cwl.phy_ras_n[1]_i_2_n_0 ;
  wire \odd_cwl.phy_we_n[1]_i_1_n_0 ;
  wire \one_rank.stg1_wr_done_i_1_n_0 ;
  wire \one_rank.stg1_wr_done_reg_0 ;
  wire \one_rank.stg1_wr_done_reg_1 ;
  wire p_0_in10_in;
  wire p_0_in14_in;
  wire [9:0]p_0_in__0;
  wire [8:0]p_0_in__0__0;
  wire [7:0]p_0_in__1;
  wire [3:0]p_0_in__10;
  wire [3:0]p_0_in__2;
  wire [7:0]p_0_in__3;
  wire [3:0]p_0_in__4;
  wire [7:0]p_0_in__5;
  wire [7:1]p_0_in__6;
  wire [3:0]p_0_in__7;
  wire [4:0]p_0_in__8;
  wire [3:0]p_0_in__9;
  wire [54:42]phy_address;
  wire [11:9]phy_bank;
  wire [1:1]phy_cas_n;
  wire phy_cmd_wr_en;
  wire [1:1]phy_cs_n;
  wire phy_ctl_ready;
  wire [10:0]\phy_ctl_wd_i1_reg[24] ;
  wire phy_ctl_wr_i1_reg;
  wire phy_data_wr_en;
  wire [15:0]phy_dout;
  wire [1:1]phy_ras_n;
  wire phy_reset_n;
  wire [1:1]phy_we_n;
  wire [511:61]phy_wrdata;
  wire phy_wrdata_en;
  wire pi_calib_done;
  wire pi_calib_done_r;
  wire pi_calib_done_r_i_1_n_0;
  wire pi_calib_rank_done_r;
  wire \pi_dqs_found_any_bank_reg[0] ;
  wire pi_dqs_found_done_r1;
  wire pi_dqs_found_done_r1_reg_0;
  wire pi_dqs_found_done_r1_reg_1;
  wire pi_dqs_found_done_r1_reg_10;
  wire pi_dqs_found_done_r1_reg_11;
  wire pi_dqs_found_done_r1_reg_12;
  wire pi_dqs_found_done_r1_reg_13;
  wire pi_dqs_found_done_r1_reg_14;
  wire pi_dqs_found_done_r1_reg_2;
  wire pi_dqs_found_done_r1_reg_3;
  wire pi_dqs_found_done_r1_reg_4;
  wire pi_dqs_found_done_r1_reg_5;
  wire pi_dqs_found_done_r1_reg_6;
  wire pi_dqs_found_done_r1_reg_7;
  wire pi_dqs_found_done_r1_reg_8;
  wire pi_dqs_found_done_r1_reg_9;
  wire pi_dqs_found_rank_done;
  wire pi_dqs_found_start_i_1_n_0;
  wire pi_phase_locked_all_r1;
  wire pi_phase_locked_all_r2;
  wire pi_phase_locked_all_r3;
  wire pi_phase_locked_all_r4;
  wire po_ck_addr_cmd_delay_done;
  wire prbs_last_byte_done_r;
  wire prech_done;
  wire \prech_done_dly_r_reg[15]_srl16_i_2_n_0 ;
  wire \prech_done_dly_r_reg[15]_srl16_i_3_n_0 ;
  wire \prech_done_dly_r_reg[15]_srl16_i_4_n_0 ;
  wire \prech_done_dly_r_reg[15]_srl16_i_5_n_0 ;
  wire \prech_done_dly_r_reg[15]_srl16_i_6_n_0 ;
  wire \prech_done_dly_r_reg[15]_srl16_n_0 ;
  wire prech_done_pre;
  wire prech_pending_r_i_1_n_0;
  wire prech_pending_r_reg_0;
  wire prech_pending_r_reg_n_0;
  wire prech_req;
  wire prech_req_posedge_r0;
  wire prech_req_r;
  wire pwron_ce_r;
  wire pwron_ce_r_i_1_n_0;
  wire pwron_ce_r_i_2_n_0;
  wire [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ;
  wire rd_active_r;
  wire [0:0]\rd_byte_data_offset_reg[0][15] ;
  wire [0:0]\rd_byte_data_offset_reg[0][3] ;
  wire [0:0]\rd_byte_data_offset_reg[0][9] ;
  wire [43:0]\rd_ptr_reg_rep[3] ;
  wire [10:0]\rd_ptr_reg_rep[3]_0 ;
  wire [44:0]\rd_ptr_reg_rep[3]_1 ;
  wire [43:0]\rd_ptr_reg_rep[3]_2 ;
  wire [43:0]\rd_ptr_reg_rep[3]_3 ;
  wire [43:0]\rd_ptr_reg_rep[3]_4 ;
  wire [43:0]\rd_ptr_reg_rep[3]_5 ;
  wire [43:0]\rd_ptr_reg_rep[3]_6 ;
  wire [43:0]\rd_ptr_reg_rep[3]_7 ;
  wire rdlvl_last_byte_done;
  wire rdlvl_last_byte_done_r;
  wire rdlvl_prech_req;
  wire [14:14]rdlvl_start_dly0_r;
  wire \rdlvl_start_dly0_r_reg[13]_srl14_n_0 ;
  wire rdlvl_start_pre;
  wire rdlvl_start_pre_i_1_n_0;
  wire rdlvl_start_pre_i_2_n_0;
  wire rdlvl_stg1_done_reg;
  wire rdlvl_stg1_done_reg_0;
  wire rdlvl_stg1_done_reg_1;
  wire rdlvl_stg1_done_reg_2;
  wire rdlvl_stg1_done_reg_3;
  wire rdlvl_stg1_done_reg_4;
  wire rdlvl_stg1_done_reg_5;
  wire [0:0]rdlvl_stg1_done_reg_6;
  wire rdlvl_stg1_done_reg_7;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_i_1_n_0;
  wire rdlvl_stg1_start_r_reg;
  wire read_calib;
  wire read_calib_i_1_n_0;
  wire read_calib_i_2_n_0;
  wire \reg_ctrl_cnt_r[3]_i_1_n_0 ;
  wire \reg_ctrl_cnt_r[3]_i_2_n_0 ;
  wire \reg_ctrl_cnt_r[3]_i_4_n_0 ;
  wire [3:0]reg_ctrl_cnt_r_reg__0;
  wire reset_rd_addr_r1;
  wire \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_11_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_12_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_13_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_14_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_15_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_16_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_17_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_7_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_1 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_2 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_3 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_4 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_5 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_6 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_7 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_2 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_3 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_5 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_6 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_7 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_1 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_2 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_3 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_4 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_5 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_6 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_7 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__22;
  wire rstdiv0_sync_r1_reg_rep__22_0;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire rstdiv0_sync_r1_reg_rep__4;
  wire stg1_wr_done;
  wire \stg1_wr_rd_cnt[0]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[1]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[2]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[3]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[3]_i_3_n_0 ;
  wire \stg1_wr_rd_cnt[3]_i_4_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_3_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_4_n_0 ;
  wire \stg1_wr_rd_cnt[5]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[6]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[6]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[7]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[7]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_3_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_4_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_5_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_6_n_0 ;
  wire \stg1_wr_rd_cnt_reg_n_0_[0] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[1] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[2] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[3] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[4] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[5] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[6] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[7] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[8] ;
  wire tempmon_sel_pi_incdec;
  wire wl_sm_start;
  wire \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ;
  wire \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ;
  wire wr_en;
  wire wr_en_0;
  wire wr_en_1;
  wire wr_level_done_reg;
  wire wr_level_dqs_asrt;
  wire wr_level_dqs_asrt_i_1_n_0;
  wire wr_level_dqs_asrt_r1;
  wire wr_level_start_r_reg;
  wire wr_lvl_start_i_1_n_0;
  wire \wr_ptr_reg[2] ;
  wire [0:0]\wr_ptr_reg[2]_0 ;
  wire [0:0]\wr_ptr_reg[2]_1 ;
  wire [4:0]\wr_ptr_timing_reg[0] ;
  wire [44:0]\wr_ptr_timing_reg[0]_0 ;
  wire [0:0]\wr_ptr_timing_reg[0]_1 ;
  wire [3:0]\wr_ptr_timing_reg[0]_10 ;
  wire [3:0]\wr_ptr_timing_reg[0]_11 ;
  wire [3:0]\wr_ptr_timing_reg[0]_12 ;
  wire [0:0]\wr_ptr_timing_reg[0]_13 ;
  wire [1:0]\wr_ptr_timing_reg[0]_2 ;
  wire [3:0]\wr_ptr_timing_reg[0]_3 ;
  wire [3:0]\wr_ptr_timing_reg[0]_4 ;
  wire [3:0]\wr_ptr_timing_reg[0]_5 ;
  wire [3:0]\wr_ptr_timing_reg[0]_6 ;
  wire [7:0]\wr_ptr_timing_reg[0]_7 ;
  wire [7:0]\wr_ptr_timing_reg[0]_8 ;
  wire [3:0]\wr_ptr_timing_reg[0]_9 ;
  wire wr_victim_inc;
  wire wr_victim_inc_i_1_n_0;
  wire wr_victim_inc_i_2_n_0;
  wire wr_victim_inc_i_3_n_0;
  wire wrcal_done_reg;
  wire wrcal_done_reg_0;
  wire wrcal_final_chk;
  wire wrcal_final_chk_i_1_n_0;
  wire wrcal_final_chk_i_2_n_0;
  wire wrcal_final_chk_i_3_n_0;
  wire wrcal_final_chk_i_4_n_0;
  wire wrcal_final_chk_i_5_n_0;
  wire wrcal_final_chk_i_6_n_0;
  wire wrcal_final_chk_i_7_n_0;
  wire wrcal_final_chk_i_8_n_0;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_rd_wait_i_1_n_0;
  wire wrcal_reads05_out;
  wire \wrcal_reads[0]_i_1_n_0 ;
  wire \wrcal_reads[1]_i_1_n_0 ;
  wire \wrcal_reads[2]_i_1_n_0 ;
  wire \wrcal_reads[3]_i_1_n_0 ;
  wire \wrcal_reads[4]_i_1_n_0 ;
  wire \wrcal_reads[5]_i_1_n_0 ;
  wire \wrcal_reads[6]_i_1_n_0 ;
  wire \wrcal_reads[7]_i_2_n_0 ;
  wire \wrcal_reads[7]_i_3_n_0 ;
  wire \wrcal_reads[7]_i_4_n_0 ;
  wire \wrcal_reads[7]_i_5_n_0 ;
  wire \wrcal_reads[7]_i_6_n_0 ;
  wire \wrcal_reads[7]_i_7_n_0 ;
  wire \wrcal_reads_reg_n_0_[0] ;
  wire \wrcal_reads_reg_n_0_[1] ;
  wire \wrcal_reads_reg_n_0_[2] ;
  wire \wrcal_reads_reg_n_0_[3] ;
  wire \wrcal_reads_reg_n_0_[4] ;
  wire \wrcal_reads_reg_n_0_[5] ;
  wire \wrcal_reads_reg_n_0_[6] ;
  wire \wrcal_reads_reg_n_0_[7] ;
  wire wrcal_resume_r;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire wrcal_sanity_chk_done;
  wire wrcal_sanity_chk_done_reg;
  wire wrcal_sanity_chk_r;
  wire \wrcal_start_dly_r_reg[4]_srl5_i_1_n_0 ;
  wire \wrcal_start_dly_r_reg[4]_srl5_i_2_n_0 ;
  wire \wrcal_start_dly_r_reg[4]_srl5_n_0 ;
  wire \wrcal_start_dly_r_reg_n_0_[5] ;
  wire wrcal_start_i_1_n_0;
  wire wrcal_start_reg_0;
  wire [3:2]wrcal_wr_cnt0;
  wire \wrcal_wr_cnt[0]_i_1_n_0 ;
  wire \wrcal_wr_cnt[1]_i_1_n_0 ;
  wire \wrcal_wr_cnt[3]_i_1_n_0 ;
  wire \wrcal_wr_cnt[3]_i_4_n_0 ;
  wire [3:0]wrcal_wr_cnt_reg__0;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1_n_0 ;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1_n_0 ;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1_n_0 ;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ;
  wire [351:0]\write_buffer.wr_buf_out_data_reg[511] ;
  wire write_calib;
  wire write_calib_i_1_n_0;
  wire wrlvl_active;
  wire wrlvl_active_i_1_n_0;
  wire wrlvl_active_r1;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_reg;
  wire wrlvl_done_r;
  wire wrlvl_done_r1;
  wire wrlvl_final_if_rst;
  wire wrlvl_final_if_rst_i_1_n_0;
  wire wrlvl_final_if_rst_i_2_n_0;
  wire wrlvl_odt;
  wire wrlvl_odt_ctl;
  wire wrlvl_odt_ctl_i_1_n_0;
  wire wrlvl_odt_ctl_i_2_n_0;
  wire wrlvl_odt_ctl_i_3_n_0;
  wire wrlvl_odt_ctl_i_4_n_0;
  wire wrlvl_rank_done;
  wire wrlvl_rank_done_r1;
  wire wrlvl_rank_done_r6_reg_srl5_n_0;
  wire wrlvl_rank_done_r7;
  wire [3:2]\NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_CO_UNCONNECTED ;
  wire [3:3]\NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_O_UNCONNECTED ;

  assign init_complete_r_timing = init_complete_r_timing_orig;
  assign \read_fifo.tail_r_reg[1]  = init_complete_r1_timing;
  LUT6 #(
    .INIT(64'h000000000000000E)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_1 
       (.I0(burst_addr_r_i_4_n_0),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I2(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I3(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),
        .I4(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(init_complete_r_i_2_n_0),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h4C0000CC4C00000C)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_3 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(mpr_rdlvl_start_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000210)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_4 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_complete_r_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(init_state_r),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000800)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_5 
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\cnt_dllk_zqinit_r[7]_i_1_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAEAAAAAAFEAAAFAA)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_6 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(complex_oclkdelay_calib_start_int_i_2_n_0),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT4 #(
    .INIT(16'hFFFD)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_7 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEFEEEEEEE)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_8 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ),
        .I1(\num_refresh[3]_i_4_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0020000000010000)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_9 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\wrcal_start_dly_r_reg[4]_srl5_i_2_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ));
  FDSE \DDR3_1rank.phy_int_cs_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ),
        .Q(phy_cs_n),
        .S(rstdiv0_sync_r1_reg_rep__18));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT5 #(
    .INIT(32'h00000032)) 
    \back_to_back_reads_4_1.num_reads[0]_i_1 
       (.I0(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),
        .I1(num_reads[0]),
        .I2(num_reads[1]),
        .I3(\back_to_back_reads_4_1.num_reads_reg[1]_0 ),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .O(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT5 #(
    .INIT(32'h000000C2)) 
    \back_to_back_reads_4_1.num_reads[1]_i_1 
       (.I0(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),
        .I1(num_reads[0]),
        .I2(num_reads[1]),
        .I3(\back_to_back_reads_4_1.num_reads_reg[1]_0 ),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .O(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    \back_to_back_reads_4_1.num_reads[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r[0]_i_5_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ));
  FDRE \back_to_back_reads_4_1.num_reads_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ),
        .Q(num_reads[0]),
        .R(1'b0));
  FDRE \back_to_back_reads_4_1.num_reads_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ),
        .Q(num_reads[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000BBBF)) 
    burst_addr_r_i_1
       (.I0(burst_addr_r_i_2_n_0),
        .I1(burst_addr_r_i_3_n_0),
        .I2(burst_addr_r_reg_n_0),
        .I3(burst_addr_r_i_4_n_0),
        .I4(wrcal_done_reg),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(burst_addr_r6_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEEEF)) 
    burst_addr_r_i_2
       (.I0(\wrcal_wr_cnt[3]_i_4_n_0 ),
        .I1(burst_addr_r_i_5_n_0),
        .I2(\wrcal_start_dly_r_reg[4]_srl5_i_2_n_0 ),
        .I3(burst_addr_r_i_6_n_0),
        .I4(first_wrcal_pat_r_i_2_n_0),
        .I5(p_0_in14_in),
        .O(burst_addr_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT5 #(
    .INIT(32'hFBF3FBFF)) 
    burst_addr_r_i_3
       (.I0(burst_addr_r_i_7_n_0),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(burst_addr_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT2 #(
    .INIT(4'h2)) 
    burst_addr_r_i_4
       (.I0(calib_wrdata_en_i_2_n_0),
        .I1(\calib_cmd[1]_i_2_n_0 ),
        .O(burst_addr_r_i_4_n_0));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    burst_addr_r_i_5
       (.I0(\init_state_r[0]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(burst_addr_r_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT4 #(
    .INIT(16'hFFFB)) 
    burst_addr_r_i_6
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .O(burst_addr_r_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    burst_addr_r_i_7
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .O(burst_addr_r_i_7_n_0));
  FDRE burst_addr_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(burst_addr_r6_out),
        .Q(burst_addr_r_reg_n_0),
        .R(1'b0));
  FDRE \calib_cke_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_pwron_cke_done_r),
        .Q(calib_cke),
        .R(rstdiv0_sync_r1_reg_rep__3));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \calib_cmd[0]_i_1 
       (.I0(wr_level_dqs_asrt),
        .I1(burst_addr_r_i_4_n_0),
        .O(\calib_cmd[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \calib_cmd[1]_i_1 
       (.I0(\calib_cmd[1]_i_2_n_0 ),
        .I1(\calib_cmd[1]_i_3_n_0 ),
        .O(\calib_cmd[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \calib_cmd[1]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I2(rdlvl_start_pre_i_2_n_0),
        .I3(read_calib_i_2_n_0),
        .I4(\calib_cmd[1]_i_4_n_0 ),
        .I5(\calib_cmd[1]_i_5_n_0 ),
        .O(\calib_cmd[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \calib_cmd[1]_i_3 
       (.I0(wr_level_dqs_asrt),
        .I1(calib_wrdata_en_i_2_n_0),
        .O(\calib_cmd[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0100020000000000)) 
    \calib_cmd[1]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\calib_cmd[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \calib_cmd[1]_i_5 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(init_state_r),
        .O(\calib_cmd[1]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \calib_cmd[2]_i_1 
       (.I0(burst_addr_r_i_4_n_0),
        .I1(wr_level_dqs_asrt),
        .O(\calib_cmd[2]_i_1_n_0 ));
  FDRE \calib_cmd_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_cmd[0]_i_1_n_0 ),
        .Q(calib_cmd[0]),
        .R(1'b0));
  FDRE \calib_cmd_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_cmd[1]_i_1_n_0 ),
        .Q(calib_cmd[1]),
        .R(1'b0));
  FDRE \calib_cmd_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_cmd[2]_i_1_n_0 ),
        .Q(calib_cmd[2]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    calib_ctl_wren_i_1
       (.I0(cnt_pwron_cke_done_r),
        .I1(phy_ctl_ready),
        .O(calib_ctl_wren0));
  FDRE calib_ctl_wren_reg
       (.C(CLK),
        .CE(1'b1),
        .D(calib_ctl_wren0),
        .Q(\wr_ptr_reg[2] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT6 #(
    .INIT(64'hBBAABBABBBAABAAA)) 
    \calib_data_offset_0[3]_i_1 
       (.I0(\calib_cmd[1]_i_3_n_0 ),
        .I1(\calib_data_offset_0[3]_i_2_n_0 ),
        .I2(pi_dqs_found_done_r1),
        .I3(Q),
        .I4(init_dqsfound_done_r2_reg),
        .I5(\rd_byte_data_offset_reg[0][3] ),
        .O(\calib_data_offset_0[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \calib_data_offset_0[3]_i_2 
       (.I0(pi_calib_done),
        .I1(\calib_cmd[1]_i_2_n_0 ),
        .O(\calib_data_offset_0[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \calib_data_offset_0[5]_i_1 
       (.I0(\calib_cmd[1]_i_3_n_0 ),
        .I1(\calib_data_offset_0[3]_i_2_n_0 ),
        .O(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_4),
        .Q(calib_data_offset_0[0]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_3),
        .Q(calib_data_offset_0[1]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_2),
        .Q(calib_data_offset_0[2]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_0[3]_i_1_n_0 ),
        .Q(calib_data_offset_0[3]),
        .R(1'b0));
  FDRE \calib_data_offset_0_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_1),
        .Q(calib_data_offset_0[4]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_0),
        .Q(calib_data_offset_0[5]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBBAABBABBBAABAAA)) 
    \calib_data_offset_1[3]_i_1 
       (.I0(\calib_cmd[1]_i_3_n_0 ),
        .I1(\calib_data_offset_0[3]_i_2_n_0 ),
        .I2(pi_dqs_found_done_r1),
        .I3(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ),
        .I4(init_dqsfound_done_r2_reg),
        .I5(\rd_byte_data_offset_reg[0][9] ),
        .O(\calib_data_offset_1[3]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_9),
        .Q(calib_data_offset_1[0]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_8),
        .Q(calib_data_offset_1[1]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_7),
        .Q(calib_data_offset_1[2]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_1[3]_i_1_n_0 ),
        .Q(calib_data_offset_1[3]),
        .R(1'b0));
  FDRE \calib_data_offset_1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_6),
        .Q(calib_data_offset_1[4]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_5),
        .Q(calib_data_offset_1[5]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBBAABBABBBAABAAA)) 
    \calib_data_offset_2[3]_i_1 
       (.I0(\calib_cmd[1]_i_3_n_0 ),
        .I1(\calib_data_offset_0[3]_i_2_n_0 ),
        .I2(pi_dqs_found_done_r1),
        .I3(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ),
        .I4(init_dqsfound_done_r2_reg),
        .I5(\rd_byte_data_offset_reg[0][15] ),
        .O(\calib_data_offset_2[3]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_14),
        .Q(calib_data_offset_2[0]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_13),
        .Q(calib_data_offset_2[1]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_12),
        .Q(calib_data_offset_2[2]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_2[3]_i_1_n_0 ),
        .Q(calib_data_offset_2[3]),
        .R(1'b0));
  FDRE \calib_data_offset_2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_11),
        .Q(calib_data_offset_2[4]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_10),
        .Q(calib_data_offset_2[5]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT4 #(
    .INIT(16'h002A)) 
    \calib_odt[0]_i_1 
       (.I0(\gen_rnk[0].mr1_r_reg[0]_0 ),
        .I1(calib_wrdata_en_i_2_n_0),
        .I2(\calib_odt[0]_i_2_n_0 ),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .O(\calib_odt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \calib_odt[0]_i_2 
       (.I0(\oclk_wr_cnt[3]_i_4_n_0 ),
        .I1(\calib_odt[0]_i_3_n_0 ),
        .I2(stg1_wr_done),
        .I3(complex_ocal_odt_ext),
        .I4(complex_odt_ext),
        .I5(\complex_address[9]_i_4_n_0 ),
        .O(\calib_odt[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF0FF7FFFFFFF7FFF)) 
    \calib_odt[0]_i_3 
       (.I0(wrlvl_odt),
        .I1(wrlvl_odt_ctl_i_3_n_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(\calib_odt[0]_i_3_n_0 ));
  FDRE \calib_odt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_odt[0]_i_1_n_0 ),
        .Q(calib_odt),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \calib_seq[0]_i_1 
       (.I0(phy_ctl_ready),
        .I1(cnt_pwron_cke_done_r),
        .I2(\phy_ctl_wd_i1_reg[24] [9]),
        .O(\calib_seq[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \calib_seq[1]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[24] [9]),
        .I1(cnt_pwron_cke_done_r),
        .I2(phy_ctl_ready),
        .I3(\phy_ctl_wd_i1_reg[24] [10]),
        .O(\calib_seq[1]_i_1_n_0 ));
  FDRE \calib_seq_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq[0]_i_1_n_0 ),
        .Q(\phy_ctl_wd_i1_reg[24] [9]),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \calib_seq_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq[1]_i_1_n_0 ),
        .Q(\phy_ctl_wd_i1_reg[24] [10]),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT1 #(
    .INIT(2'h1)) 
    calib_wrdata_en_i_1
       (.I0(calib_wrdata_en_i_2_n_0),
        .O(phy_wrdata_en));
  LUT6 #(
    .INIT(64'h3131313101313101)) 
    calib_wrdata_en_i_2
       (.I0(first_wrcal_pat_r_i_2_n_0),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(burst_addr_r_i_7_n_0),
        .O(calib_wrdata_en_i_2_n_0));
  FDRE calib_wrdata_en_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_wrdata_en),
        .Q(\my_empty_reg[7] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00000020)) 
    cnt_cmd_done_m7_r_i_1
       (.I0(cnt_cmd_done_m7_r_i_2_n_0),
        .I1(\cnt_cmd_r_reg_n_0_[2] ),
        .I2(\cnt_cmd_r_reg_n_0_[6] ),
        .I3(\cnt_cmd_r_reg_n_0_[1] ),
        .I4(\cnt_cmd_r_reg_n_0_[0] ),
        .O(cnt_cmd_done_m7_r_i_1_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    cnt_cmd_done_m7_r_i_2
       (.I0(\cnt_cmd_r_reg_n_0_[5] ),
        .I1(\cnt_cmd_r_reg_n_0_[4] ),
        .I2(\cnt_cmd_r_reg_n_0_[3] ),
        .O(cnt_cmd_done_m7_r_i_2_n_0));
  FDRE cnt_cmd_done_m7_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_cmd_done_m7_r_i_1_n_0),
        .Q(cnt_cmd_done_m7_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT2 #(
    .INIT(4'h2)) 
    cnt_cmd_done_r_i_1
       (.I0(\cnt_cmd_r_reg_n_0_[6] ),
        .I1(\cnt_cmd_r[6]_i_3_n_0 ),
        .O(cnt_cmd_done_r_i_1_n_0));
  FDRE cnt_cmd_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_cmd_done_r_i_1_n_0),
        .Q(cnt_cmd_done_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h04)) 
    \cnt_cmd_r[0]_i_1 
       (.I0(\cnt_cmd_r[2]_i_3_n_0 ),
        .I1(\cnt_cmd_r[2]_i_2_n_0 ),
        .I2(\cnt_cmd_r_reg_n_0_[0] ),
        .O(\cnt_cmd_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT4 #(
    .INIT(16'h0028)) 
    \cnt_cmd_r[1]_i_1 
       (.I0(\cnt_cmd_r[2]_i_2_n_0 ),
        .I1(\cnt_cmd_r_reg_n_0_[1] ),
        .I2(\cnt_cmd_r_reg_n_0_[0] ),
        .I3(\cnt_cmd_r[2]_i_3_n_0 ),
        .O(\cnt_cmd_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT5 #(
    .INIT(32'h00002888)) 
    \cnt_cmd_r[2]_i_1 
       (.I0(\cnt_cmd_r[2]_i_2_n_0 ),
        .I1(\cnt_cmd_r_reg_n_0_[2] ),
        .I2(\cnt_cmd_r_reg_n_0_[0] ),
        .I3(\cnt_cmd_r_reg_n_0_[1] ),
        .I4(\cnt_cmd_r[2]_i_3_n_0 ),
        .O(\cnt_cmd_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000E6F7F7F7)) 
    \cnt_cmd_r[2]_i_2 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\cnt_cmd_r[2]_i_4_n_0 ),
        .O(\cnt_cmd_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAA8AA88A2A0A020)) 
    \cnt_cmd_r[2]_i_3 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\cnt_cmd_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBAABBAABBABBBAAB)) 
    \cnt_cmd_r[2]_i_4 
       (.I0(\cnt_cmd_r[5]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\cnt_cmd_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT5 #(
    .INIT(32'h2AAA8000)) 
    \cnt_cmd_r[3]_i_1 
       (.I0(\cnt_cmd_r[6]_i_2_n_0 ),
        .I1(\cnt_cmd_r_reg_n_0_[0] ),
        .I2(\cnt_cmd_r_reg_n_0_[1] ),
        .I3(\cnt_cmd_r_reg_n_0_[2] ),
        .I4(\cnt_cmd_r_reg_n_0_[3] ),
        .O(\cnt_cmd_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h2AAAAAAA80000000)) 
    \cnt_cmd_r[4]_i_1 
       (.I0(\cnt_cmd_r[6]_i_2_n_0 ),
        .I1(\cnt_cmd_r_reg_n_0_[2] ),
        .I2(\cnt_cmd_r_reg_n_0_[1] ),
        .I3(\cnt_cmd_r_reg_n_0_[0] ),
        .I4(\cnt_cmd_r_reg_n_0_[3] ),
        .I5(\cnt_cmd_r_reg_n_0_[4] ),
        .O(\cnt_cmd_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0220220022002200)) 
    \cnt_cmd_r[5]_i_1 
       (.I0(\cnt_cmd_r[5]_i_2_n_0 ),
        .I1(\cnt_cmd_r[5]_i_3_n_0 ),
        .I2(\cnt_cmd_r[5]_i_4_n_0 ),
        .I3(\cnt_cmd_r_reg_n_0_[5] ),
        .I4(\cnt_cmd_r_reg_n_0_[4] ),
        .I5(\cnt_cmd_r_reg_n_0_[3] ),
        .O(\cnt_cmd_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h013C5114033C351C)) 
    \cnt_cmd_r[5]_i_2 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\cnt_cmd_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \cnt_cmd_r[5]_i_3 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\cnt_cmd_r[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \cnt_cmd_r[5]_i_4 
       (.I0(\cnt_cmd_r_reg_n_0_[0] ),
        .I1(\cnt_cmd_r_reg_n_0_[1] ),
        .I2(\cnt_cmd_r_reg_n_0_[2] ),
        .O(\cnt_cmd_r[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT3 #(
    .INIT(8'h82)) 
    \cnt_cmd_r[6]_i_1 
       (.I0(\cnt_cmd_r[6]_i_2_n_0 ),
        .I1(\cnt_cmd_r[6]_i_3_n_0 ),
        .I2(\cnt_cmd_r_reg_n_0_[6] ),
        .O(\cnt_cmd_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \cnt_cmd_r[6]_i_2 
       (.I0(\cnt_cmd_r[6]_i_4_n_0 ),
        .I1(\cnt_cmd_r[6]_i_5_n_0 ),
        .I2(init_state_r),
        .O(\cnt_cmd_r[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \cnt_cmd_r[6]_i_3 
       (.I0(\cnt_cmd_r_reg_n_0_[3] ),
        .I1(\cnt_cmd_r_reg_n_0_[4] ),
        .I2(\cnt_cmd_r_reg_n_0_[5] ),
        .I3(\cnt_cmd_r_reg_n_0_[2] ),
        .I4(\cnt_cmd_r_reg_n_0_[1] ),
        .I5(\cnt_cmd_r_reg_n_0_[0] ),
        .O(\cnt_cmd_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555557F5D7D575D)) 
    \cnt_cmd_r[6]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\cnt_cmd_r[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h5511105555010055)) 
    \cnt_cmd_r[6]_i_5 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\cnt_cmd_r[6]_i_5_n_0 ));
  FDRE \cnt_cmd_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[0]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cnt_cmd_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[1]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cnt_cmd_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[2]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \cnt_cmd_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[3]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cnt_cmd_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[4]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \cnt_cmd_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[5]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \cnt_cmd_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[6]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[6] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    cnt_dllk_zqinit_done_r_i_1
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(cnt_dllk_zqinit_r_reg__0[6]),
        .I2(mem_init_done_r_i_2_n_0),
        .I3(cnt_dllk_zqinit_r_reg__0[7]),
        .O(cnt_dllk_zqinit_done_r_i_1_n_0));
  FDRE cnt_dllk_zqinit_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_dllk_zqinit_done_r_i_1_n_0),
        .Q(cnt_dllk_zqinit_done_r),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_dllk_zqinit_r[0]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg__0[0]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_dllk_zqinit_r[1]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg__0[0]),
        .I1(cnt_dllk_zqinit_r_reg__0[1]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_dllk_zqinit_r[2]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg__0[2]),
        .I1(cnt_dllk_zqinit_r_reg__0[1]),
        .I2(cnt_dllk_zqinit_r_reg__0[0]),
        .O(p_0_in__3[2]));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_dllk_zqinit_r[3]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg__0[3]),
        .I1(cnt_dllk_zqinit_r_reg__0[0]),
        .I2(cnt_dllk_zqinit_r_reg__0[1]),
        .I3(cnt_dllk_zqinit_r_reg__0[2]),
        .O(p_0_in__3[3]));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_dllk_zqinit_r[4]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg__0[4]),
        .I1(cnt_dllk_zqinit_r_reg__0[2]),
        .I2(cnt_dllk_zqinit_r_reg__0[1]),
        .I3(cnt_dllk_zqinit_r_reg__0[0]),
        .I4(cnt_dllk_zqinit_r_reg__0[3]),
        .O(p_0_in__3[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_dllk_zqinit_r[5]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg__0[5]),
        .I1(cnt_dllk_zqinit_r_reg__0[3]),
        .I2(cnt_dllk_zqinit_r_reg__0[0]),
        .I3(cnt_dllk_zqinit_r_reg__0[1]),
        .I4(cnt_dllk_zqinit_r_reg__0[2]),
        .I5(cnt_dllk_zqinit_r_reg__0[4]),
        .O(p_0_in__3[5]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_dllk_zqinit_r[6]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg__0[6]),
        .I1(mem_init_done_r_i_2_n_0),
        .O(p_0_in__3[6]));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \cnt_dllk_zqinit_r[7]_i_1 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_complete_r_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_dllk_zqinit_r[7]_i_2 
       (.I0(cnt_dllk_zqinit_r_reg__0[7]),
        .I1(mem_init_done_r_i_2_n_0),
        .I2(cnt_dllk_zqinit_r_reg__0[6]),
        .O(p_0_in__3[7]));
  FDRE \cnt_dllk_zqinit_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[0]),
        .Q(cnt_dllk_zqinit_r_reg__0[0]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[1]),
        .Q(cnt_dllk_zqinit_r_reg__0[1]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[2]),
        .Q(cnt_dllk_zqinit_r_reg__0[2]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[3]),
        .Q(cnt_dllk_zqinit_r_reg__0[3]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[4]),
        .Q(cnt_dllk_zqinit_r_reg__0[4]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[5]),
        .Q(cnt_dllk_zqinit_r_reg__0[5]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[6]),
        .Q(cnt_dllk_zqinit_r_reg__0[6]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[7]),
        .Q(cnt_dllk_zqinit_r_reg__0[7]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000BA8A8A8A)) 
    cnt_init_af_done_r_i_1
       (.I0(cnt_init_af_done_r),
        .I1(mem_init_done_r),
        .I2(\cnt_init_mr_r[1]_i_3_n_0 ),
        .I3(\cnt_init_af_r_reg_n_0_[1] ),
        .I4(\cnt_init_af_r_reg_n_0_[0] ),
        .I5(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(cnt_init_af_done_r_i_1_n_0));
  FDRE cnt_init_af_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_init_af_done_r_i_1_n_0),
        .Q(cnt_init_af_done_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT4 #(
    .INIT(16'h00A6)) 
    \cnt_init_af_r[0]_i_1 
       (.I0(\cnt_init_af_r_reg_n_0_[0] ),
        .I1(\cnt_init_mr_r[1]_i_3_n_0 ),
        .I2(mem_init_done_r),
        .I3(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(\cnt_init_af_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT5 #(
    .INIT(32'h00009AAA)) 
    \cnt_init_af_r[1]_i_1 
       (.I0(\cnt_init_af_r_reg_n_0_[1] ),
        .I1(mem_init_done_r),
        .I2(\cnt_init_mr_r[1]_i_3_n_0 ),
        .I3(\cnt_init_af_r_reg_n_0_[0] ),
        .I4(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(\cnt_init_af_r[1]_i_1_n_0 ));
  FDRE \cnt_init_af_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_af_r[0]_i_1_n_0 ),
        .Q(\cnt_init_af_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cnt_init_af_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_af_r[1]_i_1_n_0 ),
        .Q(\cnt_init_af_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000E222)) 
    cnt_init_mr_done_r_i_1
       (.I0(cnt_init_mr_done_r),
        .I1(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I2(cnt_init_mr_r[0]),
        .I3(cnt_init_mr_r[1]),
        .I4(cnt_init_mr_r0),
        .O(cnt_init_mr_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000100)) 
    cnt_init_mr_done_r_i_2
       (.I0(mem_init_done_r),
        .I1(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(cnt_init_mr_r0));
  FDRE cnt_init_mr_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_init_mr_done_r_i_1_n_0),
        .Q(cnt_init_mr_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AA9AAA8A)) 
    \cnt_init_mr_r[0]_i_1 
       (.I0(cnt_init_mr_r[0]),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(cnt_init_mr_r1),
        .O(\cnt_init_mr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \cnt_init_mr_r[0]_i_2 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .O(\cnt_init_mr_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    \cnt_init_mr_r[0]_i_3 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r[0]_i_5_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I5(mem_init_done_r),
        .O(cnt_init_mr_r1));
  LUT6 #(
    .INIT(64'h006A006A0000006A)) 
    \cnt_init_mr_r[1]_i_1 
       (.I0(cnt_init_mr_r[1]),
        .I1(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I2(cnt_init_mr_r[0]),
        .I3(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I4(\cnt_init_mr_r[1]_i_3_n_0 ),
        .I5(mem_init_done_r),
        .O(\cnt_init_mr_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \cnt_init_mr_r[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(\cnt_init_mr_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000002000000)) 
    \cnt_init_mr_r[1]_i_3 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r[0]_i_5_n_0 ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\cnt_init_mr_r[1]_i_3_n_0 ));
  FDRE \cnt_init_mr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_mr_r[0]_i_1_n_0 ),
        .Q(cnt_init_mr_r[0]),
        .R(1'b0));
  FDRE \cnt_init_mr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_mr_r[1]_i_1_n_0 ),
        .Q(cnt_init_mr_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_pwron_ce_r[0]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_ce_r[1]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[0]),
        .I1(cnt_pwron_ce_r_reg__0[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_ce_r[2]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[2]),
        .I1(cnt_pwron_ce_r_reg__0[1]),
        .I2(cnt_pwron_ce_r_reg__0[0]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_ce_r[3]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[3]),
        .I1(cnt_pwron_ce_r_reg__0[0]),
        .I2(cnt_pwron_ce_r_reg__0[1]),
        .I3(cnt_pwron_ce_r_reg__0[2]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_ce_r[4]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[4]),
        .I1(cnt_pwron_ce_r_reg__0[2]),
        .I2(cnt_pwron_ce_r_reg__0[1]),
        .I3(cnt_pwron_ce_r_reg__0[0]),
        .I4(cnt_pwron_ce_r_reg__0[3]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_pwron_ce_r[5]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[5]),
        .I1(cnt_pwron_ce_r_reg__0[3]),
        .I2(cnt_pwron_ce_r_reg__0[0]),
        .I3(cnt_pwron_ce_r_reg__0[1]),
        .I4(cnt_pwron_ce_r_reg__0[2]),
        .I5(cnt_pwron_ce_r_reg__0[4]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_ce_r[6]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[6]),
        .I1(pwron_ce_r_i_2_n_0),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_ce_r[7]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[7]),
        .I1(pwron_ce_r_i_2_n_0),
        .I2(cnt_pwron_ce_r_reg__0[6]),
        .O(p_0_in__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_ce_r[8]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[8]),
        .I1(cnt_pwron_ce_r_reg__0[6]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg__0[7]),
        .O(p_0_in__0[8]));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_ce_r[9]_i_1 
       (.I0(cnt_pwron_ce_r_reg__0[9]),
        .I1(cnt_pwron_ce_r_reg__0[7]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg__0[6]),
        .I4(cnt_pwron_ce_r_reg__0[8]),
        .O(p_0_in__0[9]));
  FDRE \cnt_pwron_ce_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(cnt_pwron_ce_r_reg__0[0]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(cnt_pwron_ce_r_reg__0[1]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(cnt_pwron_ce_r_reg__0[2]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(cnt_pwron_ce_r_reg__0[3]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(cnt_pwron_ce_r_reg__0[4]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[5]),
        .Q(cnt_pwron_ce_r_reg__0[5]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[6]),
        .Q(cnt_pwron_ce_r_reg__0[6]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[7]),
        .Q(cnt_pwron_ce_r_reg__0[7]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[8]),
        .Q(cnt_pwron_ce_r_reg__0[8]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_ce_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[9]),
        .Q(cnt_pwron_ce_r_reg__0[9]),
        .R(rstdiv0_sync_r1_reg_rep));
  LUT5 #(
    .INIT(32'h0000F200)) 
    cnt_pwron_cke_done_r_i_1
       (.I0(cnt_pwron_cke_done_r_i_2_n_0),
        .I1(cnt_pwron_cke_done_r_i_3_n_0),
        .I2(cnt_pwron_cke_done_r),
        .I3(phy_ctl_ready),
        .I4(rstdiv0_sync_r1_reg_rep__22),
        .O(cnt_pwron_cke_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT3 #(
    .INIT(8'h01)) 
    cnt_pwron_cke_done_r_i_2
       (.I0(cnt_pwron_r_reg__0[7]),
        .I1(cnt_pwron_r_reg__0[8]),
        .I2(cnt_pwron_r_reg__0[6]),
        .O(cnt_pwron_cke_done_r_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    cnt_pwron_cke_done_r_i_3
       (.I0(cnt_pwron_r_reg__0[1]),
        .I1(cnt_pwron_r_reg__0[0]),
        .I2(cnt_pwron_r_reg__0[3]),
        .I3(cnt_pwron_r_reg__0[5]),
        .I4(cnt_pwron_r_reg__0[2]),
        .I5(cnt_pwron_r_reg__0[4]),
        .O(cnt_pwron_cke_done_r_i_3_n_0));
  FDRE cnt_pwron_cke_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_pwron_cke_done_r_i_1_n_0),
        .Q(cnt_pwron_cke_done_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_pwron_r[0]_i_1 
       (.I0(cnt_pwron_r_reg__0[0]),
        .O(p_0_in__0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_r[1]_i_1 
       (.I0(cnt_pwron_r_reg__0[0]),
        .I1(cnt_pwron_r_reg__0[1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_r[2]_i_1 
       (.I0(cnt_pwron_r_reg__0[2]),
        .I1(cnt_pwron_r_reg__0[1]),
        .I2(cnt_pwron_r_reg__0[0]),
        .O(p_0_in__0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_r[3]_i_1 
       (.I0(cnt_pwron_r_reg__0[3]),
        .I1(cnt_pwron_r_reg__0[0]),
        .I2(cnt_pwron_r_reg__0[1]),
        .I3(cnt_pwron_r_reg__0[2]),
        .O(p_0_in__0__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_r[4]_i_1 
       (.I0(cnt_pwron_r_reg__0[4]),
        .I1(cnt_pwron_r_reg__0[2]),
        .I2(cnt_pwron_r_reg__0[1]),
        .I3(cnt_pwron_r_reg__0[0]),
        .I4(cnt_pwron_r_reg__0[3]),
        .O(p_0_in__0__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_pwron_r[5]_i_1 
       (.I0(cnt_pwron_r_reg__0[5]),
        .I1(cnt_pwron_r_reg__0[3]),
        .I2(cnt_pwron_r_reg__0[0]),
        .I3(cnt_pwron_r_reg__0[1]),
        .I4(cnt_pwron_r_reg__0[2]),
        .I5(cnt_pwron_r_reg__0[4]),
        .O(p_0_in__0__0[5]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_pwron_r[6]_i_1 
       (.I0(cnt_pwron_r_reg__0[6]),
        .I1(cnt_pwron_r_reg__0[4]),
        .I2(cnt_pwron_r_reg__0[2]),
        .I3(\cnt_pwron_r[6]_i_2_n_0 ),
        .I4(cnt_pwron_r_reg__0[3]),
        .I5(cnt_pwron_r_reg__0[5]),
        .O(p_0_in__0__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \cnt_pwron_r[6]_i_2 
       (.I0(cnt_pwron_r_reg__0[0]),
        .I1(cnt_pwron_r_reg__0[1]),
        .O(\cnt_pwron_r[6]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_r[7]_i_1 
       (.I0(cnt_pwron_r_reg__0[7]),
        .I1(\cnt_pwron_r[8]_i_2_n_0 ),
        .I2(cnt_pwron_r_reg__0[6]),
        .O(p_0_in__0__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_r[8]_i_1 
       (.I0(cnt_pwron_r_reg__0[8]),
        .I1(cnt_pwron_r_reg__0[7]),
        .I2(cnt_pwron_r_reg__0[6]),
        .I3(\cnt_pwron_r[8]_i_2_n_0 ),
        .O(p_0_in__0__0[8]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cnt_pwron_r[8]_i_2 
       (.I0(cnt_pwron_r_reg__0[5]),
        .I1(cnt_pwron_r_reg__0[3]),
        .I2(cnt_pwron_r_reg__0[0]),
        .I3(cnt_pwron_r_reg__0[1]),
        .I4(cnt_pwron_r_reg__0[2]),
        .I5(cnt_pwron_r_reg__0[4]),
        .O(\cnt_pwron_r[8]_i_2_n_0 ));
  FDRE \cnt_pwron_r_reg[0] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[0]),
        .Q(cnt_pwron_r_reg__0[0]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[1] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[1]),
        .Q(cnt_pwron_r_reg__0[1]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[2] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[2]),
        .Q(cnt_pwron_r_reg__0[2]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[3] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[3]),
        .Q(cnt_pwron_r_reg__0[3]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[4] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[4]),
        .Q(cnt_pwron_r_reg__0[4]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[5] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[5]),
        .Q(cnt_pwron_r_reg__0[5]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[6] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[6]),
        .Q(cnt_pwron_r_reg__0[6]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[7] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[7]),
        .Q(cnt_pwron_r_reg__0[7]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \cnt_pwron_r_reg[8] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[8]),
        .Q(cnt_pwron_r_reg__0[8]),
        .R(rstdiv0_sync_r1_reg_rep));
  LUT5 #(
    .INIT(32'h0000F200)) 
    cnt_pwron_reset_done_r_i_1
       (.I0(cnt_pwron_cke_done_r_i_2_n_0),
        .I1(cnt_pwron_reset_done_r_i_2_n_0),
        .I2(cnt_pwron_reset_done_r),
        .I3(phy_ctl_ready),
        .I4(rstdiv0_sync_r1_reg_rep__22),
        .O(cnt_pwron_reset_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFDFFFFFFFF)) 
    cnt_pwron_reset_done_r_i_2
       (.I0(cnt_pwron_r_reg__0[0]),
        .I1(cnt_pwron_r_reg__0[1]),
        .I2(cnt_pwron_r_reg__0[3]),
        .I3(cnt_pwron_r_reg__0[5]),
        .I4(cnt_pwron_r_reg__0[2]),
        .I5(cnt_pwron_r_reg__0[4]),
        .O(cnt_pwron_reset_done_r_i_2_n_0));
  FDRE cnt_pwron_reset_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_pwron_reset_done_r_i_1_n_0),
        .Q(cnt_pwron_reset_done_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \cnt_shift_r[3]_i_2 
       (.I0(rdlvl_stg1_start_r_reg),
        .I1(rd_active_r),
        .O(\cnt_shift_r_reg[3] ));
  LUT4 #(
    .INIT(16'hAAEA)) 
    cnt_txpr_done_r_i_1
       (.I0(cnt_txpr_done_r),
        .I1(cnt_txpr_done_r_i_2_n_0),
        .I2(cnt_txpr_r_reg__0[2]),
        .I3(cnt_txpr_r_reg__0[5]),
        .O(cnt_txpr_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    cnt_txpr_done_r_i_2
       (.I0(cnt_txpr_r_reg__0[3]),
        .I1(cnt_txpr_r_reg__0[4]),
        .I2(cnt_txpr_r_reg__0[6]),
        .I3(cnt_txpr_r_reg__0[7]),
        .I4(cnt_txpr_r_reg__0[0]),
        .I5(cnt_txpr_r_reg__0[1]),
        .O(cnt_txpr_done_r_i_2_n_0));
  FDRE cnt_txpr_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_txpr_done_r_i_1_n_0),
        .Q(cnt_txpr_done_r),
        .R(clear));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_txpr_r[0]_i_1 
       (.I0(cnt_txpr_r_reg__0[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_txpr_r[1]_i_1 
       (.I0(cnt_txpr_r_reg__0[0]),
        .I1(cnt_txpr_r_reg__0[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_txpr_r[2]_i_1 
       (.I0(cnt_txpr_r_reg__0[2]),
        .I1(cnt_txpr_r_reg__0[1]),
        .I2(cnt_txpr_r_reg__0[0]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_txpr_r[3]_i_1 
       (.I0(cnt_txpr_r_reg__0[3]),
        .I1(cnt_txpr_r_reg__0[0]),
        .I2(cnt_txpr_r_reg__0[1]),
        .I3(cnt_txpr_r_reg__0[2]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_txpr_r[4]_i_1 
       (.I0(cnt_txpr_r_reg__0[4]),
        .I1(cnt_txpr_r_reg__0[2]),
        .I2(cnt_txpr_r_reg__0[1]),
        .I3(cnt_txpr_r_reg__0[0]),
        .I4(cnt_txpr_r_reg__0[3]),
        .O(p_0_in__1[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_txpr_r[5]_i_1 
       (.I0(cnt_txpr_r_reg__0[5]),
        .I1(cnt_txpr_r_reg__0[3]),
        .I2(cnt_txpr_r_reg__0[0]),
        .I3(cnt_txpr_r_reg__0[1]),
        .I4(cnt_txpr_r_reg__0[2]),
        .I5(cnt_txpr_r_reg__0[4]),
        .O(p_0_in__1[5]));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_txpr_r[6]_i_1 
       (.I0(cnt_txpr_r_reg__0[6]),
        .I1(\cnt_txpr_r[7]_i_3_n_0 ),
        .O(p_0_in__1[6]));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_txpr_r[7]_i_1 
       (.I0(cnt_pwron_cke_done_r),
        .O(clear));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_txpr_r[7]_i_2 
       (.I0(cnt_txpr_r_reg__0[7]),
        .I1(\cnt_txpr_r[7]_i_3_n_0 ),
        .I2(cnt_txpr_r_reg__0[6]),
        .O(p_0_in__1[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cnt_txpr_r[7]_i_3 
       (.I0(cnt_txpr_r_reg__0[5]),
        .I1(cnt_txpr_r_reg__0[3]),
        .I2(cnt_txpr_r_reg__0[0]),
        .I3(cnt_txpr_r_reg__0[1]),
        .I4(cnt_txpr_r_reg__0[2]),
        .I5(cnt_txpr_r_reg__0[4]),
        .O(\cnt_txpr_r[7]_i_3_n_0 ));
  FDRE \cnt_txpr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[0]),
        .Q(cnt_txpr_r_reg__0[0]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[1]),
        .Q(cnt_txpr_r_reg__0[1]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[2]),
        .Q(cnt_txpr_r_reg__0[2]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[3]),
        .Q(cnt_txpr_r_reg__0[3]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[4]),
        .Q(cnt_txpr_r_reg__0[4]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[5]),
        .Q(cnt_txpr_r_reg__0[5]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[6]),
        .Q(cnt_txpr_r_reg__0[6]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[7]),
        .Q(cnt_txpr_r_reg__0[7]),
        .R(clear));
  LUT5 #(
    .INIT(32'hFEFFCCC8)) 
    \complex_address[9]_i_1 
       (.I0(\complex_address[9]_i_2_n_0 ),
        .I1(\complex_address[9]_i_3_n_0 ),
        .I2(init_state_r1[6]),
        .I3(init_state_r1[2]),
        .I4(\complex_address[9]_i_4_n_0 ),
        .O(complex_address0));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT5 #(
    .INIT(32'hDFFFFFFF)) 
    \complex_address[9]_i_2 
       (.I0(init_state_r1[0]),
        .I1(init_state_r1[1]),
        .I2(init_state_r1[3]),
        .I3(init_state_r1[4]),
        .I4(init_state_r1[5]),
        .O(\complex_address[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000008000000000)) 
    \complex_address[9]_i_3 
       (.I0(\init_state_r[0]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\complex_address[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \complex_address[9]_i_4 
       (.I0(\init_state_r[0]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\complex_address[9]_i_4_n_0 ));
  FDRE \complex_address_reg[0] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[42]),
        .Q(\complex_address_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[1] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[43]),
        .Q(\complex_address_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[2] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[44]),
        .Q(\complex_address_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[3] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[45]),
        .Q(\complex_address_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[4] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[46]),
        .Q(\complex_address_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[5] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[47]),
        .Q(\complex_address_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[6] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[48]),
        .Q(\complex_address_reg_n_0_[6] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[7] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[49]),
        .Q(\complex_address_reg_n_0_[7] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[8] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[50]),
        .Q(\complex_address_reg_n_0_[8] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \complex_address_reg[9] 
       (.C(CLK),
        .CE(complex_address0),
        .D(phy_address[51]),
        .Q(\complex_address_reg_n_0_[9] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT5 #(
    .INIT(32'h0000000E)) 
    complex_byte_rd_done_i_1
       (.I0(complex_byte_rd_done),
        .I1(complex_byte_rd_done_i_2_n_0),
        .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .I4(complex_row1_rd_done_reg_0),
        .O(complex_byte_rd_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    complex_byte_rd_done_i_2
       (.I0(complex_row1_rd_cnt[1]),
        .I1(complex_row1_rd_cnt[0]),
        .I2(complex_row1_rd_cnt[2]),
        .I3(complex_row1_rd_done),
        .I4(complex_row1_rd_done_r1),
        .I5(rdlvl_stg1_done_reg_0),
        .O(complex_byte_rd_done_i_2_n_0));
  FDRE complex_byte_rd_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_byte_rd_done_i_1_n_0),
        .Q(complex_byte_rd_done),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hEEEFEFEFEEFFEFFF)) 
    \complex_num_reads[0]_i_1 
       (.I0(\complex_num_writes[4]_i_9_n_0 ),
        .I1(\complex_num_reads[3]_i_8_n_0 ),
        .I2(\complex_num_writes[0]_i_4_n_0 ),
        .I3(\complex_num_reads_reg_n_0_[0] ),
        .I4(\complex_num_reads[0]_i_2_n_0 ),
        .I5(\complex_num_reads[1]_i_4_n_0 ),
        .O(\complex_num_reads[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \complex_num_reads[0]_i_2 
       (.I0(\complex_num_reads_reg_n_0_[3] ),
        .I1(\complex_num_reads_reg_n_0_[2] ),
        .I2(\complex_num_reads_reg_n_0_[1] ),
        .O(\complex_num_reads[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EAEEEAEF)) 
    \complex_num_reads[1]_i_1 
       (.I0(\complex_num_writes[4]_i_5_n_0 ),
        .I1(\complex_num_reads[1]_i_2_n_0 ),
        .I2(\complex_num_reads[1]_i_3_n_0 ),
        .I3(\complex_num_reads[1]_i_4_n_0 ),
        .I4(\complex_num_reads[1]_i_5_n_0 ),
        .I5(\complex_num_reads[1]_i_6_n_0 ),
        .O(\complex_num_reads[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \complex_num_reads[1]_i_2 
       (.I0(\complex_num_reads_reg_n_0_[0] ),
        .I1(\complex_num_reads_reg_n_0_[1] ),
        .O(\complex_num_reads[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h00FE)) 
    \complex_num_reads[1]_i_3 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I3(\complex_num_writes[2]_i_4_n_0 ),
        .O(\complex_num_reads[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h2000000000000000)) 
    \complex_num_reads[1]_i_4 
       (.I0(\complex_num_reads[1]_i_7_n_0 ),
        .I1(\complex_num_reads[1]_i_8_n_0 ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_reads[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFDFFFFFFFF)) 
    \complex_num_reads[1]_i_5 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(complex_sample_cnt_inc_i_2_n_0),
        .I4(\complex_num_writes[0]_i_7_n_0 ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .O(\complex_num_reads[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBAABBBABBBB)) 
    \complex_num_reads[1]_i_6 
       (.I0(\complex_num_reads[3]_i_8_n_0 ),
        .I1(\complex_num_writes[0]_i_4_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[2] ),
        .I3(\complex_num_reads_reg_n_0_[3] ),
        .I4(\complex_num_reads_reg_n_0_[1] ),
        .I5(\complex_num_reads_reg_n_0_[0] ),
        .O(\complex_num_reads[1]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \complex_num_reads[1]_i_7 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\complex_num_reads[1]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_reads[1]_i_8 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\complex_num_reads[1]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT5 #(
    .INIT(32'h0000FF6A)) 
    \complex_num_reads[2]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[2] ),
        .I1(\complex_num_reads_reg_n_0_[1] ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .I3(\complex_num_writes[2]_i_2_n_0 ),
        .I4(\complex_num_reads[2]_i_2_n_0 ),
        .O(\complex_num_reads[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFEAAAAAAAAA)) 
    \complex_num_reads[2]_i_2 
       (.I0(\complex_num_reads[3]_i_8_n_0 ),
        .I1(\complex_num_reads_reg_n_0_[1] ),
        .I2(\complex_num_reads_reg_n_0_[2] ),
        .I3(\complex_num_reads_reg_n_0_[3] ),
        .I4(\complex_num_writes[0]_i_4_n_0 ),
        .I5(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_reads[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFD00)) 
    \complex_num_reads[3]_i_1 
       (.I0(\complex_num_reads[3]_i_3_n_0 ),
        .I1(\complex_num_reads[3]_i_4_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .I3(\complex_num_reads[3]_i_5_n_0 ),
        .I4(\complex_num_reads[3]_i_6_n_0 ),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(\complex_num_reads[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \complex_num_reads[3]_i_2 
       (.I0(\complex_num_reads[3]_i_7_n_0 ),
        .I1(\complex_num_writes[4]_i_9_n_0 ),
        .I2(\complex_num_writes[0]_i_4_n_0 ),
        .I3(\complex_num_reads[3]_i_8_n_0 ),
        .O(\complex_num_reads[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF5000CCC0)) 
    \complex_num_reads[3]_i_3 
       (.I0(\complex_num_reads[1]_i_4_n_0 ),
        .I1(\complex_num_reads[1]_i_5_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[1] ),
        .I3(\complex_num_reads_reg_n_0_[2] ),
        .I4(\complex_num_writes[4]_i_12_n_0 ),
        .I5(\complex_num_reads[1]_i_3_n_0 ),
        .O(\complex_num_reads[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555555501555555)) 
    \complex_num_reads[3]_i_4 
       (.I0(\complex_num_reads_reg_n_0_[3] ),
        .I1(\complex_num_reads_reg_n_0_[0] ),
        .I2(\complex_num_reads_reg_n_0_[1] ),
        .I3(\complex_num_reads_reg_n_0_[2] ),
        .I4(complex_sample_cnt_inc_i_3_n_0),
        .I5(\complex_num_writes[2]_i_4_n_0 ),
        .O(\complex_num_reads[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \complex_num_reads[3]_i_5 
       (.I0(\complex_address[9]_i_3_n_0 ),
        .I1(complex_wait_cnt_reg__0[3]),
        .I2(complex_wait_cnt_reg__0[2]),
        .I3(complex_wait_cnt_reg__0[1]),
        .I4(complex_wait_cnt_reg__0[0]),
        .I5(complex_row0_rd_done),
        .O(\complex_num_reads[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000008)) 
    \complex_num_reads[3]_i_6 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\complex_num_writes[4]_i_18_n_0 ),
        .I4(init_complete_r_i_3_n_0),
        .I5(stg1_wr_done),
        .O(\complex_num_reads[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT5 #(
    .INIT(32'hBFFFEAAA)) 
    \complex_num_reads[3]_i_7 
       (.I0(\complex_num_reads[1]_i_4_n_0 ),
        .I1(\complex_num_reads_reg_n_0_[2] ),
        .I2(\complex_num_reads_reg_n_0_[1] ),
        .I3(\complex_num_reads_reg_n_0_[0] ),
        .I4(\complex_num_reads_reg_n_0_[3] ),
        .O(\complex_num_reads[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \complex_num_reads[3]_i_8 
       (.I0(rstdiv0_sync_r1_reg_rep__22),
        .I1(complex_row0_rd_done),
        .I2(complex_wait_cnt_reg__0[0]),
        .I3(complex_wait_cnt_reg__0[1]),
        .I4(\complex_num_reads[3]_i_9_n_0 ),
        .I5(\complex_address[9]_i_3_n_0 ),
        .O(\complex_num_reads[3]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \complex_num_reads[3]_i_9 
       (.I0(complex_wait_cnt_reg__0[2]),
        .I1(complex_wait_cnt_reg__0[3]),
        .O(\complex_num_reads[3]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \complex_num_reads_dec[0]_i_1 
       (.I0(complex_num_reads_dec_reg__0[0]),
        .I1(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .O(p_0_in__9[0]));
  LUT4 #(
    .INIT(16'h9F90)) 
    \complex_num_reads_dec[1]_i_1 
       (.I0(complex_num_reads_dec_reg__0[0]),
        .I1(complex_num_reads_dec_reg__0[1]),
        .I2(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I3(\complex_num_reads_reg_n_0_[1] ),
        .O(p_0_in__9[1]));
  LUT5 #(
    .INIT(32'hA9FFA900)) 
    \complex_num_reads_dec[2]_i_1 
       (.I0(complex_num_reads_dec_reg__0[2]),
        .I1(complex_num_reads_dec_reg__0[1]),
        .I2(complex_num_reads_dec_reg__0[0]),
        .I3(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I4(\complex_num_reads_reg_n_0_[2] ),
        .O(p_0_in__9[2]));
  LUT6 #(
    .INIT(64'h0000FFFEFFFFFFFF)) 
    \complex_num_reads_dec[3]_i_1 
       (.I0(complex_num_reads_dec_reg__0[1]),
        .I1(complex_num_reads_dec_reg__0[0]),
        .I2(complex_num_reads_dec_reg__0[3]),
        .I3(complex_num_reads_dec_reg__0[2]),
        .I4(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I5(\complex_num_reads_dec[3]_i_3_n_0 ),
        .O(\complex_num_reads_dec[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAA9FFFFAAA90000)) 
    \complex_num_reads_dec[3]_i_2 
       (.I0(complex_num_reads_dec_reg__0[3]),
        .I1(complex_num_reads_dec_reg__0[2]),
        .I2(complex_num_reads_dec_reg__0[0]),
        .I3(complex_num_reads_dec_reg__0[1]),
        .I4(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I5(\complex_num_reads_reg_n_0_[3] ),
        .O(p_0_in__9[3]));
  LUT6 #(
    .INIT(64'h5555555545555555)) 
    \complex_num_reads_dec[3]_i_3 
       (.I0(\complex_num_reads[3]_i_6_n_0 ),
        .I1(complex_row0_rd_done),
        .I2(\complex_wait_cnt[3]_i_6_n_0 ),
        .I3(\init_state_r[0]_i_5_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(complex_oclkdelay_calib_start_int_i_2_n_0),
        .O(\complex_num_reads_dec[3]_i_3_n_0 ));
  FDSE \complex_num_reads_dec_reg[0] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(p_0_in__9[0]),
        .Q(complex_num_reads_dec_reg__0[0]),
        .S(rstdiv0_sync_r1));
  FDRE \complex_num_reads_dec_reg[1] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(p_0_in__9[1]),
        .Q(complex_num_reads_dec_reg__0[1]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \complex_num_reads_dec_reg[2] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(p_0_in__9[2]),
        .Q(complex_num_reads_dec_reg__0[2]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \complex_num_reads_dec_reg[3] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(p_0_in__9[3]),
        .Q(complex_num_reads_dec_reg__0[3]),
        .R(rstdiv0_sync_r1_reg_rep));
  FDRE \complex_num_reads_reg[0] 
       (.C(CLK),
        .CE(\complex_num_reads[3]_i_1_n_0 ),
        .D(\complex_num_reads[0]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[1] 
       (.C(CLK),
        .CE(\complex_num_reads[3]_i_1_n_0 ),
        .D(\complex_num_reads[1]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[2] 
       (.C(CLK),
        .CE(\complex_num_reads[3]_i_1_n_0 ),
        .D(\complex_num_reads[2]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[3] 
       (.C(CLK),
        .CE(\complex_num_reads[3]_i_1_n_0 ),
        .D(\complex_num_reads[3]_i_2_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[3] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h73337F337F337F33)) 
    \complex_num_writes[0]_i_1 
       (.I0(\complex_num_writes[0]_i_2_n_0 ),
        .I1(\complex_num_writes[0]_i_3_n_0 ),
        .I2(\complex_num_writes[0]_i_4_n_0 ),
        .I3(\complex_num_writes[4]_i_6_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[0] ),
        .I5(\complex_num_writes[0]_i_5_n_0 ),
        .O(\complex_num_writes[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4444FFC0)) 
    \complex_num_writes[0]_i_2 
       (.I0(\complex_num_writes[4]_i_15_n_0 ),
        .I1(\complex_num_writes_reg_n_0_[0] ),
        .I2(\complex_num_reads[1]_i_5_n_0 ),
        .I3(\complex_num_reads[1]_i_4_n_0 ),
        .I4(\complex_num_reads[1]_i_3_n_0 ),
        .O(\complex_num_writes[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT4 #(
    .INIT(16'h1110)) 
    \complex_num_writes[0]_i_3 
       (.I0(complex_row1_rd_done_reg_0),
        .I1(rstdiv0_sync_r1_reg_rep__22),
        .I2(\complex_num_writes[4]_i_6_n_0 ),
        .I3(\complex_num_writes[4]_i_11_n_0 ),
        .O(\complex_num_writes[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000FF57FF)) 
    \complex_num_writes[0]_i_4 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\complex_num_writes[0]_i_6_n_0 ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I5(\complex_num_writes[0]_i_7_n_0 ),
        .O(\complex_num_writes[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT4 #(
    .INIT(16'h0111)) 
    \complex_num_writes[0]_i_5 
       (.I0(\complex_num_writes_reg_n_0_[4] ),
        .I1(\complex_num_writes_reg_n_0_[3] ),
        .I2(\complex_num_writes_reg_n_0_[2] ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .O(\complex_num_writes[0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \complex_num_writes[0]_i_6 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_writes[0]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_writes[0]_i_7 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .O(\complex_num_writes[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0302030003020302)) 
    \complex_num_writes[1]_i_1 
       (.I0(\complex_num_writes[4]_i_6_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__22),
        .I2(complex_row1_rd_done_reg_0),
        .I3(\complex_num_writes[4]_i_11_n_0 ),
        .I4(\complex_num_writes[4]_i_9_n_0 ),
        .I5(\complex_num_writes[1]_i_2_n_0 ),
        .O(\complex_num_writes[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h9F999F9F)) 
    \complex_num_writes[1]_i_2 
       (.I0(\complex_num_writes_reg_n_0_[1] ),
        .I1(\complex_num_writes_reg_n_0_[0] ),
        .I2(\complex_num_writes[2]_i_5_n_0 ),
        .I3(\complex_num_reads[1]_i_4_n_0 ),
        .I4(\complex_num_writes[0]_i_4_n_0 ),
        .O(\complex_num_writes[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0302030003020302)) 
    \complex_num_writes[2]_i_1 
       (.I0(\complex_num_writes[4]_i_6_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__22),
        .I2(complex_row1_rd_done_reg_0),
        .I3(\complex_num_writes[4]_i_11_n_0 ),
        .I4(\complex_num_writes[2]_i_2_n_0 ),
        .I5(\complex_num_writes[2]_i_3_n_0 ),
        .O(\complex_num_writes[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \complex_num_writes[2]_i_2 
       (.I0(\complex_num_reads[1]_i_4_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\complex_num_writes[2]_i_4_n_0 ),
        .I3(\complex_num_writes[3]_i_3_n_0 ),
        .O(\complex_num_writes[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h8787FF87)) 
    \complex_num_writes[2]_i_3 
       (.I0(\complex_num_writes_reg_n_0_[0] ),
        .I1(\complex_num_writes_reg_n_0_[1] ),
        .I2(\complex_num_writes_reg_n_0_[2] ),
        .I3(\complex_num_writes[4]_i_5_n_0 ),
        .I4(\complex_num_writes[2]_i_5_n_0 ),
        .O(\complex_num_writes[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0001000100010101)) 
    \complex_num_writes[2]_i_4 
       (.I0(\complex_num_writes[0]_i_7_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_writes[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000700000000)) 
    \complex_num_writes[2]_i_5 
       (.I0(\complex_num_writes_reg_n_0_[1] ),
        .I1(\complex_num_writes_reg_n_0_[2] ),
        .I2(\complex_num_writes_reg_n_0_[3] ),
        .I3(\complex_num_writes_reg_n_0_[4] ),
        .I4(\complex_num_writes[0]_i_4_n_0 ),
        .I5(\complex_num_writes[4]_i_6_n_0 ),
        .O(\complex_num_writes[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h11110010)) 
    \complex_num_writes[3]_i_1 
       (.I0(complex_row1_rd_done_reg_0),
        .I1(rstdiv0_sync_r1_reg_rep__22),
        .I2(\complex_num_writes[4]_i_8_n_0 ),
        .I3(\complex_num_writes[3]_i_2_n_0 ),
        .I4(\complex_num_writes[4]_i_11_n_0 ),
        .O(\complex_num_writes[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF0BBAA)) 
    \complex_num_writes[3]_i_2 
       (.I0(\complex_num_writes[3]_i_3_n_0 ),
        .I1(\complex_num_reads[1]_i_4_n_0 ),
        .I2(\complex_num_writes[4]_i_15_n_0 ),
        .I3(\complex_num_writes[3]_i_4_n_0 ),
        .I4(\complex_num_reads[1]_i_3_n_0 ),
        .O(\complex_num_writes[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    \complex_num_writes[3]_i_3 
       (.I0(\complex_num_writes[4]_i_12_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I4(complex_sample_cnt_inc_i_2_n_0),
        .O(\complex_num_writes[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT4 #(
    .INIT(16'h9555)) 
    \complex_num_writes[3]_i_4 
       (.I0(\complex_num_writes_reg_n_0_[3] ),
        .I1(\complex_num_writes_reg_n_0_[0] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .O(\complex_num_writes[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF200)) 
    \complex_num_writes[4]_i_1 
       (.I0(\complex_num_writes[4]_i_3_n_0 ),
        .I1(\complex_num_writes_reg[4]_i_4_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .I3(\complex_num_writes[4]_i_6_n_0 ),
        .I4(\complex_num_writes[4]_i_7_n_0 ),
        .I5(complex_row0_rd_done1),
        .O(\complex_num_writes[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAABFFFFFFF)) 
    \complex_num_writes[4]_i_10 
       (.I0(\complex_num_reads[1]_i_4_n_0 ),
        .I1(\complex_num_writes_reg_n_0_[0] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes_reg_n_0_[3] ),
        .I5(\complex_num_writes_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \complex_num_writes[4]_i_11 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\complex_num_writes[4]_i_18_n_0 ),
        .I4(init_complete_r_i_3_n_0),
        .I5(complex_row0_wr_done),
        .O(\complex_num_writes[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0001000100010101)) 
    \complex_num_writes[4]_i_12 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\complex_num_writes[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAA88888)) 
    \complex_num_writes[4]_i_13 
       (.I0(\complex_num_reads[1]_i_5_n_0 ),
        .I1(\complex_num_writes_reg_n_0_[4] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes_reg_n_0_[3] ),
        .I5(\complex_num_writes[4]_i_12_n_0 ),
        .O(\complex_num_writes[4]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFE0)) 
    \complex_num_writes[4]_i_14 
       (.I0(\complex_num_writes_reg_n_0_[0] ),
        .I1(\complex_num_writes_reg_n_0_[1] ),
        .I2(\complex_num_writes_reg_n_0_[2] ),
        .I3(\complex_num_writes_reg_n_0_[4] ),
        .I4(\complex_num_writes_reg_n_0_[3] ),
        .O(\complex_num_writes[4]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h0000002000000000)) 
    \complex_num_writes[4]_i_15 
       (.I0(\complex_num_writes[4]_i_17_n_0 ),
        .I1(\complex_num_writes[4]_i_16_n_0 ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \complex_num_writes[4]_i_16 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .O(\complex_num_writes[4]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \complex_num_writes[4]_i_17 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\complex_num_writes[4]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \complex_num_writes[4]_i_18 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(\complex_num_writes[4]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h1111111100000010)) 
    \complex_num_writes[4]_i_2 
       (.I0(complex_row1_rd_done_reg_0),
        .I1(rstdiv0_sync_r1_reg_rep__22),
        .I2(\complex_num_writes[4]_i_8_n_0 ),
        .I3(\complex_num_writes[4]_i_9_n_0 ),
        .I4(\complex_num_writes[4]_i_10_n_0 ),
        .I5(\complex_num_writes[4]_i_11_n_0 ),
        .O(\complex_num_writes[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAABFFFFFFFFFFF)) 
    \complex_num_writes[4]_i_3 
       (.I0(\complex_num_reads[1]_i_4_n_0 ),
        .I1(\complex_num_writes_reg_n_0_[3] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes_reg_n_0_[4] ),
        .I5(\complex_num_writes[4]_i_12_n_0 ),
        .O(\complex_num_writes[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \complex_num_writes[4]_i_5 
       (.I0(\complex_num_writes[4]_i_15_n_0 ),
        .I1(\complex_num_writes[0]_i_4_n_0 ),
        .O(\complex_num_writes[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000400000000000)) 
    \complex_num_writes[4]_i_6 
       (.I0(complex_row0_wr_done),
        .I1(complex_wait_cnt_reg__0[3]),
        .I2(complex_wait_cnt_reg__0[2]),
        .I3(complex_wait_cnt_reg__0[1]),
        .I4(complex_wait_cnt_reg__0[0]),
        .I5(\complex_address[9]_i_4_n_0 ),
        .O(\complex_num_writes[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0040000000000000)) 
    \complex_num_writes[4]_i_7 
       (.I0(init_complete_r_i_3_n_0),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\complex_num_writes[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \complex_num_writes[4]_i_8 
       (.I0(\complex_num_writes[4]_i_6_n_0 ),
        .I1(\complex_num_writes[0]_i_4_n_0 ),
        .O(\complex_num_writes[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000040200000000)) 
    \complex_num_writes[4]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\complex_num_writes[4]_i_16_n_0 ),
        .I5(\complex_num_writes[4]_i_17_n_0 ),
        .O(\complex_num_writes[4]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \complex_num_writes_dec[0]_i_1 
       (.I0(complex_num_writes_dec_reg__0[0]),
        .I1(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[0] ),
        .O(p_0_in__8[0]));
  LUT4 #(
    .INIT(16'h9F90)) 
    \complex_num_writes_dec[1]_i_1 
       (.I0(complex_num_writes_dec_reg__0[0]),
        .I1(complex_num_writes_dec_reg__0[1]),
        .I2(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .O(p_0_in__8[1]));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT5 #(
    .INIT(32'hA9FFA900)) 
    \complex_num_writes_dec[2]_i_1 
       (.I0(complex_num_writes_dec_reg__0[2]),
        .I1(complex_num_writes_dec_reg__0[1]),
        .I2(complex_num_writes_dec_reg__0[0]),
        .I3(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[2] ),
        .O(p_0_in__8[2]));
  LUT6 #(
    .INIT(64'hAAA9FFFFAAA90000)) 
    \complex_num_writes_dec[3]_i_1 
       (.I0(complex_num_writes_dec_reg__0[3]),
        .I1(complex_num_writes_dec_reg__0[2]),
        .I2(complex_num_writes_dec_reg__0[0]),
        .I3(complex_num_writes_dec_reg__0[1]),
        .I4(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I5(\complex_num_writes_reg_n_0_[3] ),
        .O(p_0_in__8[3]));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDD5D)) 
    \complex_num_writes_dec[4]_i_2 
       (.I0(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I2(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I3(complex_num_writes_dec_reg__0[2]),
        .I4(complex_num_writes_dec_reg__0[3]),
        .I5(complex_num_writes_dec_reg__0[4]),
        .O(\complex_num_writes_dec[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hA9AAFFFFA9AA0000)) 
    \complex_num_writes_dec[4]_i_3 
       (.I0(complex_num_writes_dec_reg__0[4]),
        .I1(complex_num_writes_dec_reg__0[2]),
        .I2(complex_num_writes_dec_reg__0[3]),
        .I3(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I4(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I5(\complex_num_writes_reg_n_0_[4] ),
        .O(p_0_in__8[4]));
  LUT4 #(
    .INIT(16'h00BF)) 
    \complex_num_writes_dec[4]_i_4 
       (.I0(complex_row0_rd_done),
        .I1(\complex_wait_cnt[3]_i_6_n_0 ),
        .I2(\complex_address[9]_i_4_n_0 ),
        .I3(\complex_num_reads[3]_i_6_n_0 ),
        .O(\complex_num_writes_dec[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \complex_num_writes_dec[4]_i_5 
       (.I0(complex_num_writes_dec_reg__0[0]),
        .I1(complex_num_writes_dec_reg__0[1]),
        .O(\complex_num_writes_dec[4]_i_5_n_0 ));
  FDSE \complex_num_writes_dec_reg[0] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__8[0]),
        .Q(complex_num_writes_dec_reg__0[0]),
        .S(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[1] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__8[1]),
        .Q(complex_num_writes_dec_reg__0[1]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[2] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__8[2]),
        .Q(complex_num_writes_dec_reg__0[2]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[3] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__8[3]),
        .Q(complex_num_writes_dec_reg__0[3]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[4] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__8[4]),
        .Q(complex_num_writes_dec_reg__0[4]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_reg[0] 
       (.C(CLK),
        .CE(\complex_num_writes[4]_i_1_n_0 ),
        .D(\complex_num_writes[0]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[1] 
       (.C(CLK),
        .CE(\complex_num_writes[4]_i_1_n_0 ),
        .D(\complex_num_writes[1]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[2] 
       (.C(CLK),
        .CE(\complex_num_writes[4]_i_1_n_0 ),
        .D(\complex_num_writes[2]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[3] 
       (.C(CLK),
        .CE(\complex_num_writes[4]_i_1_n_0 ),
        .D(\complex_num_writes[3]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[4] 
       (.C(CLK),
        .CE(\complex_num_writes[4]_i_1_n_0 ),
        .D(\complex_num_writes[4]_i_2_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[4] ),
        .R(1'b0));
  MUXF7 \complex_num_writes_reg[4]_i_4 
       (.I0(\complex_num_writes[4]_i_13_n_0 ),
        .I1(\complex_num_writes[4]_i_14_n_0 ),
        .O(\complex_num_writes_reg[4]_i_4_n_0 ),
        .S(\complex_num_reads[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAAE)) 
    complex_ocal_odt_ext_i_1
       (.I0(complex_ocal_odt_ext),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(\init_state_r[2]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(complex_ocal_odt_ext_i_2_n_0),
        .O(complex_ocal_odt_ext_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFC0500050)) 
    complex_ocal_odt_ext_i_2
       (.I0(complex_ocal_odt_ext_i_3_n_0),
        .I1(complex_ocal_odt_ext_i_4_n_0),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(cnt_cmd_done_m7_r),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(complex_ocal_odt_ext_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT5 #(
    .INIT(32'hFFEFFFFF)) 
    complex_ocal_odt_ext_i_3
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .O(complex_ocal_odt_ext_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'h00000100)) 
    complex_ocal_odt_ext_i_4
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(complex_ocal_odt_ext_i_4_n_0));
  FDRE complex_ocal_odt_ext_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_ocal_odt_ext_i_1_n_0),
        .Q(complex_ocal_odt_ext),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAEAAAAAAAAAA)) 
    complex_ocal_reset_rd_addr_i_1
       (.I0(rdlvl_stg1_done_reg),
        .I1(complex_wait_cnt_reg__0[0]),
        .I2(complex_wait_cnt_reg__0[1]),
        .I3(complex_wait_cnt_reg__0[3]),
        .I4(complex_wait_cnt_reg__0[2]),
        .I5(complex_ocal_reset_rd_addr_i_2_n_0),
        .O(complex_ocal_reset_rd_addr0));
  LUT6 #(
    .INIT(64'h2000000000000000)) 
    complex_ocal_reset_rd_addr_i_2
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(complex_ocal_reset_rd_addr_i_2_n_0));
  FDRE complex_ocal_reset_rd_addr_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_ocal_reset_rd_addr0),
        .Q(complex_ocal_reset_rd_addr_reg_n_0),
        .R(1'b0));
  FDRE complex_oclkdelay_calib_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_done_reg_0),
        .Q(complex_oclkdelay_calib_done_r1),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000800)) 
    complex_oclkdelay_calib_start_int_i_1
       (.I0(prbs_last_byte_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I5(complex_oclkdelay_calib_start_int),
        .O(complex_oclkdelay_calib_start_int_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT4 #(
    .INIT(16'hFDFF)) 
    complex_oclkdelay_calib_start_int_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .O(complex_oclkdelay_calib_start_int_i_2_n_0));
  FDRE complex_oclkdelay_calib_start_int_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_oclkdelay_calib_start_int_i_1_n_0),
        .Q(complex_oclkdelay_calib_start_int),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE complex_oclkdelay_calib_start_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_oclkdelay_calib_start_int),
        .Q(complex_oclkdelay_calib_start_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000AAEA)) 
    complex_odt_ext_i_1
       (.I0(complex_odt_ext),
        .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I2(prbs_last_byte_done_r),
        .I3(complex_odt_ext_i_2_n_0),
        .I4(complex_row1_rd_done_i_2_n_0),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(complex_odt_ext_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    complex_odt_ext_i_2
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(complex_sample_cnt_inc_i_3_n_0),
        .I4(complex_sample_cnt_inc_i_2_n_0),
        .O(complex_odt_ext_i_2_n_0));
  FDRE complex_odt_ext_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_odt_ext_i_1_n_0),
        .Q(complex_odt_ext),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000EAAA)) 
    complex_row0_rd_done_i_1
       (.I0(complex_row0_rd_done),
        .I1(complex_row1_wr_done0),
        .I2(complex_oclkdelay_calib_start_int),
        .I3(complex_row1_wr_done),
        .I4(complex_row0_rd_done1),
        .I5(complex_sample_cnt_inc_reg_n_0),
        .O(complex_row0_rd_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    complex_row0_rd_done_i_2
       (.I0(complex_row0_wr_done),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(complex_sample_cnt_inc_i_3_n_0),
        .I5(wr_victim_inc_i_3_n_0),
        .O(complex_row1_wr_done0));
  FDRE complex_row0_rd_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_row0_rd_done_i_1_n_0),
        .Q(complex_row0_rd_done),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000A6)) 
    \complex_row1_rd_cnt[0]_i_1 
       (.I0(complex_row1_rd_cnt[0]),
        .I1(complex_row1_rd_done),
        .I2(complex_row1_rd_done_r1),
        .I3(complex_row1_rd_done_reg_0),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .O(\complex_row1_rd_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000009AAA)) 
    \complex_row1_rd_cnt[1]_i_1 
       (.I0(complex_row1_rd_cnt[1]),
        .I1(complex_row1_rd_done_r1),
        .I2(complex_row1_rd_done),
        .I3(complex_row1_rd_cnt[0]),
        .I4(complex_row1_rd_done_reg_0),
        .I5(rstdiv0_sync_r1_reg_rep__21),
        .O(\complex_row1_rd_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000009AAAAAAA)) 
    \complex_row1_rd_cnt[2]_i_1 
       (.I0(complex_row1_rd_cnt[2]),
        .I1(complex_row1_rd_done_r1),
        .I2(complex_row1_rd_done),
        .I3(complex_row1_rd_cnt[1]),
        .I4(complex_row1_rd_cnt[0]),
        .I5(complex_row0_rd_done1),
        .O(\complex_row1_rd_cnt[2]_i_1_n_0 ));
  FDRE \complex_row1_rd_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[0]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[0]),
        .R(1'b0));
  FDRE \complex_row1_rd_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[1]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[1]),
        .R(1'b0));
  FDRE \complex_row1_rd_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[2]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000000000AE)) 
    complex_row1_rd_done_i_1
       (.I0(complex_row1_rd_done),
        .I1(complex_row0_rd_done),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(complex_row1_rd_done_i_2_n_0),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .I5(complex_row1_rd_done_reg_0),
        .O(complex_row1_rd_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    complex_row1_rd_done_i_2
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(complex_row1_rd_done_i_2_n_0));
  FDRE complex_row1_rd_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_row1_rd_done),
        .Q(complex_row1_rd_done_r1),
        .R(1'b0));
  FDRE complex_row1_rd_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_row1_rd_done_i_1_n_0),
        .Q(complex_row1_rd_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \complex_row_cnt_ocal[0]_i_1 
       (.I0(complex_row_cnt_ocal_reg__0[0]),
        .O(p_0_in__5[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \complex_row_cnt_ocal[1]_i_1 
       (.I0(complex_row_cnt_ocal_reg__0[0]),
        .I1(complex_row_cnt_ocal_reg__0[1]),
        .O(p_0_in__5[1]));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \complex_row_cnt_ocal[2]_i_1 
       (.I0(complex_row_cnt_ocal_reg__0[2]),
        .I1(complex_row_cnt_ocal_reg__0[1]),
        .I2(complex_row_cnt_ocal_reg__0[0]),
        .O(p_0_in__5[2]));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \complex_row_cnt_ocal[3]_i_1 
       (.I0(complex_row_cnt_ocal_reg__0[3]),
        .I1(complex_row_cnt_ocal_reg__0[0]),
        .I2(complex_row_cnt_ocal_reg__0[1]),
        .I3(complex_row_cnt_ocal_reg__0[2]),
        .O(p_0_in__5[3]));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \complex_row_cnt_ocal[4]_i_1 
       (.I0(complex_row_cnt_ocal_reg__0[4]),
        .I1(complex_row_cnt_ocal_reg__0[2]),
        .I2(complex_row_cnt_ocal_reg__0[1]),
        .I3(complex_row_cnt_ocal_reg__0[0]),
        .I4(complex_row_cnt_ocal_reg__0[3]),
        .O(p_0_in__5[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \complex_row_cnt_ocal[5]_i_1 
       (.I0(complex_row_cnt_ocal_reg__0[5]),
        .I1(complex_row_cnt_ocal_reg__0[3]),
        .I2(complex_row_cnt_ocal_reg__0[0]),
        .I3(complex_row_cnt_ocal_reg__0[1]),
        .I4(complex_row_cnt_ocal_reg__0[2]),
        .I5(complex_row_cnt_ocal_reg__0[4]),
        .O(p_0_in__5[5]));
  LUT4 #(
    .INIT(16'h6AAA)) 
    \complex_row_cnt_ocal[6]_i_1 
       (.I0(complex_row_cnt_ocal_reg__0[6]),
        .I1(complex_row_cnt_ocal_reg__0[4]),
        .I2(\complex_row_cnt_ocal[7]_i_5_n_0 ),
        .I3(complex_row_cnt_ocal_reg__0[5]),
        .O(p_0_in__5[6]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF40FF)) 
    \complex_row_cnt_ocal[7]_i_1 
       (.I0(\complex_row_cnt_ocal[7]_i_4_n_0 ),
        .I1(wr_victim_inc),
        .I2(\complex_row_cnt_ocal[7]_i_5_n_0 ),
        .I3(prbs_last_byte_done_r),
        .I4(complex_byte_rd_done),
        .I5(complex_row0_rd_done1),
        .O(complex_row_cnt_ocal0));
  LUT5 #(
    .INIT(32'hAAAAAA80)) 
    \complex_row_cnt_ocal[7]_i_2 
       (.I0(\complex_row_cnt_ocal[7]_i_6_n_0 ),
        .I1(\complex_row_cnt_ocal[7]_i_7_n_0 ),
        .I2(\complex_row_cnt_ocal[7]_i_8_n_0 ),
        .I3(wr_victim_inc),
        .I4(complex_sample_cnt_inc_r2),
        .O(\complex_row_cnt_ocal[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \complex_row_cnt_ocal[7]_i_3 
       (.I0(complex_row_cnt_ocal_reg__0[7]),
        .I1(complex_row_cnt_ocal_reg__0[5]),
        .I2(\complex_row_cnt_ocal[7]_i_5_n_0 ),
        .I3(complex_row_cnt_ocal_reg__0[4]),
        .I4(complex_row_cnt_ocal_reg__0[6]),
        .O(p_0_in__5[7]));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \complex_row_cnt_ocal[7]_i_4 
       (.I0(complex_row_cnt_ocal_reg__0[5]),
        .I1(complex_row_cnt_ocal_reg__0[4]),
        .I2(complex_row_cnt_ocal_reg__0[7]),
        .I3(complex_row_cnt_ocal_reg__0[6]),
        .O(\complex_row_cnt_ocal[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \complex_row_cnt_ocal[7]_i_5 
       (.I0(complex_row_cnt_ocal_reg__0[3]),
        .I1(complex_row_cnt_ocal_reg__0[0]),
        .I2(complex_row_cnt_ocal_reg__0[1]),
        .I3(complex_row_cnt_ocal_reg__0[2]),
        .O(\complex_row_cnt_ocal[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \complex_row_cnt_ocal[7]_i_6 
       (.I0(complex_row_cnt_ocal_reg__0[5]),
        .I1(complex_row_cnt_ocal_reg__0[4]),
        .I2(complex_row_cnt_ocal_reg__0[7]),
        .I3(complex_row_cnt_ocal_reg__0[6]),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(\complex_row_cnt_ocal[7]_i_5_n_0 ),
        .O(\complex_row_cnt_ocal[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \complex_row_cnt_ocal[7]_i_7 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\wrcal_reads[7]_i_5_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\complex_row_cnt_ocal[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000040000000000)) 
    \complex_row_cnt_ocal[7]_i_8 
       (.I0(\complex_row_cnt_ocal[7]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(complex_sample_cnt_inc_i_3_n_0),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\complex_row_cnt_ocal[7]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \complex_row_cnt_ocal[7]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\complex_row_cnt_ocal[7]_i_9_n_0 ));
  FDRE \complex_row_cnt_ocal_reg[0] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[0]),
        .Q(complex_row_cnt_ocal_reg__0[0]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[1] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[1]),
        .Q(complex_row_cnt_ocal_reg__0[1]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[2] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[2]),
        .Q(complex_row_cnt_ocal_reg__0[2]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[3] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[3]),
        .Q(complex_row_cnt_ocal_reg__0[3]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[4] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[4]),
        .Q(complex_row_cnt_ocal_reg__0[4]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[5] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[5]),
        .Q(complex_row_cnt_ocal_reg__0[5]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[6] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[6]),
        .Q(complex_row_cnt_ocal_reg__0[6]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[7] 
       (.C(CLK),
        .CE(\complex_row_cnt_ocal[7]_i_2_n_0 ),
        .D(p_0_in__5[7]),
        .Q(complex_row_cnt_ocal_reg__0[7]),
        .R(complex_row_cnt_ocal0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    complex_sample_cnt_inc_i_1
       (.I0(complex_row1_rd_done),
        .I1(complex_sample_cnt_inc_i_2_n_0),
        .I2(complex_sample_cnt_inc_i_3_n_0),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .O(complex_sample_cnt_inc0));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    complex_sample_cnt_inc_i_2
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(complex_sample_cnt_inc_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    complex_sample_cnt_inc_i_3
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .O(complex_sample_cnt_inc_i_3_n_0));
  FDRE complex_sample_cnt_inc_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_sample_cnt_inc_reg_n_0),
        .Q(complex_sample_cnt_inc_r1),
        .R(1'b0));
  FDRE complex_sample_cnt_inc_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_sample_cnt_inc_r1),
        .Q(complex_sample_cnt_inc_r2),
        .R(1'b0));
  FDRE complex_sample_cnt_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_sample_cnt_inc0),
        .Q(complex_sample_cnt_inc_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT1 #(
    .INIT(2'h1)) 
    \complex_wait_cnt[0]_i_1 
       (.I0(complex_wait_cnt_reg__0[0]),
        .O(p_0_in__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \complex_wait_cnt[1]_i_1 
       (.I0(complex_wait_cnt_reg__0[0]),
        .I1(complex_wait_cnt_reg__0[1]),
        .O(p_0_in__7[1]));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \complex_wait_cnt[2]_i_1 
       (.I0(complex_wait_cnt_reg__0[2]),
        .I1(complex_wait_cnt_reg__0[1]),
        .I2(complex_wait_cnt_reg__0[0]),
        .O(p_0_in__7[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0100)) 
    \complex_wait_cnt[3]_i_1 
       (.I0(\complex_wait_cnt[3]_i_3_n_0 ),
        .I1(complex_ocal_reset_rd_addr_i_2_n_0),
        .I2(\complex_wait_cnt[3]_i_4_n_0 ),
        .I3(\complex_wait_cnt[3]_i_5_n_0 ),
        .I4(\complex_wait_cnt[3]_i_6_n_0 ),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(\complex_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \complex_wait_cnt[3]_i_2 
       (.I0(complex_wait_cnt_reg__0[3]),
        .I1(complex_wait_cnt_reg__0[0]),
        .I2(complex_wait_cnt_reg__0[1]),
        .I3(complex_wait_cnt_reg__0[2]),
        .O(p_0_in__7[3]));
  LUT6 #(
    .INIT(64'h0000008000000000)) 
    \complex_wait_cnt[3]_i_3 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\complex_wait_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000200000000000)) 
    \complex_wait_cnt[3]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\complex_wait_cnt[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \complex_wait_cnt[3]_i_5 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r[0]_i_5_n_0 ),
        .O(\complex_wait_cnt[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \complex_wait_cnt[3]_i_6 
       (.I0(complex_wait_cnt_reg__0[1]),
        .I1(complex_wait_cnt_reg__0[0]),
        .I2(complex_wait_cnt_reg__0[3]),
        .I3(complex_wait_cnt_reg__0[2]),
        .O(\complex_wait_cnt[3]_i_6_n_0 ));
  FDRE \complex_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__7[0]),
        .Q(complex_wait_cnt_reg__0[0]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__7[1]),
        .Q(complex_wait_cnt_reg__0[1]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__7[2]),
        .Q(complex_wait_cnt_reg__0[2]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__7[3]),
        .Q(complex_wait_cnt_reg__0[3]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[0] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_1[0]),
        .O(\data_offset_1_i1_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[1] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_1[1]),
        .O(\data_offset_1_i1_reg[5] [1]));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_1[2]),
        .O(\data_offset_1_i1_reg[5] [2]));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[3] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_1[3]),
        .O(\data_offset_1_i1_reg[5] [3]));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[4]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[4] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_1[4]),
        .O(\data_offset_1_i1_reg[5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_1_reg[5] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_1[5]),
        .O(\data_offset_1_i1_reg[5] [5]));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_2[0]),
        .O(\data_offset_2_i1_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[1] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_2[1]),
        .O(\data_offset_2_i1_reg[5] [1]));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[2] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_2[2]),
        .O(\data_offset_2_i1_reg[5] [2]));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[3] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_2[3]),
        .O(\data_offset_2_i1_reg[5] [3]));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[4]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[4] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_2[4]),
        .O(\data_offset_2_i1_reg[5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[5] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(calib_data_offset_2[5]),
        .O(\data_offset_2_i1_reg[5] [5]));
  LUT6 #(
    .INIT(64'h0020FFEF00200020)) 
    ddr2_pre_flag_r_i_1
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(ddr2_pre_flag_r_i_2_n_0),
        .I5(ddr2_pre_flag_r_reg_n_0),
        .O(ddr2_pre_flag_r_i_1_n_0));
  LUT5 #(
    .INIT(32'h40000000)) 
    ddr2_pre_flag_r_i_2
       (.I0(ddr2_pre_flag_r_i_3_n_0),
        .I1(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I2(cnt_cmd_done_r),
        .I3(cnt_init_mr_done_r),
        .I4(ddr2_refresh_flag_r_reg_n_0),
        .O(ddr2_pre_flag_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    ddr2_pre_flag_r_i_3
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(ddr2_pre_flag_r_i_3_n_0));
  FDRE ddr2_pre_flag_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ddr2_pre_flag_r_i_1_n_0),
        .Q(ddr2_pre_flag_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hCCDCDCDCDCDCDCDC)) 
    ddr2_refresh_flag_r_i_1
       (.I0(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I1(cnt_init_mr_r1),
        .I2(ddr2_refresh_flag_r_reg_n_0),
        .I3(cnt_init_mr_done_r),
        .I4(cnt_cmd_done_r),
        .I5(ddr2_refresh_flag_r_i_2_n_0),
        .O(ddr2_refresh_flag_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000010000000000)) 
    ddr2_refresh_flag_r_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(ddr2_refresh_flag_r_i_2_n_0));
  FDRE ddr2_refresh_flag_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ddr2_refresh_flag_r_i_1_n_0),
        .Q(ddr2_refresh_flag_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF08000000)) 
    ddr3_lm_done_r_i_1
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(wrcal_done_reg),
        .I5(ddr3_lm_done_r),
        .O(ddr3_lm_done_r_i_1_n_0));
  FDRE ddr3_lm_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ddr3_lm_done_r_i_1_n_0),
        .Q(ddr3_lm_done_r),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    detect_pi_found_dqs_i_1
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I2(detect_pi_found_dqs_i_3_n_0),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\cnt_cmd_r[6]_i_3_n_0 ),
        .I5(\cnt_cmd_r_reg_n_0_[6] ),
        .O(detect_pi_found_dqs0));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT2 #(
    .INIT(4'h2)) 
    detect_pi_found_dqs_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(detect_pi_found_dqs_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT2 #(
    .INIT(4'hB)) 
    detect_pi_found_dqs_i_3
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[4] ),
        .O(detect_pi_found_dqs_i_3_n_0));
  FDRE detect_pi_found_dqs_reg
       (.C(CLK),
        .CE(1'b1),
        .D(detect_pi_found_dqs0),
        .Q(detect_pi_found_dqs),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT6 #(
    .INIT(64'h00000000E6E600E6)) 
    \dqs_asrt_cnt[0]_i_1 
       (.I0(dqs_asrt_cnt[0]),
        .I1(wr_level_dqs_asrt),
        .I2(dqs_asrt_cnt[1]),
        .I3(wrlvl_done_r),
        .I4(wrlvl_done_r1),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(\dqs_asrt_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EAEA00EA)) 
    \dqs_asrt_cnt[1]_i_1 
       (.I0(dqs_asrt_cnt[1]),
        .I1(dqs_asrt_cnt[0]),
        .I2(wr_level_dqs_asrt),
        .I3(wrlvl_done_r),
        .I4(wrlvl_done_r1),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(\dqs_asrt_cnt[1]_i_1_n_0 ));
  FDRE \dqs_asrt_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqs_asrt_cnt[0]_i_1_n_0 ),
        .Q(dqs_asrt_cnt[0]),
        .R(1'b0));
  FDRE \dqs_asrt_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqs_asrt_cnt[1]_i_1_n_0 ),
        .Q(dqs_asrt_cnt[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000005554)) 
    \en_cnt_div4.enable_wrlvl_cnt[0]_i_1 
       (.I0(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ),
        .I2(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ),
        .I3(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ),
        .I4(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000009998)) 
    \en_cnt_div4.enable_wrlvl_cnt[1]_i_1 
       (.I0(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ),
        .I2(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ),
        .I3(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ),
        .I4(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ),
        .I5(rstdiv0_sync_r1_reg_rep__21),
        .O(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT5 #(
    .INIT(32'hFFFFEE10)) 
    \en_cnt_div4.enable_wrlvl_cnt[2]_i_1 
       (.I0(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ),
        .I2(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ),
        .I3(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ),
        .I4(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT5 #(
    .INIT(32'hFFFFF0E0)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_1 
       (.I0(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ),
        .I2(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ),
        .I3(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ),
        .I4(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0008FFFF00080008)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_2 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(wrlvl_odt_ctl_i_3_n_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0 ),
        .I5(wrlvl_odt),
        .O(\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_3 
       (.I0(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ),
        .I2(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ),
        .I3(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0 ));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ),
        .Q(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ),
        .Q(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ),
        .Q(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ),
        .Q(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT4 #(
    .INIT(16'h000E)) 
    \en_cnt_div4.wrlvl_odt_i_1 
       (.I0(wrlvl_odt),
        .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I2(wrlvl_odt_ctl),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\en_cnt_div4.wrlvl_odt_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \en_cnt_div4.wrlvl_odt_i_2 
       (.I0(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[1] ),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[0] ),
        .I2(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[3] ),
        .I3(\en_cnt_div4.enable_wrlvl_cnt_reg_n_0_[2] ),
        .O(\en_cnt_div4.wrlvl_odt_i_2_n_0 ));
  FDRE \en_cnt_div4.wrlvl_odt_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.wrlvl_odt_i_1_n_0 ),
        .Q(wrlvl_odt),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF47FF)) 
    \entry_cnt[4]_i_3__5 
       (.I0(mc_wrdata_en),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[7] ),
        .I3(B_of_data_full),
        .I4(\my_full_reg[4] ),
        .O(\entry_cnt_reg[3] ));
  LUT5 #(
    .INIT(32'hFFFF47FF)) 
    \entry_cnt[4]_i_3__6 
       (.I0(mc_wrdata_en),
        .I1(init_calib_complete_reg_rep__9),
        .I2(\my_empty_reg[7] ),
        .I3(C_of_data_full),
        .I4(\my_full_reg[4]_0 ),
        .O(\entry_cnt_reg[3]_0 ));
  LUT4 #(
    .INIT(16'hFFF4)) 
    first_rdlvl_pat_r_i_1
       (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I1(first_rdlvl_pat_r),
        .I2(rdlvl_stg1_rank_done),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .O(first_rdlvl_pat_r_i_1_n_0));
  FDRE first_rdlvl_pat_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(first_rdlvl_pat_r_i_1_n_0),
        .Q(first_rdlvl_pat_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFD0)) 
    first_wrcal_pat_r_i_1
       (.I0(first_wrcal_pat_r_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(first_wrcal_pat_r),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .I4(wrcal_resume_w),
        .I5(first_wrcal_pat_r_i_3_n_0),
        .O(first_wrcal_pat_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    first_wrcal_pat_r_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(first_wrcal_pat_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    first_wrcal_pat_r_i_3
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\wrcal_reads[7]_i_5_n_0 ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(first_wrcal_pat_r_i_3_n_0));
  FDRE first_wrcal_pat_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(first_wrcal_pat_r_i_1_n_0),
        .Q(first_wrcal_pat_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0888888888888888)) 
    \gen_byte_sel_div2.calib_in_common_i_5 
       (.I0(pi_calib_done),
        .I1(dqs_found_done_r_reg),
        .I2(wr_level_done_reg),
        .I3(rdlvl_stg1_done_reg_0),
        .I4(wrcal_done_reg),
        .I5(tempmon_sel_pi_incdec),
        .O(\gen_byte_sel_div2.calib_in_common_reg ));
  LUT5 #(
    .INIT(32'hFFFF7500)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDDDFFFDF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .I2(phy_address[42]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\complex_address_reg_n_0_[0] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hCDCC)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ),
        .I1(reg_ctrl_cnt_r_reg__0[3]),
        .I2(reg_ctrl_cnt_r_reg__0[0]),
        .I3(init_state_r),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h02A2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I1(phy_address[42]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\complex_address_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT5 #(
    .INIT(32'hFFFFFF47)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6 
       (.I0(complex_row_cnt_ocal_reg__0[0]),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I3(first_wrcal_pat_r_i_2_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT5 #(
    .INIT(32'hDCCCCCFC)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\cnt_dllk_zqinit_r[7]_i_1_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000200)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I3(\init_state_r[0]_i_5_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_3 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\wrcal_reads[7]_i_4_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hBFBBAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4444454444444444)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2 
       (.I0(init_state_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ),
        .I4(reg_ctrl_cnt_r_reg__0[3]),
        .I5(reg_ctrl_cnt_r_reg__0[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDDDFFFDF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .I2(phy_address[43]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\complex_address_reg_n_0_[1] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT4 #(
    .INIT(16'hCDCC)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0040000000000010)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h02A2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I1(phy_address[43]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\complex_address_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF47)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7 
       (.I0(complex_row_cnt_ocal_reg__0[1]),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I3(first_wrcal_pat_r_i_2_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7500)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDDDFFFDF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .I2(phy_address[44]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\complex_address_reg_n_0_[2] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hCDCC)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000888F)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4 
       (.I0(\gen_rnk[0].mr1_r_reg[0]_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),
        .I4(init_state_r),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h02A2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I1(phy_address[44]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\complex_address_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF47)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6 
       (.I0(complex_row_cnt_ocal_reg__0[2]),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I3(first_wrcal_pat_r_i_2_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFF7BF7EFFFFFF7F)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00005555FFFFFEFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ),
        .I1(reg_ctrl_cnt_r_reg__0[3]),
        .I2(reg_ctrl_cnt_r_reg__0[1]),
        .I3(reg_ctrl_cnt_r_reg__0[2]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_3_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT4 #(
    .INIT(16'h6EEF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'h02A2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFDFD5)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\complex_address_reg_n_0_[3] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I3(phy_address[45]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAABA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(read_calib_i_2_n_0),
        .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I3(rdlvl_start_pre_i_2_n_0),
        .I4(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF10FFFFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAEBFFFFFAEBF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5 
       (.I0(first_wrcal_pat_r_i_2_n_0),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(complex_row_cnt_ocal_reg__0[3]),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),
        .I5(burst_addr_r_reg_n_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I1(phy_address[45]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\complex_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hCEFFCECECCCCCCCC)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_10 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h54FF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2 
       (.I0(complex_row0_rd_done),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[7]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEBFFEBAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .I1(\complex_address_reg_n_0_[3] ),
        .I2(\complex_address_reg_n_0_[4] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT5 #(
    .INIT(32'h30753030)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5 
       (.I0(phy_address[45]),
        .I1(phy_address[46]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h66666666666606F6)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6 
       (.I0(phy_address[45]),
        .I1(phy_address[46]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_10_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF47)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7 
       (.I0(complex_row_cnt_ocal_reg__0[4]),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I3(first_wrcal_pat_r_i_2_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9 
       (.I0(\complex_address_reg_n_0_[3] ),
        .I1(\complex_address_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0000C080CCCCCCCC)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hABABABAAAAAAABAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),
        .I2(first_wrcal_pat_r_i_2_n_0),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(complex_row_cnt_ocal_reg__0[5]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hA202020202A2A2A2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\complex_address_reg_n_0_[3] ),
        .I4(\complex_address_reg_n_0_[4] ),
        .I5(\complex_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDDDFFFDF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5 
       (.I0(phy_address[47]),
        .I1(phy_address[46]),
        .I2(phy_address[45]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6 
       (.I0(\complex_address_reg_n_0_[5] ),
        .I1(\complex_address_reg_n_0_[4] ),
        .I2(\complex_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7500)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF47)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10 
       (.I0(complex_row_cnt_ocal_reg__0[6]),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I3(first_wrcal_pat_r_i_2_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAAAEAEAEAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13_n_0 ),
        .I1(cnt_init_mr_r[1]),
        .I2(cnt_init_mr_r[0]),
        .I3(dqs_found_done_r_reg),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000020004)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDDDFFFDF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30753030)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT4 #(
    .INIT(16'h00CE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT4 #(
    .INIT(16'h0200)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .I3(\gen_rnk[0].mr1_r_reg[0]_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAABAAAAAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(rdlvl_stg1_done_reg_0),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7 
       (.I0(phy_address[48]),
        .I1(phy_address[45]),
        .I2(phy_address[46]),
        .I3(phy_address[47]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8 
       (.I0(\complex_address_reg_n_0_[6] ),
        .I1(\complex_address_reg_n_0_[3] ),
        .I2(\complex_address_reg_n_0_[4] ),
        .I3(\complex_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAFFFF6AAA0000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9 
       (.I0(\complex_address_reg_n_0_[6] ),
        .I1(\complex_address_reg_n_0_[3] ),
        .I2(\complex_address_reg_n_0_[4] ),
        .I3(\complex_address_reg_n_0_[5] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hC0C0CCC8C0C0C0C0)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFFFFFBB7FEEEF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0020000000000222)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12 
       (.I0(\complex_address_reg_n_0_[7] ),
        .I1(\complex_address_reg_n_0_[5] ),
        .I2(\complex_address_reg_n_0_[4] ),
        .I3(\complex_address_reg_n_0_[3] ),
        .I4(\complex_address_reg_n_0_[6] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13 
       (.I0(phy_address[49]),
        .I1(phy_address[47]),
        .I2(phy_address[46]),
        .I3(phy_address[45]),
        .I4(phy_address[48]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAEAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I4(\init_state_r[0]_i_5_n_0 ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I2(p_0_in14_in),
        .I3(burst_addr_r_i_5_n_0),
        .I4(first_wrcal_pat_r_i_2_n_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT5 #(
    .INIT(32'h00000200)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),
        .I1(oclk_wr_cnt_reg__0[0]),
        .I2(oclk_wr_cnt_reg__0[1]),
        .I3(oclk_wr_cnt_reg__0[2]),
        .I4(oclk_wr_cnt_reg__0[3]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h0000444044444444)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .I4(complex_row0_rd_done),
        .I5(\complex_row_cnt_ocal[7]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF4F4FF4444444444)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4 
       (.I0(init_state_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hABABABAAAAAAABAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),
        .I2(first_wrcal_pat_r_i_2_n_0),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(complex_row_cnt_ocal_reg__0[7]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h02A2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000040C00)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9 
       (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4700)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h9555555555555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2 
       (.I0(\complex_address_reg_n_0_[8] ),
        .I1(\complex_address_reg_n_0_[6] ),
        .I2(\complex_address_reg_n_0_[3] ),
        .I3(\complex_address_reg_n_0_[4] ),
        .I4(\complex_address_reg_n_0_[5] ),
        .I5(\complex_address_reg_n_0_[7] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9555555555555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3 
       (.I0(phy_address[50]),
        .I1(phy_address[48]),
        .I2(phy_address[45]),
        .I3(phy_address[46]),
        .I4(phy_address[47]),
        .I5(phy_address[49]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000800080008000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_2_n_0 ),
        .I2(cnt_init_mr_r[1]),
        .I3(cnt_init_mr_r[0]),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(dqs_found_done_r_reg),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h02A2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF8A80)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(init_state_r),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11 
       (.I0(init_state_r1[3]),
        .I1(wrlvl_odt_ctl_i_4_n_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12 
       (.I0(phy_address[49]),
        .I1(phy_address[47]),
        .I2(phy_address[46]),
        .I3(phy_address[45]),
        .I4(phy_address[48]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'h55545555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(init_state_r1[1]),
        .I2(init_state_r1[6]),
        .I3(init_state_r1[2]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16 
       (.I0(wrcal_wr_cnt_reg__0[0]),
        .I1(wrcal_wr_cnt_reg__0[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0010)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17 
       (.I0(\init_state_r[2]_i_4_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(init_complete_r_i_2_n_0),
        .I4(p_0_in14_in),
        .I5(burst_addr_r_i_5_n_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18 
       (.I0(oclk_wr_cnt_reg__0[3]),
        .I1(oclk_wr_cnt_reg__0[2]),
        .I2(oclk_wr_cnt_reg__0[1]),
        .I3(oclk_wr_cnt_reg__0[0]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19 
       (.I0(init_state_r1[0]),
        .I1(init_state_r1[5]),
        .I2(init_state_r1[3]),
        .I3(init_state_r1[4]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3 
       (.I0(\complex_address_reg_n_0_[9] ),
        .I1(\complex_address_reg_n_0_[8] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5 
       (.I0(phy_address[51]),
        .I1(phy_address[50]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h8888800080008000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_2_n_0 ),
        .I2(cnt_init_mr_r[1]),
        .I3(cnt_init_mr_r[0]),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(dqs_found_done_r_reg),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h2EEEE22200000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I3(\complex_address_reg_n_0_[8] ),
        .I4(\complex_address_reg_n_0_[9] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFD00FD00FFFFFD00)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8 
       (.I0(wrcal_wr_cnt_reg__0[2]),
        .I1(wrcal_wr_cnt_reg__0[3]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),
        .I3(first_wrcal_pat_r_i_2_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9 
       (.I0(\complex_address_reg_n_0_[7] ),
        .I1(\complex_address_reg_n_0_[5] ),
        .I2(\complex_address_reg_n_0_[4] ),
        .I3(\complex_address_reg_n_0_[3] ),
        .I4(\complex_address_reg_n_0_[6] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ),
        .Q(phy_address[42]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .Q(phy_address[52]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),
        .Q(phy_address[54]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ),
        .Q(phy_address[43]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ),
        .Q(phy_address[44]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ),
        .Q(phy_address[45]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ),
        .Q(phy_address[46]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ),
        .Q(phy_address[47]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ),
        .Q(phy_address[48]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ),
        .Q(phy_address[49]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ),
        .Q(phy_address[50]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ),
        .Q(phy_address[51]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000000011F1)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1 
       (.I0(init_complete_r_i_2_n_0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ),
        .O(bank_w[0]));
  LUT6 #(
    .INIT(64'hFFFFFF0000FFD7FF)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2 
       (.I0(rdlvl_stg1_done_reg_2),
        .I1(cnt_init_mr_r[0]),
        .I2(cnt_init_mr_r[1]),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT3 #(
    .INIT(8'hD7)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(bank_w[1]));
  LUT6 #(
    .INIT(64'hBE7FBE7EBE7FBE7F)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(cnt_init_mr_r[1]),
        .I5(rdlvl_stg1_done_reg_2),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000200000)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_3_n_0 ),
        .I2(reg_ctrl_cnt_r_reg__0[2]),
        .I3(reg_ctrl_cnt_r_reg__0[3]),
        .I4(reg_ctrl_cnt_r_reg__0[1]),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_4_n_0 ),
        .O(bank_w[2]));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_2 
       (.I0(init_state_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_3 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_4 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_4_n_0 ));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_w[0]),
        .Q(phy_bank[9]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_w[1]),
        .Q(phy_bank[10]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_w[2]),
        .Q(phy_bank[11]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \gen_reset_obuf.u_reset_obuf_i_1 
       (.I0(init_calib_complete_reg_rep__14),
        .I1(phy_reset_n),
        .O(mux_reset_n));
  FDRE \gen_rnk[0].mr1_r_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b1),
        .Q(\gen_rnk[0].mr1_r_reg[0]_0 ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE init_calib_complete_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r2),
        .Q(calib_complete),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE init_complete_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_reg_n_0),
        .Q(init_complete_r1),
        .R(rstdiv0_sync_r1_reg_rep__3));
  (* KEEP = "yes" *) 
  FDRE init_complete_r1_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_timing_reg_0),
        .Q(init_complete_r1_timing),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE init_complete_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r1),
        .Q(init_complete_r2),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000040)) 
    init_complete_r_i_1
       (.I0(init_complete_r_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(init_complete_r_i_3_n_0),
        .I5(init_complete_r_reg_n_0),
        .O(init_complete_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT2 #(
    .INIT(4'hE)) 
    init_complete_r_i_2
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(init_complete_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT2 #(
    .INIT(4'hB)) 
    init_complete_r_i_3
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(init_complete_r_i_3_n_0));
  FDRE init_complete_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_i_1_n_0),
        .Q(init_complete_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000040)) 
    init_complete_r_timing_i_1
       (.I0(init_complete_r_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(init_complete_r_i_3_n_0),
        .I5(init_complete_r_timing_orig),
        .O(init_complete_r_timing_i_1_n_0));
  (* KEEP = "yes" *) 
  FDRE init_complete_r_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_timing_i_1_n_0),
        .Q(init_complete_r_timing_orig),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \init_state_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[0] ),
        .Q(init_state_r1[0]),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[1] ),
        .Q(init_state_r1[1]),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[2] ),
        .Q(init_state_r1[2]),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[3] ),
        .Q(init_state_r1[3]),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[4] ),
        .Q(init_state_r1[4]),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[5] ),
        .Q(init_state_r1[5]),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(init_state_r),
        .Q(init_state_r1[6]),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT6 #(
    .INIT(64'h757F303F5555303F)) 
    \init_state_r[0]_i_1 
       (.I0(\init_state_r[0]_i_2_n_0 ),
        .I1(\init_state_r[0]_i_3_n_0 ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r[0]_i_4_n_0 ),
        .I4(init_state_r),
        .I5(\init_state_r[0]_i_5_n_0 ),
        .O(\init_state_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7F7F7F00FFFFFFFF)) 
    \init_state_r[0]_i_10 
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(ddr2_pre_flag_r_reg_n_0),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r[4]_i_23_n_0 ),
        .I4(\init_state_r[0]_i_22_n_0 ),
        .I5(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .O(\init_state_r[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0808080800000800)) 
    \init_state_r[0]_i_11 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r[3]_i_19_n_0 ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F7F3F7C3)) 
    \init_state_r[0]_i_12 
       (.I0(wrcal_sanity_chk_done_reg),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[1]_i_28_n_0 ),
        .I4(\init_state_r[0]_i_23_n_0 ),
        .I5(\init_state_r[0]_i_24_n_0 ),
        .O(\init_state_r[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BBFB)) 
    \init_state_r[0]_i_13 
       (.I0(\init_state_r[0]_i_25_n_0 ),
        .I1(\init_state_r[6]_i_6_n_0 ),
        .I2(\init_state_r[0]_i_26_n_0 ),
        .I3(\init_state_r[2]_i_20_n_0 ),
        .I4(\init_state_r[0]_i_27_n_0 ),
        .I5(\init_state_r[0]_i_28_n_0 ),
        .O(\init_state_r[0]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA000088A8)) 
    \init_state_r[0]_i_14 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_10_n_0 ),
        .I1(\init_state_r[0]_i_29_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ),
        .I3(complex_sample_cnt_inc_i_2_n_0),
        .I4(\init_state_r[6]_i_17_n_0 ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT5 #(
    .INIT(32'hBBBBFFBF)) 
    \init_state_r[0]_i_15 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(rdlvl_stg1_done_reg_0),
        .I3(prbs_last_byte_done_r),
        .I4(prech_pending_r_reg_0),
        .O(\init_state_r[0]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0400FFFF)) 
    \init_state_r[0]_i_16 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\complex_wait_cnt[3]_i_6_n_0 ),
        .O(\init_state_r[0]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAABAAAA)) 
    \init_state_r[0]_i_17 
       (.I0(\init_state_r[6]_i_20_n_0 ),
        .I1(rdlvl_stg1_done_reg_5),
        .I2(\init_state_r[0]_i_31_n_0 ),
        .I3(complex_num_reads_dec_reg__0[1]),
        .I4(complex_num_reads_dec_reg__0[0]),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h5D555D5500005D00)) 
    \init_state_r[0]_i_18 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I1(complex_row1_wr_done),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(\complex_wait_cnt[3]_i_6_n_0 ),
        .I4(rdlvl_stg1_done_reg_1),
        .I5(\init_state_r[6]_i_22_n_0 ),
        .O(\init_state_r[0]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \init_state_r[0]_i_19 
       (.I0(wrcal_resume_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(prech_pending_r_reg_0),
        .I3(wrcal_done_reg),
        .I4(wrlvl_byte_redo),
        .O(\init_state_r[0]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h0444444444444444)) 
    \init_state_r[0]_i_2 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(ocal_act_wait_cnt_reg__0[1]),
        .I3(ocal_act_wait_cnt_reg__0[0]),
        .I4(ocal_act_wait_cnt_reg__0[2]),
        .I5(ocal_act_wait_cnt_reg__0[3]),
        .O(\init_state_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0A0A3F3000000000)) 
    \init_state_r[0]_i_20 
       (.I0(init_next_state1110_out),
        .I1(burst_addr_r_reg_n_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h44444444C0C0CCC0)) 
    \init_state_r[0]_i_21 
       (.I0(\init_state_r[6]_i_29_n_0 ),
        .I1(\init_state_r[4]_i_27_n_0 ),
        .I2(\init_state_r[4]_i_41_n_0 ),
        .I3(cnt_cmd_done_r),
        .I4(wrcal_prech_req),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F2FFF2)) 
    \init_state_r[0]_i_22 
       (.I0(mem_init_done_r),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\init_state_r[4]_i_21_n_0 ),
        .I3(rdlvl_stg1_done_reg_3),
        .I4(\init_state_r[1]_i_31_n_0 ),
        .I5(\init_state_r[1]_i_30_n_0 ),
        .O(\init_state_r[0]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \init_state_r[0]_i_23 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(cnt_cmd_done_r),
        .I2(dqs_found_done_r_reg),
        .I3(pi_dqs_found_rank_done),
        .I4(prech_pending_r_reg_0),
        .O(\init_state_r[0]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h0202020200020202)) 
    \init_state_r[0]_i_24 
       (.I0(\init_state_r[0]_i_33_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(num_reads[0]),
        .I5(num_reads[1]),
        .O(\init_state_r[0]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h4000404044444444)) 
    \init_state_r[0]_i_25 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r[1]_i_28_n_0 ),
        .I2(dqs_found_done_r_reg),
        .I3(rdlvl_stg1_done_reg_0),
        .I4(rdlvl_last_byte_done),
        .I5(pi_calib_done),
        .O(\init_state_r[0]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT4 #(
    .INIT(16'hAA8A)) 
    \init_state_r[0]_i_26 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(reset_rd_addr_r1),
        .O(\init_state_r[0]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00001DFF)) 
    \init_state_r[0]_i_27 
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(wrlvl_rank_done_r7),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(init_complete_r_i_3_n_0),
        .I5(\init_state_r[0]_i_34_n_0 ),
        .O(\init_state_r[0]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h0054045450545454)) 
    \init_state_r[0]_i_28 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I1(\init_state_r[0]_i_35_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(cnt_txpr_done_r),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[0]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT5 #(
    .INIT(32'h8000FFFF)) 
    \init_state_r[0]_i_29 
       (.I0(complex_wait_cnt_reg__0[2]),
        .I1(complex_wait_cnt_reg__0[3]),
        .I2(complex_wait_cnt_reg__0[0]),
        .I3(complex_wait_cnt_reg__0[1]),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \init_state_r[0]_i_3 
       (.I0(\init_state_r[0]_i_6_n_0 ),
        .I1(\init_state_r[0]_i_7_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r[0]_i_8_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[0]_i_9_n_0 ),
        .O(\init_state_r[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[0]_i_31 
       (.I0(complex_num_reads_dec_reg__0[2]),
        .I1(complex_num_reads_dec_reg__0[3]),
        .O(\init_state_r[0]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT5 #(
    .INIT(32'hFEFEFFFE)) 
    \init_state_r[0]_i_33 
       (.I0(rdlvl_stg1_rank_done),
        .I1(prech_pending_r_reg_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(rdlvl_stg1_done_reg_0),
        .I4(prbs_last_byte_done_r),
        .O(\init_state_r[0]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'h08000C0C0C0C0C0C)) 
    \init_state_r[0]_i_34 
       (.I0(wrlvl_done_r1),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_34_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    \init_state_r[0]_i_35 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(phy_ctl_ready),
        .I2(cnt_pwron_cke_done_r),
        .I3(po_ck_addr_cmd_delay_done),
        .O(\init_state_r[0]_i_35_n_0 ));
  LUT6 #(
    .INIT(64'h2220FFFF22200000)) 
    \init_state_r[0]_i_4 
       (.I0(\init_state_r[0]_i_10_n_0 ),
        .I1(\init_state_r[0]_i_11_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r[0]_i_12_n_0 ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r[0]_i_13_n_0 ),
        .O(\init_state_r[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[0]_i_5 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B88888B888)) 
    \init_state_r[0]_i_6 
       (.I0(\init_state_r[0]_i_14_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r[0]_i_15_n_0 ),
        .I3(\init_state_r[0]_i_16_n_0 ),
        .I4(\init_state_r[0]_i_17_n_0 ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h2F2F202F3030303F)) 
    \init_state_r[0]_i_7 
       (.I0(\complex_wait_cnt[3]_i_6_n_0 ),
        .I1(\init_state_r[0]_i_18_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT5 #(
    .INIT(32'h0CCCDDDD)) 
    \init_state_r[0]_i_8 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r[6]_i_26_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FFFD)) 
    \init_state_r[0]_i_9 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[0]_i_19_n_0 ),
        .I3(\init_state_r[6]_i_13_n_0 ),
        .I4(\init_state_r[0]_i_20_n_0 ),
        .I5(\init_state_r[0]_i_21_n_0 ),
        .O(\init_state_r[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFF000000FF00FD00)) 
    \init_state_r[1]_i_1 
       (.I0(\init_state_r[1]_i_2_n_0 ),
        .I1(\init_state_r[1]_i_3_n_0 ),
        .I2(\init_state_r[1]_i_4_n_0 ),
        .I3(\init_state_r[1]_i_5_n_0 ),
        .I4(\init_state_r[1]_i_6_n_0 ),
        .I5(\init_state_r[2]_i_5_n_0 ),
        .O(\init_state_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000020222222)) 
    \init_state_r[1]_i_10 
       (.I0(\init_state_r[1]_i_21_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r[1]_i_22_n_0 ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r[1]_i_23_n_0 ),
        .I5(\init_state_r[1]_i_24_n_0 ),
        .O(\init_state_r[1]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT5 #(
    .INIT(32'h00C07777)) 
    \init_state_r[1]_i_11 
       (.I0(cnt_txpr_done_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r[1]_i_25_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT5 #(
    .INIT(32'hFD0D0F0F)) 
    \init_state_r[1]_i_12 
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(mem_init_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(wrlvl_rank_done_r7),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0B000F000A000FFF)) 
    \init_state_r[1]_i_13 
       (.I0(\init_state_r[1]_i_26_n_0 ),
        .I1(reset_rd_addr_r1),
        .I2(\init_state_r[1]_i_27_n_0 ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[1]_i_28_n_0 ),
        .O(\init_state_r[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h00CCCC8800CCCC08)) 
    \init_state_r[1]_i_14 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(ddr2_pre_flag_r_reg_n_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[1]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hEFEEEFEEFFFFEFEE)) 
    \init_state_r[1]_i_15 
       (.I0(\init_state_r[4]_i_23_n_0 ),
        .I1(\init_state_r[1]_i_29_n_0 ),
        .I2(rdlvl_stg1_done_reg_2),
        .I3(mem_init_done_r),
        .I4(\init_state_r[1]_i_30_n_0 ),
        .I5(\init_state_r[1]_i_31_n_0 ),
        .O(\init_state_r[1]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT3 #(
    .INIT(8'h5E)) 
    \init_state_r[1]_i_16 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAFFFEAAAAAFAE)) 
    \init_state_r[1]_i_17 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r[1]_i_32_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[1]_i_33_n_0 ),
        .I5(\init_state_r[1]_i_34_n_0 ),
        .O(\init_state_r[1]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \init_state_r[1]_i_18 
       (.I0(complex_wait_cnt_reg__0[1]),
        .I1(complex_wait_cnt_reg__0[0]),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(complex_wait_cnt_reg__0[2]),
        .I5(complex_wait_cnt_reg__0[3]),
        .O(\init_state_r[1]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h0110FFFF1110FFFF)) 
    \init_state_r[1]_i_19 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[1]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF1011FFFF)) 
    \init_state_r[1]_i_2 
       (.I0(\init_state_r[1]_i_7_n_0 ),
        .I1(\init_state_r[1]_i_8_n_0 ),
        .I2(\init_state_r[1]_i_9_n_0 ),
        .I3(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r[1]_i_10_n_0 ),
        .O(\init_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00CCDD0000CFDD00)) 
    \init_state_r[1]_i_20 
       (.I0(\complex_wait_cnt[3]_i_6_n_0 ),
        .I1(\init_state_r[6]_i_20_n_0 ),
        .I2(\init_state_r[1]_i_35_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(wr_victim_inc_i_3_n_0),
        .O(\init_state_r[1]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAAAFFFFEEFE)) 
    \init_state_r[1]_i_21 
       (.I0(init_complete_r_i_3_n_0),
        .I1(\init_state_r[0]_i_19_n_0 ),
        .I2(wrcal_resume_r),
        .I3(wrcal_final_chk),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT3 #(
    .INIT(8'h41)) 
    \init_state_r[1]_i_22 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDFFF)) 
    \init_state_r[1]_i_23 
       (.I0(oclk_wr_cnt_reg__0[0]),
        .I1(oclk_wr_cnt_reg__0[1]),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(oclk_wr_cnt_reg__0[2]),
        .I5(oclk_wr_cnt_reg__0[3]),
        .O(\init_state_r[1]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h000000000FECFFEC)) 
    \init_state_r[1]_i_24 
       (.I0(\init_state_r[6]_i_29_n_0 ),
        .I1(\init_state_r[5]_i_32_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(burst_addr_r_reg_n_0),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .O(\init_state_r[1]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT4 #(
    .INIT(16'h0070)) 
    \init_state_r[1]_i_25 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(dqs_found_done_r_reg),
        .I2(cnt_cmd_done_r),
        .I3(cnt_init_mr_done_r),
        .O(\init_state_r[1]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \init_state_r[1]_i_26 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r[5]_i_37_n_0 ),
        .I2(complex_num_writes_dec_reg__0[4]),
        .I3(complex_num_writes_dec_reg__0[1]),
        .O(\init_state_r[1]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h080808AA08080808)) 
    \init_state_r[1]_i_27 
       (.I0(\init_state_r[0]_i_5_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(pi_calib_done),
        .I3(rdlvl_last_byte_done),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(\init_state_r[1]_i_36_n_0 ),
        .O(\init_state_r[1]_i_27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[1]_i_28 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[1]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \init_state_r[1]_i_29 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h000002A2AAAA02A2)) 
    \init_state_r[1]_i_3 
       (.I0(\init_state_r[4]_i_8_n_0 ),
        .I1(\init_state_r[1]_i_11_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[1]_i_12_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[1]_i_13_n_0 ),
        .O(\init_state_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \init_state_r[1]_i_30 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(prbs_last_byte_done_r),
        .I2(mem_init_done_r),
        .I3(dqs_found_done_r_reg),
        .O(\init_state_r[1]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \init_state_r[1]_i_31 
       (.I0(num_refresh_reg__0[1]),
        .I1(num_refresh_reg__0[0]),
        .I2(num_refresh_reg__0[3]),
        .I3(num_refresh_reg__0[2]),
        .O(\init_state_r[1]_i_31_n_0 ));
  LUT6 #(
    .INIT(64'hBB00BB00BB00BB0F)) 
    \init_state_r[1]_i_32 
       (.I0(num_reads[1]),
        .I1(num_reads[0]),
        .I2(rdlvl_stg1_done_reg),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(prech_pending_r_reg_0),
        .I5(rdlvl_stg1_rank_done),
        .O(\init_state_r[1]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'h1111555511105555)) 
    \init_state_r[1]_i_33 
       (.I0(\init_state_r[2]_i_34_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(pi_dqs_found_rank_done),
        .I3(dqs_found_done_r_reg),
        .I4(cnt_cmd_done_r),
        .I5(prech_pending_r_reg_0),
        .O(\init_state_r[1]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'h1111011155555555)) 
    \init_state_r[1]_i_34 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(wrcal_sanity_chk_done),
        .I2(wrcal_done_reg),
        .I3(wrlvl_done_r1),
        .I4(rdlvl_stg1_done_reg_2),
        .I5(\init_state_r[1]_i_37_n_0 ),
        .O(\init_state_r[1]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \init_state_r[1]_i_35 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\init_state_r[1]_i_35_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \init_state_r[1]_i_36 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(cnt_cmd_done_r),
        .I2(dqs_found_done_r_reg),
        .O(\init_state_r[1]_i_36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \init_state_r[1]_i_37 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_37_n_0 ));
  LUT6 #(
    .INIT(64'h8A808080AAAAAAAA)) 
    \init_state_r[1]_i_4 
       (.I0(\init_state_r[5]_i_11_n_0 ),
        .I1(\init_state_r[1]_i_14_n_0 ),
        .I2(\init_state_r[1]_i_15_n_0 ),
        .I3(\init_state_r[1]_i_16_n_0 ),
        .I4(\init_state_r[6]_i_6_n_0 ),
        .I5(\init_state_r[1]_i_17_n_0 ),
        .O(\init_state_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT4 #(
    .INIT(16'hFDDD)) 
    \init_state_r[1]_i_5 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(prech_pending_r_reg_0),
        .O(\init_state_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF0000FFFF0000)) 
    \init_state_r[1]_i_6 
       (.I0(ocal_act_wait_cnt_reg__0[3]),
        .I1(ocal_act_wait_cnt_reg__0[2]),
        .I2(ocal_act_wait_cnt_reg__0[0]),
        .I3(ocal_act_wait_cnt_reg__0[1]),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h8888888088888888)) 
    \init_state_r[1]_i_7 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r[6]_i_17_n_0 ),
        .I3(\complex_wait_cnt[3]_i_6_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[5]_i_26_n_0 ),
        .O(\init_state_r[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hCDCDCCCCCDCDCFCC)) 
    \init_state_r[1]_i_8 
       (.I0(\init_state_r[1]_i_18_n_0 ),
        .I1(\init_state_r[1]_i_19_n_0 ),
        .I2(init_complete_r_i_3_n_0),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[4]_i_32_n_0 ),
        .O(\init_state_r[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEEFEEFF)) 
    \init_state_r[1]_i_9 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .I3(\init_state_r[6]_i_20_n_0 ),
        .I4(\init_state_r[6]_i_21_n_0 ),
        .I5(\init_state_r[1]_i_20_n_0 ),
        .O(\init_state_r[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h50C000C050CF00C0)) 
    \init_state_r[2]_i_1 
       (.I0(\init_state_r[2]_i_2_n_0 ),
        .I1(\init_state_r[2]_i_3_n_0 ),
        .I2(\init_state_r[2]_i_4_n_0 ),
        .I3(\init_state_r[2]_i_5_n_0 ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(prech_pending_r_reg_0),
        .O(\init_state_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT5 #(
    .INIT(32'hFFFF0DFF)) 
    \init_state_r[2]_i_10 
       (.I0(\complex_wait_cnt[3]_i_6_n_0 ),
        .I1(\init_state_r[6]_i_20_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h1F1F1F0000000000)) 
    \init_state_r[2]_i_11 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r[2]_i_23_n_0 ),
        .I3(\init_state_r[6]_i_19_n_0 ),
        .I4(\init_state_r[6]_i_18_n_0 ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \init_state_r[2]_i_12 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h000000A2AAAAAAAA)) 
    \init_state_r[2]_i_13 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I2(\init_state_r[2]_i_24_n_0 ),
        .I3(\init_state_r[2]_i_25_n_0 ),
        .I4(init_complete_r_i_3_n_0),
        .I5(\init_state_r[2]_i_26_n_0 ),
        .O(\init_state_r[2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAAAA2000AAAA20A0)) 
    \init_state_r[2]_i_14 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\init_state_r[2]_i_27_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[2]_i_28_n_0 ),
        .I5(\init_state_r[2]_i_29_n_0 ),
        .O(\init_state_r[2]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h4455500055000000)) 
    \init_state_r[2]_i_15 
       (.I0(\init_state_r[4]_i_42_n_0 ),
        .I1(\init_state_r[6]_i_26_n_0 ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[2]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h55555555F7FFFFFF)) 
    \init_state_r[2]_i_16 
       (.I0(cnt_cmd_done_r),
        .I1(ddr3_lm_done_r),
        .I2(rdlvl_stg1_done_reg_2),
        .I3(wrlvl_done_r1),
        .I4(wrcal_done_reg),
        .I5(wrcal_sanity_chk_done),
        .O(\init_state_r[2]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDFDFFFDDD)) 
    \init_state_r[2]_i_17 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r[2]_i_30_n_0 ),
        .I2(\init_state_r[1]_i_31_n_0 ),
        .I3(\init_state_r[4]_i_38_n_0 ),
        .I4(wrcal_done_reg_0),
        .I5(\init_state_r[2]_i_32_n_0 ),
        .O(\init_state_r[2]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h4404FFFFFFFFFFFF)) 
    \init_state_r[2]_i_18 
       (.I0(\init_state_r[4]_i_37_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(dqs_found_done_r_reg),
        .I3(\one_rank.stg1_wr_done_reg_1 ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[2]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBB0000000B)) 
    \init_state_r[2]_i_19 
       (.I0(\init_state_r[0]_i_26_n_0 ),
        .I1(\init_state_r[2]_i_34_n_0 ),
        .I2(wr_victim_inc_i_3_n_0),
        .I3(complex_sample_cnt_inc_i_2_n_0),
        .I4(complex_sample_cnt_inc_i_3_n_0),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[2]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \init_state_r[2]_i_2 
       (.I0(ocal_act_wait_cnt_reg__0[3]),
        .I1(ocal_act_wait_cnt_reg__0[2]),
        .I2(ocal_act_wait_cnt_reg__0[0]),
        .I3(ocal_act_wait_cnt_reg__0[1]),
        .O(\init_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0404040404040455)) 
    \init_state_r[2]_i_20 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r[2]_i_35_n_0 ),
        .I2(\init_state_r[6]_i_18_n_0 ),
        .I3(complex_num_writes_dec_reg__0[1]),
        .I4(complex_num_writes_dec_reg__0[4]),
        .I5(\init_state_r[5]_i_37_n_0 ),
        .O(\init_state_r[2]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h0000000053000000)) 
    \init_state_r[2]_i_21 
       (.I0(wrlvl_done_r1),
        .I1(\init_state_r[1]_i_25_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h808C8080808C8C8C)) 
    \init_state_r[2]_i_22 
       (.I0(wrlvl_rank_done_r7),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(mem_init_done_r),
        .I4(cnt_dllk_zqinit_done_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT5 #(
    .INIT(32'hEFEEAAAA)) 
    \init_state_r[2]_i_23 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(prech_pending_r_reg_0),
        .I2(complex_oclkdelay_calib_done_r1),
        .I3(rdlvl_stg1_done_reg_0),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[2]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF40000000)) 
    \init_state_r[2]_i_24 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(complex_wait_cnt_reg__0[1]),
        .I2(complex_wait_cnt_reg__0[0]),
        .I3(complex_wait_cnt_reg__0[3]),
        .I4(complex_wait_cnt_reg__0[2]),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'h00F20000)) 
    \init_state_r[2]_i_25 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(prbs_last_byte_done_r),
        .I2(prech_pending_r_reg_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[2]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT5 #(
    .INIT(32'hFFFFBFFF)) 
    \init_state_r[2]_i_26 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_26_n_0 ));
  LUT3 #(
    .INIT(8'hBA)) 
    \init_state_r[2]_i_27 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(pi_phase_locked_all_r4),
        .I2(pi_phase_locked_all_r3),
        .O(\init_state_r[2]_i_27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \init_state_r[2]_i_28 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(burst_addr_r_reg_n_0),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[2]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT5 #(
    .INIT(32'h00FF00FE)) 
    \init_state_r[2]_i_29 
       (.I0(wrlvl_byte_redo),
        .I1(wrcal_done_reg),
        .I2(prech_pending_r_reg_0),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(wrcal_resume_r),
        .O(\init_state_r[2]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h505C5050535F5353)) 
    \init_state_r[2]_i_3 
       (.I0(\init_state_r[2]_i_6_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r[2]_i_7_n_0 ),
        .I4(\init_state_r[2]_i_8_n_0 ),
        .I5(\init_state_r[2]_i_9_n_0 ),
        .O(\init_state_r[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[2]_i_30 
       (.I0(cnt_init_af_done_r),
        .I1(mem_init_done_r),
        .O(\init_state_r[2]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \init_state_r[2]_i_32 
       (.I0(wrlvl_done_r1),
        .I1(dqs_found_done_r_reg),
        .I2(wrlvl_byte_redo),
        .O(\init_state_r[2]_i_32_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_state_r[2]_i_34 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[2]_i_34_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \init_state_r[2]_i_35 
       (.I0(prbs_last_byte_done_r),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\init_state_r[2]_i_35_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_state_r[2]_i_4 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .O(\init_state_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \init_state_r[2]_i_5 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000000F2)) 
    \init_state_r[2]_i_6 
       (.I0(\init_state_r[2]_i_10_n_0 ),
        .I1(\init_state_r[2]_i_11_n_0 ),
        .I2(\init_state_r[2]_i_12_n_0 ),
        .I3(\init_state_r[2]_i_13_n_0 ),
        .I4(\init_state_r[2]_i_14_n_0 ),
        .I5(\init_state_r[2]_i_15_n_0 ),
        .O(\init_state_r[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000C3F3B333)) 
    \init_state_r[2]_i_7 
       (.I0(\init_state_r[2]_i_16_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h3FF33FF3F733F7F3)) 
    \init_state_r[2]_i_8 
       (.I0(\init_state_r[2]_i_17_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00AE00AE00AE0000)) 
    \init_state_r[2]_i_9 
       (.I0(\init_state_r[2]_i_18_n_0 ),
        .I1(\init_state_r[2]_i_19_n_0 ),
        .I2(\init_state_r[2]_i_20_n_0 ),
        .I3(\init_state_r[2]_i_21_n_0 ),
        .I4(init_complete_r_i_3_n_0),
        .I5(\init_state_r[2]_i_22_n_0 ),
        .O(\init_state_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAFEFEFFFE)) 
    \init_state_r[3]_i_1 
       (.I0(\init_state_r[3]_i_2_n_0 ),
        .I1(\init_state_r[3]_i_3_n_0 ),
        .I2(\init_state_r[3]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r[3]_i_5_n_0 ),
        .I5(\init_state_r[3]_i_6_n_0 ),
        .O(\init_state_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hC8CCC8C0C8C0C8C0)) 
    \init_state_r[3]_i_10 
       (.I0(\init_state_r[3]_i_18_n_0 ),
        .I1(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(ddr2_pre_flag_r_reg_n_0),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[3]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[3]_i_11 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(cnt_cmd_done_r),
        .O(\init_state_r[3]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hCCEE03FFCCEE33FF)) 
    \init_state_r[3]_i_12 
       (.I0(\init_state_r[3]_i_19_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(wrcal_sanity_chk_done_reg),
        .O(\init_state_r[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFFFFFE0FFE0)) 
    \init_state_r[3]_i_13 
       (.I0(\init_state_r[6]_i_18_n_0 ),
        .I1(\init_state_r[6]_i_19_n_0 ),
        .I2(\init_state_r[3]_i_21_n_0 ),
        .I3(\init_state_r[6]_i_17_n_0 ),
        .I4(\init_state_r[5]_i_27_n_0 ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[3]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h00800080008000A0)) 
    \init_state_r[3]_i_14 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I2(\complex_wait_cnt[3]_i_6_n_0 ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r[6]_i_22_n_0 ),
        .I5(rdlvl_stg1_done_reg_1),
        .O(\init_state_r[3]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h3000303000001030)) 
    \init_state_r[3]_i_15 
       (.I0(\complex_wait_cnt[3]_i_6_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[6]_i_20_n_0 ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[3]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h503F00000FFFFFFF)) 
    \init_state_r[3]_i_16 
       (.I0(\init_state_r[6]_i_26_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[3]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h1111FFFF0FFFFFFF)) 
    \init_state_r[3]_i_17 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(wrlvl_rank_done_r7),
        .I2(mem_init_done_r),
        .I3(cnt_dllk_zqinit_done_r),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[3]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT5 #(
    .INIT(32'hBBBBB0BB)) 
    \init_state_r[3]_i_18 
       (.I0(mem_init_done_r),
        .I1(cnt_init_af_done_r),
        .I2(wrlvl_byte_redo),
        .I3(dqs_found_done_r_reg),
        .I4(wrlvl_done_r1),
        .O(\init_state_r[3]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \init_state_r[3]_i_19 
       (.I0(reg_ctrl_cnt_r_reg__0[1]),
        .I1(reg_ctrl_cnt_r_reg__0[0]),
        .I2(reg_ctrl_cnt_r_reg__0[3]),
        .I3(reg_ctrl_cnt_r_reg__0[2]),
        .O(\init_state_r[3]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \init_state_r[3]_i_2 
       (.I0(init_state_r),
        .I1(prech_pending_r_reg_0),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT5 #(
    .INIT(32'h15555555)) 
    \init_state_r[3]_i_21 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(complex_wait_cnt_reg__0[2]),
        .I2(complex_wait_cnt_reg__0[3]),
        .I3(complex_wait_cnt_reg__0[0]),
        .I4(complex_wait_cnt_reg__0[1]),
        .O(\init_state_r[3]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEEAEAAAAAAAA)) 
    \init_state_r[3]_i_3 
       (.I0(\init_state_r[2]_i_5_n_0 ),
        .I1(\init_state_r[6]_i_6_n_0 ),
        .I2(\init_state_r[3]_i_7_n_0 ),
        .I3(\init_state_r[3]_i_8_n_0 ),
        .I4(\init_state_r[3]_i_9_n_0 ),
        .I5(\init_state_r[4]_i_8_n_0 ),
        .O(\init_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8AAA8888AAAAA8A8)) 
    \init_state_r[3]_i_4 
       (.I0(\init_state_r[5]_i_11_n_0 ),
        .I1(\init_state_r[3]_i_10_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[3]_i_11_n_0 ),
        .I5(\init_state_r[3]_i_12_n_0 ),
        .O(\init_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000DFFFF000D0000)) 
    \init_state_r[3]_i_5 
       (.I0(\init_state_r[6]_i_6_n_0 ),
        .I1(\init_state_r[3]_i_13_n_0 ),
        .I2(\init_state_r[3]_i_14_n_0 ),
        .I3(\init_state_r[3]_i_15_n_0 ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r[3]_i_16_n_0 ),
        .O(\init_state_r[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT4 #(
    .INIT(16'hAA2A)) 
    \init_state_r[3]_i_6 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[2]_i_2_n_0 ),
        .O(\init_state_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h550057005500DF00)) 
    \init_state_r[3]_i_7 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(reset_rd_addr_r1),
        .I5(prbs_last_byte_done_r),
        .O(\init_state_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00005F5700005555)) 
    \init_state_r[3]_i_8 
       (.I0(cnt_cmd_done_r),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(rdlvl_stg1_done_reg_0),
        .I3(rdlvl_last_byte_done),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(dqs_found_done_r_reg_0),
        .O(\init_state_r[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF7F7F0000)) 
    \init_state_r[3]_i_9 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[3]_i_17_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFE0FFE0E0E0E0)) 
    \init_state_r[4]_i_1 
       (.I0(prech_pending_r_reg_0),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r[4]_i_2_n_0 ),
        .I3(\init_state_r[4]_i_3_n_0 ),
        .I4(\init_state_r[4]_i_4_n_0 ),
        .I5(\init_state_r[4]_i_5_n_0 ),
        .O(\init_state_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT5 #(
    .INIT(32'hAFBFAFAF)) 
    \init_state_r[4]_i_10 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r[4]_i_27_n_0 ),
        .I4(\init_state_r[4]_i_28_n_0 ),
        .O(\init_state_r[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00FFBFFF00FFFFFF)) 
    \init_state_r[4]_i_11 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I2(\complex_wait_cnt[3]_i_6_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAB00AB00ABFFAB00)) 
    \init_state_r[4]_i_12 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(rdlvl_stg1_done_reg_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[4]_i_29_n_0 ),
        .I5(\init_state_r[4]_i_30_n_0 ),
        .O(\init_state_r[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000003000000022)) 
    \init_state_r[4]_i_13 
       (.I0(\init_state_r[4]_i_31_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r[4]_i_32_n_0 ),
        .I3(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF8088FFFF)) 
    \init_state_r[4]_i_14 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\init_state_r[4]_i_33_n_0 ),
        .I2(\init_state_r[4]_i_34_n_0 ),
        .I3(\init_state_r[4]_i_27_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r[4]_i_35_n_0 ),
        .O(\init_state_r[4]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h8F00DFFF8FFFDFFF)) 
    \init_state_r[4]_i_15 
       (.I0(cnt_cmd_done_r),
        .I1(rdlvl_stg1_done_reg_2),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r[5]_i_20_n_0 ),
        .O(\init_state_r[4]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[4]_i_16 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT5 #(
    .INIT(32'h2FAF7FFF)) 
    \init_state_r[4]_i_17 
       (.I0(cnt_cmd_done_r),
        .I1(wrlvl_done_r1),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h000000000ACCFFCC)) 
    \init_state_r[4]_i_18 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(rdlvl_stg1_done_reg_4),
        .I3(cnt_cmd_done_r),
        .I4(dqs_found_done_r_reg),
        .I5(\init_state_r[4]_i_37_n_0 ),
        .O(\init_state_r[4]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT5 #(
    .INIT(32'h0010FFFF)) 
    \init_state_r[4]_i_19 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(reset_rd_addr_r1),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \init_state_r[4]_i_2 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAABA8A)) 
    \init_state_r[4]_i_20 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(wr_victim_inc_i_3_n_0),
        .I2(\complex_num_reads[1]_i_7_n_0 ),
        .I3(prbs_last_byte_done_r),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(\complex_num_writes[4]_i_16_n_0 ),
        .O(\init_state_r[4]_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \init_state_r[4]_i_21 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .O(\init_state_r[4]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h0002020233333333)) 
    \init_state_r[4]_i_22 
       (.I0(wrlvl_done_r1),
        .I1(\init_state_r[1]_i_31_n_0 ),
        .I2(rdlvl_stg1_done_reg_0),
        .I3(prbs_last_byte_done_r),
        .I4(mem_init_done_r),
        .I5(dqs_found_done_r_reg),
        .O(\init_state_r[4]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT4 #(
    .INIT(16'h04FF)) 
    \init_state_r[4]_i_23 
       (.I0(\init_state_r[4]_i_38_n_0 ),
        .I1(wrlvl_byte_redo),
        .I2(wrcal_done_reg),
        .I3(\init_state_r[3]_i_18_n_0 ),
        .O(\init_state_r[4]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT5 #(
    .INIT(32'hFFFFFFDF)) 
    \init_state_r[4]_i_24 
       (.I0(mem_init_done_r),
        .I1(wrlvl_done_r1),
        .I2(dqs_found_done_r_reg),
        .I3(prbs_last_byte_done_r),
        .I4(rdlvl_stg1_done_reg_0),
        .O(\init_state_r[4]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h77F30000FFFFFFFF)) 
    \init_state_r[4]_i_25 
       (.I0(\init_state_r[3]_i_19_n_0 ),
        .I1(\wrcal_reads[7]_i_5_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r[4]_i_39_n_0 ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[4]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAFB)) 
    \init_state_r[4]_i_26 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(ddr2_pre_flag_r_reg_n_0),
        .O(\init_state_r[4]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \init_state_r[4]_i_27 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008000000)) 
    \init_state_r[4]_i_28 
       (.I0(wrcal_done_reg),
        .I1(wrlvl_done_r1),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r[4]_i_40_n_0 ),
        .O(\init_state_r[4]_i_28_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \init_state_r[4]_i_29 
       (.I0(complex_sample_cnt_inc_i_3_n_0),
        .I1(wr_victim_inc_i_3_n_0),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h000000004F4F004F)) 
    \init_state_r[4]_i_3 
       (.I0(\init_state_r[4]_i_6_n_0 ),
        .I1(\init_state_r[4]_i_7_n_0 ),
        .I2(\init_state_r[4]_i_8_n_0 ),
        .I3(\init_state_r[4]_i_9_n_0 ),
        .I4(\init_state_r[4]_i_10_n_0 ),
        .I5(\init_state_r[2]_i_5_n_0 ),
        .O(\init_state_r[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBA00FFFFBA00BA00)) 
    \init_state_r[4]_i_30 
       (.I0(prech_pending_r_reg_0),
        .I1(complex_oclkdelay_calib_done_r1),
        .I2(rdlvl_stg1_done_reg_0),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\complex_wait_cnt[3]_i_6_n_0 ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT4 #(
    .INIT(16'h00A2)) 
    \init_state_r[4]_i_31 
       (.I0(\init_state_r[6]_i_21_n_0 ),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(prbs_last_byte_done_r),
        .I3(prech_pending_r_reg_0),
        .O(\init_state_r[4]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT4 #(
    .INIT(16'h0051)) 
    \init_state_r[4]_i_32 
       (.I0(\complex_wait_cnt[3]_i_6_n_0 ),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(prbs_last_byte_done_r),
        .I3(prech_pending_r_reg_0),
        .O(\init_state_r[4]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'hF3F1FFFDFFFFFFFF)) 
    \init_state_r[4]_i_33 
       (.I0(wrlvl_byte_redo_reg),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(wrcal_resume_r),
        .I4(init_next_state1110_out),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[4]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'hFF00FFFF30307575)) 
    \init_state_r[4]_i_34 
       (.I0(\init_state_r[4]_i_41_n_0 ),
        .I1(wrcal_prech_req),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r[6]_i_29_n_0 ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h4455555550550055)) 
    \init_state_r[4]_i_35 
       (.I0(\init_state_r[4]_i_42_n_0 ),
        .I1(\init_state_r[6]_i_26_n_0 ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_35_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT4 #(
    .INIT(16'hF4FF)) 
    \init_state_r[4]_i_37 
       (.I0(pi_calib_done),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_37_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT5 #(
    .INIT(32'h3333FBBB)) 
    \init_state_r[4]_i_38 
       (.I0(wrlvl_done_r1),
        .I1(dqs_found_done_r_reg),
        .I2(mem_init_done_r),
        .I3(prbs_last_byte_done_r),
        .I4(rdlvl_stg1_done_reg_0),
        .O(\init_state_r[4]_i_38_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    \init_state_r[4]_i_39 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'h00000000BAAABAFA)) 
    \init_state_r[4]_i_4 
       (.I0(\init_state_r[4]_i_11_n_0 ),
        .I1(\init_state_r[4]_i_12_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r[4]_i_13_n_0 ),
        .I5(\init_state_r[4]_i_14_n_0 ),
        .O(\init_state_r[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF7F)) 
    \init_state_r[4]_i_40 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(dqs_found_done_r_reg),
        .I2(cnt_cmd_done_r),
        .I3(ddr3_lm_done_r),
        .I4(wrcal_sanity_chk_done),
        .O(\init_state_r[4]_i_40_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[4]_i_41 
       (.I0(prech_pending_r_reg_0),
        .I1(wrcal_done_reg),
        .O(\init_state_r[4]_i_41_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_state_r[4]_i_42 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[4]_i_42_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT4 #(
    .INIT(16'h08FF)) 
    \init_state_r[4]_i_5 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[2]_i_2_n_0 ),
        .I3(init_state_r),
        .O(\init_state_r[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h010131010D0D3D0D)) 
    \init_state_r[4]_i_6 
       (.I0(\init_state_r[4]_i_15_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[4]_i_16_n_0 ),
        .I4(\init_state_r[5]_i_21_n_0 ),
        .I5(\init_state_r[4]_i_17_n_0 ),
        .O(\init_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h44444544FFFFFFFF)) 
    \init_state_r[4]_i_7 
       (.I0(\init_state_r[4]_i_18_n_0 ),
        .I1(\init_state_r[4]_i_19_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[5]_i_22_n_0 ),
        .I4(\init_state_r[4]_i_20_n_0 ),
        .I5(\init_state_r[6]_i_6_n_0 ),
        .O(\init_state_r[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \init_state_r[4]_i_8 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFFABAA)) 
    \init_state_r[4]_i_9 
       (.I0(\init_state_r[4]_i_21_n_0 ),
        .I1(\init_state_r[4]_i_22_n_0 ),
        .I2(\init_state_r[4]_i_23_n_0 ),
        .I3(\init_state_r[4]_i_24_n_0 ),
        .I4(\init_state_r[4]_i_25_n_0 ),
        .I5(\init_state_r[4]_i_26_n_0 ),
        .O(\init_state_r[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF54545554)) 
    \init_state_r[5]_i_1 
       (.I0(\init_state_r[5]_i_2_n_0 ),
        .I1(\init_state_r[5]_i_3_n_0 ),
        .I2(\init_state_r[5]_i_4_n_0 ),
        .I3(\init_state_r[5]_i_5_n_0 ),
        .I4(\init_state_r[5]_i_6_n_0 ),
        .I5(\init_state_r[5]_i_7_n_0 ),
        .O(\init_state_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000555DDD5D)) 
    \init_state_r[5]_i_10 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[5]_i_22_n_0 ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .I4(prbs_last_byte_done_r),
        .I5(\init_state_r[5]_i_23_n_0 ),
        .O(\init_state_r[5]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[5]_i_11 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF50445555)) 
    \init_state_r[5]_i_12 
       (.I0(\init_state_r[5]_i_24_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(\complex_wait_cnt[3]_i_6_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I5(\init_state_r[5]_i_25_n_0 ),
        .O(\init_state_r[5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h00EAFFEEFFEAFFEE)) 
    \init_state_r[5]_i_13 
       (.I0(\init_state_r[6]_i_17_n_0 ),
        .I1(\init_state_r[5]_i_26_n_0 ),
        .I2(\complex_wait_cnt[3]_i_6_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r[5]_i_27_n_0 ),
        .O(\init_state_r[5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFFFFEFF)) 
    \init_state_r[5]_i_14 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[6]_i_21_n_0 ),
        .I4(\init_state_r[5]_i_28_n_0 ),
        .I5(\init_state_r[6]_i_20_n_0 ),
        .O(\init_state_r[5]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F4F4F4F4FFF4F)) 
    \init_state_r[5]_i_15 
       (.I0(\init_state_r[5]_i_29_n_0 ),
        .I1(detect_pi_found_dqs_i_2_n_0),
        .I2(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I3(complex_odt_ext_i_2_n_0),
        .I4(\complex_wait_cnt[3]_i_6_n_0 ),
        .I5(\prech_done_dly_r_reg[15]_srl16_i_4_n_0 ),
        .O(\init_state_r[5]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00FB000000FB00FB)) 
    \init_state_r[5]_i_16 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[5]_i_30_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I4(\init_state_r[5]_i_31_n_0 ),
        .I5(\init_state_r[5]_i_32_n_0 ),
        .O(\init_state_r[5]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFB8B00000)) 
    \init_state_r[5]_i_17 
       (.I0(\init_state_r[5]_i_33_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r[6]_i_6_n_0 ),
        .I5(\init_state_r[5]_i_34_n_0 ),
        .O(\init_state_r[5]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'hFBAA0000)) 
    \init_state_r[5]_i_18 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(pi_phase_locked_all_r3),
        .I2(pi_phase_locked_all_r4),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFABAAABAB)) 
    \init_state_r[5]_i_19 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(wrcal_resume_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(wrlvl_byte_redo_reg),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r[5]_i_36_n_0 ),
        .O(\init_state_r[5]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT4 #(
    .INIT(16'hCC4C)) 
    \init_state_r[5]_i_2 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r[2]_i_2_n_0 ),
        .O(\init_state_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT5 #(
    .INIT(32'h007FFF7F)) 
    \init_state_r[5]_i_20 
       (.I0(po_ck_addr_cmd_delay_done),
        .I1(cnt_pwron_cke_done_r),
        .I2(phy_ctl_ready),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(cnt_txpr_done_r),
        .O(\init_state_r[5]_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \init_state_r[5]_i_21 
       (.I0(wrlvl_rank_done_r7),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_dllk_zqinit_done_r),
        .O(\init_state_r[5]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[5]_i_22 
       (.I0(complex_num_writes_dec_reg__0[1]),
        .I1(complex_num_writes_dec_reg__0[4]),
        .I2(\init_state_r[5]_i_37_n_0 ),
        .O(\init_state_r[5]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF7F4C0000)) 
    \init_state_r[5]_i_23 
       (.I0(rdlvl_stg1_done_reg_2),
        .I1(cnt_cmd_done_r),
        .I2(pi_calib_done),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r[0]_i_5_n_0 ),
        .I5(\init_state_r[5]_i_38_n_0 ),
        .O(\init_state_r[5]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFDDDDDDDD)) 
    \init_state_r[5]_i_24 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r[6]_i_20_n_0 ),
        .I3(\complex_wait_cnt[3]_i_6_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r[0]_i_5_n_0 ),
        .O(\init_state_r[5]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h0101010111010100)) 
    \init_state_r[5]_i_25 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[5]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \init_state_r[5]_i_26 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(complex_sample_cnt_inc_i_3_n_0),
        .I5(wr_victim_inc_i_3_n_0),
        .O(\init_state_r[5]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \init_state_r[5]_i_27 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(rdlvl_stg1_done_reg_0),
        .O(\init_state_r[5]_i_27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \init_state_r[5]_i_28 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(complex_sample_cnt_inc_i_2_n_0),
        .I4(complex_sample_cnt_inc_i_3_n_0),
        .O(\init_state_r[5]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT5 #(
    .INIT(32'h0D0D0D00)) 
    \init_state_r[5]_i_29 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(prbs_last_byte_done_r),
        .I2(prech_pending_r_reg_0),
        .I3(\complex_wait_cnt[3]_i_6_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h1110111111101110)) 
    \init_state_r[5]_i_3 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r[5]_i_8_n_0 ),
        .I3(\init_state_r[5]_i_9_n_0 ),
        .I4(\init_state_r[5]_i_10_n_0 ),
        .I5(\init_state_r[6]_i_6_n_0 ),
        .O(\init_state_r[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \init_state_r[5]_i_30 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(burst_addr_r_reg_n_0),
        .O(\init_state_r[5]_i_30_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAABAAAAAAAAAA)) 
    \init_state_r[5]_i_31 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(wrcal_wr_cnt_reg__0[3]),
        .I2(wrcal_wr_cnt_reg__0[2]),
        .I3(wrcal_wr_cnt_reg__0[0]),
        .I4(wrcal_wr_cnt_reg__0[1]),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT5 #(
    .INIT(32'h0000EE0E)) 
    \init_state_r[5]_i_32 
       (.I0(wrcal_done_reg),
        .I1(prech_pending_r_reg_0),
        .I2(cnt_cmd_done_r),
        .I3(wrcal_prech_req),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDFDD)) 
    \init_state_r[5]_i_33 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(oclk_wr_cnt_reg__0[1]),
        .I3(oclk_wr_cnt_reg__0[0]),
        .I4(oclk_wr_cnt_reg__0[2]),
        .I5(oclk_wr_cnt_reg__0[3]),
        .O(\init_state_r[5]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFFEAAAA)) 
    \init_state_r[5]_i_34 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[5]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFD0000)) 
    \init_state_r[5]_i_36 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\init_state_r[6]_i_24_n_0 ),
        .I3(\init_state_r[6]_i_23_n_0 ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_36_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEFFFFFFFFFFF)) 
    \init_state_r[5]_i_37 
       (.I0(complex_num_writes_dec_reg__0[2]),
        .I1(complex_num_writes_dec_reg__0[3]),
        .I2(prbs_last_byte_done_r),
        .I3(rdlvl_stg1_done_reg_0),
        .I4(complex_row0_wr_done),
        .I5(complex_num_writes_dec_reg__0[0]),
        .O(\init_state_r[5]_i_37_n_0 ));
  LUT6 #(
    .INIT(64'h8888888088880080)) 
    \init_state_r[5]_i_38 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(cnt_cmd_done_r),
        .I4(reset_rd_addr_r1),
        .I5(prbs_last_byte_done_r),
        .O(\init_state_r[5]_i_38_n_0 ));
  LUT6 #(
    .INIT(64'hC8AA88AA88AA88AA)) 
    \init_state_r[5]_i_4 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[5]_i_11_n_0 ),
        .O(\init_state_r[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAEFFAEFFFFFFAEFF)) 
    \init_state_r[5]_i_5 
       (.I0(\init_state_r[5]_i_12_n_0 ),
        .I1(\init_state_r[6]_i_6_n_0 ),
        .I2(\init_state_r[5]_i_13_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r[5]_i_14_n_0 ),
        .I5(\init_state_r[5]_i_15_n_0 ),
        .O(\init_state_r[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h10111010FFFFFFFF)) 
    \init_state_r[5]_i_6 
       (.I0(\init_state_r[5]_i_16_n_0 ),
        .I1(\init_state_r[5]_i_17_n_0 ),
        .I2(init_complete_r_i_3_n_0),
        .I3(\init_state_r[5]_i_18_n_0 ),
        .I4(\init_state_r[5]_i_19_n_0 ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    \init_state_r[5]_i_7 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(prech_pending_r_reg_0),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0040504000400040)) 
    \init_state_r[5]_i_8 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I1(\init_state_r[5]_i_20_n_0 ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h000C404000000000)) 
    \init_state_r[5]_i_9 
       (.I0(\init_state_r[5]_i_21_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA0000A800)) 
    \init_state_r[6]_i_1 
       (.I0(\init_state_r[6]_i_2_n_0 ),
        .I1(\init_state_r[6]_i_3_n_0 ),
        .I2(\init_state_r[6]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r[6]_i_5_n_0 ),
        .I5(init_state_r),
        .O(\init_state_r[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0100000000000100)) 
    \init_state_r[6]_i_10 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(cnt_cmd_done_r),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[6]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040005050)) 
    \init_state_r[6]_i_11 
       (.I0(\complex_wait_cnt[3]_i_6_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r[6]_i_22_n_0 ),
        .I5(init_complete_r_i_3_n_0),
        .O(\init_state_r[6]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFAFAFAFAFAFAE)) 
    \init_state_r[6]_i_12 
       (.I0(\init_state_r[2]_i_4_n_0 ),
        .I1(wrcal_resume_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(prech_pending_r_reg_0),
        .I4(wrcal_done_reg),
        .I5(wrlvl_byte_redo),
        .O(\init_state_r[6]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT5 #(
    .INIT(32'h00000020)) 
    \init_state_r[6]_i_13 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[6]_i_23_n_0 ),
        .I4(\init_state_r[6]_i_24_n_0 ),
        .O(\init_state_r[6]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'h45000000)) 
    \init_state_r[6]_i_14 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(pi_phase_locked_all_r4),
        .I2(pi_phase_locked_all_r3),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(init_state_r),
        .O(\init_state_r[6]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \init_state_r[6]_i_15 
       (.I0(\init_state_r[6]_i_25_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[6]_i_26_n_0 ),
        .O(\init_state_r[6]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h4544454545444544)) 
    \init_state_r[6]_i_16 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I1(\init_state_r[6]_i_27_n_0 ),
        .I2(\init_state_r[2]_i_4_n_0 ),
        .I3(\init_state_r[6]_i_28_n_0 ),
        .I4(\init_state_r[6]_i_29_n_0 ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[6]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT4 #(
    .INIT(16'hAA08)) 
    \init_state_r[6]_i_17 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(complex_oclkdelay_calib_done_r1),
        .I3(prech_pending_r_reg_0),
        .O(\init_state_r[6]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \init_state_r[6]_i_18 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\init_state_r[6]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    \init_state_r[6]_i_19 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\init_state_r[6]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT4 #(
    .INIT(16'hDFFF)) 
    \init_state_r[6]_i_2 
       (.I0(prech_pending_r_reg_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \init_state_r[6]_i_20 
       (.I0(prech_pending_r_reg_0),
        .I1(prbs_last_byte_done_r),
        .I2(rdlvl_stg1_done_reg_0),
        .O(\init_state_r[6]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    \init_state_r[6]_i_21 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(complex_row0_rd_done),
        .I2(complex_num_reads_dec_reg__0[2]),
        .I3(complex_num_reads_dec_reg__0[3]),
        .I4(complex_num_reads_dec_reg__0[1]),
        .I5(complex_num_reads_dec_reg__0[0]),
        .O(\init_state_r[6]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'hFFFFFF4F)) 
    \init_state_r[6]_i_22 
       (.I0(prbs_last_byte_done_r),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(prech_pending_r_reg_0),
        .O(\init_state_r[6]_i_22_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \init_state_r[6]_i_23 
       (.I0(\wrcal_reads_reg_n_0_[5] ),
        .I1(\wrcal_reads_reg_n_0_[4] ),
        .I2(\wrcal_reads_reg_n_0_[6] ),
        .I3(\wrcal_reads_reg_n_0_[7] ),
        .O(\init_state_r[6]_i_23_n_0 ));
  LUT4 #(
    .INIT(16'hFFF4)) 
    \init_state_r[6]_i_24 
       (.I0(\wrcal_reads_reg_n_0_[4] ),
        .I1(\wrcal_reads_reg_n_0_[3] ),
        .I2(\wrcal_reads_reg_n_0_[5] ),
        .I3(\wrcal_reads_reg_n_0_[2] ),
        .O(\init_state_r[6]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    \init_state_r[6]_i_25 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[6]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \init_state_r[6]_i_26 
       (.I0(oclk_wr_cnt_reg__0[3]),
        .I1(oclk_wr_cnt_reg__0[2]),
        .I2(oclk_wr_cnt_reg__0[0]),
        .I3(oclk_wr_cnt_reg__0[1]),
        .O(\init_state_r[6]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT5 #(
    .INIT(32'h08000888)) 
    \init_state_r[6]_i_27 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(burst_addr_r_reg_n_0),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(cnt_cmd_done_r),
        .O(\init_state_r[6]_i_27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT5 #(
    .INIT(32'h00001101)) 
    \init_state_r[6]_i_28 
       (.I0(wrcal_done_reg),
        .I1(prech_pending_r_reg_0),
        .I2(cnt_cmd_done_r),
        .I3(wrcal_prech_req),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[6]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \init_state_r[6]_i_29 
       (.I0(wrcal_wr_cnt_reg__0[3]),
        .I1(wrcal_wr_cnt_reg__0[2]),
        .I2(wrcal_wr_cnt_reg__0[0]),
        .I3(wrcal_wr_cnt_reg__0[1]),
        .O(\init_state_r[6]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h2F000000FFFFFFFF)) 
    \init_state_r[6]_i_3 
       (.I0(init_state_r),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(detect_pi_found_dqs_i_2_n_0),
        .I3(\init_state_r[6]_i_6_n_0 ),
        .I4(\init_state_r[6]_i_7_n_0 ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7500)) 
    \init_state_r[6]_i_4 
       (.I0(\init_state_r[6]_i_8_n_0 ),
        .I1(\init_state_r[6]_i_9_n_0 ),
        .I2(complex_odt_ext_i_2_n_0),
        .I3(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I4(\init_state_r[6]_i_10_n_0 ),
        .I5(\init_state_r[6]_i_11_n_0 ),
        .O(\init_state_r[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FF0E)) 
    \init_state_r[6]_i_5 
       (.I0(\init_state_r[6]_i_12_n_0 ),
        .I1(\init_state_r[6]_i_13_n_0 ),
        .I2(\init_state_r[6]_i_14_n_0 ),
        .I3(init_complete_r_i_3_n_0),
        .I4(\init_state_r[6]_i_15_n_0 ),
        .I5(\init_state_r[6]_i_16_n_0 ),
        .O(\init_state_r[6]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[6]_i_6 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hABAAABAAABAAAAAA)) 
    \init_state_r[6]_i_7 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r[6]_i_17_n_0 ),
        .I2(\complex_wait_cnt[3]_i_6_n_0 ),
        .I3(init_state_r),
        .I4(\init_state_r[6]_i_18_n_0 ),
        .I5(\init_state_r[6]_i_19_n_0 ),
        .O(\init_state_r[6]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \init_state_r[6]_i_8 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[6]_i_20_n_0 ),
        .I4(\complex_wait_cnt[3]_i_6_n_0 ),
        .O(\init_state_r[6]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hBFBFFFFFBF00FFFF)) 
    \init_state_r[6]_i_9 
       (.I0(\init_state_r[6]_i_20_n_0 ),
        .I1(\wrcal_reads[7]_i_5_n_0 ),
        .I2(\init_state_r[6]_i_21_n_0 ),
        .I3(\init_state_r[6]_i_22_n_0 ),
        .I4(init_state_r),
        .I5(\complex_wait_cnt[3]_i_6_n_0 ),
        .O(\init_state_r[6]_i_9_n_0 ));
  FDRE \init_state_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[0]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[1]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[2]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[3]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[4]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[5]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE \init_state_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[6]_i_1_n_0 ),
        .Q(init_state_r),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    mem_init_done_r_i_1
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(cnt_dllk_zqinit_r_reg__0[7]),
        .I2(mem_init_done_r_i_2_n_0),
        .I3(cnt_dllk_zqinit_r_reg__0[6]),
        .I4(mem_init_done_r),
        .O(mem_init_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    mem_init_done_r_i_2
       (.I0(cnt_dllk_zqinit_r_reg__0[5]),
        .I1(cnt_dllk_zqinit_r_reg__0[3]),
        .I2(cnt_dllk_zqinit_r_reg__0[0]),
        .I3(cnt_dllk_zqinit_r_reg__0[1]),
        .I4(cnt_dllk_zqinit_r_reg__0[2]),
        .I5(cnt_dllk_zqinit_r_reg__0[4]),
        .O(mem_init_done_r_i_2_n_0));
  FDRE mem_init_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mem_init_done_r_i_1_n_0),
        .Q(mem_init_done_r),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_2
       (.I0(mc_ras_n),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_ras_n),
        .O(\wr_ptr_timing_reg[0]_0 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [159]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [79]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_4__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [141]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [61]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [135]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[79]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [111]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [55]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [93]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [37]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_5__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [87]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[55]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [191]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [95]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_7__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [179]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [83]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_0_5_i_7__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [175]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[95]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [21]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[51]),
        .O(phy_dout[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_1__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [4]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[10]),
        .O(\wr_ptr_timing_reg[0]_0 [6]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [239]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [119]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [221]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [101]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_1__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [215]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[119]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [9]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[51]),
        .O(phy_dout[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_2__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [1]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[10]),
        .O(\wr_ptr_timing_reg[0]_0 [5]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [187]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [91]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [183]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [87]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [171]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[91]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [167]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[87]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_2__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [163]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[83]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [350]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [174]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [345]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [169]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [339]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [163]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [332]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [156]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [326]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[174]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [321]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[169]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [315]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[163]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_3__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [309]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[157]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [302]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [150]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [295]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [143]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [287]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [135]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [278]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [126]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [270]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[150]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [263]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[143]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [255]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[135]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [247]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[127]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [63]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [31]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [51]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [19]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [47]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[31]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [30]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [14]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [27]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [11]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [23]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [18]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [14]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[14]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [11]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[11]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [7]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_6__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [3]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[3]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_18_23_i_1
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[51]),
        .O(phy_dout[7]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_18_23_i_1__0
       (.I0(init_calib_complete_reg_rep__16),
        .I1(phy_bank[10]),
        .O(\wr_ptr_timing_reg[0]_0 [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [158]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [78]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [140]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [60]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_1__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [134]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[78]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [32]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[51]),
        .O(phy_dout[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_2__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [7]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[10]),
        .O(\wr_ptr_timing_reg[0]_0 [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [104]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [48]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [98]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [42]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [80]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[48]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [74]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[42]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_2__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [68]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[36]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [238]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [118]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [233]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [113]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [227]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [107]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [220]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [100]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [214]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[118]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [209]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[113]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [203]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[107]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_3__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [197]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[101]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [349]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [173]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [344]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [168]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [338]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [162]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [331]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [155]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [325]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[173]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [320]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[168]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [314]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[162]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_5__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [308]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[156]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [301]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [149]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [294]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [142]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [286]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [134]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [277]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [125]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [269]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[149]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [262]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[142]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [254]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[134]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_18_23_i_6__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [246]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[126]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1
       (.I0(mc_cke),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_cke),
        .O(\wr_ptr_timing_reg[0] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [22]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[52]),
        .O(phy_dout[9]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [5]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[11]),
        .O(\wr_ptr_timing_reg[0]_0 [10]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [62]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [30]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [59]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [27]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [55]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [23]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [50]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [18]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [46]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[30]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [43]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[27]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [39]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[23]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_1__9
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [35]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[19]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [10]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[52]),
        .O(phy_dout[8]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_2__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [2]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[11]),
        .O(\wr_ptr_timing_reg[0]_0 [9]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [26]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [10]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [22]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [6]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [10]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[10]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [6]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_2__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [2]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[2]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_24_29_i_3
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[52]),
        .O(phy_dout[11]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_24_29_i_3__0
       (.I0(init_calib_complete_reg_rep__16),
        .I1(phy_bank[11]),
        .O(\wr_ptr_timing_reg[0]_0 [12]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [157]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [77]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [152]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [72]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [146]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [66]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [139]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [59]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [133]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[77]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [128]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[72]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [122]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[66]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_3__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [116]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[60]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_4
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [33]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[52]),
        .O(phy_dout[10]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_4__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [8]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[11]),
        .O(\wr_ptr_timing_reg[0]_0 [11]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [109]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [53]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_4__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [91]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [35]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_4__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [85]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[53]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [237]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [117]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [232]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [112]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [226]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [106]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [219]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [99]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [213]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[117]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [208]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[112]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [202]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[106]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_5__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [196]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[100]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [190]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [94]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [178]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [82]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_24_29_i_6__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [174]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[94]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_1__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [12]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[42]),
        .O(\wr_ptr_timing_reg[0]_0 [14]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_1__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [343]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [167]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [337]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [161]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_1__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [319]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[167]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_1__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [313]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[161]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_1__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [307]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[155]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [0]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[42]),
        .O(\wr_ptr_timing_reg[0]_0 [13]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [300]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [148]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [293]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [141]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [285]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [133]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [276]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [124]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [268]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[148]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [261]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[141]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [253]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[133]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_2__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [245]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[125]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_30_35_i_3
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[42]),
        .O(\wr_ptr_timing_reg[0]_0 [16]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [58]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [26]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [54]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [22]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_3__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [42]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[26]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_3__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [38]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[22]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_3__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [34]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[18]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_4
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [23]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[42]),
        .O(\wr_ptr_timing_reg[0]_0 [15]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [156]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [76]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [151]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [71]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [145]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [65]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [138]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [58]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [132]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[76]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [127]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[71]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [121]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[65]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_5__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [115]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[59]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [108]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [52]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [103]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [47]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [97]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [41]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [90]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [34]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [84]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[52]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [79]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[47]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [73]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[41]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_6__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [67]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[35]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1
       (.I0(mc_cas_n),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_cs_n),
        .O(\wr_ptr_timing_reg[0] [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__0
       (.I0(mc_ras_n),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[54]),
        .O(phy_dout[13]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [13]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[43]),
        .O(\wr_ptr_timing_reg[0]_0 [18]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [231]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [111]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [225]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [105]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [207]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[111]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [201]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[105]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__9
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [195]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[99]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [11]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[54]),
        .O(phy_dout[12]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [1]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[43]),
        .O(\wr_ptr_timing_reg[0]_0 [17]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [189]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [93]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [186]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [90]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [182]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [86]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [177]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [81]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [173]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[93]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [170]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[90]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [166]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[86]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_2__9
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [162]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[82]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [348]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [172]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [330]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [154]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [324]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[172]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [299]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [147]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [292]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [140]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [284]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [132]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [275]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [123]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [267]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[147]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [260]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[140]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [252]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[132]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [244]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[124]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [29]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [13]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [17]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [13]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[13]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_1__0
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[54]),
        .O(phy_dout[15]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_1__1
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[43]),
        .O(\wr_ptr_timing_reg[0]_0 [20]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [144]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [64]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_1__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [120]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[64]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_1__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [114]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[58]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2
       (.I0(\cmd_pipe_plus.mc_we_n_reg[1] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_we_n),
        .O(\wr_ptr_timing_reg[0] [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [34]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[54]),
        .O(phy_dout[14]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [24]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[43]),
        .O(\wr_ptr_timing_reg[0]_0 [19]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [107]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [51]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [96]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [40]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [89]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [33]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [83]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[51]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [72]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[40]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [66]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[34]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_3__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [14]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[44]),
        .O(\wr_ptr_timing_reg[0]_0 [22]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [236]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [116]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [218]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [98]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_3__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [212]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[116]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_4__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [2]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[44]),
        .O(\wr_ptr_timing_reg[0]_0 [21]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_4__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [181]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [85]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [165]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[85]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_4__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [161]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[81]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_5
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[44]),
        .O(\wr_ptr_timing_reg[0]_0 [24]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [347]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [171]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_5__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [336]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [160]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [329]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [153]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [323]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[171]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_5__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [312]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[160]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_5__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [306]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[154]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_6
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [25]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[44]),
        .O(\wr_ptr_timing_reg[0]_0 [23]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [298]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [146]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [283]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [131]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [274]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [122]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_6__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [266]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[146]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_6__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [251]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[131]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_6__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [243]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[123]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_1
       (.I0(mc_cas_n),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_cas_n),
        .O(\wr_ptr_timing_reg[0] [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_1__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [16]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[46]),
        .O(\wr_ptr_timing_reg[0]_0 [26]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [61]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [29]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [49]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [17]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_1__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [45]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[29]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_2__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [4]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[46]),
        .O(\wr_ptr_timing_reg[0]_0 [25]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [28]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [12]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [21]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [5]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_2__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [16]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_2__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [12]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[12]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [5]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_2__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [1]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[1]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_48_53_i_3
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[46]),
        .O(\wr_ptr_timing_reg[0]_0 [28]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [155]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [75]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [150]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [70]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [137]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [57]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [131]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[75]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_3__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [126]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[70]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_4
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [27]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[46]),
        .O(\wr_ptr_timing_reg[0]_0 [27]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [102]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [46]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [95]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [39]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_4__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [78]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[46]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [71]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[39]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_4__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [65]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[33]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [15]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[45]),
        .O(\wr_ptr_timing_reg[0]_0 [30]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [235]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [115]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [224]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [104]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [217]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [97]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [211]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[115]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [200]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[104]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [194]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[98]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_6
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [3]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[45]),
        .O(\wr_ptr_timing_reg[0]_0 [29]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [185]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [89]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_6__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [169]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[89]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_54_59_i_1__0
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[45]),
        .O(\wr_ptr_timing_reg[0]_0 [32]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [346]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [170]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [342]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [166]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [335]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [159]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [328]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [152]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [322]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[170]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [318]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[166]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [311]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[159]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_1__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [305]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[153]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [26]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[45]),
        .O(\wr_ptr_timing_reg[0]_0 [31]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [297]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [145]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [291]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [139]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [282]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [130]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [273]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [121]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [265]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[145]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [259]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[139]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [250]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[130]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [242]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[122]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_3
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [17]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[47]),
        .O(\wr_ptr_timing_reg[0]_0 [34]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [60]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [28]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [53]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [21]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [48]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [16]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [44]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[28]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_3__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [37]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[21]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_3__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [33]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[17]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_4
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [5]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[47]),
        .O(\wr_ptr_timing_reg[0]_0 [33]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [25]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [9]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [20]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_4__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [9]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[9]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [4]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_4__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [0]),
        .I1(init_calib_complete_reg_rep__27),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[0]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_54_59_i_5
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[47]),
        .O(\wr_ptr_timing_reg[0]_0 [36]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [154]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [74]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [143]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [63]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [136]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [56]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_5__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [130]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[74]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_5__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [119]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[63]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_5__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [113]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[57]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_6
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [28]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[47]),
        .O(\wr_ptr_timing_reg[0]_0 [35]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [106]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [50]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [101]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [45]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_6__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [88]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [32]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_6__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [82]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[50]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_6__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [77]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[45]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [18]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[48]),
        .O(\wr_ptr_timing_reg[0]_0 [38]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [234]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [114]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [230]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [110]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [223]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [103]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [216]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [96]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [210]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[114]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [206]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[110]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [199]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[103]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_1__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [193]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[97]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [6]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[48]),
        .O(\wr_ptr_timing_reg[0]_0 [37]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_2__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [188]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [92]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [176]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [80]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_2__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [172]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[92]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [341]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(\my_empty_reg[7]_0 [165]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [334]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [158]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [317]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[510]),
        .O(mux_wrdata[165]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_3__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [310]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[158]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_3__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [304]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[152]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [296]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [144]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [290]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [138]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [281]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [129]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [272]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [120]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [264]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[144]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [258]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[138]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [249]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[129]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [241]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[121]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [57]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[125]),
        .O(\my_empty_reg[7]_0 [25]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [52]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [20]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_5__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [41]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[125]),
        .O(mux_wrdata[25]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [36]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[20]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_5__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [32]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[16]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [24]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(\my_empty_reg[7]_0 [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_60_65_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [8]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[61]),
        .O(mux_wrdata[8]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_66_71_i_1
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[48]),
        .O(\wr_ptr_timing_reg[0]_0 [40]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_1__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [149]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [69]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [142]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [62]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_1__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [125]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[69]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [118]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[62]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [112]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[56]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [29]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[48]),
        .O(\wr_ptr_timing_reg[0]_0 [39]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [94]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [38]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [70]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[38]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_2__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [64]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[32]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [229]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [109]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [222]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [102]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [205]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[109]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [198]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[102]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [192]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[96]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_4__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [180]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [84]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [164]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[84]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_4__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [160]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[80]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [340]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [164]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_5__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [316]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[164]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [289]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [137]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [280]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [128]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [257]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[137]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [248]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[128]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_66_71_i_6__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [240]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[120]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_1
       (.I0(mc_odt),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_odt),
        .O(\wr_ptr_timing_reg[0] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_1__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [20]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[50]),
        .O(phy_dout[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_1__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [3]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[9]),
        .O(\wr_ptr_timing_reg[0]_0 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_1__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [351]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [175]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_1__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [333]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(\my_empty_reg[7]_0 [157]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_1__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [327]),
        .I1(init_calib_complete_reg_rep__17),
        .I2(phy_wrdata[511]),
        .O(mux_wrdata[175]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [8]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[50]),
        .O(phy_dout[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_2__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [0]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[9]),
        .O(\wr_ptr_timing_reg[0]_0 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [303]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [151]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [279]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [127]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_2__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [271]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[151]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_6_11_i_3
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[50]),
        .O(phy_dout[3]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_6_11_i_3__0
       (.I0(init_calib_complete_reg_rep__16),
        .I1(phy_bank[9]),
        .O(\wr_ptr_timing_reg[0]_0 [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [153]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [73]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [147]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(\my_empty_reg[7]_0 [67]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_3__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [129]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[73]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_3__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [123]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[67]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_3__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [117]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[61]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [31]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[50]),
        .O(phy_dout[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [6]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_bank[9]),
        .O(\wr_ptr_timing_reg[0]_0 [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [105]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [49]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [99]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [43]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [81]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[49]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [75]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[43]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [69]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[37]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [31]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [15]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [19]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_4__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [15]),
        .I1(init_calib_complete_reg_rep__26),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[15]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [110]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [54]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [92]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [36]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_6_11_i_6__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [86]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[54]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [19]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[49]),
        .O(\wr_ptr_timing_reg[0]_0 [42]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_1__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [56]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[190]),
        .O(\my_empty_reg[7]_0 [24]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [40]),
        .I1(init_calib_complete_reg_rep__25),
        .I2(phy_wrdata[190]),
        .O(mux_wrdata[24]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_2
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [7]),
        .I1(init_calib_complete_reg_rep__16),
        .I2(phy_address[49]),
        .O(\wr_ptr_timing_reg[0]_0 [41]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_72_77_i_3
       (.I0(init_calib_complete_reg_rep__15),
        .I1(phy_address[49]),
        .O(\wr_ptr_timing_reg[0]_0 [44]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [148]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [68]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_3__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [124]),
        .I1(init_calib_complete_reg_rep__22),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[68]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_4
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [30]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(phy_address[49]),
        .O(\wr_ptr_timing_reg[0]_0 [43]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_4__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [100]),
        .I1(init_calib_complete_reg_rep__23),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [44]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_4__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [76]),
        .I1(init_calib_complete_reg_rep__24),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[44]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [228]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .O(\my_empty_reg[7]_0 [108]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [204]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[441]),
        .O(mux_wrdata[108]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [184]),
        .I1(init_calib_complete_reg_rep__20),
        .I2(phy_wrdata[505]),
        .O(\my_empty_reg[7]_0 [88]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_72_77_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [168]),
        .I1(init_calib_complete_reg_rep__21),
        .I2(phy_wrdata[505]),
        .O(mux_wrdata[88]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_78_79_i_2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [288]),
        .I1(init_calib_complete_reg_rep__18),
        .I2(phy_wrdata[447]),
        .O(\my_empty_reg[7]_0 [136]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_78_79_i_2__0
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [256]),
        .I1(init_calib_complete_reg_rep__19),
        .I2(phy_wrdata[447]),
        .O(mux_wrdata[136]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00002000)) 
    mpr_rdlvl_start_i_1
       (.I0(dqs_found_done_r_reg),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(mpr_rdlvl_start_i_2_n_0),
        .I5(mpr_rdlvl_start_r_reg),
        .O(mpr_rdlvl_start_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT4 #(
    .INIT(16'hFEFF)) 
    mpr_rdlvl_start_i_2
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .O(mpr_rdlvl_start_i_2_n_0));
  FDRE mpr_rdlvl_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mpr_rdlvl_start_i_1_n_0),
        .Q(mpr_rdlvl_start_r_reg),
        .R(rstdiv0_sync_r1_reg_rep__4));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \my_empty[7]_i_4__6 
       (.I0(mc_wrdata_en),
        .I1(init_calib_complete_reg_rep__14),
        .I2(\my_empty_reg[7] ),
        .O(phy_data_wr_en));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \my_full[3]_i_3__1 
       (.I0(init_calib_complete_reg_rep__14),
        .I1(\wr_ptr_reg[2] ),
        .O(phy_cmd_wr_en));
  LUT1 #(
    .INIT(2'h1)) 
    \num_refresh[0]_i_1 
       (.I0(num_refresh_reg__0[0]),
        .O(p_0_in__4[0]));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \num_refresh[1]_i_1 
       (.I0(num_refresh_reg__0[0]),
        .I1(num_refresh_reg__0[1]),
        .O(p_0_in__4[1]));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \num_refresh[2]_i_1 
       (.I0(num_refresh_reg__0[2]),
        .I1(num_refresh_reg__0[1]),
        .I2(num_refresh_reg__0[0]),
        .O(p_0_in__4[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEE)) 
    \num_refresh[3]_i_1 
       (.I0(\num_refresh[3]_i_4_n_0 ),
        .I1(\num_refresh[3]_i_5_n_0 ),
        .I2(\num_refresh[3]_i_6_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(rstdiv0_sync_r1_reg_rep__22),
        .I5(\num_refresh[3]_i_7_n_0 ),
        .O(\num_refresh[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h20AA)) 
    \num_refresh[3]_i_2 
       (.I0(\cnt_init_mr_r[1]_i_3_n_0 ),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(wrlvl_done_r1),
        .I3(dqs_found_done_r_reg),
        .O(num_refresh0));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \num_refresh[3]_i_3 
       (.I0(num_refresh_reg__0[3]),
        .I1(num_refresh_reg__0[0]),
        .I2(num_refresh_reg__0[1]),
        .I3(num_refresh_reg__0[2]),
        .O(p_0_in__4[3]));
  LUT6 #(
    .INIT(64'h4000000010000000)) 
    \num_refresh[3]_i_4 
       (.I0(\wrcal_start_dly_r_reg[4]_srl5_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\num_refresh[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000002000000000)) 
    \num_refresh[3]_i_5 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(\num_refresh[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT5 #(
    .INIT(32'hFDFFFFFF)) 
    \num_refresh[3]_i_6 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(\num_refresh[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \num_refresh[3]_i_7 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\num_refresh[3]_i_7_n_0 ));
  FDRE \num_refresh_reg[0] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__4[0]),
        .Q(num_refresh_reg__0[0]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[1] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__4[1]),
        .Q(num_refresh_reg__0[1]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[2] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__4[2]),
        .Q(num_refresh_reg__0[2]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[3] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__4[3]),
        .Q(num_refresh_reg__0[3]),
        .R(\num_refresh[3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \ocal_act_wait_cnt[0]_i_1 
       (.I0(ocal_act_wait_cnt_reg__0[0]),
        .O(p_0_in__10[0]));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \ocal_act_wait_cnt[1]_i_1 
       (.I0(ocal_act_wait_cnt_reg__0[0]),
        .I1(ocal_act_wait_cnt_reg__0[1]),
        .O(p_0_in__10[1]));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \ocal_act_wait_cnt[2]_i_1 
       (.I0(ocal_act_wait_cnt_reg__0[2]),
        .I1(ocal_act_wait_cnt_reg__0[1]),
        .I2(ocal_act_wait_cnt_reg__0[0]),
        .O(p_0_in__10[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \ocal_act_wait_cnt[3]_i_1 
       (.I0(\init_state_r[2]_i_2_n_0 ),
        .I1(\ocal_act_wait_cnt[3]_i_3_n_0 ),
        .I2(rstdiv0_sync_r1_reg_rep__22),
        .I3(\wrcal_reads[7]_i_4_n_0 ),
        .I4(init_complete_r_i_2_n_0),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \ocal_act_wait_cnt[3]_i_2 
       (.I0(ocal_act_wait_cnt_reg__0[3]),
        .I1(ocal_act_wait_cnt_reg__0[0]),
        .I2(ocal_act_wait_cnt_reg__0[1]),
        .I3(ocal_act_wait_cnt_reg__0[2]),
        .O(p_0_in__10[3]));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ocal_act_wait_cnt[3]_i_3 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .O(\ocal_act_wait_cnt[3]_i_3_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__10[0]),
        .Q(ocal_act_wait_cnt_reg__0[0]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__10[1]),
        .Q(ocal_act_wait_cnt_reg__0[1]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__10[2]),
        .Q(ocal_act_wait_cnt_reg__0[2]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__10[3]),
        .Q(ocal_act_wait_cnt_reg__0[3]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oclk_wr_cnt[0]_i_1 
       (.I0(oclk_wr_cnt_reg__0[0]),
        .O(\oclk_wr_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \oclk_wr_cnt[1]_i_1 
       (.I0(oclk_wr_cnt_reg__0[1]),
        .I1(oclk_wr_cnt_reg__0[0]),
        .O(\oclk_wr_cnt[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \oclk_wr_cnt[2]_i_1 
       (.I0(oclk_wr_cnt_reg__0[2]),
        .I1(oclk_wr_cnt_reg__0[0]),
        .I2(oclk_wr_cnt_reg__0[1]),
        .O(oclk_wr_cnt0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAAB)) 
    \oclk_wr_cnt[3]_i_1 
       (.I0(\oclk_wr_cnt[3]_i_4_n_0 ),
        .I1(oclk_wr_cnt_reg__0[0]),
        .I2(oclk_wr_cnt_reg__0[1]),
        .I3(oclk_wr_cnt_reg__0[3]),
        .I4(oclk_wr_cnt_reg__0[2]),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(\oclk_wr_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    \oclk_wr_cnt[3]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(p_0_in14_in));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \oclk_wr_cnt[3]_i_3 
       (.I0(oclk_wr_cnt_reg__0[3]),
        .I1(oclk_wr_cnt_reg__0[2]),
        .I2(oclk_wr_cnt_reg__0[1]),
        .I3(oclk_wr_cnt_reg__0[0]),
        .O(oclk_wr_cnt0[3]));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \oclk_wr_cnt[3]_i_4 
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\oclk_wr_cnt[3]_i_4_n_0 ));
  FDRE \oclk_wr_cnt_reg[0] 
       (.C(CLK),
        .CE(p_0_in14_in),
        .D(\oclk_wr_cnt[0]_i_1_n_0 ),
        .Q(oclk_wr_cnt_reg__0[0]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDRE \oclk_wr_cnt_reg[1] 
       (.C(CLK),
        .CE(p_0_in14_in),
        .D(\oclk_wr_cnt[1]_i_1_n_0 ),
        .Q(oclk_wr_cnt_reg__0[1]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDSE \oclk_wr_cnt_reg[2] 
       (.C(CLK),
        .CE(p_0_in14_in),
        .D(oclk_wr_cnt0[2]),
        .Q(oclk_wr_cnt_reg__0[2]),
        .S(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDRE \oclk_wr_cnt_reg[3] 
       (.C(CLK),
        .CE(p_0_in14_in),
        .D(oclk_wr_cnt0[3]),
        .Q(oclk_wr_cnt_reg__0[3]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h2222222222202222)) 
    \odd_cwl.phy_cas_n[1]_i_1 
       (.I0(burst_addr_r_i_4_n_0),
        .I1(\odd_cwl.phy_ras_n[1]_i_2_n_0 ),
        .I2(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\odd_cwl.phy_cas_n[1]_i_1_n_0 ));
  FDRE \odd_cwl.phy_cas_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\odd_cwl.phy_cas_n[1]_i_1_n_0 ),
        .Q(phy_cas_n),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h1110111111111111)) 
    \odd_cwl.phy_ras_n[1]_i_1 
       (.I0(\odd_cwl.phy_ras_n[1]_i_2_n_0 ),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),
        .I2(init_complete_r_i_3_n_0),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(\odd_cwl.phy_ras_n[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAABAAAAA)) 
    \odd_cwl.phy_ras_n[1]_i_2 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I1(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),
        .O(\odd_cwl.phy_ras_n[1]_i_2_n_0 ));
  FDRE \odd_cwl.phy_ras_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\odd_cwl.phy_ras_n[1]_i_1_n_0 ),
        .Q(phy_ras_n),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \odd_cwl.phy_we_n[1]_i_1 
       (.I0(\odd_cwl.phy_ras_n[1]_i_2_n_0 ),
        .I1(calib_wrdata_en_i_2_n_0),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),
        .O(\odd_cwl.phy_we_n[1]_i_1_n_0 ));
  FDRE \odd_cwl.phy_we_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\odd_cwl.phy_we_n[1]_i_1_n_0 ),
        .Q(phy_we_n),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_14 
       (.I0(init_calib_complete_reg_rep),
        .I1(phy_address[50]),
        .I2(init_calib_complete_reg_rep__28[3]),
        .I3(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6] [3]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_15 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [31]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[50]),
        .I3(init_calib_complete_reg_rep__28[2]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6] [2]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_16 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [20]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[50]),
        .I3(init_calib_complete_reg_rep__28[1]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6] [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_17 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [8]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[50]),
        .I3(init_calib_complete_reg_rep__28[0]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6] [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_22 
       (.I0(init_calib_complete_reg_rep),
        .I1(phy_address[51]),
        .I2(init_calib_complete_reg_rep__28[7]),
        .I3(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_0 [3]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_23 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [32]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[51]),
        .I3(init_calib_complete_reg_rep__28[6]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_0 [2]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_24 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [21]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[51]),
        .I3(init_calib_complete_reg_rep__28[5]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_0 [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_25 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [9]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[51]),
        .I3(init_calib_complete_reg_rep__28[4]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_30 
       (.I0(init_calib_complete_reg_rep),
        .I1(phy_address[52]),
        .I2(init_calib_complete_reg_rep__28[11]),
        .I3(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_1 [3]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_31 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [33]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[52]),
        .I3(init_calib_complete_reg_rep__28[10]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_1 [2]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_32 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [22]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[52]),
        .I3(init_calib_complete_reg_rep__28[9]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_1 [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_33 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [10]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[52]),
        .I3(init_calib_complete_reg_rep__28[8]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_1 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_46 
       (.I0(init_calib_complete_reg_rep),
        .I1(phy_address[54]),
        .I2(init_calib_complete_reg_rep__28[15]),
        .I3(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_2 [3]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_47 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [34]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[54]),
        .I3(init_calib_complete_reg_rep__28[14]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_2 [2]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_48 
       (.I0(mc_ras_n),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[54]),
        .I3(init_calib_complete_reg_rep__28[13]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_2 [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_49 
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [11]),
        .I1(init_calib_complete_reg_rep),
        .I2(phy_address[54]),
        .I3(init_calib_complete_reg_rep__28[12]),
        .I4(\my_empty_reg[1]_9 ),
        .O(\my_empty_reg[6]_2 [0]));
  LUT6 #(
    .INIT(64'h000000000000000E)) 
    \one_rank.stg1_wr_done_i_1 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(stg1_wr_done),
        .I2(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I3(rdlvl_last_byte_done),
        .I4(complex_row1_rd_done_reg_0),
        .I5(complex_byte_rd_done),
        .O(\one_rank.stg1_wr_done_i_1_n_0 ));
  FDRE \one_rank.stg1_wr_done_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\one_rank.stg1_wr_done_i_1_n_0 ),
        .Q(\one_rank.stg1_wr_done_reg_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [332]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [9]),
        .O(D1[4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__0
       (.I0(mc_odt),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_odt),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [3]),
        .O(\wr_ptr_timing_reg[0]_4 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [326]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[9]),
        .O(\my_empty_reg[7]_7 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [321]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [4]),
        .O(\my_empty_reg[7]_16 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [315]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [4]),
        .O(\my_empty_reg[7]_24 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [309]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [4]),
        .O(\my_empty_reg[7]_32 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [350]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [9]),
        .O(\my_empty_reg[7]_39 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [345]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [4]),
        .O(\my_empty_reg[7]_48 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_10__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [339]),
        .I1(init_calib_complete_reg_rep__14),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [4]),
        .O(\my_empty_reg[7]_56 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [278]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [8]),
        .O(D1[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__0
       (.I0(mc_odt),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_odt),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [2]),
        .O(\wr_ptr_timing_reg[0]_4 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [270]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[8]),
        .O(\my_empty_reg[7]_7 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [263]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [3]),
        .O(\my_empty_reg[7]_16 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [255]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [3]),
        .O(\my_empty_reg[7]_24 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [247]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [3]),
        .O(\my_empty_reg[7]_32 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [302]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [8]),
        .O(\my_empty_reg[7]_39 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [295]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [3]),
        .O(\my_empty_reg[7]_48 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_11__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [287]),
        .I1(init_calib_complete_reg_rep__14),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [3]),
        .O(\my_empty_reg[7]_56 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_12
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [221]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [7]),
        .O(D1[2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_12__0
       (.I0(mc_odt),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_odt),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [1]),
        .O(\wr_ptr_timing_reg[0]_4 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_12__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [215]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[7]),
        .O(\my_empty_reg[7]_7 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_12__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [239]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [7]),
        .O(\my_empty_reg[7]_39 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_13__0
       (.I0(mc_odt),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_odt),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [0]),
        .O(\wr_ptr_timing_reg[0]_4 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_13__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [171]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [2]),
        .O(\my_empty_reg[7]_16 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_13__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [167]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [2]),
        .O(\my_empty_reg[7]_24 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_13__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [163]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [2]),
        .O(\my_empty_reg[7]_32 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_13__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [187]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [2]),
        .O(\my_empty_reg[7]_48 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_13__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [183]),
        .I1(init_calib_complete_reg_rep__14),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [2]),
        .O(\my_empty_reg[7]_56 [2]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_14__1
       (.I0(init_calib_complete_reg_rep__3),
        .I1(phy_bank[9]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [4]),
        .O(\wr_ptr_timing_reg[0]_12 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_14__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [129]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [1]),
        .O(\my_empty_reg[7]_16 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_14__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [123]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [1]),
        .O(\my_empty_reg[7]_24 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_14__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [117]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [1]),
        .O(\my_empty_reg[7]_32 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_14__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [153]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [1]),
        .O(\my_empty_reg[7]_48 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_14__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [147]),
        .I1(init_calib_complete_reg_rep__14),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [1]),
        .O(\my_empty_reg[7]_56 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [92]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [6]),
        .O(D1[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [6]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_bank[9]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [3]),
        .O(\wr_ptr_timing_reg[0]_12 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [86]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[6]),
        .O(\my_empty_reg[7]_7 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [81]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [0]),
        .O(\my_empty_reg[7]_16 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [75]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [0]),
        .O(\my_empty_reg[7]_24 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [69]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [0]),
        .O(\my_empty_reg[7]_32 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [110]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [6]),
        .O(\my_empty_reg[7]_39 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [105]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [0]),
        .O(\my_empty_reg[7]_48 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_15__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [99]),
        .I1(init_calib_complete_reg_rep__14),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [0]),
        .O(\my_empty_reg[7]_56 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_16__0
       (.I0(mc_cke),
        .I1(init_calib_complete_reg_rep__1),
        .I2(calib_cke),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [7]),
        .O(\wr_ptr_timing_reg[0]_3 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_16__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [3]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_bank[9]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [2]),
        .O(\wr_ptr_timing_reg[0]_12 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_17
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [19]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [5]),
        .O(D1[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_17__0
       (.I0(mc_cke),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_cke),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [6]),
        .O(\wr_ptr_timing_reg[0]_3 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_17__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [0]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_bank[9]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [1]),
        .O(\wr_ptr_timing_reg[0]_12 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_17__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [15]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[5]),
        .O(\my_empty_reg[7]_7 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_17__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [31]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [5]),
        .O(\my_empty_reg[7]_39 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [331]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [15]),
        .O(D2[5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__0
       (.I0(mc_cke),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_cke),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [5]),
        .O(\wr_ptr_timing_reg[0]_3 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [325]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[15]),
        .O(\my_empty_reg[7]_6 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [320]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [9]),
        .O(\my_empty_reg[7]_15 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [314]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [9]),
        .O(\my_empty_reg[7]_23 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [308]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [9]),
        .O(\my_empty_reg[7]_31 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [349]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [15]),
        .O(\my_empty_reg[7]_38 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [344]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [9]),
        .O(\my_empty_reg[7]_47 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_18__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [338]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [9]),
        .O(\my_empty_reg[7]_55 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [277]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [14]),
        .O(D2[4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__0
       (.I0(mc_cke),
        .I1(init_calib_complete_reg_rep__2),
        .I2(calib_cke),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [4]),
        .O(\wr_ptr_timing_reg[0]_3 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [269]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[14]),
        .O(\my_empty_reg[7]_6 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [262]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [8]),
        .O(\my_empty_reg[7]_15 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [254]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [8]),
        .O(\my_empty_reg[7]_23 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [246]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [8]),
        .O(\my_empty_reg[7]_31 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [301]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [14]),
        .O(\my_empty_reg[7]_38 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [294]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [8]),
        .O(\my_empty_reg[7]_47 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_19__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [286]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [8]),
        .O(\my_empty_reg[7]_55 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [333]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [4]),
        .O(D0[4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [220]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [13]),
        .O(D2[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [214]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[13]),
        .O(\my_empty_reg[7]_6 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [209]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [7]),
        .O(\my_empty_reg[7]_15 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [203]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [7]),
        .O(\my_empty_reg[7]_23 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [197]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [7]),
        .O(\my_empty_reg[7]_31 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [238]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [13]),
        .O(\my_empty_reg[7]_38 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [233]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [7]),
        .O(\my_empty_reg[7]_47 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_20__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [227]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [7]),
        .O(\my_empty_reg[7]_55 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_22
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [140]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [12]),
        .O(D2[2]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_22__1
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_bank[10]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [8]),
        .O(\wr_ptr_timing_reg[0]_11 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_22__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [134]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[12]),
        .O(\my_empty_reg[7]_6 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_22__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [158]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [12]),
        .O(\my_empty_reg[7]_38 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_23__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [7]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_bank[10]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [7]),
        .O(\wr_ptr_timing_reg[0]_11 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_23__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [80]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [6]),
        .O(\my_empty_reg[7]_15 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_23__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [74]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [6]),
        .O(\my_empty_reg[7]_23 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_23__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [68]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [6]),
        .O(\my_empty_reg[7]_31 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_23__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [104]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [6]),
        .O(\my_empty_reg[7]_47 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_23__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [98]),
        .I1(init_calib_complete_reg_rep__14),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [6]),
        .O(\my_empty_reg[7]_55 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_24
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [51]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [11]),
        .O(D2[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_24__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [4]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_bank[10]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [6]),
        .O(\wr_ptr_timing_reg[0]_11 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_24__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [47]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[11]),
        .O(\my_empty_reg[7]_6 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_24__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [63]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [11]),
        .O(\my_empty_reg[7]_38 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [18]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [10]),
        .O(D2[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [1]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_bank[10]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [5]),
        .O(\wr_ptr_timing_reg[0]_11 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [14]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[10]),
        .O(\my_empty_reg[7]_6 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [11]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [5]),
        .O(\my_empty_reg[7]_15 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [7]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [5]),
        .O(\my_empty_reg[7]_23 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [3]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [5]),
        .O(\my_empty_reg[7]_31 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [30]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [10]),
        .O(\my_empty_reg[7]_38 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [27]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [5]),
        .O(\my_empty_reg[7]_47 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_25__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [23]),
        .I1(init_calib_complete_reg_rep__14),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [5]),
        .O(\my_empty_reg[7]_55 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_26__0
       (.I0(\cmd_pipe_plus.mc_we_n_reg[1] ),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_we_n),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [9]),
        .O(\wr_ptr_timing_reg[0]_2 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_26__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [319]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [15]),
        .O(\my_empty_reg[7]_14 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_26__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [313]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [15]),
        .O(\my_empty_reg[7]_22 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_26__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [307]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [15]),
        .O(\my_empty_reg[7]_30 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_26__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [343]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [15]),
        .O(\my_empty_reg[7]_46 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_26__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [337]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [15]),
        .O(\my_empty_reg[7]_54 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [276]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [21]),
        .O(D3[5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [268]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[21]),
        .O(\my_empty_reg[7]_5 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [261]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [14]),
        .O(\my_empty_reg[7]_14 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [253]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [14]),
        .O(\my_empty_reg[7]_22 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [245]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [14]),
        .O(\my_empty_reg[7]_30 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [300]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [21]),
        .O(\my_empty_reg[7]_37 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [293]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [14]),
        .O(\my_empty_reg[7]_46 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_27__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [285]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [14]),
        .O(\my_empty_reg[7]_54 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [219]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [20]),
        .O(D3[4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [213]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[20]),
        .O(\my_empty_reg[7]_5 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [208]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [13]),
        .O(\my_empty_reg[7]_14 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [202]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [13]),
        .O(\my_empty_reg[7]_22 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [196]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [13]),
        .O(\my_empty_reg[7]_30 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [237]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [20]),
        .O(\my_empty_reg[7]_37 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [232]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [13]),
        .O(\my_empty_reg[7]_46 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_28__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [226]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [13]),
        .O(\my_empty_reg[7]_54 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_29
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [178]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [19]),
        .O(D3[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_29__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [174]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[19]),
        .O(\my_empty_reg[7]_5 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_29__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [190]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [19]),
        .O(\my_empty_reg[7]_37 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_2__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [327]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[4]),
        .O(\my_empty_reg[7]_8 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_2__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [351]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [4]),
        .O(\my_empty_reg[7]_40 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [279]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [3]),
        .O(D0[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [139]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [18]),
        .O(D3[2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__0
       (.I0(mc_cas_n),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_cs_n),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [8]),
        .O(\wr_ptr_timing_reg[0]_2 [0]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_30__1
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_bank[11]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [12]),
        .O(\wr_ptr_timing_reg[0]_10 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [133]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[18]),
        .O(\my_empty_reg[7]_5 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [128]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [12]),
        .O(\my_empty_reg[7]_14 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [122]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [12]),
        .O(\my_empty_reg[7]_22 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [116]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [12]),
        .O(\my_empty_reg[7]_30 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [157]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [18]),
        .O(\my_empty_reg[7]_37 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [152]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [12]),
        .O(\my_empty_reg[7]_46 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_30__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [146]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [12]),
        .O(\my_empty_reg[7]_54 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_31
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [91]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [17]),
        .O(D3[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_31__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [8]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_bank[11]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [11]),
        .O(\wr_ptr_timing_reg[0]_10 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_31__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [85]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[17]),
        .O(\my_empty_reg[7]_5 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_31__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [109]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [17]),
        .O(\my_empty_reg[7]_37 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [50]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [16]),
        .O(D3[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__0
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [5]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_bank[11]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [10]),
        .O(\wr_ptr_timing_reg[0]_10 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [46]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[16]),
        .O(\my_empty_reg[7]_5 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [43]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [11]),
        .O(\my_empty_reg[7]_14 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [39]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [11]),
        .O(\my_empty_reg[7]_22 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [35]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [11]),
        .O(\my_empty_reg[7]_30 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [62]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [16]),
        .O(\my_empty_reg[7]_37 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [59]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [11]),
        .O(\my_empty_reg[7]_46 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_32__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [55]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [11]),
        .O(\my_empty_reg[7]_54 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_33__1
       (.I0(\cmd_pipe_plus.mc_bank_reg[8] [2]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_bank[11]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [9]),
        .O(\wr_ptr_timing_reg[0]_10 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_33__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [10]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [10]),
        .O(\my_empty_reg[7]_14 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_33__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [6]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [10]),
        .O(\my_empty_reg[7]_22 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_33__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [2]),
        .I1(init_calib_complete_reg_rep__9),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [10]),
        .O(\my_empty_reg[7]_30 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_33__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [26]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [10]),
        .O(\my_empty_reg[7]_46 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_33__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [22]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [10]),
        .O(\my_empty_reg[7]_54 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_34
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [330]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [26]),
        .O(D4[4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_34__0
       (.I0(mc_cas_n),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_cas_n),
        .I3(\my_empty_reg[1]_0 ),
        .I4(\rd_ptr_reg_rep[3]_0 [10]),
        .O(\wr_ptr_timing_reg[0]_1 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_34__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [324]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[26]),
        .O(\my_empty_reg[7]_4 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_34__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [348]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [26]),
        .O(\my_empty_reg[7]_36 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [275]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [25]),
        .O(D4[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [267]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[25]),
        .O(\my_empty_reg[7]_4 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [260]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [21]),
        .O(\my_empty_reg[7]_13 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [252]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [21]),
        .O(\my_empty_reg[7]_21 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [244]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [21]),
        .O(\my_empty_reg[7]_29 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [299]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [25]),
        .O(\my_empty_reg[7]_36 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [292]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [21]),
        .O(\my_empty_reg[7]_45 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_35__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [284]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [21]),
        .O(\my_empty_reg[7]_53 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_36__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [207]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [20]),
        .O(\my_empty_reg[7]_13 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_36__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [201]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [20]),
        .O(\my_empty_reg[7]_21 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_36__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [195]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [20]),
        .O(\my_empty_reg[7]_29 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_36__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [231]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [20]),
        .O(\my_empty_reg[7]_45 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_36__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [225]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [20]),
        .O(\my_empty_reg[7]_53 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [177]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [24]),
        .O(D4[2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [173]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[24]),
        .O(\my_empty_reg[7]_4 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [170]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [19]),
        .O(\my_empty_reg[7]_13 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [166]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [19]),
        .O(\my_empty_reg[7]_21 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [162]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [19]),
        .O(\my_empty_reg[7]_29 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [189]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [24]),
        .O(\my_empty_reg[7]_36 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [186]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [19]),
        .O(\my_empty_reg[7]_45 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_37__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [182]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [19]),
        .O(\my_empty_reg[7]_53 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [138]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [23]),
        .O(D4[1]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_38__1
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[42]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [16]),
        .O(\wr_ptr_timing_reg[0]_9 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [132]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[23]),
        .O(\my_empty_reg[7]_4 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [127]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [18]),
        .O(\my_empty_reg[7]_13 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [121]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [18]),
        .O(\my_empty_reg[7]_21 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [115]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [18]),
        .O(\my_empty_reg[7]_29 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [156]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [23]),
        .O(\my_empty_reg[7]_36 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [151]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [18]),
        .O(\my_empty_reg[7]_45 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_38__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [145]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [18]),
        .O(\my_empty_reg[7]_53 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [90]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [22]),
        .O(D4[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [23]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[42]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [15]),
        .O(\wr_ptr_timing_reg[0]_9 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [84]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[22]),
        .O(\my_empty_reg[7]_4 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [79]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [17]),
        .O(\my_empty_reg[7]_13 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [73]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [17]),
        .O(\my_empty_reg[7]_21 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [67]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [17]),
        .O(\my_empty_reg[7]_29 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [108]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [22]),
        .O(\my_empty_reg[7]_36 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [103]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [17]),
        .O(\my_empty_reg[7]_45 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_39__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [97]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [17]),
        .O(\my_empty_reg[7]_53 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_3__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [271]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[3]),
        .O(\my_empty_reg[7]_8 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_3__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [303]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [3]),
        .O(\my_empty_reg[7]_40 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_40__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [12]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[42]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [14]),
        .O(\wr_ptr_timing_reg[0]_9 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_40__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [42]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [16]),
        .O(\my_empty_reg[7]_13 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_40__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [38]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [16]),
        .O(\my_empty_reg[7]_21 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_40__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [34]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [16]),
        .O(\my_empty_reg[7]_29 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_40__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [58]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [16]),
        .O(\my_empty_reg[7]_45 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_40__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [54]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [16]),
        .O(\my_empty_reg[7]_53 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_41__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [0]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[42]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [13]),
        .O(\wr_ptr_timing_reg[0]_9 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_42
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [329]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [31]),
        .O(D5[4]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_42__1
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[44]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [24]),
        .O(\wr_ptr_timing_reg[0]_8 [7]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_42__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [323]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[31]),
        .O(\my_empty_reg[7]_3 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_42__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [312]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [26]),
        .O(\my_empty_reg[7]_20 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_42__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [306]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [26]),
        .O(\my_empty_reg[7]_28 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_42__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [347]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [31]),
        .O(\my_empty_reg[7]_35 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_42__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [336]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [26]),
        .O(\my_empty_reg[7]_52 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_43
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [274]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [30]),
        .O(D5[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_43__1
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [25]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[44]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [23]),
        .O(\wr_ptr_timing_reg[0]_8 [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_43__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [266]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[30]),
        .O(\my_empty_reg[7]_3 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_43__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [251]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [25]),
        .O(\my_empty_reg[7]_20 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_43__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [243]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [25]),
        .O(\my_empty_reg[7]_28 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_43__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [298]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [30]),
        .O(\my_empty_reg[7]_35 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_43__8
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [283]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [25]),
        .O(\my_empty_reg[7]_52 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_44
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [218]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [29]),
        .O(D5[2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_44__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [14]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[44]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [22]),
        .O(\wr_ptr_timing_reg[0]_8 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_44__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [212]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[29]),
        .O(\my_empty_reg[7]_3 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_44__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [236]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [29]),
        .O(\my_empty_reg[7]_35 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_45__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [2]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[44]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [21]),
        .O(\wr_ptr_timing_reg[0]_8 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_45__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [165]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [24]),
        .O(\my_empty_reg[7]_20 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_45__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [161]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [24]),
        .O(\my_empty_reg[7]_28 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_45__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [181]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [24]),
        .O(\my_empty_reg[7]_52 [2]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_46__0
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[43]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [20]),
        .O(\wr_ptr_timing_reg[0]_8 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_46__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [120]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [23]),
        .O(\my_empty_reg[7]_20 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_46__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [114]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [23]),
        .O(\my_empty_reg[7]_28 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_46__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [144]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [23]),
        .O(\my_empty_reg[7]_52 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_47
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [89]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [28]),
        .O(D5[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_47__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [24]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[43]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [19]),
        .O(\wr_ptr_timing_reg[0]_8 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_47__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [83]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[28]),
        .O(\my_empty_reg[7]_3 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_47__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [72]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [22]),
        .O(\my_empty_reg[7]_20 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_47__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [66]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [22]),
        .O(\my_empty_reg[7]_28 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_47__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [107]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [28]),
        .O(\my_empty_reg[7]_35 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_47__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [96]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [22]),
        .O(\my_empty_reg[7]_52 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_48__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [13]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[43]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [18]),
        .O(\wr_ptr_timing_reg[0]_8 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_49
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [17]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [27]),
        .O(D5[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_49__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [1]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[43]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [17]),
        .O(\wr_ptr_timing_reg[0]_8 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_49__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [13]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[27]),
        .O(\my_empty_reg[7]_3 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_49__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [29]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [27]),
        .O(\my_empty_reg[7]_35 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [179]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [2]),
        .O(D0[2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [328]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [37]),
        .O(D6[5]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_50__0
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[45]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [32]),
        .O(\wr_ptr_timing_reg[0]_7 [7]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [322]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[37]),
        .O(\my_empty_reg[7]_2 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [318]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [26]),
        .O(\my_empty_reg[7]_12 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [311]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [31]),
        .O(\my_empty_reg[7]_19 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [305]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [31]),
        .O(\my_empty_reg[7]_27 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [346]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [37]),
        .O(\my_empty_reg[7]_34 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [342]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [26]),
        .O(\my_empty_reg[7]_44 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_50__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [335]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [31]),
        .O(\my_empty_reg[7]_51 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [273]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [36]),
        .O(D6[4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [26]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[45]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [31]),
        .O(\wr_ptr_timing_reg[0]_7 [6]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [265]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[36]),
        .O(\my_empty_reg[7]_2 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [259]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [25]),
        .O(\my_empty_reg[7]_12 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [250]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [30]),
        .O(\my_empty_reg[7]_19 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [242]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [30]),
        .O(\my_empty_reg[7]_27 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [297]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [36]),
        .O(\my_empty_reg[7]_34 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [291]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [25]),
        .O(\my_empty_reg[7]_44 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_51__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [282]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [30]),
        .O(\my_empty_reg[7]_51 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_52
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [217]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [35]),
        .O(D6[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_52__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [15]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[45]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [30]),
        .O(\wr_ptr_timing_reg[0]_7 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_52__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [211]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[35]),
        .O(\my_empty_reg[7]_2 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_52__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [200]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [29]),
        .O(\my_empty_reg[7]_19 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_52__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [194]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [29]),
        .O(\my_empty_reg[7]_27 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_52__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [235]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [35]),
        .O(\my_empty_reg[7]_34 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_52__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [224]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [29]),
        .O(\my_empty_reg[7]_51 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_53__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [3]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[45]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [29]),
        .O(\wr_ptr_timing_reg[0]_7 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_53__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [169]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [24]),
        .O(\my_empty_reg[7]_12 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_53__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [185]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [24]),
        .O(\my_empty_reg[7]_44 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_54
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [137]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [34]),
        .O(D6[2]));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_54__0
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[46]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [28]),
        .O(\wr_ptr_timing_reg[0]_7 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_54__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [131]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[34]),
        .O(\my_empty_reg[7]_2 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_54__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [126]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [23]),
        .O(\my_empty_reg[7]_12 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_54__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [155]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [34]),
        .O(\my_empty_reg[7]_34 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_54__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [150]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [23]),
        .O(\my_empty_reg[7]_44 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_55__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [27]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[46]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [27]),
        .O(\wr_ptr_timing_reg[0]_7 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_55__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [78]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [22]),
        .O(\my_empty_reg[7]_12 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_55__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [71]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [28]),
        .O(\my_empty_reg[7]_19 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_55__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [65]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [28]),
        .O(\my_empty_reg[7]_27 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_55__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [102]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [22]),
        .O(\my_empty_reg[7]_44 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_55__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [95]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [28]),
        .O(\my_empty_reg[7]_51 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_56
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [49]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [33]),
        .O(D6[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_56__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [16]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[46]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [26]),
        .O(\wr_ptr_timing_reg[0]_7 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_56__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [45]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[33]),
        .O(\my_empty_reg[7]_2 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_56__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [61]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [33]),
        .O(\my_empty_reg[7]_34 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_57
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [16]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [32]),
        .O(D6[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_57__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [4]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[46]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [25]),
        .O(\wr_ptr_timing_reg[0]_7 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_57__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [12]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[32]),
        .O(\my_empty_reg[7]_2 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_57__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [5]),
        .I1(init_calib_complete_reg_rep__7),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [27]),
        .O(\my_empty_reg[7]_19 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_57__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [1]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [27]),
        .O(\my_empty_reg[7]_27 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_57__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [28]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [32]),
        .O(\my_empty_reg[7]_34 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_57__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [21]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [27]),
        .O(\my_empty_reg[7]_51 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_58__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [317]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [31]),
        .O(\my_empty_reg[7]_11 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_58__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [310]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [37]),
        .O(\my_empty_reg[7]_18 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_58__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [304]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [37]),
        .O(\my_empty_reg[7]_26 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_58__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [341]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[510]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [31]),
        .O(\my_empty_reg[7]_43 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_58__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [334]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [37]),
        .O(\my_empty_reg[7]_50 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [272]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [43]),
        .O(D7[5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [264]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[43]),
        .O(\my_empty_reg[7]_1 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [258]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [30]),
        .O(\my_empty_reg[7]_11 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [249]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [36]),
        .O(\my_empty_reg[7]_18 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [241]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [36]),
        .O(\my_empty_reg[7]_26 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [296]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [43]),
        .O(\my_empty_reg[7]_33 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [290]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [30]),
        .O(\my_empty_reg[7]_43 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_59__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [281]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [36]),
        .O(\my_empty_reg[7]_50 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_5__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [175]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[2]),
        .O(\my_empty_reg[7]_8 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_5__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [191]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [2]),
        .O(\my_empty_reg[7]_40 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [141]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [1]),
        .O(D0[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [216]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [42]),
        .O(D7[4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [210]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[42]),
        .O(\my_empty_reg[7]_1 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [206]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [29]),
        .O(\my_empty_reg[7]_11 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [199]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [35]),
        .O(\my_empty_reg[7]_18 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [193]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [35]),
        .O(\my_empty_reg[7]_26 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [234]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [42]),
        .O(\my_empty_reg[7]_33 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [230]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[511]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [29]),
        .O(\my_empty_reg[7]_43 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_60__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [223]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [35]),
        .O(\my_empty_reg[7]_50 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_61
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [176]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [41]),
        .O(D7[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_61__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [172]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[41]),
        .O(\my_empty_reg[7]_1 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_61__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [188]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [41]),
        .O(\my_empty_reg[7]_33 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_62
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [136]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [40]),
        .O(D7[2]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_62__0
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[47]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [36]),
        .O(\wr_ptr_timing_reg[0]_6 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_62__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [130]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[40]),
        .O(\my_empty_reg[7]_1 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_62__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [119]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [34]),
        .O(\my_empty_reg[7]_18 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_62__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [113]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [34]),
        .O(\my_empty_reg[7]_26 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_62__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [154]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [40]),
        .O(\my_empty_reg[7]_33 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_62__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [143]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [34]),
        .O(\my_empty_reg[7]_50 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_63
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [88]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [39]),
        .O(D7[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_63__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [28]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[47]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [35]),
        .O(\wr_ptr_timing_reg[0]_6 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_63__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [82]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[39]),
        .O(\my_empty_reg[7]_1 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_63__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [77]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [28]),
        .O(\my_empty_reg[7]_11 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_63__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [106]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [39]),
        .O(\my_empty_reg[7]_33 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_63__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [101]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [28]),
        .O(\my_empty_reg[7]_43 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_64
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [48]),
        .I1(init_calib_complete_reg_rep__0),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [38]),
        .O(D7[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_64__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [17]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[47]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [34]),
        .O(\wr_ptr_timing_reg[0]_6 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_64__1
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [44]),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[38]),
        .O(\my_empty_reg[7]_1 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_64__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [37]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [33]),
        .O(\my_empty_reg[7]_18 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_64__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [33]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [33]),
        .O(\my_empty_reg[7]_26 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_64__5
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [60]),
        .I1(init_calib_complete_reg_rep__10),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [38]),
        .O(\my_empty_reg[7]_33 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_64__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [53]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [33]),
        .O(\my_empty_reg[7]_50 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_65__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [5]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[47]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [33]),
        .O(\wr_ptr_timing_reg[0]_6 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_65__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [9]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [27]),
        .O(\my_empty_reg[7]_11 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_65__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [4]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [32]),
        .O(\my_empty_reg[7]_18 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_65__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [0]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [32]),
        .O(\my_empty_reg[7]_26 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_65__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [25]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [27]),
        .O(\my_empty_reg[7]_43 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_65__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [20]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [32]),
        .O(\my_empty_reg[7]_50 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_66__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [316]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [37]),
        .O(\my_empty_reg[7]_10 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_66__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [340]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [37]),
        .O(\my_empty_reg[7]_42 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_67__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [257]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [36]),
        .O(\my_empty_reg[7]_10 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_67__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [248]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [43]),
        .O(\my_empty_reg[7]_17 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_67__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [240]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [43]),
        .O(\my_empty_reg[7]_25 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_67__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [289]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [36]),
        .O(\my_empty_reg[7]_42 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_67__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [280]),
        .I1(init_calib_complete_reg_rep__12),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [43]),
        .O(\my_empty_reg[7]_49 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_68__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [205]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [35]),
        .O(\my_empty_reg[7]_10 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_68__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [198]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [42]),
        .O(\my_empty_reg[7]_17 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_68__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [192]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [42]),
        .O(\my_empty_reg[7]_25 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_68__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [229]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [35]),
        .O(\my_empty_reg[7]_42 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_68__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [222]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [42]),
        .O(\my_empty_reg[7]_49 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_69__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [164]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [41]),
        .O(\my_empty_reg[7]_17 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_69__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [160]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [41]),
        .O(\my_empty_reg[7]_25 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_69__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [180]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [41]),
        .O(\my_empty_reg[7]_49 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_6__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [135]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[1]),
        .O(\my_empty_reg[7]_8 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_6__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [159]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [1]),
        .O(\my_empty_reg[7]_40 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [93]),
        .I1(init_calib_complete_reg_rep__1),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1] ),
        .I4(\rd_ptr_reg_rep[3] [0]),
        .O(D0[0]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_70__0
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[48]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [40]),
        .O(D8[3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_70__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [125]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [34]),
        .O(\my_empty_reg[7]_10 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_70__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [118]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [40]),
        .O(\my_empty_reg[7]_17 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_70__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [112]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [40]),
        .O(\my_empty_reg[7]_25 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_70__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [149]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [34]),
        .O(\my_empty_reg[7]_42 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_70__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [142]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [40]),
        .O(\my_empty_reg[7]_49 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_71__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [29]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[48]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [39]),
        .O(D8[2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_71__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [70]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [39]),
        .O(\my_empty_reg[7]_17 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_71__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [64]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [39]),
        .O(\my_empty_reg[7]_25 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_71__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [94]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [39]),
        .O(\my_empty_reg[7]_49 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_72__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [18]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[48]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [38]),
        .O(D8[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_72__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [41]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [33]),
        .O(\my_empty_reg[7]_10 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_72__3
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [36]),
        .I1(init_calib_complete_reg_rep__6),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_4 ),
        .I4(\rd_ptr_reg_rep[3]_3 [38]),
        .O(\my_empty_reg[7]_17 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_72__4
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [32]),
        .I1(init_calib_complete_reg_rep__8),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_5 ),
        .I4(\rd_ptr_reg_rep[3]_4 [38]),
        .O(\my_empty_reg[7]_25 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_72__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [57]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[125]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [33]),
        .O(\my_empty_reg[7]_42 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_72__7
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [52]),
        .I1(init_calib_complete_reg_rep__13),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_8 ),
        .I4(\rd_ptr_reg_rep[3]_7 [38]),
        .O(\my_empty_reg[7]_49 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_73__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [6]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[48]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [37]),
        .O(D8[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_73__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [8]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [32]),
        .O(\my_empty_reg[7]_10 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_73__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [24]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[61]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [32]),
        .O(\my_empty_reg[7]_42 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_75__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [256]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [43]),
        .O(\my_empty_reg[7]_9 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_75__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [288]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [43]),
        .O(\my_empty_reg[7]_41 [5]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_76__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [204]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [42]),
        .O(\my_empty_reg[7]_9 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_76__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [228]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [42]),
        .O(\my_empty_reg[7]_41 [4]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_77__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [168]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [41]),
        .O(\my_empty_reg[7]_9 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_77__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [184]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [41]),
        .O(\my_empty_reg[7]_41 [3]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    out_fifo_i_78__0
       (.I0(init_calib_complete_reg_rep__2),
        .I1(phy_address[49]),
        .I2(\my_empty_reg[1]_1 ),
        .I3(\rd_ptr_reg_rep[3]_1 [44]),
        .O(\wr_ptr_timing_reg[0]_5 [3]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_78__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [124]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [40]),
        .O(\my_empty_reg[7]_9 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_78__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [148]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[505]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [40]),
        .O(\my_empty_reg[7]_41 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_79__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [30]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[49]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [43]),
        .O(\wr_ptr_timing_reg[0]_5 [2]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_79__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [76]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[441]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [39]),
        .O(\my_empty_reg[7]_9 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_79__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [100]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [39]),
        .O(\my_empty_reg[7]_41 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_7__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [87]),
        .I1(init_calib_complete_reg_rep__4),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_2 ),
        .I4(mem_out[0]),
        .O(\my_empty_reg[7]_8 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_7__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [111]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[447]),
        .I3(\my_empty_reg[1]_6 ),
        .I4(\rd_ptr_reg_rep[3]_5 [0]),
        .O(\my_empty_reg[7]_40 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_80__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [19]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[49]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [42]),
        .O(\wr_ptr_timing_reg[0]_5 [1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_80__2
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [40]),
        .I1(init_calib_complete_reg_rep__5),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_3 ),
        .I4(\rd_ptr_reg_rep[3]_2 [38]),
        .O(\my_empty_reg[7]_9 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_80__6
       (.I0(\write_buffer.wr_buf_out_data_reg[511] [56]),
        .I1(init_calib_complete_reg_rep__11),
        .I2(phy_wrdata[190]),
        .I3(\my_empty_reg[1]_7 ),
        .I4(\rd_ptr_reg_rep[3]_6 [38]),
        .O(\my_empty_reg[7]_41 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_81__0
       (.I0(\cmd_pipe_plus.mc_address_reg[40] [7]),
        .I1(init_calib_complete_reg_rep__2),
        .I2(phy_address[49]),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [41]),
        .O(\wr_ptr_timing_reg[0]_5 [0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    out_fifo_i_8__1
       (.I0(mc_ras_n),
        .I1(init_calib_complete_reg_rep__3),
        .I2(phy_ras_n),
        .I3(\my_empty_reg[1]_1 ),
        .I4(\rd_ptr_reg_rep[3]_1 [0]),
        .O(\wr_ptr_timing_reg[0]_13 ));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[0]_i_1 
       (.I0(mc_cmd[0]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_cmd[0]),
        .O(\phy_ctl_wd_i1_reg[24] [0]));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[17]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[0] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_0[0]),
        .O(\phy_ctl_wd_i1_reg[24] [3]));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[18]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[1] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_0[1]),
        .O(\phy_ctl_wd_i1_reg[24] [4]));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[19]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[2] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_0[2]),
        .O(\phy_ctl_wd_i1_reg[24] [5]));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[1]_i_1 
       (.I0(mc_cmd[1]),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_cmd[1]),
        .O(\phy_ctl_wd_i1_reg[24] [1]));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[20]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_0[3]),
        .O(\phy_ctl_wd_i1_reg[24] [6]));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[21]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[4] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_0[4]),
        .O(\phy_ctl_wd_i1_reg[24] [7]));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[22]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[5] ),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_data_offset_0[5]),
        .O(\phy_ctl_wd_i1_reg[24] [8]));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \phy_ctl_wd_i1[2]_i_1 
       (.I0(mc_cas_n),
        .I1(init_calib_complete_reg_rep__15),
        .I2(calib_cmd[2]),
        .O(\phy_ctl_wd_i1_reg[24] [2]));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT2 #(
    .INIT(4'hE)) 
    phy_ctl_wr_i1_i_1
       (.I0(\wr_ptr_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .O(phy_ctl_wr_i1_reg));
  FDCE phy_reset_n_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(rstdiv0_sync_r1_reg_rep__3),
        .D(cnt_pwron_reset_done_r),
        .Q(phy_reset_n));
  FDRE pi_calib_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_calib_done_r),
        .Q(pi_calib_done),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    pi_calib_done_r_i_1
       (.I0(pi_calib_rank_done_r),
        .I1(pi_calib_done_r),
        .O(pi_calib_done_r_i_1_n_0));
  FDRE pi_calib_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_calib_done_r_i_1_n_0),
        .Q(pi_calib_done_r),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT2 #(
    .INIT(4'h2)) 
    pi_calib_rank_done_r_i_1
       (.I0(pi_phase_locked_all_r3),
        .I1(pi_phase_locked_all_r4),
        .O(init_next_state1110_out));
  FDRE pi_calib_rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_next_state1110_out),
        .Q(pi_calib_rank_done_r),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE pi_dqs_found_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_found_done_r_reg),
        .Q(pi_dqs_found_done_r1),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT5 #(
    .INIT(32'h000000AE)) 
    pi_dqs_found_start_i_1
       (.I0(\pi_dqs_found_any_bank_reg[0] ),
        .I1(\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),
        .I2(dqs_found_done_r_reg),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .I4(wrlvl_byte_redo),
        .O(pi_dqs_found_start_i_1_n_0));
  FDRE pi_dqs_found_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_start_i_1_n_0),
        .Q(\pi_dqs_found_any_bank_reg[0] ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(A_rst_primitives_reg),
        .Q(pi_phase_locked_all_r1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_phase_locked_all_r1),
        .Q(pi_phase_locked_all_r2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r3_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_phase_locked_all_r2),
        .Q(pi_phase_locked_all_r3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_phase_locked_all_r3),
        .Q(pi_phase_locked_all_r4),
        .R(1'b0));
  FDRE prbs_last_byte_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_done_reg_0),
        .Q(prbs_last_byte_done_r),
        .R(1'b0));
  FDRE prbs_rdlvl_done_pulse_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_done_reg),
        .Q(complex_row1_rd_done_reg_0),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 " *) 
  SRL16E \prech_done_dly_r_reg[15]_srl16 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(prech_done_pre),
        .Q(\prech_done_dly_r_reg[15]_srl16_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0000)) 
    \prech_done_dly_r_reg[15]_srl16_i_1 
       (.I0(\prech_done_dly_r_reg[15]_srl16_i_2_n_0 ),
        .I1(rdlvl_start_pre_i_2_n_0),
        .I2(stg1_wr_done),
        .I3(\prech_done_dly_r_reg[15]_srl16_i_3_n_0 ),
        .I4(prech_pending_r_reg_n_0),
        .I5(prech_pending_r_reg_0),
        .O(prech_done_pre));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \prech_done_dly_r_reg[15]_srl16_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\prech_done_dly_r_reg[15]_srl16_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF020202)) 
    \prech_done_dly_r_reg[15]_srl16_i_3 
       (.I0(dqs_found_prech_req),
        .I1(burst_addr_r_i_7_n_0),
        .I2(\prech_done_dly_r_reg[15]_srl16_i_4_n_0 ),
        .I3(complex_oclkdelay_calib_start_r1),
        .I4(\complex_wait_cnt[3]_i_3_n_0 ),
        .I5(\prech_done_dly_r_reg[15]_srl16_i_5_n_0 ),
        .O(\prech_done_dly_r_reg[15]_srl16_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \prech_done_dly_r_reg[15]_srl16_i_4 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\prech_done_dly_r_reg[15]_srl16_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFEAFFEAFFFFFFEA)) 
    \prech_done_dly_r_reg[15]_srl16_i_5 
       (.I0(\num_refresh[3]_i_7_n_0 ),
        .I1(\complex_row_cnt_ocal[7]_i_7_n_0 ),
        .I2(prbs_last_byte_done_r),
        .I3(\prech_done_dly_r_reg[15]_srl16_i_6_n_0 ),
        .I4(cnt_cmd_done_r),
        .I5(burst_addr_r_i_3_n_0),
        .O(\prech_done_dly_r_reg[15]_srl16_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000005400)) 
    \prech_done_dly_r_reg[15]_srl16_i_6 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(rdlvl_last_byte_done_r),
        .I2(prbs_last_byte_done_r),
        .I3(\init_state_r[1]_i_28_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .O(\prech_done_dly_r_reg[15]_srl16_i_6_n_0 ));
  FDRE prech_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\prech_done_dly_r_reg[15]_srl16_n_0 ),
        .Q(prech_done),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0D0C)) 
    prech_pending_r_i_1
       (.I0(prech_done_pre),
        .I1(prech_pending_r_reg_0),
        .I2(rstdiv0_sync_r1_reg_rep__22),
        .I3(prech_pending_r_reg_n_0),
        .O(prech_pending_r_i_1_n_0));
  FDRE prech_pending_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(prech_pending_r_i_1_n_0),
        .Q(prech_pending_r_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h55545454)) 
    prech_req_posedge_r_i_1
       (.I0(prech_req_r),
        .I1(wrcal_prech_req),
        .I2(rdlvl_prech_req),
        .I3(dqs_found_prech_req),
        .I4(\back_to_back_reads_4_1.num_reads_reg[1]_0 ),
        .O(prech_req_posedge_r0));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    prech_req_posedge_r_i_2
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(\back_to_back_reads_4_1.num_reads_reg[1]_0 ));
  FDRE prech_req_posedge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(prech_req_posedge_r0),
        .Q(prech_pending_r_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE prech_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(prech_req),
        .Q(prech_req_r),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT5 #(
    .INIT(32'h80000000)) 
    pwron_ce_r_i_1
       (.I0(cnt_pwron_ce_r_reg__0[9]),
        .I1(cnt_pwron_ce_r_reg__0[7]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg__0[6]),
        .I4(cnt_pwron_ce_r_reg__0[8]),
        .O(pwron_ce_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    pwron_ce_r_i_2
       (.I0(cnt_pwron_ce_r_reg__0[5]),
        .I1(cnt_pwron_ce_r_reg__0[3]),
        .I2(cnt_pwron_ce_r_reg__0[0]),
        .I3(cnt_pwron_ce_r_reg__0[1]),
        .I4(cnt_pwron_ce_r_reg__0[2]),
        .I5(cnt_pwron_ce_r_reg__0[4]),
        .O(pwron_ce_r_i_2_n_0));
  FDRE pwron_ce_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pwron_ce_r_i_1_n_0),
        .Q(pwron_ce_r),
        .R(rstdiv0_sync_r1_reg_rep__4));
  FDRE rdlvl_last_byte_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_last_byte_done),
        .Q(rdlvl_last_byte_done_r),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 " *) 
  SRL16E \rdlvl_start_dly0_r_reg[13]_srl14 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(rdlvl_start_pre),
        .Q(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ));
  FDRE \rdlvl_start_dly0_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ),
        .Q(rdlvl_start_dly0_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF8)) 
    rdlvl_start_pre_i_1
       (.I0(dqs_found_done_r_reg),
        .I1(rdlvl_start_pre_i_2_n_0),
        .I2(rdlvl_start_pre),
        .O(rdlvl_start_pre_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    rdlvl_start_pre_i_2
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\wrcal_reads[7]_i_5_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(rdlvl_start_pre_i_2_n_0));
  FDRE rdlvl_start_pre_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_start_pre_i_1_n_0),
        .Q(rdlvl_start_pre),
        .R(rstdiv0_sync_r1_reg_rep__3));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT4 #(
    .INIT(16'hBF80)) 
    rdlvl_stg1_start_i_1
       (.I0(rdlvl_start_dly0_r),
        .I1(rdlvl_start_pre_i_2_n_0),
        .I2(dqs_found_done_r_reg),
        .I3(rdlvl_stg1_start_r_reg),
        .O(rdlvl_stg1_start_i_1_n_0));
  FDRE rdlvl_stg1_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_start_i_1_n_0),
        .Q(rdlvl_stg1_start_r_reg),
        .R(rstdiv0_sync_r1_reg_rep__4));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT4 #(
    .INIT(16'h000E)) 
    read_calib_i_1
       (.I0(read_calib),
        .I1(read_calib_i_2_n_0),
        .I2(pi_calib_done),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .O(read_calib_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000020000000)) 
    read_calib_i_2
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(init_state_r),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(read_calib_i_2_n_0));
  FDRE read_calib_reg
       (.C(CLK),
        .CE(1'b1),
        .D(read_calib_i_1_n_0),
        .Q(read_calib),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \reg_ctrl_cnt_r[0]_i_1 
       (.I0(reg_ctrl_cnt_r_reg__0[0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \reg_ctrl_cnt_r[1]_i_1 
       (.I0(reg_ctrl_cnt_r_reg__0[0]),
        .I1(reg_ctrl_cnt_r_reg__0[1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \reg_ctrl_cnt_r[2]_i_1 
       (.I0(reg_ctrl_cnt_r_reg__0[2]),
        .I1(reg_ctrl_cnt_r_reg__0[1]),
        .I2(reg_ctrl_cnt_r_reg__0[0]),
        .O(p_0_in__2[2]));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \reg_ctrl_cnt_r[3]_i_1 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000200000000000)) 
    \reg_ctrl_cnt_r[3]_i_2 
       (.I0(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\reg_ctrl_cnt_r[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \reg_ctrl_cnt_r[3]_i_3 
       (.I0(reg_ctrl_cnt_r_reg__0[3]),
        .I1(reg_ctrl_cnt_r_reg__0[2]),
        .I2(reg_ctrl_cnt_r_reg__0[0]),
        .I3(reg_ctrl_cnt_r_reg__0[1]),
        .O(p_0_in__2[3]));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \reg_ctrl_cnt_r[3]_i_4 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\reg_ctrl_cnt_r[3]_i_4_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[0] 
       (.C(CLK),
        .CE(\reg_ctrl_cnt_r[3]_i_2_n_0 ),
        .D(p_0_in__2[0]),
        .Q(reg_ctrl_cnt_r_reg__0[0]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[1] 
       (.C(CLK),
        .CE(\reg_ctrl_cnt_r[3]_i_2_n_0 ),
        .D(p_0_in__2[1]),
        .Q(reg_ctrl_cnt_r_reg__0[1]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[2] 
       (.C(CLK),
        .CE(\reg_ctrl_cnt_r[3]_i_2_n_0 ),
        .D(p_0_in__2[2]),
        .Q(reg_ctrl_cnt_r_reg__0[2]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[3] 
       (.C(CLK),
        .CE(\reg_ctrl_cnt_r[3]_i_2_n_0 ),
        .D(p_0_in__2[3]),
        .Q(reg_ctrl_cnt_r_reg__0[3]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE reset_rd_addr_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_ocal_reset_rd_addr_reg_n_0),
        .Q(reset_rd_addr_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \row_cnt_victim_rotate.complex_row_cnt[0]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \row_cnt_victim_rotate.complex_row_cnt[1]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ),
        .O(p_0_in__6[1]));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT4 #(
    .INIT(16'h0078)) 
    \row_cnt_victim_rotate.complex_row_cnt[2]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ),
        .O(p_0_in__6[2]));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT5 #(
    .INIT(32'h00007F80)) 
    \row_cnt_victim_rotate.complex_row_cnt[3]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ),
        .O(p_0_in__6[3]));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ),
        .O(p_0_in__6[4]));
  LUT6 #(
    .INIT(64'h00000000BFFF4000)) 
    \row_cnt_victim_rotate.complex_row_cnt[5]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ),
        .O(p_0_in__6[5]));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \row_cnt_victim_rotate.complex_row_cnt[5]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \row_cnt_victim_rotate.complex_row_cnt[6]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ),
        .O(p_0_in__6[6]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[6]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT5 #(
    .INIT(32'hEF00EFEF)) 
    \row_cnt_victim_rotate.complex_row_cnt[6]_i_3 
       (.I0(complex_sample_cnt_inc_r2),
        .I1(reset_rd_addr_r1),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_5 ),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF08FFFFFFFF)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0 ),
        .I1(wr_victim_inc),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .I4(rdlvl_stg1_done_reg_0),
        .I5(prbs_last_byte_done_r),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_11 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_11_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_12 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_12_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_13 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_13_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_14 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_14_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_15 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_15_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_16 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_16_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_17 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_17_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_18 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .O(complex_row_cnt0));
  LUT6 #(
    .INIT(64'hEEEEEEE0EEE0EEE0)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0 ),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(wr_victim_inc),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0 ),
        .I4(\complex_row_cnt_ocal[7]_i_7_n_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_7_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT5 #(
    .INIT(32'h00000028)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_3 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_5 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0 ),
        .I3(reset_rd_addr_r1),
        .I4(complex_sample_cnt_inc_r2),
        .O(p_0_in__6[7]));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_5 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_6 
       (.I0(complex_sample_cnt_inc_r2),
        .I1(reset_rd_addr_r1),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000010000000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_7 
       (.I0(\complex_row_cnt_ocal[7]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(complex_sample_cnt_inc_i_3_n_0),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_7_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[0] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[1] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(p_0_in__6[1]),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[2] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(p_0_in__6[2]),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[3] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(p_0_in__6[3]),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[4] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(p_0_in__6[4]),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[5] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(p_0_in__6[5]),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[6] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(p_0_in__6[6]),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[7] 
       (.C(CLK),
        .CE(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .D(p_0_in__6[7]),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  CARRY4 \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10 
       (.CI(1'b0),
        .CO({\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_0 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_1 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_2 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] }),
        .O({\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_4 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_5 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_6 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_7 }),
        .S({\row_cnt_victim_rotate.complex_row_cnt[7]_i_15_n_0 ,\row_cnt_victim_rotate.complex_row_cnt[7]_i_16_n_0 ,\row_cnt_victim_rotate.complex_row_cnt[7]_i_17_n_0 ,complex_row_cnt0}));
  CARRY4 \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8 
       (.CI(\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_0 ),
        .CO({\NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_CO_UNCONNECTED [3:2],\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_2 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_O_UNCONNECTED [3],\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_5 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_6 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_8_n_7 }),
        .S({1'b0,1'b1,1'b1,1'b1}));
  CARRY4 \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9 
       (.CI(\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_0 ),
        .CO({\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_0 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_1 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_2 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_3 }),
        .CYINIT(1'b0),
        .DI({\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ,\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ,\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ,\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] }),
        .O({\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_4 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_5 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_6 ,\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_7 }),
        .S({\row_cnt_victim_rotate.complex_row_cnt[7]_i_11_n_0 ,\row_cnt_victim_rotate.complex_row_cnt[7]_i_12_n_0 ,\row_cnt_victim_rotate.complex_row_cnt[7]_i_13_n_0 ,\row_cnt_victim_rotate.complex_row_cnt[7]_i_14_n_0 }));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \stg1_wr_rd_cnt[0]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\stg1_wr_rd_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0D00000D0D0D0D0D)) 
    \stg1_wr_rd_cnt[1]_i_1 
       (.I0(stg1_wr_done),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(rstdiv0_sync_r1_reg_rep__22),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I5(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT4 #(
    .INIT(16'hE1FF)) 
    \stg1_wr_rd_cnt[2]_i_1 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\stg1_wr_rd_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h008AAA8AAA8A008A)) 
    \stg1_wr_rd_cnt[3]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__22_0),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(\stg1_wr_rd_cnt[3]_i_3_n_0 ),
        .I3(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .I4(\stg1_wr_rd_cnt[3]_i_4_n_0 ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\stg1_wr_rd_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00005D00)) 
    \stg1_wr_rd_cnt[3]_i_3 
       (.I0(complex_row1_wr_done),
        .I1(complex_row0_rd_done),
        .I2(complex_row1_rd_done),
        .I3(complex_row0_wr_done),
        .I4(wr_victim_inc),
        .O(\stg1_wr_rd_cnt[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \stg1_wr_rd_cnt[3]_i_4 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\stg1_wr_rd_cnt[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000D0D000D0D0D0D)) 
    \stg1_wr_rd_cnt[4]_i_1 
       (.I0(stg1_wr_done),
        .I1(rdlvl_stg1_done_reg_0),
        .I2(rstdiv0_sync_r1_reg_rep__22),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt[7]_i_2_n_0 ),
        .I5(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000100000000000)) 
    \stg1_wr_rd_cnt[4]_i_2 
       (.I0(\wrcal_start_dly_r_reg[4]_srl5_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(stg1_wr_done));
  LUT3 #(
    .INIT(8'h01)) 
    \stg1_wr_rd_cnt[4]_i_3 
       (.I0(complex_ocal_reset_rd_addr_i_2_n_0),
        .I1(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .I2(rdlvl_last_byte_done),
        .O(\stg1_wr_rd_cnt[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \stg1_wr_rd_cnt[4]_i_4 
       (.I0(wr_victim_inc_i_3_n_0),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I4(complex_sample_cnt_inc_i_2_n_0),
        .O(\stg1_wr_rd_cnt[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hEBEEAAAA)) 
    \stg1_wr_rd_cnt[5]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(\stg1_wr_rd_cnt[7]_i_2_n_0 ),
        .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\stg1_wr_rd_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEBEAAAAAAAA)) 
    \stg1_wr_rd_cnt[6]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\stg1_wr_rd_cnt[7]_i_2_n_0 ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I5(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\stg1_wr_rd_cnt[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT5 #(
    .INIT(32'h00001011)) 
    \stg1_wr_rd_cnt[6]_i_2 
       (.I0(\stg1_wr_rd_cnt[3]_i_3_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__22),
        .I2(rdlvl_stg1_done_reg_0),
        .I3(stg1_wr_done),
        .I4(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA200000008)) 
    \stg1_wr_rd_cnt[7]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I1(\stg1_wr_rd_cnt[7]_i_2_n_0 ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\stg1_wr_rd_cnt[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \stg1_wr_rd_cnt[7]_i_2 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\stg1_wr_rd_cnt[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \stg1_wr_rd_cnt[8]_i_1 
       (.I0(rdlvl_stg1_done_reg_0),
        .I1(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\stg1_wr_rd_cnt[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT5 #(
    .INIT(32'hA8AA0200)) 
    \stg1_wr_rd_cnt[8]_i_2 
       (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt[8]_i_6_n_0 ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .O(\stg1_wr_rd_cnt[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF7FFFFFFFFF)) 
    \stg1_wr_rd_cnt[8]_i_3 
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\stg1_wr_rd_cnt[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000040000000000)) 
    \stg1_wr_rd_cnt[8]_i_4 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(detect_pi_found_dqs_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\stg1_wr_rd_cnt[8]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT4 #(
    .INIT(16'h00A2)) 
    \stg1_wr_rd_cnt[8]_i_5 
       (.I0(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .I1(stg1_wr_done),
        .I2(rdlvl_stg1_done_reg_0),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .O(\stg1_wr_rd_cnt[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \stg1_wr_rd_cnt[8]_i_6 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\stg1_wr_rd_cnt[8]_i_6_n_0 ));
  FDRE \stg1_wr_rd_cnt_reg[0] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[0]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[1] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[1]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[2] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[2]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[3] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[3]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[4] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[4]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[5] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[5]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[6] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[6]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[7] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[7]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[8] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[8]_i_2_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .R(1'b0));
  FDRE wl_sm_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_dqs_asrt_r1),
        .Q(wl_sm_start),
        .R(rstdiv0_sync_r1_reg_rep__4));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT4 #(
    .INIT(16'h00AE)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_1 
       (.I0(complex_row0_wr_done),
        .I1(prbs_last_byte_done_r),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(complex_row0_wr_done0),
        .O(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEEFEEEEEEEEE)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_2 
       (.I0(complex_row0_rd_done1),
        .I1(complex_byte_rd_done),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0 ),
        .I3(rdlvl_stg1_done_reg_0),
        .I4(\complex_row_cnt_ocal[7]_i_6_n_0 ),
        .I5(wr_victim_inc),
        .O(complex_row0_wr_done0));
  FDRE \wr_done_victim_rotate.complex_row0_wr_done_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ),
        .Q(complex_row0_wr_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT4 #(
    .INIT(16'h00AE)) 
    \wr_done_victim_rotate.complex_row1_wr_done_i_1 
       (.I0(complex_row1_wr_done),
        .I1(complex_row0_wr_done),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(complex_row0_wr_done0),
        .O(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ));
  FDRE \wr_done_victim_rotate.complex_row1_wr_done_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ),
        .Q(complex_row1_wr_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    wr_en_inferred__0_i_1
       (.I0(\wr_ptr_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(\my_empty_reg[3] ),
        .O(wr_en));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    wr_en_inferred__0_i_1__0
       (.I0(\wr_ptr_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(\my_empty_reg[3]_0 ),
        .O(wr_en_0));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    wr_en_inferred__0_i_1__1
       (.I0(\wr_ptr_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(\my_empty_reg[3]_1 ),
        .O(wr_en_1));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT4 #(
    .INIT(16'h00E0)) 
    wr_level_dqs_asrt_i_1
       (.I0(wr_level_dqs_asrt),
        .I1(wrlvl_active_r1),
        .I2(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .O(wr_level_dqs_asrt_i_1_n_0));
  FDRE wr_level_dqs_asrt_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_dqs_asrt),
        .Q(wr_level_dqs_asrt_r1),
        .R(1'b0));
  FDRE wr_level_dqs_asrt_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_dqs_asrt_i_1_n_0),
        .Q(wr_level_dqs_asrt),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000EA00)) 
    wr_lvl_start_i_1
       (.I0(wr_level_start_r_reg),
        .I1(dqs_asrt_cnt[1]),
        .I2(dqs_asrt_cnt[0]),
        .I3(wrlvl_active),
        .I4(rstdiv0_sync_r1_reg_rep__22),
        .O(wr_lvl_start_i_1_n_0));
  FDRE wr_lvl_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_lvl_start_i_1_n_0),
        .Q(wr_level_start_r_reg),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \wr_ptr[2]_i_1__10 
       (.I0(\wr_ptr_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(\my_empty_reg[5] ),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \wr_ptr[2]_i_1__11 
       (.I0(\wr_ptr_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(\my_empty_reg[5]_0 ),
        .O(\wr_ptr_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \wr_ptr[2]_i_1__12 
       (.I0(\wr_ptr_reg[2] ),
        .I1(init_calib_complete_reg_rep__14),
        .I2(\my_empty_reg[5]_1 ),
        .O(\wr_ptr_reg[2]_1 ));
  LUT3 #(
    .INIT(8'h10)) 
    wr_victim_inc_i_1
       (.I0(wr_victim_inc_i_2_n_0),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(complex_row0_wr_done),
        .O(wr_victim_inc_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    wr_victim_inc_i_2
       (.I0(wr_victim_inc_i_3_n_0),
        .I1(complex_sample_cnt_inc_i_3_n_0),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(wr_victim_inc_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    wr_victim_inc_i_3
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(wr_victim_inc_i_3_n_0));
  FDRE wr_victim_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_victim_inc_i_1_n_0),
        .Q(wr_victim_inc),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT2 #(
    .INIT(4'h2)) 
    \wrcal_dqs_cnt_r[3]_i_4 
       (.I0(wrcal_sanity_chk),
        .I1(wrcal_sanity_chk_r),
        .O(cal2_done_r_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFF40000000)) 
    wrcal_final_chk_i_1
       (.I0(\init_state_r[5]_i_1_n_0 ),
        .I1(\init_state_r[2]_i_1_n_0 ),
        .I2(wrcal_final_chk_i_2_n_0),
        .I3(\init_state_r[0]_i_1_n_0 ),
        .I4(\init_state_r[1]_i_1_n_0 ),
        .I5(wrcal_final_chk),
        .O(wrcal_final_chk_i_1_n_0));
  LUT6 #(
    .INIT(64'hFF8A000000000000)) 
    wrcal_final_chk_i_2
       (.I0(\init_state_r[4]_i_5_n_0 ),
        .I1(\init_state_r[4]_i_4_n_0 ),
        .I2(\init_state_r[4]_i_3_n_0 ),
        .I3(wrcal_final_chk_i_3_n_0),
        .I4(wrcal_final_chk_i_4_n_0),
        .I5(\init_state_r[3]_i_1_n_0 ),
        .O(wrcal_final_chk_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT5 #(
    .INIT(32'h40404000)) 
    wrcal_final_chk_i_3
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(prech_pending_r_reg_0),
        .O(wrcal_final_chk_i_3_n_0));
  LUT6 #(
    .INIT(64'h20202022AAAAAAAA)) 
    wrcal_final_chk_i_4
       (.I0(wrcal_done_reg),
        .I1(init_state_r),
        .I2(wrcal_final_chk_i_5_n_0),
        .I3(\init_state_r[6]_i_4_n_0 ),
        .I4(\init_state_r[6]_i_3_n_0 ),
        .I5(\init_state_r[6]_i_2_n_0 ),
        .O(wrcal_final_chk_i_4_n_0));
  LUT6 #(
    .INIT(64'h00FE00CEFFFFFFFF)) 
    wrcal_final_chk_i_5
       (.I0(wrcal_final_chk_i_6_n_0),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[6]_i_15_n_0 ),
        .I4(wrcal_final_chk_i_7_n_0),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(wrcal_final_chk_i_5_n_0));
  LUT6 #(
    .INIT(64'hFF000D0DFFFFFFFF)) 
    wrcal_final_chk_i_6
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r[6]_i_29_n_0 ),
        .I2(\init_state_r[6]_i_28_n_0 ),
        .I3(\init_state_r[5]_i_30_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(init_state_r),
        .O(wrcal_final_chk_i_6_n_0));
  LUT6 #(
    .INIT(64'h00000000EEEEEEEF)) 
    wrcal_final_chk_i_7
       (.I0(\init_state_r[2]_i_4_n_0 ),
        .I1(\init_state_r[2]_i_29_n_0 ),
        .I2(wrcal_final_chk_i_8_n_0),
        .I3(\init_state_r[6]_i_23_n_0 ),
        .I4(\init_state_r[6]_i_24_n_0 ),
        .I5(\init_state_r[6]_i_14_n_0 ),
        .O(wrcal_final_chk_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    wrcal_final_chk_i_8
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(wrcal_final_chk_i_8_n_0));
  FDRE wrcal_final_chk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_final_chk_i_1_n_0),
        .Q(wrcal_final_chk),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT6 #(
    .INIT(64'h0002000000000000)) 
    wrcal_rd_wait_i_1
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(wrcal_rd_wait_i_1_n_0));
  FDRE wrcal_rd_wait_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_rd_wait_i_1_n_0),
        .Q(wrcal_rd_wait),
        .R(rstdiv0_sync_r1_reg_rep__18));
  LUT2 #(
    .INIT(4'hB)) 
    \wrcal_reads[0]_i_1 
       (.I0(\wrcal_reads[7]_i_7_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .O(\wrcal_reads[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT3 #(
    .INIT(8'hF9)) 
    \wrcal_reads[1]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[1] ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .I2(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT4 #(
    .INIT(16'hFFE1)) 
    \wrcal_reads[2]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\wrcal_reads_reg_n_0_[2] ),
        .I3(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT5 #(
    .INIT(32'hFFFFFE01)) 
    \wrcal_reads[3]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[1] ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .I2(\wrcal_reads_reg_n_0_[2] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .I4(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFE0001)) 
    \wrcal_reads[4]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[3] ),
        .I1(\wrcal_reads_reg_n_0_[2] ),
        .I2(\wrcal_reads_reg_n_0_[0] ),
        .I3(\wrcal_reads_reg_n_0_[1] ),
        .I4(\wrcal_reads_reg_n_0_[4] ),
        .I5(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT4 #(
    .INIT(16'hFFE1)) 
    \wrcal_reads[5]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[4] ),
        .I1(\wrcal_reads[7]_i_6_n_0 ),
        .I2(\wrcal_reads_reg_n_0_[5] ),
        .I3(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT5 #(
    .INIT(32'hFFFFFE01)) 
    \wrcal_reads[6]_i_1 
       (.I0(\wrcal_reads[7]_i_6_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[4] ),
        .I2(\wrcal_reads_reg_n_0_[5] ),
        .I3(\wrcal_reads_reg_n_0_[6] ),
        .I4(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAEAAAAAAAAAAAAA)) 
    \wrcal_reads[7]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__22),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(init_state_r),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(wrcal_reads05_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wrcal_reads[7]_i_2 
       (.I0(\wrcal_reads[7]_i_6_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .I2(\wrcal_reads_reg_n_0_[4] ),
        .I3(\wrcal_reads_reg_n_0_[6] ),
        .I4(\wrcal_reads_reg_n_0_[7] ),
        .I5(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFE0001)) 
    \wrcal_reads[7]_i_3 
       (.I0(\wrcal_reads_reg_n_0_[5] ),
        .I1(\wrcal_reads_reg_n_0_[4] ),
        .I2(\wrcal_reads[7]_i_6_n_0 ),
        .I3(\wrcal_reads_reg_n_0_[6] ),
        .I4(\wrcal_reads_reg_n_0_[7] ),
        .I5(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wrcal_reads[7]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .O(\wrcal_reads[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wrcal_reads[7]_i_5 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(\wrcal_reads[7]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \wrcal_reads[7]_i_6 
       (.I0(\wrcal_reads_reg_n_0_[3] ),
        .I1(\wrcal_reads_reg_n_0_[2] ),
        .I2(\wrcal_reads_reg_n_0_[0] ),
        .I3(\wrcal_reads_reg_n_0_[1] ),
        .O(\wrcal_reads[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \wrcal_reads[7]_i_7 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_3_n_0 ),
        .I1(\wrcal_reads[7]_i_6_n_0 ),
        .I2(\wrcal_reads_reg_n_0_[5] ),
        .I3(\wrcal_reads_reg_n_0_[4] ),
        .I4(\wrcal_reads_reg_n_0_[6] ),
        .I5(\wrcal_reads_reg_n_0_[7] ),
        .O(\wrcal_reads[7]_i_7_n_0 ));
  FDRE \wrcal_reads_reg[0] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[0]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[0] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[1] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[1]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[1] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[2] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[2]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[2] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[3] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[3]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[3] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[4] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[4]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[4] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[5] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[5]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[5] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[6] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[6]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[6] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[7] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[7]_i_3_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[7] ),
        .R(wrcal_reads05_out));
  FDRE wrcal_resume_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_resume_w),
        .Q(wrcal_resume_r),
        .R(1'b0));
  FDRE wrcal_sanity_chk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_final_chk),
        .Q(wrcal_sanity_chk),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 " *) 
  SRL16E \wrcal_start_dly_r_reg[4]_srl5 
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(\wrcal_start_dly_r_reg[4]_srl5_i_1_n_0 ),
        .Q(\wrcal_start_dly_r_reg[4]_srl5_n_0 ));
  LUT6 #(
    .INIT(64'hF022000000000000)) 
    \wrcal_start_dly_r_reg[4]_srl5_i_1 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\wrcal_start_dly_r_reg[4]_srl5_i_2_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\wrcal_start_dly_r_reg[4]_srl5_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrcal_start_dly_r_reg[4]_srl5_i_2 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\wrcal_start_dly_r_reg[4]_srl5_i_2_n_0 ));
  FDRE \wrcal_start_dly_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrcal_start_dly_r_reg[4]_srl5_n_0 ),
        .Q(\wrcal_start_dly_r_reg_n_0_[5] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h000E)) 
    wrcal_start_i_1
       (.I0(wrcal_start_reg_0),
        .I1(\wrcal_start_dly_r_reg_n_0_[5] ),
        .I2(rstdiv0_sync_r1_reg_rep__22),
        .I3(wrlvl_byte_redo),
        .O(wrcal_start_i_1_n_0));
  FDRE wrcal_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_start_i_1_n_0),
        .Q(wrcal_start_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wrcal_wr_cnt[0]_i_1 
       (.I0(wrcal_wr_cnt_reg__0[0]),
        .O(\wrcal_wr_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrcal_wr_cnt[1]_i_1 
       (.I0(wrcal_wr_cnt_reg__0[1]),
        .I1(wrcal_wr_cnt_reg__0[0]),
        .O(\wrcal_wr_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wrcal_wr_cnt[2]_i_1 
       (.I0(wrcal_wr_cnt_reg__0[2]),
        .I1(wrcal_wr_cnt_reg__0[0]),
        .I2(wrcal_wr_cnt_reg__0[1]),
        .O(wrcal_wr_cnt0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAAB)) 
    \wrcal_wr_cnt[3]_i_1 
       (.I0(\wrcal_wr_cnt[3]_i_4_n_0 ),
        .I1(wrcal_wr_cnt_reg__0[0]),
        .I2(wrcal_wr_cnt_reg__0[1]),
        .I3(wrcal_wr_cnt_reg__0[3]),
        .I4(wrcal_wr_cnt_reg__0[2]),
        .I5(rstdiv0_sync_r1_reg_rep__22),
        .O(\wrcal_wr_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    \wrcal_wr_cnt[3]_i_2 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(p_0_in10_in));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wrcal_wr_cnt[3]_i_3 
       (.I0(wrcal_wr_cnt_reg__0[3]),
        .I1(wrcal_wr_cnt_reg__0[2]),
        .I2(wrcal_wr_cnt_reg__0[1]),
        .I3(wrcal_wr_cnt_reg__0[0]),
        .O(wrcal_wr_cnt0[3]));
  LUT6 #(
    .INIT(64'h0000000001000000)) 
    \wrcal_wr_cnt[3]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\wrcal_wr_cnt[3]_i_4_n_0 ));
  FDRE \wrcal_wr_cnt_reg[0] 
       (.C(CLK),
        .CE(p_0_in10_in),
        .D(\wrcal_wr_cnt[0]_i_1_n_0 ),
        .Q(wrcal_wr_cnt_reg__0[0]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDRE \wrcal_wr_cnt_reg[1] 
       (.C(CLK),
        .CE(p_0_in10_in),
        .D(\wrcal_wr_cnt[1]_i_1_n_0 ),
        .Q(wrcal_wr_cnt_reg__0[1]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDSE \wrcal_wr_cnt_reg[2] 
       (.C(CLK),
        .CE(p_0_in10_in),
        .D(wrcal_wr_cnt0[2]),
        .Q(wrcal_wr_cnt_reg__0[2]),
        .S(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDRE \wrcal_wr_cnt_reg[3] 
       (.C(CLK),
        .CE(p_0_in10_in),
        .D(wrcal_wr_cnt0[3]),
        .Q(wrcal_wr_cnt_reg__0[3]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1 
       (.I0(first_rdlvl_pat_r),
        .I1(rdlvl_stg1_done_reg_0),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1 
       (.I0(first_wrcal_pat_r),
        .I1(rdlvl_stg1_done_reg_0),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1 
       (.I0(first_wrcal_pat_r),
        .I1(rdlvl_stg1_done_reg_0),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1_n_0 ));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[125] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1_n_0 ),
        .Q(phy_wrdata[125]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[190] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1_n_0 ),
        .Q(phy_wrdata[190]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]" *) 
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(D[1]),
        .Q(phy_wrdata[441]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]" *) 
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(rdlvl_stg1_done_reg_7),
        .Q(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep_n_0 ),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(rdlvl_stg1_done_reg_0),
        .Q(phy_wrdata[447]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[505] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(D[2]),
        .Q(phy_wrdata[505]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[510] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1_n_0 ),
        .Q(phy_wrdata[510]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(D[3]),
        .Q(phy_wrdata[511]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[61] 
       (.C(CLK),
        .CE(rdlvl_stg1_done_reg_6),
        .D(D[0]),
        .Q(phy_wrdata[61]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000EE0E)) 
    write_calib_i_1
       (.I0(write_calib),
        .I1(wrlvl_active_r1),
        .I2(done_dqs_tap_inc),
        .I3(wrlvl_final_if_rst_i_2_n_0),
        .I4(rstdiv0_sync_r1_reg_rep__22),
        .O(write_calib_i_1_n_0));
  FDRE write_calib_reg
       (.C(CLK),
        .CE(1'b1),
        .D(write_calib_i_1_n_0),
        .Q(write_calib),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000000000EA)) 
    wrlvl_active_i_1
       (.I0(wrlvl_active),
        .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I2(wrlvl_odt),
        .I3(rstdiv0_sync_r1_reg_rep__22),
        .I4(done_dqs_tap_inc),
        .I5(wrlvl_rank_done),
        .O(wrlvl_active_i_1_n_0));
  FDRE wrlvl_active_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_active),
        .Q(wrlvl_active_r1),
        .R(1'b0));
  FDRE wrlvl_active_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_active_i_1_n_0),
        .Q(wrlvl_active),
        .R(1'b0));
  FDRE wrlvl_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_done_r),
        .Q(wrlvl_done_r1),
        .R(1'b0));
  FDRE wrlvl_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_reg),
        .Q(wrlvl_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000000000AE)) 
    wrlvl_final_if_rst_i_1
       (.I0(wrlvl_final_if_rst),
        .I1(wrlvl_done_r),
        .I2(wrlvl_final_if_rst_i_2_n_0),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .I4(\cnt_init_mr_r[1]_i_3_n_0 ),
        .I5(p_0_in10_in),
        .O(wrlvl_final_if_rst_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    wrlvl_final_if_rst_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\reg_ctrl_cnt_r[3]_i_4_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(wrlvl_final_if_rst_i_2_n_0));
  FDRE wrlvl_final_if_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_final_if_rst_i_1_n_0),
        .Q(wrlvl_final_if_rst),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000AE)) 
    wrlvl_odt_ctl_i_1
       (.I0(wrlvl_odt_ctl),
        .I1(wrlvl_rank_done),
        .I2(wrlvl_rank_done_r1),
        .I3(wrlvl_odt_ctl_i_2_n_0),
        .I4(rstdiv0_sync_r1_reg_rep__21),
        .O(wrlvl_odt_ctl_i_1_n_0));
  LUT6 #(
    .INIT(64'h0008000800080000)) 
    wrlvl_odt_ctl_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(wrlvl_odt_ctl_i_3_n_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(wrlvl_odt_ctl_i_4_n_0),
        .I5(init_state_r1[3]),
        .O(wrlvl_odt_ctl_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    wrlvl_odt_ctl_i_3
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .O(wrlvl_odt_ctl_i_3_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFDF)) 
    wrlvl_odt_ctl_i_4
       (.I0(init_state_r1[2]),
        .I1(init_state_r1[6]),
        .I2(init_state_r1[1]),
        .I3(init_state_r1[0]),
        .I4(init_state_r1[5]),
        .I5(init_state_r1[4]),
        .O(wrlvl_odt_ctl_i_4_n_0));
  FDRE wrlvl_odt_ctl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_odt_ctl_i_1_n_0),
        .Q(wrlvl_odt_ctl),
        .R(1'b0));
  FDRE wrlvl_rank_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_rank_done),
        .Q(wrlvl_rank_done_r1),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 " *) 
  SRL16E wrlvl_rank_done_r6_reg_srl5
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(wrlvl_rank_done_r1),
        .Q(wrlvl_rank_done_r6_reg_srl5_n_0));
  FDRE wrlvl_rank_done_r7_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_rank_done_r6_reg_srl5_n_0),
        .Q(wrlvl_rank_done_r7),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_rdlvl" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_rdlvl
   (idelay_tap_limit_r_reg_0,
    samp_edge_cnt0_en_r,
    idelay_ce_int,
    idelay_inc_int,
    rdlvl_prech_req,
    pi_fine_dly_dec_done,
    fine_dly_dec_done_r1_reg_0,
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ,
    rdlvl_stg1_rank_done,
    rdlvl_last_byte_done,
    COUNTERLOADVAL,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \stg1_wr_rd_cnt_reg[3] ,
    \FSM_onehot_cal1_state_r_reg[0]_0 ,
    \idelay_tap_cnt_r_reg[0][7][3]_0 ,
    \idelay_tap_cnt_r_reg[0][7][4]_0 ,
    prbs_rdlvl_done_pulse_reg,
    \rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 ,
    \init_state_r_reg[0] ,
    \init_state_r_reg[0]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,
    \init_state_r_reg[4] ,
    \init_state_r_reg[3] ,
    \init_state_r_reg[2] ,
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511] ,
    D,
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep ,
    A_pi_fine_enable157_out,
    A_pi_fine_inc159_out,
    A_pi_counter_load_en161_out,
    D_pi_fine_inc88_out,
    D_pi_fine_enable86_out,
    D_pi_counter_load_en90_out,
    A_pi_fine_enable112_out,
    A_pi_fine_inc114_out,
    A_pi_counter_load_en116_out,
    B_pi_fine_enable34_out,
    B_pi_fine_inc36_out,
    B_pi_counter_load_en38_out,
    C_pi_fine_enable60_out,
    C_pi_fine_inc62_out,
    C_pi_counter_load_en64_out,
    A_pi_fine_enable83_out,
    A_pi_fine_inc85_out,
    A_pi_counter_load_en87_out,
    B_pi_fine_enable31_out,
    B_pi_fine_inc33_out,
    B_pi_counter_load_en35_out,
    C_pi_fine_enable57_out,
    C_pi_fine_inc59_out,
    C_pi_counter_load_en61_out,
    reset_if_reg,
    \gen_byte_sel_div2.byte_sel_cnt_reg[3] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[2] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    \ctl_lane_cnt_reg[1] ,
    \pi_dqs_found_lanes_r1_reg[4] ,
    \pi_dqs_found_lanes_r1_reg[1] ,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[10] ,
    CLK,
    rstdiv0_sync_r1_reg_rep__2,
    \rd_mux_sel_r_reg[0]_0 ,
    \rd_mux_sel_r_reg[0]_1 ,
    \rd_mux_sel_r_reg[0]_2 ,
    \rd_mux_sel_r_reg[0]_3 ,
    \rd_mux_sel_r_reg[0]_4 ,
    \rd_mux_sel_r_reg[0]_5 ,
    \rd_mux_sel_r_reg[0]_6 ,
    \rd_mux_sel_r_reg[0]_7 ,
    \rd_mux_sel_r_reg[0]_8 ,
    \rd_mux_sel_r_reg[0]_9 ,
    \rd_mux_sel_r_reg[0]_10 ,
    \rd_mux_sel_r_reg[0]_11 ,
    \rd_mux_sel_r_reg[0]_12 ,
    \rd_mux_sel_r_reg[0]_13 ,
    \rd_mux_sel_r_reg[0]_14 ,
    \rd_mux_sel_r_reg[0]_15 ,
    \rd_mux_sel_r_reg[0]_16 ,
    \rd_mux_sel_r_reg[0]_17 ,
    \rd_mux_sel_r_reg[0]_18 ,
    \rd_mux_sel_r_reg[0]_19 ,
    \rd_mux_sel_r_reg[0]_20 ,
    \rd_mux_sel_r_reg[0]_21 ,
    \rd_mux_sel_r_reg[0]_22 ,
    \rd_mux_sel_r_reg[0]_23 ,
    \rd_mux_sel_r_reg[0]_24 ,
    \rd_mux_sel_r_reg[0]_25 ,
    \rd_mux_sel_r_reg[0]_26 ,
    \rd_mux_sel_r_reg[0]_27 ,
    \rd_mux_sel_r_reg[0]_28 ,
    \rd_mux_sel_r_reg[0]_29 ,
    \rd_mux_sel_r_reg[0]_30 ,
    \rd_mux_sel_r_reg[0]_31 ,
    \rd_mux_sel_r_reg[0]_32 ,
    \rd_mux_sel_r_reg[0]_33 ,
    \rd_mux_sel_r_reg[0]_34 ,
    \rd_mux_sel_r_reg[0]_35 ,
    \rd_mux_sel_r_reg[0]_36 ,
    \rd_mux_sel_r_reg[0]_37 ,
    \rd_mux_sel_r_reg[0]_38 ,
    \rd_mux_sel_r_reg[0]_39 ,
    \rd_mux_sel_r_reg[0]_40 ,
    \rd_mux_sel_r_reg[0]_41 ,
    \rd_mux_sel_r_reg[0]_42 ,
    \rd_mux_sel_r_reg[0]_43 ,
    \rd_mux_sel_r_reg[0]_44 ,
    \rd_mux_sel_r_reg[0]_45 ,
    \rd_mux_sel_r_reg[0]_46 ,
    \rd_mux_sel_r_reg[0]_47 ,
    \rd_mux_sel_r_reg[0]_48 ,
    \rd_mux_sel_r_reg[0]_49 ,
    \rd_mux_sel_r_reg[0]_50 ,
    \rd_mux_sel_r_reg[0]_51 ,
    \rd_mux_sel_r_reg[0]_52 ,
    \rd_mux_sel_r_reg[0]_53 ,
    \rd_mux_sel_r_reg[0]_54 ,
    \rd_mux_sel_r_reg[0]_55 ,
    \rd_mux_sel_r_reg[0]_56 ,
    \rd_mux_sel_r_reg[0]_57 ,
    \rd_mux_sel_r_reg[0]_58 ,
    \rd_mux_sel_r_reg[0]_59 ,
    \rd_mux_sel_r_reg[0]_60 ,
    \rd_mux_sel_r_reg[0]_61 ,
    \rd_mux_sel_r_reg[0]_62 ,
    \rd_mux_sel_r_reg[0]_63 ,
    rstdiv0_sync_r1_reg_rep__1,
    mpr_rdlvl_start_reg,
    rdlvl_stg1_start_reg,
    rd_active_r,
    dqs_po_dec_done,
    rstdiv0_sync_r1_reg_rep__24,
    rstdiv0_sync_r1_reg_rep__18,
    \pi_counter_read_val_reg[0] ,
    \pi_counter_read_val_reg[1] ,
    \pi_counter_read_val_reg[0]_0 ,
    \pi_counter_read_val_reg[2] ,
    \pi_counter_read_val_reg[1]_0 ,
    \pi_counter_read_val_reg[2]_0 ,
    \pi_counter_read_val_reg[3] ,
    \pi_counter_read_val_reg[4] ,
    Q,
    \gen_byte_sel_div2.calib_in_common_reg ,
    \calib_sel_reg[1] ,
    rstdiv0_sync_r1_reg_rep__22,
    stg1_wr_done,
    prech_done,
    rstdiv0_sync_r1_reg_rep__24_0,
    prbs_last_byte_done_r,
    wrlvl_done_r1,
    dqs_found_done_r_reg,
    complex_row0_rd_done,
    \one_rank.stg1_wr_done_reg ,
    wrcal_done_reg,
    first_rdlvl_pat_r,
    first_wrcal_pat_r,
    \pi_counter_read_val_reg[5] ,
    \po_stg2_wrcal_cnt_reg[0] ,
    \po_stg2_wrcal_cnt_reg[2] ,
    rstdiv0_sync_r1_reg_rep__23,
    \po_stg2_wrcal_cnt_reg[3] ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[0]_0 ,
    \po_stg2_wrcal_cnt_reg[0]_1 ,
    tempmon_pi_f_en_r,
    tempmon_pi_f_inc_r,
    reset_if,
    reset_if_r9,
    wr_level_done_reg,
    \dqs_count_r_reg[3] ,
    \dqs_count_r_reg[2]_rep__0 ,
    \dqs_count_r_reg[1]_rep ,
    \dqs_count_r_reg[0]_rep ,
    rstdiv0_sync_r1_reg_rep__3,
    rstdiv0_sync_r1_reg_rep__24_1,
    E,
    rstdiv0_sync_r1_reg_rep__24_2,
    rstdiv0_sync_r1_reg_rep__24_3,
    rdlvl_stg1_start_reg_0,
    rstdiv0_sync_r1_reg_rep__24_4,
    rstdiv0_sync_r1,
    \pi_counter_read_val_reg[4]_0 );
  output idelay_tap_limit_r_reg_0;
  output samp_edge_cnt0_en_r;
  output idelay_ce_int;
  output idelay_inc_int;
  output rdlvl_prech_req;
  output pi_fine_dly_dec_done;
  output fine_dly_dec_done_r1_reg_0;
  output \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ;
  output rdlvl_stg1_rank_done;
  output rdlvl_last_byte_done;
  output [5:0]COUNTERLOADVAL;
  output [5:0]\pi_dqs_found_lanes_r1_reg[8] ;
  output \stg1_wr_rd_cnt_reg[3] ;
  output \FSM_onehot_cal1_state_r_reg[0]_0 ;
  output \idelay_tap_cnt_r_reg[0][7][3]_0 ;
  output \idelay_tap_cnt_r_reg[0][7][4]_0 ;
  output prbs_rdlvl_done_pulse_reg;
  output [2:0]\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 ;
  output \init_state_r_reg[0] ;
  output \init_state_r_reg[0]_0 ;
  output \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;
  output \init_state_r_reg[4] ;
  output \init_state_r_reg[3] ;
  output \init_state_r_reg[2] ;
  output [0:0]\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511] ;
  output [3:0]D;
  output \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep ;
  output A_pi_fine_enable157_out;
  output A_pi_fine_inc159_out;
  output A_pi_counter_load_en161_out;
  output D_pi_fine_inc88_out;
  output D_pi_fine_enable86_out;
  output D_pi_counter_load_en90_out;
  output A_pi_fine_enable112_out;
  output A_pi_fine_inc114_out;
  output A_pi_counter_load_en116_out;
  output B_pi_fine_enable34_out;
  output B_pi_fine_inc36_out;
  output B_pi_counter_load_en38_out;
  output C_pi_fine_enable60_out;
  output C_pi_fine_inc62_out;
  output C_pi_counter_load_en64_out;
  output A_pi_fine_enable83_out;
  output A_pi_fine_inc85_out;
  output A_pi_counter_load_en87_out;
  output B_pi_fine_enable31_out;
  output B_pi_fine_inc33_out;
  output B_pi_counter_load_en35_out;
  output C_pi_fine_enable57_out;
  output C_pi_fine_inc59_out;
  output C_pi_counter_load_en61_out;
  output reset_if_reg;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[2] ;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  output \ctl_lane_cnt_reg[1] ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[4] ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[1] ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[2] ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[3] ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[9] ;
  output [5:0]\pi_dqs_found_lanes_r1_reg[10] ;
  input CLK;
  input [0:0]rstdiv0_sync_r1_reg_rep__2;
  input \rd_mux_sel_r_reg[0]_0 ;
  input \rd_mux_sel_r_reg[0]_1 ;
  input \rd_mux_sel_r_reg[0]_2 ;
  input \rd_mux_sel_r_reg[0]_3 ;
  input \rd_mux_sel_r_reg[0]_4 ;
  input \rd_mux_sel_r_reg[0]_5 ;
  input \rd_mux_sel_r_reg[0]_6 ;
  input \rd_mux_sel_r_reg[0]_7 ;
  input \rd_mux_sel_r_reg[0]_8 ;
  input \rd_mux_sel_r_reg[0]_9 ;
  input \rd_mux_sel_r_reg[0]_10 ;
  input \rd_mux_sel_r_reg[0]_11 ;
  input \rd_mux_sel_r_reg[0]_12 ;
  input \rd_mux_sel_r_reg[0]_13 ;
  input \rd_mux_sel_r_reg[0]_14 ;
  input \rd_mux_sel_r_reg[0]_15 ;
  input \rd_mux_sel_r_reg[0]_16 ;
  input \rd_mux_sel_r_reg[0]_17 ;
  input \rd_mux_sel_r_reg[0]_18 ;
  input \rd_mux_sel_r_reg[0]_19 ;
  input \rd_mux_sel_r_reg[0]_20 ;
  input \rd_mux_sel_r_reg[0]_21 ;
  input \rd_mux_sel_r_reg[0]_22 ;
  input \rd_mux_sel_r_reg[0]_23 ;
  input \rd_mux_sel_r_reg[0]_24 ;
  input \rd_mux_sel_r_reg[0]_25 ;
  input \rd_mux_sel_r_reg[0]_26 ;
  input \rd_mux_sel_r_reg[0]_27 ;
  input \rd_mux_sel_r_reg[0]_28 ;
  input \rd_mux_sel_r_reg[0]_29 ;
  input \rd_mux_sel_r_reg[0]_30 ;
  input \rd_mux_sel_r_reg[0]_31 ;
  input \rd_mux_sel_r_reg[0]_32 ;
  input \rd_mux_sel_r_reg[0]_33 ;
  input \rd_mux_sel_r_reg[0]_34 ;
  input \rd_mux_sel_r_reg[0]_35 ;
  input \rd_mux_sel_r_reg[0]_36 ;
  input \rd_mux_sel_r_reg[0]_37 ;
  input \rd_mux_sel_r_reg[0]_38 ;
  input \rd_mux_sel_r_reg[0]_39 ;
  input \rd_mux_sel_r_reg[0]_40 ;
  input \rd_mux_sel_r_reg[0]_41 ;
  input \rd_mux_sel_r_reg[0]_42 ;
  input \rd_mux_sel_r_reg[0]_43 ;
  input \rd_mux_sel_r_reg[0]_44 ;
  input \rd_mux_sel_r_reg[0]_45 ;
  input \rd_mux_sel_r_reg[0]_46 ;
  input \rd_mux_sel_r_reg[0]_47 ;
  input \rd_mux_sel_r_reg[0]_48 ;
  input \rd_mux_sel_r_reg[0]_49 ;
  input \rd_mux_sel_r_reg[0]_50 ;
  input \rd_mux_sel_r_reg[0]_51 ;
  input \rd_mux_sel_r_reg[0]_52 ;
  input \rd_mux_sel_r_reg[0]_53 ;
  input \rd_mux_sel_r_reg[0]_54 ;
  input \rd_mux_sel_r_reg[0]_55 ;
  input \rd_mux_sel_r_reg[0]_56 ;
  input \rd_mux_sel_r_reg[0]_57 ;
  input \rd_mux_sel_r_reg[0]_58 ;
  input \rd_mux_sel_r_reg[0]_59 ;
  input \rd_mux_sel_r_reg[0]_60 ;
  input \rd_mux_sel_r_reg[0]_61 ;
  input \rd_mux_sel_r_reg[0]_62 ;
  input \rd_mux_sel_r_reg[0]_63 ;
  input rstdiv0_sync_r1_reg_rep__1;
  input mpr_rdlvl_start_reg;
  input rdlvl_stg1_start_reg;
  input rd_active_r;
  input dqs_po_dec_done;
  input rstdiv0_sync_r1_reg_rep__24;
  input rstdiv0_sync_r1_reg_rep__18;
  input \pi_counter_read_val_reg[0] ;
  input \pi_counter_read_val_reg[1] ;
  input \pi_counter_read_val_reg[0]_0 ;
  input \pi_counter_read_val_reg[2] ;
  input \pi_counter_read_val_reg[1]_0 ;
  input \pi_counter_read_val_reg[2]_0 ;
  input \pi_counter_read_val_reg[3] ;
  input \pi_counter_read_val_reg[4] ;
  input [2:0]Q;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input [1:0]\calib_sel_reg[1] ;
  input rstdiv0_sync_r1_reg_rep__22;
  input stg1_wr_done;
  input prech_done;
  input rstdiv0_sync_r1_reg_rep__24_0;
  input prbs_last_byte_done_r;
  input wrlvl_done_r1;
  input dqs_found_done_r_reg;
  input complex_row0_rd_done;
  input \one_rank.stg1_wr_done_reg ;
  input wrcal_done_reg;
  input first_rdlvl_pat_r;
  input first_wrcal_pat_r;
  input \pi_counter_read_val_reg[5] ;
  input \po_stg2_wrcal_cnt_reg[0] ;
  input \po_stg2_wrcal_cnt_reg[2] ;
  input rstdiv0_sync_r1_reg_rep__23;
  input \po_stg2_wrcal_cnt_reg[3] ;
  input \po_stg2_wrcal_cnt_reg[1] ;
  input \po_stg2_wrcal_cnt_reg[0]_0 ;
  input \po_stg2_wrcal_cnt_reg[0]_1 ;
  input tempmon_pi_f_en_r;
  input tempmon_pi_f_inc_r;
  input reset_if;
  input reset_if_r9;
  input wr_level_done_reg;
  input [0:0]\dqs_count_r_reg[3] ;
  input \dqs_count_r_reg[2]_rep__0 ;
  input \dqs_count_r_reg[1]_rep ;
  input \dqs_count_r_reg[0]_rep ;
  input rstdiv0_sync_r1_reg_rep__3;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  input [0:0]E;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  input [0:0]rdlvl_stg1_start_reg_0;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  input rstdiv0_sync_r1;
  input \pi_counter_read_val_reg[4]_0 ;

  wire A_pi_counter_load_en116_out;
  wire A_pi_counter_load_en161_out;
  wire A_pi_counter_load_en87_out;
  wire A_pi_fine_enable112_out;
  wire A_pi_fine_enable157_out;
  wire A_pi_fine_enable83_out;
  wire A_pi_fine_inc114_out;
  wire A_pi_fine_inc159_out;
  wire A_pi_fine_inc85_out;
  wire B_pi_counter_load_en35_out;
  wire B_pi_counter_load_en38_out;
  wire B_pi_fine_enable31_out;
  wire B_pi_fine_enable34_out;
  wire B_pi_fine_inc33_out;
  wire B_pi_fine_inc36_out;
  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire C_pi_counter_load_en61_out;
  wire C_pi_counter_load_en64_out;
  wire C_pi_fine_enable57_out;
  wire C_pi_fine_enable60_out;
  wire C_pi_fine_inc59_out;
  wire C_pi_fine_inc62_out;
  wire [3:0]D;
  wire D_pi_counter_load_en90_out;
  wire D_pi_fine_enable86_out;
  wire D_pi_fine_inc88_out;
  wire [0:0]E;
  wire \FSM_onehot_cal1_state_r[0]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[17]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[17]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[18]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[19]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[19]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[19]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[19]_i_4_n_0 ;
  wire \FSM_onehot_cal1_state_r[1]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[20]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[22]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[23]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[23]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[24]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[24]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[25]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[26]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[27]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[27]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[27]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[28]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[29]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[29]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[29]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[2]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[30]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[31]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[31]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_10_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_11_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_12_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_13_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_14_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_6_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_7_n_0 ;
  wire \FSM_onehot_cal1_state_r[32]_i_9_n_0 ;
  wire \FSM_onehot_cal1_state_r[3]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[4]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[4]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[4]_i_4_n_0 ;
  wire \FSM_onehot_cal1_state_r[5]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[5]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r_reg[0]_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[10] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[11] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[12] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[13] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[14] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[15] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[16] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[17] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[18] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[19] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[20] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[21] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[22] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[23] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[24] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[25] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[26] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[27] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[28] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[29] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[30] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[31] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[32] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[6] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[7] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[8] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_cal1_state_r_reg_n_0_[9] ;
  wire [2:0]Q;
  wire \cal1_cnt_cpt_r[0]_i_1_n_0 ;
  wire \cal1_cnt_cpt_r[0]_i_2_n_0 ;
  wire \cal1_cnt_cpt_r[1]_i_1_n_0 ;
  wire \cal1_cnt_cpt_r[2]_i_1_n_0 ;
  wire \cal1_cnt_cpt_r[2]_i_2_n_0 ;
  wire \cal1_cnt_cpt_r_reg_n_0_[0] ;
  wire \cal1_cnt_cpt_r_reg_n_0_[1] ;
  wire \cal1_cnt_cpt_r_reg_n_0_[2] ;
  wire cal1_dlyce_cpt_r;
  wire cal1_dlyce_cpt_r_reg_n_0;
  wire cal1_dlyinc_cpt_r_i_1_n_0;
  wire cal1_dlyinc_cpt_r_reg_n_0;
  wire cal1_dq_idel_ce;
  wire cal1_prech_req_r_reg_n_0;
  wire cal1_state_r1;
  wire cal1_state_r1538_out;
  wire \cal1_state_r1[0]_i_1_n_0 ;
  wire \cal1_state_r1[0]_i_2_n_0 ;
  wire \cal1_state_r1[1]_i_1_n_0 ;
  wire \cal1_state_r1[1]_i_2_n_0 ;
  wire \cal1_state_r1[1]_i_3_n_0 ;
  wire \cal1_state_r1[2]_i_1_n_0 ;
  wire \cal1_state_r1[3]_i_1_n_0 ;
  wire \cal1_state_r1[3]_i_2_n_0 ;
  wire \cal1_state_r1[4]_i_1_n_0 ;
  wire \cal1_state_r1_reg_n_0_[0] ;
  wire \cal1_state_r1_reg_n_0_[1] ;
  wire \cal1_state_r1_reg_n_0_[2] ;
  wire \cal1_state_r1_reg_n_0_[3] ;
  wire \cal1_state_r1_reg_n_0_[4] ;
  wire \cal1_state_r1_reg_n_0_[5] ;
  wire cal1_wait_cnt_en_r;
  wire cal1_wait_cnt_en_r0;
  wire cal1_wait_cnt_en_r_i_2_n_0;
  wire cal1_wait_cnt_en_r_i_3_n_0;
  wire \cal1_wait_cnt_r[4]_i_1_n_0 ;
  wire [4:0]cal1_wait_cnt_r_reg__0;
  wire cal1_wait_r;
  wire cal1_wait_r_i_1_n_0;
  wire [1:0]\calib_sel_reg[1] ;
  wire [5:0]cnt_idel_dec_cpt_r;
  wire \cnt_idel_dec_cpt_r[0]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[0]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_10_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_12_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_13_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_14_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_15_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_8_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_9_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_10_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_11_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_13_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_14_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_8_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_9_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_10_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_1_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_8_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_9_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_2 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_4 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_5 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_11_n_7 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_4 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_5 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_7 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_12_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_12_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_12_n_7 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_2_n_2 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_2_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_2_n_5 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_2_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[3]_i_2_n_7 ;
  wire \cnt_idel_dec_cpt_r_reg[5]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[0] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[1] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[2] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[3] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[4] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[5] ;
  wire [3:0]cnt_shift_r_reg__0;
  wire complex_row0_rd_done;
  wire \ctl_lane_cnt_reg[1] ;
  wire detect_edge_done_r;
  wire detect_edge_done_r_i_1_n_0;
  wire detect_edge_done_r_i_2_n_0;
  wire done_cnt1;
  wire \done_cnt[0]_i_1_n_0 ;
  wire \done_cnt[1]_i_1_n_0 ;
  wire \done_cnt[2]_i_1_n_0 ;
  wire \done_cnt[3]_i_1_n_0 ;
  wire \done_cnt_reg_n_0_[0] ;
  wire \done_cnt_reg_n_0_[1] ;
  wire \done_cnt_reg_n_0_[2] ;
  wire \done_cnt_reg_n_0_[3] ;
  wire \dqs_count_r_reg[0]_rep ;
  wire \dqs_count_r_reg[1]_rep ;
  wire \dqs_count_r_reg[2]_rep__0 ;
  wire [0:0]\dqs_count_r_reg[3] ;
  wire dqs_found_done_r_reg;
  wire dqs_po_dec_done;
  wire dqs_po_dec_done_r1;
  wire dqs_po_dec_done_r2;
  wire fine_dly_dec_done_r1;
  wire fine_dly_dec_done_r1_i_1_n_0;
  wire fine_dly_dec_done_r1_i_2_n_0;
  wire fine_dly_dec_done_r1_reg_0;
  wire fine_dly_dec_done_r2;
  wire \first_edge_taps_r[5]_i_1_n_0 ;
  wire \first_edge_taps_r[5]_i_2_n_0 ;
  wire \first_edge_taps_r[5]_i_3_n_0 ;
  wire \first_edge_taps_r_reg_n_0_[0] ;
  wire \first_edge_taps_r_reg_n_0_[1] ;
  wire \first_edge_taps_r_reg_n_0_[2] ;
  wire \first_edge_taps_r_reg_n_0_[3] ;
  wire \first_edge_taps_r_reg_n_0_[4] ;
  wire \first_edge_taps_r_reg_n_0_[5] ;
  wire first_rdlvl_pat_r;
  wire first_wrcal_pat_r;
  wire found_edge_r_i_1_n_0;
  wire found_edge_r_i_2_n_0;
  wire found_edge_r_reg_n_0;
  wire found_first_edge_r_i_1_n_0;
  wire found_first_edge_r_reg_n_0;
  wire found_second_edge_r_i_1_n_0;
  wire found_second_edge_r_reg_n_0;
  wire found_stable_eye_last_r;
  wire found_stable_eye_last_r_i_1_n_0;
  wire found_stable_eye_r_i_1_n_0;
  wire found_stable_eye_r_i_2_n_0;
  wire found_stable_eye_r_reg_n_0;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[2] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_215 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_199 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_239 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_207 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_247 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_223 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_231 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_255 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_135 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_151 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_191 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_167 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_183 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_143 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_175 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_159 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_216 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_200 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_240 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_208 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_248 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_224 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_232 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_256 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_136 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_152 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_192 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_168 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_184 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_144 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_176 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_160 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_217 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_201 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_241 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_209 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_249 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_225 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_233 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_257 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_137 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_153 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_193 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_169 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_185 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_145 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_177 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_161 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_218 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_202 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_242 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_210 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_250 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_226 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_234 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_258 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_138 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_154 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_194 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_170 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_186 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_146 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_178 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_162 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_219 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_203 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_243 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_211 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_251 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_227 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_235 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_259 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_139 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_155 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_195 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_171 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_187 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_147 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_179 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_163 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_220 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_204 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_244 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_212 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_252 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_228 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_236 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_260 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_140 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_156 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_196 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_172 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_188 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_148 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_180 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_164 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_221 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_205 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_245 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_213 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_253 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_229 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_237 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_261 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_141 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_157 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_197 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_173 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_189 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_149 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_181 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_165 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_222 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_206 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_246 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_214 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_254 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_230 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_238 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_262 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_142 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_158 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_198 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_174 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_190 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_150 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_182 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_166 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 ;
  wire \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ;
  wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ;
  wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 ;
  wire \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ;
  wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0 ;
  wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4_n_0 ;
  wire \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 ;
  wire \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ;
  wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0 ;
  wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4_n_0 ;
  wire \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 ;
  wire \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ;
  wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0 ;
  wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4_n_0 ;
  wire \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 ;
  wire \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ;
  wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0 ;
  wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4_n_0 ;
  wire \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 ;
  wire \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ;
  wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0 ;
  wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4_n_0 ;
  wire \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 ;
  wire \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ;
  wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0 ;
  wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4_n_0 ;
  wire \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_6_n_0 ;
  wire [4:0]\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 ;
  wire \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ;
  wire \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0 ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0 ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4_n_0 ;
  wire \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ;
  wire idel_adj_inc_i_1_n_0;
  wire idel_adj_inc_i_2_n_0;
  wire idel_adj_inc_reg_n_0;
  wire [4:0]idel_dec_cnt;
  wire \idel_dec_cnt[0]_i_3_n_0 ;
  wire \idel_dec_cnt[0]_i_4_n_0 ;
  wire \idel_dec_cnt[1]_i_3_n_0 ;
  wire \idel_dec_cnt[1]_i_4_n_0 ;
  wire \idel_dec_cnt[3]_i_2_n_0 ;
  wire \idel_dec_cnt[4]_i_1_n_0 ;
  wire \idel_dec_cnt[4]_i_3_n_0 ;
  wire \idel_dec_cnt[4]_i_4_n_0 ;
  wire \idel_dec_cnt[4]_i_5_n_0 ;
  wire \idel_dec_cnt[4]_i_6_n_0 ;
  wire \idel_dec_cnt[4]_i_7_n_0 ;
  wire \idel_dec_cnt_reg[0]_i_2_n_0 ;
  wire \idel_dec_cnt_reg[1]_i_2_n_0 ;
  wire \idel_dec_cnt_reg_n_0_[0] ;
  wire \idel_dec_cnt_reg_n_0_[1] ;
  wire \idel_dec_cnt_reg_n_0_[2] ;
  wire \idel_dec_cnt_reg_n_0_[3] ;
  wire \idel_dec_cnt_reg_n_0_[4] ;
  wire idel_mpr_pat_detect_r;
  wire idel_pat0_data_match_r0;
  wire idel_pat0_match_fall0_and_r;
  wire [7:0]idel_pat0_match_fall0_r;
  wire idel_pat0_match_fall1_and_r;
  wire [7:0]idel_pat0_match_fall1_r;
  wire idel_pat0_match_fall2_and_r;
  wire [7:0]idel_pat0_match_fall2_r;
  wire idel_pat0_match_fall3_and_r;
  wire [7:0]idel_pat0_match_fall3_r;
  wire idel_pat0_match_rise0_and_r;
  wire [7:0]idel_pat0_match_rise0_r;
  wire idel_pat0_match_rise1_and_r;
  wire [7:0]idel_pat0_match_rise1_r;
  wire idel_pat0_match_rise2_and_r;
  wire [7:0]idel_pat0_match_rise2_r;
  wire idel_pat0_match_rise3_and_r;
  wire [7:0]idel_pat0_match_rise3_r;
  wire idel_pat1_data_match_r0;
  wire idel_pat1_match_fall0_and_r;
  wire [7:1]idel_pat1_match_fall0_r;
  wire idel_pat1_match_fall1_and_r;
  wire [7:0]idel_pat1_match_fall1_r;
  wire idel_pat1_match_fall2_and_r;
  wire [7:1]idel_pat1_match_fall2_r;
  wire idel_pat1_match_fall3_and_r;
  wire [7:0]idel_pat1_match_fall3_r;
  wire idel_pat1_match_rise0_and_r;
  wire [6:0]idel_pat1_match_rise0_r;
  wire idel_pat1_match_rise1_and_r;
  wire [7:0]idel_pat1_match_rise1_r;
  wire idel_pat1_match_rise2_and_r;
  wire [6:0]idel_pat1_match_rise2_r;
  wire idel_pat1_match_rise3_and_r;
  wire [7:0]idel_pat1_match_rise3_r;
  wire idel_pat_detect_valid_r_i_1_n_0;
  wire idel_pat_detect_valid_r_reg_n_0;
  wire idelay_ce_int;
  wire idelay_inc_int;
  wire [4:0]idelay_tap_cnt_r;
  wire \idelay_tap_cnt_r[0][0][0]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][1]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][2]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][4]_i_2_n_0 ;
  wire \idelay_tap_cnt_r[0][0][4]_i_5_n_0 ;
  wire \idelay_tap_cnt_r[0][0][4]_i_6_n_0 ;
  wire \idelay_tap_cnt_r[0][1][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][1][4]_i_2_n_0 ;
  wire \idelay_tap_cnt_r[0][2][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][3][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][4][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][5][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][5][4]_i_2_n_0 ;
  wire \idelay_tap_cnt_r[0][6][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r_reg[0][7][3]_0 ;
  wire \idelay_tap_cnt_r_reg[0][7][4]_0 ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][4] ;
  wire [4:0]idelay_tap_cnt_slice_r;
  wire \idelay_tap_cnt_slice_r[2]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[2]_i_3_n_0 ;
  wire \idelay_tap_cnt_slice_r[3]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[3]_i_3_n_0 ;
  wire \idelay_tap_cnt_slice_r[4]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[4]_i_3_n_0 ;
  wire idelay_tap_limit_r_i_1_n_0;
  wire idelay_tap_limit_r_i_2_n_0;
  wire idelay_tap_limit_r_reg_0;
  wire idelay_tap_limit_r_reg_n_0;
  wire inhibit_edge_detect_r;
  wire inhibit_edge_detect_r0;
  wire \init_state_r_reg[0] ;
  wire \init_state_r_reg[0]_0 ;
  wire \init_state_r_reg[2] ;
  wire \init_state_r_reg[3] ;
  wire \init_state_r_reg[4] ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[1]_i_2_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[1]_i_3_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[1]_i_4_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[1]_i_5_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_2_n_0 ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[0] ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[1] ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[2] ;
  wire mpr_dec_cpt_r;
  wire mpr_dec_cpt_r_i_1_n_0;
  wire mpr_dec_cpt_r_reg_n_0;
  wire mpr_rd_fall0_prev_r;
  wire mpr_rd_fall1_prev_r;
  wire mpr_rd_fall2_prev_r;
  wire mpr_rd_fall3_prev_r;
  wire mpr_rd_rise0_prev_r;
  wire mpr_rd_rise0_prev_r0;
  wire mpr_rd_rise1_prev_r;
  wire mpr_rd_rise2_prev_r;
  wire mpr_rd_rise3_prev_r;
  wire mpr_rdlvl_start_r;
  wire mpr_rdlvl_start_reg;
  wire new_cnt_cpt_r;
  wire new_cnt_cpt_r_i_2_n_0;
  wire \one_rank.stg1_wr_done_reg ;
  wire [5:2]p_0_in;
  wire p_0_in100_in;
  wire p_0_in103_in;
  wire p_0_in106_in;
  wire p_0_in10_in;
  wire p_0_in138_in;
  wire p_0_in13_in;
  wire p_0_in160_in;
  wire p_0_in16_in;
  wire p_0_in185_in;
  wire p_0_in1_in;
  wire p_0_in210_in;
  wire p_0_in235_in;
  wire p_0_in260_in;
  wire p_0_in285_in;
  wire p_0_in310_in;
  wire p_0_in335_in;
  wire p_0_in360_in;
  wire p_0_in385_in;
  wire p_0_in410_in;
  wire p_0_in435_in;
  wire p_0_in460_in;
  wire p_0_in4_in;
  wire p_0_in7_in;
  wire p_0_in91_in;
  wire p_0_in94_in;
  wire p_0_in97_in;
  wire [4:0]p_0_in__0;
  wire [3:0]p_0_in__1;
  wire [4:0]p_0_in__2;
  wire [4:0]p_0_in__3;
  wire [4:0]p_0_in__4;
  wire [4:0]p_0_in__5;
  wire [4:0]p_0_in__6;
  wire [4:0]p_0_in__7;
  wire [4:0]p_0_in__8;
  wire [4:0]p_0_in__9;
  wire p_143_out;
  wire p_145_out;
  wire p_147_out;
  wire p_149_out;
  wire p_151_out;
  wire p_153_out;
  wire p_155_out;
  wire p_157_out;
  wire p_159_out;
  wire p_168_out;
  wire p_170_out;
  wire p_172_out;
  wire p_174_out;
  wire p_176_out;
  wire p_178_out;
  wire p_180_out;
  wire p_182_out;
  wire p_184_out;
  wire p_193_out;
  wire p_195_out;
  wire p_197_out;
  wire p_199_out;
  wire p_1_in11_in;
  wire p_1_in142_in;
  wire p_1_in14_in;
  wire p_1_in167_in;
  wire p_1_in17_in;
  wire p_1_in192_in;
  wire p_1_in217_in;
  wire p_1_in242_in;
  wire p_1_in267_in;
  wire p_1_in292_in;
  wire p_1_in2_in;
  wire p_1_in317_in;
  wire p_1_in342_in;
  wire p_1_in367_in;
  wire p_1_in392_in;
  wire p_1_in417_in;
  wire p_1_in442_in;
  wire p_1_in467_in;
  wire p_1_in5_in;
  wire p_1_in8_in;
  wire p_201_out;
  wire p_203_out;
  wire p_205_out;
  wire p_207_out;
  wire p_209_out;
  wire p_218_out;
  wire p_220_out;
  wire p_222_out;
  wire p_224_out;
  wire p_226_out;
  wire p_228_out;
  wire p_230_out;
  wire p_232_out;
  wire p_234_out;
  wire p_243_out;
  wire p_245_out;
  wire p_247_out;
  wire p_249_out;
  wire p_251_out;
  wire p_253_out;
  wire p_255_out;
  wire p_257_out;
  wire p_259_out;
  wire p_268_out;
  wire p_270_out;
  wire p_272_out;
  wire p_274_out;
  wire p_276_out;
  wire p_278_out;
  wire p_280_out;
  wire p_282_out;
  wire p_284_out;
  wire p_293_out;
  wire p_295_out;
  wire p_297_out;
  wire p_299_out;
  wire p_2_in161_in;
  wire p_2_in186_in;
  wire p_2_in211_in;
  wire p_2_in236_in;
  wire p_2_in261_in;
  wire p_2_in286_in;
  wire p_2_in311_in;
  wire p_2_in336_in;
  wire p_2_in361_in;
  wire p_2_in386_in;
  wire p_2_in411_in;
  wire p_2_in436_in;
  wire p_2_in461_in;
  wire p_301_out;
  wire p_303_out;
  wire p_305_out;
  wire p_307_out;
  wire p_309_out;
  wire p_318_out;
  wire p_320_out;
  wire p_322_out;
  wire p_324_out;
  wire p_326_out;
  wire p_328_out;
  wire p_330_out;
  wire p_332_out;
  wire p_334_out;
  wire p_343_out;
  wire p_345_out;
  wire p_347_out;
  wire p_349_out;
  wire p_351_out;
  wire p_353_out;
  wire p_355_out;
  wire p_357_out;
  wire p_359_out;
  wire p_368_out;
  wire p_370_out;
  wire p_372_out;
  wire p_374_out;
  wire p_376_out;
  wire p_378_out;
  wire p_380_out;
  wire p_382_out;
  wire p_384_out;
  wire p_393_out;
  wire p_395_out;
  wire p_397_out;
  wire p_399_out;
  wire p_3_in139_in;
  wire p_3_in162_in;
  wire p_3_in187_in;
  wire p_3_in212_in;
  wire p_3_in237_in;
  wire p_3_in262_in;
  wire p_3_in287_in;
  wire p_3_in312_in;
  wire p_3_in337_in;
  wire p_3_in362_in;
  wire p_3_in387_in;
  wire p_3_in412_in;
  wire p_3_in437_in;
  wire p_3_in462_in;
  wire p_401_out;
  wire p_403_out;
  wire p_405_out;
  wire p_407_out;
  wire p_409_out;
  wire p_418_out;
  wire p_420_out;
  wire p_422_out;
  wire p_424_out;
  wire p_426_out;
  wire p_428_out;
  wire p_430_out;
  wire p_432_out;
  wire p_434_out;
  wire p_443_out;
  wire p_445_out;
  wire p_447_out;
  wire p_449_out;
  wire p_451_out;
  wire p_453_out;
  wire p_455_out;
  wire p_457_out;
  wire p_459_out;
  wire p_468_out;
  wire p_470_out;
  wire p_472_out;
  wire p_474_out;
  wire p_476_out;
  wire p_478_out;
  wire p_480_out;
  wire p_482_out;
  wire p_484_out;
  wire p_493_out;
  wire p_495_out;
  wire p_497_out;
  wire p_499_out;
  wire p_4_in140_in;
  wire p_4_in163_in;
  wire p_4_in188_in;
  wire p_4_in213_in;
  wire p_4_in238_in;
  wire p_4_in263_in;
  wire p_4_in288_in;
  wire p_4_in313_in;
  wire p_4_in338_in;
  wire p_4_in363_in;
  wire p_4_in388_in;
  wire p_4_in413_in;
  wire p_4_in438_in;
  wire p_4_in463_in;
  wire p_501_out;
  wire p_503_out;
  wire p_505_out;
  wire p_507_out;
  wire p_509_out;
  wire p_518_out;
  wire p_520_out;
  wire p_522_out;
  wire p_524_out;
  wire p_526_out;
  wire p_528_out;
  wire p_530_out;
  wire p_532_out;
  wire p_536_out;
  wire p_5_in164_in;
  wire p_5_in189_in;
  wire p_5_in214_in;
  wire p_5_in239_in;
  wire p_5_in264_in;
  wire p_5_in289_in;
  wire p_5_in314_in;
  wire p_5_in339_in;
  wire p_5_in364_in;
  wire p_5_in389_in;
  wire p_5_in414_in;
  wire p_5_in439_in;
  wire p_5_in464_in;
  wire p_6_in165_in;
  wire p_6_in190_in;
  wire p_6_in215_in;
  wire p_6_in240_in;
  wire p_6_in265_in;
  wire p_6_in290_in;
  wire p_6_in315_in;
  wire p_6_in340_in;
  wire p_6_in365_in;
  wire p_6_in390_in;
  wire p_6_in415_in;
  wire p_6_in440_in;
  wire p_6_in465_in;
  wire p_7_in141_in;
  wire p_7_in166_in;
  wire p_7_in191_in;
  wire p_7_in216_in;
  wire p_7_in241_in;
  wire p_7_in266_in;
  wire p_7_in291_in;
  wire p_7_in316_in;
  wire p_7_in341_in;
  wire p_7_in366_in;
  wire p_7_in391_in;
  wire p_7_in416_in;
  wire p_7_in441_in;
  wire p_7_in466_in;
  wire pat0_data_match_r0;
  wire pat0_match_fall0_and_r;
  wire [4:0]pat0_match_fall0_r;
  wire pat0_match_fall1_and_r;
  wire [6:2]pat0_match_fall1_r;
  wire pat0_match_fall2_and_r;
  wire pat0_match_fall3_and_r;
  wire [5:1]pat0_match_fall3_r;
  wire pat0_match_rise0_and_r;
  wire [5:1]pat0_match_rise0_r;
  wire pat0_match_rise1_and_r;
  wire [5:1]pat0_match_rise1_r;
  wire pat0_match_rise2_and_r;
  wire [7:3]pat0_match_rise2_r;
  wire pat0_match_rise3_and_r;
  wire [5:1]pat0_match_rise3_r;
  wire pat1_data_match_r0;
  wire pat1_match_fall0_and_r;
  wire pat1_match_fall1_and_r;
  wire pat1_match_fall2_and_r;
  wire [4:0]pat1_match_fall2_r;
  wire pat1_match_fall3_and_r;
  wire [6:2]pat1_match_fall3_r;
  wire pat1_match_rise0_and_r;
  wire [7:3]pat1_match_rise0_r;
  wire pat1_match_rise1_and_r;
  wire pat1_match_rise2_and_r;
  wire pat1_match_rise3_and_r;
  wire pb_detect_edge;
  wire [7:0]pb_detect_edge_done_r;
  wire pb_detect_edge_setup;
  wire [7:0]pb_found_stable_eye_r;
  wire pb_found_stable_eye_r55_out;
  wire pb_found_stable_eye_r59_out;
  wire pb_found_stable_eye_r63_out;
  wire pb_found_stable_eye_r67_out;
  wire pb_found_stable_eye_r71_out;
  wire pb_found_stable_eye_r75_out;
  wire pb_found_stable_eye_r79_out;
  wire pi_cnt_dec_i_1_n_0;
  wire pi_cnt_dec_i_2_n_0;
  wire \pi_counter_read_val_reg[0] ;
  wire \pi_counter_read_val_reg[0]_0 ;
  wire \pi_counter_read_val_reg[1] ;
  wire \pi_counter_read_val_reg[1]_0 ;
  wire \pi_counter_read_val_reg[2] ;
  wire \pi_counter_read_val_reg[2]_0 ;
  wire \pi_counter_read_val_reg[3] ;
  wire \pi_counter_read_val_reg[4] ;
  wire \pi_counter_read_val_reg[4]_0 ;
  wire \pi_counter_read_val_reg[5] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[10] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[1] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[2] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[4] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[8] ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[9] ;
  wire pi_en_stg2_f_timing;
  wire pi_en_stg2_f_timing_i_1_n_0;
  wire pi_fine_dly_dec_done;
  wire [5:0]pi_rdval_cnt;
  wire \pi_rdval_cnt[0]_i_1_n_0 ;
  wire \pi_rdval_cnt[1]_i_1_n_0 ;
  wire \pi_rdval_cnt[2]_i_1_n_0 ;
  wire \pi_rdval_cnt[2]_i_3_n_0 ;
  wire \pi_rdval_cnt[3]_i_1_n_0 ;
  wire \pi_rdval_cnt[3]_i_3_n_0 ;
  wire \pi_rdval_cnt[4]_i_1_n_0 ;
  wire \pi_rdval_cnt[4]_i_2_n_0 ;
  wire \pi_rdval_cnt[5]_i_1_n_0 ;
  wire \pi_rdval_cnt[5]_i_2_n_0 ;
  wire \pi_rdval_cnt[5]_i_3_n_0 ;
  wire \pi_rdval_cnt[5]_i_4_n_0 ;
  wire pi_stg2_f_incdec_timing;
  wire pi_stg2_f_incdec_timing0;
  wire pi_stg2_load;
  wire pi_stg2_load_timing;
  wire pi_stg2_load_timing_i_1_n_0;
  wire [5:0]pi_stg2_reg_l;
  wire [5:0]pi_stg2_reg_l_timing;
  wire \pi_stg2_reg_l_timing[0]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[0]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[1]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[1]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[2]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[2]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[3]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[3]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[4]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[4]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_4_n_0 ;
  wire \po_stg2_wrcal_cnt_reg[0] ;
  wire \po_stg2_wrcal_cnt_reg[0]_0 ;
  wire \po_stg2_wrcal_cnt_reg[0]_1 ;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[3] ;
  wire prbs_last_byte_done_r;
  wire prbs_rdlvl_done_pulse_reg;
  wire prech_done;
  wire rd_active_r;
  wire \rd_mux_sel_r_reg[0]_0 ;
  wire \rd_mux_sel_r_reg[0]_1 ;
  wire \rd_mux_sel_r_reg[0]_10 ;
  wire \rd_mux_sel_r_reg[0]_11 ;
  wire \rd_mux_sel_r_reg[0]_12 ;
  wire \rd_mux_sel_r_reg[0]_13 ;
  wire \rd_mux_sel_r_reg[0]_14 ;
  wire \rd_mux_sel_r_reg[0]_15 ;
  wire \rd_mux_sel_r_reg[0]_16 ;
  wire \rd_mux_sel_r_reg[0]_17 ;
  wire \rd_mux_sel_r_reg[0]_18 ;
  wire \rd_mux_sel_r_reg[0]_19 ;
  wire \rd_mux_sel_r_reg[0]_2 ;
  wire \rd_mux_sel_r_reg[0]_20 ;
  wire \rd_mux_sel_r_reg[0]_21 ;
  wire \rd_mux_sel_r_reg[0]_22 ;
  wire \rd_mux_sel_r_reg[0]_23 ;
  wire \rd_mux_sel_r_reg[0]_24 ;
  wire \rd_mux_sel_r_reg[0]_25 ;
  wire \rd_mux_sel_r_reg[0]_26 ;
  wire \rd_mux_sel_r_reg[0]_27 ;
  wire \rd_mux_sel_r_reg[0]_28 ;
  wire \rd_mux_sel_r_reg[0]_29 ;
  wire \rd_mux_sel_r_reg[0]_3 ;
  wire \rd_mux_sel_r_reg[0]_30 ;
  wire \rd_mux_sel_r_reg[0]_31 ;
  wire \rd_mux_sel_r_reg[0]_32 ;
  wire \rd_mux_sel_r_reg[0]_33 ;
  wire \rd_mux_sel_r_reg[0]_34 ;
  wire \rd_mux_sel_r_reg[0]_35 ;
  wire \rd_mux_sel_r_reg[0]_36 ;
  wire \rd_mux_sel_r_reg[0]_37 ;
  wire \rd_mux_sel_r_reg[0]_38 ;
  wire \rd_mux_sel_r_reg[0]_39 ;
  wire \rd_mux_sel_r_reg[0]_4 ;
  wire \rd_mux_sel_r_reg[0]_40 ;
  wire \rd_mux_sel_r_reg[0]_41 ;
  wire \rd_mux_sel_r_reg[0]_42 ;
  wire \rd_mux_sel_r_reg[0]_43 ;
  wire \rd_mux_sel_r_reg[0]_44 ;
  wire \rd_mux_sel_r_reg[0]_45 ;
  wire \rd_mux_sel_r_reg[0]_46 ;
  wire \rd_mux_sel_r_reg[0]_47 ;
  wire \rd_mux_sel_r_reg[0]_48 ;
  wire \rd_mux_sel_r_reg[0]_49 ;
  wire \rd_mux_sel_r_reg[0]_5 ;
  wire \rd_mux_sel_r_reg[0]_50 ;
  wire \rd_mux_sel_r_reg[0]_51 ;
  wire \rd_mux_sel_r_reg[0]_52 ;
  wire \rd_mux_sel_r_reg[0]_53 ;
  wire \rd_mux_sel_r_reg[0]_54 ;
  wire \rd_mux_sel_r_reg[0]_55 ;
  wire \rd_mux_sel_r_reg[0]_56 ;
  wire \rd_mux_sel_r_reg[0]_57 ;
  wire \rd_mux_sel_r_reg[0]_58 ;
  wire \rd_mux_sel_r_reg[0]_59 ;
  wire \rd_mux_sel_r_reg[0]_6 ;
  wire \rd_mux_sel_r_reg[0]_60 ;
  wire \rd_mux_sel_r_reg[0]_61 ;
  wire \rd_mux_sel_r_reg[0]_62 ;
  wire \rd_mux_sel_r_reg[0]_63 ;
  wire \rd_mux_sel_r_reg[0]_7 ;
  wire \rd_mux_sel_r_reg[0]_8 ;
  wire \rd_mux_sel_r_reg[0]_9 ;
  wire [5:0]rdlvl_dqs_tap_cnt_r;
  wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ;
  wire [2:0]\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5] ;
  wire rdlvl_last_byte_done;
  wire rdlvl_last_byte_done_i_1_n_0;
  wire rdlvl_pi_stg2_f_en;
  wire rdlvl_pi_stg2_f_incdec;
  wire rdlvl_prech_req;
  wire rdlvl_rank_done_r_i_1_n_0;
  wire rdlvl_rank_done_r_i_2_n_0;
  wire rdlvl_stg1_done_i_1_n_0;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_r;
  wire rdlvl_stg1_start_reg;
  wire [0:0]rdlvl_stg1_start_reg_0;
  wire [3:0]regl_dqs_cnt;
  wire \regl_dqs_cnt[0]_i_1_n_0 ;
  wire \regl_dqs_cnt[1]_i_1_n_0 ;
  wire \regl_dqs_cnt[2]_i_1_n_0 ;
  wire \regl_dqs_cnt[3]_i_1_n_0 ;
  wire \regl_dqs_cnt[3]_i_2_n_0 ;
  wire \regl_dqs_cnt[3]_i_3_n_0 ;
  wire \regl_dqs_cnt[3]_i_4_n_0 ;
  wire [3:0]regl_dqs_cnt_r;
  wire reset_if;
  wire reset_if_r9;
  wire reset_if_reg;
  wire [5:0]right_edge_taps_r;
  wire \right_edge_taps_r[5]_i_1_n_0 ;
  wire \right_edge_taps_r_reg_n_0_[0] ;
  wire \right_edge_taps_r_reg_n_0_[1] ;
  wire \right_edge_taps_r_reg_n_0_[2] ;
  wire \right_edge_taps_r_reg_n_0_[3] ;
  wire \right_edge_taps_r_reg_n_0_[4] ;
  wire \right_edge_taps_r_reg_n_0_[5] ;
  wire \rnk_cnt_r[0]_i_1__0_n_0 ;
  wire \rnk_cnt_r[1]_i_1__0_n_0 ;
  wire \rnk_cnt_r_reg_n_0_[0] ;
  wire \rnk_cnt_r_reg_n_0_[1] ;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire [0:0]rstdiv0_sync_r1_reg_rep__2;
  wire rstdiv0_sync_r1_reg_rep__22;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__24_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire samp_cnt_done_r_i_1_n_0;
  wire samp_cnt_done_r_i_2_n_0;
  wire samp_cnt_done_r_i_3_n_0;
  wire samp_cnt_done_r_reg_n_0;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt0_r[0]_i_3_n_0 ;
  wire [11:0]samp_edge_cnt0_r_reg;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[10]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[10]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[11]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[1]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[1]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[2]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[2]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[3]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[3]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[4]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[5]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[5]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[6]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[6]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[7]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[7]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[8]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[9]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[9]_i_2_n_0 ;
  wire samp_edge_cnt1_en_r;
  wire samp_edge_cnt1_en_r0;
  wire samp_edge_cnt1_en_r_i_2_n_0;
  wire samp_edge_cnt1_en_r_i_3_n_0;
  wire \samp_edge_cnt1_r[0]_i_2_n_0 ;
  wire [11:0]samp_edge_cnt1_r_reg;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[10]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[10]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[11]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[1]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[1]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[2]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[2]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[3]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[3]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[4]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[5]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[5]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[6]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[6]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[7]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[7]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[8]_i_2_n_0 ;
  wire \samp_edge_cnt1_r_reg[9]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[9]_i_2_n_0 ;
  wire \second_edge_taps_r[0]_i_1_n_0 ;
  wire \second_edge_taps_r[1]_i_1_n_0 ;
  wire \second_edge_taps_r[2]_i_1_n_0 ;
  wire \second_edge_taps_r[3]_i_1_n_0 ;
  wire \second_edge_taps_r[4]_i_1_n_0 ;
  wire \second_edge_taps_r[5]_i_1_n_0 ;
  wire \second_edge_taps_r[5]_i_2_n_0 ;
  wire \second_edge_taps_r[5]_i_3_n_0 ;
  wire \second_edge_taps_r_reg_n_0_[0] ;
  wire \second_edge_taps_r_reg_n_0_[1] ;
  wire \second_edge_taps_r_reg_n_0_[2] ;
  wire \second_edge_taps_r_reg_n_0_[3] ;
  wire \second_edge_taps_r_reg_n_0_[4] ;
  wire \second_edge_taps_r_reg_n_0_[5] ;
  wire sr_valid_r1;
  wire sr_valid_r2;
  wire sr_valid_r_i_1_n_0;
  wire sr_valid_r_reg_n_0;
  wire stable_idel_cnt0;
  wire stable_idel_cnt23_in;
  wire stg1_wr_done;
  wire \stg1_wr_rd_cnt_reg[3] ;
  wire store_sr_r0;
  wire store_sr_r_i_1_n_0;
  wire store_sr_r_reg_n_0;
  wire store_sr_req_pulsed_r__0;
  wire store_sr_req_r;
  wire store_sr_req_r_reg_n_0;
  wire \tap_cnt_cpt_r[1]_i_1_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_2_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_4_n_0 ;
  wire \tap_cnt_cpt_r_reg_n_0_[0] ;
  wire \tap_cnt_cpt_r_reg_n_0_[1] ;
  wire \tap_cnt_cpt_r_reg_n_0_[2] ;
  wire \tap_cnt_cpt_r_reg_n_0_[3] ;
  wire \tap_cnt_cpt_r_reg_n_0_[4] ;
  wire \tap_cnt_cpt_r_reg_n_0_[5] ;
  wire tap_limit_cpt_r;
  wire tap_limit_cpt_r_i_1_n_0;
  wire tap_limit_cpt_r_i_2_n_0;
  wire tap_limit_cpt_r_i_3_n_0;
  wire tempmon_pi_f_en_r;
  wire tempmon_pi_f_inc_r;
  wire wait_cnt_r0;
  wire [3:0]wait_cnt_r0__0;
  wire \wait_cnt_r[1]_i_1__0_n_0 ;
  wire [3:0]wait_cnt_r_reg__0__0;
  wire wr_level_done_reg;
  wire wrcal_done_reg;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep ;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ;
  wire [0:0]\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511] ;
  wire wrlvl_done_r1;
  wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[3]_i_12_CO_UNCONNECTED ;
  wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[3]_i_12_O_UNCONNECTED ;
  wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[3]_i_2_CO_UNCONNECTED ;
  wire [3:3]\NLW_cnt_idel_dec_cpt_r_reg[3]_i_2_O_UNCONNECTED ;
  wire [3:2]\NLW_samp_edge_cnt0_r_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
  wire [3:3]\NLW_samp_edge_cnt0_r_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_samp_edge_cnt1_r_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
  wire [3:3]\NLW_samp_edge_cnt1_r_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;

  LUT5 #(
    .INIT(32'hA8000000)) 
    \FSM_onehot_cal1_state_r[0]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[32]_i_7_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I4(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .O(\FSM_onehot_cal1_state_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_cal1_state_r[0]_i_2 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(\FSM_onehot_cal1_state_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h0000000000000F04)) 
    \FSM_onehot_cal1_state_r[17]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[18] ),
        .I1(\FSM_onehot_cal1_state_r[17]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .O(\FSM_onehot_cal1_state_r[17]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \FSM_onehot_cal1_state_r[17]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I4(idel_adj_inc_reg_n_0),
        .O(\FSM_onehot_cal1_state_r[17]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \FSM_onehot_cal1_state_r[18]_i_1 
       (.I0(idel_pat_detect_valid_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I2(\FSM_onehot_cal1_state_r[24]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[18]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF10FF10FFFFFF10)) 
    \FSM_onehot_cal1_state_r[19]_i_1 
       (.I0(mpr_dec_cpt_r_reg_n_0),
        .I1(cal1_state_r1),
        .I2(\FSM_onehot_cal1_state_r[23]_i_2_n_0 ),
        .I3(\FSM_onehot_cal1_state_r[19]_i_2_n_0 ),
        .I4(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ),
        .I5(\FSM_onehot_cal1_state_r[19]_i_3_n_0 ),
        .O(\FSM_onehot_cal1_state_r[19]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h200020002000FFFF)) 
    \FSM_onehot_cal1_state_r[19]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .I2(idel_adj_inc_reg_n_0),
        .I3(\FSM_onehot_cal1_state_r[27]_i_3_n_0 ),
        .I4(\FSM_onehot_cal1_state_r[19]_i_4_n_0 ),
        .I5(\FSM_onehot_cal1_state_r[24]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[19]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hEF)) 
    \FSM_onehot_cal1_state_r[19]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .O(\FSM_onehot_cal1_state_r[19]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h001FFF1FFF1FFF1F)) 
    \FSM_onehot_cal1_state_r[19]_i_4 
       (.I0(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I4(idel_pat_detect_valid_r_reg_n_0),
        .I5(idel_mpr_pat_detect_r),
        .O(\FSM_onehot_cal1_state_r[19]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \FSM_onehot_cal1_state_r[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .I1(mpr_rdlvl_start_r),
        .I2(mpr_rdlvl_start_reg),
        .O(\FSM_onehot_cal1_state_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_onehot_cal1_state_r[20]_i_1 
       (.I0(idelay_tap_limit_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[21]_i_1 
       (.I0(idelay_tap_limit_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[21]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFAAEFFFEFFFEFFF)) 
    \FSM_onehot_cal1_state_r[21]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[24]_i_2_n_0 ),
        .I1(idel_mpr_pat_detect_r),
        .I2(idel_pat_detect_valid_r_reg_n_0),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(idel_adj_inc_i_2_n_0),
        .O(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \FSM_onehot_cal1_state_r[22]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .I1(\FSM_onehot_cal1_state_r[24]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .O(\FSM_onehot_cal1_state_r[22]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88F8888888888888)) 
    \FSM_onehot_cal1_state_r[23]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[23]_i_2_n_0 ),
        .I1(cal1_state_r1),
        .I2(mpr_dec_cpt_r_reg_n_0),
        .I3(\FSM_onehot_cal1_state_r[29]_i_3_n_0 ),
        .I4(stable_idel_cnt23_in),
        .I5(\FSM_onehot_cal1_state_r[29]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[23]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_onehot_cal1_state_r[23]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[27]_i_3_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[24] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .O(\FSM_onehot_cal1_state_r[23]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_onehot_cal1_state_r[23]_i_3 
       (.I0(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I1(\idel_dec_cnt_reg_n_0_[2] ),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\idel_dec_cnt_reg_n_0_[0] ),
        .I4(\idel_dec_cnt_reg_n_0_[3] ),
        .I5(\idel_dec_cnt_reg_n_0_[4] ),
        .O(cal1_state_r1));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \FSM_onehot_cal1_state_r[23]_i_4 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),
        .I1(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),
        .I2(\idel_dec_cnt_reg[0]_i_2_n_0 ),
        .O(stable_idel_cnt23_in));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \FSM_onehot_cal1_state_r[24]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[24]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .O(\FSM_onehot_cal1_state_r[24]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_onehot_cal1_state_r[24]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[18] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF80000000000000)) 
    \FSM_onehot_cal1_state_r[25]_i_1 
       (.I0(found_edge_r_reg_n_0),
        .I1(found_stable_eye_last_r),
        .I2(found_first_edge_r_reg_n_0),
        .I3(tap_limit_cpt_r),
        .I4(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\FSM_onehot_cal1_state_r[25]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007F000000000000)) 
    \FSM_onehot_cal1_state_r[26]_i_1 
       (.I0(found_edge_r_reg_n_0),
        .I1(found_stable_eye_last_r),
        .I2(found_first_edge_r_reg_n_0),
        .I3(tap_limit_cpt_r),
        .I4(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\FSM_onehot_cal1_state_r[26]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \FSM_onehot_cal1_state_r[27]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\FSM_onehot_cal1_state_r[27]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \FSM_onehot_cal1_state_r[27]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[27]_i_3_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[24] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .O(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_cal1_state_r[27]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I2(\FSM_onehot_cal1_state_r[24]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[27]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_cal1_state_r[28]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[29]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[29]_i_3_n_0 ),
        .O(\FSM_onehot_cal1_state_r[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_cal1_state_r[29]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[29]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[29]_i_3_n_0 ),
        .I2(mpr_dec_cpt_r_reg_n_0),
        .O(\FSM_onehot_cal1_state_r[29]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    \FSM_onehot_cal1_state_r[29]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I1(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .O(\FSM_onehot_cal1_state_r[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \FSM_onehot_cal1_state_r[29]_i_3 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .O(\FSM_onehot_cal1_state_r[29]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hD0FFD0D0D0D0D0D0)) 
    \FSM_onehot_cal1_state_r[2]_i_1 
       (.I0(mpr_rdlvl_start_reg),
        .I1(mpr_rdlvl_start_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .I5(\FSM_onehot_cal1_state_r[32]_i_7_n_0 ),
        .O(\FSM_onehot_cal1_state_r[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h08888888)) 
    \FSM_onehot_cal1_state_r[30]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[32]_i_7_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(\FSM_onehot_cal1_state_r[30]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0200)) 
    \FSM_onehot_cal1_state_r[31]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[32]_i_7_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .I3(\FSM_onehot_cal1_state_r[31]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h2000000000000000)) 
    \FSM_onehot_cal1_state_r[31]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I1(regl_dqs_cnt[3]),
        .I2(regl_dqs_cnt[0]),
        .I3(regl_dqs_cnt[1]),
        .I4(regl_dqs_cnt[2]),
        .I5(\FSM_onehot_cal1_state_r[32]_i_13_n_0 ),
        .O(\FSM_onehot_cal1_state_r[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAA2)) 
    \FSM_onehot_cal1_state_r[32]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I1(cal1_wait_r),
        .I2(\pi_counter_read_val_reg[1] ),
        .I3(\pi_counter_read_val_reg[0]_0 ),
        .I4(\pi_counter_read_val_reg[2] ),
        .I5(\FSM_onehot_cal1_state_r[32]_i_6_n_0 ),
        .O(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_onehot_cal1_state_r[32]_i_10 
       (.I0(\FSM_onehot_cal1_state_r[32]_i_14_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .O(\FSM_onehot_cal1_state_r[32]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hFFE0E0E0)) 
    \FSM_onehot_cal1_state_r[32]_i_11 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(detect_edge_done_r),
        .I3(prech_done),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\FSM_onehot_cal1_state_r[32]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    \FSM_onehot_cal1_state_r[32]_i_12 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[32]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \FSM_onehot_cal1_state_r[32]_i_13 
       (.I0(\done_cnt_reg_n_0_[3] ),
        .I1(\done_cnt_reg_n_0_[2] ),
        .I2(\done_cnt_reg_n_0_[0] ),
        .I3(\done_cnt_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[32]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF4F440000)) 
    \FSM_onehot_cal1_state_r[32]_i_14 
       (.I0(mpr_rdlvl_start_r),
        .I1(mpr_rdlvl_start_reg),
        .I2(rdlvl_stg1_start_r),
        .I3(rdlvl_stg1_start_reg),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .I5(cal1_dq_idel_ce),
        .O(\FSM_onehot_cal1_state_r[32]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h00000200AAAAAAAA)) 
    \FSM_onehot_cal1_state_r[32]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[32]_i_7_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I4(cal1_state_r1538_out),
        .I5(\FSM_onehot_cal1_state_r[32]_i_9_n_0 ),
        .O(\FSM_onehot_cal1_state_r[32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEFFFFFFEF)) 
    \FSM_onehot_cal1_state_r[32]_i_6 
       (.I0(\FSM_onehot_cal1_state_r[32]_i_10_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[32]_i_11_n_0 ),
        .I2(\cal1_state_r1[1]_i_3_n_0 ),
        .I3(\cal1_state_r1[0]_i_2_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .I5(cal1_wait_r),
        .O(\FSM_onehot_cal1_state_r[32]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_cal1_state_r[32]_i_7 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[28] ),
        .I2(\FSM_onehot_cal1_state_r[32]_i_12_n_0 ),
        .O(\FSM_onehot_cal1_state_r[32]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00008000)) 
    \FSM_onehot_cal1_state_r[32]_i_8 
       (.I0(\FSM_onehot_cal1_state_r[32]_i_13_n_0 ),
        .I1(regl_dqs_cnt[2]),
        .I2(regl_dqs_cnt[1]),
        .I3(regl_dqs_cnt[0]),
        .I4(regl_dqs_cnt[3]),
        .O(cal1_state_r1538_out));
  LUT6 #(
    .INIT(64'hFBFFFFFFFFFFFFFF)) 
    \FSM_onehot_cal1_state_r[32]_i_9 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I5(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(\FSM_onehot_cal1_state_r[32]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h0A0A0B0A)) 
    \FSM_onehot_cal1_state_r[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[18] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .O(\FSM_onehot_cal1_state_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF8FFF8F888888888)) 
    \FSM_onehot_cal1_state_r[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[4]_i_2_n_0 ),
        .I1(mpr_dec_cpt_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[28] ),
        .I5(\FSM_onehot_cal1_state_r[4]_i_4_n_0 ),
        .O(\FSM_onehot_cal1_state_r[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_onehot_cal1_state_r[4]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .O(\FSM_onehot_cal1_state_r[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_cal1_state_r[4]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I1(\pi_counter_read_val_reg[4]_0 ),
        .O(mpr_dec_cpt_r));
  LUT4 #(
    .INIT(16'h0002)) 
    \FSM_onehot_cal1_state_r[4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[27]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .O(\FSM_onehot_cal1_state_r[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT5 #(
    .INIT(32'hFFFF0400)) 
    \FSM_onehot_cal1_state_r[5]_i_1 
       (.I0(stable_idel_cnt23_in),
        .I1(mpr_dec_cpt_r_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r[29]_i_3_n_0 ),
        .I3(\FSM_onehot_cal1_state_r[29]_i_2_n_0 ),
        .I4(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h40FF404040404040)) 
    \FSM_onehot_cal1_state_r[5]_i_2 
       (.I0(\pi_counter_read_val_reg[4]_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I2(\FSM_onehot_cal1_state_r[4]_i_2_n_0 ),
        .I3(cal1_state_r1),
        .I4(mpr_dec_cpt_r_reg_n_0),
        .I5(\FSM_onehot_cal1_state_r[23]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_cal1_state_r_reg[0] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[0]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .S(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[10] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[10] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[11] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[11] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[12] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[13] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[14] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[14] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[15] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[16] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[17] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[17]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[18] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[18]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[18] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[19] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[19]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[1] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[1]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[20] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[20]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[21] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[21]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[21] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[22] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[22]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[23] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[23]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[24] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[24]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[24] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[25] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[25]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[26] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[26]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[27] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[27]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[28] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[28]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[28] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[29] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[29]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[2] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[2]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[30] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[30]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[31] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[31]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[32] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[32]_i_2_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[3] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[3]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[4] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[4]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[5] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[6] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[7] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[8] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .R(rstdiv0_sync_r1));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[9] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[32]_i_1_n_0 ),
        .D(1'b0),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[9] ),
        .R(rstdiv0_sync_r1));
  LUT6 #(
    .INIT(64'h15115555EAEE0000)) 
    \cal1_cnt_cpt_r[0]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I1(prech_done),
        .I2(\cal1_cnt_cpt_r[0]_i_2_n_0 ),
        .I3(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I5(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .O(\cal1_cnt_cpt_r[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \cal1_cnt_cpt_r[0]_i_2 
       (.I0(\rnk_cnt_r_reg_n_0_[1] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\cal1_cnt_cpt_r[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h2F80)) 
    \cal1_cnt_cpt_r[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\cal1_cnt_cpt_r[2]_i_2_n_0 ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cal1_cnt_cpt_r[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h2AFF8000)) 
    \cal1_cnt_cpt_r[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\cal1_cnt_cpt_r[2]_i_2_n_0 ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(\cal1_cnt_cpt_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEAEEEEAAAAAAAA)) 
    \cal1_cnt_cpt_r[2]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I1(prech_done),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\cal1_cnt_cpt_r[2]_i_2_n_0 ));
  FDRE \cal1_cnt_cpt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r[0]_i_1_n_0 ),
        .Q(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \cal1_cnt_cpt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r[1]_i_1_n_0 ),
        .Q(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \cal1_cnt_cpt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r[2]_i_1_n_0 ),
        .Q(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT3 #(
    .INIT(8'hBA)) 
    cal1_dlyce_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I1(tap_limit_cpt_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .O(cal1_dlyce_cpt_r));
  FDRE cal1_dlyce_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_dlyce_cpt_r),
        .Q(cal1_dlyce_cpt_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT2 #(
    .INIT(4'h2)) 
    cal1_dlyinc_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I1(tap_limit_cpt_r),
        .O(cal1_dlyinc_cpt_r_i_1_n_0));
  FDRE cal1_dlyinc_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_dlyinc_cpt_r_i_1_n_0),
        .Q(cal1_dlyinc_cpt_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT2 #(
    .INIT(4'hE)) 
    cal1_dq_idel_ce_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .O(cal1_dq_idel_ce));
  FDRE cal1_dq_idel_ce_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_dq_idel_ce),
        .Q(idelay_ce_int),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE cal1_dq_idel_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .Q(idelay_inc_int),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE cal1_prech_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .Q(cal1_prech_req_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[0]_i_1 
       (.I0(\cal1_state_r1[0]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I5(\cal1_state_r1[1]_i_2_n_0 ),
        .O(\cal1_state_r1[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \cal1_state_r1[0]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[28] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[24] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .O(\cal1_state_r1[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    \cal1_state_r1[1]_i_1 
       (.I0(\cal1_state_r1[1]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[24] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I5(\cal1_state_r1[1]_i_3_n_0 ),
        .O(\cal1_state_r1[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[1]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .O(\cal1_state_r1[1]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \cal1_state_r1[1]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[18] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .O(\cal1_state_r1[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cal1_state_r1[2]_i_1 
       (.I0(\cal1_state_r1[3]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[24] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .O(\cal1_state_r1[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[3]_i_1 
       (.I0(\cal1_state_r1[3]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[26] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\cal1_state_r1[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cal1_state_r1[3]_i_2 
       (.I0(\cal1_state_r1[4]_i_1_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[28] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\cal1_state_r1[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[18] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[21] ),
        .O(\cal1_state_r1[4]_i_1_n_0 ));
  FDRE \cal1_state_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[0]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[1]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[2]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[3]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[3] ),
        .R(1'b0));
  FDSE \cal1_state_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[4]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[4] ),
        .S(\FSM_onehot_cal1_state_r_reg_n_0_[32] ));
  FDRE \cal1_state_r1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .Q(\cal1_state_r1_reg_n_0_[5] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    cal1_wait_cnt_en_r_i_1
       (.I0(cal1_wait_cnt_en_r_i_2_n_0),
        .I1(cal1_wait_cnt_en_r_i_3_n_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .O(cal1_wait_cnt_en_r0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    cal1_wait_cnt_en_r_i_2
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[27] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[24] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[28] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .O(cal1_wait_cnt_en_r_i_2_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    cal1_wait_cnt_en_r_i_3
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[11] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[18] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(cal1_wait_cnt_en_r_i_3_n_0));
  FDRE cal1_wait_cnt_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_wait_cnt_en_r0),
        .Q(cal1_wait_cnt_en_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cal1_wait_cnt_r[0]_i_1 
       (.I0(cal1_wait_cnt_r_reg__0[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cal1_wait_cnt_r[1]_i_1 
       (.I0(cal1_wait_cnt_r_reg__0[1]),
        .I1(cal1_wait_cnt_r_reg__0[0]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cal1_wait_cnt_r[2]_i_1 
       (.I0(cal1_wait_cnt_r_reg__0[2]),
        .I1(cal1_wait_cnt_r_reg__0[0]),
        .I2(cal1_wait_cnt_r_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cal1_wait_cnt_r[3]_i_1 
       (.I0(cal1_wait_cnt_r_reg__0[3]),
        .I1(cal1_wait_cnt_r_reg__0[1]),
        .I2(cal1_wait_cnt_r_reg__0[0]),
        .I3(cal1_wait_cnt_r_reg__0[2]),
        .O(p_0_in__0[3]));
  LUT6 #(
    .INIT(64'h40000000FFFFFFFF)) 
    \cal1_wait_cnt_r[4]_i_1 
       (.I0(cal1_wait_cnt_r_reg__0[4]),
        .I1(cal1_wait_cnt_r_reg__0[3]),
        .I2(cal1_wait_cnt_r_reg__0[1]),
        .I3(cal1_wait_cnt_r_reg__0[0]),
        .I4(cal1_wait_cnt_r_reg__0[2]),
        .I5(cal1_wait_cnt_en_r),
        .O(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cal1_wait_cnt_r[4]_i_2 
       (.I0(cal1_wait_cnt_r_reg__0[4]),
        .I1(cal1_wait_cnt_r_reg__0[2]),
        .I2(cal1_wait_cnt_r_reg__0[0]),
        .I3(cal1_wait_cnt_r_reg__0[1]),
        .I4(cal1_wait_cnt_r_reg__0[3]),
        .O(p_0_in__0[4]));
  FDRE \cal1_wait_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(cal1_wait_cnt_r_reg__0[0]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(cal1_wait_cnt_r_reg__0[1]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(cal1_wait_cnt_r_reg__0[2]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(cal1_wait_cnt_r_reg__0[3]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(cal1_wait_cnt_r_reg__0[4]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFFFFFFFFFFFFF)) 
    cal1_wait_r_i_1
       (.I0(cal1_wait_cnt_r_reg__0[4]),
        .I1(cal1_wait_cnt_r_reg__0[3]),
        .I2(cal1_wait_cnt_r_reg__0[1]),
        .I3(cal1_wait_cnt_r_reg__0[0]),
        .I4(cal1_wait_cnt_r_reg__0[2]),
        .I5(cal1_wait_cnt_en_r),
        .O(cal1_wait_r_i_1_n_0));
  FDRE cal1_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_wait_r_i_1_n_0),
        .Q(cal1_wait_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF2A20)) 
    \cnt_idel_dec_cpt_r[0]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I1(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_6 ),
        .I2(found_second_edge_r_reg_n_0),
        .I3(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ),
        .O(cnt_idel_dec_cpt_r[0]));
  LUT6 #(
    .INIT(64'h6F606F6F6F606060)) 
    \cnt_idel_dec_cpt_r[0]_i_2 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\right_edge_taps_r_reg_n_0_[1] ),
        .I2(\cnt_idel_dec_cpt_r[3]_i_9_n_0 ),
        .I3(\cnt_idel_dec_cpt_r_reg[2]_i_11_n_6 ),
        .I4(found_first_edge_r_reg_n_0),
        .I5(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \cnt_idel_dec_cpt_r[0]_i_3 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I2(\pi_counter_read_val_reg[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I1(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_5 ),
        .I2(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_6 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[1]_i_2_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ),
        .O(cnt_idel_dec_cpt_r[1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \cnt_idel_dec_cpt_r[1]_i_2 
       (.I0(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ),
        .I1(\cnt_idel_dec_cpt_r[3]_i_9_n_0 ),
        .I2(\cnt_idel_dec_cpt_r_reg[2]_i_11_n_5 ),
        .I3(found_first_edge_r_reg_n_0),
        .I4(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF909090)) 
    \cnt_idel_dec_cpt_r[1]_i_3 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I3(\pi_counter_read_val_reg[1]_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT4 #(
    .INIT(16'h4BB4)) 
    \cnt_idel_dec_cpt_r[1]_i_4 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\right_edge_taps_r_reg_n_0_[1] ),
        .I2(\right_edge_taps_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I1(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_4 ),
        .I2(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ),
        .O(cnt_idel_dec_cpt_r[2]));
  LUT6 #(
    .INIT(64'h40F4BF0BBF0B40F4)) 
    \cnt_idel_dec_cpt_r[2]_i_10 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\right_edge_taps_r_reg_n_0_[1] ),
        .I2(\right_edge_taps_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\right_edge_taps_r_reg_n_0_[3] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_12 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\first_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_13 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\first_edge_taps_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_14 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I1(\first_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_15 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\first_edge_taps_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \cnt_idel_dec_cpt_r[2]_i_3 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_5 ),
        .I1(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_6 ),
        .O(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \cnt_idel_dec_cpt_r[2]_i_4 
       (.I0(\cnt_idel_dec_cpt_r[2]_i_10_n_0 ),
        .I1(\cnt_idel_dec_cpt_r[3]_i_9_n_0 ),
        .I2(\cnt_idel_dec_cpt_r_reg[2]_i_11_n_4 ),
        .I3(found_first_edge_r_reg_n_0),
        .I4(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFA900A900A900)) 
    \cnt_idel_dec_cpt_r[2]_i_5 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I4(\pi_counter_read_val_reg[2]_0 ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_6 
       (.I0(\second_edge_taps_r_reg_n_0_[3] ),
        .I1(\first_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_7 
       (.I0(\second_edge_taps_r_reg_n_0_[2] ),
        .I1(\first_edge_taps_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_8 
       (.I0(\second_edge_taps_r_reg_n_0_[1] ),
        .I1(\first_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_9 
       (.I0(\second_edge_taps_r_reg_n_0_[0] ),
        .I1(\first_edge_taps_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I1(\cnt_idel_dec_cpt_r_reg[3]_i_2_n_7 ),
        .I2(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ),
        .O(cnt_idel_dec_cpt_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cnt_idel_dec_cpt_r[3]_i_10 
       (.I0(\cnt_idel_dec_cpt_r_reg[3]_i_12_n_7 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \cnt_idel_dec_cpt_r[3]_i_11 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[3]_i_13 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(\first_edge_taps_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[3]_i_14 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I1(\first_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \cnt_idel_dec_cpt_r[3]_i_3 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_4 ),
        .I1(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_6 ),
        .I2(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_5 ),
        .O(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h96FF9600)) 
    \cnt_idel_dec_cpt_r[3]_i_4 
       (.I0(\cnt_idel_dec_cpt_r[3]_i_8_n_0 ),
        .I1(\right_edge_taps_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I3(\cnt_idel_dec_cpt_r[3]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[3]_i_10_n_0 ),
        .O(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF606060)) 
    \cnt_idel_dec_cpt_r[3]_i_5 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I1(\cnt_idel_dec_cpt_r[3]_i_11_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I3(\pi_counter_read_val_reg[3] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[3]_i_6 
       (.I0(\second_edge_taps_r_reg_n_0_[5] ),
        .I1(\first_edge_taps_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[3]_i_7 
       (.I0(\second_edge_taps_r_reg_n_0_[4] ),
        .I1(\first_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h2B222222BBBB2B22)) 
    \cnt_idel_dec_cpt_r[3]_i_8 
       (.I0(\right_edge_taps_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\right_edge_taps_r_reg_n_0_[1] ),
        .I4(\right_edge_taps_r_reg_n_0_[2] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cnt_idel_dec_cpt_r[3]_i_9 
       (.I0(\right_edge_taps_r_reg_n_0_[0] ),
        .I1(\right_edge_taps_r_reg_n_0_[5] ),
        .I2(\right_edge_taps_r_reg_n_0_[1] ),
        .I3(\right_edge_taps_r_reg_n_0_[4] ),
        .I4(\right_edge_taps_r_reg_n_0_[2] ),
        .I5(\right_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hEAEAFFEAFFEAEAEA)) 
    \cnt_idel_dec_cpt_r[4]_i_1 
       (.I0(\cnt_idel_dec_cpt_r[4]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I2(\pi_counter_read_val_reg[4] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I4(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .O(cnt_idel_dec_cpt_r[4]));
  LUT6 #(
    .INIT(64'h2EEEE22200000000)) 
    \cnt_idel_dec_cpt_r[4]_i_2 
       (.I0(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ),
        .I1(found_second_edge_r_reg_n_0),
        .I2(\cnt_idel_dec_cpt_r_reg[3]_i_2_n_7 ),
        .I3(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ),
        .I4(\cnt_idel_dec_cpt_r_reg[3]_i_2_n_6 ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \cnt_idel_dec_cpt_r[4]_i_4 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h96FF9600)) 
    \cnt_idel_dec_cpt_r[4]_i_5 
       (.I0(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),
        .I1(\right_edge_taps_r_reg_n_0_[5] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r[3]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[4]_i_6_n_0 ),
        .O(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cnt_idel_dec_cpt_r[4]_i_6 
       (.I0(\cnt_idel_dec_cpt_r_reg[3]_i_12_n_6 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \cnt_idel_dec_cpt_r[5]_i_1 
       (.I0(mpr_dec_cpt_r),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT5 #(
    .INIT(32'h2F0FFF2F)) 
    \cnt_idel_dec_cpt_r[5]_i_10 
       (.I0(\right_edge_taps_r_reg_n_0_[1] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\right_edge_taps_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hFFF8F8F8)) 
    \cnt_idel_dec_cpt_r[5]_i_2 
       (.I0(\pi_counter_read_val_reg[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I2(\cnt_idel_dec_cpt_r[5]_i_4_n_0 ),
        .I3(\cnt_idel_dec_cpt_r_reg[5]_i_5_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[25] ),
        .O(cnt_idel_dec_cpt_r[5]));
  LUT4 #(
    .INIT(16'hA208)) 
    \cnt_idel_dec_cpt_r[5]_i_4 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I1(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h20A28A08)) 
    \cnt_idel_dec_cpt_r[5]_i_6 
       (.I0(\cnt_idel_dec_cpt_r[3]_i_9_n_0 ),
        .I1(\right_edge_taps_r_reg_n_0_[5] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_idel_dec_cpt_r[5]_i_7 
       (.I0(\cnt_idel_dec_cpt_r_reg[3]_i_2_n_5 ),
        .I1(\cnt_idel_dec_cpt_r_reg[3]_i_2_n_7 ),
        .I2(\cnt_idel_dec_cpt_r_reg[3]_i_2_n_6 ),
        .I3(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_4 ),
        .I4(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_6 ),
        .I5(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_5 ),
        .O(\cnt_idel_dec_cpt_r[5]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h20BA)) 
    \cnt_idel_dec_cpt_r[5]_i_8 
       (.I0(\right_edge_taps_r_reg_n_0_[4] ),
        .I1(\cnt_idel_dec_cpt_r[5]_i_9_n_0 ),
        .I2(\cnt_idel_dec_cpt_r[5]_i_10_n_0 ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFBB2B)) 
    \cnt_idel_dec_cpt_r[5]_i_9 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I1(\right_edge_taps_r_reg_n_0_[2] ),
        .I2(\right_edge_taps_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\right_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_9_n_0 ));
  FDRE \cnt_idel_dec_cpt_r_reg[0] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[0]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[1] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[1]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[2] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[2]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .R(1'b0));
  CARRY4 \cnt_idel_dec_cpt_r_reg[2]_i_11 
       (.CI(1'b0),
        .CO({\cnt_idel_dec_cpt_r_reg[2]_i_11_n_0 ,\cnt_idel_dec_cpt_r_reg[2]_i_11_n_1 ,\cnt_idel_dec_cpt_r_reg[2]_i_11_n_2 ,\cnt_idel_dec_cpt_r_reg[2]_i_11_n_3 }),
        .CYINIT(1'b1),
        .DI({\tap_cnt_cpt_r_reg_n_0_[3] ,\tap_cnt_cpt_r_reg_n_0_[2] ,\tap_cnt_cpt_r_reg_n_0_[1] ,\tap_cnt_cpt_r_reg_n_0_[0] }),
        .O({\cnt_idel_dec_cpt_r_reg[2]_i_11_n_4 ,\cnt_idel_dec_cpt_r_reg[2]_i_11_n_5 ,\cnt_idel_dec_cpt_r_reg[2]_i_11_n_6 ,\cnt_idel_dec_cpt_r_reg[2]_i_11_n_7 }),
        .S({\cnt_idel_dec_cpt_r[2]_i_12_n_0 ,\cnt_idel_dec_cpt_r[2]_i_13_n_0 ,\cnt_idel_dec_cpt_r[2]_i_14_n_0 ,\cnt_idel_dec_cpt_r[2]_i_15_n_0 }));
  CARRY4 \cnt_idel_dec_cpt_r_reg[2]_i_2 
       (.CI(1'b0),
        .CO({\cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_1 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_2 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_3 }),
        .CYINIT(1'b1),
        .DI({\second_edge_taps_r_reg_n_0_[3] ,\second_edge_taps_r_reg_n_0_[2] ,\second_edge_taps_r_reg_n_0_[1] ,\second_edge_taps_r_reg_n_0_[0] }),
        .O({\cnt_idel_dec_cpt_r_reg[2]_i_2_n_4 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_5 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_6 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_7 }),
        .S({\cnt_idel_dec_cpt_r[2]_i_6_n_0 ,\cnt_idel_dec_cpt_r[2]_i_7_n_0 ,\cnt_idel_dec_cpt_r[2]_i_8_n_0 ,\cnt_idel_dec_cpt_r[2]_i_9_n_0 }));
  FDRE \cnt_idel_dec_cpt_r_reg[3] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[3]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .R(1'b0));
  CARRY4 \cnt_idel_dec_cpt_r_reg[3]_i_12 
       (.CI(\cnt_idel_dec_cpt_r_reg[2]_i_11_n_0 ),
        .CO({\NLW_cnt_idel_dec_cpt_r_reg[3]_i_12_CO_UNCONNECTED [3:1],\cnt_idel_dec_cpt_r_reg[3]_i_12_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\tap_cnt_cpt_r_reg_n_0_[4] }),
        .O({\NLW_cnt_idel_dec_cpt_r_reg[3]_i_12_O_UNCONNECTED [3:2],\cnt_idel_dec_cpt_r_reg[3]_i_12_n_6 ,\cnt_idel_dec_cpt_r_reg[3]_i_12_n_7 }),
        .S({1'b0,1'b0,\cnt_idel_dec_cpt_r[3]_i_13_n_0 ,\cnt_idel_dec_cpt_r[3]_i_14_n_0 }));
  CARRY4 \cnt_idel_dec_cpt_r_reg[3]_i_2 
       (.CI(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ),
        .CO({\NLW_cnt_idel_dec_cpt_r_reg[3]_i_2_CO_UNCONNECTED [3:2],\cnt_idel_dec_cpt_r_reg[3]_i_2_n_2 ,\cnt_idel_dec_cpt_r_reg[3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\second_edge_taps_r_reg_n_0_[5] ,\second_edge_taps_r_reg_n_0_[4] }),
        .O({\NLW_cnt_idel_dec_cpt_r_reg[3]_i_2_O_UNCONNECTED [3],\cnt_idel_dec_cpt_r_reg[3]_i_2_n_5 ,\cnt_idel_dec_cpt_r_reg[3]_i_2_n_6 ,\cnt_idel_dec_cpt_r_reg[3]_i_2_n_7 }),
        .S({1'b0,1'b1,\cnt_idel_dec_cpt_r[3]_i_6_n_0 ,\cnt_idel_dec_cpt_r[3]_i_7_n_0 }));
  FDRE \cnt_idel_dec_cpt_r_reg[4] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[4]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[5] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[5]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .R(1'b0));
  MUXF7 \cnt_idel_dec_cpt_r_reg[5]_i_5 
       (.I0(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ),
        .I1(\cnt_idel_dec_cpt_r[5]_i_7_n_0 ),
        .O(\cnt_idel_dec_cpt_r_reg[5]_i_5_n_0 ),
        .S(found_second_edge_r_reg_n_0));
  LUT6 #(
    .INIT(64'h5554555555555555)) 
    \cnt_shift_r[0]_i_1 
       (.I0(cnt_shift_r_reg__0[0]),
        .I1(cnt_shift_r_reg__0[1]),
        .I2(cnt_shift_r_reg__0[3]),
        .I3(cnt_shift_r_reg__0[2]),
        .I4(rdlvl_stg1_start_reg),
        .I5(rd_active_r),
        .O(p_0_in__1[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_shift_r[1]_i_1 
       (.I0(cnt_shift_r_reg__0[1]),
        .I1(cnt_shift_r_reg__0[0]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_shift_r[2]_i_1 
       (.I0(cnt_shift_r_reg__0[2]),
        .I1(cnt_shift_r_reg__0[0]),
        .I2(cnt_shift_r_reg__0[1]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_shift_r[3]_i_3 
       (.I0(cnt_shift_r_reg__0[3]),
        .I1(cnt_shift_r_reg__0[1]),
        .I2(cnt_shift_r_reg__0[0]),
        .I3(cnt_shift_r_reg__0[2]),
        .O(p_0_in__1[3]));
  FDSE \cnt_shift_r_reg[0] 
       (.C(CLK),
        .CE(rdlvl_stg1_start_reg_0),
        .D(p_0_in__1[0]),
        .Q(cnt_shift_r_reg__0[0]),
        .S(rstdiv0_sync_r1_reg_rep__24_3));
  FDRE \cnt_shift_r_reg[1] 
       (.C(CLK),
        .CE(rdlvl_stg1_start_reg_0),
        .D(p_0_in__1[1]),
        .Q(cnt_shift_r_reg__0[1]),
        .R(rstdiv0_sync_r1_reg_rep__24_3));
  FDRE \cnt_shift_r_reg[2] 
       (.C(CLK),
        .CE(rdlvl_stg1_start_reg_0),
        .D(p_0_in__1[2]),
        .Q(cnt_shift_r_reg__0[2]),
        .R(rstdiv0_sync_r1_reg_rep__24_3));
  FDRE \cnt_shift_r_reg[3] 
       (.C(CLK),
        .CE(rdlvl_stg1_start_reg_0),
        .D(p_0_in__1[3]),
        .Q(cnt_shift_r_reg__0[3]),
        .R(rstdiv0_sync_r1_reg_rep__24_3));
  LUT2 #(
    .INIT(4'h7)) 
    \ctl_lane_cnt[1]_i_4 
       (.I0(pi_fine_dly_dec_done),
        .I1(dqs_po_dec_done),
        .O(\ctl_lane_cnt_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_10 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[1]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[9] [1]));
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_10__0 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[1]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[10] [1]));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_11 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[0]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[9] [0]));
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_11__0 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[0]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[10] [0]));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_6 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[5]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[9] [5]));
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_6__0 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[5]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[10] [5]));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_7 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[4]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[9] [4]));
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_7__0 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[4]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[10] [4]));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_8 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[3]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[9] [3]));
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_8__0 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[3]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[10] [3]));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_9 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[2]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[9] [2]));
  LUT5 #(
    .INIT(32'h44440040)) 
    \ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_in_gen.phaser_in_i_9__0 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[2]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[10] [2]));
  LUT3 #(
    .INIT(8'h80)) 
    detect_edge_done_r_i_1
       (.I0(pb_detect_edge_done_r[1]),
        .I1(pb_detect_edge_done_r[0]),
        .I2(detect_edge_done_r_i_2_n_0),
        .O(detect_edge_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    detect_edge_done_r_i_2
       (.I0(pb_detect_edge_done_r[3]),
        .I1(pb_detect_edge_done_r[2]),
        .I2(pb_detect_edge_done_r[6]),
        .I3(pb_detect_edge_done_r[7]),
        .I4(pb_detect_edge_done_r[4]),
        .I5(pb_detect_edge_done_r[5]),
        .O(detect_edge_done_r_i_2_n_0));
  FDRE detect_edge_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(detect_edge_done_r_i_1_n_0),
        .Q(detect_edge_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000005554)) 
    \done_cnt[0]_i_1 
       (.I0(\done_cnt_reg_n_0_[0] ),
        .I1(\done_cnt_reg_n_0_[1] ),
        .I2(\done_cnt_reg_n_0_[3] ),
        .I3(\done_cnt_reg_n_0_[2] ),
        .I4(done_cnt1),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\done_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT5 #(
    .INIT(32'hFFAAAAFE)) 
    \done_cnt[1]_i_1 
       (.I0(done_cnt1),
        .I1(\done_cnt_reg_n_0_[2] ),
        .I2(\done_cnt_reg_n_0_[3] ),
        .I3(\done_cnt_reg_n_0_[0] ),
        .I4(\done_cnt_reg_n_0_[1] ),
        .O(\done_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000AAA4)) 
    \done_cnt[2]_i_1 
       (.I0(\done_cnt_reg_n_0_[2] ),
        .I1(\done_cnt_reg_n_0_[3] ),
        .I2(\done_cnt_reg_n_0_[0] ),
        .I3(\done_cnt_reg_n_0_[1] ),
        .I4(done_cnt1),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\done_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT5 #(
    .INIT(32'hFAFAFAEA)) 
    \done_cnt[3]_i_1 
       (.I0(done_cnt1),
        .I1(\done_cnt_reg_n_0_[2] ),
        .I2(\done_cnt_reg_n_0_[3] ),
        .I3(\done_cnt_reg_n_0_[0] ),
        .I4(\done_cnt_reg_n_0_[1] ),
        .O(\done_cnt[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \done_cnt[3]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I1(\FSM_onehot_cal1_state_r[32]_i_13_n_0 ),
        .I2(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .O(done_cnt1));
  FDRE \done_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[0]_i_1_n_0 ),
        .Q(\done_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \done_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[1]_i_1_n_0 ),
        .Q(\done_cnt_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \done_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[2]_i_1_n_0 ),
        .Q(\done_cnt_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \done_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[3]_i_1_n_0 ),
        .Q(\done_cnt_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE dqs_po_dec_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_dec_done),
        .Q(dqs_po_dec_done_r1),
        .R(1'b0));
  FDRE dqs_po_dec_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_dec_done_r1),
        .Q(dqs_po_dec_done_r2),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF88F8)) 
    fine_dly_dec_done_r1_i_1
       (.I0(fine_dly_dec_done_r1_i_2_n_0),
        .I1(fine_dly_dec_done_r1_reg_0),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(fine_dly_dec_done_r1),
        .O(fine_dly_dec_done_r1_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    fine_dly_dec_done_r1_i_2
       (.I0(pi_rdval_cnt[1]),
        .I1(pi_rdval_cnt[5]),
        .I2(pi_rdval_cnt[3]),
        .I3(pi_rdval_cnt[4]),
        .I4(pi_rdval_cnt[0]),
        .I5(pi_rdval_cnt[2]),
        .O(fine_dly_dec_done_r1_i_2_n_0));
  FDRE fine_dly_dec_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_dly_dec_done_r1_i_1_n_0),
        .Q(fine_dly_dec_done_r1),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE fine_dly_dec_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_dly_dec_done_r1),
        .Q(fine_dly_dec_done_r2),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \first_edge_taps_r[5]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\first_edge_taps_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAEEEAAAA)) 
    \first_edge_taps_r[5]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\first_edge_taps_r[5]_i_3_n_0 ),
        .I2(found_stable_eye_last_r),
        .I3(found_first_edge_r_reg_n_0),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\first_edge_taps_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \first_edge_taps_r[5]_i_3 
       (.I0(found_edge_r_reg_n_0),
        .I1(detect_edge_done_r),
        .I2(tap_limit_cpt_r),
        .O(\first_edge_taps_r[5]_i_3_n_0 ));
  FDRE \first_edge_taps_r_reg[0] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\first_edge_taps_r_reg_n_0_[0] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[1] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\first_edge_taps_r_reg_n_0_[1] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[2] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\first_edge_taps_r_reg_n_0_[2] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[3] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\first_edge_taps_r_reg_n_0_[3] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[4] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\first_edge_taps_r_reg_n_0_[4] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[5] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\first_edge_taps_r_reg_n_0_[5] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    found_edge_r_i_1
       (.I0(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I1(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I2(found_edge_r_i_2_n_0),
        .O(found_edge_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    found_edge_r_i_2
       (.I0(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I1(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I2(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I3(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I4(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I5(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .O(found_edge_r_i_2_n_0));
  FDRE found_edge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_edge_r_i_1_n_0),
        .Q(found_edge_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hDDDD555588C80000)) 
    found_first_edge_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(found_edge_r_reg_n_0),
        .I2(detect_edge_done_r),
        .I3(tap_limit_cpt_r),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I5(found_first_edge_r_reg_n_0),
        .O(found_first_edge_r_i_1_n_0));
  FDRE found_first_edge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_first_edge_r_i_1_n_0),
        .Q(found_first_edge_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT6 #(
    .INIT(64'hD5D55555C0800000)) 
    found_second_edge_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(found_stable_eye_last_r),
        .I2(found_first_edge_r_reg_n_0),
        .I3(\first_edge_taps_r[5]_i_3_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I5(found_second_edge_r_reg_n_0),
        .O(found_second_edge_r_i_1_n_0));
  FDRE found_second_edge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_second_edge_r_i_1_n_0),
        .Q(found_second_edge_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    found_stable_eye_last_r_i_1
       (.I0(found_stable_eye_r_reg_n_0),
        .I1(detect_edge_done_r),
        .I2(found_stable_eye_last_r),
        .O(found_stable_eye_last_r_i_1_n_0));
  FDRE found_stable_eye_last_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_stable_eye_last_r_i_1_n_0),
        .Q(found_stable_eye_last_r),
        .R(pb_detect_edge_setup));
  LUT3 #(
    .INIT(8'h80)) 
    found_stable_eye_r_i_1
       (.I0(found_stable_eye_r_i_2_n_0),
        .I1(pb_found_stable_eye_r[4]),
        .I2(pb_found_stable_eye_r[5]),
        .O(found_stable_eye_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    found_stable_eye_r_i_2
       (.I0(pb_found_stable_eye_r[6]),
        .I1(pb_found_stable_eye_r[7]),
        .I2(pb_found_stable_eye_r[1]),
        .I3(pb_found_stable_eye_r[0]),
        .I4(pb_found_stable_eye_r[3]),
        .I5(pb_found_stable_eye_r[2]),
        .O(found_stable_eye_r_i_2_n_0));
  FDRE found_stable_eye_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_stable_eye_r_i_1_n_0),
        .Q(found_stable_eye_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4540FFFF45400000)) 
    \gen_byte_sel_div2.byte_sel_cnt[0]_i_2 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(regl_dqs_cnt_r[0]),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I4(wr_level_done_reg),
        .I5(\dqs_count_r_reg[0]_rep ),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ));
  LUT6 #(
    .INIT(64'h4540FFFF45400000)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_2 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(regl_dqs_cnt_r[1]),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I4(wr_level_done_reg),
        .I5(\dqs_count_r_reg[1]_rep ),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ));
  LUT6 #(
    .INIT(64'h3A0A3A3A3A0A0A0A)) 
    \gen_byte_sel_div2.byte_sel_cnt[2]_i_2 
       (.I0(\dqs_count_r_reg[2]_rep__0 ),
        .I1(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I2(wr_level_done_reg),
        .I3(regl_dqs_cnt_r[2]),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I5(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[2] ));
  LUT5 #(
    .INIT(32'h40FF4000)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_5 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I2(regl_dqs_cnt_r[3]),
        .I3(wr_level_done_reg),
        .I4(\dqs_count_r_reg[3] ),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[3] ));
  FDRE \gen_mux_rd[0].mux_rd_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_8 ),
        .Q(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_24 ),
        .Q(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_40 ),
        .Q(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_56 ),
        .Q(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_16 ),
        .Q(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_32 ),
        .Q(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_48 ),
        .Q(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_9 ),
        .Q(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_25 ),
        .Q(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_41 ),
        .Q(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_57 ),
        .Q(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_1 ),
        .Q(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_17 ),
        .Q(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_33 ),
        .Q(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_49 ),
        .Q(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_10 ),
        .Q(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_26 ),
        .Q(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_42 ),
        .Q(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_58 ),
        .Q(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_2 ),
        .Q(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_18 ),
        .Q(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_34 ),
        .Q(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_50 ),
        .Q(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_11 ),
        .Q(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_27 ),
        .Q(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_43 ),
        .Q(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_59 ),
        .Q(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_3 ),
        .Q(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_19 ),
        .Q(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_35 ),
        .Q(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_51 ),
        .Q(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_12 ),
        .Q(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_28 ),
        .Q(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_44 ),
        .Q(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_60 ),
        .Q(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_4 ),
        .Q(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_20 ),
        .Q(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_36 ),
        .Q(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_52 ),
        .Q(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_13 ),
        .Q(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_29 ),
        .Q(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_45 ),
        .Q(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_61 ),
        .Q(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_5 ),
        .Q(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_21 ),
        .Q(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_37 ),
        .Q(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_53 ),
        .Q(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_14 ),
        .Q(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_30 ),
        .Q(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_46 ),
        .Q(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_62 ),
        .Q(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_6 ),
        .Q(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_22 ),
        .Q(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_38 ),
        .Q(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_54 ),
        .Q(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_15 ),
        .Q(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_31 ),
        .Q(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_47 ),
        .Q(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_63 ),
        .Q(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_7 ),
        .Q(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_23 ),
        .Q(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_39 ),
        .Q(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_mux_sel_r_reg[0]_55 ),
        .Q(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_3 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(dqs_found_done_r_reg),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_215 ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r[0][0]_i_1 
       (.I0(store_sr_r_reg_n_0),
        .I1(sr_valid_r_reg_n_0),
        .O(store_sr_r0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_199 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_239 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_207 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_247 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_223 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_231 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_255 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_135 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_151 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_191 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_167 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_183 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_143 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_175 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_159 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_216 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_200 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_240 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_208 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_248 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_224 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_232 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_256 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_136 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_152 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_192 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_168 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_184 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_144 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_176 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_160 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_217 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_201 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_241 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_209 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_249 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_225 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_233 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_257 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_137 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_153 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_193 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_169 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_185 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_145 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_177 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_161 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_218 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_202 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_242 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_210 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_250 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_226 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_234 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_258 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_138 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_154 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_194 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_170 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_186 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_146 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_178 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_162 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_219 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_203 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_243 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_211 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_251 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_227 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_235 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_259 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_139 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_155 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_195 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_171 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_187 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_147 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_179 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_163 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_220 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_204 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_244 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_212 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_252 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_228 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_236 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_260 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_140 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_156 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_196 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_172 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_188 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_148 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_180 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_164 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_221 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_205 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_245 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_213 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_253 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_229 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_237 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_261 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_141 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_157 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_197 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_173 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_189 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_149 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_181 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_165 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_222 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_206 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_246 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_214 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_254 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_230 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_238 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_262 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_142 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_158 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_198 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_174 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_190 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_150 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_182 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_166 ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ),
        .Q(idel_pat0_match_fall0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ),
        .Q(idel_pat0_match_fall1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ),
        .Q(idel_pat0_match_fall3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ),
        .Q(idel_pat0_match_rise0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ),
        .Q(idel_pat0_match_rise1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ),
        .Q(idel_pat0_match_rise2_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ),
        .Q(idel_pat1_match_fall1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ),
        .Q(idel_pat1_match_fall3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ),
        .Q(idel_pat1_match_rise0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ),
        .Q(idel_pat1_match_rise1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ),
        .Q(idel_pat1_match_rise2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ),
        .Q(idel_pat1_match_rise3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ),
        .Q(pat0_match_fall0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ),
        .Q(pat1_match_fall2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ),
        .Q(idel_pat0_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ),
        .Q(idel_pat0_match_fall1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ),
        .Q(idel_pat0_match_fall2_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ),
        .Q(idel_pat0_match_fall3_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ),
        .Q(idel_pat0_match_rise1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ),
        .Q(idel_pat0_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ),
        .Q(idel_pat1_match_fall0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ),
        .Q(idel_pat1_match_fall1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ),
        .Q(idel_pat1_match_fall2_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ),
        .Q(idel_pat1_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ),
        .Q(pat0_match_rise0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ),
        .Q(pat0_match_rise3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ),
        .Q(idel_pat0_match_fall0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ),
        .Q(idel_pat0_match_fall1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ),
        .Q(idel_pat0_match_fall3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ),
        .Q(idel_pat0_match_rise1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ),
        .Q(idel_pat0_match_rise2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ),
        .Q(idel_pat0_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ),
        .Q(idel_pat1_match_fall0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ),
        .Q(idel_pat1_match_fall2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ),
        .Q(idel_pat1_match_rise0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ),
        .Q(idel_pat1_match_rise2_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ),
        .Q(idel_pat1_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ),
        .Q(pat1_match_fall3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ),
        .Q(idel_pat0_match_fall0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ),
        .Q(idel_pat0_match_fall1_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ),
        .Q(idel_pat0_match_fall3_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ),
        .Q(idel_pat0_match_rise1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ),
        .Q(idel_pat0_match_rise2_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ),
        .Q(idel_pat1_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ),
        .Q(idel_pat1_match_fall1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ),
        .Q(idel_pat1_match_fall2_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ),
        .Q(idel_pat1_match_fall3_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ),
        .Q(idel_pat1_match_rise3_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ),
        .Q(pat1_match_rise0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ),
        .Q(idel_pat0_match_fall0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ),
        .Q(idel_pat0_match_fall1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ),
        .Q(idel_pat0_match_fall3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ),
        .Q(idel_pat0_match_rise0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ),
        .Q(idel_pat0_match_rise1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ),
        .Q(idel_pat0_match_rise2_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ),
        .Q(idel_pat1_match_fall1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ),
        .Q(idel_pat1_match_fall3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ),
        .Q(idel_pat1_match_rise0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ),
        .Q(idel_pat1_match_rise1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ),
        .Q(idel_pat1_match_rise2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ),
        .Q(idel_pat1_match_rise3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ),
        .Q(pat0_match_fall0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ),
        .Q(pat1_match_fall2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ),
        .Q(idel_pat0_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ),
        .Q(idel_pat0_match_fall1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ),
        .Q(idel_pat0_match_fall2_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ),
        .Q(idel_pat0_match_fall3_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ),
        .Q(idel_pat0_match_rise1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ),
        .Q(idel_pat0_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ),
        .Q(idel_pat1_match_fall0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ),
        .Q(idel_pat1_match_fall1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ),
        .Q(idel_pat1_match_fall2_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ),
        .Q(idel_pat1_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ),
        .Q(pat0_match_rise0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ),
        .Q(pat0_match_rise3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ),
        .Q(idel_pat0_match_fall0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ),
        .Q(idel_pat0_match_fall1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ),
        .Q(idel_pat0_match_fall3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ),
        .Q(idel_pat0_match_rise1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ),
        .Q(idel_pat0_match_rise2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ),
        .Q(idel_pat0_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ),
        .Q(idel_pat1_match_fall0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ),
        .Q(idel_pat1_match_fall2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ),
        .Q(idel_pat1_match_rise0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ),
        .Q(idel_pat1_match_rise2_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ),
        .Q(idel_pat1_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ),
        .Q(pat1_match_fall3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ),
        .Q(idel_pat0_match_fall0_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ),
        .Q(idel_pat0_match_fall1_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ),
        .Q(idel_pat0_match_fall3_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ),
        .Q(idel_pat0_match_rise1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ),
        .Q(idel_pat0_match_rise2_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ),
        .Q(idel_pat1_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ),
        .Q(idel_pat1_match_fall1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ),
        .Q(idel_pat1_match_fall2_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ),
        .Q(idel_pat1_match_fall3_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ),
        .Q(idel_pat1_match_rise3_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ),
        .Q(pat1_match_rise0_r[7]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat0_data_match_r_i_1 
       (.I0(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ),
        .I1(idel_pat0_match_fall2_and_r),
        .I2(idel_pat0_match_fall3_and_r),
        .O(idel_pat0_data_match_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_data_match_r_i_2 
       (.I0(idel_pat0_match_rise2_and_r),
        .I1(idel_pat0_match_rise0_and_r),
        .I2(idel_pat0_match_rise1_and_r),
        .I3(idel_pat0_match_fall1_and_r),
        .I4(idel_pat0_match_rise3_and_r),
        .I5(idel_pat0_match_fall0_and_r),
        .O(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(idel_pat0_data_match_r0),
        .Q(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_fall0_r[2]),
        .I2(idel_pat0_match_fall0_r[6]),
        .I3(idel_pat0_match_fall0_r[0]),
        .I4(idel_pat0_match_fall0_r[4]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_fall1_r[1]),
        .I2(idel_pat0_match_fall1_r[5]),
        .I3(idel_pat0_match_fall1_r[2]),
        .I4(idel_pat0_match_fall1_r[6]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_fall2_r[2]),
        .I2(idel_pat0_match_fall2_r[5]),
        .I3(idel_pat0_match_fall2_r[6]),
        .I4(idel_pat0_match_fall2_r[1]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2 
       (.I0(idel_pat0_match_fall2_r[3]),
        .I1(idel_pat0_match_fall2_r[7]),
        .I2(idel_pat0_match_fall2_r[4]),
        .I3(idel_pat0_match_fall2_r[0]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_fall3_r[7]),
        .I2(idel_pat0_match_fall3_r[3]),
        .I3(idel_pat0_match_fall3_r[4]),
        .I4(idel_pat0_match_fall3_r[0]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise0_r[3]),
        .I2(idel_pat0_match_rise0_r[7]),
        .I3(idel_pat0_match_rise0_r[2]),
        .I4(idel_pat0_match_rise0_r[6]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise1_r[0]),
        .I2(idel_pat0_match_rise1_r[4]),
        .I3(idel_pat0_match_rise1_r[1]),
        .I4(idel_pat0_match_rise1_r[5]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1 
       (.I0(idel_pat0_match_rise2_r[0]),
        .I1(idel_pat0_match_rise2_r[4]),
        .I2(idel_pat0_match_rise2_r[3]),
        .I3(idel_pat0_match_rise2_r[7]),
        .I4(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2 
       (.I0(idel_pat0_match_rise2_r[5]),
        .I1(idel_pat0_match_rise2_r[1]),
        .I2(idel_pat0_match_rise2_r[6]),
        .I3(idel_pat0_match_rise2_r[2]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise3_r[2]),
        .I2(idel_pat0_match_rise3_r[6]),
        .I3(idel_pat0_match_rise3_r[1]),
        .I4(idel_pat0_match_rise3_r[5]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat1_data_match_r_i_1 
       (.I0(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ),
        .I1(idel_pat1_match_fall3_and_r),
        .I2(idel_pat1_match_rise0_and_r),
        .O(idel_pat1_data_match_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat1_data_match_r_i_2 
       (.I0(idel_pat1_match_rise2_and_r),
        .I1(idel_pat1_match_fall2_and_r),
        .I2(idel_pat1_match_rise1_and_r),
        .I3(idel_pat1_match_fall1_and_r),
        .I4(idel_pat1_match_rise3_and_r),
        .I5(idel_pat1_match_fall0_and_r),
        .O(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(idel_pat1_data_match_r0),
        .Q(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_fall0_r[7]),
        .I2(idel_pat1_match_fall0_r[1]),
        .I3(idel_pat1_match_fall0_r[3]),
        .I4(idel_pat1_match_fall0_r[5]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2 
       (.I0(idel_pat1_match_fall0_r[6]),
        .I1(idel_pat1_match_fall0_r[2]),
        .I2(idel_pat0_match_fall0_r[4]),
        .I3(idel_pat0_match_fall0_r[0]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_fall1_r[4]),
        .I2(idel_pat1_match_fall1_r[3]),
        .I3(idel_pat1_match_fall1_r[0]),
        .I4(idel_pat1_match_fall1_r[7]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2 
       (.I0(idel_pat1_match_fall1_r[5]),
        .I1(idel_pat1_match_fall1_r[1]),
        .I2(idel_pat0_match_fall1_r[6]),
        .I3(idel_pat0_match_fall1_r[2]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_fall2_r[7]),
        .I2(idel_pat1_match_fall2_r[3]),
        .I3(idel_pat0_match_fall2_r[0]),
        .I4(idel_pat0_match_fall2_r[4]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall2_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1 
       (.I0(idel_pat1_match_fall3_r[4]),
        .I1(idel_pat1_match_fall3_r[0]),
        .I2(idel_pat1_match_fall3_r[7]),
        .I3(idel_pat1_match_fall3_r[3]),
        .I4(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_2 
       (.I0(idel_pat0_match_fall3_r[2]),
        .I1(idel_pat0_match_fall3_r[6]),
        .I2(idel_pat0_match_fall3_r[1]),
        .I3(idel_pat0_match_fall3_r[5]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise0_r[0]),
        .I2(idel_pat1_match_rise0_r[4]),
        .I3(idel_pat0_match_rise0_r[1]),
        .I4(idel_pat0_match_rise0_r[5]),
        .O(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise1_r[2]),
        .I2(idel_pat1_match_rise1_r[6]),
        .I3(idel_pat1_match_rise1_r[3]),
        .I4(idel_pat1_match_rise1_r[7]),
        .O(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1 
       (.I0(idel_pat1_match_rise2_r[2]),
        .I1(idel_pat1_match_rise2_r[6]),
        .I2(idel_pat0_match_rise2_r[3]),
        .I3(idel_pat0_match_rise2_r[7]),
        .I4(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise3_r[1]),
        .I2(idel_pat0_match_rise3_r[5]),
        .I3(idel_pat1_match_rise3_r[2]),
        .I4(idel_pat1_match_rise3_r[6]),
        .O(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise3_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_data_match_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ),
        .I1(pat0_match_fall3_and_r),
        .I2(pat0_match_rise0_and_r),
        .O(pat0_data_match_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_data_match_r_i_2 
       (.I0(pat0_match_fall1_and_r),
        .I1(pat0_match_rise2_and_r),
        .I2(pat0_match_rise1_and_r),
        .I3(pat0_match_fall2_and_r),
        .I4(pat0_match_rise3_and_r),
        .I5(pat0_match_fall0_and_r),
        .O(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pat0_data_match_r0),
        .Q(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_fall0_and_r_i_1 
       (.I0(idel_pat0_match_fall0_r[2]),
        .I1(idel_pat1_match_fall0_r[3]),
        .I2(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_fall0_and_r_i_2 
       (.I0(idel_pat0_match_fall0_r[6]),
        .I1(pat0_match_fall0_r[0]),
        .I2(idel_pat0_match_fall0_r[1]),
        .I3(idel_pat0_match_fall0_r[5]),
        .I4(idel_pat1_match_fall0_r[7]),
        .I5(pat0_match_fall0_r[4]),
        .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ),
        .Q(pat0_match_fall0_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_fall1_and_r_i_1 
       (.I0(pat0_match_fall1_r[2]),
        .I1(idel_pat1_match_fall1_r[0]),
        .I2(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_fall1_and_r_i_2 
       (.I0(idel_pat1_match_fall1_r[4]),
        .I1(idel_pat0_match_fall1_r[1]),
        .I2(idel_pat0_match_fall1_r[3]),
        .I3(idel_pat0_match_fall1_r[7]),
        .I4(pat0_match_fall1_r[6]),
        .I5(idel_pat0_match_fall1_r[5]),
        .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ),
        .Q(pat0_match_fall1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_fall2_and_r_i_1 
       (.I0(idel_pat0_match_fall2_r[0]),
        .I1(idel_pat0_match_fall2_r[4]),
        .I2(idel_pat0_match_fall2_r[7]),
        .I3(idel_pat0_match_fall2_r[3]),
        .I4(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_fall2_and_r_i_2 
       (.I0(idel_pat1_match_fall2_r[2]),
        .I1(idel_pat1_match_fall2_r[5]),
        .I2(idel_pat1_match_fall2_r[6]),
        .I3(idel_pat1_match_fall2_r[1]),
        .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ),
        .Q(pat0_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat0_match_fall3_and_r_i_1 
       (.I0(idel_pat0_match_fall3_r[4]),
        .I1(idel_pat0_match_fall3_r[0]),
        .I2(idel_pat1_match_fall3_r[7]),
        .I3(idel_pat1_match_fall3_r[3]),
        .I4(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat0_match_fall3_and_r_i_2 
       (.I0(pat0_match_fall3_r[1]),
        .I1(pat0_match_fall3_r[5]),
        .I2(idel_pat0_match_fall3_r[2]),
        .I3(idel_pat0_match_fall3_r[6]),
        .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ),
        .Q(pat0_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),
        .I1(pat0_match_rise0_r[1]),
        .I2(pat0_match_rise0_r[5]),
        .I3(idel_pat0_match_rise0_r[0]),
        .I4(idel_pat0_match_rise0_r[4]),
        .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise0_and_r_i_2 
       (.I0(idel_pat1_match_rise0_r[6]),
        .I1(idel_pat1_match_rise0_r[2]),
        .I2(idel_pat0_match_rise0_r[7]),
        .I3(idel_pat0_match_rise0_r[3]),
        .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ),
        .Q(pat0_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),
        .I1(pat0_match_rise1_r[1]),
        .I2(pat0_match_rise1_r[5]),
        .I3(idel_pat0_match_rise1_r[0]),
        .I4(idel_pat0_match_rise1_r[4]),
        .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise1_and_r_i_2 
       (.I0(idel_pat0_match_rise1_r[6]),
        .I1(idel_pat0_match_rise1_r[2]),
        .I2(idel_pat0_match_rise1_r[7]),
        .I3(idel_pat0_match_rise1_r[3]),
        .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ),
        .Q(pat0_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat0_match_rise2_and_r_i_1 
       (.I0(pat0_match_rise2_r[3]),
        .I1(pat0_match_rise2_r[7]),
        .I2(idel_pat0_match_rise2_r[2]),
        .I3(idel_pat0_match_rise2_r[6]),
        .I4(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat0_match_rise2_and_r_i_2 
       (.I0(idel_pat1_match_rise2_r[4]),
        .I1(idel_pat1_match_rise2_r[0]),
        .I2(idel_pat1_match_rise2_r[5]),
        .I3(idel_pat1_match_rise2_r[1]),
        .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ),
        .Q(pat0_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise3_and_r_i_1 
       (.I0(idel_pat1_match_rise3_r[2]),
        .I1(idel_pat1_match_rise3_r[6]),
        .I2(pat0_match_rise3_r[1]),
        .I3(pat0_match_rise3_r[5]),
        .I4(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise3_and_r_i_2 
       (.I0(idel_pat1_match_rise3_r[4]),
        .I1(idel_pat1_match_rise3_r[3]),
        .I2(idel_pat1_match_rise3_r[0]),
        .I3(idel_pat1_match_rise3_r[7]),
        .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ),
        .Q(pat0_match_rise3_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_data_match_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ),
        .I1(pat1_match_fall3_and_r),
        .I2(pat1_match_rise0_and_r),
        .O(pat1_data_match_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_data_match_r_i_2 
       (.I0(pat1_match_fall1_and_r),
        .I1(pat1_match_rise2_and_r),
        .I2(pat1_match_fall0_and_r),
        .I3(pat1_match_rise1_and_r),
        .I4(pat1_match_rise3_and_r),
        .I5(pat1_match_fall2_and_r),
        .O(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pat1_data_match_r0),
        .Q(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_fall0_and_r_i_1 
       (.I0(idel_pat0_match_fall0_r[0]),
        .I1(idel_pat0_match_fall0_r[4]),
        .I2(idel_pat1_match_fall0_r[2]),
        .I3(idel_pat1_match_fall0_r[6]),
        .I4(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_fall0_and_r_i_2 
       (.I0(idel_pat0_match_fall0_r[7]),
        .I1(idel_pat0_match_fall0_r[1]),
        .I2(idel_pat0_match_fall0_r[3]),
        .I3(idel_pat0_match_fall0_r[5]),
        .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ),
        .Q(pat1_match_fall0_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_fall1_and_r_i_1 
       (.I0(idel_pat0_match_fall1_r[2]),
        .I1(idel_pat0_match_fall1_r[6]),
        .I2(idel_pat1_match_fall1_r[1]),
        .I3(idel_pat1_match_fall1_r[5]),
        .I4(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_fall1_and_r_i_2 
       (.I0(idel_pat0_match_fall1_r[4]),
        .I1(idel_pat0_match_fall1_r[3]),
        .I2(idel_pat0_match_fall1_r[0]),
        .I3(idel_pat0_match_fall1_r[7]),
        .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ),
        .Q(pat1_match_fall1_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_fall2_and_r_i_1 
       (.I0(idel_pat1_match_fall2_r[5]),
        .I1(pat1_match_fall2_r[4]),
        .I2(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_fall2_and_r_i_2 
       (.I0(idel_pat0_match_fall2_r[6]),
        .I1(idel_pat1_match_fall2_r[7]),
        .I2(idel_pat0_match_fall2_r[2]),
        .I3(idel_pat1_match_fall2_r[3]),
        .I4(pat1_match_fall2_r[0]),
        .I5(idel_pat1_match_fall2_r[1]),
        .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ),
        .Q(pat1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ),
        .I1(pat1_match_fall3_r[6]),
        .I2(pat1_match_fall3_r[2]),
        .I3(pat0_match_fall3_r[5]),
        .I4(pat0_match_fall3_r[1]),
        .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_fall3_and_r_i_2 
       (.I0(idel_pat1_match_fall3_r[3]),
        .I1(idel_pat1_match_fall3_r[7]),
        .I2(idel_pat1_match_fall3_r[0]),
        .I3(idel_pat1_match_fall3_r[4]),
        .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ),
        .Q(pat1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),
        .I1(pat1_match_rise0_r[3]),
        .I2(pat1_match_rise0_r[7]),
        .I3(idel_pat0_match_rise0_r[2]),
        .I4(idel_pat0_match_rise0_r[6]),
        .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise0_and_r_i_2 
       (.I0(idel_pat0_match_rise0_r[4]),
        .I1(idel_pat0_match_rise0_r[0]),
        .I2(idel_pat0_match_rise0_r[5]),
        .I3(idel_pat0_match_rise0_r[1]),
        .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ),
        .Q(pat1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise1_r[2]),
        .I2(idel_pat0_match_rise1_r[6]),
        .I3(idel_pat1_match_rise1_r[3]),
        .I4(idel_pat1_match_rise1_r[7]),
        .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise1_and_r_i_2 
       (.I0(idel_pat1_match_rise1_r[4]),
        .I1(idel_pat1_match_rise1_r[0]),
        .I2(idel_pat0_match_rise1_r[5]),
        .I3(idel_pat0_match_rise1_r[1]),
        .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ),
        .Q(pat1_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise2_r[0]),
        .I2(idel_pat1_match_rise2_r[4]),
        .I3(idel_pat0_match_rise2_r[1]),
        .I4(idel_pat0_match_rise2_r[5]),
        .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise2_and_r_i_2 
       (.I0(idel_pat0_match_rise2_r[7]),
        .I1(idel_pat0_match_rise2_r[3]),
        .I2(idel_pat1_match_rise2_r[6]),
        .I3(idel_pat1_match_rise2_r[2]),
        .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ),
        .Q(pat1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise3_and_r_i_1 
       (.I0(idel_pat1_match_rise3_r[2]),
        .I1(idel_pat1_match_rise3_r[6]),
        .I2(pat0_match_rise3_r[1]),
        .I3(pat0_match_rise3_r[5]),
        .I4(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise3_and_r_i_2 
       (.I0(idel_pat0_match_rise3_r[0]),
        .I1(idel_pat0_match_rise3_r[3]),
        .I2(idel_pat0_match_rise3_r[4]),
        .I3(idel_pat0_match_rise3_r[7]),
        .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ),
        .Q(pat1_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0] 
       (.C(CLK),
        .CE(rd_active_r),
        .D(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),
        .O(p_493_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),
        .I5(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_493_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_215 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ),
        .O(p_536_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_536_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_199 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ),
        .O(p_532_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_532_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_239 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ),
        .O(p_526_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_526_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_207 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ),
        .O(p_524_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_524_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_247 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ),
        .O(p_530_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_530_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_223 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ),
        .O(p_528_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_528_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_231 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ),
        .O(p_522_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_522_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_255 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ),
        .O(p_520_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_520_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1 
       (.I0(sr_valid_r2),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),
        .O(p_518_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),
        .I5(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_518_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_111 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_135 ),
        .O(p_509_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_509_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_95 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_151 ),
        .O(p_507_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_507_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_119 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_191 ),
        .O(p_501_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_501_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_79 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_167 ),
        .O(p_499_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_499_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_71 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_183 ),
        .O(p_505_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_505_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_103 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_143 ),
        .O(p_503_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_503_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_87 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_175 ),
        .O(p_497_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_497_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_127 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_159 ),
        .O(p_495_out));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_495_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .Q(p_1_in17_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ),
        .I1(p_0_in435_in),
        .I2(p_3_in437_in),
        .O(p_443_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2 
       (.I0(p_4_in438_in),
        .I1(p_2_in436_in),
        .I2(p_7_in441_in),
        .I3(p_5_in439_in),
        .I4(p_6_in440_in),
        .I5(p_1_in442_in),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_443_out),
        .Q(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_216 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ),
        .O(p_484_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_484_out),
        .Q(p_0_in435_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_200 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ),
        .O(p_482_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_482_out),
        .Q(p_3_in437_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_240 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ),
        .O(p_476_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_476_out),
        .Q(p_5_in439_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_208 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ),
        .O(p_474_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_474_out),
        .Q(p_7_in441_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_248 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ),
        .O(p_480_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_480_out),
        .Q(p_1_in442_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_224 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ),
        .O(p_478_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_478_out),
        .Q(p_2_in436_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_232 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ),
        .O(p_472_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_472_out),
        .Q(p_4_in438_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_256 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ),
        .O(p_470_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_470_out),
        .Q(p_6_in440_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .Q(p_0_in106_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ),
        .I1(p_0_in460_in),
        .I2(p_3_in462_in),
        .O(p_468_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2 
       (.I0(p_4_in463_in),
        .I1(p_2_in461_in),
        .I2(p_6_in465_in),
        .I3(p_5_in464_in),
        .I4(p_7_in466_in),
        .I5(p_1_in467_in),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_468_out),
        .Q(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_112 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_136 ),
        .O(p_459_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_459_out),
        .Q(p_0_in460_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_96 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_152 ),
        .O(p_457_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_457_out),
        .Q(p_3_in462_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_120 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_192 ),
        .O(p_451_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_451_out),
        .Q(p_5_in464_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_80 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_168 ),
        .O(p_449_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_449_out),
        .Q(p_7_in466_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_72 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_184 ),
        .O(p_455_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_455_out),
        .Q(p_1_in467_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_104 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_144 ),
        .O(p_453_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_453_out),
        .Q(p_2_in461_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_88 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_176 ),
        .O(p_447_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_447_out),
        .Q(p_4_in463_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_128 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_160 ),
        .O(p_445_out));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_445_out),
        .Q(p_6_in465_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .Q(p_1_in14_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ),
        .I1(p_2_in386_in),
        .I2(p_1_in392_in),
        .O(p_393_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2 
       (.I0(p_3_in387_in),
        .I1(p_5_in389_in),
        .I2(p_6_in390_in),
        .I3(p_4_in388_in),
        .I4(p_0_in385_in),
        .I5(p_7_in391_in),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_393_out),
        .Q(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_217 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ),
        .O(p_434_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_434_out),
        .Q(p_0_in385_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_201 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ),
        .O(p_432_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_432_out),
        .Q(p_3_in387_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_241 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ),
        .O(p_426_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_426_out),
        .Q(p_5_in389_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_209 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ),
        .O(p_424_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_424_out),
        .Q(p_7_in391_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_249 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ),
        .O(p_430_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_430_out),
        .Q(p_1_in392_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_225 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ),
        .O(p_428_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_428_out),
        .Q(p_2_in386_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_233 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ),
        .O(p_422_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_422_out),
        .Q(p_4_in388_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_257 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ),
        .O(p_420_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_420_out),
        .Q(p_6_in390_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .Q(p_0_in103_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ),
        .I1(p_0_in410_in),
        .I2(p_3_in412_in),
        .O(p_418_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2 
       (.I0(p_4_in413_in),
        .I1(p_2_in411_in),
        .I2(p_7_in416_in),
        .I3(p_5_in414_in),
        .I4(p_6_in415_in),
        .I5(p_1_in417_in),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_418_out),
        .Q(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_113 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_137 ),
        .O(p_409_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_409_out),
        .Q(p_0_in410_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_97 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_153 ),
        .O(p_407_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_407_out),
        .Q(p_3_in412_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_121 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_193 ),
        .O(p_401_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_401_out),
        .Q(p_5_in414_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_81 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_169 ),
        .O(p_399_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_399_out),
        .Q(p_7_in416_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_73 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_185 ),
        .O(p_405_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_405_out),
        .Q(p_1_in417_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_105 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_145 ),
        .O(p_403_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_403_out),
        .Q(p_2_in411_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_89 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_177 ),
        .O(p_397_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_397_out),
        .Q(p_4_in413_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_129 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_161 ),
        .O(p_395_out));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_395_out),
        .Q(p_6_in415_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .Q(p_1_in11_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ),
        .I1(p_2_in336_in),
        .I2(p_0_in335_in),
        .O(p_343_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2 
       (.I0(p_5_in339_in),
        .I1(p_4_in338_in),
        .I2(p_7_in341_in),
        .I3(p_6_in340_in),
        .I4(p_3_in337_in),
        .I5(p_1_in342_in),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_343_out),
        .Q(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_218 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ),
        .O(p_384_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_384_out),
        .Q(p_0_in335_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_202 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ),
        .O(p_382_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_382_out),
        .Q(p_3_in337_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_242 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ),
        .O(p_376_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_376_out),
        .Q(p_5_in339_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_210 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ),
        .O(p_374_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_374_out),
        .Q(p_7_in341_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_250 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ),
        .O(p_380_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_380_out),
        .Q(p_1_in342_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_226 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ),
        .O(p_378_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_378_out),
        .Q(p_2_in336_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_234 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ),
        .O(p_372_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_372_out),
        .Q(p_4_in338_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_258 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ),
        .O(p_370_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_370_out),
        .Q(p_6_in340_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .Q(p_0_in100_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ),
        .I1(p_3_in362_in),
        .I2(p_0_in360_in),
        .O(p_368_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2 
       (.I0(p_5_in364_in),
        .I1(p_4_in363_in),
        .I2(p_7_in366_in),
        .I3(p_6_in365_in),
        .I4(p_2_in361_in),
        .I5(p_1_in367_in),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_368_out),
        .Q(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_114 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_138 ),
        .O(p_359_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_359_out),
        .Q(p_0_in360_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_98 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_154 ),
        .O(p_357_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_357_out),
        .Q(p_3_in362_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_122 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_194 ),
        .O(p_351_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_351_out),
        .Q(p_5_in364_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_82 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_170 ),
        .O(p_349_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_349_out),
        .Q(p_7_in366_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_74 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_186 ),
        .O(p_355_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_355_out),
        .Q(p_1_in367_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_106 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_146 ),
        .O(p_353_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_353_out),
        .Q(p_2_in361_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_90 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_178 ),
        .O(p_347_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_347_out),
        .Q(p_4_in363_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_130 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_162 ),
        .O(p_345_out));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_345_out),
        .Q(p_6_in365_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .Q(p_1_in8_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ),
        .I1(p_3_in287_in),
        .I2(p_2_in286_in),
        .O(p_293_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2 
       (.I0(p_5_in289_in),
        .I1(p_4_in288_in),
        .I2(p_7_in291_in),
        .I3(p_6_in290_in),
        .I4(p_0_in285_in),
        .I5(p_1_in292_in),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_293_out),
        .Q(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_219 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ),
        .O(p_334_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_334_out),
        .Q(p_0_in285_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_203 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ),
        .O(p_332_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_332_out),
        .Q(p_3_in287_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_243 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ),
        .O(p_326_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_326_out),
        .Q(p_5_in289_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_211 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ),
        .O(p_324_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_324_out),
        .Q(p_7_in291_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_251 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ),
        .O(p_330_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_330_out),
        .Q(p_1_in292_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_227 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ),
        .O(p_328_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_328_out),
        .Q(p_2_in286_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_235 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ),
        .O(p_322_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_322_out),
        .Q(p_4_in288_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_259 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ),
        .O(p_320_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_320_out),
        .Q(p_6_in290_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .Q(p_0_in97_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ),
        .I1(p_3_in312_in),
        .I2(p_2_in311_in),
        .O(p_318_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2 
       (.I0(p_5_in314_in),
        .I1(p_4_in313_in),
        .I2(p_7_in316_in),
        .I3(p_6_in315_in),
        .I4(p_0_in310_in),
        .I5(p_1_in317_in),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_318_out),
        .Q(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_115 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_139 ),
        .O(p_309_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_309_out),
        .Q(p_0_in310_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_99 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_155 ),
        .O(p_307_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_307_out),
        .Q(p_3_in312_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_123 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_195 ),
        .O(p_301_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_301_out),
        .Q(p_5_in314_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_83 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_171 ),
        .O(p_299_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_299_out),
        .Q(p_7_in316_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_75 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_187 ),
        .O(p_305_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_305_out),
        .Q(p_1_in317_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_107 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_147 ),
        .O(p_303_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_303_out),
        .Q(p_2_in311_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_91 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_179 ),
        .O(p_297_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_297_out),
        .Q(p_4_in313_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_131 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_163 ),
        .O(p_295_out));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_295_out),
        .Q(p_6_in315_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .Q(p_1_in5_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ),
        .I1(p_3_in237_in),
        .I2(p_2_in236_in),
        .O(p_243_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2 
       (.I0(p_5_in239_in),
        .I1(p_4_in238_in),
        .I2(p_7_in241_in),
        .I3(p_6_in240_in),
        .I4(p_0_in235_in),
        .I5(p_1_in242_in),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_243_out),
        .Q(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_220 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ),
        .O(p_284_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_284_out),
        .Q(p_0_in235_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_204 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ),
        .O(p_282_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_282_out),
        .Q(p_3_in237_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_244 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ),
        .O(p_276_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_276_out),
        .Q(p_5_in239_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_212 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ),
        .O(p_274_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_274_out),
        .Q(p_7_in241_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_252 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ),
        .O(p_280_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_280_out),
        .Q(p_1_in242_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_228 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ),
        .O(p_278_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_278_out),
        .Q(p_2_in236_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_236 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ),
        .O(p_272_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_272_out),
        .Q(p_4_in238_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_260 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ),
        .O(p_270_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_270_out),
        .Q(p_6_in240_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .Q(p_0_in94_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ),
        .I1(p_3_in262_in),
        .I2(p_2_in261_in),
        .O(p_268_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2 
       (.I0(p_5_in264_in),
        .I1(p_4_in263_in),
        .I2(p_7_in266_in),
        .I3(p_6_in265_in),
        .I4(p_0_in260_in),
        .I5(p_1_in267_in),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_268_out),
        .Q(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_116 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_140 ),
        .O(p_259_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_259_out),
        .Q(p_0_in260_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_100 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_156 ),
        .O(p_257_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_257_out),
        .Q(p_3_in262_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_124 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_196 ),
        .O(p_251_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_251_out),
        .Q(p_5_in264_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_84 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_172 ),
        .O(p_249_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_249_out),
        .Q(p_7_in266_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_76 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_188 ),
        .O(p_255_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_255_out),
        .Q(p_1_in267_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_108 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_148 ),
        .O(p_253_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_253_out),
        .Q(p_2_in261_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_92 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_180 ),
        .O(p_247_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_247_out),
        .Q(p_4_in263_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_132 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_164 ),
        .O(p_245_out));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_245_out),
        .Q(p_6_in265_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .Q(p_1_in2_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ),
        .I1(p_3_in187_in),
        .I2(p_2_in186_in),
        .O(p_193_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2 
       (.I0(p_5_in189_in),
        .I1(p_4_in188_in),
        .I2(p_7_in191_in),
        .I3(p_6_in190_in),
        .I4(p_0_in185_in),
        .I5(p_1_in192_in),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_193_out),
        .Q(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_221 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ),
        .O(p_234_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_234_out),
        .Q(p_0_in185_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_205 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ),
        .O(p_232_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_232_out),
        .Q(p_3_in187_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_245 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ),
        .O(p_226_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_226_out),
        .Q(p_5_in189_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_213 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ),
        .O(p_224_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_224_out),
        .Q(p_7_in191_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_253 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ),
        .O(p_230_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_230_out),
        .Q(p_1_in192_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_229 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ),
        .O(p_228_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_228_out),
        .Q(p_2_in186_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_237 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ),
        .O(p_222_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_222_out),
        .Q(p_4_in188_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_261 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ),
        .O(p_220_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_220_out),
        .Q(p_6_in190_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .Q(p_0_in91_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ),
        .I1(p_3_in212_in),
        .I2(p_2_in211_in),
        .O(p_218_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2 
       (.I0(p_5_in214_in),
        .I1(p_4_in213_in),
        .I2(p_7_in216_in),
        .I3(p_6_in215_in),
        .I4(p_0_in210_in),
        .I5(p_1_in217_in),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_218_out),
        .Q(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_117 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_141 ),
        .O(p_209_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_209_out),
        .Q(p_0_in210_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_101 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_157 ),
        .O(p_207_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_207_out),
        .Q(p_3_in212_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_125 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_197 ),
        .O(p_201_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_201_out),
        .Q(p_5_in214_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_85 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_173 ),
        .O(p_199_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_199_out),
        .Q(p_7_in216_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_77 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_189 ),
        .O(p_205_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_205_out),
        .Q(p_1_in217_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_109 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_149 ),
        .O(p_203_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_203_out),
        .Q(p_2_in211_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_93 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_181 ),
        .O(p_197_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_197_out),
        .Q(p_4_in213_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_133 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_165 ),
        .O(p_195_out));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_195_out),
        .Q(p_6_in215_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ),
        .I1(p_3_in139_in),
        .I2(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),
        .O(p_143_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7] ),
        .I1(p_4_in140_in),
        .I2(p_7_in141_in),
        .I3(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),
        .I4(p_0_in138_in),
        .I5(p_1_in142_in),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_143_out),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_222 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ),
        .O(p_184_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_184_out),
        .Q(p_0_in138_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_206 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ),
        .O(p_182_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_182_out),
        .Q(p_3_in139_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_246 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ),
        .O(p_176_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_176_out),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_214 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ),
        .O(p_174_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_174_out),
        .Q(p_7_in141_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_254 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ),
        .O(p_180_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_180_out),
        .Q(p_1_in142_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_230 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ),
        .O(p_178_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_178_out),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_238 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ),
        .O(p_172_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_172_out),
        .Q(p_4_in140_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_262 ),
        .I3(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ),
        .O(p_170_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_170_out),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ),
        .I1(p_3_in162_in),
        .I2(p_2_in161_in),
        .O(p_168_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2 
       (.I0(p_5_in164_in),
        .I1(p_4_in163_in),
        .I2(p_7_in166_in),
        .I3(p_6_in165_in),
        .I4(p_0_in160_in),
        .I5(p_1_in167_in),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(p_168_out),
        .Q(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_118 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_142 ),
        .O(p_159_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_159_out),
        .Q(p_0_in160_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_102 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_158 ),
        .O(p_157_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_157_out),
        .Q(p_3_in162_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_126 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_198 ),
        .O(p_151_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_151_out),
        .Q(p_5_in164_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_86 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_174 ),
        .O(p_149_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_149_out),
        .Q(p_7_in166_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_78 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_190 ),
        .O(p_155_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_155_out),
        .Q(p_1_in167_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_110 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_150 ),
        .O(p_153_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_153_out),
        .Q(p_2_in161_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_94 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_182 ),
        .O(p_147_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_147_out),
        .Q(p_4_in163_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_134 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_166 ),
        .O(p_145_out));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_145_out),
        .Q(p_6_in165_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),
        .O(p_0_in__2[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .I5(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),
        .O(p_0_in__2[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4 
       (.I0(pb_detect_edge_done_r[0]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[0]),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2_n_0 ),
        .D(p_0_in__2[0]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2_n_0 ),
        .D(p_0_in__2[1]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2_n_0 ),
        .D(p_0_in__2[2]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2_n_0 ),
        .D(p_0_in__2[3]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2_n_0 ),
        .D(p_0_in__2[4]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(pb_detect_edge_done_r[0]),
        .O(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[0]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[0].pb_found_edge_r[0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),
        .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I4(pb_detect_edge_done_r[0]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gen_track_left_edge[0].pb_found_edge_r[0]_i_2 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ));
  FDRE \gen_track_left_edge[0].pb_found_edge_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ),
        .Q(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1 
       (.I0(pb_found_stable_eye_r79_out),
        .I1(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[0]),
        .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .O(pb_found_stable_eye_r79_out));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),
        .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .I5(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0 ));
  FDRE \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[0]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[0]),
        .O(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .O(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .O(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ));
  FDRE \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ),
        .Q(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),
        .O(p_0_in__3[2]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),
        .O(p_0_in__3[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1 
       (.I0(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in16_in),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .I5(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),
        .O(p_0_in__3[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4 
       (.I0(pb_detect_edge_done_r[1]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5 
       (.I0(p_0_in106_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in16_in),
        .I3(p_1_in17_in),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[1]),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[0]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[1]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[2]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[3]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[4]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in106_in),
        .I3(pb_detect_edge_done_r[1]),
        .O(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[1]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[1].pb_found_edge_r[1]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),
        .I1(p_0_in16_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I4(pb_detect_edge_done_r[1]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_found_edge_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ),
        .Q(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1 
       (.I0(pb_found_stable_eye_r75_out),
        .I1(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0 ),
        .I2(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[1]),
        .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(p_0_in16_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .O(pb_found_stable_eye_r75_out));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),
        .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(p_0_in106_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in16_in),
        .I4(p_1_in17_in),
        .I5(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4_n_0 ));
  FDRE \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1 
       (.I0(p_0_in16_in),
        .I1(p_0_in106_in),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[1]),
        .O(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ),
        .Q(p_0_in16_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .O(p_0_in__4[0]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .O(p_0_in__4[1]));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),
        .O(p_0_in__4[2]));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),
        .O(p_0_in__4[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1 
       (.I0(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in13_in),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .I5(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),
        .O(p_0_in__4[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4 
       (.I0(pb_detect_edge_done_r[2]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5 
       (.I0(p_0_in103_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in13_in),
        .I3(p_1_in14_in),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[2]),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[0]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[1]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[2]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[3]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[4]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in103_in),
        .I3(pb_detect_edge_done_r[2]),
        .O(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[2]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[2].pb_found_edge_r[2]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),
        .I1(p_0_in13_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I4(pb_detect_edge_done_r[2]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_found_edge_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ),
        .Q(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1 
       (.I0(pb_found_stable_eye_r71_out),
        .I1(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0 ),
        .I2(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[2]),
        .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(p_0_in13_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .O(pb_found_stable_eye_r71_out));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),
        .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(p_0_in103_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in13_in),
        .I4(p_1_in14_in),
        .I5(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4_n_0 ));
  FDRE \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1 
       (.I0(p_0_in13_in),
        .I1(p_0_in103_in),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[2]),
        .O(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ),
        .Q(p_0_in13_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .O(p_0_in__5[0]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .O(p_0_in__5[1]));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),
        .O(p_0_in__5[2]));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),
        .O(p_0_in__5[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1 
       (.I0(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in10_in),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .I5(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),
        .O(p_0_in__5[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4 
       (.I0(pb_detect_edge_done_r[3]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5 
       (.I0(p_0_in100_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in10_in),
        .I3(p_1_in11_in),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[3]),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[0]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[1]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[2]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[3]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[4]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in100_in),
        .I3(pb_detect_edge_done_r[3]),
        .O(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[3]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[3].pb_found_edge_r[3]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),
        .I1(p_0_in10_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I4(pb_detect_edge_done_r[3]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_found_edge_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ),
        .Q(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1 
       (.I0(pb_found_stable_eye_r67_out),
        .I1(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0 ),
        .I2(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[3]),
        .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(p_0_in10_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .O(pb_found_stable_eye_r67_out));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),
        .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(p_0_in100_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in10_in),
        .I4(p_1_in11_in),
        .I5(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4_n_0 ));
  FDRE \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1 
       (.I0(p_0_in10_in),
        .I1(p_0_in100_in),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[3]),
        .O(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ),
        .Q(p_0_in10_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .O(p_0_in__6[0]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .O(p_0_in__6[1]));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),
        .O(p_0_in__6[2]));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),
        .O(p_0_in__6[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1 
       (.I0(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in7_in),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .I5(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),
        .O(p_0_in__6[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4 
       (.I0(pb_detect_edge_done_r[4]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5 
       (.I0(p_0_in97_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[4]),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[0]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[1]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[2]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[3]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[4]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in97_in),
        .I3(pb_detect_edge_done_r[4]),
        .O(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[4]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[4].pb_found_edge_r[4]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),
        .I1(p_0_in7_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I4(pb_detect_edge_done_r[4]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_found_edge_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ),
        .Q(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1 
       (.I0(pb_found_stable_eye_r63_out),
        .I1(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0 ),
        .I2(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[4]),
        .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(p_0_in7_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .O(pb_found_stable_eye_r63_out));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),
        .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(p_0_in97_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4_n_0 ));
  FDRE \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[4]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1 
       (.I0(p_0_in7_in),
        .I1(p_0_in97_in),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[4]),
        .O(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ),
        .Q(p_0_in7_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .O(p_0_in__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .O(p_0_in__7[1]));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),
        .O(p_0_in__7[2]));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),
        .O(p_0_in__7[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1 
       (.I0(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in4_in),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .I5(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),
        .O(p_0_in__7[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4 
       (.I0(pb_detect_edge_done_r[5]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5 
       (.I0(p_0_in94_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in4_in),
        .I3(p_1_in5_in),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[5]),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[0]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[1]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[2]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[3]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[4]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in94_in),
        .I3(pb_detect_edge_done_r[5]),
        .O(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[5]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[5].pb_found_edge_r[5]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),
        .I1(p_0_in4_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I4(pb_detect_edge_done_r[5]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_found_edge_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ),
        .Q(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1 
       (.I0(pb_found_stable_eye_r59_out),
        .I1(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0 ),
        .I2(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[5]),
        .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(p_0_in4_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .O(pb_found_stable_eye_r59_out));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),
        .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(p_0_in94_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in4_in),
        .I4(p_1_in5_in),
        .I5(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4_n_0 ));
  FDRE \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[5]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1 
       (.I0(p_0_in4_in),
        .I1(p_0_in94_in),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[5]),
        .O(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ),
        .Q(p_0_in4_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .O(p_0_in__8[0]));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .O(p_0_in__8[1]));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),
        .O(p_0_in__8[2]));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),
        .O(p_0_in__8[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1 
       (.I0(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in1_in),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .I5(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),
        .O(p_0_in__8[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4 
       (.I0(pb_detect_edge_done_r[6]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5 
       (.I0(p_0_in91_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in1_in),
        .I3(p_1_in2_in),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[6]),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[0]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[1]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[2]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[3]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[4]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in91_in),
        .I3(pb_detect_edge_done_r[6]),
        .O(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[6]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[6].pb_found_edge_r[6]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),
        .I1(p_0_in1_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I4(pb_detect_edge_done_r[6]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_found_edge_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ),
        .Q(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1 
       (.I0(pb_found_stable_eye_r55_out),
        .I1(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0 ),
        .I2(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[6]),
        .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(p_0_in1_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .O(pb_found_stable_eye_r55_out));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),
        .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(p_0_in91_in),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in1_in),
        .I4(p_1_in2_in),
        .I5(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4_n_0 ));
  FDRE \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[6]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1 
       (.I0(p_0_in1_in),
        .I1(p_0_in91_in),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[6]),
        .O(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ),
        .Q(p_0_in1_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .O(p_0_in__9[0]));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .O(p_0_in__9[1]));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),
        .O(p_0_in__9[2]));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),
        .O(p_0_in__9[3]));
  LUT6 #(
    .INIT(64'h0000FB00FFFFFFFF)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1 
       (.I0(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),
        .I5(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_6_n_0 ),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .I5(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),
        .O(p_0_in__9[4]));
  LUT5 #(
    .INIT(32'h55555554)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4 
       (.I0(pb_detect_edge_done_r[7]),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5 
       (.I0(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ),
        .I3(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_6 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I5(pb_detect_edge_done_r[7]),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_6_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[0]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[1]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[2]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[3]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[4]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .O(pb_detect_edge_setup));
  LUT4 #(
    .INIT(16'h5554)) 
    \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I3(pb_detect_edge_done_r[7]),
        .O(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ));
  FDRE \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ),
        .Q(pb_detect_edge_done_r[7]),
        .R(pb_detect_edge_setup));
  LUT6 #(
    .INIT(64'hFF00FF4500000000)) 
    \gen_track_left_edge[7].pb_found_edge_r[7]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),
        .I1(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I4(pb_detect_edge_done_r[7]),
        .I5(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .O(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_found_edge_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ),
        .Q(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFA08)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1 
       (.I0(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0 ),
        .I1(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0 ),
        .I2(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4_n_0 ),
        .I3(pb_found_stable_eye_r[7]),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[6] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000002AAAAAAAA)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4 
       (.I0(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I1(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ),
        .I4(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),
        .I5(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4_n_0 ));
  FDRE \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[7]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA0A0A0A0A0A000E0)) 
    \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1 
       (.I0(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ),
        .I1(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2_n_0 ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_3_n_0 ),
        .I5(pb_detect_edge_done_r[7]),
        .O(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ),
        .Q(\gen_track_left_edge[7].pb_last_tap_jitter_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF00DFDF20000000)) 
    idel_adj_inc_i_1
       (.I0(detect_edge_done_r),
        .I1(idel_adj_inc_i_2_n_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I3(cal1_wait_r),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I5(idel_adj_inc_reg_n_0),
        .O(idel_adj_inc_i_1_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    idel_adj_inc_i_2
       (.I0(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .O(idel_adj_inc_i_2_n_0));
  FDRE idel_adj_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idel_adj_inc_i_1_n_0),
        .Q(idel_adj_inc_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT4 #(
    .INIT(16'h4F44)) 
    \idel_dec_cnt[0]_i_1 
       (.I0(\idel_dec_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I2(\idel_dec_cnt_reg[0]_i_2_n_0 ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .O(idel_dec_cnt[0]));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \idel_dec_cnt[0]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][6][0] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][4][0] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .O(\idel_dec_cnt[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \idel_dec_cnt[0]_i_4 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][0] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][0] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .O(\idel_dec_cnt[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h90FF9090)) 
    \idel_dec_cnt[1]_i_1 
       (.I0(\idel_dec_cnt_reg_n_0_[1] ),
        .I1(\idel_dec_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I3(\idel_dec_cnt_reg[1]_i_2_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .O(idel_dec_cnt[1]));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \idel_dec_cnt[1]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][6][1] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][4][1] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),
        .O(\idel_dec_cnt[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \idel_dec_cnt[1]_i_4 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][1] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][1] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),
        .O(\idel_dec_cnt[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFA900A900A900)) 
    \idel_dec_cnt[2]_i_1 
       (.I0(\idel_dec_cnt_reg_n_0_[2] ),
        .I1(\idel_dec_cnt_reg_n_0_[0] ),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I4(idelay_tap_cnt_r[2]),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .O(idel_dec_cnt[2]));
  LUT5 #(
    .INIT(32'hFF606060)) 
    \idel_dec_cnt[3]_i_1 
       (.I0(\idel_dec_cnt_reg_n_0_[3] ),
        .I1(\idel_dec_cnt[3]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I3(idelay_tap_cnt_r[3]),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .O(idel_dec_cnt[3]));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \idel_dec_cnt[3]_i_2 
       (.I0(\idel_dec_cnt_reg_n_0_[0] ),
        .I1(\idel_dec_cnt_reg_n_0_[1] ),
        .I2(\idel_dec_cnt_reg_n_0_[2] ),
        .O(\idel_dec_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF80)) 
    \idel_dec_cnt[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I1(idel_mpr_pat_detect_r),
        .I2(idel_pat_detect_valid_r_reg_n_0),
        .I3(\idel_dec_cnt[4]_i_3_n_0 ),
        .I4(\idel_dec_cnt[4]_i_4_n_0 ),
        .I5(\idel_dec_cnt[4]_i_5_n_0 ),
        .O(\idel_dec_cnt[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF606060)) 
    \idel_dec_cnt[4]_i_2 
       (.I0(\idel_dec_cnt_reg_n_0_[4] ),
        .I1(\idel_dec_cnt[4]_i_6_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I3(idelay_tap_cnt_r[4]),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .O(idel_dec_cnt[4]));
  LUT4 #(
    .INIT(16'hA800)) 
    \idel_dec_cnt[4]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I3(detect_edge_done_r),
        .O(\idel_dec_cnt[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00F7000000000000)) 
    \idel_dec_cnt[4]_i_4 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),
        .I1(\idel_dec_cnt_reg[0]_i_2_n_0 ),
        .I2(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I5(\idel_dec_cnt[4]_i_7_n_0 ),
        .O(\idel_dec_cnt[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA8)) 
    \idel_dec_cnt[4]_i_5 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[23] ),
        .I1(\idel_dec_cnt_reg_n_0_[2] ),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\idel_dec_cnt_reg_n_0_[0] ),
        .I4(\idel_dec_cnt_reg_n_0_[3] ),
        .I5(\idel_dec_cnt_reg_n_0_[4] ),
        .O(\idel_dec_cnt[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \idel_dec_cnt[4]_i_6 
       (.I0(\idel_dec_cnt_reg_n_0_[2] ),
        .I1(\idel_dec_cnt_reg_n_0_[1] ),
        .I2(\idel_dec_cnt_reg_n_0_[0] ),
        .I3(\idel_dec_cnt_reg_n_0_[3] ),
        .O(\idel_dec_cnt[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \idel_dec_cnt[4]_i_7 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .I1(mpr_dec_cpt_r_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .O(\idel_dec_cnt[4]_i_7_n_0 ));
  FDRE \idel_dec_cnt_reg[0] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[0]),
        .Q(\idel_dec_cnt_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  MUXF7 \idel_dec_cnt_reg[0]_i_2 
       (.I0(\idel_dec_cnt[0]_i_3_n_0 ),
        .I1(\idel_dec_cnt[0]_i_4_n_0 ),
        .O(\idel_dec_cnt_reg[0]_i_2_n_0 ),
        .S(\cal1_cnt_cpt_r_reg_n_0_[0] ));
  FDRE \idel_dec_cnt_reg[1] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[1]),
        .Q(\idel_dec_cnt_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  MUXF7 \idel_dec_cnt_reg[1]_i_2 
       (.I0(\idel_dec_cnt[1]_i_3_n_0 ),
        .I1(\idel_dec_cnt[1]_i_4_n_0 ),
        .O(\idel_dec_cnt_reg[1]_i_2_n_0 ),
        .S(\cal1_cnt_cpt_r_reg_n_0_[0] ));
  FDRE \idel_dec_cnt_reg[2] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[2]),
        .Q(\idel_dec_cnt_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \idel_dec_cnt_reg[3] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[3]),
        .Q(\idel_dec_cnt_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \idel_dec_cnt_reg[4] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[4]),
        .Q(\idel_dec_cnt_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT4 #(
    .INIT(16'hCCCE)) 
    idel_pat_detect_valid_r_i_1
       (.I0(idel_pat_detect_valid_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[20] ),
        .O(idel_pat_detect_valid_r_i_1_n_0));
  FDRE idel_pat_detect_valid_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idel_pat_detect_valid_r_i_1_n_0),
        .Q(idel_pat_detect_valid_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__2));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \idelay_tap_cnt_r[0][0][0]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__24_0),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[0]),
        .O(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT5 #(
    .INIT(32'h04404004)) 
    \idelay_tap_cnt_r[0][0][1]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__24_0),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[1]),
        .I3(idelay_inc_int),
        .I4(idelay_tap_cnt_slice_r[0]),
        .O(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0440404040404004)) 
    \idelay_tap_cnt_r[0][0][2]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__24_0),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[2]),
        .I3(idelay_tap_cnt_slice_r[0]),
        .I4(idelay_inc_int),
        .I5(idelay_tap_cnt_slice_r[1]),
        .O(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h80017FFEFFFFFFFF)) 
    \idelay_tap_cnt_r[0][0][3]_i_2 
       (.I0(idelay_tap_cnt_slice_r[2]),
        .I1(idelay_tap_cnt_slice_r[0]),
        .I2(idelay_inc_int),
        .I3(idelay_tap_cnt_slice_r[1]),
        .I4(idelay_tap_cnt_slice_r[3]),
        .I5(idelay_ce_int),
        .O(\idelay_tap_cnt_r_reg[0][7][3]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF444444F4)) 
    \idelay_tap_cnt_r[0][0][4]_i_1 
       (.I0(\po_stg2_wrcal_cnt_reg[0] ),
        .I1(\po_stg2_wrcal_cnt_reg[2] ),
        .I2(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \idelay_tap_cnt_r[0][0][4]_i_2 
       (.I0(rstdiv0_sync_r1_reg_rep__24_0),
        .I1(\idelay_tap_cnt_r[0][0][4]_i_6_n_0 ),
        .I2(idelay_ce_int),
        .O(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \idelay_tap_cnt_r[0][0][4]_i_5 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I1(idelay_ce_int),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \idelay_tap_cnt_r[0][0][4]_i_6 
       (.I0(idelay_tap_cnt_slice_r[4]),
        .I1(idelay_tap_cnt_slice_r[2]),
        .I2(idelay_tap_cnt_slice_r[0]),
        .I3(idelay_inc_int),
        .I4(idelay_tap_cnt_slice_r[1]),
        .I5(idelay_tap_cnt_slice_r[3]),
        .O(\idelay_tap_cnt_r[0][0][4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0404FF04)) 
    \idelay_tap_cnt_r[0][1][4]_i_1 
       (.I0(\idelay_tap_cnt_r[0][1][4]_i_2_n_0 ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\po_stg2_wrcal_cnt_reg[2] ),
        .I4(\po_stg2_wrcal_cnt_reg[1] ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT4 #(
    .INIT(16'hFFFB)) 
    \idelay_tap_cnt_r[0][1][4]_i_2 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I1(idelay_ce_int),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\idelay_tap_cnt_r[0][1][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0404FF04)) 
    \idelay_tap_cnt_r[0][2][4]_i_1 
       (.I0(\idelay_tap_cnt_r[0][1][4]_i_2_n_0 ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\po_stg2_wrcal_cnt_reg[2] ),
        .I4(\po_stg2_wrcal_cnt_reg[0]_0 ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF4040FF40)) 
    \idelay_tap_cnt_r[0][3][4]_i_1 
       (.I0(\idelay_tap_cnt_r[0][1][4]_i_2_n_0 ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\po_stg2_wrcal_cnt_reg[2] ),
        .I4(\po_stg2_wrcal_cnt_reg[0]_1 ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF1111F111)) 
    \idelay_tap_cnt_r[0][4][4]_i_1 
       (.I0(\po_stg2_wrcal_cnt_reg[3] ),
        .I1(\po_stg2_wrcal_cnt_reg[0] ),
        .I2(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\idelay_tap_cnt_r[0][4][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF040404FF)) 
    \idelay_tap_cnt_r[0][5][4]_i_1 
       (.I0(\idelay_tap_cnt_r[0][5][4]_i_2_n_0 ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\po_stg2_wrcal_cnt_reg[1] ),
        .I4(\po_stg2_wrcal_cnt_reg[3] ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\idelay_tap_cnt_r[0][5][4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT4 #(
    .INIT(16'hFDFF)) 
    \idelay_tap_cnt_r[0][5][4]_i_2 
       (.I0(idelay_ce_int),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(\idelay_tap_cnt_r[0][5][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF040404FF)) 
    \idelay_tap_cnt_r[0][6][4]_i_1 
       (.I0(\idelay_tap_cnt_r[0][5][4]_i_2_n_0 ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\po_stg2_wrcal_cnt_reg[0]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[3] ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\idelay_tap_cnt_r[0][6][4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \idelay_tap_cnt_r[0][7][4]_i_2 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(idelay_ce_int),
        .O(\idelay_tap_cnt_r_reg[0][7][4]_0 ));
  FDRE \idelay_tap_cnt_r_reg[0][0][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][4][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][4][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][4][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][4][4]_i_1_n_0 ),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][4][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][5][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][5][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][5][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][5][4]_i_1_n_0 ),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][5][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][6][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][6][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][6][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][6][4]_i_1_n_0 ),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][6][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][0] 
       (.C(CLK),
        .CE(E),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][1] 
       (.C(CLK),
        .CE(E),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][2] 
       (.C(CLK),
        .CE(E),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][3] 
       (.C(CLK),
        .CE(E),
        .D(rstdiv0_sync_r1_reg_rep__24_1),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][4] 
       (.C(CLK),
        .CE(E),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \idelay_tap_cnt_slice_r[0]_i_1 
       (.I0(\idel_dec_cnt_reg[0]_i_2_n_0 ),
        .O(idelay_tap_cnt_r[0]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \idelay_tap_cnt_slice_r[1]_i_1 
       (.I0(\idel_dec_cnt_reg[1]_i_2_n_0 ),
        .O(idelay_tap_cnt_r[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[2]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][6][2] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][4][2] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),
        .O(\idelay_tap_cnt_slice_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[2]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][2] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][2] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),
        .O(\idelay_tap_cnt_slice_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[3]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][6][3] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][4][3] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),
        .O(\idelay_tap_cnt_slice_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[3]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][3] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][3] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),
        .O(\idelay_tap_cnt_slice_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[4]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][6][4] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][4][4] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .O(\idelay_tap_cnt_slice_r[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[4]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][4] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][4] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .O(\idelay_tap_cnt_slice_r[4]_i_3_n_0 ));
  FDRE \idelay_tap_cnt_slice_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[0]),
        .Q(idelay_tap_cnt_slice_r[0]),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \idelay_tap_cnt_slice_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[1]),
        .Q(idelay_tap_cnt_slice_r[1]),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \idelay_tap_cnt_slice_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[2]),
        .Q(idelay_tap_cnt_slice_r[2]),
        .R(rstdiv0_sync_r1_reg_rep__2));
  MUXF7 \idelay_tap_cnt_slice_r_reg[2]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[2]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[2]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[2]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[0] ));
  FDRE \idelay_tap_cnt_slice_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[3]),
        .Q(idelay_tap_cnt_slice_r[3]),
        .R(rstdiv0_sync_r1_reg_rep__2));
  MUXF7 \idelay_tap_cnt_slice_r_reg[3]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[3]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[3]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[3]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[0] ));
  FDRE \idelay_tap_cnt_slice_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[4]),
        .Q(idelay_tap_cnt_slice_r[4]),
        .R(rstdiv0_sync_r1_reg_rep__2));
  MUXF7 \idelay_tap_cnt_slice_r_reg[4]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[4]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[4]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[4]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[0] ));
  LUT3 #(
    .INIT(8'h02)) 
    idelay_tap_limit_r_i_1
       (.I0(idelay_tap_limit_r_i_2_n_0),
        .I1(idelay_tap_limit_r_reg_0),
        .I2(rstdiv0_sync_r1_reg_rep__23),
        .O(idelay_tap_limit_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00004000)) 
    idelay_tap_limit_r_i_2
       (.I0(\idel_dec_cnt_reg[1]_i_2_n_0 ),
        .I1(idelay_tap_cnt_r[4]),
        .I2(idelay_tap_cnt_r[3]),
        .I3(idelay_tap_cnt_r[2]),
        .I4(\idel_dec_cnt_reg[0]_i_2_n_0 ),
        .I5(idelay_tap_limit_r_reg_n_0),
        .O(idelay_tap_limit_r_i_2_n_0));
  FDRE idelay_tap_limit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_limit_r_i_1_n_0),
        .Q(idelay_tap_limit_r_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[0]_i_30 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(complex_row0_rd_done),
        .O(\init_state_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \init_state_r[0]_i_32 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(wrlvl_done_r1),
        .I2(dqs_found_done_r_reg),
        .O(\init_state_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT3 #(
    .INIT(8'hCE)) 
    \init_state_r[2]_i_33 
       (.I0(\one_rank.stg1_wr_done_reg ),
        .I1(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I2(rdlvl_last_byte_done),
        .O(\init_state_r_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \init_state_r[3]_i_22 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(prbs_last_byte_done_r),
        .O(\init_state_r_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[4]_i_36 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(rdlvl_last_byte_done),
        .O(\init_state_r_reg[4] ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_1 
       (.I0(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ),
        .I1(\mpr_4to1.stable_idel_cnt[1]_i_3_n_0 ),
        .I2(inhibit_edge_detect_r),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I4(inhibit_edge_detect_r0),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00100000)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_2 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),
        .I1(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I4(\mpr_4to1.stable_idel_cnt[1]_i_2_n_0 ),
        .I5(idel_mpr_pat_detect_r),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ));
  FDRE \mpr_4to1.idel_mpr_pat_detect_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ),
        .Q(idel_mpr_pat_detect_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFF2FF0000)) 
    \mpr_4to1.inhibit_edge_detect_r_i_1 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),
        .I1(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),
        .I2(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I4(inhibit_edge_detect_r),
        .I5(inhibit_edge_detect_r0),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \mpr_4to1.inhibit_edge_detect_r_i_2 
       (.I0(idelay_tap_cnt_r[2]),
        .I1(idelay_tap_cnt_r[3]),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \mpr_4to1.inhibit_edge_detect_r_i_3 
       (.I0(idelay_tap_cnt_r[4]),
        .I1(\idel_dec_cnt_reg[1]_i_2_n_0 ),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \mpr_4to1.inhibit_edge_detect_r_i_4 
       (.I0(mpr_rd_fall3_prev_r),
        .I1(mpr_rd_rise3_prev_r),
        .I2(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT4 #(
    .INIT(16'hAAEA)) 
    \mpr_4to1.inhibit_edge_detect_r_i_5 
       (.I0(rstdiv0_sync_r1_reg_rep__24_0),
        .I1(\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ),
        .I2(mpr_rd_rise3_prev_r),
        .I3(mpr_rd_fall3_prev_r),
        .O(inhibit_edge_detect_r0));
  LUT6 #(
    .INIT(64'hFFFFFDFFFFFFFFFF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_6 
       (.I0(mpr_rd_fall0_prev_r),
        .I1(mpr_rd_rise0_prev_r),
        .I2(mpr_rd_rise1_prev_r),
        .I3(mpr_rd_fall1_prev_r),
        .I4(mpr_rd_rise2_prev_r),
        .I5(mpr_rd_fall2_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    \mpr_4to1.inhibit_edge_detect_r_i_7 
       (.I0(mpr_rd_fall0_prev_r),
        .I1(mpr_rd_rise0_prev_r),
        .I2(mpr_rd_rise1_prev_r),
        .I3(mpr_rd_fall1_prev_r),
        .I4(mpr_rd_rise2_prev_r),
        .I5(mpr_rd_fall2_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ));
  FDRE \mpr_4to1.inhibit_edge_detect_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ),
        .Q(inhibit_edge_detect_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000006A)) 
    \mpr_4to1.stable_idel_cnt[0]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I1(stable_idel_cnt23_in),
        .I2(\mpr_4to1.stable_idel_cnt[1]_i_3_n_0 ),
        .I3(rstdiv0_sync_r1_reg_rep__23),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .I5(\mpr_4to1.stable_idel_cnt[1]_i_2_n_0 ),
        .O(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000009AAAAAAA)) 
    \mpr_4to1.stable_idel_cnt[1]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I1(\mpr_4to1.stable_idel_cnt[1]_i_2_n_0 ),
        .I2(\mpr_4to1.stable_idel_cnt[1]_i_3_n_0 ),
        .I3(stable_idel_cnt23_in),
        .I4(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I5(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \mpr_4to1.stable_idel_cnt[1]_i_2 
       (.I0(mpr_rd_fall3_prev_r),
        .I1(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .I2(mpr_rd_rise3_prev_r),
        .I3(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .I4(\mpr_4to1.stable_idel_cnt[1]_i_4_n_0 ),
        .I5(\mpr_4to1.stable_idel_cnt[1]_i_5_n_0 ),
        .O(\mpr_4to1.stable_idel_cnt[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0008)) 
    \mpr_4to1.stable_idel_cnt[1]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .O(\mpr_4to1.stable_idel_cnt[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \mpr_4to1.stable_idel_cnt[1]_i_4 
       (.I0(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .I1(mpr_rd_rise2_prev_r),
        .I2(mpr_rd_rise1_prev_r),
        .I3(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .I4(mpr_rd_fall1_prev_r),
        .I5(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .O(\mpr_4to1.stable_idel_cnt[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \mpr_4to1.stable_idel_cnt[1]_i_5 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .I1(mpr_rd_rise0_prev_r),
        .I2(mpr_rd_fall2_prev_r),
        .I3(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .I4(mpr_rd_fall0_prev_r),
        .I5(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .O(\mpr_4to1.stable_idel_cnt[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h000000009AAAAAAA)) 
    \mpr_4to1.stable_idel_cnt[2]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I1(\mpr_4to1.stable_idel_cnt[2]_i_2_n_0 ),
        .I2(stable_idel_cnt23_in),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I4(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I5(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFEFFFFFF)) 
    \mpr_4to1.stable_idel_cnt[2]_i_2 
       (.I0(\mpr_4to1.stable_idel_cnt[1]_i_2_n_0 ),
        .I1(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(idel_pat_detect_valid_r_reg_n_0),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \mpr_4to1.stable_idel_cnt[2]_i_3 
       (.I0(\mpr_4to1.stable_idel_cnt[1]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[30] ),
        .I2(rstdiv0_sync_r1_reg_rep__24_0),
        .O(stable_idel_cnt0));
  FDRE \mpr_4to1.stable_idel_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \mpr_4to1.stable_idel_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \mpr_4to1.stable_idel_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hDC)) 
    mpr_dec_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[5] ),
        .I1(mpr_dec_cpt_r),
        .I2(mpr_dec_cpt_r_reg_n_0),
        .O(mpr_dec_cpt_r_i_1_n_0));
  FDRE mpr_dec_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mpr_dec_cpt_r_i_1_n_0),
        .Q(mpr_dec_cpt_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT3 #(
    .INIT(8'hEA)) 
    mpr_rd_fall0_prev_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I2(idel_pat_detect_valid_r_reg_n_0),
        .O(mpr_rd_rise0_prev_r0));
  FDRE mpr_rd_fall0_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall0_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall1_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall1_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall2_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall2_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall3_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall3_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise0_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise0_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise1_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise1_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise2_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise2_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise3_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise3_prev_r),
        .R(1'b0));
  FDRE mpr_rdlvl_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mpr_rdlvl_start_reg),
        .Q(mpr_rdlvl_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hBAAABABAAAAAAAAA)) 
    new_cnt_cpt_r_i_1
       (.I0(new_cnt_cpt_r_i_2_n_0),
        .I1(rdlvl_stg1_start_r),
        .I2(rdlvl_stg1_start_reg),
        .I3(mpr_rdlvl_start_r),
        .I4(mpr_rdlvl_start_reg),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .O(new_cnt_cpt_r));
  LUT5 #(
    .INIT(32'hAAA20000)) 
    new_cnt_cpt_r_i_2
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(prech_done),
        .O(new_cnt_cpt_r_i_2_n_0));
  FDRE new_cnt_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(new_cnt_cpt_r),
        .Q(idelay_tap_limit_r_reg_0),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT5 #(
    .INIT(32'h44440004)) 
    \phaser_in_gen.phaser_in_i_1 
       (.I0(Q[1]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_counter_load_en161_out));
  LUT5 #(
    .INIT(32'h20202022)) 
    \phaser_in_gen.phaser_in_i_10 
       (.I0(pi_stg2_reg_l[1]),
        .I1(Q[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[4] [1]));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_10__0 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[1]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[1] [1]));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_10__1 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[1]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[2] [1]));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_10__2 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[1]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[3] [1]));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_10__3 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(COUNTERLOADVAL[1]));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_10__4 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[8] [1]));
  LUT5 #(
    .INIT(32'h20202022)) 
    \phaser_in_gen.phaser_in_i_11 
       (.I0(pi_stg2_reg_l[0]),
        .I1(Q[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[4] [0]));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_11__0 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[0]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[1] [0]));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_11__1 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[0]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[2] [0]));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_11__2 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[0]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[3] [0]));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_11__3 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[0]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(COUNTERLOADVAL[0]));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_11__4 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[0]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[8] [0]));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_1__0 
       (.I0(Q[0]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(D_pi_counter_load_en90_out));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    \phaser_in_gen.phaser_in_i_1__1 
       (.I0(Q[0]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_counter_load_en116_out));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_1__2 
       (.I0(Q[0]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(B_pi_counter_load_en38_out));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_1__3 
       (.I0(Q[0]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(C_pi_counter_load_en64_out));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    \phaser_in_gen.phaser_in_i_1__4 
       (.I0(Q[2]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_counter_load_en87_out));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_1__5 
       (.I0(Q[2]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(B_pi_counter_load_en35_out));
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_1__6 
       (.I0(Q[2]),
        .I1(pi_stg2_load),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(C_pi_counter_load_en61_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    \phaser_in_gen.phaser_in_i_3 
       (.I0(Q[1]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_fine_enable157_out));
  LUT6 #(
    .INIT(64'h5454545454000000)) 
    \phaser_in_gen.phaser_in_i_3__0 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(D_pi_fine_enable86_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    \phaser_in_gen.phaser_in_i_3__1 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_fine_enable112_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_3__2 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(B_pi_fine_enable34_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_3__3 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(C_pi_fine_enable60_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    \phaser_in_gen.phaser_in_i_3__4 
       (.I0(Q[2]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_fine_enable83_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_3__5 
       (.I0(Q[2]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(B_pi_fine_enable31_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_3__6 
       (.I0(Q[2]),
        .I1(tempmon_pi_f_en_r),
        .I2(rdlvl_pi_stg2_f_en),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(C_pi_fine_enable57_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    \phaser_in_gen.phaser_in_i_4 
       (.I0(Q[1]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_fine_inc159_out));
  LUT6 #(
    .INIT(64'h5454545454000000)) 
    \phaser_in_gen.phaser_in_i_4__0 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(D_pi_fine_inc88_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    \phaser_in_gen.phaser_in_i_4__1 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_fine_inc114_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_4__2 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(B_pi_fine_inc36_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_4__3 
       (.I0(Q[0]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(C_pi_fine_inc62_out));
  LUT6 #(
    .INIT(64'h5454545400000054)) 
    \phaser_in_gen.phaser_in_i_4__4 
       (.I0(Q[2]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(A_pi_fine_inc85_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_4__5 
       (.I0(Q[2]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(B_pi_fine_inc33_out));
  LUT6 #(
    .INIT(64'h5454545400005400)) 
    \phaser_in_gen.phaser_in_i_4__6 
       (.I0(Q[2]),
        .I1(tempmon_pi_f_inc_r),
        .I2(rdlvl_pi_stg2_f_incdec),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .I5(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(C_pi_fine_inc59_out));
  LUT5 #(
    .INIT(32'h20202022)) 
    \phaser_in_gen.phaser_in_i_6 
       (.I0(pi_stg2_reg_l[5]),
        .I1(Q[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[4] [5]));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_6__0 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[5]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[1] [5]));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_6__1 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[5]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[2] [5]));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_6__2 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[5]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[3] [5]));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_6__3 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[5]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(COUNTERLOADVAL[5]));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_6__4 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[5]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[8] [5]));
  LUT5 #(
    .INIT(32'h20202022)) 
    \phaser_in_gen.phaser_in_i_7 
       (.I0(pi_stg2_reg_l[4]),
        .I1(Q[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[4] [4]));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_7__0 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[4]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[1] [4]));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_7__1 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[4]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[2] [4]));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_7__2 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[4]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[3] [4]));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_7__3 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[4]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(COUNTERLOADVAL[4]));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_7__4 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[4]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[8] [4]));
  LUT5 #(
    .INIT(32'h20202022)) 
    \phaser_in_gen.phaser_in_i_8 
       (.I0(pi_stg2_reg_l[3]),
        .I1(Q[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[4] [3]));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_8__0 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[3]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[1] [3]));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_8__1 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[3]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[2] [3]));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_8__2 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[3]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[3] [3]));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_8__3 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[3]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(COUNTERLOADVAL[3]));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_8__4 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[3]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[8] [3]));
  LUT5 #(
    .INIT(32'h20202022)) 
    \phaser_in_gen.phaser_in_i_9 
       (.I0(pi_stg2_reg_l[2]),
        .I1(Q[1]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[4] [2]));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_9__0 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[2]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[1] [2]));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    \phaser_in_gen.phaser_in_i_9__1 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[2]),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[2] [2]));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    \phaser_in_gen.phaser_in_i_9__2 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[2]),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg ),
        .O(\pi_dqs_found_lanes_r1_reg[3] [2]));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_9__3 
       (.I0(Q[0]),
        .I1(pi_stg2_reg_l[2]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(COUNTERLOADVAL[2]));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT5 #(
    .INIT(32'h40404044)) 
    \phaser_in_gen.phaser_in_i_9__4 
       (.I0(Q[2]),
        .I1(pi_stg2_reg_l[2]),
        .I2(\gen_byte_sel_div2.calib_in_common_reg ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(\pi_dqs_found_lanes_r1_reg[8] [2]));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    pi_cnt_dec_i_1
       (.I0(pi_cnt_dec_i_2_n_0),
        .I1(wait_cnt_r_reg__0__0[0]),
        .I2(dqs_po_dec_done_r2),
        .I3(wait_cnt_r_reg__0__0[1]),
        .I4(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(pi_cnt_dec_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT2 #(
    .INIT(4'hE)) 
    pi_cnt_dec_i_2
       (.I0(wait_cnt_r_reg__0__0[2]),
        .I1(wait_cnt_r_reg__0__0[3]),
        .O(pi_cnt_dec_i_2_n_0));
  FDRE pi_cnt_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_cnt_dec_i_1_n_0),
        .Q(fine_dly_dec_done_r1_reg_0),
        .R(1'b0));
  FDRE pi_en_stg2_f_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_en_stg2_f_timing),
        .Q(rdlvl_pi_stg2_f_en),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    pi_en_stg2_f_timing_i_1
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(fine_dly_dec_done_r1_reg_0),
        .O(pi_en_stg2_f_timing_i_1_n_0));
  FDRE pi_en_stg2_f_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_en_stg2_f_timing_i_1_n_0),
        .Q(pi_en_stg2_f_timing),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE pi_fine_dly_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_dly_dec_done_r2),
        .Q(pi_fine_dly_dec_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \pi_rdval_cnt[0]_i_1 
       (.I0(\pi_counter_read_val_reg[0] ),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(pi_rdval_cnt[0]),
        .O(\pi_rdval_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB0808FBFB08FB08)) 
    \pi_rdval_cnt[1]_i_1 
       (.I0(\pi_counter_read_val_reg[1]_0 ),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[1]),
        .I4(pi_rdval_cnt[0]),
        .I5(\pi_rdval_cnt[5]_i_3_n_0 ),
        .O(\pi_rdval_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B888888888B8)) 
    \pi_rdval_cnt[2]_i_1 
       (.I0(\pi_counter_read_val_reg[2]_0 ),
        .I1(\pi_rdval_cnt[2]_i_3_n_0 ),
        .I2(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I3(pi_rdval_cnt[1]),
        .I4(pi_rdval_cnt[0]),
        .I5(pi_rdval_cnt[2]),
        .O(\pi_rdval_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \pi_rdval_cnt[2]_i_3 
       (.I0(dqs_po_dec_done_r1),
        .I1(dqs_po_dec_done_r2),
        .O(\pi_rdval_cnt[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0808FB08FB080808)) 
    \pi_rdval_cnt[3]_i_1 
       (.I0(\pi_counter_read_val_reg[3] ),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(\pi_rdval_cnt[3]_i_3_n_0 ),
        .I5(pi_rdval_cnt[3]),
        .O(\pi_rdval_cnt[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \pi_rdval_cnt[3]_i_3 
       (.I0(pi_rdval_cnt[0]),
        .I1(pi_rdval_cnt[1]),
        .I2(pi_rdval_cnt[2]),
        .O(\pi_rdval_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0808FBFBFB080808)) 
    \pi_rdval_cnt[4]_i_1 
       (.I0(\pi_counter_read_val_reg[4] ),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[5]),
        .I4(\pi_rdval_cnt[4]_i_2_n_0 ),
        .I5(pi_rdval_cnt[4]),
        .O(\pi_rdval_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \pi_rdval_cnt[4]_i_2 
       (.I0(pi_rdval_cnt[2]),
        .I1(pi_rdval_cnt[1]),
        .I2(pi_rdval_cnt[0]),
        .I3(pi_rdval_cnt[3]),
        .O(\pi_rdval_cnt[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hBBFB)) 
    \pi_rdval_cnt[5]_i_1 
       (.I0(fine_dly_dec_done_r1_reg_0),
        .I1(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I2(dqs_po_dec_done_r1),
        .I3(dqs_po_dec_done_r2),
        .O(\pi_rdval_cnt[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \pi_rdval_cnt[5]_i_2 
       (.I0(\pi_counter_read_val_reg[5] ),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[5]),
        .I4(\pi_rdval_cnt[5]_i_4_n_0 ),
        .O(\pi_rdval_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \pi_rdval_cnt[5]_i_3 
       (.I0(pi_rdval_cnt[5]),
        .I1(pi_rdval_cnt[4]),
        .I2(pi_rdval_cnt[2]),
        .I3(pi_rdval_cnt[1]),
        .I4(pi_rdval_cnt[0]),
        .I5(pi_rdval_cnt[3]),
        .O(\pi_rdval_cnt[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \pi_rdval_cnt[5]_i_4 
       (.I0(pi_rdval_cnt[3]),
        .I1(pi_rdval_cnt[0]),
        .I2(pi_rdval_cnt[1]),
        .I3(pi_rdval_cnt[2]),
        .I4(pi_rdval_cnt[4]),
        .O(\pi_rdval_cnt[5]_i_4_n_0 ));
  FDRE \pi_rdval_cnt_reg[0] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[0]_i_1_n_0 ),
        .Q(pi_rdval_cnt[0]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \pi_rdval_cnt_reg[1] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[1]_i_1_n_0 ),
        .Q(pi_rdval_cnt[1]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \pi_rdval_cnt_reg[2] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[2]_i_1_n_0 ),
        .Q(pi_rdval_cnt[2]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \pi_rdval_cnt_reg[3] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[3]_i_1_n_0 ),
        .Q(pi_rdval_cnt[3]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \pi_rdval_cnt_reg[4] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[4]_i_1_n_0 ),
        .Q(pi_rdval_cnt[4]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \pi_rdval_cnt_reg[5] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[5]_i_2_n_0 ),
        .Q(pi_rdval_cnt[5]),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE pi_stg2_f_incdec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing),
        .Q(rdlvl_pi_stg2_f_incdec),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0008)) 
    pi_stg2_f_incdec_timing_i_1
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(cal1_dlyinc_cpt_r_reg_n_0),
        .I2(fine_dly_dec_done_r1_reg_0),
        .I3(rstdiv0_sync_r1_reg_rep__24_0),
        .O(pi_stg2_f_incdec_timing0));
  FDRE pi_stg2_f_incdec_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing0),
        .Q(pi_stg2_f_incdec_timing),
        .R(1'b0));
  FDRE pi_stg2_load_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_load_timing),
        .Q(pi_stg2_load),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h20)) 
    pi_stg2_load_timing_i_1
       (.I0(\regl_dqs_cnt[3]_i_4_n_0 ),
        .I1(regl_dqs_cnt[3]),
        .I2(\regl_dqs_cnt[3]_i_3_n_0 ),
        .O(pi_stg2_load_timing_i_1_n_0));
  FDRE pi_stg2_load_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_load_timing_i_1_n_0),
        .Q(pi_stg2_load_timing),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[0]),
        .Q(pi_stg2_reg_l[0]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[1]),
        .Q(pi_stg2_reg_l[1]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[2]),
        .Q(pi_stg2_reg_l[2]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[3]),
        .Q(pi_stg2_reg_l[3]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[4]),
        .Q(pi_stg2_reg_l[4]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[5]),
        .Q(pi_stg2_reg_l[5]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[0]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),
        .O(\pi_stg2_reg_l_timing[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[0]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0] ),
        .O(\pi_stg2_reg_l_timing[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[1]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),
        .O(\pi_stg2_reg_l_timing[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[1]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1] ),
        .O(\pi_stg2_reg_l_timing[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[2]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),
        .O(\pi_stg2_reg_l_timing[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[2]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2] ),
        .O(\pi_stg2_reg_l_timing[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[3]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),
        .O(\pi_stg2_reg_l_timing[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[3]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3] ),
        .O(\pi_stg2_reg_l_timing[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[4]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),
        .O(\pi_stg2_reg_l_timing[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[4]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4] ),
        .O(\pi_stg2_reg_l_timing[4]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hDF)) 
    \pi_stg2_reg_l_timing[5]_i_1 
       (.I0(\regl_dqs_cnt[3]_i_3_n_0 ),
        .I1(regl_dqs_cnt[3]),
        .I2(\regl_dqs_cnt[3]_i_4_n_0 ),
        .O(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[5]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),
        .O(\pi_stg2_reg_l_timing[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[5]_i_4 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5] ),
        .O(\pi_stg2_reg_l_timing[5]_i_4_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[0]),
        .Q(pi_stg2_reg_l_timing[0]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[0]_i_1 
       (.I0(\pi_stg2_reg_l_timing[0]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[0]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[0]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[1]),
        .Q(pi_stg2_reg_l_timing[1]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[1]_i_1 
       (.I0(\pi_stg2_reg_l_timing[1]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[1]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[1]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[2]),
        .Q(pi_stg2_reg_l_timing[2]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[2]_i_1 
       (.I0(\pi_stg2_reg_l_timing[2]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[2]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[2]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[3]),
        .Q(pi_stg2_reg_l_timing[3]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[3]_i_1 
       (.I0(\pi_stg2_reg_l_timing[3]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[3]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[3]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[4]),
        .Q(pi_stg2_reg_l_timing[4]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[4]_i_1 
       (.I0(\pi_stg2_reg_l_timing[4]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[4]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[4]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[5]),
        .Q(pi_stg2_reg_l_timing[5]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[5]_i_2 
       (.I0(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .I1(\pi_stg2_reg_l_timing[5]_i_4_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[5]),
        .S(regl_dqs_cnt[2]));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT2 #(
    .INIT(4'h2)) 
    prbs_rdlvl_done_pulse_i_1
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(prbs_last_byte_done_r),
        .O(prbs_rdlvl_done_pulse_reg));
  FDRE \rd_mux_sel_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .R(1'b0));
  FDRE \rd_mux_sel_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .R(1'b0));
  FDRE \rd_mux_sel_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I1(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2 
       (.I0(\cal1_state_r1_reg_n_0_[5] ),
        .I1(\cal1_state_r1_reg_n_0_[0] ),
        .I2(\cal1_state_r1_reg_n_0_[2] ),
        .I3(\cal1_state_r1_reg_n_0_[4] ),
        .I4(\cal1_state_r1_reg_n_0_[3] ),
        .I5(\cal1_state_r1_reg_n_0_[1] ),
        .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I1(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .O(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I1(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .O(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I1(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .O(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .O(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000010000000000)) 
    \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .O(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000010000000000)) 
    \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .O(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0100000000000000)) 
    \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [2]),
        .I4(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0 [1]),
        .O(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5] ),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT6 #(
    .INIT(64'hCCCCCCCFCCCCCCC8)) 
    rdlvl_last_byte_done_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(\FSM_onehot_cal1_state_r[31]_i_2_n_0 ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .I5(rdlvl_last_byte_done),
        .O(rdlvl_last_byte_done_i_1_n_0));
  FDRE rdlvl_last_byte_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_last_byte_done_i_1_n_0),
        .Q(rdlvl_last_byte_done),
        .R(rstdiv0_sync_r1_reg_rep__1));
  FDRE rdlvl_prech_req_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_prech_req_r_reg_n_0),
        .Q(rdlvl_prech_req),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT6 #(
    .INIT(64'hC0C0C0FFC0C0C080)) 
    rdlvl_rank_done_r_i_1
       (.I0(prech_done),
        .I1(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I3(rdlvl_rank_done_r_i_2_n_0),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I5(rdlvl_stg1_rank_done),
        .O(rdlvl_rank_done_r_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    rdlvl_rank_done_r_i_2
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[0] ),
        .O(rdlvl_rank_done_r_i_2_n_0));
  FDRE rdlvl_rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_rank_done_r_i_1_n_0),
        .Q(rdlvl_stg1_rank_done),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT3 #(
    .INIT(8'h0E)) 
    rdlvl_stg1_done_i_1
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I2(rstdiv0_sync_r1_reg_rep__24_0),
        .O(rdlvl_stg1_done_i_1_n_0));
  FDRE rdlvl_stg1_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_done_i_1_n_0),
        .Q(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .R(1'b0));
  FDRE rdlvl_stg1_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_start_reg),
        .Q(rdlvl_stg1_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000AAAA8000AAAA)) 
    \regl_dqs_cnt[0]_i_1 
       (.I0(\regl_dqs_cnt[3]_i_4_n_0 ),
        .I1(\regl_dqs_cnt[3]_i_3_n_0 ),
        .I2(regl_dqs_cnt[2]),
        .I3(regl_dqs_cnt[1]),
        .I4(regl_dqs_cnt[0]),
        .I5(regl_dqs_cnt[3]),
        .O(\regl_dqs_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h28282828A8282828)) 
    \regl_dqs_cnt[1]_i_1 
       (.I0(\regl_dqs_cnt[3]_i_4_n_0 ),
        .I1(regl_dqs_cnt[0]),
        .I2(regl_dqs_cnt[1]),
        .I3(\regl_dqs_cnt[3]_i_3_n_0 ),
        .I4(regl_dqs_cnt[2]),
        .I5(regl_dqs_cnt[3]),
        .O(\regl_dqs_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h28882888A8882888)) 
    \regl_dqs_cnt[2]_i_1 
       (.I0(\regl_dqs_cnt[3]_i_4_n_0 ),
        .I1(regl_dqs_cnt[2]),
        .I2(regl_dqs_cnt[1]),
        .I3(regl_dqs_cnt[0]),
        .I4(\regl_dqs_cnt[3]_i_3_n_0 ),
        .I5(regl_dqs_cnt[3]),
        .O(\regl_dqs_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000023)) 
    \regl_dqs_cnt[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I1(\done_cnt_reg_n_0_[1] ),
        .I2(\done_cnt_reg_n_0_[0] ),
        .I3(\done_cnt_reg_n_0_[3] ),
        .I4(\done_cnt_reg_n_0_[2] ),
        .I5(rstdiv0_sync_r1_reg_rep__24_0),
        .O(\regl_dqs_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0CCCCCCC40000000)) 
    \regl_dqs_cnt[3]_i_2 
       (.I0(\regl_dqs_cnt[3]_i_3_n_0 ),
        .I1(\regl_dqs_cnt[3]_i_4_n_0 ),
        .I2(regl_dqs_cnt[2]),
        .I3(regl_dqs_cnt[1]),
        .I4(regl_dqs_cnt[0]),
        .I5(regl_dqs_cnt[3]),
        .O(\regl_dqs_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \regl_dqs_cnt[3]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I1(\done_cnt_reg_n_0_[1] ),
        .I2(\done_cnt_reg_n_0_[0] ),
        .I3(\done_cnt_reg_n_0_[2] ),
        .I4(\done_cnt_reg_n_0_[3] ),
        .O(\regl_dqs_cnt[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT5 #(
    .INIT(32'h55555554)) 
    \regl_dqs_cnt[3]_i_4 
       (.I0(rstdiv0_sync_r1_reg_rep__24_0),
        .I1(\done_cnt_reg_n_0_[2] ),
        .I2(\done_cnt_reg_n_0_[3] ),
        .I3(\done_cnt_reg_n_0_[0] ),
        .I4(\done_cnt_reg_n_0_[1] ),
        .O(\regl_dqs_cnt[3]_i_4_n_0 ));
  FDRE \regl_dqs_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(regl_dqs_cnt[0]),
        .Q(regl_dqs_cnt_r[0]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(regl_dqs_cnt[1]),
        .Q(regl_dqs_cnt_r[1]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(regl_dqs_cnt[2]),
        .Q(regl_dqs_cnt_r[2]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(regl_dqs_cnt[3]),
        .Q(regl_dqs_cnt_r[3]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[0] 
       (.C(CLK),
        .CE(\regl_dqs_cnt[3]_i_1_n_0 ),
        .D(\regl_dqs_cnt[0]_i_1_n_0 ),
        .Q(regl_dqs_cnt[0]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[1] 
       (.C(CLK),
        .CE(\regl_dqs_cnt[3]_i_1_n_0 ),
        .D(\regl_dqs_cnt[1]_i_1_n_0 ),
        .Q(regl_dqs_cnt[1]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[2] 
       (.C(CLK),
        .CE(\regl_dqs_cnt[3]_i_1_n_0 ),
        .D(\regl_dqs_cnt[2]_i_1_n_0 ),
        .Q(regl_dqs_cnt[2]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[3] 
       (.C(CLK),
        .CE(\regl_dqs_cnt[3]_i_1_n_0 ),
        .D(\regl_dqs_cnt[3]_i_2_n_0 ),
        .Q(regl_dqs_cnt[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT5 #(
    .INIT(32'h000000AE)) 
    reset_if_i_1
       (.I0(reset_if),
        .I1(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I2(prbs_last_byte_done_r),
        .I3(rstdiv0_sync_r1_reg_rep__24_0),
        .I4(reset_if_r9),
        .O(reset_if_reg));
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[0]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(right_edge_taps_r[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(right_edge_taps_r[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(right_edge_taps_r[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(right_edge_taps_r[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(right_edge_taps_r[4]));
  LUT5 #(
    .INIT(32'hAAEAAAAA)) 
    \right_edge_taps_r[5]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\first_edge_taps_r[5]_i_3_n_0 ),
        .I2(found_stable_eye_last_r),
        .I3(found_first_edge_r_reg_n_0),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\right_edge_taps_r[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[5]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .O(right_edge_taps_r[5]));
  FDRE \right_edge_taps_r_reg[0] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[0]),
        .Q(\right_edge_taps_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \right_edge_taps_r_reg[1] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[1]),
        .Q(\right_edge_taps_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \right_edge_taps_r_reg[2] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[2]),
        .Q(\right_edge_taps_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \right_edge_taps_r_reg[3] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[3]),
        .Q(\right_edge_taps_r_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \right_edge_taps_r_reg[4] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[4]),
        .Q(\right_edge_taps_r_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \right_edge_taps_r_reg[5] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[5]),
        .Q(\right_edge_taps_r_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT6 #(
    .INIT(64'h3266666644444444)) 
    \rnk_cnt_r[0]_i_1__0 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .I4(prech_done),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\rnk_cnt_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h3C78787850505050)) 
    \rnk_cnt_r[1]_i_1__0 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[32] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\FSM_onehot_cal1_state_r_reg[0]_0 ),
        .I4(prech_done),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\rnk_cnt_r[1]_i_1__0_n_0 ));
  FDRE \rnk_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[0]_i_1__0_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  FDRE \rnk_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[1]_i_1__0_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT5 #(
    .INIT(32'h0000EA00)) 
    samp_cnt_done_r_i_1
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(samp_cnt_done_r_i_2_n_0),
        .I2(samp_cnt_done_r_i_3_n_0),
        .I3(samp_edge_cnt0_en_r),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .O(samp_cnt_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    samp_cnt_done_r_i_2
       (.I0(samp_edge_cnt1_r_reg[10]),
        .I1(samp_edge_cnt1_r_reg[7]),
        .I2(samp_edge_cnt1_r_reg[11]),
        .I3(samp_edge_cnt1_r_reg[4]),
        .I4(samp_edge_cnt1_r_reg[0]),
        .I5(samp_edge_cnt1_r_reg[8]),
        .O(samp_cnt_done_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    samp_cnt_done_r_i_3
       (.I0(samp_edge_cnt1_r_reg[1]),
        .I1(samp_edge_cnt1_r_reg[3]),
        .I2(samp_edge_cnt1_r_reg[5]),
        .I3(samp_edge_cnt1_r_reg[6]),
        .I4(samp_edge_cnt1_r_reg[9]),
        .I5(samp_edge_cnt1_r_reg[2]),
        .O(samp_cnt_done_r_i_3_n_0));
  FDRE samp_cnt_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(samp_cnt_done_r_i_1_n_0),
        .Q(samp_cnt_done_r_reg_n_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    samp_edge_cnt0_en_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[17] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[13] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(pb_detect_edge));
  FDRE samp_edge_cnt0_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pb_detect_edge),
        .Q(samp_edge_cnt0_en_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \samp_edge_cnt0_r[0]_i_3 
       (.I0(samp_edge_cnt0_r_reg[0]),
        .O(\samp_edge_cnt0_r[0]_i_3_n_0 ));
  FDRE \samp_edge_cnt0_r_reg[0] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_0 ),
        .Q(samp_edge_cnt0_r_reg[0]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[10] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[10]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[10]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[11] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[11]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[11]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[1] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[1]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[1]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \samp_edge_cnt0_r_reg[1]_i_2_CARRY4 
       (.CI(1'b0),
        .CO({\samp_edge_cnt0_r_reg[4]_i_2_n_0 ,\samp_edge_cnt0_r_reg[3]_i_2_n_0 ,\samp_edge_cnt0_r_reg[2]_i_2_n_0 ,\samp_edge_cnt0_r_reg[1]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\samp_edge_cnt0_r_reg[3]_i_1_n_0 ,\samp_edge_cnt0_r_reg[2]_i_1_n_0 ,\samp_edge_cnt0_r_reg[1]_i_1_n_0 ,\samp_edge_cnt0_r_reg[0]_i_2_n_0 }),
        .S({samp_edge_cnt0_r_reg[3:1],\samp_edge_cnt0_r[0]_i_3_n_0 }));
  FDRE \samp_edge_cnt0_r_reg[2] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[2]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[2]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[3] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[3]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[3]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[4] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[4]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[5] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[5]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[5]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \samp_edge_cnt0_r_reg[5]_i_2_CARRY4 
       (.CI(\samp_edge_cnt0_r_reg[4]_i_2_n_0 ),
        .CO({\samp_edge_cnt0_r_reg[8]_i_2_n_0 ,\samp_edge_cnt0_r_reg[7]_i_2_n_0 ,\samp_edge_cnt0_r_reg[6]_i_2_n_0 ,\samp_edge_cnt0_r_reg[5]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt0_r_reg[7]_i_1_n_0 ,\samp_edge_cnt0_r_reg[6]_i_1_n_0 ,\samp_edge_cnt0_r_reg[5]_i_1_n_0 ,\samp_edge_cnt0_r_reg[4]_i_1_n_0 }),
        .S(samp_edge_cnt0_r_reg[7:4]));
  FDRE \samp_edge_cnt0_r_reg[6] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[6]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[6]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[7] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[7]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[7]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[8] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[8]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt0_r_reg[9] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[9]_i_1_n_0 ),
        .Q(samp_edge_cnt0_r_reg[9]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \samp_edge_cnt0_r_reg[9]_i_2_CARRY4 
       (.CI(\samp_edge_cnt0_r_reg[8]_i_2_n_0 ),
        .CO({\NLW_samp_edge_cnt0_r_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\samp_edge_cnt0_r_reg[10]_i_2_n_0 ,\samp_edge_cnt0_r_reg[9]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({\NLW_samp_edge_cnt0_r_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt0_r_reg[11]_i_1_n_0 ,\samp_edge_cnt0_r_reg[10]_i_1_n_0 ,\samp_edge_cnt0_r_reg[9]_i_1_n_0 ,\samp_edge_cnt0_r_reg[8]_i_1_n_0 }),
        .S(samp_edge_cnt0_r_reg[11:8]));
  LUT3 #(
    .INIT(8'h20)) 
    samp_edge_cnt1_en_r_i_1
       (.I0(samp_edge_cnt1_en_r_i_2_n_0),
        .I1(samp_edge_cnt0_r_reg[7]),
        .I2(samp_edge_cnt1_en_r_i_3_n_0),
        .O(samp_edge_cnt1_en_r0));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    samp_edge_cnt1_en_r_i_2
       (.I0(samp_edge_cnt0_r_reg[4]),
        .I1(sr_valid_r2),
        .I2(samp_edge_cnt0_r_reg[3]),
        .I3(samp_edge_cnt0_r_reg[10]),
        .I4(samp_edge_cnt0_r_reg[1]),
        .I5(samp_edge_cnt0_r_reg[9]),
        .O(samp_edge_cnt1_en_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    samp_edge_cnt1_en_r_i_3
       (.I0(samp_edge_cnt0_r_reg[6]),
        .I1(samp_edge_cnt0_r_reg[11]),
        .I2(samp_edge_cnt0_r_reg[0]),
        .I3(samp_edge_cnt0_r_reg[5]),
        .I4(samp_edge_cnt0_r_reg[8]),
        .I5(samp_edge_cnt0_r_reg[2]),
        .O(samp_edge_cnt1_en_r_i_3_n_0));
  FDRE samp_edge_cnt1_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(samp_edge_cnt1_en_r0),
        .Q(samp_edge_cnt1_en_r),
        .R(rstdiv0_sync_r1_reg_rep__2));
  LUT1 #(
    .INIT(2'h1)) 
    \samp_edge_cnt1_r[0]_i_2 
       (.I0(samp_edge_cnt1_r_reg[0]),
        .O(\samp_edge_cnt1_r[0]_i_2_n_0 ));
  FDRE \samp_edge_cnt1_r_reg[0] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[0]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[10] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[10]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[10]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[11] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[11]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[11]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[1] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[1]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[1]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \samp_edge_cnt1_r_reg[1]_i_2_CARRY4 
       (.CI(1'b0),
        .CO({\samp_edge_cnt1_r_reg[4]_i_2_n_0 ,\samp_edge_cnt1_r_reg[3]_i_2_n_0 ,\samp_edge_cnt1_r_reg[2]_i_2_n_0 ,\samp_edge_cnt1_r_reg[1]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\samp_edge_cnt1_r_reg[3]_i_1_n_0 ,\samp_edge_cnt1_r_reg[2]_i_1_n_0 ,\samp_edge_cnt1_r_reg[1]_i_1_n_0 ,\samp_edge_cnt1_r_reg[0]_i_1_n_0 }),
        .S({samp_edge_cnt1_r_reg[3:1],\samp_edge_cnt1_r[0]_i_2_n_0 }));
  FDRE \samp_edge_cnt1_r_reg[2] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[2]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[2]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[3] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[3]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[3]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[4] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[4]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[5] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[5]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[5]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \samp_edge_cnt1_r_reg[5]_i_2_CARRY4 
       (.CI(\samp_edge_cnt1_r_reg[4]_i_2_n_0 ),
        .CO({\samp_edge_cnt1_r_reg[8]_i_2_n_0 ,\samp_edge_cnt1_r_reg[7]_i_2_n_0 ,\samp_edge_cnt1_r_reg[6]_i_2_n_0 ,\samp_edge_cnt1_r_reg[5]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt1_r_reg[7]_i_1_n_0 ,\samp_edge_cnt1_r_reg[6]_i_1_n_0 ,\samp_edge_cnt1_r_reg[5]_i_1_n_0 ,\samp_edge_cnt1_r_reg[4]_i_1_n_0 }),
        .S(samp_edge_cnt1_r_reg[7:4]));
  FDRE \samp_edge_cnt1_r_reg[6] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[6]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[6]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[7] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[7]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[7]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[8] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[8]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  FDRE \samp_edge_cnt1_r_reg[9] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[9]_i_1_n_0 ),
        .Q(samp_edge_cnt1_r_reg[9]),
        .R(rstdiv0_sync_r1_reg_rep__24));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \samp_edge_cnt1_r_reg[9]_i_2_CARRY4 
       (.CI(\samp_edge_cnt1_r_reg[8]_i_2_n_0 ),
        .CO({\NLW_samp_edge_cnt1_r_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\samp_edge_cnt1_r_reg[10]_i_2_n_0 ,\samp_edge_cnt1_r_reg[9]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({\NLW_samp_edge_cnt1_r_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt1_r_reg[11]_i_1_n_0 ,\samp_edge_cnt1_r_reg[10]_i_1_n_0 ,\samp_edge_cnt1_r_reg[9]_i_1_n_0 ,\samp_edge_cnt1_r_reg[8]_i_1_n_0 }),
        .S(samp_edge_cnt1_r_reg[11:8]));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \second_edge_taps_r[0]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(\second_edge_taps_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \second_edge_taps_r[1]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(\second_edge_taps_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \second_edge_taps_r[2]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(\second_edge_taps_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \second_edge_taps_r[3]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\second_edge_taps_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \second_edge_taps_r[4]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(\second_edge_taps_r[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \second_edge_taps_r[5]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\second_edge_taps_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    \second_edge_taps_r[5]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(found_stable_eye_last_r),
        .I2(found_first_edge_r_reg_n_0),
        .I3(\first_edge_taps_r[5]_i_3_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .O(\second_edge_taps_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \second_edge_taps_r[5]_i_3 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\second_edge_taps_r[5]_i_3_n_0 ));
  FDRE \second_edge_taps_r_reg[0] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[0]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[0] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[1] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[1]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[1] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[2] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[2]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[2] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[3] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[3]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[3] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[4] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[4]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[4] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[5] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[5]_i_3_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[5] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE sr_valid_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sr_valid_r_reg_n_0),
        .Q(sr_valid_r1),
        .R(1'b0));
  FDRE sr_valid_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sr_valid_r1),
        .Q(sr_valid_r2),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    sr_valid_r_i_1
       (.I0(rd_active_r),
        .I1(rdlvl_stg1_start_reg),
        .I2(cnt_shift_r_reg__0[2]),
        .I3(cnt_shift_r_reg__0[3]),
        .I4(cnt_shift_r_reg__0[1]),
        .I5(cnt_shift_r_reg__0[0]),
        .O(sr_valid_r_i_1_n_0));
  FDRE sr_valid_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sr_valid_r_i_1_n_0),
        .Q(sr_valid_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__18));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \stg1_wr_rd_cnt[3]_i_2 
       (.I0(rstdiv0_sync_r1_reg_rep__22),
        .I1(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I2(stg1_wr_done),
        .O(\stg1_wr_rd_cnt_reg[3] ));
  LUT4 #(
    .INIT(16'h00F4)) 
    store_sr_r_i_1
       (.I0(sr_valid_r_reg_n_0),
        .I1(store_sr_r_reg_n_0),
        .I2(store_sr_req_r_reg_n_0),
        .I3(rstdiv0_sync_r1_reg_rep__23),
        .O(store_sr_r_i_1_n_0));
  FDRE store_sr_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(store_sr_r_i_1_n_0),
        .Q(store_sr_r_reg_n_0),
        .R(1'b0));
  FDRE store_sr_req_pulsed_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .Q(store_sr_req_pulsed_r__0),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT5 #(
    .INIT(32'h444F4444)) 
    store_sr_req_r_i_1
       (.I0(store_sr_req_pulsed_r__0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[19] ),
        .I2(cal1_wait_r),
        .I3(\pi_counter_read_val_reg[4]_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[2] ),
        .O(store_sr_req_r));
  FDRE store_sr_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(store_sr_req_r),
        .Q(store_sr_req_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__1));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \tap_cnt_cpt_r[1]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(\tap_cnt_cpt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT4 #(
    .INIT(16'h6CC9)) 
    \tap_cnt_cpt_r[2]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT5 #(
    .INIT(32'h6CCCCCC9)) 
    \tap_cnt_cpt_r[3]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(p_0_in[3]));
  LUT6 #(
    .INIT(64'h6CCCCCCCCCCCCCC9)) 
    \tap_cnt_cpt_r[4]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(p_0_in[4]));
  LUT4 #(
    .INIT(16'hAA8A)) 
    \tap_cnt_cpt_r[5]_i_2 
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I2(\tap_cnt_cpt_r[5]_i_4_n_0 ),
        .I3(cal1_dlyinc_cpt_r_reg_n_0),
        .O(\tap_cnt_cpt_r[5]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h6F60)) 
    \tap_cnt_cpt_r[5]_i_3 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(tap_limit_cpt_r_i_2_n_0),
        .I2(cal1_dlyinc_cpt_r_reg_n_0),
        .I3(\second_edge_taps_r[5]_i_3_n_0 ),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \tap_cnt_cpt_r[5]_i_4 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\tap_cnt_cpt_r[5]_i_4_n_0 ));
  FDRE \tap_cnt_cpt_r_reg[0] 
       (.C(CLK),
        .CE(\tap_cnt_cpt_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[0]_i_1_n_0 ),
        .Q(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__24_2));
  FDRE \tap_cnt_cpt_r_reg[1] 
       (.C(CLK),
        .CE(\tap_cnt_cpt_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r[1]_i_1_n_0 ),
        .Q(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__24_2));
  FDRE \tap_cnt_cpt_r_reg[2] 
       (.C(CLK),
        .CE(\tap_cnt_cpt_r[5]_i_2_n_0 ),
        .D(p_0_in[2]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__24_2));
  FDRE \tap_cnt_cpt_r_reg[3] 
       (.C(CLK),
        .CE(\tap_cnt_cpt_r[5]_i_2_n_0 ),
        .D(p_0_in[3]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__24_2));
  FDRE \tap_cnt_cpt_r_reg[4] 
       (.C(CLK),
        .CE(\tap_cnt_cpt_r[5]_i_2_n_0 ),
        .D(p_0_in[4]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__24_2));
  FDRE \tap_cnt_cpt_r_reg[5] 
       (.C(CLK),
        .CE(\tap_cnt_cpt_r[5]_i_2_n_0 ),
        .D(p_0_in[5]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__24_2));
  LUT6 #(
    .INIT(64'h00000000000000EA)) 
    tap_limit_cpt_r_i_1
       (.I0(tap_limit_cpt_r),
        .I1(tap_limit_cpt_r_i_2_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I3(tap_limit_cpt_r_i_3_n_0),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .I5(idelay_tap_limit_r_reg_0),
        .O(tap_limit_cpt_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    tap_limit_cpt_r_i_2
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(tap_limit_cpt_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    tap_limit_cpt_r_i_3
       (.I0(\cal1_state_r1_reg_n_0_[5] ),
        .I1(\cal1_state_r1_reg_n_0_[0] ),
        .I2(\cal1_state_r1_reg_n_0_[2] ),
        .I3(\cal1_state_r1_reg_n_0_[4] ),
        .I4(\cal1_state_r1_reg_n_0_[3] ),
        .I5(\cal1_state_r1_reg_n_0_[1] ),
        .O(tap_limit_cpt_r_i_3_n_0));
  FDRE tap_limit_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tap_limit_cpt_r_i_1_n_0),
        .Q(tap_limit_cpt_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt_r[0]_i_1__0 
       (.I0(wait_cnt_r_reg__0__0[0]),
        .O(wait_cnt_r0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt_r[1]_i_1__0 
       (.I0(wait_cnt_r_reg__0__0[1]),
        .I1(wait_cnt_r_reg__0__0[0]),
        .O(\wait_cnt_r[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt_r[2]_i_1__0 
       (.I0(wait_cnt_r_reg__0__0[2]),
        .I1(wait_cnt_r_reg__0__0[0]),
        .I2(wait_cnt_r_reg__0__0[1]),
        .O(wait_cnt_r0__0[2]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \wait_cnt_r[3]_i_2 
       (.I0(dqs_po_dec_done_r2),
        .I1(wait_cnt_r_reg__0__0[2]),
        .I2(wait_cnt_r_reg__0__0[3]),
        .I3(wait_cnt_r_reg__0__0[1]),
        .I4(wait_cnt_r_reg__0__0[0]),
        .O(wait_cnt_r0));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt_r[3]_i_3__0 
       (.I0(wait_cnt_r_reg__0__0[3]),
        .I1(wait_cnt_r_reg__0__0[2]),
        .I2(wait_cnt_r_reg__0__0[1]),
        .I3(wait_cnt_r_reg__0__0[0]),
        .O(wait_cnt_r0__0[3]));
  FDRE \wait_cnt_r_reg[0] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[0]),
        .Q(wait_cnt_r_reg__0__0[0]),
        .R(rstdiv0_sync_r1_reg_rep__24_4));
  FDRE \wait_cnt_r_reg[1] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(\wait_cnt_r[1]_i_1__0_n_0 ),
        .Q(wait_cnt_r_reg__0__0[1]),
        .R(rstdiv0_sync_r1_reg_rep__24_4));
  FDRE \wait_cnt_r_reg[2] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[2]),
        .Q(wait_cnt_r_reg__0__0[2]),
        .R(rstdiv0_sync_r1_reg_rep__24_4));
  FDSE \wait_cnt_r_reg[3] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[3]),
        .Q(wait_cnt_r_reg__0__0[3]),
        .S(rstdiv0_sync_r1_reg_rep__24_4));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[441]_i_1 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .O(D[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[441]_rep_i_1 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[441]_rep ));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[505]_i_1 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(first_wrcal_pat_r),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[511]_i_1 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(wrcal_done_reg),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511] ));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[511]_i_2 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(first_wrcal_pat_r),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[61]_i_1 
       (.I0(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447] ),
        .I1(first_rdlvl_pat_r),
        .O(D[0]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_tempmon" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_tempmon
   (tempmon_pi_f_inc_r_reg,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    D,
    \calib_zero_inputs_reg[0] ,
    \gen_byte_sel_div2.calib_in_common_reg ,
    E,
    \calib_sel_reg[3] ,
    CLK,
    rstdiv0_sync_r1_reg_rep__13,
    tempmon_sample_en,
    rstdiv0_sync_r1_reg_rep__15,
    calib_complete,
    Q,
    pi_fine_dly_dec_done_reg,
    fine_adjust_done,
    rd_data_offset_cal_done,
    po_ck_addr_cmd_delay_done,
    rstdiv0_sync_r1_reg_rep__24,
    wr_level_done_reg,
    rdlvl_stg1_done_reg,
    wrcal_done_reg,
    \pi_rst_stg1_cal_reg[0] ,
    dqs_po_dec_done_reg,
    \pi_rst_stg1_cal_reg[0]_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    delay_done_r4_reg,
    dqs_po_dec_done,
    pi_fine_dly_dec_done,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2] ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[0] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1] ,
    \device_temp_r_reg[11] ,
    rstdiv0_sync_r1_reg_rep__16,
    rstdiv0_sync_r1_reg_rep__14,
    rstdiv0_sync_r1_reg_rep__17);
  output tempmon_pi_f_inc_r_reg;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  output [2:0]D;
  output \calib_zero_inputs_reg[0] ;
  output \gen_byte_sel_div2.calib_in_common_reg ;
  output [0:0]E;
  output [1:0]\calib_sel_reg[3] ;
  input CLK;
  input [0:0]rstdiv0_sync_r1_reg_rep__13;
  input tempmon_sample_en;
  input [0:0]rstdiv0_sync_r1_reg_rep__15;
  input calib_complete;
  input [3:0]Q;
  input pi_fine_dly_dec_done_reg;
  input fine_adjust_done;
  input rd_data_offset_cal_done;
  input po_ck_addr_cmd_delay_done;
  input rstdiv0_sync_r1_reg_rep__24;
  input wr_level_done_reg;
  input rdlvl_stg1_done_reg;
  input wrcal_done_reg;
  input \pi_rst_stg1_cal_reg[0] ;
  input dqs_po_dec_done_reg;
  input \pi_rst_stg1_cal_reg[0]_0 ;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input delay_done_r4_reg;
  input dqs_po_dec_done;
  input pi_fine_dly_dec_done;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[2] ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  input [11:0]\device_temp_r_reg[11] ;
  input [0:0]rstdiv0_sync_r1_reg_rep__16;
  input [0:0]rstdiv0_sync_r1_reg_rep__14;
  input [0:0]rstdiv0_sync_r1_reg_rep__17;

  wire CLK;
  wire [2:0]D;
  wire [0:0]E;
  wire [3:0]Q;
  wire calib_complete;
  wire [1:0]\calib_sel_reg[3] ;
  wire \calib_zero_inputs[2]_i_2_n_0 ;
  wire \calib_zero_inputs_reg[0] ;
  wire delay_done_r4_reg;
  wire [11:0]device_temp_101;
  wire [11:0]device_temp_init;
  wire \device_temp_init[11]_i_1_n_0 ;
  wire \device_temp_init[11]_i_2_n_0 ;
  wire \device_temp_init[11]_i_3_n_0 ;
  wire [11:0]\device_temp_r_reg[11] ;
  wire dqs_po_dec_done;
  wire dqs_po_dec_done_reg;
  wire fine_adjust_done;
  wire [11:0]four_dec_min_limit;
  wire \four_dec_min_limit[11]_i_2_n_0 ;
  wire \four_dec_min_limit[11]_i_3_n_0 ;
  wire \four_dec_min_limit[5]_i_2_n_0 ;
  wire \four_dec_min_limit[5]_i_3_n_0 ;
  wire \four_dec_min_limit[5]_i_4_n_0 ;
  wire \four_dec_min_limit[5]_i_5_n_0 ;
  wire \four_dec_min_limit[9]_i_2_n_0 ;
  wire \four_dec_min_limit[9]_i_3_n_0 ;
  wire \four_dec_min_limit[9]_i_4_n_0 ;
  wire \four_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]four_dec_min_limit_nxt;
  wire \four_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]four_inc_max_limit;
  wire \four_inc_max_limit[11]_i_2_n_0 ;
  wire \four_inc_max_limit[11]_i_3_n_0 ;
  wire \four_inc_max_limit[11]_i_4_n_0 ;
  wire \four_inc_max_limit[11]_i_5_n_0 ;
  wire \four_inc_max_limit[3]_i_2_n_0 ;
  wire \four_inc_max_limit[3]_i_3_n_0 ;
  wire \four_inc_max_limit[3]_i_4_n_0 ;
  wire \four_inc_max_limit[3]_i_5_n_0 ;
  wire \four_inc_max_limit[7]_i_2_n_0 ;
  wire \four_inc_max_limit[7]_i_3_n_0 ;
  wire \four_inc_max_limit[7]_i_4_n_0 ;
  wire \four_inc_max_limit[7]_i_5_n_0 ;
  wire [11:0]four_inc_max_limit_nxt;
  wire \four_inc_max_limit_reg[11]_i_1_n_1 ;
  wire \four_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \four_inc_max_limit_reg[3]_i_1_n_0 ;
  wire \four_inc_max_limit_reg[3]_i_1_n_1 ;
  wire \four_inc_max_limit_reg[3]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[3]_i_1_n_3 ;
  wire \four_inc_max_limit_reg[7]_i_1_n_0 ;
  wire \four_inc_max_limit_reg[7]_i_1_n_1 ;
  wire \four_inc_max_limit_reg[7]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[7]_i_1_n_3 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2] ;
  wire [11:0]neutral_max_limit;
  wire \neutral_max_limit[11]_i_2_n_0 ;
  wire \neutral_max_limit[11]_i_3_n_0 ;
  wire \neutral_max_limit[11]_i_4_n_0 ;
  wire \neutral_max_limit[11]_i_5_n_0 ;
  wire \neutral_max_limit[3]_i_2_n_0 ;
  wire \neutral_max_limit[3]_i_3_n_0 ;
  wire \neutral_max_limit[3]_i_4_n_0 ;
  wire \neutral_max_limit[3]_i_5_n_0 ;
  wire \neutral_max_limit[7]_i_2_n_0 ;
  wire \neutral_max_limit[7]_i_3_n_0 ;
  wire \neutral_max_limit[7]_i_4_n_0 ;
  wire \neutral_max_limit[7]_i_5_n_0 ;
  wire [11:0]neutral_max_limit_nxt;
  wire \neutral_max_limit_reg[11]_i_1_n_1 ;
  wire \neutral_max_limit_reg[11]_i_1_n_2 ;
  wire \neutral_max_limit_reg[11]_i_1_n_3 ;
  wire \neutral_max_limit_reg[3]_i_1_n_0 ;
  wire \neutral_max_limit_reg[3]_i_1_n_1 ;
  wire \neutral_max_limit_reg[3]_i_1_n_2 ;
  wire \neutral_max_limit_reg[3]_i_1_n_3 ;
  wire \neutral_max_limit_reg[7]_i_1_n_0 ;
  wire \neutral_max_limit_reg[7]_i_1_n_1 ;
  wire \neutral_max_limit_reg[7]_i_1_n_2 ;
  wire \neutral_max_limit_reg[7]_i_1_n_3 ;
  wire [11:0]neutral_min_limit;
  wire \neutral_min_limit[11]_i_2_n_0 ;
  wire \neutral_min_limit[11]_i_3_n_0 ;
  wire \neutral_min_limit[5]_i_2_n_0 ;
  wire \neutral_min_limit[5]_i_3_n_0 ;
  wire \neutral_min_limit[5]_i_4_n_0 ;
  wire \neutral_min_limit[5]_i_5_n_0 ;
  wire \neutral_min_limit[9]_i_2_n_0 ;
  wire \neutral_min_limit[9]_i_3_n_0 ;
  wire \neutral_min_limit[9]_i_4_n_0 ;
  wire \neutral_min_limit[9]_i_5_n_0 ;
  wire [11:2]neutral_min_limit_nxt;
  wire \neutral_min_limit_reg[11]_i_1_n_3 ;
  wire \neutral_min_limit_reg[5]_i_1_n_0 ;
  wire \neutral_min_limit_reg[5]_i_1_n_1 ;
  wire \neutral_min_limit_reg[5]_i_1_n_2 ;
  wire \neutral_min_limit_reg[5]_i_1_n_3 ;
  wire \neutral_min_limit_reg[9]_i_1_n_0 ;
  wire \neutral_min_limit_reg[9]_i_1_n_1 ;
  wire \neutral_min_limit_reg[9]_i_1_n_2 ;
  wire \neutral_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]one_dec_max_limit;
  wire \one_dec_max_limit[11]_i_2_n_0 ;
  wire \one_dec_max_limit[11]_i_3_n_0 ;
  wire \one_dec_max_limit[11]_i_4_n_0 ;
  wire \one_dec_max_limit[11]_i_5_n_0 ;
  wire \one_dec_max_limit[3]_i_2_n_0 ;
  wire \one_dec_max_limit[3]_i_3_n_0 ;
  wire \one_dec_max_limit[3]_i_4_n_0 ;
  wire \one_dec_max_limit[3]_i_5_n_0 ;
  wire \one_dec_max_limit[7]_i_2_n_0 ;
  wire \one_dec_max_limit[7]_i_3_n_0 ;
  wire \one_dec_max_limit[7]_i_4_n_0 ;
  wire \one_dec_max_limit[7]_i_5_n_0 ;
  wire [11:0]one_dec_max_limit_nxt;
  wire \one_dec_max_limit_reg[11]_i_1_n_1 ;
  wire \one_dec_max_limit_reg[11]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[11]_i_1_n_3 ;
  wire \one_dec_max_limit_reg[3]_i_1_n_0 ;
  wire \one_dec_max_limit_reg[3]_i_1_n_1 ;
  wire \one_dec_max_limit_reg[3]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[3]_i_1_n_3 ;
  wire \one_dec_max_limit_reg[7]_i_1_n_0 ;
  wire \one_dec_max_limit_reg[7]_i_1_n_1 ;
  wire \one_dec_max_limit_reg[7]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[7]_i_1_n_3 ;
  wire [11:0]one_dec_min_limit;
  wire \one_dec_min_limit[11]_i_2_n_0 ;
  wire \one_dec_min_limit[11]_i_3_n_0 ;
  wire \one_dec_min_limit[5]_i_2_n_0 ;
  wire \one_dec_min_limit[5]_i_3_n_0 ;
  wire \one_dec_min_limit[5]_i_4_n_0 ;
  wire \one_dec_min_limit[5]_i_5_n_0 ;
  wire \one_dec_min_limit[9]_i_2_n_0 ;
  wire \one_dec_min_limit[9]_i_3_n_0 ;
  wire \one_dec_min_limit[9]_i_4_n_0 ;
  wire \one_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]one_dec_min_limit_nxt;
  wire \one_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]one_inc_max_limit;
  wire \one_inc_max_limit[11]_i_2_n_0 ;
  wire \one_inc_max_limit[11]_i_3_n_0 ;
  wire \one_inc_max_limit[11]_i_4_n_0 ;
  wire \one_inc_max_limit[11]_i_5_n_0 ;
  wire \one_inc_max_limit[3]_i_2_n_0 ;
  wire \one_inc_max_limit[3]_i_3_n_0 ;
  wire \one_inc_max_limit[3]_i_4_n_0 ;
  wire \one_inc_max_limit[3]_i_5_n_0 ;
  wire \one_inc_max_limit[7]_i_2_n_0 ;
  wire \one_inc_max_limit[7]_i_3_n_0 ;
  wire \one_inc_max_limit[7]_i_4_n_0 ;
  wire \one_inc_max_limit[7]_i_5_n_0 ;
  wire [11:0]one_inc_max_limit_nxt;
  wire \one_inc_max_limit_reg[11]_i_1_n_1 ;
  wire \one_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \one_inc_max_limit_reg[3]_i_1_n_0 ;
  wire \one_inc_max_limit_reg[3]_i_1_n_1 ;
  wire \one_inc_max_limit_reg[3]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[3]_i_1_n_3 ;
  wire \one_inc_max_limit_reg[7]_i_1_n_0 ;
  wire \one_inc_max_limit_reg[7]_i_1_n_1 ;
  wire \one_inc_max_limit_reg[7]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[7]_i_1_n_3 ;
  wire [11:0]one_inc_min_limit;
  wire \one_inc_min_limit[11]_i_2_n_0 ;
  wire \one_inc_min_limit[11]_i_3_n_0 ;
  wire \one_inc_min_limit[5]_i_2_n_0 ;
  wire \one_inc_min_limit[5]_i_3_n_0 ;
  wire \one_inc_min_limit[5]_i_4_n_0 ;
  wire \one_inc_min_limit[5]_i_5_n_0 ;
  wire \one_inc_min_limit[9]_i_2_n_0 ;
  wire \one_inc_min_limit[9]_i_3_n_0 ;
  wire \one_inc_min_limit[9]_i_4_n_0 ;
  wire \one_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]one_inc_min_limit_nxt;
  wire \one_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_3 ;
  wire p_0_in;
  wire pi_f_dec_i_2_n_0;
  wire pi_f_dec_i_3_n_0;
  wire pi_f_dec_i_4_n_0;
  wire pi_f_dec_i_5_n_0;
  wire pi_f_dec_nxt;
  wire pi_f_inc_i_2_n_0;
  wire pi_f_inc_i_5_n_0;
  wire pi_f_inc_i_6_n_0;
  wire pi_f_inc_i_7_n_0;
  wire pi_f_inc_i_8_n_0;
  wire pi_f_inc_i_9_n_0;
  wire pi_f_inc_nxt;
  wire pi_fine_dly_dec_done;
  wire pi_fine_dly_dec_done_reg;
  wire \pi_rst_stg1_cal_reg[0] ;
  wire \pi_rst_stg1_cal_reg[0]_0 ;
  wire po_ck_addr_cmd_delay_done;
  wire rd_data_offset_cal_done;
  wire rdlvl_stg1_done_reg;
  wire [0:0]rstdiv0_sync_r1_reg_rep__13;
  wire [0:0]rstdiv0_sync_r1_reg_rep__14;
  wire [0:0]rstdiv0_sync_r1_reg_rep__15;
  wire [0:0]rstdiv0_sync_r1_reg_rep__16;
  wire [0:0]rstdiv0_sync_r1_reg_rep__17;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire temp_cmp_four_dec_min_101;
  wire temp_cmp_four_dec_min_102;
  wire temp_cmp_four_dec_min_102_i_10_n_0;
  wire temp_cmp_four_dec_min_102_i_11_n_0;
  wire temp_cmp_four_dec_min_102_i_12_n_0;
  wire temp_cmp_four_dec_min_102_i_13_n_0;
  wire temp_cmp_four_dec_min_102_i_14_n_0;
  wire temp_cmp_four_dec_min_102_i_3_n_0;
  wire temp_cmp_four_dec_min_102_i_4_n_0;
  wire temp_cmp_four_dec_min_102_i_5_n_0;
  wire temp_cmp_four_dec_min_102_i_6_n_0;
  wire temp_cmp_four_dec_min_102_i_7_n_0;
  wire temp_cmp_four_dec_min_102_i_8_n_0;
  wire temp_cmp_four_dec_min_102_i_9_n_0;
  wire temp_cmp_four_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_four_inc_max_101;
  wire temp_cmp_four_inc_max_102;
  wire temp_cmp_four_inc_max_102_i_10_n_0;
  wire temp_cmp_four_inc_max_102_i_11_n_0;
  wire temp_cmp_four_inc_max_102_i_12_n_0;
  wire temp_cmp_four_inc_max_102_i_13_n_0;
  wire temp_cmp_four_inc_max_102_i_14_n_0;
  wire temp_cmp_four_inc_max_102_i_3_n_0;
  wire temp_cmp_four_inc_max_102_i_4_n_0;
  wire temp_cmp_four_inc_max_102_i_5_n_0;
  wire temp_cmp_four_inc_max_102_i_6_n_0;
  wire temp_cmp_four_inc_max_102_i_7_n_0;
  wire temp_cmp_four_inc_max_102_i_8_n_0;
  wire temp_cmp_four_inc_max_102_i_9_n_0;
  wire temp_cmp_four_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_neutral_max_101;
  wire temp_cmp_neutral_max_102;
  wire temp_cmp_neutral_max_102_i_10_n_0;
  wire temp_cmp_neutral_max_102_i_11_n_0;
  wire temp_cmp_neutral_max_102_i_12_n_0;
  wire temp_cmp_neutral_max_102_i_13_n_0;
  wire temp_cmp_neutral_max_102_i_14_n_0;
  wire temp_cmp_neutral_max_102_i_3_n_0;
  wire temp_cmp_neutral_max_102_i_4_n_0;
  wire temp_cmp_neutral_max_102_i_5_n_0;
  wire temp_cmp_neutral_max_102_i_6_n_0;
  wire temp_cmp_neutral_max_102_i_7_n_0;
  wire temp_cmp_neutral_max_102_i_8_n_0;
  wire temp_cmp_neutral_max_102_i_9_n_0;
  wire temp_cmp_neutral_max_102_reg_i_1_n_3;
  wire temp_cmp_neutral_max_102_reg_i_2_n_0;
  wire temp_cmp_neutral_max_102_reg_i_2_n_1;
  wire temp_cmp_neutral_max_102_reg_i_2_n_2;
  wire temp_cmp_neutral_max_102_reg_i_2_n_3;
  wire temp_cmp_neutral_min_101;
  wire temp_cmp_neutral_min_102;
  wire temp_cmp_neutral_min_102_i_10_n_0;
  wire temp_cmp_neutral_min_102_i_11_n_0;
  wire temp_cmp_neutral_min_102_i_12_n_0;
  wire temp_cmp_neutral_min_102_i_13_n_0;
  wire temp_cmp_neutral_min_102_i_14_n_0;
  wire temp_cmp_neutral_min_102_i_3_n_0;
  wire temp_cmp_neutral_min_102_i_4_n_0;
  wire temp_cmp_neutral_min_102_i_5_n_0;
  wire temp_cmp_neutral_min_102_i_6_n_0;
  wire temp_cmp_neutral_min_102_i_7_n_0;
  wire temp_cmp_neutral_min_102_i_8_n_0;
  wire temp_cmp_neutral_min_102_i_9_n_0;
  wire temp_cmp_neutral_min_102_reg_i_1_n_3;
  wire temp_cmp_neutral_min_102_reg_i_2_n_0;
  wire temp_cmp_neutral_min_102_reg_i_2_n_1;
  wire temp_cmp_neutral_min_102_reg_i_2_n_2;
  wire temp_cmp_neutral_min_102_reg_i_2_n_3;
  wire temp_cmp_one_dec_max_101;
  wire temp_cmp_one_dec_max_102;
  wire temp_cmp_one_dec_max_102_i_10_n_0;
  wire temp_cmp_one_dec_max_102_i_11_n_0;
  wire temp_cmp_one_dec_max_102_i_12_n_0;
  wire temp_cmp_one_dec_max_102_i_13_n_0;
  wire temp_cmp_one_dec_max_102_i_14_n_0;
  wire temp_cmp_one_dec_max_102_i_3_n_0;
  wire temp_cmp_one_dec_max_102_i_4_n_0;
  wire temp_cmp_one_dec_max_102_i_5_n_0;
  wire temp_cmp_one_dec_max_102_i_6_n_0;
  wire temp_cmp_one_dec_max_102_i_7_n_0;
  wire temp_cmp_one_dec_max_102_i_8_n_0;
  wire temp_cmp_one_dec_max_102_i_9_n_0;
  wire temp_cmp_one_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_one_dec_min_101;
  wire temp_cmp_one_dec_min_102;
  wire temp_cmp_one_dec_min_102_i_10_n_0;
  wire temp_cmp_one_dec_min_102_i_11_n_0;
  wire temp_cmp_one_dec_min_102_i_12_n_0;
  wire temp_cmp_one_dec_min_102_i_13_n_0;
  wire temp_cmp_one_dec_min_102_i_14_n_0;
  wire temp_cmp_one_dec_min_102_i_3_n_0;
  wire temp_cmp_one_dec_min_102_i_4_n_0;
  wire temp_cmp_one_dec_min_102_i_5_n_0;
  wire temp_cmp_one_dec_min_102_i_6_n_0;
  wire temp_cmp_one_dec_min_102_i_7_n_0;
  wire temp_cmp_one_dec_min_102_i_8_n_0;
  wire temp_cmp_one_dec_min_102_i_9_n_0;
  wire temp_cmp_one_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_one_inc_max_101;
  wire temp_cmp_one_inc_max_102;
  wire temp_cmp_one_inc_max_102_i_10_n_0;
  wire temp_cmp_one_inc_max_102_i_11_n_0;
  wire temp_cmp_one_inc_max_102_i_12_n_0;
  wire temp_cmp_one_inc_max_102_i_13_n_0;
  wire temp_cmp_one_inc_max_102_i_14_n_0;
  wire temp_cmp_one_inc_max_102_i_3_n_0;
  wire temp_cmp_one_inc_max_102_i_4_n_0;
  wire temp_cmp_one_inc_max_102_i_5_n_0;
  wire temp_cmp_one_inc_max_102_i_6_n_0;
  wire temp_cmp_one_inc_max_102_i_7_n_0;
  wire temp_cmp_one_inc_max_102_i_8_n_0;
  wire temp_cmp_one_inc_max_102_i_9_n_0;
  wire temp_cmp_one_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_one_inc_min_101;
  wire temp_cmp_one_inc_min_102;
  wire temp_cmp_one_inc_min_102_i_10_n_0;
  wire temp_cmp_one_inc_min_102_i_11_n_0;
  wire temp_cmp_one_inc_min_102_i_12_n_0;
  wire temp_cmp_one_inc_min_102_i_13_n_0;
  wire temp_cmp_one_inc_min_102_i_14_n_0;
  wire temp_cmp_one_inc_min_102_i_3_n_0;
  wire temp_cmp_one_inc_min_102_i_4_n_0;
  wire temp_cmp_one_inc_min_102_i_5_n_0;
  wire temp_cmp_one_inc_min_102_i_6_n_0;
  wire temp_cmp_one_inc_min_102_i_7_n_0;
  wire temp_cmp_one_inc_min_102_i_8_n_0;
  wire temp_cmp_one_inc_min_102_i_9_n_0;
  wire temp_cmp_one_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_3;
  wire temp_cmp_three_dec_max_101;
  wire temp_cmp_three_dec_max_102;
  wire temp_cmp_three_dec_max_102_i_10_n_0;
  wire temp_cmp_three_dec_max_102_i_11_n_0;
  wire temp_cmp_three_dec_max_102_i_12_n_0;
  wire temp_cmp_three_dec_max_102_i_13_n_0;
  wire temp_cmp_three_dec_max_102_i_14_n_0;
  wire temp_cmp_three_dec_max_102_i_3_n_0;
  wire temp_cmp_three_dec_max_102_i_4_n_0;
  wire temp_cmp_three_dec_max_102_i_5_n_0;
  wire temp_cmp_three_dec_max_102_i_6_n_0;
  wire temp_cmp_three_dec_max_102_i_7_n_0;
  wire temp_cmp_three_dec_max_102_i_8_n_0;
  wire temp_cmp_three_dec_max_102_i_9_n_0;
  wire temp_cmp_three_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_three_dec_min_101;
  wire temp_cmp_three_dec_min_102;
  wire temp_cmp_three_dec_min_102_i_10_n_0;
  wire temp_cmp_three_dec_min_102_i_11_n_0;
  wire temp_cmp_three_dec_min_102_i_12_n_0;
  wire temp_cmp_three_dec_min_102_i_13_n_0;
  wire temp_cmp_three_dec_min_102_i_14_n_0;
  wire temp_cmp_three_dec_min_102_i_3_n_0;
  wire temp_cmp_three_dec_min_102_i_4_n_0;
  wire temp_cmp_three_dec_min_102_i_5_n_0;
  wire temp_cmp_three_dec_min_102_i_6_n_0;
  wire temp_cmp_three_dec_min_102_i_7_n_0;
  wire temp_cmp_three_dec_min_102_i_8_n_0;
  wire temp_cmp_three_dec_min_102_i_9_n_0;
  wire temp_cmp_three_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_three_inc_max_101;
  wire temp_cmp_three_inc_max_102;
  wire temp_cmp_three_inc_max_102_i_10_n_0;
  wire temp_cmp_three_inc_max_102_i_11_n_0;
  wire temp_cmp_three_inc_max_102_i_12_n_0;
  wire temp_cmp_three_inc_max_102_i_13_n_0;
  wire temp_cmp_three_inc_max_102_i_14_n_0;
  wire temp_cmp_three_inc_max_102_i_3_n_0;
  wire temp_cmp_three_inc_max_102_i_4_n_0;
  wire temp_cmp_three_inc_max_102_i_5_n_0;
  wire temp_cmp_three_inc_max_102_i_6_n_0;
  wire temp_cmp_three_inc_max_102_i_7_n_0;
  wire temp_cmp_three_inc_max_102_i_8_n_0;
  wire temp_cmp_three_inc_max_102_i_9_n_0;
  wire temp_cmp_three_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_three_inc_min_101;
  wire temp_cmp_three_inc_min_102;
  wire temp_cmp_three_inc_min_102_i_10_n_0;
  wire temp_cmp_three_inc_min_102_i_11_n_0;
  wire temp_cmp_three_inc_min_102_i_12_n_0;
  wire temp_cmp_three_inc_min_102_i_13_n_0;
  wire temp_cmp_three_inc_min_102_i_14_n_0;
  wire temp_cmp_three_inc_min_102_i_3_n_0;
  wire temp_cmp_three_inc_min_102_i_4_n_0;
  wire temp_cmp_three_inc_min_102_i_5_n_0;
  wire temp_cmp_three_inc_min_102_i_6_n_0;
  wire temp_cmp_three_inc_min_102_i_7_n_0;
  wire temp_cmp_three_inc_min_102_i_8_n_0;
  wire temp_cmp_three_inc_min_102_i_9_n_0;
  wire temp_cmp_three_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_3;
  wire temp_cmp_two_dec_max_101;
  wire temp_cmp_two_dec_max_102;
  wire temp_cmp_two_dec_max_102_i_10_n_0;
  wire temp_cmp_two_dec_max_102_i_11_n_0;
  wire temp_cmp_two_dec_max_102_i_12_n_0;
  wire temp_cmp_two_dec_max_102_i_13_n_0;
  wire temp_cmp_two_dec_max_102_i_14_n_0;
  wire temp_cmp_two_dec_max_102_i_3_n_0;
  wire temp_cmp_two_dec_max_102_i_4_n_0;
  wire temp_cmp_two_dec_max_102_i_5_n_0;
  wire temp_cmp_two_dec_max_102_i_6_n_0;
  wire temp_cmp_two_dec_max_102_i_7_n_0;
  wire temp_cmp_two_dec_max_102_i_8_n_0;
  wire temp_cmp_two_dec_max_102_i_9_n_0;
  wire temp_cmp_two_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_two_dec_min_101;
  wire temp_cmp_two_dec_min_102;
  wire temp_cmp_two_dec_min_102_i_10_n_0;
  wire temp_cmp_two_dec_min_102_i_11_n_0;
  wire temp_cmp_two_dec_min_102_i_12_n_0;
  wire temp_cmp_two_dec_min_102_i_13_n_0;
  wire temp_cmp_two_dec_min_102_i_14_n_0;
  wire temp_cmp_two_dec_min_102_i_3_n_0;
  wire temp_cmp_two_dec_min_102_i_4_n_0;
  wire temp_cmp_two_dec_min_102_i_5_n_0;
  wire temp_cmp_two_dec_min_102_i_6_n_0;
  wire temp_cmp_two_dec_min_102_i_7_n_0;
  wire temp_cmp_two_dec_min_102_i_8_n_0;
  wire temp_cmp_two_dec_min_102_i_9_n_0;
  wire temp_cmp_two_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_two_inc_max_101;
  wire temp_cmp_two_inc_max_102;
  wire temp_cmp_two_inc_max_102_i_10_n_0;
  wire temp_cmp_two_inc_max_102_i_11_n_0;
  wire temp_cmp_two_inc_max_102_i_12_n_0;
  wire temp_cmp_two_inc_max_102_i_13_n_0;
  wire temp_cmp_two_inc_max_102_i_14_n_0;
  wire temp_cmp_two_inc_max_102_i_3_n_0;
  wire temp_cmp_two_inc_max_102_i_4_n_0;
  wire temp_cmp_two_inc_max_102_i_5_n_0;
  wire temp_cmp_two_inc_max_102_i_6_n_0;
  wire temp_cmp_two_inc_max_102_i_7_n_0;
  wire temp_cmp_two_inc_max_102_i_8_n_0;
  wire temp_cmp_two_inc_max_102_i_9_n_0;
  wire temp_cmp_two_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_two_inc_min_101;
  wire temp_cmp_two_inc_min_102;
  wire temp_cmp_two_inc_min_102_i_10_n_0;
  wire temp_cmp_two_inc_min_102_i_11_n_0;
  wire temp_cmp_two_inc_min_102_i_12_n_0;
  wire temp_cmp_two_inc_min_102_i_13_n_0;
  wire temp_cmp_two_inc_min_102_i_14_n_0;
  wire temp_cmp_two_inc_min_102_i_3_n_0;
  wire temp_cmp_two_inc_min_102_i_4_n_0;
  wire temp_cmp_two_inc_min_102_i_5_n_0;
  wire temp_cmp_two_inc_min_102_i_6_n_0;
  wire temp_cmp_two_inc_min_102_i_7_n_0;
  wire temp_cmp_two_inc_min_102_i_8_n_0;
  wire temp_cmp_two_inc_min_102_i_9_n_0;
  wire temp_cmp_two_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_3;
  wire temp_gte_one_dec_max;
  wire temp_gte_one_inc_max;
  wire temp_gte_three_inc_max;
  wire temp_lte_three_inc_min;
  wire tempmon_init_complete;
  wire tempmon_init_complete_i_1_n_0;
  wire tempmon_pi_f_inc_r_reg;
  wire tempmon_sample_en;
  wire tempmon_sample_en_101;
  wire tempmon_sample_en_102;
  wire [10:0]tempmon_state;
  wire \tempmon_state[0]_i_1_n_0 ;
  wire \tempmon_state[10]_i_10_n_0 ;
  wire \tempmon_state[10]_i_11_n_0 ;
  wire \tempmon_state[10]_i_12_n_0 ;
  wire \tempmon_state[10]_i_13_n_0 ;
  wire \tempmon_state[10]_i_14_n_0 ;
  wire \tempmon_state[10]_i_15_n_0 ;
  wire \tempmon_state[10]_i_1_n_0 ;
  wire \tempmon_state[10]_i_2_n_0 ;
  wire \tempmon_state[10]_i_3_n_0 ;
  wire \tempmon_state[10]_i_4_n_0 ;
  wire \tempmon_state[10]_i_5_n_0 ;
  wire \tempmon_state[10]_i_6_n_0 ;
  wire \tempmon_state[10]_i_7_n_0 ;
  wire \tempmon_state[10]_i_8_n_0 ;
  wire \tempmon_state[10]_i_9_n_0 ;
  wire \tempmon_state[1]_i_1_n_0 ;
  wire \tempmon_state[2]_i_1_n_0 ;
  wire \tempmon_state[3]_i_1_n_0 ;
  wire \tempmon_state[4]_i_1_n_0 ;
  wire \tempmon_state[5]_i_1_n_0 ;
  wire \tempmon_state[6]_i_1_n_0 ;
  wire \tempmon_state[7]_i_1_n_0 ;
  wire \tempmon_state[8]_i_1_n_0 ;
  wire \tempmon_state[9]_i_1_n_0 ;
  wire [11:0]three_dec_max_limit;
  wire \three_dec_max_limit[0]_i_1_n_0 ;
  wire \three_dec_max_limit[10]_i_1_n_0 ;
  wire \three_dec_max_limit[11]_i_1_n_0 ;
  wire \three_dec_max_limit[11]_i_3_n_0 ;
  wire \three_dec_max_limit[11]_i_4_n_0 ;
  wire \three_dec_max_limit[11]_i_5_n_0 ;
  wire \three_dec_max_limit[11]_i_6_n_0 ;
  wire \three_dec_max_limit[1]_i_1_n_0 ;
  wire \three_dec_max_limit[2]_i_1_n_0 ;
  wire \three_dec_max_limit[3]_i_1_n_0 ;
  wire \three_dec_max_limit[3]_i_3_n_0 ;
  wire \three_dec_max_limit[3]_i_4_n_0 ;
  wire \three_dec_max_limit[3]_i_5_n_0 ;
  wire \three_dec_max_limit[3]_i_6_n_0 ;
  wire \three_dec_max_limit[4]_i_1_n_0 ;
  wire \three_dec_max_limit[5]_i_1_n_0 ;
  wire \three_dec_max_limit[6]_i_1_n_0 ;
  wire \three_dec_max_limit[7]_i_1_n_0 ;
  wire \three_dec_max_limit[7]_i_3_n_0 ;
  wire \three_dec_max_limit[7]_i_4_n_0 ;
  wire \three_dec_max_limit[7]_i_5_n_0 ;
  wire \three_dec_max_limit[7]_i_6_n_0 ;
  wire \three_dec_max_limit[8]_i_1_n_0 ;
  wire \three_dec_max_limit[9]_i_1_n_0 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_1 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_4 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_7 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_0 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_1 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_4 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[3]_i_2_n_7 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_0 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_1 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_4 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[7]_i_2_n_7 ;
  wire [11:0]three_dec_min_limit;
  wire \three_dec_min_limit[11]_i_2_n_0 ;
  wire \three_dec_min_limit[11]_i_3_n_0 ;
  wire \three_dec_min_limit[5]_i_2_n_0 ;
  wire \three_dec_min_limit[5]_i_3_n_0 ;
  wire \three_dec_min_limit[5]_i_4_n_0 ;
  wire \three_dec_min_limit[5]_i_5_n_0 ;
  wire \three_dec_min_limit[9]_i_2_n_0 ;
  wire \three_dec_min_limit[9]_i_3_n_0 ;
  wire \three_dec_min_limit[9]_i_4_n_0 ;
  wire \three_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]three_dec_min_limit_nxt;
  wire \three_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]three_inc_max_limit;
  wire \three_inc_max_limit[11]_i_2_n_0 ;
  wire \three_inc_max_limit[11]_i_3_n_0 ;
  wire \three_inc_max_limit[11]_i_4_n_0 ;
  wire \three_inc_max_limit[11]_i_5_n_0 ;
  wire \three_inc_max_limit[3]_i_2_n_0 ;
  wire \three_inc_max_limit[3]_i_3_n_0 ;
  wire \three_inc_max_limit[3]_i_4_n_0 ;
  wire \three_inc_max_limit[3]_i_5_n_0 ;
  wire \three_inc_max_limit[7]_i_2_n_0 ;
  wire \three_inc_max_limit[7]_i_3_n_0 ;
  wire \three_inc_max_limit[7]_i_4_n_0 ;
  wire \three_inc_max_limit[7]_i_5_n_0 ;
  wire [11:0]three_inc_max_limit_nxt;
  wire \three_inc_max_limit_reg[11]_i_1_n_1 ;
  wire \three_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \three_inc_max_limit_reg[3]_i_1_n_0 ;
  wire \three_inc_max_limit_reg[3]_i_1_n_1 ;
  wire \three_inc_max_limit_reg[3]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[3]_i_1_n_3 ;
  wire \three_inc_max_limit_reg[7]_i_1_n_0 ;
  wire \three_inc_max_limit_reg[7]_i_1_n_1 ;
  wire \three_inc_max_limit_reg[7]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[7]_i_1_n_3 ;
  wire [11:0]three_inc_min_limit;
  wire \three_inc_min_limit[11]_i_2_n_0 ;
  wire \three_inc_min_limit[11]_i_3_n_0 ;
  wire \three_inc_min_limit[5]_i_2_n_0 ;
  wire \three_inc_min_limit[5]_i_3_n_0 ;
  wire \three_inc_min_limit[5]_i_4_n_0 ;
  wire \three_inc_min_limit[5]_i_5_n_0 ;
  wire \three_inc_min_limit[9]_i_2_n_0 ;
  wire \three_inc_min_limit[9]_i_3_n_0 ;
  wire \three_inc_min_limit[9]_i_4_n_0 ;
  wire \three_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]three_inc_min_limit_nxt;
  wire \three_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]two_dec_max_limit;
  wire \two_dec_max_limit[11]_i_2_n_0 ;
  wire \two_dec_max_limit[11]_i_3_n_0 ;
  wire \two_dec_max_limit[11]_i_4_n_0 ;
  wire \two_dec_max_limit[11]_i_5_n_0 ;
  wire \two_dec_max_limit[3]_i_2_n_0 ;
  wire \two_dec_max_limit[3]_i_3_n_0 ;
  wire \two_dec_max_limit[3]_i_4_n_0 ;
  wire \two_dec_max_limit[3]_i_5_n_0 ;
  wire \two_dec_max_limit[7]_i_2_n_0 ;
  wire \two_dec_max_limit[7]_i_3_n_0 ;
  wire \two_dec_max_limit[7]_i_4_n_0 ;
  wire \two_dec_max_limit[7]_i_5_n_0 ;
  wire [11:0]two_dec_max_limit_nxt;
  wire \two_dec_max_limit_reg[11]_i_1_n_1 ;
  wire \two_dec_max_limit_reg[11]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[11]_i_1_n_3 ;
  wire \two_dec_max_limit_reg[3]_i_1_n_0 ;
  wire \two_dec_max_limit_reg[3]_i_1_n_1 ;
  wire \two_dec_max_limit_reg[3]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[3]_i_1_n_3 ;
  wire \two_dec_max_limit_reg[7]_i_1_n_0 ;
  wire \two_dec_max_limit_reg[7]_i_1_n_1 ;
  wire \two_dec_max_limit_reg[7]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[7]_i_1_n_3 ;
  wire [11:0]two_dec_min_limit;
  wire \two_dec_min_limit[11]_i_2_n_0 ;
  wire \two_dec_min_limit[11]_i_3_n_0 ;
  wire \two_dec_min_limit[5]_i_2_n_0 ;
  wire \two_dec_min_limit[5]_i_3_n_0 ;
  wire \two_dec_min_limit[5]_i_4_n_0 ;
  wire \two_dec_min_limit[5]_i_5_n_0 ;
  wire \two_dec_min_limit[9]_i_2_n_0 ;
  wire \two_dec_min_limit[9]_i_3_n_0 ;
  wire \two_dec_min_limit[9]_i_4_n_0 ;
  wire \two_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]two_dec_min_limit_nxt;
  wire \two_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]two_inc_max_limit;
  wire \two_inc_max_limit[11]_i_2_n_0 ;
  wire \two_inc_max_limit[11]_i_3_n_0 ;
  wire \two_inc_max_limit[11]_i_4_n_0 ;
  wire \two_inc_max_limit[11]_i_5_n_0 ;
  wire \two_inc_max_limit[3]_i_2_n_0 ;
  wire \two_inc_max_limit[3]_i_3_n_0 ;
  wire \two_inc_max_limit[3]_i_4_n_0 ;
  wire \two_inc_max_limit[3]_i_5_n_0 ;
  wire \two_inc_max_limit[7]_i_2_n_0 ;
  wire \two_inc_max_limit[7]_i_3_n_0 ;
  wire \two_inc_max_limit[7]_i_4_n_0 ;
  wire \two_inc_max_limit[7]_i_5_n_0 ;
  wire [11:0]two_inc_max_limit_nxt;
  wire \two_inc_max_limit_reg[11]_i_1_n_1 ;
  wire \two_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \two_inc_max_limit_reg[3]_i_1_n_0 ;
  wire \two_inc_max_limit_reg[3]_i_1_n_1 ;
  wire \two_inc_max_limit_reg[3]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[3]_i_1_n_3 ;
  wire \two_inc_max_limit_reg[7]_i_1_n_0 ;
  wire \two_inc_max_limit_reg[7]_i_1_n_1 ;
  wire \two_inc_max_limit_reg[7]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[7]_i_1_n_3 ;
  wire [11:0]two_inc_min_limit;
  wire \two_inc_min_limit[11]_i_2_n_0 ;
  wire \two_inc_min_limit[11]_i_3_n_0 ;
  wire \two_inc_min_limit[5]_i_2_n_0 ;
  wire \two_inc_min_limit[5]_i_3_n_0 ;
  wire \two_inc_min_limit[5]_i_4_n_0 ;
  wire \two_inc_min_limit[5]_i_5_n_0 ;
  wire \two_inc_min_limit[9]_i_2_n_0 ;
  wire \two_inc_min_limit[9]_i_3_n_0 ;
  wire \two_inc_min_limit[9]_i_4_n_0 ;
  wire \two_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]two_inc_min_limit_nxt;
  wire \two_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_3 ;
  wire update_temp_101;
  wire update_temp_102;
  wire wr_level_done_reg;
  wire wrcal_done_reg;
  wire [3:1]\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:3]\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:3]\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:3]\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:1]\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:3]\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:3]\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:3]\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;

  LUT5 #(
    .INIT(32'h0002AA02)) 
    \calib_sel[0]_i_1 
       (.I0(\calib_zero_inputs_reg[0] ),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ),
        .I2(\gen_byte_sel_div2.ctl_lane_sel_reg[0] ),
        .I3(dqs_po_dec_done_reg),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ),
        .O(\calib_sel_reg[3] [0]));
  LUT6 #(
    .INIT(64'h00020000AAAAAAAA)) 
    \calib_sel[3]_i_1 
       (.I0(\calib_zero_inputs_reg[0] ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(dqs_po_dec_done_reg),
        .O(\calib_sel_reg[3] [1]));
  LUT4 #(
    .INIT(16'h5455)) 
    \calib_sel[4]_i_2 
       (.I0(rstdiv0_sync_r1_reg_rep__24),
        .I1(tempmon_pi_f_inc_r_reg),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I3(calib_complete),
        .O(\calib_zero_inputs_reg[0] ));
  LUT6 #(
    .INIT(64'h5D5D5D5D5DFF5D5D)) 
    \calib_zero_inputs[0]_i_1 
       (.I0(\calib_zero_inputs_reg[0] ),
        .I1(\pi_rst_stg1_cal_reg[0] ),
        .I2(dqs_po_dec_done_reg),
        .I3(\calib_zero_inputs[2]_i_2_n_0 ),
        .I4(Q[2]),
        .I5(Q[3]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h55545555FFFFFFFF)) 
    \calib_zero_inputs[1]_i_1 
       (.I0(\calib_zero_inputs[2]_i_2_n_0 ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\calib_zero_inputs_reg[0] ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFF55015555)) 
    \calib_zero_inputs[2]_i_1 
       (.I0(\calib_zero_inputs[2]_i_2_n_0 ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\pi_rst_stg1_cal_reg[0]_0 ),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hFFFBFFFFFFFFFFFF)) 
    \calib_zero_inputs[2]_i_2 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I1(delay_done_r4_reg),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I3(tempmon_pi_f_inc_r_reg),
        .I4(dqs_po_dec_done),
        .I5(pi_fine_dly_dec_done),
        .O(\calib_zero_inputs[2]_i_2_n_0 ));
  FDRE \device_temp_101_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [0]),
        .Q(device_temp_101[0]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [10]),
        .Q(device_temp_101[10]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [11]),
        .Q(device_temp_101[11]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [1]),
        .Q(device_temp_101[1]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [2]),
        .Q(device_temp_101[2]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [3]),
        .Q(device_temp_101[3]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [4]),
        .Q(device_temp_101[4]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [5]),
        .Q(device_temp_101[5]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [6]),
        .Q(device_temp_101[6]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [7]),
        .Q(device_temp_101[7]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [8]),
        .Q(device_temp_101[8]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_101_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_r_reg[11] [9]),
        .Q(device_temp_101[9]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  LUT6 #(
    .INIT(64'h0000100010001000)) 
    \device_temp_init[11]_i_1 
       (.I0(tempmon_state[9]),
        .I1(tempmon_state[10]),
        .I2(\device_temp_init[11]_i_2_n_0 ),
        .I3(\device_temp_init[11]_i_3_n_0 ),
        .I4(tempmon_state[1]),
        .I5(tempmon_state[0]),
        .O(\device_temp_init[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \device_temp_init[11]_i_2 
       (.I0(tempmon_state[7]),
        .I1(tempmon_state[8]),
        .I2(tempmon_state[1]),
        .I3(tempmon_state[2]),
        .I4(tempmon_state[5]),
        .I5(tempmon_state[4]),
        .O(\device_temp_init[11]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \device_temp_init[11]_i_3 
       (.I0(tempmon_state[4]),
        .I1(tempmon_state[3]),
        .I2(tempmon_state[7]),
        .I3(tempmon_state[6]),
        .O(\device_temp_init[11]_i_3_n_0 ));
  FDRE \device_temp_init_reg[0] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[0]),
        .Q(device_temp_init[0]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[10] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[10]),
        .Q(device_temp_init[10]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[11] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[11]),
        .Q(device_temp_init[11]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[1] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[1]),
        .Q(device_temp_init[1]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[2] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[2]),
        .Q(device_temp_init[2]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[3] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[3]),
        .Q(device_temp_init[3]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[4] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[4]),
        .Q(device_temp_init[4]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[5] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[5]),
        .Q(device_temp_init[5]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[6] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[6]),
        .Q(device_temp_init[6]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[7] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[7]),
        .Q(device_temp_init[7]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[8] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[8]),
        .Q(device_temp_init[8]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \device_temp_init_reg[9] 
       (.C(CLK),
        .CE(\device_temp_init[11]_i_1_n_0 ),
        .D(device_temp_101[9]),
        .Q(device_temp_init[9]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[11]_i_2 
       (.I0(three_dec_max_limit[11]),
        .O(\four_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[11]_i_3 
       (.I0(three_dec_max_limit[10]),
        .O(\four_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_2 
       (.I0(three_dec_max_limit[5]),
        .O(\four_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_3 
       (.I0(three_dec_max_limit[4]),
        .O(\four_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_4 
       (.I0(three_dec_max_limit[3]),
        .O(\four_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \four_dec_min_limit[5]_i_5 
       (.I0(three_dec_max_limit[2]),
        .O(\four_dec_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_2 
       (.I0(three_dec_max_limit[9]),
        .O(\four_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_3 
       (.I0(three_dec_max_limit[8]),
        .O(\four_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_4 
       (.I0(three_dec_max_limit[7]),
        .O(\four_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_5 
       (.I0(three_dec_max_limit[6]),
        .O(\four_dec_min_limit[9]_i_5_n_0 ));
  FDRE \four_dec_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_max_limit[0]),
        .Q(four_dec_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[10]),
        .Q(four_dec_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[11]),
        .Q(four_dec_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \four_dec_min_limit_reg[11]_i_1 
       (.CI(\four_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\four_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,three_dec_max_limit[10]}),
        .O({\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],four_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\four_dec_min_limit[11]_i_2_n_0 ,\four_dec_min_limit[11]_i_3_n_0 }));
  FDRE \four_dec_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_max_limit[1]),
        .Q(four_dec_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[2]),
        .Q(four_dec_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[3]),
        .Q(four_dec_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[4]),
        .Q(four_dec_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[5]),
        .Q(four_dec_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \four_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\four_dec_min_limit_reg[5]_i_1_n_0 ,\four_dec_min_limit_reg[5]_i_1_n_1 ,\four_dec_min_limit_reg[5]_i_1_n_2 ,\four_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({three_dec_max_limit[5:3],1'b0}),
        .O(four_dec_min_limit_nxt[5:2]),
        .S({\four_dec_min_limit[5]_i_2_n_0 ,\four_dec_min_limit[5]_i_3_n_0 ,\four_dec_min_limit[5]_i_4_n_0 ,\four_dec_min_limit[5]_i_5_n_0 }));
  FDRE \four_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[6]),
        .Q(four_dec_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[7]),
        .Q(four_dec_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[8]),
        .Q(four_dec_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \four_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[9]),
        .Q(four_dec_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \four_dec_min_limit_reg[9]_i_1 
       (.CI(\four_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\four_dec_min_limit_reg[9]_i_1_n_0 ,\four_dec_min_limit_reg[9]_i_1_n_1 ,\four_dec_min_limit_reg[9]_i_1_n_2 ,\four_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(three_dec_max_limit[9:6]),
        .O(four_dec_min_limit_nxt[9:6]),
        .S({\four_dec_min_limit[9]_i_2_n_0 ,\four_dec_min_limit[9]_i_3_n_0 ,\four_dec_min_limit[9]_i_4_n_0 ,\four_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\four_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\four_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \four_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\four_inc_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \four_inc_max_limit[11]_i_5 
       (.I0(device_temp_init[8]),
        .O(\four_inc_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[3]_i_2 
       (.I0(device_temp_init[3]),
        .O(\four_inc_max_limit[3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[3]_i_3 
       (.I0(device_temp_init[2]),
        .O(\four_inc_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[3]_i_4 
       (.I0(device_temp_init[1]),
        .O(\four_inc_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[3]_i_5 
       (.I0(device_temp_init[0]),
        .O(\four_inc_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[7]_i_2 
       (.I0(device_temp_init[7]),
        .O(\four_inc_max_limit[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \four_inc_max_limit[7]_i_3 
       (.I0(device_temp_init[6]),
        .O(\four_inc_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[7]_i_4 
       (.I0(device_temp_init[5]),
        .O(\four_inc_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[7]_i_5 
       (.I0(device_temp_init[4]),
        .O(\four_inc_max_limit[7]_i_5_n_0 ));
  FDRE \four_inc_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[0]),
        .Q(four_inc_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[10]),
        .Q(four_inc_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[11]),
        .Q(four_inc_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  CARRY4 \four_inc_max_limit_reg[11]_i_1 
       (.CI(\four_inc_max_limit_reg[7]_i_1_n_0 ),
        .CO({\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3],\four_inc_max_limit_reg[11]_i_1_n_1 ,\four_inc_max_limit_reg[11]_i_1_n_2 ,\four_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[10],1'b0,1'b0}),
        .O(four_inc_max_limit_nxt[11:8]),
        .S({\four_inc_max_limit[11]_i_2_n_0 ,\four_inc_max_limit[11]_i_3_n_0 ,\four_inc_max_limit[11]_i_4_n_0 ,\four_inc_max_limit[11]_i_5_n_0 }));
  FDRE \four_inc_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[1]),
        .Q(four_inc_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[2]),
        .Q(four_inc_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[3]),
        .Q(four_inc_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  CARRY4 \four_inc_max_limit_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\four_inc_max_limit_reg[3]_i_1_n_0 ,\four_inc_max_limit_reg[3]_i_1_n_1 ,\four_inc_max_limit_reg[3]_i_1_n_2 ,\four_inc_max_limit_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(device_temp_init[3:0]),
        .O(four_inc_max_limit_nxt[3:0]),
        .S({\four_inc_max_limit[3]_i_2_n_0 ,\four_inc_max_limit[3]_i_3_n_0 ,\four_inc_max_limit[3]_i_4_n_0 ,\four_inc_max_limit[3]_i_5_n_0 }));
  FDRE \four_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[4]),
        .Q(four_inc_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[5]),
        .Q(four_inc_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[6]),
        .Q(four_inc_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[7]),
        .Q(four_inc_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  CARRY4 \four_inc_max_limit_reg[7]_i_1 
       (.CI(\four_inc_max_limit_reg[3]_i_1_n_0 ),
        .CO({\four_inc_max_limit_reg[7]_i_1_n_0 ,\four_inc_max_limit_reg[7]_i_1_n_1 ,\four_inc_max_limit_reg[7]_i_1_n_2 ,\four_inc_max_limit_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[7],1'b0,device_temp_init[5:4]}),
        .O(four_inc_max_limit_nxt[7:4]),
        .S({\four_inc_max_limit[7]_i_2_n_0 ,\four_inc_max_limit[7]_i_3_n_0 ,\four_inc_max_limit[7]_i_4_n_0 ,\four_inc_max_limit[7]_i_5_n_0 }));
  FDRE \four_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[8]),
        .Q(four_inc_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \four_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[9]),
        .Q(four_inc_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAA2AAA)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_2 
       (.I0(po_ck_addr_cmd_delay_done),
        .I1(wr_level_done_reg),
        .I2(rdlvl_stg1_done_reg),
        .I3(wrcal_done_reg),
        .I4(tempmon_pi_f_inc_r_reg),
        .I5(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .O(E));
  LUT6 #(
    .INIT(64'hFEFFFEFEFFFFFFFF)) 
    \gen_byte_sel_div2.calib_in_common_i_3 
       (.I0(pi_fine_dly_dec_done_reg),
        .I1(tempmon_pi_f_inc_r_reg),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I3(fine_adjust_done),
        .I4(rd_data_offset_cal_done),
        .I5(po_ck_addr_cmd_delay_done),
        .O(\gen_byte_sel_div2.calib_in_common_reg ));
  LUT1 #(
    .INIT(2'h2)) 
    \neutral_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\neutral_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \neutral_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\neutral_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \neutral_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\neutral_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \neutral_max_limit[11]_i_5 
       (.I0(device_temp_init[8]),
        .O(\neutral_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \neutral_max_limit[3]_i_2 
       (.I0(device_temp_init[3]),
        .O(\neutral_max_limit[3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[3]_i_3 
       (.I0(device_temp_init[2]),
        .O(\neutral_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[3]_i_4 
       (.I0(device_temp_init[1]),
        .O(\neutral_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[3]_i_5 
       (.I0(device_temp_init[0]),
        .O(\neutral_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \neutral_max_limit[7]_i_2 
       (.I0(device_temp_init[7]),
        .O(\neutral_max_limit[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[7]_i_3 
       (.I0(device_temp_init[6]),
        .O(\neutral_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[7]_i_4 
       (.I0(device_temp_init[5]),
        .O(\neutral_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[7]_i_5 
       (.I0(device_temp_init[4]),
        .O(\neutral_max_limit[7]_i_5_n_0 ));
  FDRE \neutral_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[0]),
        .Q(neutral_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[10]),
        .Q(neutral_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[11]),
        .Q(neutral_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \neutral_max_limit_reg[11]_i_1 
       (.CI(\neutral_max_limit_reg[7]_i_1_n_0 ),
        .CO({\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED [3],\neutral_max_limit_reg[11]_i_1_n_1 ,\neutral_max_limit_reg[11]_i_1_n_2 ,\neutral_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(neutral_max_limit_nxt[11:8]),
        .S({\neutral_max_limit[11]_i_2_n_0 ,\neutral_max_limit[11]_i_3_n_0 ,\neutral_max_limit[11]_i_4_n_0 ,\neutral_max_limit[11]_i_5_n_0 }));
  FDRE \neutral_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[1]),
        .Q(neutral_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[2]),
        .Q(neutral_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[3]),
        .Q(neutral_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \neutral_max_limit_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\neutral_max_limit_reg[3]_i_1_n_0 ,\neutral_max_limit_reg[3]_i_1_n_1 ,\neutral_max_limit_reg[3]_i_1_n_2 ,\neutral_max_limit_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[2:0]}),
        .O(neutral_max_limit_nxt[3:0]),
        .S({\neutral_max_limit[3]_i_2_n_0 ,\neutral_max_limit[3]_i_3_n_0 ,\neutral_max_limit[3]_i_4_n_0 ,\neutral_max_limit[3]_i_5_n_0 }));
  FDRE \neutral_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[4]),
        .Q(neutral_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[5]),
        .Q(neutral_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[6]),
        .Q(neutral_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[7]),
        .Q(neutral_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \neutral_max_limit_reg[7]_i_1 
       (.CI(\neutral_max_limit_reg[3]_i_1_n_0 ),
        .CO({\neutral_max_limit_reg[7]_i_1_n_0 ,\neutral_max_limit_reg[7]_i_1_n_1 ,\neutral_max_limit_reg[7]_i_1_n_2 ,\neutral_max_limit_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[6:4]}),
        .O(neutral_max_limit_nxt[7:4]),
        .S({\neutral_max_limit[7]_i_2_n_0 ,\neutral_max_limit[7]_i_3_n_0 ,\neutral_max_limit[7]_i_4_n_0 ,\neutral_max_limit[7]_i_5_n_0 }));
  FDRE \neutral_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[8]),
        .Q(neutral_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \neutral_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[9]),
        .Q(neutral_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[11]_i_2 
       (.I0(one_inc_max_limit[11]),
        .O(\neutral_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[11]_i_3 
       (.I0(one_inc_max_limit[10]),
        .O(\neutral_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_2 
       (.I0(one_inc_max_limit[5]),
        .O(\neutral_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_3 
       (.I0(one_inc_max_limit[4]),
        .O(\neutral_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_4 
       (.I0(one_inc_max_limit[3]),
        .O(\neutral_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \neutral_min_limit[5]_i_5 
       (.I0(one_inc_max_limit[2]),
        .O(\neutral_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_2 
       (.I0(one_inc_max_limit[9]),
        .O(\neutral_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_3 
       (.I0(one_inc_max_limit[8]),
        .O(\neutral_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_4 
       (.I0(one_inc_max_limit[7]),
        .O(\neutral_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_5 
       (.I0(one_inc_max_limit[6]),
        .O(\neutral_min_limit[9]_i_5_n_0 ));
  FDRE \neutral_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit[0]),
        .Q(neutral_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[10]),
        .Q(neutral_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[11]),
        .Q(neutral_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \neutral_min_limit_reg[11]_i_1 
       (.CI(\neutral_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\neutral_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,one_inc_max_limit[10]}),
        .O({\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],neutral_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\neutral_min_limit[11]_i_2_n_0 ,\neutral_min_limit[11]_i_3_n_0 }));
  FDRE \neutral_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit[1]),
        .Q(neutral_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[2]),
        .Q(neutral_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[3]),
        .Q(neutral_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[4]),
        .Q(neutral_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[5]),
        .Q(neutral_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \neutral_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\neutral_min_limit_reg[5]_i_1_n_0 ,\neutral_min_limit_reg[5]_i_1_n_1 ,\neutral_min_limit_reg[5]_i_1_n_2 ,\neutral_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({one_inc_max_limit[5:3],1'b0}),
        .O(neutral_min_limit_nxt[5:2]),
        .S({\neutral_min_limit[5]_i_2_n_0 ,\neutral_min_limit[5]_i_3_n_0 ,\neutral_min_limit[5]_i_4_n_0 ,\neutral_min_limit[5]_i_5_n_0 }));
  FDRE \neutral_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[6]),
        .Q(neutral_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[7]),
        .Q(neutral_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[8]),
        .Q(neutral_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \neutral_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[9]),
        .Q(neutral_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \neutral_min_limit_reg[9]_i_1 
       (.CI(\neutral_min_limit_reg[5]_i_1_n_0 ),
        .CO({\neutral_min_limit_reg[9]_i_1_n_0 ,\neutral_min_limit_reg[9]_i_1_n_1 ,\neutral_min_limit_reg[9]_i_1_n_2 ,\neutral_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(one_inc_max_limit[9:6]),
        .O(neutral_min_limit_nxt[9:6]),
        .S({\neutral_min_limit[9]_i_2_n_0 ,\neutral_min_limit[9]_i_3_n_0 ,\neutral_min_limit[9]_i_4_n_0 ,\neutral_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\one_dec_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\one_dec_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\one_dec_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[11]_i_5 
       (.I0(device_temp_init[8]),
        .O(\one_dec_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_max_limit[3]_i_2 
       (.I0(device_temp_init[3]),
        .O(\one_dec_max_limit[3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[3]_i_3 
       (.I0(device_temp_init[2]),
        .O(\one_dec_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_max_limit[3]_i_4 
       (.I0(device_temp_init[1]),
        .O(\one_dec_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[3]_i_5 
       (.I0(device_temp_init[0]),
        .O(\one_dec_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_max_limit[7]_i_2 
       (.I0(device_temp_init[7]),
        .O(\one_dec_max_limit[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[7]_i_3 
       (.I0(device_temp_init[6]),
        .O(\one_dec_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[7]_i_4 
       (.I0(device_temp_init[5]),
        .O(\one_dec_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_max_limit[7]_i_5 
       (.I0(device_temp_init[4]),
        .O(\one_dec_max_limit[7]_i_5_n_0 ));
  FDRE \one_dec_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[0]),
        .Q(one_dec_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[10]),
        .Q(one_dec_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[11]),
        .Q(one_dec_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \one_dec_max_limit_reg[11]_i_1 
       (.CI(\one_dec_max_limit_reg[7]_i_1_n_0 ),
        .CO({\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3],\one_dec_max_limit_reg[11]_i_1_n_1 ,\one_dec_max_limit_reg[11]_i_1_n_2 ,\one_dec_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,device_temp_init[8]}),
        .O(one_dec_max_limit_nxt[11:8]),
        .S({\one_dec_max_limit[11]_i_2_n_0 ,\one_dec_max_limit[11]_i_3_n_0 ,\one_dec_max_limit[11]_i_4_n_0 ,\one_dec_max_limit[11]_i_5_n_0 }));
  FDRE \one_dec_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[1]),
        .Q(one_dec_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[2]),
        .Q(one_dec_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[3]),
        .Q(one_dec_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \one_dec_max_limit_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\one_dec_max_limit_reg[3]_i_1_n_0 ,\one_dec_max_limit_reg[3]_i_1_n_1 ,\one_dec_max_limit_reg[3]_i_1_n_2 ,\one_dec_max_limit_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[2],1'b0,device_temp_init[0]}),
        .O(one_dec_max_limit_nxt[3:0]),
        .S({\one_dec_max_limit[3]_i_2_n_0 ,\one_dec_max_limit[3]_i_3_n_0 ,\one_dec_max_limit[3]_i_4_n_0 ,\one_dec_max_limit[3]_i_5_n_0 }));
  FDRE \one_dec_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[4]),
        .Q(one_dec_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[5]),
        .Q(one_dec_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[6]),
        .Q(one_dec_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[7]),
        .Q(one_dec_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \one_dec_max_limit_reg[7]_i_1 
       (.CI(\one_dec_max_limit_reg[3]_i_1_n_0 ),
        .CO({\one_dec_max_limit_reg[7]_i_1_n_0 ,\one_dec_max_limit_reg[7]_i_1_n_1 ,\one_dec_max_limit_reg[7]_i_1_n_2 ,\one_dec_max_limit_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[6:5],1'b0}),
        .O(one_dec_max_limit_nxt[7:4]),
        .S({\one_dec_max_limit[7]_i_2_n_0 ,\one_dec_max_limit[7]_i_3_n_0 ,\one_dec_max_limit[7]_i_4_n_0 ,\one_dec_max_limit[7]_i_5_n_0 }));
  FDRE \one_dec_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[8]),
        .Q(one_dec_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \one_dec_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[9]),
        .Q(one_dec_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[11]_i_2 
       (.I0(neutral_max_limit[11]),
        .O(\one_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[11]_i_3 
       (.I0(neutral_max_limit[10]),
        .O(\one_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_2 
       (.I0(neutral_max_limit[5]),
        .O(\one_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_3 
       (.I0(neutral_max_limit[4]),
        .O(\one_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_4 
       (.I0(neutral_max_limit[3]),
        .O(\one_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_dec_min_limit[5]_i_5 
       (.I0(neutral_max_limit[2]),
        .O(\one_dec_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_2 
       (.I0(neutral_max_limit[9]),
        .O(\one_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_3 
       (.I0(neutral_max_limit[8]),
        .O(\one_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_4 
       (.I0(neutral_max_limit[7]),
        .O(\one_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_5 
       (.I0(neutral_max_limit[6]),
        .O(\one_dec_min_limit[9]_i_5_n_0 ));
  FDRE \one_dec_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit[0]),
        .Q(one_dec_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[10]),
        .Q(one_dec_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[11]),
        .Q(one_dec_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \one_dec_min_limit_reg[11]_i_1 
       (.CI(\one_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,neutral_max_limit[10]}),
        .O({\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\one_dec_min_limit[11]_i_2_n_0 ,\one_dec_min_limit[11]_i_3_n_0 }));
  FDRE \one_dec_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit[1]),
        .Q(one_dec_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[2]),
        .Q(one_dec_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[3]),
        .Q(one_dec_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[4]),
        .Q(one_dec_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[5]),
        .Q(one_dec_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \one_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\one_dec_min_limit_reg[5]_i_1_n_0 ,\one_dec_min_limit_reg[5]_i_1_n_1 ,\one_dec_min_limit_reg[5]_i_1_n_2 ,\one_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({neutral_max_limit[5:3],1'b0}),
        .O(one_dec_min_limit_nxt[5:2]),
        .S({\one_dec_min_limit[5]_i_2_n_0 ,\one_dec_min_limit[5]_i_3_n_0 ,\one_dec_min_limit[5]_i_4_n_0 ,\one_dec_min_limit[5]_i_5_n_0 }));
  FDRE \one_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[6]),
        .Q(one_dec_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[7]),
        .Q(one_dec_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[8]),
        .Q(one_dec_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \one_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[9]),
        .Q(one_dec_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \one_dec_min_limit_reg[9]_i_1 
       (.CI(\one_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\one_dec_min_limit_reg[9]_i_1_n_0 ,\one_dec_min_limit_reg[9]_i_1_n_1 ,\one_dec_min_limit_reg[9]_i_1_n_2 ,\one_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(neutral_max_limit[9:6]),
        .O(one_dec_min_limit_nxt[9:6]),
        .S({\one_dec_min_limit[9]_i_2_n_0 ,\one_dec_min_limit[9]_i_3_n_0 ,\one_dec_min_limit[9]_i_4_n_0 ,\one_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\one_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\one_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\one_inc_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_5 
       (.I0(device_temp_init[8]),
        .O(\one_inc_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[3]_i_2 
       (.I0(device_temp_init[3]),
        .O(\one_inc_max_limit[3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_inc_max_limit[3]_i_3 
       (.I0(device_temp_init[2]),
        .O(\one_inc_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_inc_max_limit[3]_i_4 
       (.I0(device_temp_init[1]),
        .O(\one_inc_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[3]_i_5 
       (.I0(device_temp_init[0]),
        .O(\one_inc_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[7]_i_2 
       (.I0(device_temp_init[7]),
        .O(\one_inc_max_limit[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_inc_max_limit[7]_i_3 
       (.I0(device_temp_init[6]),
        .O(\one_inc_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_inc_max_limit[7]_i_4 
       (.I0(device_temp_init[5]),
        .O(\one_inc_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_inc_max_limit[7]_i_5 
       (.I0(device_temp_init[4]),
        .O(\one_inc_max_limit[7]_i_5_n_0 ));
  FDRE \one_inc_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[0]),
        .Q(one_inc_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[10]),
        .Q(one_inc_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[11]),
        .Q(one_inc_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \one_inc_max_limit_reg[11]_i_1 
       (.CI(\one_inc_max_limit_reg[7]_i_1_n_0 ),
        .CO({\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3],\one_inc_max_limit_reg[11]_i_1_n_1 ,\one_inc_max_limit_reg[11]_i_1_n_2 ,\one_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[10:8]}),
        .O(one_inc_max_limit_nxt[11:8]),
        .S({\one_inc_max_limit[11]_i_2_n_0 ,\one_inc_max_limit[11]_i_3_n_0 ,\one_inc_max_limit[11]_i_4_n_0 ,\one_inc_max_limit[11]_i_5_n_0 }));
  FDRE \one_inc_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[1]),
        .Q(one_inc_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[2]),
        .Q(one_inc_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[3]),
        .Q(one_inc_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \one_inc_max_limit_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\one_inc_max_limit_reg[3]_i_1_n_0 ,\one_inc_max_limit_reg[3]_i_1_n_1 ,\one_inc_max_limit_reg[3]_i_1_n_2 ,\one_inc_max_limit_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[3],1'b0,1'b0,device_temp_init[0]}),
        .O(one_inc_max_limit_nxt[3:0]),
        .S({\one_inc_max_limit[3]_i_2_n_0 ,\one_inc_max_limit[3]_i_3_n_0 ,\one_inc_max_limit[3]_i_4_n_0 ,\one_inc_max_limit[3]_i_5_n_0 }));
  FDRE \one_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[4]),
        .Q(one_inc_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[5]),
        .Q(one_inc_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[6]),
        .Q(one_inc_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[7]),
        .Q(one_inc_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \one_inc_max_limit_reg[7]_i_1 
       (.CI(\one_inc_max_limit_reg[3]_i_1_n_0 ),
        .CO({\one_inc_max_limit_reg[7]_i_1_n_0 ,\one_inc_max_limit_reg[7]_i_1_n_1 ,\one_inc_max_limit_reg[7]_i_1_n_2 ,\one_inc_max_limit_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[7],1'b0,1'b0,1'b0}),
        .O(one_inc_max_limit_nxt[7:4]),
        .S({\one_inc_max_limit[7]_i_2_n_0 ,\one_inc_max_limit[7]_i_3_n_0 ,\one_inc_max_limit[7]_i_4_n_0 ,\one_inc_max_limit[7]_i_5_n_0 }));
  FDRE \one_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[8]),
        .Q(one_inc_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \one_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[9]),
        .Q(one_inc_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[11]_i_2 
       (.I0(two_inc_max_limit[11]),
        .O(\one_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[11]_i_3 
       (.I0(two_inc_max_limit[10]),
        .O(\one_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_2 
       (.I0(two_inc_max_limit[5]),
        .O(\one_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_3 
       (.I0(two_inc_max_limit[4]),
        .O(\one_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_4 
       (.I0(two_inc_max_limit[3]),
        .O(\one_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \one_inc_min_limit[5]_i_5 
       (.I0(two_inc_max_limit[2]),
        .O(\one_inc_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_2 
       (.I0(two_inc_max_limit[9]),
        .O(\one_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_3 
       (.I0(two_inc_max_limit[8]),
        .O(\one_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_4 
       (.I0(two_inc_max_limit[7]),
        .O(\one_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_5 
       (.I0(two_inc_max_limit[6]),
        .O(\one_inc_min_limit[9]_i_5_n_0 ));
  FDRE \one_inc_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit[0]),
        .Q(one_inc_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[10]),
        .Q(one_inc_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[11]),
        .Q(one_inc_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \one_inc_min_limit_reg[11]_i_1 
       (.CI(\one_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,two_inc_max_limit[10]}),
        .O({\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\one_inc_min_limit[11]_i_2_n_0 ,\one_inc_min_limit[11]_i_3_n_0 }));
  FDRE \one_inc_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit[1]),
        .Q(one_inc_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[2]),
        .Q(one_inc_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[3]),
        .Q(one_inc_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[4]),
        .Q(one_inc_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[5]),
        .Q(one_inc_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \one_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\one_inc_min_limit_reg[5]_i_1_n_0 ,\one_inc_min_limit_reg[5]_i_1_n_1 ,\one_inc_min_limit_reg[5]_i_1_n_2 ,\one_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({two_inc_max_limit[5:3],1'b0}),
        .O(one_inc_min_limit_nxt[5:2]),
        .S({\one_inc_min_limit[5]_i_2_n_0 ,\one_inc_min_limit[5]_i_3_n_0 ,\one_inc_min_limit[5]_i_4_n_0 ,\one_inc_min_limit[5]_i_5_n_0 }));
  FDRE \one_inc_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[6]),
        .Q(one_inc_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[7]),
        .Q(one_inc_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[8]),
        .Q(one_inc_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \one_inc_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[9]),
        .Q(one_inc_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \one_inc_min_limit_reg[9]_i_1 
       (.CI(\one_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\one_inc_min_limit_reg[9]_i_1_n_0 ,\one_inc_min_limit_reg[9]_i_1_n_1 ,\one_inc_min_limit_reg[9]_i_1_n_2 ,\one_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(two_inc_max_limit[9:6]),
        .O(one_inc_min_limit_nxt[9:6]),
        .S({\one_inc_min_limit[9]_i_2_n_0 ,\one_inc_min_limit[9]_i_3_n_0 ,\one_inc_min_limit[9]_i_4_n_0 ,\one_inc_min_limit[9]_i_5_n_0 }));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8A8)) 
    pi_f_dec_i_1
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(pi_f_dec_i_2_n_0),
        .I2(pi_f_dec_i_3_n_0),
        .I3(tempmon_state[3]),
        .I4(temp_gte_three_inc_max),
        .I5(pi_f_dec_i_4_n_0),
        .O(pi_f_dec_nxt));
  LUT6 #(
    .INIT(64'hFFFFFFFFF0808080)) 
    pi_f_dec_i_2
       (.I0(tempmon_state[8]),
        .I1(temp_cmp_two_dec_max_102),
        .I2(update_temp_102),
        .I3(tempmon_state[7]),
        .I4(temp_cmp_one_dec_max_102),
        .I5(pi_f_dec_i_5_n_0),
        .O(pi_f_dec_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'h80)) 
    pi_f_dec_i_3
       (.I0(tempmon_state[4]),
        .I1(temp_cmp_two_inc_max_102),
        .I2(update_temp_102),
        .O(pi_f_dec_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT5 #(
    .INIT(32'hF0808080)) 
    pi_f_dec_i_4
       (.I0(temp_cmp_one_inc_max_102),
        .I1(tempmon_state[5]),
        .I2(update_temp_102),
        .I3(temp_cmp_neutral_max_102),
        .I4(tempmon_state[6]),
        .O(pi_f_dec_i_4_n_0));
  LUT5 #(
    .INIT(32'hF0808080)) 
    pi_f_dec_i_5
       (.I0(temp_cmp_three_dec_max_102),
        .I1(tempmon_state[9]),
        .I2(update_temp_102),
        .I3(temp_cmp_four_inc_max_102),
        .I4(tempmon_state[2]),
        .O(pi_f_dec_i_5_n_0));
  FDRE pi_f_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_f_dec_nxt),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .R(rstdiv0_sync_r1_reg_rep__15));
  LUT6 #(
    .INIT(64'hAAAAAAAA88A88888)) 
    pi_f_inc_i_1
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(pi_f_inc_i_2_n_0),
        .I2(temp_lte_three_inc_min),
        .I3(temp_gte_three_inc_max),
        .I4(tempmon_state[3]),
        .I5(pi_f_inc_i_5_n_0),
        .O(pi_f_inc_nxt));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAAAAA)) 
    pi_f_inc_i_2
       (.I0(pi_f_inc_i_6_n_0),
        .I1(tempmon_state[5]),
        .I2(update_temp_102),
        .I3(temp_cmp_one_inc_max_102),
        .I4(temp_cmp_one_inc_min_102),
        .I5(pi_f_inc_i_7_n_0),
        .O(pi_f_inc_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h8)) 
    pi_f_inc_i_3
       (.I0(update_temp_102),
        .I1(temp_cmp_three_inc_min_102),
        .O(temp_lte_three_inc_min));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'h8)) 
    pi_f_inc_i_4
       (.I0(update_temp_102),
        .I1(temp_cmp_three_inc_max_102),
        .O(temp_gte_three_inc_max));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    pi_f_inc_i_5
       (.I0(tempmon_state[4]),
        .I1(update_temp_102),
        .I2(temp_cmp_two_inc_max_102),
        .I3(temp_cmp_two_inc_min_102),
        .O(pi_f_inc_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    pi_f_inc_i_6
       (.I0(tempmon_state[6]),
        .I1(update_temp_102),
        .I2(temp_cmp_neutral_max_102),
        .I3(temp_cmp_neutral_min_102),
        .O(pi_f_inc_i_6_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAAAAA)) 
    pi_f_inc_i_7
       (.I0(pi_f_inc_i_8_n_0),
        .I1(tempmon_state[7]),
        .I2(update_temp_102),
        .I3(temp_cmp_one_dec_max_102),
        .I4(temp_cmp_one_dec_min_102),
        .I5(pi_f_inc_i_9_n_0),
        .O(pi_f_inc_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    pi_f_inc_i_8
       (.I0(tempmon_state[8]),
        .I1(update_temp_102),
        .I2(temp_cmp_two_dec_max_102),
        .I3(temp_cmp_two_dec_min_102),
        .O(pi_f_inc_i_8_n_0));
  LUT6 #(
    .INIT(64'hFF00200020002000)) 
    pi_f_inc_i_9
       (.I0(temp_cmp_three_dec_min_102),
        .I1(temp_cmp_three_dec_max_102),
        .I2(tempmon_state[9]),
        .I3(update_temp_102),
        .I4(temp_cmp_four_dec_min_102),
        .I5(tempmon_state[10]),
        .O(pi_f_inc_i_9_n_0));
  FDRE pi_f_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_f_inc_nxt),
        .Q(tempmon_pi_f_inc_r_reg),
        .R(rstdiv0_sync_r1_reg_rep__13));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_10
       (.I0(four_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(four_dec_min_limit[1]),
        .O(temp_cmp_four_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_11
       (.I0(four_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(four_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_four_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_12
       (.I0(four_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(four_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_four_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_13
       (.I0(four_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(four_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_four_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_14
       (.I0(four_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(four_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_four_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_3
       (.I0(four_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(four_dec_min_limit[11]),
        .O(temp_cmp_four_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_4
       (.I0(four_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(four_dec_min_limit[9]),
        .O(temp_cmp_four_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_5
       (.I0(four_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(four_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_four_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_6
       (.I0(four_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(four_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_four_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_7
       (.I0(four_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(four_dec_min_limit[7]),
        .O(temp_cmp_four_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_8
       (.I0(four_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(four_dec_min_limit[5]),
        .O(temp_cmp_four_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_9
       (.I0(four_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(four_dec_min_limit[3]),
        .O(temp_cmp_four_dec_min_102_i_9_n_0));
  FDRE temp_cmp_four_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_four_dec_min_101),
        .Q(temp_cmp_four_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_four_dec_min_102_reg_i_1
       (.CI(temp_cmp_four_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_dec_min_101,temp_cmp_four_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_four_dec_min_102_i_3_n_0,temp_cmp_four_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_four_dec_min_102_i_5_n_0,temp_cmp_four_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_four_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_four_dec_min_102_reg_i_2_n_0,temp_cmp_four_dec_min_102_reg_i_2_n_1,temp_cmp_four_dec_min_102_reg_i_2_n_2,temp_cmp_four_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_four_dec_min_102_i_7_n_0,temp_cmp_four_dec_min_102_i_8_n_0,temp_cmp_four_dec_min_102_i_9_n_0,temp_cmp_four_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_four_dec_min_102_i_11_n_0,temp_cmp_four_dec_min_102_i_12_n_0,temp_cmp_four_dec_min_102_i_13_n_0,temp_cmp_four_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(four_inc_max_limit[0]),
        .I2(four_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_four_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(four_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(four_inc_max_limit[7]),
        .O(temp_cmp_four_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(four_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(four_inc_max_limit[5]),
        .O(temp_cmp_four_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(four_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(four_inc_max_limit[3]),
        .O(temp_cmp_four_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(four_inc_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(four_inc_max_limit[1]),
        .O(temp_cmp_four_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(four_inc_max_limit[10]),
        .I2(four_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_four_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(four_inc_max_limit[8]),
        .I2(four_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_four_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(four_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(four_inc_max_limit[11]),
        .O(temp_cmp_four_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(four_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(four_inc_max_limit[9]),
        .O(temp_cmp_four_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(four_inc_max_limit[6]),
        .I2(four_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_four_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(four_inc_max_limit[4]),
        .I2(four_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_four_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(four_inc_max_limit[2]),
        .I2(four_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_four_inc_max_102_i_9_n_0));
  FDRE temp_cmp_four_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_four_inc_max_101),
        .Q(temp_cmp_four_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_four_inc_max_102_reg_i_1
       (.CI(temp_cmp_four_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_inc_max_101,temp_cmp_four_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_four_inc_max_102_i_3_n_0,temp_cmp_four_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_four_inc_max_102_i_5_n_0,temp_cmp_four_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_four_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_four_inc_max_102_reg_i_2_n_0,temp_cmp_four_inc_max_102_reg_i_2_n_1,temp_cmp_four_inc_max_102_reg_i_2_n_2,temp_cmp_four_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_four_inc_max_102_i_7_n_0,temp_cmp_four_inc_max_102_i_8_n_0,temp_cmp_four_inc_max_102_i_9_n_0,temp_cmp_four_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_four_inc_max_102_i_11_n_0,temp_cmp_four_inc_max_102_i_12_n_0,temp_cmp_four_inc_max_102_i_13_n_0,temp_cmp_four_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(neutral_max_limit[0]),
        .I2(neutral_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_neutral_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(neutral_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(neutral_max_limit[7]),
        .O(temp_cmp_neutral_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(neutral_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(neutral_max_limit[5]),
        .O(temp_cmp_neutral_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(neutral_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(neutral_max_limit[3]),
        .O(temp_cmp_neutral_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(neutral_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(neutral_max_limit[1]),
        .O(temp_cmp_neutral_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(neutral_max_limit[10]),
        .I2(neutral_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_neutral_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(neutral_max_limit[8]),
        .I2(neutral_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_neutral_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(neutral_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(neutral_max_limit[11]),
        .O(temp_cmp_neutral_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(neutral_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(neutral_max_limit[9]),
        .O(temp_cmp_neutral_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(neutral_max_limit[6]),
        .I2(neutral_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_neutral_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(neutral_max_limit[4]),
        .I2(neutral_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_neutral_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(neutral_max_limit[2]),
        .I2(neutral_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_neutral_max_102_i_9_n_0));
  FDRE temp_cmp_neutral_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_neutral_max_101),
        .Q(temp_cmp_neutral_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_neutral_max_102_reg_i_1
       (.CI(temp_cmp_neutral_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_max_101,temp_cmp_neutral_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_neutral_max_102_i_3_n_0,temp_cmp_neutral_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_neutral_max_102_i_5_n_0,temp_cmp_neutral_max_102_i_6_n_0}));
  CARRY4 temp_cmp_neutral_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_neutral_max_102_reg_i_2_n_0,temp_cmp_neutral_max_102_reg_i_2_n_1,temp_cmp_neutral_max_102_reg_i_2_n_2,temp_cmp_neutral_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_neutral_max_102_i_7_n_0,temp_cmp_neutral_max_102_i_8_n_0,temp_cmp_neutral_max_102_i_9_n_0,temp_cmp_neutral_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_neutral_max_102_i_11_n_0,temp_cmp_neutral_max_102_i_12_n_0,temp_cmp_neutral_max_102_i_13_n_0,temp_cmp_neutral_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_10
       (.I0(neutral_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(neutral_min_limit[1]),
        .O(temp_cmp_neutral_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_11
       (.I0(neutral_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(neutral_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_neutral_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_12
       (.I0(neutral_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(neutral_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_neutral_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_13
       (.I0(neutral_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(neutral_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_neutral_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_14
       (.I0(neutral_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(neutral_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_neutral_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_3
       (.I0(neutral_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(neutral_min_limit[11]),
        .O(temp_cmp_neutral_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_4
       (.I0(neutral_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(neutral_min_limit[9]),
        .O(temp_cmp_neutral_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_5
       (.I0(neutral_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(neutral_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_neutral_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_6
       (.I0(neutral_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(neutral_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_neutral_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_7
       (.I0(neutral_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(neutral_min_limit[7]),
        .O(temp_cmp_neutral_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_8
       (.I0(neutral_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(neutral_min_limit[5]),
        .O(temp_cmp_neutral_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_9
       (.I0(neutral_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(neutral_min_limit[3]),
        .O(temp_cmp_neutral_min_102_i_9_n_0));
  FDRE temp_cmp_neutral_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_neutral_min_101),
        .Q(temp_cmp_neutral_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_neutral_min_102_reg_i_1
       (.CI(temp_cmp_neutral_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_min_101,temp_cmp_neutral_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_neutral_min_102_i_3_n_0,temp_cmp_neutral_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_neutral_min_102_i_5_n_0,temp_cmp_neutral_min_102_i_6_n_0}));
  CARRY4 temp_cmp_neutral_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_neutral_min_102_reg_i_2_n_0,temp_cmp_neutral_min_102_reg_i_2_n_1,temp_cmp_neutral_min_102_reg_i_2_n_2,temp_cmp_neutral_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_neutral_min_102_i_7_n_0,temp_cmp_neutral_min_102_i_8_n_0,temp_cmp_neutral_min_102_i_9_n_0,temp_cmp_neutral_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_neutral_min_102_i_11_n_0,temp_cmp_neutral_min_102_i_12_n_0,temp_cmp_neutral_min_102_i_13_n_0,temp_cmp_neutral_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(one_dec_max_limit[0]),
        .I2(one_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(one_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(one_dec_max_limit[7]),
        .O(temp_cmp_one_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(one_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(one_dec_max_limit[5]),
        .O(temp_cmp_one_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(one_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(one_dec_max_limit[3]),
        .O(temp_cmp_one_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(one_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_dec_max_limit[1]),
        .O(temp_cmp_one_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(one_dec_max_limit[10]),
        .I2(one_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(one_dec_max_limit[8]),
        .I2(one_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(one_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(one_dec_max_limit[11]),
        .O(temp_cmp_one_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(one_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(one_dec_max_limit[9]),
        .O(temp_cmp_one_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(one_dec_max_limit[6]),
        .I2(one_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(one_dec_max_limit[4]),
        .I2(one_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(one_dec_max_limit[2]),
        .I2(one_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_dec_max_102_i_9_n_0));
  FDRE temp_cmp_one_dec_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_dec_max_101),
        .Q(temp_cmp_one_dec_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_dec_max_102_reg_i_1
       (.CI(temp_cmp_one_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_max_101,temp_cmp_one_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_dec_max_102_i_3_n_0,temp_cmp_one_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_dec_max_102_i_5_n_0,temp_cmp_one_dec_max_102_i_6_n_0}));
  CARRY4 temp_cmp_one_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_dec_max_102_reg_i_2_n_0,temp_cmp_one_dec_max_102_reg_i_2_n_1,temp_cmp_one_dec_max_102_reg_i_2_n_2,temp_cmp_one_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_one_dec_max_102_i_7_n_0,temp_cmp_one_dec_max_102_i_8_n_0,temp_cmp_one_dec_max_102_i_9_n_0,temp_cmp_one_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_dec_max_102_i_11_n_0,temp_cmp_one_dec_max_102_i_12_n_0,temp_cmp_one_dec_max_102_i_13_n_0,temp_cmp_one_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_10
       (.I0(one_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(one_dec_min_limit[1]),
        .O(temp_cmp_one_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_11
       (.I0(one_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(one_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_12
       (.I0(one_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(one_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_13
       (.I0(one_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(one_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_14
       (.I0(one_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(one_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_3
       (.I0(one_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(one_dec_min_limit[11]),
        .O(temp_cmp_one_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_4
       (.I0(one_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(one_dec_min_limit[9]),
        .O(temp_cmp_one_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_5
       (.I0(one_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(one_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_6
       (.I0(one_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(one_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_7
       (.I0(one_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(one_dec_min_limit[7]),
        .O(temp_cmp_one_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_8
       (.I0(one_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(one_dec_min_limit[5]),
        .O(temp_cmp_one_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_9
       (.I0(one_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(one_dec_min_limit[3]),
        .O(temp_cmp_one_dec_min_102_i_9_n_0));
  FDRE temp_cmp_one_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_dec_min_101),
        .Q(temp_cmp_one_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_dec_min_102_reg_i_1
       (.CI(temp_cmp_one_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_min_101,temp_cmp_one_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_dec_min_102_i_3_n_0,temp_cmp_one_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_dec_min_102_i_5_n_0,temp_cmp_one_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_one_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_dec_min_102_reg_i_2_n_0,temp_cmp_one_dec_min_102_reg_i_2_n_1,temp_cmp_one_dec_min_102_reg_i_2_n_2,temp_cmp_one_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_one_dec_min_102_i_7_n_0,temp_cmp_one_dec_min_102_i_8_n_0,temp_cmp_one_dec_min_102_i_9_n_0,temp_cmp_one_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_dec_min_102_i_11_n_0,temp_cmp_one_dec_min_102_i_12_n_0,temp_cmp_one_dec_min_102_i_13_n_0,temp_cmp_one_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(one_inc_max_limit[0]),
        .I2(one_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(one_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(one_inc_max_limit[7]),
        .O(temp_cmp_one_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(one_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(one_inc_max_limit[5]),
        .O(temp_cmp_one_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(one_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(one_inc_max_limit[3]),
        .O(temp_cmp_one_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(one_inc_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_max_limit[1]),
        .O(temp_cmp_one_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(one_inc_max_limit[10]),
        .I2(one_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(one_inc_max_limit[8]),
        .I2(one_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(one_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(one_inc_max_limit[11]),
        .O(temp_cmp_one_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(one_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(one_inc_max_limit[9]),
        .O(temp_cmp_one_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(one_inc_max_limit[6]),
        .I2(one_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(one_inc_max_limit[4]),
        .I2(one_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(one_inc_max_limit[2]),
        .I2(one_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_inc_max_102_i_9_n_0));
  FDRE temp_cmp_one_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_inc_max_101),
        .Q(temp_cmp_one_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_inc_max_102_reg_i_1
       (.CI(temp_cmp_one_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_max_101,temp_cmp_one_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_inc_max_102_i_3_n_0,temp_cmp_one_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_inc_max_102_i_5_n_0,temp_cmp_one_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_one_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_inc_max_102_reg_i_2_n_0,temp_cmp_one_inc_max_102_reg_i_2_n_1,temp_cmp_one_inc_max_102_reg_i_2_n_2,temp_cmp_one_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_one_inc_max_102_i_7_n_0,temp_cmp_one_inc_max_102_i_8_n_0,temp_cmp_one_inc_max_102_i_9_n_0,temp_cmp_one_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_inc_max_102_i_11_n_0,temp_cmp_one_inc_max_102_i_12_n_0,temp_cmp_one_inc_max_102_i_13_n_0,temp_cmp_one_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_10
       (.I0(one_inc_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_min_limit[1]),
        .O(temp_cmp_one_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_11
       (.I0(one_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(one_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_12
       (.I0(one_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(one_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_13
       (.I0(one_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(one_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_14
       (.I0(one_inc_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(one_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_3
       (.I0(one_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(one_inc_min_limit[11]),
        .O(temp_cmp_one_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_4
       (.I0(one_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(one_inc_min_limit[9]),
        .O(temp_cmp_one_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_5
       (.I0(one_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(one_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_6
       (.I0(one_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(one_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_7
       (.I0(one_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(one_inc_min_limit[7]),
        .O(temp_cmp_one_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_8
       (.I0(one_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(one_inc_min_limit[5]),
        .O(temp_cmp_one_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_9
       (.I0(one_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(one_inc_min_limit[3]),
        .O(temp_cmp_one_inc_min_102_i_9_n_0));
  FDRE temp_cmp_one_inc_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_inc_min_101),
        .Q(temp_cmp_one_inc_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_inc_min_102_reg_i_1
       (.CI(temp_cmp_one_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_min_101,temp_cmp_one_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_inc_min_102_i_3_n_0,temp_cmp_one_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_inc_min_102_i_5_n_0,temp_cmp_one_inc_min_102_i_6_n_0}));
  CARRY4 temp_cmp_one_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_inc_min_102_reg_i_2_n_0,temp_cmp_one_inc_min_102_reg_i_2_n_1,temp_cmp_one_inc_min_102_reg_i_2_n_2,temp_cmp_one_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_one_inc_min_102_i_7_n_0,temp_cmp_one_inc_min_102_i_8_n_0,temp_cmp_one_inc_min_102_i_9_n_0,temp_cmp_one_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_inc_min_102_i_11_n_0,temp_cmp_one_inc_min_102_i_12_n_0,temp_cmp_one_inc_min_102_i_13_n_0,temp_cmp_one_inc_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(three_dec_max_limit[0]),
        .I2(three_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(three_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(three_dec_max_limit[7]),
        .O(temp_cmp_three_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(three_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(three_dec_max_limit[5]),
        .O(temp_cmp_three_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(three_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(three_dec_max_limit[3]),
        .O(temp_cmp_three_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(three_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(three_dec_max_limit[1]),
        .O(temp_cmp_three_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(three_dec_max_limit[10]),
        .I2(three_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(three_dec_max_limit[8]),
        .I2(three_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(three_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(three_dec_max_limit[11]),
        .O(temp_cmp_three_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(three_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(three_dec_max_limit[9]),
        .O(temp_cmp_three_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(three_dec_max_limit[6]),
        .I2(three_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(three_dec_max_limit[4]),
        .I2(three_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(three_dec_max_limit[2]),
        .I2(three_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_dec_max_102_i_9_n_0));
  FDRE temp_cmp_three_dec_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_dec_max_101),
        .Q(temp_cmp_three_dec_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_dec_max_102_reg_i_1
       (.CI(temp_cmp_three_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_max_101,temp_cmp_three_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_dec_max_102_i_3_n_0,temp_cmp_three_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_dec_max_102_i_5_n_0,temp_cmp_three_dec_max_102_i_6_n_0}));
  CARRY4 temp_cmp_three_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_dec_max_102_reg_i_2_n_0,temp_cmp_three_dec_max_102_reg_i_2_n_1,temp_cmp_three_dec_max_102_reg_i_2_n_2,temp_cmp_three_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_three_dec_max_102_i_7_n_0,temp_cmp_three_dec_max_102_i_8_n_0,temp_cmp_three_dec_max_102_i_9_n_0,temp_cmp_three_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_dec_max_102_i_11_n_0,temp_cmp_three_dec_max_102_i_12_n_0,temp_cmp_three_dec_max_102_i_13_n_0,temp_cmp_three_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(three_dec_min_limit[1]),
        .O(temp_cmp_three_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_11
       (.I0(three_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(three_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_12
       (.I0(three_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(three_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_13
       (.I0(three_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(three_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(three_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_3
       (.I0(three_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(three_dec_min_limit[11]),
        .O(temp_cmp_three_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_4
       (.I0(three_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(three_dec_min_limit[9]),
        .O(temp_cmp_three_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_5
       (.I0(three_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(three_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_6
       (.I0(three_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(three_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_7
       (.I0(three_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(three_dec_min_limit[7]),
        .O(temp_cmp_three_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_8
       (.I0(three_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(three_dec_min_limit[5]),
        .O(temp_cmp_three_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_9
       (.I0(three_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(three_dec_min_limit[3]),
        .O(temp_cmp_three_dec_min_102_i_9_n_0));
  FDRE temp_cmp_three_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_dec_min_101),
        .Q(temp_cmp_three_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_dec_min_102_reg_i_1
       (.CI(temp_cmp_three_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_min_101,temp_cmp_three_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_dec_min_102_i_3_n_0,temp_cmp_three_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_dec_min_102_i_5_n_0,temp_cmp_three_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_three_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_dec_min_102_reg_i_2_n_0,temp_cmp_three_dec_min_102_reg_i_2_n_1,temp_cmp_three_dec_min_102_reg_i_2_n_2,temp_cmp_three_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_three_dec_min_102_i_7_n_0,temp_cmp_three_dec_min_102_i_8_n_0,temp_cmp_three_dec_min_102_i_9_n_0,temp_cmp_three_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_dec_min_102_i_11_n_0,temp_cmp_three_dec_min_102_i_12_n_0,temp_cmp_three_dec_min_102_i_13_n_0,temp_cmp_three_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(three_inc_max_limit[0]),
        .I2(three_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(three_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(three_inc_max_limit[7]),
        .O(temp_cmp_three_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(three_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(three_inc_max_limit[5]),
        .O(temp_cmp_three_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(three_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(three_inc_max_limit[3]),
        .O(temp_cmp_three_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(three_inc_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(three_inc_max_limit[1]),
        .O(temp_cmp_three_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(three_inc_max_limit[10]),
        .I2(three_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(three_inc_max_limit[8]),
        .I2(three_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(three_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(three_inc_max_limit[11]),
        .O(temp_cmp_three_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(three_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(three_inc_max_limit[9]),
        .O(temp_cmp_three_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(three_inc_max_limit[6]),
        .I2(three_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(three_inc_max_limit[4]),
        .I2(three_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(three_inc_max_limit[2]),
        .I2(three_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_inc_max_102_i_9_n_0));
  FDRE temp_cmp_three_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_inc_max_101),
        .Q(temp_cmp_three_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_inc_max_102_reg_i_1
       (.CI(temp_cmp_three_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_max_101,temp_cmp_three_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_inc_max_102_i_3_n_0,temp_cmp_three_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_inc_max_102_i_5_n_0,temp_cmp_three_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_three_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_inc_max_102_reg_i_2_n_0,temp_cmp_three_inc_max_102_reg_i_2_n_1,temp_cmp_three_inc_max_102_reg_i_2_n_2,temp_cmp_three_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_three_inc_max_102_i_7_n_0,temp_cmp_three_inc_max_102_i_8_n_0,temp_cmp_three_inc_max_102_i_9_n_0,temp_cmp_three_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_inc_max_102_i_11_n_0,temp_cmp_three_inc_max_102_i_12_n_0,temp_cmp_three_inc_max_102_i_13_n_0,temp_cmp_three_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_10
       (.I0(three_inc_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(three_inc_min_limit[1]),
        .O(temp_cmp_three_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_11
       (.I0(three_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(three_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_12
       (.I0(three_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(three_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_13
       (.I0(three_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(three_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_14
       (.I0(three_inc_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(three_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_3
       (.I0(three_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(three_inc_min_limit[11]),
        .O(temp_cmp_three_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_4
       (.I0(three_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(three_inc_min_limit[9]),
        .O(temp_cmp_three_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_5
       (.I0(three_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(three_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_6
       (.I0(three_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(three_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_7
       (.I0(three_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(three_inc_min_limit[7]),
        .O(temp_cmp_three_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_8
       (.I0(three_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(three_inc_min_limit[5]),
        .O(temp_cmp_three_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_9
       (.I0(three_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(three_inc_min_limit[3]),
        .O(temp_cmp_three_inc_min_102_i_9_n_0));
  FDRE temp_cmp_three_inc_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_inc_min_101),
        .Q(temp_cmp_three_inc_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_inc_min_102_reg_i_1
       (.CI(temp_cmp_three_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_min_101,temp_cmp_three_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_inc_min_102_i_3_n_0,temp_cmp_three_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_inc_min_102_i_5_n_0,temp_cmp_three_inc_min_102_i_6_n_0}));
  CARRY4 temp_cmp_three_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_inc_min_102_reg_i_2_n_0,temp_cmp_three_inc_min_102_reg_i_2_n_1,temp_cmp_three_inc_min_102_reg_i_2_n_2,temp_cmp_three_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_three_inc_min_102_i_7_n_0,temp_cmp_three_inc_min_102_i_8_n_0,temp_cmp_three_inc_min_102_i_9_n_0,temp_cmp_three_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_inc_min_102_i_11_n_0,temp_cmp_three_inc_min_102_i_12_n_0,temp_cmp_three_inc_min_102_i_13_n_0,temp_cmp_three_inc_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(two_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(two_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(two_dec_max_limit[7]),
        .O(temp_cmp_two_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(two_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(two_dec_max_limit[5]),
        .O(temp_cmp_two_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(two_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(two_dec_max_limit[3]),
        .O(temp_cmp_two_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(two_dec_max_limit[1]),
        .O(temp_cmp_two_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(two_dec_max_limit[10]),
        .I2(two_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(two_dec_max_limit[8]),
        .I2(two_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(two_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(two_dec_max_limit[11]),
        .O(temp_cmp_two_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(two_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(two_dec_max_limit[9]),
        .O(temp_cmp_two_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(two_dec_max_limit[6]),
        .I2(two_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(two_dec_max_limit[4]),
        .I2(two_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(two_dec_max_limit[2]),
        .I2(two_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_dec_max_102_i_9_n_0));
  FDRE temp_cmp_two_dec_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_dec_max_101),
        .Q(temp_cmp_two_dec_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_dec_max_102_reg_i_1
       (.CI(temp_cmp_two_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_max_101,temp_cmp_two_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_dec_max_102_i_3_n_0,temp_cmp_two_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_dec_max_102_i_5_n_0,temp_cmp_two_dec_max_102_i_6_n_0}));
  CARRY4 temp_cmp_two_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_dec_max_102_reg_i_2_n_0,temp_cmp_two_dec_max_102_reg_i_2_n_1,temp_cmp_two_dec_max_102_reg_i_2_n_2,temp_cmp_two_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_two_dec_max_102_i_7_n_0,temp_cmp_two_dec_max_102_i_8_n_0,temp_cmp_two_dec_max_102_i_9_n_0,temp_cmp_two_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_dec_max_102_i_11_n_0,temp_cmp_two_dec_max_102_i_12_n_0,temp_cmp_two_dec_max_102_i_13_n_0,temp_cmp_two_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_10
       (.I0(two_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_dec_min_limit[1]),
        .O(temp_cmp_two_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_11
       (.I0(two_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(two_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_12
       (.I0(two_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(two_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_13
       (.I0(two_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(two_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_14
       (.I0(two_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_3
       (.I0(two_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(two_dec_min_limit[11]),
        .O(temp_cmp_two_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_4
       (.I0(two_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(two_dec_min_limit[9]),
        .O(temp_cmp_two_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_5
       (.I0(two_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(two_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_6
       (.I0(two_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(two_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_7
       (.I0(two_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(two_dec_min_limit[7]),
        .O(temp_cmp_two_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_8
       (.I0(two_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(two_dec_min_limit[5]),
        .O(temp_cmp_two_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_9
       (.I0(two_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(two_dec_min_limit[3]),
        .O(temp_cmp_two_dec_min_102_i_9_n_0));
  FDRE temp_cmp_two_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_dec_min_101),
        .Q(temp_cmp_two_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_dec_min_102_reg_i_1
       (.CI(temp_cmp_two_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_min_101,temp_cmp_two_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_dec_min_102_i_3_n_0,temp_cmp_two_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_dec_min_102_i_5_n_0,temp_cmp_two_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_two_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_dec_min_102_reg_i_2_n_0,temp_cmp_two_dec_min_102_reg_i_2_n_1,temp_cmp_two_dec_min_102_reg_i_2_n_2,temp_cmp_two_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_two_dec_min_102_i_7_n_0,temp_cmp_two_dec_min_102_i_8_n_0,temp_cmp_two_dec_min_102_i_9_n_0,temp_cmp_two_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_dec_min_102_i_11_n_0,temp_cmp_two_dec_min_102_i_12_n_0,temp_cmp_two_dec_min_102_i_13_n_0,temp_cmp_two_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_inc_max_limit[0]),
        .I2(two_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(two_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(two_inc_max_limit[7]),
        .O(temp_cmp_two_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(two_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(two_inc_max_limit[5]),
        .O(temp_cmp_two_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(two_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(two_inc_max_limit[3]),
        .O(temp_cmp_two_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_inc_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_max_limit[1]),
        .O(temp_cmp_two_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(two_inc_max_limit[10]),
        .I2(two_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(two_inc_max_limit[8]),
        .I2(two_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(two_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(two_inc_max_limit[11]),
        .O(temp_cmp_two_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(two_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(two_inc_max_limit[9]),
        .O(temp_cmp_two_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(two_inc_max_limit[6]),
        .I2(two_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(two_inc_max_limit[4]),
        .I2(two_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(two_inc_max_limit[2]),
        .I2(two_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_inc_max_102_i_9_n_0));
  FDRE temp_cmp_two_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_inc_max_101),
        .Q(temp_cmp_two_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_inc_max_102_reg_i_1
       (.CI(temp_cmp_two_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_max_101,temp_cmp_two_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_inc_max_102_i_3_n_0,temp_cmp_two_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_inc_max_102_i_5_n_0,temp_cmp_two_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_two_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_inc_max_102_reg_i_2_n_0,temp_cmp_two_inc_max_102_reg_i_2_n_1,temp_cmp_two_inc_max_102_reg_i_2_n_2,temp_cmp_two_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_two_inc_max_102_i_7_n_0,temp_cmp_two_inc_max_102_i_8_n_0,temp_cmp_two_inc_max_102_i_9_n_0,temp_cmp_two_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_inc_max_102_i_11_n_0,temp_cmp_two_inc_max_102_i_12_n_0,temp_cmp_two_inc_max_102_i_13_n_0,temp_cmp_two_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_10
       (.I0(two_inc_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_min_limit[1]),
        .O(temp_cmp_two_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_11
       (.I0(two_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(two_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_12
       (.I0(two_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(two_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_13
       (.I0(two_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(two_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_14
       (.I0(two_inc_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_3
       (.I0(two_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(two_inc_min_limit[11]),
        .O(temp_cmp_two_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_4
       (.I0(two_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(two_inc_min_limit[9]),
        .O(temp_cmp_two_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_5
       (.I0(two_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(two_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_6
       (.I0(two_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(two_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_7
       (.I0(two_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(two_inc_min_limit[7]),
        .O(temp_cmp_two_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_8
       (.I0(two_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(two_inc_min_limit[5]),
        .O(temp_cmp_two_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_9
       (.I0(two_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(two_inc_min_limit[3]),
        .O(temp_cmp_two_inc_min_102_i_9_n_0));
  FDRE temp_cmp_two_inc_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_inc_min_101),
        .Q(temp_cmp_two_inc_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_inc_min_102_reg_i_1
       (.CI(temp_cmp_two_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_min_101,temp_cmp_two_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_inc_min_102_i_3_n_0,temp_cmp_two_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_inc_min_102_i_5_n_0,temp_cmp_two_inc_min_102_i_6_n_0}));
  CARRY4 temp_cmp_two_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_inc_min_102_reg_i_2_n_0,temp_cmp_two_inc_min_102_reg_i_2_n_1,temp_cmp_two_inc_min_102_reg_i_2_n_2,temp_cmp_two_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_two_inc_min_102_i_7_n_0,temp_cmp_two_inc_min_102_i_8_n_0,temp_cmp_two_inc_min_102_i_9_n_0,temp_cmp_two_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_inc_min_102_i_11_n_0,temp_cmp_two_inc_min_102_i_12_n_0,temp_cmp_two_inc_min_102_i_13_n_0,temp_cmp_two_inc_min_102_i_14_n_0}));
  LUT2 #(
    .INIT(4'hE)) 
    tempmon_init_complete_i_1
       (.I0(\device_temp_init[11]_i_1_n_0 ),
        .I1(tempmon_init_complete),
        .O(tempmon_init_complete_i_1_n_0));
  FDRE tempmon_init_complete_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_init_complete_i_1_n_0),
        .Q(tempmon_init_complete),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE tempmon_sample_en_101_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_sample_en),
        .Q(tempmon_sample_en_101),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE tempmon_sample_en_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_sample_en_101),
        .Q(tempmon_sample_en_102),
        .R(rstdiv0_sync_r1_reg_rep__15));
  LUT1 #(
    .INIT(2'h1)) 
    \tempmon_state[0]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .O(\tempmon_state[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \tempmon_state[10]_i_1 
       (.I0(tempmon_state[1]),
        .I1(\tempmon_state[10]_i_3_n_0 ),
        .I2(\tempmon_state[10]_i_4_n_0 ),
        .I3(\tempmon_state[10]_i_5_n_0 ),
        .I4(\tempmon_state[10]_i_6_n_0 ),
        .I5(\tempmon_state[10]_i_7_n_0 ),
        .O(\tempmon_state[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \tempmon_state[10]_i_10 
       (.I0(tempmon_state[5]),
        .I1(tempmon_state[6]),
        .I2(tempmon_state[7]),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[9]),
        .I5(tempmon_state[10]),
        .O(\tempmon_state[10]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFEFEE8)) 
    \tempmon_state[10]_i_11 
       (.I0(tempmon_state[5]),
        .I1(tempmon_state[6]),
        .I2(tempmon_state[7]),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[9]),
        .I5(tempmon_state[10]),
        .O(\tempmon_state[10]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT4 #(
    .INIT(16'h8880)) 
    \tempmon_state[10]_i_12 
       (.I0(tempmon_state[4]),
        .I1(update_temp_102),
        .I2(temp_cmp_two_inc_min_102),
        .I3(temp_cmp_two_inc_max_102),
        .O(\tempmon_state[10]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT4 #(
    .INIT(16'h8880)) 
    \tempmon_state[10]_i_13 
       (.I0(tempmon_state[6]),
        .I1(update_temp_102),
        .I2(temp_cmp_neutral_min_102),
        .I3(temp_cmp_neutral_max_102),
        .O(\tempmon_state[10]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'hFFFFE000)) 
    \tempmon_state[10]_i_14 
       (.I0(temp_cmp_one_dec_max_102),
        .I1(temp_cmp_one_dec_min_102),
        .I2(update_temp_102),
        .I3(tempmon_state[7]),
        .I4(\tempmon_state[10]_i_15_n_0 ),
        .O(\tempmon_state[10]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT4 #(
    .INIT(16'h8880)) 
    \tempmon_state[10]_i_15 
       (.I0(tempmon_state[8]),
        .I1(update_temp_102),
        .I2(temp_cmp_two_dec_min_102),
        .I3(temp_cmp_two_dec_max_102),
        .O(\tempmon_state[10]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \tempmon_state[10]_i_2 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(update_temp_102),
        .I2(temp_cmp_three_dec_max_102),
        .I3(tempmon_state[9]),
        .O(\tempmon_state[10]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0012)) 
    \tempmon_state[10]_i_3 
       (.I0(\tempmon_state[10]_i_8_n_0 ),
        .I1(\tempmon_state[10]_i_9_n_0 ),
        .I2(\tempmon_state[10]_i_10_n_0 ),
        .I3(\tempmon_state[10]_i_11_n_0 ),
        .O(\tempmon_state[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFF00E000E000E000)) 
    \tempmon_state[10]_i_4 
       (.I0(temp_cmp_three_dec_max_102),
        .I1(temp_cmp_three_dec_min_102),
        .I2(tempmon_state[9]),
        .I3(update_temp_102),
        .I4(temp_cmp_four_dec_min_102),
        .I5(tempmon_state[10]),
        .O(\tempmon_state[10]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hF8888888)) 
    \tempmon_state[10]_i_5 
       (.I0(calib_complete),
        .I1(tempmon_state[0]),
        .I2(update_temp_102),
        .I3(temp_cmp_four_inc_max_102),
        .I4(tempmon_state[2]),
        .O(\tempmon_state[10]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'hFFFFE000)) 
    \tempmon_state[10]_i_6 
       (.I0(temp_cmp_three_inc_max_102),
        .I1(temp_cmp_three_inc_min_102),
        .I2(update_temp_102),
        .I3(tempmon_state[3]),
        .I4(\tempmon_state[10]_i_12_n_0 ),
        .O(\tempmon_state[10]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEAEAEAAA)) 
    \tempmon_state[10]_i_7 
       (.I0(\tempmon_state[10]_i_13_n_0 ),
        .I1(tempmon_state[5]),
        .I2(update_temp_102),
        .I3(temp_cmp_one_inc_min_102),
        .I4(temp_cmp_one_inc_max_102),
        .I5(\tempmon_state[10]_i_14_n_0 ),
        .O(\tempmon_state[10]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'h00010116)) 
    \tempmon_state[10]_i_8 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[1]),
        .I2(tempmon_state[2]),
        .I3(tempmon_state[3]),
        .I4(tempmon_state[4]),
        .O(\tempmon_state[10]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'hFFFEFEE8)) 
    \tempmon_state[10]_i_9 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[1]),
        .I2(tempmon_state[2]),
        .I3(tempmon_state[3]),
        .I4(tempmon_state[4]),
        .O(\tempmon_state[10]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tempmon_state[1]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(tempmon_state[0]),
        .O(\tempmon_state[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'h2A00)) 
    \tempmon_state[2]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(update_temp_102),
        .I2(temp_cmp_three_inc_max_102),
        .I3(tempmon_state[3]),
        .O(\tempmon_state[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'hAAAA0888)) 
    \tempmon_state[3]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(tempmon_state[4]),
        .I2(temp_cmp_two_inc_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[2]),
        .O(\tempmon_state[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAA88088808880888)) 
    \tempmon_state[4]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(tempmon_state[5]),
        .I2(temp_cmp_one_inc_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[3]),
        .I5(temp_cmp_three_inc_max_102),
        .O(\tempmon_state[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAA88088808880888)) 
    \tempmon_state[5]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(tempmon_state[6]),
        .I2(temp_cmp_neutral_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[4]),
        .I5(temp_cmp_two_inc_max_102),
        .O(\tempmon_state[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA80AA8080)) 
    \tempmon_state[6]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(temp_gte_one_inc_max),
        .I2(tempmon_state[5]),
        .I3(temp_gte_one_dec_max),
        .I4(tempmon_state[7]),
        .I5(tempmon_state[1]),
        .O(\tempmon_state[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tempmon_state[6]_i_2 
       (.I0(update_temp_102),
        .I1(temp_cmp_one_inc_max_102),
        .O(temp_gte_one_inc_max));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tempmon_state[6]_i_3 
       (.I0(update_temp_102),
        .I1(temp_cmp_one_dec_max_102),
        .O(temp_gte_one_dec_max));
  LUT6 #(
    .INIT(64'hAA88088808880888)) 
    \tempmon_state[7]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(tempmon_state[8]),
        .I2(temp_cmp_two_dec_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[6]),
        .I5(temp_cmp_neutral_max_102),
        .O(\tempmon_state[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAA88088808880888)) 
    \tempmon_state[8]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(tempmon_state[9]),
        .I2(temp_cmp_three_dec_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[7]),
        .I5(temp_cmp_one_dec_max_102),
        .O(\tempmon_state[8]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \tempmon_state[9]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(tempmon_state[10]),
        .I2(tempmon_state[8]),
        .I3(temp_cmp_two_dec_max_102),
        .I4(update_temp_102),
        .O(\tempmon_state[9]_i_1_n_0 ));
  FDSE \tempmon_state_reg[0] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[0]_i_1_n_0 ),
        .Q(tempmon_state[0]),
        .S(rstdiv0_sync_r1_reg_rep__13));
  FDRE \tempmon_state_reg[10] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[10]_i_2_n_0 ),
        .Q(tempmon_state[10]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[1] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[1]_i_1_n_0 ),
        .Q(tempmon_state[1]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[2] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[2]_i_1_n_0 ),
        .Q(tempmon_state[2]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[3] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[3]_i_1_n_0 ),
        .Q(tempmon_state[3]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[4] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[4]_i_1_n_0 ),
        .Q(tempmon_state[4]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[5] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[5]_i_1_n_0 ),
        .Q(tempmon_state[5]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[6] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[6]_i_1_n_0 ),
        .Q(tempmon_state[6]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[7] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[7]_i_1_n_0 ),
        .Q(tempmon_state[7]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[8] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[8]_i_1_n_0 ),
        .Q(tempmon_state[8]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  FDRE \tempmon_state_reg[9] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(\tempmon_state[9]_i_1_n_0 ),
        .Q(tempmon_state[9]),
        .R(rstdiv0_sync_r1_reg_rep__15));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[0]_i_1 
       (.I0(\three_dec_max_limit_reg[3]_i_2_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[10]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[11]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_4 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[11]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[11]_i_3 
       (.I0(device_temp_init[11]),
        .O(\three_dec_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[11]_i_4 
       (.I0(device_temp_init[10]),
        .O(\three_dec_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[11]_i_5 
       (.I0(device_temp_init[9]),
        .O(\three_dec_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[11]_i_6 
       (.I0(device_temp_init[8]),
        .O(\three_dec_max_limit[11]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[1]_i_1 
       (.I0(\three_dec_max_limit_reg[3]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[2]_i_1 
       (.I0(\three_dec_max_limit_reg[3]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[3]_i_1 
       (.I0(\three_dec_max_limit_reg[3]_i_2_n_4 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[3]_i_3 
       (.I0(device_temp_init[3]),
        .O(\three_dec_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[3]_i_4 
       (.I0(device_temp_init[2]),
        .O(\three_dec_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[3]_i_5 
       (.I0(device_temp_init[1]),
        .O(\three_dec_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[3]_i_6 
       (.I0(device_temp_init[0]),
        .O(\three_dec_max_limit[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[4]_i_1 
       (.I0(\three_dec_max_limit_reg[7]_i_2_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[5]_i_1 
       (.I0(\three_dec_max_limit_reg[7]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[6]_i_1 
       (.I0(\three_dec_max_limit_reg[7]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[7]_i_1 
       (.I0(\three_dec_max_limit_reg[7]_i_2_n_4 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[7]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[7]_i_3 
       (.I0(device_temp_init[7]),
        .O(\three_dec_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[7]_i_4 
       (.I0(device_temp_init[6]),
        .O(\three_dec_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[7]_i_5 
       (.I0(device_temp_init[5]),
        .O(\three_dec_max_limit[7]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_max_limit[7]_i_6 
       (.I0(device_temp_init[4]),
        .O(\three_dec_max_limit[7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[8]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[9]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[9]_i_1_n_0 ));
  FDRE \three_dec_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[0]_i_1_n_0 ),
        .Q(three_dec_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[10]_i_1_n_0 ),
        .Q(three_dec_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[11]_i_1_n_0 ),
        .Q(three_dec_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \three_dec_max_limit_reg[11]_i_2 
       (.CI(\three_dec_max_limit_reg[7]_i_2_n_0 ),
        .CO({p_0_in,\three_dec_max_limit_reg[11]_i_2_n_1 ,\three_dec_max_limit_reg[11]_i_2_n_2 ,\three_dec_max_limit_reg[11]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[9:8]}),
        .O({\three_dec_max_limit_reg[11]_i_2_n_4 ,\three_dec_max_limit_reg[11]_i_2_n_5 ,\three_dec_max_limit_reg[11]_i_2_n_6 ,\three_dec_max_limit_reg[11]_i_2_n_7 }),
        .S({\three_dec_max_limit[11]_i_3_n_0 ,\three_dec_max_limit[11]_i_4_n_0 ,\three_dec_max_limit[11]_i_5_n_0 ,\three_dec_max_limit[11]_i_6_n_0 }));
  FDRE \three_dec_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[1]_i_1_n_0 ),
        .Q(three_dec_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[2]_i_1_n_0 ),
        .Q(three_dec_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[3]_i_1_n_0 ),
        .Q(three_dec_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \three_dec_max_limit_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\three_dec_max_limit_reg[3]_i_2_n_0 ,\three_dec_max_limit_reg[3]_i_2_n_1 ,\three_dec_max_limit_reg[3]_i_2_n_2 ,\three_dec_max_limit_reg[3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,device_temp_init[0]}),
        .O({\three_dec_max_limit_reg[3]_i_2_n_4 ,\three_dec_max_limit_reg[3]_i_2_n_5 ,\three_dec_max_limit_reg[3]_i_2_n_6 ,\three_dec_max_limit_reg[3]_i_2_n_7 }),
        .S({\three_dec_max_limit[3]_i_3_n_0 ,\three_dec_max_limit[3]_i_4_n_0 ,\three_dec_max_limit[3]_i_5_n_0 ,\three_dec_max_limit[3]_i_6_n_0 }));
  FDRE \three_dec_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[4]_i_1_n_0 ),
        .Q(three_dec_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[5]_i_1_n_0 ),
        .Q(three_dec_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[6]_i_1_n_0 ),
        .Q(three_dec_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[7]_i_1_n_0 ),
        .Q(three_dec_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \three_dec_max_limit_reg[7]_i_2 
       (.CI(\three_dec_max_limit_reg[3]_i_2_n_0 ),
        .CO({\three_dec_max_limit_reg[7]_i_2_n_0 ,\three_dec_max_limit_reg[7]_i_2_n_1 ,\three_dec_max_limit_reg[7]_i_2_n_2 ,\three_dec_max_limit_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[6],1'b0,1'b0}),
        .O({\three_dec_max_limit_reg[7]_i_2_n_4 ,\three_dec_max_limit_reg[7]_i_2_n_5 ,\three_dec_max_limit_reg[7]_i_2_n_6 ,\three_dec_max_limit_reg[7]_i_2_n_7 }),
        .S({\three_dec_max_limit[7]_i_3_n_0 ,\three_dec_max_limit[7]_i_4_n_0 ,\three_dec_max_limit[7]_i_5_n_0 ,\three_dec_max_limit[7]_i_6_n_0 }));
  FDRE \three_dec_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[8]_i_1_n_0 ),
        .Q(three_dec_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \three_dec_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[9]_i_1_n_0 ),
        .Q(three_dec_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[11]_i_2 
       (.I0(two_dec_max_limit[11]),
        .O(\three_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[11]_i_3 
       (.I0(two_dec_max_limit[10]),
        .O(\three_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_2 
       (.I0(two_dec_max_limit[5]),
        .O(\three_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_3 
       (.I0(two_dec_max_limit[4]),
        .O(\three_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_4 
       (.I0(two_dec_max_limit[3]),
        .O(\three_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_dec_min_limit[5]_i_5 
       (.I0(two_dec_max_limit[2]),
        .O(\three_dec_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_2 
       (.I0(two_dec_max_limit[9]),
        .O(\three_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_3 
       (.I0(two_dec_max_limit[8]),
        .O(\three_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_4 
       (.I0(two_dec_max_limit[7]),
        .O(\three_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_5 
       (.I0(two_dec_max_limit[6]),
        .O(\three_dec_min_limit[9]_i_5_n_0 ));
  FDRE \three_dec_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit[0]),
        .Q(three_dec_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[10]),
        .Q(three_dec_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[11]),
        .Q(three_dec_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \three_dec_min_limit_reg[11]_i_1 
       (.CI(\three_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,two_dec_max_limit[10]}),
        .O({\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\three_dec_min_limit[11]_i_2_n_0 ,\three_dec_min_limit[11]_i_3_n_0 }));
  FDRE \three_dec_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit[1]),
        .Q(three_dec_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[2]),
        .Q(three_dec_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[3]),
        .Q(three_dec_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[4]),
        .Q(three_dec_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[5]),
        .Q(three_dec_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \three_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\three_dec_min_limit_reg[5]_i_1_n_0 ,\three_dec_min_limit_reg[5]_i_1_n_1 ,\three_dec_min_limit_reg[5]_i_1_n_2 ,\three_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({two_dec_max_limit[5:3],1'b0}),
        .O(three_dec_min_limit_nxt[5:2]),
        .S({\three_dec_min_limit[5]_i_2_n_0 ,\three_dec_min_limit[5]_i_3_n_0 ,\three_dec_min_limit[5]_i_4_n_0 ,\three_dec_min_limit[5]_i_5_n_0 }));
  FDRE \three_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[6]),
        .Q(three_dec_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[7]),
        .Q(three_dec_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[8]),
        .Q(three_dec_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \three_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[9]),
        .Q(three_dec_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \three_dec_min_limit_reg[9]_i_1 
       (.CI(\three_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\three_dec_min_limit_reg[9]_i_1_n_0 ,\three_dec_min_limit_reg[9]_i_1_n_1 ,\three_dec_min_limit_reg[9]_i_1_n_2 ,\three_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(two_dec_max_limit[9:6]),
        .O(three_dec_min_limit_nxt[9:6]),
        .S({\three_dec_min_limit[9]_i_2_n_0 ,\three_dec_min_limit[9]_i_3_n_0 ,\three_dec_min_limit[9]_i_4_n_0 ,\three_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\three_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\three_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\three_inc_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[11]_i_5 
       (.I0(device_temp_init[8]),
        .O(\three_inc_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[3]_i_2 
       (.I0(device_temp_init[3]),
        .O(\three_inc_max_limit[3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[3]_i_3 
       (.I0(device_temp_init[2]),
        .O(\three_inc_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_inc_max_limit[3]_i_4 
       (.I0(device_temp_init[1]),
        .O(\three_inc_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[3]_i_5 
       (.I0(device_temp_init[0]),
        .O(\three_inc_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[7]_i_2 
       (.I0(device_temp_init[7]),
        .O(\three_inc_max_limit[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_inc_max_limit[7]_i_3 
       (.I0(device_temp_init[6]),
        .O(\three_inc_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[7]_i_4 
       (.I0(device_temp_init[5]),
        .O(\three_inc_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_inc_max_limit[7]_i_5 
       (.I0(device_temp_init[4]),
        .O(\three_inc_max_limit[7]_i_5_n_0 ));
  FDRE \three_inc_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[0]),
        .Q(three_inc_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[10]),
        .Q(three_inc_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[11]),
        .Q(three_inc_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \three_inc_max_limit_reg[11]_i_1 
       (.CI(\three_inc_max_limit_reg[7]_i_1_n_0 ),
        .CO({\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3],\three_inc_max_limit_reg[11]_i_1_n_1 ,\three_inc_max_limit_reg[11]_i_1_n_2 ,\three_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[10],1'b0,device_temp_init[8]}),
        .O(three_inc_max_limit_nxt[11:8]),
        .S({\three_inc_max_limit[11]_i_2_n_0 ,\three_inc_max_limit[11]_i_3_n_0 ,\three_inc_max_limit[11]_i_4_n_0 ,\three_inc_max_limit[11]_i_5_n_0 }));
  FDRE \three_inc_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[1]),
        .Q(three_inc_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[2]),
        .Q(three_inc_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[3]),
        .Q(three_inc_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \three_inc_max_limit_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\three_inc_max_limit_reg[3]_i_1_n_0 ,\three_inc_max_limit_reg[3]_i_1_n_1 ,\three_inc_max_limit_reg[3]_i_1_n_2 ,\three_inc_max_limit_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[3:2],1'b0,device_temp_init[0]}),
        .O(three_inc_max_limit_nxt[3:0]),
        .S({\three_inc_max_limit[3]_i_2_n_0 ,\three_inc_max_limit[3]_i_3_n_0 ,\three_inc_max_limit[3]_i_4_n_0 ,\three_inc_max_limit[3]_i_5_n_0 }));
  FDRE \three_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[4]),
        .Q(three_inc_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[5]),
        .Q(three_inc_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[6]),
        .Q(three_inc_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[7]),
        .Q(three_inc_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \three_inc_max_limit_reg[7]_i_1 
       (.CI(\three_inc_max_limit_reg[3]_i_1_n_0 ),
        .CO({\three_inc_max_limit_reg[7]_i_1_n_0 ,\three_inc_max_limit_reg[7]_i_1_n_1 ,\three_inc_max_limit_reg[7]_i_1_n_2 ,\three_inc_max_limit_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[7],1'b0,device_temp_init[5],1'b0}),
        .O(three_inc_max_limit_nxt[7:4]),
        .S({\three_inc_max_limit[7]_i_2_n_0 ,\three_inc_max_limit[7]_i_3_n_0 ,\three_inc_max_limit[7]_i_4_n_0 ,\three_inc_max_limit[7]_i_5_n_0 }));
  FDRE \three_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[8]),
        .Q(three_inc_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[9]),
        .Q(three_inc_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[11]_i_2 
       (.I0(four_inc_max_limit[11]),
        .O(\three_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[11]_i_3 
       (.I0(four_inc_max_limit[10]),
        .O(\three_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_2 
       (.I0(four_inc_max_limit[5]),
        .O(\three_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_3 
       (.I0(four_inc_max_limit[4]),
        .O(\three_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_4 
       (.I0(four_inc_max_limit[3]),
        .O(\three_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \three_inc_min_limit[5]_i_5 
       (.I0(four_inc_max_limit[2]),
        .O(\three_inc_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_2 
       (.I0(four_inc_max_limit[9]),
        .O(\three_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_3 
       (.I0(four_inc_max_limit[8]),
        .O(\three_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_4 
       (.I0(four_inc_max_limit[7]),
        .O(\three_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_5 
       (.I0(four_inc_max_limit[6]),
        .O(\three_inc_min_limit[9]_i_5_n_0 ));
  FDRE \three_inc_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit[0]),
        .Q(three_inc_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[10]),
        .Q(three_inc_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[11]),
        .Q(three_inc_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \three_inc_min_limit_reg[11]_i_1 
       (.CI(\three_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,four_inc_max_limit[10]}),
        .O({\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\three_inc_min_limit[11]_i_2_n_0 ,\three_inc_min_limit[11]_i_3_n_0 }));
  FDRE \three_inc_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit[1]),
        .Q(three_inc_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[2]),
        .Q(three_inc_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[3]),
        .Q(three_inc_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[4]),
        .Q(three_inc_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[5]),
        .Q(three_inc_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \three_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\three_inc_min_limit_reg[5]_i_1_n_0 ,\three_inc_min_limit_reg[5]_i_1_n_1 ,\three_inc_min_limit_reg[5]_i_1_n_2 ,\three_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({four_inc_max_limit[5:3],1'b0}),
        .O(three_inc_min_limit_nxt[5:2]),
        .S({\three_inc_min_limit[5]_i_2_n_0 ,\three_inc_min_limit[5]_i_3_n_0 ,\three_inc_min_limit[5]_i_4_n_0 ,\three_inc_min_limit[5]_i_5_n_0 }));
  FDRE \three_inc_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[6]),
        .Q(three_inc_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[7]),
        .Q(three_inc_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[8]),
        .Q(three_inc_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  FDRE \three_inc_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[9]),
        .Q(three_inc_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__16));
  CARRY4 \three_inc_min_limit_reg[9]_i_1 
       (.CI(\three_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\three_inc_min_limit_reg[9]_i_1_n_0 ,\three_inc_min_limit_reg[9]_i_1_n_1 ,\three_inc_min_limit_reg[9]_i_1_n_2 ,\three_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(four_inc_max_limit[9:6]),
        .O(three_inc_min_limit_nxt[9:6]),
        .S({\three_inc_min_limit[9]_i_2_n_0 ,\three_inc_min_limit[9]_i_3_n_0 ,\three_inc_min_limit[9]_i_4_n_0 ,\three_inc_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\two_dec_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\two_dec_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\two_dec_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_max_limit[11]_i_5 
       (.I0(device_temp_init[8]),
        .O(\two_dec_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_max_limit[3]_i_2 
       (.I0(device_temp_init[3]),
        .O(\two_dec_max_limit[3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_max_limit[3]_i_3 
       (.I0(device_temp_init[2]),
        .O(\two_dec_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[3]_i_4 
       (.I0(device_temp_init[1]),
        .O(\two_dec_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[3]_i_5 
       (.I0(device_temp_init[0]),
        .O(\two_dec_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_max_limit[7]_i_2 
       (.I0(device_temp_init[7]),
        .O(\two_dec_max_limit[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[7]_i_3 
       (.I0(device_temp_init[6]),
        .O(\two_dec_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_max_limit[7]_i_4 
       (.I0(device_temp_init[5]),
        .O(\two_dec_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[7]_i_5 
       (.I0(device_temp_init[4]),
        .O(\two_dec_max_limit[7]_i_5_n_0 ));
  FDRE \two_dec_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[0]),
        .Q(two_dec_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[10]),
        .Q(two_dec_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[11]),
        .Q(two_dec_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \two_dec_max_limit_reg[11]_i_1 
       (.CI(\two_dec_max_limit_reg[7]_i_1_n_0 ),
        .CO({\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3],\two_dec_max_limit_reg[11]_i_1_n_1 ,\two_dec_max_limit_reg[11]_i_1_n_2 ,\two_dec_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[9],1'b0}),
        .O(two_dec_max_limit_nxt[11:8]),
        .S({\two_dec_max_limit[11]_i_2_n_0 ,\two_dec_max_limit[11]_i_3_n_0 ,\two_dec_max_limit[11]_i_4_n_0 ,\two_dec_max_limit[11]_i_5_n_0 }));
  FDRE \two_dec_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[1]),
        .Q(two_dec_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[2]),
        .Q(two_dec_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[3]),
        .Q(two_dec_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \two_dec_max_limit_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\two_dec_max_limit_reg[3]_i_1_n_0 ,\two_dec_max_limit_reg[3]_i_1_n_1 ,\two_dec_max_limit_reg[3]_i_1_n_2 ,\two_dec_max_limit_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[1:0]}),
        .O(two_dec_max_limit_nxt[3:0]),
        .S({\two_dec_max_limit[3]_i_2_n_0 ,\two_dec_max_limit[3]_i_3_n_0 ,\two_dec_max_limit[3]_i_4_n_0 ,\two_dec_max_limit[3]_i_5_n_0 }));
  FDRE \two_dec_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[4]),
        .Q(two_dec_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[5]),
        .Q(two_dec_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[6]),
        .Q(two_dec_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[7]),
        .Q(two_dec_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  CARRY4 \two_dec_max_limit_reg[7]_i_1 
       (.CI(\two_dec_max_limit_reg[3]_i_1_n_0 ),
        .CO({\two_dec_max_limit_reg[7]_i_1_n_0 ,\two_dec_max_limit_reg[7]_i_1_n_1 ,\two_dec_max_limit_reg[7]_i_1_n_2 ,\two_dec_max_limit_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[6],1'b0,device_temp_init[4]}),
        .O(two_dec_max_limit_nxt[7:4]),
        .S({\two_dec_max_limit[7]_i_2_n_0 ,\two_dec_max_limit[7]_i_3_n_0 ,\two_dec_max_limit[7]_i_4_n_0 ,\two_dec_max_limit[7]_i_5_n_0 }));
  FDRE \two_dec_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[8]),
        .Q(two_dec_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  FDRE \two_dec_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[9]),
        .Q(two_dec_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__17));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[11]_i_2 
       (.I0(one_dec_max_limit[11]),
        .O(\two_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[11]_i_3 
       (.I0(one_dec_max_limit[10]),
        .O(\two_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_2 
       (.I0(one_dec_max_limit[5]),
        .O(\two_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_3 
       (.I0(one_dec_max_limit[4]),
        .O(\two_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_4 
       (.I0(one_dec_max_limit[3]),
        .O(\two_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_dec_min_limit[5]_i_5 
       (.I0(one_dec_max_limit[2]),
        .O(\two_dec_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_2 
       (.I0(one_dec_max_limit[9]),
        .O(\two_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_3 
       (.I0(one_dec_max_limit[8]),
        .O(\two_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_4 
       (.I0(one_dec_max_limit[7]),
        .O(\two_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_5 
       (.I0(one_dec_max_limit[6]),
        .O(\two_dec_min_limit[9]_i_5_n_0 ));
  FDRE \two_dec_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit[0]),
        .Q(two_dec_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[10]),
        .Q(two_dec_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[11]),
        .Q(two_dec_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \two_dec_min_limit_reg[11]_i_1 
       (.CI(\two_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,one_dec_max_limit[10]}),
        .O({\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\two_dec_min_limit[11]_i_2_n_0 ,\two_dec_min_limit[11]_i_3_n_0 }));
  FDRE \two_dec_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit[1]),
        .Q(two_dec_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[2]),
        .Q(two_dec_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[3]),
        .Q(two_dec_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[4]),
        .Q(two_dec_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[5]),
        .Q(two_dec_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \two_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\two_dec_min_limit_reg[5]_i_1_n_0 ,\two_dec_min_limit_reg[5]_i_1_n_1 ,\two_dec_min_limit_reg[5]_i_1_n_2 ,\two_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({one_dec_max_limit[5:3],1'b0}),
        .O(two_dec_min_limit_nxt[5:2]),
        .S({\two_dec_min_limit[5]_i_2_n_0 ,\two_dec_min_limit[5]_i_3_n_0 ,\two_dec_min_limit[5]_i_4_n_0 ,\two_dec_min_limit[5]_i_5_n_0 }));
  FDRE \two_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[6]),
        .Q(two_dec_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[7]),
        .Q(two_dec_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[8]),
        .Q(two_dec_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  FDRE \two_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[9]),
        .Q(two_dec_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__13));
  CARRY4 \two_dec_min_limit_reg[9]_i_1 
       (.CI(\two_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\two_dec_min_limit_reg[9]_i_1_n_0 ,\two_dec_min_limit_reg[9]_i_1_n_1 ,\two_dec_min_limit_reg[9]_i_1_n_2 ,\two_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(one_dec_max_limit[9:6]),
        .O(two_dec_min_limit_nxt[9:6]),
        .S({\two_dec_min_limit[9]_i_2_n_0 ,\two_dec_min_limit[9]_i_3_n_0 ,\two_dec_min_limit[9]_i_4_n_0 ,\two_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\two_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\two_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\two_inc_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_inc_max_limit[11]_i_5 
       (.I0(device_temp_init[8]),
        .O(\two_inc_max_limit[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[3]_i_2 
       (.I0(device_temp_init[3]),
        .O(\two_inc_max_limit[3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_inc_max_limit[3]_i_3 
       (.I0(device_temp_init[2]),
        .O(\two_inc_max_limit[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[3]_i_4 
       (.I0(device_temp_init[1]),
        .O(\two_inc_max_limit[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[3]_i_5 
       (.I0(device_temp_init[0]),
        .O(\two_inc_max_limit[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[7]_i_2 
       (.I0(device_temp_init[7]),
        .O(\two_inc_max_limit[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_inc_max_limit[7]_i_3 
       (.I0(device_temp_init[6]),
        .O(\two_inc_max_limit[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_inc_max_limit[7]_i_4 
       (.I0(device_temp_init[5]),
        .O(\two_inc_max_limit[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[7]_i_5 
       (.I0(device_temp_init[4]),
        .O(\two_inc_max_limit[7]_i_5_n_0 ));
  FDRE \two_inc_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[0]),
        .Q(two_inc_max_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[10]),
        .Q(two_inc_max_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[11]),
        .Q(two_inc_max_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \two_inc_max_limit_reg[11]_i_1 
       (.CI(\two_inc_max_limit_reg[7]_i_1_n_0 ),
        .CO({\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3],\two_inc_max_limit_reg[11]_i_1_n_1 ,\two_inc_max_limit_reg[11]_i_1_n_2 ,\two_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[10:9],1'b0}),
        .O(two_inc_max_limit_nxt[11:8]),
        .S({\two_inc_max_limit[11]_i_2_n_0 ,\two_inc_max_limit[11]_i_3_n_0 ,\two_inc_max_limit[11]_i_4_n_0 ,\two_inc_max_limit[11]_i_5_n_0 }));
  FDRE \two_inc_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[1]),
        .Q(two_inc_max_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[2]),
        .Q(two_inc_max_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[3]),
        .Q(two_inc_max_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \two_inc_max_limit_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\two_inc_max_limit_reg[3]_i_1_n_0 ,\two_inc_max_limit_reg[3]_i_1_n_1 ,\two_inc_max_limit_reg[3]_i_1_n_2 ,\two_inc_max_limit_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[3],1'b0,device_temp_init[1:0]}),
        .O(two_inc_max_limit_nxt[3:0]),
        .S({\two_inc_max_limit[3]_i_2_n_0 ,\two_inc_max_limit[3]_i_3_n_0 ,\two_inc_max_limit[3]_i_4_n_0 ,\two_inc_max_limit[3]_i_5_n_0 }));
  FDRE \two_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[4]),
        .Q(two_inc_max_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[5]),
        .Q(two_inc_max_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[6]),
        .Q(two_inc_max_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[7]),
        .Q(two_inc_max_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \two_inc_max_limit_reg[7]_i_1 
       (.CI(\two_inc_max_limit_reg[3]_i_1_n_0 ),
        .CO({\two_inc_max_limit_reg[7]_i_1_n_0 ,\two_inc_max_limit_reg[7]_i_1_n_1 ,\two_inc_max_limit_reg[7]_i_1_n_2 ,\two_inc_max_limit_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[7],1'b0,1'b0,device_temp_init[4]}),
        .O(two_inc_max_limit_nxt[7:4]),
        .S({\two_inc_max_limit[7]_i_2_n_0 ,\two_inc_max_limit[7]_i_3_n_0 ,\two_inc_max_limit[7]_i_4_n_0 ,\two_inc_max_limit[7]_i_5_n_0 }));
  FDRE \two_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[8]),
        .Q(two_inc_max_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[9]),
        .Q(two_inc_max_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[11]_i_2 
       (.I0(three_inc_max_limit[11]),
        .O(\two_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[11]_i_3 
       (.I0(three_inc_max_limit[10]),
        .O(\two_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_2 
       (.I0(three_inc_max_limit[5]),
        .O(\two_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_3 
       (.I0(three_inc_max_limit[4]),
        .O(\two_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_4 
       (.I0(three_inc_max_limit[3]),
        .O(\two_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \two_inc_min_limit[5]_i_5 
       (.I0(three_inc_max_limit[2]),
        .O(\two_inc_min_limit[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_2 
       (.I0(three_inc_max_limit[9]),
        .O(\two_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_3 
       (.I0(three_inc_max_limit[8]),
        .O(\two_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_4 
       (.I0(three_inc_max_limit[7]),
        .O(\two_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_5 
       (.I0(three_inc_max_limit[6]),
        .O(\two_inc_min_limit[9]_i_5_n_0 ));
  FDRE \two_inc_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit[0]),
        .Q(two_inc_min_limit[0]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[10]),
        .Q(two_inc_min_limit[10]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[11]),
        .Q(two_inc_min_limit[11]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \two_inc_min_limit_reg[11]_i_1 
       (.CI(\two_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,three_inc_max_limit[10]}),
        .O({\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\two_inc_min_limit[11]_i_2_n_0 ,\two_inc_min_limit[11]_i_3_n_0 }));
  FDRE \two_inc_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit[1]),
        .Q(two_inc_min_limit[1]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[2]),
        .Q(two_inc_min_limit[2]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[3]),
        .Q(two_inc_min_limit[3]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[4]),
        .Q(two_inc_min_limit[4]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[5]),
        .Q(two_inc_min_limit[5]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \two_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\two_inc_min_limit_reg[5]_i_1_n_0 ,\two_inc_min_limit_reg[5]_i_1_n_1 ,\two_inc_min_limit_reg[5]_i_1_n_2 ,\two_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({three_inc_max_limit[5:3],1'b0}),
        .O(two_inc_min_limit_nxt[5:2]),
        .S({\two_inc_min_limit[5]_i_2_n_0 ,\two_inc_min_limit[5]_i_3_n_0 ,\two_inc_min_limit[5]_i_4_n_0 ,\two_inc_min_limit[5]_i_5_n_0 }));
  FDRE \two_inc_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[6]),
        .Q(two_inc_min_limit[6]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[7]),
        .Q(two_inc_min_limit[7]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[8]),
        .Q(two_inc_min_limit[8]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  FDRE \two_inc_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[9]),
        .Q(two_inc_min_limit[9]),
        .R(rstdiv0_sync_r1_reg_rep__14));
  CARRY4 \two_inc_min_limit_reg[9]_i_1 
       (.CI(\two_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\two_inc_min_limit_reg[9]_i_1_n_0 ,\two_inc_min_limit_reg[9]_i_1_n_1 ,\two_inc_min_limit_reg[9]_i_1_n_2 ,\two_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(three_inc_max_limit[9:6]),
        .O(two_inc_min_limit_nxt[9:6]),
        .S({\two_inc_min_limit[9]_i_2_n_0 ,\two_inc_min_limit[9]_i_3_n_0 ,\two_inc_min_limit[9]_i_4_n_0 ,\two_inc_min_limit[9]_i_5_n_0 }));
  LUT3 #(
    .INIT(8'h40)) 
    update_temp_102_i_1
       (.I0(tempmon_sample_en_102),
        .I1(tempmon_init_complete),
        .I2(tempmon_sample_en_101),
        .O(update_temp_101));
  FDRE update_temp_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(update_temp_101),
        .Q(update_temp_102),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_top" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_top
   (ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_reset_n,
    out,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \rd_ptr_timing_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \rd_ptr_timing_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \rd_ptr_timing_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    init_complete_r_timing,
    \read_fifo.tail_r_reg[1] ,
    complex_row1_rd_done_reg,
    rdlvl_stg1_start_r_reg,
    init_calib_complete,
    app_zq_r_reg,
    \data_offset_2_i1_reg[2] ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    \my_empty_reg[7]_7 ,
    dqs_po_en_stg2_f_reg,
    idelay_tap_limit_r_reg,
    samp_edge_cnt0_en_r,
    fine_dly_dec_done_r1_reg,
    phy_mc_ctl_full,
    rd_active_r_reg,
    \read_fifo.tail_r_reg[1]_0 ,
    rd_buf_we,
    \cmd_pipe_plus.mc_data_offset_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    \read_fifo.tail_r_reg[3] ,
    ADDRA,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \not_strict_mode.app_rd_data_reg[352] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    phy_mc_data_full,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    rst_sync_r1_reg,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \not_strict_mode.app_rd_data_reg[488] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \idelay_tap_cnt_r_reg[0][7][3] ,
    maint_prescaler_r1,
    maint_ref_zq_wip_r_reg,
    D,
    \cmd_pipe_plus.mc_data_offset_1_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[1] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[4] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[1] ,
    \read_fifo.tail_r_reg[0] ,
    \read_fifo.tail_r_reg[1]_1 ,
    \cmd_pipe_plus.mc_data_offset_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    DIA,
    DIB,
    DIC,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ,
    phy_dout,
    \wr_ptr_timing_reg[0] ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \not_strict_mode.app_rd_data_reg[511] ,
    \not_strict_mode.app_rd_data_reg[24] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7]_10 ,
    \wr_ptr_timing_reg[3]_0 ,
    \wr_ptr_timing_reg[0]_0 ,
    \wr_ptr_timing_reg[3]_1 ,
    \wr_ptr_timing_reg[0]_1 ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_timing_reg[3]_2 ,
    \my_empty_reg[7]_11 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_2 ,
    \wr_ptr_timing_reg[3]_3 ,
    \my_empty_reg[7]_12 ,
    \wr_ptr_reg[0]_1 ,
    \wr_ptr_reg[1]_3 ,
    \wr_ptr_timing_reg[3]_4 ,
    \my_empty_reg[7]_13 ,
    p_0_in1_in,
    \not_strict_mode.app_rd_data_reg[232] ,
    \not_strict_mode.app_rd_data_reg[496]_0 ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    wr_en,
    wr_en_10,
    wr_en_11,
    of_ctl_full_v,
    wr_en_12,
    wr_en_13,
    wr_en_14,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    CLK,
    A_rst_primitives_reg,
    pll_lock,
    rstdiv0_sync_r1,
    sys_rst_0,
    rstdiv0_sync_r1_reg_rep__0,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    rstdiv0_sync_r1_reg_rep__1,
    idle,
    rstdiv0_sync_r1_reg_rep__4,
    rstdiv0_sync_r1_reg_rep__3,
    rstdiv0_sync_r1_reg_rep__18,
    init_complete_r_timing_reg,
    rstdiv0_sync_r1_reg_rep__24,
    SR,
    rstdiv0_sync_r1_reg_rep__10,
    rstdiv0_sync_r1_reg_rep__2,
    rstdiv0_sync_r1_reg_rep__24_0,
    rstdiv0_sync_r1_reg_rep__13,
    tempmon_sample_en,
    rstdiv0_sync_r1_reg_rep__15,
    rstdiv0_sync_r1_reg_rep__22,
    ram_init_done_r,
    Q,
    tail_r,
    rstdiv0_sync_r1_reg_rep__21,
    mem_out,
    sys_rst,
    iodelay_ctrl_rdy,
    sys_rst_1,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    refresh_bank_r,
    sent_col,
    col_rd_wr,
    complex_row0_rd_done1,
    rstdiv0_sync_r1_reg_rep__23,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ,
    mc_cas_n,
    mc_ras_n,
    mc_odt,
    mc_cke,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[0]_0 ,
    mc_cmd,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \write_buffer.wr_buf_out_data_reg[575] ,
    DOC,
    DOB,
    DOA,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    ram_init_addr,
    \write_buffer.wr_buf_out_data_reg[351] ,
    rstdiv0_sync_r1_reg_rep,
    rstdiv0_sync_r1_reg_rep__9,
    rstdiv0_sync_r1_reg_rep__7,
    rstdiv0_sync_r1_reg_rep__6,
    SS,
    rstdiv0_sync_r1_reg_rep__24_1,
    rstdiv0_sync_r1_reg_rep__24_2,
    rstdiv0_sync_r1_reg_rep__24_3,
    rstdiv0_sync_r1_reg_rep__24_4,
    \device_temp_r_reg[11] ,
    rstdiv0_sync_r1_reg_rep__16,
    rstdiv0_sync_r1_reg_rep__14,
    rstdiv0_sync_r1_reg_rep__17,
    \rd_ptr_reg_rep[3] ,
    \rd_ptr_reg_rep[3]_0 ,
    mc_cs_n,
    \rd_ptr_reg_rep[3]_1 ,
    \rd_ptr_reg_rep[3]_2 ,
    \rd_ptr_reg_rep[3]_3 ,
    \rd_ptr_reg_rep[3]_4 ,
    rstdiv0_sync_r1_reg_rep__12);
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [1:0]out;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output [1:0]\rd_ptr_timing_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output init_complete_r_timing;
  output \read_fifo.tail_r_reg[1] ;
  output complex_row1_rd_done_reg;
  output rdlvl_stg1_start_r_reg;
  output init_calib_complete;
  output app_zq_r_reg;
  output \data_offset_2_i1_reg[2] ;
  output \my_empty_reg[7] ;
  output \my_empty_reg[7]_0 ;
  output \my_empty_reg[7]_1 ;
  output \my_empty_reg[7]_2 ;
  output \my_empty_reg[7]_3 ;
  output \my_empty_reg[7]_4 ;
  output \my_empty_reg[7]_5 ;
  output \my_empty_reg[7]_6 ;
  output \my_empty_reg[7]_7 ;
  output dqs_po_en_stg2_f_reg;
  output idelay_tap_limit_r_reg;
  output samp_edge_cnt0_en_r;
  output fine_dly_dec_done_r1_reg;
  output phy_mc_ctl_full;
  output rd_active_r_reg;
  output \read_fifo.tail_r_reg[1]_0 ;
  output rd_buf_we;
  output \cmd_pipe_plus.mc_data_offset_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_reg[5] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  output \read_fifo.tail_r_reg[3] ;
  output [2:0]ADDRA;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  output phy_mc_data_full;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  output rst_sync_r1_reg;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  output [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \idelay_tap_cnt_r_reg[0][7][3] ;
  output maint_prescaler_r1;
  output maint_ref_zq_wip_r_reg;
  output [0:0]D;
  output [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  output \cmd_pipe_plus.mc_data_offset_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  output \read_fifo.tail_r_reg[0] ;
  output \read_fifo.tail_r_reg[1]_1 ;
  output \cmd_pipe_plus.mc_data_offset_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  output [1:0]DIA;
  output [1:0]DIB;
  output [1:0]DIC;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  output [4:0]phy_dout;
  output [44:0]\wr_ptr_timing_reg[0] ;
  output [207:0]\my_empty_reg[7]_8 ;
  output [31:0]\my_empty_reg[7]_9 ;
  output [511:0]\not_strict_mode.app_rd_data_reg[511] ;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7]_10 ;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\wr_ptr_timing_reg[0]_1 ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1]_1 ;
  output [3:0]\wr_ptr_timing_reg[3]_2 ;
  output [3:0]\my_empty_reg[7]_11 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_2 ;
  output [3:0]\wr_ptr_timing_reg[3]_3 ;
  output [3:0]\my_empty_reg[7]_12 ;
  output \wr_ptr_reg[0]_1 ;
  output \wr_ptr_reg[1]_3 ;
  output [3:0]\wr_ptr_timing_reg[3]_4 ;
  output [3:0]\my_empty_reg[7]_13 ;
  output p_0_in1_in;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \not_strict_mode.app_rd_data_reg[496]_0 ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output wr_en;
  output wr_en_10;
  output wr_en_11;
  output [0:0]of_ctl_full_v;
  output wr_en_12;
  output wr_en_13;
  output wr_en_14;
  output [1:0]ddr_ck_out;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input CLK;
  input A_rst_primitives_reg;
  input pll_lock;
  input rstdiv0_sync_r1;
  input sys_rst_0;
  input rstdiv0_sync_r1_reg_rep__0;
  input A_rst_primitives_reg_0;
  input A_rst_primitives_reg_1;
  input A_rst_primitives_reg_2;
  input A_rst_primitives_reg_3;
  input A_rst_primitives_reg_4;
  input A_rst_primitives_reg_5;
  input A_rst_primitives_reg_6;
  input rstdiv0_sync_r1_reg_rep__1;
  input idle;
  input rstdiv0_sync_r1_reg_rep__4;
  input rstdiv0_sync_r1_reg_rep__3;
  input rstdiv0_sync_r1_reg_rep__18;
  input init_complete_r_timing_reg;
  input rstdiv0_sync_r1_reg_rep__24;
  input [0:0]SR;
  input [1:0]rstdiv0_sync_r1_reg_rep__10;
  input [0:0]rstdiv0_sync_r1_reg_rep__2;
  input rstdiv0_sync_r1_reg_rep__24_0;
  input [0:0]rstdiv0_sync_r1_reg_rep__13;
  input tempmon_sample_en;
  input [0:0]rstdiv0_sync_r1_reg_rep__15;
  input rstdiv0_sync_r1_reg_rep__22;
  input ram_init_done_r;
  input [1:0]Q;
  input [3:0]tail_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input [63:0]mem_out;
  input sys_rst;
  input [0:0]iodelay_ctrl_rdy;
  input sys_rst_1;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input refresh_bank_r;
  input sent_col;
  input col_rd_wr;
  input complex_row0_rd_done1;
  input rstdiv0_sync_r1_reg_rep__23;
  input mc_wrdata_en;
  input \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  input [2:0]mc_cas_n;
  input [2:0]mc_ras_n;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [2:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  input \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  input \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  input [1:0]mc_cmd;
  input [38:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input [575:0]\write_buffer.wr_buf_out_data_reg[575] ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]DOA;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  input \read_fifo.fifo_out_data_r_reg[5] ;
  input [0:0]ram_init_addr;
  input [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  input rstdiv0_sync_r1_reg_rep;
  input [0:0]rstdiv0_sync_r1_reg_rep__9;
  input [1:0]rstdiv0_sync_r1_reg_rep__7;
  input [0:0]rstdiv0_sync_r1_reg_rep__6;
  input [0:0]SS;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  input [11:0]\device_temp_r_reg[11] ;
  input [0:0]rstdiv0_sync_r1_reg_rep__16;
  input [0:0]rstdiv0_sync_r1_reg_rep__14;
  input [0:0]rstdiv0_sync_r1_reg_rep__17;
  input [79:0]\rd_ptr_reg_rep[3] ;
  input [41:0]\rd_ptr_reg_rep[3]_0 ;
  input [0:0]mc_cs_n;
  input [79:0]\rd_ptr_reg_rep[3]_1 ;
  input [79:0]\rd_ptr_reg_rep[3]_2 ;
  input [79:0]\rd_ptr_reg_rep[3]_3 ;
  input [79:0]\rd_ptr_reg_rep[3]_4 ;
  input [0:0]rstdiv0_sync_r1_reg_rep__12;

  wire [2:0]ADDRA;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire CLK;
  wire [0:0]D;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire app_zq_r_reg;
  wire calib_cmd_wren;
  wire calib_in_common;
  wire [4:0]calib_sel;
  wire calib_wrdata_en;
  wire [38:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[2] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[2] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire col_rd_wr;
  wire complex_row0_rd_done1;
  wire complex_row1_rd_done_reg;
  wire [5:0]data_offset_1;
  wire [5:0]data_offset_2;
  wire \data_offset_2_i1_reg[2] ;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire [11:0]\device_temp_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire dqs_po_en_stg2_f_reg;
  wire fine_dly_dec_done_r1_reg;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_i_1_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \genblk24.phy_ctl_pre_fifo_0/wr_en ;
  wire \genblk24.phy_ctl_pre_fifo_1/wr_en ;
  wire \genblk24.phy_ctl_pre_fifo_2/wr_en ;
  wire idelay_inc;
  wire \idelay_tap_cnt_r_reg[0][7][3] ;
  wire idelay_tap_limit_r_reg;
  wire idle;
  wire init_calib_complete;
  wire init_complete_r_timing;
  wire init_complete_r_timing_reg;
  wire [0:0]iodelay_ctrl_rdy;
  wire maint_prescaler_r1;
  wire maint_ref_zq_wip_r_reg;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire mc_wrdata_en;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire [54:8]mux_address;
  wire mux_reset_n;
  wire [479:1]mux_wrdata;
  wire [59:0]mux_wrdata_mask;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_10 ;
  wire [3:0]\my_empty_reg[7]_11 ;
  wire [3:0]\my_empty_reg[7]_12 ;
  wire [3:0]\my_empty_reg[7]_13 ;
  wire \my_empty_reg[7]_2 ;
  wire \my_empty_reg[7]_3 ;
  wire \my_empty_reg[7]_4 ;
  wire \my_empty_reg[7]_5 ;
  wire \my_empty_reg[7]_6 ;
  wire \my_empty_reg[7]_7 ;
  wire [207:0]\my_empty_reg[7]_8 ;
  wire [31:0]\my_empty_reg[7]_9 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  wire [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  wire \not_strict_mode.app_rd_data_reg[496]_0 ;
  wire [511:0]\not_strict_mode.app_rd_data_reg[511] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  wire [0:0]of_ctl_full_v;
  wire [1:0]out;
  wire p_0_in1_in;
  wire phy_cmd_wr_en;
  wire phy_ctl_ready;
  wire [24:0]phy_ctl_wd;
  wire phy_data_wr_en;
  wire [4:0]phy_dout;
  wire phy_if_reset;
  wire phy_if_reset0;
  wire phy_if_reset_w;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire pll_lock;
  wire [2:0]po_stg2_wrcal_cnt;
  wire [0:0]ram_init_addr;
  wire ram_init_done_r;
  wire rd_active_r_reg;
  wire rd_buf_we;
  wire [79:0]\rd_ptr_reg_rep[3] ;
  wire [41:0]\rd_ptr_reg_rep[3]_0 ;
  wire [79:0]\rd_ptr_reg_rep[3]_1 ;
  wire [79:0]\rd_ptr_reg_rep[3]_2 ;
  wire [79:0]\rd_ptr_reg_rep[3]_3 ;
  wire [79:0]\rd_ptr_reg_rep[3]_4 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rd_ptr_timing_reg[1]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1]_1 ;
  wire rdlvl_stg1_start_r_reg;
  wire read_calib;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire \read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire \read_fifo.tail_r_reg[1]_1 ;
  wire \read_fifo.tail_r_reg[3] ;
  wire refresh_bank_r;
  wire reset_if;
  wire rst_sync_r1_reg;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire [1:0]rstdiv0_sync_r1_reg_rep__10;
  wire [0:0]rstdiv0_sync_r1_reg_rep__12;
  wire [0:0]rstdiv0_sync_r1_reg_rep__13;
  wire [0:0]rstdiv0_sync_r1_reg_rep__14;
  wire [0:0]rstdiv0_sync_r1_reg_rep__15;
  wire [0:0]rstdiv0_sync_r1_reg_rep__16;
  wire [0:0]rstdiv0_sync_r1_reg_rep__17;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire [0:0]rstdiv0_sync_r1_reg_rep__2;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__22;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__24_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire rstdiv0_sync_r1_reg_rep__4;
  wire [0:0]rstdiv0_sync_r1_reg_rep__6;
  wire [1:0]rstdiv0_sync_r1_reg_rep__7;
  wire [0:0]rstdiv0_sync_r1_reg_rep__9;
  wire samp_edge_cnt0_en_r;
  wire sent_col;
  wire sync_pulse;
  wire sys_rst;
  wire sys_rst_0;
  wire sys_rst_1;
  wire [3:0]tail_r;
  wire tempmon_pi_f_dec;
  wire tempmon_pi_f_inc;
  wire tempmon_sample_en;
  wire tempmon_sel_pi_incdec;
  wire u_ddr_calib_top_n_104;
  wire u_ddr_calib_top_n_1056;
  wire u_ddr_calib_top_n_1057;
  wire u_ddr_calib_top_n_106;
  wire u_ddr_calib_top_n_108;
  wire u_ddr_calib_top_n_110;
  wire u_ddr_calib_top_n_111;
  wire u_ddr_calib_top_n_112;
  wire u_ddr_calib_top_n_1122;
  wire u_ddr_calib_top_n_1123;
  wire u_ddr_calib_top_n_1124;
  wire u_ddr_calib_top_n_1125;
  wire u_ddr_calib_top_n_1126;
  wire u_ddr_calib_top_n_1127;
  wire u_ddr_calib_top_n_1128;
  wire u_ddr_calib_top_n_1129;
  wire u_ddr_calib_top_n_113;
  wire u_ddr_calib_top_n_114;
  wire u_ddr_calib_top_n_115;
  wire u_ddr_calib_top_n_116;
  wire u_ddr_calib_top_n_117;
  wire u_ddr_calib_top_n_118;
  wire u_ddr_calib_top_n_119;
  wire u_ddr_calib_top_n_12;
  wire u_ddr_calib_top_n_120;
  wire u_ddr_calib_top_n_121;
  wire u_ddr_calib_top_n_1274;
  wire u_ddr_calib_top_n_1275;
  wire u_ddr_calib_top_n_1276;
  wire u_ddr_calib_top_n_13;
  wire u_ddr_calib_top_n_1344;
  wire u_ddr_calib_top_n_1345;
  wire u_ddr_calib_top_n_136;
  wire u_ddr_calib_top_n_14;
  wire u_ddr_calib_top_n_15;
  wire u_ddr_calib_top_n_16;
  wire u_ddr_calib_top_n_17;
  wire u_ddr_calib_top_n_18;
  wire u_ddr_calib_top_n_19;
  wire u_ddr_calib_top_n_20;
  wire u_ddr_calib_top_n_21;
  wire u_ddr_calib_top_n_22;
  wire u_ddr_calib_top_n_23;
  wire u_ddr_calib_top_n_24;
  wire u_ddr_calib_top_n_41;
  wire u_ddr_calib_top_n_64;
  wire u_ddr_calib_top_n_69;
  wire u_ddr_calib_top_n_693;
  wire u_ddr_calib_top_n_70;
  wire u_ddr_calib_top_n_71;
  wire u_ddr_calib_top_n_72;
  wire u_ddr_calib_top_n_79;
  wire u_ddr_calib_top_n_80;
  wire u_ddr_calib_top_n_808;
  wire u_ddr_calib_top_n_809;
  wire u_ddr_calib_top_n_81;
  wire u_ddr_calib_top_n_810;
  wire u_ddr_calib_top_n_811;
  wire u_ddr_calib_top_n_812;
  wire u_ddr_calib_top_n_813;
  wire u_ddr_calib_top_n_814;
  wire u_ddr_calib_top_n_815;
  wire u_ddr_calib_top_n_82;
  wire u_ddr_calib_top_n_83;
  wire u_ddr_calib_top_n_84;
  wire u_ddr_calib_top_n_85;
  wire u_ddr_calib_top_n_86;
  wire u_ddr_calib_top_n_87;
  wire u_ddr_calib_top_n_877;
  wire u_ddr_calib_top_n_878;
  wire u_ddr_calib_top_n_879;
  wire u_ddr_calib_top_n_88;
  wire u_ddr_calib_top_n_89;
  wire u_ddr_calib_top_n_90;
  wire u_ddr_calib_top_n_91;
  wire u_ddr_calib_top_n_919;
  wire u_ddr_calib_top_n_92;
  wire u_ddr_calib_top_n_920;
  wire u_ddr_calib_top_n_921;
  wire u_ddr_calib_top_n_922;
  wire u_ddr_calib_top_n_923;
  wire u_ddr_calib_top_n_93;
  wire u_ddr_calib_top_n_94;
  wire u_ddr_calib_top_n_95;
  wire u_ddr_calib_top_n_96;
  wire u_ddr_calib_top_n_97;
  wire u_ddr_calib_top_n_98;
  wire u_ddr_calib_top_n_99;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_idelay_ce13_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_en116_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_fine_enable112_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_fine_inc114_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_rst_dqs_find110_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_coarse_enable98_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_fine_enable96_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_fine_inc100_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_idelay_ce9_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_en38_out ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_fine_enable34_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_fine_inc36_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_rst_dqs_find32_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_coarse_enable20_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_fine_enable18_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_fine_inc22_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_idelay_ce5_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_en64_out ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_fine_enable60_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_fine_inc62_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_rst_dqs_find58_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_coarse_enable46_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_fine_enable44_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_fine_inc48_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_idelay_ce1_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_en90_out ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_fine_enable86_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_fine_inc88_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_rst_dqs_find84_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_coarse_enable72_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_fine_enable70_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_fine_inc74_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ;
  wire [7:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;
  wire [7:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;
  wire [7:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;
  wire [7:2]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;
  wire [6:1]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_idelay_ce19_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_load_en161_out ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_read_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_fine_enable157_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_fine_inc159_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_rst_dqs_find155_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_coarse_enable143_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_fine_enable141_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_fine_inc145_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_rst_primitives ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_coarse_enable27_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_fine_enable24_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_fine_inc30_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable66_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable63_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc69_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable105_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable102_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc108_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst0 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;
  wire [6:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;
  wire [6:4]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;
  wire [43:8]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_idelay_ce10_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_en87_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_fine_enable83_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_fine_inc85_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_rst_dqs_find81_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_coarse_enable69_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_fine_enable67_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_fine_inc71_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_idelay_ce6_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_of_data_full ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_en35_out ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_fine_enable31_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_fine_inc33_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_rst_dqs_find29_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_coarse_enable17_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_fine_enable15_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_fine_inc19_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_idelay_ce2_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_of_data_full ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_en61_out ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_fine_enable57_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_fine_inc59_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_rst_dqs_find55_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_coarse_enable43_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_fine_enable41_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_fine_inc45_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;
  wire u_ddr_mc_phy_wrapper_n_10;
  wire u_ddr_mc_phy_wrapper_n_11;
  wire u_ddr_mc_phy_wrapper_n_12;
  wire u_ddr_mc_phy_wrapper_n_13;
  wire u_ddr_mc_phy_wrapper_n_1525;
  wire u_ddr_mc_phy_wrapper_n_1526;
  wire u_ddr_mc_phy_wrapper_n_1527;
  wire u_ddr_mc_phy_wrapper_n_1528;
  wire u_ddr_mc_phy_wrapper_n_1529;
  wire u_ddr_mc_phy_wrapper_n_1530;
  wire u_ddr_mc_phy_wrapper_n_1531;
  wire u_ddr_mc_phy_wrapper_n_1532;
  wire u_ddr_mc_phy_wrapper_n_1533;
  wire u_ddr_mc_phy_wrapper_n_1534;
  wire u_ddr_mc_phy_wrapper_n_1535;
  wire u_ddr_mc_phy_wrapper_n_1536;
  wire u_ddr_mc_phy_wrapper_n_1537;
  wire u_ddr_mc_phy_wrapper_n_1538;
  wire u_ddr_mc_phy_wrapper_n_1539;
  wire u_ddr_mc_phy_wrapper_n_1540;
  wire u_ddr_mc_phy_wrapper_n_1541;
  wire u_ddr_mc_phy_wrapper_n_1542;
  wire u_ddr_mc_phy_wrapper_n_1543;
  wire u_ddr_mc_phy_wrapper_n_1544;
  wire u_ddr_mc_phy_wrapper_n_1545;
  wire u_ddr_mc_phy_wrapper_n_1546;
  wire u_ddr_mc_phy_wrapper_n_1547;
  wire u_ddr_mc_phy_wrapper_n_1548;
  wire u_ddr_mc_phy_wrapper_n_1549;
  wire u_ddr_mc_phy_wrapper_n_1550;
  wire u_ddr_mc_phy_wrapper_n_1551;
  wire u_ddr_mc_phy_wrapper_n_1552;
  wire u_ddr_mc_phy_wrapper_n_1553;
  wire u_ddr_mc_phy_wrapper_n_1554;
  wire u_ddr_mc_phy_wrapper_n_1555;
  wire u_ddr_mc_phy_wrapper_n_1556;
  wire u_ddr_mc_phy_wrapper_n_1557;
  wire u_ddr_mc_phy_wrapper_n_1558;
  wire u_ddr_mc_phy_wrapper_n_1559;
  wire u_ddr_mc_phy_wrapper_n_1560;
  wire u_ddr_mc_phy_wrapper_n_1561;
  wire u_ddr_mc_phy_wrapper_n_1562;
  wire u_ddr_mc_phy_wrapper_n_1563;
  wire u_ddr_mc_phy_wrapper_n_1564;
  wire u_ddr_mc_phy_wrapper_n_1565;
  wire u_ddr_mc_phy_wrapper_n_1566;
  wire u_ddr_mc_phy_wrapper_n_1567;
  wire u_ddr_mc_phy_wrapper_n_1568;
  wire u_ddr_mc_phy_wrapper_n_1569;
  wire u_ddr_mc_phy_wrapper_n_1570;
  wire u_ddr_mc_phy_wrapper_n_1571;
  wire u_ddr_mc_phy_wrapper_n_1572;
  wire u_ddr_mc_phy_wrapper_n_1573;
  wire u_ddr_mc_phy_wrapper_n_1574;
  wire u_ddr_mc_phy_wrapper_n_1575;
  wire u_ddr_mc_phy_wrapper_n_1576;
  wire u_ddr_mc_phy_wrapper_n_1577;
  wire u_ddr_mc_phy_wrapper_n_1578;
  wire u_ddr_mc_phy_wrapper_n_1579;
  wire u_ddr_mc_phy_wrapper_n_1580;
  wire u_ddr_mc_phy_wrapper_n_1581;
  wire u_ddr_mc_phy_wrapper_n_1582;
  wire u_ddr_mc_phy_wrapper_n_1583;
  wire u_ddr_mc_phy_wrapper_n_1584;
  wire u_ddr_mc_phy_wrapper_n_1585;
  wire u_ddr_mc_phy_wrapper_n_1586;
  wire u_ddr_mc_phy_wrapper_n_1587;
  wire u_ddr_mc_phy_wrapper_n_1588;
  wire u_ddr_mc_phy_wrapper_n_1589;
  wire u_ddr_mc_phy_wrapper_n_1590;
  wire u_ddr_mc_phy_wrapper_n_1591;
  wire u_ddr_mc_phy_wrapper_n_1592;
  wire u_ddr_mc_phy_wrapper_n_1593;
  wire u_ddr_mc_phy_wrapper_n_1594;
  wire u_ddr_mc_phy_wrapper_n_1595;
  wire u_ddr_mc_phy_wrapper_n_1596;
  wire u_ddr_mc_phy_wrapper_n_1597;
  wire u_ddr_mc_phy_wrapper_n_1598;
  wire u_ddr_mc_phy_wrapper_n_1599;
  wire u_ddr_mc_phy_wrapper_n_1600;
  wire u_ddr_mc_phy_wrapper_n_1601;
  wire u_ddr_mc_phy_wrapper_n_1602;
  wire u_ddr_mc_phy_wrapper_n_1603;
  wire u_ddr_mc_phy_wrapper_n_1604;
  wire u_ddr_mc_phy_wrapper_n_1605;
  wire u_ddr_mc_phy_wrapper_n_1606;
  wire u_ddr_mc_phy_wrapper_n_1607;
  wire u_ddr_mc_phy_wrapper_n_1608;
  wire u_ddr_mc_phy_wrapper_n_1609;
  wire u_ddr_mc_phy_wrapper_n_161;
  wire u_ddr_mc_phy_wrapper_n_1610;
  wire u_ddr_mc_phy_wrapper_n_1611;
  wire u_ddr_mc_phy_wrapper_n_1612;
  wire u_ddr_mc_phy_wrapper_n_1613;
  wire u_ddr_mc_phy_wrapper_n_1614;
  wire u_ddr_mc_phy_wrapper_n_1615;
  wire u_ddr_mc_phy_wrapper_n_1616;
  wire u_ddr_mc_phy_wrapper_n_1617;
  wire u_ddr_mc_phy_wrapper_n_1618;
  wire u_ddr_mc_phy_wrapper_n_1619;
  wire u_ddr_mc_phy_wrapper_n_1620;
  wire u_ddr_mc_phy_wrapper_n_1621;
  wire u_ddr_mc_phy_wrapper_n_1622;
  wire u_ddr_mc_phy_wrapper_n_1623;
  wire u_ddr_mc_phy_wrapper_n_1624;
  wire u_ddr_mc_phy_wrapper_n_1625;
  wire u_ddr_mc_phy_wrapper_n_1626;
  wire u_ddr_mc_phy_wrapper_n_1627;
  wire u_ddr_mc_phy_wrapper_n_1628;
  wire u_ddr_mc_phy_wrapper_n_1629;
  wire u_ddr_mc_phy_wrapper_n_163;
  wire u_ddr_mc_phy_wrapper_n_1630;
  wire u_ddr_mc_phy_wrapper_n_1631;
  wire u_ddr_mc_phy_wrapper_n_1632;
  wire u_ddr_mc_phy_wrapper_n_1633;
  wire u_ddr_mc_phy_wrapper_n_1634;
  wire u_ddr_mc_phy_wrapper_n_1635;
  wire u_ddr_mc_phy_wrapper_n_1636;
  wire u_ddr_mc_phy_wrapper_n_1637;
  wire u_ddr_mc_phy_wrapper_n_1638;
  wire u_ddr_mc_phy_wrapper_n_1639;
  wire u_ddr_mc_phy_wrapper_n_164;
  wire u_ddr_mc_phy_wrapper_n_1640;
  wire u_ddr_mc_phy_wrapper_n_1641;
  wire u_ddr_mc_phy_wrapper_n_1642;
  wire u_ddr_mc_phy_wrapper_n_1643;
  wire u_ddr_mc_phy_wrapper_n_1644;
  wire u_ddr_mc_phy_wrapper_n_1645;
  wire u_ddr_mc_phy_wrapper_n_1646;
  wire u_ddr_mc_phy_wrapper_n_1647;
  wire u_ddr_mc_phy_wrapper_n_1648;
  wire u_ddr_mc_phy_wrapper_n_1649;
  wire u_ddr_mc_phy_wrapper_n_165;
  wire u_ddr_mc_phy_wrapper_n_1650;
  wire u_ddr_mc_phy_wrapper_n_1651;
  wire u_ddr_mc_phy_wrapper_n_1652;
  wire u_ddr_mc_phy_wrapper_n_1653;
  wire u_ddr_mc_phy_wrapper_n_1654;
  wire u_ddr_mc_phy_wrapper_n_1655;
  wire u_ddr_mc_phy_wrapper_n_1656;
  wire u_ddr_mc_phy_wrapper_n_1657;
  wire u_ddr_mc_phy_wrapper_n_1658;
  wire u_ddr_mc_phy_wrapper_n_1659;
  wire u_ddr_mc_phy_wrapper_n_1660;
  wire u_ddr_mc_phy_wrapper_n_1661;
  wire u_ddr_mc_phy_wrapper_n_1662;
  wire u_ddr_mc_phy_wrapper_n_1663;
  wire u_ddr_mc_phy_wrapper_n_1664;
  wire u_ddr_mc_phy_wrapper_n_1665;
  wire u_ddr_mc_phy_wrapper_n_1666;
  wire u_ddr_mc_phy_wrapper_n_1667;
  wire u_ddr_mc_phy_wrapper_n_1668;
  wire u_ddr_mc_phy_wrapper_n_1669;
  wire u_ddr_mc_phy_wrapper_n_1670;
  wire u_ddr_mc_phy_wrapper_n_1671;
  wire u_ddr_mc_phy_wrapper_n_1672;
  wire u_ddr_mc_phy_wrapper_n_1673;
  wire u_ddr_mc_phy_wrapper_n_1674;
  wire u_ddr_mc_phy_wrapper_n_1675;
  wire u_ddr_mc_phy_wrapper_n_1676;
  wire u_ddr_mc_phy_wrapper_n_1677;
  wire u_ddr_mc_phy_wrapper_n_1678;
  wire u_ddr_mc_phy_wrapper_n_1679;
  wire u_ddr_mc_phy_wrapper_n_1680;
  wire u_ddr_mc_phy_wrapper_n_1681;
  wire u_ddr_mc_phy_wrapper_n_1682;
  wire u_ddr_mc_phy_wrapper_n_1683;
  wire u_ddr_mc_phy_wrapper_n_1684;
  wire u_ddr_mc_phy_wrapper_n_1685;
  wire u_ddr_mc_phy_wrapper_n_1686;
  wire u_ddr_mc_phy_wrapper_n_1687;
  wire u_ddr_mc_phy_wrapper_n_1688;
  wire u_ddr_mc_phy_wrapper_n_1689;
  wire u_ddr_mc_phy_wrapper_n_1690;
  wire u_ddr_mc_phy_wrapper_n_1691;
  wire u_ddr_mc_phy_wrapper_n_1692;
  wire u_ddr_mc_phy_wrapper_n_1693;
  wire u_ddr_mc_phy_wrapper_n_1694;
  wire u_ddr_mc_phy_wrapper_n_1695;
  wire u_ddr_mc_phy_wrapper_n_1696;
  wire u_ddr_mc_phy_wrapper_n_1697;
  wire u_ddr_mc_phy_wrapper_n_1698;
  wire u_ddr_mc_phy_wrapper_n_1699;
  wire u_ddr_mc_phy_wrapper_n_1700;
  wire u_ddr_mc_phy_wrapper_n_173;
  wire u_ddr_mc_phy_wrapper_n_1731;
  wire u_ddr_mc_phy_wrapper_n_1732;
  wire u_ddr_mc_phy_wrapper_n_1733;
  wire u_ddr_mc_phy_wrapper_n_1734;
  wire u_ddr_mc_phy_wrapper_n_1735;
  wire u_ddr_mc_phy_wrapper_n_1736;
  wire u_ddr_mc_phy_wrapper_n_174;
  wire u_ddr_mc_phy_wrapper_n_1741;
  wire u_ddr_mc_phy_wrapper_n_1742;
  wire u_ddr_mc_phy_wrapper_n_1743;
  wire u_ddr_mc_phy_wrapper_n_1744;
  wire u_ddr_mc_phy_wrapper_n_1745;
  wire u_ddr_mc_phy_wrapper_n_1746;
  wire u_ddr_mc_phy_wrapper_n_1747;
  wire u_ddr_mc_phy_wrapper_n_1748;
  wire u_ddr_mc_phy_wrapper_n_1749;
  wire u_ddr_mc_phy_wrapper_n_1750;
  wire u_ddr_mc_phy_wrapper_n_1751;
  wire u_ddr_mc_phy_wrapper_n_1752;
  wire u_ddr_mc_phy_wrapper_n_1753;
  wire u_ddr_mc_phy_wrapper_n_1754;
  wire u_ddr_mc_phy_wrapper_n_1756;
  wire u_ddr_mc_phy_wrapper_n_1757;
  wire u_ddr_mc_phy_wrapper_n_1758;
  wire u_ddr_mc_phy_wrapper_n_1759;
  wire u_ddr_mc_phy_wrapper_n_1760;
  wire u_ddr_mc_phy_wrapper_n_1761;
  wire u_ddr_mc_phy_wrapper_n_1762;
  wire u_ddr_mc_phy_wrapper_n_1763;
  wire u_ddr_mc_phy_wrapper_n_1764;
  wire u_ddr_mc_phy_wrapper_n_1765;
  wire u_ddr_mc_phy_wrapper_n_1766;
  wire u_ddr_mc_phy_wrapper_n_1767;
  wire u_ddr_mc_phy_wrapper_n_1768;
  wire u_ddr_mc_phy_wrapper_n_1769;
  wire u_ddr_mc_phy_wrapper_n_1770;
  wire u_ddr_mc_phy_wrapper_n_1771;
  wire u_ddr_mc_phy_wrapper_n_1772;
  wire u_ddr_mc_phy_wrapper_n_1773;
  wire u_ddr_mc_phy_wrapper_n_1774;
  wire u_ddr_mc_phy_wrapper_n_1775;
  wire u_ddr_mc_phy_wrapper_n_1776;
  wire u_ddr_mc_phy_wrapper_n_1777;
  wire u_ddr_mc_phy_wrapper_n_1778;
  wire u_ddr_mc_phy_wrapper_n_1779;
  wire u_ddr_mc_phy_wrapper_n_1780;
  wire u_ddr_mc_phy_wrapper_n_1781;
  wire u_ddr_mc_phy_wrapper_n_1782;
  wire u_ddr_mc_phy_wrapper_n_1783;
  wire u_ddr_mc_phy_wrapper_n_1784;
  wire u_ddr_mc_phy_wrapper_n_1785;
  wire u_ddr_mc_phy_wrapper_n_1786;
  wire u_ddr_mc_phy_wrapper_n_1787;
  wire u_ddr_mc_phy_wrapper_n_1788;
  wire u_ddr_mc_phy_wrapper_n_1789;
  wire u_ddr_mc_phy_wrapper_n_1790;
  wire u_ddr_mc_phy_wrapper_n_1791;
  wire u_ddr_mc_phy_wrapper_n_1792;
  wire u_ddr_mc_phy_wrapper_n_1793;
  wire u_ddr_mc_phy_wrapper_n_1794;
  wire u_ddr_mc_phy_wrapper_n_1795;
  wire u_ddr_mc_phy_wrapper_n_1796;
  wire u_ddr_mc_phy_wrapper_n_1797;
  wire u_ddr_mc_phy_wrapper_n_1798;
  wire u_ddr_mc_phy_wrapper_n_1799;
  wire u_ddr_mc_phy_wrapper_n_1800;
  wire u_ddr_mc_phy_wrapper_n_1801;
  wire u_ddr_mc_phy_wrapper_n_1802;
  wire u_ddr_mc_phy_wrapper_n_1803;
  wire u_ddr_mc_phy_wrapper_n_1804;
  wire u_ddr_mc_phy_wrapper_n_1805;
  wire u_ddr_mc_phy_wrapper_n_1806;
  wire u_ddr_mc_phy_wrapper_n_1807;
  wire u_ddr_mc_phy_wrapper_n_1808;
  wire u_ddr_mc_phy_wrapper_n_1809;
  wire u_ddr_mc_phy_wrapper_n_1810;
  wire u_ddr_mc_phy_wrapper_n_1811;
  wire u_ddr_mc_phy_wrapper_n_1812;
  wire u_ddr_mc_phy_wrapper_n_1813;
  wire u_ddr_mc_phy_wrapper_n_182;
  wire u_ddr_mc_phy_wrapper_n_183;
  wire u_ddr_mc_phy_wrapper_n_191;
  wire u_ddr_mc_phy_wrapper_n_192;
  wire u_ddr_mc_phy_wrapper_n_200;
  wire u_ddr_mc_phy_wrapper_n_202;
  wire u_ddr_mc_phy_wrapper_n_276;
  wire u_ddr_mc_phy_wrapper_n_352;
  wire u_ddr_mc_phy_wrapper_n_42;
  wire u_ddr_mc_phy_wrapper_n_426;
  wire u_ddr_mc_phy_wrapper_n_427;
  wire u_ddr_mc_phy_wrapper_n_428;
  wire u_ddr_mc_phy_wrapper_n_44;
  wire u_ddr_mc_phy_wrapper_n_445;
  wire u_ddr_mc_phy_wrapper_n_448;
  wire u_ddr_mc_phy_wrapper_n_457;
  wire u_ddr_mc_phy_wrapper_n_466;
  wire u_ddr_mc_phy_wrapper_n_475;
  wire u_ddr_mc_phy_wrapper_n_484;
  wire u_ddr_mc_phy_wrapper_n_493;
  wire u_ddr_mc_phy_wrapper_n_502;
  wire u_ddr_mc_phy_wrapper_n_511;
  wire u_ddr_mc_phy_wrapper_n_512;
  wire u_ddr_mc_phy_wrapper_n_513;
  wire u_ddr_mc_phy_wrapper_n_514;
  wire u_ddr_mc_phy_wrapper_n_515;
  wire u_ddr_mc_phy_wrapper_n_516;
  wire u_ddr_mc_phy_wrapper_n_517;
  wire u_ddr_mc_phy_wrapper_n_518;
  wire u_ddr_mc_phy_wrapper_n_519;
  wire u_ddr_mc_phy_wrapper_n_520;
  wire u_ddr_mc_phy_wrapper_n_529;
  wire u_ddr_mc_phy_wrapper_n_538;
  wire u_ddr_mc_phy_wrapper_n_547;
  wire u_ddr_mc_phy_wrapper_n_556;
  wire u_ddr_mc_phy_wrapper_n_565;
  wire u_ddr_mc_phy_wrapper_n_574;
  wire u_ddr_mc_phy_wrapper_n_583;
  wire u_ddr_mc_phy_wrapper_n_584;
  wire u_ddr_mc_phy_wrapper_n_585;
  wire u_ddr_mc_phy_wrapper_n_586;
  wire u_ddr_mc_phy_wrapper_n_587;
  wire u_ddr_mc_phy_wrapper_n_588;
  wire u_ddr_mc_phy_wrapper_n_589;
  wire u_ddr_mc_phy_wrapper_n_590;
  wire u_ddr_mc_phy_wrapper_n_591;
  wire u_ddr_mc_phy_wrapper_n_596;
  wire u_ddr_mc_phy_wrapper_n_6;
  wire u_ddr_mc_phy_wrapper_n_605;
  wire u_ddr_mc_phy_wrapper_n_614;
  wire u_ddr_mc_phy_wrapper_n_623;
  wire u_ddr_mc_phy_wrapper_n_632;
  wire u_ddr_mc_phy_wrapper_n_641;
  wire u_ddr_mc_phy_wrapper_n_650;
  wire u_ddr_mc_phy_wrapper_n_659;
  wire u_ddr_mc_phy_wrapper_n_660;
  wire u_ddr_mc_phy_wrapper_n_661;
  wire u_ddr_mc_phy_wrapper_n_662;
  wire u_ddr_mc_phy_wrapper_n_663;
  wire u_ddr_mc_phy_wrapper_n_664;
  wire u_ddr_mc_phy_wrapper_n_665;
  wire u_ddr_mc_phy_wrapper_n_666;
  wire u_ddr_mc_phy_wrapper_n_667;
  wire u_ddr_mc_phy_wrapper_n_668;
  wire u_ddr_mc_phy_wrapper_n_677;
  wire u_ddr_mc_phy_wrapper_n_686;
  wire u_ddr_mc_phy_wrapper_n_695;
  wire u_ddr_mc_phy_wrapper_n_7;
  wire u_ddr_mc_phy_wrapper_n_704;
  wire u_ddr_mc_phy_wrapper_n_713;
  wire u_ddr_mc_phy_wrapper_n_722;
  wire u_ddr_mc_phy_wrapper_n_731;
  wire u_ddr_mc_phy_wrapper_n_732;
  wire u_ddr_mc_phy_wrapper_n_733;
  wire u_ddr_mc_phy_wrapper_n_734;
  wire u_ddr_mc_phy_wrapper_n_735;
  wire u_ddr_mc_phy_wrapper_n_736;
  wire u_ddr_mc_phy_wrapper_n_737;
  wire u_ddr_mc_phy_wrapper_n_738;
  wire u_ddr_mc_phy_wrapper_n_739;
  wire u_ddr_mc_phy_wrapper_n_8;
  wire u_ddr_mc_phy_wrapper_n_82;
  wire u_ddr_mc_phy_wrapper_n_87;
  wire u_ddr_mc_phy_wrapper_n_9;
  wire u_ddr_mc_phy_wrapper_n_968;
  wire u_ddr_mc_phy_wrapper_n_969;
  wire u_ddr_mc_phy_wrapper_n_970;
  wire u_ddr_mc_phy_wrapper_n_971;
  wire u_ddr_mc_phy_wrapper_n_972;
  wire u_ddr_mc_phy_wrapper_n_973;
  wire u_ddr_mc_phy_wrapper_n_974;
  wire u_ddr_mc_phy_wrapper_n_975;
  wire u_ddr_mc_phy_wrapper_n_976;
  wire u_ddr_mc_phy_wrapper_n_977;
  wire \u_ddr_phy_wrcal/p_0_out ;
  wire wr_en;
  wire wr_en_10;
  wire wr_en_11;
  wire wr_en_12;
  wire wr_en_13;
  wire wr_en_14;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[0]_1 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;
  wire \wr_ptr_reg[1]_3 ;
  wire [44:0]\wr_ptr_timing_reg[0] ;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;
  wire [3:0]\wr_ptr_timing_reg[0]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3]_3 ;
  wire [3:0]\wr_ptr_timing_reg[3]_4 ;
  wire [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  wire [575:0]\write_buffer.wr_buf_out_data_reg[575] ;
  wire write_calib;
  wire wrlvl_final_if_rst;

  LUT6 #(
    .INIT(64'h0505070505050405)) 
    \gen_byte_sel_div2.calib_in_common_i_1 
       (.I0(u_ddr_calib_top_n_1344),
        .I1(u_ddr_calib_top_n_104),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .I3(u_ddr_calib_top_n_136),
        .I4(u_ddr_calib_top_n_1345),
        .I5(calib_in_common),
        .O(\gen_byte_sel_div2.calib_in_common_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    phy_if_reset_i_1
       (.I0(reset_if),
        .I1(phy_if_reset_w),
        .I2(wrlvl_final_if_rst),
        .O(phy_if_reset0));
  LUT2 #(
    .INIT(4'hE)) 
    tempmon_pi_f_en_r_i_1
       (.I0(tempmon_pi_f_inc),
        .I1(tempmon_pi_f_dec),
        .O(tempmon_sel_pi_incdec));
  mig_7series_0_mig_7series_v2_3_ddr_calib_top u_ddr_calib_top
       (.A_idelay_ce10_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_idelay_ce10_out ),
        .A_idelay_ce13_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_idelay_ce13_out ),
        .A_idelay_ce19_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_idelay_ce19_out ),
        .A_pi_counter_load_en116_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_en116_out ),
        .A_pi_counter_load_en161_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_load_en161_out ),
        .A_pi_counter_load_en87_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_en87_out ),
        .A_pi_fine_enable112_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_fine_enable112_out ),
        .A_pi_fine_enable157_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_fine_enable157_out ),
        .A_pi_fine_enable83_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_fine_enable83_out ),
        .A_pi_fine_inc114_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_fine_inc114_out ),
        .A_pi_fine_inc159_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_fine_inc159_out ),
        .A_pi_fine_inc85_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_fine_inc85_out ),
        .A_pi_rst_dqs_find110_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_rst_dqs_find110_out ),
        .A_pi_rst_dqs_find155_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_rst_dqs_find155_out ),
        .A_pi_rst_dqs_find81_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_rst_dqs_find81_out ),
        .A_po_coarse_enable143_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_coarse_enable143_out ),
        .A_po_coarse_enable69_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_coarse_enable69_out ),
        .A_po_coarse_enable98_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_coarse_enable98_out ),
        .A_po_fine_enable141_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_fine_enable141_out ),
        .A_po_fine_enable67_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_fine_enable67_out ),
        .A_po_fine_enable96_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_fine_enable96_out ),
        .A_po_fine_inc100_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_fine_inc100_out ),
        .A_po_fine_inc145_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_fine_inc145_out ),
        .A_po_fine_inc71_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_fine_inc71_out ),
        .A_rst_primitives(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_rst_primitives ),
        .A_rst_primitives_reg(u_ddr_mc_phy_wrapper_n_445),
        .B_idelay_ce6_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_idelay_ce6_out ),
        .B_idelay_ce9_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_idelay_ce9_out ),
        .B_of_data_full(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_of_data_full ),
        .B_pi_counter_load_en35_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_en35_out ),
        .B_pi_counter_load_en38_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_en38_out ),
        .B_pi_fine_enable31_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_fine_enable31_out ),
        .B_pi_fine_enable34_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_fine_enable34_out ),
        .B_pi_fine_inc33_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_fine_inc33_out ),
        .B_pi_fine_inc36_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_fine_inc36_out ),
        .B_pi_rst_dqs_find29_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_rst_dqs_find29_out ),
        .B_pi_rst_dqs_find32_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_rst_dqs_find32_out ),
        .B_po_coarse_enable17_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_coarse_enable17_out ),
        .B_po_coarse_enable20_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_coarse_enable20_out ),
        .B_po_coarse_enable27_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_coarse_enable27_out ),
        .B_po_fine_enable15_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_fine_enable15_out ),
        .B_po_fine_enable18_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_fine_enable18_out ),
        .B_po_fine_enable24_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_fine_enable24_out ),
        .B_po_fine_inc19_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_fine_inc19_out ),
        .B_po_fine_inc22_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_fine_inc22_out ),
        .B_po_fine_inc30_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_fine_inc30_out ),
        .CLK(CLK),
        .COUNTERLOADVAL({u_ddr_calib_top_n_81,u_ddr_calib_top_n_82,u_ddr_calib_top_n_83,u_ddr_calib_top_n_84,u_ddr_calib_top_n_85,u_ddr_calib_top_n_86}),
        .COUNTERREADVAL(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_read_val ),
        .C_idelay_ce2_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_idelay_ce2_out ),
        .C_idelay_ce5_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_idelay_ce5_out ),
        .C_of_data_full(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_of_data_full ),
        .C_pi_counter_load_en61_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_en61_out ),
        .C_pi_counter_load_en64_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_en64_out ),
        .C_pi_fine_enable57_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_fine_enable57_out ),
        .C_pi_fine_enable60_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_fine_enable60_out ),
        .C_pi_fine_inc59_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_fine_inc59_out ),
        .C_pi_fine_inc62_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_fine_inc62_out ),
        .C_pi_rst_dqs_find55_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_rst_dqs_find55_out ),
        .C_pi_rst_dqs_find58_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_rst_dqs_find58_out ),
        .C_po_coarse_enable43_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_coarse_enable43_out ),
        .C_po_coarse_enable46_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_coarse_enable46_out ),
        .C_po_coarse_enable66_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable66_out ),
        .C_po_fine_enable41_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_fine_enable41_out ),
        .C_po_fine_enable44_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_fine_enable44_out ),
        .C_po_fine_enable63_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable63_out ),
        .C_po_fine_inc45_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_fine_inc45_out ),
        .C_po_fine_inc48_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_fine_inc48_out ),
        .C_po_fine_inc69_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc69_out ),
        .D({u_ddr_calib_top_n_111,u_ddr_calib_top_n_112,u_ddr_calib_top_n_113,u_ddr_calib_top_n_114,u_ddr_calib_top_n_115,u_ddr_calib_top_n_116}),
        .D0({u_ddr_calib_top_n_808,u_ddr_calib_top_n_809,u_ddr_calib_top_n_810,u_ddr_calib_top_n_811,u_ddr_calib_top_n_812,u_ddr_calib_top_n_813,u_ddr_calib_top_n_814,u_ddr_calib_top_n_815}),
        .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .D2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .D_idelay_ce1_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_idelay_ce1_out ),
        .D_pi_counter_load_en90_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_en90_out ),
        .D_pi_fine_enable86_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_fine_enable86_out ),
        .D_pi_fine_inc88_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_fine_inc88_out ),
        .D_pi_rst_dqs_find84_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_rst_dqs_find84_out ),
        .D_po_coarse_enable105_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable105_out ),
        .D_po_coarse_enable72_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_coarse_enable72_out ),
        .D_po_fine_enable102_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable102_out ),
        .D_po_fine_enable70_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_fine_enable70_out ),
        .D_po_fine_inc108_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc108_out ),
        .D_po_fine_inc74_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_fine_inc74_out ),
        .E(u_ddr_calib_top_n_106),
        .Q({calib_sel[4:3],calib_sel[1:0]}),
        .SR(SR),
        .SS(SS),
        .app_zq_r_reg(app_zq_r_reg),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_in_common(calib_in_common),
        .calib_wrdata_en(calib_wrdata_en),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0] (\cmd_pipe_plus.mc_data_offset_1_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[1] (\cmd_pipe_plus.mc_data_offset_1_reg[1] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[2] (\cmd_pipe_plus.mc_data_offset_1_reg[2] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[4] (\cmd_pipe_plus.mc_data_offset_1_reg[4] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[1] (\cmd_pipe_plus.mc_data_offset_2_reg[1] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[1]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[2] (\cmd_pipe_plus.mc_data_offset_2_reg[2] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[2]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[3] (\cmd_pipe_plus.mc_data_offset_2_reg[3] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[4] (\cmd_pipe_plus.mc_data_offset_2_reg[4] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[4]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (\cmd_pipe_plus.mc_data_offset_2_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[0] (\cmd_pipe_plus.mc_data_offset_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[1] (\cmd_pipe_plus.mc_data_offset_reg[1] ),
        .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[2] (\cmd_pipe_plus.mc_data_offset_reg[2] ),
        .\cmd_pipe_plus.mc_data_offset_reg[2]_0 (\cmd_pipe_plus.mc_data_offset_reg[2]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[3] (D),
        .\cmd_pipe_plus.mc_data_offset_reg[3]_0 (\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .\cmd_pipe_plus.mc_data_offset_reg[4] (\cmd_pipe_plus.mc_data_offset_reg[4] ),
        .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),
        .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ),
        .col_rd_wr(col_rd_wr),
        .complex_row0_rd_done1(complex_row0_rd_done1),
        .complex_row1_rd_done_reg(complex_row1_rd_done_reg),
        .\data_offset_1_i1_reg[5] (data_offset_1),
        .\data_offset_2_i1_reg[2] (\data_offset_2_i1_reg[2] ),
        .\data_offset_2_i1_reg[3] (u_ddr_calib_top_n_24),
        .\data_offset_2_i1_reg[5] (data_offset_2),
        .\device_temp_r_reg[11] (\device_temp_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (u_ddr_calib_top_n_693),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (u_ddr_calib_top_n_64),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (u_ddr_calib_top_n_69),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (u_ddr_calib_top_n_70),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (u_ddr_calib_top_n_71),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (u_ddr_calib_top_n_1274),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (u_ddr_calib_top_n_1275),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (u_ddr_calib_top_n_1276),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (u_ddr_mc_phy_wrapper_n_165),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (u_ddr_mc_phy_wrapper_n_87),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (u_ddr_mc_phy_wrapper_n_352),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (u_ddr_mc_phy_wrapper_n_192),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (u_ddr_mc_phy_wrapper_n_183),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (u_ddr_mc_phy_wrapper_n_174),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (u_ddr_mc_phy_wrapper_n_202),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (u_ddr_mc_phy_wrapper_n_276),
        .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg),
        .\entry_cnt_reg[3] (u_ddr_calib_top_n_1056),
        .\entry_cnt_reg[3]_0 (u_ddr_calib_top_n_1057),
        .fine_dly_dec_done_r1_reg(fine_dly_dec_done_r1_reg),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 (u_ddr_calib_top_n_136),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 (po_stg2_wrcal_cnt),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (u_ddr_calib_top_n_104),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (u_ddr_calib_top_n_1344),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (u_ddr_calib_top_n_1345),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_3(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_4(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_6(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_7(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_8(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .\idelay_tap_cnt_r_reg[0][7][3] (\idelay_tap_cnt_r_reg[0][7][3] ),
        .idelay_tap_limit_r_reg(idelay_tap_limit_r_reg),
        .init_calib_complete(init_calib_complete),
        .init_calib_complete_reg_rep__28_0({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}),
        .init_complete_r_timing(init_complete_r_timing),
        .init_complete_r_timing_reg(init_complete_r_timing_reg),
        .maint_prescaler_r1(maint_prescaler_r1),
        .maint_ref_zq_wip_r_reg(maint_ref_zq_wip_r_reg),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out({u_ddr_mc_phy_wrapper_n_1525,u_ddr_mc_phy_wrapper_n_1526,u_ddr_mc_phy_wrapper_n_1527,u_ddr_mc_phy_wrapper_n_1528,u_ddr_mc_phy_wrapper_n_1529,u_ddr_mc_phy_wrapper_n_1530,u_ddr_mc_phy_wrapper_n_1531,u_ddr_mc_phy_wrapper_n_1532,u_ddr_mc_phy_wrapper_n_1533,u_ddr_mc_phy_wrapper_n_1534,u_ddr_mc_phy_wrapper_n_1535,u_ddr_mc_phy_wrapper_n_1536,u_ddr_mc_phy_wrapper_n_1537,u_ddr_mc_phy_wrapper_n_1538,u_ddr_mc_phy_wrapper_n_1539,u_ddr_mc_phy_wrapper_n_1540,u_ddr_mc_phy_wrapper_n_1541,u_ddr_mc_phy_wrapper_n_1542,u_ddr_mc_phy_wrapper_n_1543,u_ddr_mc_phy_wrapper_n_1544,u_ddr_mc_phy_wrapper_n_1545,u_ddr_mc_phy_wrapper_n_1546,u_ddr_mc_phy_wrapper_n_1547,u_ddr_mc_phy_wrapper_n_1548,u_ddr_mc_phy_wrapper_n_1549,u_ddr_mc_phy_wrapper_n_1550,u_ddr_mc_phy_wrapper_n_1551,u_ddr_mc_phy_wrapper_n_1552,u_ddr_mc_phy_wrapper_n_1553,u_ddr_mc_phy_wrapper_n_1554,u_ddr_mc_phy_wrapper_n_1555,u_ddr_mc_phy_wrapper_n_1556,u_ddr_mc_phy_wrapper_n_1557,u_ddr_mc_phy_wrapper_n_1558,u_ddr_mc_phy_wrapper_n_1559,u_ddr_mc_phy_wrapper_n_1560,u_ddr_mc_phy_wrapper_n_1561,u_ddr_mc_phy_wrapper_n_1562,u_ddr_mc_phy_wrapper_n_1563,u_ddr_mc_phy_wrapper_n_1564,u_ddr_mc_phy_wrapper_n_1565,u_ddr_mc_phy_wrapper_n_1566,u_ddr_mc_phy_wrapper_n_1567,u_ddr_mc_phy_wrapper_n_1568}),
        .mux_reset_n(mux_reset_n),
        .mux_wrdata({mux_wrdata[479:448],mux_wrdata[415:384],mux_wrdata[350:348],mux_wrdata[346:344],mux_wrdata[342:340],mux_wrdata[338:336],mux_wrdata[334:332],mux_wrdata[330:328],mux_wrdata[326:324],mux_wrdata[322:320],mux_wrdata[287],mux_wrdata[285:283],mux_wrdata[281:279],mux_wrdata[277:275],mux_wrdata[273:271],mux_wrdata[269:267],mux_wrdata[265:263],mux_wrdata[261:259],mux_wrdata[257:256],mux_wrdata[223],mux_wrdata[221:219],mux_wrdata[217:215],mux_wrdata[213:211],mux_wrdata[209:207],mux_wrdata[205:203],mux_wrdata[201:199],mux_wrdata[197:195],mux_wrdata[193:192],mux_wrdata[159:158],mux_wrdata[156:154],mux_wrdata[152:150],mux_wrdata[148:146],mux_wrdata[144:142],mux_wrdata[140:138],mux_wrdata[136:134],mux_wrdata[132:130],mux_wrdata[128],mux_wrdata[95:64],mux_wrdata[30:29],mux_wrdata[26:25],mux_wrdata[22:21],mux_wrdata[18:17],mux_wrdata[14:13],mux_wrdata[10:9],mux_wrdata[6:5],mux_wrdata[2:1]}),
        .mux_wrdata_mask({mux_wrdata_mask[59:56],mux_wrdata_mask[51:48],mux_wrdata_mask[43:40],mux_wrdata_mask[35:32],mux_wrdata_mask[27:24],mux_wrdata_mask[19:16],mux_wrdata_mask[11:8],mux_wrdata_mask[3:0]}),
        .\my_empty_reg[1] (u_ddr_calib_top_n_13),
        .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_161),
        .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_163),
        .\my_empty_reg[1]_10 (u_ddr_mc_phy_wrapper_n_82),
        .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_164),
        .\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_173),
        .\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_182),
        .\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_191),
        .\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_200),
        .\my_empty_reg[1]_7 (u_ddr_mc_phy_wrapper_n_426),
        .\my_empty_reg[1]_8 (u_ddr_mc_phy_wrapper_n_427),
        .\my_empty_reg[1]_9 (u_ddr_mc_phy_wrapper_n_428),
        .\my_empty_reg[3] (u_ddr_mc_phy_wrapper_n_1736),
        .\my_empty_reg[3]_0 (u_ddr_mc_phy_wrapper_n_1734),
        .\my_empty_reg[3]_1 (u_ddr_mc_phy_wrapper_n_1732),
        .\my_empty_reg[5] (u_ddr_mc_phy_wrapper_n_1735),
        .\my_empty_reg[5]_0 (u_ddr_mc_phy_wrapper_n_1733),
        .\my_empty_reg[5]_1 (u_ddr_mc_phy_wrapper_n_1731),
        .\my_empty_reg[6] (u_ddr_calib_top_n_12),
        .\my_empty_reg[6]_0 (u_ddr_calib_top_n_14),
        .\my_empty_reg[6]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),
        .\my_empty_reg[6]_2 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .\my_empty_reg[6]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .\my_empty_reg[6]_4 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .\my_empty_reg[7] (u_ddr_calib_top_n_15),
        .\my_empty_reg[7]_0 (u_ddr_calib_top_n_16),
        .\my_empty_reg[7]_1 (u_ddr_calib_top_n_17),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_14 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_15 (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_16 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_17 (\my_empty_reg[7]_9 ),
        .\my_empty_reg[7]_18 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\my_empty_reg[7]_19 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 [1:0]}),
        .\my_empty_reg[7]_2 (u_ddr_calib_top_n_18),
        .\my_empty_reg[7]_20 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 [0]}),
        .\my_empty_reg[7]_21 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 [4:2]}),
        .\my_empty_reg[7]_22 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .\my_empty_reg[7]_23 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 [1:0]}),
        .\my_empty_reg[7]_24 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 [0]}),
        .\my_empty_reg[7]_25 ({u_ddr_calib_top_n_919,u_ddr_calib_top_n_920,u_ddr_calib_top_n_921,u_ddr_calib_top_n_922,u_ddr_calib_top_n_923}),
        .\my_empty_reg[7]_26 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\my_empty_reg[7]_27 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 [1:0]}),
        .\my_empty_reg[7]_28 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 [0]}),
        .\my_empty_reg[7]_29 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [4:2]}),
        .\my_empty_reg[7]_3 (u_ddr_calib_top_n_19),
        .\my_empty_reg[7]_30 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\my_empty_reg[7]_31 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 [1:0]}),
        .\my_empty_reg[7]_32 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 [0]}),
        .\my_empty_reg[7]_33 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 [4:2]}),
        .\my_empty_reg[7]_34 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\my_empty_reg[7]_35 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 [1:0]}),
        .\my_empty_reg[7]_36 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 [0]}),
        .\my_empty_reg[7]_37 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 [4:2]}),
        .\my_empty_reg[7]_38 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\my_empty_reg[7]_39 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 [1:0]}),
        .\my_empty_reg[7]_4 (u_ddr_calib_top_n_21),
        .\my_empty_reg[7]_40 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 [0]}),
        .\my_empty_reg[7]_41 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 [4:2]}),
        .\my_empty_reg[7]_42 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .\my_empty_reg[7]_43 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 [1:0]}),
        .\my_empty_reg[7]_44 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 [0]}),
        .\my_empty_reg[7]_45 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 [4:2]}),
        .\my_empty_reg[7]_46 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\my_empty_reg[7]_47 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 [1:0]}),
        .\my_empty_reg[7]_48 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 [0]}),
        .\my_empty_reg[7]_49 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 [4:2]}),
        .\my_empty_reg[7]_5 (u_ddr_calib_top_n_22),
        .\my_empty_reg[7]_50 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .\my_empty_reg[7]_51 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\my_empty_reg[7]_52 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\my_empty_reg[7]_53 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\my_empty_reg[7]_54 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\my_empty_reg[7]_55 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .\my_empty_reg[7]_56 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .\my_empty_reg[7]_57 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .\my_empty_reg[7]_58 ({u_ddr_calib_top_n_1122,u_ddr_calib_top_n_1123,u_ddr_calib_top_n_1124,u_ddr_calib_top_n_1125,u_ddr_calib_top_n_1126,u_ddr_calib_top_n_1127,u_ddr_calib_top_n_1128,u_ddr_calib_top_n_1129}),
        .\my_empty_reg[7]_59 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\my_empty_reg[7]_6 (u_ddr_calib_top_n_23),
        .\my_empty_reg[7]_60 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\my_empty_reg[7]_61 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\my_empty_reg[7]_62 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\my_empty_reg[7]_63 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .\my_empty_reg[7]_64 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\my_empty_reg[7]_65 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\my_empty_reg[7]_66 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\my_empty_reg[7]_67 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),
        .\my_empty_reg[7]_68 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .\my_empty_reg[7]_69 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7] ),
        .\my_empty_reg[7]_70 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .\my_empty_reg[7]_71 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\my_empty_reg[7]_72 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\my_empty_reg[7]_73 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\my_empty_reg[7]_74 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .\my_empty_reg[7]_75 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .\my_empty_reg[7]_76 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_1 ),
        .\my_full_reg[4] (u_ddr_mc_phy_wrapper_n_42),
        .\my_full_reg[4]_0 (u_ddr_mc_phy_wrapper_n_44),
        .ofifo_rst0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst0 ),
        .p_0_out(\u_ddr_phy_wrcal/p_0_out ),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_ctl_ready(phy_ctl_ready),
        .\phy_ctl_wd_i1_reg[24] ({phy_ctl_wd[24:17],phy_ctl_wd[2:0]}),
        .phy_ctl_wr_i1_reg(u_ddr_calib_top_n_72),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_address[41],mux_address[13],mux_address[54],mux_address[40],mux_address[26],mux_address[12],u_ddr_calib_top_n_41,mux_address[39],mux_address[27],mux_address[11],mux_address[52],mux_address[38],mux_address[24],mux_address[10],mux_address[51],mux_address[37],mux_address[23],mux_address[9],mux_address[50],mux_address[36],mux_address[22],mux_address[8]}),
        .phy_if_reset(phy_if_reset),
        .phy_if_reset0(phy_if_reset0),
        .phy_if_reset_w(phy_if_reset_w),
        .phy_rddata_en(phy_rddata_en),
        .\pi_counter_read_val_reg[0] (u_ddr_mc_phy_wrapper_n_973),
        .\pi_counter_read_val_reg[0]_0 (u_ddr_mc_phy_wrapper_n_975),
        .\pi_counter_read_val_reg[1] (u_ddr_mc_phy_wrapper_n_976),
        .\pi_counter_read_val_reg[1]_0 (u_ddr_mc_phy_wrapper_n_970),
        .\pi_counter_read_val_reg[2] (u_ddr_mc_phy_wrapper_n_977),
        .\pi_counter_read_val_reg[2]_0 (u_ddr_mc_phy_wrapper_n_971),
        .\pi_counter_read_val_reg[3] (u_ddr_mc_phy_wrapper_n_972),
        .\pi_counter_read_val_reg[4] (u_ddr_mc_phy_wrapper_n_969),
        .\pi_counter_read_val_reg[4]_0 (u_ddr_mc_phy_wrapper_n_968),
        .\pi_counter_read_val_reg[5] (u_ddr_mc_phy_wrapper_n_974),
        .pi_dqs_found_lanes({u_ddr_mc_phy_wrapper_n_6,u_ddr_mc_phy_wrapper_n_7,u_ddr_mc_phy_wrapper_n_8,u_ddr_mc_phy_wrapper_n_9,u_ddr_mc_phy_wrapper_n_10,u_ddr_mc_phy_wrapper_n_11,u_ddr_mc_phy_wrapper_n_12,u_ddr_mc_phy_wrapper_n_13}),
        .\pi_dqs_found_lanes_r1_reg[0] (u_ddr_calib_top_n_93),
        .\pi_dqs_found_lanes_r1_reg[10] (u_ddr_calib_top_n_99),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[1] (u_ddr_calib_top_n_96),
        .\pi_dqs_found_lanes_r1_reg[1]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[2] (u_ddr_calib_top_n_98),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[3] (u_ddr_calib_top_n_79),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[4] (u_ddr_calib_top_n_94),
        .\pi_dqs_found_lanes_r1_reg[4]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[8] ({u_ddr_calib_top_n_87,u_ddr_calib_top_n_88,u_ddr_calib_top_n_89,u_ddr_calib_top_n_90,u_ddr_calib_top_n_91,u_ddr_calib_top_n_92}),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (u_ddr_calib_top_n_95),
        .\pi_dqs_found_lanes_r1_reg[9] (u_ddr_calib_top_n_97),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .\po_counter_read_val_reg[0] (u_ddr_mc_phy_wrapper_n_1741),
        .\po_counter_read_val_reg[1] (u_ddr_mc_phy_wrapper_n_1742),
        .\po_counter_read_val_reg[2] (u_ddr_mc_phy_wrapper_n_1743),
        .\po_counter_read_val_reg[3] (u_ddr_mc_phy_wrapper_n_1744),
        .\po_counter_read_val_reg[4] (u_ddr_mc_phy_wrapper_n_1745),
        .\po_counter_read_val_reg[5] (u_ddr_mc_phy_wrapper_n_1746),
        .\po_counter_read_val_reg[6] (u_ddr_mc_phy_wrapper_n_1747),
        .\po_counter_read_val_reg[7] (u_ddr_mc_phy_wrapper_n_1748),
        .\po_counter_read_val_reg[8] (u_ddr_calib_top_n_80),
        .\po_counter_read_val_reg[8]_0 (u_ddr_calib_top_n_117),
        .\po_counter_read_val_reg[8]_1 (u_ddr_calib_top_n_118),
        .\po_counter_read_val_reg[8]_2 (u_ddr_mc_phy_wrapper_n_1749),
        .\po_stg2_wrcal_cnt_reg[0] (u_ddr_mc_phy_wrapper_n_1763),
        .\po_stg2_wrcal_cnt_reg[0]_0 (u_ddr_mc_phy_wrapper_n_1771),
        .\po_stg2_wrcal_cnt_reg[0]_1 (u_ddr_mc_phy_wrapper_n_1779),
        .\po_stg2_wrcal_cnt_reg[0]_10 (u_ddr_mc_phy_wrapper_n_1782),
        .\po_stg2_wrcal_cnt_reg[0]_11 (u_ddr_mc_phy_wrapper_n_1790),
        .\po_stg2_wrcal_cnt_reg[0]_12 (u_ddr_mc_phy_wrapper_n_1798),
        .\po_stg2_wrcal_cnt_reg[0]_13 (u_ddr_mc_phy_wrapper_n_1806),
        .\po_stg2_wrcal_cnt_reg[0]_14 (u_ddr_mc_phy_wrapper_n_1756),
        .\po_stg2_wrcal_cnt_reg[0]_15 (u_ddr_mc_phy_wrapper_n_1764),
        .\po_stg2_wrcal_cnt_reg[0]_16 (u_ddr_mc_phy_wrapper_n_1772),
        .\po_stg2_wrcal_cnt_reg[0]_17 (u_ddr_mc_phy_wrapper_n_1780),
        .\po_stg2_wrcal_cnt_reg[0]_18 (u_ddr_mc_phy_wrapper_n_1788),
        .\po_stg2_wrcal_cnt_reg[0]_19 (u_ddr_mc_phy_wrapper_n_1796),
        .\po_stg2_wrcal_cnt_reg[0]_2 (u_ddr_mc_phy_wrapper_n_1787),
        .\po_stg2_wrcal_cnt_reg[0]_20 (u_ddr_mc_phy_wrapper_n_1804),
        .\po_stg2_wrcal_cnt_reg[0]_21 (u_ddr_mc_phy_wrapper_n_1812),
        .\po_stg2_wrcal_cnt_reg[0]_22 (u_ddr_mc_phy_wrapper_n_1753),
        .\po_stg2_wrcal_cnt_reg[0]_23 (u_ddr_mc_phy_wrapper_n_1761),
        .\po_stg2_wrcal_cnt_reg[0]_24 (u_ddr_mc_phy_wrapper_n_1769),
        .\po_stg2_wrcal_cnt_reg[0]_25 (u_ddr_mc_phy_wrapper_n_1777),
        .\po_stg2_wrcal_cnt_reg[0]_26 (u_ddr_mc_phy_wrapper_n_1785),
        .\po_stg2_wrcal_cnt_reg[0]_27 (u_ddr_mc_phy_wrapper_n_1793),
        .\po_stg2_wrcal_cnt_reg[0]_28 (u_ddr_mc_phy_wrapper_n_1801),
        .\po_stg2_wrcal_cnt_reg[0]_29 (u_ddr_mc_phy_wrapper_n_1809),
        .\po_stg2_wrcal_cnt_reg[0]_3 (u_ddr_mc_phy_wrapper_n_1795),
        .\po_stg2_wrcal_cnt_reg[0]_30 (u_ddr_mc_phy_wrapper_n_1752),
        .\po_stg2_wrcal_cnt_reg[0]_31 (u_ddr_mc_phy_wrapper_n_1760),
        .\po_stg2_wrcal_cnt_reg[0]_32 (u_ddr_mc_phy_wrapper_n_1768),
        .\po_stg2_wrcal_cnt_reg[0]_33 (u_ddr_mc_phy_wrapper_n_1776),
        .\po_stg2_wrcal_cnt_reg[0]_34 (u_ddr_mc_phy_wrapper_n_1784),
        .\po_stg2_wrcal_cnt_reg[0]_35 (u_ddr_mc_phy_wrapper_n_1792),
        .\po_stg2_wrcal_cnt_reg[0]_36 (u_ddr_mc_phy_wrapper_n_1800),
        .\po_stg2_wrcal_cnt_reg[0]_37 (u_ddr_mc_phy_wrapper_n_1808),
        .\po_stg2_wrcal_cnt_reg[0]_38 (u_ddr_mc_phy_wrapper_n_1751),
        .\po_stg2_wrcal_cnt_reg[0]_39 (u_ddr_mc_phy_wrapper_n_1759),
        .\po_stg2_wrcal_cnt_reg[0]_4 (u_ddr_mc_phy_wrapper_n_1803),
        .\po_stg2_wrcal_cnt_reg[0]_40 (u_ddr_mc_phy_wrapper_n_1767),
        .\po_stg2_wrcal_cnt_reg[0]_41 (u_ddr_mc_phy_wrapper_n_1775),
        .\po_stg2_wrcal_cnt_reg[0]_42 (u_ddr_mc_phy_wrapper_n_1783),
        .\po_stg2_wrcal_cnt_reg[0]_43 (u_ddr_mc_phy_wrapper_n_1791),
        .\po_stg2_wrcal_cnt_reg[0]_44 (u_ddr_mc_phy_wrapper_n_1799),
        .\po_stg2_wrcal_cnt_reg[0]_45 (u_ddr_mc_phy_wrapper_n_1807),
        .\po_stg2_wrcal_cnt_reg[0]_46 (u_ddr_mc_phy_wrapper_n_1757),
        .\po_stg2_wrcal_cnt_reg[0]_47 (u_ddr_mc_phy_wrapper_n_1765),
        .\po_stg2_wrcal_cnt_reg[0]_48 (u_ddr_mc_phy_wrapper_n_1773),
        .\po_stg2_wrcal_cnt_reg[0]_49 (u_ddr_mc_phy_wrapper_n_1781),
        .\po_stg2_wrcal_cnt_reg[0]_5 (u_ddr_mc_phy_wrapper_n_1811),
        .\po_stg2_wrcal_cnt_reg[0]_50 (u_ddr_mc_phy_wrapper_n_1789),
        .\po_stg2_wrcal_cnt_reg[0]_51 (u_ddr_mc_phy_wrapper_n_1797),
        .\po_stg2_wrcal_cnt_reg[0]_52 (u_ddr_mc_phy_wrapper_n_1805),
        .\po_stg2_wrcal_cnt_reg[0]_53 (u_ddr_mc_phy_wrapper_n_1813),
        .\po_stg2_wrcal_cnt_reg[0]_54 (u_ddr_mc_phy_wrapper_n_1754),
        .\po_stg2_wrcal_cnt_reg[0]_55 (u_ddr_mc_phy_wrapper_n_1762),
        .\po_stg2_wrcal_cnt_reg[0]_56 (u_ddr_mc_phy_wrapper_n_1770),
        .\po_stg2_wrcal_cnt_reg[0]_57 (u_ddr_mc_phy_wrapper_n_1778),
        .\po_stg2_wrcal_cnt_reg[0]_58 (u_ddr_mc_phy_wrapper_n_1786),
        .\po_stg2_wrcal_cnt_reg[0]_59 (u_ddr_mc_phy_wrapper_n_1794),
        .\po_stg2_wrcal_cnt_reg[0]_6 (u_ddr_mc_phy_wrapper_n_1750),
        .\po_stg2_wrcal_cnt_reg[0]_60 (u_ddr_mc_phy_wrapper_n_1802),
        .\po_stg2_wrcal_cnt_reg[0]_61 (u_ddr_mc_phy_wrapper_n_1810),
        .\po_stg2_wrcal_cnt_reg[0]_7 (u_ddr_mc_phy_wrapper_n_1758),
        .\po_stg2_wrcal_cnt_reg[0]_8 (u_ddr_mc_phy_wrapper_n_1766),
        .\po_stg2_wrcal_cnt_reg[0]_9 (u_ddr_mc_phy_wrapper_n_1774),
        .\rd_mux_sel_r_reg[0] (u_ddr_mc_phy_wrapper_n_511),
        .\rd_mux_sel_r_reg[0]_0 (u_ddr_mc_phy_wrapper_n_519),
        .\rd_mux_sel_r_reg[0]_1 (u_ddr_mc_phy_wrapper_n_583),
        .\rd_mux_sel_r_reg[0]_10 (u_ddr_mc_phy_wrapper_n_590),
        .\rd_mux_sel_r_reg[0]_11 (u_ddr_mc_phy_wrapper_n_650),
        .\rd_mux_sel_r_reg[0]_12 (u_ddr_mc_phy_wrapper_n_666),
        .\rd_mux_sel_r_reg[0]_13 (u_ddr_mc_phy_wrapper_n_722),
        .\rd_mux_sel_r_reg[0]_14 (u_ddr_mc_phy_wrapper_n_738),
        .\rd_mux_sel_r_reg[0]_15 (u_ddr_mc_phy_wrapper_n_493),
        .\rd_mux_sel_r_reg[0]_16 (u_ddr_mc_phy_wrapper_n_517),
        .\rd_mux_sel_r_reg[0]_17 (u_ddr_mc_phy_wrapper_n_565),
        .\rd_mux_sel_r_reg[0]_18 (u_ddr_mc_phy_wrapper_n_589),
        .\rd_mux_sel_r_reg[0]_19 (u_ddr_mc_phy_wrapper_n_641),
        .\rd_mux_sel_r_reg[0]_2 (u_ddr_mc_phy_wrapper_n_591),
        .\rd_mux_sel_r_reg[0]_20 (u_ddr_mc_phy_wrapper_n_665),
        .\rd_mux_sel_r_reg[0]_21 (u_ddr_mc_phy_wrapper_n_713),
        .\rd_mux_sel_r_reg[0]_22 (u_ddr_mc_phy_wrapper_n_737),
        .\rd_mux_sel_r_reg[0]_23 (u_ddr_mc_phy_wrapper_n_484),
        .\rd_mux_sel_r_reg[0]_24 (u_ddr_mc_phy_wrapper_n_516),
        .\rd_mux_sel_r_reg[0]_25 (u_ddr_mc_phy_wrapper_n_556),
        .\rd_mux_sel_r_reg[0]_26 (u_ddr_mc_phy_wrapper_n_588),
        .\rd_mux_sel_r_reg[0]_27 (u_ddr_mc_phy_wrapper_n_632),
        .\rd_mux_sel_r_reg[0]_28 (u_ddr_mc_phy_wrapper_n_664),
        .\rd_mux_sel_r_reg[0]_29 (u_ddr_mc_phy_wrapper_n_704),
        .\rd_mux_sel_r_reg[0]_3 (u_ddr_mc_phy_wrapper_n_659),
        .\rd_mux_sel_r_reg[0]_30 (u_ddr_mc_phy_wrapper_n_736),
        .\rd_mux_sel_r_reg[0]_31 (u_ddr_mc_phy_wrapper_n_475),
        .\rd_mux_sel_r_reg[0]_32 (u_ddr_mc_phy_wrapper_n_515),
        .\rd_mux_sel_r_reg[0]_33 (u_ddr_mc_phy_wrapper_n_547),
        .\rd_mux_sel_r_reg[0]_34 (u_ddr_mc_phy_wrapper_n_587),
        .\rd_mux_sel_r_reg[0]_35 (u_ddr_mc_phy_wrapper_n_623),
        .\rd_mux_sel_r_reg[0]_36 (u_ddr_mc_phy_wrapper_n_663),
        .\rd_mux_sel_r_reg[0]_37 (u_ddr_mc_phy_wrapper_n_695),
        .\rd_mux_sel_r_reg[0]_38 (u_ddr_mc_phy_wrapper_n_735),
        .\rd_mux_sel_r_reg[0]_39 (u_ddr_mc_phy_wrapper_n_466),
        .\rd_mux_sel_r_reg[0]_4 (u_ddr_mc_phy_wrapper_n_667),
        .\rd_mux_sel_r_reg[0]_40 (u_ddr_mc_phy_wrapper_n_514),
        .\rd_mux_sel_r_reg[0]_41 (u_ddr_mc_phy_wrapper_n_538),
        .\rd_mux_sel_r_reg[0]_42 (u_ddr_mc_phy_wrapper_n_586),
        .\rd_mux_sel_r_reg[0]_43 (u_ddr_mc_phy_wrapper_n_614),
        .\rd_mux_sel_r_reg[0]_44 (u_ddr_mc_phy_wrapper_n_662),
        .\rd_mux_sel_r_reg[0]_45 (u_ddr_mc_phy_wrapper_n_686),
        .\rd_mux_sel_r_reg[0]_46 (u_ddr_mc_phy_wrapper_n_734),
        .\rd_mux_sel_r_reg[0]_47 (u_ddr_mc_phy_wrapper_n_457),
        .\rd_mux_sel_r_reg[0]_48 (u_ddr_mc_phy_wrapper_n_513),
        .\rd_mux_sel_r_reg[0]_49 (u_ddr_mc_phy_wrapper_n_529),
        .\rd_mux_sel_r_reg[0]_5 (u_ddr_mc_phy_wrapper_n_731),
        .\rd_mux_sel_r_reg[0]_50 (u_ddr_mc_phy_wrapper_n_585),
        .\rd_mux_sel_r_reg[0]_51 (u_ddr_mc_phy_wrapper_n_605),
        .\rd_mux_sel_r_reg[0]_52 (u_ddr_mc_phy_wrapper_n_661),
        .\rd_mux_sel_r_reg[0]_53 (u_ddr_mc_phy_wrapper_n_677),
        .\rd_mux_sel_r_reg[0]_54 (u_ddr_mc_phy_wrapper_n_733),
        .\rd_mux_sel_r_reg[0]_55 (u_ddr_mc_phy_wrapper_n_448),
        .\rd_mux_sel_r_reg[0]_56 (u_ddr_mc_phy_wrapper_n_512),
        .\rd_mux_sel_r_reg[0]_57 (u_ddr_mc_phy_wrapper_n_520),
        .\rd_mux_sel_r_reg[0]_58 (u_ddr_mc_phy_wrapper_n_584),
        .\rd_mux_sel_r_reg[0]_59 (u_ddr_mc_phy_wrapper_n_596),
        .\rd_mux_sel_r_reg[0]_6 (u_ddr_mc_phy_wrapper_n_739),
        .\rd_mux_sel_r_reg[0]_60 (u_ddr_mc_phy_wrapper_n_660),
        .\rd_mux_sel_r_reg[0]_61 (u_ddr_mc_phy_wrapper_n_668),
        .\rd_mux_sel_r_reg[0]_62 (u_ddr_mc_phy_wrapper_n_732),
        .\rd_mux_sel_r_reg[0]_7 (u_ddr_mc_phy_wrapper_n_502),
        .\rd_mux_sel_r_reg[0]_8 (u_ddr_mc_phy_wrapper_n_518),
        .\rd_mux_sel_r_reg[0]_9 (u_ddr_mc_phy_wrapper_n_574),
        .\rd_ptr_reg_rep[3] ({\rd_ptr_reg_rep[3] [79:72],\rd_ptr_reg_rep[3] [63:0]}),
        .\rd_ptr_reg_rep[3]_0 ({\rd_ptr_reg_rep[3]_0 [36:34],\rd_ptr_reg_rep[3]_0 [28:26],\rd_ptr_reg_rep[3]_0 [24:22],\rd_ptr_reg_rep[3]_0 [15:8]}),
        .\rd_ptr_reg_rep[3]_1 ({\rd_ptr_reg_rep[3]_1 [75:72],\rd_ptr_reg_rep[3]_1 [67:64],\rd_ptr_reg_rep[3]_1 [59:40],\rd_ptr_reg_rep[3]_1 [35:32],\rd_ptr_reg_rep[3]_1 [27:24],\rd_ptr_reg_rep[3]_1 [19:16],\rd_ptr_reg_rep[3]_1 [11:8],\rd_ptr_reg_rep[3]_1 [2:0]}),
        .\rd_ptr_reg_rep[3]_2 ({u_ddr_mc_phy_wrapper_n_1569,u_ddr_mc_phy_wrapper_n_1570,u_ddr_mc_phy_wrapper_n_1571,u_ddr_mc_phy_wrapper_n_1572,u_ddr_mc_phy_wrapper_n_1573,u_ddr_mc_phy_wrapper_n_1574,u_ddr_mc_phy_wrapper_n_1575,u_ddr_mc_phy_wrapper_n_1576,u_ddr_mc_phy_wrapper_n_1577,u_ddr_mc_phy_wrapper_n_1578,u_ddr_mc_phy_wrapper_n_1579,u_ddr_mc_phy_wrapper_n_1580,u_ddr_mc_phy_wrapper_n_1581,u_ddr_mc_phy_wrapper_n_1582,u_ddr_mc_phy_wrapper_n_1583,u_ddr_mc_phy_wrapper_n_1584,u_ddr_mc_phy_wrapper_n_1585,u_ddr_mc_phy_wrapper_n_1586,u_ddr_mc_phy_wrapper_n_1587,u_ddr_mc_phy_wrapper_n_1588,u_ddr_mc_phy_wrapper_n_1589,u_ddr_mc_phy_wrapper_n_1590,u_ddr_mc_phy_wrapper_n_1591,u_ddr_mc_phy_wrapper_n_1592,u_ddr_mc_phy_wrapper_n_1593,u_ddr_mc_phy_wrapper_n_1594,u_ddr_mc_phy_wrapper_n_1595,u_ddr_mc_phy_wrapper_n_1596,u_ddr_mc_phy_wrapper_n_1597,u_ddr_mc_phy_wrapper_n_1598,u_ddr_mc_phy_wrapper_n_1599,u_ddr_mc_phy_wrapper_n_1600,u_ddr_mc_phy_wrapper_n_1601,u_ddr_mc_phy_wrapper_n_1602,u_ddr_mc_phy_wrapper_n_1603,u_ddr_mc_phy_wrapper_n_1604,u_ddr_mc_phy_wrapper_n_1605,u_ddr_mc_phy_wrapper_n_1606,u_ddr_mc_phy_wrapper_n_1607,u_ddr_mc_phy_wrapper_n_1608,u_ddr_mc_phy_wrapper_n_1609,u_ddr_mc_phy_wrapper_n_1610,u_ddr_mc_phy_wrapper_n_1611,u_ddr_mc_phy_wrapper_n_1612}),
        .\rd_ptr_reg_rep[3]_3 ({u_ddr_mc_phy_wrapper_n_1613,u_ddr_mc_phy_wrapper_n_1614,u_ddr_mc_phy_wrapper_n_1615,u_ddr_mc_phy_wrapper_n_1616,u_ddr_mc_phy_wrapper_n_1617,u_ddr_mc_phy_wrapper_n_1618,u_ddr_mc_phy_wrapper_n_1619,u_ddr_mc_phy_wrapper_n_1620,u_ddr_mc_phy_wrapper_n_1621,u_ddr_mc_phy_wrapper_n_1622,u_ddr_mc_phy_wrapper_n_1623,u_ddr_mc_phy_wrapper_n_1624,u_ddr_mc_phy_wrapper_n_1625,u_ddr_mc_phy_wrapper_n_1626,u_ddr_mc_phy_wrapper_n_1627,u_ddr_mc_phy_wrapper_n_1628,u_ddr_mc_phy_wrapper_n_1629,u_ddr_mc_phy_wrapper_n_1630,u_ddr_mc_phy_wrapper_n_1631,u_ddr_mc_phy_wrapper_n_1632,u_ddr_mc_phy_wrapper_n_1633,u_ddr_mc_phy_wrapper_n_1634,u_ddr_mc_phy_wrapper_n_1635,u_ddr_mc_phy_wrapper_n_1636,u_ddr_mc_phy_wrapper_n_1637,u_ddr_mc_phy_wrapper_n_1638,u_ddr_mc_phy_wrapper_n_1639,u_ddr_mc_phy_wrapper_n_1640,u_ddr_mc_phy_wrapper_n_1641,u_ddr_mc_phy_wrapper_n_1642,u_ddr_mc_phy_wrapper_n_1643,u_ddr_mc_phy_wrapper_n_1644,u_ddr_mc_phy_wrapper_n_1645,u_ddr_mc_phy_wrapper_n_1646,u_ddr_mc_phy_wrapper_n_1647,u_ddr_mc_phy_wrapper_n_1648,u_ddr_mc_phy_wrapper_n_1649,u_ddr_mc_phy_wrapper_n_1650,u_ddr_mc_phy_wrapper_n_1651,u_ddr_mc_phy_wrapper_n_1652,u_ddr_mc_phy_wrapper_n_1653,u_ddr_mc_phy_wrapper_n_1654,u_ddr_mc_phy_wrapper_n_1655,u_ddr_mc_phy_wrapper_n_1656}),
        .\rd_ptr_reg_rep[3]_4 ({u_ddr_mc_phy_wrapper_n_1657,u_ddr_mc_phy_wrapper_n_1658,u_ddr_mc_phy_wrapper_n_1659,u_ddr_mc_phy_wrapper_n_1660,u_ddr_mc_phy_wrapper_n_1661,u_ddr_mc_phy_wrapper_n_1662,u_ddr_mc_phy_wrapper_n_1663,u_ddr_mc_phy_wrapper_n_1664,u_ddr_mc_phy_wrapper_n_1665,u_ddr_mc_phy_wrapper_n_1666,u_ddr_mc_phy_wrapper_n_1667,u_ddr_mc_phy_wrapper_n_1668,u_ddr_mc_phy_wrapper_n_1669,u_ddr_mc_phy_wrapper_n_1670,u_ddr_mc_phy_wrapper_n_1671,u_ddr_mc_phy_wrapper_n_1672,u_ddr_mc_phy_wrapper_n_1673,u_ddr_mc_phy_wrapper_n_1674,u_ddr_mc_phy_wrapper_n_1675,u_ddr_mc_phy_wrapper_n_1676,u_ddr_mc_phy_wrapper_n_1677,u_ddr_mc_phy_wrapper_n_1678,u_ddr_mc_phy_wrapper_n_1679,u_ddr_mc_phy_wrapper_n_1680,u_ddr_mc_phy_wrapper_n_1681,u_ddr_mc_phy_wrapper_n_1682,u_ddr_mc_phy_wrapper_n_1683,u_ddr_mc_phy_wrapper_n_1684,u_ddr_mc_phy_wrapper_n_1685,u_ddr_mc_phy_wrapper_n_1686,u_ddr_mc_phy_wrapper_n_1687,u_ddr_mc_phy_wrapper_n_1688,u_ddr_mc_phy_wrapper_n_1689,u_ddr_mc_phy_wrapper_n_1690,u_ddr_mc_phy_wrapper_n_1691,u_ddr_mc_phy_wrapper_n_1692,u_ddr_mc_phy_wrapper_n_1693,u_ddr_mc_phy_wrapper_n_1694,u_ddr_mc_phy_wrapper_n_1695,u_ddr_mc_phy_wrapper_n_1696,u_ddr_mc_phy_wrapper_n_1697,u_ddr_mc_phy_wrapper_n_1698,u_ddr_mc_phy_wrapper_n_1699,u_ddr_mc_phy_wrapper_n_1700}),
        .\rd_ptr_reg_rep[3]_5 ({\rd_ptr_reg_rep[3]_2 [79:72],\rd_ptr_reg_rep[3]_2 [63:0]}),
        .\rd_ptr_reg_rep[3]_6 (\rd_ptr_reg_rep[3]_3 [79:8]),
        .\rd_ptr_reg_rep[3]_7 (\rd_ptr_reg_rep[3]_4 [79:8]),
        .\rdlvl_dqs_tap_cnt_r_reg[0][4][0] ({u_ddr_calib_top_n_119,u_ddr_calib_top_n_120,u_ddr_calib_top_n_121}),
        .rdlvl_stg1_start_r_reg(rdlvl_stg1_start_r_reg),
        .read_calib(read_calib),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .refresh_bank_r(refresh_bank_r),
        .reset_if(reset_if),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),
        .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),
        .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),
        .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),
        .rstdiv0_sync_r1_reg_rep__15(rstdiv0_sync_r1_reg_rep__15),
        .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),
        .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__24(\gen_byte_sel_div2.calib_in_common_i_1_n_0 ),
        .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0),
        .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24),
        .rstdiv0_sync_r1_reg_rep__24_2(rstdiv0_sync_r1_reg_rep__24_1),
        .rstdiv0_sync_r1_reg_rep__24_3(rstdiv0_sync_r1_reg_rep__24_2),
        .rstdiv0_sync_r1_reg_rep__24_4(rstdiv0_sync_r1_reg_rep__24_3),
        .rstdiv0_sync_r1_reg_rep__24_5(rstdiv0_sync_r1_reg_rep__24_4),
        .rstdiv0_sync_r1_reg_rep__3(rstdiv0_sync_r1_reg_rep__3),
        .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),
        .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),
        .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),
        .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .sent_col(sent_col),
        .tempmon_pi_f_dec(tempmon_pi_f_dec),
        .tempmon_pi_f_inc(tempmon_pi_f_inc),
        .tempmon_sample_en(tempmon_sample_en),
        .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec),
        .wr_en(\genblk24.phy_ctl_pre_fifo_0/wr_en ),
        .wr_en_0(\genblk24.phy_ctl_pre_fifo_1/wr_en ),
        .wr_en_1(\genblk24.phy_ctl_pre_fifo_2/wr_en ),
        .\wr_ptr_reg[2] (u_ddr_calib_top_n_108),
        .\wr_ptr_reg[2]_0 (u_ddr_calib_top_n_110),
        .\wr_ptr_timing_reg[0] (u_ddr_calib_top_n_20),
        .\wr_ptr_timing_reg[0]_0 (phy_dout),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_10 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\wr_ptr_timing_reg[0]_11 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .\wr_ptr_timing_reg[0]_12 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .\wr_ptr_timing_reg[0]_13 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),
        .\wr_ptr_timing_reg[0]_14 ({u_ddr_calib_top_n_877,u_ddr_calib_top_n_878,u_ddr_calib_top_n_879}),
        .\wr_ptr_timing_reg[0]_2 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\wr_ptr_timing_reg[0]_3 ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [6:4],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [2:0]}),
        .\wr_ptr_timing_reg[0]_4 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\wr_ptr_timing_reg[0]_5 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),
        .\wr_ptr_timing_reg[0]_6 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .\wr_ptr_timing_reg[0]_7 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .\wr_ptr_timing_reg[0]_8 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\wr_ptr_timing_reg[0]_9 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[575] ({\write_buffer.wr_buf_out_data_reg[575] [575:352],\write_buffer.wr_buf_out_data_reg[575] [350:348],\write_buffer.wr_buf_out_data_reg[575] [346:344],\write_buffer.wr_buf_out_data_reg[575] [342:340],\write_buffer.wr_buf_out_data_reg[575] [338:336],\write_buffer.wr_buf_out_data_reg[575] [334:332],\write_buffer.wr_buf_out_data_reg[575] [330:328],\write_buffer.wr_buf_out_data_reg[575] [326:324],\write_buffer.wr_buf_out_data_reg[575] [322:287],\write_buffer.wr_buf_out_data_reg[575] [285:283],\write_buffer.wr_buf_out_data_reg[575] [281:279],\write_buffer.wr_buf_out_data_reg[575] [277:275],\write_buffer.wr_buf_out_data_reg[575] [273:271],\write_buffer.wr_buf_out_data_reg[575] [269:267],\write_buffer.wr_buf_out_data_reg[575] [265:263],\write_buffer.wr_buf_out_data_reg[575] [261:259],\write_buffer.wr_buf_out_data_reg[575] [257:223],\write_buffer.wr_buf_out_data_reg[575] [221:219],\write_buffer.wr_buf_out_data_reg[575] [217:215],\write_buffer.wr_buf_out_data_reg[575] [213:211],\write_buffer.wr_buf_out_data_reg[575] [209:207],\write_buffer.wr_buf_out_data_reg[575] [205:203],\write_buffer.wr_buf_out_data_reg[575] [201:199],\write_buffer.wr_buf_out_data_reg[575] [197:195],\write_buffer.wr_buf_out_data_reg[575] [193:158],\write_buffer.wr_buf_out_data_reg[575] [156:154],\write_buffer.wr_buf_out_data_reg[575] [152:150],\write_buffer.wr_buf_out_data_reg[575] [148:146],\write_buffer.wr_buf_out_data_reg[575] [144:142],\write_buffer.wr_buf_out_data_reg[575] [140:138],\write_buffer.wr_buf_out_data_reg[575] [136:134],\write_buffer.wr_buf_out_data_reg[575] [132:130],\write_buffer.wr_buf_out_data_reg[575] [128:32],\write_buffer.wr_buf_out_data_reg[575] [30:29],\write_buffer.wr_buf_out_data_reg[575] [26:25],\write_buffer.wr_buf_out_data_reg[575] [22:21],\write_buffer.wr_buf_out_data_reg[575] [18:17],\write_buffer.wr_buf_out_data_reg[575] [14:13],\write_buffer.wr_buf_out_data_reg[575] [10:9],\write_buffer.wr_buf_out_data_reg[575] [6:5],\write_buffer.wr_buf_out_data_reg[575] [2:1]}),
        .write_calib(write_calib),
        .wrlvl_final_if_rst(wrlvl_final_if_rst));
  mig_7series_0_mig_7series_v2_3_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapper
       (.ADDRA(ADDRA),
        .A_idelay_ce10_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_idelay_ce10_out ),
        .A_idelay_ce13_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_idelay_ce13_out ),
        .A_idelay_ce19_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_idelay_ce19_out ),
        .A_pi_counter_load_en116_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_en116_out ),
        .A_pi_counter_load_en161_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_load_en161_out ),
        .A_pi_counter_load_en87_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_en87_out ),
        .A_pi_fine_enable112_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_fine_enable112_out ),
        .A_pi_fine_enable157_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_fine_enable157_out ),
        .A_pi_fine_enable83_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_fine_enable83_out ),
        .A_pi_fine_inc114_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_fine_inc114_out ),
        .A_pi_fine_inc159_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_fine_inc159_out ),
        .A_pi_fine_inc85_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_fine_inc85_out ),
        .A_pi_rst_dqs_find110_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_rst_dqs_find110_out ),
        .A_pi_rst_dqs_find155_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_rst_dqs_find155_out ),
        .A_pi_rst_dqs_find81_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_rst_dqs_find81_out ),
        .A_po_coarse_enable143_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_coarse_enable143_out ),
        .A_po_coarse_enable69_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_coarse_enable69_out ),
        .A_po_coarse_enable98_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_coarse_enable98_out ),
        .A_po_fine_enable141_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_fine_enable141_out ),
        .A_po_fine_enable67_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_fine_enable67_out ),
        .A_po_fine_enable96_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_fine_enable96_out ),
        .A_po_fine_inc100_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_po_fine_inc100_out ),
        .A_po_fine_inc145_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_po_fine_inc145_out ),
        .A_po_fine_inc71_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_po_fine_inc71_out ),
        .A_rst_primitives(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_rst_primitives ),
        .A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .B_idelay_ce6_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_idelay_ce6_out ),
        .B_idelay_ce9_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_idelay_ce9_out ),
        .B_of_data_full(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_of_data_full ),
        .B_pi_counter_load_en35_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_en35_out ),
        .B_pi_counter_load_en38_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_en38_out ),
        .B_pi_fine_enable31_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_fine_enable31_out ),
        .B_pi_fine_enable34_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_fine_enable34_out ),
        .B_pi_fine_inc33_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_fine_inc33_out ),
        .B_pi_fine_inc36_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_fine_inc36_out ),
        .B_pi_rst_dqs_find29_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_rst_dqs_find29_out ),
        .B_pi_rst_dqs_find32_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_rst_dqs_find32_out ),
        .B_po_coarse_enable17_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_coarse_enable17_out ),
        .B_po_coarse_enable20_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_coarse_enable20_out ),
        .B_po_coarse_enable27_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_coarse_enable27_out ),
        .B_po_fine_enable15_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_fine_enable15_out ),
        .B_po_fine_enable18_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_fine_enable18_out ),
        .B_po_fine_enable24_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_fine_enable24_out ),
        .B_po_fine_inc19_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_po_fine_inc19_out ),
        .B_po_fine_inc22_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_po_fine_inc22_out ),
        .B_po_fine_inc30_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/B_po_fine_inc30_out ),
        .CLK(CLK),
        .COUNTERLOADVAL({u_ddr_calib_top_n_81,u_ddr_calib_top_n_82,u_ddr_calib_top_n_83,u_ddr_calib_top_n_84,u_ddr_calib_top_n_85,u_ddr_calib_top_n_86}),
        .COUNTERREADVAL(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_read_val ),
        .C_idelay_ce2_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_idelay_ce2_out ),
        .C_idelay_ce5_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_idelay_ce5_out ),
        .C_of_data_full(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_of_data_full ),
        .C_pi_counter_load_en61_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_en61_out ),
        .C_pi_counter_load_en64_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_en64_out ),
        .C_pi_fine_enable57_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_fine_enable57_out ),
        .C_pi_fine_enable60_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_fine_enable60_out ),
        .C_pi_fine_inc59_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_fine_inc59_out ),
        .C_pi_fine_inc62_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_fine_inc62_out ),
        .C_pi_rst_dqs_find55_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_rst_dqs_find55_out ),
        .C_pi_rst_dqs_find58_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_rst_dqs_find58_out ),
        .C_po_coarse_enable43_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_coarse_enable43_out ),
        .C_po_coarse_enable46_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_coarse_enable46_out ),
        .C_po_coarse_enable66_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable66_out ),
        .C_po_fine_enable41_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_fine_enable41_out ),
        .C_po_fine_enable44_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_fine_enable44_out ),
        .C_po_fine_enable63_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable63_out ),
        .C_po_fine_inc45_out(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_po_fine_inc45_out ),
        .C_po_fine_inc48_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_po_fine_inc48_out ),
        .C_po_fine_inc69_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc69_out ),
        .D({u_ddr_calib_top_n_111,u_ddr_calib_top_n_112,u_ddr_calib_top_n_113,u_ddr_calib_top_n_114,u_ddr_calib_top_n_115,u_ddr_calib_top_n_116}),
        .D0({u_ddr_calib_top_n_808,u_ddr_calib_top_n_809,u_ddr_calib_top_n_810,u_ddr_calib_top_n_811,u_ddr_calib_top_n_812,u_ddr_calib_top_n_813,u_ddr_calib_top_n_814,u_ddr_calib_top_n_815}),
        .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .D2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .D_idelay_ce1_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_idelay_ce1_out ),
        .D_pi_counter_load_en90_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_en90_out ),
        .D_pi_fine_enable86_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_fine_enable86_out ),
        .D_pi_fine_inc88_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_fine_inc88_out ),
        .D_pi_rst_dqs_find84_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_rst_dqs_find84_out ),
        .D_po_coarse_enable105_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable105_out ),
        .D_po_coarse_enable72_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_coarse_enable72_out ),
        .D_po_fine_enable102_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable102_out ),
        .D_po_fine_enable70_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_fine_enable70_out ),
        .D_po_fine_inc108_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc108_out ),
        .D_po_fine_inc74_out(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_po_fine_inc74_out ),
        .E(u_ddr_calib_top_n_110),
        .\FSM_onehot_cal1_state_r_reg[0] (u_ddr_mc_phy_wrapper_n_975),
        .\FSM_onehot_cal1_state_r_reg[0]_0 (u_ddr_mc_phy_wrapper_n_976),
        .\FSM_onehot_cal1_state_r_reg[0]_1 (u_ddr_mc_phy_wrapper_n_977),
        .Q(Q),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_ctl_wren_reg(u_ddr_calib_top_n_72),
        .calib_ctl_wren_reg_0(u_ddr_calib_top_n_108),
        .calib_ctl_wren_reg_1(u_ddr_calib_top_n_106),
        .\calib_sel_reg[0] (u_ddr_calib_top_n_94),
        .\calib_sel_reg[0]_0 (u_ddr_calib_top_n_93),
        .\calib_sel_reg[0]_1 (u_ddr_calib_top_n_96),
        .\calib_sel_reg[0]_2 (u_ddr_calib_top_n_79),
        .\calib_sel_reg[0]_3 (u_ddr_calib_top_n_95),
        .\calib_sel_reg[0]_4 (u_ddr_calib_top_n_97),
        .\calib_sel_reg[1] (u_ddr_calib_top_n_98),
        .\calib_sel_reg[1]_0 (u_ddr_calib_top_n_99),
        .\calib_sel_reg[4] ({calib_sel[4:3],calib_sel[1:0]}),
        .\calib_seq_reg[1] ({phy_ctl_wd[24:17],phy_ctl_wd[2:0]}),
        .calib_wrdata_en(calib_wrdata_en),
        .\calib_zero_inputs_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .\calib_zero_inputs_reg[0]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\calib_zero_inputs_reg[0]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .\calib_zero_inputs_reg[2] ({u_ddr_calib_top_n_87,u_ddr_calib_top_n_88,u_ddr_calib_top_n_89,u_ddr_calib_top_n_90,u_ddr_calib_top_n_91,u_ddr_calib_top_n_92}),
        .\calib_zero_inputs_reg[2]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .\calib_zero_inputs_reg[2]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\cmd_pipe_plus.mc_address_reg[41] ({\cmd_pipe_plus.mc_address_reg[41] [38],\cmd_pipe_plus.mc_address_reg[41] [36],\cmd_pipe_plus.mc_address_reg[41] [13],\cmd_pipe_plus.mc_address_reg[41] [11]}),
        .\cmd_pipe_plus.mc_cas_n_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\cmd_pipe_plus.mc_cke_reg[3] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (data_offset_1),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (data_offset_2),
        .\cmd_pipe_plus.mc_odt_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),
        .\cmd_pipe_plus.mc_ras_n_reg[2] ({u_ddr_calib_top_n_877,u_ddr_calib_top_n_878,u_ddr_calib_top_n_879}),
        .\cmd_pipe_plus.mc_we_n_reg[2] ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [6:4],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [2:0]}),
        .\cmd_pipe_plus.mc_wrdata_en_reg (u_ddr_calib_top_n_1056),
        .\cmd_pipe_plus.mc_wrdata_en_reg_0 (u_ddr_calib_top_n_1057),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .freq_refclk(freq_refclk),
        .\gen_byte_sel_div2.calib_in_common_reg (u_ddr_calib_top_n_693),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (u_ddr_calib_top_n_117),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (u_ddr_calib_top_n_118),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (u_ddr_calib_top_n_64),
        .\gen_byte_sel_div2.calib_in_common_reg_3 (u_ddr_calib_top_n_69),
        .\gen_byte_sel_div2.calib_in_common_reg_4 (u_ddr_calib_top_n_70),
        .\gen_byte_sel_div2.calib_in_common_reg_5 (u_ddr_calib_top_n_71),
        .\gen_byte_sel_div2.calib_in_common_reg_6 (u_ddr_calib_top_n_1274),
        .\gen_byte_sel_div2.calib_in_common_reg_7 (u_ddr_calib_top_n_1275),
        .\gen_byte_sel_div2.calib_in_common_reg_8 (u_ddr_calib_top_n_1276),
        .\gen_byte_sel_div2.calib_in_common_reg_9 (u_ddr_calib_top_n_80),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_502),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_484),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_466),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_448),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (u_ddr_mc_phy_wrapper_n_511),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (u_ddr_mc_phy_wrapper_n_493),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_475),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_457),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_518),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_516),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_514),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (u_ddr_mc_phy_wrapper_n_512),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (u_ddr_mc_phy_wrapper_n_519),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_517),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_515),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_513),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_7 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_574),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_556),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_538),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_520),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (u_ddr_mc_phy_wrapper_n_583),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_565),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_547),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_529),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_590),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_588),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_586),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_584),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_591),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_589),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_587),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_585),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_7 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_650),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_632),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_614),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_596),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_659),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_641),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_623),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_605),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 (u_ddr_mc_phy_wrapper_n_666),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 (u_ddr_mc_phy_wrapper_n_664),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 (u_ddr_mc_phy_wrapper_n_662),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 (u_ddr_mc_phy_wrapper_n_660),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_667),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 (u_ddr_mc_phy_wrapper_n_665),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 (u_ddr_mc_phy_wrapper_n_663),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 (u_ddr_mc_phy_wrapper_n_661),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_7 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_722),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_704),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_686),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_668),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_731),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_713),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_695),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_677),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 (u_ddr_mc_phy_wrapper_n_738),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 (u_ddr_mc_phy_wrapper_n_736),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 (u_ddr_mc_phy_wrapper_n_734),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 (u_ddr_mc_phy_wrapper_n_732),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_739),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 (u_ddr_mc_phy_wrapper_n_737),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 (u_ddr_mc_phy_wrapper_n_735),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 (u_ddr_mc_phy_wrapper_n_733),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_7 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1756),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_1754),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1752),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1750),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1757),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1753),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1751),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1764),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1762),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1760),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1758),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1765),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1763),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1761),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1759),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1772),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1770),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1768),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1766),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1773),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1771),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1769),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1767),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1780),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1778),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1776),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1774),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1781),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1779),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1777),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1775),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1788),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1786),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1784),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1782),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1789),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1787),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1785),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1783),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1796),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1794),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1792),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1790),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1797),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1795),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1793),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1791),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1804),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1802),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1800),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1798),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1805),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1803),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1801),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1799),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1812),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1810),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1808),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1806),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1813),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1811),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1809),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1807),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (u_ddr_mc_phy_wrapper_n_192),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (u_ddr_mc_phy_wrapper_n_183),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (u_ddr_mc_phy_wrapper_n_174),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\gen_rd[2].rd_data_rise_wl_r_reg[2] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (u_ddr_mc_phy_wrapper_n_165),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\gen_rd[3].rd_data_rise_wl_r_reg[3] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (u_ddr_mc_phy_wrapper_n_87),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\gen_rd[4].rd_data_rise_wl_r_reg[4] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (u_ddr_mc_phy_wrapper_n_202),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (u_ddr_mc_phy_wrapper_n_276),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (u_ddr_mc_phy_wrapper_n_352),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\gen_rd[7].rd_data_rise_wl_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_3(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_4(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_5(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idle(idle),
        .init_calib_complete_reg_rep(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),
        .init_calib_complete_reg_rep_0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .init_calib_complete_reg_rep_1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .init_calib_complete_reg_rep_2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .init_calib_complete_reg_rep_3(app_zq_r_reg),
        .init_calib_complete_reg_rep__0(u_ddr_calib_top_n_12),
        .init_calib_complete_reg_rep__1(u_ddr_calib_top_n_13),
        .init_calib_complete_reg_rep__10(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .init_calib_complete_reg_rep__10_0(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .init_calib_complete_reg_rep__11(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .init_calib_complete_reg_rep__11_0(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .init_calib_complete_reg_rep__11_1(u_ddr_calib_top_n_22),
        .init_calib_complete_reg_rep__12(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .init_calib_complete_reg_rep__12_0(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .init_calib_complete_reg_rep__12_1(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .init_calib_complete_reg_rep__12_2(u_ddr_calib_top_n_23),
        .init_calib_complete_reg_rep__13(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .init_calib_complete_reg_rep__14(u_ddr_calib_top_n_24),
        .init_calib_complete_reg_rep__2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .init_calib_complete_reg_rep__2_0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .init_calib_complete_reg_rep__2_1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .init_calib_complete_reg_rep__2_2(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .init_calib_complete_reg_rep__2_3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .init_calib_complete_reg_rep__2_4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .init_calib_complete_reg_rep__2_5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .init_calib_complete_reg_rep__2_6(u_ddr_calib_top_n_14),
        .init_calib_complete_reg_rep__3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),
        .init_calib_complete_reg_rep__3_0(u_ddr_calib_top_n_15),
        .init_calib_complete_reg_rep__4(u_ddr_calib_top_n_16),
        .init_calib_complete_reg_rep__5(u_ddr_calib_top_n_17),
        .init_calib_complete_reg_rep__6(u_ddr_calib_top_n_18),
        .init_calib_complete_reg_rep__7(u_ddr_calib_top_n_19),
        .init_calib_complete_reg_rep__8(u_ddr_calib_top_n_20),
        .init_calib_complete_reg_rep__9(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .init_calib_complete_reg_rep__9_0(u_ddr_calib_top_n_21),
        .init_complete_r1_timing_reg(\read_fifo.tail_r_reg[1] ),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .mc_cas_n(mc_cas_n[1]),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .mux_reset_n(mux_reset_n),
        .mux_wrdata({mux_wrdata[479:448],mux_wrdata[415:384],mux_wrdata[350:348],mux_wrdata[346:344],mux_wrdata[342:340],mux_wrdata[338:336],mux_wrdata[334:332],mux_wrdata[330:328],mux_wrdata[326:324],mux_wrdata[322:320],mux_wrdata[287],mux_wrdata[285:283],mux_wrdata[281:279],mux_wrdata[277:275],mux_wrdata[273:271],mux_wrdata[269:267],mux_wrdata[265:263],mux_wrdata[261:259],mux_wrdata[257:256],mux_wrdata[223],mux_wrdata[221:219],mux_wrdata[217:215],mux_wrdata[213:211],mux_wrdata[209:207],mux_wrdata[205:203],mux_wrdata[201:199],mux_wrdata[197:195],mux_wrdata[193:192],mux_wrdata[159:158],mux_wrdata[156:154],mux_wrdata[152:150],mux_wrdata[148:146],mux_wrdata[144:142],mux_wrdata[140:138],mux_wrdata[136:134],mux_wrdata[132:130],mux_wrdata[128],mux_wrdata[95:64],mux_wrdata[30:29],mux_wrdata[26:25],mux_wrdata[22:21],mux_wrdata[18:17],mux_wrdata[14:13],mux_wrdata[10:9],mux_wrdata[6:5],mux_wrdata[2:1]}),
        .mux_wrdata_mask({mux_wrdata_mask[59:56],mux_wrdata_mask[51:48],mux_wrdata_mask[43:40],mux_wrdata_mask[35:32],mux_wrdata_mask[27:24],mux_wrdata_mask[19:16],mux_wrdata_mask[11:8],mux_wrdata_mask[3:0]}),
        .\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_82),
        .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_161),
        .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_163),
        .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_164),
        .\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_173),
        .\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_182),
        .\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_191),
        .\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_200),
        .\my_empty_reg[1]_7 (u_ddr_mc_phy_wrapper_n_426),
        .\my_empty_reg[1]_8 (u_ddr_mc_phy_wrapper_n_427),
        .\my_empty_reg[1]_9 (u_ddr_mc_phy_wrapper_n_428),
        .\my_empty_reg[3] (u_ddr_mc_phy_wrapper_n_1732),
        .\my_empty_reg[3]_0 (u_ddr_mc_phy_wrapper_n_1734),
        .\my_empty_reg[3]_1 (u_ddr_mc_phy_wrapper_n_1736),
        .\my_empty_reg[5] (u_ddr_mc_phy_wrapper_n_1731),
        .\my_empty_reg[5]_0 (u_ddr_mc_phy_wrapper_n_1733),
        .\my_empty_reg[5]_1 (u_ddr_mc_phy_wrapper_n_1735),
        .\my_empty_reg[6] ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}),
        .\my_empty_reg[7] (u_ddr_mc_phy_wrapper_n_42),
        .\my_empty_reg[7]_0 (u_ddr_mc_phy_wrapper_n_44),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_2 ({u_ddr_mc_phy_wrapper_n_1525,u_ddr_mc_phy_wrapper_n_1526,u_ddr_mc_phy_wrapper_n_1527,u_ddr_mc_phy_wrapper_n_1528,u_ddr_mc_phy_wrapper_n_1529,u_ddr_mc_phy_wrapper_n_1530,u_ddr_mc_phy_wrapper_n_1531,u_ddr_mc_phy_wrapper_n_1532,u_ddr_mc_phy_wrapper_n_1533,u_ddr_mc_phy_wrapper_n_1534,u_ddr_mc_phy_wrapper_n_1535,u_ddr_mc_phy_wrapper_n_1536,u_ddr_mc_phy_wrapper_n_1537,u_ddr_mc_phy_wrapper_n_1538,u_ddr_mc_phy_wrapper_n_1539,u_ddr_mc_phy_wrapper_n_1540,u_ddr_mc_phy_wrapper_n_1541,u_ddr_mc_phy_wrapper_n_1542,u_ddr_mc_phy_wrapper_n_1543,u_ddr_mc_phy_wrapper_n_1544,u_ddr_mc_phy_wrapper_n_1545,u_ddr_mc_phy_wrapper_n_1546,u_ddr_mc_phy_wrapper_n_1547,u_ddr_mc_phy_wrapper_n_1548,u_ddr_mc_phy_wrapper_n_1549,u_ddr_mc_phy_wrapper_n_1550,u_ddr_mc_phy_wrapper_n_1551,u_ddr_mc_phy_wrapper_n_1552,u_ddr_mc_phy_wrapper_n_1553,u_ddr_mc_phy_wrapper_n_1554,u_ddr_mc_phy_wrapper_n_1555,u_ddr_mc_phy_wrapper_n_1556,u_ddr_mc_phy_wrapper_n_1557,u_ddr_mc_phy_wrapper_n_1558,u_ddr_mc_phy_wrapper_n_1559,u_ddr_mc_phy_wrapper_n_1560,u_ddr_mc_phy_wrapper_n_1561,u_ddr_mc_phy_wrapper_n_1562,u_ddr_mc_phy_wrapper_n_1563,u_ddr_mc_phy_wrapper_n_1564,u_ddr_mc_phy_wrapper_n_1565,u_ddr_mc_phy_wrapper_n_1566,u_ddr_mc_phy_wrapper_n_1567,u_ddr_mc_phy_wrapper_n_1568}),
        .\my_empty_reg[7]_3 ({u_ddr_mc_phy_wrapper_n_1569,u_ddr_mc_phy_wrapper_n_1570,u_ddr_mc_phy_wrapper_n_1571,u_ddr_mc_phy_wrapper_n_1572,u_ddr_mc_phy_wrapper_n_1573,u_ddr_mc_phy_wrapper_n_1574,u_ddr_mc_phy_wrapper_n_1575,u_ddr_mc_phy_wrapper_n_1576,u_ddr_mc_phy_wrapper_n_1577,u_ddr_mc_phy_wrapper_n_1578,u_ddr_mc_phy_wrapper_n_1579,u_ddr_mc_phy_wrapper_n_1580,u_ddr_mc_phy_wrapper_n_1581,u_ddr_mc_phy_wrapper_n_1582,u_ddr_mc_phy_wrapper_n_1583,u_ddr_mc_phy_wrapper_n_1584,u_ddr_mc_phy_wrapper_n_1585,u_ddr_mc_phy_wrapper_n_1586,u_ddr_mc_phy_wrapper_n_1587,u_ddr_mc_phy_wrapper_n_1588,u_ddr_mc_phy_wrapper_n_1589,u_ddr_mc_phy_wrapper_n_1590,u_ddr_mc_phy_wrapper_n_1591,u_ddr_mc_phy_wrapper_n_1592,u_ddr_mc_phy_wrapper_n_1593,u_ddr_mc_phy_wrapper_n_1594,u_ddr_mc_phy_wrapper_n_1595,u_ddr_mc_phy_wrapper_n_1596,u_ddr_mc_phy_wrapper_n_1597,u_ddr_mc_phy_wrapper_n_1598,u_ddr_mc_phy_wrapper_n_1599,u_ddr_mc_phy_wrapper_n_1600,u_ddr_mc_phy_wrapper_n_1601,u_ddr_mc_phy_wrapper_n_1602,u_ddr_mc_phy_wrapper_n_1603,u_ddr_mc_phy_wrapper_n_1604,u_ddr_mc_phy_wrapper_n_1605,u_ddr_mc_phy_wrapper_n_1606,u_ddr_mc_phy_wrapper_n_1607,u_ddr_mc_phy_wrapper_n_1608,u_ddr_mc_phy_wrapper_n_1609,u_ddr_mc_phy_wrapper_n_1610,u_ddr_mc_phy_wrapper_n_1611,u_ddr_mc_phy_wrapper_n_1612}),
        .\my_empty_reg[7]_4 ({u_ddr_mc_phy_wrapper_n_1613,u_ddr_mc_phy_wrapper_n_1614,u_ddr_mc_phy_wrapper_n_1615,u_ddr_mc_phy_wrapper_n_1616,u_ddr_mc_phy_wrapper_n_1617,u_ddr_mc_phy_wrapper_n_1618,u_ddr_mc_phy_wrapper_n_1619,u_ddr_mc_phy_wrapper_n_1620,u_ddr_mc_phy_wrapper_n_1621,u_ddr_mc_phy_wrapper_n_1622,u_ddr_mc_phy_wrapper_n_1623,u_ddr_mc_phy_wrapper_n_1624,u_ddr_mc_phy_wrapper_n_1625,u_ddr_mc_phy_wrapper_n_1626,u_ddr_mc_phy_wrapper_n_1627,u_ddr_mc_phy_wrapper_n_1628,u_ddr_mc_phy_wrapper_n_1629,u_ddr_mc_phy_wrapper_n_1630,u_ddr_mc_phy_wrapper_n_1631,u_ddr_mc_phy_wrapper_n_1632,u_ddr_mc_phy_wrapper_n_1633,u_ddr_mc_phy_wrapper_n_1634,u_ddr_mc_phy_wrapper_n_1635,u_ddr_mc_phy_wrapper_n_1636,u_ddr_mc_phy_wrapper_n_1637,u_ddr_mc_phy_wrapper_n_1638,u_ddr_mc_phy_wrapper_n_1639,u_ddr_mc_phy_wrapper_n_1640,u_ddr_mc_phy_wrapper_n_1641,u_ddr_mc_phy_wrapper_n_1642,u_ddr_mc_phy_wrapper_n_1643,u_ddr_mc_phy_wrapper_n_1644,u_ddr_mc_phy_wrapper_n_1645,u_ddr_mc_phy_wrapper_n_1646,u_ddr_mc_phy_wrapper_n_1647,u_ddr_mc_phy_wrapper_n_1648,u_ddr_mc_phy_wrapper_n_1649,u_ddr_mc_phy_wrapper_n_1650,u_ddr_mc_phy_wrapper_n_1651,u_ddr_mc_phy_wrapper_n_1652,u_ddr_mc_phy_wrapper_n_1653,u_ddr_mc_phy_wrapper_n_1654,u_ddr_mc_phy_wrapper_n_1655,u_ddr_mc_phy_wrapper_n_1656}),
        .\my_empty_reg[7]_5 ({u_ddr_mc_phy_wrapper_n_1657,u_ddr_mc_phy_wrapper_n_1658,u_ddr_mc_phy_wrapper_n_1659,u_ddr_mc_phy_wrapper_n_1660,u_ddr_mc_phy_wrapper_n_1661,u_ddr_mc_phy_wrapper_n_1662,u_ddr_mc_phy_wrapper_n_1663,u_ddr_mc_phy_wrapper_n_1664,u_ddr_mc_phy_wrapper_n_1665,u_ddr_mc_phy_wrapper_n_1666,u_ddr_mc_phy_wrapper_n_1667,u_ddr_mc_phy_wrapper_n_1668,u_ddr_mc_phy_wrapper_n_1669,u_ddr_mc_phy_wrapper_n_1670,u_ddr_mc_phy_wrapper_n_1671,u_ddr_mc_phy_wrapper_n_1672,u_ddr_mc_phy_wrapper_n_1673,u_ddr_mc_phy_wrapper_n_1674,u_ddr_mc_phy_wrapper_n_1675,u_ddr_mc_phy_wrapper_n_1676,u_ddr_mc_phy_wrapper_n_1677,u_ddr_mc_phy_wrapper_n_1678,u_ddr_mc_phy_wrapper_n_1679,u_ddr_mc_phy_wrapper_n_1680,u_ddr_mc_phy_wrapper_n_1681,u_ddr_mc_phy_wrapper_n_1682,u_ddr_mc_phy_wrapper_n_1683,u_ddr_mc_phy_wrapper_n_1684,u_ddr_mc_phy_wrapper_n_1685,u_ddr_mc_phy_wrapper_n_1686,u_ddr_mc_phy_wrapper_n_1687,u_ddr_mc_phy_wrapper_n_1688,u_ddr_mc_phy_wrapper_n_1689,u_ddr_mc_phy_wrapper_n_1690,u_ddr_mc_phy_wrapper_n_1691,u_ddr_mc_phy_wrapper_n_1692,u_ddr_mc_phy_wrapper_n_1693,u_ddr_mc_phy_wrapper_n_1694,u_ddr_mc_phy_wrapper_n_1695,u_ddr_mc_phy_wrapper_n_1696,u_ddr_mc_phy_wrapper_n_1697,u_ddr_mc_phy_wrapper_n_1698,u_ddr_mc_phy_wrapper_n_1699,u_ddr_mc_phy_wrapper_n_1700}),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_13 ),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ),
        .\not_strict_mode.app_rd_data_reg[352] (\not_strict_mode.app_rd_data_reg[352] ),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376] ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[488] (\not_strict_mode.app_rd_data_reg[488] ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496] ),
        .\not_strict_mode.app_rd_data_reg[496]_0 (\not_strict_mode.app_rd_data_reg[496]_0 ),
        .\not_strict_mode.app_rd_data_reg[511] (\not_strict_mode.app_rd_data_reg[511] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ),
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        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),
        .of_ctl_full_v(of_ctl_full_v),
        .ofifo_rst0(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst0 ),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .p_0_out(\u_ddr_phy_wrcal/p_0_out ),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_ctl_ready(phy_ctl_ready),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_address[41],mux_address[13],mux_address[54],mux_address[40],mux_address[26],mux_address[12],u_ddr_calib_top_n_41,mux_address[39],mux_address[27],mux_address[11],mux_address[52],mux_address[38],mux_address[24],mux_address[10],mux_address[51],mux_address[37],mux_address[23],mux_address[9],mux_address[50],mux_address[36],mux_address[22],mux_address[8]}),
        .phy_if_reset(phy_if_reset),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .pi_dqs_found_lanes({u_ddr_mc_phy_wrapper_n_6,u_ddr_mc_phy_wrapper_n_7,u_ddr_mc_phy_wrapper_n_8,u_ddr_mc_phy_wrapper_n_9,u_ddr_mc_phy_wrapper_n_10,u_ddr_mc_phy_wrapper_n_11,u_ddr_mc_phy_wrapper_n_12,u_ddr_mc_phy_wrapper_n_13}),
        .pi_phase_locked_all_r1_reg(u_ddr_mc_phy_wrapper_n_445),
        .\pi_rdval_cnt_reg[0] (u_ddr_mc_phy_wrapper_n_973),
        .\pi_rdval_cnt_reg[1] (u_ddr_mc_phy_wrapper_n_970),
        .\pi_rdval_cnt_reg[2] (u_ddr_mc_phy_wrapper_n_971),
        .\pi_rdval_cnt_reg[3] (u_ddr_mc_phy_wrapper_n_972),
        .\pi_rdval_cnt_reg[4] (u_ddr_mc_phy_wrapper_n_969),
        .\pi_rdval_cnt_reg[5] (u_ddr_mc_phy_wrapper_n_974),
        .\pi_stg2_reg_l_reg[5] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_load_val ),
        .pll_lock(pll_lock),
        .\po_rdval_cnt_reg[0] (u_ddr_mc_phy_wrapper_n_1741),
        .\po_rdval_cnt_reg[1] (u_ddr_mc_phy_wrapper_n_1742),
        .\po_rdval_cnt_reg[2] (u_ddr_mc_phy_wrapper_n_1743),
        .\po_rdval_cnt_reg[3] (u_ddr_mc_phy_wrapper_n_1744),
        .\po_rdval_cnt_reg[4] (u_ddr_mc_phy_wrapper_n_1745),
        .\po_rdval_cnt_reg[5] (u_ddr_mc_phy_wrapper_n_1746),
        .\po_rdval_cnt_reg[6] (u_ddr_mc_phy_wrapper_n_1747),
        .\po_rdval_cnt_reg[7] (u_ddr_mc_phy_wrapper_n_1748),
        .\po_rdval_cnt_reg[8] (u_ddr_mc_phy_wrapper_n_1749),
        .\po_stg2_wrcal_cnt_reg[2] (po_stg2_wrcal_cnt),
        .ram_init_addr(ram_init_addr),
        .ram_init_done_r(ram_init_done_r),
        .rd_active_r_reg(rd_active_r_reg),
        .rd_buf_we(rd_buf_we),
        .\rd_mux_sel_r_reg[2] ({u_ddr_calib_top_n_119,u_ddr_calib_top_n_120,u_ddr_calib_top_n_121}),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] [71:64]),
        .\rd_ptr_reg_rep[3]_0 ({\rd_ptr_reg_rep[3]_0 [41:37],\rd_ptr_reg_rep[3]_0 [33:29],\rd_ptr_reg_rep[3]_0 [25],\rd_ptr_reg_rep[3]_0 [21:16],\rd_ptr_reg_rep[3]_0 [7:0]}),
        .\rd_ptr_reg_rep[3]_1 ({\rd_ptr_reg_rep[3]_1 [79:76],\rd_ptr_reg_rep[3]_1 [71:68],\rd_ptr_reg_rep[3]_1 [63:60],\rd_ptr_reg_rep[3]_1 [39:36],\rd_ptr_reg_rep[3]_1 [31:28],\rd_ptr_reg_rep[3]_1 [23:20],\rd_ptr_reg_rep[3]_1 [15:12],\rd_ptr_reg_rep[3]_1 [7:3]}),
        .\rd_ptr_reg_rep[3]_2 (\rd_ptr_reg_rep[3]_2 [71:64]),
        .\rd_ptr_reg_rep[3]_3 (\rd_ptr_reg_rep[3]_3 [7:0]),
        .\rd_ptr_reg_rep[3]_4 (\rd_ptr_reg_rep[3]_4 [7:0]),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1]_0 ),
        .\rd_ptr_timing_reg[1]_1 (\rd_ptr_timing_reg[1]_1 ),
        .read_calib(read_calib),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1]_0 ),
        .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1]_1 ),
        .\read_fifo.tail_r_reg[3] (\read_fifo.tail_r_reg[3] ),
        .rst_sync_r1_reg(rst_sync_r1_reg),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .store_sr_req_r_reg(u_ddr_mc_phy_wrapper_n_968),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst),
        .sys_rst_0(sys_rst_0),
        .sys_rst_1(sys_rst_1),
        .tail_r(tail_r),
        .wr_en(wr_en),
        .wr_en_10(wr_en_10),
        .wr_en_11(wr_en_11),
        .wr_en_12(wr_en_12),
        .wr_en_13(wr_en_13),
        .wr_en_14(wr_en_14),
        .wr_en_7(\genblk24.phy_ctl_pre_fifo_2/wr_en ),
        .wr_en_8(\genblk24.phy_ctl_pre_fifo_1/wr_en ),
        .wr_en_9(\genblk24.phy_ctl_pre_fifo_0/wr_en ),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[0]_1 (\wr_ptr_reg[0]_1 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_reg[1]_2 (\wr_ptr_reg[1]_2 ),
        .\wr_ptr_reg[1]_3 (\wr_ptr_reg[1]_3 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_1 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3]_0 ),
        .\wr_ptr_timing_reg[3]_1 (\wr_ptr_timing_reg[3]_1 ),
        .\wr_ptr_timing_reg[3]_2 (\wr_ptr_timing_reg[3]_2 ),
        .\wr_ptr_timing_reg[3]_3 (\wr_ptr_timing_reg[3]_3 ),
        .\wr_ptr_timing_reg[3]_4 (\wr_ptr_timing_reg[3]_4 ),
        .\write_buffer.wr_buf_out_data_reg[351] (\write_buffer.wr_buf_out_data_reg[351] ),
        .\write_buffer.wr_buf_out_data_reg[384] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[388] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[392] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[396] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[400] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[404] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[408] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[412] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[449] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[450] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 [0]}),
        .\write_buffer.wr_buf_out_data_reg[451] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[453] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[454] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 [0]}),
        .\write_buffer.wr_buf_out_data_reg[455] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[457] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[458] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 [0]}),
        .\write_buffer.wr_buf_out_data_reg[459] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[461] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[462] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 [0]}),
        .\write_buffer.wr_buf_out_data_reg[463] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[465] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[466] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 [0]}),
        .\write_buffer.wr_buf_out_data_reg[467] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[469] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[470] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 [0]}),
        .\write_buffer.wr_buf_out_data_reg[471] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[473] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[474] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 [0]}),
        .\write_buffer.wr_buf_out_data_reg[475] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 [7:6],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[477] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 [3],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[478] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 [7:5],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 [2],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 [0]}),
        .\write_buffer.wr_buf_out_data_reg[479] ({u_ddr_calib_top_n_919,u_ddr_calib_top_n_920,u_ddr_calib_top_n_921,u_ddr_calib_top_n_922,u_ddr_calib_top_n_923}),
        .\write_buffer.wr_buf_out_data_reg[489] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[490] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[491] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[493] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[494] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[495] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),
        .\write_buffer.wr_buf_out_data_reg[497] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[498] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[499] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[501] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[502] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[503] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),
        .\write_buffer.wr_buf_out_data_reg[505] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[506] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[507] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[509] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[510] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .\write_buffer.wr_buf_out_data_reg[511] ({u_ddr_calib_top_n_1122,u_ddr_calib_top_n_1123,u_ddr_calib_top_n_1124,u_ddr_calib_top_n_1125,u_ddr_calib_top_n_1126,u_ddr_calib_top_n_1127,u_ddr_calib_top_n_1128,u_ddr_calib_top_n_1129}),
        .\write_buffer.wr_buf_out_data_reg[571] ({\write_buffer.wr_buf_out_data_reg[575] [571:568],\write_buffer.wr_buf_out_data_reg[575] [563:560],\write_buffer.wr_buf_out_data_reg[575] [555:552],\write_buffer.wr_buf_out_data_reg[575] [547:544],\write_buffer.wr_buf_out_data_reg[575] [539:536],\write_buffer.wr_buf_out_data_reg[575] [531:528],\write_buffer.wr_buf_out_data_reg[575] [523:520],\write_buffer.wr_buf_out_data_reg[575] [515:512],\write_buffer.wr_buf_out_data_reg[575] [476],\write_buffer.wr_buf_out_data_reg[575] [472],\write_buffer.wr_buf_out_data_reg[575] [468],\write_buffer.wr_buf_out_data_reg[575] [464],\write_buffer.wr_buf_out_data_reg[575] [460],\write_buffer.wr_buf_out_data_reg[575] [456],\write_buffer.wr_buf_out_data_reg[575] [452],\write_buffer.wr_buf_out_data_reg[575] [448],\write_buffer.wr_buf_out_data_reg[575] [351],\write_buffer.wr_buf_out_data_reg[575] [347],\write_buffer.wr_buf_out_data_reg[575] [343],\write_buffer.wr_buf_out_data_reg[575] [339],\write_buffer.wr_buf_out_data_reg[575] [335],\write_buffer.wr_buf_out_data_reg[575] [331],\write_buffer.wr_buf_out_data_reg[575] [327],\write_buffer.wr_buf_out_data_reg[575] [323],\write_buffer.wr_buf_out_data_reg[575] [286:285],\write_buffer.wr_buf_out_data_reg[575] [282:281],\write_buffer.wr_buf_out_data_reg[575] [278:277],\write_buffer.wr_buf_out_data_reg[575] [274:273],\write_buffer.wr_buf_out_data_reg[575] [270:269],\write_buffer.wr_buf_out_data_reg[575] [266:265],\write_buffer.wr_buf_out_data_reg[575] [262:261],\write_buffer.wr_buf_out_data_reg[575] [258:257],\write_buffer.wr_buf_out_data_reg[575] [222],\write_buffer.wr_buf_out_data_reg[575] [218],\write_buffer.wr_buf_out_data_reg[575] [214],\write_buffer.wr_buf_out_data_reg[575] [210],\write_buffer.wr_buf_out_data_reg[575] [206],\write_buffer.wr_buf_out_data_reg[575] [202],\write_buffer.wr_buf_out_data_reg[575] [198],\write_buffer.wr_buf_out_data_reg[575] [194],\write_buffer.wr_buf_out_data_reg[575] [157],\write_buffer.wr_buf_out_data_reg[575] [153],\write_buffer.wr_buf_out_data_reg[575] [149],\write_buffer.wr_buf_out_data_reg[575] [145],\write_buffer.wr_buf_out_data_reg[575] [141],\write_buffer.wr_buf_out_data_reg[575] [137],\write_buffer.wr_buf_out_data_reg[575] [133],\write_buffer.wr_buf_out_data_reg[575] [129],\write_buffer.wr_buf_out_data_reg[575] [95:94],\write_buffer.wr_buf_out_data_reg[575] [91:90],\write_buffer.wr_buf_out_data_reg[575] [87:86],\write_buffer.wr_buf_out_data_reg[575] [83:82],\write_buffer.wr_buf_out_data_reg[575] [79:78],\write_buffer.wr_buf_out_data_reg[575] [75:74],\write_buffer.wr_buf_out_data_reg[575] [71:70],\write_buffer.wr_buf_out_data_reg[575] [67:66],\write_buffer.wr_buf_out_data_reg[575] [31],\write_buffer.wr_buf_out_data_reg[575] [28:27],\write_buffer.wr_buf_out_data_reg[575] [24:23],\write_buffer.wr_buf_out_data_reg[575] [20:19],\write_buffer.wr_buf_out_data_reg[575] [16:15],\write_buffer.wr_buf_out_data_reg[575] [12:11],\write_buffer.wr_buf_out_data_reg[575] [8:7],\write_buffer.wr_buf_out_data_reg[575] [4:3],\write_buffer.wr_buf_out_data_reg[575] [0]}),
        .write_calib(write_calib));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_wrcal" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_wrcal
   (rd_active_r,
    wrcal_resume_w,
    wrcal_sanity_chk_r,
    wrcal_prech_req,
    wrcal_sanity_chk_done,
    wrlvl_byte_redo,
    early1_data,
    early2_data,
    phy_if_reset_w,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \init_state_r_reg[0] ,
    wrcal_done_reg_0,
    \init_state_r_reg[2] ,
    \corse_cnt_reg[7][0] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[3] ,
    \idelay_tap_cnt_r_reg[0][7][4] ,
    \idelay_tap_cnt_r_reg[0][0][0] ,
    prech_req,
    \init_state_r_reg[5] ,
    \corse_cnt_reg[6][0] ,
    \corse_cnt_reg[3][0] ,
    \corse_cnt_reg[3][0]_0 ,
    wr_level_done0,
    \wl_state_r_reg[0] ,
    \wl_state_r_reg[2] ,
    \wl_state_r_reg[2]_0 ,
    \idelay_tap_cnt_r_reg[0][0][0]_0 ,
    \idelay_tap_cnt_r_reg[0][1][0] ,
    \idelay_tap_cnt_r_reg[0][2][0] ,
    \idelay_tap_cnt_r_reg[0][3][0] ,
    E,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    D,
    phy_rddata_en,
    CLK,
    wrcal_sanity_chk,
    p_0_out,
    \po_stg2_wrcal_cnt_reg[0]_0 ,
    \po_stg2_wrcal_cnt_reg[0]_1 ,
    \po_stg2_wrcal_cnt_reg[0]_2 ,
    \po_stg2_wrcal_cnt_reg[0]_3 ,
    \po_stg2_wrcal_cnt_reg[0]_4 ,
    \po_stg2_wrcal_cnt_reg[0]_5 ,
    \po_stg2_wrcal_cnt_reg[0]_6 ,
    \po_stg2_wrcal_cnt_reg[0]_7 ,
    \po_stg2_wrcal_cnt_reg[0]_8 ,
    \po_stg2_wrcal_cnt_reg[0]_9 ,
    \po_stg2_wrcal_cnt_reg[0]_10 ,
    \po_stg2_wrcal_cnt_reg[0]_11 ,
    \po_stg2_wrcal_cnt_reg[0]_12 ,
    \po_stg2_wrcal_cnt_reg[0]_13 ,
    \po_stg2_wrcal_cnt_reg[0]_14 ,
    \po_stg2_wrcal_cnt_reg[0]_15 ,
    \po_stg2_wrcal_cnt_reg[0]_16 ,
    \po_stg2_wrcal_cnt_reg[0]_17 ,
    \po_stg2_wrcal_cnt_reg[0]_18 ,
    \po_stg2_wrcal_cnt_reg[0]_19 ,
    \po_stg2_wrcal_cnt_reg[0]_20 ,
    \po_stg2_wrcal_cnt_reg[0]_21 ,
    \po_stg2_wrcal_cnt_reg[0]_22 ,
    \po_stg2_wrcal_cnt_reg[0]_23 ,
    \po_stg2_wrcal_cnt_reg[0]_24 ,
    \po_stg2_wrcal_cnt_reg[0]_25 ,
    \po_stg2_wrcal_cnt_reg[0]_26 ,
    \po_stg2_wrcal_cnt_reg[0]_27 ,
    \po_stg2_wrcal_cnt_reg[0]_28 ,
    \po_stg2_wrcal_cnt_reg[0]_29 ,
    \po_stg2_wrcal_cnt_reg[0]_30 ,
    \po_stg2_wrcal_cnt_reg[0]_31 ,
    \po_stg2_wrcal_cnt_reg[0]_32 ,
    \po_stg2_wrcal_cnt_reg[0]_33 ,
    \po_stg2_wrcal_cnt_reg[0]_34 ,
    \po_stg2_wrcal_cnt_reg[0]_35 ,
    \po_stg2_wrcal_cnt_reg[0]_36 ,
    \po_stg2_wrcal_cnt_reg[0]_37 ,
    \po_stg2_wrcal_cnt_reg[0]_38 ,
    \po_stg2_wrcal_cnt_reg[0]_39 ,
    \po_stg2_wrcal_cnt_reg[0]_40 ,
    \po_stg2_wrcal_cnt_reg[0]_41 ,
    \po_stg2_wrcal_cnt_reg[0]_42 ,
    \po_stg2_wrcal_cnt_reg[0]_43 ,
    \po_stg2_wrcal_cnt_reg[0]_44 ,
    \po_stg2_wrcal_cnt_reg[0]_45 ,
    \po_stg2_wrcal_cnt_reg[0]_46 ,
    \po_stg2_wrcal_cnt_reg[0]_47 ,
    \po_stg2_wrcal_cnt_reg[0]_48 ,
    \po_stg2_wrcal_cnt_reg[0]_49 ,
    \po_stg2_wrcal_cnt_reg[0]_50 ,
    \po_stg2_wrcal_cnt_reg[0]_51 ,
    \po_stg2_wrcal_cnt_reg[0]_52 ,
    \po_stg2_wrcal_cnt_reg[0]_53 ,
    \po_stg2_wrcal_cnt_reg[0]_54 ,
    \po_stg2_wrcal_cnt_reg[0]_55 ,
    \po_stg2_wrcal_cnt_reg[0]_56 ,
    \po_stg2_wrcal_cnt_reg[0]_57 ,
    \po_stg2_wrcal_cnt_reg[0]_58 ,
    \po_stg2_wrcal_cnt_reg[0]_59 ,
    \po_stg2_wrcal_cnt_reg[0]_60 ,
    \po_stg2_wrcal_cnt_reg[0]_61 ,
    \po_stg2_wrcal_cnt_reg[0]_62 ,
    rstdiv0_sync_r1_reg_rep__3,
    wrlvl_byte_done,
    \gen_byte_sel_div2.calib_in_common_reg ,
    Q,
    \calib_zero_inputs_reg[2] ,
    idelay_ld_rst,
    idelay_ld_rst_2,
    idelay_ld_rst_3,
    idelay_ld_rst_4,
    ddr3_lm_done_r,
    dqs_found_done_r_reg,
    rdlvl_stg1_done_reg,
    wrlvl_done_r1,
    mem_init_done_r,
    \wl_state_r_reg[4] ,
    wrlvl_byte_redo_r,
    idelay_ce_int,
    rdlvl_prech_req,
    dqs_found_prech_req,
    \init_state_r_reg[5]_0 ,
    prech_req_posedge_r_reg,
    wr_level_done_r5_reg,
    \dqs_count_r_reg[2]_rep ,
    \dqs_count_r_reg[1] ,
    wr_level_done_r5,
    \dqs_count_r_reg[2]_rep__0 ,
    wl_sm_start,
    \cal1_cnt_cpt_r_reg[0] ,
    \rnk_cnt_r_reg[0] ,
    rstdiv0_sync_r1_reg_rep__23,
    idelay_ld_rst_5,
    idelay_ld_rst_6,
    idelay_ld_rst_7,
    idelay_ld_rst_8,
    wrcal_sanity_chk_reg,
    wr_level_done_reg,
    rdlvl_stg1_done_reg_0,
    \dqs_count_r_reg[2]_rep__0_0 ,
    rdlvl_stg1_done_reg_1,
    rdlvl_stg1_done_reg_2,
    rstdiv0_sync_r1_reg_rep__22,
    wrcal_rd_wait,
    wrcal_start_reg,
    prech_done);
  output rd_active_r;
  output wrcal_resume_w;
  output wrcal_sanity_chk_r;
  output wrcal_prech_req;
  output wrcal_sanity_chk_done;
  output wrlvl_byte_redo;
  output early1_data;
  output early2_data;
  output phy_if_reset_w;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output \init_state_r_reg[0] ;
  output wrcal_done_reg_0;
  output \init_state_r_reg[2] ;
  output \corse_cnt_reg[7][0] ;
  output [3:0]\gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  output \idelay_tap_cnt_r_reg[0][7][4] ;
  output \idelay_tap_cnt_r_reg[0][0][0] ;
  output prech_req;
  output \init_state_r_reg[5] ;
  output \corse_cnt_reg[6][0] ;
  output \corse_cnt_reg[3][0] ;
  output \corse_cnt_reg[3][0]_0 ;
  output wr_level_done0;
  output \wl_state_r_reg[0] ;
  output \wl_state_r_reg[2] ;
  output \wl_state_r_reg[2]_0 ;
  output \idelay_tap_cnt_r_reg[0][0][0]_0 ;
  output \idelay_tap_cnt_r_reg[0][1][0] ;
  output \idelay_tap_cnt_r_reg[0][2][0] ;
  output \idelay_tap_cnt_r_reg[0][3][0] ;
  output [0:0]E;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output [3:0]D;
  input phy_rddata_en;
  input CLK;
  input wrcal_sanity_chk;
  input p_0_out;
  input \po_stg2_wrcal_cnt_reg[0]_0 ;
  input \po_stg2_wrcal_cnt_reg[0]_1 ;
  input \po_stg2_wrcal_cnt_reg[0]_2 ;
  input \po_stg2_wrcal_cnt_reg[0]_3 ;
  input \po_stg2_wrcal_cnt_reg[0]_4 ;
  input \po_stg2_wrcal_cnt_reg[0]_5 ;
  input \po_stg2_wrcal_cnt_reg[0]_6 ;
  input \po_stg2_wrcal_cnt_reg[0]_7 ;
  input \po_stg2_wrcal_cnt_reg[0]_8 ;
  input \po_stg2_wrcal_cnt_reg[0]_9 ;
  input \po_stg2_wrcal_cnt_reg[0]_10 ;
  input \po_stg2_wrcal_cnt_reg[0]_11 ;
  input \po_stg2_wrcal_cnt_reg[0]_12 ;
  input \po_stg2_wrcal_cnt_reg[0]_13 ;
  input \po_stg2_wrcal_cnt_reg[0]_14 ;
  input \po_stg2_wrcal_cnt_reg[0]_15 ;
  input \po_stg2_wrcal_cnt_reg[0]_16 ;
  input \po_stg2_wrcal_cnt_reg[0]_17 ;
  input \po_stg2_wrcal_cnt_reg[0]_18 ;
  input \po_stg2_wrcal_cnt_reg[0]_19 ;
  input \po_stg2_wrcal_cnt_reg[0]_20 ;
  input \po_stg2_wrcal_cnt_reg[0]_21 ;
  input \po_stg2_wrcal_cnt_reg[0]_22 ;
  input \po_stg2_wrcal_cnt_reg[0]_23 ;
  input \po_stg2_wrcal_cnt_reg[0]_24 ;
  input \po_stg2_wrcal_cnt_reg[0]_25 ;
  input \po_stg2_wrcal_cnt_reg[0]_26 ;
  input \po_stg2_wrcal_cnt_reg[0]_27 ;
  input \po_stg2_wrcal_cnt_reg[0]_28 ;
  input \po_stg2_wrcal_cnt_reg[0]_29 ;
  input \po_stg2_wrcal_cnt_reg[0]_30 ;
  input \po_stg2_wrcal_cnt_reg[0]_31 ;
  input \po_stg2_wrcal_cnt_reg[0]_32 ;
  input \po_stg2_wrcal_cnt_reg[0]_33 ;
  input \po_stg2_wrcal_cnt_reg[0]_34 ;
  input \po_stg2_wrcal_cnt_reg[0]_35 ;
  input \po_stg2_wrcal_cnt_reg[0]_36 ;
  input \po_stg2_wrcal_cnt_reg[0]_37 ;
  input \po_stg2_wrcal_cnt_reg[0]_38 ;
  input \po_stg2_wrcal_cnt_reg[0]_39 ;
  input \po_stg2_wrcal_cnt_reg[0]_40 ;
  input \po_stg2_wrcal_cnt_reg[0]_41 ;
  input \po_stg2_wrcal_cnt_reg[0]_42 ;
  input \po_stg2_wrcal_cnt_reg[0]_43 ;
  input \po_stg2_wrcal_cnt_reg[0]_44 ;
  input \po_stg2_wrcal_cnt_reg[0]_45 ;
  input \po_stg2_wrcal_cnt_reg[0]_46 ;
  input \po_stg2_wrcal_cnt_reg[0]_47 ;
  input \po_stg2_wrcal_cnt_reg[0]_48 ;
  input \po_stg2_wrcal_cnt_reg[0]_49 ;
  input \po_stg2_wrcal_cnt_reg[0]_50 ;
  input \po_stg2_wrcal_cnt_reg[0]_51 ;
  input \po_stg2_wrcal_cnt_reg[0]_52 ;
  input \po_stg2_wrcal_cnt_reg[0]_53 ;
  input \po_stg2_wrcal_cnt_reg[0]_54 ;
  input \po_stg2_wrcal_cnt_reg[0]_55 ;
  input \po_stg2_wrcal_cnt_reg[0]_56 ;
  input \po_stg2_wrcal_cnt_reg[0]_57 ;
  input \po_stg2_wrcal_cnt_reg[0]_58 ;
  input \po_stg2_wrcal_cnt_reg[0]_59 ;
  input \po_stg2_wrcal_cnt_reg[0]_60 ;
  input \po_stg2_wrcal_cnt_reg[0]_61 ;
  input \po_stg2_wrcal_cnt_reg[0]_62 ;
  input rstdiv0_sync_r1_reg_rep__3;
  input wrlvl_byte_done;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input [1:0]Q;
  input [2:0]\calib_zero_inputs_reg[2] ;
  input idelay_ld_rst;
  input idelay_ld_rst_2;
  input idelay_ld_rst_3;
  input idelay_ld_rst_4;
  input ddr3_lm_done_r;
  input dqs_found_done_r_reg;
  input rdlvl_stg1_done_reg;
  input wrlvl_done_r1;
  input mem_init_done_r;
  input [2:0]\wl_state_r_reg[4] ;
  input wrlvl_byte_redo_r;
  input idelay_ce_int;
  input rdlvl_prech_req;
  input dqs_found_prech_req;
  input \init_state_r_reg[5]_0 ;
  input prech_req_posedge_r_reg;
  input wr_level_done_r5_reg;
  input \dqs_count_r_reg[2]_rep ;
  input \dqs_count_r_reg[1] ;
  input wr_level_done_r5;
  input \dqs_count_r_reg[2]_rep__0 ;
  input wl_sm_start;
  input \cal1_cnt_cpt_r_reg[0] ;
  input \rnk_cnt_r_reg[0] ;
  input rstdiv0_sync_r1_reg_rep__23;
  input idelay_ld_rst_5;
  input idelay_ld_rst_6;
  input idelay_ld_rst_7;
  input idelay_ld_rst_8;
  input wrcal_sanity_chk_reg;
  input wr_level_done_reg;
  input rdlvl_stg1_done_reg_0;
  input \dqs_count_r_reg[2]_rep__0_0 ;
  input rdlvl_stg1_done_reg_1;
  input rdlvl_stg1_done_reg_2;
  input rstdiv0_sync_r1_reg_rep__22;
  input wrcal_rd_wait;
  input wrcal_start_reg;
  input prech_done;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [1:0]Q;
  wire \cal1_cnt_cpt_r_reg[0] ;
  wire cal2_done_r;
  wire cal2_done_r_i_1_n_0;
  wire cal2_if_reset_i_1_n_0;
  wire cal2_if_reset_i_2_n_0;
  wire cal2_if_reset_i_3_n_0;
  wire cal2_if_reset_i_4_n_0;
  wire cal2_if_reset_i_5_n_0;
  wire cal2_prech_req_r;
  wire cal2_prech_req_r_i_1_n_0;
  wire cal2_prech_req_r_i_2_n_0;
  wire \cal2_state_r[0]_i_2_n_0 ;
  wire \cal2_state_r[0]_i_3_n_0 ;
  wire \cal2_state_r[0]_i_4_n_0 ;
  wire \cal2_state_r[0]_i_5_n_0 ;
  wire \cal2_state_r[0]_i_6_n_0 ;
  wire \cal2_state_r[1]_i_2_n_0 ;
  wire \cal2_state_r[1]_i_3_n_0 ;
  wire \cal2_state_r[1]_i_4_n_0 ;
  wire \cal2_state_r[2]_i_1_n_0 ;
  wire \cal2_state_r[2]_i_2_n_0 ;
  wire \cal2_state_r[2]_i_3_n_0 ;
  wire \cal2_state_r[3]_i_10_n_0 ;
  wire \cal2_state_r[3]_i_2_n_0 ;
  wire \cal2_state_r[3]_i_3_n_0 ;
  wire \cal2_state_r[3]_i_4_n_0 ;
  wire \cal2_state_r[3]_i_5_n_0 ;
  wire \cal2_state_r[3]_i_6_n_0 ;
  wire \cal2_state_r[3]_i_7_n_0 ;
  wire \cal2_state_r[3]_i_8_n_0 ;
  wire \cal2_state_r[3]_i_9_n_0 ;
  wire \cal2_state_r_reg[0]_i_1_n_0 ;
  wire \cal2_state_r_reg[1]_i_1_n_0 ;
  wire \cal2_state_r_reg[3]_i_1_n_0 ;
  wire \cal2_state_r_reg_n_0_[0] ;
  wire \cal2_state_r_reg_n_0_[1] ;
  wire \cal2_state_r_reg_n_0_[2] ;
  wire \cal2_state_r_reg_n_0_[3] ;
  wire [2:0]\calib_zero_inputs_reg[2] ;
  wire \corse_cnt_reg[3][0] ;
  wire \corse_cnt_reg[3][0]_0 ;
  wire \corse_cnt_reg[6][0] ;
  wire \corse_cnt_reg[7][0] ;
  wire ddr3_lm_done_r;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire \dqs_count_r_reg[1] ;
  wire \dqs_count_r_reg[2]_rep ;
  wire \dqs_count_r_reg[2]_rep__0 ;
  wire \dqs_count_r_reg[2]_rep__0_0 ;
  wire dqs_found_done_r_reg;
  wire dqs_found_prech_req;
  wire early1_data;
  wire early1_data_i_1_n_0;
  wire early1_data_i_2_n_0;
  wire early1_data_i_3_n_0;
  wire early1_data_match_r;
  wire early1_data_match_r0;
  wire early1_match_fall0_and_r;
  wire [6:0]early1_match_fall0_r;
  wire early1_match_fall1_and_r;
  wire [7:0]early1_match_fall1_r;
  wire early1_match_fall2_and_r;
  wire [7:2]early1_match_fall2_r;
  wire early1_match_fall3_and_r;
  wire [6:0]early1_match_fall3_r;
  wire early1_match_rise0_and_r;
  wire [6:0]early1_match_rise0_r;
  wire early1_match_rise1_and_r;
  wire [7:0]early1_match_rise1_r;
  wire early1_match_rise2_and_r;
  wire [7:2]early1_match_rise2_r;
  wire early1_match_rise3_and_r;
  wire [5:1]early1_match_rise3_r;
  wire early2_data;
  wire early2_data_i_1_n_0;
  wire early2_data_match_r;
  wire early2_data_match_r0;
  wire early2_match_fall0_and_r;
  wire [7:1]early2_match_fall0_r;
  wire early2_match_fall1_and_r;
  wire early2_match_fall2_and_r;
  wire [5:0]early2_match_fall2_r;
  wire early2_match_fall3_and_r;
  wire early2_match_rise0_and_r;
  wire [7:1]early2_match_rise0_r;
  wire early2_match_rise1_and_r;
  wire early2_match_rise2_and_r;
  wire [5:1]early2_match_rise2_r;
  wire early2_match_rise3_and_r;
  wire [6:0]early2_match_rise3_r;
  wire [3:0]\gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ;
  wire \gen_pat_match_div4.early1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_23 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_63 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_39 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_15 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_55 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_7 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_31 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_47 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_24 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_64 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_40 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_16 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_56 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_8 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_32 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_48 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_25 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_65 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_41 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_17 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_57 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_9 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_33 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_49 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_26 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_66 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_42 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_18 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_58 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_10 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_34 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_50 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_27 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_67 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_43 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_19 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_59 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_11 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_35 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_51 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_28 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_68 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_44 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_20 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_60 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_12 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_36 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_52 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_29 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_69 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_45 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_21 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_61 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_13 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_37 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_53 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_30 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_70 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_46 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_22 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_62 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_14 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_38 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_54 ;
  wire idelay_ce_int;
  wire idelay_ld;
  wire idelay_ld_done_i_1_n_0;
  wire idelay_ld_done_i_2_n_0;
  wire idelay_ld_done_reg_n_0;
  wire idelay_ld_i_1_n_0;
  wire idelay_ld_i_2_n_0;
  wire idelay_ld_rst;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_6;
  wire idelay_ld_rst_7;
  wire idelay_ld_rst_8;
  wire \idelay_tap_cnt_r_reg[0][0][0] ;
  wire \idelay_tap_cnt_r_reg[0][0][0]_0 ;
  wire \idelay_tap_cnt_r_reg[0][1][0] ;
  wire \idelay_tap_cnt_r_reg[0][2][0] ;
  wire \idelay_tap_cnt_r_reg[0][3][0] ;
  wire \idelay_tap_cnt_r_reg[0][7][4] ;
  wire \init_state_r_reg[0] ;
  wire \init_state_r_reg[2] ;
  wire \init_state_r_reg[5] ;
  wire \init_state_r_reg[5]_0 ;
  wire mem_init_done_r;
  wire \not_empty_wait_cnt[4]_i_1_n_0 ;
  wire \not_empty_wait_cnt_reg_n_0_[0] ;
  wire \not_empty_wait_cnt_reg_n_0_[1] ;
  wire \not_empty_wait_cnt_reg_n_0_[2] ;
  wire \not_empty_wait_cnt_reg_n_0_[3] ;
  wire \not_empty_wait_cnt_reg_n_0_[4] ;
  wire [4:0]p_0_in;
  wire [3:0]p_0_in__0;
  wire p_0_out;
  wire pat_data_match_r;
  wire pat_data_match_r0;
  wire pat_data_match_valid_r;
  wire pat_match_fall0_and_r;
  wire [7:0]pat_match_fall0_r;
  wire pat_match_fall1_and_r;
  wire [7:0]pat_match_fall1_r;
  wire pat_match_fall2_and_r;
  wire [7:0]pat_match_fall2_r;
  wire pat_match_fall3_and_r;
  wire [7:0]pat_match_fall3_r;
  wire pat_match_rise0_and_r;
  wire [7:0]pat_match_rise0_r;
  wire pat_match_rise1_and_r;
  wire [7:0]pat_match_rise1_r;
  wire pat_match_rise2_and_r;
  wire [7:0]pat_match_rise2_r;
  wire pat_match_rise3_and_r;
  wire [7:0]pat_match_rise3_r;
  wire phy_if_reset_w;
  wire phy_rddata_en;
  wire \po_stg2_wrcal_cnt_reg[0]_0 ;
  wire \po_stg2_wrcal_cnt_reg[0]_1 ;
  wire \po_stg2_wrcal_cnt_reg[0]_10 ;
  wire \po_stg2_wrcal_cnt_reg[0]_11 ;
  wire \po_stg2_wrcal_cnt_reg[0]_12 ;
  wire \po_stg2_wrcal_cnt_reg[0]_13 ;
  wire \po_stg2_wrcal_cnt_reg[0]_14 ;
  wire \po_stg2_wrcal_cnt_reg[0]_15 ;
  wire \po_stg2_wrcal_cnt_reg[0]_16 ;
  wire \po_stg2_wrcal_cnt_reg[0]_17 ;
  wire \po_stg2_wrcal_cnt_reg[0]_18 ;
  wire \po_stg2_wrcal_cnt_reg[0]_19 ;
  wire \po_stg2_wrcal_cnt_reg[0]_2 ;
  wire \po_stg2_wrcal_cnt_reg[0]_20 ;
  wire \po_stg2_wrcal_cnt_reg[0]_21 ;
  wire \po_stg2_wrcal_cnt_reg[0]_22 ;
  wire \po_stg2_wrcal_cnt_reg[0]_23 ;
  wire \po_stg2_wrcal_cnt_reg[0]_24 ;
  wire \po_stg2_wrcal_cnt_reg[0]_25 ;
  wire \po_stg2_wrcal_cnt_reg[0]_26 ;
  wire \po_stg2_wrcal_cnt_reg[0]_27 ;
  wire \po_stg2_wrcal_cnt_reg[0]_28 ;
  wire \po_stg2_wrcal_cnt_reg[0]_29 ;
  wire \po_stg2_wrcal_cnt_reg[0]_3 ;
  wire \po_stg2_wrcal_cnt_reg[0]_30 ;
  wire \po_stg2_wrcal_cnt_reg[0]_31 ;
  wire \po_stg2_wrcal_cnt_reg[0]_32 ;
  wire \po_stg2_wrcal_cnt_reg[0]_33 ;
  wire \po_stg2_wrcal_cnt_reg[0]_34 ;
  wire \po_stg2_wrcal_cnt_reg[0]_35 ;
  wire \po_stg2_wrcal_cnt_reg[0]_36 ;
  wire \po_stg2_wrcal_cnt_reg[0]_37 ;
  wire \po_stg2_wrcal_cnt_reg[0]_38 ;
  wire \po_stg2_wrcal_cnt_reg[0]_39 ;
  wire \po_stg2_wrcal_cnt_reg[0]_4 ;
  wire \po_stg2_wrcal_cnt_reg[0]_40 ;
  wire \po_stg2_wrcal_cnt_reg[0]_41 ;
  wire \po_stg2_wrcal_cnt_reg[0]_42 ;
  wire \po_stg2_wrcal_cnt_reg[0]_43 ;
  wire \po_stg2_wrcal_cnt_reg[0]_44 ;
  wire \po_stg2_wrcal_cnt_reg[0]_45 ;
  wire \po_stg2_wrcal_cnt_reg[0]_46 ;
  wire \po_stg2_wrcal_cnt_reg[0]_47 ;
  wire \po_stg2_wrcal_cnt_reg[0]_48 ;
  wire \po_stg2_wrcal_cnt_reg[0]_49 ;
  wire \po_stg2_wrcal_cnt_reg[0]_5 ;
  wire \po_stg2_wrcal_cnt_reg[0]_50 ;
  wire \po_stg2_wrcal_cnt_reg[0]_51 ;
  wire \po_stg2_wrcal_cnt_reg[0]_52 ;
  wire \po_stg2_wrcal_cnt_reg[0]_53 ;
  wire \po_stg2_wrcal_cnt_reg[0]_54 ;
  wire \po_stg2_wrcal_cnt_reg[0]_55 ;
  wire \po_stg2_wrcal_cnt_reg[0]_56 ;
  wire \po_stg2_wrcal_cnt_reg[0]_57 ;
  wire \po_stg2_wrcal_cnt_reg[0]_58 ;
  wire \po_stg2_wrcal_cnt_reg[0]_59 ;
  wire \po_stg2_wrcal_cnt_reg[0]_6 ;
  wire \po_stg2_wrcal_cnt_reg[0]_60 ;
  wire \po_stg2_wrcal_cnt_reg[0]_61 ;
  wire \po_stg2_wrcal_cnt_reg[0]_62 ;
  wire \po_stg2_wrcal_cnt_reg[0]_7 ;
  wire \po_stg2_wrcal_cnt_reg[0]_8 ;
  wire \po_stg2_wrcal_cnt_reg[0]_9 ;
  wire prech_done;
  wire prech_req;
  wire prech_req_posedge_r_reg;
  wire rd_active_r;
  wire rd_active_r1;
  wire rd_active_r3_reg_srl2_n_0;
  wire rdlvl_prech_req;
  wire rdlvl_stg1_done_reg;
  wire rdlvl_stg1_done_reg_0;
  wire rdlvl_stg1_done_reg_1;
  wire rdlvl_stg1_done_reg_2;
  wire \rnk_cnt_r_reg[0] ;
  wire rstdiv0_sync_r1_reg_rep__22;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire \tap_inc_wait_cnt[3]_i_1_n_0 ;
  wire [3:0]tap_inc_wait_cnt_reg__0;
  wire wl_sm_start;
  wire \wl_state_r_reg[0] ;
  wire \wl_state_r_reg[2] ;
  wire \wl_state_r_reg[2]_0 ;
  wire [2:0]\wl_state_r_reg[4] ;
  wire wr_level_done0;
  wire wr_level_done_r5;
  wire wr_level_done_r5_reg;
  wire wr_level_done_reg;
  wire wrcal_done_i_1_n_0;
  wire wrcal_done_reg_0;
  wire [3:0]wrcal_dqs_cnt_r;
  wire \wrcal_dqs_cnt_r[0]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[1]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[2]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[3]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[3]_i_2_n_0 ;
  wire \wrcal_dqs_cnt_r[3]_i_3_n_0 ;
  wire wrcal_pat_resume_r;
  wire wrcal_pat_resume_r2_reg_srl2_n_0;
  wire wrcal_pat_resume_r_i_1_n_0;
  wire wrcal_pat_resume_r_i_2_n_0;
  wire wrcal_pat_resume_r_i_3_n_0;
  wire wrcal_pat_resume_r_i_4_n_0;
  wire wrcal_pat_resume_r_i_5_n_0;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire wrcal_sanity_chk_done;
  wire wrcal_sanity_chk_done_i_1_n_0;
  wire wrcal_sanity_chk_r;
  wire wrcal_sanity_chk_reg;
  wire wrcal_start_reg;
  wire wrlvl_byte_done;
  wire wrlvl_byte_done_r;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_i_1_n_0;
  wire wrlvl_byte_redo_i_2_n_0;
  wire wrlvl_byte_redo_i_3_n_0;
  wire wrlvl_byte_redo_r;
  wire wrlvl_done_r1;

  LUT6 #(
    .INIT(64'hFFFFDFFF00001000)) 
    cal2_done_r_i_1
       (.I0(wrcal_sanity_chk_reg),
        .I1(\cal2_state_r_reg_n_0_[3] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(cal2_done_r),
        .O(cal2_done_r_i_1_n_0));
  FDRE cal2_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_done_r_i_1_n_0),
        .Q(cal2_done_r),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT6 #(
    .INIT(64'hFFFFBABF00008A80)) 
    cal2_if_reset_i_1
       (.I0(cal2_if_reset_i_2_n_0),
        .I1(cal2_if_reset_i_3_n_0),
        .I2(\cal2_state_r_reg_n_0_[0] ),
        .I3(cal2_if_reset_i_4_n_0),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .I5(phy_if_reset_w),
        .O(cal2_if_reset_i_1_n_0));
  LUT6 #(
    .INIT(64'h004F0040F000F000)) 
    cal2_if_reset_i_2
       (.I0(rd_active_r),
        .I1(rd_active_r1),
        .I2(\cal2_state_r_reg_n_0_[0] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(wrcal_sanity_chk_r),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(cal2_if_reset_i_2_n_0));
  LUT6 #(
    .INIT(64'h00FF000008FF08FF)) 
    cal2_if_reset_i_3
       (.I0(wrlvl_byte_done),
        .I1(rd_active_r1),
        .I2(rd_active_r),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(idelay_ld_done_i_2_n_0),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(cal2_if_reset_i_3_n_0));
  LUT6 #(
    .INIT(64'hFF80FFFFFF800000)) 
    cal2_if_reset_i_4
       (.I0(prech_done),
        .I1(cal2_prech_req_r_i_2_n_0),
        .I2(wrcal_sanity_chk_r),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(cal2_if_reset_i_5_n_0),
        .O(cal2_if_reset_i_4_n_0));
  LUT6 #(
    .INIT(64'h8000FFFF80000000)) 
    cal2_if_reset_i_5
       (.I0(tap_inc_wait_cnt_reg__0[3]),
        .I1(tap_inc_wait_cnt_reg__0[0]),
        .I2(tap_inc_wait_cnt_reg__0[1]),
        .I3(tap_inc_wait_cnt_reg__0[2]),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .I5(wrcal_start_reg),
        .O(cal2_if_reset_i_5_n_0));
  FDRE cal2_if_reset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_if_reset_i_1_n_0),
        .Q(phy_if_reset_w),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT6 #(
    .INIT(64'h0000000010110000)) 
    cal2_prech_req_r_i_1
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(cal2_prech_req_r_i_2_n_0),
        .I3(wrcal_sanity_chk_r),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(\cal2_state_r_reg_n_0_[0] ),
        .O(cal2_prech_req_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    cal2_prech_req_r_i_2
       (.I0(wrcal_dqs_cnt_r[2]),
        .I1(wrcal_dqs_cnt_r[1]),
        .I2(wrcal_dqs_cnt_r[0]),
        .I3(wrcal_dqs_cnt_r[3]),
        .O(cal2_prech_req_r_i_2_n_0));
  FDRE cal2_prech_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_prech_req_r_i_1_n_0),
        .Q(cal2_prech_req_r),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT6 #(
    .INIT(64'h000000005D0D5D5D)) 
    \cal2_state_r[0]_i_2 
       (.I0(\cal2_state_r_reg_n_0_[2] ),
        .I1(\cal2_state_r[0]_i_4_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(\cal2_state_r[0]_i_5_n_0 ),
        .I4(prech_done),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000CCE2)) 
    \cal2_state_r[0]_i_3 
       (.I0(\cal2_state_r[0]_i_6_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(tap_inc_wait_cnt_reg__0[0]),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \cal2_state_r[0]_i_4 
       (.I0(idelay_ld_done_reg_n_0),
        .I1(wrcal_sanity_chk_r),
        .O(\cal2_state_r[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT4 #(
    .INIT(16'hFF7F)) 
    \cal2_state_r[0]_i_5 
       (.I0(wrcal_dqs_cnt_r[2]),
        .I1(wrcal_dqs_cnt_r[0]),
        .I2(wrcal_dqs_cnt_r[1]),
        .I3(wrcal_dqs_cnt_r[3]),
        .O(\cal2_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000A8AA)) 
    \cal2_state_r[0]_i_6 
       (.I0(pat_data_match_valid_r),
        .I1(early2_data_match_r),
        .I2(early1_data_match_r),
        .I3(idelay_ld_done_reg_n_0),
        .I4(wrcal_sanity_chk_r),
        .I5(pat_data_match_r),
        .O(\cal2_state_r[0]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h0F0050D0)) 
    \cal2_state_r[1]_i_2 
       (.I0(prech_done),
        .I1(cal2_prech_req_r_i_2_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrcal_sanity_chk_r),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \cal2_state_r[1]_i_3 
       (.I0(\cal2_state_r[1]_i_4_n_0 ),
        .I1(pat_data_match_r),
        .I2(pat_data_match_valid_r),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(tap_inc_wait_cnt_reg__0[1]),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(\cal2_state_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT4 #(
    .INIT(16'h5400)) 
    \cal2_state_r[1]_i_4 
       (.I0(wrcal_sanity_chk_r),
        .I1(early1_data_match_r),
        .I2(early2_data_match_r),
        .I3(pat_data_match_valid_r),
        .O(\cal2_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4F4AFFFF4F4A0000)) 
    \cal2_state_r[2]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[1] ),
        .I1(tap_inc_wait_cnt_reg__0[2]),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r[2]_i_2_n_0 ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(\cal2_state_r[2]_i_3_n_0 ),
        .O(\cal2_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \cal2_state_r[2]_i_2 
       (.I0(pat_data_match_valid_r),
        .I1(wrcal_sanity_chk_r),
        .I2(early2_data_match_r),
        .I3(early1_data_match_r),
        .I4(idelay_ld_done_reg_n_0),
        .I5(pat_data_match_r),
        .O(\cal2_state_r[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT5 #(
    .INIT(32'h0F00D0D0)) 
    \cal2_state_r[2]_i_3 
       (.I0(prech_done),
        .I1(cal2_prech_req_r_i_2_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrcal_sanity_chk_r),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \cal2_state_r[3]_i_10 
       (.I0(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00E2FFFF00E20000)) 
    \cal2_state_r[3]_i_2 
       (.I0(\cal2_state_r[3]_i_5_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(tap_inc_wait_cnt_reg__0[3]),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h45404F4F45404A4A)) 
    \cal2_state_r[3]_i_3 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r[3]_i_6_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(\cal2_state_r[3]_i_7_n_0 ),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .I5(wrcal_start_reg),
        .O(\cal2_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE222E2)) 
    \cal2_state_r[3]_i_4 
       (.I0(\cal2_state_r[3]_i_8_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r[3]_i_9_n_0 ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(\cal2_state_r[3]_i_7_n_0 ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h44444454FFFFFFFF)) 
    \cal2_state_r[3]_i_5 
       (.I0(pat_data_match_r),
        .I1(wrcal_sanity_chk_r),
        .I2(idelay_ld_done_reg_n_0),
        .I3(early2_data_match_r),
        .I4(early1_data_match_r),
        .I5(pat_data_match_valid_r),
        .O(\cal2_state_r[3]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h3B3B3808)) 
    \cal2_state_r[3]_i_6 
       (.I0(wrcal_sanity_chk),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(wrcal_sanity_chk_r),
        .I3(\cal2_state_r[0]_i_5_n_0 ),
        .I4(prech_done),
        .O(\cal2_state_r[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \cal2_state_r[3]_i_7 
       (.I0(tap_inc_wait_cnt_reg__0[3]),
        .I1(tap_inc_wait_cnt_reg__0[0]),
        .I2(tap_inc_wait_cnt_reg__0[1]),
        .I3(tap_inc_wait_cnt_reg__0[2]),
        .O(\cal2_state_r[3]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hBBBBB888)) 
    \cal2_state_r[3]_i_8 
       (.I0(idelay_ld_done_i_2_n_0),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(\cal2_state_r[3]_i_10_n_0 ),
        .I3(\not_empty_wait_cnt_reg_n_0_[4] ),
        .I4(pat_data_match_valid_r),
        .O(\cal2_state_r[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \cal2_state_r[3]_i_9 
       (.I0(rd_active_r),
        .I1(rd_active_r1),
        .I2(wrlvl_byte_done),
        .O(\cal2_state_r[3]_i_9_n_0 ));
  FDRE \cal2_state_r_reg[0] 
       (.C(CLK),
        .CE(\cal2_state_r_reg[3]_i_1_n_0 ),
        .D(\cal2_state_r_reg[0]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  MUXF7 \cal2_state_r_reg[0]_i_1 
       (.I0(\cal2_state_r[0]_i_2_n_0 ),
        .I1(\cal2_state_r[0]_i_3_n_0 ),
        .O(\cal2_state_r_reg[0]_i_1_n_0 ),
        .S(\cal2_state_r_reg_n_0_[0] ));
  FDRE \cal2_state_r_reg[1] 
       (.C(CLK),
        .CE(\cal2_state_r_reg[3]_i_1_n_0 ),
        .D(\cal2_state_r_reg[1]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  MUXF7 \cal2_state_r_reg[1]_i_1 
       (.I0(\cal2_state_r[1]_i_2_n_0 ),
        .I1(\cal2_state_r[1]_i_3_n_0 ),
        .O(\cal2_state_r_reg[1]_i_1_n_0 ),
        .S(\cal2_state_r_reg_n_0_[0] ));
  FDRE \cal2_state_r_reg[2] 
       (.C(CLK),
        .CE(\cal2_state_r_reg[3]_i_1_n_0 ),
        .D(\cal2_state_r[2]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \cal2_state_r_reg[3] 
       (.C(CLK),
        .CE(\cal2_state_r_reg[3]_i_1_n_0 ),
        .D(\cal2_state_r[3]_i_2_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__3));
  MUXF7 \cal2_state_r_reg[3]_i_1 
       (.I0(\cal2_state_r[3]_i_3_n_0 ),
        .I1(\cal2_state_r[3]_i_4_n_0 ),
        .O(\cal2_state_r_reg[3]_i_1_n_0 ),
        .S(\cal2_state_r_reg_n_0_[0] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \corse_cnt[1][2]_i_8 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [2]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [3]),
        .I2(\wl_state_r_reg[4] [1]),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(\wl_state_r_reg[4] [2]),
        .O(\corse_cnt_reg[3][0]_0 ));
  LUT6 #(
    .INIT(64'hF200F2F2F2F2F2F2)) 
    \corse_cnt[3][2]_i_3 
       (.I0(wr_level_done_r5),
        .I1(wrlvl_byte_redo),
        .I2(\dqs_count_r_reg[2]_rep__0 ),
        .I3(\corse_cnt_reg[3][0]_0 ),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I5(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .O(\corse_cnt_reg[3][0] ));
  LUT6 #(
    .INIT(64'hEF00EFEFEFEFEFEF)) 
    \corse_cnt[6][2]_i_3 
       (.I0(\corse_cnt_reg[7][0] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .I3(wr_level_done_r5_reg),
        .I4(\dqs_count_r_reg[2]_rep ),
        .I5(\dqs_count_r_reg[1] ),
        .O(\corse_cnt_reg[6][0] ));
  LUT6 #(
    .INIT(64'hFFFFFFEFFFFFFFFF)) 
    \corse_cnt[7][2]_i_4 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [3]),
        .I1(\wl_state_r_reg[4] [1]),
        .I2(wrlvl_byte_redo),
        .I3(wrlvl_byte_redo_r),
        .I4(\wl_state_r_reg[4] [2]),
        .I5(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [2]),
        .O(\corse_cnt_reg[7][0] ));
  LUT4 #(
    .INIT(16'h2F20)) 
    early1_data_i_1
       (.I0(early1_data_match_r),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(early1_data_i_2_n_0),
        .I3(early1_data),
        .O(early1_data_i_1_n_0));
  LUT5 #(
    .INIT(32'h45400000)) 
    early1_data_i_2
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(early1_data_i_3_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo_i_3_n_0),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .O(early1_data_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    early1_data_i_3
       (.I0(wrlvl_byte_done),
        .I1(rd_active_r1),
        .I2(rd_active_r),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .O(early1_data_i_3_n_0));
  FDRE early1_data_reg
       (.C(CLK),
        .CE(1'b1),
        .D(early1_data_i_1_n_0),
        .Q(early1_data),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    early2_data_i_1
       (.I0(early1_data_match_r),
        .I1(early2_data_match_r),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(early1_data_i_2_n_0),
        .I4(early2_data),
        .O(early2_data_i_1_n_0));
  FDRE early2_data_reg
       (.C(CLK),
        .CE(1'b1),
        .D(early2_data_i_1_n_0),
        .Q(early2_data),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    \gen_byte_sel_div2.byte_sel_cnt[0]_i_1 
       (.I0(wrcal_done_reg_0),
        .I1(wr_level_done_reg),
        .I2(rdlvl_stg1_done_reg),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I4(rdlvl_stg1_done_reg_2),
        .O(D[0]));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_1 
       (.I0(wrcal_done_reg_0),
        .I1(wr_level_done_reg),
        .I2(rdlvl_stg1_done_reg),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .I4(rdlvl_stg1_done_reg_1),
        .O(D[1]));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    \gen_byte_sel_div2.byte_sel_cnt[2]_i_1 
       (.I0(wrcal_done_reg_0),
        .I1(wr_level_done_reg),
        .I2(rdlvl_stg1_done_reg),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [2]),
        .I4(\dqs_count_r_reg[2]_rep__0_0 ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_3 
       (.I0(wrcal_done_reg_0),
        .I1(wr_level_done_reg),
        .I2(rdlvl_stg1_done_reg),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [3]),
        .I4(rdlvl_stg1_done_reg_0),
        .O(D[3]));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_15 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_55 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_31 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_7 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_47 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_out),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_23 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_39 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_16 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_56 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_32 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_8 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_48 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_24 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_40 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_17 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_57 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_33 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_9 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_49 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_1 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_25 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_41 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_18 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_58 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_34 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_10 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_50 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_2 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_26 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_42 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_19 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_59 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_35 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_11 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_51 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_3 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_27 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_43 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_20 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_60 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_36 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_12 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_52 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_4 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_28 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_44 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_21 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_61 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_37 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_13 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_53 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_5 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_29 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_45 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_22 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_62 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_38 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_14 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_54 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_6 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_30 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\po_stg2_wrcal_cnt_reg[0]_46 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.early1_data_match_r_i_1 
       (.I0(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ),
        .I1(early1_match_fall1_and_r),
        .I2(early1_match_rise1_and_r),
        .O(early1_data_match_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.early1_data_match_r_i_2 
       (.I0(early1_match_rise3_and_r),
        .I1(early1_match_rise2_and_r),
        .I2(early1_match_rise0_and_r),
        .I3(early1_match_fall3_and_r),
        .I4(early1_match_fall0_and_r),
        .I5(early1_match_fall2_and_r),
        .O(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(early1_data_match_r0),
        .Q(early1_data_match_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_match_fall0_and_r_i_1 
       (.I0(early1_match_fall0_r[0]),
        .I1(early1_match_fall0_r[6]),
        .I2(early1_match_fall0_r[2]),
        .I3(early1_match_fall0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_match_fall0_and_r_i_2 
       (.I0(pat_match_fall0_r[7]),
        .I1(pat_match_fall0_r[1]),
        .I2(pat_match_fall0_r[5]),
        .I3(pat_match_fall0_r[3]),
        .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ),
        .Q(early1_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ),
        .I1(early1_match_fall1_r[2]),
        .I2(early1_match_fall1_r[6]),
        .I3(early1_match_fall1_r[3]),
        .I4(early1_match_fall1_r[7]),
        .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall1_and_r_i_2 
       (.I0(early1_match_fall1_r[4]),
        .I1(early1_match_fall1_r[1]),
        .I2(early1_match_fall1_r[5]),
        .I3(early1_match_fall1_r[0]),
        .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ),
        .Q(early1_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),
        .I1(early1_match_fall2_r[2]),
        .I2(early1_match_fall2_r[6]),
        .I3(early1_match_fall2_r[3]),
        .I4(early1_match_fall2_r[7]),
        .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall2_and_r_i_2 
       (.I0(pat_match_fall2_r[4]),
        .I1(pat_match_fall2_r[1]),
        .I2(pat_match_fall2_r[5]),
        .I3(pat_match_fall2_r[0]),
        .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ),
        .Q(early1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ),
        .I1(early1_match_fall3_r[0]),
        .I2(early1_match_fall3_r[6]),
        .I3(early1_match_fall3_r[2]),
        .I4(early1_match_fall3_r[4]),
        .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall3_and_r_i_2 
       (.I0(early1_match_fall3_r[5]),
        .I1(early1_match_fall3_r[1]),
        .I2(pat_match_fall3_r[7]),
        .I3(pat_match_fall3_r[3]),
        .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ),
        .Q(early1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_match_rise0_and_r_i_1 
       (.I0(early1_match_rise0_r[0]),
        .I1(early1_match_rise0_r[6]),
        .I2(early1_match_rise0_r[2]),
        .I3(early1_match_rise0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_match_rise0_and_r_i_2 
       (.I0(pat_match_rise0_r[7]),
        .I1(pat_match_rise0_r[1]),
        .I2(pat_match_rise0_r[5]),
        .I3(pat_match_rise0_r[3]),
        .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ),
        .Q(early1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ),
        .I1(early1_match_rise1_r[2]),
        .I2(early1_match_rise1_r[6]),
        .I3(early1_match_rise1_r[3]),
        .I4(early1_match_rise1_r[7]),
        .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise1_and_r_i_2 
       (.I0(early1_match_rise1_r[4]),
        .I1(early1_match_rise1_r[1]),
        .I2(early1_match_rise1_r[5]),
        .I3(early1_match_rise1_r[0]),
        .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ),
        .Q(early1_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise2_and_r_i_1 
       (.I0(early1_match_rise2_r[3]),
        .I1(early1_match_rise2_r[2]),
        .I2(early1_match_rise2_r[6]),
        .I3(early1_match_rise2_r[7]),
        .I4(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise2_and_r_i_2 
       (.I0(pat_match_rise2_r[4]),
        .I1(pat_match_rise2_r[0]),
        .I2(pat_match_rise2_r[5]),
        .I3(pat_match_rise2_r[1]),
        .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ),
        .Q(early1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),
        .I1(early1_match_rise3_r[1]),
        .I2(early1_match_rise3_r[5]),
        .I3(pat_match_rise3_r[0]),
        .I4(pat_match_rise3_r[4]),
        .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise3_and_r_i_2 
       (.I0(pat_match_rise3_r[7]),
        .I1(pat_match_rise3_r[3]),
        .I2(pat_match_rise3_r[6]),
        .I3(pat_match_rise3_r[2]),
        .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ),
        .Q(early1_match_rise3_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.early2_data_match_r_i_1 
       (.I0(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ),
        .I1(early2_match_fall3_and_r),
        .I2(early2_match_rise1_and_r),
        .O(early2_data_match_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.early2_data_match_r_i_2 
       (.I0(early2_match_rise2_and_r),
        .I1(early2_match_fall0_and_r),
        .I2(early2_match_rise3_and_r),
        .I3(early2_match_fall2_and_r),
        .I4(early2_match_fall1_and_r),
        .I5(early2_match_rise0_and_r),
        .O(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(early2_data_match_r0),
        .Q(early2_data_match_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ),
        .I1(early2_match_fall0_r[1]),
        .I2(early2_match_fall0_r[7]),
        .I3(early2_match_fall0_r[3]),
        .I4(early2_match_fall0_r[5]),
        .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall0_and_r_i_2 
       (.I0(pat_match_fall0_r[4]),
        .I1(pat_match_fall0_r[2]),
        .I2(pat_match_fall0_r[6]),
        .I3(pat_match_fall0_r[0]),
        .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ),
        .Q(early2_match_fall0_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall1_and_r_i_1 
       (.I0(early1_match_fall1_r[0]),
        .I1(early1_match_fall1_r[5]),
        .I2(early1_match_fall1_r[1]),
        .I3(early1_match_fall1_r[4]),
        .I4(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall1_and_r_i_2 
       (.I0(pat_match_fall1_r[7]),
        .I1(pat_match_fall1_r[3]),
        .I2(pat_match_fall1_r[6]),
        .I3(pat_match_fall1_r[2]),
        .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ),
        .Q(early2_match_fall1_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.early2_match_fall2_and_r_i_1 
       (.I0(early2_match_fall2_r[4]),
        .I1(early1_match_fall2_r[3]),
        .I2(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.early2_match_fall2_and_r_i_2 
       (.I0(early2_match_fall2_r[5]),
        .I1(pat_match_fall2_r[2]),
        .I2(early2_match_fall2_r[0]),
        .I3(pat_match_fall2_r[6]),
        .I4(early2_match_fall2_r[1]),
        .I5(early1_match_fall2_r[7]),
        .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ),
        .Q(early2_match_fall2_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall3_and_r_i_1 
       (.I0(pat_match_fall3_r[3]),
        .I1(pat_match_fall3_r[7]),
        .I2(early1_match_fall3_r[1]),
        .I3(early1_match_fall3_r[5]),
        .I4(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall3_and_r_i_2 
       (.I0(pat_match_fall3_r[4]),
        .I1(pat_match_fall3_r[2]),
        .I2(pat_match_fall3_r[0]),
        .I3(pat_match_fall3_r[6]),
        .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ),
        .Q(early2_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ),
        .I1(early2_match_rise0_r[1]),
        .I2(early2_match_rise0_r[7]),
        .I3(early2_match_rise0_r[3]),
        .I4(early2_match_rise0_r[5]),
        .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise0_and_r_i_2 
       (.I0(pat_match_rise0_r[4]),
        .I1(pat_match_rise0_r[2]),
        .I2(pat_match_rise0_r[6]),
        .I3(pat_match_rise0_r[0]),
        .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ),
        .Q(early2_match_rise0_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise1_and_r_i_1 
       (.I0(early1_match_rise1_r[0]),
        .I1(early1_match_rise1_r[5]),
        .I2(early1_match_rise1_r[1]),
        .I3(early1_match_rise1_r[4]),
        .I4(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise1_and_r_i_2 
       (.I0(pat_match_rise1_r[7]),
        .I1(pat_match_rise1_r[3]),
        .I2(pat_match_rise1_r[6]),
        .I3(pat_match_rise1_r[2]),
        .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ),
        .Q(early2_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ),
        .I1(pat_match_rise2_r[0]),
        .I2(pat_match_rise2_r[4]),
        .I3(early2_match_rise2_r[1]),
        .I4(early2_match_rise2_r[5]),
        .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise2_and_r_i_2 
       (.I0(early1_match_rise2_r[7]),
        .I1(early1_match_rise2_r[6]),
        .I2(early1_match_rise2_r[2]),
        .I3(early1_match_rise2_r[3]),
        .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ),
        .Q(early2_match_rise2_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.early2_match_rise3_and_r_i_1 
       (.I0(early2_match_rise3_r[0]),
        .I1(pat_match_rise3_r[3]),
        .I2(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.early2_match_rise3_and_r_i_2 
       (.I0(early1_match_rise3_r[1]),
        .I1(early2_match_rise3_r[2]),
        .I2(early2_match_rise3_r[6]),
        .I3(early1_match_rise3_r[5]),
        .I4(pat_match_rise3_r[7]),
        .I5(early2_match_rise3_r[4]),
        .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ),
        .Q(early2_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_23 ),
        .Q(early1_match_fall0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_63 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ),
        .Q(early1_match_fall1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_15 ),
        .Q(early1_match_fall3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_55 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ),
        .Q(early1_match_rise0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_7 ),
        .Q(early1_match_rise1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_39 ),
        .Q(early2_match_fall2_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_47 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ),
        .Q(early2_match_rise3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_23 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ),
        .Q(pat_match_fall0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_63 ),
        .Q(pat_match_fall1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_39 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ),
        .Q(pat_match_fall2_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_15 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ),
        .Q(pat_match_fall3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_55 ),
        .Q(pat_match_rise0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_7 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ),
        .Q(pat_match_rise1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_31 ),
        .Q(pat_match_rise2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_47 ),
        .Q(pat_match_rise3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_64 ),
        .Q(early1_match_fall1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_16 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ),
        .Q(early1_match_fall3_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_8 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ),
        .Q(early1_match_rise1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_48 ),
        .Q(early1_match_rise3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_24 ),
        .Q(early2_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_40 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ),
        .Q(early2_match_fall2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_56 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ),
        .Q(early2_match_rise0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_32 ),
        .Q(early2_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_24 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ),
        .Q(pat_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_64 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ),
        .Q(pat_match_fall1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_40 ),
        .Q(pat_match_fall2_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_16 ),
        .Q(pat_match_fall3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_56 ),
        .Q(pat_match_rise0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_8 ),
        .Q(pat_match_rise1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_32 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ),
        .Q(pat_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_48 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ),
        .Q(pat_match_rise3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_25 ),
        .Q(early1_match_fall0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_65 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ),
        .Q(early1_match_fall1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_41 ),
        .Q(early1_match_fall2_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_17 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ),
        .Q(early1_match_fall3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_57 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ),
        .Q(early1_match_rise0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_9 ),
        .Q(early1_match_rise1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_33 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ),
        .Q(early1_match_rise2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_49 ),
        .Q(early2_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_25 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ),
        .Q(pat_match_fall0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_65 ),
        .Q(pat_match_fall1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_41 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ),
        .Q(pat_match_fall2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_17 ),
        .Q(pat_match_fall3_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_57 ),
        .Q(pat_match_rise0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_9 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ),
        .Q(pat_match_rise1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_33 ),
        .Q(pat_match_rise2_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_49 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ),
        .Q(pat_match_rise3_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_66 ),
        .Q(early1_match_fall1_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_42 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ),
        .Q(early1_match_fall2_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_10 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ),
        .Q(early1_match_rise1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_34 ),
        .Q(early1_match_rise2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_26 ),
        .Q(early2_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_58 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ),
        .Q(early2_match_rise0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_26 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ),
        .Q(pat_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_66 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ),
        .Q(pat_match_fall1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_42 ),
        .Q(pat_match_fall2_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_18 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ),
        .Q(pat_match_fall3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_58 ),
        .Q(pat_match_rise0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_10 ),
        .Q(pat_match_rise1_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_34 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ),
        .Q(pat_match_rise2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_50 ),
        .Q(pat_match_rise3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_27 ),
        .Q(early1_match_fall0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_67 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ),
        .Q(early1_match_fall1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_19 ),
        .Q(early1_match_fall3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_59 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ),
        .Q(early1_match_rise0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_11 ),
        .Q(early1_match_rise1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_43 ),
        .Q(early2_match_fall2_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_51 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ),
        .Q(early2_match_rise3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_27 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ),
        .Q(pat_match_fall0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_67 ),
        .Q(pat_match_fall1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_43 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ),
        .Q(pat_match_fall2_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_19 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ),
        .Q(pat_match_fall3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_59 ),
        .Q(pat_match_rise0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_11 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ),
        .Q(pat_match_rise1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_35 ),
        .Q(pat_match_rise2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_51 ),
        .Q(pat_match_rise3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_68 ),
        .Q(early1_match_fall1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_20 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ),
        .Q(early1_match_fall3_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_12 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ),
        .Q(early1_match_rise1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_52 ),
        .Q(early1_match_rise3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_28 ),
        .Q(early2_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_44 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ),
        .Q(early2_match_fall2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_60 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ),
        .Q(early2_match_rise0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_36 ),
        .Q(early2_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_28 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ),
        .Q(pat_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_68 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ),
        .Q(pat_match_fall1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_44 ),
        .Q(pat_match_fall2_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_20 ),
        .Q(pat_match_fall3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_60 ),
        .Q(pat_match_rise0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_12 ),
        .Q(pat_match_rise1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_36 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ),
        .Q(pat_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_52 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ),
        .Q(pat_match_rise3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_29 ),
        .Q(early1_match_fall0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_69 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ),
        .Q(early1_match_fall1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_45 ),
        .Q(early1_match_fall2_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_21 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ),
        .Q(early1_match_fall3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_61 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ),
        .Q(early1_match_rise0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_13 ),
        .Q(early1_match_rise1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_37 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ),
        .Q(early1_match_rise2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_53 ),
        .Q(early2_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_29 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ),
        .Q(pat_match_fall0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_69 ),
        .Q(pat_match_fall1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_45 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ),
        .Q(pat_match_fall2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_21 ),
        .Q(pat_match_fall3_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_61 ),
        .Q(pat_match_rise0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_13 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ),
        .Q(pat_match_rise1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_37 ),
        .Q(pat_match_rise2_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_53 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ),
        .Q(pat_match_rise3_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_70 ),
        .Q(early1_match_fall1_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_46 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ),
        .Q(early1_match_fall2_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_14 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ),
        .Q(early1_match_rise1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_38 ),
        .Q(early1_match_rise2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_30 ),
        .Q(early2_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_62 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ),
        .Q(early2_match_rise0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_30 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ),
        .Q(pat_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_70 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ),
        .Q(pat_match_fall1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_46 ),
        .Q(pat_match_fall2_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_22 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ),
        .Q(pat_match_fall3_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_62 ),
        .Q(pat_match_rise0_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_14 ),
        .Q(pat_match_rise1_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_38 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ),
        .Q(pat_match_rise2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_54 ),
        .Q(pat_match_rise3_r[7]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat_data_match_r_i_1 
       (.I0(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ),
        .I1(pat_match_fall2_and_r),
        .I2(pat_match_fall3_and_r),
        .O(pat_data_match_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat_data_match_r_i_2 
       (.I0(pat_match_rise3_and_r),
        .I1(pat_match_rise0_and_r),
        .I2(pat_match_fall0_and_r),
        .I3(pat_match_rise2_and_r),
        .I4(pat_match_rise1_and_r),
        .I5(pat_match_fall1_and_r),
        .O(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pat_data_match_r0),
        .Q(pat_data_match_r),
        .R(1'b0));
  FDRE \gen_pat_match_div4.pat_data_match_valid_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_active_r3_reg_srl2_n_0),
        .Q(pat_data_match_valid_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_match_fall0_and_r_i_1 
       (.I0(pat_match_fall0_r[0]),
        .I1(pat_match_fall0_r[6]),
        .I2(pat_match_fall0_r[2]),
        .I3(pat_match_fall0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ),
        .Q(pat_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),
        .I1(pat_match_fall1_r[0]),
        .I2(pat_match_fall1_r[5]),
        .I3(pat_match_fall1_r[1]),
        .I4(pat_match_fall1_r[4]),
        .O(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ),
        .Q(pat_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),
        .I1(pat_match_fall2_r[3]),
        .I2(pat_match_fall2_r[7]),
        .I3(pat_match_fall2_r[2]),
        .I4(pat_match_fall2_r[6]),
        .O(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ),
        .Q(pat_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),
        .I1(pat_match_fall3_r[1]),
        .I2(pat_match_fall3_r[5]),
        .I3(pat_match_fall3_r[3]),
        .I4(pat_match_fall3_r[7]),
        .O(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ),
        .Q(pat_match_fall3_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_match_rise0_and_r_i_1 
       (.I0(pat_match_rise0_r[0]),
        .I1(pat_match_rise0_r[6]),
        .I2(pat_match_rise0_r[2]),
        .I3(pat_match_rise0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ),
        .Q(pat_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),
        .I1(pat_match_rise1_r[0]),
        .I2(pat_match_rise1_r[5]),
        .I3(pat_match_rise1_r[1]),
        .I4(pat_match_rise1_r[4]),
        .O(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ),
        .Q(pat_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),
        .I1(pat_match_rise2_r[2]),
        .I2(pat_match_rise2_r[6]),
        .I3(pat_match_rise2_r[3]),
        .I4(pat_match_rise2_r[7]),
        .O(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ),
        .Q(pat_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),
        .I1(pat_match_rise3_r[1]),
        .I2(pat_match_rise3_r[5]),
        .I3(pat_match_rise3_r[0]),
        .I4(pat_match_rise3_r[4]),
        .O(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ),
        .Q(pat_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_23 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_63 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_39 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_15 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_55 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_7 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_31 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_47 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_24 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_64 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_40 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_16 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_56 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_8 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_32 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_48 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_25 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_65 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_41 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_17 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_57 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_9 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_33 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_49 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_26 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_66 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_42 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_18 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_58 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_10 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_34 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_50 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_27 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_67 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_43 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_19 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_59 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_11 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_35 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_51 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_28 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_68 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_44 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_20 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_60 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_12 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_36 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_52 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_29 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_69 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_45 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_21 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_61 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_13 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_37 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_53 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_30 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_70 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_46 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_22 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_62 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_14 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_38 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_54 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFCFF00000080)) 
    idelay_ld_done_i_1
       (.I0(idelay_ld_done_i_2_n_0),
        .I1(\cal2_state_r_reg_n_0_[0] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .I5(idelay_ld_done_reg_n_0),
        .O(idelay_ld_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    idelay_ld_done_i_2
       (.I0(tap_inc_wait_cnt_reg__0[3]),
        .I1(tap_inc_wait_cnt_reg__0[0]),
        .I2(tap_inc_wait_cnt_reg__0[1]),
        .I3(tap_inc_wait_cnt_reg__0[2]),
        .O(idelay_ld_done_i_2_n_0));
  FDRE idelay_ld_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_done_i_1_n_0),
        .Q(idelay_ld_done_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT4 #(
    .INIT(16'h2F20)) 
    idelay_ld_i_1
       (.I0(pat_data_match_valid_r),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(idelay_ld_i_2_n_0),
        .I3(idelay_ld),
        .O(idelay_ld_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000540400000000)) 
    idelay_ld_i_2
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r[2]_i_2_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(idelay_ld_done_i_2_n_0),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(\cal2_state_r_reg_n_0_[0] ),
        .O(idelay_ld_i_2_n_0));
  FDRE idelay_ld_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_i_1_n_0),
        .Q(idelay_ld),
        .R(rstdiv0_sync_r1_reg_rep__3));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \idelay_tap_cnt_r[0][0][4]_i_3 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .O(\idelay_tap_cnt_r_reg[0][0][0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \idelay_tap_cnt_r[0][0][4]_i_4 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [2]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [3]),
        .I2(idelay_ld),
        .I3(idelay_ce_int),
        .O(\idelay_tap_cnt_r_reg[0][0][0] ));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \idelay_tap_cnt_r[0][1][4]_i_3 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .O(\idelay_tap_cnt_r_reg[0][1][0] ));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \idelay_tap_cnt_r[0][2][4]_i_2 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .O(\idelay_tap_cnt_r_reg[0][2][0] ));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \idelay_tap_cnt_r[0][3][4]_i_2 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .O(\idelay_tap_cnt_r_reg[0][3][0] ));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT4 #(
    .INIT(16'hFBFF)) 
    \idelay_tap_cnt_r[0][4][4]_i_2 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [3]),
        .I1(idelay_ld),
        .I2(idelay_ce_int),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [2]),
        .O(\idelay_tap_cnt_r_reg[0][7][4] ));
  LUT6 #(
    .INIT(64'hFFFFFFFF4040FF40)) 
    \idelay_tap_cnt_r[0][7][4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][7][4] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .I3(\cal1_cnt_cpt_r_reg[0] ),
        .I4(\rnk_cnt_r_reg[0] ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \init_state_r[2]_i_31 
       (.I0(wrcal_done_reg_0),
        .I1(wrlvl_byte_redo),
        .I2(mem_init_done_r),
        .O(\init_state_r_reg[2] ));
  LUT6 #(
    .INIT(64'h4555555555555555)) 
    \init_state_r[3]_i_20 
       (.I0(wrcal_sanity_chk_done),
        .I1(ddr3_lm_done_r),
        .I2(dqs_found_done_r_reg),
        .I3(rdlvl_stg1_done_reg),
        .I4(wrlvl_done_r1),
        .I5(wrcal_done_reg_0),
        .O(\init_state_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[5]_i_35 
       (.I0(wrlvl_byte_redo),
        .I1(wrcal_done_reg_0),
        .I2(prech_req_posedge_r_reg),
        .O(\init_state_r_reg[5] ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000AB00)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [1]),
        .I5(idelay_ld_rst_5),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000AB00)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2__0 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [0]),
        .I5(idelay_ld_rst),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000AB00)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2__1 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [2]),
        .I5(idelay_ld_rst_6),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000BA00)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [0]),
        .I5(idelay_ld_rst_2),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000BA00)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__0 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [0]),
        .I5(idelay_ld_rst_3),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000EA00)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__1 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [0]),
        .I5(idelay_ld_rst_4),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000BA00)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__2 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [2]),
        .I5(idelay_ld_rst_7),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000BA00)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__3 
       (.I0(\gen_byte_sel_div2.calib_in_common_reg ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(idelay_ld),
        .I4(\calib_zero_inputs_reg[2] [2]),
        .I5(idelay_ld_rst_8),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \not_empty_wait_cnt[0]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[0] ),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_empty_wait_cnt[1]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[0] ),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_empty_wait_cnt[2]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[2] ),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \not_empty_wait_cnt[3]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[3] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[1] ),
        .O(p_0_in[3]));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \not_empty_wait_cnt[4]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__22),
        .I1(\cal2_state_r_reg_n_0_[3] ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrcal_rd_wait),
        .O(\not_empty_wait_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \not_empty_wait_cnt[4]_i_2 
       (.I0(\not_empty_wait_cnt_reg_n_0_[4] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I4(\not_empty_wait_cnt_reg_n_0_[3] ),
        .O(p_0_in[4]));
  FDRE \not_empty_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\not_empty_wait_cnt_reg_n_0_[0] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\not_empty_wait_cnt_reg_n_0_[1] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\not_empty_wait_cnt_reg_n_0_[2] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(\not_empty_wait_cnt_reg_n_0_[3] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(\not_empty_wait_cnt_reg_n_0_[4] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \po_stg2_wrcal_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_dqs_cnt_r[0]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [0]),
        .R(1'b0));
  FDRE \po_stg2_wrcal_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_dqs_cnt_r[1]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [1]),
        .R(1'b0));
  FDRE \po_stg2_wrcal_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_dqs_cnt_r[2]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [2]),
        .R(1'b0));
  FDRE \po_stg2_wrcal_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_dqs_cnt_r[3]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg[3] [3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFEEE)) 
    prech_req_r_i_1
       (.I0(wrcal_prech_req),
        .I1(rdlvl_prech_req),
        .I2(dqs_found_prech_req),
        .I3(\init_state_r_reg[5]_0 ),
        .O(prech_req));
  FDRE rd_active_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_active_r),
        .Q(rd_active_r1),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3_reg_srl2 " *) 
  SRL16E rd_active_r3_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(rd_active_r1),
        .Q(rd_active_r3_reg_srl2_n_0));
  FDRE rd_active_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_rddata_en),
        .Q(rd_active_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \single_rank.done_dqs_dec_i_2 
       (.I0(wrlvl_byte_redo),
        .I1(wrlvl_byte_redo_r),
        .O(wr_level_done0));
  LUT1 #(
    .INIT(2'h1)) 
    \tap_inc_wait_cnt[0]_i_1 
       (.I0(tap_inc_wait_cnt_reg__0[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \tap_inc_wait_cnt[1]_i_1 
       (.I0(tap_inc_wait_cnt_reg__0[1]),
        .I1(tap_inc_wait_cnt_reg__0[0]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \tap_inc_wait_cnt[2]_i_1 
       (.I0(tap_inc_wait_cnt_reg__0[2]),
        .I1(tap_inc_wait_cnt_reg__0[1]),
        .I2(tap_inc_wait_cnt_reg__0[0]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hFFFFAFEF)) 
    \tap_inc_wait_cnt[3]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[0] ),
        .I4(rstdiv0_sync_r1_reg_rep__22),
        .O(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \tap_inc_wait_cnt[3]_i_2 
       (.I0(tap_inc_wait_cnt_reg__0[1]),
        .I1(tap_inc_wait_cnt_reg__0[0]),
        .I2(tap_inc_wait_cnt_reg__0[2]),
        .I3(tap_inc_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  FDRE \tap_inc_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(tap_inc_wait_cnt_reg__0[0]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(tap_inc_wait_cnt_reg__0[1]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(tap_inc_wait_cnt_reg__0[2]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(tap_inc_wait_cnt_reg__0[3]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \wl_state_r[2]_i_10 
       (.I0(wrlvl_byte_redo),
        .I1(wr_level_done_r5),
        .I2(wl_sm_start),
        .O(\wl_state_r_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wl_state_r[2]_i_13 
       (.I0(wrlvl_byte_redo),
        .I1(\wl_state_r_reg[4] [0]),
        .O(\wl_state_r_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wl_state_r[4]_i_12 
       (.I0(wrlvl_byte_redo),
        .I1(wl_sm_start),
        .O(\wl_state_r_reg[0] ));
  LUT5 #(
    .INIT(32'h0E0E000E)) 
    wrcal_done_i_1
       (.I0(wrcal_done_reg_0),
        .I1(cal2_done_r),
        .I2(rstdiv0_sync_r1_reg_rep__22),
        .I3(wrcal_sanity_chk),
        .I4(wrcal_sanity_chk_r),
        .O(wrcal_done_i_1_n_0));
  FDRE wrcal_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_done_i_1_n_0),
        .Q(wrcal_done_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wrcal_dqs_cnt_r[0]_i_1 
       (.I0(wrcal_dqs_cnt_r[0]),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \wrcal_dqs_cnt_r[1]_i_1 
       (.I0(wrcal_dqs_cnt_r[1]),
        .I1(wrcal_dqs_cnt_r[0]),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT4 #(
    .INIT(16'h0078)) 
    \wrcal_dqs_cnt_r[2]_i_1 
       (.I0(wrcal_dqs_cnt_r[1]),
        .I1(wrcal_dqs_cnt_r[0]),
        .I2(wrcal_dqs_cnt_r[2]),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000054040000)) 
    \wrcal_dqs_cnt_r[3]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\wrcal_dqs_cnt_r[3]_i_3_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(wrcal_sanity_chk_reg),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(\cal2_state_r_reg_n_0_[0] ),
        .O(\wrcal_dqs_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT5 #(
    .INIT(32'h00007F80)) 
    \wrcal_dqs_cnt_r[3]_i_2 
       (.I0(wrcal_dqs_cnt_r[2]),
        .I1(wrcal_dqs_cnt_r[1]),
        .I2(wrcal_dqs_cnt_r[0]),
        .I3(wrcal_dqs_cnt_r[3]),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFFFFFFF8AAAAAAA)) 
    \wrcal_dqs_cnt_r[3]_i_3 
       (.I0(prech_done),
        .I1(wrcal_dqs_cnt_r[3]),
        .I2(wrcal_dqs_cnt_r[1]),
        .I3(wrcal_dqs_cnt_r[0]),
        .I4(wrcal_dqs_cnt_r[2]),
        .I5(wrcal_sanity_chk_r),
        .O(\wrcal_dqs_cnt_r[3]_i_3_n_0 ));
  FDRE \wrcal_dqs_cnt_r_reg[0] 
       (.C(CLK),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[0]_i_1_n_0 ),
        .Q(wrcal_dqs_cnt_r[0]),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \wrcal_dqs_cnt_r_reg[1] 
       (.C(CLK),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[1]_i_1_n_0 ),
        .Q(wrcal_dqs_cnt_r[1]),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \wrcal_dqs_cnt_r_reg[2] 
       (.C(CLK),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[2]_i_1_n_0 ),
        .Q(wrcal_dqs_cnt_r[2]),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE \wrcal_dqs_cnt_r_reg[3] 
       (.C(CLK),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[3]_i_2_n_0 ),
        .Q(wrcal_dqs_cnt_r[3]),
        .R(rstdiv0_sync_r1_reg_rep__3));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 " *) 
  SRL16E wrcal_pat_resume_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(wrcal_pat_resume_r),
        .Q(wrcal_pat_resume_r2_reg_srl2_n_0));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    wrcal_pat_resume_r_i_1
       (.I0(\cal2_state_r_reg_n_0_[2] ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrcal_pat_resume_r_i_2_n_0),
        .I4(wrcal_pat_resume_r),
        .O(wrcal_pat_resume_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0003B33F0003800C)) 
    wrcal_pat_resume_r_i_2
       (.I0(\cal2_state_r[3]_i_7_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[0] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .I5(wrcal_pat_resume_r_i_3_n_0),
        .O(wrcal_pat_resume_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000400000000000)) 
    wrcal_pat_resume_r_i_3
       (.I0(wrcal_sanity_chk_r),
        .I1(idelay_ld_done_reg_n_0),
        .I2(tap_inc_wait_cnt_reg__0[2]),
        .I3(tap_inc_wait_cnt_reg__0[3]),
        .I4(wrcal_pat_resume_r_i_4_n_0),
        .I5(wrcal_pat_resume_r_i_5_n_0),
        .O(wrcal_pat_resume_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT2 #(
    .INIT(4'hB)) 
    wrcal_pat_resume_r_i_4
       (.I0(\cal2_state_r_reg_n_0_[1] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .O(wrcal_pat_resume_r_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT2 #(
    .INIT(4'h8)) 
    wrcal_pat_resume_r_i_5
       (.I0(tap_inc_wait_cnt_reg__0[0]),
        .I1(tap_inc_wait_cnt_reg__0[1]),
        .O(wrcal_pat_resume_r_i_5_n_0));
  FDRE wrcal_pat_resume_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_pat_resume_r_i_1_n_0),
        .Q(wrcal_pat_resume_r),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE wrcal_pat_resume_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_pat_resume_r2_reg_srl2_n_0),
        .Q(wrcal_resume_w),
        .R(1'b0));
  FDRE wrcal_prech_req_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_prech_req_r),
        .Q(wrcal_prech_req),
        .R(rstdiv0_sync_r1_reg_rep__3));
  LUT6 #(
    .INIT(64'hFFFFFFFF00004000)) 
    wrcal_sanity_chk_done_i_1
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(wrcal_sanity_chk_r),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrcal_sanity_chk_done),
        .O(wrcal_sanity_chk_done_i_1_n_0));
  FDRE wrcal_sanity_chk_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_sanity_chk_done_i_1_n_0),
        .Q(wrcal_sanity_chk_done),
        .R(rstdiv0_sync_r1_reg_rep__3));
  FDRE wrcal_sanity_chk_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_sanity_chk),
        .Q(wrcal_sanity_chk_r),
        .R(1'b0));
  FDRE wrlvl_byte_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_done),
        .Q(wrlvl_byte_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0EFFFFFF0E000000)) 
    wrlvl_byte_redo_i_1
       (.I0(early2_data_match_r),
        .I1(early1_data_match_r),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo_i_2_n_0),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrlvl_byte_redo),
        .O(wrlvl_byte_redo_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000022222E22)) 
    wrlvl_byte_redo_i_2
       (.I0(wrlvl_byte_redo_i_3_n_0),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(wrlvl_byte_done),
        .I4(wrlvl_byte_done_r),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(wrlvl_byte_redo_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000011100000)) 
    wrlvl_byte_redo_i_3
       (.I0(pat_data_match_r),
        .I1(wrcal_sanity_chk_r),
        .I2(early1_data_match_r),
        .I3(early2_data_match_r),
        .I4(pat_data_match_valid_r),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(wrlvl_byte_redo_i_3_n_0));
  FDRE wrlvl_byte_redo_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_redo_i_1_n_0),
        .Q(wrlvl_byte_redo),
        .R(rstdiv0_sync_r1_reg_rep__3));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ddr_phy_wrlvl" *) 
module mig_7series_0_mig_7series_v2_3_ddr_phy_wrlvl
   (wrlvl_byte_redo_r,
    wr_level_done_r5,
    dqs_po_dec_done,
    dqs_po_stg2_f_incdec,
    dqs_po_en_stg2_f,
    dqs_po_en_stg2_f_reg_0,
    wrlvl_done_r_reg,
    wrlvl_rank_done,
    Q,
    \dqs_count_r_reg[3]_0 ,
    \fine_inc_reg[6][0]_0 ,
    \corse_cnt_reg[3][0]_0 ,
    delay_dec_done_reg,
    \smallest_reg[7][0]_0 ,
    \corse_dec_reg[2][0]_0 ,
    \corse_cnt_reg[2][0]_0 ,
    \wl_corse_cnt_reg[0][7][2]_0 ,
    \wl_corse_cnt_reg[0][7][2]_1 ,
    done_dqs_tap_inc,
    D_po_coarse_enable105_out,
    C_po_coarse_enable66_out,
    B_po_coarse_enable27_out,
    A_po_coarse_enable143_out,
    B_po_fine_enable24_out,
    C_po_fine_enable63_out,
    D_po_fine_enable102_out,
    D_po_coarse_enable72_out,
    C_po_coarse_enable46_out,
    B_po_coarse_enable20_out,
    A_po_coarse_enable98_out,
    C_po_coarse_enable43_out,
    B_po_coarse_enable17_out,
    A_po_coarse_enable69_out,
    \gen_byte_sel_div2.calib_in_common_reg ,
    wrlvl_byte_done,
    phy_ctl_ready,
    CLK,
    wrlvl_byte_redo,
    wr_lvl_start_reg,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    rstdiv0_sync_r1_reg_rep__4,
    rstdiv0_sync_r1_reg_rep__18,
    SR,
    rstdiv0_sync_r1_reg_rep__10,
    wl_sm_start,
    wrlvl_byte_redo_reg,
    early1_data,
    ck_po_stg2_f_en,
    cmd_po_en_stg2_f,
    \calib_zero_inputs_reg[2] ,
    pi_fine_dly_dec_done,
    rstdiv0_sync_r1_reg_rep__24,
    \po_counter_read_val_reg[0] ,
    \po_counter_read_val_reg[1] ,
    \po_counter_read_val_reg[2] ,
    \po_counter_read_val_reg[3] ,
    \po_counter_read_val_reg[4] ,
    \po_counter_read_val_reg[5] ,
    \po_counter_read_val_reg[6] ,
    \po_counter_read_val_reg[7] ,
    \po_counter_read_val_reg[8] ,
    \po_stg2_wrcal_cnt_reg[0] ,
    \po_stg2_wrcal_cnt_reg[3] ,
    \po_stg2_wrcal_cnt_reg[0]_0 ,
    wr_level_done_r5_reg_0,
    \po_stg2_wrcal_cnt_reg[3]_0 ,
    wr_level_done0,
    wrlvl_byte_redo_reg_0,
    rstdiv0_sync_r1_reg_rep__23,
    \po_stg2_wrcal_cnt_reg[0]_1 ,
    \po_stg2_wrcal_cnt_reg[0]_2 ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[2] ,
    wrlvl_byte_redo_reg_1,
    early2_data,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    \calib_sel_reg[1] ,
    rdlvl_stg1_done_reg,
    wrcal_done_reg,
    rstdiv0_sync_r1_reg_rep__9,
    rstdiv0_sync_r1_reg_rep__7,
    rstdiv0_sync_r1_reg_rep__6,
    rstdiv0_sync_r1,
    SS);
  output wrlvl_byte_redo_r;
  output wr_level_done_r5;
  output dqs_po_dec_done;
  output dqs_po_stg2_f_incdec;
  output dqs_po_en_stg2_f;
  output dqs_po_en_stg2_f_reg_0;
  output wrlvl_done_r_reg;
  output wrlvl_rank_done;
  output [2:0]Q;
  output [0:0]\dqs_count_r_reg[3]_0 ;
  output \fine_inc_reg[6][0]_0 ;
  output \corse_cnt_reg[3][0]_0 ;
  output delay_dec_done_reg;
  output \smallest_reg[7][0]_0 ;
  output \corse_dec_reg[2][0]_0 ;
  output \corse_cnt_reg[2][0]_0 ;
  output \wl_corse_cnt_reg[0][7][2]_0 ;
  output \wl_corse_cnt_reg[0][7][2]_1 ;
  output done_dqs_tap_inc;
  output D_po_coarse_enable105_out;
  output C_po_coarse_enable66_out;
  output B_po_coarse_enable27_out;
  output A_po_coarse_enable143_out;
  output B_po_fine_enable24_out;
  output C_po_fine_enable63_out;
  output D_po_fine_enable102_out;
  output D_po_coarse_enable72_out;
  output C_po_coarse_enable46_out;
  output B_po_coarse_enable20_out;
  output A_po_coarse_enable98_out;
  output C_po_coarse_enable43_out;
  output B_po_coarse_enable17_out;
  output A_po_coarse_enable69_out;
  output \gen_byte_sel_div2.calib_in_common_reg ;
  output wrlvl_byte_done;
  input phy_ctl_ready;
  input CLK;
  input wrlvl_byte_redo;
  input wr_lvl_start_reg;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  input \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input rstdiv0_sync_r1_reg_rep__4;
  input rstdiv0_sync_r1_reg_rep__18;
  input [0:0]SR;
  input [1:0]rstdiv0_sync_r1_reg_rep__10;
  input wl_sm_start;
  input wrlvl_byte_redo_reg;
  input early1_data;
  input ck_po_stg2_f_en;
  input cmd_po_en_stg2_f;
  input [2:0]\calib_zero_inputs_reg[2] ;
  input pi_fine_dly_dec_done;
  input rstdiv0_sync_r1_reg_rep__24;
  input \po_counter_read_val_reg[0] ;
  input \po_counter_read_val_reg[1] ;
  input \po_counter_read_val_reg[2] ;
  input \po_counter_read_val_reg[3] ;
  input \po_counter_read_val_reg[4] ;
  input \po_counter_read_val_reg[5] ;
  input \po_counter_read_val_reg[6] ;
  input \po_counter_read_val_reg[7] ;
  input \po_counter_read_val_reg[8] ;
  input \po_stg2_wrcal_cnt_reg[0] ;
  input \po_stg2_wrcal_cnt_reg[3] ;
  input \po_stg2_wrcal_cnt_reg[0]_0 ;
  input wr_level_done_r5_reg_0;
  input [3:0]\po_stg2_wrcal_cnt_reg[3]_0 ;
  input wr_level_done0;
  input wrlvl_byte_redo_reg_0;
  input rstdiv0_sync_r1_reg_rep__23;
  input \po_stg2_wrcal_cnt_reg[0]_1 ;
  input \po_stg2_wrcal_cnt_reg[0]_2 ;
  input \po_stg2_wrcal_cnt_reg[1] ;
  input \po_stg2_wrcal_cnt_reg[2] ;
  input wrlvl_byte_redo_reg_1;
  input early2_data;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input [1:0]\calib_sel_reg[1] ;
  input rdlvl_stg1_done_reg;
  input wrcal_done_reg;
  input [0:0]rstdiv0_sync_r1_reg_rep__9;
  input [1:0]rstdiv0_sync_r1_reg_rep__7;
  input [0:0]rstdiv0_sync_r1_reg_rep__6;
  input rstdiv0_sync_r1;
  input [0:0]SS;

  wire A_po_coarse_enable143_out;
  wire A_po_coarse_enable69_out;
  wire A_po_coarse_enable98_out;
  wire B_po_coarse_enable17_out;
  wire B_po_coarse_enable20_out;
  wire B_po_coarse_enable27_out;
  wire B_po_fine_enable24_out;
  wire CLK;
  wire C_po_coarse_enable43_out;
  wire C_po_coarse_enable46_out;
  wire C_po_coarse_enable66_out;
  wire C_po_fine_enable63_out;
  wire D_po_coarse_enable105_out;
  wire D_po_coarse_enable72_out;
  wire D_po_fine_enable102_out;
  wire [2:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire [1:0]\calib_sel_reg[1] ;
  wire [2:0]\calib_zero_inputs_reg[2] ;
  wire ck_po_stg2_f_en;
  wire cmd_po_en_stg2_f;
  wire \corse_cnt[0][0]_i_1_n_0 ;
  wire \corse_cnt[0][1]_i_1_n_0 ;
  wire \corse_cnt[0][2]_i_1_n_0 ;
  wire \corse_cnt[0][2]_i_2_n_0 ;
  wire \corse_cnt[0][2]_i_3_n_0 ;
  wire \corse_cnt[1][0]_i_1_n_0 ;
  wire \corse_cnt[1][0]_i_2_n_0 ;
  wire \corse_cnt[1][0]_i_3_n_0 ;
  wire \corse_cnt[1][0]_i_4_n_0 ;
  wire \corse_cnt[1][0]_i_5_n_0 ;
  wire \corse_cnt[1][1]_i_1_n_0 ;
  wire \corse_cnt[1][1]_i_2_n_0 ;
  wire \corse_cnt[1][1]_i_3_n_0 ;
  wire \corse_cnt[1][1]_i_4_n_0 ;
  wire \corse_cnt[1][1]_i_5_n_0 ;
  wire \corse_cnt[1][2]_i_10_n_0 ;
  wire \corse_cnt[1][2]_i_1_n_0 ;
  wire \corse_cnt[1][2]_i_2_n_0 ;
  wire \corse_cnt[1][2]_i_3_n_0 ;
  wire \corse_cnt[1][2]_i_4_n_0 ;
  wire \corse_cnt[1][2]_i_5_n_0 ;
  wire \corse_cnt[1][2]_i_6_n_0 ;
  wire \corse_cnt[1][2]_i_9_n_0 ;
  wire \corse_cnt[2][0]_i_1_n_0 ;
  wire \corse_cnt[2][1]_i_1_n_0 ;
  wire \corse_cnt[2][2]_i_1_n_0 ;
  wire \corse_cnt[2][2]_i_2_n_0 ;
  wire \corse_cnt[2][2]_i_3_n_0 ;
  wire \corse_cnt[3][0]_i_1_n_0 ;
  wire \corse_cnt[3][1]_i_1_n_0 ;
  wire \corse_cnt[3][2]_i_1_n_0 ;
  wire \corse_cnt[3][2]_i_2_n_0 ;
  wire \corse_cnt[4][0]_i_1_n_0 ;
  wire \corse_cnt[4][1]_i_1_n_0 ;
  wire \corse_cnt[4][2]_i_1_n_0 ;
  wire \corse_cnt[4][2]_i_2_n_0 ;
  wire \corse_cnt[4][2]_i_3_n_0 ;
  wire \corse_cnt[5][0]_i_1_n_0 ;
  wire \corse_cnt[5][1]_i_1_n_0 ;
  wire \corse_cnt[5][2]_i_1_n_0 ;
  wire \corse_cnt[5][2]_i_2_n_0 ;
  wire \corse_cnt[5][2]_i_3_n_0 ;
  wire \corse_cnt[6][0]_i_1_n_0 ;
  wire \corse_cnt[6][1]_i_1_n_0 ;
  wire \corse_cnt[6][2]_i_1_n_0 ;
  wire \corse_cnt[6][2]_i_2_n_0 ;
  wire \corse_cnt[7][0]_i_1_n_0 ;
  wire \corse_cnt[7][1]_i_1_n_0 ;
  wire \corse_cnt[7][2]_i_1_n_0 ;
  wire \corse_cnt[7][2]_i_2_n_0 ;
  wire \corse_cnt[7][2]_i_3_n_0 ;
  wire \corse_cnt[7][2]_i_5_n_0 ;
  wire \corse_cnt_reg[1][2]_i_7_n_0 ;
  wire \corse_cnt_reg[2][0]_0 ;
  wire \corse_cnt_reg[3][0]_0 ;
  wire \corse_cnt_reg_n_0_[0][0] ;
  wire \corse_cnt_reg_n_0_[0][1] ;
  wire \corse_cnt_reg_n_0_[0][2] ;
  wire \corse_cnt_reg_n_0_[1][0] ;
  wire \corse_cnt_reg_n_0_[1][1] ;
  wire \corse_cnt_reg_n_0_[1][2] ;
  wire \corse_cnt_reg_n_0_[2][0] ;
  wire \corse_cnt_reg_n_0_[2][1] ;
  wire \corse_cnt_reg_n_0_[2][2] ;
  wire \corse_cnt_reg_n_0_[3][0] ;
  wire \corse_cnt_reg_n_0_[3][1] ;
  wire \corse_cnt_reg_n_0_[3][2] ;
  wire \corse_cnt_reg_n_0_[4][0] ;
  wire \corse_cnt_reg_n_0_[4][1] ;
  wire \corse_cnt_reg_n_0_[4][2] ;
  wire \corse_cnt_reg_n_0_[5][0] ;
  wire \corse_cnt_reg_n_0_[5][1] ;
  wire \corse_cnt_reg_n_0_[5][2] ;
  wire \corse_cnt_reg_n_0_[6][0] ;
  wire \corse_cnt_reg_n_0_[6][1] ;
  wire \corse_cnt_reg_n_0_[6][2] ;
  wire \corse_cnt_reg_n_0_[7][0] ;
  wire \corse_cnt_reg_n_0_[7][1] ;
  wire \corse_cnt_reg_n_0_[7][2] ;
  wire \corse_dec[0][0]_i_1_n_0 ;
  wire \corse_dec[0][0]_i_2_n_0 ;
  wire \corse_dec[0][0]_i_4_n_0 ;
  wire \corse_dec[0][0]_i_5_n_0 ;
  wire \corse_dec[0][1]_i_1_n_0 ;
  wire \corse_dec[0][1]_i_2_n_0 ;
  wire \corse_dec[0][2]_i_10_n_0 ;
  wire \corse_dec[0][2]_i_11_n_0 ;
  wire \corse_dec[0][2]_i_1_n_0 ;
  wire \corse_dec[0][2]_i_2_n_0 ;
  wire \corse_dec[0][2]_i_3_n_0 ;
  wire \corse_dec[0][2]_i_6_n_0 ;
  wire \corse_dec[0][2]_i_7_n_0 ;
  wire \corse_dec[0][2]_i_8_n_0 ;
  wire \corse_dec[0][2]_i_9_n_0 ;
  wire \corse_dec[1][0]_i_1_n_0 ;
  wire \corse_dec[1][1]_i_1_n_0 ;
  wire \corse_dec[1][2]_i_1_n_0 ;
  wire \corse_dec[1][2]_i_2_n_0 ;
  wire \corse_dec[2][0]_i_1_n_0 ;
  wire \corse_dec[2][1]_i_1_n_0 ;
  wire \corse_dec[2][2]_i_1_n_0 ;
  wire \corse_dec[2][2]_i_2_n_0 ;
  wire \corse_dec[3][0]_i_1_n_0 ;
  wire \corse_dec[3][1]_i_1_n_0 ;
  wire \corse_dec[3][2]_i_1_n_0 ;
  wire \corse_dec[3][2]_i_2_n_0 ;
  wire \corse_dec[3][2]_i_3_n_0 ;
  wire \corse_dec[4][0]_i_1_n_0 ;
  wire \corse_dec[4][1]_i_1_n_0 ;
  wire \corse_dec[4][2]_i_1_n_0 ;
  wire \corse_dec[4][2]_i_2_n_0 ;
  wire \corse_dec[5][0]_i_1_n_0 ;
  wire \corse_dec[5][1]_i_1_n_0 ;
  wire \corse_dec[5][2]_i_1_n_0 ;
  wire \corse_dec[5][2]_i_2_n_0 ;
  wire \corse_dec[6][0]_i_1_n_0 ;
  wire \corse_dec[6][1]_i_1_n_0 ;
  wire \corse_dec[6][2]_i_1_n_0 ;
  wire \corse_dec[6][2]_i_2_n_0 ;
  wire \corse_dec[7][0]_i_1_n_0 ;
  wire \corse_dec[7][1]_i_1_n_0 ;
  wire \corse_dec[7][2]_i_1_n_0 ;
  wire \corse_dec[7][2]_i_2_n_0 ;
  wire \corse_dec_reg[0][0]_i_3_n_0 ;
  wire \corse_dec_reg[0][2]_i_4_n_0 ;
  wire \corse_dec_reg[0][2]_i_5_n_0 ;
  wire [2:0]\corse_dec_reg[0]__0 ;
  wire [2:0]\corse_dec_reg[1]__0 ;
  wire \corse_dec_reg[2][0]_0 ;
  wire [2:0]\corse_dec_reg[2]__0 ;
  wire [2:0]\corse_dec_reg[3]__0 ;
  wire [2:0]\corse_dec_reg[4]__0 ;
  wire [2:0]\corse_dec_reg[5]__0 ;
  wire [2:0]\corse_dec_reg[6]__0 ;
  wire [2:0]\corse_dec_reg[7]__0 ;
  wire \corse_inc[0][0]_i_1_n_0 ;
  wire \corse_inc[0][0]_i_2_n_0 ;
  wire \corse_inc[0][1]_i_1_n_0 ;
  wire \corse_inc[0][1]_i_2_n_0 ;
  wire \corse_inc[0][1]_i_5_n_0 ;
  wire \corse_inc[0][1]_i_6_n_0 ;
  wire \corse_inc[0][1]_i_7_n_0 ;
  wire \corse_inc[0][1]_i_8_n_0 ;
  wire \corse_inc[0][2]_i_1_n_0 ;
  wire \corse_inc[0][2]_i_2_n_0 ;
  wire \corse_inc[0][2]_i_3_n_0 ;
  wire \corse_inc[0][2]_i_4_n_0 ;
  wire \corse_inc[0][2]_i_5_n_0 ;
  wire \corse_inc[0][2]_i_7_n_0 ;
  wire \corse_inc[0][2]_i_8_n_0 ;
  wire \corse_inc[0][2]_i_9_n_0 ;
  wire \corse_inc[1][0]_i_1_n_0 ;
  wire \corse_inc[1][0]_i_2_n_0 ;
  wire \corse_inc[1][1]_i_1_n_0 ;
  wire \corse_inc[1][1]_i_2_n_0 ;
  wire \corse_inc[1][2]_i_1_n_0 ;
  wire \corse_inc[1][2]_i_2_n_0 ;
  wire \corse_inc[2][0]_i_1_n_0 ;
  wire \corse_inc[2][0]_i_2_n_0 ;
  wire \corse_inc[2][1]_i_1_n_0 ;
  wire \corse_inc[2][1]_i_2_n_0 ;
  wire \corse_inc[2][2]_i_1_n_0 ;
  wire \corse_inc[2][2]_i_2_n_0 ;
  wire \corse_inc[3][0]_i_1_n_0 ;
  wire \corse_inc[3][0]_i_2_n_0 ;
  wire \corse_inc[3][1]_i_1_n_0 ;
  wire \corse_inc[3][1]_i_2_n_0 ;
  wire \corse_inc[3][2]_i_1_n_0 ;
  wire \corse_inc[3][2]_i_2_n_0 ;
  wire \corse_inc[4][0]_i_1_n_0 ;
  wire \corse_inc[4][0]_i_2_n_0 ;
  wire \corse_inc[4][1]_i_1_n_0 ;
  wire \corse_inc[4][1]_i_2_n_0 ;
  wire \corse_inc[4][2]_i_1_n_0 ;
  wire \corse_inc[4][2]_i_2_n_0 ;
  wire \corse_inc[5][0]_i_1_n_0 ;
  wire \corse_inc[5][0]_i_2_n_0 ;
  wire \corse_inc[5][1]_i_1_n_0 ;
  wire \corse_inc[5][1]_i_2_n_0 ;
  wire \corse_inc[5][2]_i_1_n_0 ;
  wire \corse_inc[5][2]_i_2_n_0 ;
  wire \corse_inc[6][0]_i_1_n_0 ;
  wire \corse_inc[6][0]_i_2_n_0 ;
  wire \corse_inc[6][1]_i_1_n_0 ;
  wire \corse_inc[6][1]_i_2_n_0 ;
  wire \corse_inc[6][2]_i_1_n_0 ;
  wire \corse_inc[6][2]_i_2_n_0 ;
  wire \corse_inc[7][0]_i_1_n_0 ;
  wire \corse_inc[7][0]_i_2_n_0 ;
  wire \corse_inc[7][1]_i_1_n_0 ;
  wire \corse_inc[7][1]_i_2_n_0 ;
  wire \corse_inc[7][2]_i_1_n_0 ;
  wire \corse_inc[7][2]_i_2_n_0 ;
  wire \corse_inc_reg[0][1]_i_3_n_0 ;
  wire \corse_inc_reg[0][1]_i_4_n_0 ;
  wire \corse_inc_reg[0][2]_i_6_n_0 ;
  wire [2:0]\corse_inc_reg[0]__0 ;
  wire [2:0]\corse_inc_reg[1]__0 ;
  wire [2:0]\corse_inc_reg[2]__0 ;
  wire [2:0]\corse_inc_reg[3]__0 ;
  wire [2:0]\corse_inc_reg[4]__0 ;
  wire [2:0]\corse_inc_reg[5]__0 ;
  wire [2:0]\corse_inc_reg[6]__0 ;
  wire [2:0]\corse_inc_reg[7]__0 ;
  wire delay_dec_done_reg;
  wire done_dqs_tap_inc;
  wire dq_cnt_inc_i_1_n_0;
  wire dq_cnt_inc_i_2_n_0;
  wire dq_cnt_inc_reg_n_0;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire [2:0]dqs_count_r;
  wire \dqs_count_r[0]_i_1_n_0 ;
  wire \dqs_count_r[0]_i_2_n_0 ;
  wire \dqs_count_r[0]_i_3_n_0 ;
  wire \dqs_count_r[0]_i_4_n_0 ;
  wire \dqs_count_r[0]_i_5_n_0 ;
  wire \dqs_count_r[0]_rep_i_1_n_0 ;
  wire \dqs_count_r[1]_i_1_n_0 ;
  wire \dqs_count_r[1]_i_2_n_0 ;
  wire \dqs_count_r[1]_i_3_n_0 ;
  wire \dqs_count_r[1]_i_4_n_0 ;
  wire \dqs_count_r[1]_i_5_n_0 ;
  wire \dqs_count_r[1]_i_6_n_0 ;
  wire \dqs_count_r[1]_rep_i_1_n_0 ;
  wire \dqs_count_r[2]_i_10_n_0 ;
  wire \dqs_count_r[2]_i_11_n_0 ;
  wire \dqs_count_r[2]_i_12_n_0 ;
  wire \dqs_count_r[2]_i_1_n_0 ;
  wire \dqs_count_r[2]_i_2_n_0 ;
  wire \dqs_count_r[2]_i_3_n_0 ;
  wire \dqs_count_r[2]_i_4_n_0 ;
  wire \dqs_count_r[2]_i_5_n_0 ;
  wire \dqs_count_r[2]_i_6_n_0 ;
  wire \dqs_count_r[2]_i_7_n_0 ;
  wire \dqs_count_r[2]_i_8_n_0 ;
  wire \dqs_count_r[2]_i_9_n_0 ;
  wire \dqs_count_r[2]_rep__0_i_1_n_0 ;
  wire \dqs_count_r[2]_rep_i_1_n_0 ;
  wire \dqs_count_r[3]_i_1_n_0 ;
  wire \dqs_count_r[3]_i_2_n_0 ;
  wire \dqs_count_r[3]_i_3_n_0 ;
  wire \dqs_count_r[3]_i_4_n_0 ;
  wire \dqs_count_r[3]_i_5_n_0 ;
  wire \dqs_count_r[3]_i_6_n_0 ;
  wire \dqs_count_r[3]_i_7_n_0 ;
  wire \dqs_count_r[3]_i_8_n_0 ;
  wire \dqs_count_r[3]_i_9_n_0 ;
  wire [0:0]\dqs_count_r_reg[3]_0 ;
  wire dqs_po_dec_done;
  wire dqs_po_en_stg2_f;
  wire dqs_po_en_stg2_f_i_1_n_0;
  wire dqs_po_en_stg2_f_reg_0;
  wire dqs_po_stg2_f_incdec;
  wire dqs_po_stg2_f_incdec0;
  wire dqs_po_stg2_f_incdec_i_2_n_0;
  wire dqs_po_stg2_f_incdec_i_3_n_0;
  wire dqs_wl_po_stg2_c_incdec_i_1_n_0;
  wire dual_rnk_dec;
  wire dual_rnk_dec_i_1_n_0;
  wire early1_data;
  wire early2_data;
  wire [2:0]\final_coarse_tap_reg[0]__0 ;
  wire [2:0]\final_coarse_tap_reg[1]__0 ;
  wire [2:0]\final_coarse_tap_reg[2]__0 ;
  wire [2:0]\final_coarse_tap_reg[3]__0 ;
  wire [2:0]\final_coarse_tap_reg[4]__0 ;
  wire [2:0]\final_coarse_tap_reg[5]__0 ;
  wire [2:0]\final_coarse_tap_reg[6]__0 ;
  wire [2:0]\final_coarse_tap_reg[7]__0 ;
  wire \fine_dec_cnt[0]_i_1_n_0 ;
  wire \fine_dec_cnt[1]_i_1_n_0 ;
  wire \fine_dec_cnt[2]_i_1_n_0 ;
  wire \fine_dec_cnt[3]_i_1_n_0 ;
  wire \fine_dec_cnt[4]_i_1_n_0 ;
  wire \fine_dec_cnt[5]_i_10_n_0 ;
  wire \fine_dec_cnt[5]_i_1_n_0 ;
  wire \fine_dec_cnt[5]_i_2_n_0 ;
  wire \fine_dec_cnt[5]_i_3_n_0 ;
  wire \fine_dec_cnt[5]_i_4_n_0 ;
  wire \fine_dec_cnt[5]_i_5_n_0 ;
  wire \fine_dec_cnt[5]_i_6_n_0 ;
  wire \fine_dec_cnt[5]_i_7_n_0 ;
  wire \fine_dec_cnt[5]_i_8_n_0 ;
  wire \fine_dec_cnt[5]_i_9_n_0 ;
  wire \fine_dec_cnt_reg_n_0_[0] ;
  wire \fine_dec_cnt_reg_n_0_[1] ;
  wire \fine_dec_cnt_reg_n_0_[2] ;
  wire \fine_dec_cnt_reg_n_0_[3] ;
  wire \fine_dec_cnt_reg_n_0_[4] ;
  wire \fine_dec_cnt_reg_n_0_[5] ;
  wire \fine_inc[0][0]_i_1_n_0 ;
  wire \fine_inc[0][1]_i_1_n_0 ;
  wire \fine_inc[0][1]_i_4_n_0 ;
  wire \fine_inc[0][1]_i_5_n_0 ;
  wire \fine_inc[0][1]_i_6_n_0 ;
  wire \fine_inc[0][1]_i_7_n_0 ;
  wire \fine_inc[0][2]_i_1_n_0 ;
  wire \fine_inc[0][2]_i_2_n_0 ;
  wire \fine_inc[0][2]_i_4_n_0 ;
  wire \fine_inc[0][2]_i_5_n_0 ;
  wire \fine_inc[0][3]_i_1_n_0 ;
  wire \fine_inc[0][4]_i_1_n_0 ;
  wire \fine_inc[0][5]_i_10_n_0 ;
  wire \fine_inc[0][5]_i_12_n_0 ;
  wire \fine_inc[0][5]_i_13_n_0 ;
  wire \fine_inc[0][5]_i_14_n_0 ;
  wire \fine_inc[0][5]_i_15_n_0 ;
  wire \fine_inc[0][5]_i_16_n_0 ;
  wire \fine_inc[0][5]_i_17_n_0 ;
  wire \fine_inc[0][5]_i_18_n_0 ;
  wire \fine_inc[0][5]_i_1_n_0 ;
  wire \fine_inc[0][5]_i_2_n_0 ;
  wire \fine_inc[0][5]_i_3_n_0 ;
  wire \fine_inc[0][5]_i_4_n_0 ;
  wire \fine_inc[0][5]_i_5_n_0 ;
  wire \fine_inc[0][5]_i_6_n_0 ;
  wire \fine_inc[0][5]_i_7_n_0 ;
  wire \fine_inc[0][5]_i_9_n_0 ;
  wire \fine_inc[1][0]_i_1_n_0 ;
  wire \fine_inc[1][1]_i_1_n_0 ;
  wire \fine_inc[1][2]_i_1_n_0 ;
  wire \fine_inc[1][3]_i_1_n_0 ;
  wire \fine_inc[1][4]_i_1_n_0 ;
  wire \fine_inc[1][5]_i_1_n_0 ;
  wire \fine_inc[1][5]_i_2_n_0 ;
  wire \fine_inc[1][5]_i_3_n_0 ;
  wire \fine_inc[2][0]_i_1_n_0 ;
  wire \fine_inc[2][1]_i_1_n_0 ;
  wire \fine_inc[2][2]_i_1_n_0 ;
  wire \fine_inc[2][3]_i_1_n_0 ;
  wire \fine_inc[2][4]_i_1_n_0 ;
  wire \fine_inc[2][5]_i_1_n_0 ;
  wire \fine_inc[2][5]_i_2_n_0 ;
  wire \fine_inc[2][5]_i_3_n_0 ;
  wire \fine_inc[3][0]_i_1_n_0 ;
  wire \fine_inc[3][1]_i_1_n_0 ;
  wire \fine_inc[3][2]_i_1_n_0 ;
  wire \fine_inc[3][3]_i_1_n_0 ;
  wire \fine_inc[3][4]_i_1_n_0 ;
  wire \fine_inc[3][5]_i_1_n_0 ;
  wire \fine_inc[3][5]_i_2_n_0 ;
  wire \fine_inc[3][5]_i_3_n_0 ;
  wire \fine_inc[4][0]_i_1_n_0 ;
  wire \fine_inc[4][1]_i_1_n_0 ;
  wire \fine_inc[4][2]_i_1_n_0 ;
  wire \fine_inc[4][3]_i_1_n_0 ;
  wire \fine_inc[4][4]_i_1_n_0 ;
  wire \fine_inc[4][5]_i_1_n_0 ;
  wire \fine_inc[4][5]_i_2_n_0 ;
  wire \fine_inc[4][5]_i_3_n_0 ;
  wire \fine_inc[5][0]_i_1_n_0 ;
  wire \fine_inc[5][1]_i_1_n_0 ;
  wire \fine_inc[5][2]_i_1_n_0 ;
  wire \fine_inc[5][3]_i_1_n_0 ;
  wire \fine_inc[5][4]_i_1_n_0 ;
  wire \fine_inc[5][5]_i_1_n_0 ;
  wire \fine_inc[5][5]_i_2_n_0 ;
  wire \fine_inc[5][5]_i_3_n_0 ;
  wire \fine_inc[6][0]_i_1_n_0 ;
  wire \fine_inc[6][1]_i_1_n_0 ;
  wire \fine_inc[6][2]_i_1_n_0 ;
  wire \fine_inc[6][3]_i_1_n_0 ;
  wire \fine_inc[6][4]_i_1_n_0 ;
  wire \fine_inc[6][5]_i_1_n_0 ;
  wire \fine_inc[6][5]_i_2_n_0 ;
  wire \fine_inc[6][5]_i_3_n_0 ;
  wire \fine_inc[7][0]_i_1_n_0 ;
  wire \fine_inc[7][1]_i_1_n_0 ;
  wire \fine_inc[7][2]_i_1_n_0 ;
  wire \fine_inc[7][3]_i_1_n_0 ;
  wire \fine_inc[7][4]_i_1_n_0 ;
  wire \fine_inc[7][5]_i_1_n_0 ;
  wire \fine_inc[7][5]_i_2_n_0 ;
  wire \fine_inc_reg[0][1]_i_2_n_0 ;
  wire \fine_inc_reg[0][1]_i_3_n_0 ;
  wire \fine_inc_reg[0][2]_i_3_n_0 ;
  wire \fine_inc_reg[0][5]_i_11_n_0 ;
  wire \fine_inc_reg[0][5]_i_8_n_0 ;
  wire [5:0]\fine_inc_reg[0]__0 ;
  wire [5:0]\fine_inc_reg[1]__0 ;
  wire [5:0]\fine_inc_reg[2]__0 ;
  wire [5:0]\fine_inc_reg[3]__0 ;
  wire [5:0]\fine_inc_reg[4]__0 ;
  wire [5:0]\fine_inc_reg[5]__0 ;
  wire \fine_inc_reg[6][0]_0 ;
  wire [5:0]\fine_inc_reg[6]__0 ;
  wire [5:0]\fine_inc_reg[7]__0 ;
  wire flag_ck_negedge_i_10_n_0;
  wire flag_ck_negedge_i_11_n_0;
  wire flag_ck_negedge_i_1_n_0;
  wire flag_ck_negedge_i_2_n_0;
  wire flag_ck_negedge_i_3_n_0;
  wire flag_ck_negedge_i_5_n_0;
  wire flag_ck_negedge_i_6_n_0;
  wire flag_ck_negedge_i_7_n_0;
  wire flag_ck_negedge_i_8_n_0;
  wire flag_ck_negedge_i_9_n_0;
  wire flag_ck_negedge_reg_i_4_n_0;
  wire flag_ck_negedge_reg_n_0;
  wire flag_init;
  wire flag_init_i_1_n_0;
  wire flag_init_i_2_n_0;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_10_n_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_2_n_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_3_n_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_4_n_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_5_n_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_7_n_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_8_n_0 ;
  wire \gen_final_tap[0].final_val[0][3]_i_9_n_0 ;
  wire \gen_final_tap[0].final_val[0][5]_i_1_n_0 ;
  wire \gen_final_tap[0].final_val[0][5]_i_3_n_0 ;
  wire \gen_final_tap[0].final_val[0][5]_i_4_n_0 ;
  wire \gen_final_tap[0].final_val[0][5]_i_6_n_0 ;
  wire \gen_final_tap[0].final_val[0][5]_i_7_n_0 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_0 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_1 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_2 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_3 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_4 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_5 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_6 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_1_n_7 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_0 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_1 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_2 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_3 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_4 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_5 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_6 ;
  wire \gen_final_tap[0].final_val_reg[0][3]_i_6_n_7 ;
  wire \gen_final_tap[0].final_val_reg[0][5]_i_2_n_3 ;
  wire \gen_final_tap[0].final_val_reg[0][5]_i_2_n_6 ;
  wire \gen_final_tap[0].final_val_reg[0][5]_i_2_n_7 ;
  wire \gen_final_tap[0].final_val_reg[0][5]_i_5_n_3 ;
  wire \gen_final_tap[0].final_val_reg[0][5]_i_5_n_6 ;
  wire \gen_final_tap[0].final_val_reg[0][5]_i_5_n_7 ;
  wire [5:0]\gen_final_tap[0].final_val_reg[0]__0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_10_n_0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_2_n_0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_3_n_0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_4_n_0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_5_n_0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_7_n_0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_8_n_0 ;
  wire \gen_final_tap[1].final_val[1][3]_i_9_n_0 ;
  wire \gen_final_tap[1].final_val[1][5]_i_2_n_0 ;
  wire \gen_final_tap[1].final_val[1][5]_i_3_n_0 ;
  wire \gen_final_tap[1].final_val[1][5]_i_5_n_0 ;
  wire \gen_final_tap[1].final_val[1][5]_i_6_n_0 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_0 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_1 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_2 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_3 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_4 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_5 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_6 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_1_n_7 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_0 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_1 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_2 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_3 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_4 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_5 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_6 ;
  wire \gen_final_tap[1].final_val_reg[1][3]_i_6_n_7 ;
  wire \gen_final_tap[1].final_val_reg[1][5]_i_1_n_3 ;
  wire \gen_final_tap[1].final_val_reg[1][5]_i_1_n_6 ;
  wire \gen_final_tap[1].final_val_reg[1][5]_i_1_n_7 ;
  wire \gen_final_tap[1].final_val_reg[1][5]_i_4_n_3 ;
  wire \gen_final_tap[1].final_val_reg[1][5]_i_4_n_6 ;
  wire \gen_final_tap[1].final_val_reg[1][5]_i_4_n_7 ;
  wire [5:0]\gen_final_tap[1].final_val_reg[1]__0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_10_n_0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_2_n_0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_3_n_0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_4_n_0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_5_n_0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_7_n_0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_8_n_0 ;
  wire \gen_final_tap[2].final_val[2][3]_i_9_n_0 ;
  wire \gen_final_tap[2].final_val[2][5]_i_2_n_0 ;
  wire \gen_final_tap[2].final_val[2][5]_i_3_n_0 ;
  wire \gen_final_tap[2].final_val[2][5]_i_5_n_0 ;
  wire \gen_final_tap[2].final_val[2][5]_i_6_n_0 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_0 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_1 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_2 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_3 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_4 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_5 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_6 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_1_n_7 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_0 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_1 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_2 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_3 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_4 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_5 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_6 ;
  wire \gen_final_tap[2].final_val_reg[2][3]_i_6_n_7 ;
  wire \gen_final_tap[2].final_val_reg[2][5]_i_1_n_3 ;
  wire \gen_final_tap[2].final_val_reg[2][5]_i_1_n_6 ;
  wire \gen_final_tap[2].final_val_reg[2][5]_i_1_n_7 ;
  wire \gen_final_tap[2].final_val_reg[2][5]_i_4_n_3 ;
  wire \gen_final_tap[2].final_val_reg[2][5]_i_4_n_6 ;
  wire \gen_final_tap[2].final_val_reg[2][5]_i_4_n_7 ;
  wire [5:0]\gen_final_tap[2].final_val_reg[2]__0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_10_n_0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_2_n_0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_3_n_0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_4_n_0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_5_n_0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_7_n_0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_8_n_0 ;
  wire \gen_final_tap[3].final_val[3][3]_i_9_n_0 ;
  wire \gen_final_tap[3].final_val[3][5]_i_2_n_0 ;
  wire \gen_final_tap[3].final_val[3][5]_i_3_n_0 ;
  wire \gen_final_tap[3].final_val[3][5]_i_5_n_0 ;
  wire \gen_final_tap[3].final_val[3][5]_i_6_n_0 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_0 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_1 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_2 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_3 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_4 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_5 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_6 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_1_n_7 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_0 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_1 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_2 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_3 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_4 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_5 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_6 ;
  wire \gen_final_tap[3].final_val_reg[3][3]_i_6_n_7 ;
  wire \gen_final_tap[3].final_val_reg[3][5]_i_1_n_3 ;
  wire \gen_final_tap[3].final_val_reg[3][5]_i_1_n_6 ;
  wire \gen_final_tap[3].final_val_reg[3][5]_i_1_n_7 ;
  wire \gen_final_tap[3].final_val_reg[3][5]_i_4_n_3 ;
  wire \gen_final_tap[3].final_val_reg[3][5]_i_4_n_6 ;
  wire \gen_final_tap[3].final_val_reg[3][5]_i_4_n_7 ;
  wire [5:0]\gen_final_tap[3].final_val_reg[3]__0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_10_n_0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_2_n_0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_3_n_0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_4_n_0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_5_n_0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_7_n_0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_8_n_0 ;
  wire \gen_final_tap[4].final_val[4][3]_i_9_n_0 ;
  wire \gen_final_tap[4].final_val[4][5]_i_2_n_0 ;
  wire \gen_final_tap[4].final_val[4][5]_i_3_n_0 ;
  wire \gen_final_tap[4].final_val[4][5]_i_5_n_0 ;
  wire \gen_final_tap[4].final_val[4][5]_i_6_n_0 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_0 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_1 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_2 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_3 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_4 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_5 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_6 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_1_n_7 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_0 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_1 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_2 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_3 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_4 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_5 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_6 ;
  wire \gen_final_tap[4].final_val_reg[4][3]_i_6_n_7 ;
  wire \gen_final_tap[4].final_val_reg[4][5]_i_1_n_3 ;
  wire \gen_final_tap[4].final_val_reg[4][5]_i_1_n_6 ;
  wire \gen_final_tap[4].final_val_reg[4][5]_i_1_n_7 ;
  wire \gen_final_tap[4].final_val_reg[4][5]_i_4_n_3 ;
  wire \gen_final_tap[4].final_val_reg[4][5]_i_4_n_6 ;
  wire \gen_final_tap[4].final_val_reg[4][5]_i_4_n_7 ;
  wire [5:0]\gen_final_tap[4].final_val_reg[4]__0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_10_n_0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_2_n_0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_3_n_0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_4_n_0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_5_n_0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_7_n_0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_8_n_0 ;
  wire \gen_final_tap[5].final_val[5][3]_i_9_n_0 ;
  wire \gen_final_tap[5].final_val[5][5]_i_2_n_0 ;
  wire \gen_final_tap[5].final_val[5][5]_i_3_n_0 ;
  wire \gen_final_tap[5].final_val[5][5]_i_5_n_0 ;
  wire \gen_final_tap[5].final_val[5][5]_i_6_n_0 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_0 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_1 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_2 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_3 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_4 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_5 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_6 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_1_n_7 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_0 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_1 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_2 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_3 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_4 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_5 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_6 ;
  wire \gen_final_tap[5].final_val_reg[5][3]_i_6_n_7 ;
  wire \gen_final_tap[5].final_val_reg[5][5]_i_1_n_3 ;
  wire \gen_final_tap[5].final_val_reg[5][5]_i_1_n_6 ;
  wire \gen_final_tap[5].final_val_reg[5][5]_i_1_n_7 ;
  wire \gen_final_tap[5].final_val_reg[5][5]_i_4_n_3 ;
  wire \gen_final_tap[5].final_val_reg[5][5]_i_4_n_6 ;
  wire \gen_final_tap[5].final_val_reg[5][5]_i_4_n_7 ;
  wire [5:0]\gen_final_tap[5].final_val_reg[5]__0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_10_n_0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_2_n_0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_3_n_0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_4_n_0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_5_n_0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_7_n_0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_8_n_0 ;
  wire \gen_final_tap[6].final_val[6][3]_i_9_n_0 ;
  wire \gen_final_tap[6].final_val[6][5]_i_2_n_0 ;
  wire \gen_final_tap[6].final_val[6][5]_i_3_n_0 ;
  wire \gen_final_tap[6].final_val[6][5]_i_5_n_0 ;
  wire \gen_final_tap[6].final_val[6][5]_i_6_n_0 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_0 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_1 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_2 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_3 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_4 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_5 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_6 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_1_n_7 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_0 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_1 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_2 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_3 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_4 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_5 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_6 ;
  wire \gen_final_tap[6].final_val_reg[6][3]_i_6_n_7 ;
  wire \gen_final_tap[6].final_val_reg[6][5]_i_1_n_3 ;
  wire \gen_final_tap[6].final_val_reg[6][5]_i_1_n_6 ;
  wire \gen_final_tap[6].final_val_reg[6][5]_i_1_n_7 ;
  wire \gen_final_tap[6].final_val_reg[6][5]_i_4_n_3 ;
  wire \gen_final_tap[6].final_val_reg[6][5]_i_4_n_6 ;
  wire \gen_final_tap[6].final_val_reg[6][5]_i_4_n_7 ;
  wire [5:0]\gen_final_tap[6].final_val_reg[6]__0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_10_n_0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_2_n_0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_3_n_0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_4_n_0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_5_n_0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_7_n_0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_8_n_0 ;
  wire \gen_final_tap[7].final_val[7][3]_i_9_n_0 ;
  wire \gen_final_tap[7].final_val[7][5]_i_2_n_0 ;
  wire \gen_final_tap[7].final_val[7][5]_i_3_n_0 ;
  wire \gen_final_tap[7].final_val[7][5]_i_5_n_0 ;
  wire \gen_final_tap[7].final_val[7][5]_i_6_n_0 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_0 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_1 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_2 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_3 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_4 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_5 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_6 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_1_n_7 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_0 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_1 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_2 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_3 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_4 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_5 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_6 ;
  wire \gen_final_tap[7].final_val_reg[7][3]_i_6_n_7 ;
  wire \gen_final_tap[7].final_val_reg[7][5]_i_1_n_3 ;
  wire \gen_final_tap[7].final_val_reg[7][5]_i_1_n_6 ;
  wire \gen_final_tap[7].final_val_reg[7][5]_i_1_n_7 ;
  wire \gen_final_tap[7].final_val_reg[7][5]_i_4_n_3 ;
  wire \gen_final_tap[7].final_val_reg[7][5]_i_4_n_6 ;
  wire \gen_final_tap[7].final_val_reg[7][5]_i_4_n_7 ;
  wire [5:0]\gen_final_tap[7].final_val_reg[7]__0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ;
  wire \incdec_wait_cnt[3]_i_1_n_0 ;
  wire [3:0]incdec_wait_cnt_reg__0;
  wire inhibit_edge_detect_r_i_1_n_0;
  wire inhibit_edge_detect_r_i_2_n_0;
  wire inhibit_edge_detect_r_i_3_n_0;
  wire inhibit_edge_detect_r_i_4_n_0;
  wire inhibit_edge_detect_r_i_5_n_0;
  wire inhibit_edge_detect_r_i_6_n_0;
  wire inhibit_edge_detect_r_reg_n_0;
  wire [5:0]largest;
  wire [3:0]p_0_in;
  wire [3:0]p_0_in__0;
  wire phaser_out_i_5_n_0;
  wire phy_ctl_ready;
  wire phy_ctl_ready_r4_reg_srl4_n_0;
  wire phy_ctl_ready_r5;
  wire phy_ctl_ready_r6_reg_n_0;
  wire pi_fine_dly_dec_done;
  wire po_cnt_dec_i_1_n_0;
  wire po_cnt_dec_i_2_n_0;
  wire \po_counter_read_val_reg[0] ;
  wire \po_counter_read_val_reg[1] ;
  wire \po_counter_read_val_reg[2] ;
  wire \po_counter_read_val_reg[3] ;
  wire \po_counter_read_val_reg[4] ;
  wire \po_counter_read_val_reg[5] ;
  wire \po_counter_read_val_reg[6] ;
  wire \po_counter_read_val_reg[7] ;
  wire \po_counter_read_val_reg[8] ;
  wire po_dec_done;
  wire po_dec_done_i_1_n_0;
  wire po_dec_done_i_2_n_0;
  wire po_dec_done_i_3_n_0;
  wire \po_rdval_cnt[0]_i_1_n_0 ;
  wire \po_rdval_cnt[1]_i_1_n_0 ;
  wire \po_rdval_cnt[2]_i_1_n_0 ;
  wire \po_rdval_cnt[3]_i_2_n_0 ;
  wire \po_rdval_cnt[4]_i_2_n_0 ;
  wire \po_rdval_cnt[5]_i_2_n_0 ;
  wire \po_rdval_cnt[5]_i_4_n_0 ;
  wire \po_rdval_cnt[6]_i_1_n_0 ;
  wire \po_rdval_cnt[7]_i_1_n_0 ;
  wire \po_rdval_cnt[8]_i_1_n_0 ;
  wire \po_rdval_cnt[8]_i_2_n_0 ;
  wire \po_rdval_cnt[8]_i_3_n_0 ;
  wire \po_rdval_cnt[8]_i_5_n_0 ;
  wire \po_rdval_cnt[8]_i_6_n_0 ;
  wire \po_rdval_cnt_reg[3]_i_1_n_0 ;
  wire \po_rdval_cnt_reg[4]_i_1_n_0 ;
  wire \po_rdval_cnt_reg[5]_i_1_n_0 ;
  wire \po_rdval_cnt_reg_n_0_[0] ;
  wire \po_rdval_cnt_reg_n_0_[1] ;
  wire \po_rdval_cnt_reg_n_0_[2] ;
  wire \po_rdval_cnt_reg_n_0_[3] ;
  wire \po_rdval_cnt_reg_n_0_[4] ;
  wire \po_rdval_cnt_reg_n_0_[5] ;
  wire \po_rdval_cnt_reg_n_0_[6] ;
  wire \po_rdval_cnt_reg_n_0_[7] ;
  wire \po_rdval_cnt_reg_n_0_[8] ;
  wire [2:2]po_stg2_c_incdec;
  wire \po_stg2_wrcal_cnt_reg[0] ;
  wire \po_stg2_wrcal_cnt_reg[0]_0 ;
  wire \po_stg2_wrcal_cnt_reg[0]_1 ;
  wire \po_stg2_wrcal_cnt_reg[0]_2 ;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[3] ;
  wire [3:0]\po_stg2_wrcal_cnt_reg[3]_0 ;
  wire rd_data_edge_detect_r0;
  wire \rd_data_edge_detect_r[0]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[2]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[3]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[4]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[5]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[6]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_2_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_3_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_4_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_6_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_7_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_8_n_0 ;
  wire \rd_data_edge_detect_r_reg[7]_i_5_n_0 ;
  wire \rd_data_edge_detect_r_reg_n_0_[0] ;
  wire \rd_data_edge_detect_r_reg_n_0_[1] ;
  wire \rd_data_edge_detect_r_reg_n_0_[2] ;
  wire \rd_data_edge_detect_r_reg_n_0_[3] ;
  wire \rd_data_edge_detect_r_reg_n_0_[4] ;
  wire \rd_data_edge_detect_r_reg_n_0_[5] ;
  wire \rd_data_edge_detect_r_reg_n_0_[6] ;
  wire \rd_data_edge_detect_r_reg_n_0_[7] ;
  wire rd_data_previous_r0;
  wire \rd_data_previous_r[7]_i_2_n_0 ;
  wire \rd_data_previous_r[7]_i_3_n_0 ;
  wire \rd_data_previous_r[7]_i_4_n_0 ;
  wire \rd_data_previous_r[7]_i_5_n_0 ;
  wire \rd_data_previous_r_reg_n_0_[0] ;
  wire \rd_data_previous_r_reg_n_0_[1] ;
  wire \rd_data_previous_r_reg_n_0_[2] ;
  wire \rd_data_previous_r_reg_n_0_[3] ;
  wire \rd_data_previous_r_reg_n_0_[4] ;
  wire \rd_data_previous_r_reg_n_0_[5] ;
  wire \rd_data_previous_r_reg_n_0_[6] ;
  wire \rd_data_previous_r_reg_n_0_[7] ;
  wire rdlvl_stg1_done_reg;
  wire rstdiv0_sync_r1;
  wire [1:0]rstdiv0_sync_r1_reg_rep__10;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__4;
  wire [0:0]rstdiv0_sync_r1_reg_rep__6;
  wire [1:0]rstdiv0_sync_r1_reg_rep__7;
  wire [0:0]rstdiv0_sync_r1_reg_rep__9;
  wire \single_rank.done_dqs_dec_i_1_n_0 ;
  wire \smallest[0][0]_i_3_n_0 ;
  wire \smallest[0][0]_i_4_n_0 ;
  wire \smallest[0][1]_i_3_n_0 ;
  wire \smallest[0][1]_i_4_n_0 ;
  wire \smallest[0][2]_i_3_n_0 ;
  wire \smallest[0][2]_i_4_n_0 ;
  wire \smallest[0][3]_i_3_n_0 ;
  wire \smallest[0][3]_i_4_n_0 ;
  wire \smallest[0][4]_i_3_n_0 ;
  wire \smallest[0][4]_i_4_n_0 ;
  wire \smallest[0][5]_i_1_n_0 ;
  wire \smallest[0][5]_i_3_n_0 ;
  wire \smallest[0][5]_i_5_n_0 ;
  wire \smallest[0][5]_i_6_n_0 ;
  wire \smallest[1][0]_i_1_n_0 ;
  wire \smallest[1][1]_i_1_n_0 ;
  wire \smallest[1][2]_i_1_n_0 ;
  wire \smallest[1][3]_i_1_n_0 ;
  wire \smallest[1][4]_i_1_n_0 ;
  wire \smallest[1][5]_i_1_n_0 ;
  wire \smallest[1][5]_i_2_n_0 ;
  wire \smallest[2][0]_i_1_n_0 ;
  wire \smallest[2][1]_i_1_n_0 ;
  wire \smallest[2][2]_i_1_n_0 ;
  wire \smallest[2][3]_i_1_n_0 ;
  wire \smallest[2][4]_i_1_n_0 ;
  wire \smallest[2][5]_i_1_n_0 ;
  wire \smallest[2][5]_i_2_n_0 ;
  wire \smallest[3][0]_i_1_n_0 ;
  wire \smallest[3][1]_i_1_n_0 ;
  wire \smallest[3][2]_i_1_n_0 ;
  wire \smallest[3][3]_i_1_n_0 ;
  wire \smallest[3][4]_i_1_n_0 ;
  wire \smallest[3][5]_i_1_n_0 ;
  wire \smallest[3][5]_i_2_n_0 ;
  wire \smallest[4][0]_i_1_n_0 ;
  wire \smallest[4][1]_i_1_n_0 ;
  wire \smallest[4][2]_i_1_n_0 ;
  wire \smallest[4][3]_i_1_n_0 ;
  wire \smallest[4][4]_i_1_n_0 ;
  wire \smallest[4][5]_i_1_n_0 ;
  wire \smallest[4][5]_i_2_n_0 ;
  wire \smallest[5][0]_i_1_n_0 ;
  wire \smallest[5][1]_i_1_n_0 ;
  wire \smallest[5][2]_i_1_n_0 ;
  wire \smallest[5][3]_i_1_n_0 ;
  wire \smallest[5][4]_i_1_n_0 ;
  wire \smallest[5][5]_i_1_n_0 ;
  wire \smallest[5][5]_i_2_n_0 ;
  wire \smallest[6][0]_i_1_n_0 ;
  wire \smallest[6][1]_i_1_n_0 ;
  wire \smallest[6][2]_i_1_n_0 ;
  wire \smallest[6][3]_i_1_n_0 ;
  wire \smallest[6][4]_i_1_n_0 ;
  wire \smallest[6][5]_i_1_n_0 ;
  wire \smallest[6][5]_i_2_n_0 ;
  wire \smallest[7][0]_i_1_n_0 ;
  wire \smallest[7][1]_i_1_n_0 ;
  wire \smallest[7][2]_i_1_n_0 ;
  wire \smallest[7][3]_i_1_n_0 ;
  wire \smallest[7][4]_i_1_n_0 ;
  wire \smallest[7][5]_i_1_n_0 ;
  wire \smallest[7][5]_i_2_n_0 ;
  wire \smallest_reg[0][0]_i_2_n_0 ;
  wire \smallest_reg[0][1]_i_2_n_0 ;
  wire \smallest_reg[0][2]_i_2_n_0 ;
  wire \smallest_reg[0][3]_i_2_n_0 ;
  wire \smallest_reg[0][4]_i_2_n_0 ;
  wire \smallest_reg[0][5]_i_4_n_0 ;
  wire [5:0]\smallest_reg[0]__0 ;
  wire [5:0]\smallest_reg[1]__0 ;
  wire [5:0]\smallest_reg[2]__0 ;
  wire [5:0]\smallest_reg[3]__0 ;
  wire [5:0]\smallest_reg[4]__0 ;
  wire [5:0]\smallest_reg[5]__0 ;
  wire [5:0]\smallest_reg[6]__0 ;
  wire \smallest_reg[7][0]_0 ;
  wire [5:0]\smallest_reg[7]__0 ;
  wire stable_cnt;
  wire stable_cnt0;
  wire \stable_cnt[3]_i_10_n_0 ;
  wire \stable_cnt[3]_i_4_n_0 ;
  wire \stable_cnt[3]_i_5_n_0 ;
  wire \stable_cnt[3]_i_6_n_0 ;
  wire \stable_cnt[3]_i_7_n_0 ;
  wire \stable_cnt[3]_i_8_n_0 ;
  wire \stable_cnt[3]_i_9_n_0 ;
  wire \stable_cnt_reg_n_0_[0] ;
  wire \stable_cnt_reg_n_0_[1] ;
  wire \stable_cnt_reg_n_0_[2] ;
  wire \stable_cnt_reg_n_0_[3] ;
  wire wait_cnt0;
  wire [3:0]wait_cnt0__0;
  wire \wait_cnt[1]_i_1_n_0 ;
  wire [3:0]wait_cnt_reg__0;
  wire \wl_corse_cnt[0][0][0]_i_2_n_0 ;
  wire \wl_corse_cnt[0][0][0]_i_3_n_0 ;
  wire \wl_corse_cnt[0][0][1]_i_2_n_0 ;
  wire \wl_corse_cnt[0][0][1]_i_3_n_0 ;
  wire \wl_corse_cnt[0][0][2]_i_1_n_0 ;
  wire \wl_corse_cnt[0][0][2]_i_3_n_0 ;
  wire \wl_corse_cnt[0][0][2]_i_4_n_0 ;
  wire \wl_corse_cnt[0][2][2]_i_1_n_0 ;
  wire \wl_corse_cnt[0][3][2]_i_1_n_0 ;
  wire \wl_corse_cnt[0][4][2]_i_1_n_0 ;
  wire \wl_corse_cnt[0][5][2]_i_1_n_0 ;
  wire \wl_corse_cnt[0][6][2]_i_1_n_0 ;
  wire \wl_corse_cnt[0][7][2]_i_1_n_0 ;
  wire \wl_corse_cnt[0][7][2]_i_2_n_0 ;
  wire \wl_corse_cnt_reg[0][0][0]_i_1_n_0 ;
  wire \wl_corse_cnt_reg[0][0][1]_i_1_n_0 ;
  wire \wl_corse_cnt_reg[0][0][2]_i_2_n_0 ;
  wire [2:0]\wl_corse_cnt_reg[0][0]__0 ;
  wire [2:0]\wl_corse_cnt_reg[0][1]__0 ;
  wire [2:0]\wl_corse_cnt_reg[0][2]__0 ;
  wire [2:0]\wl_corse_cnt_reg[0][3]__0 ;
  wire [2:0]\wl_corse_cnt_reg[0][4]__0 ;
  wire [2:0]\wl_corse_cnt_reg[0][5]__0 ;
  wire [2:0]\wl_corse_cnt_reg[0][6]__0 ;
  wire \wl_corse_cnt_reg[0][7][2]_0 ;
  wire \wl_corse_cnt_reg[0][7][2]_1 ;
  wire [2:0]\wl_corse_cnt_reg[0][7]__0 ;
  wire \wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][5] ;
  wire wl_edge_detect_valid_r_i_1_n_0;
  wire wl_edge_detect_valid_r_reg_n_0;
  wire wl_sm_start;
  wire \wl_state_r1_reg_n_0_[0] ;
  wire \wl_state_r1_reg_n_0_[1] ;
  wire \wl_state_r1_reg_n_0_[2] ;
  wire \wl_state_r1_reg_n_0_[3] ;
  wire \wl_state_r1_reg_n_0_[4] ;
  wire \wl_state_r[0]_i_10_n_0 ;
  wire \wl_state_r[0]_i_1_n_0 ;
  wire \wl_state_r[0]_i_2_n_0 ;
  wire \wl_state_r[0]_i_3_n_0 ;
  wire \wl_state_r[0]_i_4_n_0 ;
  wire \wl_state_r[0]_i_5_n_0 ;
  wire \wl_state_r[0]_i_6_n_0 ;
  wire \wl_state_r[0]_i_7_n_0 ;
  wire \wl_state_r[0]_i_8_n_0 ;
  wire \wl_state_r[0]_i_9_n_0 ;
  wire \wl_state_r[1]_i_10_n_0 ;
  wire \wl_state_r[1]_i_11_n_0 ;
  wire \wl_state_r[1]_i_12_n_0 ;
  wire \wl_state_r[1]_i_13_n_0 ;
  wire \wl_state_r[1]_i_1_n_0 ;
  wire \wl_state_r[1]_i_2_n_0 ;
  wire \wl_state_r[1]_i_3_n_0 ;
  wire \wl_state_r[1]_i_4_n_0 ;
  wire \wl_state_r[1]_i_5_n_0 ;
  wire \wl_state_r[1]_i_6_n_0 ;
  wire \wl_state_r[1]_i_7_n_0 ;
  wire \wl_state_r[1]_i_8_n_0 ;
  wire \wl_state_r[1]_i_9_n_0 ;
  wire \wl_state_r[2]_i_11_n_0 ;
  wire \wl_state_r[2]_i_12_n_0 ;
  wire \wl_state_r[2]_i_14_n_0 ;
  wire \wl_state_r[2]_i_15_n_0 ;
  wire \wl_state_r[2]_i_2_n_0 ;
  wire \wl_state_r[2]_i_3_n_0 ;
  wire \wl_state_r[2]_i_4_n_0 ;
  wire \wl_state_r[2]_i_5_n_0 ;
  wire \wl_state_r[2]_i_6_n_0 ;
  wire \wl_state_r[2]_i_7_n_0 ;
  wire \wl_state_r[2]_i_8_n_0 ;
  wire \wl_state_r[2]_i_9_n_0 ;
  wire \wl_state_r[3]_i_10_n_0 ;
  wire \wl_state_r[3]_i_11_n_0 ;
  wire \wl_state_r[3]_i_12_n_0 ;
  wire \wl_state_r[3]_i_2_n_0 ;
  wire \wl_state_r[3]_i_3_n_0 ;
  wire \wl_state_r[3]_i_4_n_0 ;
  wire \wl_state_r[3]_i_5_n_0 ;
  wire \wl_state_r[3]_i_6_n_0 ;
  wire \wl_state_r[3]_i_7_n_0 ;
  wire \wl_state_r[3]_i_8_n_0 ;
  wire \wl_state_r[3]_i_9_n_0 ;
  wire \wl_state_r[4]_i_10_n_0 ;
  wire \wl_state_r[4]_i_11_n_0 ;
  wire \wl_state_r[4]_i_13_n_0 ;
  wire \wl_state_r[4]_i_14_n_0 ;
  wire \wl_state_r[4]_i_15_n_0 ;
  wire \wl_state_r[4]_i_16_n_0 ;
  wire \wl_state_r[4]_i_17_n_0 ;
  wire \wl_state_r[4]_i_18_n_0 ;
  wire \wl_state_r[4]_i_19_n_0 ;
  wire \wl_state_r[4]_i_20_n_0 ;
  wire \wl_state_r[4]_i_21_n_0 ;
  wire \wl_state_r[4]_i_22_n_0 ;
  wire \wl_state_r[4]_i_23_n_0 ;
  wire \wl_state_r[4]_i_24_n_0 ;
  wire \wl_state_r[4]_i_25_n_0 ;
  wire \wl_state_r[4]_i_26_n_0 ;
  wire \wl_state_r[4]_i_27_n_0 ;
  wire \wl_state_r[4]_i_3_n_0 ;
  wire \wl_state_r[4]_i_4_n_0 ;
  wire \wl_state_r[4]_i_5_n_0 ;
  wire \wl_state_r[4]_i_6_n_0 ;
  wire \wl_state_r[4]_i_7_n_0 ;
  wire \wl_state_r[4]_i_8_n_0 ;
  wire \wl_state_r[4]_i_9_n_0 ;
  wire \wl_state_r_reg[2]_i_1_n_0 ;
  wire \wl_state_r_reg[3]_i_1_n_0 ;
  wire \wl_state_r_reg[4]_i_1_n_0 ;
  wire \wl_state_r_reg[4]_i_2_n_0 ;
  wire \wl_state_r_reg_n_0_[1] ;
  wire \wl_state_r_reg_n_0_[2] ;
  wire [5:1]wl_tap_count_r;
  wire \wl_tap_count_r[0]_i_1_n_0 ;
  wire \wl_tap_count_r[0]_i_2_n_0 ;
  wire \wl_tap_count_r[0]_i_3_n_0 ;
  wire \wl_tap_count_r[0]_i_4_n_0 ;
  wire \wl_tap_count_r[0]_i_5_n_0 ;
  wire \wl_tap_count_r[1]_i_3_n_0 ;
  wire \wl_tap_count_r[1]_i_4_n_0 ;
  wire \wl_tap_count_r[1]_i_5_n_0 ;
  wire \wl_tap_count_r[2]_i_2_n_0 ;
  wire \wl_tap_count_r[2]_i_3_n_0 ;
  wire \wl_tap_count_r[2]_i_4_n_0 ;
  wire \wl_tap_count_r[2]_i_5_n_0 ;
  wire \wl_tap_count_r[3]_i_3_n_0 ;
  wire \wl_tap_count_r[3]_i_4_n_0 ;
  wire \wl_tap_count_r[3]_i_5_n_0 ;
  wire \wl_tap_count_r[4]_i_1_n_0 ;
  wire \wl_tap_count_r[4]_i_2_n_0 ;
  wire \wl_tap_count_r[4]_i_3_n_0 ;
  wire \wl_tap_count_r[4]_i_4_n_0 ;
  wire \wl_tap_count_r[4]_i_5_n_0 ;
  wire \wl_tap_count_r[4]_i_6_n_0 ;
  wire \wl_tap_count_r[4]_i_7_n_0 ;
  wire \wl_tap_count_r[5]_i_1_n_0 ;
  wire \wl_tap_count_r[5]_i_3_n_0 ;
  wire \wl_tap_count_r[5]_i_5_n_0 ;
  wire \wl_tap_count_r[5]_i_6_n_0 ;
  wire \wl_tap_count_r[5]_i_7_n_0 ;
  wire \wl_tap_count_r_reg[1]_i_2_n_0 ;
  wire \wl_tap_count_r_reg[3]_i_2_n_0 ;
  wire \wl_tap_count_r_reg[5]_i_4_n_0 ;
  wire \wl_tap_count_r_reg_n_0_[0] ;
  wire \wl_tap_count_r_reg_n_0_[1] ;
  wire \wl_tap_count_r_reg_n_0_[2] ;
  wire \wl_tap_count_r_reg_n_0_[3] ;
  wire \wl_tap_count_r_reg_n_0_[4] ;
  wire \wl_tap_count_r_reg_n_0_[5] ;
  wire wr_level_done0;
  wire wr_level_done_i_1_n_0;
  wire wr_level_done_r1;
  wire wr_level_done_r2;
  wire wr_level_done_r3;
  wire wr_level_done_r4;
  wire wr_level_done_r5;
  wire wr_level_done_r5_reg_0;
  wire wr_level_done_r_i_1_n_0;
  wire wr_level_done_r_i_2_n_0;
  wire wr_level_done_r_reg_n_0;
  wire wr_level_start_r;
  wire wr_lvl_start_reg;
  wire wrcal_done_reg;
  wire wrlvl_byte_done;
  wire wrlvl_byte_done_i_1_n_0;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_r;
  wire wrlvl_byte_redo_reg;
  wire wrlvl_byte_redo_reg_0;
  wire wrlvl_byte_redo_reg_1;
  wire wrlvl_done_r_reg;
  wire wrlvl_rank_done;
  wire wrlvl_rank_done_r_i_1_n_0;
  wire wrlvl_rank_done_r_i_2_n_0;
  wire \wrlvl_redo_corse_inc[0]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_10_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_11_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_2_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_6_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_7_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_8_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_9_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_2_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_3_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_4_n_0 ;
  wire \wrlvl_redo_corse_inc_reg[1]_i_3_n_0 ;
  wire \wrlvl_redo_corse_inc_reg[1]_i_4_n_0 ;
  wire \wrlvl_redo_corse_inc_reg[1]_i_5_n_0 ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[0] ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[1] ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[2] ;
  wire [3:1]\NLW_gen_final_tap[0].final_val_reg[0][5]_i_2_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[0].final_val_reg[0][5]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[0].final_val_reg[0][5]_i_5_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[0].final_val_reg[0][5]_i_5_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[1].final_val_reg[1][5]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[1].final_val_reg[1][5]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[1].final_val_reg[1][5]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[1].final_val_reg[1][5]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[2].final_val_reg[2][5]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[2].final_val_reg[2][5]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[2].final_val_reg[2][5]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[2].final_val_reg[2][5]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[3].final_val_reg[3][5]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[3].final_val_reg[3][5]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[3].final_val_reg[3][5]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[3].final_val_reg[3][5]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[4].final_val_reg[4][5]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[4].final_val_reg[4][5]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[4].final_val_reg[4][5]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[4].final_val_reg[4][5]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[5].final_val_reg[5][5]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[5].final_val_reg[5][5]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[5].final_val_reg[5][5]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[5].final_val_reg[5][5]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[6].final_val_reg[6][5]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[6].final_val_reg[6][5]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[6].final_val_reg[6][5]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[6].final_val_reg[6][5]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[7].final_val_reg[7][5]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[7].final_val_reg[7][5]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_gen_final_tap[7].final_val_reg[7][5]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_gen_final_tap[7].final_val_reg[7][5]_i_4_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[0][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][0] ),
        .O(\corse_cnt[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[0][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][1] ),
        .O(\corse_cnt[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[0][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][2] ),
        .O(\corse_cnt[0][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0202A202)) 
    \corse_cnt[0][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(\corse_cnt[0][2]_i_3_n_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\corse_cnt[0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF2FFF2FFF2F0000)) 
    \corse_cnt[0][2]_i_3 
       (.I0(wr_level_done_r5),
        .I1(wrlvl_byte_redo),
        .I2(\corse_dec[0][2]_i_6_n_0 ),
        .I3(\fine_inc_reg[6][0]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] ),
        .I5(\po_stg2_wrcal_cnt_reg[0]_1 ),
        .O(\corse_cnt[0][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[1][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][0] ),
        .O(\corse_cnt[1][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \corse_cnt[1][0]_i_2 
       (.I0(dq_cnt_inc_reg_n_0),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I3(Q[2]),
        .I4(\corse_cnt[1][0]_i_3_n_0 ),
        .O(\corse_cnt[1][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE222E2)) 
    \corse_cnt[1][0]_i_3 
       (.I0(\wrlvl_redo_corse_inc_reg[1]_i_4_n_0 ),
        .I1(Q[0]),
        .I2(\corse_cnt[1][0]_i_4_n_0 ),
        .I3(\fine_inc_reg[6][0]_0 ),
        .I4(\corse_cnt[1][0]_i_5_n_0 ),
        .I5(Q[2]),
        .O(\corse_cnt[1][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[1][0]_i_4 
       (.I0(\final_coarse_tap_reg[3]__0 [0]),
        .I1(\final_coarse_tap_reg[2]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\final_coarse_tap_reg[1]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\final_coarse_tap_reg[0]__0 [0]),
        .O(\corse_cnt[1][0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[1][0]_i_5 
       (.I0(\final_coarse_tap_reg[7]__0 [0]),
        .I1(\final_coarse_tap_reg[6]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\final_coarse_tap_reg[5]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\final_coarse_tap_reg[4]__0 [0]),
        .O(\corse_cnt[1][0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[1][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][1] ),
        .O(\corse_cnt[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8BB8BBBB8BB88888)) 
    \corse_cnt[1][1]_i_2 
       (.I0(dq_cnt_inc_reg_n_0),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I3(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I4(Q[2]),
        .I5(\corse_cnt[1][1]_i_3_n_0 ),
        .O(\corse_cnt[1][1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_cnt[1][1]_i_3 
       (.I0(\corse_cnt[1][1]_i_4_n_0 ),
        .I1(\fine_inc_reg[6][0]_0 ),
        .I2(\corse_cnt[1][1]_i_5_n_0 ),
        .I3(Q[0]),
        .I4(\wrlvl_redo_corse_inc_reg[1]_i_3_n_0 ),
        .O(\corse_cnt[1][1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[1][1]_i_4 
       (.I0(\final_coarse_tap_reg[7]__0 [1]),
        .I1(\final_coarse_tap_reg[6]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\final_coarse_tap_reg[5]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\final_coarse_tap_reg[4]__0 [1]),
        .O(\corse_cnt[1][1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[1][1]_i_5 
       (.I0(\final_coarse_tap_reg[3]__0 [1]),
        .I1(\final_coarse_tap_reg[2]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\final_coarse_tap_reg[1]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\final_coarse_tap_reg[0]__0 [1]),
        .O(\corse_cnt[1][1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[1][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][2] ),
        .O(\corse_cnt[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[1][2]_i_10 
       (.I0(\final_coarse_tap_reg[7]__0 [2]),
        .I1(\final_coarse_tap_reg[6]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\final_coarse_tap_reg[5]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\final_coarse_tap_reg[4]__0 [2]),
        .O(\corse_cnt[1][2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAABEEEAAAA)) 
    \corse_cnt[1][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_4_n_0 ),
        .I1(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I3(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I4(Q[2]),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\corse_cnt[1][2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0202A202)) 
    \corse_cnt[1][2]_i_3 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(\corse_cnt[1][2]_i_6_n_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\corse_cnt[1][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \corse_cnt[1][2]_i_4 
       (.I0(dq_cnt_inc_reg_n_0),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wrlvl_redo_corse_inc_reg[1]_i_5_n_0 ),
        .I3(Q[0]),
        .I4(\corse_cnt_reg[1][2]_i_7_n_0 ),
        .I5(Q[2]),
        .O(\corse_cnt[1][2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT4 #(
    .INIT(16'h0015)) 
    \corse_cnt[1][2]_i_5 
       (.I0(Q[0]),
        .I1(dq_cnt_inc_reg_n_0),
        .I2(Q[1]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .O(\corse_cnt[1][2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h2FFF2FFF2FFF0000)) 
    \corse_cnt[1][2]_i_6 
       (.I0(wr_level_done_r5),
        .I1(wrlvl_byte_redo),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\wl_state_r[4]_i_6_n_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[2] ),
        .I5(\po_stg2_wrcal_cnt_reg[1] ),
        .O(\corse_cnt[1][2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[1][2]_i_9 
       (.I0(\final_coarse_tap_reg[3]__0 [2]),
        .I1(\final_coarse_tap_reg[2]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\final_coarse_tap_reg[1]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\final_coarse_tap_reg[0]__0 [2]),
        .O(\corse_cnt[1][2]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[2][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[2][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[2][0] ),
        .O(\corse_cnt[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[2][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[2][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[2][1] ),
        .O(\corse_cnt[2][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[2][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[2][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[2][2] ),
        .O(\corse_cnt[2][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0202A202)) 
    \corse_cnt[2][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(\corse_cnt[2][2]_i_3_n_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\corse_cnt[2][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEFEFEF00EFEFEFEF)) 
    \corse_cnt[2][2]_i_3 
       (.I0(\corse_cnt_reg[2][0]_0 ),
        .I1(\smallest_reg[7][0]_0 ),
        .I2(\corse_dec_reg[2][0]_0 ),
        .I3(\po_stg2_wrcal_cnt_reg[2] ),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .O(\corse_cnt[2][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \corse_cnt[2][2]_i_4 
       (.I0(wr_level_done_r5),
        .I1(wrlvl_byte_redo),
        .O(\corse_cnt_reg[2][0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[3][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[3][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[3][0] ),
        .O(\corse_cnt[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[3][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[3][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[3][1] ),
        .O(\corse_cnt[3][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[3][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[3][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[3][2] ),
        .O(\corse_cnt[3][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0202A202)) 
    \corse_cnt[3][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(wr_level_done_r5_reg_0),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\corse_cnt[3][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFFFFFFFFFFFF)) 
    \corse_cnt[3][2]_i_4 
       (.I0(\fine_inc_reg[6][0]_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(dqs_count_r[1]),
        .I5(dqs_count_r[0]),
        .O(\corse_cnt_reg[3][0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[4][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[4][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[4][0] ),
        .O(\corse_cnt[4][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[4][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[4][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[4][1] ),
        .O(\corse_cnt[4][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[4][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[4][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[4][2] ),
        .O(\corse_cnt[4][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0202A202)) 
    \corse_cnt[4][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(\corse_cnt[4][2]_i_3_n_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\corse_cnt[4][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h75FF75FF75FF0000)) 
    \corse_cnt[4][2]_i_3 
       (.I0(\corse_dec[0][2]_i_6_n_0 ),
        .I1(wrlvl_byte_redo),
        .I2(wr_level_done_r5),
        .I3(\fine_inc_reg[6][0]_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[3] ),
        .I5(\po_stg2_wrcal_cnt_reg[0]_1 ),
        .O(\corse_cnt[4][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[5][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[5][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[5][0] ),
        .O(\corse_cnt[5][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[5][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[5][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[5][1] ),
        .O(\corse_cnt[5][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[5][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[5][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[5][2] ),
        .O(\corse_cnt[5][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0202A202)) 
    \corse_cnt[5][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(\corse_cnt[5][2]_i_3_n_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\corse_cnt[5][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2FFF2FFF2FFF0000)) 
    \corse_cnt[5][2]_i_3 
       (.I0(wr_level_done_r5),
        .I1(wrlvl_byte_redo),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\wl_state_r[4]_i_6_n_0 ),
        .I4(\po_stg2_wrcal_cnt_reg[3] ),
        .I5(\po_stg2_wrcal_cnt_reg[1] ),
        .O(\corse_cnt[5][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[6][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[6][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[6][0] ),
        .O(\corse_cnt[6][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[6][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[6][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[6][1] ),
        .O(\corse_cnt[6][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[6][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[6][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[6][2] ),
        .O(\corse_cnt[6][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT5 #(
    .INIT(32'h0202A202)) 
    \corse_cnt[6][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[0]_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\corse_cnt[6][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[7][0]_i_1 
       (.I0(\corse_cnt[1][0]_i_2_n_0 ),
        .I1(\corse_cnt[7][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[7][0] ),
        .O(\corse_cnt[7][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[7][1]_i_1 
       (.I0(\corse_cnt[1][1]_i_2_n_0 ),
        .I1(\corse_cnt[7][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[7][1] ),
        .O(\corse_cnt[7][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[7][2]_i_1 
       (.I0(\corse_cnt[1][2]_i_2_n_0 ),
        .I1(\corse_cnt[7][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[7][2] ),
        .O(\corse_cnt[7][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000888AAAAA888A)) 
    \corse_cnt[7][2]_i_2 
       (.I0(\corse_cnt[1][2]_i_5_n_0 ),
        .I1(\corse_cnt[7][2]_i_3_n_0 ),
        .I2(\po_stg2_wrcal_cnt_reg[0] ),
        .I3(\po_stg2_wrcal_cnt_reg[3] ),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .I5(\corse_cnt[7][2]_i_5_n_0 ),
        .O(\corse_cnt[7][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040000000)) 
    \corse_cnt[7][2]_i_3 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\wl_state_r[4]_i_6_n_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(\fine_inc_reg[6][0]_0 ),
        .I5(\corse_cnt_reg[2][0]_0 ),
        .O(\corse_cnt[7][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \corse_cnt[7][2]_i_5 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\corse_cnt[7][2]_i_5_n_0 ));
  FDRE \corse_cnt_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[0][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[0][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[0][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][2] ),
        .R(SR));
  FDRE \corse_cnt_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[1][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[1][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[1][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][2] ),
        .R(SR));
  MUXF7 \corse_cnt_reg[1][2]_i_7 
       (.I0(\corse_cnt[1][2]_i_9_n_0 ),
        .I1(\corse_cnt[1][2]_i_10_n_0 ),
        .O(\corse_cnt_reg[1][2]_i_7_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_cnt_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[2][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[2][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[2][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[2][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[2][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[2][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[2][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[2][2] ),
        .R(SR));
  FDRE \corse_cnt_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[3][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[3][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[3][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[3][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[3][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[3][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[3][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[3][2] ),
        .R(SR));
  FDRE \corse_cnt_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[4][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[4][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[4][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[4][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[4][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[4][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[4][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[4][2] ),
        .R(SR));
  FDRE \corse_cnt_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[5][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[5][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[5][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[5][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[5][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[5][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[5][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[5][2] ),
        .R(SR));
  FDRE \corse_cnt_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[6][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[6][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[6][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[6][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[6][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[6][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[6][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[6][2] ),
        .R(SR));
  FDRE \corse_cnt_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[7][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[7][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \corse_cnt_reg[7][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[7][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[7][1] ),
        .R(SR));
  FDRE \corse_cnt_reg[7][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[7][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[7][2] ),
        .R(SR));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[0][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[0][0] ),
        .I4(\corse_dec[0][2]_i_3_n_0 ),
        .I5(\corse_dec_reg[0]__0 [0]),
        .O(\corse_dec[0][0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \corse_dec[0][0]_i_2 
       (.I0(\corse_dec_reg[0][2]_i_5_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_4_n_0 ),
        .O(\corse_dec[0][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][0]_i_4 
       (.I0(\corse_dec_reg[3]__0 [0]),
        .I1(\corse_dec_reg[2]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_dec_reg[1]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_dec_reg[0]__0 [0]),
        .O(\corse_dec[0][0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][0]_i_5 
       (.I0(\corse_dec_reg[7]__0 [0]),
        .I1(\corse_dec_reg[6]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_dec_reg[5]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_dec_reg[4]__0 [0]),
        .O(\corse_dec[0][0]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[0][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[0][1] ),
        .I3(\corse_dec[0][2]_i_3_n_0 ),
        .I4(\corse_dec_reg[0]__0 [1]),
        .O(\corse_dec[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'hA4)) 
    \corse_dec[0][1]_i_2 
       (.I0(\corse_dec_reg[0][2]_i_4_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_5_n_0 ),
        .I2(\corse_dec_reg[0][0]_i_3_n_0 ),
        .O(\corse_dec[0][1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[0][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[0][2] ),
        .I3(\corse_dec[0][2]_i_3_n_0 ),
        .I4(\corse_dec_reg[0]__0 [2]),
        .O(\corse_dec[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_10 
       (.I0(\corse_dec_reg[3]__0 [2]),
        .I1(\corse_dec_reg[2]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_dec_reg[1]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_dec_reg[0]__0 [2]),
        .O(\corse_dec[0][2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_11 
       (.I0(\corse_dec_reg[7]__0 [2]),
        .I1(\corse_dec_reg[6]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_dec_reg[5]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_dec_reg[4]__0 [2]),
        .O(\corse_dec[0][2]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT4 #(
    .INIT(16'hE000)) 
    \corse_dec[0][2]_i_2 
       (.I0(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_4_n_0 ),
        .I2(\corse_dec_reg[0][2]_i_5_n_0 ),
        .I3(Q[2]),
        .O(\corse_dec[0][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT5 #(
    .INIT(32'h22F20000)) 
    \corse_dec[0][2]_i_3 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(\corse_dec[0][2]_i_6_n_0 ),
        .I3(\smallest_reg[7][0]_0 ),
        .I4(\corse_dec[0][2]_i_7_n_0 ),
        .O(\corse_dec[0][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT5 #(
    .INIT(32'h00000010)) 
    \corse_dec[0][2]_i_6 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\dqs_count_r_reg[3]_0 ),
        .O(\corse_dec[0][2]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \corse_dec[0][2]_i_7 
       (.I0(Q[0]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .O(\corse_dec[0][2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_8 
       (.I0(\corse_dec_reg[3]__0 [1]),
        .I1(\corse_dec_reg[2]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_dec_reg[1]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_dec_reg[0]__0 [1]),
        .O(\corse_dec[0][2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_9 
       (.I0(\corse_dec_reg[7]__0 [1]),
        .I1(\corse_dec_reg[6]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_dec_reg[5]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_dec_reg[4]__0 [1]),
        .O(\corse_dec[0][2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[1][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[1][0] ),
        .I4(\corse_dec[1][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[1]__0 [0]),
        .O(\corse_dec[1][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[1][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[1][1] ),
        .I3(\corse_dec[1][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[1]__0 [1]),
        .O(\corse_dec[1][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[1][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[1][2] ),
        .I3(\corse_dec[1][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[1]__0 [2]),
        .O(\corse_dec[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000002C0000)) 
    \corse_dec[1][2]_i_2 
       (.I0(\fine_inc[1][5]_i_3_n_0 ),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\corse_dec[1][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[2][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[2][0] ),
        .I4(\corse_dec[2][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[2]__0 [0]),
        .O(\corse_dec[2][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[2][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[2][1] ),
        .I3(\corse_dec[2][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[2]__0 [1]),
        .O(\corse_dec[2][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[2][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[2][2] ),
        .I3(\corse_dec[2][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[2]__0 [2]),
        .O(\corse_dec[2][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT5 #(
    .INIT(32'h2F220000)) 
    \corse_dec[2][2]_i_2 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(\corse_dec_reg[2][0]_0 ),
        .I4(\corse_dec[0][2]_i_7_n_0 ),
        .O(\corse_dec[2][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT5 #(
    .INIT(32'h00000020)) 
    \corse_dec[2][2]_i_3 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\dqs_count_r_reg[3]_0 ),
        .O(\corse_dec_reg[2][0]_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[3][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[3][0] ),
        .I4(\corse_dec[3][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[3]__0 [0]),
        .O(\corse_dec[3][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[3][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[3][1] ),
        .I3(\corse_dec[3][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[3]__0 [1]),
        .O(\corse_dec[3][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[3][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[3][2] ),
        .I3(\corse_dec[3][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[3]__0 [2]),
        .O(\corse_dec[3][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0808080808080828)) 
    \corse_dec[3][2]_i_2 
       (.I0(\corse_dec[0][2]_i_7_n_0 ),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(\smallest_reg[7][0]_0 ),
        .I4(\dqs_count_r_reg[3]_0 ),
        .I5(\corse_dec[3][2]_i_3_n_0 ),
        .O(\corse_dec[3][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \corse_dec[3][2]_i_3 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .O(\corse_dec[3][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[4][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[4][0] ),
        .I4(\corse_dec[4][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[4]__0 [0]),
        .O(\corse_dec[4][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[4][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[4][1] ),
        .I3(\corse_dec[4][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[4]__0 [1]),
        .O(\corse_dec[4][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[4][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[4][2] ),
        .I3(\corse_dec[4][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[4]__0 [2]),
        .O(\corse_dec[4][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT5 #(
    .INIT(32'hF2002200)) 
    \corse_dec[4][2]_i_2 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(\corse_dec[0][2]_i_7_n_0 ),
        .I4(\corse_dec[0][2]_i_6_n_0 ),
        .O(\corse_dec[4][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[5][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[5][0] ),
        .I4(\corse_dec[5][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[5]__0 [0]),
        .O(\corse_dec[5][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[5][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[5][1] ),
        .I3(\corse_dec[5][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[5]__0 [1]),
        .O(\corse_dec[5][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[5][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[5][2] ),
        .I3(\corse_dec[5][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[5]__0 [2]),
        .O(\corse_dec[5][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000002C0000)) 
    \corse_dec[5][2]_i_2 
       (.I0(\fine_inc[5][5]_i_3_n_0 ),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\corse_dec[5][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[6][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[6][0] ),
        .I4(\corse_dec[6][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[6]__0 [0]),
        .O(\corse_dec[6][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[6][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[6][1] ),
        .I3(\corse_dec[6][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[6]__0 [1]),
        .O(\corse_dec[6][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[6][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[6][2] ),
        .I3(\corse_dec[6][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[6]__0 [2]),
        .O(\corse_dec[6][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT5 #(
    .INIT(32'hF2002200)) 
    \corse_dec[6][2]_i_2 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(\corse_dec[0][2]_i_7_n_0 ),
        .I4(\corse_dec_reg[2][0]_0 ),
        .O(\corse_dec[6][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \corse_dec[7][0]_i_1 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(Q[2]),
        .I3(\corse_cnt_reg_n_0_[7][0] ),
        .I4(\corse_dec[7][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[7]__0 [0]),
        .O(\corse_dec[7][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \corse_dec[7][1]_i_1 
       (.I0(\corse_dec[0][1]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[7][1] ),
        .I3(\corse_dec[7][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[7]__0 [1]),
        .O(\corse_dec[7][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBAFFBA00)) 
    \corse_dec[7][2]_i_1 
       (.I0(\corse_dec[0][2]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\corse_cnt_reg_n_0_[7][2] ),
        .I3(\corse_dec[7][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[7]__0 [2]),
        .O(\corse_dec[7][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0004040000000400)) 
    \corse_dec[7][2]_i_2 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .O(\corse_dec[7][2]_i_2_n_0 ));
  FDRE \corse_dec_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[0][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  MUXF7 \corse_dec_reg[0][0]_i_3 
       (.I0(\corse_dec[0][0]_i_4_n_0 ),
        .I1(\corse_dec[0][0]_i_5_n_0 ),
        .O(\corse_dec_reg[0][0]_i_3_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_dec_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[0][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[0][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  MUXF7 \corse_dec_reg[0][2]_i_4 
       (.I0(\corse_dec[0][2]_i_8_n_0 ),
        .I1(\corse_dec[0][2]_i_9_n_0 ),
        .O(\corse_dec_reg[0][2]_i_4_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \corse_dec_reg[0][2]_i_5 
       (.I0(\corse_dec[0][2]_i_10_n_0 ),
        .I1(\corse_dec[0][2]_i_11_n_0 ),
        .O(\corse_dec_reg[0][2]_i_5_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_dec_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[1][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[1][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[1][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[2][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[2]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[2][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[2][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[2]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[2][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[2][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[2]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[3][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[3]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[3][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[3][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[3]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[3][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[3][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[3]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[4][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[4]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[4][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[4][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[4]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[4][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[4][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[4]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[5][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[5]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[5][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[5][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[5]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[5][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[5][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[5]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[6][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[6]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[6][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[6][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[6]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[6][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[6][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[6]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[7][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[7]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[7][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[7][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[7]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_dec_reg[7][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[7][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[7]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[0][0]_i_1 
       (.I0(\corse_inc[0][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[0][5]_i_5_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[0]__0 [0]),
        .O(\corse_inc[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[0][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[0]__0 [0]),
        .O(\corse_inc[0][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[0][1]_i_1 
       (.I0(\corse_inc[0][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[0][5]_i_5_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[0]__0 [1]),
        .O(\corse_inc[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[0][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[0]__0 [1]),
        .O(\corse_inc[0][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_5 
       (.I0(\corse_inc_reg[3]__0 [0]),
        .I1(\corse_inc_reg[2]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_inc_reg[1]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_inc_reg[0]__0 [0]),
        .O(\corse_inc[0][1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_6 
       (.I0(\corse_inc_reg[7]__0 [0]),
        .I1(\corse_inc_reg[6]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_inc_reg[5]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_inc_reg[4]__0 [0]),
        .O(\corse_inc[0][1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_7 
       (.I0(\corse_inc_reg[3]__0 [1]),
        .I1(\corse_inc_reg[2]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_inc_reg[1]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_inc_reg[0]__0 [1]),
        .O(\corse_inc[0][1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_8 
       (.I0(\corse_inc_reg[7]__0 [1]),
        .I1(\corse_inc_reg[6]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_inc_reg[5]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_inc_reg[4]__0 [1]),
        .O(\corse_inc[0][1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[0][2]_i_1 
       (.I0(\corse_inc[0][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[0][5]_i_5_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[0]__0 [2]),
        .O(\corse_inc[0][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[0][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[0]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[0][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \corse_inc[0][2]_i_3 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[0]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[2]),
        .O(\corse_inc[0][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'hFFFB)) 
    \corse_inc[0][2]_i_4 
       (.I0(\wl_state_r[4]_i_16_n_0 ),
        .I1(wr_level_done_r5),
        .I2(wrlvl_byte_redo),
        .I3(Q[1]),
        .O(\corse_inc[0][2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \corse_inc[0][2]_i_5 
       (.I0(wr_level_done_r4),
        .I1(wr_level_done_r5),
        .I2(Q[1]),
        .O(\corse_inc[0][2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \corse_inc[0][2]_i_7 
       (.I0(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .O(\corse_inc[0][2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][2]_i_8 
       (.I0(\corse_inc_reg[3]__0 [2]),
        .I1(\corse_inc_reg[2]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_inc_reg[1]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_inc_reg[0]__0 [2]),
        .O(\corse_inc[0][2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][2]_i_9 
       (.I0(\corse_inc_reg[7]__0 [2]),
        .I1(\corse_inc_reg[6]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_inc_reg[5]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_inc_reg[4]__0 [2]),
        .O(\corse_inc[0][2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[1][0]_i_1 
       (.I0(\corse_inc[1][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[1]__0 [0]),
        .O(\corse_inc[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[1][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[1]__0 [0]),
        .O(\corse_inc[1][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[1][1]_i_1 
       (.I0(\corse_inc[1][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[1]__0 [1]),
        .O(\corse_inc[1][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[1][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[1]__0 [1]),
        .O(\corse_inc[1][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[1][2]_i_1 
       (.I0(\corse_inc[1][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[1]__0 [2]),
        .O(\corse_inc[1][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[1][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[1]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[1][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[2][0]_i_1 
       (.I0(\corse_inc[2][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[2]__0 [0]),
        .O(\corse_inc[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[2][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[2]__0 [0]),
        .O(\corse_inc[2][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[2][1]_i_1 
       (.I0(\corse_inc[2][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[2]__0 [1]),
        .O(\corse_inc[2][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[2][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[2]__0 [1]),
        .O(\corse_inc[2][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[2][2]_i_1 
       (.I0(\corse_inc[2][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[2]__0 [2]),
        .O(\corse_inc[2][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[2][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[2]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[2][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[3][0]_i_1 
       (.I0(\corse_inc[3][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[3]__0 [0]),
        .O(\corse_inc[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[3][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[3]__0 [0]),
        .O(\corse_inc[3][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[3][1]_i_1 
       (.I0(\corse_inc[3][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[3]__0 [1]),
        .O(\corse_inc[3][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[3][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[3]__0 [1]),
        .O(\corse_inc[3][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[3][2]_i_1 
       (.I0(\corse_inc[3][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[3]__0 [2]),
        .O(\corse_inc[3][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[3][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[3]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[3][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[4][0]_i_1 
       (.I0(\corse_inc[4][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[4]__0 [0]),
        .O(\corse_inc[4][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[4][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[4]__0 [0]),
        .O(\corse_inc[4][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[4][1]_i_1 
       (.I0(\corse_inc[4][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[4]__0 [1]),
        .O(\corse_inc[4][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[4][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[4]__0 [1]),
        .O(\corse_inc[4][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[4][2]_i_1 
       (.I0(\corse_inc[4][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[4]__0 [2]),
        .O(\corse_inc[4][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[4][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[4]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[4][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[5][0]_i_1 
       (.I0(\corse_inc[5][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[5]__0 [0]),
        .O(\corse_inc[5][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[5][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[5]__0 [0]),
        .O(\corse_inc[5][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[5][1]_i_1 
       (.I0(\corse_inc[5][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[5]__0 [1]),
        .O(\corse_inc[5][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[5][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[5]__0 [1]),
        .O(\corse_inc[5][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[5][2]_i_1 
       (.I0(\corse_inc[5][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[5]__0 [2]),
        .O(\corse_inc[5][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[5][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[5]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[5][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[6][0]_i_1 
       (.I0(\corse_inc[6][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[6]__0 [0]),
        .O(\corse_inc[6][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[6][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[6]__0 [0]),
        .O(\corse_inc[6][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[6][1]_i_1 
       (.I0(\corse_inc[6][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[6]__0 [1]),
        .O(\corse_inc[6][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[6][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[6]__0 [1]),
        .O(\corse_inc[6][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[6][2]_i_1 
       (.I0(\corse_inc[6][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[6]__0 [2]),
        .O(\corse_inc[6][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[6][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[6]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[6][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[7][0]_i_1 
       (.I0(\corse_inc[7][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[7]__0 [0]),
        .O(\corse_inc[7][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \corse_inc[7][0]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg[7]__0 [0]),
        .O(\corse_inc[7][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[7][1]_i_1 
       (.I0(\corse_inc[7][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[7]__0 [1]),
        .O(\corse_inc[7][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \corse_inc[7][1]_i_2 
       (.I0(Q[1]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\final_coarse_tap_reg[7]__0 [1]),
        .O(\corse_inc[7][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFBBBB00808888)) 
    \corse_inc[7][2]_i_1 
       (.I0(\corse_inc[7][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[7]__0 [2]),
        .O(\corse_inc[7][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \corse_inc[7][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(\final_coarse_tap_reg[7]__0 [2]),
        .I3(Q[1]),
        .O(\corse_inc[7][2]_i_2_n_0 ));
  FDRE \corse_inc_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[0][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[0]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[0][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[0]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  MUXF7 \corse_inc_reg[0][1]_i_3 
       (.I0(\corse_inc[0][1]_i_5_n_0 ),
        .I1(\corse_inc[0][1]_i_6_n_0 ),
        .O(\corse_inc_reg[0][1]_i_3_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \corse_inc_reg[0][1]_i_4 
       (.I0(\corse_inc[0][1]_i_7_n_0 ),
        .I1(\corse_inc[0][1]_i_8_n_0 ),
        .O(\corse_inc_reg[0][1]_i_4_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_inc_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[0][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[0]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  MUXF7 \corse_inc_reg[0][2]_i_6 
       (.I0(\corse_inc[0][2]_i_8_n_0 ),
        .I1(\corse_inc[0][2]_i_9_n_0 ),
        .O(\corse_inc_reg[0][2]_i_6_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_inc_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[1][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[1]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[1][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[1]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[1][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[1]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[2][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[2]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[2][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[2][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[2]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[2][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[2][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[2]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[3][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[3]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[3][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[3][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[3]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[3][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[3][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[3]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[4][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[4]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[4][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[4][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[4]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[4][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[4][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[4]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[5][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[5]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[5][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[5][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[5]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[5][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[5][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[5]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[6][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[6]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[6][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[6][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[6]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[6][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[6][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[6]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[7][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[7]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \corse_inc_reg[7][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[7][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[7]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \corse_inc_reg[7][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[7][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[7]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  LUT3 #(
    .INIT(8'hF7)) 
    delay_dec_done_i_2
       (.I0(dqs_po_dec_done),
        .I1(pi_fine_dly_dec_done),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .O(delay_dec_done_reg));
  LUT5 #(
    .INIT(32'h45FF4500)) 
    dq_cnt_inc_i_1
       (.I0(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(wrlvl_byte_redo),
        .I3(dq_cnt_inc_i_2_n_0),
        .I4(dq_cnt_inc_reg_n_0),
        .O(dq_cnt_inc_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT5 #(
    .INIT(32'h04400000)) 
    dq_cnt_inc_i_2
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(Q[1]),
        .O(dq_cnt_inc_i_2_n_0));
  FDSE dq_cnt_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dq_cnt_inc_i_1_n_0),
        .Q(dq_cnt_inc_reg_n_0),
        .S(SR));
  LUT6 #(
    .INIT(64'hFFFFFFFF44470000)) 
    \dqs_count_r[0]_i_1 
       (.I0(\dqs_count_r[0]_i_2_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(\dqs_count_r[0]_i_3_n_0 ),
        .I4(Q[0]),
        .I5(\dqs_count_r[0]_i_4_n_0 ),
        .O(\dqs_count_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h66662666FFFFFFFF)) 
    \dqs_count_r[0]_i_2 
       (.I0(wrlvl_byte_redo),
        .I1(dqs_count_r[0]),
        .I2(dqs_count_r[1]),
        .I3(\fine_inc_reg[6][0]_0 ),
        .I4(\dqs_count_r_reg[3]_0 ),
        .I5(Q[1]),
        .O(\dqs_count_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h55150000AAAAFFFF)) 
    \dqs_count_r[0]_i_3 
       (.I0(\dqs_count_r[2]_i_8_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\dqs_count_r[3]_i_7_n_0 ),
        .I5(dqs_count_r[0]),
        .O(\dqs_count_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFCFCECCCDCFCDCFC)) 
    \dqs_count_r[0]_i_4 
       (.I0(\dqs_count_r[2]_i_8_n_0 ),
        .I1(\dqs_count_r[0]_i_5_n_0 ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .I5(dqs_count_r[0]),
        .O(\dqs_count_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h88888A8888888088)) 
    \dqs_count_r[0]_i_5 
       (.I0(\dqs_count_r[2]_i_11_n_0 ),
        .I1(dqs_count_r[0]),
        .I2(Q[1]),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .O(\dqs_count_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44470000)) 
    \dqs_count_r[0]_rep_i_1 
       (.I0(\dqs_count_r[0]_i_2_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(\dqs_count_r[0]_i_3_n_0 ),
        .I4(Q[0]),
        .I5(\dqs_count_r[0]_i_4_n_0 ),
        .O(\dqs_count_r[0]_rep_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44470000)) 
    \dqs_count_r[1]_i_1 
       (.I0(\dqs_count_r[1]_i_2_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(\dqs_count_r[1]_i_3_n_0 ),
        .I4(Q[0]),
        .I5(\dqs_count_r[1]_i_4_n_0 ),
        .O(\dqs_count_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h55FF55FFDF5555FF)) 
    \dqs_count_r[1]_i_2 
       (.I0(Q[1]),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .I5(wrlvl_byte_redo),
        .O(\dqs_count_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h51000000AAFFFFFF)) 
    \dqs_count_r[1]_i_3 
       (.I0(\dqs_count_r[2]_i_8_n_0 ),
        .I1(\fine_inc_reg[6][0]_0 ),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(dqs_count_r[0]),
        .I4(\dqs_count_r[3]_i_7_n_0 ),
        .I5(dqs_count_r[1]),
        .O(\dqs_count_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF8000B0F0)) 
    \dqs_count_r[1]_i_4 
       (.I0(dqs_count_r[1]),
        .I1(\dqs_count_r[2]_i_8_n_0 ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\dqs_count_r[1]_i_5_n_0 ),
        .I5(\dqs_count_r[1]_i_6_n_0 ),
        .O(\dqs_count_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'hD00F)) 
    \dqs_count_r[1]_i_5 
       (.I0(\fine_inc_reg[6][0]_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .O(\dqs_count_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h88888A8888888088)) 
    \dqs_count_r[1]_i_6 
       (.I0(\dqs_count_r[2]_i_11_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(Q[1]),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .O(\dqs_count_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF44470000)) 
    \dqs_count_r[1]_rep_i_1 
       (.I0(\dqs_count_r[1]_i_2_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(\dqs_count_r[1]_i_3_n_0 ),
        .I4(Q[0]),
        .I5(\dqs_count_r[1]_i_4_n_0 ),
        .O(\dqs_count_r[1]_rep_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFD0FFD0FFFFFFD0)) 
    \dqs_count_r[2]_i_1 
       (.I0(\dqs_count_r[2]_i_2_n_0 ),
        .I1(\dqs_count_r[2]_i_3_n_0 ),
        .I2(Q[0]),
        .I3(\dqs_count_r[2]_i_4_n_0 ),
        .I4(\dqs_count_r[2]_i_5_n_0 ),
        .I5(\dqs_count_r[2]_i_6_n_0 ),
        .O(\dqs_count_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \dqs_count_r[2]_i_10 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .O(\dqs_count_r[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EFEFEF2F)) 
    \dqs_count_r[2]_i_11 
       (.I0(\dqs_count_r[2]_i_12_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(dq_cnt_inc_reg_n_0),
        .I4(wrlvl_byte_redo),
        .I5(Q[0]),
        .O(\dqs_count_r[2]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \dqs_count_r[2]_i_12 
       (.I0(wr_level_done_r5),
        .I1(wr_level_done_r4),
        .O(\dqs_count_r[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h7777FFFFF7777FFF)) 
    \dqs_count_r[2]_i_2 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[1]),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(\fine_inc_reg[6][0]_0 ),
        .I5(\dqs_count_r[2]_i_7_n_0 ),
        .O(\dqs_count_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000B0001000F0000)) 
    \dqs_count_r[2]_i_3 
       (.I0(\dqs_count_r[2]_i_8_n_0 ),
        .I1(\dqs_count_r[2]_i_9_n_0 ),
        .I2(Q[1]),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\fine_inc_reg[6][0]_0 ),
        .I5(\dqs_count_r[3]_i_7_n_0 ),
        .O(\dqs_count_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF1FFF11111111111)) 
    \dqs_count_r[2]_i_4 
       (.I0(\dqs_count_r[2]_i_9_n_0 ),
        .I1(\dqs_count_r[2]_i_10_n_0 ),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [2]),
        .I3(\wl_tap_count_r[5]_i_3_n_0 ),
        .I4(\smallest_reg[7][0]_0 ),
        .I5(\dqs_count_r[2]_i_11_n_0 ),
        .O(\dqs_count_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \dqs_count_r[2]_i_5 
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .O(\dqs_count_r[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT5 #(
    .INIT(32'h4000AFFF)) 
    \dqs_count_r[2]_i_6 
       (.I0(\dqs_count_r[2]_i_8_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(\fine_inc_reg[6][0]_0 ),
        .O(\dqs_count_r[2]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT5 #(
    .INIT(32'hAAAAEAAA)) 
    \dqs_count_r[2]_i_7 
       (.I0(wrlvl_byte_redo),
        .I1(dqs_count_r[0]),
        .I2(dqs_count_r[1]),
        .I3(\fine_inc_reg[6][0]_0 ),
        .I4(\dqs_count_r_reg[3]_0 ),
        .O(\dqs_count_r[2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT4 #(
    .INIT(16'hFEFF)) 
    \dqs_count_r[2]_i_8 
       (.I0(\fine_inc[0][5]_i_12_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\fine_inc[0][2]_i_2_n_0 ),
        .O(\dqs_count_r[2]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT4 #(
    .INIT(16'h803F)) 
    \dqs_count_r[2]_i_9 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .I3(\fine_inc_reg[6][0]_0 ),
        .O(\dqs_count_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFD0FFD0FFFFFFD0)) 
    \dqs_count_r[2]_rep__0_i_1 
       (.I0(\dqs_count_r[2]_i_2_n_0 ),
        .I1(\dqs_count_r[2]_i_3_n_0 ),
        .I2(Q[0]),
        .I3(\dqs_count_r[2]_i_4_n_0 ),
        .I4(\dqs_count_r[2]_i_5_n_0 ),
        .I5(\dqs_count_r[2]_i_6_n_0 ),
        .O(\dqs_count_r[2]_rep__0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFD0FFD0FFFFFFD0)) 
    \dqs_count_r[2]_rep_i_1 
       (.I0(\dqs_count_r[2]_i_2_n_0 ),
        .I1(\dqs_count_r[2]_i_3_n_0 ),
        .I2(Q[0]),
        .I3(\dqs_count_r[2]_i_4_n_0 ),
        .I4(\dqs_count_r[2]_i_5_n_0 ),
        .I5(\dqs_count_r[2]_i_6_n_0 ),
        .O(\dqs_count_r[2]_rep_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h20444029)) 
    \dqs_count_r[3]_i_1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .O(\dqs_count_r[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF8880)) 
    \dqs_count_r[3]_i_2 
       (.I0(Q[0]),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r[3]_i_3_n_0 ),
        .I3(\dqs_count_r[3]_i_4_n_0 ),
        .I4(\dqs_count_r[3]_i_5_n_0 ),
        .O(\dqs_count_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8888888808888888)) 
    \dqs_count_r[3]_i_3 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[1]),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .I4(\fine_inc_reg[6][0]_0 ),
        .I5(wrlvl_byte_redo),
        .O(\dqs_count_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h1011111111111111)) 
    \dqs_count_r[3]_i_4 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[1]),
        .I2(\fine_inc[0][5]_i_12_n_0 ),
        .I3(\dqs_count_r[3]_i_6_n_0 ),
        .I4(\fine_inc[0][2]_i_2_n_0 ),
        .I5(\dqs_count_r[3]_i_7_n_0 ),
        .O(\dqs_count_r[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hBABBBBBB)) 
    \dqs_count_r[3]_i_5 
       (.I0(\dqs_count_r[3]_i_8_n_0 ),
        .I1(\dqs_count_r[3]_i_9_n_0 ),
        .I2(\fine_inc[0][5]_i_12_n_0 ),
        .I3(\dqs_count_r[3]_i_6_n_0 ),
        .I4(\fine_inc[0][2]_i_2_n_0 ),
        .O(\dqs_count_r[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT5 #(
    .INIT(32'h00000080)) 
    \dqs_count_r[3]_i_6 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I4(\fine_inc_reg[0][2]_i_3_n_0 ),
        .O(\dqs_count_r[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \dqs_count_r[3]_i_7 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(wr_level_done_r5),
        .I2(wrlvl_byte_redo),
        .I3(\corse_inc[0][2]_i_7_n_0 ),
        .O(\dqs_count_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88888A8888888088)) 
    \dqs_count_r[3]_i_8 
       (.I0(\dqs_count_r[2]_i_11_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(Q[1]),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(\po_stg2_wrcal_cnt_reg[3]_0 [3]),
        .O(\dqs_count_r[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0080FFFFFFFFFFFF)) 
    \dqs_count_r[3]_i_9 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\dqs_count_r_reg[3]_0 ),
        .I5(\wl_state_r_reg_n_0_[2] ),
        .O(\dqs_count_r[3]_i_9_n_0 ));
  (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) 
  FDRE \dqs_count_r_reg[0] 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[0]_i_1_n_0 ),
        .Q(dqs_count_r[0]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) 
  FDRE \dqs_count_r_reg[0]_rep 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[0]_rep_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7][2]_1 ),
        .R(rstdiv0_sync_r1));
  (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) 
  FDRE \dqs_count_r_reg[1] 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[1]_i_1_n_0 ),
        .Q(dqs_count_r[1]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) 
  FDRE \dqs_count_r_reg[1]_rep 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[1]_rep_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7][2]_0 ),
        .R(rstdiv0_sync_r1));
  (* ORIG_CELL_NAME = "dqs_count_r_reg[2]" *) 
  FDRE \dqs_count_r_reg[2] 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[2]_i_1_n_0 ),
        .Q(dqs_count_r[2]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  (* ORIG_CELL_NAME = "dqs_count_r_reg[2]" *) 
  FDRE \dqs_count_r_reg[2]_rep 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[2]_rep_i_1_n_0 ),
        .Q(\smallest_reg[7][0]_0 ),
        .R(rstdiv0_sync_r1));
  (* ORIG_CELL_NAME = "dqs_count_r_reg[2]" *) 
  FDRE \dqs_count_r_reg[2]_rep__0 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[2]_rep__0_i_1_n_0 ),
        .Q(\fine_inc_reg[6][0]_0 ),
        .R(rstdiv0_sync_r1));
  FDRE \dqs_count_r_reg[3] 
       (.C(CLK),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[3]_i_2_n_0 ),
        .Q(\dqs_count_r_reg[3]_0 ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE dqs_po_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_dec_done),
        .Q(dqs_po_dec_done),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAFAAEAAE)) 
    dqs_po_en_stg2_f_i_1
       (.I0(dqs_po_en_stg2_f_reg_0),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(dqs_po_en_stg2_f_i_1_n_0));
  FDRE dqs_po_en_stg2_f_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_en_stg2_f_i_1_n_0),
        .Q(dqs_po_en_stg2_f),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT3 #(
    .INIT(8'h02)) 
    dqs_po_stg2_f_incdec_i_1
       (.I0(dqs_po_stg2_f_incdec_i_2_n_0),
        .I1(dqs_po_stg2_f_incdec_i_3_n_0),
        .I2(rstdiv0_sync_r1_reg_rep__23),
        .O(dqs_po_stg2_f_incdec0));
  LUT6 #(
    .INIT(64'h00000000EFFFFFBF)) 
    dqs_po_stg2_f_incdec_i_2
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .I5(dqs_po_en_stg2_f_reg_0),
        .O(dqs_po_stg2_f_incdec_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT5 #(
    .INIT(32'hFFFFDFFD)) 
    dqs_po_stg2_f_incdec_i_3
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[1]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(dqs_po_stg2_f_incdec_i_3_n_0));
  FDRE dqs_po_stg2_f_incdec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_stg2_f_incdec0),
        .Q(dqs_po_stg2_f_incdec),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    dqs_wl_po_stg2_c_incdec_i_1
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(Q[2]),
        .O(dqs_wl_po_stg2_c_incdec_i_1_n_0));
  FDRE dqs_wl_po_stg2_c_incdec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_wl_po_stg2_c_incdec_i_1_n_0),
        .Q(po_stg2_c_incdec),
        .R(rstdiv0_sync_r1_reg_rep__18));
  LUT6 #(
    .INIT(64'hFFEFDFFF00001000)) 
    dual_rnk_dec_i_1
       (.I0(Q[0]),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dual_rnk_dec),
        .O(dual_rnk_dec_i_1_n_0));
  FDRE dual_rnk_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dual_rnk_dec_i_1_n_0),
        .Q(dual_rnk_dec),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \final_coarse_tap_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]__0 [0]),
        .Q(\final_coarse_tap_reg[0]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]__0 [1]),
        .Q(\final_coarse_tap_reg[0]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]__0 [2]),
        .Q(\final_coarse_tap_reg[0]__0 [2]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]__0 [0]),
        .Q(\final_coarse_tap_reg[1]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]__0 [1]),
        .Q(\final_coarse_tap_reg[1]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]__0 [2]),
        .Q(\final_coarse_tap_reg[1]__0 [2]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][2]__0 [0]),
        .Q(\final_coarse_tap_reg[2]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[2][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][2]__0 [1]),
        .Q(\final_coarse_tap_reg[2]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[2][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][2]__0 [2]),
        .Q(\final_coarse_tap_reg[2]__0 [2]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][3]__0 [0]),
        .Q(\final_coarse_tap_reg[3]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[3][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][3]__0 [1]),
        .Q(\final_coarse_tap_reg[3]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[3][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][3]__0 [2]),
        .Q(\final_coarse_tap_reg[3]__0 [2]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][4]__0 [0]),
        .Q(\final_coarse_tap_reg[4]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[4][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][4]__0 [1]),
        .Q(\final_coarse_tap_reg[4]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[4][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][4]__0 [2]),
        .Q(\final_coarse_tap_reg[4]__0 [2]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][5]__0 [0]),
        .Q(\final_coarse_tap_reg[5]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[5][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][5]__0 [1]),
        .Q(\final_coarse_tap_reg[5]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[5][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][5]__0 [2]),
        .Q(\final_coarse_tap_reg[5]__0 [2]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][6]__0 [0]),
        .Q(\final_coarse_tap_reg[6]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[6][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][6]__0 [1]),
        .Q(\final_coarse_tap_reg[6]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[6][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][6]__0 [2]),
        .Q(\final_coarse_tap_reg[6]__0 [2]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][7]__0 [0]),
        .Q(\final_coarse_tap_reg[7]__0 [0]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[7][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][7]__0 [1]),
        .Q(\final_coarse_tap_reg[7]__0 [1]),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[7][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][7]__0 [2]),
        .Q(\final_coarse_tap_reg[7]__0 [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT5 #(
    .INIT(32'h0A2AFAEA)) 
    \fine_dec_cnt[0]_i_1 
       (.I0(\wl_tap_count_r_reg_n_0_[0] ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[0]),
        .I4(\fine_dec_cnt_reg_n_0_[0] ),
        .O(\fine_dec_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFAEA0A2A0A2AFAEA)) 
    \fine_dec_cnt[1]_i_1 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[0]),
        .I4(\fine_dec_cnt_reg_n_0_[0] ),
        .I5(\fine_dec_cnt_reg_n_0_[1] ),
        .O(\fine_dec_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT5 #(
    .INIT(32'hBBB8888B)) 
    \fine_dec_cnt[2]_i_1 
       (.I0(\wl_tap_count_r_reg_n_0_[2] ),
        .I1(\fine_dec_cnt[5]_i_8_n_0 ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .I3(\fine_dec_cnt_reg_n_0_[1] ),
        .I4(\fine_dec_cnt_reg_n_0_[2] ),
        .O(\fine_dec_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBB88888888B)) 
    \fine_dec_cnt[3]_i_1 
       (.I0(\wl_tap_count_r_reg_n_0_[3] ),
        .I1(\fine_dec_cnt[5]_i_8_n_0 ),
        .I2(\fine_dec_cnt_reg_n_0_[2] ),
        .I3(\fine_dec_cnt_reg_n_0_[1] ),
        .I4(\fine_dec_cnt_reg_n_0_[0] ),
        .I5(\fine_dec_cnt_reg_n_0_[3] ),
        .O(\fine_dec_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h9999F0F099F0F0F0)) 
    \fine_dec_cnt[4]_i_1 
       (.I0(\fine_dec_cnt[5]_i_6_n_0 ),
        .I1(\fine_dec_cnt_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(Q[0]),
        .O(\fine_dec_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4444454455555555)) 
    \fine_dec_cnt[5]_i_1 
       (.I0(Q[2]),
        .I1(\fine_dec_cnt[5]_i_3_n_0 ),
        .I2(\fine_dec_cnt[5]_i_4_n_0 ),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(Q[0]),
        .I5(\fine_dec_cnt[5]_i_5_n_0 ),
        .O(\fine_dec_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \fine_dec_cnt[5]_i_10 
       (.I0(wl_edge_detect_valid_r_reg_n_0),
        .I1(\wl_state_r[3]_i_4_n_0 ),
        .I2(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .I4(\wl_tap_count_r_reg_n_0_[4] ),
        .I5(\wl_tap_count_r_reg_n_0_[5] ),
        .O(\fine_dec_cnt[5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFE0FFE0)) 
    \fine_dec_cnt[5]_i_2 
       (.I0(\fine_dec_cnt_reg_n_0_[4] ),
        .I1(\fine_dec_cnt[5]_i_6_n_0 ),
        .I2(\fine_dec_cnt_reg_n_0_[5] ),
        .I3(\fine_dec_cnt[5]_i_7_n_0 ),
        .I4(\wl_tap_count_r_reg_n_0_[5] ),
        .I5(\fine_dec_cnt[5]_i_8_n_0 ),
        .O(\fine_dec_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \fine_dec_cnt[5]_i_3 
       (.I0(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(wrlvl_byte_redo),
        .O(\fine_dec_cnt[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF00FF007F007F)) 
    \fine_dec_cnt[5]_i_4 
       (.I0(flag_ck_negedge_i_5_n_0),
        .I1(wl_sm_start),
        .I2(flag_ck_negedge_reg_i_4_n_0),
        .I3(Q[1]),
        .I4(\fine_dec_cnt[5]_i_7_n_0 ),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\fine_dec_cnt[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hDDD0DDDDFFFFFFFF)) 
    \fine_dec_cnt[5]_i_5 
       (.I0(\fine_dec_cnt[5]_i_9_n_0 ),
        .I1(\fine_dec_cnt[5]_i_10_n_0 ),
        .I2(\fine_dec_cnt[5]_i_7_n_0 ),
        .I3(Q[1]),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(\wl_state_r[2]_i_8_n_0 ),
        .O(\fine_dec_cnt[5]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \fine_dec_cnt[5]_i_6 
       (.I0(\fine_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_dec_cnt_reg_n_0_[2] ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .I3(\fine_dec_cnt_reg_n_0_[1] ),
        .O(\fine_dec_cnt[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \fine_dec_cnt[5]_i_7 
       (.I0(\fine_dec_cnt_reg_n_0_[4] ),
        .I1(\fine_dec_cnt_reg_n_0_[5] ),
        .I2(\fine_dec_cnt_reg_n_0_[2] ),
        .I3(\fine_dec_cnt_reg_n_0_[3] ),
        .I4(\fine_dec_cnt_reg_n_0_[0] ),
        .I5(\fine_dec_cnt_reg_n_0_[1] ),
        .O(\fine_dec_cnt[5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT3 #(
    .INIT(8'h37)) 
    \fine_dec_cnt[5]_i_8 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(Q[0]),
        .O(\fine_dec_cnt[5]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \fine_dec_cnt[5]_i_9 
       (.I0(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I1(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .O(\fine_dec_cnt[5]_i_9_n_0 ));
  FDRE \fine_dec_cnt_reg[0] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(\fine_dec_cnt[0]_i_1_n_0 ),
        .Q(\fine_dec_cnt_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \fine_dec_cnt_reg[1] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(\fine_dec_cnt[1]_i_1_n_0 ),
        .Q(\fine_dec_cnt_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \fine_dec_cnt_reg[2] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(\fine_dec_cnt[2]_i_1_n_0 ),
        .Q(\fine_dec_cnt_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \fine_dec_cnt_reg[3] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(\fine_dec_cnt[3]_i_1_n_0 ),
        .Q(\fine_dec_cnt_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \fine_dec_cnt_reg[4] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(\fine_dec_cnt[4]_i_1_n_0 ),
        .Q(\fine_dec_cnt_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \fine_dec_cnt_reg[5] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(\fine_dec_cnt[5]_i_2_n_0 ),
        .Q(\fine_dec_cnt_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[0][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[0].final_val_reg[0]__0 [0]),
        .O(\fine_inc[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[0][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[0].final_val_reg[0]__0 [1]),
        .O(\fine_inc[0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_4 
       (.I0(\fine_inc_reg[3]__0 [0]),
        .I1(\fine_inc_reg[2]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[1]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[0]__0 [0]),
        .O(\fine_inc[0][1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_5 
       (.I0(\fine_inc_reg[7]__0 [0]),
        .I1(\fine_inc_reg[6]__0 [0]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[5]__0 [0]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[4]__0 [0]),
        .O(\fine_inc[0][1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_6 
       (.I0(\fine_inc_reg[3]__0 [1]),
        .I1(\fine_inc_reg[2]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[1]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[0]__0 [1]),
        .O(\fine_inc[0][1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_7 
       (.I0(\fine_inc_reg[7]__0 [1]),
        .I1(\fine_inc_reg[6]__0 [1]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[5]__0 [1]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[4]__0 [1]),
        .O(\fine_inc[0][1]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[0][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[0].final_val_reg[0]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[0][2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \fine_inc[0][2]_i_2 
       (.I0(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .O(\fine_inc[0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][2]_i_4 
       (.I0(\fine_inc_reg[3]__0 [2]),
        .I1(\fine_inc_reg[2]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[1]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[0]__0 [2]),
        .O(\fine_inc[0][2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][2]_i_5 
       (.I0(\fine_inc_reg[7]__0 [2]),
        .I1(\fine_inc_reg[6]__0 [2]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[5]__0 [2]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[4]__0 [2]),
        .O(\fine_inc[0][2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[0][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[0].final_val_reg[0]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[0][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF0F0BB44)) 
    \fine_inc[0][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[0].final_val_reg[0]__0 [4]),
        .I3(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I4(Q[2]),
        .O(\fine_inc[0][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h55750000)) 
    \fine_inc[0][5]_i_1 
       (.I0(\fine_inc[0][5]_i_3_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\fine_inc[0][5]_i_5_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_7_n_0 ),
        .O(\fine_inc[0][5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h53)) 
    \fine_inc[0][5]_i_10 
       (.I0(\fine_inc[0][5]_i_15_n_0 ),
        .I1(\fine_inc[0][5]_i_16_n_0 ),
        .I2(\fine_inc_reg[6][0]_0 ),
        .O(\fine_inc[0][5]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fine_inc[0][5]_i_12 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_10_n_0 ),
        .O(\fine_inc[0][5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_13 
       (.I0(\fine_inc_reg[3]__0 [3]),
        .I1(\fine_inc_reg[2]__0 [3]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[1]__0 [3]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[0]__0 [3]),
        .O(\fine_inc[0][5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_14 
       (.I0(\fine_inc_reg[7]__0 [3]),
        .I1(\fine_inc_reg[6]__0 [3]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[5]__0 [3]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[4]__0 [3]),
        .O(\fine_inc[0][5]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_15 
       (.I0(\fine_inc_reg[7]__0 [5]),
        .I1(\fine_inc_reg[6]__0 [5]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[5]__0 [5]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[4]__0 [5]),
        .O(\fine_inc[0][5]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_16 
       (.I0(\fine_inc_reg[3]__0 [5]),
        .I1(\fine_inc_reg[2]__0 [5]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[1]__0 [5]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[0]__0 [5]),
        .O(\fine_inc[0][5]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_17 
       (.I0(\fine_inc_reg[3]__0 [4]),
        .I1(\fine_inc_reg[2]__0 [4]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[1]__0 [4]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[0]__0 [4]),
        .O(\fine_inc[0][5]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_18 
       (.I0(\fine_inc_reg[7]__0 [4]),
        .I1(\fine_inc_reg[6]__0 [4]),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\fine_inc_reg[5]__0 [4]),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\fine_inc_reg[4]__0 [4]),
        .O(\fine_inc[0][5]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[0][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[0].final_val_reg[0]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[0][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT5 #(
    .INIT(32'hFFFFDFFF)) 
    \fine_inc[0][5]_i_3 
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(wr_level_done_r4),
        .I4(wr_level_done_r5),
        .O(\fine_inc[0][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \fine_inc[0][5]_i_4 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc[0][5]_i_12_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[0][5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \fine_inc[0][5]_i_5 
       (.I0(\smallest_reg[7][0]_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .O(\fine_inc[0][5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT4 #(
    .INIT(16'hEFFF)) 
    \fine_inc[0][5]_i_6 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(wr_level_done_r5),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .O(\fine_inc[0][5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT3 #(
    .INIT(8'h81)) 
    \fine_inc[0][5]_i_7 
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(Q[0]),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .O(\fine_inc[0][5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \fine_inc[0][5]_i_9 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .O(\fine_inc[0][5]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[1][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[1].final_val_reg[1]__0 [0]),
        .O(\fine_inc[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[1][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[1].final_val_reg[1]__0 [1]),
        .O(\fine_inc[1][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[1][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[1].final_val_reg[1]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[1][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[1][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[1].final_val_reg[1]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[1][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B4B4)) 
    \fine_inc[1][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\gen_final_tap[1].final_val_reg[1]__0 [4]),
        .I4(Q[2]),
        .O(\fine_inc[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \fine_inc[1][5]_i_1 
       (.I0(\fine_inc[0][5]_i_7_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\fine_inc[1][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[1][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[1].final_val_reg[1]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[1][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \fine_inc[1][5]_i_3 
       (.I0(\smallest_reg[7][0]_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .O(\fine_inc[1][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[2][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[2].final_val_reg[2]__0 [0]),
        .O(\fine_inc[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[2][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[2].final_val_reg[2]__0 [1]),
        .O(\fine_inc[2][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[2][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[2].final_val_reg[2]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[2][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[2][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[2].final_val_reg[2]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[2][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B4B4)) 
    \fine_inc[2][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\gen_final_tap[2].final_val_reg[2]__0 [4]),
        .I4(Q[2]),
        .O(\fine_inc[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \fine_inc[2][5]_i_1 
       (.I0(\fine_inc[0][5]_i_7_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\fine_inc[2][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[2][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[2].final_val_reg[2]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[2][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \fine_inc[2][5]_i_3 
       (.I0(\smallest_reg[7][0]_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .O(\fine_inc[2][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[3][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[3].final_val_reg[3]__0 [0]),
        .O(\fine_inc[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[3][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[3].final_val_reg[3]__0 [1]),
        .O(\fine_inc[3][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[3][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[3].final_val_reg[3]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[3][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[3][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[3].final_val_reg[3]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[3][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B4B4)) 
    \fine_inc[3][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\gen_final_tap[3].final_val_reg[3]__0 [4]),
        .I4(Q[2]),
        .O(\fine_inc[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \fine_inc[3][5]_i_1 
       (.I0(\fine_inc[0][5]_i_7_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\fine_inc[3][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[3][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[3].final_val_reg[3]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[3][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \fine_inc[3][5]_i_3 
       (.I0(\smallest_reg[7][0]_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .O(\fine_inc[3][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[4][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[4].final_val_reg[4]__0 [0]),
        .O(\fine_inc[4][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[4][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[4].final_val_reg[4]__0 [1]),
        .O(\fine_inc[4][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[4][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[4].final_val_reg[4]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[4][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[4][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[4].final_val_reg[4]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[4][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B4B4)) 
    \fine_inc[4][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\gen_final_tap[4].final_val_reg[4]__0 [4]),
        .I4(Q[2]),
        .O(\fine_inc[4][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \fine_inc[4][5]_i_1 
       (.I0(\fine_inc[0][5]_i_7_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\fine_inc[4][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[4][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[4].final_val_reg[4]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[4][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \fine_inc[4][5]_i_3 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[4][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[5][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[5].final_val_reg[5]__0 [0]),
        .O(\fine_inc[5][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[5][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[5].final_val_reg[5]__0 [1]),
        .O(\fine_inc[5][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[5][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[5].final_val_reg[5]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[5][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[5][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[5].final_val_reg[5]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[5][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B4B4)) 
    \fine_inc[5][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\gen_final_tap[5].final_val_reg[5]__0 [4]),
        .I4(Q[2]),
        .O(\fine_inc[5][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \fine_inc[5][5]_i_1 
       (.I0(\fine_inc[0][5]_i_7_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\fine_inc[5][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[5][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[5].final_val_reg[5]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[5][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \fine_inc[5][5]_i_3 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[5][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[6][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[6].final_val_reg[6]__0 [0]),
        .O(\fine_inc[6][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[6][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[6].final_val_reg[6]__0 [1]),
        .O(\fine_inc[6][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[6][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[6].final_val_reg[6]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[6][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[6][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[6].final_val_reg[6]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[6][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B4B4)) 
    \fine_inc[6][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\gen_final_tap[6].final_val_reg[6]__0 [4]),
        .I4(Q[2]),
        .O(\fine_inc[6][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \fine_inc[6][5]_i_1 
       (.I0(\fine_inc[0][5]_i_7_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\fine_inc[6][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[6][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[6].final_val_reg[6]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[6][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \fine_inc[6][5]_i_3 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[6][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT3 #(
    .INIT(8'hB1)) 
    \fine_inc[7][0]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\gen_final_tap[7].final_val_reg[7]__0 [0]),
        .O(\fine_inc[7][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT4 #(
    .INIT(16'hEB41)) 
    \fine_inc[7][1]_i_1 
       (.I0(Q[2]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\gen_final_tap[7].final_val_reg[7]__0 [1]),
        .O(\fine_inc[7][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[7][2]_i_1 
       (.I0(\fine_inc[0][2]_i_2_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I2(\gen_final_tap[7].final_val_reg[7]__0 [2]),
        .I3(Q[2]),
        .O(\fine_inc[7][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF066)) 
    \fine_inc[7][3]_i_1 
       (.I0(\fine_inc[0][5]_i_9_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I2(\gen_final_tap[7].final_val_reg[7]__0 [3]),
        .I3(Q[2]),
        .O(\fine_inc[7][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B4B4)) 
    \fine_inc[7][4]_i_1 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\gen_final_tap[7].final_val_reg[7]__0 [4]),
        .I4(Q[2]),
        .O(\fine_inc[7][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \fine_inc[7][5]_i_1 
       (.I0(\fine_inc[0][5]_i_7_n_0 ),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .I3(\fine_inc[0][5]_i_6_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\fine_inc[7][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF000F0FFF044F0BB)) 
    \fine_inc[7][5]_i_2 
       (.I0(\fine_inc_reg[0][5]_i_8_n_0 ),
        .I1(\fine_inc[0][5]_i_9_n_0 ),
        .I2(\gen_final_tap[7].final_val_reg[7]__0 [5]),
        .I3(Q[2]),
        .I4(\fine_inc[0][5]_i_10_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\fine_inc[7][5]_i_2_n_0 ));
  FDRE \fine_inc_reg[0][0] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(\fine_inc[0][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[0]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[0][1] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(\fine_inc[0][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[0]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  MUXF7 \fine_inc_reg[0][1]_i_2 
       (.I0(\fine_inc[0][1]_i_4_n_0 ),
        .I1(\fine_inc[0][1]_i_5_n_0 ),
        .O(\fine_inc_reg[0][1]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \fine_inc_reg[0][1]_i_3 
       (.I0(\fine_inc[0][1]_i_6_n_0 ),
        .I1(\fine_inc[0][1]_i_7_n_0 ),
        .O(\fine_inc_reg[0][1]_i_3_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \fine_inc_reg[0][2] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(\fine_inc[0][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[0]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  MUXF7 \fine_inc_reg[0][2]_i_3 
       (.I0(\fine_inc[0][2]_i_4_n_0 ),
        .I1(\fine_inc[0][2]_i_5_n_0 ),
        .O(\fine_inc_reg[0][2]_i_3_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \fine_inc_reg[0][3] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(\fine_inc[0][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[0]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[0][4] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(\fine_inc[0][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[0]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[0][5] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(\fine_inc[0][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[0]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  MUXF7 \fine_inc_reg[0][5]_i_11 
       (.I0(\fine_inc[0][5]_i_17_n_0 ),
        .I1(\fine_inc[0][5]_i_18_n_0 ),
        .O(\fine_inc_reg[0][5]_i_11_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \fine_inc_reg[0][5]_i_8 
       (.I0(\fine_inc[0][5]_i_13_n_0 ),
        .I1(\fine_inc[0][5]_i_14_n_0 ),
        .O(\fine_inc_reg[0][5]_i_8_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \fine_inc_reg[1][0] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[1][1] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[1][2] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[1][3] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[1][4] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[1][5] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[1]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[2][0] 
       (.C(CLK),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[2][1] 
       (.C(CLK),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[2][2] 
       (.C(CLK),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[2][3] 
       (.C(CLK),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[2][4] 
       (.C(CLK),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[2][5] 
       (.C(CLK),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[2]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[3][0] 
       (.C(CLK),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[3][1] 
       (.C(CLK),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[3][2] 
       (.C(CLK),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[3][3] 
       (.C(CLK),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[3][4] 
       (.C(CLK),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[3][5] 
       (.C(CLK),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[3]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[4][0] 
       (.C(CLK),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[4][1] 
       (.C(CLK),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[4][2] 
       (.C(CLK),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[4][3] 
       (.C(CLK),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[4][4] 
       (.C(CLK),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[4][5] 
       (.C(CLK),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[4]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[5][0] 
       (.C(CLK),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[5][1] 
       (.C(CLK),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[5][2] 
       (.C(CLK),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[5][3] 
       (.C(CLK),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[5][4] 
       (.C(CLK),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[5][5] 
       (.C(CLK),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[5]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[6][0] 
       (.C(CLK),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[6][1] 
       (.C(CLK),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[6][2] 
       (.C(CLK),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[6][3] 
       (.C(CLK),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[6][4] 
       (.C(CLK),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[6][5] 
       (.C(CLK),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[6]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[7][0] 
       (.C(CLK),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[7][1] 
       (.C(CLK),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[7][2] 
       (.C(CLK),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[7][3] 
       (.C(CLK),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__6));
  FDRE \fine_inc_reg[7][4] 
       (.C(CLK),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \fine_inc_reg[7][5] 
       (.C(CLK),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[7]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  LUT6 #(
    .INIT(64'h3333323322222222)) 
    flag_ck_negedge_i_1
       (.I0(flag_ck_negedge_i_2_n_0),
        .I1(flag_ck_negedge_i_3_n_0),
        .I2(flag_ck_negedge_reg_i_4_n_0),
        .I3(flag_ck_negedge_i_5_n_0),
        .I4(\stable_cnt_reg_n_0_[0] ),
        .I5(flag_ck_negedge_reg_n_0),
        .O(flag_ck_negedge_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    flag_ck_negedge_i_10
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .O(flag_ck_negedge_i_10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    flag_ck_negedge_i_11
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[1]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(flag_ck_negedge_i_11_n_0));
  LUT6 #(
    .INIT(64'h0008FFFF00080008)) 
    flag_ck_negedge_i_2
       (.I0(Q[2]),
        .I1(flag_ck_negedge_i_6_n_0),
        .I2(Q[1]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(flag_ck_negedge_i_7_n_0),
        .I5(flag_ck_negedge_reg_i_4_n_0),
        .O(flag_ck_negedge_i_2_n_0));
  LUT6 #(
    .INIT(64'hFEFEFEFEFFFEFEFE)) 
    flag_ck_negedge_i_3
       (.I0(\stable_cnt[3]_i_8_n_0 ),
        .I1(rstdiv0_sync_r1_reg_rep__23),
        .I2(wr_level_done_r_reg_n_0),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\wl_state_r[3]_i_4_n_0 ),
        .I5(Q[2]),
        .O(flag_ck_negedge_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT3 #(
    .INIT(8'h80)) 
    flag_ck_negedge_i_5
       (.I0(\stable_cnt_reg_n_0_[3] ),
        .I1(\stable_cnt_reg_n_0_[2] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .O(flag_ck_negedge_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT2 #(
    .INIT(4'h1)) 
    flag_ck_negedge_i_6
       (.I0(Q[0]),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .O(flag_ck_negedge_i_6_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    flag_ck_negedge_i_7
       (.I0(\stable_cnt_reg_n_0_[1] ),
        .I1(\stable_cnt_reg_n_0_[0] ),
        .I2(\stable_cnt_reg_n_0_[3] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .I4(flag_ck_negedge_i_10_n_0),
        .I5(flag_ck_negedge_i_11_n_0),
        .O(flag_ck_negedge_i_7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    flag_ck_negedge_i_8
       (.I0(\rd_data_previous_r_reg_n_0_[3] ),
        .I1(\rd_data_previous_r_reg_n_0_[2] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\rd_data_previous_r_reg_n_0_[1] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\rd_data_previous_r_reg_n_0_[0] ),
        .O(flag_ck_negedge_i_8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    flag_ck_negedge_i_9
       (.I0(\rd_data_previous_r_reg_n_0_[7] ),
        .I1(\rd_data_previous_r_reg_n_0_[6] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\rd_data_previous_r_reg_n_0_[5] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\rd_data_previous_r_reg_n_0_[4] ),
        .O(flag_ck_negedge_i_9_n_0));
  FDRE flag_ck_negedge_reg
       (.C(CLK),
        .CE(1'b1),
        .D(flag_ck_negedge_i_1_n_0),
        .Q(flag_ck_negedge_reg_n_0),
        .R(1'b0));
  MUXF7 flag_ck_negedge_reg_i_4
       (.I0(flag_ck_negedge_i_8_n_0),
        .I1(flag_ck_negedge_i_9_n_0),
        .O(flag_ck_negedge_reg_i_4_n_0),
        .S(dqs_count_r[2]));
  LUT6 #(
    .INIT(64'hAAAAA8AAAAAAAAAA)) 
    flag_init_i_1
       (.I0(flag_init),
        .I1(\wl_state_r1_reg_n_0_[0] ),
        .I2(\wl_state_r1_reg_n_0_[3] ),
        .I3(\wl_state_r1_reg_n_0_[2] ),
        .I4(\wl_state_r1_reg_n_0_[4] ),
        .I5(flag_init_i_2_n_0),
        .O(flag_init_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT5 #(
    .INIT(32'h00000010)) 
    flag_init_i_2
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(flag_init_i_2_n_0));
  FDSE flag_init_reg
       (.C(CLK),
        .CE(1'b1),
        .D(flag_init_i_1_n_0),
        .Q(flag_init),
        .S(rstdiv0_sync_r1_reg_rep__4));
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_byte_sel_div2.calib_in_common_i_4 
       (.I0(wrlvl_done_r_reg),
        .I1(rdlvl_stg1_done_reg),
        .I2(wrcal_done_reg),
        .O(\gen_byte_sel_div2.calib_in_common_reg ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_10 
       (.I0(\smallest_reg[0]__0 [0]),
        .O(\gen_final_tap[0].final_val[0][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_2 
       (.I0(\gen_final_tap[0].final_val_reg[0][3]_i_6_n_4 ),
        .O(\gen_final_tap[0].final_val[0][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_3 
       (.I0(\gen_final_tap[0].final_val_reg[0][3]_i_6_n_5 ),
        .O(\gen_final_tap[0].final_val[0][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_4 
       (.I0(\gen_final_tap[0].final_val_reg[0][3]_i_6_n_6 ),
        .O(\gen_final_tap[0].final_val[0][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_5 
       (.I0(\gen_final_tap[0].final_val_reg[0][3]_i_6_n_7 ),
        .O(\gen_final_tap[0].final_val[0][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_7 
       (.I0(\smallest_reg[0]__0 [3]),
        .O(\gen_final_tap[0].final_val[0][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_8 
       (.I0(\smallest_reg[0]__0 [2]),
        .O(\gen_final_tap[0].final_val[0][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][3]_i_9 
       (.I0(\smallest_reg[0]__0 [1]),
        .O(\gen_final_tap[0].final_val[0][3]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gen_final_tap[0].final_val[0][5]_i_1 
       (.I0(wr_level_done_r2),
        .I1(wr_level_done_r3),
        .O(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][5]_i_3 
       (.I0(\gen_final_tap[0].final_val_reg[0][5]_i_5_n_6 ),
        .O(\gen_final_tap[0].final_val[0][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][5]_i_4 
       (.I0(\gen_final_tap[0].final_val_reg[0][5]_i_5_n_7 ),
        .O(\gen_final_tap[0].final_val[0][5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][5]_i_6 
       (.I0(\smallest_reg[0]__0 [5]),
        .O(\gen_final_tap[0].final_val[0][5]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[0].final_val[0][5]_i_7 
       (.I0(\smallest_reg[0]__0 [4]),
        .O(\gen_final_tap[0].final_val[0][5]_i_7_n_0 ));
  FDRE \gen_final_tap[0].final_val_reg[0][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[0].final_val_reg[0][3]_i_1_n_7 ),
        .Q(\gen_final_tap[0].final_val_reg[0]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[0].final_val_reg[0][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[0].final_val_reg[0][3]_i_1_n_6 ),
        .Q(\gen_final_tap[0].final_val_reg[0]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[0].final_val_reg[0][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[0].final_val_reg[0][3]_i_1_n_5 ),
        .Q(\gen_final_tap[0].final_val_reg[0]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[0].final_val_reg[0][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[0].final_val_reg[0][3]_i_1_n_4 ),
        .Q(\gen_final_tap[0].final_val_reg[0]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[0].final_val_reg[0][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[0].final_val_reg[0][3]_i_1_n_0 ,\gen_final_tap[0].final_val_reg[0][3]_i_1_n_1 ,\gen_final_tap[0].final_val_reg[0][3]_i_1_n_2 ,\gen_final_tap[0].final_val_reg[0][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[0].final_val_reg[0][3]_i_1_n_4 ,\gen_final_tap[0].final_val_reg[0][3]_i_1_n_5 ,\gen_final_tap[0].final_val_reg[0][3]_i_1_n_6 ,\gen_final_tap[0].final_val_reg[0][3]_i_1_n_7 }),
        .S({\gen_final_tap[0].final_val[0][3]_i_2_n_0 ,\gen_final_tap[0].final_val[0][3]_i_3_n_0 ,\gen_final_tap[0].final_val[0][3]_i_4_n_0 ,\gen_final_tap[0].final_val[0][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[0].final_val_reg[0][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[0].final_val_reg[0][3]_i_6_n_0 ,\gen_final_tap[0].final_val_reg[0][3]_i_6_n_1 ,\gen_final_tap[0].final_val_reg[0][3]_i_6_n_2 ,\gen_final_tap[0].final_val_reg[0][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[0]__0 [3:0]),
        .O({\gen_final_tap[0].final_val_reg[0][3]_i_6_n_4 ,\gen_final_tap[0].final_val_reg[0][3]_i_6_n_5 ,\gen_final_tap[0].final_val_reg[0][3]_i_6_n_6 ,\gen_final_tap[0].final_val_reg[0][3]_i_6_n_7 }),
        .S({\gen_final_tap[0].final_val[0][3]_i_7_n_0 ,\gen_final_tap[0].final_val[0][3]_i_8_n_0 ,\gen_final_tap[0].final_val[0][3]_i_9_n_0 ,\gen_final_tap[0].final_val[0][3]_i_10_n_0 }));
  FDRE \gen_final_tap[0].final_val_reg[0][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[0].final_val_reg[0][5]_i_2_n_7 ),
        .Q(\gen_final_tap[0].final_val_reg[0]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[0].final_val_reg[0][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[0].final_val_reg[0][5]_i_2_n_6 ),
        .Q(\gen_final_tap[0].final_val_reg[0]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[0].final_val_reg[0][5]_i_2 
       (.CI(\gen_final_tap[0].final_val_reg[0][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[0].final_val_reg[0][5]_i_2_CO_UNCONNECTED [3:1],\gen_final_tap[0].final_val_reg[0][5]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[0].final_val_reg[0][5]_i_2_O_UNCONNECTED [3:2],\gen_final_tap[0].final_val_reg[0][5]_i_2_n_6 ,\gen_final_tap[0].final_val_reg[0][5]_i_2_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[0].final_val[0][5]_i_3_n_0 ,\gen_final_tap[0].final_val[0][5]_i_4_n_0 }));
  CARRY4 \gen_final_tap[0].final_val_reg[0][5]_i_5 
       (.CI(\gen_final_tap[0].final_val_reg[0][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[0].final_val_reg[0][5]_i_5_CO_UNCONNECTED [3:1],\gen_final_tap[0].final_val_reg[0][5]_i_5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[0]__0 [4]}),
        .O({\NLW_gen_final_tap[0].final_val_reg[0][5]_i_5_O_UNCONNECTED [3:2],\gen_final_tap[0].final_val_reg[0][5]_i_5_n_6 ,\gen_final_tap[0].final_val_reg[0][5]_i_5_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[0].final_val[0][5]_i_6_n_0 ,\gen_final_tap[0].final_val[0][5]_i_7_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_10 
       (.I0(\smallest_reg[1]__0 [0]),
        .O(\gen_final_tap[1].final_val[1][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_2 
       (.I0(\gen_final_tap[1].final_val_reg[1][3]_i_6_n_4 ),
        .O(\gen_final_tap[1].final_val[1][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_3 
       (.I0(\gen_final_tap[1].final_val_reg[1][3]_i_6_n_5 ),
        .O(\gen_final_tap[1].final_val[1][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_4 
       (.I0(\gen_final_tap[1].final_val_reg[1][3]_i_6_n_6 ),
        .O(\gen_final_tap[1].final_val[1][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_5 
       (.I0(\gen_final_tap[1].final_val_reg[1][3]_i_6_n_7 ),
        .O(\gen_final_tap[1].final_val[1][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_7 
       (.I0(\smallest_reg[1]__0 [3]),
        .O(\gen_final_tap[1].final_val[1][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_8 
       (.I0(\smallest_reg[1]__0 [2]),
        .O(\gen_final_tap[1].final_val[1][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][3]_i_9 
       (.I0(\smallest_reg[1]__0 [1]),
        .O(\gen_final_tap[1].final_val[1][3]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][5]_i_2 
       (.I0(\gen_final_tap[1].final_val_reg[1][5]_i_4_n_6 ),
        .O(\gen_final_tap[1].final_val[1][5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][5]_i_3 
       (.I0(\gen_final_tap[1].final_val_reg[1][5]_i_4_n_7 ),
        .O(\gen_final_tap[1].final_val[1][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][5]_i_5 
       (.I0(\smallest_reg[1]__0 [5]),
        .O(\gen_final_tap[1].final_val[1][5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[1].final_val[1][5]_i_6 
       (.I0(\smallest_reg[1]__0 [4]),
        .O(\gen_final_tap[1].final_val[1][5]_i_6_n_0 ));
  FDRE \gen_final_tap[1].final_val_reg[1][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[1].final_val_reg[1][3]_i_1_n_7 ),
        .Q(\gen_final_tap[1].final_val_reg[1]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[1].final_val_reg[1][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[1].final_val_reg[1][3]_i_1_n_6 ),
        .Q(\gen_final_tap[1].final_val_reg[1]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[1].final_val_reg[1][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[1].final_val_reg[1][3]_i_1_n_5 ),
        .Q(\gen_final_tap[1].final_val_reg[1]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[1].final_val_reg[1][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[1].final_val_reg[1][3]_i_1_n_4 ),
        .Q(\gen_final_tap[1].final_val_reg[1]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[1].final_val_reg[1][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[1].final_val_reg[1][3]_i_1_n_0 ,\gen_final_tap[1].final_val_reg[1][3]_i_1_n_1 ,\gen_final_tap[1].final_val_reg[1][3]_i_1_n_2 ,\gen_final_tap[1].final_val_reg[1][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[1].final_val_reg[1][3]_i_1_n_4 ,\gen_final_tap[1].final_val_reg[1][3]_i_1_n_5 ,\gen_final_tap[1].final_val_reg[1][3]_i_1_n_6 ,\gen_final_tap[1].final_val_reg[1][3]_i_1_n_7 }),
        .S({\gen_final_tap[1].final_val[1][3]_i_2_n_0 ,\gen_final_tap[1].final_val[1][3]_i_3_n_0 ,\gen_final_tap[1].final_val[1][3]_i_4_n_0 ,\gen_final_tap[1].final_val[1][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[1].final_val_reg[1][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[1].final_val_reg[1][3]_i_6_n_0 ,\gen_final_tap[1].final_val_reg[1][3]_i_6_n_1 ,\gen_final_tap[1].final_val_reg[1][3]_i_6_n_2 ,\gen_final_tap[1].final_val_reg[1][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[1]__0 [3:0]),
        .O({\gen_final_tap[1].final_val_reg[1][3]_i_6_n_4 ,\gen_final_tap[1].final_val_reg[1][3]_i_6_n_5 ,\gen_final_tap[1].final_val_reg[1][3]_i_6_n_6 ,\gen_final_tap[1].final_val_reg[1][3]_i_6_n_7 }),
        .S({\gen_final_tap[1].final_val[1][3]_i_7_n_0 ,\gen_final_tap[1].final_val[1][3]_i_8_n_0 ,\gen_final_tap[1].final_val[1][3]_i_9_n_0 ,\gen_final_tap[1].final_val[1][3]_i_10_n_0 }));
  FDRE \gen_final_tap[1].final_val_reg[1][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[1].final_val_reg[1][5]_i_1_n_7 ),
        .Q(\gen_final_tap[1].final_val_reg[1]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[1].final_val_reg[1][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[1].final_val_reg[1][5]_i_1_n_6 ),
        .Q(\gen_final_tap[1].final_val_reg[1]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[1].final_val_reg[1][5]_i_1 
       (.CI(\gen_final_tap[1].final_val_reg[1][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[1].final_val_reg[1][5]_i_1_CO_UNCONNECTED [3:1],\gen_final_tap[1].final_val_reg[1][5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[1].final_val_reg[1][5]_i_1_O_UNCONNECTED [3:2],\gen_final_tap[1].final_val_reg[1][5]_i_1_n_6 ,\gen_final_tap[1].final_val_reg[1][5]_i_1_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[1].final_val[1][5]_i_2_n_0 ,\gen_final_tap[1].final_val[1][5]_i_3_n_0 }));
  CARRY4 \gen_final_tap[1].final_val_reg[1][5]_i_4 
       (.CI(\gen_final_tap[1].final_val_reg[1][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[1].final_val_reg[1][5]_i_4_CO_UNCONNECTED [3:1],\gen_final_tap[1].final_val_reg[1][5]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[1]__0 [4]}),
        .O({\NLW_gen_final_tap[1].final_val_reg[1][5]_i_4_O_UNCONNECTED [3:2],\gen_final_tap[1].final_val_reg[1][5]_i_4_n_6 ,\gen_final_tap[1].final_val_reg[1][5]_i_4_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[1].final_val[1][5]_i_5_n_0 ,\gen_final_tap[1].final_val[1][5]_i_6_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_10 
       (.I0(\smallest_reg[2]__0 [0]),
        .O(\gen_final_tap[2].final_val[2][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_2 
       (.I0(\gen_final_tap[2].final_val_reg[2][3]_i_6_n_4 ),
        .O(\gen_final_tap[2].final_val[2][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_3 
       (.I0(\gen_final_tap[2].final_val_reg[2][3]_i_6_n_5 ),
        .O(\gen_final_tap[2].final_val[2][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_4 
       (.I0(\gen_final_tap[2].final_val_reg[2][3]_i_6_n_6 ),
        .O(\gen_final_tap[2].final_val[2][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_5 
       (.I0(\gen_final_tap[2].final_val_reg[2][3]_i_6_n_7 ),
        .O(\gen_final_tap[2].final_val[2][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_7 
       (.I0(\smallest_reg[2]__0 [3]),
        .O(\gen_final_tap[2].final_val[2][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_8 
       (.I0(\smallest_reg[2]__0 [2]),
        .O(\gen_final_tap[2].final_val[2][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][3]_i_9 
       (.I0(\smallest_reg[2]__0 [1]),
        .O(\gen_final_tap[2].final_val[2][3]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][5]_i_2 
       (.I0(\gen_final_tap[2].final_val_reg[2][5]_i_4_n_6 ),
        .O(\gen_final_tap[2].final_val[2][5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][5]_i_3 
       (.I0(\gen_final_tap[2].final_val_reg[2][5]_i_4_n_7 ),
        .O(\gen_final_tap[2].final_val[2][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][5]_i_5 
       (.I0(\smallest_reg[2]__0 [5]),
        .O(\gen_final_tap[2].final_val[2][5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[2].final_val[2][5]_i_6 
       (.I0(\smallest_reg[2]__0 [4]),
        .O(\gen_final_tap[2].final_val[2][5]_i_6_n_0 ));
  FDRE \gen_final_tap[2].final_val_reg[2][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[2].final_val_reg[2][3]_i_1_n_7 ),
        .Q(\gen_final_tap[2].final_val_reg[2]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[2].final_val_reg[2][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[2].final_val_reg[2][3]_i_1_n_6 ),
        .Q(\gen_final_tap[2].final_val_reg[2]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[2].final_val_reg[2][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[2].final_val_reg[2][3]_i_1_n_5 ),
        .Q(\gen_final_tap[2].final_val_reg[2]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[2].final_val_reg[2][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[2].final_val_reg[2][3]_i_1_n_4 ),
        .Q(\gen_final_tap[2].final_val_reg[2]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[2].final_val_reg[2][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[2].final_val_reg[2][3]_i_1_n_0 ,\gen_final_tap[2].final_val_reg[2][3]_i_1_n_1 ,\gen_final_tap[2].final_val_reg[2][3]_i_1_n_2 ,\gen_final_tap[2].final_val_reg[2][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[2].final_val_reg[2][3]_i_1_n_4 ,\gen_final_tap[2].final_val_reg[2][3]_i_1_n_5 ,\gen_final_tap[2].final_val_reg[2][3]_i_1_n_6 ,\gen_final_tap[2].final_val_reg[2][3]_i_1_n_7 }),
        .S({\gen_final_tap[2].final_val[2][3]_i_2_n_0 ,\gen_final_tap[2].final_val[2][3]_i_3_n_0 ,\gen_final_tap[2].final_val[2][3]_i_4_n_0 ,\gen_final_tap[2].final_val[2][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[2].final_val_reg[2][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[2].final_val_reg[2][3]_i_6_n_0 ,\gen_final_tap[2].final_val_reg[2][3]_i_6_n_1 ,\gen_final_tap[2].final_val_reg[2][3]_i_6_n_2 ,\gen_final_tap[2].final_val_reg[2][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[2]__0 [3:0]),
        .O({\gen_final_tap[2].final_val_reg[2][3]_i_6_n_4 ,\gen_final_tap[2].final_val_reg[2][3]_i_6_n_5 ,\gen_final_tap[2].final_val_reg[2][3]_i_6_n_6 ,\gen_final_tap[2].final_val_reg[2][3]_i_6_n_7 }),
        .S({\gen_final_tap[2].final_val[2][3]_i_7_n_0 ,\gen_final_tap[2].final_val[2][3]_i_8_n_0 ,\gen_final_tap[2].final_val[2][3]_i_9_n_0 ,\gen_final_tap[2].final_val[2][3]_i_10_n_0 }));
  FDRE \gen_final_tap[2].final_val_reg[2][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[2].final_val_reg[2][5]_i_1_n_7 ),
        .Q(\gen_final_tap[2].final_val_reg[2]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[2].final_val_reg[2][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[2].final_val_reg[2][5]_i_1_n_6 ),
        .Q(\gen_final_tap[2].final_val_reg[2]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[2].final_val_reg[2][5]_i_1 
       (.CI(\gen_final_tap[2].final_val_reg[2][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[2].final_val_reg[2][5]_i_1_CO_UNCONNECTED [3:1],\gen_final_tap[2].final_val_reg[2][5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[2].final_val_reg[2][5]_i_1_O_UNCONNECTED [3:2],\gen_final_tap[2].final_val_reg[2][5]_i_1_n_6 ,\gen_final_tap[2].final_val_reg[2][5]_i_1_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[2].final_val[2][5]_i_2_n_0 ,\gen_final_tap[2].final_val[2][5]_i_3_n_0 }));
  CARRY4 \gen_final_tap[2].final_val_reg[2][5]_i_4 
       (.CI(\gen_final_tap[2].final_val_reg[2][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[2].final_val_reg[2][5]_i_4_CO_UNCONNECTED [3:1],\gen_final_tap[2].final_val_reg[2][5]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[2]__0 [4]}),
        .O({\NLW_gen_final_tap[2].final_val_reg[2][5]_i_4_O_UNCONNECTED [3:2],\gen_final_tap[2].final_val_reg[2][5]_i_4_n_6 ,\gen_final_tap[2].final_val_reg[2][5]_i_4_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[2].final_val[2][5]_i_5_n_0 ,\gen_final_tap[2].final_val[2][5]_i_6_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_10 
       (.I0(\smallest_reg[3]__0 [0]),
        .O(\gen_final_tap[3].final_val[3][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_2 
       (.I0(\gen_final_tap[3].final_val_reg[3][3]_i_6_n_4 ),
        .O(\gen_final_tap[3].final_val[3][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_3 
       (.I0(\gen_final_tap[3].final_val_reg[3][3]_i_6_n_5 ),
        .O(\gen_final_tap[3].final_val[3][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_4 
       (.I0(\gen_final_tap[3].final_val_reg[3][3]_i_6_n_6 ),
        .O(\gen_final_tap[3].final_val[3][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_5 
       (.I0(\gen_final_tap[3].final_val_reg[3][3]_i_6_n_7 ),
        .O(\gen_final_tap[3].final_val[3][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_7 
       (.I0(\smallest_reg[3]__0 [3]),
        .O(\gen_final_tap[3].final_val[3][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_8 
       (.I0(\smallest_reg[3]__0 [2]),
        .O(\gen_final_tap[3].final_val[3][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][3]_i_9 
       (.I0(\smallest_reg[3]__0 [1]),
        .O(\gen_final_tap[3].final_val[3][3]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][5]_i_2 
       (.I0(\gen_final_tap[3].final_val_reg[3][5]_i_4_n_6 ),
        .O(\gen_final_tap[3].final_val[3][5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][5]_i_3 
       (.I0(\gen_final_tap[3].final_val_reg[3][5]_i_4_n_7 ),
        .O(\gen_final_tap[3].final_val[3][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][5]_i_5 
       (.I0(\smallest_reg[3]__0 [5]),
        .O(\gen_final_tap[3].final_val[3][5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[3].final_val[3][5]_i_6 
       (.I0(\smallest_reg[3]__0 [4]),
        .O(\gen_final_tap[3].final_val[3][5]_i_6_n_0 ));
  FDRE \gen_final_tap[3].final_val_reg[3][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[3].final_val_reg[3][3]_i_1_n_7 ),
        .Q(\gen_final_tap[3].final_val_reg[3]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[3].final_val_reg[3][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[3].final_val_reg[3][3]_i_1_n_6 ),
        .Q(\gen_final_tap[3].final_val_reg[3]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[3].final_val_reg[3][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[3].final_val_reg[3][3]_i_1_n_5 ),
        .Q(\gen_final_tap[3].final_val_reg[3]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[3].final_val_reg[3][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[3].final_val_reg[3][3]_i_1_n_4 ),
        .Q(\gen_final_tap[3].final_val_reg[3]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[3].final_val_reg[3][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[3].final_val_reg[3][3]_i_1_n_0 ,\gen_final_tap[3].final_val_reg[3][3]_i_1_n_1 ,\gen_final_tap[3].final_val_reg[3][3]_i_1_n_2 ,\gen_final_tap[3].final_val_reg[3][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[3].final_val_reg[3][3]_i_1_n_4 ,\gen_final_tap[3].final_val_reg[3][3]_i_1_n_5 ,\gen_final_tap[3].final_val_reg[3][3]_i_1_n_6 ,\gen_final_tap[3].final_val_reg[3][3]_i_1_n_7 }),
        .S({\gen_final_tap[3].final_val[3][3]_i_2_n_0 ,\gen_final_tap[3].final_val[3][3]_i_3_n_0 ,\gen_final_tap[3].final_val[3][3]_i_4_n_0 ,\gen_final_tap[3].final_val[3][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[3].final_val_reg[3][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[3].final_val_reg[3][3]_i_6_n_0 ,\gen_final_tap[3].final_val_reg[3][3]_i_6_n_1 ,\gen_final_tap[3].final_val_reg[3][3]_i_6_n_2 ,\gen_final_tap[3].final_val_reg[3][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[3]__0 [3:0]),
        .O({\gen_final_tap[3].final_val_reg[3][3]_i_6_n_4 ,\gen_final_tap[3].final_val_reg[3][3]_i_6_n_5 ,\gen_final_tap[3].final_val_reg[3][3]_i_6_n_6 ,\gen_final_tap[3].final_val_reg[3][3]_i_6_n_7 }),
        .S({\gen_final_tap[3].final_val[3][3]_i_7_n_0 ,\gen_final_tap[3].final_val[3][3]_i_8_n_0 ,\gen_final_tap[3].final_val[3][3]_i_9_n_0 ,\gen_final_tap[3].final_val[3][3]_i_10_n_0 }));
  FDRE \gen_final_tap[3].final_val_reg[3][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[3].final_val_reg[3][5]_i_1_n_7 ),
        .Q(\gen_final_tap[3].final_val_reg[3]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \gen_final_tap[3].final_val_reg[3][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[3].final_val_reg[3][5]_i_1_n_6 ),
        .Q(\gen_final_tap[3].final_val_reg[3]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[3].final_val_reg[3][5]_i_1 
       (.CI(\gen_final_tap[3].final_val_reg[3][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[3].final_val_reg[3][5]_i_1_CO_UNCONNECTED [3:1],\gen_final_tap[3].final_val_reg[3][5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[3].final_val_reg[3][5]_i_1_O_UNCONNECTED [3:2],\gen_final_tap[3].final_val_reg[3][5]_i_1_n_6 ,\gen_final_tap[3].final_val_reg[3][5]_i_1_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[3].final_val[3][5]_i_2_n_0 ,\gen_final_tap[3].final_val[3][5]_i_3_n_0 }));
  CARRY4 \gen_final_tap[3].final_val_reg[3][5]_i_4 
       (.CI(\gen_final_tap[3].final_val_reg[3][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[3].final_val_reg[3][5]_i_4_CO_UNCONNECTED [3:1],\gen_final_tap[3].final_val_reg[3][5]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[3]__0 [4]}),
        .O({\NLW_gen_final_tap[3].final_val_reg[3][5]_i_4_O_UNCONNECTED [3:2],\gen_final_tap[3].final_val_reg[3][5]_i_4_n_6 ,\gen_final_tap[3].final_val_reg[3][5]_i_4_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[3].final_val[3][5]_i_5_n_0 ,\gen_final_tap[3].final_val[3][5]_i_6_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_10 
       (.I0(\smallest_reg[4]__0 [0]),
        .O(\gen_final_tap[4].final_val[4][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_2 
       (.I0(\gen_final_tap[4].final_val_reg[4][3]_i_6_n_4 ),
        .O(\gen_final_tap[4].final_val[4][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_3 
       (.I0(\gen_final_tap[4].final_val_reg[4][3]_i_6_n_5 ),
        .O(\gen_final_tap[4].final_val[4][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_4 
       (.I0(\gen_final_tap[4].final_val_reg[4][3]_i_6_n_6 ),
        .O(\gen_final_tap[4].final_val[4][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_5 
       (.I0(\gen_final_tap[4].final_val_reg[4][3]_i_6_n_7 ),
        .O(\gen_final_tap[4].final_val[4][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_7 
       (.I0(\smallest_reg[4]__0 [3]),
        .O(\gen_final_tap[4].final_val[4][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_8 
       (.I0(\smallest_reg[4]__0 [2]),
        .O(\gen_final_tap[4].final_val[4][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][3]_i_9 
       (.I0(\smallest_reg[4]__0 [1]),
        .O(\gen_final_tap[4].final_val[4][3]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][5]_i_2 
       (.I0(\gen_final_tap[4].final_val_reg[4][5]_i_4_n_6 ),
        .O(\gen_final_tap[4].final_val[4][5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][5]_i_3 
       (.I0(\gen_final_tap[4].final_val_reg[4][5]_i_4_n_7 ),
        .O(\gen_final_tap[4].final_val[4][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][5]_i_5 
       (.I0(\smallest_reg[4]__0 [5]),
        .O(\gen_final_tap[4].final_val[4][5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[4].final_val[4][5]_i_6 
       (.I0(\smallest_reg[4]__0 [4]),
        .O(\gen_final_tap[4].final_val[4][5]_i_6_n_0 ));
  FDRE \gen_final_tap[4].final_val_reg[4][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[4].final_val_reg[4][3]_i_1_n_7 ),
        .Q(\gen_final_tap[4].final_val_reg[4]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[4].final_val_reg[4][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[4].final_val_reg[4][3]_i_1_n_6 ),
        .Q(\gen_final_tap[4].final_val_reg[4]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[4].final_val_reg[4][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[4].final_val_reg[4][3]_i_1_n_5 ),
        .Q(\gen_final_tap[4].final_val_reg[4]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[4].final_val_reg[4][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[4].final_val_reg[4][3]_i_1_n_4 ),
        .Q(\gen_final_tap[4].final_val_reg[4]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  CARRY4 \gen_final_tap[4].final_val_reg[4][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[4].final_val_reg[4][3]_i_1_n_0 ,\gen_final_tap[4].final_val_reg[4][3]_i_1_n_1 ,\gen_final_tap[4].final_val_reg[4][3]_i_1_n_2 ,\gen_final_tap[4].final_val_reg[4][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[4].final_val_reg[4][3]_i_1_n_4 ,\gen_final_tap[4].final_val_reg[4][3]_i_1_n_5 ,\gen_final_tap[4].final_val_reg[4][3]_i_1_n_6 ,\gen_final_tap[4].final_val_reg[4][3]_i_1_n_7 }),
        .S({\gen_final_tap[4].final_val[4][3]_i_2_n_0 ,\gen_final_tap[4].final_val[4][3]_i_3_n_0 ,\gen_final_tap[4].final_val[4][3]_i_4_n_0 ,\gen_final_tap[4].final_val[4][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[4].final_val_reg[4][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[4].final_val_reg[4][3]_i_6_n_0 ,\gen_final_tap[4].final_val_reg[4][3]_i_6_n_1 ,\gen_final_tap[4].final_val_reg[4][3]_i_6_n_2 ,\gen_final_tap[4].final_val_reg[4][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[4]__0 [3:0]),
        .O({\gen_final_tap[4].final_val_reg[4][3]_i_6_n_4 ,\gen_final_tap[4].final_val_reg[4][3]_i_6_n_5 ,\gen_final_tap[4].final_val_reg[4][3]_i_6_n_6 ,\gen_final_tap[4].final_val_reg[4][3]_i_6_n_7 }),
        .S({\gen_final_tap[4].final_val[4][3]_i_7_n_0 ,\gen_final_tap[4].final_val[4][3]_i_8_n_0 ,\gen_final_tap[4].final_val[4][3]_i_9_n_0 ,\gen_final_tap[4].final_val[4][3]_i_10_n_0 }));
  FDRE \gen_final_tap[4].final_val_reg[4][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[4].final_val_reg[4][5]_i_1_n_7 ),
        .Q(\gen_final_tap[4].final_val_reg[4]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[4].final_val_reg[4][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[4].final_val_reg[4][5]_i_1_n_6 ),
        .Q(\gen_final_tap[4].final_val_reg[4]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  CARRY4 \gen_final_tap[4].final_val_reg[4][5]_i_1 
       (.CI(\gen_final_tap[4].final_val_reg[4][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[4].final_val_reg[4][5]_i_1_CO_UNCONNECTED [3:1],\gen_final_tap[4].final_val_reg[4][5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[4].final_val_reg[4][5]_i_1_O_UNCONNECTED [3:2],\gen_final_tap[4].final_val_reg[4][5]_i_1_n_6 ,\gen_final_tap[4].final_val_reg[4][5]_i_1_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[4].final_val[4][5]_i_2_n_0 ,\gen_final_tap[4].final_val[4][5]_i_3_n_0 }));
  CARRY4 \gen_final_tap[4].final_val_reg[4][5]_i_4 
       (.CI(\gen_final_tap[4].final_val_reg[4][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[4].final_val_reg[4][5]_i_4_CO_UNCONNECTED [3:1],\gen_final_tap[4].final_val_reg[4][5]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[4]__0 [4]}),
        .O({\NLW_gen_final_tap[4].final_val_reg[4][5]_i_4_O_UNCONNECTED [3:2],\gen_final_tap[4].final_val_reg[4][5]_i_4_n_6 ,\gen_final_tap[4].final_val_reg[4][5]_i_4_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[4].final_val[4][5]_i_5_n_0 ,\gen_final_tap[4].final_val[4][5]_i_6_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_10 
       (.I0(\smallest_reg[5]__0 [0]),
        .O(\gen_final_tap[5].final_val[5][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_2 
       (.I0(\gen_final_tap[5].final_val_reg[5][3]_i_6_n_4 ),
        .O(\gen_final_tap[5].final_val[5][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_3 
       (.I0(\gen_final_tap[5].final_val_reg[5][3]_i_6_n_5 ),
        .O(\gen_final_tap[5].final_val[5][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_4 
       (.I0(\gen_final_tap[5].final_val_reg[5][3]_i_6_n_6 ),
        .O(\gen_final_tap[5].final_val[5][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_5 
       (.I0(\gen_final_tap[5].final_val_reg[5][3]_i_6_n_7 ),
        .O(\gen_final_tap[5].final_val[5][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_7 
       (.I0(\smallest_reg[5]__0 [3]),
        .O(\gen_final_tap[5].final_val[5][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_8 
       (.I0(\smallest_reg[5]__0 [2]),
        .O(\gen_final_tap[5].final_val[5][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][3]_i_9 
       (.I0(\smallest_reg[5]__0 [1]),
        .O(\gen_final_tap[5].final_val[5][3]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][5]_i_2 
       (.I0(\gen_final_tap[5].final_val_reg[5][5]_i_4_n_6 ),
        .O(\gen_final_tap[5].final_val[5][5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][5]_i_3 
       (.I0(\gen_final_tap[5].final_val_reg[5][5]_i_4_n_7 ),
        .O(\gen_final_tap[5].final_val[5][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][5]_i_5 
       (.I0(\smallest_reg[5]__0 [5]),
        .O(\gen_final_tap[5].final_val[5][5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[5].final_val[5][5]_i_6 
       (.I0(\smallest_reg[5]__0 [4]),
        .O(\gen_final_tap[5].final_val[5][5]_i_6_n_0 ));
  FDRE \gen_final_tap[5].final_val_reg[5][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[5].final_val_reg[5][3]_i_1_n_7 ),
        .Q(\gen_final_tap[5].final_val_reg[5]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[5].final_val_reg[5][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[5].final_val_reg[5][3]_i_1_n_6 ),
        .Q(\gen_final_tap[5].final_val_reg[5]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[5].final_val_reg[5][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[5].final_val_reg[5][3]_i_1_n_5 ),
        .Q(\gen_final_tap[5].final_val_reg[5]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[5].final_val_reg[5][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[5].final_val_reg[5][3]_i_1_n_4 ),
        .Q(\gen_final_tap[5].final_val_reg[5]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  CARRY4 \gen_final_tap[5].final_val_reg[5][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[5].final_val_reg[5][3]_i_1_n_0 ,\gen_final_tap[5].final_val_reg[5][3]_i_1_n_1 ,\gen_final_tap[5].final_val_reg[5][3]_i_1_n_2 ,\gen_final_tap[5].final_val_reg[5][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[5].final_val_reg[5][3]_i_1_n_4 ,\gen_final_tap[5].final_val_reg[5][3]_i_1_n_5 ,\gen_final_tap[5].final_val_reg[5][3]_i_1_n_6 ,\gen_final_tap[5].final_val_reg[5][3]_i_1_n_7 }),
        .S({\gen_final_tap[5].final_val[5][3]_i_2_n_0 ,\gen_final_tap[5].final_val[5][3]_i_3_n_0 ,\gen_final_tap[5].final_val[5][3]_i_4_n_0 ,\gen_final_tap[5].final_val[5][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[5].final_val_reg[5][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[5].final_val_reg[5][3]_i_6_n_0 ,\gen_final_tap[5].final_val_reg[5][3]_i_6_n_1 ,\gen_final_tap[5].final_val_reg[5][3]_i_6_n_2 ,\gen_final_tap[5].final_val_reg[5][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[5]__0 [3:0]),
        .O({\gen_final_tap[5].final_val_reg[5][3]_i_6_n_4 ,\gen_final_tap[5].final_val_reg[5][3]_i_6_n_5 ,\gen_final_tap[5].final_val_reg[5][3]_i_6_n_6 ,\gen_final_tap[5].final_val_reg[5][3]_i_6_n_7 }),
        .S({\gen_final_tap[5].final_val[5][3]_i_7_n_0 ,\gen_final_tap[5].final_val[5][3]_i_8_n_0 ,\gen_final_tap[5].final_val[5][3]_i_9_n_0 ,\gen_final_tap[5].final_val[5][3]_i_10_n_0 }));
  FDRE \gen_final_tap[5].final_val_reg[5][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[5].final_val_reg[5][5]_i_1_n_7 ),
        .Q(\gen_final_tap[5].final_val_reg[5]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[5].final_val_reg[5][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[5].final_val_reg[5][5]_i_1_n_6 ),
        .Q(\gen_final_tap[5].final_val_reg[5]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  CARRY4 \gen_final_tap[5].final_val_reg[5][5]_i_1 
       (.CI(\gen_final_tap[5].final_val_reg[5][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[5].final_val_reg[5][5]_i_1_CO_UNCONNECTED [3:1],\gen_final_tap[5].final_val_reg[5][5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[5].final_val_reg[5][5]_i_1_O_UNCONNECTED [3:2],\gen_final_tap[5].final_val_reg[5][5]_i_1_n_6 ,\gen_final_tap[5].final_val_reg[5][5]_i_1_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[5].final_val[5][5]_i_2_n_0 ,\gen_final_tap[5].final_val[5][5]_i_3_n_0 }));
  CARRY4 \gen_final_tap[5].final_val_reg[5][5]_i_4 
       (.CI(\gen_final_tap[5].final_val_reg[5][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[5].final_val_reg[5][5]_i_4_CO_UNCONNECTED [3:1],\gen_final_tap[5].final_val_reg[5][5]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[5]__0 [4]}),
        .O({\NLW_gen_final_tap[5].final_val_reg[5][5]_i_4_O_UNCONNECTED [3:2],\gen_final_tap[5].final_val_reg[5][5]_i_4_n_6 ,\gen_final_tap[5].final_val_reg[5][5]_i_4_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[5].final_val[5][5]_i_5_n_0 ,\gen_final_tap[5].final_val[5][5]_i_6_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_10 
       (.I0(\smallest_reg[6]__0 [0]),
        .O(\gen_final_tap[6].final_val[6][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_2 
       (.I0(\gen_final_tap[6].final_val_reg[6][3]_i_6_n_4 ),
        .O(\gen_final_tap[6].final_val[6][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_3 
       (.I0(\gen_final_tap[6].final_val_reg[6][3]_i_6_n_5 ),
        .O(\gen_final_tap[6].final_val[6][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_4 
       (.I0(\gen_final_tap[6].final_val_reg[6][3]_i_6_n_6 ),
        .O(\gen_final_tap[6].final_val[6][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_5 
       (.I0(\gen_final_tap[6].final_val_reg[6][3]_i_6_n_7 ),
        .O(\gen_final_tap[6].final_val[6][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_7 
       (.I0(\smallest_reg[6]__0 [3]),
        .O(\gen_final_tap[6].final_val[6][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_8 
       (.I0(\smallest_reg[6]__0 [2]),
        .O(\gen_final_tap[6].final_val[6][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][3]_i_9 
       (.I0(\smallest_reg[6]__0 [1]),
        .O(\gen_final_tap[6].final_val[6][3]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][5]_i_2 
       (.I0(\gen_final_tap[6].final_val_reg[6][5]_i_4_n_6 ),
        .O(\gen_final_tap[6].final_val[6][5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][5]_i_3 
       (.I0(\gen_final_tap[6].final_val_reg[6][5]_i_4_n_7 ),
        .O(\gen_final_tap[6].final_val[6][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][5]_i_5 
       (.I0(\smallest_reg[6]__0 [5]),
        .O(\gen_final_tap[6].final_val[6][5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[6].final_val[6][5]_i_6 
       (.I0(\smallest_reg[6]__0 [4]),
        .O(\gen_final_tap[6].final_val[6][5]_i_6_n_0 ));
  FDRE \gen_final_tap[6].final_val_reg[6][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[6].final_val_reg[6][3]_i_1_n_7 ),
        .Q(\gen_final_tap[6].final_val_reg[6]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[6].final_val_reg[6][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[6].final_val_reg[6][3]_i_1_n_6 ),
        .Q(\gen_final_tap[6].final_val_reg[6]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[6].final_val_reg[6][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[6].final_val_reg[6][3]_i_1_n_5 ),
        .Q(\gen_final_tap[6].final_val_reg[6]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[6].final_val_reg[6][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[6].final_val_reg[6][3]_i_1_n_4 ),
        .Q(\gen_final_tap[6].final_val_reg[6]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  CARRY4 \gen_final_tap[6].final_val_reg[6][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[6].final_val_reg[6][3]_i_1_n_0 ,\gen_final_tap[6].final_val_reg[6][3]_i_1_n_1 ,\gen_final_tap[6].final_val_reg[6][3]_i_1_n_2 ,\gen_final_tap[6].final_val_reg[6][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[6].final_val_reg[6][3]_i_1_n_4 ,\gen_final_tap[6].final_val_reg[6][3]_i_1_n_5 ,\gen_final_tap[6].final_val_reg[6][3]_i_1_n_6 ,\gen_final_tap[6].final_val_reg[6][3]_i_1_n_7 }),
        .S({\gen_final_tap[6].final_val[6][3]_i_2_n_0 ,\gen_final_tap[6].final_val[6][3]_i_3_n_0 ,\gen_final_tap[6].final_val[6][3]_i_4_n_0 ,\gen_final_tap[6].final_val[6][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[6].final_val_reg[6][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[6].final_val_reg[6][3]_i_6_n_0 ,\gen_final_tap[6].final_val_reg[6][3]_i_6_n_1 ,\gen_final_tap[6].final_val_reg[6][3]_i_6_n_2 ,\gen_final_tap[6].final_val_reg[6][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[6]__0 [3:0]),
        .O({\gen_final_tap[6].final_val_reg[6][3]_i_6_n_4 ,\gen_final_tap[6].final_val_reg[6][3]_i_6_n_5 ,\gen_final_tap[6].final_val_reg[6][3]_i_6_n_6 ,\gen_final_tap[6].final_val_reg[6][3]_i_6_n_7 }),
        .S({\gen_final_tap[6].final_val[6][3]_i_7_n_0 ,\gen_final_tap[6].final_val[6][3]_i_8_n_0 ,\gen_final_tap[6].final_val[6][3]_i_9_n_0 ,\gen_final_tap[6].final_val[6][3]_i_10_n_0 }));
  FDRE \gen_final_tap[6].final_val_reg[6][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[6].final_val_reg[6][5]_i_1_n_7 ),
        .Q(\gen_final_tap[6].final_val_reg[6]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[6].final_val_reg[6][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[6].final_val_reg[6][5]_i_1_n_6 ),
        .Q(\gen_final_tap[6].final_val_reg[6]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  CARRY4 \gen_final_tap[6].final_val_reg[6][5]_i_1 
       (.CI(\gen_final_tap[6].final_val_reg[6][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[6].final_val_reg[6][5]_i_1_CO_UNCONNECTED [3:1],\gen_final_tap[6].final_val_reg[6][5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[6].final_val_reg[6][5]_i_1_O_UNCONNECTED [3:2],\gen_final_tap[6].final_val_reg[6][5]_i_1_n_6 ,\gen_final_tap[6].final_val_reg[6][5]_i_1_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[6].final_val[6][5]_i_2_n_0 ,\gen_final_tap[6].final_val[6][5]_i_3_n_0 }));
  CARRY4 \gen_final_tap[6].final_val_reg[6][5]_i_4 
       (.CI(\gen_final_tap[6].final_val_reg[6][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[6].final_val_reg[6][5]_i_4_CO_UNCONNECTED [3:1],\gen_final_tap[6].final_val_reg[6][5]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[6]__0 [4]}),
        .O({\NLW_gen_final_tap[6].final_val_reg[6][5]_i_4_O_UNCONNECTED [3:2],\gen_final_tap[6].final_val_reg[6][5]_i_4_n_6 ,\gen_final_tap[6].final_val_reg[6][5]_i_4_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[6].final_val[6][5]_i_5_n_0 ,\gen_final_tap[6].final_val[6][5]_i_6_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_10 
       (.I0(\smallest_reg[7]__0 [0]),
        .O(\gen_final_tap[7].final_val[7][3]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_2 
       (.I0(\gen_final_tap[7].final_val_reg[7][3]_i_6_n_4 ),
        .O(\gen_final_tap[7].final_val[7][3]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_3 
       (.I0(\gen_final_tap[7].final_val_reg[7][3]_i_6_n_5 ),
        .O(\gen_final_tap[7].final_val[7][3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_4 
       (.I0(\gen_final_tap[7].final_val_reg[7][3]_i_6_n_6 ),
        .O(\gen_final_tap[7].final_val[7][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_5 
       (.I0(\gen_final_tap[7].final_val_reg[7][3]_i_6_n_7 ),
        .O(\gen_final_tap[7].final_val[7][3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_7 
       (.I0(\smallest_reg[7]__0 [3]),
        .O(\gen_final_tap[7].final_val[7][3]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_8 
       (.I0(\smallest_reg[7]__0 [2]),
        .O(\gen_final_tap[7].final_val[7][3]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][3]_i_9 
       (.I0(\smallest_reg[7]__0 [1]),
        .O(\gen_final_tap[7].final_val[7][3]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][5]_i_2 
       (.I0(\gen_final_tap[7].final_val_reg[7][5]_i_4_n_6 ),
        .O(\gen_final_tap[7].final_val[7][5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][5]_i_3 
       (.I0(\gen_final_tap[7].final_val_reg[7][5]_i_4_n_7 ),
        .O(\gen_final_tap[7].final_val[7][5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][5]_i_5 
       (.I0(\smallest_reg[7]__0 [5]),
        .O(\gen_final_tap[7].final_val[7][5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \gen_final_tap[7].final_val[7][5]_i_6 
       (.I0(\smallest_reg[7]__0 [4]),
        .O(\gen_final_tap[7].final_val[7][5]_i_6_n_0 ));
  FDRE \gen_final_tap[7].final_val_reg[7][0] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[7].final_val_reg[7][3]_i_1_n_7 ),
        .Q(\gen_final_tap[7].final_val_reg[7]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[7].final_val_reg[7][1] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[7].final_val_reg[7][3]_i_1_n_6 ),
        .Q(\gen_final_tap[7].final_val_reg[7]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[7].final_val_reg[7][2] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[7].final_val_reg[7][3]_i_1_n_5 ),
        .Q(\gen_final_tap[7].final_val_reg[7]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[7].final_val_reg[7][3] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[7].final_val_reg[7][3]_i_1_n_4 ),
        .Q(\gen_final_tap[7].final_val_reg[7]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  CARRY4 \gen_final_tap[7].final_val_reg[7][3]_i_1 
       (.CI(1'b0),
        .CO({\gen_final_tap[7].final_val_reg[7][3]_i_1_n_0 ,\gen_final_tap[7].final_val_reg[7][3]_i_1_n_1 ,\gen_final_tap[7].final_val_reg[7][3]_i_1_n_2 ,\gen_final_tap[7].final_val_reg[7][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\gen_final_tap[7].final_val_reg[7][3]_i_1_n_4 ,\gen_final_tap[7].final_val_reg[7][3]_i_1_n_5 ,\gen_final_tap[7].final_val_reg[7][3]_i_1_n_6 ,\gen_final_tap[7].final_val_reg[7][3]_i_1_n_7 }),
        .S({\gen_final_tap[7].final_val[7][3]_i_2_n_0 ,\gen_final_tap[7].final_val[7][3]_i_3_n_0 ,\gen_final_tap[7].final_val[7][3]_i_4_n_0 ,\gen_final_tap[7].final_val[7][3]_i_5_n_0 }));
  CARRY4 \gen_final_tap[7].final_val_reg[7][3]_i_6 
       (.CI(1'b0),
        .CO({\gen_final_tap[7].final_val_reg[7][3]_i_6_n_0 ,\gen_final_tap[7].final_val_reg[7][3]_i_6_n_1 ,\gen_final_tap[7].final_val_reg[7][3]_i_6_n_2 ,\gen_final_tap[7].final_val_reg[7][3]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI(\smallest_reg[7]__0 [3:0]),
        .O({\gen_final_tap[7].final_val_reg[7][3]_i_6_n_4 ,\gen_final_tap[7].final_val_reg[7][3]_i_6_n_5 ,\gen_final_tap[7].final_val_reg[7][3]_i_6_n_6 ,\gen_final_tap[7].final_val_reg[7][3]_i_6_n_7 }),
        .S({\gen_final_tap[7].final_val[7][3]_i_7_n_0 ,\gen_final_tap[7].final_val[7][3]_i_8_n_0 ,\gen_final_tap[7].final_val[7][3]_i_9_n_0 ,\gen_final_tap[7].final_val[7][3]_i_10_n_0 }));
  FDRE \gen_final_tap[7].final_val_reg[7][4] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[7].final_val_reg[7][5]_i_1_n_7 ),
        .Q(\gen_final_tap[7].final_val_reg[7]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \gen_final_tap[7].final_val_reg[7][5] 
       (.C(CLK),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\gen_final_tap[7].final_val_reg[7][5]_i_1_n_6 ),
        .Q(\gen_final_tap[7].final_val_reg[7]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  CARRY4 \gen_final_tap[7].final_val_reg[7][5]_i_1 
       (.CI(\gen_final_tap[7].final_val_reg[7][3]_i_1_n_0 ),
        .CO({\NLW_gen_final_tap[7].final_val_reg[7][5]_i_1_CO_UNCONNECTED [3:1],\gen_final_tap[7].final_val_reg[7][5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_gen_final_tap[7].final_val_reg[7][5]_i_1_O_UNCONNECTED [3:2],\gen_final_tap[7].final_val_reg[7][5]_i_1_n_6 ,\gen_final_tap[7].final_val_reg[7][5]_i_1_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[7].final_val[7][5]_i_2_n_0 ,\gen_final_tap[7].final_val[7][5]_i_3_n_0 }));
  CARRY4 \gen_final_tap[7].final_val_reg[7][5]_i_4 
       (.CI(\gen_final_tap[7].final_val_reg[7][3]_i_6_n_0 ),
        .CO({\NLW_gen_final_tap[7].final_val_reg[7][5]_i_4_CO_UNCONNECTED [3:1],\gen_final_tap[7].final_val_reg[7][5]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\smallest_reg[7]__0 [4]}),
        .O({\NLW_gen_final_tap[7].final_val_reg[7][5]_i_4_O_UNCONNECTED [3:2],\gen_final_tap[7].final_val_reg[7][5]_i_4_n_6 ,\gen_final_tap[7].final_val_reg[7][5]_i_4_n_7 }),
        .S({1'b0,1'b0,\gen_final_tap[7].final_val[7][5]_i_5_n_0 ,\gen_final_tap[7].final_val[7][5]_i_6_n_0 }));
  FDRE \gen_rd[0].rd_data_rise_wl_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .Q(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_rd[1].rd_data_rise_wl_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .Q(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_rd[2].rd_data_rise_wl_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .Q(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_rd[3].rd_data_rise_wl_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .Q(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_rd[4].rd_data_rise_wl_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .Q(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_rd[5].rd_data_rise_wl_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .Q(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_rd[6].rd_data_rise_wl_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .Q(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_rd[7].rd_data_rise_wl_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .Q(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \incdec_wait_cnt[0]_i_1 
       (.I0(incdec_wait_cnt_reg__0[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \incdec_wait_cnt[1]_i_1 
       (.I0(incdec_wait_cnt_reg__0[0]),
        .I1(incdec_wait_cnt_reg__0[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \incdec_wait_cnt[2]_i_1 
       (.I0(incdec_wait_cnt_reg__0[2]),
        .I1(incdec_wait_cnt_reg__0[1]),
        .I2(incdec_wait_cnt_reg__0[0]),
        .O(p_0_in__0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFDFDFDFFF)) 
    \incdec_wait_cnt[3]_i_1 
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(\incdec_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \incdec_wait_cnt[3]_i_2 
       (.I0(incdec_wait_cnt_reg__0[3]),
        .I1(incdec_wait_cnt_reg__0[0]),
        .I2(incdec_wait_cnt_reg__0[1]),
        .I3(incdec_wait_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE \incdec_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(incdec_wait_cnt_reg__0[0]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(incdec_wait_cnt_reg__0[1]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(incdec_wait_cnt_reg__0[2]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(incdec_wait_cnt_reg__0[3]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAABABBBBAA8A8888)) 
    inhibit_edge_detect_r_i_1
       (.I0(inhibit_edge_detect_r_i_2_n_0),
        .I1(inhibit_edge_detect_r_i_3_n_0),
        .I2(Q[2]),
        .I3(inhibit_edge_detect_r_i_4_n_0),
        .I4(inhibit_edge_detect_r_i_5_n_0),
        .I5(inhibit_edge_detect_r_reg_n_0),
        .O(inhibit_edge_detect_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h2FEF2FEF20E02FEF)) 
    inhibit_edge_detect_r_i_2
       (.I0(flag_ck_negedge_reg_i_4_n_0),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(\fine_dec_cnt[5]_i_7_n_0 ),
        .I4(Q[2]),
        .I5(wrlvl_byte_redo),
        .O(inhibit_edge_detect_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000F80000)) 
    inhibit_edge_detect_r_i_3
       (.I0(inhibit_edge_detect_r_i_6_n_0),
        .I1(wl_sm_start),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(\stable_cnt[3]_i_7_n_0 ),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(Q[1]),
        .O(inhibit_edge_detect_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT5 #(
    .INIT(32'h01000000)) 
    inhibit_edge_detect_r_i_4
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I3(Q[0]),
        .I4(wrlvl_byte_redo),
        .O(inhibit_edge_detect_r_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT3 #(
    .INIT(8'h01)) 
    inhibit_edge_detect_r_i_5
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .O(inhibit_edge_detect_r_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    inhibit_edge_detect_r_i_6
       (.I0(\stable_cnt_reg_n_0_[1] ),
        .I1(\stable_cnt_reg_n_0_[2] ),
        .I2(\stable_cnt_reg_n_0_[3] ),
        .I3(flag_ck_negedge_reg_i_4_n_0),
        .O(inhibit_edge_detect_r_i_6_n_0));
  FDSE inhibit_edge_detect_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(inhibit_edge_detect_r_i_1_n_0),
        .Q(inhibit_edge_detect_r_reg_n_0),
        .S(rstdiv0_sync_r1_reg_rep__10[0]));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    phaser_out_i_1
       (.I0(\calib_zero_inputs_reg[2] [1]),
        .I1(po_stg2_c_incdec),
        .I2(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .O(D_po_coarse_enable105_out));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT5 #(
    .INIT(32'h00000400)) 
    phaser_out_i_1__0
       (.I0(\calib_zero_inputs_reg[2] [1]),
        .I1(po_stg2_c_incdec),
        .I2(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\calib_sel_reg[1] [0]),
        .O(C_po_coarse_enable66_out));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT5 #(
    .INIT(32'h00000400)) 
    phaser_out_i_1__1
       (.I0(\calib_zero_inputs_reg[2] [1]),
        .I1(po_stg2_c_incdec),
        .I2(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\calib_sel_reg[1] [1]),
        .O(B_po_coarse_enable27_out));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    phaser_out_i_1__2
       (.I0(\calib_zero_inputs_reg[2] [1]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_po_coarse_enable143_out));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT5 #(
    .INIT(32'h44444000)) 
    phaser_out_i_1__3
       (.I0(\calib_zero_inputs_reg[2] [0]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(D_po_coarse_enable72_out));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    phaser_out_i_1__4
       (.I0(\calib_zero_inputs_reg[2] [0]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(C_po_coarse_enable46_out));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    phaser_out_i_1__5
       (.I0(\calib_zero_inputs_reg[2] [0]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(B_po_coarse_enable20_out));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    phaser_out_i_1__6
       (.I0(\calib_zero_inputs_reg[2] [0]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_po_coarse_enable98_out));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT5 #(
    .INIT(32'h44440040)) 
    phaser_out_i_1__7
       (.I0(\calib_zero_inputs_reg[2] [2]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(C_po_coarse_enable43_out));
  LUT5 #(
    .INIT(32'h44440040)) 
    phaser_out_i_1__8
       (.I0(\calib_zero_inputs_reg[2] [2]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(B_po_coarse_enable17_out));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT5 #(
    .INIT(32'h44440004)) 
    phaser_out_i_1__9
       (.I0(\calib_zero_inputs_reg[2] [2]),
        .I1(po_stg2_c_incdec),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .I4(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .O(A_po_coarse_enable69_out));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    phaser_out_i_3__0
       (.I0(phaser_out_i_5_n_0),
        .I1(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .O(B_po_fine_enable24_out));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    phaser_out_i_3__1
       (.I0(phaser_out_i_5_n_0),
        .I1(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I2(\calib_sel_reg[1] [1]),
        .I3(\calib_sel_reg[1] [0]),
        .O(C_po_fine_enable63_out));
  LUT4 #(
    .INIT(16'h2000)) 
    phaser_out_i_3__2
       (.I0(phaser_out_i_5_n_0),
        .I1(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I2(\calib_sel_reg[1] [0]),
        .I3(\calib_sel_reg[1] [1]),
        .O(D_po_fine_enable102_out));
  LUT4 #(
    .INIT(16'h00FE)) 
    phaser_out_i_5
       (.I0(dqs_po_en_stg2_f),
        .I1(ck_po_stg2_f_en),
        .I2(cmd_po_en_stg2_f),
        .I3(\calib_zero_inputs_reg[2] [1]),
        .O(phaser_out_i_5_n_0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 " *) 
  SRL16E phy_ctl_ready_r4_reg_srl4
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(phy_ctl_ready),
        .Q(phy_ctl_ready_r4_reg_srl4_n_0));
  FDRE phy_ctl_ready_r5_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_ready_r4_reg_srl4_n_0),
        .Q(phy_ctl_ready_r5),
        .R(1'b0));
  FDRE phy_ctl_ready_r6_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_ready_r5),
        .Q(phy_ctl_ready_r6_reg_n_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    po_cnt_dec_i_1
       (.I0(po_cnt_dec_i_2_n_0),
        .I1(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(po_cnt_dec_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000100000)) 
    po_cnt_dec_i_2
       (.I0(wait_cnt_reg__0[2]),
        .I1(wait_cnt_reg__0[1]),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(rstdiv0_sync_r1_reg_rep__24),
        .I4(wait_cnt_reg__0[0]),
        .I5(wait_cnt_reg__0[3]),
        .O(po_cnt_dec_i_2_n_0));
  FDRE po_cnt_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_cnt_dec_i_1_n_0),
        .Q(dqs_po_en_stg2_f_reg_0),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF4)) 
    po_dec_done_i_1
       (.I0(po_dec_done_i_2_n_0),
        .I1(po_dec_done_i_3_n_0),
        .I2(po_dec_done),
        .O(po_dec_done_i_1_n_0));
  LUT5 #(
    .INIT(32'hEEEFFFEF)) 
    po_dec_done_i_2
       (.I0(\po_rdval_cnt_reg_n_0_[2] ),
        .I1(\po_rdval_cnt_reg_n_0_[1] ),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt_reg_n_0_[0] ),
        .I4(dqs_po_en_stg2_f_reg_0),
        .O(po_dec_done_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    po_dec_done_i_3
       (.I0(\po_rdval_cnt_reg_n_0_[3] ),
        .I1(\po_rdval_cnt_reg_n_0_[4] ),
        .I2(\po_rdval_cnt_reg_n_0_[7] ),
        .I3(\po_rdval_cnt_reg_n_0_[8] ),
        .I4(\po_rdval_cnt_reg_n_0_[6] ),
        .I5(\po_rdval_cnt_reg_n_0_[5] ),
        .O(po_dec_done_i_3_n_0));
  FDRE po_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_dec_done_i_1_n_0),
        .Q(po_dec_done),
        .R(rstdiv0_sync_r1_reg_rep__4));
  LUT5 #(
    .INIT(32'h080808FB)) 
    \po_rdval_cnt[0]_i_1 
       (.I0(\po_counter_read_val_reg[0] ),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt_reg_n_0_[0] ),
        .I4(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h08080808FB0808FB)) 
    \po_rdval_cnt[1]_i_1 
       (.I0(\po_counter_read_val_reg[1] ),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt_reg_n_0_[0] ),
        .I4(\po_rdval_cnt_reg_n_0_[1] ),
        .I5(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB8888B)) 
    \po_rdval_cnt[2]_i_1 
       (.I0(\po_counter_read_val_reg[2] ),
        .I1(\po_rdval_cnt[8]_i_5_n_0 ),
        .I2(\po_rdval_cnt_reg_n_0_[1] ),
        .I3(\po_rdval_cnt_reg_n_0_[0] ),
        .I4(\po_rdval_cnt_reg_n_0_[2] ),
        .I5(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \po_rdval_cnt[3]_i_2 
       (.I0(\po_rdval_cnt_reg_n_0_[3] ),
        .I1(po_dec_done_i_3_n_0),
        .I2(\po_rdval_cnt_reg_n_0_[0] ),
        .I3(\po_rdval_cnt_reg_n_0_[1] ),
        .I4(\po_rdval_cnt_reg_n_0_[2] ),
        .O(\po_rdval_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \po_rdval_cnt[4]_i_2 
       (.I0(\po_rdval_cnt_reg_n_0_[4] ),
        .I1(\po_rdval_cnt_reg_n_0_[3] ),
        .I2(\po_rdval_cnt_reg_n_0_[2] ),
        .I3(\po_rdval_cnt_reg_n_0_[1] ),
        .I4(\po_rdval_cnt_reg_n_0_[0] ),
        .I5(po_dec_done_i_3_n_0),
        .O(\po_rdval_cnt[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0FF00FE0)) 
    \po_rdval_cnt[5]_i_2 
       (.I0(\po_rdval_cnt_reg_n_0_[8] ),
        .I1(\po_rdval_cnt_reg_n_0_[7] ),
        .I2(\po_rdval_cnt[5]_i_4_n_0 ),
        .I3(\po_rdval_cnt_reg_n_0_[5] ),
        .I4(\po_rdval_cnt_reg_n_0_[6] ),
        .O(\po_rdval_cnt[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \po_rdval_cnt[5]_i_4 
       (.I0(\po_rdval_cnt_reg_n_0_[2] ),
        .I1(\po_rdval_cnt_reg_n_0_[1] ),
        .I2(\po_rdval_cnt_reg_n_0_[0] ),
        .I3(\po_rdval_cnt_reg_n_0_[3] ),
        .I4(\po_rdval_cnt_reg_n_0_[4] ),
        .O(\po_rdval_cnt[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h8888BBBBBBB88888)) 
    \po_rdval_cnt[6]_i_1 
       (.I0(\po_counter_read_val_reg[6] ),
        .I1(\po_rdval_cnt[8]_i_5_n_0 ),
        .I2(\po_rdval_cnt_reg_n_0_[8] ),
        .I3(\po_rdval_cnt_reg_n_0_[7] ),
        .I4(\po_rdval_cnt[8]_i_6_n_0 ),
        .I5(\po_rdval_cnt_reg_n_0_[6] ),
        .O(\po_rdval_cnt[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBB88BBBB88B88888)) 
    \po_rdval_cnt[7]_i_1 
       (.I0(\po_counter_read_val_reg[7] ),
        .I1(\po_rdval_cnt[8]_i_5_n_0 ),
        .I2(\po_rdval_cnt_reg_n_0_[8] ),
        .I3(\po_rdval_cnt_reg_n_0_[6] ),
        .I4(\po_rdval_cnt[8]_i_6_n_0 ),
        .I5(\po_rdval_cnt_reg_n_0_[7] ),
        .O(\po_rdval_cnt[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFAE)) 
    \po_rdval_cnt[8]_i_1 
       (.I0(dqs_po_en_stg2_f_reg_0),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \po_rdval_cnt[8]_i_2 
       (.I0(\po_counter_read_val_reg[8] ),
        .I1(\po_rdval_cnt[8]_i_5_n_0 ),
        .I2(\po_rdval_cnt_reg_n_0_[8] ),
        .I3(\po_rdval_cnt_reg_n_0_[6] ),
        .I4(\po_rdval_cnt[8]_i_6_n_0 ),
        .I5(\po_rdval_cnt_reg_n_0_[7] ),
        .O(\po_rdval_cnt[8]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \po_rdval_cnt[8]_i_3 
       (.I0(\po_rdval_cnt_reg_n_0_[6] ),
        .I1(\po_rdval_cnt[8]_i_6_n_0 ),
        .I2(\po_rdval_cnt_reg_n_0_[7] ),
        .I3(\po_rdval_cnt_reg_n_0_[8] ),
        .O(\po_rdval_cnt[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \po_rdval_cnt[8]_i_5 
       (.I0(phy_ctl_ready_r5),
        .I1(phy_ctl_ready_r6_reg_n_0),
        .O(\po_rdval_cnt[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \po_rdval_cnt[8]_i_6 
       (.I0(\po_rdval_cnt_reg_n_0_[4] ),
        .I1(\po_rdval_cnt_reg_n_0_[3] ),
        .I2(\po_rdval_cnt_reg_n_0_[0] ),
        .I3(\po_rdval_cnt_reg_n_0_[1] ),
        .I4(\po_rdval_cnt_reg_n_0_[2] ),
        .I5(\po_rdval_cnt_reg_n_0_[5] ),
        .O(\po_rdval_cnt[8]_i_6_n_0 ));
  FDRE \po_rdval_cnt_reg[0] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[0]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \po_rdval_cnt_reg[1] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[1]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \po_rdval_cnt_reg[2] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[2]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \po_rdval_cnt_reg[3] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt_reg[3]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  MUXF7 \po_rdval_cnt_reg[3]_i_1 
       (.I0(\po_rdval_cnt[3]_i_2_n_0 ),
        .I1(\po_counter_read_val_reg[3] ),
        .O(\po_rdval_cnt_reg[3]_i_1_n_0 ),
        .S(\po_rdval_cnt[8]_i_5_n_0 ));
  FDRE \po_rdval_cnt_reg[4] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt_reg[4]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  MUXF7 \po_rdval_cnt_reg[4]_i_1 
       (.I0(\po_rdval_cnt[4]_i_2_n_0 ),
        .I1(\po_counter_read_val_reg[4] ),
        .O(\po_rdval_cnt_reg[4]_i_1_n_0 ),
        .S(\po_rdval_cnt[8]_i_5_n_0 ));
  FDRE \po_rdval_cnt_reg[5] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt_reg[5]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  MUXF7 \po_rdval_cnt_reg[5]_i_1 
       (.I0(\po_rdval_cnt[5]_i_2_n_0 ),
        .I1(\po_counter_read_val_reg[5] ),
        .O(\po_rdval_cnt_reg[5]_i_1_n_0 ),
        .S(\po_rdval_cnt[8]_i_5_n_0 ));
  FDRE \po_rdval_cnt_reg[6] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[6]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[6] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \po_rdval_cnt_reg[7] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[7]_i_1_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[7] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \po_rdval_cnt_reg[8] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[8]_i_2_n_0 ),
        .Q(\po_rdval_cnt_reg_n_0_[8] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[0]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[0] ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[1]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[1] ),
        .I2(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[2]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[2] ),
        .I2(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[3]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[3] ),
        .I2(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[4]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[4] ),
        .I2(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[5]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[5] ),
        .I2(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[6]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[6] ),
        .I2(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \rd_data_edge_detect_r[7]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I1(flag_ck_negedge_reg_n_0),
        .I2(inhibit_edge_detect_r_reg_n_0),
        .I3(rstdiv0_sync_r1_reg_rep__23),
        .I4(flag_init),
        .O(rd_data_edge_detect_r0));
  LUT5 #(
    .INIT(32'h6044FFFF)) 
    \rd_data_edge_detect_r[7]_i_2 
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(Q[2]),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[7]_i_3 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[7] ),
        .I2(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rd_data_edge_detect_r[7]_i_4 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\wl_tap_count_r_reg_n_0_[2] ),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .I4(\wl_tap_count_r_reg_n_0_[5] ),
        .I5(\wl_tap_count_r_reg_n_0_[4] ),
        .O(\rd_data_edge_detect_r[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT4 #(
    .INIT(16'h80FF)) 
    \rd_data_edge_detect_r[7]_i_6 
       (.I0(\stable_cnt_reg_n_0_[1] ),
        .I1(\stable_cnt_reg_n_0_[2] ),
        .I2(\stable_cnt_reg_n_0_[3] ),
        .I3(flag_ck_negedge_reg_i_4_n_0),
        .O(\rd_data_edge_detect_r[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data_edge_detect_r[7]_i_7 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[3] ),
        .I1(\rd_data_edge_detect_r_reg_n_0_[2] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .O(\rd_data_edge_detect_r[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data_edge_detect_r[7]_i_8 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[7] ),
        .I1(\rd_data_edge_detect_r_reg_n_0_[6] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\rd_data_edge_detect_r_reg_n_0_[5] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\rd_data_edge_detect_r_reg_n_0_[4] ),
        .O(\rd_data_edge_detect_r[7]_i_8_n_0 ));
  FDRE \rd_data_edge_detect_r_reg[0] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[0]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[1] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[1]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[2] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[2]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[2] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[3] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[3]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[3] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[4] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[4]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[4] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[5] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[5]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[5] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[6] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[6]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[6] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[7] 
       (.C(CLK),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[7]_i_3_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[7] ),
        .R(rd_data_edge_detect_r0));
  MUXF7 \rd_data_edge_detect_r_reg[7]_i_5 
       (.I0(\rd_data_edge_detect_r[7]_i_7_n_0 ),
        .I1(\rd_data_edge_detect_r[7]_i_8_n_0 ),
        .O(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .S(dqs_count_r[2]));
  LUT6 #(
    .INIT(64'hBBEEAAAAAAEEAAFE)) 
    \rd_data_previous_r[7]_i_1 
       (.I0(\rd_data_previous_r[7]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .I5(Q[1]),
        .O(rd_data_previous_r0));
  LUT6 #(
    .INIT(64'h0200FFFF02000200)) 
    \rd_data_previous_r[7]_i_2 
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(\rd_data_previous_r[7]_i_3_n_0 ),
        .I4(\rd_data_previous_r[7]_i_4_n_0 ),
        .I5(\rd_data_previous_r[7]_i_5_n_0 ),
        .O(\rd_data_previous_r[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rd_data_previous_r[7]_i_3 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(wl_edge_detect_valid_r_reg_n_0),
        .I2(Q[0]),
        .O(\rd_data_previous_r[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT5 #(
    .INIT(32'hFFFFFFEF)) 
    \rd_data_previous_r[7]_i_4 
       (.I0(\wl_state_r1_reg_n_0_[0] ),
        .I1(\wl_state_r1_reg_n_0_[4] ),
        .I2(\wl_state_r1_reg_n_0_[2] ),
        .I3(\wl_state_r1_reg_n_0_[3] ),
        .I4(\wl_state_r1_reg_n_0_[1] ),
        .O(\rd_data_previous_r[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \rd_data_previous_r[7]_i_5 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .O(\rd_data_previous_r[7]_i_5_n_0 ));
  FDRE \rd_data_previous_r_reg[0] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .Q(\rd_data_previous_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[1] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .Q(\rd_data_previous_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[2] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .Q(\rd_data_previous_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[3] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .Q(\rd_data_previous_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[4] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .Q(\rd_data_previous_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[5] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .Q(\rd_data_previous_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[6] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .Q(\rd_data_previous_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[7] 
       (.C(CLK),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .Q(\rd_data_previous_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000BA)) 
    \single_rank.done_dqs_dec_i_1 
       (.I0(done_dqs_tap_inc),
        .I1(wr_level_done_r4),
        .I2(wr_level_done_r3),
        .I3(wr_level_done0),
        .I4(rstdiv0_sync_r1_reg_rep__24),
        .O(\single_rank.done_dqs_dec_i_1_n_0 ));
  FDRE \single_rank.done_dqs_dec_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\single_rank.done_dqs_dec_i_1_n_0 ),
        .Q(done_dqs_tap_inc),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[0][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(largest[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][0]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),
        .O(\smallest[0][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][0]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][0] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][0] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][0] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][0] ),
        .O(\smallest[0][0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[0][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(largest[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][1]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),
        .O(\smallest[0][1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][1]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][1] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][1] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][1] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][1] ),
        .O(\smallest[0][1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[0][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(largest[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][2]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),
        .O(\smallest[0][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][2]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][2] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][2] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][2] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][2] ),
        .O(\smallest[0][2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[0][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(largest[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][3]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),
        .O(\smallest[0][3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][3]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][3] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][3] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][3] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][3] ),
        .O(\smallest[0][3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[0][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(largest[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][4]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),
        .O(\smallest[0][4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][4]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][4] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][4] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][4] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][4] ),
        .O(\smallest[0][4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \smallest[0][5]_i_1 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(\smallest_reg[7][0]_0 ),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[0][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[0][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(largest[5]));
  LUT5 #(
    .INIT(32'hFFDFFDFF)) 
    \smallest[0][5]_i_3 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .O(\smallest[0][5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][5]_i_5 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),
        .O(\smallest[0][5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][5]_i_6 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][5] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][5] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][5] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][5] ),
        .O(\smallest[0][5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[1][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(\smallest[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[1][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(\smallest[1][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[1][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(\smallest[1][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[1][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(\smallest[1][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[1][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(\smallest[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000004)) 
    \smallest[1][5]_i_1 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(\smallest_reg[7][0]_0 ),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[1][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[1][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(\smallest[1][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[2][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(\smallest[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[2][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(\smallest[2][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[2][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(\smallest[2][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[2][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(\smallest[2][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[2][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(\smallest[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000004)) 
    \smallest[2][5]_i_1 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(\smallest_reg[7][0]_0 ),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[2][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[2][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(\smallest[2][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[3][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(\smallest[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[3][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(\smallest[3][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[3][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(\smallest[3][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[3][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(\smallest[3][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[3][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(\smallest[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000008)) 
    \smallest[3][5]_i_1 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(\smallest_reg[7][0]_0 ),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[3][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[3][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(\smallest[3][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[4][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][4][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(\smallest[4][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[4][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][4][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(\smallest[4][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[4][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][4][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(\smallest[4][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[4][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][4][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(\smallest[4][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[4][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][4][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(\smallest[4][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000004)) 
    \smallest[4][5]_i_1 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\smallest_reg[7][0]_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[4][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[4][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][4][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(\smallest[4][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[5][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][5][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(\smallest[5][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[5][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][5][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(\smallest[5][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[5][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][5][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(\smallest[5][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[5][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][5][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(\smallest[5][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[5][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][5][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(\smallest[5][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000400)) 
    \smallest[5][5]_i_1 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\smallest_reg[7][0]_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[5][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[5][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][5][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(\smallest[5][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[6][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][6][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(\smallest[6][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[6][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][6][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(\smallest[6][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[6][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][6][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(\smallest[6][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[6][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][6][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(\smallest[6][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[6][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][6][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(\smallest[6][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000400)) 
    \smallest[6][5]_i_1 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\smallest_reg[7][0]_0 ),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[6][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[6][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][6][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(\smallest[6][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[7][0]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][0] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][0]_i_2_n_0 ),
        .O(\smallest[7][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[7][1]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][1] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][1]_i_2_n_0 ),
        .O(\smallest[7][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[7][2]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][2] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][2]_i_2_n_0 ),
        .O(\smallest[7][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[7][3]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][3] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][3]_i_2_n_0 ),
        .O(\smallest[7][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[7][4]_i_1 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][4] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][4]_i_2_n_0 ),
        .O(\smallest[7][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \smallest[7][5]_i_1 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[7][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \smallest[7][5]_i_2 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][5] ),
        .I1(\smallest[0][5]_i_3_n_0 ),
        .I2(\smallest_reg[0][5]_i_4_n_0 ),
        .O(\smallest[7][5]_i_2_n_0 ));
  FDRE \smallest_reg[0][0] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[0]),
        .Q(\smallest_reg[0]__0 [0]),
        .R(SR));
  MUXF7 \smallest_reg[0][0]_i_2 
       (.I0(\smallest[0][0]_i_3_n_0 ),
        .I1(\smallest[0][0]_i_4_n_0 ),
        .O(\smallest_reg[0][0]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][1] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[1]),
        .Q(\smallest_reg[0]__0 [1]),
        .R(SR));
  MUXF7 \smallest_reg[0][1]_i_2 
       (.I0(\smallest[0][1]_i_3_n_0 ),
        .I1(\smallest[0][1]_i_4_n_0 ),
        .O(\smallest_reg[0][1]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][2] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[2]),
        .Q(\smallest_reg[0]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \smallest_reg[0][2]_i_2 
       (.I0(\smallest[0][2]_i_3_n_0 ),
        .I1(\smallest[0][2]_i_4_n_0 ),
        .O(\smallest_reg[0][2]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][3] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[3]),
        .Q(\smallest_reg[0]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \smallest_reg[0][3]_i_2 
       (.I0(\smallest[0][3]_i_3_n_0 ),
        .I1(\smallest[0][3]_i_4_n_0 ),
        .O(\smallest_reg[0][3]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][4] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[4]),
        .Q(\smallest_reg[0]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \smallest_reg[0][4]_i_2 
       (.I0(\smallest[0][4]_i_3_n_0 ),
        .I1(\smallest[0][4]_i_4_n_0 ),
        .O(\smallest_reg[0][4]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][5] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[5]),
        .Q(\smallest_reg[0]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \smallest_reg[0][5]_i_4 
       (.I0(\smallest[0][5]_i_5_n_0 ),
        .I1(\smallest[0][5]_i_6_n_0 ),
        .O(\smallest_reg[0][5]_i_4_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[1][0] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][0]_i_1_n_0 ),
        .Q(\smallest_reg[1]__0 [0]),
        .R(SR));
  FDRE \smallest_reg[1][1] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][1]_i_1_n_0 ),
        .Q(\smallest_reg[1]__0 [1]),
        .R(SR));
  FDRE \smallest_reg[1][2] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][2]_i_1_n_0 ),
        .Q(\smallest_reg[1]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[1][3] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][3]_i_1_n_0 ),
        .Q(\smallest_reg[1]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[1][4] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][4]_i_1_n_0 ),
        .Q(\smallest_reg[1]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[1][5] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][5]_i_2_n_0 ),
        .Q(\smallest_reg[1]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[2][0] 
       (.C(CLK),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][0]_i_1_n_0 ),
        .Q(\smallest_reg[2]__0 [0]),
        .R(SR));
  FDRE \smallest_reg[2][1] 
       (.C(CLK),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][1]_i_1_n_0 ),
        .Q(\smallest_reg[2]__0 [1]),
        .R(SR));
  FDRE \smallest_reg[2][2] 
       (.C(CLK),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][2]_i_1_n_0 ),
        .Q(\smallest_reg[2]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[2][3] 
       (.C(CLK),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][3]_i_1_n_0 ),
        .Q(\smallest_reg[2]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[2][4] 
       (.C(CLK),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][4]_i_1_n_0 ),
        .Q(\smallest_reg[2]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[2][5] 
       (.C(CLK),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][5]_i_2_n_0 ),
        .Q(\smallest_reg[2]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[3][0] 
       (.C(CLK),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][0]_i_1_n_0 ),
        .Q(\smallest_reg[3]__0 [0]),
        .R(SR));
  FDRE \smallest_reg[3][1] 
       (.C(CLK),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][1]_i_1_n_0 ),
        .Q(\smallest_reg[3]__0 [1]),
        .R(SR));
  FDRE \smallest_reg[3][2] 
       (.C(CLK),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][2]_i_1_n_0 ),
        .Q(\smallest_reg[3]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[3][3] 
       (.C(CLK),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][3]_i_1_n_0 ),
        .Q(\smallest_reg[3]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[3][4] 
       (.C(CLK),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][4]_i_1_n_0 ),
        .Q(\smallest_reg[3]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[3][5] 
       (.C(CLK),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][5]_i_2_n_0 ),
        .Q(\smallest_reg[3]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[4][0] 
       (.C(CLK),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][0]_i_1_n_0 ),
        .Q(\smallest_reg[4]__0 [0]),
        .R(SR));
  FDRE \smallest_reg[4][1] 
       (.C(CLK),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][1]_i_1_n_0 ),
        .Q(\smallest_reg[4]__0 [1]),
        .R(SR));
  FDRE \smallest_reg[4][2] 
       (.C(CLK),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][2]_i_1_n_0 ),
        .Q(\smallest_reg[4]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[4][3] 
       (.C(CLK),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][3]_i_1_n_0 ),
        .Q(\smallest_reg[4]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[4][4] 
       (.C(CLK),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][4]_i_1_n_0 ),
        .Q(\smallest_reg[4]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[4][5] 
       (.C(CLK),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][5]_i_2_n_0 ),
        .Q(\smallest_reg[4]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[5][0] 
       (.C(CLK),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][0]_i_1_n_0 ),
        .Q(\smallest_reg[5]__0 [0]),
        .R(SR));
  FDRE \smallest_reg[5][1] 
       (.C(CLK),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][1]_i_1_n_0 ),
        .Q(\smallest_reg[5]__0 [1]),
        .R(SR));
  FDRE \smallest_reg[5][2] 
       (.C(CLK),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][2]_i_1_n_0 ),
        .Q(\smallest_reg[5]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[5][3] 
       (.C(CLK),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][3]_i_1_n_0 ),
        .Q(\smallest_reg[5]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[5][4] 
       (.C(CLK),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][4]_i_1_n_0 ),
        .Q(\smallest_reg[5]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[5][5] 
       (.C(CLK),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][5]_i_2_n_0 ),
        .Q(\smallest_reg[5]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[6][0] 
       (.C(CLK),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][0]_i_1_n_0 ),
        .Q(\smallest_reg[6]__0 [0]),
        .R(SR));
  FDRE \smallest_reg[6][1] 
       (.C(CLK),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][1]_i_1_n_0 ),
        .Q(\smallest_reg[6]__0 [1]),
        .R(SR));
  FDRE \smallest_reg[6][2] 
       (.C(CLK),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][2]_i_1_n_0 ),
        .Q(\smallest_reg[6]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[6][3] 
       (.C(CLK),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][3]_i_1_n_0 ),
        .Q(\smallest_reg[6]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[6][4] 
       (.C(CLK),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][4]_i_1_n_0 ),
        .Q(\smallest_reg[6]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[6][5] 
       (.C(CLK),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][5]_i_2_n_0 ),
        .Q(\smallest_reg[6]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[7][0] 
       (.C(CLK),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][0]_i_1_n_0 ),
        .Q(\smallest_reg[7]__0 [0]),
        .R(SR));
  FDRE \smallest_reg[7][1] 
       (.C(CLK),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][1]_i_1_n_0 ),
        .Q(\smallest_reg[7]__0 [1]),
        .R(SR));
  FDRE \smallest_reg[7][2] 
       (.C(CLK),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][2]_i_1_n_0 ),
        .Q(\smallest_reg[7]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[7][3] 
       (.C(CLK),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][3]_i_1_n_0 ),
        .Q(\smallest_reg[7]__0 [3]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[7][4] 
       (.C(CLK),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][4]_i_1_n_0 ),
        .Q(\smallest_reg[7]__0 [4]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \smallest_reg[7][5] 
       (.C(CLK),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][5]_i_2_n_0 ),
        .Q(\smallest_reg[7]__0 [5]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  LUT1 #(
    .INIT(2'h1)) 
    \stable_cnt[0]_i_1 
       (.I0(\stable_cnt_reg_n_0_[0] ),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \stable_cnt[1]_i_1 
       (.I0(\stable_cnt_reg_n_0_[0] ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \stable_cnt[2]_i_1 
       (.I0(\stable_cnt_reg_n_0_[2] ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .I2(\stable_cnt_reg_n_0_[0] ),
        .O(p_0_in[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEEFE)) 
    \stable_cnt[3]_i_1 
       (.I0(\stable_cnt[3]_i_4_n_0 ),
        .I1(\stable_cnt[3]_i_5_n_0 ),
        .I2(\stable_cnt[3]_i_6_n_0 ),
        .I3(\stable_cnt[3]_i_7_n_0 ),
        .I4(rstdiv0_sync_r1_reg_rep__23),
        .I5(\stable_cnt[3]_i_8_n_0 ),
        .O(stable_cnt0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \stable_cnt[3]_i_10 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .I1(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .O(\stable_cnt[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000015550000)) 
    \stable_cnt[3]_i_2 
       (.I0(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .I2(\stable_cnt_reg_n_0_[2] ),
        .I3(\stable_cnt_reg_n_0_[3] ),
        .I4(\rd_data_previous_r[7]_i_2_n_0 ),
        .I5(\stable_cnt[3]_i_4_n_0 ),
        .O(stable_cnt));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \stable_cnt[3]_i_3 
       (.I0(\stable_cnt_reg_n_0_[3] ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .I2(\stable_cnt_reg_n_0_[2] ),
        .I3(\stable_cnt_reg_n_0_[0] ),
        .O(p_0_in[3]));
  LUT4 #(
    .INIT(16'h56A6)) 
    \stable_cnt[3]_i_4 
       (.I0(flag_ck_negedge_reg_i_4_n_0),
        .I1(\stable_cnt[3]_i_9_n_0 ),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(\stable_cnt[3]_i_10_n_0 ),
        .O(\stable_cnt[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \stable_cnt[3]_i_5 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[1]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[2]),
        .I4(Q[0]),
        .O(\stable_cnt[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \stable_cnt[3]_i_6 
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(Q[1]),
        .O(\stable_cnt[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \stable_cnt[3]_i_7 
       (.I0(Q[2]),
        .I1(Q[0]),
        .O(\stable_cnt[3]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT5 #(
    .INIT(32'h00000020)) 
    \stable_cnt[3]_i_8 
       (.I0(\wl_state_r1_reg_n_0_[0] ),
        .I1(\wl_state_r1_reg_n_0_[4] ),
        .I2(\wl_state_r1_reg_n_0_[2] ),
        .I3(\wl_state_r1_reg_n_0_[3] ),
        .I4(\wl_state_r1_reg_n_0_[1] ),
        .O(\stable_cnt[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \stable_cnt[3]_i_9 
       (.I0(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .O(\stable_cnt[3]_i_9_n_0 ));
  FDRE \stable_cnt_reg[0] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in[0]),
        .Q(\stable_cnt_reg_n_0_[0] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[1] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in[1]),
        .Q(\stable_cnt_reg_n_0_[1] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[2] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in[2]),
        .Q(\stable_cnt_reg_n_0_[2] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[3] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in[3]),
        .Q(\stable_cnt_reg_n_0_[3] ),
        .R(stable_cnt0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt[0]_i_1 
       (.I0(wait_cnt_reg__0[0]),
        .O(wait_cnt0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt[1]_i_1 
       (.I0(wait_cnt_reg__0[0]),
        .I1(wait_cnt_reg__0[1]),
        .O(\wait_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt[2]_i_1 
       (.I0(wait_cnt_reg__0[2]),
        .I1(wait_cnt_reg__0[1]),
        .I2(wait_cnt_reg__0[0]),
        .O(wait_cnt0__0[2]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \wait_cnt[3]_i_2 
       (.I0(phy_ctl_ready_r6_reg_n_0),
        .I1(wait_cnt_reg__0[3]),
        .I2(wait_cnt_reg__0[1]),
        .I3(wait_cnt_reg__0[0]),
        .I4(wait_cnt_reg__0[2]),
        .O(wait_cnt0));
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt[3]_i_3 
       (.I0(wait_cnt_reg__0[3]),
        .I1(wait_cnt_reg__0[2]),
        .I2(wait_cnt_reg__0[0]),
        .I3(wait_cnt_reg__0[1]),
        .O(wait_cnt0__0[3]));
  FDRE \wait_cnt_reg[0] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[0]),
        .Q(wait_cnt_reg__0[0]),
        .R(SS));
  FDRE \wait_cnt_reg[1] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(\wait_cnt[1]_i_1_n_0 ),
        .Q(wait_cnt_reg__0[1]),
        .R(SS));
  FDRE \wait_cnt_reg[2] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[2]),
        .Q(wait_cnt_reg__0[2]),
        .R(SS));
  FDSE \wait_cnt_reg[3] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[3]),
        .Q(wait_cnt_reg__0[3]),
        .S(SS));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][0]_i_2 
       (.I0(\corse_cnt_reg_n_0_[3][0] ),
        .I1(\corse_cnt_reg_n_0_[2][0] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_cnt_reg_n_0_[1][0] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_cnt_reg_n_0_[0][0] ),
        .O(\wl_corse_cnt[0][0][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][0]_i_3 
       (.I0(\corse_cnt_reg_n_0_[7][0] ),
        .I1(\corse_cnt_reg_n_0_[6][0] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_cnt_reg_n_0_[5][0] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_cnt_reg_n_0_[4][0] ),
        .O(\wl_corse_cnt[0][0][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][1]_i_2 
       (.I0(\corse_cnt_reg_n_0_[3][1] ),
        .I1(\corse_cnt_reg_n_0_[2][1] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_cnt_reg_n_0_[1][1] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_cnt_reg_n_0_[0][1] ),
        .O(\wl_corse_cnt[0][0][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][1]_i_3 
       (.I0(\corse_cnt_reg_n_0_[7][1] ),
        .I1(\corse_cnt_reg_n_0_[6][1] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_cnt_reg_n_0_[5][1] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_cnt_reg_n_0_[4][1] ),
        .O(\wl_corse_cnt[0][0][1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \wl_corse_cnt[0][0][2]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\smallest_reg[7][0]_0 ),
        .O(\wl_corse_cnt[0][0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][2]_i_3 
       (.I0(\corse_cnt_reg_n_0_[3][2] ),
        .I1(\corse_cnt_reg_n_0_[2][2] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_cnt_reg_n_0_[1][2] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_cnt_reg_n_0_[0][2] ),
        .O(\wl_corse_cnt[0][0][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][2]_i_4 
       (.I0(\corse_cnt_reg_n_0_[7][2] ),
        .I1(\corse_cnt_reg_n_0_[6][2] ),
        .I2(\wl_corse_cnt_reg[0][7][2]_0 ),
        .I3(\corse_cnt_reg_n_0_[5][2] ),
        .I4(\wl_corse_cnt_reg[0][7][2]_1 ),
        .I5(\corse_cnt_reg_n_0_[4][2] ),
        .O(\wl_corse_cnt[0][0][2]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \wl_corse_cnt[0][2][2]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ),
        .I1(dqs_count_r[0]),
        .I2(dqs_count_r[1]),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\smallest_reg[7][0]_0 ),
        .O(\wl_corse_cnt[0][2][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \wl_corse_cnt[0][3][2]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\smallest_reg[7][0]_0 ),
        .O(\wl_corse_cnt[0][3][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \wl_corse_cnt[0][4][2]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\wl_corse_cnt[0][4][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00200000)) 
    \wl_corse_cnt[0][5][2]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\wl_corse_cnt[0][5][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00200000)) 
    \wl_corse_cnt[0][6][2]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\smallest_reg[7][0]_0 ),
        .I3(dqs_count_r[0]),
        .I4(dqs_count_r[1]),
        .O(\wl_corse_cnt[0][6][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0028020200000000)) 
    \wl_corse_cnt[0][7][2]_i_1 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .I5(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .O(\wl_corse_cnt[0][7][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wl_corse_cnt[0][7][2]_i_2 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\fine_inc_reg[6][0]_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .O(\wl_corse_cnt[0][7][2]_i_2_n_0 ));
  FDRE \wl_corse_cnt_reg[0][0][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]__0 [0]),
        .R(SR));
  MUXF7 \wl_corse_cnt_reg[0][0][0]_i_1 
       (.I0(\wl_corse_cnt[0][0][0]_i_2_n_0 ),
        .I1(\wl_corse_cnt[0][0][0]_i_3_n_0 ),
        .O(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \wl_corse_cnt_reg[0][0][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]__0 [1]),
        .R(SR));
  MUXF7 \wl_corse_cnt_reg[0][0][1]_i_1 
       (.I0(\wl_corse_cnt[0][0][1]_i_2_n_0 ),
        .I1(\wl_corse_cnt[0][0][1]_i_3_n_0 ),
        .O(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \wl_corse_cnt_reg[0][0][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]__0 [2]),
        .R(SR));
  MUXF7 \wl_corse_cnt_reg[0][0][2]_i_2 
       (.I0(\wl_corse_cnt[0][0][2]_i_3_n_0 ),
        .I1(\wl_corse_cnt[0][0][2]_i_4_n_0 ),
        .O(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \wl_corse_cnt_reg[0][1][0] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]__0 [0]),
        .R(SR));
  FDRE \wl_corse_cnt_reg[0][1][1] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]__0 [1]),
        .R(SR));
  FDRE \wl_corse_cnt_reg[0][1][2] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]__0 [2]),
        .R(SR));
  FDRE \wl_corse_cnt_reg[0][2][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][2]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_corse_cnt_reg[0][2][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][2]__0 [1]),
        .R(SR));
  FDRE \wl_corse_cnt_reg[0][2][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][2]__0 [2]),
        .R(SR));
  FDRE \wl_corse_cnt_reg[0][3][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][3]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_corse_cnt_reg[0][3][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][3]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_corse_cnt_reg[0][3][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][3]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_corse_cnt_reg[0][4][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][4]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_corse_cnt_reg[0][4][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][4]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_corse_cnt_reg[0][4][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][4]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_corse_cnt_reg[0][5][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][5]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_corse_cnt_reg[0][5][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][5]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_corse_cnt_reg[0][5][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][5]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_corse_cnt_reg[0][6][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][6]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_corse_cnt_reg[0][6][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][6]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_corse_cnt_reg[0][6][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][6]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_corse_cnt_reg[0][7][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7]__0 [0]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_corse_cnt_reg[0][7][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7]__0 [1]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_corse_cnt_reg[0][7][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7]__0 [2]),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  LUT5 #(
    .INIT(32'h00040000)) 
    \wl_dqs_tap_count_r[0][1][5]_i_1 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(\smallest_reg[7][0]_0 ),
        .I4(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ),
        .O(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT5 #(
    .INIT(32'h02250000)) 
    \wl_dqs_tap_count_r[0][1][5]_i_2 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(\wl_dqs_tap_count_r[0][1][5]_i_2_n_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][0][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][3] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][4] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][5] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][0] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .R(SR));
  FDRE \wl_dqs_tap_count_r_reg[0][1][1] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .R(SR));
  FDRE \wl_dqs_tap_count_r_reg[0][1][2] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .R(SR));
  FDRE \wl_dqs_tap_count_r_reg[0][1][3] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .R(SR));
  FDRE \wl_dqs_tap_count_r_reg[0][1][4] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .R(SR));
  FDRE \wl_dqs_tap_count_r_reg[0][1][5] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .R(SR));
  FDRE \wl_dqs_tap_count_r_reg[0][2][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][3] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][4] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][5] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][2][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][3] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][4] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][5] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][3][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][1] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][2] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][3] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][3] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][4] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][4] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][5] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][4][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][5] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][5][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][0] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][5][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][1] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][5][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][2] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][5][3] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][3] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][5][4] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][4] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][5][5] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][5][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][5] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][1] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][2] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][3] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][3] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][4] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][4] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][5] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][6][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][5] ),
        .R(rstdiv0_sync_r1_reg_rep__7[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][7][0] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][0] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][7][1] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][1] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][7][2] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][2] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][7][3] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][3] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][7][4] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][4] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_dqs_tap_count_r_reg[0][7][5] 
       (.C(CLK),
        .CE(\wl_corse_cnt[0][7][2]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][5] ),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  LUT6 #(
    .INIT(64'hCCCCCCCC84580CCC)) 
    wl_edge_detect_valid_r_i_1
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(wl_edge_detect_valid_r_reg_n_0),
        .I2(Q[1]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(wl_edge_detect_valid_r_i_1_n_0));
  FDRE wl_edge_detect_valid_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wl_edge_detect_valid_r_i_1_n_0),
        .Q(wl_edge_detect_valid_r_reg_n_0),
        .R(rstdiv0_sync_r1_reg_rep__10[1]));
  FDRE \wl_state_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(Q[0]),
        .Q(\wl_state_r1_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \wl_state_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_state_r_reg_n_0_[1] ),
        .Q(\wl_state_r1_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \wl_state_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_state_r_reg_n_0_[2] ),
        .Q(\wl_state_r1_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \wl_state_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(Q[1]),
        .Q(\wl_state_r1_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  FDRE \wl_state_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(Q[2]),
        .Q(\wl_state_r1_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  LUT6 #(
    .INIT(64'hAFA0BFBFAFA0B0B0)) 
    \wl_state_r[0]_i_1 
       (.I0(\wl_state_r[0]_i_2_n_0 ),
        .I1(\wl_state_r[0]_i_3_n_0 ),
        .I2(\wl_state_r[4]_i_6_n_0 ),
        .I3(\wl_state_r[0]_i_4_n_0 ),
        .I4(\wl_state_r[0]_i_5_n_0 ),
        .I5(\wl_state_r[0]_i_6_n_0 ),
        .O(\wl_state_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0F00FF770F000077)) 
    \wl_state_r[0]_i_10 
       (.I0(flag_ck_negedge_i_5_n_0),
        .I1(flag_ck_negedge_reg_i_4_n_0),
        .I2(wr_level_done_r5),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(Q[0]),
        .I5(\fine_dec_cnt[5]_i_7_n_0 ),
        .O(\wl_state_r[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00004000CCCCCCCC)) 
    \wl_state_r[0]_i_2 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r[0]_i_5_n_0 ),
        .I2(\wl_state_r[2]_i_9_n_0 ),
        .I3(\wl_state_r[4]_i_16_n_0 ),
        .I4(wrlvl_byte_redo_reg_1),
        .I5(Q[0]),
        .O(\wl_state_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT4 #(
    .INIT(16'h5FC0)) 
    \wl_state_r[0]_i_3 
       (.I0(\wl_state_r[2]_i_9_n_0 ),
        .I1(\wl_state_r[1]_i_8_n_0 ),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \wl_state_r[0]_i_4 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[0]),
        .I2(\wl_state_r[4]_i_16_n_0 ),
        .O(\wl_state_r[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \wl_state_r[0]_i_5 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .O(\wl_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04FF04FF)) 
    \wl_state_r[0]_i_6 
       (.I0(\wl_state_r[0]_i_7_n_0 ),
        .I1(Q[1]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(\wl_state_r[0]_i_8_n_0 ),
        .I4(\wl_state_r[0]_i_9_n_0 ),
        .I5(\wl_state_r[1]_i_9_n_0 ),
        .O(\wl_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDD00C0CCCC)) 
    \wl_state_r[0]_i_7 
       (.I0(dq_cnt_inc_reg_n_0),
        .I1(Q[0]),
        .I2(\wl_state_r[3]_i_9_n_0 ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I4(wl_edge_detect_valid_r_reg_n_0),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF00F1F1)) 
    \wl_state_r[0]_i_8 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r[4]_i_9_n_0 ),
        .I2(Q[0]),
        .I3(\wl_state_r[0]_i_10_n_0 ),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(Q[1]),
        .O(\wl_state_r[0]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT5 #(
    .INIT(32'hEFFFFFFF)) 
    \wl_state_r[0]_i_9 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(dual_rnk_dec),
        .I3(Q[1]),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .O(\wl_state_r[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h2F2F2F2F2F2F202F)) 
    \wl_state_r[1]_i_1 
       (.I0(\wl_state_r[1]_i_2_n_0 ),
        .I1(\wl_state_r[1]_i_3_n_0 ),
        .I2(\wl_state_r[4]_i_6_n_0 ),
        .I3(\wl_state_r[1]_i_4_n_0 ),
        .I4(\wl_state_r[1]_i_5_n_0 ),
        .I5(\wl_state_r[1]_i_6_n_0 ),
        .O(\wl_state_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF00000002FFFF)) 
    \wl_state_r[1]_i_10 
       (.I0(wrlvl_byte_redo),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\wl_tap_count_r_reg_n_0_[1] ),
        .I3(\wl_state_r[1]_i_13_n_0 ),
        .I4(Q[0]),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[1]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT5 #(
    .INIT(32'h020FFFFF)) 
    \wl_state_r[1]_i_11 
       (.I0(\wl_state_r[2]_i_14_n_0 ),
        .I1(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(wl_edge_detect_valid_r_reg_n_0),
        .I4(Q[0]),
        .O(\wl_state_r[1]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wl_state_r[1]_i_12 
       (.I0(\fine_dec_cnt_reg_n_0_[1] ),
        .I1(\fine_dec_cnt_reg_n_0_[0] ),
        .O(\wl_state_r[1]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \wl_state_r[1]_i_13 
       (.I0(\wl_tap_count_r_reg_n_0_[3] ),
        .I1(\wl_tap_count_r_reg_n_0_[2] ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\wl_tap_count_r_reg_n_0_[5] ),
        .O(\wl_state_r[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h7F7F7F7F7F777777)) 
    \wl_state_r[1]_i_2 
       (.I0(\wl_state_r[0]_i_5_n_0 ),
        .I1(Q[0]),
        .I2(\wl_state_r[1]_i_7_n_0 ),
        .I3(\wl_state_r[2]_i_9_n_0 ),
        .I4(\wl_state_r[4]_i_16_n_0 ),
        .I5(wrlvl_byte_redo_reg_1),
        .O(\wl_state_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT5 #(
    .INIT(32'h00005F3F)) 
    \wl_state_r[1]_i_3 
       (.I0(\wl_state_r[2]_i_9_n_0 ),
        .I1(\wl_state_r[1]_i_8_n_0 ),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\wl_state_r[0]_i_5_n_0 ),
        .O(\wl_state_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hEEFFFFFAEEAAFFFA)) 
    \wl_state_r[1]_i_4 
       (.I0(Q[2]),
        .I1(\wl_state_r[1]_i_9_n_0 ),
        .I2(\wl_state_r[1]_i_10_n_0 ),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(Q[1]),
        .I5(\wl_state_r[1]_i_11_n_0 ),
        .O(\wl_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4000400400000004)) 
    \wl_state_r[1]_i_5 
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[0]),
        .I4(flag_ck_negedge_i_5_n_0),
        .I5(wr_level_done_r5),
        .O(\wl_state_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00008A8A8A8A8A00)) 
    \wl_state_r[1]_i_6 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(\wl_state_r[4]_i_16_n_0 ),
        .I4(Q[0]),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[1]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFEAAAA)) 
    \wl_state_r[1]_i_7 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I4(wrlvl_byte_redo),
        .O(\wl_state_r[1]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wl_state_r[1]_i_8 
       (.I0(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I1(\corse_dec[0][0]_i_2_n_0 ),
        .O(\wl_state_r[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \wl_state_r[1]_i_9 
       (.I0(\wl_state_r[1]_i_12_n_0 ),
        .I1(\wl_state_r[4]_i_22_n_0 ),
        .I2(\fine_dec_cnt_reg_n_0_[3] ),
        .I3(\fine_dec_cnt_reg_n_0_[2] ),
        .I4(\fine_dec_cnt_reg_n_0_[5] ),
        .I5(\fine_dec_cnt_reg_n_0_[4] ),
        .O(\wl_state_r[1]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT5 #(
    .INIT(32'h00000800)) 
    \wl_state_r[2]_i_11 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[0]),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\fine_inc[0][5]_i_9_n_0 ),
        .I4(\fine_inc[0][5]_i_12_n_0 ),
        .O(\wl_state_r[2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0100FFFFFFFF0000)) 
    \wl_state_r[2]_i_12 
       (.I0(dual_rnk_dec),
        .I1(\fine_dec_cnt_reg_n_0_[1] ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .I3(\wl_state_r[2]_i_15_n_0 ),
        .I4(Q[0]),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \wl_state_r[2]_i_14 
       (.I0(\wl_tap_count_r_reg_n_0_[5] ),
        .I1(\wl_tap_count_r_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[3] ),
        .I3(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .I4(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I5(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .O(\wl_state_r[2]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \wl_state_r[2]_i_15 
       (.I0(\fine_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_dec_cnt_reg_n_0_[2] ),
        .I2(\fine_dec_cnt_reg_n_0_[5] ),
        .I3(\fine_dec_cnt_reg_n_0_[4] ),
        .O(\wl_state_r[2]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFBFBFBFBFBFBAAFA)) 
    \wl_state_r[2]_i_2 
       (.I0(\wl_state_r[1]_i_6_n_0 ),
        .I1(Q[2]),
        .I2(\wl_state_r[2]_i_4_n_0 ),
        .I3(\wl_state_r[2]_i_5_n_0 ),
        .I4(\wl_state_r[2]_i_6_n_0 ),
        .I5(\wl_state_r[2]_i_7_n_0 ),
        .O(\wl_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h008000800000FFFF)) 
    \wl_state_r[2]_i_3 
       (.I0(\wl_state_r[2]_i_8_n_0 ),
        .I1(\wl_state_r[2]_i_9_n_0 ),
        .I2(\wl_state_r[4]_i_16_n_0 ),
        .I3(wrlvl_byte_redo_reg_1),
        .I4(\wl_state_r[2]_i_11_n_0 ),
        .I5(\wl_state_r[0]_i_5_n_0 ),
        .O(\wl_state_r[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \wl_state_r[2]_i_4 
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(Q[1]),
        .O(\wl_state_r[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h33FFAA0F33FFAAFF)) 
    \wl_state_r[2]_i_5 
       (.I0(\fine_dec_cnt[5]_i_7_n_0 ),
        .I1(wr_level_done_r5),
        .I2(flag_ck_negedge_i_5_n_0),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(Q[0]),
        .I5(flag_ck_negedge_reg_i_4_n_0),
        .O(\wl_state_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h555500000000FF0C)) 
    \wl_state_r[2]_i_6 
       (.I0(\wl_state_r[2]_i_12_n_0 ),
        .I1(wrlvl_byte_redo_reg),
        .I2(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I3(\wl_state_r[4]_i_22_n_0 ),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(Q[1]),
        .O(\wl_state_r[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    \wl_state_r[2]_i_7 
       (.I0(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I1(Q[0]),
        .I2(wl_edge_detect_valid_r_reg_n_0),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\wl_state_r[3]_i_4_n_0 ),
        .I5(\wl_state_r[2]_i_14_n_0 ),
        .O(\wl_state_r[2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wl_state_r[2]_i_8 
       (.I0(Q[0]),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[2]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'hFEFF)) 
    \wl_state_r[2]_i_9 
       (.I0(\fine_inc[0][5]_i_12_n_0 ),
        .I1(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I2(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I3(\fine_inc[0][2]_i_2_n_0 ),
        .O(\wl_state_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h3FFA000030FA0000)) 
    \wl_state_r[3]_i_10 
       (.I0(inhibit_edge_detect_r_i_6_n_0),
        .I1(wr_level_done_r5),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\wl_state_r[2]_i_4_n_0 ),
        .I5(\fine_dec_cnt[5]_i_7_n_0 ),
        .O(\wl_state_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBAAAAAAA)) 
    \wl_state_r[3]_i_11 
       (.I0(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\fine_inc_reg[6][0]_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .I5(\fine_inc_reg[0][5]_i_11_n_0 ),
        .O(\wl_state_r[3]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'hF2FF)) 
    \wl_state_r[3]_i_12 
       (.I0(wl_sm_start),
        .I1(wr_level_done_r5),
        .I2(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I3(\corse_inc[0][2]_i_7_n_0 ),
        .O(\wl_state_r[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h7575757565202020)) 
    \wl_state_r[3]_i_2 
       (.I0(\wl_state_r[0]_i_5_n_0 ),
        .I1(Q[0]),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(\wl_state_r[3]_i_4_n_0 ),
        .I4(\wl_state_r[3]_i_5_n_0 ),
        .I5(\wl_state_r[3]_i_6_n_0 ),
        .O(\wl_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC3F3C3C355555555)) 
    \wl_state_r[3]_i_3 
       (.I0(\wl_state_r[3]_i_7_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[0]),
        .I3(\wl_state_r[3]_i_8_n_0 ),
        .I4(\fine_inc[0][5]_i_4_n_0 ),
        .I5(\wl_state_r[0]_i_5_n_0 ),
        .O(\wl_state_r[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wl_state_r[3]_i_4 
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .O(\wl_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF7F00FFFF)) 
    \wl_state_r[3]_i_5 
       (.I0(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I1(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .I3(\wl_state_r[3]_i_9_n_0 ),
        .I4(\rd_data_previous_r[7]_i_3_n_0 ),
        .I5(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\wl_state_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7555)) 
    \wl_state_r[3]_i_6 
       (.I0(\wl_state_r[0]_i_9_n_0 ),
        .I1(\wl_state_r[1]_i_9_n_0 ),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(\fine_dec_cnt[5]_i_3_n_0 ),
        .I5(\wl_state_r[3]_i_10_n_0 ),
        .O(\wl_state_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFAFFFAFCFAFFFAF)) 
    \wl_state_r[3]_i_7 
       (.I0(\wl_state_r[1]_i_8_n_0 ),
        .I1(\wl_state_r[3]_i_11_n_0 ),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\fine_inc[0][2]_i_2_n_0 ),
        .I5(\fine_inc[0][5]_i_12_n_0 ),
        .O(\wl_state_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4000)) 
    \wl_state_r[3]_i_8 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\fine_inc_reg[6][0]_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(wrlvl_byte_redo),
        .I5(\wl_state_r[3]_i_12_n_0 ),
        .O(\wl_state_r[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \wl_state_r[3]_i_9 
       (.I0(\wl_tap_count_r_reg_n_0_[5] ),
        .I1(\wl_tap_count_r_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\wl_state_r[3]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT5 #(
    .INIT(32'hFFCFCDCD)) 
    \wl_state_r[4]_i_10 
       (.I0(early2_data),
        .I1(\wrlvl_redo_corse_inc_reg[1]_i_5_n_0 ),
        .I2(early1_data),
        .I3(\wrlvl_redo_corse_inc_reg[1]_i_4_n_0 ),
        .I4(\wrlvl_redo_corse_inc_reg[1]_i_3_n_0 ),
        .O(\wl_state_r[4]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'hCC4EC991)) 
    \wl_state_r[4]_i_11 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[4]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT5 #(
    .INIT(32'h9DD81106)) 
    \wl_state_r[4]_i_13 
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\wl_state_r[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h7777777777747777)) 
    \wl_state_r[4]_i_14 
       (.I0(wl_sm_start),
        .I1(\wl_state_r[4]_i_13_n_0 ),
        .I2(incdec_wait_cnt_reg__0[1]),
        .I3(incdec_wait_cnt_reg__0[0]),
        .I4(incdec_wait_cnt_reg__0[3]),
        .I5(incdec_wait_cnt_reg__0[2]),
        .O(\wl_state_r[4]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT4 #(
    .INIT(16'h0155)) 
    \wl_state_r[4]_i_15 
       (.I0(wr_level_done_r5),
        .I1(wrlvl_byte_redo),
        .I2(wl_sm_start),
        .I3(\wl_state_r[4]_i_13_n_0 ),
        .O(\wl_state_r[4]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \wl_state_r[4]_i_16 
       (.I0(\corse_inc[0][2]_i_7_n_0 ),
        .I1(\corse_inc_reg[0][2]_i_6_n_0 ),
        .O(\wl_state_r[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF08880000)) 
    \wl_state_r[4]_i_17 
       (.I0(\wl_state_r[4]_i_23_n_0 ),
        .I1(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I4(\wl_state_r[4]_i_24_n_0 ),
        .I5(\wl_state_r[4]_i_25_n_0 ),
        .O(\wl_state_r[4]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h2A2A2A2A2AAA2A2A)) 
    \wl_state_r[4]_i_18 
       (.I0(Q[0]),
        .I1(\wl_state_r[4]_i_26_n_0 ),
        .I2(\fine_dec_cnt[5]_i_7_n_0 ),
        .I3(\wl_state_r[4]_i_27_n_0 ),
        .I4(wrlvl_byte_redo),
        .I5(dual_rnk_dec),
        .O(\wl_state_r[4]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDFDDFFFF)) 
    \wl_state_r[4]_i_19 
       (.I0(\corse_inc[0][2]_i_7_n_0 ),
        .I1(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I2(wr_level_done_r5),
        .I3(wl_sm_start),
        .I4(Q[0]),
        .I5(wrlvl_byte_redo),
        .O(\wl_state_r[4]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'hFEFF)) 
    \wl_state_r[4]_i_20 
       (.I0(\corse_dec[0][0]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[0]),
        .O(\wl_state_r[4]_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT5 #(
    .INIT(32'h00000100)) 
    \wl_state_r[4]_i_21 
       (.I0(\fine_inc_reg[0][2]_i_3_n_0 ),
        .I1(\wl_corse_cnt[0][7][2]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][5]_i_11_n_0 ),
        .I3(\fine_inc[0][2]_i_2_n_0 ),
        .I4(\fine_inc[0][5]_i_12_n_0 ),
        .O(\wl_state_r[4]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wl_state_r[4]_i_22 
       (.I0(Q[0]),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_state_r[4]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT5 #(
    .INIT(32'h01000000)) 
    \wl_state_r[4]_i_23 
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(wrlvl_byte_redo),
        .O(\wl_state_r[4]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h11111FFF1FFFFFFF)) 
    \wl_state_r[4]_i_24 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I1(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I4(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wl_state_r[4]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAC0F0AAAA)) 
    \wl_state_r[4]_i_25 
       (.I0(Q[2]),
        .I1(wr_level_done_r5),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(\wl_state_r_reg_n_0_[2] ),
        .I5(Q[1]),
        .O(\wl_state_r[4]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \wl_state_r[4]_i_26 
       (.I0(dual_rnk_dec),
        .I1(\corse_dec_reg[0][0]_i_3_n_0 ),
        .I2(\corse_dec[0][0]_i_2_n_0 ),
        .O(\wl_state_r[4]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h1111177717777777)) 
    \wl_state_r[4]_i_27 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I1(\wl_corse_cnt_reg[0][0][2]_i_2_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I4(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wl_state_r[4]_i_27_n_0 ));
  LUT5 #(
    .INIT(32'h337A0124)) 
    \wl_state_r[4]_i_3 
       (.I0(Q[0]),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_state_r_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\wl_state_r[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000FFEAFFEAFF)) 
    \wl_state_r[4]_i_4 
       (.I0(\wl_state_r[4]_i_9_n_0 ),
        .I1(wr_level_done0),
        .I2(\wl_state_r[4]_i_10_n_0 ),
        .I3(\wl_state_r[4]_i_11_n_0 ),
        .I4(wrlvl_byte_redo_reg_0),
        .I5(\wl_state_r[4]_i_13_n_0 ),
        .O(\wl_state_r[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4747444747474747)) 
    \wl_state_r[4]_i_5 
       (.I0(\wl_state_r[4]_i_14_n_0 ),
        .I1(\wl_state_r[4]_i_11_n_0 ),
        .I2(\wl_state_r[4]_i_15_n_0 ),
        .I3(\fine_inc[0][5]_i_4_n_0 ),
        .I4(\wl_state_r[4]_i_13_n_0 ),
        .I5(\wl_state_r[4]_i_16_n_0 ),
        .O(\wl_state_r[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \wl_state_r[4]_i_6 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\wl_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h4544444444444444)) 
    \wl_state_r[4]_i_7 
       (.I0(\wl_state_r[1]_i_6_n_0 ),
        .I1(\wl_state_r[4]_i_17_n_0 ),
        .I2(\wl_state_r[4]_i_18_n_0 ),
        .I3(Q[1]),
        .I4(\wl_state_r_reg_n_0_[1] ),
        .I5(\wl_state_r_reg_n_0_[2] ),
        .O(\wl_state_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0F0000005F504F40)) 
    \wl_state_r[4]_i_8 
       (.I0(inhibit_edge_detect_r_i_4_n_0),
        .I1(\wl_state_r[4]_i_19_n_0 ),
        .I2(\wl_state_r[0]_i_5_n_0 ),
        .I3(\wl_state_r[4]_i_20_n_0 ),
        .I4(\wl_state_r[4]_i_21_n_0 ),
        .I5(\wl_state_r[4]_i_22_n_0 ),
        .O(\wl_state_r[4]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \wl_state_r[4]_i_9 
       (.I0(wr_level_start_r),
        .I1(wl_sm_start),
        .I2(wr_level_done_r_reg_n_0),
        .O(\wl_state_r[4]_i_9_n_0 ));
  FDRE \wl_state_r_reg[0] 
       (.C(CLK),
        .CE(\wl_state_r_reg[4]_i_1_n_0 ),
        .D(\wl_state_r[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_state_r_reg[1] 
       (.C(CLK),
        .CE(\wl_state_r_reg[4]_i_1_n_0 ),
        .D(\wl_state_r[1]_i_1_n_0 ),
        .Q(\wl_state_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_state_r_reg[2] 
       (.C(CLK),
        .CE(\wl_state_r_reg[4]_i_1_n_0 ),
        .D(\wl_state_r_reg[2]_i_1_n_0 ),
        .Q(\wl_state_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \wl_state_r_reg[2]_i_1 
       (.I0(\wl_state_r[2]_i_2_n_0 ),
        .I1(\wl_state_r[2]_i_3_n_0 ),
        .O(\wl_state_r_reg[2]_i_1_n_0 ),
        .S(\wl_state_r[4]_i_6_n_0 ));
  FDRE \wl_state_r_reg[3] 
       (.C(CLK),
        .CE(\wl_state_r_reg[4]_i_1_n_0 ),
        .D(\wl_state_r_reg[3]_i_1_n_0 ),
        .Q(Q[1]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \wl_state_r_reg[3]_i_1 
       (.I0(\wl_state_r[3]_i_2_n_0 ),
        .I1(\wl_state_r[3]_i_3_n_0 ),
        .O(\wl_state_r_reg[3]_i_1_n_0 ),
        .S(\wl_state_r[4]_i_6_n_0 ));
  FDRE \wl_state_r_reg[4] 
       (.C(CLK),
        .CE(\wl_state_r_reg[4]_i_1_n_0 ),
        .D(\wl_state_r_reg[4]_i_2_n_0 ),
        .Q(Q[2]),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \wl_state_r_reg[4]_i_1 
       (.I0(\wl_state_r[4]_i_4_n_0 ),
        .I1(\wl_state_r[4]_i_5_n_0 ),
        .O(\wl_state_r_reg[4]_i_1_n_0 ),
        .S(\wl_state_r[4]_i_3_n_0 ));
  MUXF7 \wl_state_r_reg[4]_i_2 
       (.I0(\wl_state_r[4]_i_7_n_0 ),
        .I1(\wl_state_r[4]_i_8_n_0 ),
        .O(\wl_state_r_reg[4]_i_2_n_0 ),
        .S(\wl_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h4445454544444444)) 
    \wl_tap_count_r[0]_i_1 
       (.I0(Q[1]),
        .I1(\wl_tap_count_r[0]_i_2_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[0] ),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(wr_level_done_r5),
        .I5(\wl_state_r_reg_n_0_[1] ),
        .O(\wl_tap_count_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000ABAAFFFF)) 
    \wl_tap_count_r[0]_i_2 
       (.I0(\wl_tap_count_r[0]_i_3_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[4]__0 [0]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [2]),
        .I5(\wl_tap_count_r[0]_i_4_n_0 ),
        .O(\wl_tap_count_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFAC00AC0)) 
    \wl_tap_count_r[0]_i_3 
       (.I0(\smallest_reg[6]__0 [0]),
        .I1(\smallest_reg[5]__0 [0]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I4(\smallest_reg[7]__0 [0]),
        .O(\wl_tap_count_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hEEEFEEEEEEEFEEEF)) 
    \wl_tap_count_r[0]_i_4 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_tap_count_r[0]_i_5_n_0 ),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [2]),
        .I4(\po_stg2_wrcal_cnt_reg[0]_1 ),
        .I5(\smallest_reg[0]__0 [0]),
        .O(\wl_tap_count_r[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \wl_tap_count_r[0]_i_5 
       (.I0(\smallest_reg[3]__0 [0]),
        .I1(\smallest_reg[2]__0 [0]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I4(\smallest_reg[1]__0 [0]),
        .O(\wl_tap_count_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000E2C0E2)) 
    \wl_tap_count_r[1]_i_1 
       (.I0(\wl_tap_count_r_reg[1]_i_2_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_tap_count_r[1]_i_3_n_0 ),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(wr_level_done_r5),
        .I5(Q[1]),
        .O(wl_tap_count_r[1]));
  LUT2 #(
    .INIT(4'h6)) 
    \wl_tap_count_r[1]_i_3 
       (.I0(\wl_tap_count_r_reg_n_0_[0] ),
        .I1(\wl_tap_count_r_reg_n_0_[1] ),
        .O(\wl_tap_count_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[1]_i_4 
       (.I0(\smallest_reg[3]__0 [1]),
        .I1(\smallest_reg[2]__0 [1]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[1]__0 [1]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\smallest_reg[0]__0 [1]),
        .O(\wl_tap_count_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[1]_i_5 
       (.I0(\smallest_reg[7]__0 [1]),
        .I1(\smallest_reg[6]__0 [1]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[5]__0 [1]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\smallest_reg[4]__0 [1]),
        .O(\wl_tap_count_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AEEAEAEA)) 
    \wl_tap_count_r[2]_i_1 
       (.I0(\wl_tap_count_r[2]_i_2_n_0 ),
        .I1(\wl_tap_count_r[4]_i_3_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[2] ),
        .I3(\wl_tap_count_r_reg_n_0_[0] ),
        .I4(\wl_tap_count_r_reg_n_0_[1] ),
        .I5(Q[1]),
        .O(wl_tap_count_r[2]));
  LUT6 #(
    .INIT(64'h00000000BAAAFFFF)) 
    \wl_tap_count_r[2]_i_2 
       (.I0(\wl_tap_count_r[2]_i_3_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I3(\smallest_reg[5]__0 [2]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [2]),
        .I5(\wl_tap_count_r[2]_i_4_n_0 ),
        .O(\wl_tap_count_r[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hA0CFA0C0)) 
    \wl_tap_count_r[2]_i_3 
       (.I0(\smallest_reg[7]__0 [2]),
        .I1(\smallest_reg[6]__0 [2]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I4(\smallest_reg[4]__0 [2]),
        .O(\wl_tap_count_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hEEEFEEEEEEEFEEEF)) 
    \wl_tap_count_r[2]_i_4 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_tap_count_r[2]_i_5_n_0 ),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [2]),
        .I4(\po_stg2_wrcal_cnt_reg[0]_2 ),
        .I5(\smallest_reg[2]__0 [2]),
        .O(\wl_tap_count_r[2]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hF0CA00CA)) 
    \wl_tap_count_r[2]_i_5 
       (.I0(\smallest_reg[0]__0 [2]),
        .I1(\smallest_reg[1]__0 [2]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I4(\smallest_reg[3]__0 [2]),
        .O(\wl_tap_count_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000E2C0E2)) 
    \wl_tap_count_r[3]_i_1 
       (.I0(\wl_tap_count_r_reg[3]_i_2_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_tap_count_r[3]_i_3_n_0 ),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(wr_level_done_r5),
        .I5(Q[1]),
        .O(wl_tap_count_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \wl_tap_count_r[3]_i_3 
       (.I0(\wl_tap_count_r_reg_n_0_[3] ),
        .I1(\wl_tap_count_r_reg_n_0_[2] ),
        .I2(\wl_tap_count_r_reg_n_0_[0] ),
        .I3(\wl_tap_count_r_reg_n_0_[1] ),
        .O(\wl_tap_count_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[3]_i_4 
       (.I0(\smallest_reg[3]__0 [3]),
        .I1(\smallest_reg[2]__0 [3]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[1]__0 [3]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\smallest_reg[0]__0 [3]),
        .O(\wl_tap_count_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[3]_i_5 
       (.I0(\smallest_reg[7]__0 [3]),
        .I1(\smallest_reg[6]__0 [3]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[5]__0 [3]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\smallest_reg[4]__0 [3]),
        .O(\wl_tap_count_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h4454544454544444)) 
    \wl_tap_count_r[4]_i_1 
       (.I0(Q[1]),
        .I1(\wl_tap_count_r[4]_i_2_n_0 ),
        .I2(\wl_tap_count_r[4]_i_3_n_0 ),
        .I3(\wl_tap_count_r[4]_i_4_n_0 ),
        .I4(\wl_tap_count_r_reg_n_0_[4] ),
        .I5(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\wl_tap_count_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EAAAFFFF)) 
    \wl_tap_count_r[4]_i_2 
       (.I0(\wl_tap_count_r[4]_i_5_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[7]__0 [4]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [2]),
        .I5(\wl_tap_count_r[4]_i_6_n_0 ),
        .O(\wl_tap_count_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    \wl_tap_count_r[4]_i_3 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(wr_level_done_r5),
        .I2(\wl_state_r_reg_n_0_[2] ),
        .O(\wl_tap_count_r[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \wl_tap_count_r[4]_i_4 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\wl_tap_count_r_reg_n_0_[2] ),
        .O(\wl_tap_count_r[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h0ACF0AC0)) 
    \wl_tap_count_r[4]_i_5 
       (.I0(\smallest_reg[5]__0 [4]),
        .I1(\smallest_reg[6]__0 [4]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I4(\smallest_reg[4]__0 [4]),
        .O(\wl_tap_count_r[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hEEEFEEEEEEEFEEEF)) 
    \wl_tap_count_r[4]_i_6 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_state_r_reg_n_0_[2] ),
        .I2(\wl_tap_count_r[4]_i_7_n_0 ),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [2]),
        .I4(\po_stg2_wrcal_cnt_reg[1] ),
        .I5(\smallest_reg[1]__0 [4]),
        .O(\wl_tap_count_r[4]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hAC0FAC00)) 
    \wl_tap_count_r[4]_i_7 
       (.I0(\smallest_reg[3]__0 [4]),
        .I1(\smallest_reg[2]__0 [4]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I3(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I4(\smallest_reg[0]__0 [4]),
        .O(\wl_tap_count_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00000E0E0000F00E)) 
    \wl_tap_count_r[5]_i_1 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(\wl_tap_count_r[5]_i_3_n_0 ),
        .I2(Q[0]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\wl_tap_count_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000E2C0E2)) 
    \wl_tap_count_r[5]_i_2 
       (.I0(\wl_tap_count_r_reg[5]_i_4_n_0 ),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(\wl_tap_count_r[5]_i_5_n_0 ),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .I4(wr_level_done_r5),
        .I5(Q[1]),
        .O(wl_tap_count_r[5]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \wl_tap_count_r[5]_i_3 
       (.I0(wrlvl_byte_redo_r),
        .I1(wrlvl_byte_redo),
        .I2(Q[1]),
        .O(\wl_tap_count_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \wl_tap_count_r[5]_i_5 
       (.I0(\wl_tap_count_r_reg_n_0_[5] ),
        .I1(\wl_tap_count_r_reg_n_0_[3] ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\wl_tap_count_r_reg_n_0_[1] ),
        .I4(\wl_tap_count_r_reg_n_0_[0] ),
        .I5(\wl_tap_count_r_reg_n_0_[2] ),
        .O(\wl_tap_count_r[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[5]_i_6 
       (.I0(\smallest_reg[3]__0 [5]),
        .I1(\smallest_reg[2]__0 [5]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[1]__0 [5]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\smallest_reg[0]__0 [5]),
        .O(\wl_tap_count_r[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[5]_i_7 
       (.I0(\smallest_reg[7]__0 [5]),
        .I1(\smallest_reg[6]__0 [5]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\smallest_reg[5]__0 [5]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\smallest_reg[4]__0 [5]),
        .O(\wl_tap_count_r[5]_i_7_n_0 ));
  FDRE \wl_tap_count_r_reg[0] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(\wl_tap_count_r[0]_i_1_n_0 ),
        .Q(\wl_tap_count_r_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_tap_count_r_reg[1] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[1]),
        .Q(\wl_tap_count_r_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \wl_tap_count_r_reg[1]_i_2 
       (.I0(\wl_tap_count_r[1]_i_4_n_0 ),
        .I1(\wl_tap_count_r[1]_i_5_n_0 ),
        .O(\wl_tap_count_r_reg[1]_i_2_n_0 ),
        .S(\po_stg2_wrcal_cnt_reg[3]_0 [2]));
  FDRE \wl_tap_count_r_reg[2] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[2]),
        .Q(\wl_tap_count_r_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_tap_count_r_reg[3] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[3]),
        .Q(\wl_tap_count_r_reg_n_0_[3] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \wl_tap_count_r_reg[3]_i_2 
       (.I0(\wl_tap_count_r[3]_i_4_n_0 ),
        .I1(\wl_tap_count_r[3]_i_5_n_0 ),
        .O(\wl_tap_count_r_reg[3]_i_2_n_0 ),
        .S(\po_stg2_wrcal_cnt_reg[3]_0 [2]));
  FDRE \wl_tap_count_r_reg[4] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(\wl_tap_count_r[4]_i_1_n_0 ),
        .Q(\wl_tap_count_r_reg_n_0_[4] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  FDRE \wl_tap_count_r_reg[5] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[5]),
        .Q(\wl_tap_count_r_reg_n_0_[5] ),
        .R(rstdiv0_sync_r1_reg_rep__9));
  MUXF7 \wl_tap_count_r_reg[5]_i_4 
       (.I0(\wl_tap_count_r[5]_i_6_n_0 ),
        .I1(\wl_tap_count_r[5]_i_7_n_0 ),
        .O(\wl_tap_count_r_reg[5]_i_4_n_0 ),
        .S(\po_stg2_wrcal_cnt_reg[3]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    wr_level_done_i_1
       (.I0(done_dqs_tap_inc),
        .I1(wrlvl_byte_redo_r),
        .I2(wrlvl_byte_redo),
        .O(wr_level_done_i_1_n_0));
  FDRE wr_level_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r_reg_n_0),
        .Q(wr_level_done_r1),
        .R(1'b0));
  FDRE wr_level_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r1),
        .Q(wr_level_done_r2),
        .R(1'b0));
  FDRE wr_level_done_r3_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r2),
        .Q(wr_level_done_r3),
        .R(1'b0));
  FDRE wr_level_done_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r3),
        .Q(wr_level_done_r4),
        .R(1'b0));
  FDRE wr_level_done_r5_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r4),
        .Q(wr_level_done_r5),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFF3FD0C00000)) 
    wr_level_done_r_i_1
       (.I0(dq_cnt_inc_reg_n_0),
        .I1(\wl_tap_count_r[5]_i_3_n_0 ),
        .I2(wr_level_done_r_i_2_n_0),
        .I3(\wl_state_r_reg_n_0_[1] ),
        .I4(Q[1]),
        .I5(wr_level_done_r_reg_n_0),
        .O(wr_level_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT3 #(
    .INIT(8'h01)) 
    wr_level_done_r_i_2
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(Q[0]),
        .I2(Q[2]),
        .O(wr_level_done_r_i_2_n_0));
  FDRE wr_level_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r_i_1_n_0),
        .Q(wr_level_done_r_reg_n_0),
        .R(SR));
  FDRE wr_level_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_i_1_n_0),
        .Q(wrlvl_done_r_reg),
        .R(1'b0));
  FDRE wr_level_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_lvl_start_reg),
        .Q(wr_level_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000BAAA00AA)) 
    wrlvl_byte_done_i_1
       (.I0(wrlvl_byte_done),
        .I1(wr_level_done_r4),
        .I2(wr_level_done_r3),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(rstdiv0_sync_r1_reg_rep__23),
        .O(wrlvl_byte_done_i_1_n_0));
  FDRE wrlvl_byte_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_done_i_1_n_0),
        .Q(wrlvl_byte_done),
        .R(1'b0));
  FDRE wrlvl_byte_redo_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_redo),
        .Q(wrlvl_byte_redo_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFEFE00000008)) 
    wrlvl_rank_done_r_i_1
       (.I0(Q[1]),
        .I1(\wl_state_r_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(wrlvl_rank_done_r_i_2_n_0),
        .I5(wrlvl_rank_done),
        .O(wrlvl_rank_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    wrlvl_rank_done_r_i_2
       (.I0(\wl_state_r_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(dq_cnt_inc_reg_n_0),
        .O(wrlvl_rank_done_r_i_2_n_0));
  FDRE wrlvl_rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_rank_done_r_i_1_n_0),
        .Q(wrlvl_rank_done),
        .R(rstdiv0_sync_r1_reg_rep__10[0]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'h4FE0)) 
    \wrlvl_redo_corse_inc[0]_i_1 
       (.I0(Q[2]),
        .I1(\wrlvl_redo_corse_inc[1]_i_2_n_0 ),
        .I2(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .O(\wrlvl_redo_corse_inc[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT5 #(
    .INIT(32'hA3FF5300)) 
    \wrlvl_redo_corse_inc[1]_i_1 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I1(\wrlvl_redo_corse_inc[1]_i_2_n_0 ),
        .I2(Q[2]),
        .I3(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I4(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wrlvl_redo_corse_inc[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[1]_i_10 
       (.I0(\final_coarse_tap_reg[3]__0 [2]),
        .I1(\final_coarse_tap_reg[2]__0 [2]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\final_coarse_tap_reg[1]__0 [2]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\final_coarse_tap_reg[0]__0 [2]),
        .O(\wrlvl_redo_corse_inc[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[1]_i_11 
       (.I0(\final_coarse_tap_reg[7]__0 [2]),
        .I1(\final_coarse_tap_reg[6]__0 [2]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\final_coarse_tap_reg[5]__0 [2]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\final_coarse_tap_reg[4]__0 [2]),
        .O(\wrlvl_redo_corse_inc[1]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT4 #(
    .INIT(16'h0070)) 
    \wrlvl_redo_corse_inc[1]_i_2 
       (.I0(\wrlvl_redo_corse_inc_reg[1]_i_3_n_0 ),
        .I1(\wrlvl_redo_corse_inc_reg[1]_i_4_n_0 ),
        .I2(early1_data),
        .I3(\wrlvl_redo_corse_inc_reg[1]_i_5_n_0 ),
        .O(\wrlvl_redo_corse_inc[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[1]_i_6 
       (.I0(\final_coarse_tap_reg[3]__0 [1]),
        .I1(\final_coarse_tap_reg[2]__0 [1]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\final_coarse_tap_reg[1]__0 [1]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\final_coarse_tap_reg[0]__0 [1]),
        .O(\wrlvl_redo_corse_inc[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[1]_i_7 
       (.I0(\final_coarse_tap_reg[7]__0 [1]),
        .I1(\final_coarse_tap_reg[6]__0 [1]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\final_coarse_tap_reg[5]__0 [1]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\final_coarse_tap_reg[4]__0 [1]),
        .O(\wrlvl_redo_corse_inc[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[1]_i_8 
       (.I0(\final_coarse_tap_reg[3]__0 [0]),
        .I1(\final_coarse_tap_reg[2]__0 [0]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\final_coarse_tap_reg[1]__0 [0]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\final_coarse_tap_reg[0]__0 [0]),
        .O(\wrlvl_redo_corse_inc[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[1]_i_9 
       (.I0(\final_coarse_tap_reg[7]__0 [0]),
        .I1(\final_coarse_tap_reg[6]__0 [0]),
        .I2(\po_stg2_wrcal_cnt_reg[3]_0 [1]),
        .I3(\final_coarse_tap_reg[5]__0 [0]),
        .I4(\po_stg2_wrcal_cnt_reg[3]_0 [0]),
        .I5(\final_coarse_tap_reg[4]__0 [0]),
        .O(\wrlvl_redo_corse_inc[1]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hEFFF1F00)) 
    \wrlvl_redo_corse_inc[2]_i_1 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I4(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .O(\wrlvl_redo_corse_inc[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAA002000000020)) 
    \wrlvl_redo_corse_inc[2]_i_2 
       (.I0(\wrlvl_redo_corse_inc[2]_i_3_n_0 ),
        .I1(\wl_state_r[4]_i_10_n_0 ),
        .I2(wrlvl_byte_redo),
        .I3(wrlvl_byte_redo_r),
        .I4(Q[2]),
        .I5(\wrlvl_redo_corse_inc[2]_i_4_n_0 ),
        .O(\wrlvl_redo_corse_inc[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \wrlvl_redo_corse_inc[2]_i_3 
       (.I0(\wl_state_r_reg_n_0_[1] ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\wl_state_r_reg_n_0_[2] ),
        .O(\wrlvl_redo_corse_inc[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \wrlvl_redo_corse_inc[2]_i_4 
       (.I0(wrlvl_byte_redo),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wrlvl_redo_corse_inc[2]_i_4_n_0 ));
  FDRE \wrlvl_redo_corse_inc_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[0]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  FDRE \wrlvl_redo_corse_inc_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[1]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
  MUXF7 \wrlvl_redo_corse_inc_reg[1]_i_3 
       (.I0(\wrlvl_redo_corse_inc[1]_i_6_n_0 ),
        .I1(\wrlvl_redo_corse_inc[1]_i_7_n_0 ),
        .O(\wrlvl_redo_corse_inc_reg[1]_i_3_n_0 ),
        .S(\po_stg2_wrcal_cnt_reg[3]_0 [2]));
  MUXF7 \wrlvl_redo_corse_inc_reg[1]_i_4 
       (.I0(\wrlvl_redo_corse_inc[1]_i_8_n_0 ),
        .I1(\wrlvl_redo_corse_inc[1]_i_9_n_0 ),
        .O(\wrlvl_redo_corse_inc_reg[1]_i_4_n_0 ),
        .S(\po_stg2_wrcal_cnt_reg[3]_0 [2]));
  MUXF7 \wrlvl_redo_corse_inc_reg[1]_i_5 
       (.I0(\wrlvl_redo_corse_inc[1]_i_10_n_0 ),
        .I1(\wrlvl_redo_corse_inc[1]_i_11_n_0 ),
        .O(\wrlvl_redo_corse_inc_reg[1]_i_5_n_0 ),
        .S(\po_stg2_wrcal_cnt_reg[3]_0 [2]));
  FDRE \wrlvl_redo_corse_inc_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[2]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .R(rstdiv0_sync_r1_reg_rep__7[0]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_infrastructure" *) 
module mig_7series_0_mig_7series_v2_3_infrastructure
   (freq_refclk,
    mem_refclk,
    sync_pulse,
    CLK,
    rst_sync_r1_reg_0,
    ui_clk_sync_rst,
    rstdiv0_sync_r1,
    \read_fifo.head_r_reg[0] ,
    \periodic_read_request.periodic_rd_r_cnt_reg ,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg ,
    SR,
    cal2_if_reset_reg,
    \complex_address_reg[0] ,
    \fine_inc_reg[7][4] ,
    \corse_inc_reg[7][1] ,
    \corse_cnt_reg[0][1] ,
    \smallest_reg[7][2] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ,
    \stable_pass_cnt_reg[0] ,
    \neutral_min_limit_reg[0] ,
    \device_temp_init_reg[0] ,
    \three_inc_min_limit_reg[11] ,
    \one_dec_max_limit_reg[11] ,
    \maintenance_request.maint_zq_r_lcl_reg ,
    \maintenance_request.maint_sre_r_lcl_reg ,
    \maint_controller.maint_wip_r_lcl_reg ,
    \last_master_r_reg[0] ,
    \complex_num_writes_dec_reg[0] ,
    \wait_cnt_reg[0] ,
    reset_reg,
    rst_sync_r1_reg_1,
    ADDRA,
    D,
    pll_lock,
    act_wait_r_lcl_reg,
    act_wait_r_lcl_reg_0,
    act_wait_r_lcl_reg_1,
    act_wait_r_lcl_reg_2,
    complex_row0_rd_done1,
    SS,
    \tap_cnt_cpt_r_reg[5] ,
    \samp_edge_cnt0_r_reg[0] ,
    \wait_cnt_r_reg[0] ,
    \cnt_shift_r_reg[0] ,
    mmcm_clk,
    AS,
    \rst_ref_sync_r_reg[0][14] ,
    \read_fifo.tail_r_reg[2] ,
    \idelay_tap_cnt_slice_r_reg[2] ,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    bm_end_r1_2,
    prbs_rdlvl_done_pulse,
    po_cnt_dec,
    new_cnt_cpt_r_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec,
    rdlvl_stg1_start_reg);
  output freq_refclk;
  output mem_refclk;
  output sync_pulse;
  output CLK;
  output rst_sync_r1_reg_0;
  output ui_clk_sync_rst;
  output rstdiv0_sync_r1;
  output \read_fifo.head_r_reg[0] ;
  output \periodic_read_request.periodic_rd_r_cnt_reg ;
  output \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  output [0:0]SR;
  output cal2_if_reset_reg;
  output \complex_address_reg[0] ;
  output [1:0]\fine_inc_reg[7][4] ;
  output [0:0]\corse_inc_reg[7][1] ;
  output [0:0]\corse_cnt_reg[0][1] ;
  output [1:0]\smallest_reg[7][2] ;
  output [1:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ;
  output [0:0]\stable_pass_cnt_reg[0] ;
  output [0:0]\neutral_min_limit_reg[0] ;
  output [0:0]\device_temp_init_reg[0] ;
  output [0:0]\three_inc_min_limit_reg[11] ;
  output [0:0]\one_dec_max_limit_reg[11] ;
  output \maintenance_request.maint_zq_r_lcl_reg ;
  output \maintenance_request.maint_sre_r_lcl_reg ;
  output \maint_controller.maint_wip_r_lcl_reg ;
  output \last_master_r_reg[0] ;
  output \complex_num_writes_dec_reg[0] ;
  output \wait_cnt_reg[0] ;
  output reset_reg;
  output rst_sync_r1_reg_1;
  output [0:0]ADDRA;
  output [0:0]D;
  output pll_lock;
  output act_wait_r_lcl_reg;
  output act_wait_r_lcl_reg_0;
  output act_wait_r_lcl_reg_1;
  output act_wait_r_lcl_reg_2;
  output complex_row0_rd_done1;
  output [0:0]SS;
  output [0:0]\tap_cnt_cpt_r_reg[5] ;
  output \samp_edge_cnt0_r_reg[0] ;
  output [0:0]\wait_cnt_r_reg[0] ;
  output [0:0]\cnt_shift_r_reg[0] ;
  input mmcm_clk;
  input [0:0]AS;
  input \rst_ref_sync_r_reg[0][14] ;
  input \read_fifo.tail_r_reg[2] ;
  input \idelay_tap_cnt_slice_r_reg[2] ;
  input bm_end_r1;
  input bm_end_r1_0;
  input bm_end_r1_1;
  input bm_end_r1_2;
  input prbs_rdlvl_done_pulse;
  input po_cnt_dec;
  input new_cnt_cpt_r_reg;
  input samp_edge_cnt0_en_r;
  input pi_cnt_dec;
  input rdlvl_stg1_start_reg;

  wire [0:0]ADDRA;
  wire [0:0]AS;
  wire CLK;
  wire [0:0]D;
  wire [0:0]SR;
  wire [0:0]SS;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire act_wait_r_lcl_reg_2;
  wire auxout_clk_i;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_2;
  wire cal2_if_reset_reg;
  wire clk_pll_i;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire \complex_address_reg[0] ;
  wire \complex_num_writes_dec_reg[0] ;
  wire complex_row0_rd_done1;
  wire [0:0]\corse_cnt_reg[0][1] ;
  wire [0:0]\corse_inc_reg[7][1] ;
  wire [0:0]\device_temp_init_reg[0] ;
  wire [1:0]\fine_inc_reg[7][4] ;
  wire freq_refclk;
  wire \gen_mmcm.mmcm_i_i_1_n_0 ;
  wire \gen_mmcm.mmcm_i_n_17 ;
  wire \gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ;
  wire \idelay_tap_cnt_slice_r_reg[2] ;
  wire \last_master_r_reg[0] ;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire \maintenance_request.maint_sre_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire mem_refclk;
  wire mmcm_clk;
  wire mmcm_ps_clk_bufg_in;
  wire [0:0]\neutral_min_limit_reg[0] ;
  wire new_cnt_cpt_r_reg;
  wire [0:0]\one_dec_max_limit_reg[11] ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  wire \periodic_read_request.periodic_rd_r_cnt_reg ;
  wire pi_cnt_dec;
  wire pll_clk3;
  wire pll_clk3_out;
  wire pll_clkfbout;
  wire pll_lock;
  wire pll_locked_i;
  wire po_cnt_dec;
  wire prbs_rdlvl_done_pulse;
  wire [1:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] ;
  wire rdlvl_stg1_start_reg;
  wire \read_fifo.head_r_reg[0] ;
  wire \read_fifo.tail_r_reg[2] ;
  wire reset_reg;
  wire \rst_ref_sync_r_reg[0][14] ;
  wire [11:0]rst_sync_r;
  (* MAX_FANOUT = "0'b" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rst_sync_r1;
  wire rst_sync_r1_reg_0;
  wire rst_sync_r1_reg_1;
  wire [11:0]rstdiv0_sync_r;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt0_r_reg[0] ;
  wire [1:0]\smallest_reg[7][2] ;
  wire [0:0]\stable_pass_cnt_reg[0] ;
  wire sync_pulse;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire [0:0]\three_inc_min_limit_reg[11] ;
  wire u_bufh_auxout_clk_n_0;
  (* MAX_FANOUT = "0'b" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "50" *) wire ui_clk_sync_rst;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire \wait_cnt_reg[0] ;
  wire \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT1_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ;
  wire [15:0]\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED ;
  wire NLW_plle2_i_CLKOUT5_UNCONNECTED;
  wire NLW_plle2_i_DRDY_UNCONNECTED;
  wire [15:0]NLW_plle2_i_DO_UNCONNECTED;

  assign rstdiv0_sync_r1 = ui_clk_sync_rst;
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'hE)) 
    act_wait_r_lcl_i_3__1
       (.I0(\maint_controller.maint_wip_r_lcl_reg ),
        .I1(bm_end_r1),
        .O(act_wait_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hE)) 
    act_wait_r_lcl_i_3__2
       (.I0(\maint_controller.maint_wip_r_lcl_reg ),
        .I1(bm_end_r1_0),
        .O(act_wait_r_lcl_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hE)) 
    act_wait_r_lcl_i_4__1
       (.I0(\maint_controller.maint_wip_r_lcl_reg ),
        .I1(bm_end_r1_1),
        .O(act_wait_r_lcl_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'hE)) 
    act_wait_r_lcl_i_4__2
       (.I0(\maint_controller.maint_wip_r_lcl_reg ),
        .I1(bm_end_r1_2),
        .O(act_wait_r_lcl_reg_2));
  LUT2 #(
    .INIT(4'hB)) 
    \cnt_shift_r[3]_i_1 
       (.I0(reset_reg),
        .I1(rdlvl_stg1_start_reg),
        .O(\cnt_shift_r_reg[0] ));
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_writes_dec[4]_i_1 
       (.I0(\complex_num_writes_dec_reg[0] ),
        .I1(prbs_rdlvl_done_pulse),
        .O(complex_row0_rd_done1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  MMCME2_ADV #(
    .BANDWIDTH("HIGH"),
    .CLKFBOUT_MULT_F(8.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(12.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(16.000000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("TRUE"),
    .CLKOUT1_DIVIDE(1),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(1),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(0.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(1),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(1),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("BUF_IN"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PSEN_INVERTED(1'b0),
    .IS_PSINCDEC_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.000000),
    .REF_JITTER2(0.010000),
    .SS_EN("FALSE"),
    .SS_MODE("CENTER_HIGH"),
    .SS_MOD_PERIOD(10000),
    .STARTUP_WAIT("FALSE")) 
    \gen_mmcm.mmcm_i 
       (.CLKFBIN(CLK),
        .CLKFBOUT(clk_pll_i),
        .CLKFBOUTB(\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ),
        .CLKFBSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ),
        .CLKIN1(pll_clk3),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ),
        .CLKOUT0(mmcm_ps_clk_bufg_in),
        .CLKOUT0B(\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ),
        .CLKOUT1(\NLW_gen_mmcm.mmcm_i_CLKOUT1_UNCONNECTED ),
        .CLKOUT1B(\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ),
        .CLKOUT2(\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ),
        .CLKOUT2B(\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ),
        .CLKOUT3(\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ),
        .CLKOUT3B(\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ),
        .CLKOUT4(\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ),
        .CLKOUT5(\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ),
        .CLKOUT6(\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED [15:0]),
        .DRDY(\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ),
        .DWE(1'b0),
        .LOCKED(rst_sync_r1_reg_0),
        .PSCLK(CLK),
        .PSDONE(\gen_mmcm.mmcm_i_n_17 ),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(\gen_mmcm.mmcm_i_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_mmcm.mmcm_i_i_1 
       (.I0(pll_locked_i),
        .O(\gen_mmcm.mmcm_i_i_1_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG \gen_mmcm.u_bufg_mmcm_ps_clk 
       (.I(mmcm_ps_clk_bufg_in),
        .O(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \idelay_tap_cnt_r[0][0][3]_i_1 
       (.I0(reset_reg),
        .I1(\idelay_tap_cnt_slice_r_reg[2] ),
        .O(D));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h7)) 
    phaser_ref_i_i_1
       (.I0(rst_sync_r1_reg_0),
        .I1(pll_locked_i),
        .O(rst_sync_r1_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phy_control_i_i_1
       (.I0(pll_locked_i),
        .I1(rst_sync_r1_reg_0),
        .O(pll_lock));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PLLE2_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT(4),
    .CLKFBOUT_PHASE(0.000000),
    .CLKIN1_PERIOD(3.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE(2),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT2_DIVIDE(64),
    .CLKOUT2_DUTY_CYCLE(0.062500),
    .CLKOUT2_PHASE(9.843750),
    .CLKOUT3_DIVIDE(16),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT4_DIVIDE(8),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(168.750000),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .STARTUP_WAIT("FALSE")) 
    plle2_i
       (.CLKFBIN(pll_clkfbout),
        .CLKFBOUT(pll_clkfbout),
        .CLKIN1(mmcm_clk),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKOUT0(freq_refclk),
        .CLKOUT1(mem_refclk),
        .CLKOUT2(sync_pulse),
        .CLKOUT3(pll_clk3_out),
        .CLKOUT4(auxout_clk_i),
        .CLKOUT5(NLW_plle2_i_CLKOUT5_UNCONNECTED),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(NLW_plle2_i_DO_UNCONNECTED[15:0]),
        .DRDY(NLW_plle2_i_DRDY_UNCONNECTED),
        .DWE(1'b0),
        .LOCKED(pll_locked_i),
        .PWRDWN(1'b0),
        .RST(AS));
  LUT2 #(
    .INIT(4'h1)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_8 
       (.I0(\last_master_r_reg[0] ),
        .I1(\read_fifo.tail_r_reg[2] ),
        .O(ADDRA));
  FDPE rst_sync_r1_reg
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r1));
  FDPE \rst_sync_r_reg[0] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[0]));
  FDPE \rst_sync_r_reg[10] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[9]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[10]));
  FDPE \rst_sync_r_reg[11] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[10]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[11]));
  FDPE \rst_sync_r_reg[1] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[0]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[1]));
  FDPE \rst_sync_r_reg[2] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[1]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[2]));
  FDPE \rst_sync_r_reg[3] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[2]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[3]));
  FDPE \rst_sync_r_reg[4] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[3]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[4]));
  FDPE \rst_sync_r_reg[5] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[4]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[5]));
  FDPE \rst_sync_r_reg[6] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[5]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[6]));
  FDPE \rst_sync_r_reg[7] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[6]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[7]));
  FDPE \rst_sync_r_reg[8] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[7]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[8]));
  FDPE \rst_sync_r_reg[9] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[8]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rst_sync_r[9]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(ui_clk_sync_rst));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\read_fifo.head_r_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__0
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\periodic_read_request.periodic_rd_r_cnt_reg ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__1
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\periodic_rd_generation.periodic_rd_cntr1_r_reg ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__10
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\smallest_reg[7][2] [0]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__11
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] [0]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__12
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] [1]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__13
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\stable_pass_cnt_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__14
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\neutral_min_limit_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__15
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\device_temp_init_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__16
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\three_inc_min_limit_reg[11] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__17
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\one_dec_max_limit_reg[11] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__18
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\maintenance_request.maint_zq_r_lcl_reg ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__19
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\maintenance_request.maint_sre_r_lcl_reg ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__2
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(SR));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__20
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\maint_controller.maint_wip_r_lcl_reg ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__21
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\last_master_r_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__22
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\complex_num_writes_dec_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__23
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\wait_cnt_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__24
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(reset_reg));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__3
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(cal2_if_reset_reg));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__4
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\complex_address_reg[0] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__5
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\fine_inc_reg[7][4] [0]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__6
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\corse_inc_reg[7][1] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__7
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\fine_inc_reg[7][4] [1]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__8
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\corse_cnt_reg[0][1] ));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__9
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(\smallest_reg[7][2] [1]));
  FDPE \rstdiv0_sync_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[0]));
  FDPE \rstdiv0_sync_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[9]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[10]));
  FDPE \rstdiv0_sync_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[10]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[11]));
  FDPE \rstdiv0_sync_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[0]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[1]));
  FDPE \rstdiv0_sync_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[1]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[2]));
  FDPE \rstdiv0_sync_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[2]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[3]));
  FDPE \rstdiv0_sync_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[3]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[4]));
  FDPE \rstdiv0_sync_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[4]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[5]));
  FDPE \rstdiv0_sync_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[5]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[6]));
  FDPE \rstdiv0_sync_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[6]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[7]));
  FDPE \rstdiv0_sync_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[7]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[8]));
  FDPE \rstdiv0_sync_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[8]),
        .PRE(\rst_ref_sync_r_reg[0][14] ),
        .Q(rstdiv0_sync_r[9]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \samp_edge_cnt0_r[0]_i_1 
       (.I0(reset_reg),
        .I1(samp_edge_cnt0_en_r),
        .O(\samp_edge_cnt0_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \tap_cnt_cpt_r[5]_i_1 
       (.I0(reset_reg),
        .I1(new_cnt_cpt_r_reg),
        .O(\tap_cnt_cpt_r_reg[5] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG u_bufg_clkdiv0
       (.I(clk_pll_i),
        .O(CLK));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFH u_bufh_auxout_clk
       (.I(auxout_clk_i),
        .O(u_bufh_auxout_clk_n_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFH u_bufh_pll_clk3
       (.I(pll_clk3_out),
        .O(pll_clk3));
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt[3]_i_1 
       (.I0(\wait_cnt_reg[0] ),
        .I1(po_cnt_dec),
        .O(SS));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt_r[3]_i_1__0 
       (.I0(reset_reg),
        .I1(pi_cnt_dec),
        .O(\wait_cnt_r_reg[0] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_iodelay_ctrl" *) 
module mig_7series_0_mig_7series_v2_3_iodelay_ctrl
   (iodelay_ctrl_rdy,
    AS,
    clk_ref_i,
    sys_rst);
  output [0:0]iodelay_ctrl_rdy;
  output [0:0]AS;
  input clk_ref_i;
  input sys_rst;

  wire [0:0]AS;
  wire clk_ref_i;
  wire [0:0]iodelay_ctrl_rdy;
  wire [0:0]rst_ref;
  wire \rst_ref_sync_r_reg_n_0_[0][0] ;
  wire \rst_ref_sync_r_reg_n_0_[0][10] ;
  wire \rst_ref_sync_r_reg_n_0_[0][11] ;
  wire \rst_ref_sync_r_reg_n_0_[0][12] ;
  wire \rst_ref_sync_r_reg_n_0_[0][13] ;
  wire \rst_ref_sync_r_reg_n_0_[0][1] ;
  wire \rst_ref_sync_r_reg_n_0_[0][2] ;
  wire \rst_ref_sync_r_reg_n_0_[0][3] ;
  wire \rst_ref_sync_r_reg_n_0_[0][4] ;
  wire \rst_ref_sync_r_reg_n_0_[0][5] ;
  wire \rst_ref_sync_r_reg_n_0_[0][6] ;
  wire \rst_ref_sync_r_reg_n_0_[0][7] ;
  wire \rst_ref_sync_r_reg_n_0_[0][8] ;
  wire \rst_ref_sync_r_reg_n_0_[0][9] ;
  wire sys_rst;

  LUT1 #(
    .INIT(2'h1)) 
    plle2_i_i_1
       (.I0(sys_rst),
        .O(AS));
  FDPE \rst_ref_sync_r_reg[0][0] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(1'b0),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][0] ));
  FDPE \rst_ref_sync_r_reg[0][10] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][9] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][10] ));
  FDPE \rst_ref_sync_r_reg[0][11] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][10] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][11] ));
  FDPE \rst_ref_sync_r_reg[0][12] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][11] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][12] ));
  FDPE \rst_ref_sync_r_reg[0][13] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][12] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][13] ));
  FDPE \rst_ref_sync_r_reg[0][14] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][13] ),
        .PRE(AS),
        .Q(rst_ref));
  FDPE \rst_ref_sync_r_reg[0][1] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][0] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][1] ));
  FDPE \rst_ref_sync_r_reg[0][2] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][1] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][2] ));
  FDPE \rst_ref_sync_r_reg[0][3] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][2] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][3] ));
  FDPE \rst_ref_sync_r_reg[0][4] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][3] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][4] ));
  FDPE \rst_ref_sync_r_reg[0][5] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][4] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][5] ));
  FDPE \rst_ref_sync_r_reg[0][6] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][5] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][6] ));
  FDPE \rst_ref_sync_r_reg[0][7] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][6] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][7] ));
  FDPE \rst_ref_sync_r_reg[0][8] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][7] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][8] ));
  FDPE \rst_ref_sync_r_reg[0][9] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][8] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][9] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  IDELAYCTRL u_idelayctrl_200
       (.RDY(iodelay_ctrl_rdy),
        .REFCLK(clk_ref_i),
        .RST(rst_ref));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_mc" *) 
module mig_7series_0_mig_7series_v2_3_mc
   (req_periodic_rd_r_lcl_reg,
    accept_ns,
    sent_col,
    col_rd_wr,
    bm_end_r1,
    bm_end_r1_0,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    app_ref_ack,
    app_zq_ack,
    mc_cmd,
    E,
    tempmon_sample_en,
    mc_ras_n,
    mc_cs_n,
    mc_odt,
    mc_cke,
    mc_wrdata_en,
    mc_cas_n,
    \periodic_read_request.periodic_rd_r_lcl_reg ,
    idle,
    periodic_rd_cntr_r,
    app_sr_active,
    refresh_bank_r,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    demand_priority_r_reg,
    demand_priority_r_reg_0,
    demand_priority_r_reg_1,
    Q,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    \cmd_pipe_plus.mc_address_reg[13]_0 ,
    \cmd_pipe_plus.mc_address_reg[13]_1 ,
    \read_fifo.tail_r_reg[3] ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    \cmd_pipe_plus.mc_bank_reg[8]_0 ,
    \cmd_pipe_plus.mc_bank_reg[8]_1 ,
    \cmd_pipe_plus.mc_address_reg[41]_0 ,
    \cmd_pipe_plus.mc_address_reg[41]_1 ,
    phy_dout,
    \wr_ptr_timing_reg[0] ,
    \wr_ptr_timing_reg[0]_0 ,
    app_rd_data_end_ns,
    \not_strict_mode.app_rd_data_end_reg ,
    pointer_we,
    \write_buffer.wr_buf_out_data_reg[389] ,
    \write_buffer.wr_buf_out_data_reg[197] ,
    \write_buffer.wr_buf_out_data_reg[53] ,
    \my_empty_reg[6] ,
    \wr_ptr_timing_reg[0]_1 ,
    \phy_ctl_wd_i1_reg[20] ,
    \phy_ctl_wd_i1_reg[22] ,
    \phy_ctl_wd_i1_reg[21] ,
    \phy_ctl_wd_i1_reg[19] ,
    \phy_ctl_wd_i1_reg[18] ,
    \phy_ctl_wd_i1_reg[17] ,
    \data_offset_1_i1_reg[3] ,
    \data_offset_1_i1_reg[5] ,
    \data_offset_1_i1_reg[4] ,
    \data_offset_1_i1_reg[2] ,
    \data_offset_1_i1_reg[1] ,
    \data_offset_1_i1_reg[0] ,
    \data_offset_2_i1_reg[3] ,
    \data_offset_2_i1_reg[5] ,
    \data_offset_2_i1_reg[4] ,
    \data_offset_2_i1_reg[2] ,
    \data_offset_2_i1_reg[1] ,
    \data_offset_2_i1_reg[0] ,
    CLK,
    was_wr0,
    rstdiv0_sync_r1_reg_rep__1,
    p_145_out,
    rstdiv0_sync_r1_reg_rep__0,
    p_106_out,
    p_67_out,
    phy_mc_ctl_full,
    of_ctl_full_v,
    p_28_out,
    ADDRC,
    rstdiv0_sync_r1_reg_rep__18,
    maint_prescaler_r1,
    rstdiv0_sync_r1_reg_rep__19,
    init_calib_complete_reg_rep,
    init_calib_complete_reg_rep_0,
    app_ref_req,
    app_zq_req,
    rstdiv0_sync_r1_reg_rep__20,
    app_rdy_r_reg,
    app_en_r2,
    app_sr_req,
    rstdiv0_sync_r1_reg_rep__21,
    \read_fifo.tail_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    init_complete_r1_timing_reg,
    rstdiv0_sync_r1_reg_rep__24,
    rstdiv0_sync_r1_reg_rep__20_0,
    S,
    \app_addr_r1_reg[22] ,
    \app_addr_r1_reg[22]_0 ,
    \app_addr_r1_reg[22]_1 ,
    rstdiv0_sync_r1_reg_rep__20_1,
    rstdiv0_sync_r1_reg_rep__20_2,
    rstdiv0_sync_r1_reg_rep__20_3,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    app_cmd_r2,
    \app_cmd_r1_reg[1] ,
    row,
    phy_mc_data_full,
    init_calib_complete_reg_rep__15,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \not_strict_mode.status_ram.rd_buf_we_r1_reg ,
    ram_init_done_r,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] ,
    init_complete_r1_timing_reg_0,
    init_complete_r1_timing_reg_1,
    D,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ,
    granted_col_r_reg,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ,
    granted_col_r_reg_0,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ,
    rstdiv0_sync_r1_reg_rep);
  output req_periodic_rd_r_lcl_reg;
  output accept_ns;
  output sent_col;
  output col_rd_wr;
  output bm_end_r1;
  output bm_end_r1_0;
  output ras_timer_zero_r_reg;
  output ras_timer_zero_r_reg_0;
  output app_ref_ack;
  output app_zq_ack;
  output [1:0]mc_cmd;
  output [0:0]E;
  output tempmon_sample_en;
  output [2:0]mc_ras_n;
  output [0:0]mc_cs_n;
  output [0:0]mc_odt;
  output [0:0]mc_cke;
  output mc_wrdata_en;
  output [2:0]mc_cas_n;
  output \periodic_read_request.periodic_rd_r_lcl_reg ;
  output idle;
  output periodic_rd_cntr_r;
  output app_sr_active;
  output refresh_bank_r;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output demand_priority_r_reg;
  output demand_priority_r_reg_0;
  output demand_priority_r_reg_1;
  output [2:0]Q;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[13]_0 ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[13]_1 ;
  output [3:0]\read_fifo.tail_r_reg[3] ;
  output \read_fifo.fifo_out_data_r_reg[5] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[41]_1 ;
  output [5:0]phy_dout;
  output [0:0]\wr_ptr_timing_reg[0] ;
  output [2:0]\wr_ptr_timing_reg[0]_0 ;
  output app_rd_data_end_ns;
  output [7:0]\not_strict_mode.app_rd_data_end_reg ;
  output pointer_we;
  output [3:0]\write_buffer.wr_buf_out_data_reg[389] ;
  output [3:0]\write_buffer.wr_buf_out_data_reg[197] ;
  output [3:0]\write_buffer.wr_buf_out_data_reg[53] ;
  output [38:0]\my_empty_reg[6] ;
  output [8:0]\wr_ptr_timing_reg[0]_1 ;
  output [0:0]\phy_ctl_wd_i1_reg[20] ;
  output \phy_ctl_wd_i1_reg[22] ;
  output \phy_ctl_wd_i1_reg[21] ;
  output \phy_ctl_wd_i1_reg[19] ;
  output \phy_ctl_wd_i1_reg[18] ;
  output \phy_ctl_wd_i1_reg[17] ;
  output [0:0]\data_offset_1_i1_reg[3] ;
  output \data_offset_1_i1_reg[5] ;
  output \data_offset_1_i1_reg[4] ;
  output \data_offset_1_i1_reg[2] ;
  output \data_offset_1_i1_reg[1] ;
  output \data_offset_1_i1_reg[0] ;
  output [0:0]\data_offset_2_i1_reg[3] ;
  output \data_offset_2_i1_reg[5] ;
  output \data_offset_2_i1_reg[4] ;
  output \data_offset_2_i1_reg[2] ;
  output \data_offset_2_i1_reg[1] ;
  output \data_offset_2_i1_reg[0] ;
  input CLK;
  input was_wr0;
  input rstdiv0_sync_r1_reg_rep__1;
  input p_145_out;
  input rstdiv0_sync_r1_reg_rep__0;
  input p_106_out;
  input p_67_out;
  input phy_mc_ctl_full;
  input [0:0]of_ctl_full_v;
  input p_28_out;
  input [3:0]ADDRC;
  input rstdiv0_sync_r1_reg_rep__18;
  input maint_prescaler_r1;
  input rstdiv0_sync_r1_reg_rep__19;
  input init_calib_complete_reg_rep;
  input init_calib_complete_reg_rep_0;
  input app_ref_req;
  input app_zq_req;
  input rstdiv0_sync_r1_reg_rep__20;
  input app_rdy_r_reg;
  input app_en_r2;
  input app_sr_req;
  input rstdiv0_sync_r1_reg_rep__21;
  input \read_fifo.tail_r_reg[1] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input init_complete_r1_timing_reg;
  input rstdiv0_sync_r1_reg_rep__24;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input [0:0]S;
  input [0:0]\app_addr_r1_reg[22] ;
  input [0:0]\app_addr_r1_reg[22]_0 ;
  input [0:0]\app_addr_r1_reg[22]_1 ;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input rstdiv0_sync_r1_reg_rep__20_2;
  input rstdiv0_sync_r1_reg_rep__20_3;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input [0:0]app_cmd_r2;
  input [0:0]\app_cmd_r1_reg[1] ;
  input [13:0]row;
  input phy_mc_data_full;
  input init_calib_complete_reg_rep__15;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ;
  input ram_init_done_r;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;
  input init_complete_r1_timing_reg_0;
  input init_complete_r1_timing_reg_1;
  input [0:0]D;
  input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ;
  input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] ;
  input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  input \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;
  input [0:0]granted_col_r_reg;
  input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ;
  input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] ;
  input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  input \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;
  input [0:0]granted_col_r_reg_0;
  input \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  input \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16] ;
  input \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14] ;
  input \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ;
  input \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ;
  input rstdiv0_sync_r1_reg_rep;

  wire [3:0]ADDRC;
  wire CLK;
  wire [0:0]D;
  wire [0:0]E;
  wire [2:0]Q;
  wire [0:0]S;
  wire accept_ns;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [0:0]\app_addr_r1_reg[22]_0 ;
  wire [0:0]\app_addr_r1_reg[22]_1 ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_en_r2;
  wire app_rd_data_end_ns;
  wire app_rdy_r_reg;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire \arb_mux0/arb_select0/cke_r ;
  wire \arb_mux0/col_rd_wr_r ;
  wire \bank_cntrl[0].bank0/wait_for_maint_r ;
  wire \bank_cntrl[1].bank0/wait_for_maint_r ;
  wire \bank_cntrl[2].bank0/wait_for_maint_r ;
  wire \bank_cntrl[3].bank0/wait_for_maint_r ;
  wire bank_mach0_n_115;
  wire bank_mach0_n_19;
  wire bank_mach0_n_20;
  wire bank_mach0_n_22;
  wire bank_mach0_n_24;
  wire bank_mach0_n_25;
  wire bank_mach0_n_26;
  wire bank_mach0_n_27;
  wire bank_mach0_n_42;
  wire bank_mach0_n_44;
  wire bank_mach0_n_45;
  wire bank_mach0_n_46;
  wire bank_mach0_n_56;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[13]_0 ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[13]_1 ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[41]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  wire [4:0]col_data_buf_addr;
  wire col_mach0_n_10;
  wire col_mach0_n_11;
  wire col_periodic_rd;
  wire col_rd_wr;
  wire [4:0]col_wr_data_buf_addr_r;
  wire \data_offset_1_i1_reg[0] ;
  wire \data_offset_1_i1_reg[1] ;
  wire \data_offset_1_i1_reg[2] ;
  wire [0:0]\data_offset_1_i1_reg[3] ;
  wire \data_offset_1_i1_reg[4] ;
  wire \data_offset_1_i1_reg[5] ;
  wire \data_offset_2_i1_reg[0] ;
  wire \data_offset_2_i1_reg[1] ;
  wire \data_offset_2_i1_reg[2] ;
  wire [0:0]\data_offset_2_i1_reg[3] ;
  wire \data_offset_2_i1_reg[4] ;
  wire \data_offset_2_i1_reg[5] ;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire [0:0]granted_col_r_reg;
  wire [0:0]granted_col_r_reg_0;
  wire idle;
  wire inhbt_act_faw_r;
  wire init_calib_complete_reg_rep;
  wire init_calib_complete_reg_rep_0;
  wire init_calib_complete_reg_rep__15;
  wire init_complete_r1_timing_reg;
  wire init_complete_r1_timing_reg_0;
  wire init_complete_r1_timing_reg_1;
  wire insert_maint_r;
  wire insert_maint_r1;
  wire maint_prescaler_r1;
  wire maint_rank_r;
  wire maint_ref_zq_wip;
  wire maint_req_r;
  wire maint_sre_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire [41:0]mc_address_ns;
  wire [8:0]mc_bank_ns;
  wire [2:0]mc_cas_n;
  wire [1:0]mc_cas_n_ns;
  wire [0:0]mc_cke;
  wire [1:1]mc_cke_ns;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_cs_n_ns;
  wire [0:0]mc_odt;
  wire [0:0]mc_odt_ns;
  wire [2:0]mc_ras_n;
  wire [2:0]mc_ras_n_ns;
  wire mc_ref_zq_wip_ns;
  wire [2:0]mc_we_n_ns;
  wire mc_wrdata_en;
  wire [38:0]\my_empty_reg[6] ;
  wire [7:0]\not_strict_mode.app_rd_data_end_reg ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ;
  wire [0:0]of_ctl_full_v;
  wire p_106_out;
  wire p_145_out;
  wire p_28_out;
  wire p_67_out;
  wire periodic_rd_cntr_r;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire \phy_ctl_wd_i1_reg[17] ;
  wire \phy_ctl_wd_i1_reg[18] ;
  wire \phy_ctl_wd_i1_reg[19] ;
  wire [0:0]\phy_ctl_wd_i1_reg[20] ;
  wire \phy_ctl_wd_i1_reg[21] ;
  wire \phy_ctl_wd_i1_reg[22] ;
  wire [5:0]phy_dout;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire pointer_we;
  wire ram_init_done_r;
  wire \rank_cntrl[0].rank_cntrl0/act_this_rank ;
  wire \rank_cntrl[0].rank_cntrl0/int_read_this_rank ;
  wire \rank_cntrl[0].rank_cntrl0/read_this_rank ;
  wire \rank_cntrl[0].rank_cntrl0/read_this_rank_r ;
  wire \rank_common0/sre_clears_sre_request ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  wire rank_mach0_n_13;
  wire rank_mach0_n_14;
  wire rank_mach0_n_15;
  wire rank_mach0_n_16;
  wire rank_mach0_n_17;
  wire rank_mach0_n_19;
  wire rank_mach0_n_20;
  wire rank_mach0_n_22;
  wire rank_mach0_n_23;
  wire rank_mach0_n_24;
  wire rank_mach0_n_25;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire [3:0]\read_fifo.tail_r_reg[3] ;
  wire refresh_bank_r;
  wire req_periodic_rd_r_lcl_reg;
  wire [13:0]row;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__20_2;
  wire rstdiv0_sync_r1_reg_rep__20_3;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire sent_col;
  wire tempmon_sample_en;
  wire was_wr0;
  wire [0:0]\wr_ptr_timing_reg[0] ;
  wire [2:0]\wr_ptr_timing_reg[0]_0 ;
  wire [8:0]\wr_ptr_timing_reg[0]_1 ;
  wire [3:0]\write_buffer.wr_buf_out_data_reg[197] ;
  wire [3:0]\write_buffer.wr_buf_out_data_reg[389] ;
  wire [3:0]\write_buffer.wr_buf_out_data_reg[53] ;
  wire [1:1]wtr_cnt_r;

  mig_7series_0_mig_7series_v2_3_bank_mach bank_mach0
       (.CLK(CLK),
        .D({mc_we_n_ns[2],bank_mach0_n_22,mc_we_n_ns[0]}),
        .DIC(col_periodic_rd),
        .E(bank_mach0_n_20),
        .Q(Q),
        .S(S),
        .accept_ns(accept_ns),
        .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ),
        .\app_addr_r1_reg[22]_0 (\app_addr_r1_reg[22]_0 ),
        .\app_addr_r1_reg[22]_1 (\app_addr_r1_reg[22]_1 ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_en_r2(app_en_r2),
        .app_rdy_r_reg(app_rdy_r_reg),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .cke_r(\arb_mux0/arb_select0/cke_r ),
        .\cmd_pipe_plus.mc_address_reg[13] (\cmd_pipe_plus.mc_address_reg[13]_0 ),
        .\cmd_pipe_plus.mc_address_reg[13]_0 (\cmd_pipe_plus.mc_address_reg[13]_1 ),
        .\cmd_pipe_plus.mc_address_reg[41] ({mc_address_ns[41:28],mc_address_ns[24:0]}),
        .\cmd_pipe_plus.mc_address_reg[41]_0 (\cmd_pipe_plus.mc_address_reg[41]_0 ),
        .\cmd_pipe_plus.mc_address_reg[41]_1 (\cmd_pipe_plus.mc_address_reg[41]_1 ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[8] (mc_bank_ns),
        .\cmd_pipe_plus.mc_bank_reg[8]_0 (\cmd_pipe_plus.mc_bank_reg[8]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[8]_1 (\cmd_pipe_plus.mc_bank_reg[8]_1 ),
        .\cmd_pipe_plus.mc_cas_n_reg[2] ({bank_mach0_n_42,mc_cas_n_ns[0]}),
        .\cmd_pipe_plus.mc_cmd_reg[0] (sent_col),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (bank_mach0_n_46),
        .\cmd_pipe_plus.mc_ras_n_reg[1] (bank_mach0_n_19),
        .\cmd_pipe_plus.wr_data_en_reg (bank_mach0_n_44),
        .col_data_buf_addr(col_data_buf_addr),
        .\col_mux.col_rd_wr_r_reg (col_rd_wr),
        .col_rd_wr_r(\arb_mux0/col_rd_wr_r ),
        .col_wr_data_buf_addr_r(col_wr_data_buf_addr_r),
        .demand_priority_r_reg(demand_priority_r_reg),
        .demand_priority_r_reg_0(demand_priority_r_reg_0),
        .demand_priority_r_reg_1(demand_priority_r_reg_1),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .insert_maint_r(insert_maint_r),
        .insert_maint_r1(insert_maint_r1),
        .int_read_this_rank(\rank_cntrl[0].rank_cntrl0/int_read_this_rank ),
        .\maint_controller.maint_hit_busies_r_reg[0] (bank_mach0_n_26),
        .\maint_controller.maint_hit_busies_r_reg[1] (bank_mach0_n_27),
        .\maint_controller.maint_hit_busies_r_reg[2] (bank_mach0_n_24),
        .\maint_controller.maint_hit_busies_r_reg[3] (bank_mach0_n_25),
        .maint_rank_r(maint_rank_r),
        .maint_req_r(maint_req_r),
        .maint_sre_r(maint_sre_r),
        .maint_srx_r(maint_srx_r),
        .maint_wip_r(maint_wip_r),
        .maint_zq_r(maint_zq_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (rank_mach0_n_25),
        .\maintenance_request.maint_sre_r_lcl_reg (rank_mach0_n_19),
        .\maintenance_request.maint_zq_r_lcl_reg (rank_mach0_n_22),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (rank_mach0_n_24),
        .\maintenance_request.maint_zq_r_lcl_reg_1 (rank_mach0_n_23),
        .\maintenance_request.upd_last_master_r_reg (bank_mach0_n_56),
        .mc_cas_n_ns(mc_cas_n_ns[1]),
        .mc_cke_ns(mc_cke_ns),
        .mc_cmd(mc_cmd[0]),
        .mc_cs_n_ns(mc_cs_n_ns),
        .mc_odt_ns(mc_odt_ns),
        .mc_ras_n_ns({mc_ras_n_ns[2],mc_ras_n_ns[0]}),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .of_ctl_full_v(of_ctl_full_v),
        .p_106_out(p_106_out),
        .p_145_out(p_145_out),
        .p_28_out(p_28_out),
        .p_67_out(p_67_out),
        .periodic_rd_cntr_r(periodic_rd_cntr_r),
        .\periodic_read_request.periodic_rd_r_lcl_reg (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .read_this_rank(\rank_cntrl[0].rank_cntrl0/read_this_rank ),
        .read_this_rank_r(\rank_cntrl[0].rank_cntrl0/read_this_rank_r ),
        .req_periodic_rd_r_lcl_reg(req_periodic_rd_r_lcl_reg),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (bank_mach0_n_115),
        .row(row),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__19_0(rank_mach0_n_20),
        .rstdiv0_sync_r1_reg_rep__20(rank_mach0_n_17),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_2(rstdiv0_sync_r1_reg_rep__20_1),
        .rstdiv0_sync_r1_reg_rep__20_3(rstdiv0_sync_r1_reg_rep__20_2),
        .rstdiv0_sync_r1_reg_rep__20_4(rstdiv0_sync_r1_reg_rep__20_3),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .sre_clears_sre_request(\rank_common0/sre_clears_sre_request ),
        .wait_for_maint_r(\bank_cntrl[0].bank0/wait_for_maint_r ),
        .wait_for_maint_r_0(\bank_cntrl[1].bank0/wait_for_maint_r ),
        .wait_for_maint_r_1(\bank_cntrl[2].bank0/wait_for_maint_r ),
        .wait_for_maint_r_2(\bank_cntrl[3].bank0/wait_for_maint_r ),
        .wait_for_maint_r_lcl_reg(rank_mach0_n_14),
        .wait_for_maint_r_lcl_reg_0(rank_mach0_n_13),
        .wait_for_maint_r_lcl_reg_1(rank_mach0_n_16),
        .wait_for_maint_r_lcl_reg_2(rank_mach0_n_15),
        .was_wr0(was_wr0),
        .\wtr_timer.wtr_cnt_r_reg[0] (bank_mach0_n_45),
        .\wtr_timer.wtr_cnt_r_reg[1] (wtr_cnt_r));
  FDRE \cmd_pipe_plus.mc_address_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[0]),
        .Q(\my_empty_reg[6] [0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[10]),
        .Q(\my_empty_reg[6] [10]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[11]),
        .Q(\my_empty_reg[6] [11]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[12]),
        .Q(\my_empty_reg[6] [12]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[13]),
        .Q(\my_empty_reg[6] [13]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[14]),
        .Q(\my_empty_reg[6] [14]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[15]),
        .Q(\my_empty_reg[6] [15]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[16]),
        .Q(\my_empty_reg[6] [16]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[17]),
        .Q(\my_empty_reg[6] [17]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[18]),
        .Q(\my_empty_reg[6] [18]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[19]),
        .Q(\my_empty_reg[6] [19]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[1]),
        .Q(\my_empty_reg[6] [1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[20]),
        .Q(\my_empty_reg[6] [20]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[21]),
        .Q(\my_empty_reg[6] [21]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[22]),
        .Q(\my_empty_reg[6] [22]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[23]),
        .Q(\my_empty_reg[6] [23]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[24]),
        .Q(\my_empty_reg[6] [24]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[28]),
        .Q(\my_empty_reg[6] [25]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[29]),
        .Q(\my_empty_reg[6] [26]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[2]),
        .Q(\my_empty_reg[6] [2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[30]),
        .Q(\my_empty_reg[6] [27]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[31]),
        .Q(\my_empty_reg[6] [28]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[32]),
        .Q(\my_empty_reg[6] [29]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[33]),
        .Q(\my_empty_reg[6] [30]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[34]),
        .Q(\my_empty_reg[6] [31]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[35]),
        .Q(\my_empty_reg[6] [32]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[36]),
        .Q(\my_empty_reg[6] [33]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[37]),
        .Q(\my_empty_reg[6] [34]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[38]),
        .Q(\my_empty_reg[6] [35]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[39]),
        .Q(\my_empty_reg[6] [36]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[3]),
        .Q(\my_empty_reg[6] [3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[40]),
        .Q(\my_empty_reg[6] [37]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[41]),
        .Q(\my_empty_reg[6] [38]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[4]),
        .Q(\my_empty_reg[6] [4]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[5]),
        .Q(\my_empty_reg[6] [5]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[6]),
        .Q(\my_empty_reg[6] [6]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[7]),
        .Q(\my_empty_reg[6] [7]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[8]),
        .Q(\my_empty_reg[6] [8]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[9]),
        .Q(\my_empty_reg[6] [9]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[0]),
        .Q(\wr_ptr_timing_reg[0]_1 [0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[1]),
        .Q(\wr_ptr_timing_reg[0]_1 [1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[2]),
        .Q(\wr_ptr_timing_reg[0]_1 [2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[3]),
        .Q(\wr_ptr_timing_reg[0]_1 [3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[4]),
        .Q(\wr_ptr_timing_reg[0]_1 [4]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[5]),
        .Q(\wr_ptr_timing_reg[0]_1 [5]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[6]),
        .Q(\wr_ptr_timing_reg[0]_1 [6]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[7]),
        .Q(\wr_ptr_timing_reg[0]_1 [7]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[8]),
        .Q(\wr_ptr_timing_reg[0]_1 [8]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cas_n_ns[0]),
        .Q(mc_cas_n[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cas_n_ns[1]),
        .Q(mc_cas_n[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_42),
        .Q(mc_cas_n[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cke_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cke_ns),
        .Q(mc_cke),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cmd_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(sent_col),
        .Q(mc_cmd[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cmd_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_20),
        .Q(mc_cmd[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cs_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cs_n_ns),
        .Q(mc_cs_n),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ),
        .Q(\data_offset_1_i1_reg[0] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ),
        .Q(\data_offset_1_i1_reg[1] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] ),
        .Q(\data_offset_1_i1_reg[2] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(granted_col_r_reg),
        .Q(\data_offset_1_i1_reg[3] ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ),
        .Q(\data_offset_1_i1_reg[4] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ),
        .Q(\data_offset_1_i1_reg[5] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ),
        .Q(\data_offset_2_i1_reg[0] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ),
        .Q(\data_offset_2_i1_reg[1] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14] ),
        .Q(\data_offset_2_i1_reg[2] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(granted_col_r_reg_0),
        .Q(\data_offset_2_i1_reg[3] ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16] ),
        .Q(\data_offset_2_i1_reg[4] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ),
        .Q(\data_offset_2_i1_reg[5] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ),
        .Q(\phy_ctl_wd_i1_reg[17] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ),
        .Q(\phy_ctl_wd_i1_reg[18] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] ),
        .Q(\phy_ctl_wd_i1_reg[19] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D),
        .Q(\phy_ctl_wd_i1_reg[20] ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ),
        .Q(\phy_ctl_wd_i1_reg[21] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .Q(\phy_ctl_wd_i1_reg[22] ),
        .R(bank_mach0_n_46));
  FDRE \cmd_pipe_plus.mc_odt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_odt_ns),
        .Q(mc_odt),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_ras_n_ns[0]),
        .Q(mc_ras_n[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_19),
        .Q(mc_ras_n[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_ras_n_ns[2]),
        .Q(mc_ras_n[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_we_n_ns[0]),
        .Q(\wr_ptr_timing_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_22),
        .Q(\wr_ptr_timing_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_we_n_ns[2]),
        .Q(\wr_ptr_timing_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_wrdata_en_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(col_mach0_n_10),
        .Q(mc_wrdata_en),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[0]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[0]),
        .Q(\write_buffer.wr_buf_out_data_reg[389] [0]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[0]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[0]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[0]),
        .Q(\write_buffer.wr_buf_out_data_reg[197] [0]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[0]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[0]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[0]),
        .Q(\write_buffer.wr_buf_out_data_reg[53] [0]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[1]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[1]),
        .Q(\write_buffer.wr_buf_out_data_reg[389] [1]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[1]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[1]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[1]),
        .Q(\write_buffer.wr_buf_out_data_reg[197] [1]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[1]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[1]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[1]),
        .Q(\write_buffer.wr_buf_out_data_reg[53] [1]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[2]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[2]),
        .Q(\write_buffer.wr_buf_out_data_reg[389] [2]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[2]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[2]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[2]),
        .Q(\write_buffer.wr_buf_out_data_reg[197] [2]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[2]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[2]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[2]),
        .Q(\write_buffer.wr_buf_out_data_reg[53] [2]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[3]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[3]),
        .Q(\write_buffer.wr_buf_out_data_reg[389] [3]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[3]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[3]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[3]),
        .Q(\write_buffer.wr_buf_out_data_reg[197] [3]),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmd_pipe_plus.wr_data_addr_reg[3]" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr_r[3]),
        .Q(\write_buffer.wr_buf_out_data_reg[53] [3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.wr_data_en_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_44),
        .Q(E),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_col_mach col_mach0
       (.ADDRC(ADDRC),
        .CLK(CLK),
        .DIC(col_periodic_rd),
        .E(bank_mach0_n_20),
        .app_rd_data_end_ns(app_rd_data_end_ns),
        .\cmd_pipe_plus.mc_wrdata_en_reg (col_mach0_n_10),
        .col_data_buf_addr(col_data_buf_addr),
        .col_rd_wr_r(\arb_mux0/col_rd_wr_r ),
        .col_wr_data_buf_addr_r(col_wr_data_buf_addr_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .init_complete_r1_timing_reg_0(init_complete_r1_timing_reg_0),
        .init_complete_r1_timing_reg_1(init_complete_r1_timing_reg_1),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .mc_cmd(mc_cmd[0]),
        .mc_read_idle_r_reg(col_mach0_n_11),
        .mc_ref_zq_wip_ns(mc_ref_zq_wip_ns),
        .\not_strict_mode.app_rd_data_end_reg (\not_strict_mode.app_rd_data_end_reg ),
        .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ),
        .\read_fifo.fifo_out_data_r_reg[4]_0 (\read_fifo.fifo_out_data_r_reg[4] ),
        .\read_fifo.fifo_out_data_r_reg[5]_0 (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1] ),
        .\read_fifo.tail_r_reg[2]_0 (\read_fifo.tail_r_reg[3] [2]),
        .\read_fifo.tail_r_reg[2]_1 (\read_fifo.tail_r_reg[3] [1]),
        .\read_fifo.tail_r_reg[2]_2 (\read_fifo.tail_r_reg[3] [0]),
        .\read_fifo.tail_r_reg[3]_0 (\read_fifo.tail_r_reg[3] [3]),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21));
  FDRE mc_read_idle_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_mach0_n_11),
        .Q(idle),
        .R(maint_prescaler_r1));
  FDRE mc_ref_zq_wip_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mc_ref_zq_wip_ns),
        .Q(tempmon_sample_en),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_3
       (.I0(mc_ras_n[0]),
        .I1(init_calib_complete_reg_rep__15),
        .O(\wr_ptr_timing_reg[0] ));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_2
       (.I0(mc_cs_n),
        .I1(init_calib_complete_reg_rep__15),
        .O(phy_dout[0]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_1
       (.I0(mc_ras_n[2]),
        .I1(init_calib_complete_reg_rep__15),
        .O(phy_dout[1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_3
       (.I0(\wr_ptr_timing_reg[0]_0 [0]),
        .I1(init_calib_complete_reg_rep__15),
        .O(phy_dout[2]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_4
       (.I0(\wr_ptr_timing_reg[0]_0 [2]),
        .I1(init_calib_complete_reg_rep__15),
        .O(phy_dout[3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_2
       (.I0(mc_cas_n[0]),
        .I1(init_calib_complete_reg_rep__15),
        .O(phy_dout[4]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_1
       (.I0(mc_cas_n[2]),
        .I1(init_calib_complete_reg_rep__15),
        .O(phy_dout[5]));
  LUT2 #(
    .INIT(4'hB)) 
    \pointer_ram.rams[0].RAM32M0_i_1 
       (.I0(E),
        .I1(ram_init_done_r),
        .O(pointer_we));
  mig_7series_0_mig_7series_v2_3_rank_mach rank_mach0
       (.CLK(CLK),
        .Q(wtr_cnt_r),
        .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ),
        .app_ref_ack(app_ref_ack),
        .app_ref_r_reg(refresh_bank_r),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .auto_pre_r_lcl_reg(rank_mach0_n_23),
        .cke_r(\arb_mux0/arb_select0/cke_r ),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (bank_mach0_n_115),
        .\grant_r_reg[2] (bank_mach0_n_45),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .init_calib_complete_reg_rep_0(init_calib_complete_reg_rep_0),
        .insert_maint_r(insert_maint_r),
        .insert_maint_r1(insert_maint_r1),
        .int_read_this_rank(\rank_cntrl[0].rank_cntrl0/int_read_this_rank ),
        .\maint_controller.maint_hit_busies_r_reg[2] (rank_mach0_n_22),
        .\maint_controller.maint_wip_r_lcl_reg (rank_mach0_n_17),
        .\maint_controller.maint_wip_r_lcl_reg_0 (bank_mach0_n_56),
        .maint_prescaler_r1(maint_prescaler_r1),
        .maint_rank_r(maint_rank_r),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .maint_req_r(maint_req_r),
        .maint_sre_r(maint_sre_r),
        .maint_srx_r(maint_srx_r),
        .maint_wip_r(maint_wip_r),
        .maint_zq_r(maint_zq_r),
        .mc_cke_ns(mc_cke_ns),
        .pass_open_bank_r_lcl_reg(rank_mach0_n_25),
        .periodic_rd_ack_r_lcl_reg(req_periodic_rd_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg_0(bank_mach0_n_27),
        .periodic_rd_ack_r_lcl_reg_1(bank_mach0_n_26),
        .periodic_rd_ack_r_lcl_reg_2(bank_mach0_n_25),
        .periodic_rd_ack_r_lcl_reg_3(bank_mach0_n_24),
        .\periodic_read_request.periodic_rd_r_lcl_reg (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .q_has_rd_r_reg(rank_mach0_n_24),
        .read_this_rank(\rank_cntrl[0].rank_cntrl0/read_this_rank ),
        .read_this_rank_r(\rank_cntrl[0].rank_cntrl0/read_this_rank_r ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (rank_mach0_n_19),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (rank_mach0_n_20),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sre_clears_sre_request(\rank_common0/sre_clears_sre_request ),
        .wait_for_maint_r(\bank_cntrl[1].bank0/wait_for_maint_r ),
        .wait_for_maint_r_0(\bank_cntrl[0].bank0/wait_for_maint_r ),
        .wait_for_maint_r_1(\bank_cntrl[3].bank0/wait_for_maint_r ),
        .wait_for_maint_r_2(\bank_cntrl[2].bank0/wait_for_maint_r ),
        .wait_for_maint_r_lcl_reg(rank_mach0_n_13),
        .wait_for_maint_r_lcl_reg_0(rank_mach0_n_14),
        .wait_for_maint_r_lcl_reg_1(rank_mach0_n_15),
        .wait_for_maint_r_lcl_reg_2(rank_mach0_n_16));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_mem_intfc" *) 
module mig_7series_0_mig_7series_v2_3_mem_intfc
   (periodic_rd_ack_r,
    accept_ns,
    bm_end_r1,
    bm_end_r1_0,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    app_ref_ack,
    app_zq_ack,
    E,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_reset_n,
    out,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \rd_ptr_timing_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \rd_ptr_timing_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \rd_ptr_timing_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    init_complete_r_timing,
    complex_row1_rd_done_reg,
    rdlvl_stg1_start_r_reg,
    init_calib_complete,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    \my_empty_reg[7]_7 ,
    periodic_rd_r,
    periodic_rd_cntr_r,
    app_sr_active,
    dqs_po_en_stg2_f_reg,
    idelay_tap_limit_r_reg,
    samp_edge_cnt0_en_r,
    fine_dly_dec_done_r1_reg,
    rd_buf_we,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    demand_priority_r_reg,
    demand_priority_r_reg_0,
    demand_priority_r_reg_1,
    Q,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[13] ,
    \cmd_pipe_plus.mc_address_reg[13]_0 ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \read_fifo.fifo_out_data_r_reg[5] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \not_strict_mode.app_rd_data_reg[352] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    rst_sync_r1_reg,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \not_strict_mode.app_rd_data_reg[488] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \idelay_tap_cnt_r_reg[0][7][3] ,
    \cmd_pipe_plus.mc_address_reg[41]_0 ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_bank_reg[8]_0 ,
    DIA,
    DIB,
    DIC,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ,
    phy_dout,
    \wr_ptr_timing_reg[0] ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    D,
    \not_strict_mode.app_rd_data_reg[24] ,
    app_rd_data_end_ns,
    \not_strict_mode.app_rd_data_end_reg ,
    pointer_we,
    \write_buffer.wr_buf_out_data_reg[389] ,
    ADDRC,
    \write_buffer.wr_buf_out_data_reg[53] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7]_10 ,
    \wr_ptr_timing_reg[3]_0 ,
    \wr_ptr_timing_reg[0]_0 ,
    \wr_ptr_timing_reg[3]_1 ,
    \wr_ptr_timing_reg[0]_1 ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_timing_reg[3]_2 ,
    \my_empty_reg[7]_11 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_2 ,
    \wr_ptr_timing_reg[3]_3 ,
    \my_empty_reg[7]_12 ,
    \wr_ptr_reg[0]_1 ,
    \wr_ptr_reg[1]_3 ,
    \wr_ptr_timing_reg[3]_4 ,
    \my_empty_reg[7]_13 ,
    p_0_in1_in,
    \not_strict_mode.app_rd_data_reg[232] ,
    \not_strict_mode.app_rd_data_reg[496]_0 ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    wr_en,
    wr_en_10,
    wr_en_11,
    wr_en_12,
    wr_en_13,
    wr_en_14,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    CLK,
    was_wr0,
    rstdiv0_sync_r1_reg_rep__1,
    p_145_out,
    rstdiv0_sync_r1_reg_rep__0,
    p_106_out,
    p_67_out,
    p_28_out,
    ADDRA,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    A_rst_primitives_reg,
    pll_lock,
    rstdiv0_sync_r1,
    sys_rst_0,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    rstdiv0_sync_r1_reg_rep__4,
    rstdiv0_sync_r1_reg_rep__3,
    rstdiv0_sync_r1_reg_rep__18,
    init_complete_r_timing_reg,
    rstdiv0_sync_r1_reg_rep__24,
    SR,
    rstdiv0_sync_r1_reg_rep__10,
    rstdiv0_sync_r1_reg_rep__2,
    rstdiv0_sync_r1_reg_rep__24_0,
    rstdiv0_sync_r1_reg_rep__13,
    rstdiv0_sync_r1_reg_rep__15,
    rstdiv0_sync_r1_reg_rep__22,
    rstdiv0_sync_r1_reg_rep__19,
    ram_init_done_r,
    app_ref_req,
    app_zq_req,
    rstdiv0_sync_r1_reg_rep__20,
    app_rdy_r_reg,
    app_en_r2,
    app_sr_req,
    rstdiv0_sync_r1_reg_rep__21,
    mem_out,
    sys_rst,
    iodelay_ctrl_rdy,
    sys_rst_1,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    rstdiv0_sync_r1_reg_rep__20_0,
    S,
    \app_addr_r1_reg[22] ,
    \app_addr_r1_reg[22]_0 ,
    \app_addr_r1_reg[22]_1 ,
    rstdiv0_sync_r1_reg_rep__20_1,
    rstdiv0_sync_r1_reg_rep__20_2,
    rstdiv0_sync_r1_reg_rep__20_3,
    \app_cmd_r2_reg[1] ,
    \app_cmd_r2_reg[0] ,
    app_cmd_r2,
    \app_cmd_r1_reg[1] ,
    row,
    complex_row0_rd_done1,
    rstdiv0_sync_r1_reg_rep__23,
    \write_buffer.wr_buf_out_data_reg[575] ,
    \write_buffer.wr_buf_out_data_reg[351] ,
    DOC,
    DOB,
    DOA,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ,
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ,
    \not_strict_mode.status_ram.rd_buf_we_r1_reg ,
    \read_fifo.fifo_out_data_r_reg[5]_0 ,
    ram_init_addr,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    \app_addr_r1_reg[26] ,
    \app_addr_r1_reg[9] ,
    rstdiv0_sync_r1_reg_rep,
    rstdiv0_sync_r1_reg_rep__9,
    rstdiv0_sync_r1_reg_rep__7,
    rstdiv0_sync_r1_reg_rep__6,
    SS,
    rstdiv0_sync_r1_reg_rep__24_1,
    rstdiv0_sync_r1_reg_rep__24_2,
    rstdiv0_sync_r1_reg_rep__24_3,
    rstdiv0_sync_r1_reg_rep__24_4,
    \device_temp_r_reg[11] ,
    rstdiv0_sync_r1_reg_rep__16,
    rstdiv0_sync_r1_reg_rep__14,
    rstdiv0_sync_r1_reg_rep__17,
    \rd_ptr_reg_rep[3] ,
    \rd_ptr_reg_rep[3]_0 ,
    \rd_ptr_reg_rep[3]_1 ,
    \rd_ptr_reg_rep[3]_2 ,
    \rd_ptr_reg_rep[3]_3 ,
    \rd_ptr_reg_rep[3]_4 ,
    rstdiv0_sync_r1_reg_rep__12);
  output periodic_rd_ack_r;
  output accept_ns;
  output bm_end_r1;
  output bm_end_r1_0;
  output ras_timer_zero_r_reg;
  output ras_timer_zero_r_reg_0;
  output app_ref_ack;
  output app_zq_ack;
  output [0:0]E;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [1:0]out;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output [1:0]\rd_ptr_timing_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output init_complete_r_timing;
  output complex_row1_rd_done_reg;
  output rdlvl_stg1_start_r_reg;
  output init_calib_complete;
  output \my_empty_reg[7] ;
  output \my_empty_reg[7]_0 ;
  output \my_empty_reg[7]_1 ;
  output \my_empty_reg[7]_2 ;
  output \my_empty_reg[7]_3 ;
  output \my_empty_reg[7]_4 ;
  output \my_empty_reg[7]_5 ;
  output \my_empty_reg[7]_6 ;
  output \my_empty_reg[7]_7 ;
  output periodic_rd_r;
  output periodic_rd_cntr_r;
  output app_sr_active;
  output dqs_po_en_stg2_f_reg;
  output idelay_tap_limit_r_reg;
  output samp_edge_cnt0_en_r;
  output fine_dly_dec_done_r1_reg;
  output rd_buf_we;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output demand_priority_r_reg;
  output demand_priority_r_reg_0;
  output demand_priority_r_reg_1;
  output [2:0]Q;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[13] ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[13]_0 ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[41] ;
  output \read_fifo.fifo_out_data_r_reg[5] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  output \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  output \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  output \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  output \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  output \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  output rst_sync_r1_reg;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  output \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  output [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  output \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  output \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  output \idelay_tap_cnt_r_reg[0][7][3] ;
  output [1:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  output [1:0]DIA;
  output [1:0]DIB;
  output [1:0]DIC;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  output [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  output [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  output [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  output [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  output [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  output [10:0]phy_dout;
  output [45:0]\wr_ptr_timing_reg[0] ;
  output [207:0]\my_empty_reg[7]_8 ;
  output [31:0]\my_empty_reg[7]_9 ;
  output [511:0]D;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output app_rd_data_end_ns;
  output [6:0]\not_strict_mode.app_rd_data_end_reg ;
  output pointer_we;
  output [3:0]\write_buffer.wr_buf_out_data_reg[389] ;
  output [3:0]ADDRC;
  output [3:0]\write_buffer.wr_buf_out_data_reg[53] ;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7]_10 ;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\wr_ptr_timing_reg[0]_1 ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1]_1 ;
  output [3:0]\wr_ptr_timing_reg[3]_2 ;
  output [3:0]\my_empty_reg[7]_11 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_2 ;
  output [3:0]\wr_ptr_timing_reg[3]_3 ;
  output [3:0]\my_empty_reg[7]_12 ;
  output \wr_ptr_reg[0]_1 ;
  output \wr_ptr_reg[1]_3 ;
  output [3:0]\wr_ptr_timing_reg[3]_4 ;
  output [3:0]\my_empty_reg[7]_13 ;
  output p_0_in1_in;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \not_strict_mode.app_rd_data_reg[496]_0 ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output wr_en;
  output wr_en_10;
  output wr_en_11;
  output wr_en_12;
  output wr_en_13;
  output wr_en_14;
  output [1:0]ddr_ck_out;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input CLK;
  input was_wr0;
  input rstdiv0_sync_r1_reg_rep__1;
  input p_145_out;
  input rstdiv0_sync_r1_reg_rep__0;
  input p_106_out;
  input p_67_out;
  input p_28_out;
  input [0:0]ADDRA;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input A_rst_primitives_reg;
  input pll_lock;
  input rstdiv0_sync_r1;
  input sys_rst_0;
  input A_rst_primitives_reg_0;
  input A_rst_primitives_reg_1;
  input A_rst_primitives_reg_2;
  input A_rst_primitives_reg_3;
  input A_rst_primitives_reg_4;
  input A_rst_primitives_reg_5;
  input A_rst_primitives_reg_6;
  input rstdiv0_sync_r1_reg_rep__4;
  input rstdiv0_sync_r1_reg_rep__3;
  input rstdiv0_sync_r1_reg_rep__18;
  input init_complete_r_timing_reg;
  input rstdiv0_sync_r1_reg_rep__24;
  input [0:0]SR;
  input [1:0]rstdiv0_sync_r1_reg_rep__10;
  input [0:0]rstdiv0_sync_r1_reg_rep__2;
  input rstdiv0_sync_r1_reg_rep__24_0;
  input [0:0]rstdiv0_sync_r1_reg_rep__13;
  input [0:0]rstdiv0_sync_r1_reg_rep__15;
  input rstdiv0_sync_r1_reg_rep__22;
  input rstdiv0_sync_r1_reg_rep__19;
  input ram_init_done_r;
  input app_ref_req;
  input app_zq_req;
  input rstdiv0_sync_r1_reg_rep__20;
  input app_rdy_r_reg;
  input app_en_r2;
  input app_sr_req;
  input rstdiv0_sync_r1_reg_rep__21;
  input [63:0]mem_out;
  input sys_rst;
  input [0:0]iodelay_ctrl_rdy;
  input sys_rst_1;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input [0:0]S;
  input [0:0]\app_addr_r1_reg[22] ;
  input [0:0]\app_addr_r1_reg[22]_0 ;
  input [0:0]\app_addr_r1_reg[22]_1 ;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input rstdiv0_sync_r1_reg_rep__20_2;
  input rstdiv0_sync_r1_reg_rep__20_3;
  input \app_cmd_r2_reg[1] ;
  input \app_cmd_r2_reg[0] ;
  input [0:0]app_cmd_r2;
  input [0:0]\app_cmd_r1_reg[1] ;
  input [13:0]row;
  input complex_row0_rd_done1;
  input rstdiv0_sync_r1_reg_rep__23;
  input [575:0]\write_buffer.wr_buf_out_data_reg[575] ;
  input [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]DOA;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  input [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ;
  input \read_fifo.fifo_out_data_r_reg[5]_0 ;
  input [0:0]ram_init_addr;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  input [2:0]\app_addr_r1_reg[26] ;
  input [9:0]\app_addr_r1_reg[9] ;
  input rstdiv0_sync_r1_reg_rep;
  input [0:0]rstdiv0_sync_r1_reg_rep__9;
  input [1:0]rstdiv0_sync_r1_reg_rep__7;
  input [0:0]rstdiv0_sync_r1_reg_rep__6;
  input [0:0]SS;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  input [11:0]\device_temp_r_reg[11] ;
  input [0:0]rstdiv0_sync_r1_reg_rep__16;
  input [0:0]rstdiv0_sync_r1_reg_rep__14;
  input [0:0]rstdiv0_sync_r1_reg_rep__17;
  input [79:0]\rd_ptr_reg_rep[3] ;
  input [41:0]\rd_ptr_reg_rep[3]_0 ;
  input [79:0]\rd_ptr_reg_rep[3]_1 ;
  input [79:0]\rd_ptr_reg_rep[3]_2 ;
  input [79:0]\rd_ptr_reg_rep[3]_3 ;
  input [79:0]\rd_ptr_reg_rep[3]_4 ;
  input [0:0]rstdiv0_sync_r1_reg_rep__12;

  wire [0:0]ADDRA;
  wire [3:0]ADDRC;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire CLK;
  wire [511:0]D;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [0:0]E;
  wire [2:0]Q;
  wire [0:0]S;
  wire [0:0]SR;
  wire [0:0]SS;
  wire accept_ns;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [0:0]\app_addr_r1_reg[22]_0 ;
  wire [0:0]\app_addr_r1_reg[22]_1 ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [0:0]\app_cmd_r1_reg[1] ;
  wire [0:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire \app_cmd_r2_reg[1] ;
  wire app_en_r2;
  wire app_rd_data_end_ns;
  wire app_rdy_r_reg;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[13]_0 ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [1:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  wire \col_mach0/p_0_in ;
  wire [3:0]\col_mach0/tail_ns ;
  wire col_rd_wr;
  wire complex_row0_rd_done1;
  wire complex_row1_rd_done_reg;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire ddr_phy_top0_n_408;
  wire ddr_phy_top0_n_412;
  wire ddr_phy_top0_n_413;
  wire ddr_phy_top0_n_414;
  wire ddr_phy_top0_n_415;
  wire ddr_phy_top0_n_416;
  wire ddr_phy_top0_n_417;
  wire ddr_phy_top0_n_418;
  wire ddr_phy_top0_n_419;
  wire ddr_phy_top0_n_420;
  wire ddr_phy_top0_n_421;
  wire ddr_phy_top0_n_422;
  wire ddr_phy_top0_n_49;
  wire ddr_phy_top0_n_53;
  wire ddr_phy_top0_n_54;
  wire ddr_phy_top0_n_69;
  wire ddr_phy_top0_n_70;
  wire ddr_phy_top0_n_72;
  wire ddr_phy_top0_n_73;
  wire ddr_phy_top0_n_74;
  wire ddr_phy_top0_n_75;
  wire ddr_phy_top0_n_76;
  wire ddr_phy_top0_n_77;
  wire ddr_phy_top0_n_78;
  wire ddr_phy_top0_n_80;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire [11:0]\device_temp_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire dqs_po_en_stg2_f_reg;
  wire fine_dly_dec_done_r1_reg;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ;
  wire [1:0]\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ;
  wire [0:0]\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ;
  wire [1:0]\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ;
  wire [1:0]\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ;
  wire [1:0]\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \idelay_tap_cnt_r_reg[0][7][3] ;
  wire idelay_tap_limit_r_reg;
  wire idle;
  wire init_calib_complete;
  wire init_complete_r_timing;
  wire init_complete_r_timing_reg;
  wire [0:0]iodelay_ctrl_rdy;
  wire mc0_n_138;
  wire mc0_n_139;
  wire mc0_n_140;
  wire mc0_n_141;
  wire mc0_n_142;
  wire mc0_n_143;
  wire mc0_n_144;
  wire mc0_n_145;
  wire mc0_n_146;
  wire mc0_n_147;
  wire mc0_n_148;
  wire mc0_n_149;
  wire mc0_n_150;
  wire mc0_n_151;
  wire mc0_n_152;
  wire mc0_n_153;
  wire mc0_n_154;
  wire mc0_n_155;
  wire [41:0]mc_address;
  wire [8:0]mc_bank;
  wire [2:0]mc_cas_n;
  wire [3:3]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [3:3]mc_data_offset_1_ns;
  wire [3:3]mc_data_offset_2_ns;
  wire [3:3]mc_data_offset_ns;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire [2:0]mc_we_n;
  wire mc_wrdata_en;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire \my_empty_reg[7] ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_10 ;
  wire [3:0]\my_empty_reg[7]_11 ;
  wire [3:0]\my_empty_reg[7]_12 ;
  wire [3:0]\my_empty_reg[7]_13 ;
  wire \my_empty_reg[7]_2 ;
  wire \my_empty_reg[7]_3 ;
  wire \my_empty_reg[7]_4 ;
  wire \my_empty_reg[7]_5 ;
  wire \my_empty_reg[7]_6 ;
  wire \my_empty_reg[7]_7 ;
  wire [207:0]\my_empty_reg[7]_8 ;
  wire [31:0]\my_empty_reg[7]_9 ;
  wire [6:0]\not_strict_mode.app_rd_data_end_reg ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[352] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  wire [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  wire \not_strict_mode.app_rd_data_reg[496]_0 ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;
  wire [0:0]\not_strict_mode.status_ram.rd_buf_we_r1_reg ;
  wire [1:0]out;
  wire p_0_in1_in;
  wire p_106_out;
  wire p_145_out;
  wire p_28_out;
  wire p_67_out;
  wire periodic_rd_ack_r;
  wire periodic_rd_cntr_r;
  wire periodic_rd_r;
  wire [10:0]phy_dout;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire pll_lock;
  wire pointer_we;
  wire [0:0]ram_init_addr;
  wire ram_init_done_r;
  wire \rank_mach0/rank_cntrl[0].rank_cntrl0/refresh_bank_r ;
  wire \rank_mach0/rank_common0/maint_prescaler_r1 ;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire rd_buf_we;
  wire [79:0]\rd_ptr_reg_rep[3] ;
  wire [41:0]\rd_ptr_reg_rep[3]_0 ;
  wire [79:0]\rd_ptr_reg_rep[3]_1 ;
  wire [79:0]\rd_ptr_reg_rep[3]_2 ;
  wire [79:0]\rd_ptr_reg_rep[3]_3 ;
  wire [79:0]\rd_ptr_reg_rep[3]_4 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rd_ptr_timing_reg[1]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1]_1 ;
  wire rdlvl_stg1_start_r_reg;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire \read_fifo.fifo_out_data_r_reg[5]_0 ;
  wire [13:0]row;
  wire rst_sync_r1_reg;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire [1:0]rstdiv0_sync_r1_reg_rep__10;
  wire [0:0]rstdiv0_sync_r1_reg_rep__12;
  wire [0:0]rstdiv0_sync_r1_reg_rep__13;
  wire [0:0]rstdiv0_sync_r1_reg_rep__14;
  wire [0:0]rstdiv0_sync_r1_reg_rep__15;
  wire [0:0]rstdiv0_sync_r1_reg_rep__16;
  wire [0:0]rstdiv0_sync_r1_reg_rep__17;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire [0:0]rstdiv0_sync_r1_reg_rep__2;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__20_2;
  wire rstdiv0_sync_r1_reg_rep__20_3;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__22;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__24_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_4;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire rstdiv0_sync_r1_reg_rep__4;
  wire [0:0]rstdiv0_sync_r1_reg_rep__6;
  wire [1:0]rstdiv0_sync_r1_reg_rep__7;
  wire [0:0]rstdiv0_sync_r1_reg_rep__9;
  wire samp_edge_cnt0_en_r;
  wire sent_col;
  wire sync_pulse;
  wire sys_rst;
  wire sys_rst_0;
  wire sys_rst_1;
  wire [3:0]tail_r;
  wire tempmon_sample_en;
  wire [1:1]\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ;
  wire was_wr0;
  wire wr_en;
  wire wr_en_10;
  wire wr_en_11;
  wire wr_en_12;
  wire wr_en_13;
  wire wr_en_14;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[0]_1 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;
  wire \wr_ptr_reg[1]_3 ;
  wire [45:0]\wr_ptr_timing_reg[0] ;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;
  wire [3:0]\wr_ptr_timing_reg[0]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3]_3 ;
  wire [3:0]\wr_ptr_timing_reg[3]_4 ;
  wire [47:0]\write_buffer.wr_buf_out_data_reg[351] ;
  wire [3:0]\write_buffer.wr_buf_out_data_reg[389] ;
  wire [3:0]\write_buffer.wr_buf_out_data_reg[53] ;
  wire [575:0]\write_buffer.wr_buf_out_data_reg[575] ;

  mig_7series_0_mig_7series_v2_3_ddr_phy_top ddr_phy_top0
       (.ADDRA({\col_mach0/tail_ns [3],ddr_phy_top0_n_80,\col_mach0/tail_ns [0]}),
        .A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .CLK(CLK),
        .D(mc_data_offset_ns),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .Q({\col_mach0/p_0_in ,\not_strict_mode.app_rd_data_end_reg [4]}),
        .SR(SR),
        .SS(SS),
        .app_zq_r_reg(ddr_phy_top0_n_53),
        .\cmd_pipe_plus.mc_address_reg[41] ({mc_address[41:28],mc_address[24:0]}),
        .\cmd_pipe_plus.mc_bank_reg[8] (mc_bank),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0] (ddr_phy_top0_n_421),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (mc0_n_149),
        .\cmd_pipe_plus.mc_data_offset_1_reg[1] (ddr_phy_top0_n_415),
        .\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (mc0_n_148),
        .\cmd_pipe_plus.mc_data_offset_1_reg[2] (ddr_phy_top0_n_74),
        .\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 (mc0_n_147),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3] (mc_data_offset_1_ns),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 (mc0_n_144),
        .\cmd_pipe_plus.mc_data_offset_1_reg[4] (ddr_phy_top0_n_414),
        .\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (mc0_n_146),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (ddr_phy_top0_n_75),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (mc0_n_145),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (ddr_phy_top0_n_422),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 (mc0_n_155),
        .\cmd_pipe_plus.mc_data_offset_2_reg[1] (ddr_phy_top0_n_417),
        .\cmd_pipe_plus.mc_data_offset_2_reg[1]_0 (mc0_n_154),
        .\cmd_pipe_plus.mc_data_offset_2_reg[2] (ddr_phy_top0_n_76),
        .\cmd_pipe_plus.mc_data_offset_2_reg[2]_0 (mc0_n_153),
        .\cmd_pipe_plus.mc_data_offset_2_reg[3] (mc_data_offset_2_ns),
        .\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 (mc0_n_150),
        .\cmd_pipe_plus.mc_data_offset_2_reg[4] (ddr_phy_top0_n_416),
        .\cmd_pipe_plus.mc_data_offset_2_reg[4]_0 (mc0_n_152),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (ddr_phy_top0_n_77),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5]_0 (mc0_n_151),
        .\cmd_pipe_plus.mc_data_offset_reg[0] (ddr_phy_top0_n_420),
        .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (mc0_n_143),
        .\cmd_pipe_plus.mc_data_offset_reg[1] (ddr_phy_top0_n_413),
        .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (mc0_n_142),
        .\cmd_pipe_plus.mc_data_offset_reg[2] (ddr_phy_top0_n_72),
        .\cmd_pipe_plus.mc_data_offset_reg[2]_0 (mc0_n_141),
        .\cmd_pipe_plus.mc_data_offset_reg[3] (mc0_n_138),
        .\cmd_pipe_plus.mc_data_offset_reg[4] (ddr_phy_top0_n_412),
        .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (mc0_n_140),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (ddr_phy_top0_n_73),
        .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (mc0_n_139),
        .\cmd_pipe_plus.mc_we_n_reg[2] (mc_we_n),
        .col_rd_wr(col_rd_wr),
        .complex_row0_rd_done1(complex_row0_rd_done1),
        .complex_row1_rd_done_reg(complex_row1_rd_done_reg),
        .\data_offset_2_i1_reg[2] (ddr_phy_top0_n_54),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\device_temp_r_reg[11] (\device_temp_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg),
        .fine_dly_dec_done_r1_reg(fine_dly_dec_done_r1_reg),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (\gen_rd[2].rd_data_rise_wl_r_reg[2] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (\gen_rd[3].rd_data_rise_wl_r_reg[3] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (\gen_rd[4].rd_data_rise_wl_r_reg[4] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (\gen_rd[5].rd_data_rise_wl_r_reg[5] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (\gen_rd[6].rd_data_rise_wl_r_reg[6] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (\gen_rd[7].rd_data_rise_wl_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .\idelay_tap_cnt_r_reg[0][7][3] (\idelay_tap_cnt_r_reg[0][7][3] ),
        .idelay_tap_limit_r_reg(idelay_tap_limit_r_reg),
        .idle(idle),
        .init_calib_complete(init_calib_complete),
        .init_complete_r_timing(init_complete_r_timing),
        .init_complete_r_timing_reg(init_complete_r_timing_reg),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .maint_prescaler_r1(\rank_mach0/rank_common0/maint_prescaler_r1 ),
        .maint_ref_zq_wip_r_reg(ddr_phy_top0_n_408),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_13 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_9 ),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[24] (\not_strict_mode.app_rd_data_reg[24] ),
        .\not_strict_mode.app_rd_data_reg[352] (\not_strict_mode.app_rd_data_reg[352] ),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376] ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[488] (\not_strict_mode.app_rd_data_reg[488] ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496] ),
        .\not_strict_mode.app_rd_data_reg[496]_0 (\not_strict_mode.app_rd_data_reg[496]_0 ),
        .\not_strict_mode.app_rd_data_reg[511] (D),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),
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        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),
        .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .phy_dout({phy_dout[9],phy_dout[6],phy_dout[3],phy_dout[1:0]}),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .pll_lock(pll_lock),
        .ram_init_addr(ram_init_addr),
        .ram_init_done_r(ram_init_done_r),
        .rd_active_r_reg(ddr_phy_top0_n_69),
        .rd_buf_we(rd_buf_we),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] ),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3]_0 ),
        .\rd_ptr_reg_rep[3]_1 (\rd_ptr_reg_rep[3]_1 ),
        .\rd_ptr_reg_rep[3]_2 (\rd_ptr_reg_rep[3]_2 ),
        .\rd_ptr_reg_rep[3]_3 (\rd_ptr_reg_rep[3]_3 ),
        .\rd_ptr_reg_rep[3]_4 (\rd_ptr_reg_rep[3]_4 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1]_0 ),
        .\rd_ptr_timing_reg[1]_1 (\rd_ptr_timing_reg[1]_1 ),
        .rdlvl_stg1_start_r_reg(rdlvl_stg1_start_r_reg),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5]_0 ),
        .\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_418),
        .\read_fifo.tail_r_reg[1] (ddr_phy_top0_n_49),
        .\read_fifo.tail_r_reg[1]_0 (ddr_phy_top0_n_70),
        .\read_fifo.tail_r_reg[1]_1 (ddr_phy_top0_n_419),
        .\read_fifo.tail_r_reg[3] (ddr_phy_top0_n_78),
        .refresh_bank_r(\rank_mach0/rank_cntrl[0].rank_cntrl0/refresh_bank_r ),
        .rst_sync_r1_reg(rst_sync_r1_reg),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),
        .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),
        .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),
        .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),
        .rstdiv0_sync_r1_reg_rep__15(rstdiv0_sync_r1_reg_rep__15),
        .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),
        .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0),
        .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1),
        .rstdiv0_sync_r1_reg_rep__24_2(rstdiv0_sync_r1_reg_rep__24_2),
        .rstdiv0_sync_r1_reg_rep__24_3(rstdiv0_sync_r1_reg_rep__24_3),
        .rstdiv0_sync_r1_reg_rep__24_4(rstdiv0_sync_r1_reg_rep__24_4),
        .rstdiv0_sync_r1_reg_rep__3(rstdiv0_sync_r1_reg_rep__3),
        .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),
        .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),
        .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),
        .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .sent_col(sent_col),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst),
        .sys_rst_0(sys_rst_0),
        .sys_rst_1(sys_rst_1),
        .tail_r(tail_r),
        .tempmon_sample_en(tempmon_sample_en),
        .wr_en(wr_en),
        .wr_en_10(wr_en_10),
        .wr_en_11(wr_en_11),
        .wr_en_12(wr_en_12),
        .wr_en_13(wr_en_13),
        .wr_en_14(wr_en_14),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[0]_1 (\wr_ptr_reg[0]_1 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_reg[1]_2 (\wr_ptr_reg[1]_2 ),
        .\wr_ptr_reg[1]_3 (\wr_ptr_reg[1]_3 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] [45:1]),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_1 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3]_0 ),
        .\wr_ptr_timing_reg[3]_1 (\wr_ptr_timing_reg[3]_1 ),
        .\wr_ptr_timing_reg[3]_2 (\wr_ptr_timing_reg[3]_2 ),
        .\wr_ptr_timing_reg[3]_3 (\wr_ptr_timing_reg[3]_3 ),
        .\wr_ptr_timing_reg[3]_4 (\wr_ptr_timing_reg[3]_4 ),
        .\write_buffer.wr_buf_out_data_reg[351] (\write_buffer.wr_buf_out_data_reg[351] ),
        .\write_buffer.wr_buf_out_data_reg[575] (\write_buffer.wr_buf_out_data_reg[575] ));
  mig_7series_0_mig_7series_v2_3_mc mc0
       (.ADDRC({\col_mach0/tail_ns [3],ADDRA,ddr_phy_top0_n_80,\col_mach0/tail_ns [0]}),
        .CLK(CLK),
        .D(mc_data_offset_ns),
        .E(E),
        .Q(Q),
        .S(S),
        .accept_ns(accept_ns),
        .\app_addr_r1_reg[22] (\app_addr_r1_reg[22] ),
        .\app_addr_r1_reg[22]_0 (\app_addr_r1_reg[22]_0 ),
        .\app_addr_r1_reg[22]_1 (\app_addr_r1_reg[22]_1 ),
        .\app_addr_r1_reg[26] (\app_addr_r1_reg[26] ),
        .\app_addr_r1_reg[9] (\app_addr_r1_reg[9] ),
        .\app_cmd_r1_reg[1] (\app_cmd_r1_reg[1] ),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0] (\app_cmd_r2_reg[0] ),
        .\app_cmd_r2_reg[1] (\app_cmd_r2_reg[1] ),
        .app_en_r2(app_en_r2),
        .app_rd_data_end_ns(app_rd_data_end_ns),
        .app_rdy_r_reg(app_rdy_r_reg),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .\cmd_pipe_plus.mc_address_reg[13]_0 (\cmd_pipe_plus.mc_address_reg[13] ),
        .\cmd_pipe_plus.mc_address_reg[13]_1 (\cmd_pipe_plus.mc_address_reg[13]_0 ),
        .\cmd_pipe_plus.mc_address_reg[41]_0 (\cmd_pipe_plus.mc_address_reg[41]_0 ),
        .\cmd_pipe_plus.mc_address_reg[41]_1 (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[8]_0 (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_bank_reg[8]_1 (\cmd_pipe_plus.mc_bank_reg[8]_0 ),
        .col_rd_wr(col_rd_wr),
        .\data_offset_1_i1_reg[0] (mc0_n_149),
        .\data_offset_1_i1_reg[1] (mc0_n_148),
        .\data_offset_1_i1_reg[2] (mc0_n_147),
        .\data_offset_1_i1_reg[3] (mc0_n_144),
        .\data_offset_1_i1_reg[4] (mc0_n_146),
        .\data_offset_1_i1_reg[5] (mc0_n_145),
        .\data_offset_2_i1_reg[0] (mc0_n_155),
        .\data_offset_2_i1_reg[1] (mc0_n_154),
        .\data_offset_2_i1_reg[2] (mc0_n_153),
        .\data_offset_2_i1_reg[3] (mc0_n_150),
        .\data_offset_2_i1_reg[4] (mc0_n_152),
        .\data_offset_2_i1_reg[5] (mc0_n_151),
        .demand_priority_r_reg(demand_priority_r_reg),
        .demand_priority_r_reg_0(demand_priority_r_reg_0),
        .demand_priority_r_reg_1(demand_priority_r_reg_1),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (ddr_phy_top0_n_70),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (ddr_phy_top0_n_69),
        .granted_col_r_reg(mc_data_offset_1_ns),
        .granted_col_r_reg_0(mc_data_offset_2_ns),
        .idle(idle),
        .init_calib_complete_reg_rep(ddr_phy_top0_n_53),
        .init_calib_complete_reg_rep_0(ddr_phy_top0_n_408),
        .init_calib_complete_reg_rep__15(ddr_phy_top0_n_54),
        .init_complete_r1_timing_reg(ddr_phy_top0_n_49),
        .init_complete_r1_timing_reg_0(ddr_phy_top0_n_418),
        .init_complete_r1_timing_reg_1(ddr_phy_top0_n_419),
        .maint_prescaler_r1(\rank_mach0/rank_common0/maint_prescaler_r1 ),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_wrdata_en(mc_wrdata_en),
        .\my_empty_reg[6] ({mc_address[41:28],mc_address[24:0]}),
        .\not_strict_mode.app_rd_data_end_reg ({\not_strict_mode.app_rd_data_end_reg [6],\col_mach0/p_0_in ,\not_strict_mode.app_rd_data_end_reg [5:0]}),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .\not_strict_mode.status_ram.rd_buf_we_r1_reg (\not_strict_mode.status_ram.rd_buf_we_r1_reg ),
        .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),
        .p_106_out(p_106_out),
        .p_145_out(p_145_out),
        .p_28_out(p_28_out),
        .p_67_out(p_67_out),
        .periodic_rd_cntr_r(periodic_rd_cntr_r),
        .\periodic_read_request.periodic_rd_r_lcl_reg (periodic_rd_r),
        .\phy_ctl_wd_i1_reg[17] (mc0_n_143),
        .\phy_ctl_wd_i1_reg[18] (mc0_n_142),
        .\phy_ctl_wd_i1_reg[19] (mc0_n_141),
        .\phy_ctl_wd_i1_reg[20] (mc0_n_138),
        .\phy_ctl_wd_i1_reg[21] (mc0_n_140),
        .\phy_ctl_wd_i1_reg[22] (mc0_n_139),
        .phy_dout({phy_dout[10],phy_dout[8:7],phy_dout[5:4],phy_dout[2]}),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .pointer_we(pointer_we),
        .ram_init_done_r(ram_init_done_r),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (ddr_phy_top0_n_413),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 (ddr_phy_top0_n_420),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] (ddr_phy_top0_n_72),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] (ddr_phy_top0_n_412),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (ddr_phy_top0_n_73),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] (ddr_phy_top0_n_414),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] (ddr_phy_top0_n_75),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (ddr_phy_top0_n_415),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 (ddr_phy_top0_n_421),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] (ddr_phy_top0_n_74),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] (ddr_phy_top0_n_417),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 (ddr_phy_top0_n_422),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14] (ddr_phy_top0_n_76),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16] (ddr_phy_top0_n_416),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] (ddr_phy_top0_n_77),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\read_fifo.fifo_out_data_r_reg[4] (\not_strict_mode.app_rd_data_reg[24] ),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.tail_r_reg[1] (ddr_phy_top0_n_78),
        .\read_fifo.tail_r_reg[3] (tail_r),
        .refresh_bank_r(\rank_mach0/rank_cntrl[0].rank_cntrl0/refresh_bank_r ),
        .req_periodic_rd_r_lcl_reg(periodic_rd_ack_r),
        .row(row),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_1),
        .rstdiv0_sync_r1_reg_rep__20_2(rstdiv0_sync_r1_reg_rep__20_2),
        .rstdiv0_sync_r1_reg_rep__20_3(rstdiv0_sync_r1_reg_rep__20_3),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .sent_col(sent_col),
        .tempmon_sample_en(tempmon_sample_en),
        .was_wr0(was_wr0),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] [0]),
        .\wr_ptr_timing_reg[0]_0 (mc_we_n),
        .\wr_ptr_timing_reg[0]_1 (mc_bank),
        .\write_buffer.wr_buf_out_data_reg[197] (ADDRC),
        .\write_buffer.wr_buf_out_data_reg[389] (\write_buffer.wr_buf_out_data_reg[389] ),
        .\write_buffer.wr_buf_out_data_reg[53] (\write_buffer.wr_buf_out_data_reg[53] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_memc_ui_top_std" *) 
module mig_7series_0_mig_7series_v2_3_memc_ui_top_std
   (bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    bm_end_r1_2,
    app_ref_ack,
    app_zq_ack,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_reset_n,
    out,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \rd_ptr_timing_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \rd_ptr_timing_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,
    \rd_ptr_timing_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    init_complete_r_timing,
    prbs_rdlvl_done_pulse,
    rdlvl_stg1_start_r_reg,
    init_calib_complete,
    app_sr_active,
    E,
    app_wdf_rdy,
    app_rd_data_valid,
    app_rd_data_end,
    po_cnt_dec,
    idelay_tap_limit_r_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec,
    \read_fifo.fifo_out_data_r_reg[5] ,
    Q,
    rst_sync_r1_reg,
    \not_strict_mode.app_rd_data_reg[488] ,
    \not_strict_mode.app_rd_data_reg[496] ,
    \not_strict_mode.app_rd_data_reg[376] ,
    \idelay_tap_cnt_r_reg[0][7][3] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_timing_reg[3] ,
    \my_empty_reg[7] ,
    \wr_ptr_timing_reg[3]_0 ,
    \wr_ptr_timing_reg[0] ,
    \wr_ptr_timing_reg[3]_1 ,
    \wr_ptr_timing_reg[0]_0 ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1]_1 ,
    \wr_ptr_timing_reg[3]_2 ,
    \my_empty_reg[7]_0 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_2 ,
    \wr_ptr_timing_reg[3]_3 ,
    \my_empty_reg[7]_1 ,
    \wr_ptr_reg[0]_1 ,
    \wr_ptr_reg[1]_3 ,
    \wr_ptr_timing_reg[3]_4 ,
    \my_empty_reg[7]_2 ,
    app_rd_data,
    p_0_in1_in,
    \not_strict_mode.app_rd_data_reg[232] ,
    \not_strict_mode.app_rd_data_reg[496]_0 ,
    \not_strict_mode.app_rd_data_reg[376]_0 ,
    phy_dout,
    \wr_ptr_timing_reg[0]_1 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    wr_en,
    wr_en_10,
    wr_en_11,
    wr_en_12,
    wr_en_13,
    wr_en_14,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    CLK,
    rstdiv0_sync_r1_reg_rep__1,
    rstdiv0_sync_r1_reg_rep__0,
    ADDRA,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    A_rst_primitives_reg,
    pll_lock,
    rstdiv0_sync_r1,
    sys_rst_0,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    rstdiv0_sync_r1_reg_rep__4,
    rstdiv0_sync_r1_reg_rep__3,
    rstdiv0_sync_r1_reg_rep__18,
    init_complete_r_timing_reg,
    rstdiv0_sync_r1_reg_rep__24,
    app_en,
    SR,
    rstdiv0_sync_r1_reg_rep__10,
    rstdiv0_sync_r1_reg_rep__2,
    rstdiv0_sync_r1_reg_rep__24_0,
    rstdiv0_sync_r1_reg_rep__13,
    rstdiv0_sync_r1_reg_rep__15,
    rstdiv0_sync_r1_reg_rep__22,
    rstdiv0_sync_r1_reg_rep__19,
    app_wdf_end,
    app_wdf_wren,
    app_ref_req,
    app_zq_req,
    rstdiv0_sync_r1_reg_rep__20,
    app_sr_req,
    rstdiv0_sync_r1_reg_rep__21,
    mem_out,
    sys_rst,
    iodelay_ctrl_rdy,
    sys_rst_1,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    rstdiv0_sync_r1_reg_rep__20_0,
    rstdiv0_sync_r1_reg_rep__20_1,
    rstdiv0_sync_r1_reg_rep__20_2,
    rstdiv0_sync_r1_reg_rep__20_3,
    complex_row0_rd_done1,
    rstdiv0_sync_r1_reg_rep__23,
    rstdiv0_sync_r1_reg_rep,
    app_addr,
    app_cmd,
    app_wdf_data,
    app_wdf_mask,
    rstdiv0_sync_r1_reg_rep__9,
    rstdiv0_sync_r1_reg_rep__7,
    rstdiv0_sync_r1_reg_rep__6,
    SS,
    D,
    rstdiv0_sync_r1_reg_rep__24_1,
    rstdiv0_sync_r1_reg_rep__24_2,
    rstdiv0_sync_r1_reg_rep__24_3,
    \device_temp_r_reg[11] ,
    rstdiv0_sync_r1_reg_rep__16,
    rstdiv0_sync_r1_reg_rep__14,
    rstdiv0_sync_r1_reg_rep__17,
    \rd_ptr_reg_rep[3] ,
    \rd_ptr_reg_rep[3]_0 ,
    \rd_ptr_reg_rep[3]_1 ,
    \rd_ptr_reg_rep[3]_2 ,
    \rd_ptr_reg_rep[3]_3 ,
    \rd_ptr_reg_rep[3]_4 ,
    rstdiv0_sync_r1_reg_rep__12);
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output bm_end_r1_2;
  output app_ref_ack;
  output app_zq_ack;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [1:0]out;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  output [1:0]\rd_ptr_timing_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output init_complete_r_timing;
  output prbs_rdlvl_done_pulse;
  output rdlvl_stg1_start_r_reg;
  output init_calib_complete;
  output app_sr_active;
  output [0:0]E;
  output app_wdf_rdy;
  output app_rd_data_valid;
  output app_rd_data_end;
  output po_cnt_dec;
  output idelay_tap_limit_r_reg;
  output samp_edge_cnt0_en_r;
  output pi_cnt_dec;
  output \read_fifo.fifo_out_data_r_reg[5] ;
  output [65:0]Q;
  output rst_sync_r1_reg;
  output [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  output [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  output [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  output \idelay_tap_cnt_r_reg[0][7][3] ;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_timing_reg[3] ;
  output [3:0]\my_empty_reg[7] ;
  output [3:0]\wr_ptr_timing_reg[3]_0 ;
  output [3:0]\wr_ptr_timing_reg[0] ;
  output [3:0]\wr_ptr_timing_reg[3]_1 ;
  output [3:0]\wr_ptr_timing_reg[0]_0 ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1]_1 ;
  output [3:0]\wr_ptr_timing_reg[3]_2 ;
  output [3:0]\my_empty_reg[7]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_2 ;
  output [3:0]\wr_ptr_timing_reg[3]_3 ;
  output [3:0]\my_empty_reg[7]_1 ;
  output \wr_ptr_reg[0]_1 ;
  output \wr_ptr_reg[1]_3 ;
  output [3:0]\wr_ptr_timing_reg[3]_4 ;
  output [3:0]\my_empty_reg[7]_2 ;
  output [511:0]app_rd_data;
  output p_0_in1_in;
  output \not_strict_mode.app_rd_data_reg[232] ;
  output \not_strict_mode.app_rd_data_reg[496]_0 ;
  output \not_strict_mode.app_rd_data_reg[376]_0 ;
  output [10:0]phy_dout;
  output [45:0]\wr_ptr_timing_reg[0]_1 ;
  output [255:0]\my_empty_reg[7]_3 ;
  output [31:0]\my_empty_reg[7]_4 ;
  output wr_en;
  output wr_en_10;
  output wr_en_11;
  output wr_en_12;
  output wr_en_13;
  output wr_en_14;
  output [1:0]ddr_ck_out;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input CLK;
  input rstdiv0_sync_r1_reg_rep__1;
  input rstdiv0_sync_r1_reg_rep__0;
  input [0:0]ADDRA;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input A_rst_primitives_reg;
  input pll_lock;
  input rstdiv0_sync_r1;
  input sys_rst_0;
  input A_rst_primitives_reg_0;
  input A_rst_primitives_reg_1;
  input A_rst_primitives_reg_2;
  input A_rst_primitives_reg_3;
  input A_rst_primitives_reg_4;
  input A_rst_primitives_reg_5;
  input A_rst_primitives_reg_6;
  input rstdiv0_sync_r1_reg_rep__4;
  input rstdiv0_sync_r1_reg_rep__3;
  input rstdiv0_sync_r1_reg_rep__18;
  input init_complete_r_timing_reg;
  input rstdiv0_sync_r1_reg_rep__24;
  input app_en;
  input [0:0]SR;
  input [1:0]rstdiv0_sync_r1_reg_rep__10;
  input [0:0]rstdiv0_sync_r1_reg_rep__2;
  input rstdiv0_sync_r1_reg_rep__24_0;
  input [0:0]rstdiv0_sync_r1_reg_rep__13;
  input [0:0]rstdiv0_sync_r1_reg_rep__15;
  input rstdiv0_sync_r1_reg_rep__22;
  input rstdiv0_sync_r1_reg_rep__19;
  input app_wdf_end;
  input app_wdf_wren;
  input app_ref_req;
  input app_zq_req;
  input rstdiv0_sync_r1_reg_rep__20;
  input app_sr_req;
  input rstdiv0_sync_r1_reg_rep__21;
  input [63:0]mem_out;
  input sys_rst;
  input [0:0]iodelay_ctrl_rdy;
  input sys_rst_1;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  input [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input rstdiv0_sync_r1_reg_rep__20_0;
  input rstdiv0_sync_r1_reg_rep__20_1;
  input rstdiv0_sync_r1_reg_rep__20_2;
  input rstdiv0_sync_r1_reg_rep__20_3;
  input complex_row0_rd_done1;
  input rstdiv0_sync_r1_reg_rep__23;
  input rstdiv0_sync_r1_reg_rep;
  input [26:0]app_addr;
  input [1:0]app_cmd;
  input [511:0]app_wdf_data;
  input [63:0]app_wdf_mask;
  input [0:0]rstdiv0_sync_r1_reg_rep__9;
  input [1:0]rstdiv0_sync_r1_reg_rep__7;
  input [0:0]rstdiv0_sync_r1_reg_rep__6;
  input [0:0]SS;
  input [0:0]D;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  input [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  input [11:0]\device_temp_r_reg[11] ;
  input [0:0]rstdiv0_sync_r1_reg_rep__16;
  input [0:0]rstdiv0_sync_r1_reg_rep__14;
  input [0:0]rstdiv0_sync_r1_reg_rep__17;
  input [79:0]\rd_ptr_reg_rep[3] ;
  input [41:0]\rd_ptr_reg_rep[3]_0 ;
  input [79:0]\rd_ptr_reg_rep[3]_1 ;
  input [79:0]\rd_ptr_reg_rep[3]_2 ;
  input [79:0]\rd_ptr_reg_rep[3]_3 ;
  input [79:0]\rd_ptr_reg_rep[3]_4 ;
  input [0:0]rstdiv0_sync_r1_reg_rep__12;

  wire [0:0]ADDRA;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire CLK;
  wire [0:0]D;
  wire [0:0]E;
  wire [65:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire accept_ns;
  wire [26:0]app_addr;
  wire [1:0]app_cmd;
  wire app_en;
  wire [511:0]app_rd_data;
  wire app_rd_data_end;
  wire [511:0]app_rd_data_ns;
  wire app_rd_data_valid;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire [2:0]bank;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_2;
  wire [9:0]col;
  wire complex_row0_rd_done1;
  wire [4:0]data_buf_addr;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire [351:0]\ddr_phy_top0/mux_wrdata ;
  wire [11:0]\device_temp_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire freq_refclk;
  wire \idelay_tap_cnt_r_reg[0][7][3] ;
  wire idelay_tap_limit_r_reg;
  wire init_calib_complete;
  wire init_complete_r_timing;
  wire init_complete_r_timing_reg;
  wire [0:0]iodelay_ctrl_rdy;
  wire \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r ;
  wire \mc0/bank_mach0/bank_common0/was_wr0 ;
  wire \mc0/bank_mach0/p_106_out ;
  wire [2:0]\mc0/bank_mach0/p_108_out ;
  wire [13:12]\mc0/bank_mach0/p_112_out ;
  wire \mc0/bank_mach0/p_145_out ;
  wire [2:0]\mc0/bank_mach0/p_147_out ;
  wire [13:12]\mc0/bank_mach0/p_151_out ;
  wire \mc0/bank_mach0/p_28_out ;
  wire [2:0]\mc0/bank_mach0/p_30_out ;
  wire [13:12]\mc0/bank_mach0/p_34_out ;
  wire \mc0/bank_mach0/p_67_out ;
  wire [2:0]\mc0/bank_mach0/p_69_out ;
  wire [13:12]\mc0/bank_mach0/p_73_out ;
  wire \mc0/periodic_rd_ack_r ;
  wire \mc0/periodic_rd_r ;
  wire mem_intfc0_n_166;
  wire mem_intfc0_n_167;
  wire mem_intfc0_n_168;
  wire mem_intfc0_n_169;
  wire mem_intfc0_n_1692;
  wire mem_intfc0_n_170;
  wire mem_intfc0_n_1706;
  wire mem_intfc0_n_1707;
  wire mem_intfc0_n_1708;
  wire mem_intfc0_n_1709;
  wire mem_intfc0_n_171;
  wire mem_intfc0_n_1710;
  wire mem_intfc0_n_1711;
  wire mem_intfc0_n_1712;
  wire mem_intfc0_n_1713;
  wire mem_intfc0_n_172;
  wire mem_intfc0_n_173;
  wire mem_intfc0_n_174;
  wire mem_intfc0_n_175;
  wire mem_intfc0_n_176;
  wire mem_intfc0_n_177;
  wire mem_intfc0_n_178;
  wire mem_intfc0_n_179;
  wire mem_intfc0_n_180;
  wire mem_intfc0_n_181;
  wire mem_intfc0_n_182;
  wire mem_intfc0_n_183;
  wire mem_intfc0_n_184;
  wire mem_intfc0_n_185;
  wire mem_intfc0_n_186;
  wire mem_intfc0_n_187;
  wire mem_intfc0_n_188;
  wire mem_intfc0_n_189;
  wire mem_intfc0_n_190;
  wire mem_intfc0_n_191;
  wire mem_intfc0_n_192;
  wire mem_intfc0_n_193;
  wire mem_intfc0_n_194;
  wire mem_intfc0_n_195;
  wire mem_intfc0_n_197;
  wire mem_intfc0_n_198;
  wire mem_intfc0_n_199;
  wire mem_intfc0_n_200;
  wire mem_intfc0_n_201;
  wire mem_intfc0_n_268;
  wire mem_intfc0_n_269;
  wire mem_intfc0_n_270;
  wire mem_intfc0_n_271;
  wire mem_intfc0_n_272;
  wire mem_intfc0_n_273;
  wire mem_intfc0_n_274;
  wire mem_intfc0_n_343;
  wire mem_intfc0_n_344;
  wire mem_intfc0_n_345;
  wire mem_intfc0_n_346;
  wire mem_intfc0_n_347;
  wire mem_intfc0_n_348;
  wire mem_intfc0_n_349;
  wire mem_intfc0_n_416;
  wire mem_intfc0_n_417;
  wire mem_intfc0_n_427;
  wire mem_intfc0_n_428;
  wire mem_intfc0_n_429;
  wire mem_intfc0_n_430;
  wire mem_intfc0_n_431;
  wire mem_intfc0_n_432;
  wire mem_intfc0_n_433;
  wire mem_intfc0_n_434;
  wire mem_intfc0_n_435;
  wire mem_intfc0_n_436;
  wire mem_intfc0_n_437;
  wire mem_intfc0_n_438;
  wire mem_intfc0_n_439;
  wire mem_intfc0_n_440;
  wire mem_intfc0_n_441;
  wire mem_intfc0_n_442;
  wire mem_intfc0_n_443;
  wire mem_intfc0_n_444;
  wire mem_intfc0_n_445;
  wire mem_intfc0_n_446;
  wire mem_intfc0_n_447;
  wire mem_intfc0_n_448;
  wire mem_intfc0_n_449;
  wire mem_intfc0_n_450;
  wire mem_intfc0_n_451;
  wire mem_intfc0_n_452;
  wire mem_intfc0_n_453;
  wire mem_intfc0_n_454;
  wire mem_intfc0_n_455;
  wire mem_intfc0_n_456;
  wire mem_intfc0_n_457;
  wire mem_intfc0_n_458;
  wire mem_intfc0_n_459;
  wire mem_intfc0_n_460;
  wire mem_intfc0_n_461;
  wire mem_intfc0_n_462;
  wire mem_intfc0_n_463;
  wire mem_intfc0_n_464;
  wire mem_intfc0_n_465;
  wire mem_intfc0_n_466;
  wire mem_intfc0_n_467;
  wire mem_intfc0_n_468;
  wire mem_intfc0_n_469;
  wire mem_intfc0_n_470;
  wire mem_intfc0_n_471;
  wire mem_intfc0_n_472;
  wire mem_intfc0_n_473;
  wire mem_intfc0_n_474;
  wire mem_intfc0_n_475;
  wire mem_intfc0_n_476;
  wire mem_intfc0_n_477;
  wire mem_intfc0_n_478;
  wire mem_intfc0_n_479;
  wire mem_intfc0_n_480;
  wire mem_intfc0_n_481;
  wire mem_intfc0_n_482;
  wire mem_intfc0_n_483;
  wire mem_intfc0_n_484;
  wire mem_intfc0_n_485;
  wire mem_intfc0_n_486;
  wire mem_intfc0_n_487;
  wire mem_intfc0_n_488;
  wire mem_intfc0_n_489;
  wire mem_intfc0_n_490;
  wire mem_intfc0_n_491;
  wire mem_intfc0_n_492;
  wire mem_intfc0_n_493;
  wire mem_intfc0_n_494;
  wire mem_intfc0_n_495;
  wire mem_intfc0_n_496;
  wire mem_intfc0_n_497;
  wire mem_intfc0_n_498;
  wire mem_intfc0_n_499;
  wire mem_intfc0_n_500;
  wire mem_intfc0_n_501;
  wire mem_intfc0_n_502;
  wire mem_intfc0_n_503;
  wire mem_intfc0_n_504;
  wire mem_intfc0_n_505;
  wire mem_intfc0_n_506;
  wire mem_intfc0_n_507;
  wire mem_intfc0_n_508;
  wire mem_intfc0_n_509;
  wire mem_intfc0_n_510;
  wire mem_intfc0_n_511;
  wire mem_intfc0_n_512;
  wire mem_intfc0_n_513;
  wire mem_intfc0_n_514;
  wire mem_intfc0_n_515;
  wire mem_intfc0_n_516;
  wire mem_intfc0_n_517;
  wire mem_intfc0_n_518;
  wire mem_intfc0_n_519;
  wire mem_intfc0_n_520;
  wire mem_intfc0_n_521;
  wire mem_intfc0_n_522;
  wire mem_intfc0_n_523;
  wire mem_intfc0_n_524;
  wire mem_intfc0_n_525;
  wire mem_intfc0_n_526;
  wire mem_intfc0_n_527;
  wire mem_intfc0_n_528;
  wire mem_intfc0_n_529;
  wire mem_intfc0_n_530;
  wire mem_intfc0_n_531;
  wire mem_intfc0_n_532;
  wire mem_intfc0_n_533;
  wire mem_intfc0_n_534;
  wire mem_intfc0_n_535;
  wire mem_intfc0_n_536;
  wire mem_intfc0_n_537;
  wire mem_intfc0_n_538;
  wire mem_intfc0_n_539;
  wire mem_intfc0_n_540;
  wire mem_intfc0_n_541;
  wire mem_intfc0_n_542;
  wire mem_intfc0_n_543;
  wire mem_intfc0_n_544;
  wire mem_intfc0_n_545;
  wire mem_intfc0_n_546;
  wire mem_intfc0_n_547;
  wire mem_intfc0_n_548;
  wire mem_intfc0_n_549;
  wire mem_intfc0_n_550;
  wire mem_intfc0_n_551;
  wire mem_intfc0_n_552;
  wire mem_intfc0_n_553;
  wire mem_intfc0_n_554;
  wire mem_intfc0_n_555;
  wire mem_intfc0_n_556;
  wire mem_intfc0_n_557;
  wire mem_intfc0_n_558;
  wire mem_intfc0_n_559;
  wire mem_intfc0_n_560;
  wire mem_intfc0_n_561;
  wire mem_intfc0_n_562;
  wire mem_intfc0_n_563;
  wire mem_intfc0_n_564;
  wire mem_intfc0_n_565;
  wire mem_intfc0_n_566;
  wire mem_intfc0_n_567;
  wire mem_intfc0_n_568;
  wire mem_intfc0_n_569;
  wire mem_intfc0_n_570;
  wire mem_intfc0_n_571;
  wire mem_intfc0_n_572;
  wire mem_intfc0_n_573;
  wire mem_intfc0_n_574;
  wire mem_intfc0_n_575;
  wire mem_intfc0_n_576;
  wire mem_intfc0_n_577;
  wire mem_intfc0_n_578;
  wire mem_intfc0_n_579;
  wire mem_intfc0_n_580;
  wire mem_intfc0_n_581;
  wire mem_intfc0_n_582;
  wire mem_intfc0_n_583;
  wire mem_intfc0_n_584;
  wire mem_intfc0_n_585;
  wire mem_intfc0_n_586;
  wire mem_intfc0_n_587;
  wire mem_intfc0_n_588;
  wire mem_intfc0_n_589;
  wire mem_intfc0_n_590;
  wire mem_intfc0_n_591;
  wire mem_intfc0_n_592;
  wire mem_intfc0_n_593;
  wire mem_intfc0_n_594;
  wire mem_intfc0_n_595;
  wire mem_intfc0_n_596;
  wire mem_intfc0_n_597;
  wire mem_intfc0_n_598;
  wire mem_intfc0_n_599;
  wire mem_intfc0_n_600;
  wire mem_intfc0_n_601;
  wire mem_intfc0_n_602;
  wire mem_intfc0_n_603;
  wire mem_intfc0_n_604;
  wire mem_intfc0_n_605;
  wire mem_intfc0_n_606;
  wire mem_intfc0_n_607;
  wire mem_intfc0_n_608;
  wire mem_intfc0_n_609;
  wire mem_intfc0_n_61;
  wire mem_intfc0_n_610;
  wire mem_intfc0_n_611;
  wire mem_intfc0_n_612;
  wire mem_intfc0_n_613;
  wire mem_intfc0_n_614;
  wire mem_intfc0_n_615;
  wire mem_intfc0_n_616;
  wire mem_intfc0_n_617;
  wire mem_intfc0_n_618;
  wire mem_intfc0_n_619;
  wire mem_intfc0_n_62;
  wire mem_intfc0_n_620;
  wire mem_intfc0_n_621;
  wire mem_intfc0_n_622;
  wire mem_intfc0_n_623;
  wire mem_intfc0_n_624;
  wire mem_intfc0_n_625;
  wire mem_intfc0_n_626;
  wire mem_intfc0_n_627;
  wire mem_intfc0_n_628;
  wire mem_intfc0_n_629;
  wire mem_intfc0_n_63;
  wire mem_intfc0_n_630;
  wire mem_intfc0_n_631;
  wire mem_intfc0_n_632;
  wire mem_intfc0_n_633;
  wire mem_intfc0_n_634;
  wire mem_intfc0_n_635;
  wire mem_intfc0_n_636;
  wire mem_intfc0_n_637;
  wire mem_intfc0_n_638;
  wire mem_intfc0_n_639;
  wire mem_intfc0_n_64;
  wire mem_intfc0_n_640;
  wire mem_intfc0_n_641;
  wire mem_intfc0_n_642;
  wire mem_intfc0_n_643;
  wire mem_intfc0_n_644;
  wire mem_intfc0_n_645;
  wire mem_intfc0_n_646;
  wire mem_intfc0_n_647;
  wire mem_intfc0_n_648;
  wire mem_intfc0_n_649;
  wire mem_intfc0_n_65;
  wire mem_intfc0_n_650;
  wire mem_intfc0_n_651;
  wire mem_intfc0_n_652;
  wire mem_intfc0_n_653;
  wire mem_intfc0_n_654;
  wire mem_intfc0_n_655;
  wire mem_intfc0_n_656;
  wire mem_intfc0_n_657;
  wire mem_intfc0_n_658;
  wire mem_intfc0_n_659;
  wire mem_intfc0_n_66;
  wire mem_intfc0_n_660;
  wire mem_intfc0_n_661;
  wire mem_intfc0_n_662;
  wire mem_intfc0_n_663;
  wire mem_intfc0_n_664;
  wire mem_intfc0_n_665;
  wire mem_intfc0_n_666;
  wire mem_intfc0_n_667;
  wire mem_intfc0_n_668;
  wire mem_intfc0_n_669;
  wire mem_intfc0_n_67;
  wire mem_intfc0_n_670;
  wire mem_intfc0_n_671;
  wire mem_intfc0_n_672;
  wire mem_intfc0_n_673;
  wire mem_intfc0_n_674;
  wire mem_intfc0_n_675;
  wire mem_intfc0_n_676;
  wire mem_intfc0_n_677;
  wire mem_intfc0_n_678;
  wire mem_intfc0_n_679;
  wire mem_intfc0_n_68;
  wire mem_intfc0_n_680;
  wire mem_intfc0_n_681;
  wire mem_intfc0_n_682;
  wire mem_intfc0_n_683;
  wire mem_intfc0_n_684;
  wire mem_intfc0_n_685;
  wire mem_intfc0_n_686;
  wire mem_intfc0_n_687;
  wire mem_intfc0_n_688;
  wire mem_intfc0_n_689;
  wire mem_intfc0_n_69;
  wire mem_intfc0_n_690;
  wire mem_intfc0_n_691;
  wire mem_intfc0_n_692;
  wire mem_intfc0_n_693;
  wire mem_intfc0_n_694;
  wire mem_intfc0_n_695;
  wire mem_intfc0_n_696;
  wire mem_intfc0_n_697;
  wire mem_intfc0_n_698;
  wire mem_intfc0_n_699;
  wire mem_intfc0_n_700;
  wire mem_intfc0_n_701;
  wire mem_intfc0_n_702;
  wire mem_intfc0_n_703;
  wire mem_intfc0_n_704;
  wire mem_intfc0_n_705;
  wire mem_intfc0_n_706;
  wire mem_intfc0_n_707;
  wire mem_intfc0_n_708;
  wire mem_intfc0_n_709;
  wire mem_intfc0_n_710;
  wire mem_intfc0_n_711;
  wire mem_intfc0_n_712;
  wire mem_intfc0_n_713;
  wire mem_intfc0_n_714;
  wire mem_intfc0_n_715;
  wire mem_intfc0_n_716;
  wire mem_intfc0_n_717;
  wire mem_intfc0_n_718;
  wire mem_intfc0_n_719;
  wire mem_intfc0_n_720;
  wire mem_intfc0_n_721;
  wire mem_intfc0_n_722;
  wire mem_intfc0_n_723;
  wire mem_intfc0_n_724;
  wire mem_intfc0_n_725;
  wire mem_intfc0_n_726;
  wire mem_intfc0_n_727;
  wire mem_intfc0_n_728;
  wire mem_intfc0_n_729;
  wire mem_intfc0_n_730;
  wire mem_intfc0_n_731;
  wire mem_intfc0_n_732;
  wire mem_intfc0_n_733;
  wire mem_intfc0_n_734;
  wire mem_intfc0_n_735;
  wire mem_intfc0_n_736;
  wire mem_intfc0_n_737;
  wire mem_intfc0_n_738;
  wire mem_intfc0_n_739;
  wire mem_intfc0_n_740;
  wire mem_intfc0_n_741;
  wire mem_intfc0_n_742;
  wire mem_intfc0_n_743;
  wire mem_intfc0_n_744;
  wire mem_intfc0_n_745;
  wire mem_intfc0_n_746;
  wire mem_intfc0_n_747;
  wire mem_intfc0_n_748;
  wire mem_intfc0_n_749;
  wire mem_intfc0_n_750;
  wire mem_intfc0_n_751;
  wire mem_intfc0_n_752;
  wire mem_intfc0_n_753;
  wire mem_intfc0_n_754;
  wire mem_intfc0_n_755;
  wire mem_intfc0_n_756;
  wire mem_intfc0_n_757;
  wire mem_intfc0_n_758;
  wire mem_intfc0_n_759;
  wire mem_intfc0_n_760;
  wire mem_intfc0_n_761;
  wire mem_intfc0_n_762;
  wire mem_intfc0_n_763;
  wire mem_intfc0_n_764;
  wire mem_intfc0_n_765;
  wire mem_intfc0_n_766;
  wire mem_intfc0_n_767;
  wire mem_intfc0_n_768;
  wire mem_intfc0_n_769;
  wire mem_intfc0_n_770;
  wire mem_intfc0_n_771;
  wire mem_intfc0_n_772;
  wire mem_intfc0_n_773;
  wire mem_intfc0_n_774;
  wire mem_intfc0_n_775;
  wire mem_intfc0_n_776;
  wire mem_intfc0_n_777;
  wire mem_intfc0_n_778;
  wire mem_intfc0_n_779;
  wire mem_intfc0_n_78;
  wire mem_intfc0_n_780;
  wire mem_intfc0_n_781;
  wire mem_intfc0_n_782;
  wire mem_intfc0_n_783;
  wire mem_intfc0_n_784;
  wire mem_intfc0_n_785;
  wire mem_intfc0_n_786;
  wire mem_intfc0_n_787;
  wire mem_intfc0_n_788;
  wire mem_intfc0_n_789;
  wire mem_intfc0_n_79;
  wire mem_intfc0_n_790;
  wire mem_intfc0_n_791;
  wire mem_intfc0_n_792;
  wire mem_intfc0_n_793;
  wire mem_intfc0_n_794;
  wire mem_intfc0_n_795;
  wire mem_intfc0_n_796;
  wire mem_intfc0_n_797;
  wire mem_intfc0_n_798;
  wire mem_intfc0_n_799;
  wire mem_intfc0_n_80;
  wire mem_intfc0_n_800;
  wire mem_intfc0_n_801;
  wire mem_intfc0_n_802;
  wire mem_intfc0_n_803;
  wire mem_intfc0_n_804;
  wire mem_intfc0_n_805;
  wire mem_intfc0_n_806;
  wire mem_intfc0_n_807;
  wire mem_intfc0_n_808;
  wire mem_intfc0_n_809;
  wire mem_intfc0_n_81;
  wire mem_intfc0_n_810;
  wire mem_intfc0_n_811;
  wire mem_intfc0_n_812;
  wire mem_intfc0_n_813;
  wire mem_intfc0_n_814;
  wire mem_intfc0_n_815;
  wire mem_intfc0_n_816;
  wire mem_intfc0_n_817;
  wire mem_intfc0_n_818;
  wire mem_intfc0_n_819;
  wire mem_intfc0_n_820;
  wire mem_intfc0_n_821;
  wire mem_intfc0_n_822;
  wire mem_intfc0_n_823;
  wire mem_intfc0_n_824;
  wire mem_intfc0_n_825;
  wire mem_intfc0_n_826;
  wire mem_intfc0_n_827;
  wire mem_intfc0_n_828;
  wire mem_intfc0_n_829;
  wire mem_intfc0_n_830;
  wire mem_intfc0_n_831;
  wire mem_intfc0_n_832;
  wire mem_intfc0_n_833;
  wire mem_intfc0_n_834;
  wire mem_intfc0_n_835;
  wire mem_intfc0_n_836;
  wire mem_intfc0_n_837;
  wire mem_intfc0_n_838;
  wire mem_intfc0_n_839;
  wire mem_intfc0_n_840;
  wire mem_intfc0_n_841;
  wire mem_intfc0_n_842;
  wire mem_intfc0_n_843;
  wire mem_intfc0_n_844;
  wire mem_intfc0_n_845;
  wire mem_intfc0_n_846;
  wire mem_intfc0_n_847;
  wire mem_intfc0_n_848;
  wire mem_intfc0_n_849;
  wire mem_intfc0_n_850;
  wire mem_intfc0_n_851;
  wire mem_intfc0_n_852;
  wire mem_intfc0_n_853;
  wire mem_intfc0_n_854;
  wire mem_intfc0_n_855;
  wire mem_intfc0_n_856;
  wire mem_intfc0_n_857;
  wire mem_intfc0_n_858;
  wire mem_intfc0_n_859;
  wire mem_intfc0_n_860;
  wire mem_intfc0_n_861;
  wire mem_intfc0_n_862;
  wire mem_intfc0_n_863;
  wire mem_intfc0_n_864;
  wire mem_intfc0_n_865;
  wire mem_intfc0_n_866;
  wire mem_intfc0_n_867;
  wire mem_intfc0_n_868;
  wire mem_intfc0_n_869;
  wire mem_intfc0_n_870;
  wire mem_intfc0_n_871;
  wire mem_intfc0_n_872;
  wire mem_intfc0_n_873;
  wire mem_intfc0_n_874;
  wire mem_intfc0_n_875;
  wire mem_intfc0_n_876;
  wire mem_intfc0_n_877;
  wire mem_intfc0_n_878;
  wire mem_intfc0_n_879;
  wire mem_intfc0_n_880;
  wire mem_intfc0_n_881;
  wire mem_intfc0_n_882;
  wire mem_intfc0_n_95;
  wire mem_intfc0_n_96;
  wire mem_intfc0_n_97;
  wire mem_intfc0_n_98;
  wire mem_intfc0_n_99;
  wire [63:0]mem_out;
  wire mem_refclk;
  wire [3:0]\my_empty_reg[7] ;
  wire [3:0]\my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_2 ;
  wire [255:0]\my_empty_reg[7]_3 ;
  wire [31:0]\my_empty_reg[7]_4 ;
  wire \not_strict_mode.app_rd_data_reg[232] ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[376] ;
  wire \not_strict_mode.app_rd_data_reg[376]_0 ;
  wire [65:0]\not_strict_mode.app_rd_data_reg[488] ;
  wire [67:0]\not_strict_mode.app_rd_data_reg[496] ;
  wire \not_strict_mode.app_rd_data_reg[496]_0 ;
  wire [1:0]out;
  wire p_0_in1_in;
  wire [10:0]phy_dout;
  wire pi_cnt_dec;
  wire pll_lock;
  wire po_cnt_dec;
  wire prbs_rdlvl_done_pulse;
  wire [3:3]ram_init_addr;
  wire ram_init_done_r;
  wire [4:0]rd_data_addr;
  wire rd_data_end;
  wire rd_data_offset;
  wire [79:0]\rd_ptr_reg_rep[3] ;
  wire [41:0]\rd_ptr_reg_rep[3]_0 ;
  wire [79:0]\rd_ptr_reg_rep[3]_1 ;
  wire [79:0]\rd_ptr_reg_rep[3]_2 ;
  wire [79:0]\rd_ptr_reg_rep[3]_3 ;
  wire [79:0]\rd_ptr_reg_rep[3]_4 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rd_ptr_timing_reg[1]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1]_1 ;
  wire rdlvl_stg1_start_r_reg;
  wire \read_fifo.fifo_out_data_r_reg[5] ;
  wire reset_reg_n_0;
  wire [13:0]row;
  wire rst_sync_r1_reg;
  wire rstdiv0_sync_r1;
  wire rstdiv0_sync_r1_reg_rep;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire [1:0]rstdiv0_sync_r1_reg_rep__10;
  wire [0:0]rstdiv0_sync_r1_reg_rep__12;
  wire [0:0]rstdiv0_sync_r1_reg_rep__13;
  wire [0:0]rstdiv0_sync_r1_reg_rep__14;
  wire [0:0]rstdiv0_sync_r1_reg_rep__15;
  wire [0:0]rstdiv0_sync_r1_reg_rep__16;
  wire [0:0]rstdiv0_sync_r1_reg_rep__17;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire [0:0]rstdiv0_sync_r1_reg_rep__2;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_1;
  wire rstdiv0_sync_r1_reg_rep__20_2;
  wire rstdiv0_sync_r1_reg_rep__20_3;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__22;
  wire rstdiv0_sync_r1_reg_rep__23;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire rstdiv0_sync_r1_reg_rep__24_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_1;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_2;
  wire [0:0]rstdiv0_sync_r1_reg_rep__24_3;
  wire rstdiv0_sync_r1_reg_rep__3;
  wire rstdiv0_sync_r1_reg_rep__4;
  wire [0:0]rstdiv0_sync_r1_reg_rep__6;
  wire [1:0]rstdiv0_sync_r1_reg_rep__7;
  wire [0:0]rstdiv0_sync_r1_reg_rep__9;
  wire samp_edge_cnt0_en_r;
  wire sync_pulse;
  wire sys_rst;
  wire sys_rst_0;
  wire sys_rst_1;
  wire u_ui_top_n_0;
  wire u_ui_top_n_520;
  wire u_ui_top_n_523;
  wire u_ui_top_n_528;
  wire u_ui_top_n_529;
  wire u_ui_top_n_544;
  wire u_ui_top_n_545;
  wire u_ui_top_n_546;
  wire [1:1]\ui_cmd0/app_cmd_r1 ;
  wire [1:1]\ui_cmd0/app_cmd_r2 ;
  wire \ui_cmd0/app_en_r2 ;
  wire \ui_rd_data0/app_rd_data_end_ns ;
  wire [1:0]\ui_rd_data0/p_0_out ;
  wire [1:0]\ui_rd_data0/p_100_out ;
  wire [1:0]\ui_rd_data0/p_101_out ;
  wire [1:0]\ui_rd_data0/p_102_out ;
  wire [1:0]\ui_rd_data0/p_103_out ;
  wire [1:0]\ui_rd_data0/p_104_out ;
  wire [1:0]\ui_rd_data0/p_105_out ;
  wire [1:0]\ui_rd_data0/p_106_out ;
  wire [1:0]\ui_rd_data0/p_107_out ;
  wire [1:0]\ui_rd_data0/p_108_out ;
  wire [1:0]\ui_rd_data0/p_109_out ;
  wire [1:0]\ui_rd_data0/p_10_out ;
  wire [1:0]\ui_rd_data0/p_110_out ;
  wire [1:0]\ui_rd_data0/p_111_out ;
  wire [1:0]\ui_rd_data0/p_112_out ;
  wire [1:0]\ui_rd_data0/p_113_out ;
  wire [1:0]\ui_rd_data0/p_114_out ;
  wire [1:0]\ui_rd_data0/p_115_out ;
  wire [1:0]\ui_rd_data0/p_116_out ;
  wire [1:0]\ui_rd_data0/p_117_out ;
  wire [1:0]\ui_rd_data0/p_118_out ;
  wire [1:0]\ui_rd_data0/p_119_out ;
  wire [1:0]\ui_rd_data0/p_11_out ;
  wire [1:0]\ui_rd_data0/p_120_out ;
  wire [1:0]\ui_rd_data0/p_121_out ;
  wire [1:0]\ui_rd_data0/p_122_out ;
  wire [1:0]\ui_rd_data0/p_123_out ;
  wire [1:0]\ui_rd_data0/p_124_out ;
  wire [1:0]\ui_rd_data0/p_125_out ;
  wire [1:0]\ui_rd_data0/p_126_out ;
  wire [1:0]\ui_rd_data0/p_127_out ;
  wire [1:0]\ui_rd_data0/p_128_out ;
  wire [1:0]\ui_rd_data0/p_129_out ;
  wire [1:0]\ui_rd_data0/p_12_out ;
  wire [1:0]\ui_rd_data0/p_130_out ;
  wire [1:0]\ui_rd_data0/p_131_out ;
  wire [1:0]\ui_rd_data0/p_132_out ;
  wire [1:0]\ui_rd_data0/p_133_out ;
  wire [1:0]\ui_rd_data0/p_134_out ;
  wire [1:0]\ui_rd_data0/p_135_out ;
  wire [1:0]\ui_rd_data0/p_136_out ;
  wire [1:0]\ui_rd_data0/p_137_out ;
  wire [1:0]\ui_rd_data0/p_138_out ;
  wire [1:0]\ui_rd_data0/p_139_out ;
  wire [1:0]\ui_rd_data0/p_13_out ;
  wire [1:0]\ui_rd_data0/p_140_out ;
  wire [1:0]\ui_rd_data0/p_141_out ;
  wire [1:0]\ui_rd_data0/p_142_out ;
  wire [1:0]\ui_rd_data0/p_143_out ;
  wire [1:0]\ui_rd_data0/p_144_out ;
  wire [1:0]\ui_rd_data0/p_145_out ;
  wire [1:0]\ui_rd_data0/p_146_out ;
  wire [1:0]\ui_rd_data0/p_147_out ;
  wire [1:0]\ui_rd_data0/p_148_out ;
  wire [1:0]\ui_rd_data0/p_149_out ;
  wire [1:0]\ui_rd_data0/p_14_out ;
  wire [1:0]\ui_rd_data0/p_150_out ;
  wire [1:0]\ui_rd_data0/p_151_out ;
  wire [1:0]\ui_rd_data0/p_152_out ;
  wire [1:0]\ui_rd_data0/p_153_out ;
  wire [1:0]\ui_rd_data0/p_154_out ;
  wire [1:0]\ui_rd_data0/p_155_out ;
  wire [1:0]\ui_rd_data0/p_156_out ;
  wire [1:0]\ui_rd_data0/p_157_out ;
  wire [1:0]\ui_rd_data0/p_158_out ;
  wire [1:0]\ui_rd_data0/p_159_out ;
  wire [1:0]\ui_rd_data0/p_15_out ;
  wire [1:0]\ui_rd_data0/p_160_out ;
  wire [1:0]\ui_rd_data0/p_161_out ;
  wire [1:0]\ui_rd_data0/p_162_out ;
  wire [1:0]\ui_rd_data0/p_163_out ;
  wire [1:0]\ui_rd_data0/p_164_out ;
  wire [1:0]\ui_rd_data0/p_165_out ;
  wire [1:0]\ui_rd_data0/p_166_out ;
  wire [1:0]\ui_rd_data0/p_167_out ;
  wire [1:0]\ui_rd_data0/p_168_out ;
  wire [1:0]\ui_rd_data0/p_169_out ;
  wire [1:0]\ui_rd_data0/p_16_out ;
  wire [1:0]\ui_rd_data0/p_170_out ;
  wire [1:0]\ui_rd_data0/p_171_out ;
  wire [1:0]\ui_rd_data0/p_172_out ;
  wire [1:0]\ui_rd_data0/p_173_out ;
  wire [1:0]\ui_rd_data0/p_174_out ;
  wire [1:0]\ui_rd_data0/p_175_out ;
  wire [1:0]\ui_rd_data0/p_176_out ;
  wire [1:0]\ui_rd_data0/p_177_out ;
  wire [1:0]\ui_rd_data0/p_178_out ;
  wire [1:0]\ui_rd_data0/p_179_out ;
  wire [1:0]\ui_rd_data0/p_17_out ;
  wire [1:0]\ui_rd_data0/p_180_out ;
  wire [1:0]\ui_rd_data0/p_181_out ;
  wire [1:0]\ui_rd_data0/p_182_out ;
  wire [1:0]\ui_rd_data0/p_183_out ;
  wire [1:0]\ui_rd_data0/p_184_out ;
  wire [1:0]\ui_rd_data0/p_185_out ;
  wire [1:0]\ui_rd_data0/p_186_out ;
  wire [1:0]\ui_rd_data0/p_187_out ;
  wire [1:0]\ui_rd_data0/p_188_out ;
  wire [1:0]\ui_rd_data0/p_189_out ;
  wire [1:0]\ui_rd_data0/p_18_out ;
  wire [1:0]\ui_rd_data0/p_190_out ;
  wire [1:0]\ui_rd_data0/p_191_out ;
  wire [1:0]\ui_rd_data0/p_192_out ;
  wire [1:0]\ui_rd_data0/p_193_out ;
  wire [1:0]\ui_rd_data0/p_194_out ;
  wire [1:0]\ui_rd_data0/p_195_out ;
  wire [1:0]\ui_rd_data0/p_196_out ;
  wire [1:0]\ui_rd_data0/p_197_out ;
  wire [1:0]\ui_rd_data0/p_198_out ;
  wire [1:0]\ui_rd_data0/p_199_out ;
  wire [1:0]\ui_rd_data0/p_19_out ;
  wire [1:0]\ui_rd_data0/p_200_out ;
  wire [1:0]\ui_rd_data0/p_201_out ;
  wire [1:0]\ui_rd_data0/p_202_out ;
  wire [1:0]\ui_rd_data0/p_203_out ;
  wire [1:0]\ui_rd_data0/p_204_out ;
  wire [1:0]\ui_rd_data0/p_205_out ;
  wire [1:0]\ui_rd_data0/p_206_out ;
  wire [1:0]\ui_rd_data0/p_207_out ;
  wire [1:0]\ui_rd_data0/p_208_out ;
  wire [1:0]\ui_rd_data0/p_209_out ;
  wire [1:0]\ui_rd_data0/p_20_out ;
  wire [1:0]\ui_rd_data0/p_210_out ;
  wire [1:0]\ui_rd_data0/p_211_out ;
  wire [1:0]\ui_rd_data0/p_212_out ;
  wire [1:0]\ui_rd_data0/p_213_out ;
  wire [1:0]\ui_rd_data0/p_214_out ;
  wire [1:0]\ui_rd_data0/p_215_out ;
  wire [1:0]\ui_rd_data0/p_216_out ;
  wire [1:0]\ui_rd_data0/p_217_out ;
  wire [1:0]\ui_rd_data0/p_218_out ;
  wire [1:0]\ui_rd_data0/p_219_out ;
  wire [1:0]\ui_rd_data0/p_21_out ;
  wire [1:0]\ui_rd_data0/p_220_out ;
  wire [1:0]\ui_rd_data0/p_221_out ;
  wire [1:0]\ui_rd_data0/p_222_out ;
  wire [1:0]\ui_rd_data0/p_223_out ;
  wire [1:0]\ui_rd_data0/p_224_out ;
  wire [1:0]\ui_rd_data0/p_225_out ;
  wire [1:0]\ui_rd_data0/p_226_out ;
  wire [1:0]\ui_rd_data0/p_227_out ;
  wire [1:0]\ui_rd_data0/p_228_out ;
  wire [1:0]\ui_rd_data0/p_229_out ;
  wire [1:0]\ui_rd_data0/p_22_out ;
  wire [1:0]\ui_rd_data0/p_230_out ;
  wire [1:0]\ui_rd_data0/p_231_out ;
  wire [1:0]\ui_rd_data0/p_232_out ;
  wire [1:0]\ui_rd_data0/p_233_out ;
  wire [1:0]\ui_rd_data0/p_234_out ;
  wire [1:0]\ui_rd_data0/p_235_out ;
  wire [1:0]\ui_rd_data0/p_236_out ;
  wire [1:0]\ui_rd_data0/p_237_out ;
  wire [1:0]\ui_rd_data0/p_238_out ;
  wire [1:0]\ui_rd_data0/p_239_out ;
  wire [1:0]\ui_rd_data0/p_23_out ;
  wire [1:0]\ui_rd_data0/p_240_out ;
  wire [1:0]\ui_rd_data0/p_241_out ;
  wire [1:0]\ui_rd_data0/p_242_out ;
  wire [1:0]\ui_rd_data0/p_243_out ;
  wire [1:0]\ui_rd_data0/p_244_out ;
  wire [1:0]\ui_rd_data0/p_245_out ;
  wire [1:0]\ui_rd_data0/p_246_out ;
  wire [1:0]\ui_rd_data0/p_247_out ;
  wire [1:0]\ui_rd_data0/p_248_out ;
  wire [1:0]\ui_rd_data0/p_249_out ;
  wire [1:0]\ui_rd_data0/p_24_out ;
  wire [1:0]\ui_rd_data0/p_250_out ;
  wire [1:0]\ui_rd_data0/p_251_out ;
  wire [1:0]\ui_rd_data0/p_252_out ;
  wire [1:0]\ui_rd_data0/p_253_out ;
  wire [1:0]\ui_rd_data0/p_254_out ;
  wire [1:0]\ui_rd_data0/p_256_out ;
  wire [1:0]\ui_rd_data0/p_257_out ;
  wire [1:0]\ui_rd_data0/p_258_out ;
  wire [1:0]\ui_rd_data0/p_25_out ;
  wire [1:0]\ui_rd_data0/p_26_out ;
  wire [1:0]\ui_rd_data0/p_27_out ;
  wire [1:0]\ui_rd_data0/p_28_out ;
  wire [1:0]\ui_rd_data0/p_29_out ;
  wire [1:0]\ui_rd_data0/p_30_out ;
  wire [1:0]\ui_rd_data0/p_31_out ;
  wire [1:0]\ui_rd_data0/p_32_out ;
  wire [1:0]\ui_rd_data0/p_33_out ;
  wire [1:0]\ui_rd_data0/p_34_out ;
  wire [1:0]\ui_rd_data0/p_35_out ;
  wire [1:0]\ui_rd_data0/p_36_out ;
  wire [1:0]\ui_rd_data0/p_37_out ;
  wire [1:0]\ui_rd_data0/p_38_out ;
  wire [1:0]\ui_rd_data0/p_39_out ;
  wire [1:0]\ui_rd_data0/p_3_out ;
  wire [1:0]\ui_rd_data0/p_40_out ;
  wire [1:0]\ui_rd_data0/p_41_out ;
  wire [1:0]\ui_rd_data0/p_42_out ;
  wire [1:0]\ui_rd_data0/p_43_out ;
  wire [1:0]\ui_rd_data0/p_44_out ;
  wire [1:0]\ui_rd_data0/p_45_out ;
  wire [1:0]\ui_rd_data0/p_46_out ;
  wire [1:0]\ui_rd_data0/p_47_out ;
  wire [1:0]\ui_rd_data0/p_48_out ;
  wire [1:0]\ui_rd_data0/p_49_out ;
  wire [1:0]\ui_rd_data0/p_4_out ;
  wire [1:0]\ui_rd_data0/p_50_out ;
  wire [1:0]\ui_rd_data0/p_51_out ;
  wire [1:0]\ui_rd_data0/p_52_out ;
  wire [1:0]\ui_rd_data0/p_53_out ;
  wire [1:0]\ui_rd_data0/p_54_out ;
  wire [1:0]\ui_rd_data0/p_55_out ;
  wire [1:0]\ui_rd_data0/p_56_out ;
  wire [1:0]\ui_rd_data0/p_57_out ;
  wire [1:0]\ui_rd_data0/p_58_out ;
  wire [1:0]\ui_rd_data0/p_59_out ;
  wire [1:0]\ui_rd_data0/p_5_out ;
  wire [1:0]\ui_rd_data0/p_60_out ;
  wire [1:0]\ui_rd_data0/p_61_out ;
  wire [1:0]\ui_rd_data0/p_62_out ;
  wire [1:0]\ui_rd_data0/p_63_out ;
  wire [1:0]\ui_rd_data0/p_64_out ;
  wire [1:0]\ui_rd_data0/p_65_out ;
  wire [1:0]\ui_rd_data0/p_66_out ;
  wire [1:0]\ui_rd_data0/p_67_out ;
  wire [1:0]\ui_rd_data0/p_68_out ;
  wire [1:0]\ui_rd_data0/p_69_out ;
  wire [1:0]\ui_rd_data0/p_6_out ;
  wire [1:0]\ui_rd_data0/p_70_out ;
  wire [1:0]\ui_rd_data0/p_71_out ;
  wire [1:0]\ui_rd_data0/p_72_out ;
  wire [1:0]\ui_rd_data0/p_73_out ;
  wire [1:0]\ui_rd_data0/p_74_out ;
  wire [1:0]\ui_rd_data0/p_75_out ;
  wire [1:0]\ui_rd_data0/p_76_out ;
  wire [1:0]\ui_rd_data0/p_77_out ;
  wire [1:0]\ui_rd_data0/p_78_out ;
  wire [1:0]\ui_rd_data0/p_79_out ;
  wire [1:0]\ui_rd_data0/p_7_out ;
  wire [1:0]\ui_rd_data0/p_80_out ;
  wire [1:0]\ui_rd_data0/p_81_out ;
  wire [1:0]\ui_rd_data0/p_82_out ;
  wire [1:0]\ui_rd_data0/p_83_out ;
  wire [1:0]\ui_rd_data0/p_84_out ;
  wire [1:0]\ui_rd_data0/p_85_out ;
  wire [1:0]\ui_rd_data0/p_86_out ;
  wire [1:0]\ui_rd_data0/p_87_out ;
  wire [1:0]\ui_rd_data0/p_88_out ;
  wire [1:0]\ui_rd_data0/p_89_out ;
  wire [1:0]\ui_rd_data0/p_8_out ;
  wire [1:0]\ui_rd_data0/p_90_out ;
  wire [1:0]\ui_rd_data0/p_91_out ;
  wire [1:0]\ui_rd_data0/p_92_out ;
  wire [1:0]\ui_rd_data0/p_93_out ;
  wire [1:0]\ui_rd_data0/p_94_out ;
  wire [1:0]\ui_rd_data0/p_95_out ;
  wire [1:0]\ui_rd_data0/p_96_out ;
  wire [1:0]\ui_rd_data0/p_97_out ;
  wire [1:0]\ui_rd_data0/p_98_out ;
  wire [1:0]\ui_rd_data0/p_99_out ;
  wire [1:0]\ui_rd_data0/p_9_out ;
  wire \ui_rd_data0/rd_buf_we ;
  wire \ui_wr_data0/pointer_we ;
  wire [511:0]wr_data;
  wire [3:0]wr_data_addr;
  wire wr_data_en;
  wire [63:0]wr_data_mask;
  wire wr_en;
  wire wr_en_10;
  wire wr_en_11;
  wire wr_en_12;
  wire wr_en_13;
  wire wr_en_14;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[0]_1 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire \wr_ptr_reg[1]_1 ;
  wire \wr_ptr_reg[1]_2 ;
  wire \wr_ptr_reg[1]_3 ;
  wire [3:0]\wr_ptr_timing_reg[0] ;
  wire [3:0]\wr_ptr_timing_reg[0]_0 ;
  wire [45:0]\wr_ptr_timing_reg[0]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3] ;
  wire [3:0]\wr_ptr_timing_reg[3]_0 ;
  wire [3:0]\wr_ptr_timing_reg[3]_1 ;
  wire [3:0]\wr_ptr_timing_reg[3]_2 ;
  wire [3:0]\wr_ptr_timing_reg[3]_3 ;
  wire [3:0]\wr_ptr_timing_reg[3]_4 ;

  mig_7series_0_mig_7series_v2_3_mem_intfc mem_intfc0
       (.ADDRA(ADDRA),
        .ADDRC({mem_intfc0_n_1706,mem_intfc0_n_1707,mem_intfc0_n_1708,mem_intfc0_n_1709}),
        .A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .CLK(CLK),
        .D(app_rd_data_ns),
        .DIA({mem_intfc0_n_427,mem_intfc0_n_428}),
        .DIB({mem_intfc0_n_429,mem_intfc0_n_430}),
        .DIC({mem_intfc0_n_431,mem_intfc0_n_432}),
        .DOA(\ui_rd_data0/p_258_out ),
        .DOB(\ui_rd_data0/p_257_out ),
        .DOC(\ui_rd_data0/p_256_out ),
        .E(wr_data_en),
        .Q(\mc0/bank_mach0/p_147_out ),
        .S(u_ui_top_n_529),
        .SR(SR),
        .SS(SS),
        .accept_ns(accept_ns),
        .\app_addr_r1_reg[22] (u_ui_top_n_544),
        .\app_addr_r1_reg[22]_0 (u_ui_top_n_545),
        .\app_addr_r1_reg[22]_1 (u_ui_top_n_546),
        .\app_addr_r1_reg[26] (bank),
        .\app_addr_r1_reg[9] (col),
        .\app_cmd_r1_reg[1] (\ui_cmd0/app_cmd_r1 ),
        .app_cmd_r2(\ui_cmd0/app_cmd_r2 ),
        .\app_cmd_r2_reg[0] (u_ui_top_n_520),
        .\app_cmd_r2_reg[1] (u_ui_top_n_528),
        .app_en_r2(\ui_cmd0/app_en_r2 ),
        .app_rd_data_end_ns(\ui_rd_data0/app_rd_data_end_ns ),
        .app_rdy_r_reg(E),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .\cmd_pipe_plus.mc_address_reg[13] (\mc0/bank_mach0/p_151_out ),
        .\cmd_pipe_plus.mc_address_reg[13]_0 (\mc0/bank_mach0/p_112_out ),
        .\cmd_pipe_plus.mc_address_reg[41] (\mc0/bank_mach0/p_34_out ),
        .\cmd_pipe_plus.mc_address_reg[41]_0 (\mc0/bank_mach0/p_73_out ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\mc0/bank_mach0/p_108_out ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\mc0/bank_mach0/p_30_out ),
        .\cmd_pipe_plus.mc_bank_reg[8]_0 (\mc0/bank_mach0/p_69_out ),
        .complex_row0_rd_done1(complex_row0_rd_done1),
        .complex_row1_rd_done_reg(prbs_rdlvl_done_pulse),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .demand_priority_r_reg(mem_intfc0_n_79),
        .demand_priority_r_reg_0(mem_intfc0_n_80),
        .demand_priority_r_reg_1(mem_intfc0_n_81),
        .\device_temp_r_reg[11] (\device_temp_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .dqs_po_en_stg2_f_reg(po_cnt_dec),
        .fine_dly_dec_done_r1_reg(pi_cnt_dec),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (mem_intfc0_n_180),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (mem_intfc0_n_416),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ({mem_intfc0_n_475,mem_intfc0_n_476}),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ({mem_intfc0_n_477,mem_intfc0_n_478}),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ({mem_intfc0_n_479,mem_intfc0_n_480}),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ({mem_intfc0_n_481,mem_intfc0_n_482}),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_3 ({mem_intfc0_n_703,mem_intfc0_n_704}),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_4 ({mem_intfc0_n_705,mem_intfc0_n_706}),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_5 ({mem_intfc0_n_707,mem_intfc0_n_708}),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_6 ({mem_intfc0_n_709,mem_intfc0_n_710}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ({mem_intfc0_n_459,mem_intfc0_n_460}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ({mem_intfc0_n_461,mem_intfc0_n_462}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ({mem_intfc0_n_463,mem_intfc0_n_464}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ({mem_intfc0_n_465,mem_intfc0_n_466}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_3 ({mem_intfc0_n_687,mem_intfc0_n_688}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_4 ({mem_intfc0_n_689,mem_intfc0_n_690}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_5 ({mem_intfc0_n_691,mem_intfc0_n_692}),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_6 ({mem_intfc0_n_693,mem_intfc0_n_694}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ({mem_intfc0_n_443,mem_intfc0_n_444}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ({mem_intfc0_n_445,mem_intfc0_n_446}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ({mem_intfc0_n_447,mem_intfc0_n_448}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ({mem_intfc0_n_449,mem_intfc0_n_450}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_3 ({mem_intfc0_n_671,mem_intfc0_n_672}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_4 ({mem_intfc0_n_673,mem_intfc0_n_674}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_5 ({mem_intfc0_n_675,mem_intfc0_n_676}),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_6 ({mem_intfc0_n_677,mem_intfc0_n_678}),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ({mem_intfc0_n_433,mem_intfc0_n_434}),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ({mem_intfc0_n_655,mem_intfc0_n_656}),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ({mem_intfc0_n_657,mem_intfc0_n_658}),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ({mem_intfc0_n_659,mem_intfc0_n_660}),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_3 ({mem_intfc0_n_661,mem_intfc0_n_662}),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (mem_intfc0_n_181),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (mem_intfc0_n_417),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ({mem_intfc0_n_467,mem_intfc0_n_468}),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ({mem_intfc0_n_469,mem_intfc0_n_470}),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ({mem_intfc0_n_471,mem_intfc0_n_472}),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ({mem_intfc0_n_473,mem_intfc0_n_474}),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_3 ({mem_intfc0_n_695,mem_intfc0_n_696}),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_4 ({mem_intfc0_n_697,mem_intfc0_n_698}),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_5 ({mem_intfc0_n_699,mem_intfc0_n_700}),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_6 ({mem_intfc0_n_701,mem_intfc0_n_702}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ({mem_intfc0_n_451,mem_intfc0_n_452}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ({mem_intfc0_n_453,mem_intfc0_n_454}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ({mem_intfc0_n_455,mem_intfc0_n_456}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ({mem_intfc0_n_457,mem_intfc0_n_458}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_3 ({mem_intfc0_n_679,mem_intfc0_n_680}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_4 ({mem_intfc0_n_681,mem_intfc0_n_682}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_5 ({mem_intfc0_n_683,mem_intfc0_n_684}),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_6 ({mem_intfc0_n_685,mem_intfc0_n_686}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ({mem_intfc0_n_435,mem_intfc0_n_436}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ({mem_intfc0_n_437,mem_intfc0_n_438}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ({mem_intfc0_n_439,mem_intfc0_n_440}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ({mem_intfc0_n_441,mem_intfc0_n_442}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_3 ({mem_intfc0_n_663,mem_intfc0_n_664}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_4 ({mem_intfc0_n_665,mem_intfc0_n_666}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_5 ({mem_intfc0_n_667,mem_intfc0_n_668}),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_6 ({mem_intfc0_n_669,mem_intfc0_n_670}),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (mem_intfc0_n_179),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (mem_intfc0_n_349),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ({mem_intfc0_n_531,mem_intfc0_n_532}),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ({mem_intfc0_n_533,mem_intfc0_n_534}),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ({mem_intfc0_n_535,mem_intfc0_n_536}),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ({mem_intfc0_n_537,mem_intfc0_n_538}),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_3 ({mem_intfc0_n_759,mem_intfc0_n_760}),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_4 ({mem_intfc0_n_761,mem_intfc0_n_762}),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_5 ({mem_intfc0_n_763,mem_intfc0_n_764}),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_6 ({mem_intfc0_n_765,mem_intfc0_n_766}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ({mem_intfc0_n_515,mem_intfc0_n_516}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ({mem_intfc0_n_517,mem_intfc0_n_518}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ({mem_intfc0_n_519,mem_intfc0_n_520}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ({mem_intfc0_n_521,mem_intfc0_n_522}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_3 ({mem_intfc0_n_743,mem_intfc0_n_744}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_4 ({mem_intfc0_n_745,mem_intfc0_n_746}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_5 ({mem_intfc0_n_747,mem_intfc0_n_748}),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_6 ({mem_intfc0_n_749,mem_intfc0_n_750}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ({mem_intfc0_n_499,mem_intfc0_n_500}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ({mem_intfc0_n_501,mem_intfc0_n_502}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ({mem_intfc0_n_503,mem_intfc0_n_504}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ({mem_intfc0_n_505,mem_intfc0_n_506}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_3 ({mem_intfc0_n_727,mem_intfc0_n_728}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_4 ({mem_intfc0_n_729,mem_intfc0_n_730}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_5 ({mem_intfc0_n_731,mem_intfc0_n_732}),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_6 ({mem_intfc0_n_733,mem_intfc0_n_734}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ({mem_intfc0_n_483,mem_intfc0_n_484}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ({mem_intfc0_n_485,mem_intfc0_n_486}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ({mem_intfc0_n_487,mem_intfc0_n_488}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ({mem_intfc0_n_489,mem_intfc0_n_490}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_3 ({mem_intfc0_n_711,mem_intfc0_n_712}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_4 ({mem_intfc0_n_713,mem_intfc0_n_714}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_5 ({mem_intfc0_n_715,mem_intfc0_n_716}),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_6 ({mem_intfc0_n_717,mem_intfc0_n_718}),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (mem_intfc0_n_539),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (mem_intfc0_n_540),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (mem_intfc0_n_541),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (mem_intfc0_n_542),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_3 (mem_intfc0_n_767),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_4 (mem_intfc0_n_768),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_5 (mem_intfc0_n_769),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_6 (mem_intfc0_n_770),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ({mem_intfc0_n_523,mem_intfc0_n_524}),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ({mem_intfc0_n_525,mem_intfc0_n_526}),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ({mem_intfc0_n_527,mem_intfc0_n_528}),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ({mem_intfc0_n_529,mem_intfc0_n_530}),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_3 ({mem_intfc0_n_751,mem_intfc0_n_752}),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_4 ({mem_intfc0_n_753,mem_intfc0_n_754}),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_5 ({mem_intfc0_n_755,mem_intfc0_n_756}),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_6 ({mem_intfc0_n_757,mem_intfc0_n_758}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ({mem_intfc0_n_507,mem_intfc0_n_508}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ({mem_intfc0_n_509,mem_intfc0_n_510}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ({mem_intfc0_n_511,mem_intfc0_n_512}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ({mem_intfc0_n_513,mem_intfc0_n_514}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_3 ({mem_intfc0_n_735,mem_intfc0_n_736}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_4 ({mem_intfc0_n_737,mem_intfc0_n_738}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_5 ({mem_intfc0_n_739,mem_intfc0_n_740}),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_6 ({mem_intfc0_n_741,mem_intfc0_n_742}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ({mem_intfc0_n_491,mem_intfc0_n_492}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ({mem_intfc0_n_493,mem_intfc0_n_494}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ({mem_intfc0_n_495,mem_intfc0_n_496}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ({mem_intfc0_n_497,mem_intfc0_n_498}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_3 ({mem_intfc0_n_719,mem_intfc0_n_720}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_4 ({mem_intfc0_n_721,mem_intfc0_n_722}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_5 ({mem_intfc0_n_723,mem_intfc0_n_724}),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_6 ({mem_intfc0_n_725,mem_intfc0_n_726}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ({mem_intfc0_n_591,mem_intfc0_n_592}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ({mem_intfc0_n_593,mem_intfc0_n_594}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ({mem_intfc0_n_595,mem_intfc0_n_596}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ({mem_intfc0_n_597,mem_intfc0_n_598}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_3 ({mem_intfc0_n_819,mem_intfc0_n_820}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_4 ({mem_intfc0_n_821,mem_intfc0_n_822}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_5 ({mem_intfc0_n_823,mem_intfc0_n_824}),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_6 ({mem_intfc0_n_825,mem_intfc0_n_826}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ({mem_intfc0_n_575,mem_intfc0_n_576}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ({mem_intfc0_n_577,mem_intfc0_n_578}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ({mem_intfc0_n_579,mem_intfc0_n_580}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ({mem_intfc0_n_581,mem_intfc0_n_582}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_3 ({mem_intfc0_n_803,mem_intfc0_n_804}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_4 ({mem_intfc0_n_805,mem_intfc0_n_806}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_5 ({mem_intfc0_n_807,mem_intfc0_n_808}),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_6 ({mem_intfc0_n_809,mem_intfc0_n_810}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ({mem_intfc0_n_559,mem_intfc0_n_560}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ({mem_intfc0_n_561,mem_intfc0_n_562}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ({mem_intfc0_n_563,mem_intfc0_n_564}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ({mem_intfc0_n_565,mem_intfc0_n_566}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_3 ({mem_intfc0_n_787,mem_intfc0_n_788}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_4 ({mem_intfc0_n_789,mem_intfc0_n_790}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_5 ({mem_intfc0_n_791,mem_intfc0_n_792}),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_6 ({mem_intfc0_n_793,mem_intfc0_n_794}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ({mem_intfc0_n_543,mem_intfc0_n_544}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ({mem_intfc0_n_545,mem_intfc0_n_546}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ({mem_intfc0_n_547,mem_intfc0_n_548}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ({mem_intfc0_n_549,mem_intfc0_n_550}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_3 ({mem_intfc0_n_771,mem_intfc0_n_772}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_4 ({mem_intfc0_n_773,mem_intfc0_n_774}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_5 ({mem_intfc0_n_775,mem_intfc0_n_776}),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_6 ({mem_intfc0_n_777,mem_intfc0_n_778}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ({mem_intfc0_n_583,mem_intfc0_n_584}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ({mem_intfc0_n_585,mem_intfc0_n_586}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ({mem_intfc0_n_587,mem_intfc0_n_588}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ({mem_intfc0_n_589,mem_intfc0_n_590}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_3 ({mem_intfc0_n_811,mem_intfc0_n_812}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_4 ({mem_intfc0_n_813,mem_intfc0_n_814}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_5 ({mem_intfc0_n_815,mem_intfc0_n_816}),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_6 ({mem_intfc0_n_817,mem_intfc0_n_818}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ({mem_intfc0_n_567,mem_intfc0_n_568}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ({mem_intfc0_n_569,mem_intfc0_n_570}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ({mem_intfc0_n_571,mem_intfc0_n_572}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ({mem_intfc0_n_573,mem_intfc0_n_574}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_3 ({mem_intfc0_n_795,mem_intfc0_n_796}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_4 ({mem_intfc0_n_797,mem_intfc0_n_798}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_5 ({mem_intfc0_n_799,mem_intfc0_n_800}),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_6 ({mem_intfc0_n_801,mem_intfc0_n_802}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ({mem_intfc0_n_551,mem_intfc0_n_552}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ({mem_intfc0_n_553,mem_intfc0_n_554}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ({mem_intfc0_n_555,mem_intfc0_n_556}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ({mem_intfc0_n_557,mem_intfc0_n_558}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_3 ({mem_intfc0_n_779,mem_intfc0_n_780}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_4 ({mem_intfc0_n_781,mem_intfc0_n_782}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_5 ({mem_intfc0_n_783,mem_intfc0_n_784}),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_6 ({mem_intfc0_n_785,mem_intfc0_n_786}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ({mem_intfc0_n_647,mem_intfc0_n_648}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ({mem_intfc0_n_649,mem_intfc0_n_650}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ({mem_intfc0_n_651,mem_intfc0_n_652}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ({mem_intfc0_n_653,mem_intfc0_n_654}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_3 ({mem_intfc0_n_875,mem_intfc0_n_876}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_4 ({mem_intfc0_n_877,mem_intfc0_n_878}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_5 ({mem_intfc0_n_879,mem_intfc0_n_880}),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_6 ({mem_intfc0_n_881,mem_intfc0_n_882}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ({mem_intfc0_n_631,mem_intfc0_n_632}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ({mem_intfc0_n_633,mem_intfc0_n_634}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ({mem_intfc0_n_635,mem_intfc0_n_636}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ({mem_intfc0_n_637,mem_intfc0_n_638}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_3 ({mem_intfc0_n_859,mem_intfc0_n_860}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_4 ({mem_intfc0_n_861,mem_intfc0_n_862}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_5 ({mem_intfc0_n_863,mem_intfc0_n_864}),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_6 ({mem_intfc0_n_865,mem_intfc0_n_866}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ({mem_intfc0_n_615,mem_intfc0_n_616}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ({mem_intfc0_n_617,mem_intfc0_n_618}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ({mem_intfc0_n_619,mem_intfc0_n_620}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ({mem_intfc0_n_621,mem_intfc0_n_622}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_3 ({mem_intfc0_n_843,mem_intfc0_n_844}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_4 ({mem_intfc0_n_845,mem_intfc0_n_846}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_5 ({mem_intfc0_n_847,mem_intfc0_n_848}),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_6 ({mem_intfc0_n_849,mem_intfc0_n_850}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ({mem_intfc0_n_599,mem_intfc0_n_600}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ({mem_intfc0_n_601,mem_intfc0_n_602}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ({mem_intfc0_n_603,mem_intfc0_n_604}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ({mem_intfc0_n_605,mem_intfc0_n_606}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_3 ({mem_intfc0_n_827,mem_intfc0_n_828}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_4 ({mem_intfc0_n_829,mem_intfc0_n_830}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_5 ({mem_intfc0_n_831,mem_intfc0_n_832}),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_6 ({mem_intfc0_n_833,mem_intfc0_n_834}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ({mem_intfc0_n_639,mem_intfc0_n_640}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ({mem_intfc0_n_641,mem_intfc0_n_642}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ({mem_intfc0_n_643,mem_intfc0_n_644}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ({mem_intfc0_n_645,mem_intfc0_n_646}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_3 ({mem_intfc0_n_867,mem_intfc0_n_868}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_4 ({mem_intfc0_n_869,mem_intfc0_n_870}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_5 ({mem_intfc0_n_871,mem_intfc0_n_872}),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_6 ({mem_intfc0_n_873,mem_intfc0_n_874}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ({mem_intfc0_n_623,mem_intfc0_n_624}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ({mem_intfc0_n_625,mem_intfc0_n_626}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ({mem_intfc0_n_627,mem_intfc0_n_628}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ({mem_intfc0_n_629,mem_intfc0_n_630}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_3 ({mem_intfc0_n_851,mem_intfc0_n_852}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_4 ({mem_intfc0_n_853,mem_intfc0_n_854}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_5 ({mem_intfc0_n_855,mem_intfc0_n_856}),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_6 ({mem_intfc0_n_857,mem_intfc0_n_858}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ({mem_intfc0_n_607,mem_intfc0_n_608}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ({mem_intfc0_n_609,mem_intfc0_n_610}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ({mem_intfc0_n_611,mem_intfc0_n_612}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ({mem_intfc0_n_613,mem_intfc0_n_614}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_3 ({mem_intfc0_n_835,mem_intfc0_n_836}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_4 ({mem_intfc0_n_837,mem_intfc0_n_838}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_5 ({mem_intfc0_n_839,mem_intfc0_n_840}),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_6 ({mem_intfc0_n_841,mem_intfc0_n_842}),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (mem_intfc0_n_189),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (mem_intfc0_n_190),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (mem_intfc0_n_191),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (mem_intfc0_n_192),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (mem_intfc0_n_193),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (mem_intfc0_n_194),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (mem_intfc0_n_195),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (mem_intfc0_n_182),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (mem_intfc0_n_183),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (mem_intfc0_n_184),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (mem_intfc0_n_185),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (mem_intfc0_n_186),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (mem_intfc0_n_187),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (mem_intfc0_n_188),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (mem_intfc0_n_175),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (mem_intfc0_n_176),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (mem_intfc0_n_177),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (mem_intfc0_n_178),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (mem_intfc0_n_168),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (mem_intfc0_n_169),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (mem_intfc0_n_170),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (mem_intfc0_n_171),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (mem_intfc0_n_172),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (mem_intfc0_n_173),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (mem_intfc0_n_174),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (mem_intfc0_n_95),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (mem_intfc0_n_96),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (mem_intfc0_n_97),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (mem_intfc0_n_98),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (mem_intfc0_n_99),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (mem_intfc0_n_166),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (mem_intfc0_n_167),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (mem_intfc0_n_197),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (mem_intfc0_n_198),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (mem_intfc0_n_199),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (mem_intfc0_n_200),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (mem_intfc0_n_201),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (mem_intfc0_n_268),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (mem_intfc0_n_269),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (mem_intfc0_n_270),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (mem_intfc0_n_271),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (mem_intfc0_n_272),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (mem_intfc0_n_273),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (mem_intfc0_n_274),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (mem_intfc0_n_343),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (mem_intfc0_n_344),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (mem_intfc0_n_345),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (mem_intfc0_n_346),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (mem_intfc0_n_347),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (mem_intfc0_n_348),
        .\idelay_tap_cnt_r_reg[0][7][3] (\idelay_tap_cnt_r_reg[0][7][3] ),
        .idelay_tap_limit_r_reg(idelay_tap_limit_r_reg),
        .init_calib_complete(init_calib_complete),
        .init_complete_r_timing(init_complete_r_timing),
        .init_complete_r_timing_reg(init_complete_r_timing_reg),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[7] (mem_intfc0_n_61),
        .\my_empty_reg[7]_0 (mem_intfc0_n_62),
        .\my_empty_reg[7]_1 (mem_intfc0_n_63),
        .\my_empty_reg[7]_10 (\my_empty_reg[7] ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_2 (mem_intfc0_n_64),
        .\my_empty_reg[7]_3 (mem_intfc0_n_65),
        .\my_empty_reg[7]_4 (mem_intfc0_n_66),
        .\my_empty_reg[7]_5 (mem_intfc0_n_67),
        .\my_empty_reg[7]_6 (mem_intfc0_n_68),
        .\my_empty_reg[7]_7 (mem_intfc0_n_69),
        .\my_empty_reg[7]_8 ({\my_empty_reg[7]_3 [255:192],\my_empty_reg[7]_3 [190:188],\my_empty_reg[7]_3 [186:184],\my_empty_reg[7]_3 [182:180],\my_empty_reg[7]_3 [178:176],\my_empty_reg[7]_3 [174:172],\my_empty_reg[7]_3 [170:168],\my_empty_reg[7]_3 [166:164],\my_empty_reg[7]_3 [162:159],\my_empty_reg[7]_3 [157:155],\my_empty_reg[7]_3 [153:151],\my_empty_reg[7]_3 [149:147],\my_empty_reg[7]_3 [145:143],\my_empty_reg[7]_3 [141:139],\my_empty_reg[7]_3 [137:135],\my_empty_reg[7]_3 [133:131],\my_empty_reg[7]_3 [129:127],\my_empty_reg[7]_3 [125:123],\my_empty_reg[7]_3 [121:119],\my_empty_reg[7]_3 [117:115],\my_empty_reg[7]_3 [113:111],\my_empty_reg[7]_3 [109:107],\my_empty_reg[7]_3 [105:103],\my_empty_reg[7]_3 [101:99],\my_empty_reg[7]_3 [97:94],\my_empty_reg[7]_3 [92:90],\my_empty_reg[7]_3 [88:86],\my_empty_reg[7]_3 [84:82],\my_empty_reg[7]_3 [80:78],\my_empty_reg[7]_3 [76:74],\my_empty_reg[7]_3 [72:70],\my_empty_reg[7]_3 [68:66],\my_empty_reg[7]_3 [64:32],\my_empty_reg[7]_3 [30:29],\my_empty_reg[7]_3 [26:25],\my_empty_reg[7]_3 [22:21],\my_empty_reg[7]_3 [18:17],\my_empty_reg[7]_3 [14:13],\my_empty_reg[7]_3 [10:9],\my_empty_reg[7]_3 [6:5],\my_empty_reg[7]_3 [2:1]}),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_4 ),
        .\not_strict_mode.app_rd_data_end_reg ({rd_data_end,rd_data_addr,rd_data_offset}),
        .\not_strict_mode.app_rd_data_reg[232] (\not_strict_mode.app_rd_data_reg[232] ),
        .\not_strict_mode.app_rd_data_reg[24] (mem_intfc0_n_1692),
        .\not_strict_mode.app_rd_data_reg[352] (Q),
        .\not_strict_mode.app_rd_data_reg[376] (\not_strict_mode.app_rd_data_reg[376] ),
        .\not_strict_mode.app_rd_data_reg[376]_0 (\not_strict_mode.app_rd_data_reg[376]_0 ),
        .\not_strict_mode.app_rd_data_reg[488] (\not_strict_mode.app_rd_data_reg[488] ),
        .\not_strict_mode.app_rd_data_reg[496] (\not_strict_mode.app_rd_data_reg[496] ),
        .\not_strict_mode.app_rd_data_reg[496]_0 (\not_strict_mode.app_rd_data_reg[496]_0 ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (data_buf_addr),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\ui_rd_data0/p_252_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\ui_rd_data0/p_253_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\ui_rd_data0/p_254_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\ui_rd_data0/p_245_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\ui_rd_data0/p_155_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\ui_rd_data0/p_150_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\ui_rd_data0/p_151_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\ui_rd_data0/p_152_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\ui_rd_data0/p_147_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\ui_rd_data0/p_148_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\ui_rd_data0/p_149_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\ui_rd_data0/p_144_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\ui_rd_data0/p_145_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\ui_rd_data0/p_146_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\ui_rd_data0/p_240_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\ui_rd_data0/p_141_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\ui_rd_data0/p_142_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\ui_rd_data0/p_143_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\ui_rd_data0/p_138_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\ui_rd_data0/p_139_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\ui_rd_data0/p_140_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\ui_rd_data0/p_135_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\ui_rd_data0/p_136_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\ui_rd_data0/p_137_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\ui_rd_data0/p_132_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\ui_rd_data0/p_241_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\ui_rd_data0/p_133_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\ui_rd_data0/p_134_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\ui_rd_data0/p_129_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\ui_rd_data0/p_130_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124 (\ui_rd_data0/p_131_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125 (\ui_rd_data0/p_126_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126 (\ui_rd_data0/p_127_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127 (\ui_rd_data0/p_128_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128 (\ui_rd_data0/p_123_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129 (\ui_rd_data0/p_124_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\ui_rd_data0/p_242_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130 (\ui_rd_data0/p_125_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131 (\ui_rd_data0/p_120_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132 (\ui_rd_data0/p_121_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133 (\ui_rd_data0/p_122_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134 (\ui_rd_data0/p_117_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135 (\ui_rd_data0/p_118_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136 (\ui_rd_data0/p_119_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137 (\ui_rd_data0/p_114_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138 (\ui_rd_data0/p_115_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139 (\ui_rd_data0/p_116_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\ui_rd_data0/p_237_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140 (\ui_rd_data0/p_111_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141 (\ui_rd_data0/p_112_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142 (\ui_rd_data0/p_113_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143 (\ui_rd_data0/p_108_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144 (\ui_rd_data0/p_109_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145 (\ui_rd_data0/p_110_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146 (\ui_rd_data0/p_105_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147 (\ui_rd_data0/p_106_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148 (\ui_rd_data0/p_107_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149 (\ui_rd_data0/p_102_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\ui_rd_data0/p_238_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150 (\ui_rd_data0/p_103_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151 (\ui_rd_data0/p_104_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152 (\ui_rd_data0/p_99_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153 (\ui_rd_data0/p_100_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154 (\ui_rd_data0/p_101_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155 (\ui_rd_data0/p_96_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156 (\ui_rd_data0/p_97_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157 (\ui_rd_data0/p_98_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158 (\ui_rd_data0/p_93_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159 (\ui_rd_data0/p_94_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\ui_rd_data0/p_239_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160 (\ui_rd_data0/p_95_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161 (\ui_rd_data0/p_90_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162 (\ui_rd_data0/p_91_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163 (\ui_rd_data0/p_92_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164 (\ui_rd_data0/p_87_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165 (\ui_rd_data0/p_88_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166 (\ui_rd_data0/p_89_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167 (\ui_rd_data0/p_84_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168 (\ui_rd_data0/p_85_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169 (\ui_rd_data0/p_86_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\ui_rd_data0/p_234_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170 (\ui_rd_data0/p_81_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171 (\ui_rd_data0/p_82_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172 (\ui_rd_data0/p_83_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173 (\ui_rd_data0/p_78_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174 (\ui_rd_data0/p_79_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175 (\ui_rd_data0/p_80_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176 (\ui_rd_data0/p_75_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177 (\ui_rd_data0/p_76_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178 (\ui_rd_data0/p_77_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179 (\ui_rd_data0/p_72_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\ui_rd_data0/p_235_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180 (\ui_rd_data0/p_73_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181 (\ui_rd_data0/p_74_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182 (\ui_rd_data0/p_69_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183 (\ui_rd_data0/p_70_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184 (\ui_rd_data0/p_71_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185 (\ui_rd_data0/p_66_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186 (\ui_rd_data0/p_67_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187 (\ui_rd_data0/p_68_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188 (\ui_rd_data0/p_63_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189 (\ui_rd_data0/p_64_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\ui_rd_data0/p_236_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190 (\ui_rd_data0/p_65_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191 (\ui_rd_data0/p_60_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192 (\ui_rd_data0/p_61_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193 (\ui_rd_data0/p_62_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194 (\ui_rd_data0/p_57_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195 (\ui_rd_data0/p_58_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196 (\ui_rd_data0/p_59_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197 (\ui_rd_data0/p_54_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198 (\ui_rd_data0/p_55_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199 (\ui_rd_data0/p_56_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\ui_rd_data0/p_249_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\ui_rd_data0/p_231_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200 (\ui_rd_data0/p_51_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201 (\ui_rd_data0/p_52_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202 (\ui_rd_data0/p_53_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203 (\ui_rd_data0/p_48_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204 (\ui_rd_data0/p_49_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205 (\ui_rd_data0/p_50_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206 (\ui_rd_data0/p_45_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207 (\ui_rd_data0/p_46_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208 (\ui_rd_data0/p_47_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209 (\ui_rd_data0/p_42_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\ui_rd_data0/p_232_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210 (\ui_rd_data0/p_43_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211 (\ui_rd_data0/p_44_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212 (\ui_rd_data0/p_39_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213 (\ui_rd_data0/p_40_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214 (\ui_rd_data0/p_41_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215 (\ui_rd_data0/p_36_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216 (\ui_rd_data0/p_37_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217 (\ui_rd_data0/p_38_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218 (\ui_rd_data0/p_33_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219 (\ui_rd_data0/p_34_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\ui_rd_data0/p_233_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220 (\ui_rd_data0/p_35_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221 (\ui_rd_data0/p_30_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222 (\ui_rd_data0/p_31_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223 (\ui_rd_data0/p_32_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224 (\ui_rd_data0/p_27_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225 (\ui_rd_data0/p_28_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226 (\ui_rd_data0/p_29_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227 (\ui_rd_data0/p_24_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228 (\ui_rd_data0/p_25_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229 (\ui_rd_data0/p_26_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\ui_rd_data0/p_228_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230 (\ui_rd_data0/p_21_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231 (\ui_rd_data0/p_22_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232 (\ui_rd_data0/p_23_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233 (\ui_rd_data0/p_18_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234 (\ui_rd_data0/p_19_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235 (\ui_rd_data0/p_20_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236 (\ui_rd_data0/p_15_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237 (\ui_rd_data0/p_16_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238 (\ui_rd_data0/p_17_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239 (\ui_rd_data0/p_12_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\ui_rd_data0/p_229_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240 (\ui_rd_data0/p_13_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241 (\ui_rd_data0/p_14_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242 (\ui_rd_data0/p_9_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243 (\ui_rd_data0/p_10_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244 (\ui_rd_data0/p_11_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245 (\ui_rd_data0/p_6_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246 (\ui_rd_data0/p_7_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247 (\ui_rd_data0/p_8_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248 (\ui_rd_data0/p_3_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249 (\ui_rd_data0/p_4_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\ui_rd_data0/p_230_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250 (\ui_rd_data0/p_5_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251 (\ui_rd_data0/p_0_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\ui_rd_data0/p_225_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\ui_rd_data0/p_226_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\ui_rd_data0/p_227_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\ui_rd_data0/p_222_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\ui_rd_data0/p_250_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\ui_rd_data0/p_223_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\ui_rd_data0/p_224_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\ui_rd_data0/p_219_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\ui_rd_data0/p_220_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\ui_rd_data0/p_221_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\ui_rd_data0/p_216_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\ui_rd_data0/p_217_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\ui_rd_data0/p_218_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\ui_rd_data0/p_213_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\ui_rd_data0/p_214_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\ui_rd_data0/p_251_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\ui_rd_data0/p_215_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\ui_rd_data0/p_210_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\ui_rd_data0/p_211_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\ui_rd_data0/p_212_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\ui_rd_data0/p_207_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\ui_rd_data0/p_208_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\ui_rd_data0/p_209_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\ui_rd_data0/p_204_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\ui_rd_data0/p_205_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\ui_rd_data0/p_206_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\ui_rd_data0/p_246_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\ui_rd_data0/p_201_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\ui_rd_data0/p_202_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\ui_rd_data0/p_203_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\ui_rd_data0/p_198_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\ui_rd_data0/p_199_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\ui_rd_data0/p_200_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\ui_rd_data0/p_195_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\ui_rd_data0/p_196_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\ui_rd_data0/p_197_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\ui_rd_data0/p_192_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\ui_rd_data0/p_247_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\ui_rd_data0/p_193_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\ui_rd_data0/p_194_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\ui_rd_data0/p_189_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\ui_rd_data0/p_190_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\ui_rd_data0/p_191_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\ui_rd_data0/p_186_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\ui_rd_data0/p_187_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\ui_rd_data0/p_188_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\ui_rd_data0/p_183_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\ui_rd_data0/p_184_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\ui_rd_data0/p_248_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\ui_rd_data0/p_185_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\ui_rd_data0/p_180_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\ui_rd_data0/p_181_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\ui_rd_data0/p_182_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\ui_rd_data0/p_177_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\ui_rd_data0/p_178_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\ui_rd_data0/p_179_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\ui_rd_data0/p_174_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\ui_rd_data0/p_175_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\ui_rd_data0/p_176_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\ui_rd_data0/p_243_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\ui_rd_data0/p_171_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\ui_rd_data0/p_172_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\ui_rd_data0/p_173_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\ui_rd_data0/p_168_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\ui_rd_data0/p_169_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\ui_rd_data0/p_170_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\ui_rd_data0/p_165_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\ui_rd_data0/p_166_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\ui_rd_data0/p_167_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\ui_rd_data0/p_162_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\ui_rd_data0/p_244_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\ui_rd_data0/p_163_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\ui_rd_data0/p_164_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\ui_rd_data0/p_159_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\ui_rd_data0/p_160_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\ui_rd_data0/p_161_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\ui_rd_data0/p_156_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\ui_rd_data0/p_157_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\ui_rd_data0/p_158_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\ui_rd_data0/p_153_out ),
        .\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\ui_rd_data0/p_154_out ),
        .\not_strict_mode.status_ram.rd_buf_we_r1_reg (u_ui_top_n_0),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .p_106_out(\mc0/bank_mach0/p_106_out ),
        .p_145_out(\mc0/bank_mach0/p_145_out ),
        .p_28_out(\mc0/bank_mach0/p_28_out ),
        .p_67_out(\mc0/bank_mach0/p_67_out ),
        .periodic_rd_ack_r(\mc0/periodic_rd_ack_r ),
        .periodic_rd_cntr_r(\mc0/bank_mach0/bank_common0/periodic_rd_cntr_r ),
        .periodic_rd_r(\mc0/periodic_rd_r ),
        .phy_dout(phy_dout),
        .pll_lock(pll_lock),
        .pointer_we(\ui_wr_data0/pointer_we ),
        .ram_init_addr(ram_init_addr),
        .ram_init_done_r(ram_init_done_r),
        .ras_timer_zero_r_reg(bm_end_r1_1),
        .ras_timer_zero_r_reg_0(bm_end_r1_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (mem_intfc0_n_78),
        .rd_buf_we(\ui_rd_data0/rd_buf_we ),
        .\rd_ptr_reg_rep[3] (\rd_ptr_reg_rep[3] ),
        .\rd_ptr_reg_rep[3]_0 (\rd_ptr_reg_rep[3]_0 ),
        .\rd_ptr_reg_rep[3]_1 (\rd_ptr_reg_rep[3]_1 ),
        .\rd_ptr_reg_rep[3]_2 (\rd_ptr_reg_rep[3]_2 ),
        .\rd_ptr_reg_rep[3]_3 (\rd_ptr_reg_rep[3]_3 ),
        .\rd_ptr_reg_rep[3]_4 (\rd_ptr_reg_rep[3]_4 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1]_0 ),
        .\rd_ptr_timing_reg[1]_1 (\rd_ptr_timing_reg[1]_1 ),
        .rdlvl_stg1_start_r_reg(rdlvl_stg1_start_r_reg),
        .\read_fifo.fifo_out_data_r_reg[5] (\read_fifo.fifo_out_data_r_reg[5] ),
        .\read_fifo.fifo_out_data_r_reg[5]_0 (u_ui_top_n_523),
        .row(row),
        .rst_sync_r1_reg(rst_sync_r1_reg),
        .rstdiv0_sync_r1(rstdiv0_sync_r1),
        .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),
        .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),
        .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),
        .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),
        .rstdiv0_sync_r1_reg_rep__15(rstdiv0_sync_r1_reg_rep__15),
        .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),
        .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__20_0(rstdiv0_sync_r1_reg_rep__20_0),
        .rstdiv0_sync_r1_reg_rep__20_1(rstdiv0_sync_r1_reg_rep__20_1),
        .rstdiv0_sync_r1_reg_rep__20_2(rstdiv0_sync_r1_reg_rep__20_2),
        .rstdiv0_sync_r1_reg_rep__20_3(rstdiv0_sync_r1_reg_rep__20_3),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),
        .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),
        .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),
        .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0),
        .rstdiv0_sync_r1_reg_rep__24_1(D),
        .rstdiv0_sync_r1_reg_rep__24_2(rstdiv0_sync_r1_reg_rep__24_1),
        .rstdiv0_sync_r1_reg_rep__24_3(rstdiv0_sync_r1_reg_rep__24_2),
        .rstdiv0_sync_r1_reg_rep__24_4(rstdiv0_sync_r1_reg_rep__24_3),
        .rstdiv0_sync_r1_reg_rep__3(rstdiv0_sync_r1_reg_rep__3),
        .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),
        .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),
        .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),
        .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .sync_pulse(sync_pulse),
        .sys_rst(sys_rst),
        .sys_rst_0(sys_rst_0),
        .sys_rst_1(sys_rst_1),
        .was_wr0(\mc0/bank_mach0/bank_common0/was_wr0 ),
        .wr_en(wr_en),
        .wr_en_10(wr_en_10),
        .wr_en_11(wr_en_11),
        .wr_en_12(wr_en_12),
        .wr_en_13(wr_en_13),
        .wr_en_14(wr_en_14),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[0]_1 (\wr_ptr_reg[0]_1 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[1]_1 (\wr_ptr_reg[1]_1 ),
        .\wr_ptr_reg[1]_2 (\wr_ptr_reg[1]_2 ),
        .\wr_ptr_reg[1]_3 (\wr_ptr_reg[1]_3 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0]_1 ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3]_0 ),
        .\wr_ptr_timing_reg[3]_1 (\wr_ptr_timing_reg[3]_1 ),
        .\wr_ptr_timing_reg[3]_2 (\wr_ptr_timing_reg[3]_2 ),
        .\wr_ptr_timing_reg[3]_3 (\wr_ptr_timing_reg[3]_3 ),
        .\wr_ptr_timing_reg[3]_4 (\wr_ptr_timing_reg[3]_4 ),
        .\write_buffer.wr_buf_out_data_reg[351] ({\ddr_phy_top0/mux_wrdata [351],\ddr_phy_top0/mux_wrdata [347],\ddr_phy_top0/mux_wrdata [343],\ddr_phy_top0/mux_wrdata [339],\ddr_phy_top0/mux_wrdata [335],\ddr_phy_top0/mux_wrdata [331],\ddr_phy_top0/mux_wrdata [327],\ddr_phy_top0/mux_wrdata [323],\ddr_phy_top0/mux_wrdata [286],\ddr_phy_top0/mux_wrdata [282],\ddr_phy_top0/mux_wrdata [278],\ddr_phy_top0/mux_wrdata [274],\ddr_phy_top0/mux_wrdata [270],\ddr_phy_top0/mux_wrdata [266],\ddr_phy_top0/mux_wrdata [262],\ddr_phy_top0/mux_wrdata [258],\ddr_phy_top0/mux_wrdata [222],\ddr_phy_top0/mux_wrdata [218],\ddr_phy_top0/mux_wrdata [214],\ddr_phy_top0/mux_wrdata [210],\ddr_phy_top0/mux_wrdata [206],\ddr_phy_top0/mux_wrdata [202],\ddr_phy_top0/mux_wrdata [198],\ddr_phy_top0/mux_wrdata [194],\ddr_phy_top0/mux_wrdata [157],\ddr_phy_top0/mux_wrdata [153],\ddr_phy_top0/mux_wrdata [149],\ddr_phy_top0/mux_wrdata [145],\ddr_phy_top0/mux_wrdata [141],\ddr_phy_top0/mux_wrdata [137],\ddr_phy_top0/mux_wrdata [133],\ddr_phy_top0/mux_wrdata [129],\ddr_phy_top0/mux_wrdata [31],\ddr_phy_top0/mux_wrdata [28:27],\ddr_phy_top0/mux_wrdata [24:23],\ddr_phy_top0/mux_wrdata [20:19],\ddr_phy_top0/mux_wrdata [16:15],\ddr_phy_top0/mux_wrdata [12:11],\ddr_phy_top0/mux_wrdata [8:7],\ddr_phy_top0/mux_wrdata [4:3],\ddr_phy_top0/mux_wrdata [0]}),
        .\write_buffer.wr_buf_out_data_reg[389] (wr_data_addr),
        .\write_buffer.wr_buf_out_data_reg[53] ({mem_intfc0_n_1710,mem_intfc0_n_1711,mem_intfc0_n_1712,mem_intfc0_n_1713}),
        .\write_buffer.wr_buf_out_data_reg[575] ({wr_data_mask,wr_data}));
  FDRE reset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r1_reg_rep__24),
        .Q(reset_reg_n_0),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_ui_top u_ui_top
       (.ADDRC({mem_intfc0_n_1706,mem_intfc0_n_1707,mem_intfc0_n_1708,mem_intfc0_n_1709}),
        .CLK(CLK),
        .D(app_rd_data_ns),
        .DIA({mem_intfc0_n_189,mem_intfc0_n_190}),
        .DIB({mem_intfc0_n_542,mem_intfc0_n_193}),
        .DIC({mem_intfc0_n_195,mem_intfc0_n_194}),
        .DOA(\ui_rd_data0/p_258_out ),
        .DOB(\ui_rd_data0/p_257_out ),
        .DOC(\ui_rd_data0/p_256_out ),
        .E(wr_data_en),
        .Q(\ui_cmd0/app_cmd_r1 ),
        .S(u_ui_top_n_529),
        .accept_ns(accept_ns),
        .app_addr(app_addr),
        .app_cmd(app_cmd),
        .app_en(app_en),
        .app_en_r2(\ui_cmd0/app_en_r2 ),
        .app_rd_data(app_rd_data),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_end_ns(\ui_rd_data0/app_rd_data_end_ns ),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rdy(E),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .\cmd_pipe_plus.wr_data_addr_reg[3] (wr_data_addr),
        .\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ({mem_intfc0_n_1710,mem_intfc0_n_1711,mem_intfc0_n_1712,mem_intfc0_n_1713}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ({mem_intfc0_n_170,mem_intfc0_n_171}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ({mem_intfc0_n_97,mem_intfc0_n_98}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ({mem_intfc0_n_347,mem_intfc0_n_348}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ({mem_intfc0_n_645,mem_intfc0_n_646}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ({mem_intfc0_n_873,mem_intfc0_n_874}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ({mem_intfc0_n_641,mem_intfc0_n_642}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ({mem_intfc0_n_871,mem_intfc0_n_872}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ({mem_intfc0_n_639,mem_intfc0_n_640}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ({mem_intfc0_n_637,mem_intfc0_n_638}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ({mem_intfc0_n_865,mem_intfc0_n_866}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ({mem_intfc0_n_633,mem_intfc0_n_634}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ({mem_intfc0_n_863,mem_intfc0_n_864}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ({mem_intfc0_n_631,mem_intfc0_n_632}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ({mem_intfc0_n_629,mem_intfc0_n_630}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ({mem_intfc0_n_857,mem_intfc0_n_858}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ({mem_intfc0_n_625,mem_intfc0_n_626}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ({mem_intfc0_n_855,mem_intfc0_n_856}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ({mem_intfc0_n_623,mem_intfc0_n_624}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ({mem_intfc0_n_621,mem_intfc0_n_622}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ({mem_intfc0_n_849,mem_intfc0_n_850}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ({mem_intfc0_n_617,mem_intfc0_n_618}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ({mem_intfc0_n_847,mem_intfc0_n_848}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ({mem_intfc0_n_615,mem_intfc0_n_616}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ({mem_intfc0_n_613,mem_intfc0_n_614}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ({mem_intfc0_n_841,mem_intfc0_n_842}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ({mem_intfc0_n_609,mem_intfc0_n_610}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ({mem_intfc0_n_839,mem_intfc0_n_840}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ({mem_intfc0_n_607,mem_intfc0_n_608}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ({mem_intfc0_n_605,mem_intfc0_n_606}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ({mem_intfc0_n_833,mem_intfc0_n_834}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ({mem_intfc0_n_601,mem_intfc0_n_602}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ({mem_intfc0_n_831,mem_intfc0_n_832}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ({mem_intfc0_n_599,mem_intfc0_n_600}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ({mem_intfc0_n_168,mem_intfc0_n_169}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ({mem_intfc0_n_95,mem_intfc0_n_96}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ({mem_intfc0_n_345,mem_intfc0_n_346}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ({mem_intfc0_n_821,mem_intfc0_n_822}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ({mem_intfc0_n_595,mem_intfc0_n_596}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ({mem_intfc0_n_819,mem_intfc0_n_820}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ({mem_intfc0_n_813,mem_intfc0_n_814}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ({mem_intfc0_n_587,mem_intfc0_n_588}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ({mem_intfc0_n_811,mem_intfc0_n_812}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ({mem_intfc0_n_805,mem_intfc0_n_806}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ({mem_intfc0_n_579,mem_intfc0_n_580}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ({mem_intfc0_n_803,mem_intfc0_n_804}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ({mem_intfc0_n_877,mem_intfc0_n_878}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ({mem_intfc0_n_651,mem_intfc0_n_652}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ({mem_intfc0_n_875,mem_intfc0_n_876}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ({mem_intfc0_n_797,mem_intfc0_n_798}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ({mem_intfc0_n_571,mem_intfc0_n_572}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ({mem_intfc0_n_795,mem_intfc0_n_796}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ({mem_intfc0_n_789,mem_intfc0_n_790}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ({mem_intfc0_n_563,mem_intfc0_n_564}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ({mem_intfc0_n_787,mem_intfc0_n_788}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ({mem_intfc0_n_781,mem_intfc0_n_782}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ({mem_intfc0_n_555,mem_intfc0_n_556}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ({mem_intfc0_n_779,mem_intfc0_n_780}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ({mem_intfc0_n_773,mem_intfc0_n_774}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ({mem_intfc0_n_547,mem_intfc0_n_548}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ({mem_intfc0_n_771,mem_intfc0_n_772}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ({mem_intfc0_n_182,mem_intfc0_n_183}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ({mem_intfc0_n_175,mem_intfc0_n_176}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ({mem_intfc0_n_197,mem_intfc0_n_198}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ({mem_intfc0_n_270,mem_intfc0_n_271}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ({mem_intfc0_n_597,mem_intfc0_n_598}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ({mem_intfc0_n_825,mem_intfc0_n_826}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ({mem_intfc0_n_593,mem_intfc0_n_594}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ({mem_intfc0_n_823,mem_intfc0_n_824}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ({mem_intfc0_n_591,mem_intfc0_n_592}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ({mem_intfc0_n_589,mem_intfc0_n_590}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ({mem_intfc0_n_817,mem_intfc0_n_818}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ({mem_intfc0_n_585,mem_intfc0_n_586}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ({mem_intfc0_n_815,mem_intfc0_n_816}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ({mem_intfc0_n_583,mem_intfc0_n_584}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ({mem_intfc0_n_581,mem_intfc0_n_582}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ({mem_intfc0_n_809,mem_intfc0_n_810}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ({mem_intfc0_n_577,mem_intfc0_n_578}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ({mem_intfc0_n_807,mem_intfc0_n_808}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ({mem_intfc0_n_575,mem_intfc0_n_576}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ({mem_intfc0_n_573,mem_intfc0_n_574}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ({mem_intfc0_n_801,mem_intfc0_n_802}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ({mem_intfc0_n_569,mem_intfc0_n_570}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ({mem_intfc0_n_799,mem_intfc0_n_800}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ({mem_intfc0_n_567,mem_intfc0_n_568}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ({mem_intfc0_n_565,mem_intfc0_n_566}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ({mem_intfc0_n_793,mem_intfc0_n_794}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ({mem_intfc0_n_561,mem_intfc0_n_562}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ({mem_intfc0_n_791,mem_intfc0_n_792}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ({mem_intfc0_n_559,mem_intfc0_n_560}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ({mem_intfc0_n_869,mem_intfc0_n_870}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ({mem_intfc0_n_643,mem_intfc0_n_644}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ({mem_intfc0_n_867,mem_intfc0_n_868}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ({mem_intfc0_n_557,mem_intfc0_n_558}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ({mem_intfc0_n_785,mem_intfc0_n_786}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ({mem_intfc0_n_553,mem_intfc0_n_554}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ({mem_intfc0_n_783,mem_intfc0_n_784}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ({mem_intfc0_n_551,mem_intfc0_n_552}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ({mem_intfc0_n_549,mem_intfc0_n_550}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ({mem_intfc0_n_777,mem_intfc0_n_778}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ({mem_intfc0_n_545,mem_intfc0_n_546}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ({mem_intfc0_n_775,mem_intfc0_n_776}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ({mem_intfc0_n_543,mem_intfc0_n_544}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ({mem_intfc0_n_768,mem_intfc0_n_172}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ({mem_intfc0_n_541,mem_intfc0_n_99}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ({mem_intfc0_n_767,mem_intfc0_n_349}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ({mem_intfc0_n_761,mem_intfc0_n_762}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ({mem_intfc0_n_535,mem_intfc0_n_536}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ({mem_intfc0_n_759,mem_intfc0_n_760}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ({mem_intfc0_n_753,mem_intfc0_n_754}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ({mem_intfc0_n_527,mem_intfc0_n_528}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ({mem_intfc0_n_751,mem_intfc0_n_752}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ({mem_intfc0_n_745,mem_intfc0_n_746}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ({mem_intfc0_n_519,mem_intfc0_n_520}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ({mem_intfc0_n_743,mem_intfc0_n_744}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ({mem_intfc0_n_737,mem_intfc0_n_738}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ({mem_intfc0_n_511,mem_intfc0_n_512}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ({mem_intfc0_n_735,mem_intfc0_n_736}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ({mem_intfc0_n_729,mem_intfc0_n_730}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ({mem_intfc0_n_503,mem_intfc0_n_504}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ({mem_intfc0_n_727,mem_intfc0_n_728}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ({mem_intfc0_n_721,mem_intfc0_n_722}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ({mem_intfc0_n_495,mem_intfc0_n_496}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ({mem_intfc0_n_719,mem_intfc0_n_720}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ({mem_intfc0_n_713,mem_intfc0_n_714}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ({mem_intfc0_n_487,mem_intfc0_n_488}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ({mem_intfc0_n_711,mem_intfc0_n_712}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ({mem_intfc0_n_861,mem_intfc0_n_862}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ({mem_intfc0_n_635,mem_intfc0_n_636}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ({mem_intfc0_n_859,mem_intfc0_n_860}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ({mem_intfc0_n_770,mem_intfc0_n_186}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ({mem_intfc0_n_769,mem_intfc0_n_201}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ({mem_intfc0_n_537,mem_intfc0_n_538}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ({mem_intfc0_n_765,mem_intfc0_n_766}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ({mem_intfc0_n_763,mem_intfc0_n_764}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ({mem_intfc0_n_529,mem_intfc0_n_530}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ({mem_intfc0_n_757,mem_intfc0_n_758}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ({mem_intfc0_n_755,mem_intfc0_n_756}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ({mem_intfc0_n_521,mem_intfc0_n_522}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ({mem_intfc0_n_749,mem_intfc0_n_750}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ({mem_intfc0_n_747,mem_intfc0_n_748}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ({mem_intfc0_n_513,mem_intfc0_n_514}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ({mem_intfc0_n_741,mem_intfc0_n_742}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ({mem_intfc0_n_739,mem_intfc0_n_740}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ({mem_intfc0_n_505,mem_intfc0_n_506}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ({mem_intfc0_n_733,mem_intfc0_n_734}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ({mem_intfc0_n_731,mem_intfc0_n_732}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ({mem_intfc0_n_497,mem_intfc0_n_498}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ({mem_intfc0_n_725,mem_intfc0_n_726}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ({mem_intfc0_n_723,mem_intfc0_n_724}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ({mem_intfc0_n_489,mem_intfc0_n_490}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ({mem_intfc0_n_717,mem_intfc0_n_718}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ({mem_intfc0_n_715,mem_intfc0_n_716}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ({mem_intfc0_n_540,mem_intfc0_n_179}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ({mem_intfc0_n_174,mem_intfc0_n_173}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ({mem_intfc0_n_167,mem_intfc0_n_166}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ({mem_intfc0_n_539,mem_intfc0_n_274}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ({mem_intfc0_n_417,mem_intfc0_n_416}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ({mem_intfc0_n_533,mem_intfc0_n_534}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ({mem_intfc0_n_705,mem_intfc0_n_706}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ({mem_intfc0_n_479,mem_intfc0_n_480}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ({mem_intfc0_n_531,mem_intfc0_n_532}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ({mem_intfc0_n_703,mem_intfc0_n_704}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ({mem_intfc0_n_853,mem_intfc0_n_854}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ({mem_intfc0_n_627,mem_intfc0_n_628}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ({mem_intfc0_n_851,mem_intfc0_n_852}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ({mem_intfc0_n_525,mem_intfc0_n_526}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ({mem_intfc0_n_697,mem_intfc0_n_698}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ({mem_intfc0_n_471,mem_intfc0_n_472}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ({mem_intfc0_n_523,mem_intfc0_n_524}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ({mem_intfc0_n_695,mem_intfc0_n_696}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ({mem_intfc0_n_517,mem_intfc0_n_518}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ({mem_intfc0_n_689,mem_intfc0_n_690}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ({mem_intfc0_n_463,mem_intfc0_n_464}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ({mem_intfc0_n_515,mem_intfc0_n_516}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ({mem_intfc0_n_687,mem_intfc0_n_688}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ({mem_intfc0_n_509,mem_intfc0_n_510}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ({mem_intfc0_n_681,mem_intfc0_n_682}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ({mem_intfc0_n_455,mem_intfc0_n_456}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ({mem_intfc0_n_507,mem_intfc0_n_508}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ({mem_intfc0_n_679,mem_intfc0_n_680}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ({mem_intfc0_n_501,mem_intfc0_n_502}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ({mem_intfc0_n_673,mem_intfc0_n_674}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ({mem_intfc0_n_447,mem_intfc0_n_448}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ({mem_intfc0_n_499,mem_intfc0_n_500}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ({mem_intfc0_n_671,mem_intfc0_n_672}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ({mem_intfc0_n_493,mem_intfc0_n_494}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ({mem_intfc0_n_665,mem_intfc0_n_666}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ({mem_intfc0_n_439,mem_intfc0_n_440}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ({mem_intfc0_n_491,mem_intfc0_n_492}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ({mem_intfc0_n_663,mem_intfc0_n_664}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ({mem_intfc0_n_485,mem_intfc0_n_486}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ({mem_intfc0_n_657,mem_intfc0_n_658}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ({mem_intfc0_n_431,mem_intfc0_n_432}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ({mem_intfc0_n_483,mem_intfc0_n_484}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ({mem_intfc0_n_655,mem_intfc0_n_656}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ({mem_intfc0_n_188,mem_intfc0_n_187}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ({mem_intfc0_n_269,mem_intfc0_n_268}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ({mem_intfc0_n_481,mem_intfc0_n_482}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ({mem_intfc0_n_709,mem_intfc0_n_710}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ({mem_intfc0_n_707,mem_intfc0_n_708}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ({mem_intfc0_n_473,mem_intfc0_n_474}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ({mem_intfc0_n_701,mem_intfc0_n_702}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ({mem_intfc0_n_699,mem_intfc0_n_700}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ({mem_intfc0_n_465,mem_intfc0_n_466}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ({mem_intfc0_n_693,mem_intfc0_n_694}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ({mem_intfc0_n_691,mem_intfc0_n_692}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ({mem_intfc0_n_845,mem_intfc0_n_846}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ({mem_intfc0_n_619,mem_intfc0_n_620}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ({mem_intfc0_n_843,mem_intfc0_n_844}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ({mem_intfc0_n_457,mem_intfc0_n_458}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ({mem_intfc0_n_685,mem_intfc0_n_686}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ({mem_intfc0_n_683,mem_intfc0_n_684}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ({mem_intfc0_n_449,mem_intfc0_n_450}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ({mem_intfc0_n_677,mem_intfc0_n_678}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ({mem_intfc0_n_675,mem_intfc0_n_676}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ({mem_intfc0_n_441,mem_intfc0_n_442}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ({mem_intfc0_n_669,mem_intfc0_n_670}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ({mem_intfc0_n_667,mem_intfc0_n_668}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ({mem_intfc0_n_433,mem_intfc0_n_434}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ({mem_intfc0_n_661,mem_intfc0_n_662}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ({mem_intfc0_n_659,mem_intfc0_n_660}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ({mem_intfc0_n_181,mem_intfc0_n_180}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ({mem_intfc0_n_344,mem_intfc0_n_343}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ({mem_intfc0_n_477,mem_intfc0_n_478}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ({mem_intfc0_n_475,mem_intfc0_n_476}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ({mem_intfc0_n_469,mem_intfc0_n_470}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ({mem_intfc0_n_467,mem_intfc0_n_468}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ({mem_intfc0_n_461,mem_intfc0_n_462}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ({mem_intfc0_n_459,mem_intfc0_n_460}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ({mem_intfc0_n_453,mem_intfc0_n_454}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ({mem_intfc0_n_451,mem_intfc0_n_452}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ({mem_intfc0_n_445,mem_intfc0_n_446}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ({mem_intfc0_n_443,mem_intfc0_n_444}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ({mem_intfc0_n_837,mem_intfc0_n_838}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ({mem_intfc0_n_611,mem_intfc0_n_612}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ({mem_intfc0_n_835,mem_intfc0_n_836}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ({mem_intfc0_n_437,mem_intfc0_n_438}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ({mem_intfc0_n_435,mem_intfc0_n_436}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ({mem_intfc0_n_429,mem_intfc0_n_430}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ({mem_intfc0_n_427,mem_intfc0_n_428}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ({mem_intfc0_n_829,mem_intfc0_n_830}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ({mem_intfc0_n_603,mem_intfc0_n_604}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ({mem_intfc0_n_827,mem_intfc0_n_828}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ({mem_intfc0_n_191,mem_intfc0_n_192}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ({mem_intfc0_n_184,mem_intfc0_n_185}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ({mem_intfc0_n_177,mem_intfc0_n_178}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ({mem_intfc0_n_199,mem_intfc0_n_200}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ({mem_intfc0_n_272,mem_intfc0_n_273}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ({mem_intfc0_n_653,mem_intfc0_n_654}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ({mem_intfc0_n_881,mem_intfc0_n_882}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ({mem_intfc0_n_649,mem_intfc0_n_650}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ({mem_intfc0_n_879,mem_intfc0_n_880}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ({mem_intfc0_n_647,mem_intfc0_n_648}),
        .idle_r_lcl_reg(mem_intfc0_n_81),
        .idle_r_lcl_reg_0(mem_intfc0_n_80),
        .idle_r_lcl_reg_1(mem_intfc0_n_79),
        .idle_r_lcl_reg_2(mem_intfc0_n_78),
        .init_calib_complete_reg_rep__19(mem_intfc0_n_61),
        .init_calib_complete_reg_rep__20(mem_intfc0_n_62),
        .init_calib_complete_reg_rep__21(mem_intfc0_n_63),
        .init_calib_complete_reg_rep__22(mem_intfc0_n_64),
        .init_calib_complete_reg_rep__23(mem_intfc0_n_65),
        .init_calib_complete_reg_rep__24(mem_intfc0_n_66),
        .init_calib_complete_reg_rep__25(mem_intfc0_n_67),
        .init_calib_complete_reg_rep__26(mem_intfc0_n_68),
        .init_calib_complete_reg_rep__27(mem_intfc0_n_69),
        .\my_empty_reg[7] ({\my_empty_reg[7]_3 [191],\my_empty_reg[7]_3 [187],\my_empty_reg[7]_3 [183],\my_empty_reg[7]_3 [179],\my_empty_reg[7]_3 [175],\my_empty_reg[7]_3 [171],\my_empty_reg[7]_3 [167],\my_empty_reg[7]_3 [163],\my_empty_reg[7]_3 [158],\my_empty_reg[7]_3 [154],\my_empty_reg[7]_3 [150],\my_empty_reg[7]_3 [146],\my_empty_reg[7]_3 [142],\my_empty_reg[7]_3 [138],\my_empty_reg[7]_3 [134],\my_empty_reg[7]_3 [130],\my_empty_reg[7]_3 [126],\my_empty_reg[7]_3 [122],\my_empty_reg[7]_3 [118],\my_empty_reg[7]_3 [114],\my_empty_reg[7]_3 [110],\my_empty_reg[7]_3 [106],\my_empty_reg[7]_3 [102],\my_empty_reg[7]_3 [98],\my_empty_reg[7]_3 [93],\my_empty_reg[7]_3 [89],\my_empty_reg[7]_3 [85],\my_empty_reg[7]_3 [81],\my_empty_reg[7]_3 [77],\my_empty_reg[7]_3 [73],\my_empty_reg[7]_3 [69],\my_empty_reg[7]_3 [65],\my_empty_reg[7]_3 [31],\my_empty_reg[7]_3 [28:27],\my_empty_reg[7]_3 [24:23],\my_empty_reg[7]_3 [20:19],\my_empty_reg[7]_3 [16:15],\my_empty_reg[7]_3 [12:11],\my_empty_reg[7]_3 [8:7],\my_empty_reg[7]_3 [4:3],\my_empty_reg[7]_3 [0]}),
        .\my_empty_reg[7]_0 ({wr_data_mask,wr_data}),
        .\my_empty_reg[7]_1 ({\ddr_phy_top0/mux_wrdata [351],\ddr_phy_top0/mux_wrdata [347],\ddr_phy_top0/mux_wrdata [343],\ddr_phy_top0/mux_wrdata [339],\ddr_phy_top0/mux_wrdata [335],\ddr_phy_top0/mux_wrdata [331],\ddr_phy_top0/mux_wrdata [327],\ddr_phy_top0/mux_wrdata [323],\ddr_phy_top0/mux_wrdata [286],\ddr_phy_top0/mux_wrdata [282],\ddr_phy_top0/mux_wrdata [278],\ddr_phy_top0/mux_wrdata [274],\ddr_phy_top0/mux_wrdata [270],\ddr_phy_top0/mux_wrdata [266],\ddr_phy_top0/mux_wrdata [262],\ddr_phy_top0/mux_wrdata [258],\ddr_phy_top0/mux_wrdata [222],\ddr_phy_top0/mux_wrdata [218],\ddr_phy_top0/mux_wrdata [214],\ddr_phy_top0/mux_wrdata [210],\ddr_phy_top0/mux_wrdata [206],\ddr_phy_top0/mux_wrdata [202],\ddr_phy_top0/mux_wrdata [198],\ddr_phy_top0/mux_wrdata [194],\ddr_phy_top0/mux_wrdata [157],\ddr_phy_top0/mux_wrdata [153],\ddr_phy_top0/mux_wrdata [149],\ddr_phy_top0/mux_wrdata [145],\ddr_phy_top0/mux_wrdata [141],\ddr_phy_top0/mux_wrdata [137],\ddr_phy_top0/mux_wrdata [133],\ddr_phy_top0/mux_wrdata [129],\ddr_phy_top0/mux_wrdata [31],\ddr_phy_top0/mux_wrdata [28:27],\ddr_phy_top0/mux_wrdata [24:23],\ddr_phy_top0/mux_wrdata [20:19],\ddr_phy_top0/mux_wrdata [16:15],\ddr_phy_top0/mux_wrdata [12:11],\ddr_phy_top0/mux_wrdata [8:7],\ddr_phy_top0/mux_wrdata [4:3],\ddr_phy_top0/mux_wrdata [0]}),
        .\not_strict_mode.app_rd_data_end_reg (u_ui_top_n_0),
        .\not_strict_mode.app_rd_data_reg[101] (\ui_rd_data0/p_209_out ),
        .\not_strict_mode.app_rd_data_reg[103] (\ui_rd_data0/p_204_out ),
        .\not_strict_mode.app_rd_data_reg[105] (\ui_rd_data0/p_205_out ),
        .\not_strict_mode.app_rd_data_reg[107] (\ui_rd_data0/p_206_out ),
        .\not_strict_mode.app_rd_data_reg[109] (\ui_rd_data0/p_201_out ),
        .\not_strict_mode.app_rd_data_reg[111] (\ui_rd_data0/p_202_out ),
        .\not_strict_mode.app_rd_data_reg[113] (\ui_rd_data0/p_203_out ),
        .\not_strict_mode.app_rd_data_reg[115] (\ui_rd_data0/p_198_out ),
        .\not_strict_mode.app_rd_data_reg[117] (\ui_rd_data0/p_199_out ),
        .\not_strict_mode.app_rd_data_reg[119] (\ui_rd_data0/p_200_out ),
        .\not_strict_mode.app_rd_data_reg[11] (\ui_rd_data0/p_254_out ),
        .\not_strict_mode.app_rd_data_reg[121] (\ui_rd_data0/p_195_out ),
        .\not_strict_mode.app_rd_data_reg[123] (\ui_rd_data0/p_196_out ),
        .\not_strict_mode.app_rd_data_reg[125] (\ui_rd_data0/p_197_out ),
        .\not_strict_mode.app_rd_data_reg[127] (\ui_rd_data0/p_192_out ),
        .\not_strict_mode.app_rd_data_reg[129] (\ui_rd_data0/p_193_out ),
        .\not_strict_mode.app_rd_data_reg[131] (\ui_rd_data0/p_194_out ),
        .\not_strict_mode.app_rd_data_reg[133] (\ui_rd_data0/p_189_out ),
        .\not_strict_mode.app_rd_data_reg[135] (\ui_rd_data0/p_190_out ),
        .\not_strict_mode.app_rd_data_reg[137] (\ui_rd_data0/p_191_out ),
        .\not_strict_mode.app_rd_data_reg[139] (\ui_rd_data0/p_186_out ),
        .\not_strict_mode.app_rd_data_reg[13] (\ui_rd_data0/p_249_out ),
        .\not_strict_mode.app_rd_data_reg[141] (\ui_rd_data0/p_187_out ),
        .\not_strict_mode.app_rd_data_reg[143] (\ui_rd_data0/p_188_out ),
        .\not_strict_mode.app_rd_data_reg[145] (\ui_rd_data0/p_183_out ),
        .\not_strict_mode.app_rd_data_reg[147] (\ui_rd_data0/p_184_out ),
        .\not_strict_mode.app_rd_data_reg[149] (\ui_rd_data0/p_185_out ),
        .\not_strict_mode.app_rd_data_reg[151] (\ui_rd_data0/p_180_out ),
        .\not_strict_mode.app_rd_data_reg[153] (\ui_rd_data0/p_181_out ),
        .\not_strict_mode.app_rd_data_reg[155] (\ui_rd_data0/p_182_out ),
        .\not_strict_mode.app_rd_data_reg[157] (\ui_rd_data0/p_177_out ),
        .\not_strict_mode.app_rd_data_reg[159] (\ui_rd_data0/p_178_out ),
        .\not_strict_mode.app_rd_data_reg[15] (\ui_rd_data0/p_250_out ),
        .\not_strict_mode.app_rd_data_reg[161] (\ui_rd_data0/p_179_out ),
        .\not_strict_mode.app_rd_data_reg[163] (\ui_rd_data0/p_174_out ),
        .\not_strict_mode.app_rd_data_reg[165] (\ui_rd_data0/p_175_out ),
        .\not_strict_mode.app_rd_data_reg[167] (\ui_rd_data0/p_176_out ),
        .\not_strict_mode.app_rd_data_reg[169] (\ui_rd_data0/p_171_out ),
        .\not_strict_mode.app_rd_data_reg[171] (\ui_rd_data0/p_172_out ),
        .\not_strict_mode.app_rd_data_reg[173] (\ui_rd_data0/p_173_out ),
        .\not_strict_mode.app_rd_data_reg[175] (\ui_rd_data0/p_168_out ),
        .\not_strict_mode.app_rd_data_reg[177] (\ui_rd_data0/p_169_out ),
        .\not_strict_mode.app_rd_data_reg[179] (\ui_rd_data0/p_170_out ),
        .\not_strict_mode.app_rd_data_reg[17] (\ui_rd_data0/p_251_out ),
        .\not_strict_mode.app_rd_data_reg[181] (\ui_rd_data0/p_165_out ),
        .\not_strict_mode.app_rd_data_reg[183] (\ui_rd_data0/p_166_out ),
        .\not_strict_mode.app_rd_data_reg[185] (\ui_rd_data0/p_167_out ),
        .\not_strict_mode.app_rd_data_reg[187] (\ui_rd_data0/p_162_out ),
        .\not_strict_mode.app_rd_data_reg[189] (\ui_rd_data0/p_163_out ),
        .\not_strict_mode.app_rd_data_reg[191] (\ui_rd_data0/p_164_out ),
        .\not_strict_mode.app_rd_data_reg[193] (\ui_rd_data0/p_159_out ),
        .\not_strict_mode.app_rd_data_reg[195] (\ui_rd_data0/p_160_out ),
        .\not_strict_mode.app_rd_data_reg[197] (\ui_rd_data0/p_161_out ),
        .\not_strict_mode.app_rd_data_reg[199] (\ui_rd_data0/p_156_out ),
        .\not_strict_mode.app_rd_data_reg[19] (\ui_rd_data0/p_246_out ),
        .\not_strict_mode.app_rd_data_reg[201] (\ui_rd_data0/p_157_out ),
        .\not_strict_mode.app_rd_data_reg[203] (\ui_rd_data0/p_158_out ),
        .\not_strict_mode.app_rd_data_reg[205] (\ui_rd_data0/p_153_out ),
        .\not_strict_mode.app_rd_data_reg[207] (\ui_rd_data0/p_154_out ),
        .\not_strict_mode.app_rd_data_reg[209] (\ui_rd_data0/p_155_out ),
        .\not_strict_mode.app_rd_data_reg[211] (\ui_rd_data0/p_150_out ),
        .\not_strict_mode.app_rd_data_reg[213] (\ui_rd_data0/p_151_out ),
        .\not_strict_mode.app_rd_data_reg[215] (\ui_rd_data0/p_152_out ),
        .\not_strict_mode.app_rd_data_reg[217] (\ui_rd_data0/p_147_out ),
        .\not_strict_mode.app_rd_data_reg[219] (\ui_rd_data0/p_148_out ),
        .\not_strict_mode.app_rd_data_reg[21] (\ui_rd_data0/p_247_out ),
        .\not_strict_mode.app_rd_data_reg[221] (\ui_rd_data0/p_149_out ),
        .\not_strict_mode.app_rd_data_reg[223] (\ui_rd_data0/p_144_out ),
        .\not_strict_mode.app_rd_data_reg[225] (\ui_rd_data0/p_145_out ),
        .\not_strict_mode.app_rd_data_reg[227] (\ui_rd_data0/p_146_out ),
        .\not_strict_mode.app_rd_data_reg[229] (\ui_rd_data0/p_141_out ),
        .\not_strict_mode.app_rd_data_reg[231] (\ui_rd_data0/p_142_out ),
        .\not_strict_mode.app_rd_data_reg[233] (\ui_rd_data0/p_143_out ),
        .\not_strict_mode.app_rd_data_reg[235] (\ui_rd_data0/p_138_out ),
        .\not_strict_mode.app_rd_data_reg[237] (\ui_rd_data0/p_139_out ),
        .\not_strict_mode.app_rd_data_reg[239] (\ui_rd_data0/p_140_out ),
        .\not_strict_mode.app_rd_data_reg[23] (\ui_rd_data0/p_248_out ),
        .\not_strict_mode.app_rd_data_reg[241] (\ui_rd_data0/p_135_out ),
        .\not_strict_mode.app_rd_data_reg[243] (\ui_rd_data0/p_136_out ),
        .\not_strict_mode.app_rd_data_reg[245] (\ui_rd_data0/p_137_out ),
        .\not_strict_mode.app_rd_data_reg[247] (\ui_rd_data0/p_132_out ),
        .\not_strict_mode.app_rd_data_reg[249] (\ui_rd_data0/p_133_out ),
        .\not_strict_mode.app_rd_data_reg[24] (u_ui_top_n_523),
        .\not_strict_mode.app_rd_data_reg[251] (\ui_rd_data0/p_134_out ),
        .\not_strict_mode.app_rd_data_reg[253] (\ui_rd_data0/p_129_out ),
        .\not_strict_mode.app_rd_data_reg[255] (\ui_rd_data0/p_130_out ),
        .\not_strict_mode.app_rd_data_reg[257] (\ui_rd_data0/p_131_out ),
        .\not_strict_mode.app_rd_data_reg[259] (\ui_rd_data0/p_126_out ),
        .\not_strict_mode.app_rd_data_reg[25] (\ui_rd_data0/p_243_out ),
        .\not_strict_mode.app_rd_data_reg[261] (\ui_rd_data0/p_127_out ),
        .\not_strict_mode.app_rd_data_reg[263] (\ui_rd_data0/p_128_out ),
        .\not_strict_mode.app_rd_data_reg[265] (\ui_rd_data0/p_123_out ),
        .\not_strict_mode.app_rd_data_reg[267] (\ui_rd_data0/p_124_out ),
        .\not_strict_mode.app_rd_data_reg[269] (\ui_rd_data0/p_125_out ),
        .\not_strict_mode.app_rd_data_reg[271] (\ui_rd_data0/p_120_out ),
        .\not_strict_mode.app_rd_data_reg[273] (\ui_rd_data0/p_121_out ),
        .\not_strict_mode.app_rd_data_reg[275] (\ui_rd_data0/p_122_out ),
        .\not_strict_mode.app_rd_data_reg[277] (\ui_rd_data0/p_117_out ),
        .\not_strict_mode.app_rd_data_reg[279] (\ui_rd_data0/p_118_out ),
        .\not_strict_mode.app_rd_data_reg[27] (\ui_rd_data0/p_244_out ),
        .\not_strict_mode.app_rd_data_reg[281] (\ui_rd_data0/p_119_out ),
        .\not_strict_mode.app_rd_data_reg[283] (\ui_rd_data0/p_114_out ),
        .\not_strict_mode.app_rd_data_reg[285] (\ui_rd_data0/p_115_out ),
        .\not_strict_mode.app_rd_data_reg[287] (\ui_rd_data0/p_116_out ),
        .\not_strict_mode.app_rd_data_reg[289] (\ui_rd_data0/p_111_out ),
        .\not_strict_mode.app_rd_data_reg[291] (\ui_rd_data0/p_112_out ),
        .\not_strict_mode.app_rd_data_reg[293] (\ui_rd_data0/p_113_out ),
        .\not_strict_mode.app_rd_data_reg[295] (\ui_rd_data0/p_108_out ),
        .\not_strict_mode.app_rd_data_reg[297] (\ui_rd_data0/p_109_out ),
        .\not_strict_mode.app_rd_data_reg[299] (\ui_rd_data0/p_110_out ),
        .\not_strict_mode.app_rd_data_reg[29] (\ui_rd_data0/p_245_out ),
        .\not_strict_mode.app_rd_data_reg[301] (\ui_rd_data0/p_105_out ),
        .\not_strict_mode.app_rd_data_reg[303] (\ui_rd_data0/p_106_out ),
        .\not_strict_mode.app_rd_data_reg[305] (\ui_rd_data0/p_107_out ),
        .\not_strict_mode.app_rd_data_reg[307] (\ui_rd_data0/p_102_out ),
        .\not_strict_mode.app_rd_data_reg[309] (\ui_rd_data0/p_103_out ),
        .\not_strict_mode.app_rd_data_reg[311] (\ui_rd_data0/p_104_out ),
        .\not_strict_mode.app_rd_data_reg[313] (\ui_rd_data0/p_99_out ),
        .\not_strict_mode.app_rd_data_reg[315] (\ui_rd_data0/p_100_out ),
        .\not_strict_mode.app_rd_data_reg[317] (\ui_rd_data0/p_101_out ),
        .\not_strict_mode.app_rd_data_reg[319] (\ui_rd_data0/p_96_out ),
        .\not_strict_mode.app_rd_data_reg[31] (\ui_rd_data0/p_240_out ),
        .\not_strict_mode.app_rd_data_reg[321] (\ui_rd_data0/p_97_out ),
        .\not_strict_mode.app_rd_data_reg[323] (\ui_rd_data0/p_98_out ),
        .\not_strict_mode.app_rd_data_reg[325] (\ui_rd_data0/p_93_out ),
        .\not_strict_mode.app_rd_data_reg[327] (\ui_rd_data0/p_94_out ),
        .\not_strict_mode.app_rd_data_reg[329] (\ui_rd_data0/p_95_out ),
        .\not_strict_mode.app_rd_data_reg[331] (\ui_rd_data0/p_90_out ),
        .\not_strict_mode.app_rd_data_reg[333] (\ui_rd_data0/p_91_out ),
        .\not_strict_mode.app_rd_data_reg[335] (\ui_rd_data0/p_92_out ),
        .\not_strict_mode.app_rd_data_reg[337] (\ui_rd_data0/p_87_out ),
        .\not_strict_mode.app_rd_data_reg[339] (\ui_rd_data0/p_88_out ),
        .\not_strict_mode.app_rd_data_reg[33] (\ui_rd_data0/p_241_out ),
        .\not_strict_mode.app_rd_data_reg[341] (\ui_rd_data0/p_89_out ),
        .\not_strict_mode.app_rd_data_reg[343] (\ui_rd_data0/p_84_out ),
        .\not_strict_mode.app_rd_data_reg[345] (\ui_rd_data0/p_85_out ),
        .\not_strict_mode.app_rd_data_reg[347] (\ui_rd_data0/p_86_out ),
        .\not_strict_mode.app_rd_data_reg[349] (\ui_rd_data0/p_81_out ),
        .\not_strict_mode.app_rd_data_reg[351] (\ui_rd_data0/p_82_out ),
        .\not_strict_mode.app_rd_data_reg[353] (\ui_rd_data0/p_83_out ),
        .\not_strict_mode.app_rd_data_reg[355] (\ui_rd_data0/p_78_out ),
        .\not_strict_mode.app_rd_data_reg[357] (\ui_rd_data0/p_79_out ),
        .\not_strict_mode.app_rd_data_reg[359] (\ui_rd_data0/p_80_out ),
        .\not_strict_mode.app_rd_data_reg[35] (\ui_rd_data0/p_242_out ),
        .\not_strict_mode.app_rd_data_reg[361] (\ui_rd_data0/p_75_out ),
        .\not_strict_mode.app_rd_data_reg[363] (\ui_rd_data0/p_76_out ),
        .\not_strict_mode.app_rd_data_reg[365] (\ui_rd_data0/p_77_out ),
        .\not_strict_mode.app_rd_data_reg[367] (\ui_rd_data0/p_72_out ),
        .\not_strict_mode.app_rd_data_reg[369] (\ui_rd_data0/p_73_out ),
        .\not_strict_mode.app_rd_data_reg[371] (\ui_rd_data0/p_74_out ),
        .\not_strict_mode.app_rd_data_reg[373] (\ui_rd_data0/p_69_out ),
        .\not_strict_mode.app_rd_data_reg[375] (\ui_rd_data0/p_70_out ),
        .\not_strict_mode.app_rd_data_reg[377] (\ui_rd_data0/p_71_out ),
        .\not_strict_mode.app_rd_data_reg[379] (\ui_rd_data0/p_66_out ),
        .\not_strict_mode.app_rd_data_reg[37] (\ui_rd_data0/p_237_out ),
        .\not_strict_mode.app_rd_data_reg[381] (\ui_rd_data0/p_67_out ),
        .\not_strict_mode.app_rd_data_reg[383] (\ui_rd_data0/p_68_out ),
        .\not_strict_mode.app_rd_data_reg[385] (\ui_rd_data0/p_63_out ),
        .\not_strict_mode.app_rd_data_reg[387] (\ui_rd_data0/p_64_out ),
        .\not_strict_mode.app_rd_data_reg[389] (\ui_rd_data0/p_65_out ),
        .\not_strict_mode.app_rd_data_reg[391] (\ui_rd_data0/p_60_out ),
        .\not_strict_mode.app_rd_data_reg[393] (\ui_rd_data0/p_61_out ),
        .\not_strict_mode.app_rd_data_reg[395] (\ui_rd_data0/p_62_out ),
        .\not_strict_mode.app_rd_data_reg[397] (\ui_rd_data0/p_57_out ),
        .\not_strict_mode.app_rd_data_reg[399] (\ui_rd_data0/p_58_out ),
        .\not_strict_mode.app_rd_data_reg[39] (\ui_rd_data0/p_238_out ),
        .\not_strict_mode.app_rd_data_reg[401] (\ui_rd_data0/p_59_out ),
        .\not_strict_mode.app_rd_data_reg[403] (\ui_rd_data0/p_54_out ),
        .\not_strict_mode.app_rd_data_reg[405] (\ui_rd_data0/p_55_out ),
        .\not_strict_mode.app_rd_data_reg[407] (\ui_rd_data0/p_56_out ),
        .\not_strict_mode.app_rd_data_reg[409] (\ui_rd_data0/p_51_out ),
        .\not_strict_mode.app_rd_data_reg[411] (\ui_rd_data0/p_52_out ),
        .\not_strict_mode.app_rd_data_reg[413] (\ui_rd_data0/p_53_out ),
        .\not_strict_mode.app_rd_data_reg[415] (\ui_rd_data0/p_48_out ),
        .\not_strict_mode.app_rd_data_reg[417] (\ui_rd_data0/p_49_out ),
        .\not_strict_mode.app_rd_data_reg[419] (\ui_rd_data0/p_50_out ),
        .\not_strict_mode.app_rd_data_reg[41] (\ui_rd_data0/p_239_out ),
        .\not_strict_mode.app_rd_data_reg[421] (\ui_rd_data0/p_45_out ),
        .\not_strict_mode.app_rd_data_reg[423] (\ui_rd_data0/p_46_out ),
        .\not_strict_mode.app_rd_data_reg[425] (\ui_rd_data0/p_47_out ),
        .\not_strict_mode.app_rd_data_reg[427] (\ui_rd_data0/p_42_out ),
        .\not_strict_mode.app_rd_data_reg[429] (\ui_rd_data0/p_43_out ),
        .\not_strict_mode.app_rd_data_reg[431] (\ui_rd_data0/p_44_out ),
        .\not_strict_mode.app_rd_data_reg[433] (\ui_rd_data0/p_39_out ),
        .\not_strict_mode.app_rd_data_reg[435] (\ui_rd_data0/p_40_out ),
        .\not_strict_mode.app_rd_data_reg[437] (\ui_rd_data0/p_41_out ),
        .\not_strict_mode.app_rd_data_reg[439] (\ui_rd_data0/p_36_out ),
        .\not_strict_mode.app_rd_data_reg[43] (\ui_rd_data0/p_234_out ),
        .\not_strict_mode.app_rd_data_reg[441] (\ui_rd_data0/p_37_out ),
        .\not_strict_mode.app_rd_data_reg[443] (\ui_rd_data0/p_38_out ),
        .\not_strict_mode.app_rd_data_reg[445] (\ui_rd_data0/p_33_out ),
        .\not_strict_mode.app_rd_data_reg[447] (\ui_rd_data0/p_34_out ),
        .\not_strict_mode.app_rd_data_reg[449] (\ui_rd_data0/p_35_out ),
        .\not_strict_mode.app_rd_data_reg[451] (\ui_rd_data0/p_30_out ),
        .\not_strict_mode.app_rd_data_reg[453] (\ui_rd_data0/p_31_out ),
        .\not_strict_mode.app_rd_data_reg[455] (\ui_rd_data0/p_32_out ),
        .\not_strict_mode.app_rd_data_reg[457] (\ui_rd_data0/p_27_out ),
        .\not_strict_mode.app_rd_data_reg[459] (\ui_rd_data0/p_28_out ),
        .\not_strict_mode.app_rd_data_reg[45] (\ui_rd_data0/p_235_out ),
        .\not_strict_mode.app_rd_data_reg[461] (\ui_rd_data0/p_29_out ),
        .\not_strict_mode.app_rd_data_reg[463] (\ui_rd_data0/p_24_out ),
        .\not_strict_mode.app_rd_data_reg[465] (\ui_rd_data0/p_25_out ),
        .\not_strict_mode.app_rd_data_reg[467] (\ui_rd_data0/p_26_out ),
        .\not_strict_mode.app_rd_data_reg[469] (\ui_rd_data0/p_21_out ),
        .\not_strict_mode.app_rd_data_reg[471] (\ui_rd_data0/p_22_out ),
        .\not_strict_mode.app_rd_data_reg[473] (\ui_rd_data0/p_23_out ),
        .\not_strict_mode.app_rd_data_reg[475] (\ui_rd_data0/p_18_out ),
        .\not_strict_mode.app_rd_data_reg[477] (\ui_rd_data0/p_19_out ),
        .\not_strict_mode.app_rd_data_reg[479] (\ui_rd_data0/p_20_out ),
        .\not_strict_mode.app_rd_data_reg[47] (\ui_rd_data0/p_236_out ),
        .\not_strict_mode.app_rd_data_reg[481] (\ui_rd_data0/p_15_out ),
        .\not_strict_mode.app_rd_data_reg[483] (\ui_rd_data0/p_16_out ),
        .\not_strict_mode.app_rd_data_reg[485] (\ui_rd_data0/p_17_out ),
        .\not_strict_mode.app_rd_data_reg[487] (\ui_rd_data0/p_12_out ),
        .\not_strict_mode.app_rd_data_reg[489] (\ui_rd_data0/p_13_out ),
        .\not_strict_mode.app_rd_data_reg[491] (\ui_rd_data0/p_14_out ),
        .\not_strict_mode.app_rd_data_reg[493] (\ui_rd_data0/p_9_out ),
        .\not_strict_mode.app_rd_data_reg[495] (\ui_rd_data0/p_10_out ),
        .\not_strict_mode.app_rd_data_reg[497] (\ui_rd_data0/p_11_out ),
        .\not_strict_mode.app_rd_data_reg[499] (\ui_rd_data0/p_6_out ),
        .\not_strict_mode.app_rd_data_reg[49] (\ui_rd_data0/p_231_out ),
        .\not_strict_mode.app_rd_data_reg[501] (\ui_rd_data0/p_7_out ),
        .\not_strict_mode.app_rd_data_reg[503] (\ui_rd_data0/p_8_out ),
        .\not_strict_mode.app_rd_data_reg[505] (\ui_rd_data0/p_3_out ),
        .\not_strict_mode.app_rd_data_reg[507] (\ui_rd_data0/p_4_out ),
        .\not_strict_mode.app_rd_data_reg[509] (\ui_rd_data0/p_5_out ),
        .\not_strict_mode.app_rd_data_reg[511] (\ui_rd_data0/p_0_out ),
        .\not_strict_mode.app_rd_data_reg[51] (\ui_rd_data0/p_232_out ),
        .\not_strict_mode.app_rd_data_reg[53] (\ui_rd_data0/p_233_out ),
        .\not_strict_mode.app_rd_data_reg[55] (\ui_rd_data0/p_228_out ),
        .\not_strict_mode.app_rd_data_reg[57] (\ui_rd_data0/p_229_out ),
        .\not_strict_mode.app_rd_data_reg[59] (\ui_rd_data0/p_230_out ),
        .\not_strict_mode.app_rd_data_reg[61] (\ui_rd_data0/p_225_out ),
        .\not_strict_mode.app_rd_data_reg[63] (\ui_rd_data0/p_226_out ),
        .\not_strict_mode.app_rd_data_reg[65] (\ui_rd_data0/p_227_out ),
        .\not_strict_mode.app_rd_data_reg[67] (\ui_rd_data0/p_222_out ),
        .\not_strict_mode.app_rd_data_reg[69] (\ui_rd_data0/p_223_out ),
        .\not_strict_mode.app_rd_data_reg[71] (\ui_rd_data0/p_224_out ),
        .\not_strict_mode.app_rd_data_reg[73] (\ui_rd_data0/p_219_out ),
        .\not_strict_mode.app_rd_data_reg[75] (\ui_rd_data0/p_220_out ),
        .\not_strict_mode.app_rd_data_reg[77] (\ui_rd_data0/p_221_out ),
        .\not_strict_mode.app_rd_data_reg[79] (\ui_rd_data0/p_216_out ),
        .\not_strict_mode.app_rd_data_reg[7] (\ui_rd_data0/p_252_out ),
        .\not_strict_mode.app_rd_data_reg[81] (\ui_rd_data0/p_217_out ),
        .\not_strict_mode.app_rd_data_reg[83] (\ui_rd_data0/p_218_out ),
        .\not_strict_mode.app_rd_data_reg[85] (\ui_rd_data0/p_213_out ),
        .\not_strict_mode.app_rd_data_reg[87] (\ui_rd_data0/p_214_out ),
        .\not_strict_mode.app_rd_data_reg[89] (\ui_rd_data0/p_215_out ),
        .\not_strict_mode.app_rd_data_reg[91] (\ui_rd_data0/p_210_out ),
        .\not_strict_mode.app_rd_data_reg[93] (\ui_rd_data0/p_211_out ),
        .\not_strict_mode.app_rd_data_reg[95] (\ui_rd_data0/p_212_out ),
        .\not_strict_mode.app_rd_data_reg[97] (\ui_rd_data0/p_207_out ),
        .\not_strict_mode.app_rd_data_reg[99] (\ui_rd_data0/p_208_out ),
        .\not_strict_mode.app_rd_data_reg[9] (\ui_rd_data0/p_253_out ),
        .\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] (ram_init_addr),
        .p_106_out(\mc0/bank_mach0/p_106_out ),
        .p_145_out(\mc0/bank_mach0/p_145_out ),
        .p_28_out(\mc0/bank_mach0/p_28_out ),
        .p_67_out(\mc0/bank_mach0/p_67_out ),
        .periodic_rd_ack_r(\mc0/periodic_rd_ack_r ),
        .periodic_rd_cntr_r(\mc0/bank_mach0/bank_common0/periodic_rd_cntr_r ),
        .periodic_rd_r(\mc0/periodic_rd_r ),
        .pointer_we(\ui_wr_data0/pointer_we ),
        .ram_init_done_r(ram_init_done_r),
        .rd_buf_we(\ui_rd_data0/rd_buf_we ),
        .\read_fifo.fifo_out_data_r_reg[4] (mem_intfc0_n_1692),
        .\read_fifo.fifo_out_data_r_reg[7] ({rd_data_end,rd_data_addr,rd_data_offset}),
        .\req_bank_r_lcl_reg[2] (bank),
        .\req_bank_r_lcl_reg[2]_0 (\mc0/bank_mach0/p_108_out ),
        .\req_bank_r_lcl_reg[2]_1 (\mc0/bank_mach0/p_147_out ),
        .\req_bank_r_lcl_reg[2]_2 (\mc0/bank_mach0/p_30_out ),
        .\req_bank_r_lcl_reg[2]_3 (\mc0/bank_mach0/p_69_out ),
        .\req_col_r_reg[9] (col),
        .\req_data_buf_addr_r_reg[4] (\ui_cmd0/app_cmd_r2 ),
        .\req_data_buf_addr_r_reg[4]_0 (data_buf_addr),
        .\req_row_r_lcl_reg[13] (\mc0/bank_mach0/p_151_out ),
        .\req_row_r_lcl_reg[13]_0 (\mc0/bank_mach0/p_112_out ),
        .\req_row_r_lcl_reg[13]_1 (\mc0/bank_mach0/p_73_out ),
        .\req_row_r_lcl_reg[13]_2 (\mc0/bank_mach0/p_34_out ),
        .req_wr_r_lcl_reg(u_ui_top_n_520),
        .req_wr_r_lcl_reg_0(u_ui_top_n_528),
        .reset_reg(reset_reg_n_0),
        .row(row),
        .row_hit_r_reg(u_ui_top_n_544),
        .row_hit_r_reg_0(u_ui_top_n_545),
        .row_hit_r_reg_1(u_ui_top_n_546),
        .was_wr0(\mc0/bank_mach0/bank_common0/was_wr0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_rank_cntrl" *) 
module mig_7series_0_mig_7series_v2_3_rank_cntrl
   (read_this_rank_r,
    inhbt_act_faw_r,
    periodic_rd_request_r,
    periodic_rd_cntr1_r,
    app_ref_r_reg,
    Q,
    app_ref_r_reg_0,
    \maintenance_request.upd_last_master_r_reg ,
    act_this_rank,
    CLK,
    read_this_rank,
    rstdiv0_sync_r1_reg_rep__18,
    rstdiv0_sync_r1_reg_rep__1,
    \periodic_read_request.periodic_rd_grant_r_reg[0] ,
    init_calib_complete_reg_rep,
    periodic_rd_ack_r_lcl_reg,
    periodic_rd_grant_r,
    int_read_this_rank,
    init_calib_complete_reg_rep_0,
    rstdiv0_sync_r1_reg_rep__20,
    \grant_r_reg[2] ,
    app_ref_req,
    app_ref_r,
    rstdiv0_sync_r1_reg_rep__21,
    sre_request_r,
    maint_prescaler_tick_r,
    maint_prescaler_r1);
  output read_this_rank_r;
  output inhbt_act_faw_r;
  output periodic_rd_request_r;
  output periodic_rd_cntr1_r;
  output app_ref_r_reg;
  output [0:0]Q;
  output app_ref_r_reg_0;
  output \maintenance_request.upd_last_master_r_reg ;
  input act_this_rank;
  input CLK;
  input read_this_rank;
  input rstdiv0_sync_r1_reg_rep__18;
  input rstdiv0_sync_r1_reg_rep__1;
  input \periodic_read_request.periodic_rd_grant_r_reg[0] ;
  input init_calib_complete_reg_rep;
  input periodic_rd_ack_r_lcl_reg;
  input periodic_rd_grant_r;
  input int_read_this_rank;
  input init_calib_complete_reg_rep_0;
  input rstdiv0_sync_r1_reg_rep__20;
  input \grant_r_reg[2] ;
  input app_ref_req;
  input app_ref_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input sre_request_r;
  input maint_prescaler_tick_r;
  input maint_prescaler_r1;

  wire CLK;
  wire [0:0]Q;
  wire act_delayed;
  wire act_this_rank;
  wire app_ref_r;
  wire app_ref_r_reg;
  wire app_ref_r_reg_0;
  wire app_ref_req;
  wire [2:0]faw_cnt_r;
  wire \grant_r_reg[2] ;
  wire \inhbt_act_faw.faw_cnt_r[0]_i_1_n_0 ;
  wire \inhbt_act_faw.faw_cnt_r[1]_i_1_n_0 ;
  wire \inhbt_act_faw.faw_cnt_r[2]_i_1_n_0 ;
  wire \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ;
  wire inhbt_act_faw_r;
  wire init_calib_complete_reg_rep;
  wire init_calib_complete_reg_rep_0;
  wire int_read_this_rank;
  wire maint_prescaler_r1;
  wire maint_prescaler_tick_r;
  wire \maintenance_request.upd_last_master_r_reg ;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_cntr1_r;
  wire \periodic_rd_generation.periodic_rd_request_r_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_request_r_i_2_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r[2]_i_2_n_0 ;
  wire periodic_rd_grant_r;
  wire periodic_rd_request_r;
  wire [2:0]periodic_rd_timer_r;
  wire \periodic_read_request.periodic_rd_grant_r_reg[0] ;
  wire read_this_rank;
  wire read_this_rank_r;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sre_request_r;
  wire [0:0]wtr_cnt_r;
  wire \wtr_timer.wtr_cnt_r[0]_i_1_n_0 ;
  wire \wtr_timer.wtr_cnt_r[1]_i_1_n_0 ;

  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    app_ref_r_i_1
       (.I0(app_ref_req),
        .I1(app_ref_r_reg),
        .I2(app_ref_r),
        .O(app_ref_r_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "SRLC32E" *) 
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \inhbt_act_faw.SRLC32E0 
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(act_this_rank),
        .Q(act_delayed));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT4 #(
    .INIT(16'h4114)) 
    \inhbt_act_faw.faw_cnt_r[0]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(act_this_rank),
        .I2(act_delayed),
        .I3(faw_cnt_r[0]),
        .O(\inhbt_act_faw.faw_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT5 #(
    .INIT(32'h45511004)) 
    \inhbt_act_faw.faw_cnt_r[1]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(act_delayed),
        .I2(act_this_rank),
        .I3(faw_cnt_r[0]),
        .I4(faw_cnt_r[1]),
        .O(\inhbt_act_faw.faw_cnt_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4555555110000004)) 
    \inhbt_act_faw.faw_cnt_r[2]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(act_delayed),
        .I2(faw_cnt_r[0]),
        .I3(act_this_rank),
        .I4(faw_cnt_r[1]),
        .I5(faw_cnt_r[2]),
        .O(\inhbt_act_faw.faw_cnt_r[2]_i_1_n_0 ));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r[0]_i_1_n_0 ),
        .Q(faw_cnt_r[0]),
        .R(1'b0));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r[1]_i_1_n_0 ),
        .Q(faw_cnt_r[1]),
        .R(1'b0));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r[2]_i_1_n_0 ),
        .Q(faw_cnt_r[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0004100010000010)) 
    \inhbt_act_faw.inhbt_act_faw_r_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(faw_cnt_r[1]),
        .I2(faw_cnt_r[2]),
        .I3(act_delayed),
        .I4(faw_cnt_r[0]),
        .I5(act_this_rank),
        .O(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ));
  FDRE \inhbt_act_faw.inhbt_act_faw_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ),
        .Q(inhbt_act_faw_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT3 #(
    .INIT(8'h2F)) 
    \maintenance_request.upd_last_master_r_i_2 
       (.I0(app_ref_r_reg),
        .I1(sre_request_r),
        .I2(init_calib_complete_reg_rep_0),
        .O(\maintenance_request.upd_last_master_r_reg ));
  FDRE \periodic_rd_generation.periodic_rd_cntr1_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_grant_r_reg[0] ),
        .Q(periodic_rd_cntr1_r),
        .R(rstdiv0_sync_r1_reg_rep__1));
  LUT6 #(
    .INIT(64'h00001555FFFFFFFF)) 
    \periodic_rd_generation.periodic_rd_request_r_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_request_r_i_2_n_0 ),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(periodic_rd_grant_r),
        .I3(periodic_rd_cntr1_r),
        .I4(int_read_this_rank),
        .I5(init_calib_complete_reg_rep_0),
        .O(\periodic_rd_generation.periodic_rd_request_r_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000FDFF)) 
    \periodic_rd_generation.periodic_rd_request_r_i_2 
       (.I0(periodic_rd_timer_r[0]),
        .I1(periodic_rd_timer_r[1]),
        .I2(periodic_rd_timer_r[2]),
        .I3(maint_prescaler_tick_r),
        .I4(periodic_rd_request_r),
        .O(\periodic_rd_generation.periodic_rd_request_r_i_2_n_0 ));
  FDRE \periodic_rd_generation.periodic_rd_request_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_request_r_i_1_n_0 ),
        .Q(periodic_rd_request_r),
        .R(rstdiv0_sync_r1_reg_rep__18));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT5 #(
    .INIT(32'hFFFF32CC)) 
    \periodic_rd_generation.periodic_rd_timer_r[0]_i_1 
       (.I0(periodic_rd_timer_r[1]),
        .I1(periodic_rd_timer_r[0]),
        .I2(periodic_rd_timer_r[2]),
        .I3(maint_prescaler_tick_r),
        .I4(int_read_this_rank),
        .O(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000098AA0000)) 
    \periodic_rd_generation.periodic_rd_timer_r[1]_i_1 
       (.I0(periodic_rd_timer_r[1]),
        .I1(periodic_rd_timer_r[0]),
        .I2(periodic_rd_timer_r[2]),
        .I3(maint_prescaler_tick_r),
        .I4(init_calib_complete_reg_rep_0),
        .I5(int_read_this_rank),
        .O(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT5 #(
    .INIT(32'hFFFFE0F0)) 
    \periodic_rd_generation.periodic_rd_timer_r[2]_i_2 
       (.I0(periodic_rd_timer_r[1]),
        .I1(periodic_rd_timer_r[0]),
        .I2(periodic_rd_timer_r[2]),
        .I3(maint_prescaler_tick_r),
        .I4(int_read_this_rank),
        .O(\periodic_rd_generation.periodic_rd_timer_r[2]_i_2_n_0 ));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ),
        .Q(periodic_rd_timer_r[0]),
        .R(maint_prescaler_r1));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ),
        .Q(periodic_rd_timer_r[1]),
        .R(1'b0));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[2]_i_2_n_0 ),
        .Q(periodic_rd_timer_r[2]),
        .R(maint_prescaler_r1));
  FDRE \periodic_rd_generation.read_this_rank_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(read_this_rank),
        .Q(read_this_rank_r),
        .R(1'b0));
  FDRE \refresh_generation.refresh_bank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(init_calib_complete_reg_rep),
        .Q(app_ref_r_reg),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT4 #(
    .INIT(16'h0455)) 
    \wtr_timer.wtr_cnt_r[0]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(Q),
        .I2(wtr_cnt_r),
        .I3(\grant_r_reg[2] ),
        .O(\wtr_timer.wtr_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT4 #(
    .INIT(16'h4055)) 
    \wtr_timer.wtr_cnt_r[1]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(wtr_cnt_r),
        .I2(Q),
        .I3(\grant_r_reg[2] ),
        .O(\wtr_timer.wtr_cnt_r[1]_i_1_n_0 ));
  FDRE \wtr_timer.wtr_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wtr_timer.wtr_cnt_r[0]_i_1_n_0 ),
        .Q(wtr_cnt_r),
        .R(1'b0));
  FDRE \wtr_timer.wtr_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wtr_timer.wtr_cnt_r[1]_i_1_n_0 ),
        .Q(Q),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_rank_common" *) 
module mig_7series_0_mig_7series_v2_3_rank_common
   (maint_prescaler_tick_r,
    \maint_controller.maint_wip_r_lcl_reg ,
    \maintenance_request.maint_srx_r_lcl_reg_0 ,
    app_ref_ack,
    app_zq_ack,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    \maint_controller.maint_srx_r1_reg ,
    sre_request_r,
    \periodic_read_request.periodic_rd_r_lcl_reg_0 ,
    app_ref_r,
    \maintenance_request.maint_rank_r_lcl_reg[0]_0 ,
    periodic_rd_grant_r,
    app_sr_active,
    maint_ref_zq_wip,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg ,
    \refresh_generation.refresh_bank_r_reg[0] ,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    \maint_controller.maint_wip_r_lcl_reg_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    mc_cke_ns,
    \maint_controller.maint_hit_busies_r_reg[2] ,
    auto_pre_r_lcl_reg,
    q_has_rd_r_reg,
    pass_open_bank_r_lcl_reg,
    CLK,
    rstdiv0_sync_r1_reg_rep__18,
    maint_prescaler_r1,
    \refresh_generation.refresh_bank_r_reg[0]_0 ,
    sre_clears_sre_request,
    rstdiv0_sync_r1_reg_rep__0,
    periodic_rd_request_r,
    init_calib_complete_reg_rep,
    insert_maint_r1,
    init_calib_complete_reg_rep_0,
    maint_wip_r,
    rstdiv0_sync_r1_reg_rep__19,
    periodic_rd_ack_r_lcl_reg,
    periodic_rd_cntr1_r,
    \refresh_generation.refresh_bank_r_reg[0]_1 ,
    app_ref_req,
    app_zq_req,
    wait_for_maint_r,
    periodic_rd_ack_r_lcl_reg_0,
    wait_for_maint_r_0,
    periodic_rd_ack_r_lcl_reg_1,
    wait_for_maint_r_1,
    periodic_rd_ack_r_lcl_reg_2,
    wait_for_maint_r_2,
    periodic_rd_ack_r_lcl_reg_3,
    app_sr_req,
    rstdiv0_sync_r1_reg_rep__20,
    rstdiv0_sync_r1_reg_rep__21,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    insert_maint_r,
    cke_r,
    \refresh_generation.refresh_bank_r_reg[0]_2 ,
    \maint_controller.maint_wip_r_lcl_reg_1 );
  output maint_prescaler_tick_r;
  output \maint_controller.maint_wip_r_lcl_reg ;
  output \maintenance_request.maint_srx_r_lcl_reg_0 ;
  output app_ref_ack;
  output app_zq_ack;
  output \maintenance_request.maint_zq_r_lcl_reg_0 ;
  output \maint_controller.maint_srx_r1_reg ;
  output sre_request_r;
  output \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  output app_ref_r;
  output \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  output periodic_rd_grant_r;
  output app_sr_active;
  output maint_ref_zq_wip;
  output \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  output \refresh_generation.refresh_bank_r_reg[0] ;
  output wait_for_maint_r_lcl_reg;
  output wait_for_maint_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_1;
  output wait_for_maint_r_lcl_reg_2;
  output \maint_controller.maint_wip_r_lcl_reg_0 ;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  output [0:0]mc_cke_ns;
  output \maint_controller.maint_hit_busies_r_reg[2] ;
  output auto_pre_r_lcl_reg;
  output q_has_rd_r_reg;
  output pass_open_bank_r_lcl_reg;
  input CLK;
  input rstdiv0_sync_r1_reg_rep__18;
  input maint_prescaler_r1;
  input \refresh_generation.refresh_bank_r_reg[0]_0 ;
  input sre_clears_sre_request;
  input rstdiv0_sync_r1_reg_rep__0;
  input periodic_rd_request_r;
  input init_calib_complete_reg_rep;
  input insert_maint_r1;
  input init_calib_complete_reg_rep_0;
  input maint_wip_r;
  input rstdiv0_sync_r1_reg_rep__19;
  input periodic_rd_ack_r_lcl_reg;
  input periodic_rd_cntr1_r;
  input \refresh_generation.refresh_bank_r_reg[0]_1 ;
  input app_ref_req;
  input app_zq_req;
  input wait_for_maint_r;
  input periodic_rd_ack_r_lcl_reg_0;
  input wait_for_maint_r_0;
  input periodic_rd_ack_r_lcl_reg_1;
  input wait_for_maint_r_1;
  input periodic_rd_ack_r_lcl_reg_2;
  input wait_for_maint_r_2;
  input periodic_rd_ack_r_lcl_reg_3;
  input app_sr_req;
  input rstdiv0_sync_r1_reg_rep__20;
  input rstdiv0_sync_r1_reg_rep__21;
  input \generate_maint_cmds.insert_maint_r_lcl_reg ;
  input insert_maint_r;
  input cke_r;
  input \refresh_generation.refresh_bank_r_reg[0]_2 ;
  input \maint_controller.maint_wip_r_lcl_reg_1 ;

  wire CLK;
  wire app_ref_ack;
  wire app_ref_ack_ns;
  wire app_ref_r;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_active_r_i_1_n_0;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_ack_ns;
  wire app_zq_r;
  wire app_zq_r_i_1_n_0;
  wire app_zq_req;
  wire auto_pre_r_lcl_reg;
  wire cke_r;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire inhbt_srx;
  wire init_calib_complete_reg_rep;
  wire init_calib_complete_reg_rep_0;
  wire insert_maint_r;
  wire insert_maint_r1;
  wire \maint_controller.maint_hit_busies_r_reg[2] ;
  wire \maint_controller.maint_srx_r1_reg ;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire \maint_controller.maint_wip_r_lcl_reg_0 ;
  wire \maint_controller.maint_wip_r_lcl_reg_1 ;
  wire \maint_prescaler.maint_prescaler_r[1]_i_1_n_0 ;
  wire \maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ;
  wire [4:0]\maint_prescaler.maint_prescaler_r_reg__0 ;
  wire [4:0]maint_prescaler_r0;
  wire maint_prescaler_r1;
  wire maint_prescaler_tick_ns;
  wire maint_prescaler_tick_r;
  wire maint_ref_zq_wip;
  wire maint_ref_zq_wip_r_i_1_n_0;
  wire maint_ref_zq_wip_r_i_3_n_0;
  wire maint_sre_ns;
  wire maint_wip_r;
  wire \maintenance_request.maint_arb0_n_0 ;
  wire \maintenance_request.maint_arb0_n_2 ;
  wire \maintenance_request.maint_arb0_n_3 ;
  wire \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  wire \maintenance_request.maint_srx_r_lcl_reg_0 ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [0:0]mc_cke_ns;
  wire new_maint_rank_r;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_ack_r_lcl_reg_2;
  wire periodic_rd_ack_r_lcl_reg_3;
  wire periodic_rd_cntr1_r;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  wire periodic_rd_grant_r;
  wire periodic_rd_r_cnt;
  wire periodic_rd_request_r;
  wire \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0 ;
  wire \periodic_read_request.periodic_rd_r_cnt_i_1_n_0 ;
  wire \periodic_read_request.periodic_rd_r_lcl_i_1_n_0 ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  wire \periodic_read_request.upd_last_master_r_reg_n_0 ;
  wire q_has_rd_r_reg;
  wire \refresh_generation.refresh_bank_r[0]_i_2_n_0 ;
  wire \refresh_generation.refresh_bank_r_reg[0] ;
  wire \refresh_generation.refresh_bank_r_reg[0]_0 ;
  wire \refresh_generation.refresh_bank_r_reg[0]_1 ;
  wire \refresh_generation.refresh_bank_r_reg[0]_2 ;
  wire \refresh_timer.refresh_timer_r[1]_i_1_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_1_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_4_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_5_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_6_n_0 ;
  wire [5:0]\refresh_timer.refresh_timer_r_reg__0 ;
  wire [5:0]refresh_timer_r0;
  wire refresh_timer_r0_0;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sel;
  wire \sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0 ;
  wire sre_clears_sre_request;
  wire sre_request_r;
  wire upd_last_master_ns;
  wire upd_last_master_ns8_out;
  wire upd_last_master_r;
  wire wait_for_maint_r;
  wire wait_for_maint_r_0;
  wire wait_for_maint_r_1;
  wire wait_for_maint_r_2;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire \zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_13_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_14_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_15_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_8_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[12]_i_2_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[12]_i_3_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[12]_i_4_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[12]_i_5_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[16]_i_2_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[16]_i_3_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[16]_i_4_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[16]_i_5_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[4]_i_2_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[4]_i_3_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[4]_i_4_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[4]_i_5_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[8]_i_2_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[8]_i_3_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[8]_i_4_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[8]_i_5_n_0 ;
  wire [19:0]\zq_cntrl.zq_timer.zq_timer_r_reg ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ;
  wire zq_request_r;
  wire zq_timer_r0;
  wire [3:3]\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED ;

  LUT3 #(
    .INIT(8'h8A)) 
    app_ref_ack_r_i_1
       (.I0(app_ref_r),
        .I1(\refresh_generation.refresh_bank_r_reg[0]_1 ),
        .I2(init_calib_complete_reg_rep),
        .O(app_ref_ack_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_ref_ack_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_ref_ack_ns),
        .Q(app_ref_ack),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    app_ref_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\refresh_generation.refresh_bank_r_reg[0]_0 ),
        .Q(app_ref_r),
        .R(maint_prescaler_r1));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    app_sr_active_r_i_1
       (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I1(\maint_controller.maint_srx_r1_reg ),
        .I2(insert_maint_r1),
        .I3(app_sr_active),
        .O(app_sr_active_r_i_1_n_0));
  FDRE app_sr_active_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_sr_active_r_i_1_n_0),
        .Q(app_sr_active),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    app_zq_ack_r_i_1
       (.I0(app_zq_r),
        .I1(init_calib_complete_reg_rep),
        .I2(zq_request_r),
        .O(app_zq_ack_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_zq_ack_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_zq_ack_ns),
        .Q(app_zq_ack),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hEA)) 
    app_zq_r_i_1
       (.I0(app_zq_req),
        .I1(app_zq_r),
        .I2(zq_request_r),
        .O(app_zq_r_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    app_zq_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_zq_r_i_1_n_0),
        .Q(app_zq_r),
        .R(maint_prescaler_r1));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT5 #(
    .INIT(32'h101010FF)) 
    auto_pre_r_lcl_i_3
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I3(\maint_controller.maint_wip_r_lcl_reg ),
        .I4(maint_wip_r),
        .O(auto_pre_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT4 #(
    .INIT(16'h3F08)) 
    cke_r_i_1
       (.I0(\maint_controller.maint_srx_r1_reg ),
        .I1(insert_maint_r1),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(cke_r),
        .O(mc_cke_ns));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT5 #(
    .INIT(32'hFFFFFF10)) 
    \maint_controller.maint_hit_busies_r[3]_i_3 
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I3(\maint_controller.maint_wip_r_lcl_reg ),
        .I4(maint_wip_r),
        .O(\maint_controller.maint_hit_busies_r_reg[2] ));
  LUT3 #(
    .INIT(8'hAB)) 
    \maint_controller.maint_wip_r_lcl_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(\maint_controller.maint_wip_r_lcl_reg ),
        .I2(maint_wip_r),
        .O(\maint_controller.maint_wip_r_lcl_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \maint_prescaler.maint_prescaler_r[0]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .O(maint_prescaler_r0[0]));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \maint_prescaler.maint_prescaler_r[1]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .I1(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .O(\maint_prescaler.maint_prescaler_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \maint_prescaler.maint_prescaler_r[2]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [2]),
        .I1(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .I2(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .O(maint_prescaler_r0[2]));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \maint_prescaler.maint_prescaler_r[3]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [3]),
        .I1(\maint_prescaler.maint_prescaler_r_reg__0 [2]),
        .I2(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .I3(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .O(maint_prescaler_r0[3]));
  LUT6 #(
    .INIT(64'h00000100FFFFFFFF)) 
    \maint_prescaler.maint_prescaler_r[4]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [3]),
        .I1(\maint_prescaler.maint_prescaler_r_reg__0 [4]),
        .I2(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .I3(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .I4(\maint_prescaler.maint_prescaler_r_reg__0 [2]),
        .I5(init_calib_complete_reg_rep),
        .O(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \maint_prescaler.maint_prescaler_r[4]_i_2 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [4]),
        .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]),
        .I2(\maint_prescaler.maint_prescaler_r_reg__0 [2]),
        .I3(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .I4(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .O(sel));
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \maint_prescaler.maint_prescaler_r[4]_i_3 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [4]),
        .I1(\maint_prescaler.maint_prescaler_r_reg__0 [3]),
        .I2(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .I3(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .I4(\maint_prescaler.maint_prescaler_r_reg__0 [2]),
        .O(maint_prescaler_r0[4]));
  FDRE \maint_prescaler.maint_prescaler_r_reg[0] 
       (.C(CLK),
        .CE(sel),
        .D(maint_prescaler_r0[0]),
        .Q(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDRE \maint_prescaler.maint_prescaler_r_reg[1] 
       (.C(CLK),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r[1]_i_1_n_0 ),
        .Q(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDRE \maint_prescaler.maint_prescaler_r_reg[2] 
       (.C(CLK),
        .CE(sel),
        .D(maint_prescaler_r0[2]),
        .Q(\maint_prescaler.maint_prescaler_r_reg__0 [2]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDRE \maint_prescaler.maint_prescaler_r_reg[3] 
       (.C(CLK),
        .CE(sel),
        .D(maint_prescaler_r0[3]),
        .Q(\maint_prescaler.maint_prescaler_r_reg__0 [3]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDSE \maint_prescaler.maint_prescaler_r_reg[4] 
       (.C(CLK),
        .CE(sel),
        .D(maint_prescaler_r0[4]),
        .Q(\maint_prescaler.maint_prescaler_r_reg__0 [4]),
        .S(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000004)) 
    \maint_prescaler.maint_prescaler_tick_r_lcl_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg__0 [2]),
        .I1(\maint_prescaler.maint_prescaler_r_reg__0 [0]),
        .I2(\maint_prescaler.maint_prescaler_r_reg__0 [1]),
        .I3(\maint_prescaler.maint_prescaler_r_reg__0 [4]),
        .I4(\maint_prescaler.maint_prescaler_r_reg__0 [3]),
        .O(maint_prescaler_tick_ns));
  FDRE \maint_prescaler.maint_prescaler_tick_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(maint_prescaler_tick_ns),
        .Q(maint_prescaler_tick_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000FFE00000E0E0)) 
    maint_ref_zq_wip_r_i_1
       (.I0(init_calib_complete_reg_rep_0),
        .I1(maint_ref_zq_wip_r_i_3_n_0),
        .I2(insert_maint_r1),
        .I3(maint_wip_r),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .I5(maint_ref_zq_wip),
        .O(maint_ref_zq_wip_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT2 #(
    .INIT(4'h8)) 
    maint_ref_zq_wip_r_i_3
       (.I0(zq_request_r),
        .I1(init_calib_complete_reg_rep),
        .O(maint_ref_zq_wip_r_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    maint_ref_zq_wip_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(maint_ref_zq_wip_r_i_1_n_0),
        .Q(maint_ref_zq_wip),
        .R(1'b0));
  mig_7series_0_mig_7series_v2_3_round_robin_arb \maintenance_request.maint_arb0 
       (.CLK(CLK),
        .app_sr_req(app_sr_req),
        .inhbt_srx(inhbt_srx),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .maint_sre_ns(maint_sre_ns),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_arb0_n_0 ),
        .\maintenance_request.maint_rank_r_lcl_reg[0]_0 (\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .\maintenance_request.maint_sre_r_lcl_reg (\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .\maintenance_request.maint_srx_r_lcl_reg (\maintenance_request.maint_arb0_n_2 ),
        .\maintenance_request.maint_srx_r_lcl_reg_0 (\maint_controller.maint_srx_r1_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_arb0_n_3 ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .\refresh_generation.refresh_bank_r_reg[0] (\refresh_generation.refresh_bank_r_reg[0]_1 ),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .\sr_cntrl.sre_request_logic.sre_request_r_reg (sre_request_r),
        .upd_last_master_r(upd_last_master_r),
        .zq_request_r(zq_request_r));
  FDRE \maintenance_request.maint_rank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_0 ),
        .Q(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .R(1'b0));
  FDRE \maintenance_request.maint_req_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(new_maint_rank_r),
        .Q(\maint_controller.maint_wip_r_lcl_reg ),
        .R(1'b0));
  FDRE \maintenance_request.maint_sre_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(maint_sre_ns),
        .Q(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .R(1'b0));
  FDRE \maintenance_request.maint_srx_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_2 ),
        .Q(\maint_controller.maint_srx_r1_reg ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \maintenance_request.maint_zq_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_3 ),
        .Q(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .R(rstdiv0_sync_r1_reg_rep__18));
  FDRE \maintenance_request.new_maint_rank_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(upd_last_master_r),
        .Q(new_maint_rank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000000000D5)) 
    \maintenance_request.upd_last_master_r_i_1 
       (.I0(\refresh_generation.refresh_bank_r_reg[0]_2 ),
        .I1(zq_request_r),
        .I2(init_calib_complete_reg_rep),
        .I3(upd_last_master_r),
        .I4(new_maint_rank_r),
        .I5(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .O(upd_last_master_ns8_out));
  FDRE \maintenance_request.upd_last_master_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(upd_last_master_ns8_out),
        .Q(upd_last_master_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT3 #(
    .INIT(8'h02)) 
    pass_open_bank_r_lcl_i_4
       (.I0(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I1(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .O(pass_open_bank_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \periodic_rd_generation.periodic_rd_cntr1_r_i_1 
       (.I0(periodic_rd_grant_r),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(periodic_rd_cntr1_r),
        .O(\periodic_rd_generation.periodic_rd_cntr1_r_reg ));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT5 #(
    .INIT(32'hFFFF0008)) 
    \periodic_read_request.periodic_rd_grant_r[0]_i_1 
       (.I0(periodic_rd_request_r),
        .I1(init_calib_complete_reg_rep),
        .I2(\periodic_read_request.upd_last_master_r_reg_n_0 ),
        .I3(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .I4(periodic_rd_grant_r),
        .O(\periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0 ));
  FDRE \periodic_read_request.periodic_rd_grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0 ),
        .Q(periodic_rd_grant_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \periodic_read_request.periodic_rd_r_cnt_i_1 
       (.I0(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .I1(periodic_rd_ack_r_lcl_reg),
        .I2(periodic_rd_r_cnt),
        .O(\periodic_read_request.periodic_rd_r_cnt_i_1_n_0 ));
  FDRE \periodic_read_request.periodic_rd_r_cnt_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_r_cnt_i_1_n_0 ),
        .Q(periodic_rd_r_cnt),
        .R(rstdiv0_sync_r1_reg_rep__0));
  LUT4 #(
    .INIT(16'hFF4C)) 
    \periodic_read_request.periodic_rd_r_lcl_i_1 
       (.I0(periodic_rd_ack_r_lcl_reg),
        .I1(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .I2(periodic_rd_r_cnt),
        .I3(\periodic_read_request.upd_last_master_r_reg_n_0 ),
        .O(\periodic_read_request.periodic_rd_r_lcl_i_1_n_0 ));
  FDRE \periodic_read_request.periodic_rd_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_r_lcl_i_1_n_0 ),
        .Q(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .R(maint_prescaler_r1));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \periodic_read_request.upd_last_master_r_i_1 
       (.I0(periodic_rd_request_r),
        .I1(init_calib_complete_reg_rep),
        .I2(\periodic_read_request.upd_last_master_r_reg_n_0 ),
        .I3(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .O(upd_last_master_ns));
  FDRE \periodic_read_request.upd_last_master_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(upd_last_master_ns),
        .Q(\periodic_read_request.upd_last_master_r_reg_n_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h10FF)) 
    q_has_rd_r_i_2
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I3(\maint_controller.maint_wip_r_lcl_reg ),
        .O(q_has_rd_r_reg));
  LUT5 #(
    .INIT(32'h88820008)) 
    \refresh_generation.refresh_bank_r[0]_i_1 
       (.I0(init_calib_complete_reg_rep),
        .I1(\refresh_generation.refresh_bank_r_reg[0]_1 ),
        .I2(app_ref_req),
        .I3(\refresh_timer.refresh_timer_r[5]_i_4_n_0 ),
        .I4(\refresh_generation.refresh_bank_r[0]_i_2_n_0 ),
        .O(\refresh_generation.refresh_bank_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT5 #(
    .INIT(32'h00000100)) 
    \refresh_generation.refresh_bank_r[0]_i_2 
       (.I0(\maint_controller.maint_srx_r1_reg ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(insert_maint_r1),
        .I4(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .O(\refresh_generation.refresh_bank_r[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \refresh_timer.refresh_timer_r[0]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .O(refresh_timer_r0[0]));
  LUT2 #(
    .INIT(4'h9)) 
    \refresh_timer.refresh_timer_r[1]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .O(\refresh_timer.refresh_timer_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \refresh_timer.refresh_timer_r[2]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [2]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .I2(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .O(refresh_timer_r0[2]));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \refresh_timer.refresh_timer_r[3]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [3]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [2]),
        .I2(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .I3(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .O(refresh_timer_r0[3]));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \refresh_timer.refresh_timer_r[4]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [4]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [3]),
        .I2(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .I3(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .I4(\refresh_timer.refresh_timer_r_reg__0 [2]),
        .O(refresh_timer_r0[4]));
  LUT2 #(
    .INIT(4'hB)) 
    \refresh_timer.refresh_timer_r[5]_i_1 
       (.I0(\refresh_timer.refresh_timer_r[5]_i_4_n_0 ),
        .I1(init_calib_complete_reg_rep),
        .O(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAA8A)) 
    \refresh_timer.refresh_timer_r[5]_i_2 
       (.I0(maint_prescaler_tick_r),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [5]),
        .I2(\refresh_timer.refresh_timer_r[5]_i_5_n_0 ),
        .I3(\refresh_timer.refresh_timer_r_reg__0 [4]),
        .I4(\refresh_timer.refresh_timer_r_reg__0 [3]),
        .O(refresh_timer_r0_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \refresh_timer.refresh_timer_r[5]_i_3 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [5]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [3]),
        .I2(\refresh_timer.refresh_timer_r_reg__0 [4]),
        .I3(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .I4(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .I5(\refresh_timer.refresh_timer_r_reg__0 [2]),
        .O(refresh_timer_r0[5]));
  LUT6 #(
    .INIT(64'h0000000000100000)) 
    \refresh_timer.refresh_timer_r[5]_i_4 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [2]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [5]),
        .I2(maint_prescaler_tick_r),
        .I3(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .I4(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .I5(\refresh_timer.refresh_timer_r[5]_i_6_n_0 ),
        .O(\refresh_timer.refresh_timer_r[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \refresh_timer.refresh_timer_r[5]_i_5 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .I2(\refresh_timer.refresh_timer_r_reg__0 [2]),
        .O(\refresh_timer.refresh_timer_r[5]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \refresh_timer.refresh_timer_r[5]_i_6 
       (.I0(\refresh_timer.refresh_timer_r_reg__0 [3]),
        .I1(\refresh_timer.refresh_timer_r_reg__0 [4]),
        .O(\refresh_timer.refresh_timer_r[5]_i_6_n_0 ));
  FDSE \refresh_timer.refresh_timer_r_reg[0] 
       (.C(CLK),
        .CE(refresh_timer_r0_0),
        .D(refresh_timer_r0[0]),
        .Q(\refresh_timer.refresh_timer_r_reg__0 [0]),
        .S(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDRE \refresh_timer.refresh_timer_r_reg[1] 
       (.C(CLK),
        .CE(refresh_timer_r0_0),
        .D(\refresh_timer.refresh_timer_r[1]_i_1_n_0 ),
        .Q(\refresh_timer.refresh_timer_r_reg__0 [1]),
        .R(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDSE \refresh_timer.refresh_timer_r_reg[2] 
       (.C(CLK),
        .CE(refresh_timer_r0_0),
        .D(refresh_timer_r0[2]),
        .Q(\refresh_timer.refresh_timer_r_reg__0 [2]),
        .S(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDRE \refresh_timer.refresh_timer_r_reg[3] 
       (.C(CLK),
        .CE(refresh_timer_r0_0),
        .D(refresh_timer_r0[3]),
        .Q(\refresh_timer.refresh_timer_r_reg__0 [3]),
        .R(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDRE \refresh_timer.refresh_timer_r_reg[4] 
       (.C(CLK),
        .CE(refresh_timer_r0_0),
        .D(refresh_timer_r0[4]),
        .Q(\refresh_timer.refresh_timer_r_reg__0 [4]),
        .R(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDSE \refresh_timer.refresh_timer_r_reg[5] 
       (.C(CLK),
        .CE(refresh_timer_r0_0),
        .D(refresh_timer_r0[5]),
        .Q(\refresh_timer.refresh_timer_r_reg__0 [5]),
        .S(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_3 
       (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(\maint_controller.maint_srx_r1_reg ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAA8AAAAA)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_5 
       (.I0(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(\maint_controller.maint_srx_r1_reg ),
        .I3(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I4(insert_maint_r),
        .I5(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ));
  FDRE #(
    .INIT(1'b0)) 
    \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(sre_clears_sre_request),
        .Q(inhbt_srx),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00F0F8F8)) 
    \sr_cntrl.sre_request_logic.sre_request_r_i_1 
       (.I0(app_sr_req),
        .I1(init_calib_complete_reg_rep),
        .I2(sre_request_r),
        .I3(insert_maint_r1),
        .I4(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .O(\sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0 ));
  FDRE \sr_cntrl.sre_request_logic.sre_request_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0 ),
        .Q(sre_request_r),
        .R(rstdiv0_sync_r1_reg_rep__18));
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_1
       (.I0(wait_for_maint_r),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .O(wait_for_maint_r_lcl_reg));
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_1__0
       (.I0(wait_for_maint_r_0),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(periodic_rd_ack_r_lcl_reg_1),
        .O(wait_for_maint_r_lcl_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_1__1
       (.I0(wait_for_maint_r_1),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(periodic_rd_ack_r_lcl_reg_2),
        .O(wait_for_maint_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_1__2
       (.I0(wait_for_maint_r_2),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(periodic_rd_ack_r_lcl_reg_3),
        .O(wait_for_maint_r_lcl_reg_2));
  LUT5 #(
    .INIT(32'hFF2AFFFF)) 
    \zq_cntrl.zq_request_logic.zq_request_r_i_1 
       (.I0(zq_request_r),
        .I1(insert_maint_r1),
        .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I3(app_zq_req),
        .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),
        .O(\zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0 ));
  FDRE \zq_cntrl.zq_request_logic.zq_request_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0 ),
        .Q(zq_request_r),
        .R(rstdiv0_sync_r1_reg_rep__18));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_1 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),
        .O(zq_timer_r0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_10 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r[0]_i_15_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_11 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .I3(maint_prescaler_tick_r),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_12 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_13 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_14 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_15 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA8AAAAAAAA)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_2 
       (.I0(maint_prescaler_tick_r),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hA8AAAAAAAAAAAAAA)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_4 
       (.I0(init_calib_complete_reg_rep),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ),
        .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ),
        .I5(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_13_n_0 ),
        .I5(\zq_cntrl.zq_timer.zq_timer_r[0]_i_14_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_6 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_7 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_8 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_9 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[12]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[12]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[12]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[12]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[16]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[16]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[16]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[16]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[4]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[8]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[8]_i_5_n_0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[0] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .R(zq_timer_r0));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3 
       (.CI(1'b0),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),
        .S({\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[0]_i_8_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0 }));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[10] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .S(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[11] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[12] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .R(zq_timer_r0));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),
        .S({\zq_cntrl.zq_timer.zq_timer_r[12]_i_2_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[12]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[12]_i_4_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[12]_i_5_n_0 }));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[13] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .R(zq_timer_r0));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[14] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .S(zq_timer_r0));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[15] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .S(zq_timer_r0));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[16] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .S(zq_timer_r0));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ),
        .CO({\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED [3],\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),
        .S({\zq_cntrl.zq_timer.zq_timer_r[16]_i_2_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[16]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[16]_i_4_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[16]_i_5_n_0 }));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[17] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[18] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .R(zq_timer_r0));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[19] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .S(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[1] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[2] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[3] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[4] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .R(zq_timer_r0));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }),
        .S({\zq_cntrl.zq_timer.zq_timer_r[4]_i_2_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[4]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[4]_i_4_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[4]_i_5_n_0 }));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[5] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[6] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[7] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .R(zq_timer_r0));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[8] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .R(zq_timer_r0));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),
        .S({\zq_cntrl.zq_timer.zq_timer_r[8]_i_2_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[8]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[8]_i_4_n_0 ,\zq_cntrl.zq_timer.zq_timer_r[8]_i_5_n_0 }));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[9] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .R(zq_timer_r0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_rank_mach" *) 
module mig_7series_0_mig_7series_v2_3_rank_mach
   (maint_req_r,
    maint_sre_r,
    app_ref_ack,
    app_zq_ack,
    read_this_rank_r,
    inhbt_act_faw_r,
    maint_zq_r,
    maint_srx_r,
    \periodic_read_request.periodic_rd_r_lcl_reg ,
    maint_rank_r,
    app_sr_active,
    maint_ref_zq_wip,
    app_ref_r_reg,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    \maint_controller.maint_wip_r_lcl_reg ,
    Q,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    mc_cke_ns,
    \maint_controller.maint_hit_busies_r_reg[2] ,
    auto_pre_r_lcl_reg,
    q_has_rd_r_reg,
    pass_open_bank_r_lcl_reg,
    act_this_rank,
    CLK,
    read_this_rank,
    rstdiv0_sync_r1_reg_rep__18,
    maint_prescaler_r1,
    sre_clears_sre_request,
    rstdiv0_sync_r1_reg_rep__0,
    rstdiv0_sync_r1_reg_rep__1,
    init_calib_complete_reg_rep,
    insert_maint_r1,
    init_calib_complete_reg_rep_0,
    maint_wip_r,
    rstdiv0_sync_r1_reg_rep__19,
    periodic_rd_ack_r_lcl_reg,
    app_ref_req,
    app_zq_req,
    int_read_this_rank,
    wait_for_maint_r,
    periodic_rd_ack_r_lcl_reg_0,
    wait_for_maint_r_0,
    periodic_rd_ack_r_lcl_reg_1,
    wait_for_maint_r_1,
    periodic_rd_ack_r_lcl_reg_2,
    wait_for_maint_r_2,
    periodic_rd_ack_r_lcl_reg_3,
    app_sr_req,
    rstdiv0_sync_r1_reg_rep__20,
    \grant_r_reg[2] ,
    rstdiv0_sync_r1_reg_rep__21,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    insert_maint_r,
    cke_r,
    \maint_controller.maint_wip_r_lcl_reg_0 );
  output maint_req_r;
  output maint_sre_r;
  output app_ref_ack;
  output app_zq_ack;
  output read_this_rank_r;
  output inhbt_act_faw_r;
  output maint_zq_r;
  output maint_srx_r;
  output \periodic_read_request.periodic_rd_r_lcl_reg ;
  output maint_rank_r;
  output app_sr_active;
  output maint_ref_zq_wip;
  output app_ref_r_reg;
  output wait_for_maint_r_lcl_reg;
  output wait_for_maint_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_1;
  output wait_for_maint_r_lcl_reg_2;
  output \maint_controller.maint_wip_r_lcl_reg ;
  output [0:0]Q;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  output [0:0]mc_cke_ns;
  output \maint_controller.maint_hit_busies_r_reg[2] ;
  output auto_pre_r_lcl_reg;
  output q_has_rd_r_reg;
  output pass_open_bank_r_lcl_reg;
  input act_this_rank;
  input CLK;
  input read_this_rank;
  input rstdiv0_sync_r1_reg_rep__18;
  input maint_prescaler_r1;
  input sre_clears_sre_request;
  input rstdiv0_sync_r1_reg_rep__0;
  input rstdiv0_sync_r1_reg_rep__1;
  input init_calib_complete_reg_rep;
  input insert_maint_r1;
  input init_calib_complete_reg_rep_0;
  input maint_wip_r;
  input rstdiv0_sync_r1_reg_rep__19;
  input periodic_rd_ack_r_lcl_reg;
  input app_ref_req;
  input app_zq_req;
  input int_read_this_rank;
  input wait_for_maint_r;
  input periodic_rd_ack_r_lcl_reg_0;
  input wait_for_maint_r_0;
  input periodic_rd_ack_r_lcl_reg_1;
  input wait_for_maint_r_1;
  input periodic_rd_ack_r_lcl_reg_2;
  input wait_for_maint_r_2;
  input periodic_rd_ack_r_lcl_reg_3;
  input app_sr_req;
  input rstdiv0_sync_r1_reg_rep__20;
  input \grant_r_reg[2] ;
  input rstdiv0_sync_r1_reg_rep__21;
  input \generate_maint_cmds.insert_maint_r_lcl_reg ;
  input insert_maint_r;
  input cke_r;
  input \maint_controller.maint_wip_r_lcl_reg_0 ;

  wire CLK;
  wire [0:0]Q;
  wire act_this_rank;
  wire app_ref_ack;
  wire app_ref_r;
  wire app_ref_r_reg;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire auto_pre_r_lcl_reg;
  wire cke_r;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r_reg[2] ;
  wire inhbt_act_faw_r;
  wire init_calib_complete_reg_rep;
  wire init_calib_complete_reg_rep_0;
  wire insert_maint_r;
  wire insert_maint_r1;
  wire int_read_this_rank;
  wire \maint_controller.maint_hit_busies_r_reg[2] ;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire \maint_controller.maint_wip_r_lcl_reg_0 ;
  wire maint_prescaler_r1;
  wire maint_prescaler_tick_r;
  wire maint_rank_r;
  wire maint_ref_zq_wip;
  wire maint_req_r;
  wire maint_sre_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire [0:0]mc_cke_ns;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_ack_r_lcl_reg_2;
  wire periodic_rd_ack_r_lcl_reg_3;
  wire periodic_rd_cntr1_r;
  wire periodic_rd_grant_r;
  wire periodic_rd_request_r;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire q_has_rd_r_reg;
  wire \rank_cntrl[0].rank_cntrl0_n_6 ;
  wire \rank_cntrl[0].rank_cntrl0_n_7 ;
  wire rank_common0_n_14;
  wire rank_common0_n_15;
  wire read_this_rank;
  wire read_this_rank_r;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire rstdiv0_sync_r1_reg_rep__0;
  wire rstdiv0_sync_r1_reg_rep__1;
  wire rstdiv0_sync_r1_reg_rep__18;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sre_clears_sre_request;
  wire sre_request_r;
  wire wait_for_maint_r;
  wire wait_for_maint_r_0;
  wire wait_for_maint_r_1;
  wire wait_for_maint_r_2;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;

  mig_7series_0_mig_7series_v2_3_rank_cntrl \rank_cntrl[0].rank_cntrl0 
       (.CLK(CLK),
        .Q(Q),
        .act_this_rank(act_this_rank),
        .app_ref_r(app_ref_r),
        .app_ref_r_reg(app_ref_r_reg),
        .app_ref_r_reg_0(\rank_cntrl[0].rank_cntrl0_n_6 ),
        .app_ref_req(app_ref_req),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .init_calib_complete_reg_rep(rank_common0_n_15),
        .init_calib_complete_reg_rep_0(init_calib_complete_reg_rep),
        .int_read_this_rank(int_read_this_rank),
        .maint_prescaler_r1(maint_prescaler_r1),
        .maint_prescaler_tick_r(maint_prescaler_tick_r),
        .\maintenance_request.upd_last_master_r_reg (\rank_cntrl[0].rank_cntrl0_n_7 ),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_cntr1_r(periodic_rd_cntr1_r),
        .periodic_rd_grant_r(periodic_rd_grant_r),
        .periodic_rd_request_r(periodic_rd_request_r),
        .\periodic_read_request.periodic_rd_grant_r_reg[0] (rank_common0_n_14),
        .read_this_rank(read_this_rank),
        .read_this_rank_r(read_this_rank_r),
        .rstdiv0_sync_r1_reg_rep__1(rstdiv0_sync_r1_reg_rep__1),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sre_request_r(sre_request_r));
  mig_7series_0_mig_7series_v2_3_rank_common rank_common0
       (.CLK(CLK),
        .app_ref_ack(app_ref_ack),
        .app_ref_r(app_ref_r),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),
        .cke_r(cke_r),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .init_calib_complete_reg_rep(init_calib_complete_reg_rep),
        .init_calib_complete_reg_rep_0(init_calib_complete_reg_rep_0),
        .insert_maint_r(insert_maint_r),
        .insert_maint_r1(insert_maint_r1),
        .\maint_controller.maint_hit_busies_r_reg[2] (\maint_controller.maint_hit_busies_r_reg[2] ),
        .\maint_controller.maint_srx_r1_reg (maint_srx_r),
        .\maint_controller.maint_wip_r_lcl_reg (maint_req_r),
        .\maint_controller.maint_wip_r_lcl_reg_0 (\maint_controller.maint_wip_r_lcl_reg ),
        .\maint_controller.maint_wip_r_lcl_reg_1 (\maint_controller.maint_wip_r_lcl_reg_0 ),
        .maint_prescaler_r1(maint_prescaler_r1),
        .maint_prescaler_tick_r(maint_prescaler_tick_r),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .maint_wip_r(maint_wip_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0]_0 (maint_rank_r),
        .\maintenance_request.maint_srx_r_lcl_reg_0 (maint_sre_r),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (maint_zq_r),
        .mc_cke_ns(mc_cke_ns),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),
        .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),
        .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg_2),
        .periodic_rd_ack_r_lcl_reg_3(periodic_rd_ack_r_lcl_reg_3),
        .periodic_rd_cntr1_r(periodic_rd_cntr1_r),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg (rank_common0_n_14),
        .periodic_rd_grant_r(periodic_rd_grant_r),
        .periodic_rd_request_r(periodic_rd_request_r),
        .\periodic_read_request.periodic_rd_r_lcl_reg_0 (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .q_has_rd_r_reg(q_has_rd_r_reg),
        .\refresh_generation.refresh_bank_r_reg[0] (rank_common0_n_15),
        .\refresh_generation.refresh_bank_r_reg[0]_0 (\rank_cntrl[0].rank_cntrl0_n_6 ),
        .\refresh_generation.refresh_bank_r_reg[0]_1 (app_ref_r_reg),
        .\refresh_generation.refresh_bank_r_reg[0]_2 (\rank_cntrl[0].rank_cntrl0_n_7 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),
        .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),
        .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),
        .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),
        .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),
        .sre_clears_sre_request(sre_clears_sre_request),
        .sre_request_r(sre_request_r),
        .wait_for_maint_r(wait_for_maint_r),
        .wait_for_maint_r_0(wait_for_maint_r_0),
        .wait_for_maint_r_1(wait_for_maint_r_1),
        .wait_for_maint_r_2(wait_for_maint_r_2),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_0),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_1),
        .wait_for_maint_r_lcl_reg_2(wait_for_maint_r_lcl_reg_2));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_round_robin_arb" *) 
module mig_7series_0_mig_7series_v2_3_round_robin_arb
   (\maintenance_request.maint_rank_r_lcl_reg[0] ,
    maint_sre_ns,
    \maintenance_request.maint_srx_r_lcl_reg ,
    \maintenance_request.maint_zq_r_lcl_reg ,
    \maintenance_request.maint_rank_r_lcl_reg[0]_0 ,
    rstdiv0_sync_r1_reg_rep__21,
    upd_last_master_r,
    app_sr_req,
    inhbt_srx,
    \maintenance_request.maint_sre_r_lcl_reg ,
    \maintenance_request.maint_srx_r_lcl_reg_0 ,
    rstdiv0_sync_r1_reg_rep__19,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    zq_request_r,
    \sr_cntrl.sre_request_logic.sre_request_r_reg ,
    init_calib_complete_reg_rep,
    \refresh_generation.refresh_bank_r_reg[0] ,
    CLK);
  output \maintenance_request.maint_rank_r_lcl_reg[0] ;
  output maint_sre_ns;
  output \maintenance_request.maint_srx_r_lcl_reg ;
  output \maintenance_request.maint_zq_r_lcl_reg ;
  input \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  input rstdiv0_sync_r1_reg_rep__21;
  input upd_last_master_r;
  input app_sr_req;
  input inhbt_srx;
  input \maintenance_request.maint_sre_r_lcl_reg ;
  input \maintenance_request.maint_srx_r_lcl_reg_0 ;
  input rstdiv0_sync_r1_reg_rep__19;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input zq_request_r;
  input \sr_cntrl.sre_request_logic.sre_request_r_reg ;
  input init_calib_complete_reg_rep;
  input \refresh_generation.refresh_bank_r_reg[0] ;
  input CLK;

  wire CLK;
  wire app_sr_req;
  wire \grant_r[0]_i_1_n_0 ;
  wire \grant_r[1]_i_1_n_0 ;
  wire \grant_r[2]_i_1_n_0 ;
  wire \grant_r[2]_i_2__2_n_0 ;
  wire \grant_r_reg_n_0_[0] ;
  wire \grant_r_reg_n_0_[1] ;
  wire \grant_r_reg_n_0_[2] ;
  wire inhbt_srx;
  wire init_calib_complete_reg_rep;
  wire [2:0]last_master_r;
  wire \last_master_r[0]_i_1__3_n_0 ;
  wire \last_master_r[1]_i_1__3_n_0 ;
  wire \last_master_r[2]_i_1__3_n_0 ;
  wire maint_sre_ns;
  wire \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0 ;
  wire \maintenance_request.maint_rank_r_lcl[0]_i_3_n_0 ;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  wire \maintenance_request.maint_sre_r_lcl_reg ;
  wire \maintenance_request.maint_srx_r_lcl_reg ;
  wire \maintenance_request.maint_srx_r_lcl_reg_0 ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire \refresh_generation.refresh_bank_r_reg[0] ;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire \sr_cntrl.sre_request_logic.sre_request_r_reg ;
  wire upd_last_master_r;
  wire zq_request_r;

  LUT6 #(
    .INIT(64'h0000000007370000)) 
    \grant_r[0]_i_1 
       (.I0(zq_request_r),
        .I1(\last_master_r[0]_i_1__3_n_0 ),
        .I2(\sr_cntrl.sre_request_logic.sre_request_r_reg ),
        .I3(\last_master_r[1]_i_1__3_n_0 ),
        .I4(init_calib_complete_reg_rep),
        .I5(\refresh_generation.refresh_bank_r_reg[0] ),
        .O(\grant_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7000500070000000)) 
    \grant_r[1]_i_1 
       (.I0(\last_master_r[1]_i_1__3_n_0 ),
        .I1(\sr_cntrl.sre_request_logic.sre_request_r_reg ),
        .I2(zq_request_r),
        .I3(init_calib_complete_reg_rep),
        .I4(\refresh_generation.refresh_bank_r_reg[0] ),
        .I5(\grant_r[2]_i_2__2_n_0 ),
        .O(\grant_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000E000A000E000)) 
    \grant_r[2]_i_1 
       (.I0(\grant_r[2]_i_2__2_n_0 ),
        .I1(\refresh_generation.refresh_bank_r_reg[0] ),
        .I2(init_calib_complete_reg_rep),
        .I3(\sr_cntrl.sre_request_logic.sre_request_r_reg ),
        .I4(zq_request_r),
        .I5(\last_master_r[0]_i_1__3_n_0 ),
        .O(\grant_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT4 #(
    .INIT(16'h0151)) 
    \grant_r[2]_i_2__2 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(last_master_r[2]),
        .I2(upd_last_master_r),
        .I3(\grant_r_reg_n_0_[2] ),
        .O(\grant_r[2]_i_2__2_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1_n_0 ),
        .Q(\grant_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1_n_0 ),
        .Q(\grant_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1_n_0 ),
        .Q(\grant_r_reg_n_0_[2] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__3 
       (.I0(last_master_r[0]),
        .I1(upd_last_master_r),
        .I2(\grant_r_reg_n_0_[0] ),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[0]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__3 
       (.I0(last_master_r[1]),
        .I1(upd_last_master_r),
        .I2(\grant_r_reg_n_0_[1] ),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[1]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT4 #(
    .INIT(16'hFFB8)) 
    \last_master_r[2]_i_1__3 
       (.I0(\grant_r_reg_n_0_[2] ),
        .I1(upd_last_master_r),
        .I2(last_master_r[2]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[2]_i_1__3_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__3_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__3_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__3_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0080)) 
    \maintenance_request.maint_rank_r_lcl[0]_i_1 
       (.I0(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I1(\maintenance_request.maint_rank_r_lcl[0]_i_2_n_0 ),
        .I2(\maintenance_request.maint_rank_r_lcl[0]_i_3_n_0 ),
        .I3(maint_sre_ns),
        .O(\maintenance_request.maint_rank_r_lcl_reg[0] ));
  LUT6 #(
    .INIT(64'hFF5DFF5DFF5D005D)) 
    \maintenance_request.maint_rank_r_lcl[0]_i_2 
       (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I1(upd_last_master_r),
        .I2(\grant_r_reg_n_0_[2] ),
        .I3(\maintenance_request.maint_sre_r_lcl_reg ),
        .I4(inhbt_srx),
        .I5(app_sr_req),
        .O(\maintenance_request.maint_rank_r_lcl[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT5 #(
    .INIT(32'h00000535)) 
    \maintenance_request.maint_rank_r_lcl[0]_i_3 
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(\grant_r_reg_n_0_[1] ),
        .I2(upd_last_master_r),
        .I3(\grant_r_reg_n_0_[0] ),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .O(\maintenance_request.maint_rank_r_lcl[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFA800A8)) 
    \maintenance_request.maint_sre_r_lcl_i_1 
       (.I0(\maintenance_request.maint_sre_r_lcl_reg ),
        .I1(app_sr_req),
        .I2(inhbt_srx),
        .I3(upd_last_master_r),
        .I4(\grant_r_reg_n_0_[2] ),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(maint_sre_ns));
  LUT6 #(
    .INIT(64'h1F101F1F10101010)) 
    \maintenance_request.maint_srx_r_lcl_i_1 
       (.I0(app_sr_req),
        .I1(inhbt_srx),
        .I2(\maintenance_request.maint_sre_r_lcl_reg ),
        .I3(\grant_r_reg_n_0_[2] ),
        .I4(upd_last_master_r),
        .I5(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .O(\maintenance_request.maint_srx_r_lcl_reg ));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \maintenance_request.maint_zq_r_lcl_i_1 
       (.I0(\grant_r_reg_n_0_[1] ),
        .I1(upd_last_master_r),
        .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .O(\maintenance_request.maint_zq_r_lcl_reg ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_round_robin_arb" *) 
module mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1
   (Q,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[1]_1 ,
    D,
    \cmd_pipe_plus.mc_address_reg[13] ,
    \cmd_pipe_plus.mc_cas_n_reg[0] ,
    mc_ras_n_ns,
    act_this_rank,
    \grant_r_reg[1]_2 ,
    mc_cs_n_ns,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    sent_row,
    insert_maint_r1_lcl_reg,
    demand_act_priority_r_reg,
    p_115_out,
    rstdiv0_sync_r1_reg_rep__20,
    maint_zq_r,
    p_154_out,
    \req_row_r_lcl_reg[13] ,
    act_wait_r_lcl_reg,
    demand_act_priority_r_reg_0,
    demand_act_priority_r,
    head_r_lcl_reg,
    act_wait_r_lcl_reg_0,
    demand_act_priority_r_4,
    head_r_lcl_reg_0,
    act_wait_r_lcl_reg_1,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    inhbt_act_faw_r,
    demand_act_priority_r_5,
    \grant_r_reg[0]_0 ,
    head_r_lcl_reg_1,
    p_76_out,
    p_37_out,
    rstdiv0_sync_r1_reg_rep__21,
    maint_srx_r,
    act_this_rank_r,
    demand_act_priority_r_9,
    maint_rank_r,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \req_row_r_lcl_reg[13]_0 ,
    \req_row_r_lcl_reg[13]_1 ,
    \req_row_r_lcl_reg[13]_2 ,
    CLK);
  output [3:0]Q;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[1]_1 ;
  output [0:0]D;
  output [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  output [0:0]\cmd_pipe_plus.mc_cas_n_reg[0] ;
  output [0:0]mc_ras_n_ns;
  output act_this_rank;
  output \grant_r_reg[1]_2 ;
  output [0:0]mc_cs_n_ns;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  output \cmd_pipe_plus.mc_bank_reg[2]_0 ;
  input sent_row;
  input insert_maint_r1_lcl_reg;
  input demand_act_priority_r_reg;
  input p_115_out;
  input rstdiv0_sync_r1_reg_rep__20;
  input maint_zq_r;
  input p_154_out;
  input [13:0]\req_row_r_lcl_reg[13] ;
  input act_wait_r_lcl_reg;
  input demand_act_priority_r_reg_0;
  input demand_act_priority_r;
  input head_r_lcl_reg;
  input act_wait_r_lcl_reg_0;
  input demand_act_priority_r_4;
  input head_r_lcl_reg_0;
  input act_wait_r_lcl_reg_1;
  input \generate_maint_cmds.insert_maint_r_lcl_reg ;
  input inhbt_act_faw_r;
  input demand_act_priority_r_5;
  input \grant_r_reg[0]_0 ;
  input head_r_lcl_reg_1;
  input p_76_out;
  input p_37_out;
  input rstdiv0_sync_r1_reg_rep__21;
  input maint_srx_r;
  input [3:0]act_this_rank_r;
  input demand_act_priority_r_9;
  input maint_rank_r;
  input [2:0]\req_bank_r_lcl_reg[2] ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [2:0]\req_bank_r_lcl_reg[2]_2 ;
  input [12:0]\req_row_r_lcl_reg[13]_0 ;
  input [13:0]\req_row_r_lcl_reg[13]_1 ;
  input [12:0]\req_row_r_lcl_reg[13]_2 ;
  input CLK;

  wire CLK;
  wire [0:0]D;
  wire [3:0]Q;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire \cmd_pipe_plus.mc_address[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[10]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[11]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[12]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[13]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[1]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[2]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[3]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[4]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[5]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[6]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[7]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[8]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[9]_i_2_n_0 ;
  wire [13:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire \cmd_pipe_plus.mc_bank[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[1]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[2]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire \cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire \cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ;
  wire [0:0]\cmd_pipe_plus.mc_cas_n_reg[0] ;
  wire \cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ;
  wire \cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ;
  wire demand_act_priority_r;
  wire demand_act_priority_r_4;
  wire demand_act_priority_r_5;
  wire demand_act_priority_r_9;
  wire demand_act_priority_r_reg;
  wire demand_act_priority_r_reg_0;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r[0]_i_1__3_n_0 ;
  wire \grant_r[1]_i_1__3_n_0 ;
  wire \grant_r[1]_i_8_n_0 ;
  wire \grant_r[2]_i_1__3_n_0 ;
  wire \grant_r[2]_i_2_n_0 ;
  wire \grant_r[2]_i_3__0_n_0 ;
  wire \grant_r[3]_i_10_n_0 ;
  wire \grant_r[3]_i_1__2_n_0 ;
  wire \grant_r[3]_i_3__0_n_0 ;
  wire \grant_r[3]_i_4__1_n_0 ;
  wire \grant_r[3]_i_5__1_n_0 ;
  wire \grant_r[3]_i_6_n_0 ;
  wire \grant_r[3]_i_7__0_n_0 ;
  wire \grant_r[3]_i_9_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire \inhbt_act_faw.SRLC32E0_i_2_n_0 ;
  wire inhbt_act_faw_r;
  wire insert_maint_r1_lcl_reg;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1__0_n_0 ;
  wire \last_master_r[1]_i_1__1_n_0 ;
  wire \last_master_r[2]_i_1__0_n_0 ;
  wire \last_master_r[3]_i_1__1_n_0 ;
  wire maint_rank_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire [0:0]mc_cs_n_ns;
  wire [0:0]mc_ras_n_ns;
  wire p_115_out;
  wire p_154_out;
  wire p_37_out;
  wire p_76_out;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [12:0]\req_row_r_lcl_reg[13]_0 ;
  wire [13:0]\req_row_r_lcl_reg[13]_1 ;
  wire [12:0]\req_row_r_lcl_reg[13]_2 ;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire sent_row;

  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[0]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [0]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[0]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [0]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[0]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [0]),
        .I2(\req_row_r_lcl_reg[13]_1 [0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [0]),
        .O(\cmd_pipe_plus.mc_address[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF800000FF80FF80)) 
    \cmd_pipe_plus.mc_address[10]_i_1 
       (.I0(\req_row_r_lcl_reg[13] [10]),
        .I1(Q[0]),
        .I2(p_154_out),
        .I3(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[10]_i_2_n_0 ),
        .I5(act_wait_r_lcl_reg),
        .O(\cmd_pipe_plus.mc_address_reg[13] [10]));
  LUT5 #(
    .INIT(32'h0800FFFF)) 
    \cmd_pipe_plus.mc_address[10]_i_2 
       (.I0(p_76_out),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(\req_row_r_lcl_reg[13]_1 [10]),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_address[11]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [11]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[11]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .I5(\req_row_r_lcl_reg[13]_0 [10]),
        .O(\cmd_pipe_plus.mc_address_reg[13] [11]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_address[11]_i_2 
       (.I0(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .I1(\req_row_r_lcl_reg[13]_1 [11]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_row_r_lcl_reg[13]_2 [10]),
        .O(\cmd_pipe_plus.mc_address[11]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \cmd_pipe_plus.mc_address[11]_i_3 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\cmd_pipe_plus.mc_bank_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[12]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [12]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[12]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [12]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[12]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [11]),
        .I2(\req_row_r_lcl_reg[13]_1 [12]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [11]),
        .O(\cmd_pipe_plus.mc_address[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[13]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [13]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[13]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [13]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[13]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [12]),
        .I2(\req_row_r_lcl_reg[13]_1 [13]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [12]),
        .O(\cmd_pipe_plus.mc_address[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[1]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [1]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[1]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [1]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[1]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [1]),
        .I2(\req_row_r_lcl_reg[13]_1 [1]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [1]),
        .O(\cmd_pipe_plus.mc_address[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_address[2]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [2]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[2]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .I5(\req_row_r_lcl_reg[13]_0 [2]),
        .O(\cmd_pipe_plus.mc_address_reg[13] [2]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_address[2]_i_2 
       (.I0(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .I1(\req_row_r_lcl_reg[13]_1 [2]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_row_r_lcl_reg[13]_2 [2]),
        .O(\cmd_pipe_plus.mc_address[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[3]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [3]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[3]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [3]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[3]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [3]),
        .I2(\req_row_r_lcl_reg[13]_1 [3]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [3]),
        .O(\cmd_pipe_plus.mc_address[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[4]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [4]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[4]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [4]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[4]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [4]),
        .I2(\req_row_r_lcl_reg[13]_1 [4]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [4]),
        .O(\cmd_pipe_plus.mc_address[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[5]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [5]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[5]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [5]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[5]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [5]),
        .I2(\req_row_r_lcl_reg[13]_1 [5]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [5]),
        .O(\cmd_pipe_plus.mc_address[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_address[6]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [6]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[6]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .I5(\req_row_r_lcl_reg[13]_0 [6]),
        .O(\cmd_pipe_plus.mc_address_reg[13] [6]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_address[6]_i_2 
       (.I0(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .I1(\req_row_r_lcl_reg[13]_1 [6]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_row_r_lcl_reg[13]_2 [6]),
        .O(\cmd_pipe_plus.mc_address[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[7]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [7]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[7]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [7]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[7]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [7]),
        .I2(\req_row_r_lcl_reg[13]_1 [7]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [7]),
        .O(\cmd_pipe_plus.mc_address[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[8]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [8]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[8]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [8]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[8]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [8]),
        .I2(\req_row_r_lcl_reg[13]_1 [8]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [8]),
        .O(\cmd_pipe_plus.mc_address[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[9]_i_1 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [9]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_address[9]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_address_reg[13] [9]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_address[9]_i_2 
       (.I0(Q[1]),
        .I1(\req_row_r_lcl_reg[13]_0 [9]),
        .I2(\req_row_r_lcl_reg[13]_1 [9]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_row_r_lcl_reg[13]_2 [9]),
        .O(\cmd_pipe_plus.mc_address[9]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_bank[0]_i_1 
       (.I0(Q[0]),
        .I1(\req_bank_r_lcl_reg[2] [0]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(\cmd_pipe_plus.mc_bank_reg[2] [0]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_bank[0]_i_2 
       (.I0(Q[1]),
        .I1(\req_bank_r_lcl_reg[2]_0 [0]),
        .I2(\req_bank_r_lcl_reg[2]_1 [0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\req_bank_r_lcl_reg[2]_2 [0]),
        .O(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_bank[1]_i_1 
       (.I0(Q[0]),
        .I1(\req_bank_r_lcl_reg[2] [1]),
        .I2(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I3(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .I5(\req_bank_r_lcl_reg[2]_0 [1]),
        .O(\cmd_pipe_plus.mc_bank_reg[2] [1]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_bank[1]_i_2 
       (.I0(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .I1(\req_bank_r_lcl_reg[2]_1 [1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_bank_r_lcl_reg[2]_2 [1]),
        .O(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEA00EAEAEA00EA00)) 
    \cmd_pipe_plus.mc_bank[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I1(Q[0]),
        .I2(\req_bank_r_lcl_reg[2] [2]),
        .I3(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .I5(\req_bank_r_lcl_reg[2]_0 [2]),
        .O(\cmd_pipe_plus.mc_bank_reg[2] [2]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_bank[2]_i_2 
       (.I0(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .I1(\req_bank_r_lcl_reg[2]_1 [2]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_bank_r_lcl_reg[2]_2 [2]),
        .O(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFEFFFFAAAA)) 
    \cmd_pipe_plus.mc_cas_n[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I1(maint_zq_r),
        .I2(maint_srx_r),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .I4(Q[0]),
        .I5(insert_maint_r1_lcl_reg),
        .O(\cmd_pipe_plus.mc_cas_n_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair757" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF1)) 
    \cmd_pipe_plus.mc_cas_n[0]_i_2 
       (.I0(sent_row),
        .I1(insert_maint_r1_lcl_reg),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0355005500550055)) 
    \cmd_pipe_plus.mc_cs_n[0]_i_1 
       (.I0(sent_row),
        .I1(rstdiv0_sync_r1_reg_rep__21),
        .I2(Q[0]),
        .I3(insert_maint_r1_lcl_reg),
        .I4(maint_rank_r),
        .I5(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(mc_cs_n_ns));
  (* SOFT_HLUTNM = "soft_lutpair758" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \cmd_pipe_plus.mc_cs_n[0]_i_2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[1]),
        .O(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000E0E0EFF)) 
    \cmd_pipe_plus.mc_ras_n[0]_i_1 
       (.I0(maint_zq_r),
        .I1(maint_srx_r),
        .I2(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ),
        .I3(insert_maint_r1_lcl_reg),
        .I4(sent_row),
        .I5(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ),
        .O(mc_ras_n_ns));
  LUT3 #(
    .INIT(8'hFD)) 
    \cmd_pipe_plus.mc_ras_n[0]_i_2 
       (.I0(insert_maint_r1_lcl_reg),
        .I1(Q[0]),
        .I2(rstdiv0_sync_r1_reg_rep__21),
        .O(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair757" *) 
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \cmd_pipe_plus.mc_ras_n[0]_i_3 
       (.I0(sent_row),
        .I1(insert_maint_r1_lcl_reg),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(\cmd_pipe_plus.mc_ras_n[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCCCCCCCCCCFCCCDD)) 
    \cmd_pipe_plus.mc_we_n[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ),
        .I2(p_115_out),
        .I3(Q[2]),
        .I4(Q[1]),
        .I5(Q[3]),
        .O(D));
  LUT5 #(
    .INIT(32'h00FDFFFD)) 
    \cmd_pipe_plus.mc_we_n[0]_i_2 
       (.I0(insert_maint_r1_lcl_reg),
        .I1(rstdiv0_sync_r1_reg_rep__20),
        .I2(maint_zq_r),
        .I3(Q[0]),
        .I4(p_154_out),
        .O(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF000F888F888F)) 
    \cmd_pipe_plus.mc_we_n[0]_i_3 
       (.I0(Q[2]),
        .I1(p_76_out),
        .I2(insert_maint_r1_lcl_reg),
        .I3(sent_row),
        .I4(p_37_out),
        .I5(Q[3]),
        .O(\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h11010000)) 
    \grant_r[0]_i_1__3 
       (.I0(\grant_r[3]_i_3__0_n_0 ),
        .I1(\grant_r[2]_i_2_n_0 ),
        .I2(\grant_r[3]_i_5__1_n_0 ),
        .I3(\grant_r_reg[1]_0 ),
        .I4(\grant_r_reg[1]_1 ),
        .O(\grant_r[0]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h0005000000450045)) 
    \grant_r[1]_i_1__3 
       (.I0(demand_act_priority_r_reg_0),
        .I1(\grant_r[2]_i_3__0_n_0 ),
        .I2(\grant_r_reg[1]_1 ),
        .I3(\grant_r[2]_i_2_n_0 ),
        .I4(\grant_r_reg[1]_0 ),
        .I5(\last_master_r[1]_i_1__1_n_0 ),
        .O(\grant_r[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FF0B)) 
    \grant_r[1]_i_3__2 
       (.I0(Q[2]),
        .I1(demand_act_priority_r),
        .I2(\grant_r[1]_i_8_n_0 ),
        .I3(demand_act_priority_r_5),
        .I4(\grant_r_reg[0]_0 ),
        .I5(head_r_lcl_reg_1),
        .O(\grant_r_reg[1]_1 ));
  LUT2 #(
    .INIT(4'h8)) 
    \grant_r[1]_i_4__0 
       (.I0(\grant_r[3]_i_6_n_0 ),
        .I1(\grant_r[3]_i_4__1_n_0 ),
        .O(\grant_r_reg[1]_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \grant_r[1]_i_5 
       (.I0(demand_act_priority_r_5),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(demand_act_priority_r),
        .O(\grant_r_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair758" *) 
  LUT4 #(
    .INIT(16'h4F44)) 
    \grant_r[1]_i_8 
       (.I0(Q[3]),
        .I1(demand_act_priority_r_4),
        .I2(Q[1]),
        .I3(demand_act_priority_r_9),
        .O(\grant_r[1]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h00001110)) 
    \grant_r[2]_i_1__3 
       (.I0(\grant_r[3]_i_3__0_n_0 ),
        .I1(\grant_r[2]_i_2_n_0 ),
        .I2(\grant_r[2]_i_3__0_n_0 ),
        .I3(demand_act_priority_r_reg),
        .I4(\grant_r[3]_i_6_n_0 ),
        .O(\grant_r[2]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair756" *) 
  LUT5 #(
    .INIT(32'h00004540)) 
    \grant_r[2]_i_2 
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(Q[2]),
        .I2(sent_row),
        .I3(last_master_r[2]),
        .I4(\grant_r[3]_i_4__1_n_0 ),
        .O(\grant_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000005000533)) 
    \grant_r[2]_i_3__0 
       (.I0(Q[2]),
        .I1(last_master_r[2]),
        .I2(Q[3]),
        .I3(sent_row),
        .I4(last_master_r[3]),
        .I5(rstdiv0_sync_r1_reg_rep__20),
        .O(\grant_r[2]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \grant_r[3]_i_10 
       (.I0(demand_act_priority_r_5),
        .I1(Q[0]),
        .I2(demand_act_priority_r_9),
        .I3(Q[1]),
        .I4(demand_act_priority_r_4),
        .I5(Q[3]),
        .O(\grant_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0202030300000003)) 
    \grant_r[3]_i_1__2 
       (.I0(demand_act_priority_r_reg),
        .I1(\grant_r[3]_i_3__0_n_0 ),
        .I2(\grant_r[3]_i_4__1_n_0 ),
        .I3(\grant_r[3]_i_5__1_n_0 ),
        .I4(\last_master_r[3]_i_1__1_n_0 ),
        .I5(\grant_r[3]_i_6_n_0 ),
        .O(\grant_r[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair755" *) 
  LUT5 #(
    .INIT(32'h00004540)) 
    \grant_r[3]_i_3__0 
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(Q[0]),
        .I2(sent_row),
        .I3(last_master_r[0]),
        .I4(demand_act_priority_r_reg_0),
        .O(\grant_r[3]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF1)) 
    \grant_r[3]_i_4__1 
       (.I0(\grant_r[3]_i_7__0_n_0 ),
        .I1(demand_act_priority_r_4),
        .I2(head_r_lcl_reg_0),
        .I3(act_wait_r_lcl_reg_1),
        .I4(Q[3]),
        .I5(\grant_r[3]_i_9_n_0 ),
        .O(\grant_r[3]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h0F0A0F0F0F0A0C0C)) 
    \grant_r[3]_i_5__1 
       (.I0(Q[0]),
        .I1(last_master_r[0]),
        .I2(rstdiv0_sync_r1_reg_rep__20),
        .I3(Q[1]),
        .I4(sent_row),
        .I5(last_master_r[1]),
        .O(\grant_r[3]_i_5__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF1)) 
    \grant_r[3]_i_6 
       (.I0(\grant_r[3]_i_10_n_0 ),
        .I1(demand_act_priority_r),
        .I2(head_r_lcl_reg),
        .I3(act_wait_r_lcl_reg_0),
        .I4(Q[2]),
        .I5(\grant_r[3]_i_9_n_0 ),
        .O(\grant_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hD0DD0000D0DDD0DD)) 
    \grant_r[3]_i_7__0 
       (.I0(demand_act_priority_r),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(demand_act_priority_r_5),
        .I4(Q[1]),
        .I5(demand_act_priority_r_9),
        .O(\grant_r[3]_i_7__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF8FFF8FFF8)) 
    \grant_r[3]_i_9 
       (.I0(Q[0]),
        .I1(p_154_out),
        .I2(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .I3(inhbt_act_faw_r),
        .I4(p_115_out),
        .I5(Q[1]),
        .O(\grant_r[3]_i_9_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__3_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__3_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__3_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__2_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \inhbt_act_faw.SRLC32E0_i_1 
       (.I0(Q[2]),
        .I1(act_this_rank_r[2]),
        .I2(Q[1]),
        .I3(act_this_rank_r[1]),
        .I4(\inhbt_act_faw.SRLC32E0_i_2_n_0 ),
        .O(act_this_rank));
  LUT4 #(
    .INIT(16'hF888)) 
    \inhbt_act_faw.SRLC32E0_i_2 
       (.I0(act_this_rank_r[3]),
        .I1(Q[3]),
        .I2(act_this_rank_r[0]),
        .I3(Q[0]),
        .O(\inhbt_act_faw.SRLC32E0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair755" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__0 
       (.I0(last_master_r[0]),
        .I1(sent_row),
        .I2(Q[0]),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .O(\last_master_r[0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__1 
       (.I0(last_master_r[1]),
        .I1(sent_row),
        .I2(Q[1]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair756" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__0 
       (.I0(last_master_r[2]),
        .I1(sent_row),
        .I2(Q[2]),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .O(\last_master_r[2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \last_master_r[3]_i_1__1 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(last_master_r[3]),
        .I2(sent_row),
        .I3(Q[3]),
        .O(\last_master_r[3]_i_1__1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__0_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__1_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__0_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__1_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_round_robin_arb" *) 
module mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized2
   (Q,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    D,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    rstdiv0_sync_r1_reg_rep__21,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_row_r_lcl_reg[13] ,
    \req_row_r_lcl_reg[13]_0 ,
    auto_pre_r_lcl_reg,
    auto_pre_r_lcl_reg_0,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    auto_pre_r_lcl_reg_1,
    ras_timer_zero_r_reg_2,
    auto_pre_r_lcl_reg_2,
    rstdiv0_sync_r1_reg_rep__20,
    p_37_out,
    p_76_out,
    p_154_out,
    p_115_out,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \req_row_r_lcl_reg[13]_1 ,
    \req_row_r_lcl_reg[13]_2 ,
    CLK);
  output [3:0]Q;
  output [0:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  output [1:0]D;
  output [0:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  output [12:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input rstdiv0_sync_r1_reg_rep__21;
  input \pre_4_1_1T_arb.granted_pre_r_reg ;
  input [2:0]\req_bank_r_lcl_reg[2] ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [12:0]\req_row_r_lcl_reg[13] ;
  input [12:0]\req_row_r_lcl_reg[13]_0 ;
  input auto_pre_r_lcl_reg;
  input auto_pre_r_lcl_reg_0;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input auto_pre_r_lcl_reg_1;
  input ras_timer_zero_r_reg_2;
  input auto_pre_r_lcl_reg_2;
  input rstdiv0_sync_r1_reg_rep__20;
  input p_37_out;
  input p_76_out;
  input p_154_out;
  input p_115_out;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [2:0]\req_bank_r_lcl_reg[2]_2 ;
  input [12:0]\req_row_r_lcl_reg[13]_1 ;
  input [12:0]\req_row_r_lcl_reg[13]_2 ;
  input CLK;

  wire CLK;
  wire [1:0]D;
  wire [3:0]Q;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire \cmd_pipe_plus.mc_address[28]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[29]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[30]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[31]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[32]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[33]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[34]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[35]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[36]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[37]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[39]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[40]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[41]_i_2_n_0 ;
  wire [12:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire \cmd_pipe_plus.mc_bank[6]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[7]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[8]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [0:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire \cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ;
  wire [0:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire \grant_r[0]_i_1__1_n_0 ;
  wire \grant_r[1]_i_1__2_n_0 ;
  wire \grant_r[1]_i_2__1_n_0 ;
  wire \grant_r[2]_i_1__1_n_0 ;
  wire \grant_r[3]_i_1__1_n_0 ;
  wire \grant_r[3]_i_2__1_n_0 ;
  wire \grant_r[3]_i_3__2_n_0 ;
  wire [3:0]last_master_r;
  wire \last_master_r[1]_i_1__2_n_0 ;
  wire \last_master_r[3]_i_1__2_n_0 ;
  wire p_115_out;
  wire p_154_out;
  wire p_37_out;
  wire p_76_out;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [12:0]\req_row_r_lcl_reg[13] ;
  wire [12:0]\req_row_r_lcl_reg[13]_0 ;
  wire [12:0]\req_row_r_lcl_reg[13]_1 ;
  wire [12:0]\req_row_r_lcl_reg[13]_2 ;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;

  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[28]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[28]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [0]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [0]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [0]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[28]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [0]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [0]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[29]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[29]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [1]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [1]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [1]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[29]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [1]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [1]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[30]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[30]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [2]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [2]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [2]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[30]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [2]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [2]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[31]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[31]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [3]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [3]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[31]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [3]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [3]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[32]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[32]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [4]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [4]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [4]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[32]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [4]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [4]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[33]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[33]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [5]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [5]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [5]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[33]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [5]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [5]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[33]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[34]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[34]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [6]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [6]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [6]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[34]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [6]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [6]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[34]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[35]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[35]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [7]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [7]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [7]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[35]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [7]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [7]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[35]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[36]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[36]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [8]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [8]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [8]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[36]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [8]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [8]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[36]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[37]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[37]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [9]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [9]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [9]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[37]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [9]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [9]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[37]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[39]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[39]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [10]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [10]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [10]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[39]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [10]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [10]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[39]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[40]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[40]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [11]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [11]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [11]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[40]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [11]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [11]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[40]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_address[41]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[41]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(\req_row_r_lcl_reg[13]_1 [12]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_row_r_lcl_reg[13]_2 [12]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address_reg[41] [12]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_address[41]_i_2 
       (.I0(Q[0]),
        .I1(\req_row_r_lcl_reg[13] [12]),
        .I2(Q[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [12]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_address[41]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_bank[6]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[6]_i_2_n_0 ),
        .I1(\req_bank_r_lcl_reg[2]_1 [0]),
        .I2(Q[3]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_bank_r_lcl_reg[2]_2 [0]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_bank_reg[8] [0]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_bank[6]_i_2 
       (.I0(\req_bank_r_lcl_reg[2] [0]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\req_bank_r_lcl_reg[2]_0 [0]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_bank[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_bank[7]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[7]_i_2_n_0 ),
        .I1(\req_bank_r_lcl_reg[2]_1 [1]),
        .I2(Q[3]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_bank_r_lcl_reg[2]_2 [1]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_bank_reg[8] [1]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_bank[7]_i_2 
       (.I0(\req_bank_r_lcl_reg[2] [1]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\req_bank_r_lcl_reg[2]_0 [1]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_bank[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_bank[8]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[8]_i_2_n_0 ),
        .I1(\req_bank_r_lcl_reg[2]_1 [2]),
        .I2(Q[3]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\req_bank_r_lcl_reg[2]_2 [2]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_bank_reg[8] [2]));
  LUT6 #(
    .INIT(64'h000000000000F808)) 
    \cmd_pipe_plus.mc_bank[8]_i_2 
       (.I0(\req_bank_r_lcl_reg[2] [2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\req_bank_r_lcl_reg[2]_0 [2]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_bank[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFB)) 
    \cmd_pipe_plus.mc_cas_n[2]_i_1 
       (.I0(Q[1]),
        .I1(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[2]),
        .O(\cmd_pipe_plus.mc_cas_n_reg[2] ));
  LUT6 #(
    .INIT(64'hFBFFEAFFEAFFEAFF)) 
    \cmd_pipe_plus.mc_we_n[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ),
        .I1(Q[3]),
        .I2(p_37_out),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(p_76_out),
        .I5(Q[2]),
        .O(\cmd_pipe_plus.mc_we_n_reg[2] ));
  LUT6 #(
    .INIT(64'h1111100000001000)) 
    \cmd_pipe_plus.mc_we_n[2]_i_2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(p_154_out),
        .I4(Q[1]),
        .I5(p_115_out),
        .O(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00F10000F0F10000)) 
    \grant_r[0]_i_1__1 
       (.I0(\last_master_r[1]_i_1__2_n_0 ),
        .I1(ras_timer_zero_r_reg),
        .I2(ras_timer_zero_r_reg_0),
        .I3(D[0]),
        .I4(auto_pre_r_lcl_reg),
        .I5(auto_pre_r_lcl_reg_0),
        .O(\grant_r[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AAAA00000000)) 
    \grant_r[1]_i_1__2 
       (.I0(\grant_r[1]_i_2__1_n_0 ),
        .I1(D[1]),
        .I2(\grant_r[3]_i_3__2_n_0 ),
        .I3(\last_master_r[1]_i_1__2_n_0 ),
        .I4(auto_pre_r_lcl_reg),
        .I5(auto_pre_r_lcl_reg_0),
        .O(\grant_r[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBAAABBBAB)) 
    \grant_r[1]_i_2__1 
       (.I0(ras_timer_zero_r_reg_0),
        .I1(ras_timer_zero_r_reg),
        .I2(last_master_r[1]),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(Q[1]),
        .I5(rstdiv0_sync_r1_reg_rep__20),
        .O(\grant_r[1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00F00020F0F00020)) 
    \grant_r[2]_i_1__1 
       (.I0(\grant_r[3]_i_3__2_n_0 ),
        .I1(ras_timer_zero_r_reg_1),
        .I2(auto_pre_r_lcl_reg_1),
        .I3(D[1]),
        .I4(ras_timer_zero_r_reg_2),
        .I5(auto_pre_r_lcl_reg_2),
        .O(\grant_r[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AAAA00000000)) 
    \grant_r[3]_i_1__1 
       (.I0(\grant_r[3]_i_2__1_n_0 ),
        .I1(D[0]),
        .I2(\grant_r[3]_i_3__2_n_0 ),
        .I3(\last_master_r[1]_i_1__2_n_0 ),
        .I4(auto_pre_r_lcl_reg_1),
        .I5(auto_pre_r_lcl_reg_2),
        .O(\grant_r[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAABABABAAAB)) 
    \grant_r[3]_i_2__1 
       (.I0(ras_timer_zero_r_reg_2),
        .I1(ras_timer_zero_r_reg_1),
        .I2(rstdiv0_sync_r1_reg_rep__20),
        .I3(last_master_r[3]),
        .I4(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I5(Q[3]),
        .O(\grant_r[3]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair754" *) 
  LUT4 #(
    .INIT(16'h0151)) 
    \grant_r[3]_i_3__2 
       (.I0(rstdiv0_sync_r1_reg_rep__21),
        .I1(last_master_r[3]),
        .I2(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I3(Q[3]),
        .O(\grant_r[3]_i_3__2_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__1_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__2_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__1_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__2 
       (.I0(last_master_r[0]),
        .I1(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I2(Q[0]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(D[0]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__2 
       (.I0(last_master_r[1]),
        .I1(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I2(Q[1]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[1]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__2 
       (.I0(last_master_r[2]),
        .I1(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I2(Q[2]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair754" *) 
  LUT4 #(
    .INIT(16'hFFB8)) 
    \last_master_r[3]_i_1__2 
       (.I0(Q[3]),
        .I1(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I2(last_master_r[3]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[3]_i_1__2_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__2_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__2_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_round_robin_arb" *) 
module mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized3
   (\grant_r_reg[2]_0 ,
    \rnk_config_r_reg[0] ,
    demand_priority_r_reg,
    col_wait_r,
    \order_q_r_reg[0] ,
    demand_priority_r_reg_0,
    col_wait_r_0,
    \order_q_r_reg[0]_0 ,
    rnk_config_strobe,
    rnk_config_r,
    rstdiv0_sync_r1_reg_rep__24,
    col_wait_r_reg,
    col_wait_r_reg_0,
    col_wait_r_reg_1,
    col_wait_r_reg_2,
    col_wait_r_reg_3,
    rstdiv0_sync_r1_reg_rep__19,
    col_wait_r_reg_4,
    rstdiv0_sync_r1_reg_rep__20,
    rnk_config_strobe_0,
    rnk_config_valid_r,
    rstdiv0_sync_r1_reg_rep__21,
    CLK);
  output \grant_r_reg[2]_0 ;
  output \rnk_config_r_reg[0] ;
  input demand_priority_r_reg;
  input col_wait_r;
  input \order_q_r_reg[0] ;
  input demand_priority_r_reg_0;
  input col_wait_r_0;
  input \order_q_r_reg[0]_0 ;
  input rnk_config_strobe;
  input rnk_config_r;
  input rstdiv0_sync_r1_reg_rep__24;
  input col_wait_r_reg;
  input col_wait_r_reg_0;
  input col_wait_r_reg_1;
  input col_wait_r_reg_2;
  input col_wait_r_reg_3;
  input rstdiv0_sync_r1_reg_rep__19;
  input col_wait_r_reg_4;
  input rstdiv0_sync_r1_reg_rep__20;
  input [1:0]rnk_config_strobe_0;
  input rnk_config_valid_r;
  input rstdiv0_sync_r1_reg_rep__21;
  input CLK;

  wire CLK;
  wire col_wait_r;
  wire col_wait_r_0;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire col_wait_r_reg_2;
  wire col_wait_r_reg_3;
  wire col_wait_r_reg_4;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire [3:0]grant_config_r;
  wire \grant_r[0]_i_1__2_n_0 ;
  wire \grant_r[1]_i_1__1_n_0 ;
  wire \grant_r[2]_i_1__2_n_0 ;
  wire \grant_r[2]_i_2__1_n_0 ;
  wire \grant_r[2]_i_3__1_n_0 ;
  wire \grant_r[2]_i_4_n_0 ;
  wire \grant_r[3]_i_1__0_n_0 ;
  wire \grant_r[3]_i_3_n_0 ;
  wire \grant_r[3]_i_4__0_n_0 ;
  wire \grant_r_reg[2]_0 ;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1__1_n_0 ;
  wire \last_master_r[1]_i_1__0_n_0 ;
  wire \last_master_r[2]_i_1__1_n_0 ;
  wire \last_master_r[3]_i_1_n_0 ;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[0]_0 ;
  wire rnk_config_r;
  wire \rnk_config_r[0]_i_2_n_0 ;
  wire \rnk_config_r_reg[0] ;
  wire rnk_config_strobe;
  wire [1:0]rnk_config_strobe_0;
  wire rnk_config_valid_r;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__21;
  wire rstdiv0_sync_r1_reg_rep__24;

  LUT6 #(
    .INIT(64'h1010101000000010)) 
    \grant_r[0]_i_1__2 
       (.I0(\grant_r[2]_i_2__1_n_0 ),
        .I1(\grant_r[2]_i_3__1_n_0 ),
        .I2(col_wait_r_reg),
        .I3(\last_master_r[0]_i_1__1_n_0 ),
        .I4(\last_master_r[1]_i_1__0_n_0 ),
        .I5(col_wait_r_reg_0),
        .O(\grant_r[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0011000010111011)) 
    \grant_r[1]_i_1__1 
       (.I0(col_wait_r_reg_3),
        .I1(\grant_r[2]_i_3__1_n_0 ),
        .I2(\grant_r[2]_i_4_n_0 ),
        .I3(col_wait_r_reg),
        .I4(col_wait_r_reg_0),
        .I5(\last_master_r[1]_i_1__0_n_0 ),
        .O(\grant_r[1]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h11010000)) 
    \grant_r[2]_i_1__2 
       (.I0(\grant_r[2]_i_2__1_n_0 ),
        .I1(\grant_r[2]_i_3__1_n_0 ),
        .I2(col_wait_r_reg_1),
        .I3(\grant_r[2]_i_4_n_0 ),
        .I4(col_wait_r_reg_2),
        .O(\grant_r[2]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \grant_r[2]_i_2__1 
       (.I0(demand_priority_r_reg_0),
        .I1(\last_master_r[0]_i_1__1_n_0 ),
        .I2(col_wait_r_0),
        .I3(\order_q_r_reg[0]_0 ),
        .I4(\grant_r_reg[2]_0 ),
        .O(\grant_r[2]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \grant_r[2]_i_3__1 
       (.I0(demand_priority_r_reg),
        .I1(\last_master_r[2]_i_1__1_n_0 ),
        .I2(col_wait_r),
        .I3(\order_q_r_reg[0] ),
        .I4(\grant_r_reg[2]_0 ),
        .O(\grant_r[2]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h0003000000030505)) 
    \grant_r[2]_i_4 
       (.I0(last_master_r[3]),
        .I1(grant_config_r[3]),
        .I2(rstdiv0_sync_r1_reg_rep__20),
        .I3(grant_config_r[2]),
        .I4(rnk_config_strobe),
        .I5(last_master_r[2]),
        .O(\grant_r[2]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFEFEFFFE)) 
    \grant_r[2]_i_7 
       (.I0(rnk_config_strobe),
        .I1(rnk_config_strobe_0[1]),
        .I2(rnk_config_strobe_0[0]),
        .I3(rnk_config_valid_r),
        .I4(\rnk_config_r_reg[0] ),
        .O(\grant_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h000000005755575F)) 
    \grant_r[3]_i_1__0 
       (.I0(col_wait_r_reg_1),
        .I1(grant_config_r[3]),
        .I2(rstdiv0_sync_r1_reg_rep__19),
        .I3(rnk_config_strobe),
        .I4(last_master_r[3]),
        .I5(\grant_r[3]_i_3_n_0 ),
        .O(\grant_r[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFB00)) 
    \grant_r[3]_i_3 
       (.I0(\last_master_r[0]_i_1__1_n_0 ),
        .I1(\grant_r[3]_i_4__0_n_0 ),
        .I2(\last_master_r[1]_i_1__0_n_0 ),
        .I3(col_wait_r_reg_2),
        .I4(col_wait_r_reg_4),
        .I5(\grant_r[2]_i_2__1_n_0 ),
        .O(\grant_r[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair753" *) 
  LUT4 #(
    .INIT(16'h1013)) 
    \grant_r[3]_i_4__0 
       (.I0(grant_config_r[3]),
        .I1(rstdiv0_sync_r1_reg_rep__20),
        .I2(rnk_config_strobe),
        .I3(last_master_r[3]),
        .O(\grant_r[3]_i_4__0_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__2_n_0 ),
        .Q(grant_config_r[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__1_n_0 ),
        .Q(grant_config_r[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__2_n_0 ),
        .Q(grant_config_r[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__0_n_0 ),
        .Q(grant_config_r[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__1 
       (.I0(last_master_r[0]),
        .I1(rnk_config_strobe),
        .I2(grant_config_r[0]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__0 
       (.I0(last_master_r[1]),
        .I1(rnk_config_strobe),
        .I2(grant_config_r[1]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__1 
       (.I0(last_master_r[2]),
        .I1(rnk_config_strobe),
        .I2(grant_config_r[2]),
        .I3(rstdiv0_sync_r1_reg_rep__21),
        .O(\last_master_r[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair753" *) 
  LUT4 #(
    .INIT(16'hFEF2)) 
    \last_master_r[3]_i_1 
       (.I0(last_master_r[3]),
        .I1(rnk_config_strobe),
        .I2(rstdiv0_sync_r1_reg_rep__20),
        .I3(grant_config_r[3]),
        .O(\last_master_r[3]_i_1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__1_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__0_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__1_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000001FF)) 
    \rnk_config_r[0]_i_1 
       (.I0(grant_config_r[2]),
        .I1(grant_config_r[0]),
        .I2(grant_config_r[1]),
        .I3(rnk_config_strobe),
        .I4(\rnk_config_r[0]_i_2_n_0 ),
        .O(\rnk_config_r_reg[0] ));
  LUT4 #(
    .INIT(16'hFF8F)) 
    \rnk_config_r[0]_i_2 
       (.I0(rnk_config_strobe),
        .I1(grant_config_r[3]),
        .I2(rnk_config_r),
        .I3(rstdiv0_sync_r1_reg_rep__24),
        .O(\rnk_config_r[0]_i_2_n_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_round_robin_arb" *) 
module mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized4
   (\cmd_pipe_plus.mc_ras_n_reg[1] ,
    Q,
    granted_col_r_reg,
    granted_col_r_reg_0,
    override_demand_ns,
    \grant_r_reg[1]_0 ,
    E,
    \col_mux.col_rd_wr_r_reg ,
    D,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[0]_1 ,
    granted_col_r_reg_1,
    \wtr_timer.wtr_cnt_r_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    read_this_rank,
    int_read_this_rank,
    granted_col_r_reg_2,
    mc_odt_ns,
    mc_aux_out_r0,
    DIC,
    col_data_buf_addr,
    \cmd_pipe_plus.mc_bank_reg[5] ,
    \cmd_pipe_plus.mc_address_reg[24] ,
    granted_col_r_reg_3,
    p_14_out,
    demand_priority_r_reg,
    \grant_r_reg[2]_0 ,
    \order_q_r_reg[0] ,
    ofs_rdy_r,
    rnk_config_valid_r,
    p_92_out,
    rd_wr_r_lcl_reg,
    idle_r_lcl_reg,
    p_131_out,
    col_rd_wr_r,
    ofs_rdy_r_1,
    rnk_config_strobe,
    rnk_config_strobe_0,
    ofs_rdy_r_2,
    \grant_r_reg[3]_0 ,
    ofs_rdy_r_3,
    rstdiv0_sync_r1_reg_rep__20,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    rstdiv0_sync_r1_reg_rep__24,
    rd_this_rank_r,
    read_this_rank_r,
    rd_wr_r_lcl_reg_0,
    rd_wr_r_lcl_reg_1,
    col_wait_r_reg,
    rd_wr_r_lcl_reg_2,
    rstdiv0_sync_r1_reg_rep__19,
    mc_aux_out_r,
    p_53_out,
    p_71_out,
    p_32_out,
    p_110_out,
    col_periodic_rd_r,
    p_149_out,
    \req_data_buf_addr_r_reg[4] ,
    \req_data_buf_addr_r_reg[4]_0 ,
    wr_this_rank_r,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \req_col_r_reg[9] ,
    \req_col_r_reg[9]_0 ,
    \req_col_r_reg[9]_1 ,
    \req_col_r_reg[9]_2 ,
    auto_pre_r,
    auto_pre_r_6,
    auto_pre_r_7,
    auto_pre_r_8,
    \req_data_buf_addr_r_reg[4]_1 ,
    \req_data_buf_addr_r_reg[4]_2 ,
    col_wr_data_buf_addr_r,
    CLK);
  output \cmd_pipe_plus.mc_ras_n_reg[1] ;
  output [3:0]Q;
  output granted_col_r_reg;
  output granted_col_r_reg_0;
  output override_demand_ns;
  output \grant_r_reg[1]_0 ;
  output [0:0]E;
  output \col_mux.col_rd_wr_r_reg ;
  output [0:0]D;
  output \grant_r_reg[0]_0 ;
  output \grant_r_reg[0]_1 ;
  output granted_col_r_reg_1;
  output \wtr_timer.wtr_cnt_r_reg[0] ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  output read_this_rank;
  output int_read_this_rank;
  output granted_col_r_reg_2;
  output [0:0]mc_odt_ns;
  output mc_aux_out_r0;
  output [0:0]DIC;
  output [4:0]col_data_buf_addr;
  output [2:0]\cmd_pipe_plus.mc_bank_reg[5] ;
  output [10:0]\cmd_pipe_plus.mc_address_reg[24] ;
  input granted_col_r_reg_3;
  input p_14_out;
  input demand_priority_r_reg;
  input \grant_r_reg[2]_0 ;
  input \order_q_r_reg[0] ;
  input ofs_rdy_r;
  input rnk_config_valid_r;
  input p_92_out;
  input rd_wr_r_lcl_reg;
  input idle_r_lcl_reg;
  input p_131_out;
  input col_rd_wr_r;
  input ofs_rdy_r_1;
  input rnk_config_strobe;
  input [1:0]rnk_config_strobe_0;
  input ofs_rdy_r_2;
  input \grant_r_reg[3]_0 ;
  input ofs_rdy_r_3;
  input rstdiv0_sync_r1_reg_rep__20;
  input [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;
  input rstdiv0_sync_r1_reg_rep__24;
  input [3:0]rd_this_rank_r;
  input read_this_rank_r;
  input rd_wr_r_lcl_reg_0;
  input rd_wr_r_lcl_reg_1;
  input col_wait_r_reg;
  input rd_wr_r_lcl_reg_2;
  input rstdiv0_sync_r1_reg_rep__19;
  input mc_aux_out_r;
  input p_53_out;
  input p_71_out;
  input p_32_out;
  input p_110_out;
  input col_periodic_rd_r;
  input p_149_out;
  input [4:0]\req_data_buf_addr_r_reg[4] ;
  input [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  input [3:0]wr_this_rank_r;
  input [2:0]\req_bank_r_lcl_reg[2] ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [2:0]\req_bank_r_lcl_reg[2]_2 ;
  input [9:0]\req_col_r_reg[9] ;
  input [9:0]\req_col_r_reg[9]_0 ;
  input [9:0]\req_col_r_reg[9]_1 ;
  input [9:0]\req_col_r_reg[9]_2 ;
  input auto_pre_r;
  input auto_pre_r_6;
  input auto_pre_r_7;
  input auto_pre_r_8;
  input [4:0]\req_data_buf_addr_r_reg[4]_1 ;
  input [4:0]\req_data_buf_addr_r_reg[4]_2 ;
  input [4:0]col_wr_data_buf_addr_r;
  input CLK;

  wire CLK;
  wire [0:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [3:0]Q;
  wire auto_pre_r;
  wire auto_pre_r_6;
  wire auto_pre_r_7;
  wire auto_pre_r_8;
  wire \cmd_pipe_plus.mc_address[14]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[15]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[16]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[17]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[18]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[19]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[20]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[21]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[22]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[23]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[24]_i_2_n_0 ;
  wire [10:0]\cmd_pipe_plus.mc_address_reg[24] ;
  wire \cmd_pipe_plus.mc_bank[3]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[4]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[5]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_ras_n_reg[1] ;
  wire [4:0]col_data_buf_addr;
  wire \col_mux.col_periodic_rd_r_i_2_n_0 ;
  wire \col_mux.col_rd_wr_r_i_2_n_0 ;
  wire \col_mux.col_rd_wr_r_reg ;
  wire col_periodic_rd_r;
  wire col_rd_wr_r;
  wire col_wait_r_reg;
  wire [4:0]col_wr_data_buf_addr_r;
  wire demand_priority_r_reg;
  wire \grant_r[0]_i_1__0_n_0 ;
  wire \grant_r[0]_i_3__0_n_0 ;
  wire \grant_r[1]_i_1__0_n_0 ;
  wire \grant_r[1]_i_3_n_0 ;
  wire \grant_r[1]_i_5__0_n_0 ;
  wire \grant_r[1]_i_7_n_0 ;
  wire \grant_r[2]_i_1__0_n_0 ;
  wire \grant_r[3]_i_10__0_n_0 ;
  wire \grant_r[3]_i_1_n_0 ;
  wire \grant_r[3]_i_3__1_n_0 ;
  wire \grant_r[3]_i_4_n_0 ;
  wire \grant_r[3]_i_5__2_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[3]_0 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire granted_col_r_reg_3;
  wire idle_r_lcl_reg;
  wire int_read_this_rank;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1_n_0 ;
  wire \last_master_r[1]_i_1_n_0 ;
  wire \last_master_r[2]_i_1_n_0 ;
  wire \last_master_r[3]_i_1__0_n_0 ;
  wire mc_aux_out_r;
  wire mc_aux_out_r0;
  wire [0:0]mc_odt_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_1;
  wire ofs_rdy_r_2;
  wire ofs_rdy_r_3;
  wire \order_q_r_reg[0] ;
  wire override_demand_ns;
  wire p_110_out;
  wire p_131_out;
  wire p_149_out;
  wire p_14_out;
  wire p_32_out;
  wire p_53_out;
  wire p_71_out;
  wire p_92_out;
  wire \periodic_rd_generation.read_this_rank_r_i_2_n_0 ;
  wire [3:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire \read_fifo.fifo_ram[0].RAM32M0_i_11_n_0 ;
  wire \read_fifo.fifo_ram[0].RAM32M0_i_12_n_0 ;
  wire \read_fifo.fifo_ram[0].RAM32M0_i_13_n_0 ;
  wire \read_fifo.fifo_ram[0].RAM32M0_i_14_n_0 ;
  wire \read_fifo.fifo_ram[0].RAM32M0_i_15_n_0 ;
  wire read_this_rank;
  wire read_this_rank_r;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [9:0]\req_col_r_reg[9]_2 ;
  wire [4:0]\req_data_buf_addr_r_reg[4] ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_1 ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_2 ;
  wire rnk_config_strobe;
  wire [1:0]rnk_config_strobe_0;
  wire rnk_config_valid_r;
  wire rstdiv0_sync_r1_reg_rep__19;
  wire rstdiv0_sync_r1_reg_rep__20;
  wire rstdiv0_sync_r1_reg_rep__24;
  wire [3:0]wr_this_rank_r;
  wire \wtr_timer.wtr_cnt_r[1]_i_3_n_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[0] ;
  wire [0:0]\wtr_timer.wtr_cnt_r_reg[1] ;

  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[14]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[14]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [0]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [0]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[14]_i_2 
       (.I0(\req_col_r_reg[9]_0 [0]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [0]),
        .O(\cmd_pipe_plus.mc_address[14]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[15]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[15]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [1]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [1]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[15]_i_2 
       (.I0(\req_col_r_reg[9]_0 [1]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [1]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [1]),
        .O(\cmd_pipe_plus.mc_address[15]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair750" *) 
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[16]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[16]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [2]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [2]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[16]_i_2 
       (.I0(\req_col_r_reg[9]_0 [2]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [2]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [2]),
        .O(\cmd_pipe_plus.mc_address[16]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[17]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[17]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [3]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [3]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[17]_i_2 
       (.I0(\req_col_r_reg[9]_0 [3]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [3]),
        .O(\cmd_pipe_plus.mc_address[17]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[18]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[18]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [4]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [4]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[18]_i_2 
       (.I0(\req_col_r_reg[9]_0 [4]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [4]),
        .O(\cmd_pipe_plus.mc_address[18]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[19]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[19]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [5]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [5]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[19]_i_2 
       (.I0(\req_col_r_reg[9]_0 [5]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [5]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [5]),
        .O(\cmd_pipe_plus.mc_address[19]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[20]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[20]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [6]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [6]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[20]_i_2 
       (.I0(\req_col_r_reg[9]_0 [6]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [6]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [6]),
        .O(\cmd_pipe_plus.mc_address[20]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[21]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[21]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [7]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [7]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[21]_i_2 
       (.I0(\req_col_r_reg[9]_0 [7]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [7]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [7]),
        .O(\cmd_pipe_plus.mc_address[21]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[22]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[22]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [8]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [8]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[22]_i_2 
       (.I0(\req_col_r_reg[9]_0 [8]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [8]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [8]),
        .O(\cmd_pipe_plus.mc_address[22]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[23]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[23]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_col_r_reg[9] [9]),
        .O(\cmd_pipe_plus.mc_address_reg[24] [9]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[23]_i_2 
       (.I0(\req_col_r_reg[9]_0 [9]),
        .I1(Q[0]),
        .I2(\req_col_r_reg[9]_1 [9]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_col_r_reg[9]_2 [9]),
        .O(\cmd_pipe_plus.mc_address[23]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[24]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[24]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(auto_pre_r),
        .O(\cmd_pipe_plus.mc_address_reg[24] [10]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[24]_i_2 
       (.I0(auto_pre_r_6),
        .I1(Q[0]),
        .I2(auto_pre_r_7),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(auto_pre_r_8),
        .O(\cmd_pipe_plus.mc_address[24]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_bank_r_lcl_reg[2] [0]),
        .O(\cmd_pipe_plus.mc_bank_reg[5] [0]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[3]_i_2 
       (.I0(\req_bank_r_lcl_reg[2]_0 [0]),
        .I1(Q[0]),
        .I2(\req_bank_r_lcl_reg[2]_1 [0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_bank_r_lcl_reg[2]_2 [0]),
        .O(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[4]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_bank_r_lcl_reg[2] [1]),
        .O(\cmd_pipe_plus.mc_bank_reg[5] [1]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[4]_i_2 
       (.I0(\req_bank_r_lcl_reg[2]_0 [1]),
        .I1(Q[0]),
        .I2(\req_bank_r_lcl_reg[2]_1 [1]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_bank_r_lcl_reg[2]_2 [1]),
        .O(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair752" *) 
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ),
        .I1(granted_col_r_reg_3),
        .I2(Q[3]),
        .I3(\req_bank_r_lcl_reg[2] [2]),
        .O(\cmd_pipe_plus.mc_bank_reg[5] [2]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[5]_i_2 
       (.I0(\req_bank_r_lcl_reg[2]_0 [2]),
        .I1(Q[0]),
        .I2(\req_bank_r_lcl_reg[2]_1 [2]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\req_bank_r_lcl_reg[2]_2 [2]),
        .O(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair750" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \cmd_pipe_plus.mc_cmd[1]_i_1 
       (.I0(\col_mux.col_rd_wr_r_reg ),
        .I1(granted_col_r_reg_3),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair751" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \cmd_pipe_plus.mc_data_offset[5]_i_1 
       (.I0(\col_mux.col_rd_wr_r_reg ),
        .I1(granted_col_r_reg_3),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[0] ));
  LUT3 #(
    .INIT(8'hBA)) 
    \cmd_pipe_plus.mc_odt[0]_i_1 
       (.I0(mc_aux_out_r),
        .I1(\col_mux.col_rd_wr_r_reg ),
        .I2(granted_col_r_reg_3),
        .O(mc_odt_ns));
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    \cmd_pipe_plus.mc_ras_n[1]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[2]),
        .I4(granted_col_r_reg_3),
        .O(\cmd_pipe_plus.mc_ras_n_reg[1] ));
  LUT6 #(
    .INIT(64'hFFFE0000FFFFFFFF)) 
    \cmd_pipe_plus.mc_we_n[1]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[2]),
        .I4(\col_mux.col_rd_wr_r_reg ),
        .I5(granted_col_r_reg_3),
        .O(D));
  LUT5 #(
    .INIT(32'hFFCA00CA)) 
    \col_mux.col_periodic_rd_r_i_1 
       (.I0(\col_mux.col_periodic_rd_r_i_2_n_0 ),
        .I1(p_71_out),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(p_32_out),
        .O(DIC));
  LUT6 #(
    .INIT(64'hAAAAFF00AAAA3030)) 
    \col_mux.col_periodic_rd_r_i_2 
       (.I0(p_110_out),
        .I1(rstdiv0_sync_r1_reg_rep__19),
        .I2(col_periodic_rd_r),
        .I3(p_149_out),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(\col_mux.col_periodic_rd_r_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFECE3202)) 
    \col_mux.col_rd_wr_r_i_1 
       (.I0(\col_mux.col_rd_wr_r_i_2_n_0 ),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(p_53_out),
        .I4(p_14_out),
        .O(\col_mux.col_rd_wr_r_reg ));
  LUT5 #(
    .INIT(32'hAACFAAC0)) 
    \col_mux.col_rd_wr_r_i_2 
       (.I0(p_92_out),
        .I1(p_131_out),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(col_rd_wr_r),
        .O(\col_mux.col_rd_wr_r_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5050100050001000)) 
    \grant_r[0]_i_1__0 
       (.I0(\grant_r[3]_i_4_n_0 ),
        .I1(\last_master_r[2]_i_1_n_0 ),
        .I2(rd_wr_r_lcl_reg_0),
        .I3(\grant_r[0]_i_3__0_n_0 ),
        .I4(\grant_r[3]_i_3__1_n_0 ),
        .I5(rd_wr_r_lcl_reg_1),
        .O(\grant_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F5F0F0F0F5F3F3)) 
    \grant_r[0]_i_3__0 
       (.I0(Q[0]),
        .I1(last_master_r[0]),
        .I2(rstdiv0_sync_r1_reg_rep__20),
        .I3(Q[1]),
        .I4(granted_col_r_reg_3),
        .I5(last_master_r[1]),
        .O(\grant_r[0]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    \grant_r[0]_i_7 
       (.I0(rnk_config_valid_r),
        .I1(Q[0]),
        .I2(ofs_rdy_r_1),
        .I3(rnk_config_strobe),
        .I4(rnk_config_strobe_0[1]),
        .I5(rnk_config_strobe_0[0]),
        .O(\grant_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h1100000011110101)) 
    \grant_r[1]_i_1__0 
       (.I0(\grant_r_reg[1]_0 ),
        .I1(\grant_r[1]_i_3_n_0 ),
        .I2(\last_master_r[2]_i_1_n_0 ),
        .I3(rd_wr_r_lcl_reg_1),
        .I4(\grant_r[3]_i_3__1_n_0 ),
        .I5(\last_master_r[1]_i_1_n_0 ),
        .O(\grant_r[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFE2)) 
    \grant_r[1]_i_2__2 
       (.I0(granted_col_r_reg),
        .I1(p_92_out),
        .I2(granted_col_r_reg_0),
        .I3(rd_wr_r_lcl_reg),
        .I4(\grant_r[1]_i_5__0_n_0 ),
        .I5(idle_r_lcl_reg),
        .O(\grant_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0000A808AAAAAAAA)) 
    \grant_r[1]_i_3 
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(last_master_r[1]),
        .I2(granted_col_r_reg_3),
        .I3(Q[1]),
        .I4(rstdiv0_sync_r1_reg_rep__19),
        .I5(\grant_r[1]_i_7_n_0 ),
        .O(\grant_r[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \grant_r[1]_i_5__0 
       (.I0(\grant_r_reg[3]_0 ),
        .I1(rnk_config_valid_r),
        .I2(Q[1]),
        .I3(ofs_rdy_r_3),
        .I4(override_demand_ns),
        .O(\grant_r[1]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000005000533)) 
    \grant_r[1]_i_7 
       (.I0(Q[2]),
        .I1(last_master_r[2]),
        .I2(Q[3]),
        .I3(granted_col_r_reg_3),
        .I4(last_master_r[3]),
        .I5(rstdiv0_sync_r1_reg_rep__20),
        .O(\grant_r[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000005070007)) 
    \grant_r[2]_i_1__0 
       (.I0(rd_wr_r_lcl_reg_2),
        .I1(\last_master_r[3]_i_1__0_n_0 ),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(\last_master_r[2]_i_1_n_0 ),
        .I4(\grant_r[3]_i_3__1_n_0 ),
        .I5(\grant_r[3]_i_4_n_0 ),
        .O(\grant_r[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0007000700000007)) 
    \grant_r[3]_i_1 
       (.I0(rd_wr_r_lcl_reg_2),
        .I1(\last_master_r[3]_i_1__0_n_0 ),
        .I2(\grant_r[3]_i_3__1_n_0 ),
        .I3(\grant_r[3]_i_4_n_0 ),
        .I4(\grant_r[3]_i_5__2_n_0 ),
        .I5(rd_wr_r_lcl_reg_1),
        .O(\grant_r[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \grant_r[3]_i_10__0 
       (.I0(\order_q_r_reg[0] ),
        .I1(ofs_rdy_r),
        .I2(Q[3]),
        .I3(rnk_config_valid_r),
        .I4(override_demand_ns),
        .O(\grant_r[3]_i_10__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \grant_r[3]_i_14 
       (.I0(rnk_config_strobe),
        .I1(rnk_config_strobe_0[1]),
        .I2(rnk_config_strobe_0[0]),
        .I3(ofs_rdy_r_2),
        .I4(Q[2]),
        .I5(rnk_config_valid_r),
        .O(\grant_r_reg[0]_1 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFE2)) 
    \grant_r[3]_i_3__1 
       (.I0(granted_col_r_reg),
        .I1(p_14_out),
        .I2(granted_col_r_reg_0),
        .I3(demand_priority_r_reg),
        .I4(\grant_r[3]_i_10__0_n_0 ),
        .I5(\grant_r_reg[2]_0 ),
        .O(\grant_r[3]_i_3__1_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \grant_r[3]_i_4 
       (.I0(rstdiv0_sync_r1_reg_rep__19),
        .I1(Q[0]),
        .I2(granted_col_r_reg_3),
        .I3(last_master_r[0]),
        .I4(\grant_r_reg[1]_0 ),
        .O(\grant_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAFEAE)) 
    \grant_r[3]_i_5__2 
       (.I0(\last_master_r[3]_i_1__0_n_0 ),
        .I1(last_master_r[0]),
        .I2(granted_col_r_reg_3),
        .I3(Q[0]),
        .I4(rstdiv0_sync_r1_reg_rep__20),
        .I5(\last_master_r[1]_i_1_n_0 ),
        .O(\grant_r[3]_i_5__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \grant_r[3]_i_7 
       (.I0(\col_mux.col_rd_wr_r_reg ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(rstdiv0_sync_r1_reg_rep__19),
        .O(granted_col_r_reg));
  LUT3 #(
    .INIT(8'h0D)) 
    \grant_r[3]_i_8__0 
       (.I0(\wtr_timer.wtr_cnt_r_reg[0] ),
        .I1(\wtr_timer.wtr_cnt_r_reg[1] ),
        .I2(rstdiv0_sync_r1_reg_rep__24),
        .O(granted_col_r_reg_0));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__0_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8A8A8)) 
    granted_col_r_i_2
       (.I0(rd_wr_r_lcl_reg_1),
        .I1(\grant_r_reg[2]_0 ),
        .I2(col_wait_r_reg),
        .I3(granted_col_r_reg_0),
        .I4(p_14_out),
        .I5(granted_col_r_reg),
        .O(granted_col_r_reg_2));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    granted_col_r_i_5
       (.I0(rnk_config_strobe),
        .I1(rnk_config_strobe_0[1]),
        .I2(rnk_config_strobe_0[0]),
        .I3(rnk_config_valid_r),
        .I4(Q[3]),
        .I5(ofs_rdy_r),
        .O(granted_col_r_reg_1));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1 
       (.I0(last_master_r[0]),
        .I1(granted_col_r_reg_3),
        .I2(Q[0]),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .O(\last_master_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1 
       (.I0(last_master_r[1]),
        .I1(granted_col_r_reg_3),
        .I2(Q[1]),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .O(\last_master_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1 
       (.I0(last_master_r[2]),
        .I1(granted_col_r_reg_3),
        .I2(Q[2]),
        .I3(rstdiv0_sync_r1_reg_rep__20),
        .O(\last_master_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair751" *) 
  LUT4 #(
    .INIT(16'hFEAE)) 
    \last_master_r[3]_i_1__0 
       (.I0(rstdiv0_sync_r1_reg_rep__20),
        .I1(last_master_r[3]),
        .I2(granted_col_r_reg_3),
        .I3(Q[3]),
        .O(\last_master_r[3]_i_1__0_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__0_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair752" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \mc_aux_out_r[0]_i_1 
       (.I0(granted_col_r_reg_3),
        .I1(\col_mux.col_rd_wr_r_reg ),
        .O(mc_aux_out_r0));
  LUT3 #(
    .INIT(8'hFE)) 
    override_demand_r_i_1
       (.I0(rnk_config_strobe_0[0]),
        .I1(rnk_config_strobe_0[1]),
        .I2(rnk_config_strobe),
        .O(override_demand_ns));
  LUT6 #(
    .INIT(64'hAAAAA888A888A888)) 
    \periodic_rd_generation.periodic_rd_timer_r[2]_i_3 
       (.I0(read_this_rank_r),
        .I1(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),
        .I2(rd_this_rank_r[1]),
        .I3(Q[1]),
        .I4(rd_this_rank_r[2]),
        .I5(Q[2]),
        .O(int_read_this_rank));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \periodic_rd_generation.read_this_rank_r_i_1 
       (.I0(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),
        .I1(rd_this_rank_r[1]),
        .I2(Q[1]),
        .I3(rd_this_rank_r[2]),
        .I4(Q[2]),
        .O(read_this_rank));
  LUT4 #(
    .INIT(16'hF888)) 
    \periodic_rd_generation.read_this_rank_r_i_2 
       (.I0(rd_this_rank_r[0]),
        .I1(Q[0]),
        .I2(rd_this_rank_r[3]),
        .I3(Q[3]),
        .O(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFCA00CA)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_1 
       (.I0(\read_fifo.fifo_ram[0].RAM32M0_i_11_n_0 ),
        .I1(\req_data_buf_addr_r_reg[4] [4]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_data_buf_addr_r_reg[4]_0 [4]),
        .O(col_data_buf_addr[4]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_11 
       (.I0(\req_data_buf_addr_r_reg[4]_1 [4]),
        .I1(Q[1]),
        .I2(\req_data_buf_addr_r_reg[4]_2 [4]),
        .I3(Q[0]),
        .I4(col_wr_data_buf_addr_r[4]),
        .O(\read_fifo.fifo_ram[0].RAM32M0_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_12 
       (.I0(\req_data_buf_addr_r_reg[4]_1 [3]),
        .I1(Q[1]),
        .I2(\req_data_buf_addr_r_reg[4]_2 [3]),
        .I3(Q[0]),
        .I4(col_wr_data_buf_addr_r[3]),
        .O(\read_fifo.fifo_ram[0].RAM32M0_i_12_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_13 
       (.I0(\req_data_buf_addr_r_reg[4]_1 [2]),
        .I1(Q[1]),
        .I2(\req_data_buf_addr_r_reg[4]_2 [2]),
        .I3(Q[0]),
        .I4(col_wr_data_buf_addr_r[2]),
        .O(\read_fifo.fifo_ram[0].RAM32M0_i_13_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_14 
       (.I0(\req_data_buf_addr_r_reg[4]_1 [1]),
        .I1(Q[1]),
        .I2(\req_data_buf_addr_r_reg[4]_2 [1]),
        .I3(Q[0]),
        .I4(col_wr_data_buf_addr_r[1]),
        .O(\read_fifo.fifo_ram[0].RAM32M0_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_15 
       (.I0(\req_data_buf_addr_r_reg[4]_1 [0]),
        .I1(Q[1]),
        .I2(\req_data_buf_addr_r_reg[4]_2 [0]),
        .I3(Q[0]),
        .I4(col_wr_data_buf_addr_r[0]),
        .O(\read_fifo.fifo_ram[0].RAM32M0_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hFFCA00CA)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_2 
       (.I0(\read_fifo.fifo_ram[0].RAM32M0_i_12_n_0 ),
        .I1(\req_data_buf_addr_r_reg[4] [3]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_data_buf_addr_r_reg[4]_0 [3]),
        .O(col_data_buf_addr[3]));
  LUT5 #(
    .INIT(32'hFFCA00CA)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_3 
       (.I0(\read_fifo.fifo_ram[0].RAM32M0_i_13_n_0 ),
        .I1(\req_data_buf_addr_r_reg[4] [2]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_data_buf_addr_r_reg[4]_0 [2]),
        .O(col_data_buf_addr[2]));
  LUT5 #(
    .INIT(32'hFFCA00CA)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_4 
       (.I0(\read_fifo.fifo_ram[0].RAM32M0_i_14_n_0 ),
        .I1(\req_data_buf_addr_r_reg[4] [1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_data_buf_addr_r_reg[4]_0 [1]),
        .O(col_data_buf_addr[1]));
  LUT5 #(
    .INIT(32'hFFCA00CA)) 
    \read_fifo.fifo_ram[0].RAM32M0_i_5 
       (.I0(\read_fifo.fifo_ram[0].RAM32M0_i_15_n_0 ),
        .I1(\req_data_buf_addr_r_reg[4] [0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\req_data_buf_addr_r_reg[4]_0 [0]),
        .O(col_data_buf_addr[0]));
  LUT5 #(
    .INIT(32'h00000777)) 
    \wtr_timer.wtr_cnt_r[1]_i_2 
       (.I0(Q[2]),
        .I1(wr_this_rank_r[2]),
        .I2(Q[1]),
        .I3(wr_this_rank_r[1]),
        .I4(\wtr_timer.wtr_cnt_r[1]_i_3_n_0 ),
        .O(\wtr_timer.wtr_cnt_r_reg[0] ));
  LUT4 #(
    .INIT(16'hF888)) 
    \wtr_timer.wtr_cnt_r[1]_i_3 
       (.I0(wr_this_rank_r[3]),
        .I1(Q[3]),
        .I2(wr_this_rank_r[0]),
        .I3(Q[0]),
        .O(\wtr_timer.wtr_cnt_r[1]_i_3_n_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_tempmon" *) 
module mig_7series_0_mig_7series_v2_3_tempmon
   (D,
    clk_ref_i,
    rstdiv0_sync_r1,
    CLK);
  output [11:0]D;
  input clk_ref_i;
  input rstdiv0_sync_r1;
  input CLK;

  wire CLK;
  wire [11:0]D;
  wire clk_ref_i;
  wire \device_temp_101[11]_i_4_n_0 ;
  wire \device_temp_101[11]_i_5_n_0 ;
  wire \device_temp_101[11]_i_6_n_0 ;
  wire \device_temp_101[11]_i_7_n_0 ;
  wire \device_temp_101[11]_i_8_n_0 ;
  wire [11:0]device_temp_lcl;
  wire [11:0]device_temp_r;
  wire \device_temp_r[11]_i_1_n_0 ;
  wire [11:0]device_temp_sync_r1;
  wire [11:0]device_temp_sync_r2;
  wire [11:0]device_temp_sync_r3;
  wire [11:0]device_temp_sync_r4;
  wire device_temp_sync_r4_neq_r3;
  wire device_temp_sync_r4_neq_r3_i_2_n_0;
  wire device_temp_sync_r4_neq_r3_i_3_n_0;
  wire device_temp_sync_r4_neq_r3_i_4_n_0;
  wire device_temp_sync_r4_neq_r3_i_5_n_0;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_0;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_1;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_2;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_3;
  wire [11:0]device_temp_sync_r5;
  wire [10:0]p_0_in;
  wire [3:0]p_0_in__0;
  wire [11:0]p_1_in;
  wire rst_r1;
  wire rst_r2;
  wire rstdiv0_sync_r1;
  wire sample_en;
  wire sample_en0;
  wire sample_timer0;
  wire sample_timer_en;
  wire sync_cntr0;
  wire \sync_cntr[2]_i_1_n_0 ;
  wire \sync_cntr[3]_i_2_n_0 ;
  wire [3:0]sync_cntr_reg__0;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ;
  wire [15:0]xadc_do;
  wire xadc_drdy;
  wire xadc_drdy_r;
  wire \xadc_supplied_temperature.sample_en_i_2_n_0 ;
  wire \xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ;
  wire \xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ;
  wire \xadc_supplied_temperature.sample_timer_clr_reg_n_0 ;
  wire \xadc_supplied_temperature.sample_timer_en_i_1_n_0 ;
  wire [10:0]\xadc_supplied_temperature.sample_timer_reg__0 ;
  wire \xadc_supplied_temperature.temperature[11]_i_1_n_0 ;
  wire \xadc_supplied_temperature.tempmon_state[0]_i_1_n_0 ;
  wire \xadc_supplied_temperature.tempmon_state[1]_i_1_n_0 ;
  wire \xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ;
  wire \xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ;
  wire [3:0]NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED;
  wire \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ;
  wire [7:0]\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED ;
  wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED ;
  wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED ;

  LUT3 #(
    .INIT(8'h10)) 
    \device_temp_101[0]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[0]),
        .O(D[0]));
  LUT3 #(
    .INIT(8'hBA)) 
    \device_temp_101[10]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[10]),
        .O(D[10]));
  LUT3 #(
    .INIT(8'hFE)) 
    \device_temp_101[11]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[11]),
        .O(D[11]));
  LUT5 #(
    .INIT(32'h0000EF0F)) 
    \device_temp_101[11]_i_2 
       (.I0(device_temp_r[1]),
        .I1(device_temp_r[0]),
        .I2(\device_temp_101[11]_i_4_n_0 ),
        .I3(device_temp_r[2]),
        .I4(\device_temp_101[11]_i_5_n_0 ),
        .O(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ));
  LUT6 #(
    .INIT(64'h000000000002AAAA)) 
    \device_temp_101[11]_i_3 
       (.I0(\device_temp_101[11]_i_6_n_0 ),
        .I1(device_temp_r[8]),
        .I2(device_temp_r[9]),
        .I3(device_temp_r[10]),
        .I4(device_temp_r[11]),
        .I5(\device_temp_101[11]_i_7_n_0 ),
        .O(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \device_temp_101[11]_i_4 
       (.I0(device_temp_r[4]),
        .I1(device_temp_r[3]),
        .I2(device_temp_r[6]),
        .I3(device_temp_r[8]),
        .I4(device_temp_r[9]),
        .O(\device_temp_101[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h04CCFFFFFFFFFFFF)) 
    \device_temp_101[11]_i_5 
       (.I0(device_temp_r[6]),
        .I1(\device_temp_101[11]_i_8_n_0 ),
        .I2(device_temp_r[5]),
        .I3(device_temp_r[7]),
        .I4(device_temp_r[10]),
        .I5(device_temp_r[11]),
        .O(\device_temp_101[11]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \device_temp_101[11]_i_6 
       (.I0(device_temp_r[4]),
        .I1(device_temp_r[5]),
        .I2(device_temp_r[7]),
        .I3(device_temp_r[11]),
        .O(\device_temp_101[11]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hC080808080808080)) 
    \device_temp_101[11]_i_7 
       (.I0(device_temp_r[6]),
        .I1(device_temp_r[11]),
        .I2(device_temp_r[7]),
        .I3(device_temp_r[5]),
        .I4(device_temp_r[2]),
        .I5(device_temp_r[3]),
        .O(\device_temp_101[11]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \device_temp_101[11]_i_8 
       (.I0(device_temp_r[8]),
        .I1(device_temp_r[9]),
        .O(\device_temp_101[11]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \device_temp_101[1]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[1]),
        .O(D[1]));
  LUT3 #(
    .INIT(8'hFE)) 
    \device_temp_101[2]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[2]),
        .O(D[2]));
  LUT3 #(
    .INIT(8'hDC)) 
    \device_temp_101[3]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[3]),
        .O(D[3]));
  LUT3 #(
    .INIT(8'h10)) 
    \device_temp_101[4]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[4]),
        .O(D[4]));
  LUT3 #(
    .INIT(8'hFE)) 
    \device_temp_101[5]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[5]),
        .O(D[5]));
  LUT3 #(
    .INIT(8'h10)) 
    \device_temp_101[6]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[6]),
        .O(D[6]));
  LUT3 #(
    .INIT(8'hFE)) 
    \device_temp_101[7]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[7]),
        .O(D[7]));
  LUT3 #(
    .INIT(8'h10)) 
    \device_temp_101[8]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[8]),
        .O(D[8]));
  LUT3 #(
    .INIT(8'h10)) 
    \device_temp_101[9]_i_1 
       (.I0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),
        .I1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I2(device_temp_r[9]),
        .O(D[9]));
  LUT4 #(
    .INIT(16'h8000)) 
    \device_temp_r[11]_i_1 
       (.I0(sync_cntr_reg__0[1]),
        .I1(sync_cntr_reg__0[0]),
        .I2(sync_cntr_reg__0[2]),
        .I3(sync_cntr_reg__0[3]),
        .O(\device_temp_r[11]_i_1_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[0] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[0]),
        .Q(device_temp_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[10] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[10]),
        .Q(device_temp_r[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[11] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[11]),
        .Q(device_temp_r[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[1] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[1]),
        .Q(device_temp_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[2] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[2]),
        .Q(device_temp_r[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[3] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[3]),
        .Q(device_temp_r[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[4] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[4]),
        .Q(device_temp_r[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[5] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[5]),
        .Q(device_temp_r[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[6] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[6]),
        .Q(device_temp_r[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[7] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[7]),
        .Q(device_temp_r[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[8] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[8]),
        .Q(device_temp_r[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[9] 
       (.C(CLK),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[9]),
        .Q(device_temp_r[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[0]),
        .Q(device_temp_sync_r1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[10]),
        .Q(device_temp_sync_r1[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[11]),
        .Q(device_temp_sync_r1[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[1]),
        .Q(device_temp_sync_r1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[2]),
        .Q(device_temp_sync_r1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[3]),
        .Q(device_temp_sync_r1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[4]),
        .Q(device_temp_sync_r1[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[5]),
        .Q(device_temp_sync_r1[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[6]),
        .Q(device_temp_sync_r1[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[7]),
        .Q(device_temp_sync_r1[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[8]),
        .Q(device_temp_sync_r1[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_lcl[9]),
        .Q(device_temp_sync_r1[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[0]),
        .Q(device_temp_sync_r2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[10]),
        .Q(device_temp_sync_r2[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[11]),
        .Q(device_temp_sync_r2[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[1]),
        .Q(device_temp_sync_r2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[2]),
        .Q(device_temp_sync_r2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[3]),
        .Q(device_temp_sync_r2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[4]),
        .Q(device_temp_sync_r2[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[5]),
        .Q(device_temp_sync_r2[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[6]),
        .Q(device_temp_sync_r2[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[7]),
        .Q(device_temp_sync_r2[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[8]),
        .Q(device_temp_sync_r2[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r1[9]),
        .Q(device_temp_sync_r2[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[0]),
        .Q(device_temp_sync_r3[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[10]),
        .Q(device_temp_sync_r3[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[11]),
        .Q(device_temp_sync_r3[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[1]),
        .Q(device_temp_sync_r3[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[2]),
        .Q(device_temp_sync_r3[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[3]),
        .Q(device_temp_sync_r3[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[4]),
        .Q(device_temp_sync_r3[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[5]),
        .Q(device_temp_sync_r3[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[6]),
        .Q(device_temp_sync_r3[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[7]),
        .Q(device_temp_sync_r3[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[8]),
        .Q(device_temp_sync_r3[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r3_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r2[9]),
        .Q(device_temp_sync_r3[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_2
       (.I0(device_temp_sync_r4[9]),
        .I1(device_temp_sync_r3[9]),
        .I2(device_temp_sync_r3[11]),
        .I3(device_temp_sync_r4[11]),
        .I4(device_temp_sync_r3[10]),
        .I5(device_temp_sync_r4[10]),
        .O(device_temp_sync_r4_neq_r3_i_2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_3
       (.I0(device_temp_sync_r4[6]),
        .I1(device_temp_sync_r3[6]),
        .I2(device_temp_sync_r3[8]),
        .I3(device_temp_sync_r4[8]),
        .I4(device_temp_sync_r3[7]),
        .I5(device_temp_sync_r4[7]),
        .O(device_temp_sync_r4_neq_r3_i_3_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_4
       (.I0(device_temp_sync_r4[3]),
        .I1(device_temp_sync_r3[3]),
        .I2(device_temp_sync_r3[5]),
        .I3(device_temp_sync_r4[5]),
        .I4(device_temp_sync_r3[4]),
        .I5(device_temp_sync_r4[4]),
        .O(device_temp_sync_r4_neq_r3_i_4_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_5
       (.I0(device_temp_sync_r4[0]),
        .I1(device_temp_sync_r3[0]),
        .I2(device_temp_sync_r3[2]),
        .I3(device_temp_sync_r4[2]),
        .I4(device_temp_sync_r3[1]),
        .I5(device_temp_sync_r4[1]),
        .O(device_temp_sync_r4_neq_r3_i_5_n_0));
  FDRE device_temp_sync_r4_neq_r3_reg
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4_neq_r3_reg_i_1_n_0),
        .Q(device_temp_sync_r4_neq_r3),
        .R(1'b0));
  CARRY4 device_temp_sync_r4_neq_r3_reg_i_1
       (.CI(1'b0),
        .CO({device_temp_sync_r4_neq_r3_reg_i_1_n_0,device_temp_sync_r4_neq_r3_reg_i_1_n_1,device_temp_sync_r4_neq_r3_reg_i_1_n_2,device_temp_sync_r4_neq_r3_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O(NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED[3:0]),
        .S({device_temp_sync_r4_neq_r3_i_2_n_0,device_temp_sync_r4_neq_r3_i_3_n_0,device_temp_sync_r4_neq_r3_i_4_n_0,device_temp_sync_r4_neq_r3_i_5_n_0}));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[0]),
        .Q(device_temp_sync_r4[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[10]),
        .Q(device_temp_sync_r4[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[11]),
        .Q(device_temp_sync_r4[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[1]),
        .Q(device_temp_sync_r4[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[2]),
        .Q(device_temp_sync_r4[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[3]),
        .Q(device_temp_sync_r4[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[4]),
        .Q(device_temp_sync_r4[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[5]),
        .Q(device_temp_sync_r4[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[6]),
        .Q(device_temp_sync_r4[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[7]),
        .Q(device_temp_sync_r4[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[8]),
        .Q(device_temp_sync_r4[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r3[9]),
        .Q(device_temp_sync_r4[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[0]),
        .Q(device_temp_sync_r5[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[10]),
        .Q(device_temp_sync_r5[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[11]),
        .Q(device_temp_sync_r5[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[1]),
        .Q(device_temp_sync_r5[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[2]),
        .Q(device_temp_sync_r5[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[3]),
        .Q(device_temp_sync_r5[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[4]),
        .Q(device_temp_sync_r5[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[5]),
        .Q(device_temp_sync_r5[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[6]),
        .Q(device_temp_sync_r5[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[7]),
        .Q(device_temp_sync_r5[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[8]),
        .Q(device_temp_sync_r5[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(device_temp_sync_r4[9]),
        .Q(device_temp_sync_r5[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \sync_cntr[0]_i_1 
       (.I0(sync_cntr_reg__0[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \sync_cntr[1]_i_1 
       (.I0(sync_cntr_reg__0[0]),
        .I1(sync_cntr_reg__0[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \sync_cntr[2]_i_1 
       (.I0(sync_cntr_reg__0[1]),
        .I1(sync_cntr_reg__0[0]),
        .I2(sync_cntr_reg__0[2]),
        .O(\sync_cntr[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \sync_cntr[3]_i_1 
       (.I0(rstdiv0_sync_r1),
        .I1(device_temp_sync_r4_neq_r3),
        .O(sync_cntr0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \sync_cntr[3]_i_2 
       (.I0(sync_cntr_reg__0[3]),
        .I1(sync_cntr_reg__0[2]),
        .I2(sync_cntr_reg__0[0]),
        .I3(sync_cntr_reg__0[1]),
        .O(\sync_cntr[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \sync_cntr[3]_i_3 
       (.I0(sync_cntr_reg__0[0]),
        .I1(sync_cntr_reg__0[1]),
        .I2(sync_cntr_reg__0[2]),
        .I3(sync_cntr_reg__0[3]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[0] 
       (.C(CLK),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__0[0]),
        .Q(sync_cntr_reg__0[0]),
        .R(sync_cntr0));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[1] 
       (.C(CLK),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__0[1]),
        .Q(sync_cntr_reg__0[1]),
        .R(sync_cntr0));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[2] 
       (.C(CLK),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(\sync_cntr[2]_i_1_n_0 ),
        .Q(sync_cntr_reg__0[2]),
        .R(sync_cntr0));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[3] 
       (.C(CLK),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__0[3]),
        .Q(sync_cntr_reg__0[3]),
        .R(sync_cntr0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  XADC #(
    .INIT_40(16'h1000),
    .INIT_41(16'h2FFF),
    .INIT_42(16'h0800),
    .INIT_43(16'h0000),
    .INIT_44(16'h0000),
    .INIT_45(16'h0000),
    .INIT_46(16'h0000),
    .INIT_47(16'h0000),
    .INIT_48(16'h0101),
    .INIT_49(16'h0000),
    .INIT_4A(16'h0100),
    .INIT_4B(16'h0000),
    .INIT_4C(16'h0000),
    .INIT_4D(16'h0000),
    .INIT_4E(16'h0000),
    .INIT_4F(16'h0000),
    .INIT_50(16'hB5ED),
    .INIT_51(16'h57E4),
    .INIT_52(16'hA147),
    .INIT_53(16'hCA33),
    .INIT_54(16'hA93A),
    .INIT_55(16'h52C6),
    .INIT_56(16'h9555),
    .INIT_57(16'hAE4E),
    .INIT_58(16'h5999),
    .INIT_59(16'h0000),
    .INIT_5A(16'h0000),
    .INIT_5B(16'h0000),
    .INIT_5C(16'h5111),
    .INIT_5D(16'h0000),
    .INIT_5E(16'h0000),
    .INIT_5F(16'h0000),
    .IS_CONVSTCLK_INVERTED(1'b0),
    .IS_DCLK_INVERTED(1'b0),
    .SIM_DEVICE("7SERIES"),
    .SIM_MONITOR_FILE("design.txt")) 
    \xadc_supplied_temperature.XADC_inst 
       (.ALM(\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED [7:0]),
        .BUSY(\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ),
        .CHANNEL(\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED [4:0]),
        .CONVST(1'b0),
        .CONVSTCLK(1'b0),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(clk_ref_i),
        .DEN(\xadc_supplied_temperature.sample_timer_clr_reg_n_0 ),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(xadc_do),
        .DRDY(xadc_drdy),
        .DWE(1'b0),
        .EOC(\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ),
        .EOS(\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ),
        .JTAGBUSY(\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ),
        .JTAGLOCKED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ),
        .JTAGMODIFIED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ),
        .MUXADDR(\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED [4:0]),
        .OT(\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ),
        .RESET(1'b0),
        .VAUXN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .VAUXP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .VN(1'b0),
        .VP(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \xadc_supplied_temperature.rst_r1_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(rstdiv0_sync_r1),
        .Q(rst_r1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \xadc_supplied_temperature.rst_r2_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(rst_r1),
        .Q(rst_r2),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0100000000000000)) 
    \xadc_supplied_temperature.sample_en_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [2]),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [4]),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [3]),
        .I4(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .I5(\xadc_supplied_temperature.sample_en_i_2_n_0 ),
        .O(sample_en0));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \xadc_supplied_temperature.sample_en_i_2 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [5]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [6]),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [9]),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [10]),
        .I4(\xadc_supplied_temperature.sample_timer_reg__0 [7]),
        .I5(\xadc_supplied_temperature.sample_timer_reg__0 [8]),
        .O(\xadc_supplied_temperature.sample_en_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_en_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(sample_en0),
        .Q(sample_en),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \xadc_supplied_temperature.sample_timer[0]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .O(p_0_in[0]));
  LUT2 #(
    .INIT(4'hE)) 
    \xadc_supplied_temperature.sample_timer[10]_i_1 
       (.I0(rst_r2),
        .I1(\xadc_supplied_temperature.sample_timer_clr_reg_n_0 ),
        .O(sample_timer0));
  LUT6 #(
    .INIT(64'hF7FFFFFF08000000)) 
    \xadc_supplied_temperature.sample_timer[10]_i_2 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [9]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [7]),
        .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [6]),
        .I4(\xadc_supplied_temperature.sample_timer_reg__0 [8]),
        .I5(\xadc_supplied_temperature.sample_timer_reg__0 [10]),
        .O(p_0_in[10]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \xadc_supplied_temperature.sample_timer[10]_i_3 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [4]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [2]),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .I4(\xadc_supplied_temperature.sample_timer_reg__0 [3]),
        .I5(\xadc_supplied_temperature.sample_timer_reg__0 [5]),
        .O(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \xadc_supplied_temperature.sample_timer[1]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \xadc_supplied_temperature.sample_timer[2]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \xadc_supplied_temperature.sample_timer[3]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [2]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \xadc_supplied_temperature.sample_timer[4]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [3]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [2]),
        .I4(\xadc_supplied_temperature.sample_timer_reg__0 [4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \xadc_supplied_temperature.sample_timer[5]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [4]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [2]),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .I4(\xadc_supplied_temperature.sample_timer_reg__0 [3]),
        .I5(\xadc_supplied_temperature.sample_timer_reg__0 [5]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \xadc_supplied_temperature.sample_timer[6]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [6]),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \xadc_supplied_temperature.sample_timer[7]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [6]),
        .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [7]),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \xadc_supplied_temperature.sample_timer[8]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [7]),
        .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg__0 [6]),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [8]),
        .O(p_0_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \xadc_supplied_temperature.sample_timer[9]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg__0 [8]),
        .I1(\xadc_supplied_temperature.sample_timer_reg__0 [6]),
        .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I3(\xadc_supplied_temperature.sample_timer_reg__0 [7]),
        .I4(\xadc_supplied_temperature.sample_timer_reg__0 [9]),
        .O(p_0_in[9]));
  LUT4 #(
    .INIT(16'h2302)) 
    \xadc_supplied_temperature.sample_timer_clr_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_clr_reg_n_0 ),
        .I1(rst_r2),
        .I2(\xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),
        .I3(\xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .O(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_clr_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.sample_timer_clr_reg_n_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h3203)) 
    \xadc_supplied_temperature.sample_timer_en_i_1 
       (.I0(sample_timer_en),
        .I1(rst_r2),
        .I2(\xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .I3(\xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),
        .O(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_en_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ),
        .Q(sample_timer_en),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[0] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[0]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [0]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[10] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[10]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [10]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[1] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[1]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [1]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[2] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[2]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [2]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[3] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[3]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [3]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[4] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[4]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [4]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[5] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[5]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [5]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[6] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[6]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [6]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[7] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[7]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [7]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[8] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[8]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [8]),
        .R(sample_timer0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[9] 
       (.C(clk_ref_i),
        .CE(sample_timer_en),
        .D(p_0_in[9]),
        .Q(\xadc_supplied_temperature.sample_timer_reg__0 [9]),
        .R(sample_timer0));
  LUT2 #(
    .INIT(4'h8)) 
    \xadc_supplied_temperature.temperature[11]_i_1 
       (.I0(\xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .I1(\xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),
        .O(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[0] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(device_temp_lcl[0]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[10] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(device_temp_lcl[10]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[11] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(device_temp_lcl[11]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[1] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(device_temp_lcl[1]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[2] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(device_temp_lcl[2]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[3] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(device_temp_lcl[3]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[4] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(device_temp_lcl[4]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[5] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(device_temp_lcl[5]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[6] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(device_temp_lcl[6]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[7] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(device_temp_lcl[7]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[8] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(device_temp_lcl[8]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[9] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature[11]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(device_temp_lcl[9]),
        .R(rst_r2));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'h00B8)) 
    \xadc_supplied_temperature.tempmon_state[0]_i_1 
       (.I0(xadc_drdy_r),
        .I1(\xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),
        .I2(sample_en),
        .I3(\xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .O(\xadc_supplied_temperature.tempmon_state[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \xadc_supplied_temperature.tempmon_state[1]_i_1 
       (.I0(\xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .I1(\xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),
        .O(\xadc_supplied_temperature.tempmon_state[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.tempmon_state_reg[0] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.tempmon_state[0]_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.tempmon_state_reg[1] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.tempmon_state[1]_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[10] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[10]),
        .Q(p_1_in[6]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[11] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[11]),
        .Q(p_1_in[7]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[12] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[12]),
        .Q(p_1_in[8]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[13] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[13]),
        .Q(p_1_in[9]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[14] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[14]),
        .Q(p_1_in[10]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[15] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[15]),
        .Q(p_1_in[11]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[4] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[4]),
        .Q(p_1_in[0]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[5] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[5]),
        .Q(p_1_in[1]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[6] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[6]),
        .Q(p_1_in[2]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[7] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[7]),
        .Q(p_1_in[3]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[8] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[8]),
        .Q(p_1_in[4]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[9] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_do[9]),
        .Q(p_1_in[5]),
        .R(rst_r2));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_drdy_r_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(xadc_drdy),
        .Q(xadc_drdy_r),
        .R(rst_r2));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ui_cmd" *) 
module mig_7series_0_mig_7series_v2_3_ui_cmd
   (E,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    req_wr_r_lcl_reg,
    app_cmd_r2,
    \req_data_buf_addr_r_reg[4] ,
    rd_accepted,
    p_106_out,
    p_145_out,
    p_28_out,
    p_67_out,
    req_wr_r_lcl_reg_0,
    Q,
    S,
    \req_row_r_lcl_reg[13] ,
    row_hit_r_reg,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    was_wr0,
    \req_bank_r_lcl_reg[2] ,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[2] ,
    D,
    wr_accepted,
    \req_data_buf_addr_r_reg[4]_0 ,
    row,
    \req_col_r_reg[9] ,
    app_rdy_ns,
    CLK,
    reset_reg,
    app_en,
    periodic_rd_ack_r,
    periodic_rd_cntr_r,
    periodic_rd_r,
    occ_cnt_r,
    \not_strict_mode.app_rd_data_end_reg ,
    \not_strict_mode.app_rd_data_valid_reg ,
    idle_r_lcl_reg,
    \req_bank_r_lcl_reg[2]_0 ,
    idle_r_lcl_reg_0,
    \req_bank_r_lcl_reg[2]_1 ,
    idle_r_lcl_reg_1,
    \req_bank_r_lcl_reg[2]_2 ,
    idle_r_lcl_reg_2,
    \req_bank_r_lcl_reg[2]_3 ,
    \req_row_r_lcl_reg[13]_0 ,
    \req_row_r_lcl_reg[13]_1 ,
    \req_row_r_lcl_reg[13]_2 ,
    \req_row_r_lcl_reg[13]_3 ,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ,
    DOB,
    \data_buf_address_counter.data_buf_addr_cnt_r_reg[3] ,
    app_addr,
    app_cmd);
  output [0:0]E;
  output \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  output req_wr_r_lcl_reg;
  output [0:0]app_cmd_r2;
  output \req_data_buf_addr_r_reg[4] ;
  output rd_accepted;
  output p_106_out;
  output p_145_out;
  output p_28_out;
  output p_67_out;
  output req_wr_r_lcl_reg_0;
  output [0:0]Q;
  output [0:0]S;
  output \req_row_r_lcl_reg[13] ;
  output [0:0]row_hit_r_reg;
  output [0:0]row_hit_r_reg_0;
  output [0:0]row_hit_r_reg_1;
  output was_wr0;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output \not_strict_mode.occupied_counter.occ_cnt_r_reg[2] ;
  output [0:0]D;
  output wr_accepted;
  output [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  output [12:0]row;
  output [9:0]\req_col_r_reg[9] ;
  input app_rdy_ns;
  input CLK;
  input reset_reg;
  input app_en;
  input periodic_rd_ack_r;
  input periodic_rd_cntr_r;
  input periodic_rd_r;
  input [3:0]occ_cnt_r;
  input \not_strict_mode.app_rd_data_end_reg ;
  input \not_strict_mode.app_rd_data_valid_reg ;
  input idle_r_lcl_reg;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input idle_r_lcl_reg_0;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input idle_r_lcl_reg_1;
  input [2:0]\req_bank_r_lcl_reg[2]_2 ;
  input idle_r_lcl_reg_2;
  input [2:0]\req_bank_r_lcl_reg[2]_3 ;
  input [1:0]\req_row_r_lcl_reg[13]_0 ;
  input [1:0]\req_row_r_lcl_reg[13]_1 ;
  input [1:0]\req_row_r_lcl_reg[13]_2 ;
  input [1:0]\req_row_r_lcl_reg[13]_3 ;
  input [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;
  input [1:0]DOB;
  input [1:0]\data_buf_address_counter.data_buf_addr_cnt_r_reg[3] ;
  input [26:0]app_addr;
  input [1:0]app_cmd;

  wire CLK;
  wire [0:0]D;
  wire [1:0]DOB;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]S;
  wire [26:0]app_addr;
  wire app_addr_r10;
  wire \app_addr_r1_reg_n_0_[0] ;
  wire \app_addr_r1_reg_n_0_[10] ;
  wire \app_addr_r1_reg_n_0_[11] ;
  wire \app_addr_r1_reg_n_0_[12] ;
  wire \app_addr_r1_reg_n_0_[13] ;
  wire \app_addr_r1_reg_n_0_[14] ;
  wire \app_addr_r1_reg_n_0_[15] ;
  wire \app_addr_r1_reg_n_0_[16] ;
  wire \app_addr_r1_reg_n_0_[17] ;
  wire \app_addr_r1_reg_n_0_[18] ;
  wire \app_addr_r1_reg_n_0_[19] ;
  wire \app_addr_r1_reg_n_0_[1] ;
  wire \app_addr_r1_reg_n_0_[20] ;
  wire \app_addr_r1_reg_n_0_[21] ;
  wire \app_addr_r1_reg_n_0_[22] ;
  wire \app_addr_r1_reg_n_0_[23] ;
  wire \app_addr_r1_reg_n_0_[2] ;
  wire \app_addr_r1_reg_n_0_[3] ;
  wire \app_addr_r1_reg_n_0_[4] ;
  wire \app_addr_r1_reg_n_0_[5] ;
  wire \app_addr_r1_reg_n_0_[6] ;
  wire \app_addr_r1_reg_n_0_[7] ;
  wire \app_addr_r1_reg_n_0_[8] ;
  wire \app_addr_r1_reg_n_0_[9] ;
  wire \app_addr_r2_reg_n_0_[0] ;
  wire \app_addr_r2_reg_n_0_[10] ;
  wire \app_addr_r2_reg_n_0_[11] ;
  wire \app_addr_r2_reg_n_0_[12] ;
  wire \app_addr_r2_reg_n_0_[13] ;
  wire \app_addr_r2_reg_n_0_[14] ;
  wire \app_addr_r2_reg_n_0_[15] ;
  wire \app_addr_r2_reg_n_0_[16] ;
  wire \app_addr_r2_reg_n_0_[17] ;
  wire \app_addr_r2_reg_n_0_[18] ;
  wire \app_addr_r2_reg_n_0_[19] ;
  wire \app_addr_r2_reg_n_0_[1] ;
  wire \app_addr_r2_reg_n_0_[20] ;
  wire \app_addr_r2_reg_n_0_[21] ;
  wire \app_addr_r2_reg_n_0_[22] ;
  wire \app_addr_r2_reg_n_0_[23] ;
  wire \app_addr_r2_reg_n_0_[2] ;
  wire \app_addr_r2_reg_n_0_[3] ;
  wire \app_addr_r2_reg_n_0_[4] ;
  wire \app_addr_r2_reg_n_0_[5] ;
  wire \app_addr_r2_reg_n_0_[6] ;
  wire \app_addr_r2_reg_n_0_[7] ;
  wire \app_addr_r2_reg_n_0_[8] ;
  wire \app_addr_r2_reg_n_0_[9] ;
  wire [1:0]app_cmd;
  wire [0:0]app_cmd_r1;
  wire [0:0]app_cmd_r2;
  wire app_en;
  wire app_en_r1;
  wire app_rdy_ns;
  wire [1:0]\data_buf_address_counter.data_buf_addr_cnt_r_reg[3] ;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire \not_strict_mode.app_rd_data_end_reg ;
  wire \not_strict_mode.app_rd_data_valid_reg ;
  wire \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_3_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_4_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[2] ;
  wire [3:0]occ_cnt_r;
  wire [2:0]p_0_in;
  wire p_106_out;
  wire p_145_out;
  wire [2:0]p_1_in;
  wire p_28_out;
  wire p_67_out;
  wire periodic_rd_ack_r;
  wire periodic_rd_cntr_r;
  wire periodic_rd_r;
  wire rb_hit_busy_r_i_2__0_n_0;
  wire rb_hit_busy_r_i_2__1_n_0;
  wire rb_hit_busy_r_i_2__2_n_0;
  wire rb_hit_busy_r_i_2_n_0;
  wire rd_accepted;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_3 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire \req_data_buf_addr_r_reg[4] ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  wire \req_row_r_lcl_reg[13] ;
  wire [1:0]\req_row_r_lcl_reg[13]_0 ;
  wire [1:0]\req_row_r_lcl_reg[13]_1 ;
  wire [1:0]\req_row_r_lcl_reg[13]_2 ;
  wire [1:0]\req_row_r_lcl_reg[13]_3 ;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire reset_reg;
  wire [12:0]row;
  wire [0:0]row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire use_addr;
  wire was_wr0;
  wire wr_accepted;

  LUT2 #(
    .INIT(4'h8)) 
    \app_addr_r1[26]_i_1 
       (.I0(E),
        .I1(app_en),
        .O(app_addr_r10));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[0] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[0]),
        .Q(\app_addr_r1_reg_n_0_[0] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[10] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[10]),
        .Q(\app_addr_r1_reg_n_0_[10] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[11] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[11]),
        .Q(\app_addr_r1_reg_n_0_[11] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[12] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[12]),
        .Q(\app_addr_r1_reg_n_0_[12] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[13] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[13]),
        .Q(\app_addr_r1_reg_n_0_[13] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[14] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[14]),
        .Q(\app_addr_r1_reg_n_0_[14] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[15] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[15]),
        .Q(\app_addr_r1_reg_n_0_[15] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[16] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[16]),
        .Q(\app_addr_r1_reg_n_0_[16] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[17] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[17]),
        .Q(\app_addr_r1_reg_n_0_[17] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[18] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[18]),
        .Q(\app_addr_r1_reg_n_0_[18] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[19] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[19]),
        .Q(\app_addr_r1_reg_n_0_[19] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[1] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[1]),
        .Q(\app_addr_r1_reg_n_0_[1] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[20] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[20]),
        .Q(\app_addr_r1_reg_n_0_[20] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[21] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[21]),
        .Q(\app_addr_r1_reg_n_0_[21] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[22] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[22]),
        .Q(\app_addr_r1_reg_n_0_[22] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[23] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[23]),
        .Q(\app_addr_r1_reg_n_0_[23] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[24] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[24]),
        .Q(p_1_in[0]),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[25] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[25]),
        .Q(p_1_in[1]),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[26] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[26]),
        .Q(p_1_in[2]),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[2] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[2]),
        .Q(\app_addr_r1_reg_n_0_[2] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[3] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[3]),
        .Q(\app_addr_r1_reg_n_0_[3] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[4] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[4]),
        .Q(\app_addr_r1_reg_n_0_[4] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[5] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[5]),
        .Q(\app_addr_r1_reg_n_0_[5] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[6] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[6]),
        .Q(\app_addr_r1_reg_n_0_[6] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[7] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[7]),
        .Q(\app_addr_r1_reg_n_0_[7] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[8] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[8]),
        .Q(\app_addr_r1_reg_n_0_[8] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[9] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[9]),
        .Q(\app_addr_r1_reg_n_0_[9] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[0] ),
        .Q(\app_addr_r2_reg_n_0_[0] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[10] ),
        .Q(\app_addr_r2_reg_n_0_[10] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[11] ),
        .Q(\app_addr_r2_reg_n_0_[11] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[12] ),
        .Q(\app_addr_r2_reg_n_0_[12] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[13] ),
        .Q(\app_addr_r2_reg_n_0_[13] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[14] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[14] ),
        .Q(\app_addr_r2_reg_n_0_[14] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[15] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[15] ),
        .Q(\app_addr_r2_reg_n_0_[15] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[16] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[16] ),
        .Q(\app_addr_r2_reg_n_0_[16] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[17] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[17] ),
        .Q(\app_addr_r2_reg_n_0_[17] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[18] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[18] ),
        .Q(\app_addr_r2_reg_n_0_[18] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[19] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[19] ),
        .Q(\app_addr_r2_reg_n_0_[19] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[1] ),
        .Q(\app_addr_r2_reg_n_0_[1] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[20] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[20] ),
        .Q(\app_addr_r2_reg_n_0_[20] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[21] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[21] ),
        .Q(\app_addr_r2_reg_n_0_[21] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[22] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[22] ),
        .Q(\app_addr_r2_reg_n_0_[22] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[23] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[23] ),
        .Q(\app_addr_r2_reg_n_0_[23] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[24] 
       (.C(CLK),
        .CE(E),
        .D(p_1_in[0]),
        .Q(p_0_in[0]),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[25] 
       (.C(CLK),
        .CE(E),
        .D(p_1_in[1]),
        .Q(p_0_in[1]),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[26] 
       (.C(CLK),
        .CE(E),
        .D(p_1_in[2]),
        .Q(p_0_in[2]),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[2] ),
        .Q(\app_addr_r2_reg_n_0_[2] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[3] ),
        .Q(\app_addr_r2_reg_n_0_[3] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[4] ),
        .Q(\app_addr_r2_reg_n_0_[4] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[5] ),
        .Q(\app_addr_r2_reg_n_0_[5] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[6] ),
        .Q(\app_addr_r2_reg_n_0_[6] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[7] ),
        .Q(\app_addr_r2_reg_n_0_[7] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[8] ),
        .Q(\app_addr_r2_reg_n_0_[8] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[9] ),
        .Q(\app_addr_r2_reg_n_0_[9] ),
        .R(reset_reg));
  FDRE \app_cmd_r1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(app_cmd[0]),
        .Q(app_cmd_r1),
        .R(1'b0));
  FDRE \app_cmd_r1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(app_cmd[1]),
        .Q(Q),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(app_cmd_r1),
        .Q(app_cmd_r2),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(Q),
        .Q(\req_data_buf_addr_r_reg[4] ),
        .R(1'b0));
  FDRE app_en_r1_reg
       (.C(CLK),
        .CE(E),
        .D(app_en),
        .Q(app_en_r1),
        .R(reset_reg));
  FDRE app_en_r2_reg
       (.C(CLK),
        .CE(E),
        .D(app_en_r1),
        .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .R(reset_reg));
  FDRE #(
    .INIT(1'b0)) 
    app_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_rdy_ns),
        .Q(E),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT4 #(
    .INIT(16'h8008)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I1(E),
        .I2(\req_data_buf_addr_r_reg[4] ),
        .I3(app_cmd_r2),
        .O(wr_accepted));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I1(E),
        .I2(app_cmd_r2),
        .I3(\req_data_buf_addr_r_reg[4] ),
        .O(rd_accepted));
  LUT6 #(
    .INIT(64'h0101010140010101)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_2 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_4_n_0 ),
        .I1(occ_cnt_r[1]),
        .I2(occ_cnt_r[0]),
        .I3(use_addr),
        .I4(app_cmd_r2),
        .I5(\req_data_buf_addr_r_reg[4] ),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_3 
       (.I0(E),
        .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .O(use_addr));
  LUT6 #(
    .INIT(64'h00000000FF3E00C1)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2_n_0 ),
        .I1(occ_cnt_r[2]),
        .I2(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_3_n_0 ),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_4_n_0 ),
        .I4(occ_cnt_r[3]),
        .I5(reset_reg),
        .O(D));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4000)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2 
       (.I0(\req_data_buf_addr_r_reg[4] ),
        .I1(app_cmd_r2),
        .I2(E),
        .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I4(occ_cnt_r[1]),
        .I5(occ_cnt_r[0]),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000080000000)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_3 
       (.I0(occ_cnt_r[1]),
        .I1(occ_cnt_r[0]),
        .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I3(E),
        .I4(app_cmd_r2),
        .I5(\req_data_buf_addr_r_reg[4] ),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4000BFFFBFFFBFFF)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_4 
       (.I0(\req_data_buf_addr_r_reg[4] ),
        .I1(app_cmd_r2),
        .I2(E),
        .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I4(\not_strict_mode.app_rd_data_end_reg ),
        .I5(\not_strict_mode.app_rd_data_valid_reg ),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h2020200202022002)) 
    rb_hit_busy_r_i_1
       (.I0(idle_r_lcl_reg),
        .I1(rb_hit_busy_r_i_2__0_n_0),
        .I2(\req_bank_r_lcl_reg[2]_0 [0]),
        .I3(p_0_in[0]),
        .I4(E),
        .I5(p_1_in[0]),
        .O(p_106_out));
  LUT6 #(
    .INIT(64'h0000000088822282)) 
    rb_hit_busy_r_i_1__0
       (.I0(idle_r_lcl_reg_0),
        .I1(\req_bank_r_lcl_reg[2]_1 [1]),
        .I2(p_0_in[1]),
        .I3(E),
        .I4(p_1_in[1]),
        .I5(rb_hit_busy_r_i_2_n_0),
        .O(p_145_out));
  LUT6 #(
    .INIT(64'h2020200202022002)) 
    rb_hit_busy_r_i_1__1
       (.I0(idle_r_lcl_reg_1),
        .I1(rb_hit_busy_r_i_2__2_n_0),
        .I2(\req_bank_r_lcl_reg[2]_2 [2]),
        .I3(p_0_in[2]),
        .I4(E),
        .I5(p_1_in[2]),
        .O(p_28_out));
  LUT6 #(
    .INIT(64'h2020200202022002)) 
    rb_hit_busy_r_i_1__2
       (.I0(idle_r_lcl_reg_2),
        .I1(rb_hit_busy_r_i_2__1_n_0),
        .I2(\req_bank_r_lcl_reg[2]_3 [2]),
        .I3(p_0_in[2]),
        .I4(E),
        .I5(p_1_in[2]),
        .O(p_67_out));
  LUT6 #(
    .INIT(64'h47B8FFFFFFFF47B8)) 
    rb_hit_busy_r_i_2
       (.I0(p_1_in[0]),
        .I1(E),
        .I2(p_0_in[0]),
        .I3(\req_bank_r_lcl_reg[2]_1 [0]),
        .I4(\req_bank_r_lcl_reg[2] [2]),
        .I5(\req_bank_r_lcl_reg[2]_1 [2]),
        .O(rb_hit_busy_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h47B8FFFFFFFF47B8)) 
    rb_hit_busy_r_i_2__0
       (.I0(p_1_in[2]),
        .I1(E),
        .I2(p_0_in[2]),
        .I3(\req_bank_r_lcl_reg[2]_0 [2]),
        .I4(\req_bank_r_lcl_reg[2] [1]),
        .I5(\req_bank_r_lcl_reg[2]_0 [1]),
        .O(rb_hit_busy_r_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h47B8FFFFFFFF47B8)) 
    rb_hit_busy_r_i_2__1
       (.I0(p_1_in[0]),
        .I1(E),
        .I2(p_0_in[0]),
        .I3(\req_bank_r_lcl_reg[2]_3 [0]),
        .I4(\req_bank_r_lcl_reg[2] [1]),
        .I5(\req_bank_r_lcl_reg[2]_3 [1]),
        .O(rb_hit_busy_r_i_2__1_n_0));
  LUT6 #(
    .INIT(64'h47B8FFFFFFFF47B8)) 
    rb_hit_busy_r_i_2__2
       (.I0(p_1_in[0]),
        .I1(E),
        .I2(p_0_in[0]),
        .I3(\req_bank_r_lcl_reg[2]_2 [0]),
        .I4(\req_bank_r_lcl_reg[2] [1]),
        .I5(\req_bank_r_lcl_reg[2]_2 [1]),
        .O(rb_hit_busy_r_i_2__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[0]_i_1 
       (.I0(p_1_in[0]),
        .I1(E),
        .I2(p_0_in[0]),
        .O(\req_bank_r_lcl_reg[2] [0]));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[1]_i_1 
       (.I0(p_1_in[1]),
        .I1(E),
        .I2(p_0_in[1]),
        .O(\req_bank_r_lcl_reg[2] [1]));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[2]_i_1 
       (.I0(p_1_in[2]),
        .I1(E),
        .I2(p_0_in[2]),
        .O(\req_bank_r_lcl_reg[2] [2]));
  LUT6 #(
    .INIT(64'hE2FFFFFFE2E2E2E2)) 
    \req_cmd_r[0]_i_2 
       (.I0(app_cmd_r2),
        .I1(E),
        .I2(app_cmd_r1),
        .I3(periodic_rd_ack_r),
        .I4(periodic_rd_cntr_r),
        .I5(periodic_rd_r),
        .O(req_wr_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[0]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[0] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[0] ),
        .O(\req_col_r_reg[9] [0]));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[1]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[1] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[1] ),
        .O(\req_col_r_reg[9] [1]));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[2]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[2] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[2] ),
        .O(\req_col_r_reg[9] [2]));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[3]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[3] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[3] ),
        .O(\req_col_r_reg[9] [3]));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[4]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[4] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[4] ),
        .O(\req_col_r_reg[9] [4]));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[5]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[5] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[5] ),
        .O(\req_col_r_reg[9] [5]));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[6]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[6] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[6] ),
        .O(\req_col_r_reg[9] [6]));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[7]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[7] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[7] ),
        .O(\req_col_r_reg[9] [7]));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[8]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[8] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[8] ),
        .O(\req_col_r_reg[9] [8]));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[9]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[9] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[9] ),
        .O(\req_col_r_reg[9] [9]));
  LUT4 #(
    .INIT(16'hEB28)) 
    \req_data_buf_addr_r[0]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),
        .I1(app_cmd_r2),
        .I2(\req_data_buf_addr_r_reg[4] ),
        .I3(DOB[0]),
        .O(\req_data_buf_addr_r_reg[4]_0 [0]));
  LUT4 #(
    .INIT(16'hEB28)) 
    \req_data_buf_addr_r[1]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),
        .I1(app_cmd_r2),
        .I2(\req_data_buf_addr_r_reg[4] ),
        .I3(DOB[1]),
        .O(\req_data_buf_addr_r_reg[4]_0 [1]));
  LUT4 #(
    .INIT(16'hEB28)) 
    \req_data_buf_addr_r[2]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),
        .I1(app_cmd_r2),
        .I2(\req_data_buf_addr_r_reg[4] ),
        .I3(\data_buf_address_counter.data_buf_addr_cnt_r_reg[3] [0]),
        .O(\req_data_buf_addr_r_reg[4]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT4 #(
    .INIT(16'hEB28)) 
    \req_data_buf_addr_r[3]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),
        .I1(app_cmd_r2),
        .I2(\req_data_buf_addr_r_reg[4] ),
        .I3(\data_buf_address_counter.data_buf_addr_cnt_r_reg[3] [1]),
        .O(\req_data_buf_addr_r_reg[4]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \req_data_buf_addr_r[4]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]),
        .I1(\req_data_buf_addr_r_reg[4] ),
        .I2(app_cmd_r2),
        .O(\req_data_buf_addr_r_reg[4]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[0]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[10] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[10] ),
        .O(row[0]));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[10]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[20] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[20] ),
        .O(row[10]));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[11]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[21] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[21] ),
        .O(row[11]));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[12]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .O(row[12]));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[13]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[23] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[23] ),
        .O(\req_row_r_lcl_reg[13] ));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[1]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[11] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[11] ),
        .O(row[1]));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[2]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[12] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[12] ),
        .O(row[2]));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[3]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[13] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[13] ),
        .O(row[3]));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[4]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[14] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[14] ),
        .O(row[4]));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[5]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[15] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[15] ),
        .O(row[5]));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[6]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[16] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[16] ),
        .O(row[6]));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[7]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[17] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[17] ),
        .O(row[7]));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[8]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[18] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[18] ),
        .O(row[8]));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[9]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[19] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[19] ),
        .O(row[9]));
  LUT6 #(
    .INIT(64'hE2000000E2E2E2E2)) 
    req_wr_r_lcl_i_2
       (.I0(\req_data_buf_addr_r_reg[4] ),
        .I1(E),
        .I2(Q),
        .I3(periodic_rd_ack_r),
        .I4(periodic_rd_cntr_r),
        .I5(periodic_rd_r),
        .O(req_wr_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'hB84700000000B847)) 
    row_hit_r_i_3
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .I3(\req_row_r_lcl_reg[13]_0 [0]),
        .I4(\req_row_r_lcl_reg[13] ),
        .I5(\req_row_r_lcl_reg[13]_0 [1]),
        .O(S));
  LUT6 #(
    .INIT(64'hB84700000000B847)) 
    row_hit_r_i_3__0
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .I3(\req_row_r_lcl_reg[13]_1 [0]),
        .I4(\req_row_r_lcl_reg[13] ),
        .I5(\req_row_r_lcl_reg[13]_1 [1]),
        .O(row_hit_r_reg));
  LUT6 #(
    .INIT(64'hB84700000000B847)) 
    row_hit_r_i_3__1
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .I3(\req_row_r_lcl_reg[13]_2 [0]),
        .I4(\req_row_r_lcl_reg[13] ),
        .I5(\req_row_r_lcl_reg[13]_2 [1]),
        .O(row_hit_r_reg_0));
  LUT6 #(
    .INIT(64'hB84700000000B847)) 
    row_hit_r_i_3__2
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .I3(\req_row_r_lcl_reg[13]_3 [0]),
        .I4(\req_row_r_lcl_reg[13] ),
        .I5(\req_row_r_lcl_reg[13]_3 [1]),
        .O(row_hit_r_reg_1));
  LUT5 #(
    .INIT(32'hE200E2E2)) 
    was_wr_i_1
       (.I0(app_cmd_r2),
        .I1(E),
        .I2(app_cmd_r1),
        .I3(periodic_rd_ack_r),
        .I4(periodic_rd_r),
        .O(was_wr0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ui_rd_data" *) 
module mig_7series_0_mig_7series_v2_3_ui_rd_data
   (\not_strict_mode.app_rd_data_end_reg_0 ,
    ADDRA,
    DOA,
    DOB,
    DOC,
    \not_strict_mode.app_rd_data_reg[11]_0 ,
    \not_strict_mode.app_rd_data_reg[9]_0 ,
    \not_strict_mode.app_rd_data_reg[7]_0 ,
    \not_strict_mode.app_rd_data_reg[17]_0 ,
    \not_strict_mode.app_rd_data_reg[15]_0 ,
    \not_strict_mode.app_rd_data_reg[13]_0 ,
    \not_strict_mode.app_rd_data_reg[23]_0 ,
    \not_strict_mode.app_rd_data_reg[21]_0 ,
    \not_strict_mode.app_rd_data_reg[19]_0 ,
    \not_strict_mode.app_rd_data_reg[29]_0 ,
    \not_strict_mode.app_rd_data_reg[27]_0 ,
    \not_strict_mode.app_rd_data_reg[25]_0 ,
    \not_strict_mode.app_rd_data_reg[35]_0 ,
    \not_strict_mode.app_rd_data_reg[33]_0 ,
    \not_strict_mode.app_rd_data_reg[31]_0 ,
    \not_strict_mode.app_rd_data_reg[41]_0 ,
    \not_strict_mode.app_rd_data_reg[39]_0 ,
    \not_strict_mode.app_rd_data_reg[37]_0 ,
    \not_strict_mode.app_rd_data_reg[47]_0 ,
    \not_strict_mode.app_rd_data_reg[45]_0 ,
    \not_strict_mode.app_rd_data_reg[43]_0 ,
    \not_strict_mode.app_rd_data_reg[53]_0 ,
    \not_strict_mode.app_rd_data_reg[51]_0 ,
    \not_strict_mode.app_rd_data_reg[49]_0 ,
    \not_strict_mode.app_rd_data_reg[59]_0 ,
    \not_strict_mode.app_rd_data_reg[57]_0 ,
    \not_strict_mode.app_rd_data_reg[55]_0 ,
    \not_strict_mode.app_rd_data_reg[65]_0 ,
    \not_strict_mode.app_rd_data_reg[63]_0 ,
    \not_strict_mode.app_rd_data_reg[61]_0 ,
    \not_strict_mode.app_rd_data_reg[71]_0 ,
    \not_strict_mode.app_rd_data_reg[69]_0 ,
    \not_strict_mode.app_rd_data_reg[67]_0 ,
    \not_strict_mode.app_rd_data_reg[77]_0 ,
    \not_strict_mode.app_rd_data_reg[75]_0 ,
    \not_strict_mode.app_rd_data_reg[73]_0 ,
    \not_strict_mode.app_rd_data_reg[83]_0 ,
    \not_strict_mode.app_rd_data_reg[81]_0 ,
    \not_strict_mode.app_rd_data_reg[79]_0 ,
    \not_strict_mode.app_rd_data_reg[89]_0 ,
    \not_strict_mode.app_rd_data_reg[87]_0 ,
    \not_strict_mode.app_rd_data_reg[85]_0 ,
    \not_strict_mode.app_rd_data_reg[95]_0 ,
    \not_strict_mode.app_rd_data_reg[93]_0 ,
    \not_strict_mode.app_rd_data_reg[91]_0 ,
    \not_strict_mode.app_rd_data_reg[101]_0 ,
    \not_strict_mode.app_rd_data_reg[99]_0 ,
    \not_strict_mode.app_rd_data_reg[97]_0 ,
    \not_strict_mode.app_rd_data_reg[107]_0 ,
    \not_strict_mode.app_rd_data_reg[105]_0 ,
    \not_strict_mode.app_rd_data_reg[103]_0 ,
    \not_strict_mode.app_rd_data_reg[113]_0 ,
    \not_strict_mode.app_rd_data_reg[111]_0 ,
    \not_strict_mode.app_rd_data_reg[109]_0 ,
    \not_strict_mode.app_rd_data_reg[119]_0 ,
    \not_strict_mode.app_rd_data_reg[117]_0 ,
    \not_strict_mode.app_rd_data_reg[115]_0 ,
    \not_strict_mode.app_rd_data_reg[125]_0 ,
    \not_strict_mode.app_rd_data_reg[123]_0 ,
    \not_strict_mode.app_rd_data_reg[121]_0 ,
    \not_strict_mode.app_rd_data_reg[131]_0 ,
    \not_strict_mode.app_rd_data_reg[129]_0 ,
    \not_strict_mode.app_rd_data_reg[127]_0 ,
    \not_strict_mode.app_rd_data_reg[137]_0 ,
    \not_strict_mode.app_rd_data_reg[135]_0 ,
    \not_strict_mode.app_rd_data_reg[133]_0 ,
    \not_strict_mode.app_rd_data_reg[143]_0 ,
    \not_strict_mode.app_rd_data_reg[141]_0 ,
    \not_strict_mode.app_rd_data_reg[139]_0 ,
    \not_strict_mode.app_rd_data_reg[149]_0 ,
    \not_strict_mode.app_rd_data_reg[147]_0 ,
    \not_strict_mode.app_rd_data_reg[145]_0 ,
    \not_strict_mode.app_rd_data_reg[155]_0 ,
    \not_strict_mode.app_rd_data_reg[153]_0 ,
    \not_strict_mode.app_rd_data_reg[151]_0 ,
    \not_strict_mode.app_rd_data_reg[161]_0 ,
    \not_strict_mode.app_rd_data_reg[159]_0 ,
    \not_strict_mode.app_rd_data_reg[157]_0 ,
    \not_strict_mode.app_rd_data_reg[167]_0 ,
    \not_strict_mode.app_rd_data_reg[165]_0 ,
    \not_strict_mode.app_rd_data_reg[163]_0 ,
    \not_strict_mode.app_rd_data_reg[173]_0 ,
    \not_strict_mode.app_rd_data_reg[171]_0 ,
    \not_strict_mode.app_rd_data_reg[169]_0 ,
    \not_strict_mode.app_rd_data_reg[179]_0 ,
    \not_strict_mode.app_rd_data_reg[177]_0 ,
    \not_strict_mode.app_rd_data_reg[175]_0 ,
    \not_strict_mode.app_rd_data_reg[185]_0 ,
    \not_strict_mode.app_rd_data_reg[183]_0 ,
    \not_strict_mode.app_rd_data_reg[181]_0 ,
    \not_strict_mode.app_rd_data_reg[191]_0 ,
    \not_strict_mode.app_rd_data_reg[189]_0 ,
    \not_strict_mode.app_rd_data_reg[187]_0 ,
    \not_strict_mode.app_rd_data_reg[197]_0 ,
    \not_strict_mode.app_rd_data_reg[195]_0 ,
    \not_strict_mode.app_rd_data_reg[193]_0 ,
    \not_strict_mode.app_rd_data_reg[203]_0 ,
    \not_strict_mode.app_rd_data_reg[201]_0 ,
    \not_strict_mode.app_rd_data_reg[199]_0 ,
    \not_strict_mode.app_rd_data_reg[209]_0 ,
    \not_strict_mode.app_rd_data_reg[207]_0 ,
    \not_strict_mode.app_rd_data_reg[205]_0 ,
    \not_strict_mode.app_rd_data_reg[215]_0 ,
    \not_strict_mode.app_rd_data_reg[213]_0 ,
    \not_strict_mode.app_rd_data_reg[211]_0 ,
    \not_strict_mode.app_rd_data_reg[221]_0 ,
    \not_strict_mode.app_rd_data_reg[219]_0 ,
    \not_strict_mode.app_rd_data_reg[217]_0 ,
    \not_strict_mode.app_rd_data_reg[227]_0 ,
    \not_strict_mode.app_rd_data_reg[225]_0 ,
    \not_strict_mode.app_rd_data_reg[223]_0 ,
    \not_strict_mode.app_rd_data_reg[233]_0 ,
    \not_strict_mode.app_rd_data_reg[231]_0 ,
    \not_strict_mode.app_rd_data_reg[229]_0 ,
    \not_strict_mode.app_rd_data_reg[239]_0 ,
    \not_strict_mode.app_rd_data_reg[237]_0 ,
    \not_strict_mode.app_rd_data_reg[235]_0 ,
    \not_strict_mode.app_rd_data_reg[245]_0 ,
    \not_strict_mode.app_rd_data_reg[243]_0 ,
    \not_strict_mode.app_rd_data_reg[241]_0 ,
    \not_strict_mode.app_rd_data_reg[251]_0 ,
    \not_strict_mode.app_rd_data_reg[249]_0 ,
    \not_strict_mode.app_rd_data_reg[247]_0 ,
    \not_strict_mode.app_rd_data_reg[257]_0 ,
    \not_strict_mode.app_rd_data_reg[255]_0 ,
    \not_strict_mode.app_rd_data_reg[253]_0 ,
    \not_strict_mode.app_rd_data_reg[263]_0 ,
    \not_strict_mode.app_rd_data_reg[261]_0 ,
    \not_strict_mode.app_rd_data_reg[259]_0 ,
    \not_strict_mode.app_rd_data_reg[269]_0 ,
    \not_strict_mode.app_rd_data_reg[267]_0 ,
    \not_strict_mode.app_rd_data_reg[265]_0 ,
    \not_strict_mode.app_rd_data_reg[275]_0 ,
    \not_strict_mode.app_rd_data_reg[273]_0 ,
    \not_strict_mode.app_rd_data_reg[271]_0 ,
    \not_strict_mode.app_rd_data_reg[281]_0 ,
    \not_strict_mode.app_rd_data_reg[279]_0 ,
    \not_strict_mode.app_rd_data_reg[277]_0 ,
    \not_strict_mode.app_rd_data_reg[287]_0 ,
    \not_strict_mode.app_rd_data_reg[285]_0 ,
    \not_strict_mode.app_rd_data_reg[283]_0 ,
    \not_strict_mode.app_rd_data_reg[293]_0 ,
    \not_strict_mode.app_rd_data_reg[291]_0 ,
    \not_strict_mode.app_rd_data_reg[289]_0 ,
    \not_strict_mode.app_rd_data_reg[299]_0 ,
    \not_strict_mode.app_rd_data_reg[297]_0 ,
    \not_strict_mode.app_rd_data_reg[295]_0 ,
    \not_strict_mode.app_rd_data_reg[305]_0 ,
    \not_strict_mode.app_rd_data_reg[303]_0 ,
    \not_strict_mode.app_rd_data_reg[301]_0 ,
    \not_strict_mode.app_rd_data_reg[311]_0 ,
    \not_strict_mode.app_rd_data_reg[309]_0 ,
    \not_strict_mode.app_rd_data_reg[307]_0 ,
    \not_strict_mode.app_rd_data_reg[317]_0 ,
    \not_strict_mode.app_rd_data_reg[315]_0 ,
    \not_strict_mode.app_rd_data_reg[313]_0 ,
    \not_strict_mode.app_rd_data_reg[323]_0 ,
    \not_strict_mode.app_rd_data_reg[321]_0 ,
    \not_strict_mode.app_rd_data_reg[319]_0 ,
    \not_strict_mode.app_rd_data_reg[329]_0 ,
    \not_strict_mode.app_rd_data_reg[327]_0 ,
    \not_strict_mode.app_rd_data_reg[325]_0 ,
    \not_strict_mode.app_rd_data_reg[335]_0 ,
    \not_strict_mode.app_rd_data_reg[333]_0 ,
    \not_strict_mode.app_rd_data_reg[331]_0 ,
    \not_strict_mode.app_rd_data_reg[341]_0 ,
    \not_strict_mode.app_rd_data_reg[339]_0 ,
    \not_strict_mode.app_rd_data_reg[337]_0 ,
    \not_strict_mode.app_rd_data_reg[347]_0 ,
    \not_strict_mode.app_rd_data_reg[345]_0 ,
    \not_strict_mode.app_rd_data_reg[343]_0 ,
    \not_strict_mode.app_rd_data_reg[353]_0 ,
    \not_strict_mode.app_rd_data_reg[351]_0 ,
    \not_strict_mode.app_rd_data_reg[349]_0 ,
    \not_strict_mode.app_rd_data_reg[359]_0 ,
    \not_strict_mode.app_rd_data_reg[357]_0 ,
    \not_strict_mode.app_rd_data_reg[355]_0 ,
    \not_strict_mode.app_rd_data_reg[365]_0 ,
    \not_strict_mode.app_rd_data_reg[363]_0 ,
    \not_strict_mode.app_rd_data_reg[361]_0 ,
    \not_strict_mode.app_rd_data_reg[371]_0 ,
    \not_strict_mode.app_rd_data_reg[369]_0 ,
    \not_strict_mode.app_rd_data_reg[367]_0 ,
    \not_strict_mode.app_rd_data_reg[377]_0 ,
    \not_strict_mode.app_rd_data_reg[375]_0 ,
    \not_strict_mode.app_rd_data_reg[373]_0 ,
    \not_strict_mode.app_rd_data_reg[383]_0 ,
    \not_strict_mode.app_rd_data_reg[381]_0 ,
    \not_strict_mode.app_rd_data_reg[379]_0 ,
    \not_strict_mode.app_rd_data_reg[389]_0 ,
    \not_strict_mode.app_rd_data_reg[387]_0 ,
    \not_strict_mode.app_rd_data_reg[385]_0 ,
    \not_strict_mode.app_rd_data_reg[395]_0 ,
    \not_strict_mode.app_rd_data_reg[393]_0 ,
    \not_strict_mode.app_rd_data_reg[391]_0 ,
    \not_strict_mode.app_rd_data_reg[401]_0 ,
    \not_strict_mode.app_rd_data_reg[399]_0 ,
    \not_strict_mode.app_rd_data_reg[397]_0 ,
    \not_strict_mode.app_rd_data_reg[407]_0 ,
    \not_strict_mode.app_rd_data_reg[405]_0 ,
    \not_strict_mode.app_rd_data_reg[403]_0 ,
    \not_strict_mode.app_rd_data_reg[413]_0 ,
    \not_strict_mode.app_rd_data_reg[411]_0 ,
    \not_strict_mode.app_rd_data_reg[409]_0 ,
    \not_strict_mode.app_rd_data_reg[419]_0 ,
    \not_strict_mode.app_rd_data_reg[417]_0 ,
    \not_strict_mode.app_rd_data_reg[415]_0 ,
    \not_strict_mode.app_rd_data_reg[425]_0 ,
    \not_strict_mode.app_rd_data_reg[423]_0 ,
    \not_strict_mode.app_rd_data_reg[421]_0 ,
    \not_strict_mode.app_rd_data_reg[431]_0 ,
    \not_strict_mode.app_rd_data_reg[429]_0 ,
    \not_strict_mode.app_rd_data_reg[427]_0 ,
    \not_strict_mode.app_rd_data_reg[437]_0 ,
    \not_strict_mode.app_rd_data_reg[435]_0 ,
    \not_strict_mode.app_rd_data_reg[433]_0 ,
    \not_strict_mode.app_rd_data_reg[443]_0 ,
    \not_strict_mode.app_rd_data_reg[441]_0 ,
    \not_strict_mode.app_rd_data_reg[439]_0 ,
    \not_strict_mode.app_rd_data_reg[449]_0 ,
    \not_strict_mode.app_rd_data_reg[447]_0 ,
    \not_strict_mode.app_rd_data_reg[445]_0 ,
    \not_strict_mode.app_rd_data_reg[455]_0 ,
    \not_strict_mode.app_rd_data_reg[453]_0 ,
    \not_strict_mode.app_rd_data_reg[451]_0 ,
    \not_strict_mode.app_rd_data_reg[461]_0 ,
    \not_strict_mode.app_rd_data_reg[459]_0 ,
    \not_strict_mode.app_rd_data_reg[457]_0 ,
    \not_strict_mode.app_rd_data_reg[467]_0 ,
    \not_strict_mode.app_rd_data_reg[465]_0 ,
    \not_strict_mode.app_rd_data_reg[463]_0 ,
    \not_strict_mode.app_rd_data_reg[473]_0 ,
    \not_strict_mode.app_rd_data_reg[471]_0 ,
    \not_strict_mode.app_rd_data_reg[469]_0 ,
    \not_strict_mode.app_rd_data_reg[479]_0 ,
    \not_strict_mode.app_rd_data_reg[477]_0 ,
    \not_strict_mode.app_rd_data_reg[475]_0 ,
    \not_strict_mode.app_rd_data_reg[485]_0 ,
    \not_strict_mode.app_rd_data_reg[483]_0 ,
    \not_strict_mode.app_rd_data_reg[481]_0 ,
    \not_strict_mode.app_rd_data_reg[491]_0 ,
    \not_strict_mode.app_rd_data_reg[489]_0 ,
    \not_strict_mode.app_rd_data_reg[487]_0 ,
    \not_strict_mode.app_rd_data_reg[497]_0 ,
    \not_strict_mode.app_rd_data_reg[495]_0 ,
    \not_strict_mode.app_rd_data_reg[493]_0 ,
    \not_strict_mode.app_rd_data_reg[503]_0 ,
    \not_strict_mode.app_rd_data_reg[501]_0 ,
    \not_strict_mode.app_rd_data_reg[499]_0 ,
    \not_strict_mode.app_rd_data_reg[509]_0 ,
    \not_strict_mode.app_rd_data_reg[507]_0 ,
    \not_strict_mode.app_rd_data_reg[505]_0 ,
    \not_strict_mode.app_rd_data_reg[511]_0 ,
    app_rd_data_valid,
    app_rd_data_end,
    \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ,
    \not_strict_mode.app_rd_data_reg[24]_0 ,
    D,
    Q,
    ADDRD,
    pointer_wr_data,
    app_rd_data,
    CLK,
    rd_buf_we,
    DIA,
    DIB,
    DIC,
    \read_fifo.fifo_out_data_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ,
    app_rd_data_end_ns,
    reset_reg,
    \read_fifo.fifo_out_data_r_reg[4] ,
    \app_cmd_r2_reg[1] ,
    app_cmd_r2,
    app_en_r2,
    app_rdy_r_reg,
    rd_accepted,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ,
    \read_data_indx.rd_data_indx_r_reg[3] ,
    \cmd_pipe_plus.wr_data_addr_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 ,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[2]_0 );
  output [0:0]\not_strict_mode.app_rd_data_end_reg_0 ;
  output [0:0]ADDRA;
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]\not_strict_mode.app_rd_data_reg[11]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[9]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[7]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[17]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[15]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[13]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[23]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[21]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[19]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[29]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[27]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[25]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[35]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[33]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[31]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[41]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[39]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[37]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[47]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[45]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[43]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[53]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[51]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[49]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[59]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[57]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[55]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[65]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[63]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[61]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[71]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[69]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[67]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[77]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[75]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[73]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[83]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[81]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[79]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[89]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[87]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[85]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[95]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[93]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[91]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[101]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[99]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[97]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[107]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[105]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[103]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[113]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[111]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[109]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[119]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[117]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[115]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[125]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[123]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[121]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[131]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[129]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[127]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[137]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[135]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[133]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[143]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[141]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[139]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[149]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[147]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[145]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[155]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[153]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[151]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[161]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[159]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[157]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[167]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[165]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[163]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[173]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[171]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[169]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[179]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[177]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[175]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[185]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[183]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[181]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[191]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[189]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[187]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[197]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[195]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[193]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[203]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[201]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[199]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[209]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[207]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[205]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[215]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[213]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[211]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[221]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[219]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[217]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[227]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[225]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[223]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[233]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[231]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[229]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[239]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[237]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[235]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[245]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[243]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[241]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[251]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[249]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[247]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[257]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[255]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[253]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[263]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[261]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[259]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[269]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[267]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[265]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[275]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[273]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[271]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[281]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[279]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[277]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[287]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[285]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[283]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[293]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[291]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[289]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[299]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[297]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[295]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[305]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[303]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[301]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[311]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[309]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[307]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[317]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[315]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[313]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[323]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[321]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[319]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[329]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[327]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[325]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[335]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[333]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[331]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[341]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[339]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[337]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[347]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[345]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[343]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[353]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[351]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[349]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[359]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[357]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[355]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[365]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[363]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[361]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[371]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[369]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[367]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[377]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[375]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[373]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[383]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[381]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[379]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[389]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[387]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[385]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[395]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[393]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[391]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[401]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[399]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[397]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[407]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[405]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[403]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[413]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[411]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[409]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[419]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[417]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[415]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[425]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[423]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[421]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[431]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[429]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[427]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[437]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[435]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[433]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[443]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[441]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[439]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[449]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[447]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[445]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[455]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[453]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[451]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[461]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[459]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[457]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[467]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[465]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[463]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[473]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[471]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[469]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[479]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[477]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[475]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[485]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[483]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[481]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[491]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[489]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[487]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[497]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[495]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[493]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[503]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[501]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[499]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[509]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[507]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[505]_0 ;
  output [1:0]\not_strict_mode.app_rd_data_reg[511]_0 ;
  output app_rd_data_valid;
  output app_rd_data_end;
  output \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ;
  output [3:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ;
  output \not_strict_mode.app_rd_data_reg[24]_0 ;
  output [0:0]D;
  output [4:0]Q;
  output [3:0]ADDRD;
  output [3:0]pointer_wr_data;
  output [511:0]app_rd_data;
  input CLK;
  input rd_buf_we;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [6:0]\read_fifo.fifo_out_data_r_reg[7] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;
  input app_rd_data_end_ns;
  input reset_reg;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input [0:0]\app_cmd_r2_reg[1] ;
  input [0:0]app_cmd_r2;
  input app_en_r2;
  input app_rdy_r_reg;
  input rd_accepted;
  input \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;
  input [3:0]\read_data_indx.rd_data_indx_r_reg[3] ;
  input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ;
  input [511:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 ;
  input [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[2]_0 ;

  wire [0:0]ADDRA;
  wire [3:0]ADDRD;
  wire CLK;
  wire [0:0]D;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [4:0]Q;
  wire [0:0]app_cmd_r2;
  wire [0:0]\app_cmd_r2_reg[1] ;
  wire app_en_r2;
  wire [511:0]app_rd_data;
  wire app_rd_data_end;
  wire app_rd_data_end_ns;
  wire app_rd_data_valid;
  wire app_rdy_r_reg;
  wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;
  wire [511:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ;
  wire \not_strict_mode.app_rd_data[511]_i_4_n_0 ;
  wire [0:0]\not_strict_mode.app_rd_data_end_reg_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[101]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[103]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[105]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[107]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[109]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[111]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[113]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[115]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[117]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[119]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[11]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[121]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[123]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[125]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[127]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[129]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[131]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[133]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[135]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[137]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[139]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[13]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[141]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[143]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[145]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[147]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[149]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[151]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[153]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[155]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[157]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[159]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[15]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[161]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[163]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[165]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[167]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[169]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[171]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[173]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[175]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[177]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[179]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[17]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[181]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[183]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[185]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[187]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[189]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[191]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[193]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[195]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[197]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[199]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[19]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[201]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[203]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[205]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[207]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[209]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[211]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[213]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[215]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[217]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[219]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[21]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[221]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[223]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[225]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[227]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[229]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[231]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[233]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[235]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[237]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[239]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[23]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[241]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[243]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[245]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[247]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[249]_0 ;
  wire \not_strict_mode.app_rd_data_reg[24]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[251]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[253]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[255]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[257]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[259]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[25]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[261]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[263]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[265]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[267]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[269]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[271]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[273]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[275]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[277]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[279]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[27]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[281]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[283]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[285]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[287]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[289]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[291]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[293]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[295]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[297]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[299]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[29]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[301]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[303]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[305]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[307]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[309]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[311]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[313]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[315]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[317]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[319]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[31]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[321]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[323]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[325]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[327]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[329]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[331]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[333]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[335]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[337]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[339]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[33]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[341]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[343]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[345]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[347]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[349]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[351]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[353]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[355]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[357]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[359]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[35]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[361]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[363]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[365]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[367]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[369]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[371]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[373]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[375]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[377]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[379]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[37]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[381]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[383]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[385]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[387]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[389]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[391]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[393]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[395]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[397]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[399]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[39]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[401]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[403]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[405]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[407]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[409]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[411]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[413]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[415]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[417]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[419]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[41]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[421]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[423]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[425]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[427]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[429]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[431]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[433]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[435]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[437]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[439]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[43]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[441]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[443]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[445]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[447]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[449]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[451]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[453]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[455]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[457]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[459]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[45]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[461]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[463]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[465]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[467]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[469]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[471]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[473]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[475]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[477]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[479]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[47]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[481]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[483]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[485]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[487]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[489]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[491]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[493]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[495]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[497]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[499]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[49]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[501]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[503]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[505]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[507]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[509]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[511]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[51]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[53]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[55]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[57]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[59]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[61]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[63]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[65]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[67]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[69]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[71]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[73]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[75]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[77]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[79]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[7]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[81]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[83]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[85]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[87]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[89]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[91]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[93]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[95]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[97]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[99]_0 ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[9]_0 ;
  wire \not_strict_mode.app_rd_data_valid_i_1_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_2_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_5_n_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;
  wire [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[2]_0 ;
  wire [3:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ;
  wire \not_strict_mode.status_ram.RAM32M0_n_1 ;
  wire \not_strict_mode.status_ram.RAM32M0_n_5 ;
  wire \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ;
  wire [5:4]occ_cnt_r;
  wire [4:0]p_0_in__2;
  wire [3:0]pointer_wr_data;
  wire [2:0]ram_init_addr;
  wire rd_accepted;
  wire \rd_buf_indx.ram_init_done_r_lcl_i_1_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[5]_i_1_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[5]_i_3_n_0 ;
  wire \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ;
  (* RTL_KEEP = "true" *) (* syn_keep = "1" *) wire [4:0]rd_buf_indx_copy_r;
  wire [4:4]rd_buf_indx_r;
  wire rd_buf_we;
  wire rd_buf_we_r1;
  wire [3:0]\read_data_indx.rd_data_indx_r_reg[3] ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire [6:0]\read_fifo.fifo_out_data_r_reg[7] ;
  wire reset_reg;
  wire [4:0]status_ram_wr_addr_ns;
  wire [4:0]status_ram_wr_addr_r;
  wire [1:0]status_ram_wr_data_ns;
  wire [1:0]status_ram_wr_data_r;
  wire wr_status_r1;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOB_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED ;

  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \not_strict_mode.app_rd_data[511]_i_3 
       (.I0(\read_fifo.fifo_out_data_r_reg[7] [5]),
        .I1(rd_buf_indx_r),
        .I2(\read_fifo.fifo_out_data_r_reg[7] [1]),
        .I3(ram_init_addr[0]),
        .I4(\not_strict_mode.app_rd_data[511]_i_4_n_0 ),
        .O(\not_strict_mode.app_rd_data_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT4 #(
    .INIT(16'h6FF6)) 
    \not_strict_mode.app_rd_data[511]_i_4 
       (.I0(ram_init_addr[1]),
        .I1(\read_fifo.fifo_out_data_r_reg[7] [2]),
        .I2(ram_init_addr[2]),
        .I3(\read_fifo.fifo_out_data_r_reg[7] [3]),
        .O(\not_strict_mode.app_rd_data[511]_i_4_n_0 ));
  FDRE \not_strict_mode.app_rd_data_end_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(app_rd_data_end_ns),
        .Q(app_rd_data_end),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [0]),
        .Q(app_rd_data[0]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[100] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [100]),
        .Q(app_rd_data[100]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[101] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [101]),
        .Q(app_rd_data[101]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[102] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [102]),
        .Q(app_rd_data[102]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[103] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [103]),
        .Q(app_rd_data[103]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[104] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [104]),
        .Q(app_rd_data[104]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[105] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [105]),
        .Q(app_rd_data[105]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[106] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [106]),
        .Q(app_rd_data[106]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[107] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [107]),
        .Q(app_rd_data[107]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[108] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [108]),
        .Q(app_rd_data[108]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[109] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [109]),
        .Q(app_rd_data[109]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [10]),
        .Q(app_rd_data[10]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[110] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [110]),
        .Q(app_rd_data[110]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[111] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [111]),
        .Q(app_rd_data[111]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[112] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [112]),
        .Q(app_rd_data[112]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[113] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [113]),
        .Q(app_rd_data[113]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[114] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [114]),
        .Q(app_rd_data[114]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[115] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [115]),
        .Q(app_rd_data[115]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[116] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [116]),
        .Q(app_rd_data[116]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[117] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [117]),
        .Q(app_rd_data[117]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[118] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [118]),
        .Q(app_rd_data[118]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[119] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [119]),
        .Q(app_rd_data[119]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [11]),
        .Q(app_rd_data[11]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[120] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [120]),
        .Q(app_rd_data[120]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[121] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [121]),
        .Q(app_rd_data[121]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[122] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [122]),
        .Q(app_rd_data[122]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[123] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [123]),
        .Q(app_rd_data[123]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[124] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [124]),
        .Q(app_rd_data[124]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[125] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [125]),
        .Q(app_rd_data[125]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[126] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [126]),
        .Q(app_rd_data[126]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[127] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [127]),
        .Q(app_rd_data[127]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[128] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [128]),
        .Q(app_rd_data[128]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[129] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [129]),
        .Q(app_rd_data[129]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [12]),
        .Q(app_rd_data[12]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[130] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [130]),
        .Q(app_rd_data[130]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[131] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [131]),
        .Q(app_rd_data[131]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[132] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [132]),
        .Q(app_rd_data[132]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[133] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [133]),
        .Q(app_rd_data[133]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[134] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [134]),
        .Q(app_rd_data[134]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[135] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [135]),
        .Q(app_rd_data[135]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[136] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [136]),
        .Q(app_rd_data[136]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[137] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [137]),
        .Q(app_rd_data[137]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[138] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [138]),
        .Q(app_rd_data[138]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[139] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [139]),
        .Q(app_rd_data[139]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [13]),
        .Q(app_rd_data[13]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[140] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [140]),
        .Q(app_rd_data[140]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[141] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [141]),
        .Q(app_rd_data[141]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[142] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [142]),
        .Q(app_rd_data[142]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[143] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [143]),
        .Q(app_rd_data[143]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[144] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [144]),
        .Q(app_rd_data[144]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[145] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [145]),
        .Q(app_rd_data[145]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[146] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [146]),
        .Q(app_rd_data[146]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[147] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [147]),
        .Q(app_rd_data[147]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[148] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [148]),
        .Q(app_rd_data[148]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[149] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [149]),
        .Q(app_rd_data[149]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [14]),
        .Q(app_rd_data[14]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[150] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [150]),
        .Q(app_rd_data[150]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[151] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [151]),
        .Q(app_rd_data[151]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[152] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [152]),
        .Q(app_rd_data[152]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[153] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [153]),
        .Q(app_rd_data[153]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[154] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [154]),
        .Q(app_rd_data[154]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[155] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [155]),
        .Q(app_rd_data[155]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[156] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [156]),
        .Q(app_rd_data[156]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[157] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [157]),
        .Q(app_rd_data[157]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[158] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [158]),
        .Q(app_rd_data[158]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[159] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [159]),
        .Q(app_rd_data[159]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [15]),
        .Q(app_rd_data[15]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[160] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [160]),
        .Q(app_rd_data[160]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[161] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [161]),
        .Q(app_rd_data[161]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[162] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [162]),
        .Q(app_rd_data[162]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[163] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [163]),
        .Q(app_rd_data[163]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[164] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [164]),
        .Q(app_rd_data[164]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[165] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [165]),
        .Q(app_rd_data[165]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[166] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [166]),
        .Q(app_rd_data[166]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[167] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [167]),
        .Q(app_rd_data[167]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[168] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [168]),
        .Q(app_rd_data[168]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[169] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [169]),
        .Q(app_rd_data[169]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [16]),
        .Q(app_rd_data[16]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[170] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [170]),
        .Q(app_rd_data[170]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[171] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [171]),
        .Q(app_rd_data[171]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[172] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [172]),
        .Q(app_rd_data[172]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[173] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [173]),
        .Q(app_rd_data[173]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[174] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [174]),
        .Q(app_rd_data[174]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[175] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [175]),
        .Q(app_rd_data[175]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[176] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [176]),
        .Q(app_rd_data[176]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[177] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [177]),
        .Q(app_rd_data[177]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[178] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [178]),
        .Q(app_rd_data[178]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[179] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [179]),
        .Q(app_rd_data[179]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [17]),
        .Q(app_rd_data[17]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[180] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [180]),
        .Q(app_rd_data[180]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[181] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [181]),
        .Q(app_rd_data[181]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[182] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [182]),
        .Q(app_rd_data[182]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[183] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [183]),
        .Q(app_rd_data[183]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[184] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [184]),
        .Q(app_rd_data[184]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[185] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [185]),
        .Q(app_rd_data[185]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[186] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [186]),
        .Q(app_rd_data[186]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[187] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [187]),
        .Q(app_rd_data[187]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[188] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [188]),
        .Q(app_rd_data[188]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[189] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [189]),
        .Q(app_rd_data[189]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [18]),
        .Q(app_rd_data[18]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[190] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [190]),
        .Q(app_rd_data[190]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[191] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [191]),
        .Q(app_rd_data[191]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[192] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [192]),
        .Q(app_rd_data[192]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[193] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [193]),
        .Q(app_rd_data[193]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[194] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [194]),
        .Q(app_rd_data[194]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[195] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [195]),
        .Q(app_rd_data[195]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[196] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [196]),
        .Q(app_rd_data[196]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[197] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [197]),
        .Q(app_rd_data[197]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[198] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [198]),
        .Q(app_rd_data[198]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[199] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [199]),
        .Q(app_rd_data[199]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [19]),
        .Q(app_rd_data[19]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [1]),
        .Q(app_rd_data[1]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[200] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [200]),
        .Q(app_rd_data[200]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[201] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [201]),
        .Q(app_rd_data[201]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[202] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [202]),
        .Q(app_rd_data[202]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[203] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [203]),
        .Q(app_rd_data[203]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[204] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [204]),
        .Q(app_rd_data[204]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[205] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [205]),
        .Q(app_rd_data[205]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[206] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [206]),
        .Q(app_rd_data[206]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[207] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [207]),
        .Q(app_rd_data[207]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[208] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [208]),
        .Q(app_rd_data[208]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[209] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [209]),
        .Q(app_rd_data[209]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [20]),
        .Q(app_rd_data[20]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[210] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [210]),
        .Q(app_rd_data[210]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[211] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [211]),
        .Q(app_rd_data[211]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[212] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [212]),
        .Q(app_rd_data[212]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[213] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [213]),
        .Q(app_rd_data[213]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[214] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [214]),
        .Q(app_rd_data[214]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[215] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [215]),
        .Q(app_rd_data[215]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[216] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [216]),
        .Q(app_rd_data[216]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[217] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [217]),
        .Q(app_rd_data[217]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[218] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [218]),
        .Q(app_rd_data[218]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[219] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [219]),
        .Q(app_rd_data[219]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [21]),
        .Q(app_rd_data[21]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[220] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [220]),
        .Q(app_rd_data[220]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[221] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [221]),
        .Q(app_rd_data[221]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[222] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [222]),
        .Q(app_rd_data[222]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[223] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [223]),
        .Q(app_rd_data[223]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[224] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [224]),
        .Q(app_rd_data[224]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[225] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [225]),
        .Q(app_rd_data[225]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[226] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [226]),
        .Q(app_rd_data[226]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[227] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [227]),
        .Q(app_rd_data[227]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[228] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [228]),
        .Q(app_rd_data[228]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[229] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [229]),
        .Q(app_rd_data[229]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [22]),
        .Q(app_rd_data[22]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[230] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [230]),
        .Q(app_rd_data[230]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[231] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [231]),
        .Q(app_rd_data[231]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[232] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [232]),
        .Q(app_rd_data[232]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[233] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [233]),
        .Q(app_rd_data[233]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[234] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [234]),
        .Q(app_rd_data[234]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[235] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [235]),
        .Q(app_rd_data[235]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[236] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [236]),
        .Q(app_rd_data[236]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[237] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [237]),
        .Q(app_rd_data[237]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[238] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [238]),
        .Q(app_rd_data[238]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[239] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [239]),
        .Q(app_rd_data[239]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [23]),
        .Q(app_rd_data[23]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[240] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [240]),
        .Q(app_rd_data[240]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[241] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [241]),
        .Q(app_rd_data[241]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[242] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [242]),
        .Q(app_rd_data[242]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[243] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [243]),
        .Q(app_rd_data[243]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[244] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [244]),
        .Q(app_rd_data[244]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[245] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [245]),
        .Q(app_rd_data[245]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[246] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [246]),
        .Q(app_rd_data[246]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[247] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [247]),
        .Q(app_rd_data[247]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[248] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [248]),
        .Q(app_rd_data[248]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[249] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [249]),
        .Q(app_rd_data[249]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [24]),
        .Q(app_rd_data[24]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[250] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [250]),
        .Q(app_rd_data[250]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[251] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [251]),
        .Q(app_rd_data[251]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[252] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [252]),
        .Q(app_rd_data[252]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[253] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [253]),
        .Q(app_rd_data[253]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[254] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [254]),
        .Q(app_rd_data[254]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[255] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [255]),
        .Q(app_rd_data[255]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[256] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [256]),
        .Q(app_rd_data[256]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[257] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [257]),
        .Q(app_rd_data[257]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[258] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [258]),
        .Q(app_rd_data[258]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[259] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [259]),
        .Q(app_rd_data[259]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [25]),
        .Q(app_rd_data[25]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[260] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [260]),
        .Q(app_rd_data[260]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[261] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [261]),
        .Q(app_rd_data[261]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[262] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [262]),
        .Q(app_rd_data[262]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[263] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [263]),
        .Q(app_rd_data[263]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[264] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [264]),
        .Q(app_rd_data[264]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[265] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [265]),
        .Q(app_rd_data[265]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[266] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [266]),
        .Q(app_rd_data[266]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[267] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [267]),
        .Q(app_rd_data[267]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[268] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [268]),
        .Q(app_rd_data[268]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[269] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [269]),
        .Q(app_rd_data[269]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [26]),
        .Q(app_rd_data[26]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[270] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [270]),
        .Q(app_rd_data[270]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[271] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [271]),
        .Q(app_rd_data[271]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[272] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [272]),
        .Q(app_rd_data[272]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[273] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [273]),
        .Q(app_rd_data[273]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[274] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [274]),
        .Q(app_rd_data[274]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[275] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [275]),
        .Q(app_rd_data[275]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[276] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [276]),
        .Q(app_rd_data[276]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[277] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [277]),
        .Q(app_rd_data[277]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[278] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [278]),
        .Q(app_rd_data[278]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[279] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [279]),
        .Q(app_rd_data[279]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [27]),
        .Q(app_rd_data[27]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[280] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [280]),
        .Q(app_rd_data[280]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[281] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [281]),
        .Q(app_rd_data[281]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[282] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [282]),
        .Q(app_rd_data[282]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[283] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [283]),
        .Q(app_rd_data[283]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[284] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [284]),
        .Q(app_rd_data[284]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[285] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [285]),
        .Q(app_rd_data[285]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[286] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [286]),
        .Q(app_rd_data[286]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[287] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [287]),
        .Q(app_rd_data[287]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[288] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [288]),
        .Q(app_rd_data[288]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[289] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [289]),
        .Q(app_rd_data[289]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [28]),
        .Q(app_rd_data[28]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[290] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [290]),
        .Q(app_rd_data[290]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[291] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [291]),
        .Q(app_rd_data[291]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[292] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [292]),
        .Q(app_rd_data[292]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[293] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [293]),
        .Q(app_rd_data[293]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[294] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [294]),
        .Q(app_rd_data[294]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[295] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [295]),
        .Q(app_rd_data[295]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[296] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [296]),
        .Q(app_rd_data[296]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[297] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [297]),
        .Q(app_rd_data[297]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[298] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [298]),
        .Q(app_rd_data[298]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[299] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [299]),
        .Q(app_rd_data[299]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [29]),
        .Q(app_rd_data[29]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [2]),
        .Q(app_rd_data[2]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[300] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [300]),
        .Q(app_rd_data[300]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[301] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [301]),
        .Q(app_rd_data[301]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[302] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [302]),
        .Q(app_rd_data[302]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[303] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [303]),
        .Q(app_rd_data[303]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[304] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [304]),
        .Q(app_rd_data[304]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[305] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [305]),
        .Q(app_rd_data[305]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[306] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [306]),
        .Q(app_rd_data[306]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[307] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [307]),
        .Q(app_rd_data[307]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[308] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [308]),
        .Q(app_rd_data[308]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[309] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [309]),
        .Q(app_rd_data[309]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [30]),
        .Q(app_rd_data[30]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[310] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [310]),
        .Q(app_rd_data[310]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[311] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [311]),
        .Q(app_rd_data[311]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[312] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [312]),
        .Q(app_rd_data[312]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[313] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [313]),
        .Q(app_rd_data[313]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[314] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [314]),
        .Q(app_rd_data[314]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[315] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [315]),
        .Q(app_rd_data[315]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[316] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [316]),
        .Q(app_rd_data[316]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[317] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [317]),
        .Q(app_rd_data[317]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[318] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [318]),
        .Q(app_rd_data[318]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[319] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [319]),
        .Q(app_rd_data[319]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [31]),
        .Q(app_rd_data[31]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[320] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [320]),
        .Q(app_rd_data[320]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[321] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [321]),
        .Q(app_rd_data[321]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[322] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [322]),
        .Q(app_rd_data[322]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[323] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [323]),
        .Q(app_rd_data[323]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[324] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [324]),
        .Q(app_rd_data[324]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[325] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [325]),
        .Q(app_rd_data[325]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[326] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [326]),
        .Q(app_rd_data[326]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[327] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [327]),
        .Q(app_rd_data[327]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[328] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [328]),
        .Q(app_rd_data[328]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[329] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [329]),
        .Q(app_rd_data[329]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [32]),
        .Q(app_rd_data[32]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[330] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [330]),
        .Q(app_rd_data[330]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[331] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [331]),
        .Q(app_rd_data[331]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[332] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [332]),
        .Q(app_rd_data[332]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[333] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [333]),
        .Q(app_rd_data[333]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[334] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [334]),
        .Q(app_rd_data[334]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[335] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [335]),
        .Q(app_rd_data[335]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[336] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [336]),
        .Q(app_rd_data[336]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[337] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [337]),
        .Q(app_rd_data[337]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[338] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [338]),
        .Q(app_rd_data[338]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[339] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [339]),
        .Q(app_rd_data[339]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [33]),
        .Q(app_rd_data[33]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[340] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [340]),
        .Q(app_rd_data[340]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[341] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [341]),
        .Q(app_rd_data[341]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[342] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [342]),
        .Q(app_rd_data[342]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[343] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [343]),
        .Q(app_rd_data[343]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[344] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [344]),
        .Q(app_rd_data[344]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[345] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [345]),
        .Q(app_rd_data[345]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[346] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [346]),
        .Q(app_rd_data[346]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[347] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [347]),
        .Q(app_rd_data[347]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[348] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [348]),
        .Q(app_rd_data[348]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[349] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [349]),
        .Q(app_rd_data[349]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [34]),
        .Q(app_rd_data[34]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[350] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [350]),
        .Q(app_rd_data[350]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[351] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [351]),
        .Q(app_rd_data[351]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[352] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [352]),
        .Q(app_rd_data[352]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[353] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [353]),
        .Q(app_rd_data[353]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[354] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [354]),
        .Q(app_rd_data[354]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[355] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [355]),
        .Q(app_rd_data[355]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[356] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [356]),
        .Q(app_rd_data[356]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[357] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [357]),
        .Q(app_rd_data[357]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[358] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [358]),
        .Q(app_rd_data[358]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[359] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [359]),
        .Q(app_rd_data[359]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [35]),
        .Q(app_rd_data[35]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[360] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [360]),
        .Q(app_rd_data[360]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[361] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [361]),
        .Q(app_rd_data[361]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[362] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [362]),
        .Q(app_rd_data[362]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[363] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [363]),
        .Q(app_rd_data[363]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[364] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [364]),
        .Q(app_rd_data[364]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[365] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [365]),
        .Q(app_rd_data[365]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[366] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [366]),
        .Q(app_rd_data[366]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[367] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [367]),
        .Q(app_rd_data[367]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[368] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [368]),
        .Q(app_rd_data[368]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[369] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [369]),
        .Q(app_rd_data[369]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [36]),
        .Q(app_rd_data[36]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[370] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [370]),
        .Q(app_rd_data[370]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[371] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [371]),
        .Q(app_rd_data[371]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[372] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [372]),
        .Q(app_rd_data[372]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[373] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [373]),
        .Q(app_rd_data[373]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[374] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [374]),
        .Q(app_rd_data[374]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[375] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [375]),
        .Q(app_rd_data[375]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[376] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [376]),
        .Q(app_rd_data[376]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[377] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [377]),
        .Q(app_rd_data[377]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[378] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [378]),
        .Q(app_rd_data[378]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[379] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [379]),
        .Q(app_rd_data[379]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [37]),
        .Q(app_rd_data[37]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[380] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [380]),
        .Q(app_rd_data[380]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[381] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [381]),
        .Q(app_rd_data[381]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[382] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [382]),
        .Q(app_rd_data[382]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[383] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [383]),
        .Q(app_rd_data[383]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[384] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [384]),
        .Q(app_rd_data[384]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[385] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [385]),
        .Q(app_rd_data[385]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[386] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [386]),
        .Q(app_rd_data[386]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[387] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [387]),
        .Q(app_rd_data[387]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[388] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [388]),
        .Q(app_rd_data[388]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[389] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [389]),
        .Q(app_rd_data[389]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [38]),
        .Q(app_rd_data[38]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[390] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [390]),
        .Q(app_rd_data[390]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[391] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [391]),
        .Q(app_rd_data[391]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[392] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [392]),
        .Q(app_rd_data[392]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[393] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [393]),
        .Q(app_rd_data[393]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[394] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [394]),
        .Q(app_rd_data[394]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[395] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [395]),
        .Q(app_rd_data[395]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[396] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [396]),
        .Q(app_rd_data[396]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[397] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [397]),
        .Q(app_rd_data[397]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[398] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [398]),
        .Q(app_rd_data[398]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[399] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [399]),
        .Q(app_rd_data[399]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [39]),
        .Q(app_rd_data[39]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [3]),
        .Q(app_rd_data[3]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[400] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [400]),
        .Q(app_rd_data[400]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[401] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [401]),
        .Q(app_rd_data[401]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[402] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [402]),
        .Q(app_rd_data[402]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[403] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [403]),
        .Q(app_rd_data[403]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[404] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [404]),
        .Q(app_rd_data[404]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[405] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [405]),
        .Q(app_rd_data[405]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[406] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [406]),
        .Q(app_rd_data[406]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[407] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [407]),
        .Q(app_rd_data[407]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[408] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [408]),
        .Q(app_rd_data[408]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[409] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [409]),
        .Q(app_rd_data[409]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [40]),
        .Q(app_rd_data[40]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[410] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [410]),
        .Q(app_rd_data[410]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[411] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [411]),
        .Q(app_rd_data[411]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[412] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [412]),
        .Q(app_rd_data[412]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[413] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [413]),
        .Q(app_rd_data[413]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[414] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [414]),
        .Q(app_rd_data[414]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[415] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [415]),
        .Q(app_rd_data[415]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[416] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [416]),
        .Q(app_rd_data[416]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[417] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [417]),
        .Q(app_rd_data[417]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[418] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [418]),
        .Q(app_rd_data[418]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[419] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [419]),
        .Q(app_rd_data[419]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [41]),
        .Q(app_rd_data[41]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[420] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [420]),
        .Q(app_rd_data[420]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[421] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [421]),
        .Q(app_rd_data[421]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[422] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [422]),
        .Q(app_rd_data[422]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[423] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [423]),
        .Q(app_rd_data[423]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[424] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [424]),
        .Q(app_rd_data[424]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[425] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [425]),
        .Q(app_rd_data[425]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[426] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [426]),
        .Q(app_rd_data[426]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[427] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [427]),
        .Q(app_rd_data[427]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[428] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [428]),
        .Q(app_rd_data[428]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[429] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [429]),
        .Q(app_rd_data[429]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [42]),
        .Q(app_rd_data[42]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[430] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [430]),
        .Q(app_rd_data[430]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[431] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [431]),
        .Q(app_rd_data[431]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[432] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [432]),
        .Q(app_rd_data[432]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[433] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [433]),
        .Q(app_rd_data[433]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[434] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [434]),
        .Q(app_rd_data[434]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[435] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [435]),
        .Q(app_rd_data[435]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[436] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [436]),
        .Q(app_rd_data[436]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[437] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [437]),
        .Q(app_rd_data[437]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[438] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [438]),
        .Q(app_rd_data[438]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[439] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [439]),
        .Q(app_rd_data[439]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [43]),
        .Q(app_rd_data[43]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[440] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [440]),
        .Q(app_rd_data[440]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[441] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [441]),
        .Q(app_rd_data[441]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[442] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [442]),
        .Q(app_rd_data[442]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[443] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [443]),
        .Q(app_rd_data[443]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[444] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [444]),
        .Q(app_rd_data[444]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[445] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [445]),
        .Q(app_rd_data[445]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[446] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [446]),
        .Q(app_rd_data[446]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[447] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [447]),
        .Q(app_rd_data[447]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[448] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [448]),
        .Q(app_rd_data[448]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[449] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [449]),
        .Q(app_rd_data[449]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [44]),
        .Q(app_rd_data[44]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[450] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [450]),
        .Q(app_rd_data[450]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[451] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [451]),
        .Q(app_rd_data[451]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[452] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [452]),
        .Q(app_rd_data[452]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[453] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [453]),
        .Q(app_rd_data[453]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[454] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [454]),
        .Q(app_rd_data[454]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[455] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [455]),
        .Q(app_rd_data[455]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[456] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [456]),
        .Q(app_rd_data[456]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[457] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [457]),
        .Q(app_rd_data[457]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[458] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [458]),
        .Q(app_rd_data[458]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[459] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [459]),
        .Q(app_rd_data[459]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [45]),
        .Q(app_rd_data[45]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[460] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [460]),
        .Q(app_rd_data[460]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[461] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [461]),
        .Q(app_rd_data[461]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[462] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [462]),
        .Q(app_rd_data[462]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[463] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [463]),
        .Q(app_rd_data[463]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[464] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [464]),
        .Q(app_rd_data[464]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[465] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [465]),
        .Q(app_rd_data[465]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[466] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [466]),
        .Q(app_rd_data[466]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[467] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [467]),
        .Q(app_rd_data[467]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[468] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [468]),
        .Q(app_rd_data[468]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[469] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [469]),
        .Q(app_rd_data[469]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [46]),
        .Q(app_rd_data[46]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[470] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [470]),
        .Q(app_rd_data[470]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[471] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [471]),
        .Q(app_rd_data[471]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[472] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [472]),
        .Q(app_rd_data[472]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[473] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [473]),
        .Q(app_rd_data[473]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[474] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [474]),
        .Q(app_rd_data[474]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[475] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [475]),
        .Q(app_rd_data[475]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[476] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [476]),
        .Q(app_rd_data[476]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[477] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [477]),
        .Q(app_rd_data[477]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[478] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [478]),
        .Q(app_rd_data[478]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[479] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [479]),
        .Q(app_rd_data[479]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [47]),
        .Q(app_rd_data[47]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[480] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [480]),
        .Q(app_rd_data[480]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[481] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [481]),
        .Q(app_rd_data[481]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[482] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [482]),
        .Q(app_rd_data[482]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[483] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [483]),
        .Q(app_rd_data[483]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[484] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [484]),
        .Q(app_rd_data[484]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[485] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [485]),
        .Q(app_rd_data[485]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[486] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [486]),
        .Q(app_rd_data[486]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[487] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [487]),
        .Q(app_rd_data[487]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[488] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [488]),
        .Q(app_rd_data[488]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[489] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [489]),
        .Q(app_rd_data[489]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [48]),
        .Q(app_rd_data[48]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[490] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [490]),
        .Q(app_rd_data[490]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[491] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [491]),
        .Q(app_rd_data[491]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[492] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [492]),
        .Q(app_rd_data[492]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[493] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [493]),
        .Q(app_rd_data[493]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[494] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [494]),
        .Q(app_rd_data[494]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[495] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [495]),
        .Q(app_rd_data[495]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[496] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [496]),
        .Q(app_rd_data[496]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[497] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [497]),
        .Q(app_rd_data[497]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[498] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [498]),
        .Q(app_rd_data[498]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[499] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [499]),
        .Q(app_rd_data[499]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [49]),
        .Q(app_rd_data[49]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [4]),
        .Q(app_rd_data[4]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[500] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [500]),
        .Q(app_rd_data[500]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[501] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [501]),
        .Q(app_rd_data[501]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[502] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [502]),
        .Q(app_rd_data[502]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[503] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [503]),
        .Q(app_rd_data[503]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[504] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [504]),
        .Q(app_rd_data[504]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[505] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [505]),
        .Q(app_rd_data[505]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[506] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [506]),
        .Q(app_rd_data[506]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[507] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [507]),
        .Q(app_rd_data[507]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[508] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [508]),
        .Q(app_rd_data[508]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[509] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [509]),
        .Q(app_rd_data[509]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [50]),
        .Q(app_rd_data[50]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[510] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [510]),
        .Q(app_rd_data[510]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[511] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [511]),
        .Q(app_rd_data[511]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [51]),
        .Q(app_rd_data[51]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [52]),
        .Q(app_rd_data[52]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [53]),
        .Q(app_rd_data[53]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [54]),
        .Q(app_rd_data[54]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [55]),
        .Q(app_rd_data[55]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [56]),
        .Q(app_rd_data[56]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [57]),
        .Q(app_rd_data[57]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [58]),
        .Q(app_rd_data[58]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [59]),
        .Q(app_rd_data[59]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [5]),
        .Q(app_rd_data[5]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [60]),
        .Q(app_rd_data[60]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [61]),
        .Q(app_rd_data[61]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [62]),
        .Q(app_rd_data[62]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [63]),
        .Q(app_rd_data[63]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [64]),
        .Q(app_rd_data[64]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [65]),
        .Q(app_rd_data[65]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [66]),
        .Q(app_rd_data[66]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [67]),
        .Q(app_rd_data[67]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [68]),
        .Q(app_rd_data[68]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [69]),
        .Q(app_rd_data[69]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [6]),
        .Q(app_rd_data[6]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [70]),
        .Q(app_rd_data[70]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [71]),
        .Q(app_rd_data[71]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[72] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [72]),
        .Q(app_rd_data[72]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[73] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [73]),
        .Q(app_rd_data[73]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[74] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [74]),
        .Q(app_rd_data[74]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[75] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [75]),
        .Q(app_rd_data[75]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[76] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [76]),
        .Q(app_rd_data[76]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[77] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [77]),
        .Q(app_rd_data[77]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[78] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [78]),
        .Q(app_rd_data[78]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[79] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [79]),
        .Q(app_rd_data[79]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [7]),
        .Q(app_rd_data[7]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[80] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [80]),
        .Q(app_rd_data[80]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[81] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [81]),
        .Q(app_rd_data[81]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[82] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [82]),
        .Q(app_rd_data[82]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[83] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [83]),
        .Q(app_rd_data[83]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[84] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [84]),
        .Q(app_rd_data[84]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[85] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [85]),
        .Q(app_rd_data[85]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[86] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [86]),
        .Q(app_rd_data[86]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[87] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [87]),
        .Q(app_rd_data[87]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[88] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [88]),
        .Q(app_rd_data[88]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[89] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [89]),
        .Q(app_rd_data[89]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [8]),
        .Q(app_rd_data[8]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[90] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [90]),
        .Q(app_rd_data[90]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[91] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [91]),
        .Q(app_rd_data[91]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[92] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [92]),
        .Q(app_rd_data[92]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[93] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [93]),
        .Q(app_rd_data[93]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[94] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [94]),
        .Q(app_rd_data[94]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[95] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [95]),
        .Q(app_rd_data[95]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[96] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [96]),
        .Q(app_rd_data[96]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[97] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [97]),
        .Q(app_rd_data[97]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[98] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [98]),
        .Q(app_rd_data[98]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[99] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [99]),
        .Q(app_rd_data[99]),
        .R(1'b0));
  FDRE \not_strict_mode.app_rd_data_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 [9]),
        .Q(app_rd_data[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT4 #(
    .INIT(16'hF900)) 
    \not_strict_mode.app_rd_data_valid_i_1 
       (.I0(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),
        .I1(\not_strict_mode.status_ram.RAM32M0_n_1 ),
        .I2(\read_fifo.fifo_out_data_r_reg[4] ),
        .I3(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .O(\not_strict_mode.app_rd_data_valid_i_1_n_0 ));
  FDRE \not_strict_mode.app_rd_data_valid_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\not_strict_mode.app_rd_data_valid_i_1_n_0 ),
        .Q(app_rd_data_valid),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[1]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[2]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[3]_i_1 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(p_0_in__2[3]));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_2 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(p_0_in__2[4]));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[0] 
       (.C(CLK),
        .CE(rd_accepted),
        .D(p_0_in__2[0]),
        .Q(Q[0]),
        .R(reset_reg));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[1] 
       (.C(CLK),
        .CE(rd_accepted),
        .D(p_0_in__2[1]),
        .Q(Q[1]),
        .R(reset_reg));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[2] 
       (.C(CLK),
        .CE(rd_accepted),
        .D(p_0_in__2[2]),
        .Q(Q[2]),
        .R(reset_reg));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[3] 
       (.C(CLK),
        .CE(rd_accepted),
        .D(p_0_in__2[3]),
        .Q(Q[3]),
        .R(reset_reg));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] 
       (.C(CLK),
        .CE(rd_accepted),
        .D(p_0_in__2[4]),
        .Q(Q[4]),
        .R(reset_reg));
  LUT4 #(
    .INIT(16'h8778)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1 
       (.I0(app_rd_data_end),
        .I1(app_rd_data_valid),
        .I2(rd_accepted),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000A96A6A6A)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),
        .I2(rd_accepted),
        .I3(app_rd_data_end),
        .I4(app_rd_data_valid),
        .I5(reset_reg),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [2]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ),
        .I2(reset_reg),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h06)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1 
       (.I0(occ_cnt_r[4]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_2_n_0 ),
        .I2(reset_reg),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h78787800)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_2 
       (.I0(app_rd_data_valid),
        .I1(app_rd_data_end),
        .I2(rd_accepted),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),
        .I4(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_1 
       (.I0(occ_cnt_r[5]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ),
        .I2(reset_reg),
        .O(D));
  LUT6 #(
    .INIT(64'h3CCC288800002888)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),
        .I1(rd_accepted),
        .I2(app_rd_data_end),
        .I3(app_rd_data_valid),
        .I4(occ_cnt_r[4]),
        .I5(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3 
       (.I0(rd_accepted),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [3]),
        .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [2]),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),
        .I4(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000800)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [3]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [2]),
        .I2(\app_cmd_r2_reg[1] ),
        .I3(app_cmd_r2),
        .I4(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_5_n_0 ),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_5 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),
        .I2(app_en_r2),
        .I3(app_rdy_r_reg),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_5_n_0 ));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),
        .R(reset_reg));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\not_strict_mode.occupied_counter.occ_cnt_r_reg[2]_0 ),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ),
        .Q(occ_cnt_r[4]),
        .R(1'b0));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(D),
        .Q(occ_cnt_r[5]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0 ),
        .Q(rd_buf_indx_copy_r[0]),
        .R(reset_reg));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0 ),
        .Q(rd_buf_indx_copy_r[1]),
        .R(reset_reg));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0 ),
        .Q(rd_buf_indx_copy_r[2]),
        .R(reset_reg));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0 ),
        .Q(rd_buf_indx_copy_r[3]),
        .R(reset_reg));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ),
        .Q(rd_buf_indx_copy_r[4]),
        .R(reset_reg));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .DID({1'b0,1'b0}),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[65]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[63]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[61]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[71]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[69]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[67]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[77]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[75]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[73]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[83]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[81]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[79]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[89]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[87]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[85]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[95]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[93]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[91]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[101]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[99]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[97]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[107]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[105]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[103]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[113]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[111]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[109]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[119]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[117]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[115]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[11]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[9]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[7]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[125]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[123]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[121]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[131]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[129]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[127]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[137]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[135]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[133]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[143]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[141]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[139]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[149]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[147]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[145]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[155]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[153]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[151]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[161]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[159]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[157]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[167]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[165]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[163]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[173]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[171]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[169]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[179]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[177]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[175]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[17]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[15]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[13]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[185]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[183]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[181]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[191]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[189]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[187]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[197]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[195]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[193]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[203]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[201]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[199]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[209]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[207]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[205]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[215]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[213]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[211]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[221]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[219]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[217]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[227]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[225]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[223]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[233]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[231]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[229]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[239]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[237]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[235]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[23]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[21]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[19]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[245]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[243]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[241]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[251]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[249]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[247]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[257]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[255]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[253]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[263]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[261]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[259]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[269]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[267]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[265]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[275]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[273]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[271]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[281]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[279]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[277]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[287]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[285]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[283]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[293]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[291]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[289]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[299]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[297]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[295]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[29]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[27]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[25]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[305]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[303]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[301]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[311]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[309]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[307]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[317]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[315]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[313]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[323]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[321]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[319]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[329]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[327]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[325]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[335]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[333]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[331]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[341]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[339]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[337]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[347]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[345]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[343]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[353]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[351]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[349]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[359]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[357]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[355]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[35]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[33]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[31]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[365]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[363]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[361]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[371]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[369]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[367]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[377]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[375]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[373]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[383]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[381]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[379]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[389]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[387]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[385]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[395]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[393]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[391]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[401]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[399]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[397]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[407]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[405]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[403]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[413]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[411]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[409]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[419]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[417]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[415]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[41]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[39]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[37]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[425]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[423]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[421]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[431]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[429]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[427]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[437]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[435]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[433]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[443]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[441]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[439]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[449]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[447]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[445]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[455]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[453]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[451]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[461]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[459]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[457]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[467]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[465]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[463]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[473]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[471]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[469]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[479]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[477]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[475]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[47]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[45]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[43]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[485]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[483]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[481]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[491]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[489]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[487]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[497]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[495]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[493]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[503]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[501]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[499]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[509]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[507]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[505]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOB_UNCONNECTED [1:0]),
        .DOC(\not_strict_mode.app_rd_data_reg[511]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[53]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[51]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[49]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 
       (.ADDRA(rd_buf_indx_copy_r),
        .ADDRB(rd_buf_indx_copy_r),
        .ADDRC(rd_buf_indx_copy_r),
        .ADDRD(\read_fifo.fifo_out_data_r_reg[7] [5:1]),
        .DIA(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .DIB(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .DIC(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.app_rd_data_reg[59]_0 ),
        .DOB(\not_strict_mode.app_rd_data_reg[57]_0 ),
        .DOC(\not_strict_mode.app_rd_data_reg[55]_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.status_ram.RAM32M0 
       (.ADDRA({rd_buf_indx_r,ADDRA,ram_init_addr}),
        .ADDRB({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRC(status_ram_wr_addr_ns),
        .ADDRD(status_ram_wr_addr_r),
        .DIA(status_ram_wr_data_r),
        .DIB({1'b0,1'b0}),
        .DIC(status_ram_wr_data_r),
        .DID(status_ram_wr_data_r),
        .DOA({\not_strict_mode.app_rd_data_end_reg_0 ,\not_strict_mode.status_ram.RAM32M0_n_1 }),
        .DOB(\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED [1:0]),
        .DOC({\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED [1],\not_strict_mode.status_ram.RAM32M0_n_5 }),
        .DOD(\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(rd_buf_we_r1));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram.RAM32M0_i_1 
       (.I0(\read_fifo.fifo_out_data_r_reg[7] [5]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(rd_buf_indx_r),
        .O(status_ram_wr_addr_ns[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram.RAM32M0_i_2 
       (.I0(\read_fifo.fifo_out_data_r_reg[7] [4]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ADDRA),
        .O(status_ram_wr_addr_ns[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram.RAM32M0_i_3 
       (.I0(\read_fifo.fifo_out_data_r_reg[7] [3]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[2]),
        .O(status_ram_wr_addr_ns[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram.RAM32M0_i_4 
       (.I0(\read_fifo.fifo_out_data_r_reg[7] [2]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[1]),
        .O(status_ram_wr_addr_ns[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram.RAM32M0_i_5 
       (.I0(\read_fifo.fifo_out_data_r_reg[7] [1]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[0]),
        .O(status_ram_wr_addr_ns[0]));
  FDRE \not_strict_mode.status_ram.rd_buf_we_r1_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_buf_we),
        .Q(rd_buf_we_r1),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(status_ram_wr_addr_ns[0]),
        .Q(status_ram_wr_addr_r[0]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(status_ram_wr_addr_ns[1]),
        .Q(status_ram_wr_addr_r[1]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(status_ram_wr_addr_ns[2]),
        .Q(status_ram_wr_addr_r[2]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(status_ram_wr_addr_ns[3]),
        .Q(status_ram_wr_addr_r[3]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(status_ram_wr_addr_ns[4]),
        .Q(status_ram_wr_addr_r[4]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h02A2)) 
    \not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1 
       (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I1(\not_strict_mode.status_ram.RAM32M0_n_5 ),
        .I2(\read_fifo.fifo_out_data_r_reg[7] [0]),
        .I3(wr_status_r1),
        .O(status_ram_wr_data_ns[0]));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \not_strict_mode.status_ram.status_ram_wr_data_r[1]_i_1 
       (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I1(\read_fifo.fifo_out_data_r_reg[7] [6]),
        .O(status_ram_wr_data_ns[1]));
  FDRE \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(status_ram_wr_data_ns[0]),
        .Q(status_ram_wr_data_r[0]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(status_ram_wr_data_ns[1]),
        .Q(status_ram_wr_data_r[1]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram.wr_status_r1_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram.RAM32M0_n_5 ),
        .Q(wr_status_r1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_2 
       (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [1]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[1]),
        .O(pointer_wr_data[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_3 
       (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [0]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[0]),
        .O(pointer_wr_data[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_4 
       (.I0(\read_data_indx.rd_data_indx_r_reg[3] [3]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ADDRA),
        .O(ADDRD[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_5 
       (.I0(\read_data_indx.rd_data_indx_r_reg[3] [2]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[2]),
        .O(ADDRD[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_6 
       (.I0(\read_data_indx.rd_data_indx_r_reg[3] [1]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[1]),
        .O(ADDRD[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_7 
       (.I0(\read_data_indx.rd_data_indx_r_reg[3] [0]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[0]),
        .O(ADDRD[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[1].RAM32M0_i_1 
       (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [3]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ADDRA),
        .O(pointer_wr_data[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[1].RAM32M0_i_2 
       (.I0(\cmd_pipe_plus.wr_data_addr_reg[3] [2]),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(ram_init_addr[2]),
        .O(pointer_wr_data[2]));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \rd_buf_indx.ram_init_done_r_lcl_i_1 
       (.I0(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I1(ADDRA),
        .I2(ram_init_addr[2]),
        .I3(rd_buf_indx_r),
        .I4(ram_init_addr[1]),
        .I5(ram_init_addr[0]),
        .O(\rd_buf_indx.ram_init_done_r_lcl_i_1_n_0 ));
  FDRE \rd_buf_indx.ram_init_done_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.ram_init_done_r_lcl_i_1_n_0 ),
        .Q(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .R(reset_reg));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT5 #(
    .INIT(32'h55556955)) 
    \rd_buf_indx.rd_buf_indx_r[0]_i_1 
       (.I0(ram_init_addr[0]),
        .I1(\not_strict_mode.status_ram.RAM32M0_n_1 ),
        .I2(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),
        .I3(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I4(\read_fifo.fifo_out_data_r_reg[4] ),
        .O(\rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h55656555AAAAAAAA)) 
    \rd_buf_indx.rd_buf_indx_r[1]_i_1 
       (.I0(ram_init_addr[1]),
        .I1(\read_fifo.fifo_out_data_r_reg[4] ),
        .I2(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I3(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),
        .I4(\not_strict_mode.status_ram.RAM32M0_n_1 ),
        .I5(ram_init_addr[0]),
        .O(\rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_buf_indx.rd_buf_indx_r[2]_i_1 
       (.I0(ram_init_addr[2]),
        .I1(ram_init_addr[1]),
        .I2(ram_init_addr[0]),
        .I3(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),
        .O(\rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT5 #(
    .INIT(32'hAAAA6AAA)) 
    \rd_buf_indx.rd_buf_indx_r[3]_i_1 
       (.I0(ADDRA),
        .I1(ram_init_addr[0]),
        .I2(ram_init_addr[1]),
        .I3(ram_init_addr[2]),
        .I4(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),
        .O(\rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA6AAAAAAA)) 
    \rd_buf_indx.rd_buf_indx_r[4]_i_1 
       (.I0(rd_buf_indx_r),
        .I1(ram_init_addr[0]),
        .I2(ram_init_addr[1]),
        .I3(ADDRA),
        .I4(ram_init_addr[2]),
        .I5(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),
        .O(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA9AAAAAAAAAAAAAA)) 
    \rd_buf_indx.rd_buf_indx_r[5]_i_1 
       (.I0(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),
        .I1(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),
        .I2(\rd_buf_indx.rd_buf_indx_r[5]_i_3_n_0 ),
        .I3(rd_buf_indx_r),
        .I4(ram_init_addr[2]),
        .I5(ADDRA),
        .O(\rd_buf_indx.rd_buf_indx_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT4 #(
    .INIT(16'h0440)) 
    \rd_buf_indx.rd_buf_indx_r[5]_i_2 
       (.I0(\read_fifo.fifo_out_data_r_reg[4] ),
        .I1(\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),
        .I2(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),
        .I3(\not_strict_mode.status_ram.RAM32M0_n_1 ),
        .O(\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \rd_buf_indx.rd_buf_indx_r[5]_i_3 
       (.I0(ram_init_addr[1]),
        .I1(ram_init_addr[0]),
        .O(\rd_buf_indx.rd_buf_indx_r[5]_i_3_n_0 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0 ),
        .Q(ram_init_addr[0]),
        .R(reset_reg));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0 ),
        .Q(ram_init_addr[1]),
        .R(reset_reg));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0 ),
        .Q(ram_init_addr[2]),
        .R(reset_reg));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0 ),
        .Q(ADDRA),
        .R(reset_reg));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ),
        .Q(rd_buf_indx_r),
        .R(reset_reg));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.rd_buf_indx_r[5]_i_1_n_0 ),
        .Q(\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),
        .R(reset_reg));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ui_top" *) 
module mig_7series_0_mig_7series_v2_3_ui_top
   (\not_strict_mode.app_rd_data_end_reg ,
    \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] ,
    DOA,
    DOB,
    DOC,
    \not_strict_mode.app_rd_data_reg[11] ,
    \not_strict_mode.app_rd_data_reg[9] ,
    \not_strict_mode.app_rd_data_reg[7] ,
    \not_strict_mode.app_rd_data_reg[17] ,
    \not_strict_mode.app_rd_data_reg[15] ,
    \not_strict_mode.app_rd_data_reg[13] ,
    \not_strict_mode.app_rd_data_reg[23] ,
    \not_strict_mode.app_rd_data_reg[21] ,
    \not_strict_mode.app_rd_data_reg[19] ,
    \not_strict_mode.app_rd_data_reg[29] ,
    \not_strict_mode.app_rd_data_reg[27] ,
    \not_strict_mode.app_rd_data_reg[25] ,
    \not_strict_mode.app_rd_data_reg[35] ,
    \not_strict_mode.app_rd_data_reg[33] ,
    \not_strict_mode.app_rd_data_reg[31] ,
    \not_strict_mode.app_rd_data_reg[41] ,
    \not_strict_mode.app_rd_data_reg[39] ,
    \not_strict_mode.app_rd_data_reg[37] ,
    \not_strict_mode.app_rd_data_reg[47] ,
    \not_strict_mode.app_rd_data_reg[45] ,
    \not_strict_mode.app_rd_data_reg[43] ,
    \not_strict_mode.app_rd_data_reg[53] ,
    \not_strict_mode.app_rd_data_reg[51] ,
    \not_strict_mode.app_rd_data_reg[49] ,
    \not_strict_mode.app_rd_data_reg[59] ,
    \not_strict_mode.app_rd_data_reg[57] ,
    \not_strict_mode.app_rd_data_reg[55] ,
    \not_strict_mode.app_rd_data_reg[65] ,
    \not_strict_mode.app_rd_data_reg[63] ,
    \not_strict_mode.app_rd_data_reg[61] ,
    \not_strict_mode.app_rd_data_reg[71] ,
    \not_strict_mode.app_rd_data_reg[69] ,
    \not_strict_mode.app_rd_data_reg[67] ,
    \not_strict_mode.app_rd_data_reg[77] ,
    \not_strict_mode.app_rd_data_reg[75] ,
    \not_strict_mode.app_rd_data_reg[73] ,
    \not_strict_mode.app_rd_data_reg[83] ,
    \not_strict_mode.app_rd_data_reg[81] ,
    \not_strict_mode.app_rd_data_reg[79] ,
    \not_strict_mode.app_rd_data_reg[89] ,
    \not_strict_mode.app_rd_data_reg[87] ,
    \not_strict_mode.app_rd_data_reg[85] ,
    \not_strict_mode.app_rd_data_reg[95] ,
    \not_strict_mode.app_rd_data_reg[93] ,
    \not_strict_mode.app_rd_data_reg[91] ,
    \not_strict_mode.app_rd_data_reg[101] ,
    \not_strict_mode.app_rd_data_reg[99] ,
    \not_strict_mode.app_rd_data_reg[97] ,
    \not_strict_mode.app_rd_data_reg[107] ,
    \not_strict_mode.app_rd_data_reg[105] ,
    \not_strict_mode.app_rd_data_reg[103] ,
    \not_strict_mode.app_rd_data_reg[113] ,
    \not_strict_mode.app_rd_data_reg[111] ,
    \not_strict_mode.app_rd_data_reg[109] ,
    \not_strict_mode.app_rd_data_reg[119] ,
    \not_strict_mode.app_rd_data_reg[117] ,
    \not_strict_mode.app_rd_data_reg[115] ,
    \not_strict_mode.app_rd_data_reg[125] ,
    \not_strict_mode.app_rd_data_reg[123] ,
    \not_strict_mode.app_rd_data_reg[121] ,
    \not_strict_mode.app_rd_data_reg[131] ,
    \not_strict_mode.app_rd_data_reg[129] ,
    \not_strict_mode.app_rd_data_reg[127] ,
    \not_strict_mode.app_rd_data_reg[137] ,
    \not_strict_mode.app_rd_data_reg[135] ,
    \not_strict_mode.app_rd_data_reg[133] ,
    \not_strict_mode.app_rd_data_reg[143] ,
    \not_strict_mode.app_rd_data_reg[141] ,
    \not_strict_mode.app_rd_data_reg[139] ,
    \not_strict_mode.app_rd_data_reg[149] ,
    \not_strict_mode.app_rd_data_reg[147] ,
    \not_strict_mode.app_rd_data_reg[145] ,
    \not_strict_mode.app_rd_data_reg[155] ,
    \not_strict_mode.app_rd_data_reg[153] ,
    \not_strict_mode.app_rd_data_reg[151] ,
    \not_strict_mode.app_rd_data_reg[161] ,
    \not_strict_mode.app_rd_data_reg[159] ,
    \not_strict_mode.app_rd_data_reg[157] ,
    \not_strict_mode.app_rd_data_reg[167] ,
    \not_strict_mode.app_rd_data_reg[165] ,
    \not_strict_mode.app_rd_data_reg[163] ,
    \not_strict_mode.app_rd_data_reg[173] ,
    \not_strict_mode.app_rd_data_reg[171] ,
    \not_strict_mode.app_rd_data_reg[169] ,
    \not_strict_mode.app_rd_data_reg[179] ,
    \not_strict_mode.app_rd_data_reg[177] ,
    \not_strict_mode.app_rd_data_reg[175] ,
    \not_strict_mode.app_rd_data_reg[185] ,
    \not_strict_mode.app_rd_data_reg[183] ,
    \not_strict_mode.app_rd_data_reg[181] ,
    \not_strict_mode.app_rd_data_reg[191] ,
    \not_strict_mode.app_rd_data_reg[189] ,
    \not_strict_mode.app_rd_data_reg[187] ,
    \not_strict_mode.app_rd_data_reg[197] ,
    \not_strict_mode.app_rd_data_reg[195] ,
    \not_strict_mode.app_rd_data_reg[193] ,
    \not_strict_mode.app_rd_data_reg[203] ,
    \not_strict_mode.app_rd_data_reg[201] ,
    \not_strict_mode.app_rd_data_reg[199] ,
    \not_strict_mode.app_rd_data_reg[209] ,
    \not_strict_mode.app_rd_data_reg[207] ,
    \not_strict_mode.app_rd_data_reg[205] ,
    \not_strict_mode.app_rd_data_reg[215] ,
    \not_strict_mode.app_rd_data_reg[213] ,
    \not_strict_mode.app_rd_data_reg[211] ,
    \not_strict_mode.app_rd_data_reg[221] ,
    \not_strict_mode.app_rd_data_reg[219] ,
    \not_strict_mode.app_rd_data_reg[217] ,
    \not_strict_mode.app_rd_data_reg[227] ,
    \not_strict_mode.app_rd_data_reg[225] ,
    \not_strict_mode.app_rd_data_reg[223] ,
    \not_strict_mode.app_rd_data_reg[233] ,
    \not_strict_mode.app_rd_data_reg[231] ,
    \not_strict_mode.app_rd_data_reg[229] ,
    \not_strict_mode.app_rd_data_reg[239] ,
    \not_strict_mode.app_rd_data_reg[237] ,
    \not_strict_mode.app_rd_data_reg[235] ,
    \not_strict_mode.app_rd_data_reg[245] ,
    \not_strict_mode.app_rd_data_reg[243] ,
    \not_strict_mode.app_rd_data_reg[241] ,
    \not_strict_mode.app_rd_data_reg[251] ,
    \not_strict_mode.app_rd_data_reg[249] ,
    \not_strict_mode.app_rd_data_reg[247] ,
    \not_strict_mode.app_rd_data_reg[257] ,
    \not_strict_mode.app_rd_data_reg[255] ,
    \not_strict_mode.app_rd_data_reg[253] ,
    \not_strict_mode.app_rd_data_reg[263] ,
    \not_strict_mode.app_rd_data_reg[261] ,
    \not_strict_mode.app_rd_data_reg[259] ,
    \not_strict_mode.app_rd_data_reg[269] ,
    \not_strict_mode.app_rd_data_reg[267] ,
    \not_strict_mode.app_rd_data_reg[265] ,
    \not_strict_mode.app_rd_data_reg[275] ,
    \not_strict_mode.app_rd_data_reg[273] ,
    \not_strict_mode.app_rd_data_reg[271] ,
    \not_strict_mode.app_rd_data_reg[281] ,
    \not_strict_mode.app_rd_data_reg[279] ,
    \not_strict_mode.app_rd_data_reg[277] ,
    \not_strict_mode.app_rd_data_reg[287] ,
    \not_strict_mode.app_rd_data_reg[285] ,
    \not_strict_mode.app_rd_data_reg[283] ,
    \not_strict_mode.app_rd_data_reg[293] ,
    \not_strict_mode.app_rd_data_reg[291] ,
    \not_strict_mode.app_rd_data_reg[289] ,
    \not_strict_mode.app_rd_data_reg[299] ,
    \not_strict_mode.app_rd_data_reg[297] ,
    \not_strict_mode.app_rd_data_reg[295] ,
    \not_strict_mode.app_rd_data_reg[305] ,
    \not_strict_mode.app_rd_data_reg[303] ,
    \not_strict_mode.app_rd_data_reg[301] ,
    \not_strict_mode.app_rd_data_reg[311] ,
    \not_strict_mode.app_rd_data_reg[309] ,
    \not_strict_mode.app_rd_data_reg[307] ,
    \not_strict_mode.app_rd_data_reg[317] ,
    \not_strict_mode.app_rd_data_reg[315] ,
    \not_strict_mode.app_rd_data_reg[313] ,
    \not_strict_mode.app_rd_data_reg[323] ,
    \not_strict_mode.app_rd_data_reg[321] ,
    \not_strict_mode.app_rd_data_reg[319] ,
    \not_strict_mode.app_rd_data_reg[329] ,
    \not_strict_mode.app_rd_data_reg[327] ,
    \not_strict_mode.app_rd_data_reg[325] ,
    \not_strict_mode.app_rd_data_reg[335] ,
    \not_strict_mode.app_rd_data_reg[333] ,
    \not_strict_mode.app_rd_data_reg[331] ,
    \not_strict_mode.app_rd_data_reg[341] ,
    \not_strict_mode.app_rd_data_reg[339] ,
    \not_strict_mode.app_rd_data_reg[337] ,
    \not_strict_mode.app_rd_data_reg[347] ,
    \not_strict_mode.app_rd_data_reg[345] ,
    \not_strict_mode.app_rd_data_reg[343] ,
    \not_strict_mode.app_rd_data_reg[353] ,
    \not_strict_mode.app_rd_data_reg[351] ,
    \not_strict_mode.app_rd_data_reg[349] ,
    \not_strict_mode.app_rd_data_reg[359] ,
    \not_strict_mode.app_rd_data_reg[357] ,
    \not_strict_mode.app_rd_data_reg[355] ,
    \not_strict_mode.app_rd_data_reg[365] ,
    \not_strict_mode.app_rd_data_reg[363] ,
    \not_strict_mode.app_rd_data_reg[361] ,
    \not_strict_mode.app_rd_data_reg[371] ,
    \not_strict_mode.app_rd_data_reg[369] ,
    \not_strict_mode.app_rd_data_reg[367] ,
    \not_strict_mode.app_rd_data_reg[377] ,
    \not_strict_mode.app_rd_data_reg[375] ,
    \not_strict_mode.app_rd_data_reg[373] ,
    \not_strict_mode.app_rd_data_reg[383] ,
    \not_strict_mode.app_rd_data_reg[381] ,
    \not_strict_mode.app_rd_data_reg[379] ,
    \not_strict_mode.app_rd_data_reg[389] ,
    \not_strict_mode.app_rd_data_reg[387] ,
    \not_strict_mode.app_rd_data_reg[385] ,
    \not_strict_mode.app_rd_data_reg[395] ,
    \not_strict_mode.app_rd_data_reg[393] ,
    \not_strict_mode.app_rd_data_reg[391] ,
    \not_strict_mode.app_rd_data_reg[401] ,
    \not_strict_mode.app_rd_data_reg[399] ,
    \not_strict_mode.app_rd_data_reg[397] ,
    \not_strict_mode.app_rd_data_reg[407] ,
    \not_strict_mode.app_rd_data_reg[405] ,
    \not_strict_mode.app_rd_data_reg[403] ,
    \not_strict_mode.app_rd_data_reg[413] ,
    \not_strict_mode.app_rd_data_reg[411] ,
    \not_strict_mode.app_rd_data_reg[409] ,
    \not_strict_mode.app_rd_data_reg[419] ,
    \not_strict_mode.app_rd_data_reg[417] ,
    \not_strict_mode.app_rd_data_reg[415] ,
    \not_strict_mode.app_rd_data_reg[425] ,
    \not_strict_mode.app_rd_data_reg[423] ,
    \not_strict_mode.app_rd_data_reg[421] ,
    \not_strict_mode.app_rd_data_reg[431] ,
    \not_strict_mode.app_rd_data_reg[429] ,
    \not_strict_mode.app_rd_data_reg[427] ,
    \not_strict_mode.app_rd_data_reg[437] ,
    \not_strict_mode.app_rd_data_reg[435] ,
    \not_strict_mode.app_rd_data_reg[433] ,
    \not_strict_mode.app_rd_data_reg[443] ,
    \not_strict_mode.app_rd_data_reg[441] ,
    \not_strict_mode.app_rd_data_reg[439] ,
    \not_strict_mode.app_rd_data_reg[449] ,
    \not_strict_mode.app_rd_data_reg[447] ,
    \not_strict_mode.app_rd_data_reg[445] ,
    \not_strict_mode.app_rd_data_reg[455] ,
    \not_strict_mode.app_rd_data_reg[453] ,
    \not_strict_mode.app_rd_data_reg[451] ,
    \not_strict_mode.app_rd_data_reg[461] ,
    \not_strict_mode.app_rd_data_reg[459] ,
    \not_strict_mode.app_rd_data_reg[457] ,
    \not_strict_mode.app_rd_data_reg[467] ,
    \not_strict_mode.app_rd_data_reg[465] ,
    \not_strict_mode.app_rd_data_reg[463] ,
    \not_strict_mode.app_rd_data_reg[473] ,
    \not_strict_mode.app_rd_data_reg[471] ,
    \not_strict_mode.app_rd_data_reg[469] ,
    \not_strict_mode.app_rd_data_reg[479] ,
    \not_strict_mode.app_rd_data_reg[477] ,
    \not_strict_mode.app_rd_data_reg[475] ,
    \not_strict_mode.app_rd_data_reg[485] ,
    \not_strict_mode.app_rd_data_reg[483] ,
    \not_strict_mode.app_rd_data_reg[481] ,
    \not_strict_mode.app_rd_data_reg[491] ,
    \not_strict_mode.app_rd_data_reg[489] ,
    \not_strict_mode.app_rd_data_reg[487] ,
    \not_strict_mode.app_rd_data_reg[497] ,
    \not_strict_mode.app_rd_data_reg[495] ,
    \not_strict_mode.app_rd_data_reg[493] ,
    \not_strict_mode.app_rd_data_reg[503] ,
    \not_strict_mode.app_rd_data_reg[501] ,
    \not_strict_mode.app_rd_data_reg[499] ,
    \not_strict_mode.app_rd_data_reg[509] ,
    \not_strict_mode.app_rd_data_reg[507] ,
    \not_strict_mode.app_rd_data_reg[505] ,
    \not_strict_mode.app_rd_data_reg[511] ,
    app_rdy,
    app_wdf_rdy,
    app_rd_data_valid,
    app_rd_data_end,
    ram_init_done_r,
    app_en_r2,
    req_wr_r_lcl_reg,
    \req_data_buf_addr_r_reg[4] ,
    Q,
    \not_strict_mode.app_rd_data_reg[24] ,
    p_106_out,
    p_145_out,
    p_28_out,
    p_67_out,
    req_wr_r_lcl_reg_0,
    S,
    row,
    row_hit_r_reg,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    was_wr0,
    \req_bank_r_lcl_reg[2] ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \req_data_buf_addr_r_reg[4]_0 ,
    \req_col_r_reg[9] ,
    app_rd_data,
    CLK,
    pointer_we,
    \cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,
    ADDRC,
    \cmd_pipe_plus.wr_data_addr_reg[3] ,
    rd_buf_we,
    DIA,
    DIB,
    DIC,
    \read_fifo.fifo_out_data_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ,
    E,
    app_rd_data_end_ns,
    reset_reg,
    app_en,
    app_wdf_end,
    app_wdf_wren,
    periodic_rd_ack_r,
    periodic_rd_cntr_r,
    periodic_rd_r,
    \read_fifo.fifo_out_data_r_reg[4] ,
    idle_r_lcl_reg,
    \req_bank_r_lcl_reg[2]_0 ,
    idle_r_lcl_reg_0,
    \req_bank_r_lcl_reg[2]_1 ,
    idle_r_lcl_reg_1,
    \req_bank_r_lcl_reg[2]_2 ,
    idle_r_lcl_reg_2,
    \req_bank_r_lcl_reg[2]_3 ,
    \req_row_r_lcl_reg[13] ,
    \req_row_r_lcl_reg[13]_0 ,
    \req_row_r_lcl_reg[13]_1 ,
    \req_row_r_lcl_reg[13]_2 ,
    init_calib_complete_reg_rep__19,
    init_calib_complete_reg_rep__20,
    init_calib_complete_reg_rep__21,
    init_calib_complete_reg_rep__22,
    init_calib_complete_reg_rep__23,
    init_calib_complete_reg_rep__24,
    init_calib_complete_reg_rep__25,
    init_calib_complete_reg_rep__26,
    init_calib_complete_reg_rep__27,
    accept_ns,
    app_wdf_mask,
    app_wdf_data,
    app_addr,
    app_cmd,
    D);
  output [0:0]\not_strict_mode.app_rd_data_end_reg ;
  output [0:0]\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] ;
  output [1:0]DOA;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]\not_strict_mode.app_rd_data_reg[11] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[9] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[7] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[17] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[15] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[13] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[23] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[21] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[19] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[29] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[27] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[25] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[35] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[33] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[31] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[41] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[39] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[37] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[47] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[45] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[43] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[53] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[51] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[49] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[59] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[57] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[55] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[65] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[63] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[61] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[71] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[69] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[67] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[77] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[75] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[73] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[83] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[81] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[79] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[89] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[87] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[85] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[95] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[93] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[91] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[101] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[99] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[97] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[107] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[105] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[103] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[113] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[111] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[109] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[119] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[117] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[115] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[125] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[123] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[121] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[131] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[129] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[127] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[137] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[135] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[133] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[143] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[141] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[139] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[149] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[147] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[145] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[155] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[153] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[151] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[161] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[159] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[157] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[167] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[165] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[163] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[173] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[171] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[169] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[179] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[177] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[175] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[185] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[183] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[181] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[191] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[189] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[187] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[197] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[195] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[193] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[203] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[201] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[199] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[209] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[207] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[205] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[215] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[213] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[211] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[221] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[219] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[217] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[227] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[225] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[223] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[233] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[231] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[229] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[239] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[237] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[235] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[245] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[243] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[241] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[251] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[249] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[247] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[257] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[255] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[253] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[263] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[261] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[259] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[269] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[267] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[265] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[275] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[273] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[271] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[281] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[279] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[277] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[287] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[285] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[283] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[293] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[291] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[289] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[299] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[297] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[295] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[305] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[303] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[301] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[311] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[309] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[307] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[317] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[315] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[313] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[323] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[321] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[319] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[329] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[327] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[325] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[335] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[333] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[331] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[341] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[339] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[337] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[347] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[345] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[343] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[353] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[351] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[349] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[359] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[357] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[355] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[365] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[363] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[361] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[371] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[369] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[367] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[377] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[375] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[373] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[383] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[381] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[379] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[389] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[387] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[385] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[395] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[393] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[391] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[401] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[399] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[397] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[407] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[405] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[403] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[413] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[411] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[409] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[419] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[417] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[415] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[425] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[423] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[421] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[431] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[429] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[427] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[437] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[435] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[433] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[443] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[441] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[439] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[449] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[447] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[445] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[455] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[453] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[451] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[461] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[459] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[457] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[467] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[465] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[463] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[473] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[471] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[469] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[479] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[477] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[475] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[485] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[483] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[481] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[491] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[489] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[487] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[497] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[495] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[493] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[503] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[501] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[499] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[509] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[507] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[505] ;
  output [1:0]\not_strict_mode.app_rd_data_reg[511] ;
  output app_rdy;
  output app_wdf_rdy;
  output app_rd_data_valid;
  output app_rd_data_end;
  output ram_init_done_r;
  output app_en_r2;
  output req_wr_r_lcl_reg;
  output [0:0]\req_data_buf_addr_r_reg[4] ;
  output [0:0]Q;
  output \not_strict_mode.app_rd_data_reg[24] ;
  output p_106_out;
  output p_145_out;
  output p_28_out;
  output p_67_out;
  output req_wr_r_lcl_reg_0;
  output [0:0]S;
  output [13:0]row;
  output [0:0]row_hit_r_reg;
  output [0:0]row_hit_r_reg_0;
  output [0:0]row_hit_r_reg_1;
  output was_wr0;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [47:0]\my_empty_reg[7] ;
  output [575:0]\my_empty_reg[7]_0 ;
  output [47:0]\my_empty_reg[7]_1 ;
  output [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  output [9:0]\req_col_r_reg[9] ;
  output [511:0]app_rd_data;
  input CLK;
  input pointer_we;
  input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ;
  input [3:0]ADDRC;
  input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ;
  input rd_buf_we;
  input [1:0]DIA;
  input [1:0]DIB;
  input [1:0]DIC;
  input [6:0]\read_fifo.fifo_out_data_r_reg[7] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  input [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;
  input [0:0]E;
  input app_rd_data_end_ns;
  input reset_reg;
  input app_en;
  input app_wdf_end;
  input app_wdf_wren;
  input periodic_rd_ack_r;
  input periodic_rd_cntr_r;
  input periodic_rd_r;
  input \read_fifo.fifo_out_data_r_reg[4] ;
  input idle_r_lcl_reg;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input idle_r_lcl_reg_0;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input idle_r_lcl_reg_1;
  input [2:0]\req_bank_r_lcl_reg[2]_2 ;
  input idle_r_lcl_reg_2;
  input [2:0]\req_bank_r_lcl_reg[2]_3 ;
  input [1:0]\req_row_r_lcl_reg[13] ;
  input [1:0]\req_row_r_lcl_reg[13]_0 ;
  input [1:0]\req_row_r_lcl_reg[13]_1 ;
  input [1:0]\req_row_r_lcl_reg[13]_2 ;
  input init_calib_complete_reg_rep__19;
  input init_calib_complete_reg_rep__20;
  input init_calib_complete_reg_rep__21;
  input init_calib_complete_reg_rep__22;
  input init_calib_complete_reg_rep__23;
  input init_calib_complete_reg_rep__24;
  input init_calib_complete_reg_rep__25;
  input init_calib_complete_reg_rep__26;
  input init_calib_complete_reg_rep__27;
  input accept_ns;
  input [63:0]app_wdf_mask;
  input [511:0]app_wdf_data;
  input [26:0]app_addr;
  input [1:0]app_cmd;
  input [511:0]D;

  wire [3:0]ADDRC;
  wire CLK;
  wire [511:0]D;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [1:0]DIC;
  wire [1:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]S;
  wire accept_ns;
  wire [26:0]app_addr;
  wire [1:0]app_cmd;
  wire [0:0]app_cmd_r2;
  wire app_en;
  wire app_en_r2;
  wire [511:0]app_rd_data;
  wire app_rd_data_end;
  wire app_rd_data_end_ns;
  wire app_rd_data_valid;
  wire app_rdy;
  wire app_rdy_ns;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ;
  wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;
  wire [1:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire init_calib_complete_reg_rep__19;
  wire init_calib_complete_reg_rep__20;
  wire init_calib_complete_reg_rep__21;
  wire init_calib_complete_reg_rep__22;
  wire init_calib_complete_reg_rep__23;
  wire init_calib_complete_reg_rep__24;
  wire init_calib_complete_reg_rep__25;
  wire init_calib_complete_reg_rep__26;
  wire init_calib_complete_reg_rep__27;
  wire [47:0]\my_empty_reg[7] ;
  wire [575:0]\my_empty_reg[7]_0 ;
  wire [47:0]\my_empty_reg[7]_1 ;
  wire [0:0]\not_strict_mode.app_rd_data_end_reg ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[101] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[103] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[105] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[107] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[109] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[111] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[113] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[115] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[117] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[119] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[11] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[121] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[123] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[125] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[127] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[129] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[131] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[133] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[135] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[137] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[139] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[13] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[141] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[143] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[145] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[147] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[149] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[151] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[153] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[155] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[157] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[159] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[15] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[161] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[163] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[165] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[167] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[169] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[171] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[173] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[175] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[177] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[179] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[17] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[181] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[183] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[185] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[187] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[189] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[191] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[193] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[195] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[197] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[199] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[19] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[201] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[203] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[205] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[207] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[209] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[211] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[213] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[215] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[217] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[219] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[21] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[221] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[223] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[225] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[227] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[229] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[231] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[233] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[235] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[237] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[239] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[23] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[241] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[243] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[245] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[247] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[249] ;
  wire \not_strict_mode.app_rd_data_reg[24] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[251] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[253] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[255] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[257] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[259] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[25] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[261] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[263] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[265] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[267] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[269] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[271] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[273] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[275] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[277] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[279] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[27] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[281] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[283] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[285] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[287] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[289] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[291] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[293] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[295] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[297] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[299] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[29] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[301] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[303] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[305] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[307] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[309] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[311] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[313] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[315] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[317] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[319] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[31] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[321] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[323] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[325] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[327] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[329] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[331] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[333] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[335] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[337] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[339] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[33] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[341] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[343] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[345] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[347] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[349] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[351] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[353] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[355] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[357] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[359] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[35] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[361] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[363] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[365] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[367] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[369] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[371] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[373] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[375] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[377] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[379] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[37] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[381] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[383] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[385] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[387] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[389] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[391] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[393] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[395] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[397] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[399] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[39] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[401] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[403] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[405] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[407] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[409] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[411] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[413] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[415] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[417] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[419] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[41] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[421] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[423] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[425] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[427] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[429] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[431] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[433] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[435] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[437] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[439] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[43] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[441] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[443] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[445] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[447] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[449] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[451] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[453] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[455] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[457] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[459] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[45] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[461] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[463] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[465] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[467] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[469] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[471] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[473] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[475] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[477] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[479] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[47] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[481] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[483] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[485] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[487] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[489] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[491] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[493] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[495] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[497] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[499] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[49] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[501] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[503] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[505] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[507] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[509] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[511] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[51] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[53] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[55] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[57] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[59] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[61] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[63] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[65] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[67] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[69] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[71] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[73] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[75] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[77] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[79] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[7] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[81] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[83] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[85] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[87] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[89] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[91] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[93] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[95] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[97] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[99] ;
  wire [1:0]\not_strict_mode.app_rd_data_reg[9] ;
  wire [0:0]\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] ;
  wire [3:0]occ_cnt_r;
  wire p_106_out;
  wire p_145_out;
  wire p_28_out;
  wire p_67_out;
  wire periodic_rd_ack_r;
  wire periodic_rd_cntr_r;
  wire periodic_rd_r;
  wire pointer_we;
  wire [3:0]pointer_wr_addr;
  wire [3:0]pointer_wr_data;
  wire ram_init_done_r;
  wire rd_accepted;
  wire rd_buf_we;
  wire [4:0]rd_data_buf_addr_r;
  wire [3:0]\read_data_indx.rd_data_indx_r_reg__0 ;
  wire \read_fifo.fifo_out_data_r_reg[4] ;
  wire [6:0]\read_fifo.fifo_out_data_r_reg[7] ;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_3 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [0:0]\req_data_buf_addr_r_reg[4] ;
  wire [4:0]\req_data_buf_addr_r_reg[4]_0 ;
  wire [1:0]\req_row_r_lcl_reg[13] ;
  wire [1:0]\req_row_r_lcl_reg[13]_0 ;
  wire [1:0]\req_row_r_lcl_reg[13]_1 ;
  wire [1:0]\req_row_r_lcl_reg[13]_2 ;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire reset_reg;
  wire [13:0]row;
  wire [0:0]row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire ui_cmd0_n_21;
  wire ui_cmd0_n_22;
  wire ui_rd_data0_n_522;
  wire ui_wr_data0_n_0;
  wire ui_wr_data0_n_1;
  wire ui_wr_data0_n_2;
  wire ui_wr_data0_n_3;
  wire was_wr0;
  wire wr_accepted;

  mig_7series_0_mig_7series_v2_3_ui_cmd ui_cmd0
       (.CLK(CLK),
        .D(ui_cmd0_n_22),
        .DOB({ui_wr_data0_n_0,ui_wr_data0_n_1}),
        .E(app_rdy),
        .Q(Q),
        .S(S),
        .app_addr(app_addr),
        .app_cmd(app_cmd),
        .app_cmd_r2(app_cmd_r2),
        .app_en(app_en),
        .app_rdy_ns(app_rdy_ns),
        .\data_buf_address_counter.data_buf_addr_cnt_r_reg[3] ({ui_wr_data0_n_2,ui_wr_data0_n_3}),
        .idle_r_lcl_reg(idle_r_lcl_reg),
        .idle_r_lcl_reg_0(idle_r_lcl_reg_0),
        .idle_r_lcl_reg_1(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_2),
        .\not_strict_mode.app_rd_data_end_reg (app_rd_data_end),
        .\not_strict_mode.app_rd_data_valid_reg (app_rd_data_valid),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (app_en_r2),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 (rd_data_buf_addr_r),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[2] (ui_cmd0_n_21),
        .occ_cnt_r(occ_cnt_r),
        .p_106_out(p_106_out),
        .p_145_out(p_145_out),
        .p_28_out(p_28_out),
        .p_67_out(p_67_out),
        .periodic_rd_ack_r(periodic_rd_ack_r),
        .periodic_rd_cntr_r(periodic_rd_cntr_r),
        .periodic_rd_r(periodic_rd_r),
        .rd_accepted(rd_accepted),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ),
        .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ),
        .\req_bank_r_lcl_reg[2]_3 (\req_bank_r_lcl_reg[2]_3 ),
        .\req_col_r_reg[9] (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[4] (\req_data_buf_addr_r_reg[4] ),
        .\req_data_buf_addr_r_reg[4]_0 (\req_data_buf_addr_r_reg[4]_0 ),
        .\req_row_r_lcl_reg[13] (row[13]),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_0 ),
        .\req_row_r_lcl_reg[13]_2 (\req_row_r_lcl_reg[13]_1 ),
        .\req_row_r_lcl_reg[13]_3 (\req_row_r_lcl_reg[13]_2 ),
        .req_wr_r_lcl_reg(req_wr_r_lcl_reg),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),
        .reset_reg(reset_reg),
        .row(row[12:0]),
        .row_hit_r_reg(row_hit_r_reg),
        .row_hit_r_reg_0(row_hit_r_reg_0),
        .row_hit_r_reg_1(row_hit_r_reg_1),
        .was_wr0(was_wr0),
        .wr_accepted(wr_accepted));
  mig_7series_0_mig_7series_v2_3_ui_rd_data ui_rd_data0
       (.ADDRA(\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] ),
        .ADDRD(pointer_wr_addr),
        .CLK(CLK),
        .D(ui_rd_data0_n_522),
        .DIA(DIA),
        .DIB(DIB),
        .DIC(DIC),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .Q(rd_data_buf_addr_r),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[1] (\req_data_buf_addr_r_reg[4] ),
        .app_en_r2(app_en_r2),
        .app_rd_data(app_rd_data),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_end_ns(app_rd_data_end_ns),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rdy_r_reg(app_rdy),
        .\cmd_pipe_plus.wr_data_addr_reg[3] (\cmd_pipe_plus.wr_data_addr_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2 (D),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3 ),
        .\not_strict_mode.app_rd_data_end_reg_0 (\not_strict_mode.app_rd_data_end_reg ),
        .\not_strict_mode.app_rd_data_reg[101]_0 (\not_strict_mode.app_rd_data_reg[101] ),
        .\not_strict_mode.app_rd_data_reg[103]_0 (\not_strict_mode.app_rd_data_reg[103] ),
        .\not_strict_mode.app_rd_data_reg[105]_0 (\not_strict_mode.app_rd_data_reg[105] ),
        .\not_strict_mode.app_rd_data_reg[107]_0 (\not_strict_mode.app_rd_data_reg[107] ),
        .\not_strict_mode.app_rd_data_reg[109]_0 (\not_strict_mode.app_rd_data_reg[109] ),
        .\not_strict_mode.app_rd_data_reg[111]_0 (\not_strict_mode.app_rd_data_reg[111] ),
        .\not_strict_mode.app_rd_data_reg[113]_0 (\not_strict_mode.app_rd_data_reg[113] ),
        .\not_strict_mode.app_rd_data_reg[115]_0 (\not_strict_mode.app_rd_data_reg[115] ),
        .\not_strict_mode.app_rd_data_reg[117]_0 (\not_strict_mode.app_rd_data_reg[117] ),
        .\not_strict_mode.app_rd_data_reg[119]_0 (\not_strict_mode.app_rd_data_reg[119] ),
        .\not_strict_mode.app_rd_data_reg[11]_0 (\not_strict_mode.app_rd_data_reg[11] ),
        .\not_strict_mode.app_rd_data_reg[121]_0 (\not_strict_mode.app_rd_data_reg[121] ),
        .\not_strict_mode.app_rd_data_reg[123]_0 (\not_strict_mode.app_rd_data_reg[123] ),
        .\not_strict_mode.app_rd_data_reg[125]_0 (\not_strict_mode.app_rd_data_reg[125] ),
        .\not_strict_mode.app_rd_data_reg[127]_0 (\not_strict_mode.app_rd_data_reg[127] ),
        .\not_strict_mode.app_rd_data_reg[129]_0 (\not_strict_mode.app_rd_data_reg[129] ),
        .\not_strict_mode.app_rd_data_reg[131]_0 (\not_strict_mode.app_rd_data_reg[131] ),
        .\not_strict_mode.app_rd_data_reg[133]_0 (\not_strict_mode.app_rd_data_reg[133] ),
        .\not_strict_mode.app_rd_data_reg[135]_0 (\not_strict_mode.app_rd_data_reg[135] ),
        .\not_strict_mode.app_rd_data_reg[137]_0 (\not_strict_mode.app_rd_data_reg[137] ),
        .\not_strict_mode.app_rd_data_reg[139]_0 (\not_strict_mode.app_rd_data_reg[139] ),
        .\not_strict_mode.app_rd_data_reg[13]_0 (\not_strict_mode.app_rd_data_reg[13] ),
        .\not_strict_mode.app_rd_data_reg[141]_0 (\not_strict_mode.app_rd_data_reg[141] ),
        .\not_strict_mode.app_rd_data_reg[143]_0 (\not_strict_mode.app_rd_data_reg[143] ),
        .\not_strict_mode.app_rd_data_reg[145]_0 (\not_strict_mode.app_rd_data_reg[145] ),
        .\not_strict_mode.app_rd_data_reg[147]_0 (\not_strict_mode.app_rd_data_reg[147] ),
        .\not_strict_mode.app_rd_data_reg[149]_0 (\not_strict_mode.app_rd_data_reg[149] ),
        .\not_strict_mode.app_rd_data_reg[151]_0 (\not_strict_mode.app_rd_data_reg[151] ),
        .\not_strict_mode.app_rd_data_reg[153]_0 (\not_strict_mode.app_rd_data_reg[153] ),
        .\not_strict_mode.app_rd_data_reg[155]_0 (\not_strict_mode.app_rd_data_reg[155] ),
        .\not_strict_mode.app_rd_data_reg[157]_0 (\not_strict_mode.app_rd_data_reg[157] ),
        .\not_strict_mode.app_rd_data_reg[159]_0 (\not_strict_mode.app_rd_data_reg[159] ),
        .\not_strict_mode.app_rd_data_reg[15]_0 (\not_strict_mode.app_rd_data_reg[15] ),
        .\not_strict_mode.app_rd_data_reg[161]_0 (\not_strict_mode.app_rd_data_reg[161] ),
        .\not_strict_mode.app_rd_data_reg[163]_0 (\not_strict_mode.app_rd_data_reg[163] ),
        .\not_strict_mode.app_rd_data_reg[165]_0 (\not_strict_mode.app_rd_data_reg[165] ),
        .\not_strict_mode.app_rd_data_reg[167]_0 (\not_strict_mode.app_rd_data_reg[167] ),
        .\not_strict_mode.app_rd_data_reg[169]_0 (\not_strict_mode.app_rd_data_reg[169] ),
        .\not_strict_mode.app_rd_data_reg[171]_0 (\not_strict_mode.app_rd_data_reg[171] ),
        .\not_strict_mode.app_rd_data_reg[173]_0 (\not_strict_mode.app_rd_data_reg[173] ),
        .\not_strict_mode.app_rd_data_reg[175]_0 (\not_strict_mode.app_rd_data_reg[175] ),
        .\not_strict_mode.app_rd_data_reg[177]_0 (\not_strict_mode.app_rd_data_reg[177] ),
        .\not_strict_mode.app_rd_data_reg[179]_0 (\not_strict_mode.app_rd_data_reg[179] ),
        .\not_strict_mode.app_rd_data_reg[17]_0 (\not_strict_mode.app_rd_data_reg[17] ),
        .\not_strict_mode.app_rd_data_reg[181]_0 (\not_strict_mode.app_rd_data_reg[181] ),
        .\not_strict_mode.app_rd_data_reg[183]_0 (\not_strict_mode.app_rd_data_reg[183] ),
        .\not_strict_mode.app_rd_data_reg[185]_0 (\not_strict_mode.app_rd_data_reg[185] ),
        .\not_strict_mode.app_rd_data_reg[187]_0 (\not_strict_mode.app_rd_data_reg[187] ),
        .\not_strict_mode.app_rd_data_reg[189]_0 (\not_strict_mode.app_rd_data_reg[189] ),
        .\not_strict_mode.app_rd_data_reg[191]_0 (\not_strict_mode.app_rd_data_reg[191] ),
        .\not_strict_mode.app_rd_data_reg[193]_0 (\not_strict_mode.app_rd_data_reg[193] ),
        .\not_strict_mode.app_rd_data_reg[195]_0 (\not_strict_mode.app_rd_data_reg[195] ),
        .\not_strict_mode.app_rd_data_reg[197]_0 (\not_strict_mode.app_rd_data_reg[197] ),
        .\not_strict_mode.app_rd_data_reg[199]_0 (\not_strict_mode.app_rd_data_reg[199] ),
        .\not_strict_mode.app_rd_data_reg[19]_0 (\not_strict_mode.app_rd_data_reg[19] ),
        .\not_strict_mode.app_rd_data_reg[201]_0 (\not_strict_mode.app_rd_data_reg[201] ),
        .\not_strict_mode.app_rd_data_reg[203]_0 (\not_strict_mode.app_rd_data_reg[203] ),
        .\not_strict_mode.app_rd_data_reg[205]_0 (\not_strict_mode.app_rd_data_reg[205] ),
        .\not_strict_mode.app_rd_data_reg[207]_0 (\not_strict_mode.app_rd_data_reg[207] ),
        .\not_strict_mode.app_rd_data_reg[209]_0 (\not_strict_mode.app_rd_data_reg[209] ),
        .\not_strict_mode.app_rd_data_reg[211]_0 (\not_strict_mode.app_rd_data_reg[211] ),
        .\not_strict_mode.app_rd_data_reg[213]_0 (\not_strict_mode.app_rd_data_reg[213] ),
        .\not_strict_mode.app_rd_data_reg[215]_0 (\not_strict_mode.app_rd_data_reg[215] ),
        .\not_strict_mode.app_rd_data_reg[217]_0 (\not_strict_mode.app_rd_data_reg[217] ),
        .\not_strict_mode.app_rd_data_reg[219]_0 (\not_strict_mode.app_rd_data_reg[219] ),
        .\not_strict_mode.app_rd_data_reg[21]_0 (\not_strict_mode.app_rd_data_reg[21] ),
        .\not_strict_mode.app_rd_data_reg[221]_0 (\not_strict_mode.app_rd_data_reg[221] ),
        .\not_strict_mode.app_rd_data_reg[223]_0 (\not_strict_mode.app_rd_data_reg[223] ),
        .\not_strict_mode.app_rd_data_reg[225]_0 (\not_strict_mode.app_rd_data_reg[225] ),
        .\not_strict_mode.app_rd_data_reg[227]_0 (\not_strict_mode.app_rd_data_reg[227] ),
        .\not_strict_mode.app_rd_data_reg[229]_0 (\not_strict_mode.app_rd_data_reg[229] ),
        .\not_strict_mode.app_rd_data_reg[231]_0 (\not_strict_mode.app_rd_data_reg[231] ),
        .\not_strict_mode.app_rd_data_reg[233]_0 (\not_strict_mode.app_rd_data_reg[233] ),
        .\not_strict_mode.app_rd_data_reg[235]_0 (\not_strict_mode.app_rd_data_reg[235] ),
        .\not_strict_mode.app_rd_data_reg[237]_0 (\not_strict_mode.app_rd_data_reg[237] ),
        .\not_strict_mode.app_rd_data_reg[239]_0 (\not_strict_mode.app_rd_data_reg[239] ),
        .\not_strict_mode.app_rd_data_reg[23]_0 (\not_strict_mode.app_rd_data_reg[23] ),
        .\not_strict_mode.app_rd_data_reg[241]_0 (\not_strict_mode.app_rd_data_reg[241] ),
        .\not_strict_mode.app_rd_data_reg[243]_0 (\not_strict_mode.app_rd_data_reg[243] ),
        .\not_strict_mode.app_rd_data_reg[245]_0 (\not_strict_mode.app_rd_data_reg[245] ),
        .\not_strict_mode.app_rd_data_reg[247]_0 (\not_strict_mode.app_rd_data_reg[247] ),
        .\not_strict_mode.app_rd_data_reg[249]_0 (\not_strict_mode.app_rd_data_reg[249] ),
        .\not_strict_mode.app_rd_data_reg[24]_0 (\not_strict_mode.app_rd_data_reg[24] ),
        .\not_strict_mode.app_rd_data_reg[251]_0 (\not_strict_mode.app_rd_data_reg[251] ),
        .\not_strict_mode.app_rd_data_reg[253]_0 (\not_strict_mode.app_rd_data_reg[253] ),
        .\not_strict_mode.app_rd_data_reg[255]_0 (\not_strict_mode.app_rd_data_reg[255] ),
        .\not_strict_mode.app_rd_data_reg[257]_0 (\not_strict_mode.app_rd_data_reg[257] ),
        .\not_strict_mode.app_rd_data_reg[259]_0 (\not_strict_mode.app_rd_data_reg[259] ),
        .\not_strict_mode.app_rd_data_reg[25]_0 (\not_strict_mode.app_rd_data_reg[25] ),
        .\not_strict_mode.app_rd_data_reg[261]_0 (\not_strict_mode.app_rd_data_reg[261] ),
        .\not_strict_mode.app_rd_data_reg[263]_0 (\not_strict_mode.app_rd_data_reg[263] ),
        .\not_strict_mode.app_rd_data_reg[265]_0 (\not_strict_mode.app_rd_data_reg[265] ),
        .\not_strict_mode.app_rd_data_reg[267]_0 (\not_strict_mode.app_rd_data_reg[267] ),
        .\not_strict_mode.app_rd_data_reg[269]_0 (\not_strict_mode.app_rd_data_reg[269] ),
        .\not_strict_mode.app_rd_data_reg[271]_0 (\not_strict_mode.app_rd_data_reg[271] ),
        .\not_strict_mode.app_rd_data_reg[273]_0 (\not_strict_mode.app_rd_data_reg[273] ),
        .\not_strict_mode.app_rd_data_reg[275]_0 (\not_strict_mode.app_rd_data_reg[275] ),
        .\not_strict_mode.app_rd_data_reg[277]_0 (\not_strict_mode.app_rd_data_reg[277] ),
        .\not_strict_mode.app_rd_data_reg[279]_0 (\not_strict_mode.app_rd_data_reg[279] ),
        .\not_strict_mode.app_rd_data_reg[27]_0 (\not_strict_mode.app_rd_data_reg[27] ),
        .\not_strict_mode.app_rd_data_reg[281]_0 (\not_strict_mode.app_rd_data_reg[281] ),
        .\not_strict_mode.app_rd_data_reg[283]_0 (\not_strict_mode.app_rd_data_reg[283] ),
        .\not_strict_mode.app_rd_data_reg[285]_0 (\not_strict_mode.app_rd_data_reg[285] ),
        .\not_strict_mode.app_rd_data_reg[287]_0 (\not_strict_mode.app_rd_data_reg[287] ),
        .\not_strict_mode.app_rd_data_reg[289]_0 (\not_strict_mode.app_rd_data_reg[289] ),
        .\not_strict_mode.app_rd_data_reg[291]_0 (\not_strict_mode.app_rd_data_reg[291] ),
        .\not_strict_mode.app_rd_data_reg[293]_0 (\not_strict_mode.app_rd_data_reg[293] ),
        .\not_strict_mode.app_rd_data_reg[295]_0 (\not_strict_mode.app_rd_data_reg[295] ),
        .\not_strict_mode.app_rd_data_reg[297]_0 (\not_strict_mode.app_rd_data_reg[297] ),
        .\not_strict_mode.app_rd_data_reg[299]_0 (\not_strict_mode.app_rd_data_reg[299] ),
        .\not_strict_mode.app_rd_data_reg[29]_0 (\not_strict_mode.app_rd_data_reg[29] ),
        .\not_strict_mode.app_rd_data_reg[301]_0 (\not_strict_mode.app_rd_data_reg[301] ),
        .\not_strict_mode.app_rd_data_reg[303]_0 (\not_strict_mode.app_rd_data_reg[303] ),
        .\not_strict_mode.app_rd_data_reg[305]_0 (\not_strict_mode.app_rd_data_reg[305] ),
        .\not_strict_mode.app_rd_data_reg[307]_0 (\not_strict_mode.app_rd_data_reg[307] ),
        .\not_strict_mode.app_rd_data_reg[309]_0 (\not_strict_mode.app_rd_data_reg[309] ),
        .\not_strict_mode.app_rd_data_reg[311]_0 (\not_strict_mode.app_rd_data_reg[311] ),
        .\not_strict_mode.app_rd_data_reg[313]_0 (\not_strict_mode.app_rd_data_reg[313] ),
        .\not_strict_mode.app_rd_data_reg[315]_0 (\not_strict_mode.app_rd_data_reg[315] ),
        .\not_strict_mode.app_rd_data_reg[317]_0 (\not_strict_mode.app_rd_data_reg[317] ),
        .\not_strict_mode.app_rd_data_reg[319]_0 (\not_strict_mode.app_rd_data_reg[319] ),
        .\not_strict_mode.app_rd_data_reg[31]_0 (\not_strict_mode.app_rd_data_reg[31] ),
        .\not_strict_mode.app_rd_data_reg[321]_0 (\not_strict_mode.app_rd_data_reg[321] ),
        .\not_strict_mode.app_rd_data_reg[323]_0 (\not_strict_mode.app_rd_data_reg[323] ),
        .\not_strict_mode.app_rd_data_reg[325]_0 (\not_strict_mode.app_rd_data_reg[325] ),
        .\not_strict_mode.app_rd_data_reg[327]_0 (\not_strict_mode.app_rd_data_reg[327] ),
        .\not_strict_mode.app_rd_data_reg[329]_0 (\not_strict_mode.app_rd_data_reg[329] ),
        .\not_strict_mode.app_rd_data_reg[331]_0 (\not_strict_mode.app_rd_data_reg[331] ),
        .\not_strict_mode.app_rd_data_reg[333]_0 (\not_strict_mode.app_rd_data_reg[333] ),
        .\not_strict_mode.app_rd_data_reg[335]_0 (\not_strict_mode.app_rd_data_reg[335] ),
        .\not_strict_mode.app_rd_data_reg[337]_0 (\not_strict_mode.app_rd_data_reg[337] ),
        .\not_strict_mode.app_rd_data_reg[339]_0 (\not_strict_mode.app_rd_data_reg[339] ),
        .\not_strict_mode.app_rd_data_reg[33]_0 (\not_strict_mode.app_rd_data_reg[33] ),
        .\not_strict_mode.app_rd_data_reg[341]_0 (\not_strict_mode.app_rd_data_reg[341] ),
        .\not_strict_mode.app_rd_data_reg[343]_0 (\not_strict_mode.app_rd_data_reg[343] ),
        .\not_strict_mode.app_rd_data_reg[345]_0 (\not_strict_mode.app_rd_data_reg[345] ),
        .\not_strict_mode.app_rd_data_reg[347]_0 (\not_strict_mode.app_rd_data_reg[347] ),
        .\not_strict_mode.app_rd_data_reg[349]_0 (\not_strict_mode.app_rd_data_reg[349] ),
        .\not_strict_mode.app_rd_data_reg[351]_0 (\not_strict_mode.app_rd_data_reg[351] ),
        .\not_strict_mode.app_rd_data_reg[353]_0 (\not_strict_mode.app_rd_data_reg[353] ),
        .\not_strict_mode.app_rd_data_reg[355]_0 (\not_strict_mode.app_rd_data_reg[355] ),
        .\not_strict_mode.app_rd_data_reg[357]_0 (\not_strict_mode.app_rd_data_reg[357] ),
        .\not_strict_mode.app_rd_data_reg[359]_0 (\not_strict_mode.app_rd_data_reg[359] ),
        .\not_strict_mode.app_rd_data_reg[35]_0 (\not_strict_mode.app_rd_data_reg[35] ),
        .\not_strict_mode.app_rd_data_reg[361]_0 (\not_strict_mode.app_rd_data_reg[361] ),
        .\not_strict_mode.app_rd_data_reg[363]_0 (\not_strict_mode.app_rd_data_reg[363] ),
        .\not_strict_mode.app_rd_data_reg[365]_0 (\not_strict_mode.app_rd_data_reg[365] ),
        .\not_strict_mode.app_rd_data_reg[367]_0 (\not_strict_mode.app_rd_data_reg[367] ),
        .\not_strict_mode.app_rd_data_reg[369]_0 (\not_strict_mode.app_rd_data_reg[369] ),
        .\not_strict_mode.app_rd_data_reg[371]_0 (\not_strict_mode.app_rd_data_reg[371] ),
        .\not_strict_mode.app_rd_data_reg[373]_0 (\not_strict_mode.app_rd_data_reg[373] ),
        .\not_strict_mode.app_rd_data_reg[375]_0 (\not_strict_mode.app_rd_data_reg[375] ),
        .\not_strict_mode.app_rd_data_reg[377]_0 (\not_strict_mode.app_rd_data_reg[377] ),
        .\not_strict_mode.app_rd_data_reg[379]_0 (\not_strict_mode.app_rd_data_reg[379] ),
        .\not_strict_mode.app_rd_data_reg[37]_0 (\not_strict_mode.app_rd_data_reg[37] ),
        .\not_strict_mode.app_rd_data_reg[381]_0 (\not_strict_mode.app_rd_data_reg[381] ),
        .\not_strict_mode.app_rd_data_reg[383]_0 (\not_strict_mode.app_rd_data_reg[383] ),
        .\not_strict_mode.app_rd_data_reg[385]_0 (\not_strict_mode.app_rd_data_reg[385] ),
        .\not_strict_mode.app_rd_data_reg[387]_0 (\not_strict_mode.app_rd_data_reg[387] ),
        .\not_strict_mode.app_rd_data_reg[389]_0 (\not_strict_mode.app_rd_data_reg[389] ),
        .\not_strict_mode.app_rd_data_reg[391]_0 (\not_strict_mode.app_rd_data_reg[391] ),
        .\not_strict_mode.app_rd_data_reg[393]_0 (\not_strict_mode.app_rd_data_reg[393] ),
        .\not_strict_mode.app_rd_data_reg[395]_0 (\not_strict_mode.app_rd_data_reg[395] ),
        .\not_strict_mode.app_rd_data_reg[397]_0 (\not_strict_mode.app_rd_data_reg[397] ),
        .\not_strict_mode.app_rd_data_reg[399]_0 (\not_strict_mode.app_rd_data_reg[399] ),
        .\not_strict_mode.app_rd_data_reg[39]_0 (\not_strict_mode.app_rd_data_reg[39] ),
        .\not_strict_mode.app_rd_data_reg[401]_0 (\not_strict_mode.app_rd_data_reg[401] ),
        .\not_strict_mode.app_rd_data_reg[403]_0 (\not_strict_mode.app_rd_data_reg[403] ),
        .\not_strict_mode.app_rd_data_reg[405]_0 (\not_strict_mode.app_rd_data_reg[405] ),
        .\not_strict_mode.app_rd_data_reg[407]_0 (\not_strict_mode.app_rd_data_reg[407] ),
        .\not_strict_mode.app_rd_data_reg[409]_0 (\not_strict_mode.app_rd_data_reg[409] ),
        .\not_strict_mode.app_rd_data_reg[411]_0 (\not_strict_mode.app_rd_data_reg[411] ),
        .\not_strict_mode.app_rd_data_reg[413]_0 (\not_strict_mode.app_rd_data_reg[413] ),
        .\not_strict_mode.app_rd_data_reg[415]_0 (\not_strict_mode.app_rd_data_reg[415] ),
        .\not_strict_mode.app_rd_data_reg[417]_0 (\not_strict_mode.app_rd_data_reg[417] ),
        .\not_strict_mode.app_rd_data_reg[419]_0 (\not_strict_mode.app_rd_data_reg[419] ),
        .\not_strict_mode.app_rd_data_reg[41]_0 (\not_strict_mode.app_rd_data_reg[41] ),
        .\not_strict_mode.app_rd_data_reg[421]_0 (\not_strict_mode.app_rd_data_reg[421] ),
        .\not_strict_mode.app_rd_data_reg[423]_0 (\not_strict_mode.app_rd_data_reg[423] ),
        .\not_strict_mode.app_rd_data_reg[425]_0 (\not_strict_mode.app_rd_data_reg[425] ),
        .\not_strict_mode.app_rd_data_reg[427]_0 (\not_strict_mode.app_rd_data_reg[427] ),
        .\not_strict_mode.app_rd_data_reg[429]_0 (\not_strict_mode.app_rd_data_reg[429] ),
        .\not_strict_mode.app_rd_data_reg[431]_0 (\not_strict_mode.app_rd_data_reg[431] ),
        .\not_strict_mode.app_rd_data_reg[433]_0 (\not_strict_mode.app_rd_data_reg[433] ),
        .\not_strict_mode.app_rd_data_reg[435]_0 (\not_strict_mode.app_rd_data_reg[435] ),
        .\not_strict_mode.app_rd_data_reg[437]_0 (\not_strict_mode.app_rd_data_reg[437] ),
        .\not_strict_mode.app_rd_data_reg[439]_0 (\not_strict_mode.app_rd_data_reg[439] ),
        .\not_strict_mode.app_rd_data_reg[43]_0 (\not_strict_mode.app_rd_data_reg[43] ),
        .\not_strict_mode.app_rd_data_reg[441]_0 (\not_strict_mode.app_rd_data_reg[441] ),
        .\not_strict_mode.app_rd_data_reg[443]_0 (\not_strict_mode.app_rd_data_reg[443] ),
        .\not_strict_mode.app_rd_data_reg[445]_0 (\not_strict_mode.app_rd_data_reg[445] ),
        .\not_strict_mode.app_rd_data_reg[447]_0 (\not_strict_mode.app_rd_data_reg[447] ),
        .\not_strict_mode.app_rd_data_reg[449]_0 (\not_strict_mode.app_rd_data_reg[449] ),
        .\not_strict_mode.app_rd_data_reg[451]_0 (\not_strict_mode.app_rd_data_reg[451] ),
        .\not_strict_mode.app_rd_data_reg[453]_0 (\not_strict_mode.app_rd_data_reg[453] ),
        .\not_strict_mode.app_rd_data_reg[455]_0 (\not_strict_mode.app_rd_data_reg[455] ),
        .\not_strict_mode.app_rd_data_reg[457]_0 (\not_strict_mode.app_rd_data_reg[457] ),
        .\not_strict_mode.app_rd_data_reg[459]_0 (\not_strict_mode.app_rd_data_reg[459] ),
        .\not_strict_mode.app_rd_data_reg[45]_0 (\not_strict_mode.app_rd_data_reg[45] ),
        .\not_strict_mode.app_rd_data_reg[461]_0 (\not_strict_mode.app_rd_data_reg[461] ),
        .\not_strict_mode.app_rd_data_reg[463]_0 (\not_strict_mode.app_rd_data_reg[463] ),
        .\not_strict_mode.app_rd_data_reg[465]_0 (\not_strict_mode.app_rd_data_reg[465] ),
        .\not_strict_mode.app_rd_data_reg[467]_0 (\not_strict_mode.app_rd_data_reg[467] ),
        .\not_strict_mode.app_rd_data_reg[469]_0 (\not_strict_mode.app_rd_data_reg[469] ),
        .\not_strict_mode.app_rd_data_reg[471]_0 (\not_strict_mode.app_rd_data_reg[471] ),
        .\not_strict_mode.app_rd_data_reg[473]_0 (\not_strict_mode.app_rd_data_reg[473] ),
        .\not_strict_mode.app_rd_data_reg[475]_0 (\not_strict_mode.app_rd_data_reg[475] ),
        .\not_strict_mode.app_rd_data_reg[477]_0 (\not_strict_mode.app_rd_data_reg[477] ),
        .\not_strict_mode.app_rd_data_reg[479]_0 (\not_strict_mode.app_rd_data_reg[479] ),
        .\not_strict_mode.app_rd_data_reg[47]_0 (\not_strict_mode.app_rd_data_reg[47] ),
        .\not_strict_mode.app_rd_data_reg[481]_0 (\not_strict_mode.app_rd_data_reg[481] ),
        .\not_strict_mode.app_rd_data_reg[483]_0 (\not_strict_mode.app_rd_data_reg[483] ),
        .\not_strict_mode.app_rd_data_reg[485]_0 (\not_strict_mode.app_rd_data_reg[485] ),
        .\not_strict_mode.app_rd_data_reg[487]_0 (\not_strict_mode.app_rd_data_reg[487] ),
        .\not_strict_mode.app_rd_data_reg[489]_0 (\not_strict_mode.app_rd_data_reg[489] ),
        .\not_strict_mode.app_rd_data_reg[491]_0 (\not_strict_mode.app_rd_data_reg[491] ),
        .\not_strict_mode.app_rd_data_reg[493]_0 (\not_strict_mode.app_rd_data_reg[493] ),
        .\not_strict_mode.app_rd_data_reg[495]_0 (\not_strict_mode.app_rd_data_reg[495] ),
        .\not_strict_mode.app_rd_data_reg[497]_0 (\not_strict_mode.app_rd_data_reg[497] ),
        .\not_strict_mode.app_rd_data_reg[499]_0 (\not_strict_mode.app_rd_data_reg[499] ),
        .\not_strict_mode.app_rd_data_reg[49]_0 (\not_strict_mode.app_rd_data_reg[49] ),
        .\not_strict_mode.app_rd_data_reg[501]_0 (\not_strict_mode.app_rd_data_reg[501] ),
        .\not_strict_mode.app_rd_data_reg[503]_0 (\not_strict_mode.app_rd_data_reg[503] ),
        .\not_strict_mode.app_rd_data_reg[505]_0 (\not_strict_mode.app_rd_data_reg[505] ),
        .\not_strict_mode.app_rd_data_reg[507]_0 (\not_strict_mode.app_rd_data_reg[507] ),
        .\not_strict_mode.app_rd_data_reg[509]_0 (\not_strict_mode.app_rd_data_reg[509] ),
        .\not_strict_mode.app_rd_data_reg[511]_0 (\not_strict_mode.app_rd_data_reg[511] ),
        .\not_strict_mode.app_rd_data_reg[51]_0 (\not_strict_mode.app_rd_data_reg[51] ),
        .\not_strict_mode.app_rd_data_reg[53]_0 (\not_strict_mode.app_rd_data_reg[53] ),
        .\not_strict_mode.app_rd_data_reg[55]_0 (\not_strict_mode.app_rd_data_reg[55] ),
        .\not_strict_mode.app_rd_data_reg[57]_0 (\not_strict_mode.app_rd_data_reg[57] ),
        .\not_strict_mode.app_rd_data_reg[59]_0 (\not_strict_mode.app_rd_data_reg[59] ),
        .\not_strict_mode.app_rd_data_reg[61]_0 (\not_strict_mode.app_rd_data_reg[61] ),
        .\not_strict_mode.app_rd_data_reg[63]_0 (\not_strict_mode.app_rd_data_reg[63] ),
        .\not_strict_mode.app_rd_data_reg[65]_0 (\not_strict_mode.app_rd_data_reg[65] ),
        .\not_strict_mode.app_rd_data_reg[67]_0 (\not_strict_mode.app_rd_data_reg[67] ),
        .\not_strict_mode.app_rd_data_reg[69]_0 (\not_strict_mode.app_rd_data_reg[69] ),
        .\not_strict_mode.app_rd_data_reg[71]_0 (\not_strict_mode.app_rd_data_reg[71] ),
        .\not_strict_mode.app_rd_data_reg[73]_0 (\not_strict_mode.app_rd_data_reg[73] ),
        .\not_strict_mode.app_rd_data_reg[75]_0 (\not_strict_mode.app_rd_data_reg[75] ),
        .\not_strict_mode.app_rd_data_reg[77]_0 (\not_strict_mode.app_rd_data_reg[77] ),
        .\not_strict_mode.app_rd_data_reg[79]_0 (\not_strict_mode.app_rd_data_reg[79] ),
        .\not_strict_mode.app_rd_data_reg[7]_0 (\not_strict_mode.app_rd_data_reg[7] ),
        .\not_strict_mode.app_rd_data_reg[81]_0 (\not_strict_mode.app_rd_data_reg[81] ),
        .\not_strict_mode.app_rd_data_reg[83]_0 (\not_strict_mode.app_rd_data_reg[83] ),
        .\not_strict_mode.app_rd_data_reg[85]_0 (\not_strict_mode.app_rd_data_reg[85] ),
        .\not_strict_mode.app_rd_data_reg[87]_0 (\not_strict_mode.app_rd_data_reg[87] ),
        .\not_strict_mode.app_rd_data_reg[89]_0 (\not_strict_mode.app_rd_data_reg[89] ),
        .\not_strict_mode.app_rd_data_reg[91]_0 (\not_strict_mode.app_rd_data_reg[91] ),
        .\not_strict_mode.app_rd_data_reg[93]_0 (\not_strict_mode.app_rd_data_reg[93] ),
        .\not_strict_mode.app_rd_data_reg[95]_0 (\not_strict_mode.app_rd_data_reg[95] ),
        .\not_strict_mode.app_rd_data_reg[97]_0 (\not_strict_mode.app_rd_data_reg[97] ),
        .\not_strict_mode.app_rd_data_reg[99]_0 (\not_strict_mode.app_rd_data_reg[99] ),
        .\not_strict_mode.app_rd_data_reg[9]_0 (\not_strict_mode.app_rd_data_reg[9] ),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 (ui_cmd0_n_21),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[2]_0 (ui_cmd0_n_22),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 (occ_cnt_r),
        .\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 (ram_init_done_r),
        .pointer_wr_data(pointer_wr_data),
        .rd_accepted(rd_accepted),
        .rd_buf_we(rd_buf_we),
        .\read_data_indx.rd_data_indx_r_reg[3] (\read_data_indx.rd_data_indx_r_reg__0 ),
        .\read_fifo.fifo_out_data_r_reg[4] (\read_fifo.fifo_out_data_r_reg[4] ),
        .\read_fifo.fifo_out_data_r_reg[7] (\read_fifo.fifo_out_data_r_reg[7] ),
        .reset_reg(reset_reg));
  mig_7series_0_mig_7series_v2_3_ui_wr_data ui_wr_data0
       (.ADDRC(ADDRC),
        .ADDRD(pointer_wr_addr),
        .CLK(CLK),
        .D(ui_rd_data0_n_522),
        .DOB({ui_wr_data0_n_0,ui_wr_data0_n_1}),
        .E(E),
        .Q(\read_data_indx.rd_data_indx_r_reg__0 ),
        .accept_ns(accept_ns),
        .app_rdy_ns(app_rdy_ns),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .\cmd_pipe_plus.wr_data_addr_reg[3] (\cmd_pipe_plus.wr_data_addr_reg[3] ),
        .\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 (\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ),
        .init_calib_complete_reg_rep__19(init_calib_complete_reg_rep__19),
        .init_calib_complete_reg_rep__20(init_calib_complete_reg_rep__20),
        .init_calib_complete_reg_rep__21(init_calib_complete_reg_rep__21),
        .init_calib_complete_reg_rep__22(init_calib_complete_reg_rep__22),
        .init_calib_complete_reg_rep__23(init_calib_complete_reg_rep__23),
        .init_calib_complete_reg_rep__24(init_calib_complete_reg_rep__24),
        .init_calib_complete_reg_rep__25(init_calib_complete_reg_rep__25),
        .init_calib_complete_reg_rep__26(init_calib_complete_reg_rep__26),
        .init_calib_complete_reg_rep__27(init_calib_complete_reg_rep__27),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .pointer_we(pointer_we),
        .pointer_wr_data(pointer_wr_data),
        .ram_init_done_r(ram_init_done_r),
        .\req_data_buf_addr_r_reg[3] ({ui_wr_data0_n_2,ui_wr_data0_n_3}),
        .reset_reg(reset_reg),
        .wr_accepted(wr_accepted));
endmodule

(* ORIG_REF_NAME = "mig_7series_v2_3_ui_wr_data" *) 
module mig_7series_0_mig_7series_v2_3_ui_wr_data
   (DOB,
    \req_data_buf_addr_r_reg[3] ,
    app_wdf_rdy,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    app_rdy_ns,
    Q,
    CLK,
    pointer_we,
    pointer_wr_data,
    ADDRD,
    \cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,
    ADDRC,
    \cmd_pipe_plus.wr_data_addr_reg[3] ,
    E,
    reset_reg,
    app_wdf_end,
    app_wdf_wren,
    wr_accepted,
    init_calib_complete_reg_rep__19,
    init_calib_complete_reg_rep__20,
    init_calib_complete_reg_rep__21,
    init_calib_complete_reg_rep__22,
    init_calib_complete_reg_rep__23,
    init_calib_complete_reg_rep__24,
    init_calib_complete_reg_rep__25,
    init_calib_complete_reg_rep__26,
    init_calib_complete_reg_rep__27,
    accept_ns,
    D,
    ram_init_done_r,
    app_wdf_mask,
    app_wdf_data);
  output [1:0]DOB;
  output [1:0]\req_data_buf_addr_r_reg[3] ;
  output app_wdf_rdy;
  output [47:0]\my_empty_reg[7] ;
  output [575:0]\my_empty_reg[7]_0 ;
  output [47:0]\my_empty_reg[7]_1 ;
  output app_rdy_ns;
  output [3:0]Q;
  input CLK;
  input pointer_we;
  input [3:0]pointer_wr_data;
  input [3:0]ADDRD;
  input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ;
  input [3:0]ADDRC;
  input [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ;
  input [0:0]E;
  input reset_reg;
  input app_wdf_end;
  input app_wdf_wren;
  input wr_accepted;
  input init_calib_complete_reg_rep__19;
  input init_calib_complete_reg_rep__20;
  input init_calib_complete_reg_rep__21;
  input init_calib_complete_reg_rep__22;
  input init_calib_complete_reg_rep__23;
  input init_calib_complete_reg_rep__24;
  input init_calib_complete_reg_rep__25;
  input init_calib_complete_reg_rep__26;
  input init_calib_complete_reg_rep__27;
  input accept_ns;
  input [0:0]D;
  input ram_init_done_r;
  input [63:0]app_wdf_mask;
  input [511:0]app_wdf_data;

  wire [3:0]ADDRC;
  wire [3:0]ADDRD;
  wire CLK;
  wire [0:0]D;
  wire [1:0]DOB;
  wire [0:0]E;
  wire [3:0]Q;
  wire accept_ns;
  wire app_rdy_ns;
  wire app_rdy_r_i_2_n_0;
  wire [511:0]app_wdf_data;
  wire [511:0]app_wdf_data_r1;
  wire app_wdf_end;
  wire app_wdf_end_r1;
  wire app_wdf_end_r1_i_1_n_0;
  wire [63:0]app_wdf_mask;
  wire [63:0]app_wdf_mask_r1;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_wdf_wren_r1;
  wire app_wdf_wren_r1_i_1_n_0;
  wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3] ;
  wire [3:0]\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ;
  wire [3:0]\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 ;
  wire init_calib_complete_reg_rep__19;
  wire init_calib_complete_reg_rep__20;
  wire init_calib_complete_reg_rep__21;
  wire init_calib_complete_reg_rep__22;
  wire init_calib_complete_reg_rep__23;
  wire init_calib_complete_reg_rep__24;
  wire init_calib_complete_reg_rep__25;
  wire init_calib_complete_reg_rep__26;
  wire init_calib_complete_reg_rep__27;
  wire [47:0]\my_empty_reg[7] ;
  wire [575:0]\my_empty_reg[7]_0 ;
  wire [47:0]\my_empty_reg[7]_1 ;
  wire \occupied_counter.occ_cnt[0]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[10]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[11]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[12]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[13]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[14]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[15]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[15]_i_2_n_0 ;
  wire \occupied_counter.occ_cnt[1]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[2]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[3]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[4]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[5]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[6]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[7]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[8]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt[9]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt_reg_n_0_[0] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[10] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[11] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[12] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[13] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[15] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[1] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[2] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[3] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[4] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[5] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[6] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[7] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[8] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[9] ;
  wire [3:0]p_0_in;
  wire [0:0]p_0_in_0;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__1;
  wire [1:0]p_100_out;
  wire [1:0]p_101_out;
  wire [1:0]p_102_out;
  wire [1:0]p_103_out;
  wire [1:0]p_104_out;
  wire [1:0]p_105_out;
  wire [1:0]p_106_out;
  wire [1:0]p_107_out;
  wire [1:0]p_108_out;
  wire [1:0]p_109_out;
  wire [1:0]p_10_out;
  wire [1:0]p_110_out;
  wire [1:0]p_111_out;
  wire [1:0]p_112_out;
  wire [1:0]p_113_out;
  wire [1:0]p_114_out;
  wire [1:0]p_115_out;
  wire [1:0]p_116_out;
  wire [1:0]p_117_out;
  wire [1:0]p_118_out;
  wire [1:0]p_119_out;
  wire [1:0]p_11_out;
  wire [1:0]p_120_out;
  wire [1:0]p_121_out;
  wire [1:0]p_122_out;
  wire [1:0]p_123_out;
  wire [1:0]p_124_out;
  wire [1:0]p_125_out;
  wire [1:0]p_126_out;
  wire [1:0]p_127_out;
  wire [1:0]p_128_out;
  wire [1:0]p_129_out;
  wire [1:0]p_12_out;
  wire [1:0]p_130_out;
  wire [1:0]p_131_out;
  wire [1:0]p_132_out;
  wire [1:0]p_133_out;
  wire [1:0]p_134_out;
  wire [1:0]p_135_out;
  wire [1:0]p_136_out;
  wire [1:0]p_137_out;
  wire [1:0]p_138_out;
  wire [1:0]p_139_out;
  wire [1:0]p_13_out;
  wire [1:0]p_140_out;
  wire [1:0]p_141_out;
  wire [1:0]p_142_out;
  wire [1:0]p_143_out;
  wire [1:0]p_144_out;
  wire [1:0]p_145_out;
  wire [1:0]p_146_out;
  wire [1:0]p_147_out;
  wire [1:0]p_148_out;
  wire [1:0]p_149_out;
  wire [1:0]p_14_out;
  wire [1:0]p_150_out;
  wire [1:0]p_151_out;
  wire [1:0]p_152_out;
  wire [1:0]p_153_out;
  wire [1:0]p_154_out;
  wire [1:0]p_155_out;
  wire [1:0]p_156_out;
  wire [1:0]p_157_out;
  wire [1:0]p_158_out;
  wire [1:0]p_159_out;
  wire [1:0]p_15_out;
  wire [1:0]p_160_out;
  wire [1:0]p_161_out;
  wire [1:0]p_162_out;
  wire [1:0]p_163_out;
  wire [1:0]p_164_out;
  wire [1:0]p_165_out;
  wire [1:0]p_166_out;
  wire [1:0]p_167_out;
  wire [1:0]p_168_out;
  wire [1:0]p_169_out;
  wire [1:0]p_16_out;
  wire [1:0]p_170_out;
  wire [1:0]p_171_out;
  wire [1:0]p_172_out;
  wire [1:0]p_173_out;
  wire [1:0]p_174_out;
  wire [1:0]p_175_out;
  wire [1:0]p_176_out;
  wire [1:0]p_177_out;
  wire [1:0]p_178_out;
  wire [1:0]p_179_out;
  wire [1:0]p_17_out;
  wire [1:0]p_180_out;
  wire [1:0]p_181_out;
  wire [1:0]p_182_out;
  wire [1:0]p_183_out;
  wire [1:0]p_184_out;
  wire [1:0]p_185_out;
  wire [1:0]p_186_out;
  wire [1:0]p_187_out;
  wire [1:0]p_188_out;
  wire [1:0]p_189_out;
  wire [1:0]p_18_out;
  wire [1:0]p_190_out;
  wire [1:0]p_191_out;
  wire [1:0]p_192_out;
  wire [1:0]p_193_out;
  wire [1:0]p_194_out;
  wire [1:0]p_195_out;
  wire [1:0]p_196_out;
  wire [1:0]p_197_out;
  wire [1:0]p_198_out;
  wire [1:0]p_199_out;
  wire [1:0]p_19_out;
  wire [1:0]p_200_out;
  wire [1:0]p_201_out;
  wire [1:0]p_202_out;
  wire [1:0]p_203_out;
  wire [1:0]p_204_out;
  wire [1:0]p_205_out;
  wire [1:0]p_206_out;
  wire [1:0]p_207_out;
  wire [1:0]p_208_out;
  wire [1:0]p_209_out;
  wire [1:0]p_20_out;
  wire [1:0]p_210_out;
  wire [1:0]p_211_out;
  wire [1:0]p_212_out;
  wire [1:0]p_213_out;
  wire [1:0]p_214_out;
  wire [1:0]p_215_out;
  wire [1:0]p_216_out;
  wire [1:0]p_217_out;
  wire [1:0]p_218_out;
  wire [1:0]p_219_out;
  wire [1:0]p_21_out;
  wire [1:0]p_220_out;
  wire [1:0]p_221_out;
  wire [1:0]p_222_out;
  wire [1:0]p_223_out;
  wire [1:0]p_224_out;
  wire [1:0]p_225_out;
  wire [1:0]p_226_out;
  wire [1:0]p_227_out;
  wire [1:0]p_228_out;
  wire [1:0]p_229_out;
  wire [1:0]p_22_out;
  wire [1:0]p_230_out;
  wire [1:0]p_231_out;
  wire [1:0]p_232_out;
  wire [1:0]p_233_out;
  wire [1:0]p_234_out;
  wire [1:0]p_235_out;
  wire [1:0]p_236_out;
  wire [1:0]p_237_out;
  wire [1:0]p_238_out;
  wire [1:0]p_239_out;
  wire [1:0]p_23_out;
  wire [1:0]p_240_out;
  wire [1:0]p_241_out;
  wire [1:0]p_242_out;
  wire [1:0]p_243_out;
  wire [1:0]p_244_out;
  wire [1:0]p_245_out;
  wire [1:0]p_246_out;
  wire [1:0]p_247_out;
  wire [1:0]p_248_out;
  wire [1:0]p_249_out;
  wire [1:0]p_24_out;
  wire [1:0]p_250_out;
  wire [1:0]p_251_out;
  wire [1:0]p_252_out;
  wire [1:0]p_253_out;
  wire [1:0]p_254_out;
  wire [1:0]p_255_out;
  wire [1:0]p_256_out;
  wire [1:0]p_257_out;
  wire [1:0]p_258_out;
  wire [1:0]p_259_out;
  wire [1:0]p_25_out;
  wire [1:0]p_260_out;
  wire [1:0]p_261_out;
  wire [1:0]p_262_out;
  wire [1:0]p_263_out;
  wire [1:0]p_264_out;
  wire [1:0]p_265_out;
  wire [1:0]p_266_out;
  wire [1:0]p_267_out;
  wire [1:0]p_268_out;
  wire [1:0]p_269_out;
  wire [1:0]p_26_out;
  wire [1:0]p_270_out;
  wire [1:0]p_271_out;
  wire [1:0]p_272_out;
  wire [1:0]p_273_out;
  wire [1:0]p_274_out;
  wire [1:0]p_275_out;
  wire [1:0]p_276_out;
  wire [1:0]p_277_out;
  wire [1:0]p_278_out;
  wire [1:0]p_279_out;
  wire [1:0]p_27_out;
  wire [1:0]p_280_out;
  wire [1:0]p_281_out;
  wire [1:0]p_282_out;
  wire [1:0]p_283_out;
  wire [1:0]p_284_out;
  wire [1:0]p_285_out;
  wire [1:0]p_286_out;
  wire [1:0]p_287_out;
  wire [1:0]p_28_out;
  wire [1:0]p_29_out;
  wire [1:0]p_30_out;
  wire [1:0]p_31_out;
  wire [1:0]p_32_out;
  wire [1:0]p_33_out;
  wire [1:0]p_34_out;
  wire [1:0]p_35_out;
  wire [1:0]p_36_out;
  wire [1:0]p_37_out;
  wire [1:0]p_38_out;
  wire [1:0]p_39_out;
  wire [1:0]p_40_out;
  wire [1:0]p_41_out;
  wire [1:0]p_42_out;
  wire [1:0]p_43_out;
  wire [1:0]p_44_out;
  wire [1:0]p_45_out;
  wire [1:0]p_46_out;
  wire [1:0]p_47_out;
  wire [1:0]p_48_out;
  wire [1:0]p_49_out;
  wire p_4_in;
  wire [1:0]p_4_out;
  wire [1:0]p_50_out;
  wire [1:0]p_51_out;
  wire [1:0]p_52_out;
  wire [1:0]p_53_out;
  wire [1:0]p_54_out;
  wire [1:0]p_55_out;
  wire [1:0]p_56_out;
  wire [1:0]p_57_out;
  wire [1:0]p_58_out;
  wire [1:0]p_59_out;
  wire [1:0]p_5_out;
  wire [1:0]p_60_out;
  wire [1:0]p_61_out;
  wire [1:0]p_62_out;
  wire [1:0]p_63_out;
  wire [1:0]p_64_out;
  wire [1:0]p_65_out;
  wire [1:0]p_66_out;
  wire [1:0]p_67_out;
  wire [1:0]p_68_out;
  wire [1:0]p_69_out;
  wire [1:0]p_6_out;
  wire [1:0]p_70_out;
  wire [1:0]p_71_out;
  wire [1:0]p_72_out;
  wire [1:0]p_73_out;
  wire [1:0]p_74_out;
  wire [1:0]p_75_out;
  wire [1:0]p_76_out;
  wire [1:0]p_77_out;
  wire [1:0]p_78_out;
  wire [1:0]p_79_out;
  wire [1:0]p_7_out;
  wire [1:0]p_80_out;
  wire [1:0]p_81_out;
  wire [1:0]p_82_out;
  wire [1:0]p_83_out;
  wire [1:0]p_84_out;
  wire [1:0]p_85_out;
  wire [1:0]p_86_out;
  wire [1:0]p_87_out;
  wire [1:0]p_88_out;
  wire [1:0]p_89_out;
  wire [1:0]p_8_out;
  wire [1:0]p_90_out;
  wire [1:0]p_91_out;
  wire [1:0]p_92_out;
  wire [1:0]p_93_out;
  wire [1:0]p_94_out;
  wire [1:0]p_95_out;
  wire [1:0]p_96_out;
  wire [1:0]p_97_out;
  wire [1:0]p_98_out;
  wire [1:0]p_99_out;
  wire [1:0]p_9_out;
  wire pointer_we;
  wire [3:0]pointer_wr_data;
  wire ram_init_done_r;
  wire [1:0]\req_data_buf_addr_r_reg[3] ;
  wire reset_reg;
  wire wb_wr_data_addr0_r;
  wire [4:1]wb_wr_data_addr_r;
  wire [4:1]wb_wr_data_addr_w;
  wire wdf_rdy_ns;
  wire wr_accepted;
  wire [575:0]wr_buf_in_data;
  wire wr_data_addr_le;
  wire [3:0]wr_data_pntr;
  wire [4:0]wr_req_cnt_r;
  wire \wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[3]_i_2_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ;
  wire \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 ;
  wire \write_buffer.wr_buffer_ram[94].RAM32M0_n_4 ;
  wire \write_buffer.wr_buffer_ram[94].RAM32M0_n_5 ;
  wire \write_buffer.wr_buffer_ram[95].RAM32M0_n_0 ;
  wire \write_buffer.wr_buffer_ram[95].RAM32M0_n_1 ;
  wire \write_buffer.wr_buffer_ram[95].RAM32M0_n_2 ;
  wire \write_buffer.wr_buffer_ram[95].RAM32M0_n_3 ;
  wire \write_buffer.wr_buffer_ram[95].RAM32M0_n_4 ;
  wire \write_buffer.wr_buffer_ram[95].RAM32M0_n_5 ;
  wire \write_data_control.wb_wr_data_addr0_r_i_1_n_0 ;
  wire \write_data_control.wb_wr_data_addr_r[4]_i_2_n_0 ;
  wire [3:0]\write_data_control.wr_data_indx_r_reg__0 ;
  wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;

  LUT5 #(
    .INIT(32'h0000FB00)) 
    app_rdy_r_i_1
       (.I0(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),
        .I1(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ),
        .I2(app_rdy_r_i_2_n_0),
        .I3(accept_ns),
        .I4(D),
        .O(app_rdy_ns));
  LUT6 #(
    .INIT(64'h3333133332233332)) 
    app_rdy_r_i_2
       (.I0(wr_req_cnt_r[2]),
        .I1(reset_reg),
        .I2(wr_req_cnt_r[0]),
        .I3(wr_accepted),
        .I4(p_0_in_0),
        .I5(wr_req_cnt_r[1]),
        .O(app_rdy_r_i_2_n_0));
  FDRE \app_wdf_data_r1_reg[0] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[0]),
        .Q(app_wdf_data_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[100] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[100]),
        .Q(app_wdf_data_r1[100]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[101] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[101]),
        .Q(app_wdf_data_r1[101]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[102] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[102]),
        .Q(app_wdf_data_r1[102]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[103] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[103]),
        .Q(app_wdf_data_r1[103]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[104] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[104]),
        .Q(app_wdf_data_r1[104]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[105] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[105]),
        .Q(app_wdf_data_r1[105]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[106] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[106]),
        .Q(app_wdf_data_r1[106]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[107] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[107]),
        .Q(app_wdf_data_r1[107]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[108] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[108]),
        .Q(app_wdf_data_r1[108]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[109] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[109]),
        .Q(app_wdf_data_r1[109]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[10] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[10]),
        .Q(app_wdf_data_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[110] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[110]),
        .Q(app_wdf_data_r1[110]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[111] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[111]),
        .Q(app_wdf_data_r1[111]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[112] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[112]),
        .Q(app_wdf_data_r1[112]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[113] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[113]),
        .Q(app_wdf_data_r1[113]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[114] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[114]),
        .Q(app_wdf_data_r1[114]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[115] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[115]),
        .Q(app_wdf_data_r1[115]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[116] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[116]),
        .Q(app_wdf_data_r1[116]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[117] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[117]),
        .Q(app_wdf_data_r1[117]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[118] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[118]),
        .Q(app_wdf_data_r1[118]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[119] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[119]),
        .Q(app_wdf_data_r1[119]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[11] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[11]),
        .Q(app_wdf_data_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[120] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[120]),
        .Q(app_wdf_data_r1[120]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[121] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[121]),
        .Q(app_wdf_data_r1[121]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[122] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[122]),
        .Q(app_wdf_data_r1[122]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[123] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[123]),
        .Q(app_wdf_data_r1[123]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[124] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[124]),
        .Q(app_wdf_data_r1[124]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[125] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[125]),
        .Q(app_wdf_data_r1[125]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[126] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[126]),
        .Q(app_wdf_data_r1[126]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[127] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[127]),
        .Q(app_wdf_data_r1[127]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[128] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[128]),
        .Q(app_wdf_data_r1[128]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[129] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[129]),
        .Q(app_wdf_data_r1[129]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[12] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[12]),
        .Q(app_wdf_data_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[130] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[130]),
        .Q(app_wdf_data_r1[130]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[131] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[131]),
        .Q(app_wdf_data_r1[131]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[132] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[132]),
        .Q(app_wdf_data_r1[132]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[133] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[133]),
        .Q(app_wdf_data_r1[133]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[134] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[134]),
        .Q(app_wdf_data_r1[134]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[135] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[135]),
        .Q(app_wdf_data_r1[135]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[136] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[136]),
        .Q(app_wdf_data_r1[136]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[137] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[137]),
        .Q(app_wdf_data_r1[137]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[138] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[138]),
        .Q(app_wdf_data_r1[138]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[139] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[139]),
        .Q(app_wdf_data_r1[139]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[13] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[13]),
        .Q(app_wdf_data_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[140] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[140]),
        .Q(app_wdf_data_r1[140]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[141] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[141]),
        .Q(app_wdf_data_r1[141]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[142] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[142]),
        .Q(app_wdf_data_r1[142]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[143] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[143]),
        .Q(app_wdf_data_r1[143]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[144] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[144]),
        .Q(app_wdf_data_r1[144]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[145] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[145]),
        .Q(app_wdf_data_r1[145]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[146] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[146]),
        .Q(app_wdf_data_r1[146]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[147] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[147]),
        .Q(app_wdf_data_r1[147]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[148] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[148]),
        .Q(app_wdf_data_r1[148]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[149] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[149]),
        .Q(app_wdf_data_r1[149]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[14] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[14]),
        .Q(app_wdf_data_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[150] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[150]),
        .Q(app_wdf_data_r1[150]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[151] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[151]),
        .Q(app_wdf_data_r1[151]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[152] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[152]),
        .Q(app_wdf_data_r1[152]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[153] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[153]),
        .Q(app_wdf_data_r1[153]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[154] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[154]),
        .Q(app_wdf_data_r1[154]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[155] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[155]),
        .Q(app_wdf_data_r1[155]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[156] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[156]),
        .Q(app_wdf_data_r1[156]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[157] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[157]),
        .Q(app_wdf_data_r1[157]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[158] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[158]),
        .Q(app_wdf_data_r1[158]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[159] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[159]),
        .Q(app_wdf_data_r1[159]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[15] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[15]),
        .Q(app_wdf_data_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[160] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[160]),
        .Q(app_wdf_data_r1[160]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[161] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[161]),
        .Q(app_wdf_data_r1[161]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[162] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[162]),
        .Q(app_wdf_data_r1[162]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[163] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[163]),
        .Q(app_wdf_data_r1[163]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[164] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[164]),
        .Q(app_wdf_data_r1[164]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[165] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[165]),
        .Q(app_wdf_data_r1[165]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[166] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[166]),
        .Q(app_wdf_data_r1[166]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[167] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[167]),
        .Q(app_wdf_data_r1[167]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[168] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[168]),
        .Q(app_wdf_data_r1[168]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[169] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[169]),
        .Q(app_wdf_data_r1[169]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[16] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[16]),
        .Q(app_wdf_data_r1[16]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[170] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[170]),
        .Q(app_wdf_data_r1[170]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[171] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[171]),
        .Q(app_wdf_data_r1[171]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[172] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[172]),
        .Q(app_wdf_data_r1[172]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[173] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[173]),
        .Q(app_wdf_data_r1[173]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[174] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[174]),
        .Q(app_wdf_data_r1[174]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[175] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[175]),
        .Q(app_wdf_data_r1[175]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[176] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[176]),
        .Q(app_wdf_data_r1[176]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[177] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[177]),
        .Q(app_wdf_data_r1[177]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[178] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[178]),
        .Q(app_wdf_data_r1[178]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[179] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[179]),
        .Q(app_wdf_data_r1[179]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[17] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[17]),
        .Q(app_wdf_data_r1[17]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[180] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[180]),
        .Q(app_wdf_data_r1[180]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[181] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[181]),
        .Q(app_wdf_data_r1[181]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[182] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[182]),
        .Q(app_wdf_data_r1[182]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[183] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[183]),
        .Q(app_wdf_data_r1[183]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[184] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[184]),
        .Q(app_wdf_data_r1[184]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[185] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[185]),
        .Q(app_wdf_data_r1[185]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[186] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[186]),
        .Q(app_wdf_data_r1[186]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[187] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[187]),
        .Q(app_wdf_data_r1[187]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[188] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[188]),
        .Q(app_wdf_data_r1[188]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[189] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[189]),
        .Q(app_wdf_data_r1[189]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[18] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[18]),
        .Q(app_wdf_data_r1[18]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[190] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[190]),
        .Q(app_wdf_data_r1[190]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[191] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[191]),
        .Q(app_wdf_data_r1[191]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[192] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[192]),
        .Q(app_wdf_data_r1[192]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[193] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[193]),
        .Q(app_wdf_data_r1[193]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[194] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[194]),
        .Q(app_wdf_data_r1[194]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[195] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[195]),
        .Q(app_wdf_data_r1[195]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[196] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[196]),
        .Q(app_wdf_data_r1[196]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[197] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[197]),
        .Q(app_wdf_data_r1[197]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[198] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[198]),
        .Q(app_wdf_data_r1[198]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[199] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[199]),
        .Q(app_wdf_data_r1[199]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[19] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[19]),
        .Q(app_wdf_data_r1[19]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[1] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[1]),
        .Q(app_wdf_data_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[200] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[200]),
        .Q(app_wdf_data_r1[200]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[201] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[201]),
        .Q(app_wdf_data_r1[201]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[202] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[202]),
        .Q(app_wdf_data_r1[202]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[203] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[203]),
        .Q(app_wdf_data_r1[203]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[204] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[204]),
        .Q(app_wdf_data_r1[204]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[205] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[205]),
        .Q(app_wdf_data_r1[205]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[206] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[206]),
        .Q(app_wdf_data_r1[206]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[207] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[207]),
        .Q(app_wdf_data_r1[207]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[208] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[208]),
        .Q(app_wdf_data_r1[208]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[209] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[209]),
        .Q(app_wdf_data_r1[209]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[20] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[20]),
        .Q(app_wdf_data_r1[20]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[210] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[210]),
        .Q(app_wdf_data_r1[210]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[211] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[211]),
        .Q(app_wdf_data_r1[211]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[212] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[212]),
        .Q(app_wdf_data_r1[212]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[213] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[213]),
        .Q(app_wdf_data_r1[213]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[214] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[214]),
        .Q(app_wdf_data_r1[214]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[215] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[215]),
        .Q(app_wdf_data_r1[215]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[216] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[216]),
        .Q(app_wdf_data_r1[216]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[217] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[217]),
        .Q(app_wdf_data_r1[217]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[218] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[218]),
        .Q(app_wdf_data_r1[218]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[219] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[219]),
        .Q(app_wdf_data_r1[219]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[21] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[21]),
        .Q(app_wdf_data_r1[21]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[220] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[220]),
        .Q(app_wdf_data_r1[220]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[221] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[221]),
        .Q(app_wdf_data_r1[221]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[222] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[222]),
        .Q(app_wdf_data_r1[222]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[223] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[223]),
        .Q(app_wdf_data_r1[223]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[224] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[224]),
        .Q(app_wdf_data_r1[224]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[225] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[225]),
        .Q(app_wdf_data_r1[225]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[226] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[226]),
        .Q(app_wdf_data_r1[226]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[227] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[227]),
        .Q(app_wdf_data_r1[227]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[228] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[228]),
        .Q(app_wdf_data_r1[228]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[229] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[229]),
        .Q(app_wdf_data_r1[229]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[22] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[22]),
        .Q(app_wdf_data_r1[22]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[230] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[230]),
        .Q(app_wdf_data_r1[230]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[231] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[231]),
        .Q(app_wdf_data_r1[231]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[232] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[232]),
        .Q(app_wdf_data_r1[232]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[233] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[233]),
        .Q(app_wdf_data_r1[233]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[234] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[234]),
        .Q(app_wdf_data_r1[234]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[235] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[235]),
        .Q(app_wdf_data_r1[235]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[236] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[236]),
        .Q(app_wdf_data_r1[236]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[237] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[237]),
        .Q(app_wdf_data_r1[237]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[238] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[238]),
        .Q(app_wdf_data_r1[238]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[239] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[239]),
        .Q(app_wdf_data_r1[239]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[23] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[23]),
        .Q(app_wdf_data_r1[23]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[240] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[240]),
        .Q(app_wdf_data_r1[240]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[241] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[241]),
        .Q(app_wdf_data_r1[241]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[242] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[242]),
        .Q(app_wdf_data_r1[242]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[243] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[243]),
        .Q(app_wdf_data_r1[243]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[244] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[244]),
        .Q(app_wdf_data_r1[244]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[245] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[245]),
        .Q(app_wdf_data_r1[245]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[246] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[246]),
        .Q(app_wdf_data_r1[246]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[247] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[247]),
        .Q(app_wdf_data_r1[247]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[248] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[248]),
        .Q(app_wdf_data_r1[248]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[249] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[249]),
        .Q(app_wdf_data_r1[249]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[24] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[24]),
        .Q(app_wdf_data_r1[24]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[250] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[250]),
        .Q(app_wdf_data_r1[250]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[251] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[251]),
        .Q(app_wdf_data_r1[251]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[252] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[252]),
        .Q(app_wdf_data_r1[252]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[253] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[253]),
        .Q(app_wdf_data_r1[253]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[254] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[254]),
        .Q(app_wdf_data_r1[254]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[255] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[255]),
        .Q(app_wdf_data_r1[255]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[256] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[256]),
        .Q(app_wdf_data_r1[256]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[257] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[257]),
        .Q(app_wdf_data_r1[257]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[258] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[258]),
        .Q(app_wdf_data_r1[258]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[259] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[259]),
        .Q(app_wdf_data_r1[259]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[25] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[25]),
        .Q(app_wdf_data_r1[25]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[260] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[260]),
        .Q(app_wdf_data_r1[260]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[261] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[261]),
        .Q(app_wdf_data_r1[261]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[262] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[262]),
        .Q(app_wdf_data_r1[262]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[263] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[263]),
        .Q(app_wdf_data_r1[263]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[264] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[264]),
        .Q(app_wdf_data_r1[264]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[265] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[265]),
        .Q(app_wdf_data_r1[265]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[266] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[266]),
        .Q(app_wdf_data_r1[266]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[267] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[267]),
        .Q(app_wdf_data_r1[267]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[268] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[268]),
        .Q(app_wdf_data_r1[268]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[269] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[269]),
        .Q(app_wdf_data_r1[269]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[26] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[26]),
        .Q(app_wdf_data_r1[26]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[270] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[270]),
        .Q(app_wdf_data_r1[270]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[271] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[271]),
        .Q(app_wdf_data_r1[271]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[272] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[272]),
        .Q(app_wdf_data_r1[272]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[273] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[273]),
        .Q(app_wdf_data_r1[273]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[274] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[274]),
        .Q(app_wdf_data_r1[274]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[275] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[275]),
        .Q(app_wdf_data_r1[275]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[276] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[276]),
        .Q(app_wdf_data_r1[276]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[277] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[277]),
        .Q(app_wdf_data_r1[277]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[278] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[278]),
        .Q(app_wdf_data_r1[278]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[279] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[279]),
        .Q(app_wdf_data_r1[279]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[27] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[27]),
        .Q(app_wdf_data_r1[27]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[280] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[280]),
        .Q(app_wdf_data_r1[280]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[281] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[281]),
        .Q(app_wdf_data_r1[281]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[282] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[282]),
        .Q(app_wdf_data_r1[282]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[283] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[283]),
        .Q(app_wdf_data_r1[283]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[284] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[284]),
        .Q(app_wdf_data_r1[284]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[285] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[285]),
        .Q(app_wdf_data_r1[285]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[286] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[286]),
        .Q(app_wdf_data_r1[286]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[287] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[287]),
        .Q(app_wdf_data_r1[287]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[288] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[288]),
        .Q(app_wdf_data_r1[288]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[289] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[289]),
        .Q(app_wdf_data_r1[289]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[28] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[28]),
        .Q(app_wdf_data_r1[28]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[290] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[290]),
        .Q(app_wdf_data_r1[290]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[291] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[291]),
        .Q(app_wdf_data_r1[291]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[292] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[292]),
        .Q(app_wdf_data_r1[292]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[293] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[293]),
        .Q(app_wdf_data_r1[293]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[294] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[294]),
        .Q(app_wdf_data_r1[294]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[295] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[295]),
        .Q(app_wdf_data_r1[295]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[296] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[296]),
        .Q(app_wdf_data_r1[296]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[297] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[297]),
        .Q(app_wdf_data_r1[297]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[298] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[298]),
        .Q(app_wdf_data_r1[298]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[299] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[299]),
        .Q(app_wdf_data_r1[299]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[29] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[29]),
        .Q(app_wdf_data_r1[29]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[2] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[2]),
        .Q(app_wdf_data_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[300] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[300]),
        .Q(app_wdf_data_r1[300]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[301] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[301]),
        .Q(app_wdf_data_r1[301]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[302] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[302]),
        .Q(app_wdf_data_r1[302]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[303] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[303]),
        .Q(app_wdf_data_r1[303]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[304] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[304]),
        .Q(app_wdf_data_r1[304]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[305] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[305]),
        .Q(app_wdf_data_r1[305]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[306] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[306]),
        .Q(app_wdf_data_r1[306]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[307] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[307]),
        .Q(app_wdf_data_r1[307]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[308] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[308]),
        .Q(app_wdf_data_r1[308]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[309] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[309]),
        .Q(app_wdf_data_r1[309]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[30] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[30]),
        .Q(app_wdf_data_r1[30]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[310] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[310]),
        .Q(app_wdf_data_r1[310]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[311] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[311]),
        .Q(app_wdf_data_r1[311]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[312] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[312]),
        .Q(app_wdf_data_r1[312]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[313] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[313]),
        .Q(app_wdf_data_r1[313]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[314] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[314]),
        .Q(app_wdf_data_r1[314]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[315] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[315]),
        .Q(app_wdf_data_r1[315]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[316] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[316]),
        .Q(app_wdf_data_r1[316]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[317] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[317]),
        .Q(app_wdf_data_r1[317]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[318] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[318]),
        .Q(app_wdf_data_r1[318]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[319] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[319]),
        .Q(app_wdf_data_r1[319]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[31] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[31]),
        .Q(app_wdf_data_r1[31]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[320] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[320]),
        .Q(app_wdf_data_r1[320]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[321] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[321]),
        .Q(app_wdf_data_r1[321]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[322] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[322]),
        .Q(app_wdf_data_r1[322]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[323] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[323]),
        .Q(app_wdf_data_r1[323]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[324] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[324]),
        .Q(app_wdf_data_r1[324]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[325] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[325]),
        .Q(app_wdf_data_r1[325]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[326] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[326]),
        .Q(app_wdf_data_r1[326]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[327] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[327]),
        .Q(app_wdf_data_r1[327]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[328] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[328]),
        .Q(app_wdf_data_r1[328]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[329] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[329]),
        .Q(app_wdf_data_r1[329]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[32] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[32]),
        .Q(app_wdf_data_r1[32]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[330] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[330]),
        .Q(app_wdf_data_r1[330]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[331] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[331]),
        .Q(app_wdf_data_r1[331]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[332] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[332]),
        .Q(app_wdf_data_r1[332]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[333] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[333]),
        .Q(app_wdf_data_r1[333]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[334] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[334]),
        .Q(app_wdf_data_r1[334]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[335] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[335]),
        .Q(app_wdf_data_r1[335]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[336] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[336]),
        .Q(app_wdf_data_r1[336]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[337] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[337]),
        .Q(app_wdf_data_r1[337]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[338] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[338]),
        .Q(app_wdf_data_r1[338]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[339] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[339]),
        .Q(app_wdf_data_r1[339]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[33] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[33]),
        .Q(app_wdf_data_r1[33]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[340] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[340]),
        .Q(app_wdf_data_r1[340]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[341] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[341]),
        .Q(app_wdf_data_r1[341]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[342] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[342]),
        .Q(app_wdf_data_r1[342]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[343] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[343]),
        .Q(app_wdf_data_r1[343]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[344] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[344]),
        .Q(app_wdf_data_r1[344]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[345] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[345]),
        .Q(app_wdf_data_r1[345]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[346] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[346]),
        .Q(app_wdf_data_r1[346]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[347] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[347]),
        .Q(app_wdf_data_r1[347]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[348] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[348]),
        .Q(app_wdf_data_r1[348]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[349] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[349]),
        .Q(app_wdf_data_r1[349]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[34] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[34]),
        .Q(app_wdf_data_r1[34]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[350] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[350]),
        .Q(app_wdf_data_r1[350]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[351] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[351]),
        .Q(app_wdf_data_r1[351]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[352] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[352]),
        .Q(app_wdf_data_r1[352]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[353] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[353]),
        .Q(app_wdf_data_r1[353]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[354] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[354]),
        .Q(app_wdf_data_r1[354]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[355] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[355]),
        .Q(app_wdf_data_r1[355]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[356] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[356]),
        .Q(app_wdf_data_r1[356]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[357] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[357]),
        .Q(app_wdf_data_r1[357]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[358] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[358]),
        .Q(app_wdf_data_r1[358]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[359] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[359]),
        .Q(app_wdf_data_r1[359]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[35] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[35]),
        .Q(app_wdf_data_r1[35]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[360] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[360]),
        .Q(app_wdf_data_r1[360]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[361] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[361]),
        .Q(app_wdf_data_r1[361]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[362] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[362]),
        .Q(app_wdf_data_r1[362]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[363] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[363]),
        .Q(app_wdf_data_r1[363]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[364] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[364]),
        .Q(app_wdf_data_r1[364]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[365] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[365]),
        .Q(app_wdf_data_r1[365]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[366] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[366]),
        .Q(app_wdf_data_r1[366]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[367] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[367]),
        .Q(app_wdf_data_r1[367]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[368] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[368]),
        .Q(app_wdf_data_r1[368]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[369] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[369]),
        .Q(app_wdf_data_r1[369]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[36] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[36]),
        .Q(app_wdf_data_r1[36]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[370] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[370]),
        .Q(app_wdf_data_r1[370]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[371] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[371]),
        .Q(app_wdf_data_r1[371]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[372] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[372]),
        .Q(app_wdf_data_r1[372]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[373] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[373]),
        .Q(app_wdf_data_r1[373]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[374] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[374]),
        .Q(app_wdf_data_r1[374]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[375] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[375]),
        .Q(app_wdf_data_r1[375]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[376] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[376]),
        .Q(app_wdf_data_r1[376]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[377] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[377]),
        .Q(app_wdf_data_r1[377]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[378] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[378]),
        .Q(app_wdf_data_r1[378]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[379] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[379]),
        .Q(app_wdf_data_r1[379]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[37] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[37]),
        .Q(app_wdf_data_r1[37]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[380] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[380]),
        .Q(app_wdf_data_r1[380]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[381] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[381]),
        .Q(app_wdf_data_r1[381]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[382] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[382]),
        .Q(app_wdf_data_r1[382]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[383] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[383]),
        .Q(app_wdf_data_r1[383]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[384] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[384]),
        .Q(app_wdf_data_r1[384]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[385] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[385]),
        .Q(app_wdf_data_r1[385]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[386] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[386]),
        .Q(app_wdf_data_r1[386]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[387] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[387]),
        .Q(app_wdf_data_r1[387]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[388] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[388]),
        .Q(app_wdf_data_r1[388]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[389] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[389]),
        .Q(app_wdf_data_r1[389]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[38] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[38]),
        .Q(app_wdf_data_r1[38]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[390] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[390]),
        .Q(app_wdf_data_r1[390]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[391] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[391]),
        .Q(app_wdf_data_r1[391]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[392] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[392]),
        .Q(app_wdf_data_r1[392]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[393] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[393]),
        .Q(app_wdf_data_r1[393]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[394] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[394]),
        .Q(app_wdf_data_r1[394]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[395] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[395]),
        .Q(app_wdf_data_r1[395]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[396] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[396]),
        .Q(app_wdf_data_r1[396]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[397] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[397]),
        .Q(app_wdf_data_r1[397]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[398] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[398]),
        .Q(app_wdf_data_r1[398]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[399] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[399]),
        .Q(app_wdf_data_r1[399]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[39] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[39]),
        .Q(app_wdf_data_r1[39]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[3] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[3]),
        .Q(app_wdf_data_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[400] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[400]),
        .Q(app_wdf_data_r1[400]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[401] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[401]),
        .Q(app_wdf_data_r1[401]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[402] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[402]),
        .Q(app_wdf_data_r1[402]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[403] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[403]),
        .Q(app_wdf_data_r1[403]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[404] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[404]),
        .Q(app_wdf_data_r1[404]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[405] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[405]),
        .Q(app_wdf_data_r1[405]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[406] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[406]),
        .Q(app_wdf_data_r1[406]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[407] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[407]),
        .Q(app_wdf_data_r1[407]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[408] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[408]),
        .Q(app_wdf_data_r1[408]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[409] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[409]),
        .Q(app_wdf_data_r1[409]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[40] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[40]),
        .Q(app_wdf_data_r1[40]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[410] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[410]),
        .Q(app_wdf_data_r1[410]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[411] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[411]),
        .Q(app_wdf_data_r1[411]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[412] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[412]),
        .Q(app_wdf_data_r1[412]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[413] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[413]),
        .Q(app_wdf_data_r1[413]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[414] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[414]),
        .Q(app_wdf_data_r1[414]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[415] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[415]),
        .Q(app_wdf_data_r1[415]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[416] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[416]),
        .Q(app_wdf_data_r1[416]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[417] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[417]),
        .Q(app_wdf_data_r1[417]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[418] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[418]),
        .Q(app_wdf_data_r1[418]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[419] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[419]),
        .Q(app_wdf_data_r1[419]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[41] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[41]),
        .Q(app_wdf_data_r1[41]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[420] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[420]),
        .Q(app_wdf_data_r1[420]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[421] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[421]),
        .Q(app_wdf_data_r1[421]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[422] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[422]),
        .Q(app_wdf_data_r1[422]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[423] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[423]),
        .Q(app_wdf_data_r1[423]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[424] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[424]),
        .Q(app_wdf_data_r1[424]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[425] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[425]),
        .Q(app_wdf_data_r1[425]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[426] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[426]),
        .Q(app_wdf_data_r1[426]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[427] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[427]),
        .Q(app_wdf_data_r1[427]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[428] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[428]),
        .Q(app_wdf_data_r1[428]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[429] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[429]),
        .Q(app_wdf_data_r1[429]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[42] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[42]),
        .Q(app_wdf_data_r1[42]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[430] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[430]),
        .Q(app_wdf_data_r1[430]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[431] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[431]),
        .Q(app_wdf_data_r1[431]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[432] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[432]),
        .Q(app_wdf_data_r1[432]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[433] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[433]),
        .Q(app_wdf_data_r1[433]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[434] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[434]),
        .Q(app_wdf_data_r1[434]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[435] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[435]),
        .Q(app_wdf_data_r1[435]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[436] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[436]),
        .Q(app_wdf_data_r1[436]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[437] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[437]),
        .Q(app_wdf_data_r1[437]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[438] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[438]),
        .Q(app_wdf_data_r1[438]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[439] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[439]),
        .Q(app_wdf_data_r1[439]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[43] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[43]),
        .Q(app_wdf_data_r1[43]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[440] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[440]),
        .Q(app_wdf_data_r1[440]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[441] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[441]),
        .Q(app_wdf_data_r1[441]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[442] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[442]),
        .Q(app_wdf_data_r1[442]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[443] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[443]),
        .Q(app_wdf_data_r1[443]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[444] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[444]),
        .Q(app_wdf_data_r1[444]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[445] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[445]),
        .Q(app_wdf_data_r1[445]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[446] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[446]),
        .Q(app_wdf_data_r1[446]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[447] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[447]),
        .Q(app_wdf_data_r1[447]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[448] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[448]),
        .Q(app_wdf_data_r1[448]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[449] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[449]),
        .Q(app_wdf_data_r1[449]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[44] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[44]),
        .Q(app_wdf_data_r1[44]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[450] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[450]),
        .Q(app_wdf_data_r1[450]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[451] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[451]),
        .Q(app_wdf_data_r1[451]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[452] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[452]),
        .Q(app_wdf_data_r1[452]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[453] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[453]),
        .Q(app_wdf_data_r1[453]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[454] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[454]),
        .Q(app_wdf_data_r1[454]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[455] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[455]),
        .Q(app_wdf_data_r1[455]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[456] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[456]),
        .Q(app_wdf_data_r1[456]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[457] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[457]),
        .Q(app_wdf_data_r1[457]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[458] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[458]),
        .Q(app_wdf_data_r1[458]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[459] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[459]),
        .Q(app_wdf_data_r1[459]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[45] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[45]),
        .Q(app_wdf_data_r1[45]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[460] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[460]),
        .Q(app_wdf_data_r1[460]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[461] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[461]),
        .Q(app_wdf_data_r1[461]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[462] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[462]),
        .Q(app_wdf_data_r1[462]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[463] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[463]),
        .Q(app_wdf_data_r1[463]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[464] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[464]),
        .Q(app_wdf_data_r1[464]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[465] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[465]),
        .Q(app_wdf_data_r1[465]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[466] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[466]),
        .Q(app_wdf_data_r1[466]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[467] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[467]),
        .Q(app_wdf_data_r1[467]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[468] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[468]),
        .Q(app_wdf_data_r1[468]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[469] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[469]),
        .Q(app_wdf_data_r1[469]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[46] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[46]),
        .Q(app_wdf_data_r1[46]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[470] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[470]),
        .Q(app_wdf_data_r1[470]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[471] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[471]),
        .Q(app_wdf_data_r1[471]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[472] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[472]),
        .Q(app_wdf_data_r1[472]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[473] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[473]),
        .Q(app_wdf_data_r1[473]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[474] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[474]),
        .Q(app_wdf_data_r1[474]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[475] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[475]),
        .Q(app_wdf_data_r1[475]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[476] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[476]),
        .Q(app_wdf_data_r1[476]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[477] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[477]),
        .Q(app_wdf_data_r1[477]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[478] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[478]),
        .Q(app_wdf_data_r1[478]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[479] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[479]),
        .Q(app_wdf_data_r1[479]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[47] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[47]),
        .Q(app_wdf_data_r1[47]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[480] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[480]),
        .Q(app_wdf_data_r1[480]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[481] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[481]),
        .Q(app_wdf_data_r1[481]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[482] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[482]),
        .Q(app_wdf_data_r1[482]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[483] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[483]),
        .Q(app_wdf_data_r1[483]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[484] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[484]),
        .Q(app_wdf_data_r1[484]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[485] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[485]),
        .Q(app_wdf_data_r1[485]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[486] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[486]),
        .Q(app_wdf_data_r1[486]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[487] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[487]),
        .Q(app_wdf_data_r1[487]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[488] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[488]),
        .Q(app_wdf_data_r1[488]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[489] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[489]),
        .Q(app_wdf_data_r1[489]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[48] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[48]),
        .Q(app_wdf_data_r1[48]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[490] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[490]),
        .Q(app_wdf_data_r1[490]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[491] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[491]),
        .Q(app_wdf_data_r1[491]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[492] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[492]),
        .Q(app_wdf_data_r1[492]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[493] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[493]),
        .Q(app_wdf_data_r1[493]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[494] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[494]),
        .Q(app_wdf_data_r1[494]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[495] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[495]),
        .Q(app_wdf_data_r1[495]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[496] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[496]),
        .Q(app_wdf_data_r1[496]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[497] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[497]),
        .Q(app_wdf_data_r1[497]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[498] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[498]),
        .Q(app_wdf_data_r1[498]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[499] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[499]),
        .Q(app_wdf_data_r1[499]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[49] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[49]),
        .Q(app_wdf_data_r1[49]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[4] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[4]),
        .Q(app_wdf_data_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[500] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[500]),
        .Q(app_wdf_data_r1[500]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[501] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[501]),
        .Q(app_wdf_data_r1[501]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[502] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[502]),
        .Q(app_wdf_data_r1[502]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[503] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[503]),
        .Q(app_wdf_data_r1[503]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[504] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[504]),
        .Q(app_wdf_data_r1[504]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[505] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[505]),
        .Q(app_wdf_data_r1[505]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[506] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[506]),
        .Q(app_wdf_data_r1[506]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[507] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[507]),
        .Q(app_wdf_data_r1[507]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[508] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[508]),
        .Q(app_wdf_data_r1[508]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[509] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[509]),
        .Q(app_wdf_data_r1[509]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[50] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[50]),
        .Q(app_wdf_data_r1[50]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[510] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[510]),
        .Q(app_wdf_data_r1[510]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[511] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[511]),
        .Q(app_wdf_data_r1[511]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[51] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[51]),
        .Q(app_wdf_data_r1[51]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[52] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[52]),
        .Q(app_wdf_data_r1[52]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[53] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[53]),
        .Q(app_wdf_data_r1[53]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[54] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[54]),
        .Q(app_wdf_data_r1[54]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[55] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[55]),
        .Q(app_wdf_data_r1[55]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[56] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[56]),
        .Q(app_wdf_data_r1[56]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[57] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[57]),
        .Q(app_wdf_data_r1[57]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[58] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[58]),
        .Q(app_wdf_data_r1[58]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[59] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[59]),
        .Q(app_wdf_data_r1[59]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[5] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[5]),
        .Q(app_wdf_data_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[60] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[60]),
        .Q(app_wdf_data_r1[60]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[61] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[61]),
        .Q(app_wdf_data_r1[61]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[62] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[62]),
        .Q(app_wdf_data_r1[62]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[63] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[63]),
        .Q(app_wdf_data_r1[63]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[64] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[64]),
        .Q(app_wdf_data_r1[64]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[65] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[65]),
        .Q(app_wdf_data_r1[65]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[66] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[66]),
        .Q(app_wdf_data_r1[66]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[67] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[67]),
        .Q(app_wdf_data_r1[67]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[68] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[68]),
        .Q(app_wdf_data_r1[68]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[69] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[69]),
        .Q(app_wdf_data_r1[69]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[6] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[6]),
        .Q(app_wdf_data_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[70] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[70]),
        .Q(app_wdf_data_r1[70]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[71] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[71]),
        .Q(app_wdf_data_r1[71]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[72] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[72]),
        .Q(app_wdf_data_r1[72]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[73] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[73]),
        .Q(app_wdf_data_r1[73]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[74] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[74]),
        .Q(app_wdf_data_r1[74]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[75] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[75]),
        .Q(app_wdf_data_r1[75]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[76] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[76]),
        .Q(app_wdf_data_r1[76]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[77] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[77]),
        .Q(app_wdf_data_r1[77]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[78] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[78]),
        .Q(app_wdf_data_r1[78]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[79] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[79]),
        .Q(app_wdf_data_r1[79]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[7] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[7]),
        .Q(app_wdf_data_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[80] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[80]),
        .Q(app_wdf_data_r1[80]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[81] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[81]),
        .Q(app_wdf_data_r1[81]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[82] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[82]),
        .Q(app_wdf_data_r1[82]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[83] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[83]),
        .Q(app_wdf_data_r1[83]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[84] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[84]),
        .Q(app_wdf_data_r1[84]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[85] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[85]),
        .Q(app_wdf_data_r1[85]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[86] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[86]),
        .Q(app_wdf_data_r1[86]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[87] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[87]),
        .Q(app_wdf_data_r1[87]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[88] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[88]),
        .Q(app_wdf_data_r1[88]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[89] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[89]),
        .Q(app_wdf_data_r1[89]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[8] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[8]),
        .Q(app_wdf_data_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[90] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[90]),
        .Q(app_wdf_data_r1[90]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[91] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[91]),
        .Q(app_wdf_data_r1[91]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[92] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[92]),
        .Q(app_wdf_data_r1[92]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[93] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[93]),
        .Q(app_wdf_data_r1[93]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[94] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[94]),
        .Q(app_wdf_data_r1[94]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[95] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[95]),
        .Q(app_wdf_data_r1[95]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[96] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[96]),
        .Q(app_wdf_data_r1[96]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[97] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[97]),
        .Q(app_wdf_data_r1[97]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[98] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[98]),
        .Q(app_wdf_data_r1[98]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[99] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[99]),
        .Q(app_wdf_data_r1[99]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[9] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_data[9]),
        .Q(app_wdf_data_r1[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    app_wdf_end_r1_i_1
       (.I0(app_wdf_end),
        .I1(app_wdf_rdy),
        .I2(app_wdf_end_r1),
        .O(app_wdf_end_r1_i_1_n_0));
  FDRE app_wdf_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_wdf_end_r1_i_1_n_0),
        .Q(app_wdf_end_r1),
        .R(reset_reg));
  FDRE \app_wdf_mask_r1_reg[0] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[0]),
        .Q(app_wdf_mask_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[10] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[10]),
        .Q(app_wdf_mask_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[11] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[11]),
        .Q(app_wdf_mask_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[12] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[12]),
        .Q(app_wdf_mask_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[13] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[13]),
        .Q(app_wdf_mask_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[14] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[14]),
        .Q(app_wdf_mask_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[15] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[15]),
        .Q(app_wdf_mask_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[16] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[16]),
        .Q(app_wdf_mask_r1[16]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[17] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[17]),
        .Q(app_wdf_mask_r1[17]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[18] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[18]),
        .Q(app_wdf_mask_r1[18]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[19] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[19]),
        .Q(app_wdf_mask_r1[19]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[1] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[1]),
        .Q(app_wdf_mask_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[20] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[20]),
        .Q(app_wdf_mask_r1[20]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[21] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[21]),
        .Q(app_wdf_mask_r1[21]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[22] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[22]),
        .Q(app_wdf_mask_r1[22]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[23] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[23]),
        .Q(app_wdf_mask_r1[23]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[24] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[24]),
        .Q(app_wdf_mask_r1[24]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[25] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[25]),
        .Q(app_wdf_mask_r1[25]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[26] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[26]),
        .Q(app_wdf_mask_r1[26]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[27] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[27]),
        .Q(app_wdf_mask_r1[27]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[28] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[28]),
        .Q(app_wdf_mask_r1[28]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[29] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[29]),
        .Q(app_wdf_mask_r1[29]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[2] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[2]),
        .Q(app_wdf_mask_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[30] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[30]),
        .Q(app_wdf_mask_r1[30]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[31] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[31]),
        .Q(app_wdf_mask_r1[31]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[32] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[32]),
        .Q(app_wdf_mask_r1[32]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[33] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[33]),
        .Q(app_wdf_mask_r1[33]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[34] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[34]),
        .Q(app_wdf_mask_r1[34]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[35] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[35]),
        .Q(app_wdf_mask_r1[35]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[36] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[36]),
        .Q(app_wdf_mask_r1[36]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[37] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[37]),
        .Q(app_wdf_mask_r1[37]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[38] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[38]),
        .Q(app_wdf_mask_r1[38]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[39] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[39]),
        .Q(app_wdf_mask_r1[39]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[3] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[3]),
        .Q(app_wdf_mask_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[40] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[40]),
        .Q(app_wdf_mask_r1[40]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[41] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[41]),
        .Q(app_wdf_mask_r1[41]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[42] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[42]),
        .Q(app_wdf_mask_r1[42]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[43] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[43]),
        .Q(app_wdf_mask_r1[43]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[44] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[44]),
        .Q(app_wdf_mask_r1[44]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[45] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[45]),
        .Q(app_wdf_mask_r1[45]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[46] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[46]),
        .Q(app_wdf_mask_r1[46]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[47] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[47]),
        .Q(app_wdf_mask_r1[47]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[48] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[48]),
        .Q(app_wdf_mask_r1[48]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[49] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[49]),
        .Q(app_wdf_mask_r1[49]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[4] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[4]),
        .Q(app_wdf_mask_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[50] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[50]),
        .Q(app_wdf_mask_r1[50]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[51] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[51]),
        .Q(app_wdf_mask_r1[51]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[52] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[52]),
        .Q(app_wdf_mask_r1[52]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[53] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[53]),
        .Q(app_wdf_mask_r1[53]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[54] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[54]),
        .Q(app_wdf_mask_r1[54]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[55] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[55]),
        .Q(app_wdf_mask_r1[55]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[56] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[56]),
        .Q(app_wdf_mask_r1[56]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[57] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[57]),
        .Q(app_wdf_mask_r1[57]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[58] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[58]),
        .Q(app_wdf_mask_r1[58]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[59] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[59]),
        .Q(app_wdf_mask_r1[59]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[5] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[5]),
        .Q(app_wdf_mask_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[60] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[60]),
        .Q(app_wdf_mask_r1[60]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[61] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[61]),
        .Q(app_wdf_mask_r1[61]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[62] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[62]),
        .Q(app_wdf_mask_r1[62]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[63] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[63]),
        .Q(app_wdf_mask_r1[63]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[6] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[6]),
        .Q(app_wdf_mask_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[7] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[7]),
        .Q(app_wdf_mask_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[8] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[8]),
        .Q(app_wdf_mask_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[9] 
       (.C(CLK),
        .CE(app_wdf_rdy),
        .D(app_wdf_mask[9]),
        .Q(app_wdf_mask_r1[9]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    app_wdf_wren_r1_i_1
       (.I0(app_wdf_wren),
        .I1(app_wdf_rdy),
        .I2(app_wdf_wren_r1),
        .O(app_wdf_wren_r1_i_1_n_0));
  FDRE app_wdf_wren_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_wdf_wren_r1_i_1_n_0),
        .Q(app_wdf_wren_r1),
        .R(reset_reg));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),
        .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),
        .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),
        .I3(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),
        .O(p_0_in[3]));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[0] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in[0]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),
        .R(reset_reg));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[1] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in[1]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),
        .R(reset_reg));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[2] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in[2]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),
        .R(reset_reg));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[3] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in[3]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]),
        .R(reset_reg));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_3__0
       (.I0(\my_empty_reg[7]_0 [63]),
        .I1(init_calib_complete_reg_rep__25),
        .O(\my_empty_reg[7] [15]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_3__1
       (.I0(\my_empty_reg[7]_0 [39]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_3__2
       (.I0(\my_empty_reg[7]_0 [31]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [15]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_6
       (.I0(\my_empty_reg[7]_0 [383]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [47]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_6__0
       (.I0(\my_empty_reg[7]_0 [359]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [41]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_6__1
       (.I0(\my_empty_reg[7]_0 [351]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [47]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_1__2
       (.I0(\my_empty_reg[7]_0 [375]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [45]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_1__3
       (.I0(\my_empty_reg[7]_0 [367]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [43]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_1__6
       (.I0(\my_empty_reg[7]_0 [343]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [45]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_1__7
       (.I0(\my_empty_reg[7]_0 [335]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [43]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_1__8
       (.I0(\my_empty_reg[7]_0 [327]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [41]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_2__1
       (.I0(\my_empty_reg[7]_0 [318]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7] [39]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_2__4
       (.I0(\my_empty_reg[7]_0 [294]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7] [33]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_2__5
       (.I0(\my_empty_reg[7]_0 [286]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [39]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_1__2
       (.I0(\my_empty_reg[7]_0 [246]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7] [29]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_1__3
       (.I0(\my_empty_reg[7]_0 [238]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7] [27]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_1__6
       (.I0(\my_empty_reg[7]_0 [214]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7]_1 [29]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_1__7
       (.I0(\my_empty_reg[7]_0 [206]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7]_1 [27]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_1__8
       (.I0(\my_empty_reg[7]_0 [198]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7]_1 [25]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_2__1
       (.I0(\my_empty_reg[7]_0 [189]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [23]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_2__4
       (.I0(\my_empty_reg[7]_0 [165]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [17]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_2__5
       (.I0(\my_empty_reg[7]_0 [157]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7]_1 [23]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_4__0
       (.I0(\my_empty_reg[7]_0 [310]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7] [37]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_4__1
       (.I0(\my_empty_reg[7]_0 [302]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7] [35]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_4__4
       (.I0(\my_empty_reg[7]_0 [278]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [37]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_4__5
       (.I0(\my_empty_reg[7]_0 [270]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [35]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_4__6
       (.I0(\my_empty_reg[7]_0 [262]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [33]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_2__1
       (.I0(\my_empty_reg[7]_0 [60]),
        .I1(init_calib_complete_reg_rep__25),
        .O(\my_empty_reg[7] [14]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_2__4
       (.I0(\my_empty_reg[7]_0 [36]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [2]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_2__5
       (.I0(\my_empty_reg[7]_0 [28]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [14]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_4__2
       (.I0(\my_empty_reg[7]_0 [181]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [21]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_4__3
       (.I0(\my_empty_reg[7]_0 [173]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [19]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_4__6
       (.I0(\my_empty_reg[7]_0 [149]),
        .I1(init_calib_complete_reg_rep__24),
        .O(\my_empty_reg[7]_1 [21]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_4__7
       (.I0(\my_empty_reg[7]_0 [141]),
        .I1(init_calib_complete_reg_rep__24),
        .O(\my_empty_reg[7]_1 [19]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_4__8
       (.I0(\my_empty_reg[7]_0 [133]),
        .I1(init_calib_complete_reg_rep__24),
        .O(\my_empty_reg[7]_1 [17]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__0
       (.I0(\my_empty_reg[7]_0 [59]),
        .I1(init_calib_complete_reg_rep__25),
        .O(\my_empty_reg[7] [13]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__1
       (.I0(\my_empty_reg[7]_0 [52]),
        .I1(init_calib_complete_reg_rep__25),
        .O(\my_empty_reg[7] [10]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__2
       (.I0(\my_empty_reg[7]_0 [44]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [6]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__3
       (.I0(\my_empty_reg[7]_0 [35]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__4
       (.I0(\my_empty_reg[7]_0 [27]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [13]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__5
       (.I0(\my_empty_reg[7]_0 [20]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [10]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__6
       (.I0(\my_empty_reg[7]_0 [12]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [6]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_4__7
       (.I0(\my_empty_reg[7]_0 [4]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [2]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_1__2
       (.I0(\my_empty_reg[7]_0 [379]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [46]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_1__5
       (.I0(\my_empty_reg[7]_0 [355]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [40]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_1__6
       (.I0(\my_empty_reg[7]_0 [347]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [46]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_6__0
       (.I0(\my_empty_reg[7]_0 [43]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [5]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_6__3
       (.I0(\my_empty_reg[7]_0 [11]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [5]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_6__4
       (.I0(\my_empty_reg[7]_0 [3]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_1__2
       (.I0(\my_empty_reg[7]_0 [250]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7] [30]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_1__4
       (.I0(\my_empty_reg[7]_0 [226]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7] [24]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_1__5
       (.I0(\my_empty_reg[7]_0 [218]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7]_1 [30]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_3__3
       (.I0(\my_empty_reg[7]_0 [363]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [42]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_3__6
       (.I0(\my_empty_reg[7]_0 [331]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [42]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_3__7
       (.I0(\my_empty_reg[7]_0 [323]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [40]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_4__2
       (.I0(\my_empty_reg[7]_0 [314]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7] [38]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_4__4
       (.I0(\my_empty_reg[7]_0 [290]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7] [32]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_4__5
       (.I0(\my_empty_reg[7]_0 [282]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [38]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_2__2
       (.I0(\my_empty_reg[7]_0 [51]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [9]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_2__6
       (.I0(\my_empty_reg[7]_0 [19]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [9]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_3__2
       (.I0(\my_empty_reg[7]_0 [234]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7] [26]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_3__6
       (.I0(\my_empty_reg[7]_0 [202]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7]_1 [26]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_3__7
       (.I0(\my_empty_reg[7]_0 [194]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7]_1 [24]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_4__0
       (.I0(\my_empty_reg[7]_0 [185]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [22]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_4__3
       (.I0(\my_empty_reg[7]_0 [161]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [16]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_4__4
       (.I0(\my_empty_reg[7]_0 [153]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7]_1 [22]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_5__1
       (.I0(\my_empty_reg[7]_0 [371]),
        .I1(init_calib_complete_reg_rep__19),
        .O(\my_empty_reg[7] [44]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_5__5
       (.I0(\my_empty_reg[7]_0 [339]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7]_1 [44]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_6__2
       (.I0(\my_empty_reg[7]_0 [298]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7] [34]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_6__6
       (.I0(\my_empty_reg[7]_0 [266]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [34]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_6__7
       (.I0(\my_empty_reg[7]_0 [258]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [32]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_4__0
       (.I0(\my_empty_reg[7]_0 [56]),
        .I1(init_calib_complete_reg_rep__25),
        .O(\my_empty_reg[7] [12]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_4__3
       (.I0(\my_empty_reg[7]_0 [32]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [0]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_4__4
       (.I0(\my_empty_reg[7]_0 [24]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [12]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_5__1
       (.I0(\my_empty_reg[7]_0 [242]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7] [28]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_5__5
       (.I0(\my_empty_reg[7]_0 [210]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7]_1 [28]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_6__2
       (.I0(\my_empty_reg[7]_0 [169]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [18]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_6__6
       (.I0(\my_empty_reg[7]_0 [137]),
        .I1(init_calib_complete_reg_rep__24),
        .O(\my_empty_reg[7]_1 [18]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_6__7
       (.I0(\my_empty_reg[7]_0 [129]),
        .I1(init_calib_complete_reg_rep__24),
        .O(\my_empty_reg[7]_1 [16]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_60_65_i_2__1
       (.I0(\my_empty_reg[7]_0 [306]),
        .I1(init_calib_complete_reg_rep__20),
        .O(\my_empty_reg[7] [36]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_60_65_i_2__5
       (.I0(\my_empty_reg[7]_0 [274]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7]_1 [36]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_60_65_i_6__0
       (.I0(\my_empty_reg[7]_0 [40]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [4]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_60_65_i_6__2
       (.I0(\my_empty_reg[7]_0 [8]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [4]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_60_65_i_6__3
       (.I0(\my_empty_reg[7]_0 [0]),
        .I1(init_calib_complete_reg_rep__27),
        .O(\my_empty_reg[7]_1 [0]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_66_71_i_2__0
       (.I0(\my_empty_reg[7]_0 [177]),
        .I1(init_calib_complete_reg_rep__23),
        .O(\my_empty_reg[7] [20]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_66_71_i_2__2
       (.I0(\my_empty_reg[7]_0 [145]),
        .I1(init_calib_complete_reg_rep__24),
        .O(\my_empty_reg[7]_1 [20]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_2__4
       (.I0(\my_empty_reg[7]_0 [55]),
        .I1(init_calib_complete_reg_rep__25),
        .O(\my_empty_reg[7] [11]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_2__5
       (.I0(\my_empty_reg[7]_0 [47]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [7]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_2__6
       (.I0(\my_empty_reg[7]_0 [23]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [11]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_2__7
       (.I0(\my_empty_reg[7]_0 [15]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [7]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_2__8
       (.I0(\my_empty_reg[7]_0 [7]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_5
       (.I0(\my_empty_reg[7]_0 [254]),
        .I1(init_calib_complete_reg_rep__21),
        .O(\my_empty_reg[7] [31]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_5__0
       (.I0(\my_empty_reg[7]_0 [230]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7] [25]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_5__1
       (.I0(\my_empty_reg[7]_0 [222]),
        .I1(init_calib_complete_reg_rep__22),
        .O(\my_empty_reg[7]_1 [31]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_72_77_i_2__0
       (.I0(\my_empty_reg[7]_0 [48]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7] [8]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_72_77_i_2__1
       (.I0(\my_empty_reg[7]_0 [16]),
        .I1(init_calib_complete_reg_rep__26),
        .O(\my_empty_reg[7]_1 [8]));
  LUT5 #(
    .INIT(32'h40404044)) 
    \occupied_counter.app_wdf_rdy_r_i_1 
       (.I0(reset_reg),
        .I1(ram_init_done_r),
        .I2(p_0_in_0),
        .I3(\occupied_counter.occ_cnt[15]_i_2_n_0 ),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .O(wdf_rdy_ns));
  (* equivalent_register_removal = "no" *) 
  FDRE \occupied_counter.app_wdf_rdy_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    \occupied_counter.occ_cnt[0]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_wren_r1),
        .O(\occupied_counter.occ_cnt[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[10]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .O(\occupied_counter.occ_cnt[10]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[11]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .O(\occupied_counter.occ_cnt[11]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[12]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .O(\occupied_counter.occ_cnt[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[13]_i_1 
       (.I0(p_4_in),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .O(\occupied_counter.occ_cnt[13]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[14]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .O(\occupied_counter.occ_cnt[14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h6AAA)) 
    \occupied_counter.occ_cnt[15]_i_1 
       (.I0(p_0_in_0),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_wren_r1),
        .O(\occupied_counter.occ_cnt[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \occupied_counter.occ_cnt[15]_i_2 
       (.I0(p_4_in),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_wren_r1),
        .O(\occupied_counter.occ_cnt[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[1]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[0] ),
        .O(\occupied_counter.occ_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[2]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .O(\occupied_counter.occ_cnt[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[3]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .O(\occupied_counter.occ_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[4]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .O(\occupied_counter.occ_cnt[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[5]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .O(\occupied_counter.occ_cnt[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[6]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .O(\occupied_counter.occ_cnt[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[7]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .O(\occupied_counter.occ_cnt[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[8]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .O(\occupied_counter.occ_cnt[8]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEAAA2AAA)) 
    \occupied_counter.occ_cnt[9]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy),
        .I3(app_wdf_end_r1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .O(\occupied_counter.occ_cnt[9]_i_1_n_0 ));
  FDRE \occupied_counter.occ_cnt_reg[0] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[0]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[0] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[10] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[10]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[11] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[11]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[12] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[12]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[13] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[13]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[14] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[14]_i_1_n_0 ),
        .Q(p_4_in),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[15] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[15]_i_2_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[1] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[1]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[2] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[2]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[3] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[3]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[4] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[4]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[5] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[5]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[6] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[6]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[7] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[7]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[8] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[8]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .R(reset_reg));
  FDRE \occupied_counter.occ_cnt_reg[9] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(\occupied_counter.occ_cnt[9]_i_1_n_0 ),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .R(reset_reg));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \pointer_ram.rams[0].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }),
        .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg__0 }),
        .ADDRD({1'b0,ADDRD}),
        .DIA({1'b0,1'b0}),
        .DIB(pointer_wr_data[1:0]),
        .DIC(pointer_wr_data[1:0]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(DOB),
        .DOC(wr_data_pntr[1:0]),
        .DOD(\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(pointer_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \pointer_ram.rams[1].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }),
        .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg__0 }),
        .ADDRD({1'b0,ADDRD}),
        .DIA({1'b0,1'b0}),
        .DIB(pointer_wr_data[3:2]),
        .DIC(pointer_wr_data[3:2]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(\req_data_buf_addr_r_reg[3] ),
        .DOC(wr_data_pntr[3:2]),
        .DOD(\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(pointer_we));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \read_data_indx.rd_data_indx_r[0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_data_indx.rd_data_indx_r[1]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \read_data_indx.rd_data_indx_r[2]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \read_data_indx.rd_data_indx_r[3]_i_1 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(p_0_in__1[3]));
  FDRE \read_data_indx.rd_data_indx_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[0]),
        .Q(Q[0]),
        .R(reset_reg));
  FDRE \read_data_indx.rd_data_indx_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[1]),
        .Q(Q[1]),
        .R(reset_reg));
  FDRE \read_data_indx.rd_data_indx_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[2]),
        .Q(Q[2]),
        .R(reset_reg));
  FDRE \read_data_indx.rd_data_indx_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[3]),
        .Q(Q[3]),
        .R(reset_reg));
  FDRE \read_data_indx.rd_data_upd_indx_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(p_0_in_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT4 #(
    .INIT(16'h4114)) 
    \wr_req_counter.wr_req_cnt_r[0]_i_1 
       (.I0(reset_reg),
        .I1(wr_req_cnt_r[0]),
        .I2(wr_accepted),
        .I3(p_0_in_0),
        .O(\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT5 #(
    .INIT(32'h54150140)) 
    \wr_req_counter.wr_req_cnt_r[1]_i_1 
       (.I0(reset_reg),
        .I1(wr_req_cnt_r[0]),
        .I2(wr_accepted),
        .I3(p_0_in_0),
        .I4(wr_req_cnt_r[1]),
        .O(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5554155500014000)) 
    \wr_req_counter.wr_req_cnt_r[2]_i_1 
       (.I0(reset_reg),
        .I1(wr_req_cnt_r[0]),
        .I2(wr_req_cnt_r[1]),
        .I3(wr_accepted),
        .I4(p_0_in_0),
        .I5(wr_req_cnt_r[2]),
        .O(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000BE)) 
    \wr_req_counter.wr_req_cnt_r[3]_i_1 
       (.I0(wr_req_cnt_r[3]),
        .I1(wr_accepted),
        .I2(p_0_in_0),
        .I3(reset_reg),
        .I4(\wr_req_counter.wr_req_cnt_r[3]_i_2_n_0 ),
        .O(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h400000021A5A5A58)) 
    \wr_req_counter.wr_req_cnt_r[3]_i_2 
       (.I0(p_0_in_0),
        .I1(wr_req_cnt_r[2]),
        .I2(wr_accepted),
        .I3(wr_req_cnt_r[0]),
        .I4(wr_req_cnt_r[1]),
        .I5(wr_req_cnt_r[3]),
        .O(\wr_req_counter.wr_req_cnt_r[3]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h06)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ),
        .I1(wr_req_cnt_r[4]),
        .I2(reset_reg),
        .O(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000800000010000)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_2 
       (.I0(wr_req_cnt_r[1]),
        .I1(wr_req_cnt_r[0]),
        .I2(wr_req_cnt_r[3]),
        .I3(wr_req_cnt_r[2]),
        .I4(p_0_in_0),
        .I5(wr_accepted),
        .O(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ),
        .Q(wr_req_cnt_r[0]),
        .R(1'b0));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ),
        .Q(wr_req_cnt_r[1]),
        .R(1'b0));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ),
        .Q(wr_req_cnt_r[2]),
        .R(1'b0));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),
        .Q(wr_req_cnt_r[3]),
        .R(1'b0));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ),
        .Q(wr_req_cnt_r[4]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_285_out[0]),
        .Q(\my_empty_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[100] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_239_out[0]),
        .Q(\my_empty_reg[7]_0 [100]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[101] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_239_out[1]),
        .Q(\my_empty_reg[7]_0 [101]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[102] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_234_out[0]),
        .Q(\my_empty_reg[7]_0 [102]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[103] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_234_out[1]),
        .Q(\my_empty_reg[7]_0 [103]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[104] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_235_out[0]),
        .Q(\my_empty_reg[7]_0 [104]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[105] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_235_out[1]),
        .Q(\my_empty_reg[7]_0 [105]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[106] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_236_out[0]),
        .Q(\my_empty_reg[7]_0 [106]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[107] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_236_out[1]),
        .Q(\my_empty_reg[7]_0 [107]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[108] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_231_out[0]),
        .Q(\my_empty_reg[7]_0 [108]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[109] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_231_out[1]),
        .Q(\my_empty_reg[7]_0 [109]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_284_out[0]),
        .Q(\my_empty_reg[7]_0 [10]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[110] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_232_out[0]),
        .Q(\my_empty_reg[7]_0 [110]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[111] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_232_out[1]),
        .Q(\my_empty_reg[7]_0 [111]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[112] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_233_out[0]),
        .Q(\my_empty_reg[7]_0 [112]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[113] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_233_out[1]),
        .Q(\my_empty_reg[7]_0 [113]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[114] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_228_out[0]),
        .Q(\my_empty_reg[7]_0 [114]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[115] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_228_out[1]),
        .Q(\my_empty_reg[7]_0 [115]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[116] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_229_out[0]),
        .Q(\my_empty_reg[7]_0 [116]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[117] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_229_out[1]),
        .Q(\my_empty_reg[7]_0 [117]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[118] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_230_out[0]),
        .Q(\my_empty_reg[7]_0 [118]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[119] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_230_out[1]),
        .Q(\my_empty_reg[7]_0 [119]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_284_out[1]),
        .Q(\my_empty_reg[7]_0 [11]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[120] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_225_out[0]),
        .Q(\my_empty_reg[7]_0 [120]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[121] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_225_out[1]),
        .Q(\my_empty_reg[7]_0 [121]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[122] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_226_out[0]),
        .Q(\my_empty_reg[7]_0 [122]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[123] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_226_out[1]),
        .Q(\my_empty_reg[7]_0 [123]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[124] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_227_out[0]),
        .Q(\my_empty_reg[7]_0 [124]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[125] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_227_out[1]),
        .Q(\my_empty_reg[7]_0 [125]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[126] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_222_out[0]),
        .Q(\my_empty_reg[7]_0 [126]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[127] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_222_out[1]),
        .Q(\my_empty_reg[7]_0 [127]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[128] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_223_out[0]),
        .Q(\my_empty_reg[7]_0 [128]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[129] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_223_out[1]),
        .Q(\my_empty_reg[7]_0 [129]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_279_out[0]),
        .Q(\my_empty_reg[7]_0 [12]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[130] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_224_out[0]),
        .Q(\my_empty_reg[7]_0 [130]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[131] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_224_out[1]),
        .Q(\my_empty_reg[7]_0 [131]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[132] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_219_out[0]),
        .Q(\my_empty_reg[7]_0 [132]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[133] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_219_out[1]),
        .Q(\my_empty_reg[7]_0 [133]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[134] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_220_out[0]),
        .Q(\my_empty_reg[7]_0 [134]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[135] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_220_out[1]),
        .Q(\my_empty_reg[7]_0 [135]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[136] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_221_out[0]),
        .Q(\my_empty_reg[7]_0 [136]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[137] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_221_out[1]),
        .Q(\my_empty_reg[7]_0 [137]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[138] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_216_out[0]),
        .Q(\my_empty_reg[7]_0 [138]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[139] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_216_out[1]),
        .Q(\my_empty_reg[7]_0 [139]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_279_out[1]),
        .Q(\my_empty_reg[7]_0 [13]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[140] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_217_out[0]),
        .Q(\my_empty_reg[7]_0 [140]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[141] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_217_out[1]),
        .Q(\my_empty_reg[7]_0 [141]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[142] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_218_out[0]),
        .Q(\my_empty_reg[7]_0 [142]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[143] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_218_out[1]),
        .Q(\my_empty_reg[7]_0 [143]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[144] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_213_out[0]),
        .Q(\my_empty_reg[7]_0 [144]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[145] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_213_out[1]),
        .Q(\my_empty_reg[7]_0 [145]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[146] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_214_out[0]),
        .Q(\my_empty_reg[7]_0 [146]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[147] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_214_out[1]),
        .Q(\my_empty_reg[7]_0 [147]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[148] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_215_out[0]),
        .Q(\my_empty_reg[7]_0 [148]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[149] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_215_out[1]),
        .Q(\my_empty_reg[7]_0 [149]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_280_out[0]),
        .Q(\my_empty_reg[7]_0 [14]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[150] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_210_out[0]),
        .Q(\my_empty_reg[7]_0 [150]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[151] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_210_out[1]),
        .Q(\my_empty_reg[7]_0 [151]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[152] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_211_out[0]),
        .Q(\my_empty_reg[7]_0 [152]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[153] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_211_out[1]),
        .Q(\my_empty_reg[7]_0 [153]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[154] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_212_out[0]),
        .Q(\my_empty_reg[7]_0 [154]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[155] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_212_out[1]),
        .Q(\my_empty_reg[7]_0 [155]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[156] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_207_out[0]),
        .Q(\my_empty_reg[7]_0 [156]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[157] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_207_out[1]),
        .Q(\my_empty_reg[7]_0 [157]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[158] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_208_out[0]),
        .Q(\my_empty_reg[7]_0 [158]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[159] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_208_out[1]),
        .Q(\my_empty_reg[7]_0 [159]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_280_out[1]),
        .Q(\my_empty_reg[7]_0 [15]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[160] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_209_out[0]),
        .Q(\my_empty_reg[7]_0 [160]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[161] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_209_out[1]),
        .Q(\my_empty_reg[7]_0 [161]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[162] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_204_out[0]),
        .Q(\my_empty_reg[7]_0 [162]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[163] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_204_out[1]),
        .Q(\my_empty_reg[7]_0 [163]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[164] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_205_out[0]),
        .Q(\my_empty_reg[7]_0 [164]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[165] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_205_out[1]),
        .Q(\my_empty_reg[7]_0 [165]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[166] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_206_out[0]),
        .Q(\my_empty_reg[7]_0 [166]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[167] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_206_out[1]),
        .Q(\my_empty_reg[7]_0 [167]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[168] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_201_out[0]),
        .Q(\my_empty_reg[7]_0 [168]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[169] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_201_out[1]),
        .Q(\my_empty_reg[7]_0 [169]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_281_out[0]),
        .Q(\my_empty_reg[7]_0 [16]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[170] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_202_out[0]),
        .Q(\my_empty_reg[7]_0 [170]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[171] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_202_out[1]),
        .Q(\my_empty_reg[7]_0 [171]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[172] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_203_out[0]),
        .Q(\my_empty_reg[7]_0 [172]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[173] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_203_out[1]),
        .Q(\my_empty_reg[7]_0 [173]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[174] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_198_out[0]),
        .Q(\my_empty_reg[7]_0 [174]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[175] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_198_out[1]),
        .Q(\my_empty_reg[7]_0 [175]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[176] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_199_out[0]),
        .Q(\my_empty_reg[7]_0 [176]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[177] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_199_out[1]),
        .Q(\my_empty_reg[7]_0 [177]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[178] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_200_out[0]),
        .Q(\my_empty_reg[7]_0 [178]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[179] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_200_out[1]),
        .Q(\my_empty_reg[7]_0 [179]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_281_out[1]),
        .Q(\my_empty_reg[7]_0 [17]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[180] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_195_out[0]),
        .Q(\my_empty_reg[7]_0 [180]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[181] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_195_out[1]),
        .Q(\my_empty_reg[7]_0 [181]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[182] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_196_out[0]),
        .Q(\my_empty_reg[7]_0 [182]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[183] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_196_out[1]),
        .Q(\my_empty_reg[7]_0 [183]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[184] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_197_out[0]),
        .Q(\my_empty_reg[7]_0 [184]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[185] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_197_out[1]),
        .Q(\my_empty_reg[7]_0 [185]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[186] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_192_out[0]),
        .Q(\my_empty_reg[7]_0 [186]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[187] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_192_out[1]),
        .Q(\my_empty_reg[7]_0 [187]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[188] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_193_out[0]),
        .Q(\my_empty_reg[7]_0 [188]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[189] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_193_out[1]),
        .Q(\my_empty_reg[7]_0 [189]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_276_out[0]),
        .Q(\my_empty_reg[7]_0 [18]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[190] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_194_out[0]),
        .Q(\my_empty_reg[7]_0 [190]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[191] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_194_out[1]),
        .Q(\my_empty_reg[7]_0 [191]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[192] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_189_out[0]),
        .Q(\my_empty_reg[7]_0 [192]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[193] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_189_out[1]),
        .Q(\my_empty_reg[7]_0 [193]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[194] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_190_out[0]),
        .Q(\my_empty_reg[7]_0 [194]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[195] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_190_out[1]),
        .Q(\my_empty_reg[7]_0 [195]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[196] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_191_out[0]),
        .Q(\my_empty_reg[7]_0 [196]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[197] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_191_out[1]),
        .Q(\my_empty_reg[7]_0 [197]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[198] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_186_out[0]),
        .Q(\my_empty_reg[7]_0 [198]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[199] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_186_out[1]),
        .Q(\my_empty_reg[7]_0 [199]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_276_out[1]),
        .Q(\my_empty_reg[7]_0 [19]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_285_out[1]),
        .Q(\my_empty_reg[7]_0 [1]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[200] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_187_out[0]),
        .Q(\my_empty_reg[7]_0 [200]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[201] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_187_out[1]),
        .Q(\my_empty_reg[7]_0 [201]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[202] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_188_out[0]),
        .Q(\my_empty_reg[7]_0 [202]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[203] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_188_out[1]),
        .Q(\my_empty_reg[7]_0 [203]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[204] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_183_out[0]),
        .Q(\my_empty_reg[7]_0 [204]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[205] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_183_out[1]),
        .Q(\my_empty_reg[7]_0 [205]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[206] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_184_out[0]),
        .Q(\my_empty_reg[7]_0 [206]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[207] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_184_out[1]),
        .Q(\my_empty_reg[7]_0 [207]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[208] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_185_out[0]),
        .Q(\my_empty_reg[7]_0 [208]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[209] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_185_out[1]),
        .Q(\my_empty_reg[7]_0 [209]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_277_out[0]),
        .Q(\my_empty_reg[7]_0 [20]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[210] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_180_out[0]),
        .Q(\my_empty_reg[7]_0 [210]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[211] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_180_out[1]),
        .Q(\my_empty_reg[7]_0 [211]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[212] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_181_out[0]),
        .Q(\my_empty_reg[7]_0 [212]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[213] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_181_out[1]),
        .Q(\my_empty_reg[7]_0 [213]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[214] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_182_out[0]),
        .Q(\my_empty_reg[7]_0 [214]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[215] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_182_out[1]),
        .Q(\my_empty_reg[7]_0 [215]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[216] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_177_out[0]),
        .Q(\my_empty_reg[7]_0 [216]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[217] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_177_out[1]),
        .Q(\my_empty_reg[7]_0 [217]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[218] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_178_out[0]),
        .Q(\my_empty_reg[7]_0 [218]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[219] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_178_out[1]),
        .Q(\my_empty_reg[7]_0 [219]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_277_out[1]),
        .Q(\my_empty_reg[7]_0 [21]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[220] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_179_out[0]),
        .Q(\my_empty_reg[7]_0 [220]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[221] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_179_out[1]),
        .Q(\my_empty_reg[7]_0 [221]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[222] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_174_out[0]),
        .Q(\my_empty_reg[7]_0 [222]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[223] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_174_out[1]),
        .Q(\my_empty_reg[7]_0 [223]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[224] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_175_out[0]),
        .Q(\my_empty_reg[7]_0 [224]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[225] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_175_out[1]),
        .Q(\my_empty_reg[7]_0 [225]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[226] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_176_out[0]),
        .Q(\my_empty_reg[7]_0 [226]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[227] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_176_out[1]),
        .Q(\my_empty_reg[7]_0 [227]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[228] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_171_out[0]),
        .Q(\my_empty_reg[7]_0 [228]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[229] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_171_out[1]),
        .Q(\my_empty_reg[7]_0 [229]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_278_out[0]),
        .Q(\my_empty_reg[7]_0 [22]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[230] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_172_out[0]),
        .Q(\my_empty_reg[7]_0 [230]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[231] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_172_out[1]),
        .Q(\my_empty_reg[7]_0 [231]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[232] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_173_out[0]),
        .Q(\my_empty_reg[7]_0 [232]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[233] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_173_out[1]),
        .Q(\my_empty_reg[7]_0 [233]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[234] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_168_out[0]),
        .Q(\my_empty_reg[7]_0 [234]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[235] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_168_out[1]),
        .Q(\my_empty_reg[7]_0 [235]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[236] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_169_out[0]),
        .Q(\my_empty_reg[7]_0 [236]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[237] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_169_out[1]),
        .Q(\my_empty_reg[7]_0 [237]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[238] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_170_out[0]),
        .Q(\my_empty_reg[7]_0 [238]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[239] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_170_out[1]),
        .Q(\my_empty_reg[7]_0 [239]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_278_out[1]),
        .Q(\my_empty_reg[7]_0 [23]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[240] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_165_out[0]),
        .Q(\my_empty_reg[7]_0 [240]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[241] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_165_out[1]),
        .Q(\my_empty_reg[7]_0 [241]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[242] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_166_out[0]),
        .Q(\my_empty_reg[7]_0 [242]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[243] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_166_out[1]),
        .Q(\my_empty_reg[7]_0 [243]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[244] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_167_out[0]),
        .Q(\my_empty_reg[7]_0 [244]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[245] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_167_out[1]),
        .Q(\my_empty_reg[7]_0 [245]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[246] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_162_out[0]),
        .Q(\my_empty_reg[7]_0 [246]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[247] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_162_out[1]),
        .Q(\my_empty_reg[7]_0 [247]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[248] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_163_out[0]),
        .Q(\my_empty_reg[7]_0 [248]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[249] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_163_out[1]),
        .Q(\my_empty_reg[7]_0 [249]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_273_out[0]),
        .Q(\my_empty_reg[7]_0 [24]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[250] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_164_out[0]),
        .Q(\my_empty_reg[7]_0 [250]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[251] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_164_out[1]),
        .Q(\my_empty_reg[7]_0 [251]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[252] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_159_out[0]),
        .Q(\my_empty_reg[7]_0 [252]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[253] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_159_out[1]),
        .Q(\my_empty_reg[7]_0 [253]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[254] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_160_out[0]),
        .Q(\my_empty_reg[7]_0 [254]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[255] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_160_out[1]),
        .Q(\my_empty_reg[7]_0 [255]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[256] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_161_out[0]),
        .Q(\my_empty_reg[7]_0 [256]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[257] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_161_out[1]),
        .Q(\my_empty_reg[7]_0 [257]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[258] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_156_out[0]),
        .Q(\my_empty_reg[7]_0 [258]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[259] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_156_out[1]),
        .Q(\my_empty_reg[7]_0 [259]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_273_out[1]),
        .Q(\my_empty_reg[7]_0 [25]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[260] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_157_out[0]),
        .Q(\my_empty_reg[7]_0 [260]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[261] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_157_out[1]),
        .Q(\my_empty_reg[7]_0 [261]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[262] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_158_out[0]),
        .Q(\my_empty_reg[7]_0 [262]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[263] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_158_out[1]),
        .Q(\my_empty_reg[7]_0 [263]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[264] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_153_out[0]),
        .Q(\my_empty_reg[7]_0 [264]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[265] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_153_out[1]),
        .Q(\my_empty_reg[7]_0 [265]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[266] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_154_out[0]),
        .Q(\my_empty_reg[7]_0 [266]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[267] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_154_out[1]),
        .Q(\my_empty_reg[7]_0 [267]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[268] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_155_out[0]),
        .Q(\my_empty_reg[7]_0 [268]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[269] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_155_out[1]),
        .Q(\my_empty_reg[7]_0 [269]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_274_out[0]),
        .Q(\my_empty_reg[7]_0 [26]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[270] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_150_out[0]),
        .Q(\my_empty_reg[7]_0 [270]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[271] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_150_out[1]),
        .Q(\my_empty_reg[7]_0 [271]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[272] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_151_out[0]),
        .Q(\my_empty_reg[7]_0 [272]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[273] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_151_out[1]),
        .Q(\my_empty_reg[7]_0 [273]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[274] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_152_out[0]),
        .Q(\my_empty_reg[7]_0 [274]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[275] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_152_out[1]),
        .Q(\my_empty_reg[7]_0 [275]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[276] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_147_out[0]),
        .Q(\my_empty_reg[7]_0 [276]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[277] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_147_out[1]),
        .Q(\my_empty_reg[7]_0 [277]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[278] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_148_out[0]),
        .Q(\my_empty_reg[7]_0 [278]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[279] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_148_out[1]),
        .Q(\my_empty_reg[7]_0 [279]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_274_out[1]),
        .Q(\my_empty_reg[7]_0 [27]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[280] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_149_out[0]),
        .Q(\my_empty_reg[7]_0 [280]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[281] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_149_out[1]),
        .Q(\my_empty_reg[7]_0 [281]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[282] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_144_out[0]),
        .Q(\my_empty_reg[7]_0 [282]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[283] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_144_out[1]),
        .Q(\my_empty_reg[7]_0 [283]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[284] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_145_out[0]),
        .Q(\my_empty_reg[7]_0 [284]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[285] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_145_out[1]),
        .Q(\my_empty_reg[7]_0 [285]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[286] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_146_out[0]),
        .Q(\my_empty_reg[7]_0 [286]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[287] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_146_out[1]),
        .Q(\my_empty_reg[7]_0 [287]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[288] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_141_out[0]),
        .Q(\my_empty_reg[7]_0 [288]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[289] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_141_out[1]),
        .Q(\my_empty_reg[7]_0 [289]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_275_out[0]),
        .Q(\my_empty_reg[7]_0 [28]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[290] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_142_out[0]),
        .Q(\my_empty_reg[7]_0 [290]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[291] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_142_out[1]),
        .Q(\my_empty_reg[7]_0 [291]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[292] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_143_out[0]),
        .Q(\my_empty_reg[7]_0 [292]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[293] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_143_out[1]),
        .Q(\my_empty_reg[7]_0 [293]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[294] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_138_out[0]),
        .Q(\my_empty_reg[7]_0 [294]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[295] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_138_out[1]),
        .Q(\my_empty_reg[7]_0 [295]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[296] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_139_out[0]),
        .Q(\my_empty_reg[7]_0 [296]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[297] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_139_out[1]),
        .Q(\my_empty_reg[7]_0 [297]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[298] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_140_out[0]),
        .Q(\my_empty_reg[7]_0 [298]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[299] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_140_out[1]),
        .Q(\my_empty_reg[7]_0 [299]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_275_out[1]),
        .Q(\my_empty_reg[7]_0 [29]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_286_out[0]),
        .Q(\my_empty_reg[7]_0 [2]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[300] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_135_out[0]),
        .Q(\my_empty_reg[7]_0 [300]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[301] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_135_out[1]),
        .Q(\my_empty_reg[7]_0 [301]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[302] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_136_out[0]),
        .Q(\my_empty_reg[7]_0 [302]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[303] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_136_out[1]),
        .Q(\my_empty_reg[7]_0 [303]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[304] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_137_out[0]),
        .Q(\my_empty_reg[7]_0 [304]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[305] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_137_out[1]),
        .Q(\my_empty_reg[7]_0 [305]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[306] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_132_out[0]),
        .Q(\my_empty_reg[7]_0 [306]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[307] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_132_out[1]),
        .Q(\my_empty_reg[7]_0 [307]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[308] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_133_out[0]),
        .Q(\my_empty_reg[7]_0 [308]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[309] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_133_out[1]),
        .Q(\my_empty_reg[7]_0 [309]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_270_out[0]),
        .Q(\my_empty_reg[7]_0 [30]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[310] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_134_out[0]),
        .Q(\my_empty_reg[7]_0 [310]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[311] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_134_out[1]),
        .Q(\my_empty_reg[7]_0 [311]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[312] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_129_out[0]),
        .Q(\my_empty_reg[7]_0 [312]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[313] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_129_out[1]),
        .Q(\my_empty_reg[7]_0 [313]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[314] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_130_out[0]),
        .Q(\my_empty_reg[7]_0 [314]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[315] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_130_out[1]),
        .Q(\my_empty_reg[7]_0 [315]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[316] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_131_out[0]),
        .Q(\my_empty_reg[7]_0 [316]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[317] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_131_out[1]),
        .Q(\my_empty_reg[7]_0 [317]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[318] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_126_out[0]),
        .Q(\my_empty_reg[7]_0 [318]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[319] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_126_out[1]),
        .Q(\my_empty_reg[7]_0 [319]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_270_out[1]),
        .Q(\my_empty_reg[7]_0 [31]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[320] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_127_out[0]),
        .Q(\my_empty_reg[7]_0 [320]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[321] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_127_out[1]),
        .Q(\my_empty_reg[7]_0 [321]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[322] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_128_out[0]),
        .Q(\my_empty_reg[7]_0 [322]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[323] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_128_out[1]),
        .Q(\my_empty_reg[7]_0 [323]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[324] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_123_out[0]),
        .Q(\my_empty_reg[7]_0 [324]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[325] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_123_out[1]),
        .Q(\my_empty_reg[7]_0 [325]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[326] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_124_out[0]),
        .Q(\my_empty_reg[7]_0 [326]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[327] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_124_out[1]),
        .Q(\my_empty_reg[7]_0 [327]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[328] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_125_out[0]),
        .Q(\my_empty_reg[7]_0 [328]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[329] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_125_out[1]),
        .Q(\my_empty_reg[7]_0 [329]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_271_out[0]),
        .Q(\my_empty_reg[7]_0 [32]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[330] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_120_out[0]),
        .Q(\my_empty_reg[7]_0 [330]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[331] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_120_out[1]),
        .Q(\my_empty_reg[7]_0 [331]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[332] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_121_out[0]),
        .Q(\my_empty_reg[7]_0 [332]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[333] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_121_out[1]),
        .Q(\my_empty_reg[7]_0 [333]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[334] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_122_out[0]),
        .Q(\my_empty_reg[7]_0 [334]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[335] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_122_out[1]),
        .Q(\my_empty_reg[7]_0 [335]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[336] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_117_out[0]),
        .Q(\my_empty_reg[7]_0 [336]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[337] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_117_out[1]),
        .Q(\my_empty_reg[7]_0 [337]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[338] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_118_out[0]),
        .Q(\my_empty_reg[7]_0 [338]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[339] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_118_out[1]),
        .Q(\my_empty_reg[7]_0 [339]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_271_out[1]),
        .Q(\my_empty_reg[7]_0 [33]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[340] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_119_out[0]),
        .Q(\my_empty_reg[7]_0 [340]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[341] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_119_out[1]),
        .Q(\my_empty_reg[7]_0 [341]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[342] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_114_out[0]),
        .Q(\my_empty_reg[7]_0 [342]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[343] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_114_out[1]),
        .Q(\my_empty_reg[7]_0 [343]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[344] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_115_out[0]),
        .Q(\my_empty_reg[7]_0 [344]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[345] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_115_out[1]),
        .Q(\my_empty_reg[7]_0 [345]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[346] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_116_out[0]),
        .Q(\my_empty_reg[7]_0 [346]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[347] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_116_out[1]),
        .Q(\my_empty_reg[7]_0 [347]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[348] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_111_out[0]),
        .Q(\my_empty_reg[7]_0 [348]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[349] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_111_out[1]),
        .Q(\my_empty_reg[7]_0 [349]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_272_out[0]),
        .Q(\my_empty_reg[7]_0 [34]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[350] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_112_out[0]),
        .Q(\my_empty_reg[7]_0 [350]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[351] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_112_out[1]),
        .Q(\my_empty_reg[7]_0 [351]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[352] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_113_out[0]),
        .Q(\my_empty_reg[7]_0 [352]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[353] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_113_out[1]),
        .Q(\my_empty_reg[7]_0 [353]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[354] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_108_out[0]),
        .Q(\my_empty_reg[7]_0 [354]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[355] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_108_out[1]),
        .Q(\my_empty_reg[7]_0 [355]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[356] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_109_out[0]),
        .Q(\my_empty_reg[7]_0 [356]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[357] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_109_out[1]),
        .Q(\my_empty_reg[7]_0 [357]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[358] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_110_out[0]),
        .Q(\my_empty_reg[7]_0 [358]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[359] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_110_out[1]),
        .Q(\my_empty_reg[7]_0 [359]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_272_out[1]),
        .Q(\my_empty_reg[7]_0 [35]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[360] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_105_out[0]),
        .Q(\my_empty_reg[7]_0 [360]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[361] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_105_out[1]),
        .Q(\my_empty_reg[7]_0 [361]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[362] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_106_out[0]),
        .Q(\my_empty_reg[7]_0 [362]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[363] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_106_out[1]),
        .Q(\my_empty_reg[7]_0 [363]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[364] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_107_out[0]),
        .Q(\my_empty_reg[7]_0 [364]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[365] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_107_out[1]),
        .Q(\my_empty_reg[7]_0 [365]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[366] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_102_out[0]),
        .Q(\my_empty_reg[7]_0 [366]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[367] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_102_out[1]),
        .Q(\my_empty_reg[7]_0 [367]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[368] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_103_out[0]),
        .Q(\my_empty_reg[7]_0 [368]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[369] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_103_out[1]),
        .Q(\my_empty_reg[7]_0 [369]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_267_out[0]),
        .Q(\my_empty_reg[7]_0 [36]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[370] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_104_out[0]),
        .Q(\my_empty_reg[7]_0 [370]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[371] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_104_out[1]),
        .Q(\my_empty_reg[7]_0 [371]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[372] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_99_out[0]),
        .Q(\my_empty_reg[7]_0 [372]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[373] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_99_out[1]),
        .Q(\my_empty_reg[7]_0 [373]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[374] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_100_out[0]),
        .Q(\my_empty_reg[7]_0 [374]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[375] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_100_out[1]),
        .Q(\my_empty_reg[7]_0 [375]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[376] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_101_out[0]),
        .Q(\my_empty_reg[7]_0 [376]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[377] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_101_out[1]),
        .Q(\my_empty_reg[7]_0 [377]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[378] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_96_out[0]),
        .Q(\my_empty_reg[7]_0 [378]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[379] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_96_out[1]),
        .Q(\my_empty_reg[7]_0 [379]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_267_out[1]),
        .Q(\my_empty_reg[7]_0 [37]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[380] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_97_out[0]),
        .Q(\my_empty_reg[7]_0 [380]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[381] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_97_out[1]),
        .Q(\my_empty_reg[7]_0 [381]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[382] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_98_out[0]),
        .Q(\my_empty_reg[7]_0 [382]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[383] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_98_out[1]),
        .Q(\my_empty_reg[7]_0 [383]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[384] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_93_out[0]),
        .Q(\my_empty_reg[7]_0 [384]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[385] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_93_out[1]),
        .Q(\my_empty_reg[7]_0 [385]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[386] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_94_out[0]),
        .Q(\my_empty_reg[7]_0 [386]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[387] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_94_out[1]),
        .Q(\my_empty_reg[7]_0 [387]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[388] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_95_out[0]),
        .Q(\my_empty_reg[7]_0 [388]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[389] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_95_out[1]),
        .Q(\my_empty_reg[7]_0 [389]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_268_out[0]),
        .Q(\my_empty_reg[7]_0 [38]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[390] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_90_out[0]),
        .Q(\my_empty_reg[7]_0 [390]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[391] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_90_out[1]),
        .Q(\my_empty_reg[7]_0 [391]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[392] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_91_out[0]),
        .Q(\my_empty_reg[7]_0 [392]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[393] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_91_out[1]),
        .Q(\my_empty_reg[7]_0 [393]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[394] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_92_out[0]),
        .Q(\my_empty_reg[7]_0 [394]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[395] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_92_out[1]),
        .Q(\my_empty_reg[7]_0 [395]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[396] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_87_out[0]),
        .Q(\my_empty_reg[7]_0 [396]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[397] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_87_out[1]),
        .Q(\my_empty_reg[7]_0 [397]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[398] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_88_out[0]),
        .Q(\my_empty_reg[7]_0 [398]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[399] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_88_out[1]),
        .Q(\my_empty_reg[7]_0 [399]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_268_out[1]),
        .Q(\my_empty_reg[7]_0 [39]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_286_out[1]),
        .Q(\my_empty_reg[7]_0 [3]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[400] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_89_out[0]),
        .Q(\my_empty_reg[7]_0 [400]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[401] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_89_out[1]),
        .Q(\my_empty_reg[7]_0 [401]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[402] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_84_out[0]),
        .Q(\my_empty_reg[7]_0 [402]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[403] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_84_out[1]),
        .Q(\my_empty_reg[7]_0 [403]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[404] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_85_out[0]),
        .Q(\my_empty_reg[7]_0 [404]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[405] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_85_out[1]),
        .Q(\my_empty_reg[7]_0 [405]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[406] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_86_out[0]),
        .Q(\my_empty_reg[7]_0 [406]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[407] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_86_out[1]),
        .Q(\my_empty_reg[7]_0 [407]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[408] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_81_out[0]),
        .Q(\my_empty_reg[7]_0 [408]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[409] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_81_out[1]),
        .Q(\my_empty_reg[7]_0 [409]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_269_out[0]),
        .Q(\my_empty_reg[7]_0 [40]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[410] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_82_out[0]),
        .Q(\my_empty_reg[7]_0 [410]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[411] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_82_out[1]),
        .Q(\my_empty_reg[7]_0 [411]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[412] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_83_out[0]),
        .Q(\my_empty_reg[7]_0 [412]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[413] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_83_out[1]),
        .Q(\my_empty_reg[7]_0 [413]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[414] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_78_out[0]),
        .Q(\my_empty_reg[7]_0 [414]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[415] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_78_out[1]),
        .Q(\my_empty_reg[7]_0 [415]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[416] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_79_out[0]),
        .Q(\my_empty_reg[7]_0 [416]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[417] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_79_out[1]),
        .Q(\my_empty_reg[7]_0 [417]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[418] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_80_out[0]),
        .Q(\my_empty_reg[7]_0 [418]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[419] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_80_out[1]),
        .Q(\my_empty_reg[7]_0 [419]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_269_out[1]),
        .Q(\my_empty_reg[7]_0 [41]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[420] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_75_out[0]),
        .Q(\my_empty_reg[7]_0 [420]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[421] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_75_out[1]),
        .Q(\my_empty_reg[7]_0 [421]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[422] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_76_out[0]),
        .Q(\my_empty_reg[7]_0 [422]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[423] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_76_out[1]),
        .Q(\my_empty_reg[7]_0 [423]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[424] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_77_out[0]),
        .Q(\my_empty_reg[7]_0 [424]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[425] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_77_out[1]),
        .Q(\my_empty_reg[7]_0 [425]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[426] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_72_out[0]),
        .Q(\my_empty_reg[7]_0 [426]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[427] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_72_out[1]),
        .Q(\my_empty_reg[7]_0 [427]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[428] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_73_out[0]),
        .Q(\my_empty_reg[7]_0 [428]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[429] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_73_out[1]),
        .Q(\my_empty_reg[7]_0 [429]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_264_out[0]),
        .Q(\my_empty_reg[7]_0 [42]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[430] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_74_out[0]),
        .Q(\my_empty_reg[7]_0 [430]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[431] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_74_out[1]),
        .Q(\my_empty_reg[7]_0 [431]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[432] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_69_out[0]),
        .Q(\my_empty_reg[7]_0 [432]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[433] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_69_out[1]),
        .Q(\my_empty_reg[7]_0 [433]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[434] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_70_out[0]),
        .Q(\my_empty_reg[7]_0 [434]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[435] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_70_out[1]),
        .Q(\my_empty_reg[7]_0 [435]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[436] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_71_out[0]),
        .Q(\my_empty_reg[7]_0 [436]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[437] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_71_out[1]),
        .Q(\my_empty_reg[7]_0 [437]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[438] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_66_out[0]),
        .Q(\my_empty_reg[7]_0 [438]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[439] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_66_out[1]),
        .Q(\my_empty_reg[7]_0 [439]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_264_out[1]),
        .Q(\my_empty_reg[7]_0 [43]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[440] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_67_out[0]),
        .Q(\my_empty_reg[7]_0 [440]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[441] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_67_out[1]),
        .Q(\my_empty_reg[7]_0 [441]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[442] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_68_out[0]),
        .Q(\my_empty_reg[7]_0 [442]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[443] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_68_out[1]),
        .Q(\my_empty_reg[7]_0 [443]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[444] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_63_out[0]),
        .Q(\my_empty_reg[7]_0 [444]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[445] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_63_out[1]),
        .Q(\my_empty_reg[7]_0 [445]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[446] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_64_out[0]),
        .Q(\my_empty_reg[7]_0 [446]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[447] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_64_out[1]),
        .Q(\my_empty_reg[7]_0 [447]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[448] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_65_out[0]),
        .Q(\my_empty_reg[7]_0 [448]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[449] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_65_out[1]),
        .Q(\my_empty_reg[7]_0 [449]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_265_out[0]),
        .Q(\my_empty_reg[7]_0 [44]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[450] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_60_out[0]),
        .Q(\my_empty_reg[7]_0 [450]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[451] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_60_out[1]),
        .Q(\my_empty_reg[7]_0 [451]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[452] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_61_out[0]),
        .Q(\my_empty_reg[7]_0 [452]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[453] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_61_out[1]),
        .Q(\my_empty_reg[7]_0 [453]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[454] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_62_out[0]),
        .Q(\my_empty_reg[7]_0 [454]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[455] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_62_out[1]),
        .Q(\my_empty_reg[7]_0 [455]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[456] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_57_out[0]),
        .Q(\my_empty_reg[7]_0 [456]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[457] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_57_out[1]),
        .Q(\my_empty_reg[7]_0 [457]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[458] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_58_out[0]),
        .Q(\my_empty_reg[7]_0 [458]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[459] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_58_out[1]),
        .Q(\my_empty_reg[7]_0 [459]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_265_out[1]),
        .Q(\my_empty_reg[7]_0 [45]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[460] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_59_out[0]),
        .Q(\my_empty_reg[7]_0 [460]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[461] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_59_out[1]),
        .Q(\my_empty_reg[7]_0 [461]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[462] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_54_out[0]),
        .Q(\my_empty_reg[7]_0 [462]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[463] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_54_out[1]),
        .Q(\my_empty_reg[7]_0 [463]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[464] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_55_out[0]),
        .Q(\my_empty_reg[7]_0 [464]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[465] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_55_out[1]),
        .Q(\my_empty_reg[7]_0 [465]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[466] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_56_out[0]),
        .Q(\my_empty_reg[7]_0 [466]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[467] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_56_out[1]),
        .Q(\my_empty_reg[7]_0 [467]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[468] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_51_out[0]),
        .Q(\my_empty_reg[7]_0 [468]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[469] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_51_out[1]),
        .Q(\my_empty_reg[7]_0 [469]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_266_out[0]),
        .Q(\my_empty_reg[7]_0 [46]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[470] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_52_out[0]),
        .Q(\my_empty_reg[7]_0 [470]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[471] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_52_out[1]),
        .Q(\my_empty_reg[7]_0 [471]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[472] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_53_out[0]),
        .Q(\my_empty_reg[7]_0 [472]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[473] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_53_out[1]),
        .Q(\my_empty_reg[7]_0 [473]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[474] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_48_out[0]),
        .Q(\my_empty_reg[7]_0 [474]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[475] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_48_out[1]),
        .Q(\my_empty_reg[7]_0 [475]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[476] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_49_out[0]),
        .Q(\my_empty_reg[7]_0 [476]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[477] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_49_out[1]),
        .Q(\my_empty_reg[7]_0 [477]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[478] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_50_out[0]),
        .Q(\my_empty_reg[7]_0 [478]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[479] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_50_out[1]),
        .Q(\my_empty_reg[7]_0 [479]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_266_out[1]),
        .Q(\my_empty_reg[7]_0 [47]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[480] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_45_out[0]),
        .Q(\my_empty_reg[7]_0 [480]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[481] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_45_out[1]),
        .Q(\my_empty_reg[7]_0 [481]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[482] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_46_out[0]),
        .Q(\my_empty_reg[7]_0 [482]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[483] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_46_out[1]),
        .Q(\my_empty_reg[7]_0 [483]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[484] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_47_out[0]),
        .Q(\my_empty_reg[7]_0 [484]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[485] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_47_out[1]),
        .Q(\my_empty_reg[7]_0 [485]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[486] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_42_out[0]),
        .Q(\my_empty_reg[7]_0 [486]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[487] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_42_out[1]),
        .Q(\my_empty_reg[7]_0 [487]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[488] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_43_out[0]),
        .Q(\my_empty_reg[7]_0 [488]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[489] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_43_out[1]),
        .Q(\my_empty_reg[7]_0 [489]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_261_out[0]),
        .Q(\my_empty_reg[7]_0 [48]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[490] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_44_out[0]),
        .Q(\my_empty_reg[7]_0 [490]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[491] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_44_out[1]),
        .Q(\my_empty_reg[7]_0 [491]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[492] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_39_out[0]),
        .Q(\my_empty_reg[7]_0 [492]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[493] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_39_out[1]),
        .Q(\my_empty_reg[7]_0 [493]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[494] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_40_out[0]),
        .Q(\my_empty_reg[7]_0 [494]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[495] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_40_out[1]),
        .Q(\my_empty_reg[7]_0 [495]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[496] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_41_out[0]),
        .Q(\my_empty_reg[7]_0 [496]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[497] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_41_out[1]),
        .Q(\my_empty_reg[7]_0 [497]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[498] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_36_out[0]),
        .Q(\my_empty_reg[7]_0 [498]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[499] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_36_out[1]),
        .Q(\my_empty_reg[7]_0 [499]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_261_out[1]),
        .Q(\my_empty_reg[7]_0 [49]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_287_out[0]),
        .Q(\my_empty_reg[7]_0 [4]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[500] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_37_out[0]),
        .Q(\my_empty_reg[7]_0 [500]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[501] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_37_out[1]),
        .Q(\my_empty_reg[7]_0 [501]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[502] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_38_out[0]),
        .Q(\my_empty_reg[7]_0 [502]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[503] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_38_out[1]),
        .Q(\my_empty_reg[7]_0 [503]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[504] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_33_out[0]),
        .Q(\my_empty_reg[7]_0 [504]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[505] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_33_out[1]),
        .Q(\my_empty_reg[7]_0 [505]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[506] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_34_out[0]),
        .Q(\my_empty_reg[7]_0 [506]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[507] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_34_out[1]),
        .Q(\my_empty_reg[7]_0 [507]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[508] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_35_out[0]),
        .Q(\my_empty_reg[7]_0 [508]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[509] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_35_out[1]),
        .Q(\my_empty_reg[7]_0 [509]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_262_out[0]),
        .Q(\my_empty_reg[7]_0 [50]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[510] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_30_out[0]),
        .Q(\my_empty_reg[7]_0 [510]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[511] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_30_out[1]),
        .Q(\my_empty_reg[7]_0 [511]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[512] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_31_out[0]),
        .Q(\my_empty_reg[7]_0 [512]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[513] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_31_out[1]),
        .Q(\my_empty_reg[7]_0 [513]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[514] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_32_out[0]),
        .Q(\my_empty_reg[7]_0 [514]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[515] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_32_out[1]),
        .Q(\my_empty_reg[7]_0 [515]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[516] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_27_out[0]),
        .Q(\my_empty_reg[7]_0 [516]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[517] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_27_out[1]),
        .Q(\my_empty_reg[7]_0 [517]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[518] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_28_out[0]),
        .Q(\my_empty_reg[7]_0 [518]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[519] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_28_out[1]),
        .Q(\my_empty_reg[7]_0 [519]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_262_out[1]),
        .Q(\my_empty_reg[7]_0 [51]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[520] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_29_out[0]),
        .Q(\my_empty_reg[7]_0 [520]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[521] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_29_out[1]),
        .Q(\my_empty_reg[7]_0 [521]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[522] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_24_out[0]),
        .Q(\my_empty_reg[7]_0 [522]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[523] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_24_out[1]),
        .Q(\my_empty_reg[7]_0 [523]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[524] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_25_out[0]),
        .Q(\my_empty_reg[7]_0 [524]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[525] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_25_out[1]),
        .Q(\my_empty_reg[7]_0 [525]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[526] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_26_out[0]),
        .Q(\my_empty_reg[7]_0 [526]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[527] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_26_out[1]),
        .Q(\my_empty_reg[7]_0 [527]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[528] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_21_out[0]),
        .Q(\my_empty_reg[7]_0 [528]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[529] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_21_out[1]),
        .Q(\my_empty_reg[7]_0 [529]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_263_out[0]),
        .Q(\my_empty_reg[7]_0 [52]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[530] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_22_out[0]),
        .Q(\my_empty_reg[7]_0 [530]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[531] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_22_out[1]),
        .Q(\my_empty_reg[7]_0 [531]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[532] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_23_out[0]),
        .Q(\my_empty_reg[7]_0 [532]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[533] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_23_out[1]),
        .Q(\my_empty_reg[7]_0 [533]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[534] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_18_out[0]),
        .Q(\my_empty_reg[7]_0 [534]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[535] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_18_out[1]),
        .Q(\my_empty_reg[7]_0 [535]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[536] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_19_out[0]),
        .Q(\my_empty_reg[7]_0 [536]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[537] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_19_out[1]),
        .Q(\my_empty_reg[7]_0 [537]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[538] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_20_out[0]),
        .Q(\my_empty_reg[7]_0 [538]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[539] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_20_out[1]),
        .Q(\my_empty_reg[7]_0 [539]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_263_out[1]),
        .Q(\my_empty_reg[7]_0 [53]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[540] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_15_out[0]),
        .Q(\my_empty_reg[7]_0 [540]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[541] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_15_out[1]),
        .Q(\my_empty_reg[7]_0 [541]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[542] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_16_out[0]),
        .Q(\my_empty_reg[7]_0 [542]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[543] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_16_out[1]),
        .Q(\my_empty_reg[7]_0 [543]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[544] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_17_out[0]),
        .Q(\my_empty_reg[7]_0 [544]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[545] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_17_out[1]),
        .Q(\my_empty_reg[7]_0 [545]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[546] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_12_out[0]),
        .Q(\my_empty_reg[7]_0 [546]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[547] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_12_out[1]),
        .Q(\my_empty_reg[7]_0 [547]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[548] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_13_out[0]),
        .Q(\my_empty_reg[7]_0 [548]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[549] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_13_out[1]),
        .Q(\my_empty_reg[7]_0 [549]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_258_out[0]),
        .Q(\my_empty_reg[7]_0 [54]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[550] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_14_out[0]),
        .Q(\my_empty_reg[7]_0 [550]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[551] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_14_out[1]),
        .Q(\my_empty_reg[7]_0 [551]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[552] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_9_out[0]),
        .Q(\my_empty_reg[7]_0 [552]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[553] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_9_out[1]),
        .Q(\my_empty_reg[7]_0 [553]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[554] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_10_out[0]),
        .Q(\my_empty_reg[7]_0 [554]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[555] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_10_out[1]),
        .Q(\my_empty_reg[7]_0 [555]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[556] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_11_out[0]),
        .Q(\my_empty_reg[7]_0 [556]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[557] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_11_out[1]),
        .Q(\my_empty_reg[7]_0 [557]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[558] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_6_out[0]),
        .Q(\my_empty_reg[7]_0 [558]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[559] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_6_out[1]),
        .Q(\my_empty_reg[7]_0 [559]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_258_out[1]),
        .Q(\my_empty_reg[7]_0 [55]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[560] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_7_out[0]),
        .Q(\my_empty_reg[7]_0 [560]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[561] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_7_out[1]),
        .Q(\my_empty_reg[7]_0 [561]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[562] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_8_out[0]),
        .Q(\my_empty_reg[7]_0 [562]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[563] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_8_out[1]),
        .Q(\my_empty_reg[7]_0 [563]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[564] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[94].RAM32M0_n_5 ),
        .Q(\my_empty_reg[7]_0 [564]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[565] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[94].RAM32M0_n_4 ),
        .Q(\my_empty_reg[7]_0 [565]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[566] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_4_out[0]),
        .Q(\my_empty_reg[7]_0 [566]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[567] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_4_out[1]),
        .Q(\my_empty_reg[7]_0 [567]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[568] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_5_out[0]),
        .Q(\my_empty_reg[7]_0 [568]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[569] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_5_out[1]),
        .Q(\my_empty_reg[7]_0 [569]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_259_out[0]),
        .Q(\my_empty_reg[7]_0 [56]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[570] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[95].RAM32M0_n_5 ),
        .Q(\my_empty_reg[7]_0 [570]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[571] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[95].RAM32M0_n_4 ),
        .Q(\my_empty_reg[7]_0 [571]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[572] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[95].RAM32M0_n_3 ),
        .Q(\my_empty_reg[7]_0 [572]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[573] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[95].RAM32M0_n_2 ),
        .Q(\my_empty_reg[7]_0 [573]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[574] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[95].RAM32M0_n_1 ),
        .Q(\my_empty_reg[7]_0 [574]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[575] 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_buffer.wr_buffer_ram[95].RAM32M0_n_0 ),
        .Q(\my_empty_reg[7]_0 [575]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_259_out[1]),
        .Q(\my_empty_reg[7]_0 [57]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_260_out[0]),
        .Q(\my_empty_reg[7]_0 [58]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_260_out[1]),
        .Q(\my_empty_reg[7]_0 [59]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_287_out[1]),
        .Q(\my_empty_reg[7]_0 [5]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_255_out[0]),
        .Q(\my_empty_reg[7]_0 [60]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_255_out[1]),
        .Q(\my_empty_reg[7]_0 [61]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_256_out[0]),
        .Q(\my_empty_reg[7]_0 [62]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_256_out[1]),
        .Q(\my_empty_reg[7]_0 [63]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_257_out[0]),
        .Q(\my_empty_reg[7]_0 [64]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_257_out[1]),
        .Q(\my_empty_reg[7]_0 [65]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_252_out[0]),
        .Q(\my_empty_reg[7]_0 [66]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_252_out[1]),
        .Q(\my_empty_reg[7]_0 [67]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_253_out[0]),
        .Q(\my_empty_reg[7]_0 [68]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_253_out[1]),
        .Q(\my_empty_reg[7]_0 [69]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_282_out[0]),
        .Q(\my_empty_reg[7]_0 [6]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_254_out[0]),
        .Q(\my_empty_reg[7]_0 [70]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_254_out[1]),
        .Q(\my_empty_reg[7]_0 [71]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[72] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_249_out[0]),
        .Q(\my_empty_reg[7]_0 [72]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[73] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_249_out[1]),
        .Q(\my_empty_reg[7]_0 [73]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[74] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_250_out[0]),
        .Q(\my_empty_reg[7]_0 [74]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[75] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_250_out[1]),
        .Q(\my_empty_reg[7]_0 [75]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[76] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_251_out[0]),
        .Q(\my_empty_reg[7]_0 [76]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[77] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_251_out[1]),
        .Q(\my_empty_reg[7]_0 [77]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[78] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_246_out[0]),
        .Q(\my_empty_reg[7]_0 [78]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[79] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_246_out[1]),
        .Q(\my_empty_reg[7]_0 [79]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_282_out[1]),
        .Q(\my_empty_reg[7]_0 [7]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[80] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_247_out[0]),
        .Q(\my_empty_reg[7]_0 [80]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[81] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_247_out[1]),
        .Q(\my_empty_reg[7]_0 [81]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[82] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_248_out[0]),
        .Q(\my_empty_reg[7]_0 [82]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[83] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_248_out[1]),
        .Q(\my_empty_reg[7]_0 [83]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[84] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_243_out[0]),
        .Q(\my_empty_reg[7]_0 [84]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[85] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_243_out[1]),
        .Q(\my_empty_reg[7]_0 [85]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[86] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_244_out[0]),
        .Q(\my_empty_reg[7]_0 [86]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[87] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_244_out[1]),
        .Q(\my_empty_reg[7]_0 [87]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[88] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_245_out[0]),
        .Q(\my_empty_reg[7]_0 [88]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[89] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_245_out[1]),
        .Q(\my_empty_reg[7]_0 [89]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_283_out[0]),
        .Q(\my_empty_reg[7]_0 [8]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[90] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_240_out[0]),
        .Q(\my_empty_reg[7]_0 [90]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[91] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_240_out[1]),
        .Q(\my_empty_reg[7]_0 [91]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[92] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_241_out[0]),
        .Q(\my_empty_reg[7]_0 [92]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[93] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_241_out[1]),
        .Q(\my_empty_reg[7]_0 [93]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[94] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_242_out[0]),
        .Q(\my_empty_reg[7]_0 [94]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[95] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_242_out[1]),
        .Q(\my_empty_reg[7]_0 [95]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[96] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_237_out[0]),
        .Q(\my_empty_reg[7]_0 [96]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[97] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_237_out[1]),
        .Q(\my_empty_reg[7]_0 [97]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[98] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_238_out[0]),
        .Q(\my_empty_reg[7]_0 [98]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[99] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_238_out[1]),
        .Q(\my_empty_reg[7]_0 [99]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_283_out[1]),
        .Q(\my_empty_reg[7]_0 [9]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[5:4]),
        .DIB(wr_buf_in_data[3:2]),
        .DIC(wr_buf_in_data[1:0]),
        .DID({1'b0,1'b0}),
        .DOA(p_287_out),
        .DOB(p_286_out),
        .DOC(p_285_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_1 
       (.I0(app_wdf_data[5]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[5]),
        .O(wr_buf_in_data[5]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_10 
       (.I0(wb_wr_data_addr_r[1]),
        .I1(wr_data_addr_le),
        .I2(wr_data_pntr[0]),
        .I3(reset_reg),
        .O(wb_wr_data_addr_w[1]));
  LUT5 #(
    .INIT(32'h04540404)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_11 
       (.I0(reset_reg),
        .I1(wb_wr_data_addr0_r),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(app_wdf_rdy),
        .O(\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_2 
       (.I0(app_wdf_data[4]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[4]),
        .O(wr_buf_in_data[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_3 
       (.I0(app_wdf_data[3]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[3]),
        .O(wr_buf_in_data[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_4 
       (.I0(app_wdf_data[2]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[2]),
        .O(wr_buf_in_data[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_5 
       (.I0(app_wdf_data[1]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[1]),
        .O(wr_buf_in_data[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_6 
       (.I0(app_wdf_data[0]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[0]),
        .O(wr_buf_in_data[0]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_7 
       (.I0(wb_wr_data_addr_r[4]),
        .I1(wr_data_addr_le),
        .I2(wr_data_pntr[3]),
        .I3(reset_reg),
        .O(wb_wr_data_addr_w[4]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_8 
       (.I0(wb_wr_data_addr_r[3]),
        .I1(wr_data_addr_le),
        .I2(wr_data_pntr[2]),
        .I3(reset_reg),
        .O(wb_wr_data_addr_w[3]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_9 
       (.I0(wb_wr_data_addr_r[2]),
        .I1(wr_data_addr_le),
        .I2(wr_data_pntr[1]),
        .I3(reset_reg),
        .O(wb_wr_data_addr_w[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[65:64]),
        .DIB(wr_buf_in_data[63:62]),
        .DIC(wr_buf_in_data[61:60]),
        .DID({1'b0,1'b0}),
        .DOA(p_257_out),
        .DOB(p_256_out),
        .DOC(p_255_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_1 
       (.I0(app_wdf_data[65]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[65]),
        .O(wr_buf_in_data[65]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_2 
       (.I0(app_wdf_data[64]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[64]),
        .O(wr_buf_in_data[64]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_3 
       (.I0(app_wdf_data[63]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[63]),
        .O(wr_buf_in_data[63]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_4 
       (.I0(app_wdf_data[62]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[62]),
        .O(wr_buf_in_data[62]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_5 
       (.I0(app_wdf_data[61]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[61]),
        .O(wr_buf_in_data[61]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_6 
       (.I0(app_wdf_data[60]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[60]),
        .O(wr_buf_in_data[60]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[71:70]),
        .DIB(wr_buf_in_data[69:68]),
        .DIC(wr_buf_in_data[67:66]),
        .DID({1'b0,1'b0}),
        .DOA(p_254_out),
        .DOB(p_253_out),
        .DOC(p_252_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_1 
       (.I0(app_wdf_data[71]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[71]),
        .O(wr_buf_in_data[71]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_2 
       (.I0(app_wdf_data[70]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[70]),
        .O(wr_buf_in_data[70]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_3 
       (.I0(app_wdf_data[69]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[69]),
        .O(wr_buf_in_data[69]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_4 
       (.I0(app_wdf_data[68]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[68]),
        .O(wr_buf_in_data[68]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_5 
       (.I0(app_wdf_data[67]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[67]),
        .O(wr_buf_in_data[67]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_6 
       (.I0(app_wdf_data[66]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[66]),
        .O(wr_buf_in_data[66]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[77:76]),
        .DIB(wr_buf_in_data[75:74]),
        .DIC(wr_buf_in_data[73:72]),
        .DID({1'b0,1'b0}),
        .DOA(p_251_out),
        .DOB(p_250_out),
        .DOC(p_249_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_1 
       (.I0(app_wdf_data[77]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[77]),
        .O(wr_buf_in_data[77]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_2 
       (.I0(app_wdf_data[76]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[76]),
        .O(wr_buf_in_data[76]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_3 
       (.I0(app_wdf_data[75]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[75]),
        .O(wr_buf_in_data[75]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_4 
       (.I0(app_wdf_data[74]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[74]),
        .O(wr_buf_in_data[74]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_5 
       (.I0(app_wdf_data[73]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[73]),
        .O(wr_buf_in_data[73]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_6 
       (.I0(app_wdf_data[72]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[72]),
        .O(wr_buf_in_data[72]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[83:82]),
        .DIB(wr_buf_in_data[81:80]),
        .DIC(wr_buf_in_data[79:78]),
        .DID({1'b0,1'b0}),
        .DOA(p_248_out),
        .DOB(p_247_out),
        .DOC(p_246_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_1 
       (.I0(app_wdf_data[83]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[83]),
        .O(wr_buf_in_data[83]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_2 
       (.I0(app_wdf_data[82]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[82]),
        .O(wr_buf_in_data[82]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_3 
       (.I0(app_wdf_data[81]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[81]),
        .O(wr_buf_in_data[81]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_4 
       (.I0(app_wdf_data[80]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[80]),
        .O(wr_buf_in_data[80]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_5 
       (.I0(app_wdf_data[79]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[79]),
        .O(wr_buf_in_data[79]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_6 
       (.I0(app_wdf_data[78]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[78]),
        .O(wr_buf_in_data[78]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[89:88]),
        .DIB(wr_buf_in_data[87:86]),
        .DIC(wr_buf_in_data[85:84]),
        .DID({1'b0,1'b0}),
        .DOA(p_245_out),
        .DOB(p_244_out),
        .DOC(p_243_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_1 
       (.I0(app_wdf_data[89]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[89]),
        .O(wr_buf_in_data[89]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_2 
       (.I0(app_wdf_data[88]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[88]),
        .O(wr_buf_in_data[88]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_3 
       (.I0(app_wdf_data[87]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[87]),
        .O(wr_buf_in_data[87]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_4 
       (.I0(app_wdf_data[86]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[86]),
        .O(wr_buf_in_data[86]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_5 
       (.I0(app_wdf_data[85]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[85]),
        .O(wr_buf_in_data[85]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_6 
       (.I0(app_wdf_data[84]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[84]),
        .O(wr_buf_in_data[84]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[95:94]),
        .DIB(wr_buf_in_data[93:92]),
        .DIC(wr_buf_in_data[91:90]),
        .DID({1'b0,1'b0}),
        .DOA(p_242_out),
        .DOB(p_241_out),
        .DOC(p_240_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_1 
       (.I0(app_wdf_data[95]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[95]),
        .O(wr_buf_in_data[95]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_2 
       (.I0(app_wdf_data[94]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[94]),
        .O(wr_buf_in_data[94]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_3 
       (.I0(app_wdf_data[93]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[93]),
        .O(wr_buf_in_data[93]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_4 
       (.I0(app_wdf_data[92]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[92]),
        .O(wr_buf_in_data[92]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_5 
       (.I0(app_wdf_data[91]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[91]),
        .O(wr_buf_in_data[91]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_6 
       (.I0(app_wdf_data[90]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[90]),
        .O(wr_buf_in_data[90]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[101:100]),
        .DIB(wr_buf_in_data[99:98]),
        .DIC(wr_buf_in_data[97:96]),
        .DID({1'b0,1'b0}),
        .DOA(p_239_out),
        .DOB(p_238_out),
        .DOC(p_237_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_1 
       (.I0(app_wdf_data[101]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[101]),
        .O(wr_buf_in_data[101]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_2 
       (.I0(app_wdf_data[100]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[100]),
        .O(wr_buf_in_data[100]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_3 
       (.I0(app_wdf_data[99]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[99]),
        .O(wr_buf_in_data[99]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_4 
       (.I0(app_wdf_data[98]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[98]),
        .O(wr_buf_in_data[98]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_5 
       (.I0(app_wdf_data[97]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[97]),
        .O(wr_buf_in_data[97]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_6 
       (.I0(app_wdf_data[96]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[96]),
        .O(wr_buf_in_data[96]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[107:106]),
        .DIB(wr_buf_in_data[105:104]),
        .DIC(wr_buf_in_data[103:102]),
        .DID({1'b0,1'b0}),
        .DOA(p_236_out),
        .DOB(p_235_out),
        .DOC(p_234_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_1 
       (.I0(app_wdf_data[107]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[107]),
        .O(wr_buf_in_data[107]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_2 
       (.I0(app_wdf_data[106]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[106]),
        .O(wr_buf_in_data[106]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_3 
       (.I0(app_wdf_data[105]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[105]),
        .O(wr_buf_in_data[105]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_4 
       (.I0(app_wdf_data[104]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[104]),
        .O(wr_buf_in_data[104]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_5 
       (.I0(app_wdf_data[103]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[103]),
        .O(wr_buf_in_data[103]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_6 
       (.I0(app_wdf_data[102]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[102]),
        .O(wr_buf_in_data[102]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[113:112]),
        .DIB(wr_buf_in_data[111:110]),
        .DIC(wr_buf_in_data[109:108]),
        .DID({1'b0,1'b0}),
        .DOA(p_233_out),
        .DOB(p_232_out),
        .DOC(p_231_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_1 
       (.I0(app_wdf_data[113]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[113]),
        .O(wr_buf_in_data[113]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_2 
       (.I0(app_wdf_data[112]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[112]),
        .O(wr_buf_in_data[112]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_3 
       (.I0(app_wdf_data[111]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[111]),
        .O(wr_buf_in_data[111]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_4 
       (.I0(app_wdf_data[110]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[110]),
        .O(wr_buf_in_data[110]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_5 
       (.I0(app_wdf_data[109]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[109]),
        .O(wr_buf_in_data[109]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_6 
       (.I0(app_wdf_data[108]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[108]),
        .O(wr_buf_in_data[108]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[119:118]),
        .DIB(wr_buf_in_data[117:116]),
        .DIC(wr_buf_in_data[115:114]),
        .DID({1'b0,1'b0}),
        .DOA(p_230_out),
        .DOB(p_229_out),
        .DOC(p_228_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_1 
       (.I0(app_wdf_data[119]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[119]),
        .O(wr_buf_in_data[119]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_2 
       (.I0(app_wdf_data[118]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[118]),
        .O(wr_buf_in_data[118]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_3 
       (.I0(app_wdf_data[117]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[117]),
        .O(wr_buf_in_data[117]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_4 
       (.I0(app_wdf_data[116]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[116]),
        .O(wr_buf_in_data[116]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_5 
       (.I0(app_wdf_data[115]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[115]),
        .O(wr_buf_in_data[115]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_6 
       (.I0(app_wdf_data[114]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[114]),
        .O(wr_buf_in_data[114]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[11:10]),
        .DIB(wr_buf_in_data[9:8]),
        .DIC(wr_buf_in_data[7:6]),
        .DID({1'b0,1'b0}),
        .DOA(p_284_out),
        .DOB(p_283_out),
        .DOC(p_282_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_1 
       (.I0(app_wdf_data[11]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[11]),
        .O(wr_buf_in_data[11]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_2 
       (.I0(app_wdf_data[10]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[10]),
        .O(wr_buf_in_data[10]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_3 
       (.I0(app_wdf_data[9]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[9]),
        .O(wr_buf_in_data[9]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_4 
       (.I0(app_wdf_data[8]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[8]),
        .O(wr_buf_in_data[8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_5 
       (.I0(app_wdf_data[7]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[7]),
        .O(wr_buf_in_data[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_6 
       (.I0(app_wdf_data[6]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[6]),
        .O(wr_buf_in_data[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[125:124]),
        .DIB(wr_buf_in_data[123:122]),
        .DIC(wr_buf_in_data[121:120]),
        .DID({1'b0,1'b0}),
        .DOA(p_227_out),
        .DOB(p_226_out),
        .DOC(p_225_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_1 
       (.I0(app_wdf_data[125]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[125]),
        .O(wr_buf_in_data[125]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_2 
       (.I0(app_wdf_data[124]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[124]),
        .O(wr_buf_in_data[124]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_3 
       (.I0(app_wdf_data[123]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[123]),
        .O(wr_buf_in_data[123]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_4 
       (.I0(app_wdf_data[122]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[122]),
        .O(wr_buf_in_data[122]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_5 
       (.I0(app_wdf_data[121]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[121]),
        .O(wr_buf_in_data[121]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_6 
       (.I0(app_wdf_data[120]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[120]),
        .O(wr_buf_in_data[120]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[131:130]),
        .DIB(wr_buf_in_data[129:128]),
        .DIC(wr_buf_in_data[127:126]),
        .DID({1'b0,1'b0}),
        .DOA(p_224_out),
        .DOB(p_223_out),
        .DOC(p_222_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_1 
       (.I0(app_wdf_data[131]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[131]),
        .O(wr_buf_in_data[131]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_2 
       (.I0(app_wdf_data[130]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[130]),
        .O(wr_buf_in_data[130]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_3 
       (.I0(app_wdf_data[129]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[129]),
        .O(wr_buf_in_data[129]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_4 
       (.I0(app_wdf_data[128]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[128]),
        .O(wr_buf_in_data[128]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_5 
       (.I0(app_wdf_data[127]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[127]),
        .O(wr_buf_in_data[127]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_6 
       (.I0(app_wdf_data[126]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[126]),
        .O(wr_buf_in_data[126]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[137:136]),
        .DIB(wr_buf_in_data[135:134]),
        .DIC(wr_buf_in_data[133:132]),
        .DID({1'b0,1'b0}),
        .DOA(p_221_out),
        .DOB(p_220_out),
        .DOC(p_219_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_1 
       (.I0(app_wdf_data[137]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[137]),
        .O(wr_buf_in_data[137]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_2 
       (.I0(app_wdf_data[136]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[136]),
        .O(wr_buf_in_data[136]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_3 
       (.I0(app_wdf_data[135]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[135]),
        .O(wr_buf_in_data[135]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_4 
       (.I0(app_wdf_data[134]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[134]),
        .O(wr_buf_in_data[134]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_5 
       (.I0(app_wdf_data[133]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[133]),
        .O(wr_buf_in_data[133]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_6 
       (.I0(app_wdf_data[132]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[132]),
        .O(wr_buf_in_data[132]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[143:142]),
        .DIB(wr_buf_in_data[141:140]),
        .DIC(wr_buf_in_data[139:138]),
        .DID({1'b0,1'b0}),
        .DOA(p_218_out),
        .DOB(p_217_out),
        .DOC(p_216_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_1 
       (.I0(app_wdf_data[143]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[143]),
        .O(wr_buf_in_data[143]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_2 
       (.I0(app_wdf_data[142]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[142]),
        .O(wr_buf_in_data[142]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_3 
       (.I0(app_wdf_data[141]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[141]),
        .O(wr_buf_in_data[141]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_4 
       (.I0(app_wdf_data[140]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[140]),
        .O(wr_buf_in_data[140]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_5 
       (.I0(app_wdf_data[139]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[139]),
        .O(wr_buf_in_data[139]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_6 
       (.I0(app_wdf_data[138]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[138]),
        .O(wr_buf_in_data[138]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[149:148]),
        .DIB(wr_buf_in_data[147:146]),
        .DIC(wr_buf_in_data[145:144]),
        .DID({1'b0,1'b0}),
        .DOA(p_215_out),
        .DOB(p_214_out),
        .DOC(p_213_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_1 
       (.I0(app_wdf_data[149]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[149]),
        .O(wr_buf_in_data[149]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_2 
       (.I0(app_wdf_data[148]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[148]),
        .O(wr_buf_in_data[148]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_3 
       (.I0(app_wdf_data[147]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[147]),
        .O(wr_buf_in_data[147]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_4 
       (.I0(app_wdf_data[146]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[146]),
        .O(wr_buf_in_data[146]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_5 
       (.I0(app_wdf_data[145]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[145]),
        .O(wr_buf_in_data[145]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_6 
       (.I0(app_wdf_data[144]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[144]),
        .O(wr_buf_in_data[144]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[155:154]),
        .DIB(wr_buf_in_data[153:152]),
        .DIC(wr_buf_in_data[151:150]),
        .DID({1'b0,1'b0}),
        .DOA(p_212_out),
        .DOB(p_211_out),
        .DOC(p_210_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_1 
       (.I0(app_wdf_data[155]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[155]),
        .O(wr_buf_in_data[155]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_2 
       (.I0(app_wdf_data[154]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[154]),
        .O(wr_buf_in_data[154]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_3 
       (.I0(app_wdf_data[153]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[153]),
        .O(wr_buf_in_data[153]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_4 
       (.I0(app_wdf_data[152]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[152]),
        .O(wr_buf_in_data[152]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_5 
       (.I0(app_wdf_data[151]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[151]),
        .O(wr_buf_in_data[151]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_6 
       (.I0(app_wdf_data[150]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[150]),
        .O(wr_buf_in_data[150]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[161:160]),
        .DIB(wr_buf_in_data[159:158]),
        .DIC(wr_buf_in_data[157:156]),
        .DID({1'b0,1'b0}),
        .DOA(p_209_out),
        .DOB(p_208_out),
        .DOC(p_207_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_1 
       (.I0(app_wdf_data[161]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[161]),
        .O(wr_buf_in_data[161]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_2 
       (.I0(app_wdf_data[160]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[160]),
        .O(wr_buf_in_data[160]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_3 
       (.I0(app_wdf_data[159]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[159]),
        .O(wr_buf_in_data[159]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_4 
       (.I0(app_wdf_data[158]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[158]),
        .O(wr_buf_in_data[158]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_5 
       (.I0(app_wdf_data[157]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[157]),
        .O(wr_buf_in_data[157]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_6 
       (.I0(app_wdf_data[156]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[156]),
        .O(wr_buf_in_data[156]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[167:166]),
        .DIB(wr_buf_in_data[165:164]),
        .DIC(wr_buf_in_data[163:162]),
        .DID({1'b0,1'b0}),
        .DOA(p_206_out),
        .DOB(p_205_out),
        .DOC(p_204_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_1 
       (.I0(app_wdf_data[167]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[167]),
        .O(wr_buf_in_data[167]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_2 
       (.I0(app_wdf_data[166]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[166]),
        .O(wr_buf_in_data[166]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_3 
       (.I0(app_wdf_data[165]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[165]),
        .O(wr_buf_in_data[165]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_4 
       (.I0(app_wdf_data[164]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[164]),
        .O(wr_buf_in_data[164]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_5 
       (.I0(app_wdf_data[163]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[163]),
        .O(wr_buf_in_data[163]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_6 
       (.I0(app_wdf_data[162]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[162]),
        .O(wr_buf_in_data[162]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[173:172]),
        .DIB(wr_buf_in_data[171:170]),
        .DIC(wr_buf_in_data[169:168]),
        .DID({1'b0,1'b0}),
        .DOA(p_203_out),
        .DOB(p_202_out),
        .DOC(p_201_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_1 
       (.I0(app_wdf_data[173]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[173]),
        .O(wr_buf_in_data[173]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_2 
       (.I0(app_wdf_data[172]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[172]),
        .O(wr_buf_in_data[172]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_3 
       (.I0(app_wdf_data[171]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[171]),
        .O(wr_buf_in_data[171]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_4 
       (.I0(app_wdf_data[170]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[170]),
        .O(wr_buf_in_data[170]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_5 
       (.I0(app_wdf_data[169]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[169]),
        .O(wr_buf_in_data[169]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_6 
       (.I0(app_wdf_data[168]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[168]),
        .O(wr_buf_in_data[168]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[179:178]),
        .DIB(wr_buf_in_data[177:176]),
        .DIC(wr_buf_in_data[175:174]),
        .DID({1'b0,1'b0}),
        .DOA(p_200_out),
        .DOB(p_199_out),
        .DOC(p_198_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_1 
       (.I0(app_wdf_data[179]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[179]),
        .O(wr_buf_in_data[179]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_2 
       (.I0(app_wdf_data[178]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[178]),
        .O(wr_buf_in_data[178]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_3 
       (.I0(app_wdf_data[177]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[177]),
        .O(wr_buf_in_data[177]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_4 
       (.I0(app_wdf_data[176]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[176]),
        .O(wr_buf_in_data[176]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_5 
       (.I0(app_wdf_data[175]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[175]),
        .O(wr_buf_in_data[175]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_6 
       (.I0(app_wdf_data[174]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[174]),
        .O(wr_buf_in_data[174]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[17:16]),
        .DIB(wr_buf_in_data[15:14]),
        .DIC(wr_buf_in_data[13:12]),
        .DID({1'b0,1'b0}),
        .DOA(p_281_out),
        .DOB(p_280_out),
        .DOC(p_279_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_1 
       (.I0(app_wdf_data[17]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[17]),
        .O(wr_buf_in_data[17]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_2 
       (.I0(app_wdf_data[16]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[16]),
        .O(wr_buf_in_data[16]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_3 
       (.I0(app_wdf_data[15]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[15]),
        .O(wr_buf_in_data[15]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_4 
       (.I0(app_wdf_data[14]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[14]),
        .O(wr_buf_in_data[14]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_5 
       (.I0(app_wdf_data[13]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[13]),
        .O(wr_buf_in_data[13]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_6 
       (.I0(app_wdf_data[12]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[12]),
        .O(wr_buf_in_data[12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[185:184]),
        .DIB(wr_buf_in_data[183:182]),
        .DIC(wr_buf_in_data[181:180]),
        .DID({1'b0,1'b0}),
        .DOA(p_197_out),
        .DOB(p_196_out),
        .DOC(p_195_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_1 
       (.I0(app_wdf_data[185]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[185]),
        .O(wr_buf_in_data[185]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_2 
       (.I0(app_wdf_data[184]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[184]),
        .O(wr_buf_in_data[184]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_3 
       (.I0(app_wdf_data[183]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[183]),
        .O(wr_buf_in_data[183]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_4 
       (.I0(app_wdf_data[182]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[182]),
        .O(wr_buf_in_data[182]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_5 
       (.I0(app_wdf_data[181]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[181]),
        .O(wr_buf_in_data[181]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_6 
       (.I0(app_wdf_data[180]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[180]),
        .O(wr_buf_in_data[180]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[191:190]),
        .DIB(wr_buf_in_data[189:188]),
        .DIC(wr_buf_in_data[187:186]),
        .DID({1'b0,1'b0}),
        .DOA(p_194_out),
        .DOB(p_193_out),
        .DOC(p_192_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_1 
       (.I0(app_wdf_data[191]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[191]),
        .O(wr_buf_in_data[191]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_2 
       (.I0(app_wdf_data[190]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[190]),
        .O(wr_buf_in_data[190]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_3 
       (.I0(app_wdf_data[189]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[189]),
        .O(wr_buf_in_data[189]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_4 
       (.I0(app_wdf_data[188]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[188]),
        .O(wr_buf_in_data[188]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_5 
       (.I0(app_wdf_data[187]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[187]),
        .O(wr_buf_in_data[187]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_6 
       (.I0(app_wdf_data[186]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[186]),
        .O(wr_buf_in_data[186]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[197:196]),
        .DIB(wr_buf_in_data[195:194]),
        .DIC(wr_buf_in_data[193:192]),
        .DID({1'b0,1'b0}),
        .DOA(p_191_out),
        .DOB(p_190_out),
        .DOC(p_189_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_1 
       (.I0(app_wdf_data[197]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[197]),
        .O(wr_buf_in_data[197]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_2 
       (.I0(app_wdf_data[196]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[196]),
        .O(wr_buf_in_data[196]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_3 
       (.I0(app_wdf_data[195]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[195]),
        .O(wr_buf_in_data[195]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_4 
       (.I0(app_wdf_data[194]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[194]),
        .O(wr_buf_in_data[194]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_5 
       (.I0(app_wdf_data[193]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[193]),
        .O(wr_buf_in_data[193]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_6 
       (.I0(app_wdf_data[192]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[192]),
        .O(wr_buf_in_data[192]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[203:202]),
        .DIB(wr_buf_in_data[201:200]),
        .DIC(wr_buf_in_data[199:198]),
        .DID({1'b0,1'b0}),
        .DOA(p_188_out),
        .DOB(p_187_out),
        .DOC(p_186_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_1 
       (.I0(app_wdf_data[203]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[203]),
        .O(wr_buf_in_data[203]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_2 
       (.I0(app_wdf_data[202]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[202]),
        .O(wr_buf_in_data[202]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_3 
       (.I0(app_wdf_data[201]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[201]),
        .O(wr_buf_in_data[201]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_4 
       (.I0(app_wdf_data[200]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[200]),
        .O(wr_buf_in_data[200]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_5 
       (.I0(app_wdf_data[199]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[199]),
        .O(wr_buf_in_data[199]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_6 
       (.I0(app_wdf_data[198]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[198]),
        .O(wr_buf_in_data[198]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[209:208]),
        .DIB(wr_buf_in_data[207:206]),
        .DIC(wr_buf_in_data[205:204]),
        .DID({1'b0,1'b0}),
        .DOA(p_185_out),
        .DOB(p_184_out),
        .DOC(p_183_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_1 
       (.I0(app_wdf_data[209]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[209]),
        .O(wr_buf_in_data[209]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_2 
       (.I0(app_wdf_data[208]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[208]),
        .O(wr_buf_in_data[208]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_3 
       (.I0(app_wdf_data[207]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[207]),
        .O(wr_buf_in_data[207]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_4 
       (.I0(app_wdf_data[206]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[206]),
        .O(wr_buf_in_data[206]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_5 
       (.I0(app_wdf_data[205]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[205]),
        .O(wr_buf_in_data[205]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_6 
       (.I0(app_wdf_data[204]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[204]),
        .O(wr_buf_in_data[204]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[215:214]),
        .DIB(wr_buf_in_data[213:212]),
        .DIC(wr_buf_in_data[211:210]),
        .DID({1'b0,1'b0}),
        .DOA(p_182_out),
        .DOB(p_181_out),
        .DOC(p_180_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_1 
       (.I0(app_wdf_data[215]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[215]),
        .O(wr_buf_in_data[215]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_2 
       (.I0(app_wdf_data[214]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[214]),
        .O(wr_buf_in_data[214]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_3 
       (.I0(app_wdf_data[213]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[213]),
        .O(wr_buf_in_data[213]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_4 
       (.I0(app_wdf_data[212]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[212]),
        .O(wr_buf_in_data[212]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_5 
       (.I0(app_wdf_data[211]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[211]),
        .O(wr_buf_in_data[211]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_6 
       (.I0(app_wdf_data[210]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[210]),
        .O(wr_buf_in_data[210]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[221:220]),
        .DIB(wr_buf_in_data[219:218]),
        .DIC(wr_buf_in_data[217:216]),
        .DID({1'b0,1'b0}),
        .DOA(p_179_out),
        .DOB(p_178_out),
        .DOC(p_177_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_1 
       (.I0(app_wdf_data[221]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[221]),
        .O(wr_buf_in_data[221]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_2 
       (.I0(app_wdf_data[220]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[220]),
        .O(wr_buf_in_data[220]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_3 
       (.I0(app_wdf_data[219]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[219]),
        .O(wr_buf_in_data[219]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_4 
       (.I0(app_wdf_data[218]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[218]),
        .O(wr_buf_in_data[218]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_5 
       (.I0(app_wdf_data[217]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[217]),
        .O(wr_buf_in_data[217]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_6 
       (.I0(app_wdf_data[216]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[216]),
        .O(wr_buf_in_data[216]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[227:226]),
        .DIB(wr_buf_in_data[225:224]),
        .DIC(wr_buf_in_data[223:222]),
        .DID({1'b0,1'b0}),
        .DOA(p_176_out),
        .DOB(p_175_out),
        .DOC(p_174_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_1 
       (.I0(app_wdf_data[227]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[227]),
        .O(wr_buf_in_data[227]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_2 
       (.I0(app_wdf_data[226]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[226]),
        .O(wr_buf_in_data[226]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_3 
       (.I0(app_wdf_data[225]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[225]),
        .O(wr_buf_in_data[225]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_4 
       (.I0(app_wdf_data[224]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[224]),
        .O(wr_buf_in_data[224]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_5 
       (.I0(app_wdf_data[223]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[223]),
        .O(wr_buf_in_data[223]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_6 
       (.I0(app_wdf_data[222]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[222]),
        .O(wr_buf_in_data[222]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[233:232]),
        .DIB(wr_buf_in_data[231:230]),
        .DIC(wr_buf_in_data[229:228]),
        .DID({1'b0,1'b0}),
        .DOA(p_173_out),
        .DOB(p_172_out),
        .DOC(p_171_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_1 
       (.I0(app_wdf_data[233]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[233]),
        .O(wr_buf_in_data[233]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_2 
       (.I0(app_wdf_data[232]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[232]),
        .O(wr_buf_in_data[232]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_3 
       (.I0(app_wdf_data[231]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[231]),
        .O(wr_buf_in_data[231]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_4 
       (.I0(app_wdf_data[230]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[230]),
        .O(wr_buf_in_data[230]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_5 
       (.I0(app_wdf_data[229]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[229]),
        .O(wr_buf_in_data[229]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_6 
       (.I0(app_wdf_data[228]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[228]),
        .O(wr_buf_in_data[228]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[239:238]),
        .DIB(wr_buf_in_data[237:236]),
        .DIC(wr_buf_in_data[235:234]),
        .DID({1'b0,1'b0}),
        .DOA(p_170_out),
        .DOB(p_169_out),
        .DOC(p_168_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_1 
       (.I0(app_wdf_data[239]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[239]),
        .O(wr_buf_in_data[239]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_2 
       (.I0(app_wdf_data[238]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[238]),
        .O(wr_buf_in_data[238]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_3 
       (.I0(app_wdf_data[237]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[237]),
        .O(wr_buf_in_data[237]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_4 
       (.I0(app_wdf_data[236]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[236]),
        .O(wr_buf_in_data[236]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_5 
       (.I0(app_wdf_data[235]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[235]),
        .O(wr_buf_in_data[235]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_6 
       (.I0(app_wdf_data[234]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[234]),
        .O(wr_buf_in_data[234]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[23:22]),
        .DIB(wr_buf_in_data[21:20]),
        .DIC(wr_buf_in_data[19:18]),
        .DID({1'b0,1'b0}),
        .DOA(p_278_out),
        .DOB(p_277_out),
        .DOC(p_276_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_1 
       (.I0(app_wdf_data[23]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[23]),
        .O(wr_buf_in_data[23]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_2 
       (.I0(app_wdf_data[22]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[22]),
        .O(wr_buf_in_data[22]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_3 
       (.I0(app_wdf_data[21]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[21]),
        .O(wr_buf_in_data[21]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_4 
       (.I0(app_wdf_data[20]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[20]),
        .O(wr_buf_in_data[20]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_5 
       (.I0(app_wdf_data[19]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[19]),
        .O(wr_buf_in_data[19]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_6 
       (.I0(app_wdf_data[18]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[18]),
        .O(wr_buf_in_data[18]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[245:244]),
        .DIB(wr_buf_in_data[243:242]),
        .DIC(wr_buf_in_data[241:240]),
        .DID({1'b0,1'b0}),
        .DOA(p_167_out),
        .DOB(p_166_out),
        .DOC(p_165_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_1 
       (.I0(app_wdf_data[245]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[245]),
        .O(wr_buf_in_data[245]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_2 
       (.I0(app_wdf_data[244]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[244]),
        .O(wr_buf_in_data[244]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_3 
       (.I0(app_wdf_data[243]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[243]),
        .O(wr_buf_in_data[243]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_4 
       (.I0(app_wdf_data[242]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[242]),
        .O(wr_buf_in_data[242]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_5 
       (.I0(app_wdf_data[241]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[241]),
        .O(wr_buf_in_data[241]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_6 
       (.I0(app_wdf_data[240]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[240]),
        .O(wr_buf_in_data[240]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[251:250]),
        .DIB(wr_buf_in_data[249:248]),
        .DIC(wr_buf_in_data[247:246]),
        .DID({1'b0,1'b0}),
        .DOA(p_164_out),
        .DOB(p_163_out),
        .DOC(p_162_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_1 
       (.I0(app_wdf_data[251]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[251]),
        .O(wr_buf_in_data[251]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_2 
       (.I0(app_wdf_data[250]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[250]),
        .O(wr_buf_in_data[250]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_3 
       (.I0(app_wdf_data[249]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[249]),
        .O(wr_buf_in_data[249]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_4 
       (.I0(app_wdf_data[248]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[248]),
        .O(wr_buf_in_data[248]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_5 
       (.I0(app_wdf_data[247]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[247]),
        .O(wr_buf_in_data[247]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_6 
       (.I0(app_wdf_data[246]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[246]),
        .O(wr_buf_in_data[246]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[257:256]),
        .DIB(wr_buf_in_data[255:254]),
        .DIC(wr_buf_in_data[253:252]),
        .DID({1'b0,1'b0}),
        .DOA(p_161_out),
        .DOB(p_160_out),
        .DOC(p_159_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_1 
       (.I0(app_wdf_data[257]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[257]),
        .O(wr_buf_in_data[257]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_2 
       (.I0(app_wdf_data[256]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[256]),
        .O(wr_buf_in_data[256]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_3 
       (.I0(app_wdf_data[255]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[255]),
        .O(wr_buf_in_data[255]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_4 
       (.I0(app_wdf_data[254]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[254]),
        .O(wr_buf_in_data[254]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_5 
       (.I0(app_wdf_data[253]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[253]),
        .O(wr_buf_in_data[253]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_6 
       (.I0(app_wdf_data[252]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[252]),
        .O(wr_buf_in_data[252]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[263:262]),
        .DIB(wr_buf_in_data[261:260]),
        .DIC(wr_buf_in_data[259:258]),
        .DID({1'b0,1'b0}),
        .DOA(p_158_out),
        .DOB(p_157_out),
        .DOC(p_156_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_1 
       (.I0(app_wdf_data[263]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[263]),
        .O(wr_buf_in_data[263]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_2 
       (.I0(app_wdf_data[262]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[262]),
        .O(wr_buf_in_data[262]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_3 
       (.I0(app_wdf_data[261]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[261]),
        .O(wr_buf_in_data[261]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_4 
       (.I0(app_wdf_data[260]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[260]),
        .O(wr_buf_in_data[260]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_5 
       (.I0(app_wdf_data[259]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[259]),
        .O(wr_buf_in_data[259]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_6 
       (.I0(app_wdf_data[258]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[258]),
        .O(wr_buf_in_data[258]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[269:268]),
        .DIB(wr_buf_in_data[267:266]),
        .DIC(wr_buf_in_data[265:264]),
        .DID({1'b0,1'b0}),
        .DOA(p_155_out),
        .DOB(p_154_out),
        .DOC(p_153_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_1 
       (.I0(app_wdf_data[269]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[269]),
        .O(wr_buf_in_data[269]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_2 
       (.I0(app_wdf_data[268]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[268]),
        .O(wr_buf_in_data[268]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_3 
       (.I0(app_wdf_data[267]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[267]),
        .O(wr_buf_in_data[267]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_4 
       (.I0(app_wdf_data[266]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[266]),
        .O(wr_buf_in_data[266]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_5 
       (.I0(app_wdf_data[265]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[265]),
        .O(wr_buf_in_data[265]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_6 
       (.I0(app_wdf_data[264]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[264]),
        .O(wr_buf_in_data[264]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[275:274]),
        .DIB(wr_buf_in_data[273:272]),
        .DIC(wr_buf_in_data[271:270]),
        .DID({1'b0,1'b0}),
        .DOA(p_152_out),
        .DOB(p_151_out),
        .DOC(p_150_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_1 
       (.I0(app_wdf_data[275]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[275]),
        .O(wr_buf_in_data[275]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_2 
       (.I0(app_wdf_data[274]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[274]),
        .O(wr_buf_in_data[274]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_3 
       (.I0(app_wdf_data[273]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[273]),
        .O(wr_buf_in_data[273]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_4 
       (.I0(app_wdf_data[272]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[272]),
        .O(wr_buf_in_data[272]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_5 
       (.I0(app_wdf_data[271]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[271]),
        .O(wr_buf_in_data[271]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_6 
       (.I0(app_wdf_data[270]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[270]),
        .O(wr_buf_in_data[270]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[281:280]),
        .DIB(wr_buf_in_data[279:278]),
        .DIC(wr_buf_in_data[277:276]),
        .DID({1'b0,1'b0}),
        .DOA(p_149_out),
        .DOB(p_148_out),
        .DOC(p_147_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_1 
       (.I0(app_wdf_data[281]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[281]),
        .O(wr_buf_in_data[281]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_2 
       (.I0(app_wdf_data[280]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[280]),
        .O(wr_buf_in_data[280]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_3 
       (.I0(app_wdf_data[279]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[279]),
        .O(wr_buf_in_data[279]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_4 
       (.I0(app_wdf_data[278]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[278]),
        .O(wr_buf_in_data[278]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_5 
       (.I0(app_wdf_data[277]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[277]),
        .O(wr_buf_in_data[277]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_6 
       (.I0(app_wdf_data[276]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[276]),
        .O(wr_buf_in_data[276]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[287:286]),
        .DIB(wr_buf_in_data[285:284]),
        .DIC(wr_buf_in_data[283:282]),
        .DID({1'b0,1'b0}),
        .DOA(p_146_out),
        .DOB(p_145_out),
        .DOC(p_144_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_1 
       (.I0(app_wdf_data[287]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[287]),
        .O(wr_buf_in_data[287]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_2 
       (.I0(app_wdf_data[286]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[286]),
        .O(wr_buf_in_data[286]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_3 
       (.I0(app_wdf_data[285]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[285]),
        .O(wr_buf_in_data[285]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_4 
       (.I0(app_wdf_data[284]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[284]),
        .O(wr_buf_in_data[284]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_5 
       (.I0(app_wdf_data[283]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[283]),
        .O(wr_buf_in_data[283]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_6 
       (.I0(app_wdf_data[282]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[282]),
        .O(wr_buf_in_data[282]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[293:292]),
        .DIB(wr_buf_in_data[291:290]),
        .DIC(wr_buf_in_data[289:288]),
        .DID({1'b0,1'b0}),
        .DOA(p_143_out),
        .DOB(p_142_out),
        .DOC(p_141_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_1 
       (.I0(app_wdf_data[293]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[293]),
        .O(wr_buf_in_data[293]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_2 
       (.I0(app_wdf_data[292]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[292]),
        .O(wr_buf_in_data[292]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_3 
       (.I0(app_wdf_data[291]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[291]),
        .O(wr_buf_in_data[291]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_4 
       (.I0(app_wdf_data[290]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[290]),
        .O(wr_buf_in_data[290]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_5 
       (.I0(app_wdf_data[289]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[289]),
        .O(wr_buf_in_data[289]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_6 
       (.I0(app_wdf_data[288]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[288]),
        .O(wr_buf_in_data[288]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[299:298]),
        .DIB(wr_buf_in_data[297:296]),
        .DIC(wr_buf_in_data[295:294]),
        .DID({1'b0,1'b0}),
        .DOA(p_140_out),
        .DOB(p_139_out),
        .DOC(p_138_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_1 
       (.I0(app_wdf_data[299]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[299]),
        .O(wr_buf_in_data[299]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_2 
       (.I0(app_wdf_data[298]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[298]),
        .O(wr_buf_in_data[298]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_3 
       (.I0(app_wdf_data[297]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[297]),
        .O(wr_buf_in_data[297]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_4 
       (.I0(app_wdf_data[296]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[296]),
        .O(wr_buf_in_data[296]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_5 
       (.I0(app_wdf_data[295]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[295]),
        .O(wr_buf_in_data[295]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_6 
       (.I0(app_wdf_data[294]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[294]),
        .O(wr_buf_in_data[294]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[29:28]),
        .DIB(wr_buf_in_data[27:26]),
        .DIC(wr_buf_in_data[25:24]),
        .DID({1'b0,1'b0}),
        .DOA(p_275_out),
        .DOB(p_274_out),
        .DOC(p_273_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_1 
       (.I0(app_wdf_data[29]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[29]),
        .O(wr_buf_in_data[29]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_2 
       (.I0(app_wdf_data[28]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[28]),
        .O(wr_buf_in_data[28]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_3 
       (.I0(app_wdf_data[27]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[27]),
        .O(wr_buf_in_data[27]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_4 
       (.I0(app_wdf_data[26]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[26]),
        .O(wr_buf_in_data[26]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_5 
       (.I0(app_wdf_data[25]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[25]),
        .O(wr_buf_in_data[25]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_6 
       (.I0(app_wdf_data[24]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[24]),
        .O(wr_buf_in_data[24]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[305:304]),
        .DIB(wr_buf_in_data[303:302]),
        .DIC(wr_buf_in_data[301:300]),
        .DID({1'b0,1'b0}),
        .DOA(p_137_out),
        .DOB(p_136_out),
        .DOC(p_135_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_1 
       (.I0(app_wdf_data[305]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[305]),
        .O(wr_buf_in_data[305]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_2 
       (.I0(app_wdf_data[304]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[304]),
        .O(wr_buf_in_data[304]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_3 
       (.I0(app_wdf_data[303]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[303]),
        .O(wr_buf_in_data[303]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_4 
       (.I0(app_wdf_data[302]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[302]),
        .O(wr_buf_in_data[302]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_5 
       (.I0(app_wdf_data[301]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[301]),
        .O(wr_buf_in_data[301]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_6 
       (.I0(app_wdf_data[300]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[300]),
        .O(wr_buf_in_data[300]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[311:310]),
        .DIB(wr_buf_in_data[309:308]),
        .DIC(wr_buf_in_data[307:306]),
        .DID({1'b0,1'b0}),
        .DOA(p_134_out),
        .DOB(p_133_out),
        .DOC(p_132_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_1 
       (.I0(app_wdf_data[311]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[311]),
        .O(wr_buf_in_data[311]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_2 
       (.I0(app_wdf_data[310]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[310]),
        .O(wr_buf_in_data[310]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_3 
       (.I0(app_wdf_data[309]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[309]),
        .O(wr_buf_in_data[309]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_4 
       (.I0(app_wdf_data[308]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[308]),
        .O(wr_buf_in_data[308]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_5 
       (.I0(app_wdf_data[307]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[307]),
        .O(wr_buf_in_data[307]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_6 
       (.I0(app_wdf_data[306]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[306]),
        .O(wr_buf_in_data[306]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[317:316]),
        .DIB(wr_buf_in_data[315:314]),
        .DIC(wr_buf_in_data[313:312]),
        .DID({1'b0,1'b0}),
        .DOA(p_131_out),
        .DOB(p_130_out),
        .DOC(p_129_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_1 
       (.I0(app_wdf_data[317]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[317]),
        .O(wr_buf_in_data[317]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_2 
       (.I0(app_wdf_data[316]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[316]),
        .O(wr_buf_in_data[316]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_3 
       (.I0(app_wdf_data[315]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[315]),
        .O(wr_buf_in_data[315]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_4 
       (.I0(app_wdf_data[314]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[314]),
        .O(wr_buf_in_data[314]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_5 
       (.I0(app_wdf_data[313]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[313]),
        .O(wr_buf_in_data[313]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_6 
       (.I0(app_wdf_data[312]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[312]),
        .O(wr_buf_in_data[312]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[323:322]),
        .DIB(wr_buf_in_data[321:320]),
        .DIC(wr_buf_in_data[319:318]),
        .DID({1'b0,1'b0}),
        .DOA(p_128_out),
        .DOB(p_127_out),
        .DOC(p_126_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_1 
       (.I0(app_wdf_data[323]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[323]),
        .O(wr_buf_in_data[323]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_2 
       (.I0(app_wdf_data[322]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[322]),
        .O(wr_buf_in_data[322]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_3 
       (.I0(app_wdf_data[321]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[321]),
        .O(wr_buf_in_data[321]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_4 
       (.I0(app_wdf_data[320]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[320]),
        .O(wr_buf_in_data[320]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_5 
       (.I0(app_wdf_data[319]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[319]),
        .O(wr_buf_in_data[319]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_6 
       (.I0(app_wdf_data[318]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[318]),
        .O(wr_buf_in_data[318]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[329:328]),
        .DIB(wr_buf_in_data[327:326]),
        .DIC(wr_buf_in_data[325:324]),
        .DID({1'b0,1'b0}),
        .DOA(p_125_out),
        .DOB(p_124_out),
        .DOC(p_123_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_1 
       (.I0(app_wdf_data[329]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[329]),
        .O(wr_buf_in_data[329]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_2 
       (.I0(app_wdf_data[328]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[328]),
        .O(wr_buf_in_data[328]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_3 
       (.I0(app_wdf_data[327]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[327]),
        .O(wr_buf_in_data[327]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_4 
       (.I0(app_wdf_data[326]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[326]),
        .O(wr_buf_in_data[326]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_5 
       (.I0(app_wdf_data[325]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[325]),
        .O(wr_buf_in_data[325]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_6 
       (.I0(app_wdf_data[324]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[324]),
        .O(wr_buf_in_data[324]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[335:334]),
        .DIB(wr_buf_in_data[333:332]),
        .DIC(wr_buf_in_data[331:330]),
        .DID({1'b0,1'b0}),
        .DOA(p_122_out),
        .DOB(p_121_out),
        .DOC(p_120_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_1 
       (.I0(app_wdf_data[335]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[335]),
        .O(wr_buf_in_data[335]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_2 
       (.I0(app_wdf_data[334]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[334]),
        .O(wr_buf_in_data[334]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_3 
       (.I0(app_wdf_data[333]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[333]),
        .O(wr_buf_in_data[333]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_4 
       (.I0(app_wdf_data[332]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[332]),
        .O(wr_buf_in_data[332]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_5 
       (.I0(app_wdf_data[331]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[331]),
        .O(wr_buf_in_data[331]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_6 
       (.I0(app_wdf_data[330]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[330]),
        .O(wr_buf_in_data[330]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[341:340]),
        .DIB(wr_buf_in_data[339:338]),
        .DIC(wr_buf_in_data[337:336]),
        .DID({1'b0,1'b0}),
        .DOA(p_119_out),
        .DOB(p_118_out),
        .DOC(p_117_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_1 
       (.I0(app_wdf_data[341]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[341]),
        .O(wr_buf_in_data[341]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_2 
       (.I0(app_wdf_data[340]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[340]),
        .O(wr_buf_in_data[340]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_3 
       (.I0(app_wdf_data[339]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[339]),
        .O(wr_buf_in_data[339]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_4 
       (.I0(app_wdf_data[338]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[338]),
        .O(wr_buf_in_data[338]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_5 
       (.I0(app_wdf_data[337]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[337]),
        .O(wr_buf_in_data[337]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_6 
       (.I0(app_wdf_data[336]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[336]),
        .O(wr_buf_in_data[336]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[347:346]),
        .DIB(wr_buf_in_data[345:344]),
        .DIC(wr_buf_in_data[343:342]),
        .DID({1'b0,1'b0}),
        .DOA(p_116_out),
        .DOB(p_115_out),
        .DOC(p_114_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_1 
       (.I0(app_wdf_data[347]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[347]),
        .O(wr_buf_in_data[347]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_2 
       (.I0(app_wdf_data[346]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[346]),
        .O(wr_buf_in_data[346]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_3 
       (.I0(app_wdf_data[345]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[345]),
        .O(wr_buf_in_data[345]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_4 
       (.I0(app_wdf_data[344]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[344]),
        .O(wr_buf_in_data[344]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_5 
       (.I0(app_wdf_data[343]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[343]),
        .O(wr_buf_in_data[343]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_6 
       (.I0(app_wdf_data[342]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[342]),
        .O(wr_buf_in_data[342]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[353:352]),
        .DIB(wr_buf_in_data[351:350]),
        .DIC(wr_buf_in_data[349:348]),
        .DID({1'b0,1'b0}),
        .DOA(p_113_out),
        .DOB(p_112_out),
        .DOC(p_111_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_1 
       (.I0(app_wdf_data[353]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[353]),
        .O(wr_buf_in_data[353]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_2 
       (.I0(app_wdf_data[352]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[352]),
        .O(wr_buf_in_data[352]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_3 
       (.I0(app_wdf_data[351]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[351]),
        .O(wr_buf_in_data[351]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_4 
       (.I0(app_wdf_data[350]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[350]),
        .O(wr_buf_in_data[350]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_5 
       (.I0(app_wdf_data[349]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[349]),
        .O(wr_buf_in_data[349]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_6 
       (.I0(app_wdf_data[348]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[348]),
        .O(wr_buf_in_data[348]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[359:358]),
        .DIB(wr_buf_in_data[357:356]),
        .DIC(wr_buf_in_data[355:354]),
        .DID({1'b0,1'b0}),
        .DOA(p_110_out),
        .DOB(p_109_out),
        .DOC(p_108_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_1 
       (.I0(app_wdf_data[359]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[359]),
        .O(wr_buf_in_data[359]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_2 
       (.I0(app_wdf_data[358]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[358]),
        .O(wr_buf_in_data[358]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_3 
       (.I0(app_wdf_data[357]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[357]),
        .O(wr_buf_in_data[357]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_4 
       (.I0(app_wdf_data[356]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[356]),
        .O(wr_buf_in_data[356]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_5 
       (.I0(app_wdf_data[355]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[355]),
        .O(wr_buf_in_data[355]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_6 
       (.I0(app_wdf_data[354]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[354]),
        .O(wr_buf_in_data[354]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[35:34]),
        .DIB(wr_buf_in_data[33:32]),
        .DIC(wr_buf_in_data[31:30]),
        .DID({1'b0,1'b0}),
        .DOA(p_272_out),
        .DOB(p_271_out),
        .DOC(p_270_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_1 
       (.I0(app_wdf_data[35]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[35]),
        .O(wr_buf_in_data[35]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_2 
       (.I0(app_wdf_data[34]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[34]),
        .O(wr_buf_in_data[34]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_3 
       (.I0(app_wdf_data[33]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[33]),
        .O(wr_buf_in_data[33]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_4 
       (.I0(app_wdf_data[32]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[32]),
        .O(wr_buf_in_data[32]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_5 
       (.I0(app_wdf_data[31]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[31]),
        .O(wr_buf_in_data[31]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_6 
       (.I0(app_wdf_data[30]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[30]),
        .O(wr_buf_in_data[30]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[365:364]),
        .DIB(wr_buf_in_data[363:362]),
        .DIC(wr_buf_in_data[361:360]),
        .DID({1'b0,1'b0}),
        .DOA(p_107_out),
        .DOB(p_106_out),
        .DOC(p_105_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_1 
       (.I0(app_wdf_data[365]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[365]),
        .O(wr_buf_in_data[365]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_2 
       (.I0(app_wdf_data[364]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[364]),
        .O(wr_buf_in_data[364]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_3 
       (.I0(app_wdf_data[363]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[363]),
        .O(wr_buf_in_data[363]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_4 
       (.I0(app_wdf_data[362]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[362]),
        .O(wr_buf_in_data[362]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_5 
       (.I0(app_wdf_data[361]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[361]),
        .O(wr_buf_in_data[361]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_6 
       (.I0(app_wdf_data[360]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[360]),
        .O(wr_buf_in_data[360]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[371:370]),
        .DIB(wr_buf_in_data[369:368]),
        .DIC(wr_buf_in_data[367:366]),
        .DID({1'b0,1'b0}),
        .DOA(p_104_out),
        .DOB(p_103_out),
        .DOC(p_102_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_1 
       (.I0(app_wdf_data[371]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[371]),
        .O(wr_buf_in_data[371]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_2 
       (.I0(app_wdf_data[370]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[370]),
        .O(wr_buf_in_data[370]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_3 
       (.I0(app_wdf_data[369]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[369]),
        .O(wr_buf_in_data[369]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_4 
       (.I0(app_wdf_data[368]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[368]),
        .O(wr_buf_in_data[368]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_5 
       (.I0(app_wdf_data[367]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[367]),
        .O(wr_buf_in_data[367]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_6 
       (.I0(app_wdf_data[366]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[366]),
        .O(wr_buf_in_data[366]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[377:376]),
        .DIB(wr_buf_in_data[375:374]),
        .DIC(wr_buf_in_data[373:372]),
        .DID({1'b0,1'b0}),
        .DOA(p_101_out),
        .DOB(p_100_out),
        .DOC(p_99_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_1 
       (.I0(app_wdf_data[377]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[377]),
        .O(wr_buf_in_data[377]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_2 
       (.I0(app_wdf_data[376]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[376]),
        .O(wr_buf_in_data[376]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_3 
       (.I0(app_wdf_data[375]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[375]),
        .O(wr_buf_in_data[375]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_4 
       (.I0(app_wdf_data[374]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[374]),
        .O(wr_buf_in_data[374]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_5 
       (.I0(app_wdf_data[373]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[373]),
        .O(wr_buf_in_data[373]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_6 
       (.I0(app_wdf_data[372]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[372]),
        .O(wr_buf_in_data[372]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[383:382]),
        .DIB(wr_buf_in_data[381:380]),
        .DIC(wr_buf_in_data[379:378]),
        .DID({1'b0,1'b0}),
        .DOA(p_98_out),
        .DOB(p_97_out),
        .DOC(p_96_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_1 
       (.I0(app_wdf_data[383]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[383]),
        .O(wr_buf_in_data[383]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_2 
       (.I0(app_wdf_data[382]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[382]),
        .O(wr_buf_in_data[382]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_3 
       (.I0(app_wdf_data[381]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[381]),
        .O(wr_buf_in_data[381]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_4 
       (.I0(app_wdf_data[380]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[380]),
        .O(wr_buf_in_data[380]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_5 
       (.I0(app_wdf_data[379]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[379]),
        .O(wr_buf_in_data[379]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_6 
       (.I0(app_wdf_data[378]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[378]),
        .O(wr_buf_in_data[378]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[389:388]),
        .DIB(wr_buf_in_data[387:386]),
        .DIC(wr_buf_in_data[385:384]),
        .DID({1'b0,1'b0}),
        .DOA(p_95_out),
        .DOB(p_94_out),
        .DOC(p_93_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_1 
       (.I0(app_wdf_data[389]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[389]),
        .O(wr_buf_in_data[389]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_2 
       (.I0(app_wdf_data[388]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[388]),
        .O(wr_buf_in_data[388]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_3 
       (.I0(app_wdf_data[387]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[387]),
        .O(wr_buf_in_data[387]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_4 
       (.I0(app_wdf_data[386]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[386]),
        .O(wr_buf_in_data[386]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_5 
       (.I0(app_wdf_data[385]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[385]),
        .O(wr_buf_in_data[385]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_6 
       (.I0(app_wdf_data[384]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[384]),
        .O(wr_buf_in_data[384]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[395:394]),
        .DIB(wr_buf_in_data[393:392]),
        .DIC(wr_buf_in_data[391:390]),
        .DID({1'b0,1'b0}),
        .DOA(p_92_out),
        .DOB(p_91_out),
        .DOC(p_90_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_1 
       (.I0(app_wdf_data[395]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[395]),
        .O(wr_buf_in_data[395]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_2 
       (.I0(app_wdf_data[394]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[394]),
        .O(wr_buf_in_data[394]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_3 
       (.I0(app_wdf_data[393]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[393]),
        .O(wr_buf_in_data[393]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_4 
       (.I0(app_wdf_data[392]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[392]),
        .O(wr_buf_in_data[392]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_5 
       (.I0(app_wdf_data[391]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[391]),
        .O(wr_buf_in_data[391]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_6 
       (.I0(app_wdf_data[390]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[390]),
        .O(wr_buf_in_data[390]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[401:400]),
        .DIB(wr_buf_in_data[399:398]),
        .DIC(wr_buf_in_data[397:396]),
        .DID({1'b0,1'b0}),
        .DOA(p_89_out),
        .DOB(p_88_out),
        .DOC(p_87_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_1 
       (.I0(app_wdf_data[401]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[401]),
        .O(wr_buf_in_data[401]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_2 
       (.I0(app_wdf_data[400]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[400]),
        .O(wr_buf_in_data[400]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_3 
       (.I0(app_wdf_data[399]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[399]),
        .O(wr_buf_in_data[399]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_4 
       (.I0(app_wdf_data[398]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[398]),
        .O(wr_buf_in_data[398]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_5 
       (.I0(app_wdf_data[397]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[397]),
        .O(wr_buf_in_data[397]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_6 
       (.I0(app_wdf_data[396]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[396]),
        .O(wr_buf_in_data[396]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[407:406]),
        .DIB(wr_buf_in_data[405:404]),
        .DIC(wr_buf_in_data[403:402]),
        .DID({1'b0,1'b0}),
        .DOA(p_86_out),
        .DOB(p_85_out),
        .DOC(p_84_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_1 
       (.I0(app_wdf_data[407]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[407]),
        .O(wr_buf_in_data[407]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_2 
       (.I0(app_wdf_data[406]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[406]),
        .O(wr_buf_in_data[406]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_3 
       (.I0(app_wdf_data[405]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[405]),
        .O(wr_buf_in_data[405]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_4 
       (.I0(app_wdf_data[404]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[404]),
        .O(wr_buf_in_data[404]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_5 
       (.I0(app_wdf_data[403]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[403]),
        .O(wr_buf_in_data[403]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_6 
       (.I0(app_wdf_data[402]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[402]),
        .O(wr_buf_in_data[402]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[413:412]),
        .DIB(wr_buf_in_data[411:410]),
        .DIC(wr_buf_in_data[409:408]),
        .DID({1'b0,1'b0}),
        .DOA(p_83_out),
        .DOB(p_82_out),
        .DOC(p_81_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_1 
       (.I0(app_wdf_data[413]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[413]),
        .O(wr_buf_in_data[413]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_2 
       (.I0(app_wdf_data[412]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[412]),
        .O(wr_buf_in_data[412]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_3 
       (.I0(app_wdf_data[411]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[411]),
        .O(wr_buf_in_data[411]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_4 
       (.I0(app_wdf_data[410]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[410]),
        .O(wr_buf_in_data[410]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_5 
       (.I0(app_wdf_data[409]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[409]),
        .O(wr_buf_in_data[409]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_6 
       (.I0(app_wdf_data[408]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[408]),
        .O(wr_buf_in_data[408]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[419:418]),
        .DIB(wr_buf_in_data[417:416]),
        .DIC(wr_buf_in_data[415:414]),
        .DID({1'b0,1'b0}),
        .DOA(p_80_out),
        .DOB(p_79_out),
        .DOC(p_78_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_1 
       (.I0(app_wdf_data[419]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[419]),
        .O(wr_buf_in_data[419]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_2 
       (.I0(app_wdf_data[418]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[418]),
        .O(wr_buf_in_data[418]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_3 
       (.I0(app_wdf_data[417]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[417]),
        .O(wr_buf_in_data[417]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_4 
       (.I0(app_wdf_data[416]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[416]),
        .O(wr_buf_in_data[416]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_5 
       (.I0(app_wdf_data[415]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[415]),
        .O(wr_buf_in_data[415]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_6 
       (.I0(app_wdf_data[414]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[414]),
        .O(wr_buf_in_data[414]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[41:40]),
        .DIB(wr_buf_in_data[39:38]),
        .DIC(wr_buf_in_data[37:36]),
        .DID({1'b0,1'b0}),
        .DOA(p_269_out),
        .DOB(p_268_out),
        .DOC(p_267_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_1 
       (.I0(app_wdf_data[41]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[41]),
        .O(wr_buf_in_data[41]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_2 
       (.I0(app_wdf_data[40]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[40]),
        .O(wr_buf_in_data[40]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_3 
       (.I0(app_wdf_data[39]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[39]),
        .O(wr_buf_in_data[39]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_4 
       (.I0(app_wdf_data[38]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[38]),
        .O(wr_buf_in_data[38]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_5 
       (.I0(app_wdf_data[37]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[37]),
        .O(wr_buf_in_data[37]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_6 
       (.I0(app_wdf_data[36]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[36]),
        .O(wr_buf_in_data[36]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[425:424]),
        .DIB(wr_buf_in_data[423:422]),
        .DIC(wr_buf_in_data[421:420]),
        .DID({1'b0,1'b0}),
        .DOA(p_77_out),
        .DOB(p_76_out),
        .DOC(p_75_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_1 
       (.I0(app_wdf_data[425]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[425]),
        .O(wr_buf_in_data[425]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_2 
       (.I0(app_wdf_data[424]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[424]),
        .O(wr_buf_in_data[424]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_3 
       (.I0(app_wdf_data[423]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[423]),
        .O(wr_buf_in_data[423]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_4 
       (.I0(app_wdf_data[422]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[422]),
        .O(wr_buf_in_data[422]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_5 
       (.I0(app_wdf_data[421]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[421]),
        .O(wr_buf_in_data[421]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_6 
       (.I0(app_wdf_data[420]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[420]),
        .O(wr_buf_in_data[420]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[431:430]),
        .DIB(wr_buf_in_data[429:428]),
        .DIC(wr_buf_in_data[427:426]),
        .DID({1'b0,1'b0}),
        .DOA(p_74_out),
        .DOB(p_73_out),
        .DOC(p_72_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_1 
       (.I0(app_wdf_data[431]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[431]),
        .O(wr_buf_in_data[431]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_2 
       (.I0(app_wdf_data[430]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[430]),
        .O(wr_buf_in_data[430]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_3 
       (.I0(app_wdf_data[429]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[429]),
        .O(wr_buf_in_data[429]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_4 
       (.I0(app_wdf_data[428]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[428]),
        .O(wr_buf_in_data[428]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_5 
       (.I0(app_wdf_data[427]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[427]),
        .O(wr_buf_in_data[427]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_6 
       (.I0(app_wdf_data[426]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[426]),
        .O(wr_buf_in_data[426]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[437:436]),
        .DIB(wr_buf_in_data[435:434]),
        .DIC(wr_buf_in_data[433:432]),
        .DID({1'b0,1'b0}),
        .DOA(p_71_out),
        .DOB(p_70_out),
        .DOC(p_69_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_1 
       (.I0(app_wdf_data[437]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[437]),
        .O(wr_buf_in_data[437]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_2 
       (.I0(app_wdf_data[436]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[436]),
        .O(wr_buf_in_data[436]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_3 
       (.I0(app_wdf_data[435]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[435]),
        .O(wr_buf_in_data[435]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_4 
       (.I0(app_wdf_data[434]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[434]),
        .O(wr_buf_in_data[434]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_5 
       (.I0(app_wdf_data[433]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[433]),
        .O(wr_buf_in_data[433]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_6 
       (.I0(app_wdf_data[432]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[432]),
        .O(wr_buf_in_data[432]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[443:442]),
        .DIB(wr_buf_in_data[441:440]),
        .DIC(wr_buf_in_data[439:438]),
        .DID({1'b0,1'b0}),
        .DOA(p_68_out),
        .DOB(p_67_out),
        .DOC(p_66_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_1 
       (.I0(app_wdf_data[443]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[443]),
        .O(wr_buf_in_data[443]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_2 
       (.I0(app_wdf_data[442]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[442]),
        .O(wr_buf_in_data[442]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_3 
       (.I0(app_wdf_data[441]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[441]),
        .O(wr_buf_in_data[441]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_4 
       (.I0(app_wdf_data[440]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[440]),
        .O(wr_buf_in_data[440]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_5 
       (.I0(app_wdf_data[439]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[439]),
        .O(wr_buf_in_data[439]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_6 
       (.I0(app_wdf_data[438]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[438]),
        .O(wr_buf_in_data[438]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[449:448]),
        .DIB(wr_buf_in_data[447:446]),
        .DIC(wr_buf_in_data[445:444]),
        .DID({1'b0,1'b0}),
        .DOA(p_65_out),
        .DOB(p_64_out),
        .DOC(p_63_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_1 
       (.I0(app_wdf_data[449]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[449]),
        .O(wr_buf_in_data[449]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_2 
       (.I0(app_wdf_data[448]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[448]),
        .O(wr_buf_in_data[448]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_3 
       (.I0(app_wdf_data[447]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[447]),
        .O(wr_buf_in_data[447]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_4 
       (.I0(app_wdf_data[446]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[446]),
        .O(wr_buf_in_data[446]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_5 
       (.I0(app_wdf_data[445]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[445]),
        .O(wr_buf_in_data[445]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_6 
       (.I0(app_wdf_data[444]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[444]),
        .O(wr_buf_in_data[444]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[455:454]),
        .DIB(wr_buf_in_data[453:452]),
        .DIC(wr_buf_in_data[451:450]),
        .DID({1'b0,1'b0}),
        .DOA(p_62_out),
        .DOB(p_61_out),
        .DOC(p_60_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_1 
       (.I0(app_wdf_data[455]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[455]),
        .O(wr_buf_in_data[455]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_2 
       (.I0(app_wdf_data[454]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[454]),
        .O(wr_buf_in_data[454]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_3 
       (.I0(app_wdf_data[453]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[453]),
        .O(wr_buf_in_data[453]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_4 
       (.I0(app_wdf_data[452]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[452]),
        .O(wr_buf_in_data[452]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_5 
       (.I0(app_wdf_data[451]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[451]),
        .O(wr_buf_in_data[451]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_6 
       (.I0(app_wdf_data[450]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[450]),
        .O(wr_buf_in_data[450]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[461:460]),
        .DIB(wr_buf_in_data[459:458]),
        .DIC(wr_buf_in_data[457:456]),
        .DID({1'b0,1'b0}),
        .DOA(p_59_out),
        .DOB(p_58_out),
        .DOC(p_57_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_1 
       (.I0(app_wdf_data[461]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[461]),
        .O(wr_buf_in_data[461]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_2 
       (.I0(app_wdf_data[460]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[460]),
        .O(wr_buf_in_data[460]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_3 
       (.I0(app_wdf_data[459]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[459]),
        .O(wr_buf_in_data[459]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_4 
       (.I0(app_wdf_data[458]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[458]),
        .O(wr_buf_in_data[458]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_5 
       (.I0(app_wdf_data[457]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[457]),
        .O(wr_buf_in_data[457]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_6 
       (.I0(app_wdf_data[456]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[456]),
        .O(wr_buf_in_data[456]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[467:466]),
        .DIB(wr_buf_in_data[465:464]),
        .DIC(wr_buf_in_data[463:462]),
        .DID({1'b0,1'b0}),
        .DOA(p_56_out),
        .DOB(p_55_out),
        .DOC(p_54_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_1 
       (.I0(app_wdf_data[467]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[467]),
        .O(wr_buf_in_data[467]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_2 
       (.I0(app_wdf_data[466]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[466]),
        .O(wr_buf_in_data[466]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_3 
       (.I0(app_wdf_data[465]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[465]),
        .O(wr_buf_in_data[465]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_4 
       (.I0(app_wdf_data[464]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[464]),
        .O(wr_buf_in_data[464]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_5 
       (.I0(app_wdf_data[463]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[463]),
        .O(wr_buf_in_data[463]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_6 
       (.I0(app_wdf_data[462]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[462]),
        .O(wr_buf_in_data[462]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[473:472]),
        .DIB(wr_buf_in_data[471:470]),
        .DIC(wr_buf_in_data[469:468]),
        .DID({1'b0,1'b0}),
        .DOA(p_53_out),
        .DOB(p_52_out),
        .DOC(p_51_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_1 
       (.I0(app_wdf_data[473]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[473]),
        .O(wr_buf_in_data[473]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_2 
       (.I0(app_wdf_data[472]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[472]),
        .O(wr_buf_in_data[472]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_3 
       (.I0(app_wdf_data[471]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[471]),
        .O(wr_buf_in_data[471]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_4 
       (.I0(app_wdf_data[470]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[470]),
        .O(wr_buf_in_data[470]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_5 
       (.I0(app_wdf_data[469]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[469]),
        .O(wr_buf_in_data[469]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_6 
       (.I0(app_wdf_data[468]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[468]),
        .O(wr_buf_in_data[468]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[479:478]),
        .DIB(wr_buf_in_data[477:476]),
        .DIC(wr_buf_in_data[475:474]),
        .DID({1'b0,1'b0}),
        .DOA(p_50_out),
        .DOB(p_49_out),
        .DOC(p_48_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_1 
       (.I0(app_wdf_data[479]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[479]),
        .O(wr_buf_in_data[479]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_2 
       (.I0(app_wdf_data[478]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[478]),
        .O(wr_buf_in_data[478]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_3 
       (.I0(app_wdf_data[477]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[477]),
        .O(wr_buf_in_data[477]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_4 
       (.I0(app_wdf_data[476]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[476]),
        .O(wr_buf_in_data[476]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_5 
       (.I0(app_wdf_data[475]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[475]),
        .O(wr_buf_in_data[475]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_6 
       (.I0(app_wdf_data[474]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[474]),
        .O(wr_buf_in_data[474]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[47:46]),
        .DIB(wr_buf_in_data[45:44]),
        .DIC(wr_buf_in_data[43:42]),
        .DID({1'b0,1'b0}),
        .DOA(p_266_out),
        .DOB(p_265_out),
        .DOC(p_264_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_1 
       (.I0(app_wdf_data[47]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[47]),
        .O(wr_buf_in_data[47]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_2 
       (.I0(app_wdf_data[46]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[46]),
        .O(wr_buf_in_data[46]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_3 
       (.I0(app_wdf_data[45]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[45]),
        .O(wr_buf_in_data[45]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_4 
       (.I0(app_wdf_data[44]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[44]),
        .O(wr_buf_in_data[44]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_5 
       (.I0(app_wdf_data[43]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[43]),
        .O(wr_buf_in_data[43]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_6 
       (.I0(app_wdf_data[42]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[42]),
        .O(wr_buf_in_data[42]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[485:484]),
        .DIB(wr_buf_in_data[483:482]),
        .DIC(wr_buf_in_data[481:480]),
        .DID({1'b0,1'b0}),
        .DOA(p_47_out),
        .DOB(p_46_out),
        .DOC(p_45_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_1 
       (.I0(app_wdf_data[485]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[485]),
        .O(wr_buf_in_data[485]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_2 
       (.I0(app_wdf_data[484]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[484]),
        .O(wr_buf_in_data[484]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_3 
       (.I0(app_wdf_data[483]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[483]),
        .O(wr_buf_in_data[483]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_4 
       (.I0(app_wdf_data[482]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[482]),
        .O(wr_buf_in_data[482]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_5 
       (.I0(app_wdf_data[481]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[481]),
        .O(wr_buf_in_data[481]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_6 
       (.I0(app_wdf_data[480]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[480]),
        .O(wr_buf_in_data[480]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[491:490]),
        .DIB(wr_buf_in_data[489:488]),
        .DIC(wr_buf_in_data[487:486]),
        .DID({1'b0,1'b0}),
        .DOA(p_44_out),
        .DOB(p_43_out),
        .DOC(p_42_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_1 
       (.I0(app_wdf_data[491]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[491]),
        .O(wr_buf_in_data[491]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_2 
       (.I0(app_wdf_data[490]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[490]),
        .O(wr_buf_in_data[490]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_3 
       (.I0(app_wdf_data[489]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[489]),
        .O(wr_buf_in_data[489]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_4 
       (.I0(app_wdf_data[488]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[488]),
        .O(wr_buf_in_data[488]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_5 
       (.I0(app_wdf_data[487]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[487]),
        .O(wr_buf_in_data[487]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_6 
       (.I0(app_wdf_data[486]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[486]),
        .O(wr_buf_in_data[486]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[497:496]),
        .DIB(wr_buf_in_data[495:494]),
        .DIC(wr_buf_in_data[493:492]),
        .DID({1'b0,1'b0}),
        .DOA(p_41_out),
        .DOB(p_40_out),
        .DOC(p_39_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_1 
       (.I0(app_wdf_data[497]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[497]),
        .O(wr_buf_in_data[497]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_2 
       (.I0(app_wdf_data[496]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[496]),
        .O(wr_buf_in_data[496]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_3 
       (.I0(app_wdf_data[495]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[495]),
        .O(wr_buf_in_data[495]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_4 
       (.I0(app_wdf_data[494]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[494]),
        .O(wr_buf_in_data[494]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_5 
       (.I0(app_wdf_data[493]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[493]),
        .O(wr_buf_in_data[493]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_6 
       (.I0(app_wdf_data[492]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[492]),
        .O(wr_buf_in_data[492]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[503:502]),
        .DIB(wr_buf_in_data[501:500]),
        .DIC(wr_buf_in_data[499:498]),
        .DID({1'b0,1'b0}),
        .DOA(p_38_out),
        .DOB(p_37_out),
        .DOC(p_36_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_1 
       (.I0(app_wdf_data[503]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[503]),
        .O(wr_buf_in_data[503]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_2 
       (.I0(app_wdf_data[502]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[502]),
        .O(wr_buf_in_data[502]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_3 
       (.I0(app_wdf_data[501]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[501]),
        .O(wr_buf_in_data[501]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_4 
       (.I0(app_wdf_data[500]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[500]),
        .O(wr_buf_in_data[500]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_5 
       (.I0(app_wdf_data[499]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[499]),
        .O(wr_buf_in_data[499]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_6 
       (.I0(app_wdf_data[498]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[498]),
        .O(wr_buf_in_data[498]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[509:508]),
        .DIB(wr_buf_in_data[507:506]),
        .DIC(wr_buf_in_data[505:504]),
        .DID({1'b0,1'b0}),
        .DOA(p_35_out),
        .DOB(p_34_out),
        .DOC(p_33_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_1 
       (.I0(app_wdf_data[509]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[509]),
        .O(wr_buf_in_data[509]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_2 
       (.I0(app_wdf_data[508]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[508]),
        .O(wr_buf_in_data[508]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_3 
       (.I0(app_wdf_data[507]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[507]),
        .O(wr_buf_in_data[507]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_4 
       (.I0(app_wdf_data[506]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[506]),
        .O(wr_buf_in_data[506]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_5 
       (.I0(app_wdf_data[505]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[505]),
        .O(wr_buf_in_data[505]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_6 
       (.I0(app_wdf_data[504]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[504]),
        .O(wr_buf_in_data[504]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[515:514]),
        .DIB(wr_buf_in_data[513:512]),
        .DIC(wr_buf_in_data[511:510]),
        .DID({1'b0,1'b0}),
        .DOA(p_32_out),
        .DOB(p_31_out),
        .DOC(p_30_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_1 
       (.I0(app_wdf_mask[3]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[3]),
        .O(wr_buf_in_data[515]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_2 
       (.I0(app_wdf_mask[2]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[2]),
        .O(wr_buf_in_data[514]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_3 
       (.I0(app_wdf_mask[1]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[1]),
        .O(wr_buf_in_data[513]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_4 
       (.I0(app_wdf_mask[0]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[0]),
        .O(wr_buf_in_data[512]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_5 
       (.I0(app_wdf_data[511]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[511]),
        .O(wr_buf_in_data[511]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_6 
       (.I0(app_wdf_data[510]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[510]),
        .O(wr_buf_in_data[510]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[521:520]),
        .DIB(wr_buf_in_data[519:518]),
        .DIC(wr_buf_in_data[517:516]),
        .DID({1'b0,1'b0}),
        .DOA(p_29_out),
        .DOB(p_28_out),
        .DOC(p_27_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_1 
       (.I0(app_wdf_mask[9]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[9]),
        .O(wr_buf_in_data[521]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_2 
       (.I0(app_wdf_mask[8]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[8]),
        .O(wr_buf_in_data[520]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_3 
       (.I0(app_wdf_mask[7]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[7]),
        .O(wr_buf_in_data[519]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_4 
       (.I0(app_wdf_mask[6]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[6]),
        .O(wr_buf_in_data[518]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_5 
       (.I0(app_wdf_mask[5]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[5]),
        .O(wr_buf_in_data[517]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_6 
       (.I0(app_wdf_mask[4]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[4]),
        .O(wr_buf_in_data[516]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[527:526]),
        .DIB(wr_buf_in_data[525:524]),
        .DIC(wr_buf_in_data[523:522]),
        .DID({1'b0,1'b0}),
        .DOA(p_26_out),
        .DOB(p_25_out),
        .DOC(p_24_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_1 
       (.I0(app_wdf_mask[15]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[15]),
        .O(wr_buf_in_data[527]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_2 
       (.I0(app_wdf_mask[14]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[14]),
        .O(wr_buf_in_data[526]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_3 
       (.I0(app_wdf_mask[13]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[13]),
        .O(wr_buf_in_data[525]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_4 
       (.I0(app_wdf_mask[12]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[12]),
        .O(wr_buf_in_data[524]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_5 
       (.I0(app_wdf_mask[11]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[11]),
        .O(wr_buf_in_data[523]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_6 
       (.I0(app_wdf_mask[10]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[10]),
        .O(wr_buf_in_data[522]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[533:532]),
        .DIB(wr_buf_in_data[531:530]),
        .DIC(wr_buf_in_data[529:528]),
        .DID({1'b0,1'b0}),
        .DOA(p_23_out),
        .DOB(p_22_out),
        .DOC(p_21_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_1 
       (.I0(app_wdf_mask[21]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[21]),
        .O(wr_buf_in_data[533]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_2 
       (.I0(app_wdf_mask[20]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[20]),
        .O(wr_buf_in_data[532]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_3 
       (.I0(app_wdf_mask[19]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[19]),
        .O(wr_buf_in_data[531]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_4 
       (.I0(app_wdf_mask[18]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[18]),
        .O(wr_buf_in_data[530]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_5 
       (.I0(app_wdf_mask[17]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[17]),
        .O(wr_buf_in_data[529]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_6 
       (.I0(app_wdf_mask[16]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[16]),
        .O(wr_buf_in_data[528]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[539:538]),
        .DIB(wr_buf_in_data[537:536]),
        .DIC(wr_buf_in_data[535:534]),
        .DID({1'b0,1'b0}),
        .DOA(p_20_out),
        .DOB(p_19_out),
        .DOC(p_18_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_1 
       (.I0(app_wdf_mask[27]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[27]),
        .O(wr_buf_in_data[539]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_2 
       (.I0(app_wdf_mask[26]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[26]),
        .O(wr_buf_in_data[538]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_3 
       (.I0(app_wdf_mask[25]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[25]),
        .O(wr_buf_in_data[537]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_4 
       (.I0(app_wdf_mask[24]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[24]),
        .O(wr_buf_in_data[536]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_5 
       (.I0(app_wdf_mask[23]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[23]),
        .O(wr_buf_in_data[535]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_6 
       (.I0(app_wdf_mask[22]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[22]),
        .O(wr_buf_in_data[534]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[53:52]),
        .DIB(wr_buf_in_data[51:50]),
        .DIC(wr_buf_in_data[49:48]),
        .DID({1'b0,1'b0}),
        .DOA(p_263_out),
        .DOB(p_262_out),
        .DOC(p_261_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_1 
       (.I0(app_wdf_data[53]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[53]),
        .O(wr_buf_in_data[53]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_2 
       (.I0(app_wdf_data[52]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[52]),
        .O(wr_buf_in_data[52]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_3 
       (.I0(app_wdf_data[51]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[51]),
        .O(wr_buf_in_data[51]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_4 
       (.I0(app_wdf_data[50]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[50]),
        .O(wr_buf_in_data[50]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_5 
       (.I0(app_wdf_data[49]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[49]),
        .O(wr_buf_in_data[49]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_6 
       (.I0(app_wdf_data[48]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[48]),
        .O(wr_buf_in_data[48]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[545:544]),
        .DIB(wr_buf_in_data[543:542]),
        .DIC(wr_buf_in_data[541:540]),
        .DID({1'b0,1'b0}),
        .DOA(p_17_out),
        .DOB(p_16_out),
        .DOC(p_15_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_1 
       (.I0(app_wdf_mask[33]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[33]),
        .O(wr_buf_in_data[545]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_2 
       (.I0(app_wdf_mask[32]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[32]),
        .O(wr_buf_in_data[544]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_3 
       (.I0(app_wdf_mask[31]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[31]),
        .O(wr_buf_in_data[543]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_4 
       (.I0(app_wdf_mask[30]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[30]),
        .O(wr_buf_in_data[542]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_5 
       (.I0(app_wdf_mask[29]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[29]),
        .O(wr_buf_in_data[541]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_6 
       (.I0(app_wdf_mask[28]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[28]),
        .O(wr_buf_in_data[540]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[551:550]),
        .DIB(wr_buf_in_data[549:548]),
        .DIC(wr_buf_in_data[547:546]),
        .DID({1'b0,1'b0}),
        .DOA(p_14_out),
        .DOB(p_13_out),
        .DOC(p_12_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_1 
       (.I0(app_wdf_mask[39]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[39]),
        .O(wr_buf_in_data[551]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_2 
       (.I0(app_wdf_mask[38]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[38]),
        .O(wr_buf_in_data[550]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_3 
       (.I0(app_wdf_mask[37]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[37]),
        .O(wr_buf_in_data[549]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_4 
       (.I0(app_wdf_mask[36]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[36]),
        .O(wr_buf_in_data[548]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_5 
       (.I0(app_wdf_mask[35]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[35]),
        .O(wr_buf_in_data[547]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_6 
       (.I0(app_wdf_mask[34]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[34]),
        .O(wr_buf_in_data[546]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[557:556]),
        .DIB(wr_buf_in_data[555:554]),
        .DIC(wr_buf_in_data[553:552]),
        .DID({1'b0,1'b0}),
        .DOA(p_11_out),
        .DOB(p_10_out),
        .DOC(p_9_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_1 
       (.I0(app_wdf_mask[45]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[45]),
        .O(wr_buf_in_data[557]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_2 
       (.I0(app_wdf_mask[44]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[44]),
        .O(wr_buf_in_data[556]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_3 
       (.I0(app_wdf_mask[43]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[43]),
        .O(wr_buf_in_data[555]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_4 
       (.I0(app_wdf_mask[42]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[42]),
        .O(wr_buf_in_data[554]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_5 
       (.I0(app_wdf_mask[41]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[41]),
        .O(wr_buf_in_data[553]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_6 
       (.I0(app_wdf_mask[40]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[40]),
        .O(wr_buf_in_data[552]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[563:562]),
        .DIB(wr_buf_in_data[561:560]),
        .DIC(wr_buf_in_data[559:558]),
        .DID({1'b0,1'b0}),
        .DOA(p_8_out),
        .DOB(p_7_out),
        .DOC(p_6_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_1 
       (.I0(app_wdf_mask[51]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[51]),
        .O(wr_buf_in_data[563]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_2 
       (.I0(app_wdf_mask[50]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[50]),
        .O(wr_buf_in_data[562]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_3 
       (.I0(app_wdf_mask[49]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[49]),
        .O(wr_buf_in_data[561]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_4 
       (.I0(app_wdf_mask[48]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[48]),
        .O(wr_buf_in_data[560]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_5 
       (.I0(app_wdf_mask[47]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[47]),
        .O(wr_buf_in_data[559]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_6 
       (.I0(app_wdf_mask[46]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[46]),
        .O(wr_buf_in_data[558]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[569:568]),
        .DIB(wr_buf_in_data[567:566]),
        .DIC(wr_buf_in_data[565:564]),
        .DID({1'b0,1'b0}),
        .DOA(p_5_out),
        .DOB(p_4_out),
        .DOC({\write_buffer.wr_buffer_ram[94].RAM32M0_n_4 ,\write_buffer.wr_buffer_ram[94].RAM32M0_n_5 }),
        .DOD(\NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_1 
       (.I0(app_wdf_mask[57]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[57]),
        .O(wr_buf_in_data[569]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_2 
       (.I0(app_wdf_mask[56]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[56]),
        .O(wr_buf_in_data[568]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_3 
       (.I0(app_wdf_mask[55]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[55]),
        .O(wr_buf_in_data[567]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_4 
       (.I0(app_wdf_mask[54]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[54]),
        .O(wr_buf_in_data[566]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_5 
       (.I0(app_wdf_mask[53]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[53]),
        .O(wr_buf_in_data[565]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_6 
       (.I0(app_wdf_mask[52]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[52]),
        .O(wr_buf_in_data[564]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[575:574]),
        .DIB(wr_buf_in_data[573:572]),
        .DIC(wr_buf_in_data[571:570]),
        .DID({1'b0,1'b0}),
        .DOA({\write_buffer.wr_buffer_ram[95].RAM32M0_n_0 ,\write_buffer.wr_buffer_ram[95].RAM32M0_n_1 }),
        .DOB({\write_buffer.wr_buffer_ram[95].RAM32M0_n_2 ,\write_buffer.wr_buffer_ram[95].RAM32M0_n_3 }),
        .DOC({\write_buffer.wr_buffer_ram[95].RAM32M0_n_4 ,\write_buffer.wr_buffer_ram[95].RAM32M0_n_5 }),
        .DOD(\NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_1 
       (.I0(app_wdf_mask[63]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[63]),
        .O(wr_buf_in_data[575]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_2 
       (.I0(app_wdf_mask[62]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[62]),
        .O(wr_buf_in_data[574]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_3 
       (.I0(app_wdf_mask[61]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[61]),
        .O(wr_buf_in_data[573]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_4 
       (.I0(app_wdf_mask[60]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[60]),
        .O(wr_buf_in_data[572]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_5 
       (.I0(app_wdf_mask[59]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[59]),
        .O(wr_buf_in_data[571]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_6 
       (.I0(app_wdf_mask[58]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_mask_r1[58]),
        .O(wr_buf_in_data[570]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0 
       (.ADDRA({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRB({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRC({\cmd_pipe_plus.wr_data_addr_reg[3]_rep__0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0 }),
        .DIA(wr_buf_in_data[59:58]),
        .DIB(wr_buf_in_data[57:56]),
        .DIC(wr_buf_in_data[55:54]),
        .DID({1'b0,1'b0}),
        .DOA(p_260_out),
        .DOB(p_259_out),
        .DOC(p_258_out),
        .DOD(\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_1 
       (.I0(app_wdf_data[59]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[59]),
        .O(wr_buf_in_data[59]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_2 
       (.I0(app_wdf_data[58]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[58]),
        .O(wr_buf_in_data[58]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_3 
       (.I0(app_wdf_data[57]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[57]),
        .O(wr_buf_in_data[57]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_4 
       (.I0(app_wdf_data[56]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[56]),
        .O(wr_buf_in_data[56]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_5 
       (.I0(app_wdf_data[55]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[55]),
        .O(wr_buf_in_data[55]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_6 
       (.I0(app_wdf_data[54]),
        .I1(app_wdf_rdy),
        .I2(app_wdf_data_r1[54]),
        .O(wr_buf_in_data[54]));
  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT4 #(
    .INIT(16'h2E22)) 
    \write_data_control.wb_wr_data_addr0_r_i_1 
       (.I0(wb_wr_data_addr0_r),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy),
        .O(\write_data_control.wb_wr_data_addr0_r_i_1_n_0 ));
  FDRE \write_data_control.wb_wr_data_addr0_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_data_control.wb_wr_data_addr0_r_i_1_n_0 ),
        .Q(wb_wr_data_addr0_r),
        .R(reset_reg));
  LUT5 #(
    .INIT(32'h40FF4000)) 
    \write_data_control.wb_wr_data_addr_r[4]_i_1 
       (.I0(\write_data_control.wb_wr_data_addr_r[4]_i_2_n_0 ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy),
        .I4(p_0_in_0),
        .O(wr_data_addr_le));
  LUT5 #(
    .INIT(32'hFFFF0EFF)) 
    \write_data_control.wb_wr_data_addr_r[4]_i_2 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .I1(\occupied_counter.occ_cnt[15]_i_2_n_0 ),
        .I2(p_0_in_0),
        .I3(ram_init_done_r),
        .I4(reset_reg),
        .O(\write_data_control.wb_wr_data_addr_r[4]_i_2_n_0 ));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[1] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(wr_data_pntr[0]),
        .Q(wb_wr_data_addr_r[1]),
        .R(reset_reg));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[2] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(wr_data_pntr[1]),
        .Q(wb_wr_data_addr_r[2]),
        .R(reset_reg));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[3] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(wr_data_pntr[2]),
        .Q(wb_wr_data_addr_r[3]),
        .R(reset_reg));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[4] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(wr_data_pntr[3]),
        .Q(wb_wr_data_addr_r[4]),
        .R(reset_reg));
  LUT1 #(
    .INIT(2'h1)) 
    \write_data_control.wr_data_indx_r[0]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg__0 [0]),
        .O(p_0_in__0[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \write_data_control.wr_data_indx_r[1]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg__0 [1]),
        .I1(\write_data_control.wr_data_indx_r_reg__0 [0]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \write_data_control.wr_data_indx_r[2]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg__0 [2]),
        .I1(\write_data_control.wr_data_indx_r_reg__0 [0]),
        .I2(\write_data_control.wr_data_indx_r_reg__0 [1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \write_data_control.wr_data_indx_r[3]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg__0 [3]),
        .I1(\write_data_control.wr_data_indx_r_reg__0 [1]),
        .I2(\write_data_control.wr_data_indx_r_reg__0 [0]),
        .I3(\write_data_control.wr_data_indx_r_reg__0 [2]),
        .O(p_0_in__0[3]));
  FDSE \write_data_control.wr_data_indx_r_reg[0] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(p_0_in__0[0]),
        .Q(\write_data_control.wr_data_indx_r_reg__0 [0]),
        .S(reset_reg));
  FDRE \write_data_control.wr_data_indx_r_reg[1] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(p_0_in__0[1]),
        .Q(\write_data_control.wr_data_indx_r_reg__0 [1]),
        .R(reset_reg));
  FDRE \write_data_control.wr_data_indx_r_reg[2] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(p_0_in__0[2]),
        .Q(\write_data_control.wr_data_indx_r_reg__0 [2]),
        .R(reset_reg));
  FDRE \write_data_control.wr_data_indx_r_reg[3] 
       (.C(CLK),
        .CE(wr_data_addr_le),
        .D(p_0_in__0[3]),
        .Q(\write_data_control.wr_data_indx_r_reg__0 [3]),
        .R(reset_reg));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
