2015.2:
 * Version 2.3 (Rev. 2)
 * Added Address Mirroring support for DDR3 Dual Rank UDIMMs.
 * Resolved DDR3 AXI, ECC enabled design failures. See (Xilinx Answer 64421) for details.

2015.1:
 * Version 2.3 (Rev. 1)
 * Enhanced RLDRAM II and RLDRAM 3 controller efficiency.
 * Resolved DDR2/DDR3 issue where additional BUFG added in "opt_design" for the "freq_refclk" can lead to minimum pulse width timing violations. See (Xilinx Answer 63165) for details.
 * Resolved issue with Virtex-7 HT where error is generated when trying to open the MIG 7 Series tool when targeting a part with an flg package - Failed to generate custom UI outputs.  See (Xilinx Answer 60527) for details.
 * Resolved issues with DDR3/DDR2 where Manual Window Check feature does not work with VIO 2.0.  See (Xilinx Answer 59284) for details.
 * Resolved issue with the "No Buffer" option always expecting a 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz. See (Xilinx Answer 63227) for details.
 * Resolved issue with CRITICAL WARNING message when multiple MIG IP are added to the same project.  See (Xilinx Answer 58621) for details.

2014.4.1:
 * Version 2.3
 * No changes

2014.4:
 * Version 2.3
 * Updated maximum frequencies and controller rates as per specifications listed in 7 Series and Zync DC and Switching Characteristics Datasheets
 * DDR3 write calibration changes

2014.3:
 * Version 2.2
 * DDR3 SDRAM, DDR2 SDRAM, RLDRAM II, LPDDR2 SDRAM, QDRIIPLUS SRAM max supported frequencies updated. See (Xilinx Answer 61853) for details."
 * Resolved (Xilinx Answer 61744) "MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2.  Errors were not seen in previous versions."
 * Resolved (Xilinx Answer 61521) "MIG 7 Series - Cannot generate data width greater than 8-bits for CPG325 packages"
 * Resolved (Xilinx Answer 60480) "MIG 7 Series - Receiving ERROR [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used"
 * Resolved (Xilinx Answer 60051) "MIG 7 Series DDR3 - VCS simulations fail with unresolved modules"

2014.2:
 * Version 2.1
 * DDR3 clocking and read path calibration updates. Refer to Answer Record 60470 for details
 * Addition of Artix-7Q(xq7a50t-cs325,xq7a50t-fg484) and XAZynq (xa7z030-fbg484) devices

2014.1:
 * Version 2.0 (Rev. 3)
 * Extended IES and VCS support to Multi-Controller and Multi-Interface designs

2013.4:
 * Version 2.0 (Rev. 2)
 * Added OOC support
 * Added support for IES and VCS Simulators

2013.3:
 * Version 2.0 (Rev. 1)
 * Added support for ILA 3.0 and VIO 3.0
 * Resolved controller hang issues on read-modify-write commands (See Xilinx Answer 54710)
 * Resolved Clock Driver Enable settings for RC1 on RDIMM interfaces (See Xilinx Answer 57279)
 * Updated Chipscope debug signals for OCLKDELAY calibration (See Xilinx Answer 54918)
 * Resolved timing failures with larger SSI devices  (See Xilinx Answer 56385)
 * Added AXI addressing support over 32 bits for DDR2 and DDR3
 * Corrected Chip Select width for single rank RDIMM devices (See Xilinx Answer 57436)

2013.2:
 * Version 2.0
 * 2013.2 software support
 * Added support for ILA 2.0 and VIO 2.0

2013.1:
 * Version 1.9.a
 * 2013.1 software support
 * Questa SIM 10.1b Support
 * Synplify Pro supported version G-2012.09-SP1
 * Support of LPDDR2 SDRAM Verilog designs
 * System Reset Pin Polarity selection
 * Additional clocks selection for AXI interface designs

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