SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE TRUE
SET_PREFERENCE ipi_mode no
SET_PREFERENCE is_ip_locked false
SET_PREFERENCE devicefamily artix7
SET_PREFERENCE device xc7a100t
SET_PREFERENCE speedgrade -1
SET_PREFERENCE package fgg484
SET_PREFERENCE verilogsim false
SET_PREFERENCE vhdlsim true
SET_PREFERENCE designentry VHDL
SET_PREFERENCE outputdirectory c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
SET_PREFERENCE subworkingdirectory c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
SET_PREFERENCE flowvendor Other
SET_PREFERENCE tool vivado
SET_PREFERENCE compnamestatus 0
SET_PARAMETER component_name mig_7series_0
SET_PARAMETER xml_input_file C:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
SET_PARAMETER data_dir_path c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3
SET_CORE_NAME Memory Interface Generator (MIG 7 Series)
SET_CORE_VERSION 2.3
SET_CORE_VLNV xilinx.com:ip:mig_7series:2.3
SET_CORE_PATH c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3
SET_CORE_DATASHEET c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3/data/docs/ds176_7series_MIS.pdf
