-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor             : Xilinx
-- \   \   \/     Version            : 2.3
--  \   \         Application	     : MIG
--  /   /         Filename           : xsim_files.prj
-- /___/   /\     Date Last Modified : $Date: 2011/06/02 08:31:16 $
-- \   \  /  \    Date Created       : Tue Jun 05 2012
--  \___\/\___\
--
-- Device          : 7 Series
-- Design Name     : DDR3 SDRAM
-- Purpose         : Contains a list of all the files associated with a design
-- Assumptions:
--      - Simulation takes place in \sim folder of MIG output directory
-- Reference       :
-- Revision History:
-------------------------------------------------------------------------------

verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_afifo.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_cmd_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_cmd_prbs_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_data_prbs_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_init_mem_pattern_ctr.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_memc_flow_vcontrol.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_memc_traffic_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_rd_data_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_read_data_path.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_read_posted_fifo.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_s7ven_data_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_tg_prbs_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_tg_status.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_traffic_gen_top.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_vio_init_pattern_bram.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_wr_data_gen.v
verilog  work  ../../../sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_write_data_path.v
vhdl  work  ../../../sources_1/imports/rtl/example_top.vhd
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_clk_ibuf.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_infrastructure.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_iodelay_ctrl.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_tempmon.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_arb_mux.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_arb_row_col.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_arb_select.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_cntrl.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_common.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_compare.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_mach.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_queue.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_state.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_col_mach.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_mc.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_rank_cntrl.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_rank_common.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_rank_mach.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_round_robin_arb.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_buf.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_dec_fix.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_gen.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_merge_enc.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_fi_xor.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ip_top/mig_7series_v2_3_mem_intfc.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ip_top/mig_7series_v2_3_memc_ui_top_std.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_group_io.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_lane.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_calib_top.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_if_post_fifo.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy_wrapper.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_of_pre_fifo.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_4lanes.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal_hr.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_init.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_cntlr.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_data.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_edge.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_lim.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_mux.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_samp.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_oclkdelay_cal.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_prbs_rdlvl.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_rdlvl.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_tempmon.v
vhdl  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_top.vhd
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrcal.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl_off_delay.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_prbs_gen.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_cc.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_edge_store.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_meta.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_pd.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_tap_base.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_top.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_cmd.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_rd_data.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_top.v
verilog  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_wr_data.v
vhdl  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.vhd
vhdl  work  ../../../sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.vhd
verilog  work  $XILINX_VIVADO/data/verilog/src/glbl.v
sv  work ddr3_model.sv -d x1Gb -d sg15E -d x8 
verilog  work  wiredly.v
verilog  work  sim_tb_top.v
