                                                          Log file                                                       

Generated by MIG MIG Version 2.3
Coregen 14.7 - Build Number P_INT.20150528 on Mon Jan 8 13:12:54 2018


Creating the directory 
c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design
Created the SDC file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/par/example_top.xdc Successfully
Copied the Traffic Gen Files Successfully
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/../docs/phy_only_support_readme.txt Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/par/readme.txt Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/ddr3_model.sv Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/ddr3_model_parameters.vh Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/xsim_files.prj Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/xsim_options.tcl Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/xsim_run.bat Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/readme.txt Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/sim.do Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/sim_tb_top.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/ies_run.sh Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/vcs_run.sh Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/wiredly.v Successfully
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Created the Top Level File - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/rtl/example_top_temp.vhd
Created the Top Level File - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/sim/sim_tb_top.v
The design output files are located in c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/example_design/rtl and ..example_design/par for rtl & ucf files respectively.
