MIG: 11:35:00 : Running customizer.xit
MIG: 11:35:00 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 11:35:00 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2014.2/data/ip/xilinx/mig_7series_v2_1... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5528-L1/coregen/mig_7series_0
MIG: 11:35:00 : synp_flow:  -- synthesis_mode: Other
MIG: 11:35:00 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5528-L1/coregen/mig_7series_0/_tmp/
MIG: 11:35:00 : vivado_mode: xpg_pa
MIG: 11:35:00 :  locked false  
MIG: 11:35:00 : HDL Language: VHDL
MIG: 11:35:00 : compInfo: true
MIG: 11:35:00 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/nt64/mig.exe
MIG: 11:35:00 : xilinx_path: C:/Xilinx/Vivado/2014.2/ids_lite/ISE
MIG: 11:35:00 : I am in catch area
MIG: 11:35:00 : Running C:/Xilinx/Vivado/2014.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5528-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5528-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 11:55:32 : Prasad before: xmlPropertyPrj --  .prj
MIG: 11:55:32 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 11:55:32 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5528-L1/coregen/mig_7series_0/mig_a.prj
MIG: 11:55:32 : Component_Name: mig_7series_0
MIG: 11:55:32 : Moving mig_7series_0 ...
MIG: 11:55:32 : Moving mig_7series_0.vho ...
MIG: 11:55:32 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:55:32 : Sending back 0
MIG: 11:55:42 : xml_input_file: mig_a.prj
MIG: 11:55:42 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:55:42 : xml_input_file: mig_a.prj
MIG: 11:55:42 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:55:42 : In updateAllModelParams
MIG: 11:55:42 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:55:42 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 11:55:42 : XGUI hdlLanguage: VHDL
MIG: 11:55:42 : xgui vivado_mode: xpg_pa
MIG: 11:55:42 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 11:55:42 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 11:55:42 : 1
MIG: 11:55:42 : Inside fn mem: DDR3
MIG: 11:55:42 : QDRII+ Inside fn ui: 100000000
MIG: 11:55:42 : 
MIG: 11:55:42 : 
MIG: 11:55:42 : 100000000
MIG: 11:55:42 : 
MIG: 11:55:42 :  polarity_value: 1
MIG: 11:55:42 : 
MIG: 11:55:42 : 
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 11:55:42 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 11:55:42 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 11:55:42 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 11:55:42 : 8
MIG: 11:55:42 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 11:55:42 : 64
MIG: 11:55:42 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 11:55:42 : 8
MIG: 11:55:42 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 11:55:42 : 3
MIG: 11:55:42 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 11:55:42 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: ECC ==> OFF
MIG: 11:55:42 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 11:55:42 : 64
MIG: 11:55:42 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 11:55:42 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 11:55:42 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 11:55:42 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 11:55:42 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 11:55:42 : 16
MIG: 11:55:42 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 11:55:42 : 30
MIG: 11:55:42 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 11:55:42 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 11:55:42 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 11:55:42 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 11:55:42 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 11:55:42 :  Invalid Param: DDR3_AL ==> "0"
MIG: 11:55:42 :  Invalid Param: DDR3_nAL ==> 0
MIG: 11:55:42 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 11:55:42 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 11:55:42 :  Invalid Param: DDR3_CL ==> 6
MIG: 11:55:42 :  Invalid Param: DDR3_CWL ==> 5
MIG: 11:55:42 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 11:55:42 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 11:55:42 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 11:55:42 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 11:55:42 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 11:55:42 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 11:55:42 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 11:55:42 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 11:55:42 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 11:55:42 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 11:55:42 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 11:55:42 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 11:55:42 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 11:55:42 :  Invalid Param: DDR3_tFAW ==> 32000
MIG: 11:55:42 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 11:55:42 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 11:55:42 :  Invalid Param: DDR3_tRCD ==> 13125
MIG: 11:55:42 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 11:55:42 :  Invalid Param: DDR3_tRFC ==> 300000
MIG: 11:55:42 :  Invalid Param: DDR3_tRP ==> 13125
MIG: 11:55:42 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 11:55:42 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 11:55:42 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 11:55:42 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 11:55:42 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 11:55:42 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 11:55:42 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 11:55:42 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 11:55:42 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 11:55:42 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 11:55:42 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 11:55:42 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 11:55:42 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 11:55:42 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 11:55:42 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 11:55:42 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 11:55:42 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 11:55:42 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 11:55:42 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 11:55:42 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 11:55:42 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 11:55:42 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 11:55:42 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 11:55:42 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 11:55:42 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 11:55:42 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 11:55:42 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 11:55:42 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 11:55:42 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 11:55:42 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 11:55:42 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 11:55:42 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 11:55:42 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 11:55:42 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 11:55:42 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 11:55:42 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 11:55:42 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 11:55:42 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 11:55:42 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 11:55:42 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 11:55:42 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 11:55:42 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 11:55:42 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 11:55:42 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 11:55:42 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 11:55:42 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 11:55:42 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 11:55:42 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 11:55:42 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 11:55:42 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 11:55:42 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 11:55:42 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 11:55:42 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 11:55:42 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 11:55:42 : 4
MIG: 11:55:42 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 11:55:42 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 11:55:42 : 
MIG: 11:55:42 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 11:55:42 : 
MIG: 11:55:42 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 11:55:43 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 11:55:43 : NOBUF
MIG: 11:55:43 : NOBUF
MIG: 11:55:43 : 
MIG: 11:55:43 : Same Interface
MIG: 11:56:43 : Running synthesis.xit
MIG: 11:56:44 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:56:44 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 11:56:45 : Running implementation.xit
MIG: 11:56:46 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:56:46 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 11:56:47 : Running vhdl_synth_rpr.xit
MIG: 11:56:48 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:56:48 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 11:56:49 : Running simulation.xit
MIG: 11:56:50 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:56:50 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 11:56:51 : Running vhdl_sim_rpr.xit
MIG: 11:56:52 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:56:52 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 13:22:36 : xml_input_file: mig_a.prj
MIG: 13:22:37 : Absolute path of xml_input_file: mig_a.prj
MIG: 13:22:37 : xml_input_file: mig_a.prj
MIG: 13:22:37 : Absolute path of xml_input_file: mig_a.prj
MIG: 13:22:37 : xml_input_file: ..\..\..\..\..\..\..\..\Documents\1VHDL\com-1800_001c\project_1\project_1.srcs\sources_1\ip\mig_7series_0\mig_a.prj
MIG: 13:22:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:22:37 : xml_input_file: ..\..\..\..\..\..\..\..\Documents\1VHDL\com-1800_001c\project_1\project_1.srcs\sources_1\ip\mig_7series_0\mig_a.prj
MIG: 13:22:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:22:37 : In updateAllModelParams
MIG: 13:22:37 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:22:37 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 13:22:37 : XGUI hdlLanguage: VHDL
MIG: 13:22:37 : xgui vivado_mode: xpg_pa
MIG: 13:22:37 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 13:22:37 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 13:22:37 : 
MIG: 13:22:37 : Inside fn mem: DDR3
MIG: 13:22:37 : QDRII+ Inside fn ui: 100000000
MIG: 13:22:37 : 
MIG: 13:22:37 : 
MIG: 13:22:37 : 
MIG: 13:22:37 : 
MIG: 13:22:37 :  polarity_value: 1
MIG: 13:22:37 : 
MIG: 13:22:37 : 
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 13:22:37 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 13:22:37 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 13:22:37 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 13:22:37 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: ECC ==> OFF
MIG: 13:22:37 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 13:22:37 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 13:22:37 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 13:22:37 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 13:22:37 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 13:22:37 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 13:22:37 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 13:22:37 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 13:22:37 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 13:22:37 :  Invalid Param: DDR3_AL ==> "0"
MIG: 13:22:37 :  Invalid Param: DDR3_nAL ==> 0
MIG: 13:22:37 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 13:22:37 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 13:22:37 :  Invalid Param: DDR3_CL ==> 6
MIG: 13:22:37 :  Invalid Param: DDR3_CWL ==> 5
MIG: 13:22:37 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 13:22:37 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 13:22:37 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 13:22:37 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 13:22:37 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 13:22:37 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 13:22:37 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 13:22:37 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 13:22:37 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 13:22:37 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 13:22:37 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 13:22:37 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 13:22:37 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 13:22:37 :  Invalid Param: DDR3_tFAW ==> 32000
MIG: 13:22:37 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 13:22:37 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 13:22:37 :  Invalid Param: DDR3_tRCD ==> 13125
MIG: 13:22:37 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 13:22:37 :  Invalid Param: DDR3_tRFC ==> 300000
MIG: 13:22:37 :  Invalid Param: DDR3_tRP ==> 13125
MIG: 13:22:37 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 13:22:37 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 13:22:37 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 13:22:37 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 13:22:37 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 13:22:37 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 13:22:37 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 13:22:37 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 13:22:37 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 13:22:37 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 13:22:37 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 13:22:37 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 13:22:37 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 13:22:37 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 13:22:37 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 13:22:37 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 13:22:37 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 13:22:37 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 13:22:37 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 13:22:37 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 13:22:37 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 13:22:37 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 13:22:37 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 13:22:37 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 13:22:37 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 13:22:37 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 13:22:37 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 13:22:37 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 13:22:37 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 13:22:37 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 13:22:37 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 13:22:37 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 13:22:37 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 13:22:37 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 13:22:37 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 13:22:37 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 13:22:37 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 13:22:37 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 13:22:37 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 13:22:37 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 13:22:37 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 13:22:37 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 13:22:37 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 13:22:37 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 13:22:37 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 13:22:37 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 13:22:37 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 13:22:37 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 13:22:37 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 13:22:37 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 13:22:37 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 13:22:37 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 13:22:37 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 13:22:37 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 13:22:37 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 13:22:37 : 
MIG: 13:22:37 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 13:22:37 : 
MIG: 13:22:37 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 13:22:37 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 13:22:37 : 
MIG: 13:22:37 : 
MIG: 13:22:37 : 
MIG: 13:22:37 : Same Interface
MIG: 13:26:31 : xml_input_file: mig_a.prj
MIG: 13:26:31 : Absolute path of xml_input_file: mig_a.prj
MIG: 13:26:31 : xml_input_file: mig_a.prj
MIG: 13:26:31 : Absolute path of xml_input_file: mig_a.prj
MIG: 13:26:31 : xml_input_file: ..\..\..\..\..\..\..\..\Documents\1VHDL\com-1800_001c\project_1\project_1.srcs\sources_1\ip\mig_7series_0\mig_a.prj
MIG: 13:26:31 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:26:31 : xml_input_file: ..\..\..\..\..\..\..\..\Documents\1VHDL\com-1800_001c\project_1\project_1.srcs\sources_1\ip\mig_7series_0\mig_a.prj
MIG: 13:26:31 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:26:31 : In updateAllModelParams
MIG: 13:26:31 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:26:31 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 13:26:31 : XGUI hdlLanguage: VHDL
MIG: 13:26:31 : xgui vivado_mode: xpg_pa
MIG: 13:26:31 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 13:26:31 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 13:26:31 : 
MIG: 13:26:31 : Inside fn mem: DDR3
MIG: 13:26:31 : QDRII+ Inside fn ui: 100000000
MIG: 13:26:31 : 
MIG: 13:26:31 : 
MIG: 13:26:31 : 
MIG: 13:26:31 : 
MIG: 13:26:31 :  polarity_value: 1
MIG: 13:26:31 : 
MIG: 13:26:31 : 
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 13:26:31 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 13:26:31 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 13:26:31 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 13:26:31 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: ECC ==> OFF
MIG: 13:26:31 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 13:26:31 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 13:26:31 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 13:26:31 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 13:26:31 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 13:26:31 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 13:26:31 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 13:26:31 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 13:26:31 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 13:26:31 :  Invalid Param: DDR3_AL ==> "0"
MIG: 13:26:31 :  Invalid Param: DDR3_nAL ==> 0
MIG: 13:26:31 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 13:26:31 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 13:26:31 :  Invalid Param: DDR3_CL ==> 6
MIG: 13:26:31 :  Invalid Param: DDR3_CWL ==> 5
MIG: 13:26:31 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 13:26:31 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 13:26:31 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 13:26:31 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 13:26:31 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 13:26:31 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 13:26:31 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 13:26:31 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 13:26:31 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 13:26:31 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 13:26:31 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 13:26:31 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 13:26:31 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 13:26:31 :  Invalid Param: DDR3_tFAW ==> 32000
MIG: 13:26:31 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 13:26:31 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 13:26:31 :  Invalid Param: DDR3_tRCD ==> 13125
MIG: 13:26:31 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 13:26:31 :  Invalid Param: DDR3_tRFC ==> 300000
MIG: 13:26:31 :  Invalid Param: DDR3_tRP ==> 13125
MIG: 13:26:31 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 13:26:31 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 13:26:31 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 13:26:31 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 13:26:31 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 13:26:31 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 13:26:31 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 13:26:31 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 13:26:31 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 13:26:31 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 13:26:31 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 13:26:31 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 13:26:31 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 13:26:31 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 13:26:31 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 13:26:31 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 13:26:31 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 13:26:31 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 13:26:31 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 13:26:31 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 13:26:31 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 13:26:31 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 13:26:31 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 13:26:31 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 13:26:31 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 13:26:31 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 13:26:31 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 13:26:31 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 13:26:31 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 13:26:31 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 13:26:31 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 13:26:31 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 13:26:31 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 13:26:31 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 13:26:31 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 13:26:31 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 13:26:31 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 13:26:31 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 13:26:31 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 13:26:31 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 13:26:31 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 13:26:31 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 13:26:31 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 13:26:31 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 13:26:31 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 13:26:31 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 13:26:31 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 13:26:31 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 13:26:31 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 13:26:31 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 13:26:31 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 13:26:31 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 13:26:31 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 13:26:31 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 13:26:31 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 13:26:31 : 
MIG: 13:26:31 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 13:26:31 : 
MIG: 13:26:31 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 13:26:31 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 13:26:31 : 
MIG: 13:26:31 : 
MIG: 13:26:31 : 
MIG: 13:26:31 : Same Interface
MIG: 13:28:27 : xml_input_file: mig_a.prj
MIG: 13:28:27 : Absolute path of xml_input_file: mig_a.prj
MIG: 13:28:27 : xml_input_file: mig_a.prj
MIG: 13:28:27 : Absolute path of xml_input_file: mig_a.prj
MIG: 13:28:27 : xml_input_file: ..\..\..\..\..\..\..\..\Documents\1VHDL\com-1800_001c\project_1\project_1.srcs\sources_1\ip\mig_7series_0\mig_a.prj
MIG: 13:28:27 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:28:27 : xml_input_file: ..\..\..\..\..\..\..\..\Documents\1VHDL\com-1800_001c\project_1\project_1.srcs\sources_1\ip\mig_7series_0\mig_a.prj
MIG: 13:28:27 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:28:28 : In updateAllModelParams
MIG: 13:28:28 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:28:28 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 13:28:28 : XGUI hdlLanguage: VHDL
MIG: 13:28:28 : xgui vivado_mode: xpg_pa
MIG: 13:28:28 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 13:28:28 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001c/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 13:28:28 : 
MIG: 13:28:28 : Inside fn mem: DDR3
MIG: 13:28:28 : QDRII+ Inside fn ui: 100000000
MIG: 13:28:28 : 
MIG: 13:28:28 : 
MIG: 13:28:28 : 
MIG: 13:28:28 : 
MIG: 13:28:28 :  polarity_value: 1
MIG: 13:28:28 : 
MIG: 13:28:28 : 
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 13:28:28 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 13:28:28 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 13:28:28 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 13:28:28 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: ECC ==> OFF
MIG: 13:28:28 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 13:28:28 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 13:28:28 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 13:28:28 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 13:28:28 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 13:28:28 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 13:28:28 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 13:28:28 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 13:28:28 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 13:28:28 :  Invalid Param: DDR3_AL ==> "0"
MIG: 13:28:28 :  Invalid Param: DDR3_nAL ==> 0
MIG: 13:28:28 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 13:28:28 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 13:28:28 :  Invalid Param: DDR3_CL ==> 6
MIG: 13:28:28 :  Invalid Param: DDR3_CWL ==> 5
MIG: 13:28:28 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 13:28:28 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 13:28:28 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 13:28:28 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 13:28:28 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 13:28:28 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 13:28:28 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 13:28:28 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 13:28:28 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 13:28:28 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 13:28:28 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 13:28:28 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 13:28:28 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 13:28:28 :  Invalid Param: DDR3_tFAW ==> 32000
MIG: 13:28:28 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 13:28:28 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 13:28:28 :  Invalid Param: DDR3_tRCD ==> 13125
MIG: 13:28:28 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 13:28:28 :  Invalid Param: DDR3_tRFC ==> 300000
MIG: 13:28:28 :  Invalid Param: DDR3_tRP ==> 13125
MIG: 13:28:28 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 13:28:28 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 13:28:28 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 13:28:28 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 13:28:28 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 13:28:28 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 13:28:28 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 13:28:28 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 13:28:28 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 13:28:28 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 13:28:28 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 13:28:28 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 13:28:28 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 13:28:28 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 13:28:28 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 13:28:28 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 13:28:28 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 13:28:28 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 13:28:28 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 13:28:28 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 13:28:28 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 13:28:28 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 13:28:28 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 13:28:28 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 13:28:28 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 13:28:28 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 13:28:28 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 13:28:28 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 13:28:28 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 13:28:28 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 13:28:28 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 13:28:28 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 13:28:28 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 13:28:28 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 13:28:28 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 13:28:28 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 13:28:28 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 13:28:28 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 13:28:28 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 13:28:28 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 13:28:28 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 13:28:28 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 13:28:28 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 13:28:28 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 13:28:28 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 13:28:28 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 13:28:28 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 13:28:28 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 13:28:28 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 13:28:28 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 13:28:28 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 13:28:28 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 13:28:28 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 13:28:28 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 13:28:28 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 13:28:28 : 
MIG: 13:28:28 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 13:28:28 : 
MIG: 13:28:28 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 13:28:28 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 13:28:28 : 
MIG: 13:28:28 : 
MIG: 13:28:28 : 
MIG: 13:28:28 : Same Interface
MIG: 18:28:00 : xml_input_file: mig_a.prj
MIG: 18:28:00 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:28:00 : xml_input_file: mig_a.prj
MIG: 18:28:00 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:28:00 : In updateAllModelParams
MIG: 18:28:00 : ################# RUNNING MIG BATCH ###################
MIG: 18:28:00 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 18:28:00 : synp_flow:  -- synthesis_mode: Other
MIG: 18:28:00 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 18:28:00 : vivado_mode: xpg_pa
MIG: 18:28:00 :  locked false  
MIG: 18:28:00 : HDL Language: VHDL
MIG: 18:28:00 : compInfo: true
MIG: 18:28:00 : Vivado Options xc7a100t fgg484 -1
MIG: 18:28:00 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:28:00 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:28:00 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:28:00 : I am in catch area
MIG: 18:28:00 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 18:28:16 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:28:16 : Component_Name: mig_7series_0
MIG: 18:28:16 : Moving mig_7series_0 ...
MIG: 18:28:16 : Moving mig_7series_0.vho ...
MIG: 18:28:16 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:28:16 : XGUI hdlLanguage: VHDL
MIG: 18:28:16 : xgui vivado_mode: xpg_pa
MIG: 18:28:16 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 18:28:16 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 18:28:16 : 1
MIG: 18:28:16 : Inside fn mem: DDR3
MIG: 18:28:16 : Inside fn detect_uiclk: 100000000
MIG: 18:28:16 : cntrl:  memtype: DDR3
MIG: 18:28:16 : 800
MIG: 18:28:16 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 18:28:16 : 
MIG: 18:28:16 : 
MIG: 18:28:16 : 100000000
MIG: 18:28:16 : 
MIG: 18:28:16 :  polarity_value: 1
MIG: 18:28:16 : 
MIG: 18:28:16 : 
MIG: 18:28:16 : cntrl:  memtype: DDR3
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 18:28:16 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 18:28:16 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 18:28:16 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 18:28:16 : 8
MIG: 18:28:16 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 18:28:16 : 64
MIG: 18:28:16 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 18:28:16 : 8
MIG: 18:28:16 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 18:28:16 : 3
MIG: 18:28:16 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 18:28:16 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: ECC ==> OFF
MIG: 18:28:16 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 18:28:16 : 64
MIG: 18:28:16 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 18:28:16 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 18:28:16 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 18:28:16 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 18:28:16 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 18:28:16 : 16
MIG: 18:28:16 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 18:28:16 : 30
MIG: 18:28:16 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 18:28:16 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 18:28:16 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 18:28:16 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 18:28:16 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 18:28:16 :  Invalid Param: DDR3_AL ==> "0"
MIG: 18:28:16 :  Invalid Param: DDR3_nAL ==> 0
MIG: 18:28:16 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 18:28:16 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 18:28:16 :  Invalid Param: DDR3_CL ==> 6
MIG: 18:28:16 :  Invalid Param: DDR3_CWL ==> 5
MIG: 18:28:16 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 18:28:16 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 18:28:16 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 18:28:16 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 18:28:16 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 18:28:16 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 18:28:16 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 18:28:16 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 18:28:16 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 18:28:16 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 18:28:16 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 18:28:16 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 18:28:16 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 18:28:16 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 18:28:16 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 18:28:16 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 18:28:16 :  Invalid Param: DDR3_tFAW ==> 32000
MIG: 18:28:16 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 18:28:16 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 18:28:16 :  Invalid Param: DDR3_tRCD ==> 13125
MIG: 18:28:16 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 18:28:16 :  Invalid Param: DDR3_tRFC ==> 300000
MIG: 18:28:16 :  Invalid Param: DDR3_tRP ==> 13125
MIG: 18:28:16 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 18:28:16 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 18:28:16 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 18:28:16 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 18:28:16 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 18:28:16 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 18:28:16 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 18:28:16 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 18:28:16 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 18:28:16 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 18:28:16 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 18:28:16 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 18:28:16 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 18:28:16 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 18:28:16 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 18:28:16 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 18:28:16 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 18:28:16 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 18:28:16 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 18:28:16 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 18:28:16 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 18:28:16 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 18:28:16 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 18:28:16 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 18:28:16 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 18:28:16 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 18:28:16 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 18:28:16 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 18:28:16 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 18:28:16 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 18:28:16 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 18:28:16 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 18:28:16 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 18:28:16 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 18:28:16 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 18:28:16 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 18:28:16 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 18:28:16 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 18:28:16 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 18:28:16 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 18:28:16 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 18:28:16 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 18:28:16 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 18:28:16 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 18:28:16 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 18:28:16 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 18:28:16 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 18:28:16 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 18:28:16 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 18:28:16 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 18:28:16 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 18:28:16 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 18:28:16 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 18:28:16 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 18:28:16 : 4
MIG: 18:28:16 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 18:28:16 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 18:28:16 : 
MIG: 18:28:16 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 18:28:16 : 
MIG: 18:28:16 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 18:28:16 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 18:28:16 : NOBUF
MIG: 18:28:17 : NOBUF
MIG: 18:28:17 : 
MIG: 18:28:17 : Same Interface
MIG: 18:31:54 : Running customizer.xit
MIG: 18:31:54 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 18:31:54 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-4332-L1/coregen/mig_7series_0
MIG: 18:31:54 : synp_flow:  -- synthesis_mode: Other
MIG: 18:31:54 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-4332-L1/coregen/mig_7series_0/_tmp/
MIG: 18:31:54 : vivado_mode: xpg_pa
MIG: 18:31:54 :  locked false  
MIG: 18:31:54 : HDL Language: VHDL
MIG: 18:31:54 : compInfo: false
MIG: 18:31:54 : Vivado Options xc7a100t fgg484 -1
MIG: 18:31:54 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:31:54 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:31:54 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:31:54 : I am in catch area
MIG: 18:31:54 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-4332-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-4332-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 18:33:20 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 18:33:20 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 18:33:20 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-4332-L1/coregen/mig_7series_0/mig_b.prj
MIG: 18:33:20 : Component_Name: mig_7series_0
MIG: 18:33:20 : Moving mig_7series_0 ...
MIG: 18:33:20 : Moving mig_7series_0.vho ...
MIG: 18:33:20 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:33:20 : Sending back 0
MIG: 18:33:22 : xml_input_file: mig_b.prj
MIG: 18:33:22 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:33:22 : xml_input_file: mig_b.prj
MIG: 18:33:22 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:33:22 : In updateAllModelParams
MIG: 18:33:22 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:33:22 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 18:33:22 : XGUI hdlLanguage: VHDL
MIG: 18:33:22 : xgui vivado_mode: xpg_pa
MIG: 18:33:22 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 18:33:22 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 18:33:22 : 
MIG: 18:33:22 : Inside fn mem: DDR3
MIG: 18:33:22 : Inside fn detect_uiclk: 100000000
MIG: 18:33:22 : cntrl:  memtype: DDR3
MIG: 18:33:22 : 
MIG: 18:33:22 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 18:33:22 : 
MIG: 18:33:22 : 
MIG: 18:33:22 : 
MIG: 18:33:22 : 
MIG: 18:33:22 :  polarity_value: 1
MIG: 18:33:22 : 
MIG: 18:33:22 : 
MIG: 18:33:22 : cntrl:  memtype: DDR3
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 18:33:22 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 18:33:22 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 18:33:22 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 18:33:22 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: ECC ==> OFF
MIG: 18:33:22 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 18:33:22 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 18:33:22 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 18:33:22 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 18:33:22 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 18:33:22 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 18:33:22 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 18:33:22 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 18:33:22 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 18:33:22 :  Invalid Param: DDR3_AL ==> "0"
MIG: 18:33:22 :  Invalid Param: DDR3_nAL ==> 0
MIG: 18:33:22 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 18:33:22 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 18:33:22 :  Invalid Param: DDR3_CL ==> 6
MIG: 18:33:22 :  Invalid Param: DDR3_CWL ==> 5
MIG: 18:33:22 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 18:33:22 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 18:33:22 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 18:33:22 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 18:33:22 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 18:33:22 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 18:33:22 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 18:33:22 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 18:33:22 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 18:33:22 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 18:33:22 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 18:33:22 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 18:33:22 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 18:33:22 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 18:33:22 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 18:33:22 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 18:33:22 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 18:33:22 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 18:33:22 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 18:33:22 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 18:33:22 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 18:33:22 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 18:33:22 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 18:33:22 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 18:33:22 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 18:33:22 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 18:33:22 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 18:33:22 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 18:33:22 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 18:33:22 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 18:33:22 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 18:33:22 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 18:33:22 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 18:33:22 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 18:33:22 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 18:33:22 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 18:33:22 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 18:33:22 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 18:33:22 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 18:33:22 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 18:33:22 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 18:33:22 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 18:33:22 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 18:33:22 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 18:33:22 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 18:33:22 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 18:33:22 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 18:33:22 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 18:33:22 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 18:33:22 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 18:33:22 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 18:33:22 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 18:33:22 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 18:33:22 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 18:33:22 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 18:33:22 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 18:33:22 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 18:33:22 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 18:33:22 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 18:33:22 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 18:33:22 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 18:33:22 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 18:33:22 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 18:33:22 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 18:33:22 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 18:33:22 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 18:33:22 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 18:33:22 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 18:33:22 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 18:33:22 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 18:33:22 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 18:33:22 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 18:33:22 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 18:33:22 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 18:33:22 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 18:33:22 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 18:33:22 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 18:33:22 : 
MIG: 18:33:22 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 18:33:22 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 18:33:22 : ON
MIG: 18:33:22 :  Valid Param: DDR3_DEBUG_PORT ==> ON
MIG: 18:33:22 : ON
MIG: 18:33:22 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 18:33:22 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 18:33:22 : 
MIG: 18:33:22 : 
MIG: 18:33:22 : 
MIG: 18:33:22 : Same Interface
MIG: 18:33:25 : ################# RUNNING MIG BATCH ###################
MIG: 18:33:25 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 18:33:25 : synp_flow:  -- synthesis_mode: Other
MIG: 18:33:25 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 18:33:25 : vivado_mode: xpg_pa
MIG: 18:33:25 :  locked false  
MIG: 18:33:25 : HDL Language: VHDL
MIG: 18:33:25 : compInfo: false
MIG: 18:33:25 : Vivado Options xc7a100t fgg484 -1
MIG: 18:33:25 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:33:25 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:33:25 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:33:25 : I am in catch area
MIG: 18:33:25 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 18:33:40 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:33:40 : Component_Name: mig_7series_0
MIG: 18:33:40 : Moving mig_7series_0 ...
MIG: 18:33:40 : Moving mig_7series_0.vho ...
MIG: 18:33:40 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:33:58 : Running synthesis.xit
MIG: 18:33:58 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:33:58 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 18:33:59 : Running vhdl_synth_rpr.xit
MIG: 18:33:59 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:33:59 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 18:33:59 : Running simulation.xit
MIG: 18:34:00 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:34:00 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 18:34:00 : Running vhdl_sim_rpr.xit
MIG: 18:34:01 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:34:01 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 18:34:01 : Running implementation.xit
MIG: 18:34:02 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:34:02 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:28:47 : xml_input_file: mig_b.prj
MIG: 09:28:47 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 09:28:47 : xml_input_file: mig_b.prj
MIG: 09:28:47 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 09:29:11 : Running customizer.xit
MIG: 09:29:11 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 09:29:11 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-2880-L1/coregen/mig_7series_0
MIG: 09:29:11 : synp_flow:  -- synthesis_mode: Other
MIG: 09:29:11 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-2880-L1/coregen/mig_7series_0/_tmp/
MIG: 09:29:11 : vivado_mode: xpg_pa
MIG: 09:29:11 :  locked false  
MIG: 09:29:11 : HDL Language: VHDL
MIG: 09:29:11 : compInfo: false
MIG: 09:29:11 : Vivado Options xc7a100t fgg484 -1
MIG: 09:29:11 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:29:11 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:29:11 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:29:11 : I am in catch area
MIG: 09:29:11 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-2880-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-2880-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 09:30:56 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 09:30:56 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 09:30:56 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/.Xil/Vivado-2880-L1/coregen/mig_7series_0/mig_a.prj
MIG: 09:30:56 : Component_Name: mig_7series_0
MIG: 09:30:56 : Moving mig_7series_0 ...
MIG: 09:30:56 : Moving mig_7series_0.vho ...
MIG: 09:30:56 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:30:56 : Sending back 0
MIG: 09:30:57 : xml_input_file: mig_a.prj
MIG: 09:30:57 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 09:30:57 : xml_input_file: mig_a.prj
MIG: 09:30:57 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 09:30:57 : In updateAllModelParams
MIG: 09:30:57 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:30:57 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:30:57 : XGUI hdlLanguage: VHDL
MIG: 09:30:57 : xgui vivado_mode: xpg_pa
MIG: 09:30:57 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 09:30:57 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 09:30:58 : 
MIG: 09:30:58 : Inside fn mem: DDR3
MIG: 09:30:58 : Inside fn detect_uiclk: 100000000
MIG: 09:30:58 : cntrl:  memtype: DDR3
MIG: 09:30:58 : 
MIG: 09:30:58 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 09:30:58 : 
MIG: 09:30:58 : 
MIG: 09:30:58 : 
MIG: 09:30:58 : 
MIG: 09:30:58 :  polarity_value: 1
MIG: 09:30:58 : 
MIG: 09:30:58 : 
MIG: 09:30:58 : cntrl:  memtype: DDR3
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 09:30:58 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 09:30:58 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 09:30:58 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 09:30:58 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: ECC ==> OFF
MIG: 09:30:58 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 09:30:58 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 09:30:58 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 09:30:58 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 09:30:58 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 09:30:58 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 09:30:58 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 09:30:58 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 09:30:58 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 09:30:58 :  Invalid Param: DDR3_AL ==> "0"
MIG: 09:30:58 :  Invalid Param: DDR3_nAL ==> 0
MIG: 09:30:58 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 09:30:58 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 09:30:58 :  Invalid Param: DDR3_CL ==> 6
MIG: 09:30:58 :  Invalid Param: DDR3_CWL ==> 5
MIG: 09:30:58 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 09:30:58 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 09:30:58 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 09:30:58 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 09:30:58 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 09:30:58 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 09:30:58 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 09:30:58 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 09:30:58 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 09:30:58 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 09:30:58 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 09:30:58 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 09:30:58 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 09:30:58 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 09:30:58 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 09:30:58 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 09:30:58 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 09:30:58 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 09:30:58 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 09:30:58 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 09:30:58 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 09:30:58 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 09:30:58 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 09:30:58 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 09:30:58 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 09:30:58 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 09:30:58 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 09:30:58 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 09:30:58 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 09:30:58 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 09:30:58 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 09:30:58 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 09:30:58 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 09:30:58 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 09:30:58 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 09:30:58 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 09:30:58 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 09:30:58 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 09:30:58 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 09:30:58 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 09:30:58 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 09:30:58 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 09:30:58 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 09:30:58 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 09:30:58 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 09:30:58 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 09:30:58 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 09:30:58 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 09:30:58 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 09:30:58 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 09:30:58 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 09:30:58 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 09:30:58 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 09:30:58 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 09:30:58 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 09:30:58 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 09:30:58 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 09:30:58 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 09:30:58 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 09:30:58 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 09:30:58 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 09:30:58 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 09:30:58 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 09:30:58 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 09:30:58 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 09:30:58 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 09:30:58 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 09:30:58 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 09:30:58 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 09:30:58 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 09:30:58 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 09:30:58 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 09:30:58 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 09:30:58 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 09:30:58 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 09:30:58 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 09:30:58 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 09:30:58 : 
MIG: 09:30:58 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 09:30:58 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 09:30:58 : OFF
MIG: 09:30:58 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 09:30:58 : OFF
MIG: 09:30:58 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 09:30:58 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 09:30:58 : 
MIG: 09:30:58 : 
MIG: 09:30:58 : 
MIG: 09:30:58 : Same Interface
MIG: 09:31:00 : ################# RUNNING MIG BATCH ###################
MIG: 09:31:00 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 09:31:00 : synp_flow:  -- synthesis_mode: Other
MIG: 09:31:00 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 09:31:00 : vivado_mode: xpg_pa
MIG: 09:31:00 :  locked false  
MIG: 09:31:00 : HDL Language: VHDL
MIG: 09:31:00 : compInfo: false
MIG: 09:31:00 : Vivado Options xc7a100t fgg484 -1
MIG: 09:31:00 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:31:00 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:31:00 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:31:00 : I am in catch area
MIG: 09:31:00 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 09:31:12 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 09:31:12 : Component_Name: mig_7series_0
MIG: 09:31:12 : Moving mig_7series_0 ...
MIG: 09:31:13 : Moving mig_7series_0.vho ...
MIG: 09:31:13 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:31:25 : Running synthesis.xit
MIG: 09:31:25 : ################# RUNNING MIG BATCH ###################
MIG: 09:31:25 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 09:31:25 : synp_flow:  -- synthesis_mode: Other
MIG: 09:31:25 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 09:31:25 : vivado_mode: xpg_pa
MIG: 09:31:25 :  locked false  
MIG: 09:31:25 : HDL Language: VHDL
MIG: 09:31:25 : compInfo: false
MIG: 09:31:25 : Vivado Options xc7a100t fgg484 -1
MIG: 09:31:25 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:31:25 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:31:25 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:31:25 : I am in catch area
MIG: 09:31:25 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 09:31:37 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 09:31:37 : Component_Name: mig_7series_0
MIG: 09:31:37 : Moving mig_7series_0 ...
MIG: 09:31:37 : Moving mig_7series_0.vho ...
MIG: 09:31:37 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:31:38 : Running vhdl_synth_rpr.xit
MIG: 09:31:38 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:31:38 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:31:38 : Running simulation.xit
MIG: 09:31:39 : ################# RUNNING MIG BATCH ###################
MIG: 09:31:39 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 09:31:39 : synp_flow:  -- synthesis_mode: Other
MIG: 09:31:39 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 09:31:39 : vivado_mode: xpg_pa
MIG: 09:31:39 :  locked false  
MIG: 09:31:39 : HDL Language: VHDL
MIG: 09:31:39 : compInfo: false
MIG: 09:31:39 : Vivado Options xc7a100t fgg484 -1
MIG: 09:31:39 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:31:39 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:31:39 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:31:39 : I am in catch area
MIG: 09:31:39 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 09:31:51 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 09:31:51 : Component_Name: mig_7series_0
MIG: 09:31:51 : Moving mig_7series_0 ...
MIG: 09:31:51 : Moving mig_7series_0.vho ...
MIG: 09:31:51 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:31:51 : Running vhdl_sim_rpr.xit
MIG: 09:31:52 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:31:52 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:31:52 : Running implementation.xit
MIG: 09:31:52 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:31:52 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 10:06:00 : Running customizer.xit
MIG: 10:06:00 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 10:06:00 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.sim/sim_1/behav/.Xil/Vivado-2880-L1/coregen/mig_7series_0
MIG: 10:06:00 : synp_flow:  -- synthesis_mode: Other
MIG: 10:06:00 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.sim/sim_1/behav/.Xil/Vivado-2880-L1/coregen/mig_7series_0/_tmp/
MIG: 10:06:00 : vivado_mode: xpg_pa
MIG: 10:06:00 :  locked false  
MIG: 10:06:00 : HDL Language: VHDL
MIG: 10:06:00 : compInfo: false
MIG: 10:06:00 : Vivado Options xc7a100t fgg484 -1
MIG: 10:06:00 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:06:00 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:06:00 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:06:00 : I am in catch area
MIG: 10:06:00 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.sim/sim_1/behav/.Xil/Vivado-2880-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.sim/sim_1/behav/.Xil/Vivado-2880-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 10:08:15 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 10:08:15 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 10:08:15 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.sim/sim_1/behav/.Xil/Vivado-2880-L1/coregen/mig_7series_0/mig_b.prj
MIG: 10:08:15 : Component_Name: mig_7series_0
MIG: 10:08:15 : Moving mig_7series_0 ...
MIG: 10:08:15 : Moving mig_7series_0.vho ...
MIG: 10:08:15 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:08:15 : Sending back 0
MIG: 10:08:17 : xml_input_file: mig_b.prj
MIG: 10:08:17 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:08:17 : xml_input_file: mig_b.prj
MIG: 10:08:17 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:08:17 : In updateAllModelParams
MIG: 10:08:17 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:08:17 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 10:08:17 : XGUI hdlLanguage: VHDL
MIG: 10:08:17 : xgui vivado_mode: xpg_pa
MIG: 10:08:17 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 10:08:17 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 10:08:17 : 
MIG: 10:08:17 : Inside fn mem: DDR3
MIG: 10:08:17 : Inside fn detect_uiclk: 100000000
MIG: 10:08:17 : cntrl:  memtype: DDR3
MIG: 10:08:17 : 
MIG: 10:08:17 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 10:08:17 : 
MIG: 10:08:17 : 
MIG: 10:08:17 : 
MIG: 10:08:17 : 
MIG: 10:08:17 :  polarity_value: 1
MIG: 10:08:17 : 
MIG: 10:08:17 : 
MIG: 10:08:17 : cntrl:  memtype: DDR3
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 10:08:17 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 10:08:17 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 10:08:17 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 10:08:17 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: ECC ==> OFF
MIG: 10:08:17 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 10:08:17 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 10:08:17 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 10:08:17 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 10:08:17 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 10:08:17 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 10:08:17 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 10:08:17 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 10:08:17 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 10:08:17 :  Invalid Param: DDR3_AL ==> "0"
MIG: 10:08:17 :  Invalid Param: DDR3_nAL ==> 0
MIG: 10:08:17 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 10:08:17 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 10:08:17 :  Invalid Param: DDR3_CL ==> 6
MIG: 10:08:17 :  Invalid Param: DDR3_CWL ==> 5
MIG: 10:08:17 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 10:08:17 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 10:08:17 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 10:08:17 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 10:08:17 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 10:08:17 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 10:08:17 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 10:08:17 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 10:08:17 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 10:08:17 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 10:08:17 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 10:08:17 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 10:08:17 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 10:08:17 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 10:08:17 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 10:08:17 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 10:08:17 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 10:08:17 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 10:08:17 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 10:08:17 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 10:08:17 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 10:08:17 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 10:08:17 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 10:08:17 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 10:08:17 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 10:08:17 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 10:08:17 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 10:08:17 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 10:08:17 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 10:08:17 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 10:08:17 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 10:08:17 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 10:08:17 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 10:08:17 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 10:08:17 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 10:08:17 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 10:08:17 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 10:08:17 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 10:08:17 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 10:08:17 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 10:08:17 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 10:08:17 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 10:08:17 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 10:08:17 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 10:08:17 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 10:08:17 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 10:08:17 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 10:08:17 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 10:08:17 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 10:08:17 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 10:08:17 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 10:08:17 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 10:08:17 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 10:08:17 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 10:08:17 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 10:08:17 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 10:08:17 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 10:08:17 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 10:08:17 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 10:08:17 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 10:08:17 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 10:08:17 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 10:08:17 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 10:08:17 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 10:08:17 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 10:08:17 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 10:08:17 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 10:08:17 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 10:08:17 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 10:08:17 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 10:08:17 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 10:08:17 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 10:08:17 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 10:08:17 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 10:08:17 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 10:08:17 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 10:08:17 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 10:08:17 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 10:08:17 : 
MIG: 10:08:17 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 10:08:17 : 
MIG: 10:08:17 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 10:08:17 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 10:08:17 : 
MIG: 10:08:17 : 
MIG: 10:08:17 : 
MIG: 10:08:17 : Same Interface
MIG: 10:08:20 : ################# RUNNING MIG BATCH ###################
MIG: 10:08:20 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 10:08:20 : synp_flow:  -- synthesis_mode: Other
MIG: 10:08:20 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 10:08:20 : vivado_mode: xpg_pa
MIG: 10:08:20 :  locked false  
MIG: 10:08:20 : HDL Language: VHDL
MIG: 10:08:20 : compInfo: false
MIG: 10:08:20 : Vivado Options xc7a100t fgg484 -1
MIG: 10:08:20 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:08:20 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:08:20 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:08:20 : I am in catch area
MIG: 10:08:20 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 10:08:33 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:08:33 : Component_Name: mig_7series_0
MIG: 10:08:33 : Moving mig_7series_0 ...
MIG: 10:08:33 : Moving mig_7series_0.vho ...
MIG: 10:08:33 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:08:39 : Running synthesis.xit
MIG: 10:08:39 : ################# RUNNING MIG BATCH ###################
MIG: 10:08:39 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 10:08:39 : synp_flow:  -- synthesis_mode: Other
MIG: 10:08:39 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 10:08:39 : vivado_mode: xpg_pa
MIG: 10:08:39 :  locked false  
MIG: 10:08:39 : HDL Language: VHDL
MIG: 10:08:39 : compInfo: false
MIG: 10:08:39 : Vivado Options xc7a100t fgg484 -1
MIG: 10:08:39 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:08:39 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:08:39 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:08:39 : I am in catch area
MIG: 10:08:39 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 10:08:52 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:08:52 : Component_Name: mig_7series_0
MIG: 10:08:52 : Moving mig_7series_0 ...
MIG: 10:08:52 : Moving mig_7series_0.vho ...
MIG: 10:08:52 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:08:53 : Running vhdl_synth_rpr.xit
MIG: 10:08:53 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:08:53 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 10:08:53 : Running simulation.xit
MIG: 10:08:54 : ################# RUNNING MIG BATCH ###################
MIG: 10:08:54 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 10:08:54 : synp_flow:  -- synthesis_mode: Other
MIG: 10:08:54 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 10:08:54 : vivado_mode: xpg_pa
MIG: 10:08:54 :  locked false  
MIG: 10:08:54 : HDL Language: VHDL
MIG: 10:08:54 : compInfo: false
MIG: 10:08:54 : Vivado Options xc7a100t fgg484 -1
MIG: 10:08:54 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:08:54 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:08:54 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:08:54 : I am in catch area
MIG: 10:08:54 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 10:09:07 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001i/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:09:07 : Component_Name: mig_7series_0
MIG: 10:09:07 : Moving mig_7series_0 ...
MIG: 10:09:07 : Moving mig_7series_0.vho ...
MIG: 10:09:07 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:09:07 : Running vhdl_sim_rpr.xit
MIG: 10:09:08 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:09:08 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 10:09:08 : Running implementation.xit
MIG: 10:09:08 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:09:08 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 12:26:11 : xml_input_file: mig_b.prj
MIG: 12:26:11 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001j/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:26:11 : xml_input_file: mig_b.prj
MIG: 12:26:11 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001j/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 13:47:45 : xml_input_file: mig_b.prj
MIG: 13:47:45 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 13:47:45 : xml_input_file: mig_b.prj
MIG: 13:47:45 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 13:48:15 : Running customizer.xit
MIG: 13:48:16 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 13:48:16 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/.Xil/Vivado-5860-L1/coregen/mig_7series_0
MIG: 13:48:16 : synp_flow:  -- synthesis_mode: Other
MIG: 13:48:16 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/.Xil/Vivado-5860-L1/coregen/mig_7series_0/_tmp/
MIG: 13:48:16 : vivado_mode: xpg_pa
MIG: 13:48:16 :  locked false  
MIG: 13:48:16 : HDL Language: VHDL
MIG: 13:48:16 : compInfo: false
MIG: 13:48:16 : Vivado Options xc7a100t fgg484 -1
MIG: 13:48:16 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:48:16 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:48:16 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:48:16 : I am in catch area
MIG: 13:48:16 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/.Xil/Vivado-5860-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/.Xil/Vivado-5860-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 13:50:52 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 13:50:52 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 13:50:52 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/.Xil/Vivado-5860-L1/coregen/mig_7series_0/mig_a.prj
MIG: 13:50:52 : Component_Name: mig_7series_0
MIG: 13:50:52 : Moving mig_7series_0 ...
MIG: 13:50:52 : Moving mig_7series_0.vho ...
MIG: 13:50:52 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:50:52 : Sending back 0
MIG: 13:50:53 : xml_input_file: mig_a.prj
MIG: 13:50:53 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:50:53 : xml_input_file: mig_a.prj
MIG: 13:50:53 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:50:53 : In updateAllModelParams
MIG: 13:50:53 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:50:53 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 13:50:54 : XGUI hdlLanguage: VHDL
MIG: 13:50:54 : xgui vivado_mode: xpg_pa
MIG: 13:50:54 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 13:50:54 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 13:50:54 : 
MIG: 13:50:54 : Inside fn mem: DDR3
MIG: 13:50:54 : Inside fn detect_uiclk: 100000000
MIG: 13:50:54 : cntrl:  memtype: DDR3
MIG: 13:50:54 : 
MIG: 13:50:54 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 13:50:54 : 
MIG: 13:50:54 : 
MIG: 13:50:54 : 
MIG: 13:50:54 : 
MIG: 13:50:54 :  polarity_value: 1
MIG: 13:50:54 : 
MIG: 13:50:54 : 
MIG: 13:50:54 : cntrl:  memtype: DDR3
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 13:50:54 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 13:50:54 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 13:50:54 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 13:50:54 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: ECC ==> OFF
MIG: 13:50:54 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 13:50:54 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 13:50:54 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 13:50:54 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 13:50:54 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 13:50:54 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 13:50:54 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 13:50:54 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 13:50:54 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 13:50:54 :  Invalid Param: DDR3_AL ==> "0"
MIG: 13:50:54 :  Invalid Param: DDR3_nAL ==> 0
MIG: 13:50:54 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 13:50:54 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 13:50:54 :  Invalid Param: DDR3_CL ==> 6
MIG: 13:50:54 :  Invalid Param: DDR3_CWL ==> 5
MIG: 13:50:54 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 13:50:54 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 13:50:54 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 13:50:54 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 13:50:54 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 13:50:54 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 13:50:54 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 13:50:54 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 13:50:54 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 13:50:54 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 13:50:54 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 13:50:54 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 13:50:54 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 13:50:54 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 13:50:54 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 13:50:54 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 13:50:54 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 13:50:54 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 13:50:54 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 13:50:54 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 13:50:54 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 13:50:54 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 13:50:54 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 13:50:54 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 13:50:54 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 13:50:54 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 13:50:54 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 13:50:54 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 13:50:54 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 13:50:54 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 13:50:54 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 13:50:54 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 13:50:54 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 13:50:54 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 13:50:54 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 13:50:54 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 13:50:54 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 13:50:54 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 13:50:54 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 13:50:54 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 13:50:54 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 13:50:54 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 13:50:54 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 13:50:54 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 13:50:54 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 13:50:54 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 13:50:54 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 13:50:54 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 13:50:54 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 13:50:54 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 13:50:54 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 13:50:54 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 13:50:54 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 13:50:54 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 13:50:54 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 13:50:54 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 13:50:54 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 13:50:54 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 13:50:54 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 13:50:54 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 13:50:54 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 13:50:54 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 13:50:54 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 13:50:54 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 13:50:54 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 13:50:54 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 13:50:54 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 13:50:54 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 13:50:54 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 13:50:54 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 13:50:54 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 13:50:54 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 13:50:54 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 13:50:54 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 13:50:54 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 13:50:54 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 13:50:54 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 13:50:54 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 13:50:54 : 
MIG: 13:50:54 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 13:50:54 : 
MIG: 13:50:54 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 13:50:54 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 13:50:54 : 
MIG: 13:50:54 : 
MIG: 13:50:54 : 
MIG: 13:50:54 : Same Interface
MIG: 13:50:56 : ################# RUNNING MIG BATCH ###################
MIG: 13:50:56 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 13:50:56 : synp_flow:  -- synthesis_mode: Other
MIG: 13:50:56 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:50:56 : vivado_mode: xpg_pa
MIG: 13:50:56 :  locked false  
MIG: 13:50:56 : HDL Language: VHDL
MIG: 13:50:56 : compInfo: false
MIG: 13:50:56 : Vivado Options xc7a100t fgg484 -1
MIG: 13:50:56 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:50:56 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:50:56 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:50:56 : I am in catch area
MIG: 13:50:56 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 13:51:09 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:51:09 : Component_Name: mig_7series_0
MIG: 13:51:09 : Moving mig_7series_0 ...
MIG: 13:51:09 : Moving mig_7series_0.vho ...
MIG: 13:51:09 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:51:15 : Running synthesis.xit
MIG: 13:51:15 : ################# RUNNING MIG BATCH ###################
MIG: 13:51:15 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 13:51:15 : synp_flow:  -- synthesis_mode: Other
MIG: 13:51:15 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:51:15 : vivado_mode: xpg_pa
MIG: 13:51:15 :  locked false  
MIG: 13:51:15 : HDL Language: VHDL
MIG: 13:51:15 : compInfo: false
MIG: 13:51:15 : Vivado Options xc7a100t fgg484 -1
MIG: 13:51:15 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:51:15 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:51:15 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:51:15 : I am in catch area
MIG: 13:51:15 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 13:51:27 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:51:27 : Component_Name: mig_7series_0
MIG: 13:51:27 : Moving mig_7series_0 ...
MIG: 13:51:27 : Moving mig_7series_0.vho ...
MIG: 13:51:27 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:51:28 : Running vhdl_synth_rpr.xit
MIG: 13:51:28 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:51:28 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 13:51:28 : Running simulation.xit
MIG: 13:51:29 : ################# RUNNING MIG BATCH ###################
MIG: 13:51:29 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 13:51:29 : synp_flow:  -- synthesis_mode: Other
MIG: 13:51:29 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:51:29 : vivado_mode: xpg_pa
MIG: 13:51:29 :  locked false  
MIG: 13:51:29 : HDL Language: VHDL
MIG: 13:51:29 : compInfo: false
MIG: 13:51:29 : Vivado Options xc7a100t fgg484 -1
MIG: 13:51:29 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:51:29 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:51:29 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:51:29 : I am in catch area
MIG: 13:51:29 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 13:51:41 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:51:41 : Component_Name: mig_7series_0
MIG: 13:51:41 : Moving mig_7series_0 ...
MIG: 13:51:41 : Moving mig_7series_0.vho ...
MIG: 13:51:41 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:51:42 : Running vhdl_sim_rpr.xit
MIG: 13:51:42 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:51:42 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 13:51:42 : Running implementation.xit
MIG: 13:51:43 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:51:43 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:46:19 : xml_input_file: mig_a.prj
MIG: 09:46:19 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 09:46:19 : xml_input_file: mig_a.prj
MIG: 09:46:19 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 09:46:48 : Running customizer.xit
MIG: 09:46:48 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 09:46:48 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0
MIG: 09:46:48 : synp_flow:  -- synthesis_mode: Other
MIG: 09:46:48 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/_tmp/
MIG: 09:46:48 : vivado_mode: xpg_pa
MIG: 09:46:48 :  locked false  
MIG: 09:46:48 : HDL Language: VHDL
MIG: 09:46:48 : compInfo: false
MIG: 09:46:48 : Vivado Options xc7a100t fgg484 -1
MIG: 09:46:48 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:46:48 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:46:48 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:46:48 : I am in catch area
MIG: 09:46:48 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 09:58:11 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 09:58:11 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 09:58:11 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/mig_b.prj
MIG: 09:58:11 : Component_Name: mig_7series_0
MIG: 09:58:11 : Moving mig_7series_0 ...
MIG: 09:58:11 : Moving mig_7series_0.vho ...
MIG: 09:58:11 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:58:11 : Sending back 0
MIG: 09:58:13 : xml_input_file: mig_b.prj
MIG: 09:58:13 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 09:58:13 : xml_input_file: mig_b.prj
MIG: 09:58:13 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 09:58:13 : In updateAllModelParams
MIG: 09:58:13 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:58:13 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:58:13 : XGUI hdlLanguage: VHDL
MIG: 09:58:13 : xgui vivado_mode: xpg_pa
MIG: 09:58:13 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 09:58:13 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 09:58:13 : 
MIG: 09:58:13 : Inside fn mem: DDR3
MIG: 09:58:13 : Inside fn detect_uiclk: 100000000
MIG: 09:58:13 : cntrl:  memtype: DDR3
MIG: 09:58:13 : 
MIG: 09:58:13 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 09:58:13 : 
MIG: 09:58:13 : 
MIG: 09:58:13 : 
MIG: 09:58:13 : 
MIG: 09:58:13 :  polarity_value: 1
MIG: 09:58:13 : 
MIG: 09:58:13 : 
MIG: 09:58:13 : cntrl:  memtype: DDR3
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 09:58:13 : 2
MIG: 09:58:13 :  Valid Param: DDR3_CK_WIDTH ==> 2
MIG: 09:58:13 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 09:58:13 : 2
MIG: 09:58:13 :  Valid Param: DDR3_CS_WIDTH ==> 2
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 09:58:13 : 2
MIG: 09:58:13 :  Valid Param: DDR3_CKE_WIDTH ==> 2
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 09:58:13 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 09:58:13 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 09:58:13 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: ECC ==> OFF
MIG: 09:58:13 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 09:58:13 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 09:58:13 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 09:58:13 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 09:58:13 :  Invalid Param: DDR3_RANKS ==> 2
MIG: 09:58:13 : 2
MIG: 09:58:13 :  Valid Param: DDR3_ODT_WIDTH ==> 2
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 09:58:13 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 09:58:13 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 09:58:13 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 09:58:13 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 09:58:13 :  Invalid Param: DDR3_AL ==> "0"
MIG: 09:58:13 :  Invalid Param: DDR3_nAL ==> 0
MIG: 09:58:13 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 09:58:13 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 09:58:13 :  Invalid Param: DDR3_CL ==> 6
MIG: 09:58:13 :  Invalid Param: DDR3_CWL ==> 5
MIG: 09:58:13 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 09:58:13 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 09:58:13 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 09:58:13 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 09:58:13 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 09:58:13 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 09:58:13 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 09:58:13 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 09:58:13 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 09:58:13 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 09:58:13 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 09:58:13 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 09:58:13 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 09:58:13 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 09:58:13 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 09:58:13 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 09:58:13 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 09:58:13 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 09:58:13 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 09:58:13 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 09:58:13 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 09:58:13 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 09:58:13 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 09:58:13 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 09:58:13 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 09:58:13 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 09:58:13 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 09:58:13 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 09:58:13 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 09:58:13 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 09:58:13 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 09:58:13 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 09:58:13 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 09:58:13 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 09:58:13 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 09:58:13 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE3F2FF"
MIG: 09:58:13 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 09:58:13 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000001313"
MIG: 09:58:13 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 09:58:13 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 09:58:13 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 09:58:13 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 09:58:13 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000112113"
MIG: 09:58:13 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000110111"
MIG: 09:58:13 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000114115"
MIG: 09:58:13 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 09:58:13 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 09:58:13 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 09:58:13 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 09:58:13 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 09:58:13 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000011"
MIG: 09:58:13 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 09:58:13 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 09:58:13 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 09:58:13 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 09:58:13 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 09:58:13 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 09:58:13 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 09:58:13 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 09:58:13 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 09:58:13 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 09:58:13 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 09:58:13 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 09:58:13 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 09:58:13 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 09:58:13 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 09:58:13 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 09:58:13 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 09:58:13 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 09:58:13 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 09:58:13 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 09:58:13 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 09:58:13 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 09:58:13 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 09:58:13 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 09:58:13 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 09:58:13 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 09:58:13 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 09:58:13 : 
MIG: 09:58:13 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 09:58:13 : 
MIG: 09:58:13 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 09:58:13 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 09:58:13 : 
MIG: 09:58:13 : 
MIG: 09:58:13 : 
MIG: 09:58:13 : Same Interface
MIG: 09:58:16 : ################# RUNNING MIG BATCH ###################
MIG: 09:58:16 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 09:58:16 : synp_flow:  -- synthesis_mode: Other
MIG: 09:58:16 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 09:58:16 : vivado_mode: xpg_pa
MIG: 09:58:16 :  locked false  
MIG: 09:58:16 : HDL Language: VHDL
MIG: 09:58:16 : compInfo: false
MIG: 09:58:16 : Vivado Options xc7a100t fgg484 -1
MIG: 09:58:16 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:58:16 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:58:16 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:58:16 : I am in catch area
MIG: 09:58:16 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 09:58:29 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 09:58:29 : Component_Name: mig_7series_0
MIG: 09:58:29 : Moving mig_7series_0 ...
MIG: 09:58:29 : Moving mig_7series_0.vho ...
MIG: 09:58:29 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:58:36 : Running synthesis.xit
MIG: 09:58:36 : ################# RUNNING MIG BATCH ###################
MIG: 09:58:36 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 09:58:36 : synp_flow:  -- synthesis_mode: Other
MIG: 09:58:36 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 09:58:36 : vivado_mode: xpg_pa
MIG: 09:58:36 :  locked false  
MIG: 09:58:36 : HDL Language: VHDL
MIG: 09:58:36 : compInfo: false
MIG: 09:58:36 : Vivado Options xc7a100t fgg484 -1
MIG: 09:58:36 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:58:36 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:58:36 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:58:36 : I am in catch area
MIG: 09:58:36 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 09:58:49 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 09:58:49 : Component_Name: mig_7series_0
MIG: 09:58:49 : Moving mig_7series_0 ...
MIG: 09:58:50 : Moving mig_7series_0.vho ...
MIG: 09:58:50 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:58:50 : Running vhdl_synth_rpr.xit
MIG: 09:58:50 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:58:50 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:58:51 : Running simulation.xit
MIG: 09:58:51 : ################# RUNNING MIG BATCH ###################
MIG: 09:58:51 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 09:58:51 : synp_flow:  -- synthesis_mode: Other
MIG: 09:58:51 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 09:58:51 : vivado_mode: xpg_pa
MIG: 09:58:51 :  locked false  
MIG: 09:58:51 : HDL Language: VHDL
MIG: 09:58:51 : compInfo: false
MIG: 09:58:51 : Vivado Options xc7a100t fgg484 -1
MIG: 09:58:51 : 1: xc7a100t 2: fgg484 3: -1
MIG: 09:58:51 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 09:58:51 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 09:58:51 : I am in catch area
MIG: 09:58:51 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 09:59:04 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 09:59:04 : Component_Name: mig_7series_0
MIG: 09:59:04 : Moving mig_7series_0 ...
MIG: 09:59:04 : Moving mig_7series_0.vho ...
MIG: 09:59:04 : Moving mig_7series_0_xmdf.tcl ...
MIG: 09:59:05 : Running vhdl_sim_rpr.xit
MIG: 09:59:05 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:59:05 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 09:59:06 : Running implementation.xit
MIG: 09:59:06 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 09:59:06 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 15:49:09 : Running customizer.xit
MIG: 15:49:09 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 15:49:09 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0
MIG: 15:49:09 : synp_flow:  -- synthesis_mode: Other
MIG: 15:49:09 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/_tmp/
MIG: 15:49:09 : vivado_mode: xpg_pa
MIG: 15:49:09 :  locked false  
MIG: 15:49:09 : HDL Language: VHDL
MIG: 15:49:09 : compInfo: false
MIG: 15:49:09 : Vivado Options xc7a100t fgg484 -1
MIG: 15:49:09 : 1: xc7a100t 2: fgg484 3: -1
MIG: 15:49:09 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 15:49:09 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 15:49:09 : I am in catch area
MIG: 15:49:09 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 15:50:52 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 15:50:52 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 15:50:52 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/mig_a.prj
MIG: 15:50:52 : Component_Name: mig_7series_0
MIG: 15:50:52 : Moving mig_7series_0 ...
MIG: 15:50:52 : Moving mig_7series_0.vho ...
MIG: 15:50:52 : Moving mig_7series_0_xmdf.tcl ...
MIG: 15:50:52 : Sending back 0
MIG: 15:50:54 : xml_input_file: mig_a.prj
MIG: 15:50:54 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:50:54 : xml_input_file: mig_a.prj
MIG: 15:50:54 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:50:54 : In updateAllModelParams
MIG: 15:50:54 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 15:50:54 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 15:50:54 : XGUI hdlLanguage: VHDL
MIG: 15:50:54 : xgui vivado_mode: xpg_pa
MIG: 15:50:54 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 15:50:54 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 15:50:54 : 
MIG: 15:50:54 : Inside fn mem: DDR3
MIG: 15:50:54 : Inside fn detect_uiclk: 100000000
MIG: 15:50:54 : cntrl:  memtype: DDR3
MIG: 15:50:54 : 
MIG: 15:50:54 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 15:50:54 : 
MIG: 15:50:54 : 
MIG: 15:50:54 : 
MIG: 15:50:54 : 
MIG: 15:50:54 :  polarity_value: 1
MIG: 15:50:54 : 
MIG: 15:50:54 : 
MIG: 15:50:54 : cntrl:  memtype: DDR3
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 15:50:54 : 1
MIG: 15:50:54 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 15:50:54 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 15:50:54 : 1
MIG: 15:50:54 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 15:50:54 : 1
MIG: 15:50:54 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 15:50:54 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 15:50:54 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 15:50:54 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: ECC ==> OFF
MIG: 15:50:54 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 15:50:54 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 15:50:54 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 15:50:54 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 15:50:54 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 15:50:54 : 1
MIG: 15:50:54 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 15:50:54 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 15:50:54 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 15:50:54 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 15:50:54 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 15:50:54 :  Invalid Param: DDR3_AL ==> "0"
MIG: 15:50:54 :  Invalid Param: DDR3_nAL ==> 0
MIG: 15:50:54 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 15:50:54 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 15:50:54 :  Invalid Param: DDR3_CL ==> 6
MIG: 15:50:54 :  Invalid Param: DDR3_CWL ==> 5
MIG: 15:50:54 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 15:50:54 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 15:50:54 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 15:50:54 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 15:50:54 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 15:50:54 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 15:50:54 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 15:50:54 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 15:50:54 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 15:50:54 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 15:50:54 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 15:50:54 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 15:50:54 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 15:50:54 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 15:50:54 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 15:50:54 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 15:50:54 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 15:50:54 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 15:50:54 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 15:50:54 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 15:50:54 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 15:50:54 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 15:50:54 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 15:50:54 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 15:50:54 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 15:50:54 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 15:50:54 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 15:50:54 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 15:50:54 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 15:50:54 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 15:50:54 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 15:50:54 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 15:50:54 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 15:50:54 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 15:50:54 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 15:50:54 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 15:50:54 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 15:50:54 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 15:50:54 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 15:50:54 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 15:50:54 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 15:50:54 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 15:50:54 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 15:50:54 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 15:50:54 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 15:50:54 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 15:50:54 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 15:50:54 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 15:50:54 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 15:50:54 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 15:50:54 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 15:50:54 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 15:50:54 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 15:50:54 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 15:50:54 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 15:50:54 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 15:50:54 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 15:50:54 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 15:50:54 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 15:50:54 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 15:50:54 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 15:50:54 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 15:50:54 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 15:50:54 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 15:50:54 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 15:50:54 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 15:50:54 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 15:50:54 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 15:50:54 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 15:50:54 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 15:50:54 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 15:50:54 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 15:50:54 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 15:50:54 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 15:50:54 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 15:50:54 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 15:50:54 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 15:50:54 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 15:50:54 : 
MIG: 15:50:54 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 15:50:54 : 
MIG: 15:50:54 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 15:50:54 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 15:50:54 : 
MIG: 15:50:54 : 
MIG: 15:50:54 : 
MIG: 15:50:54 : Same Interface
MIG: 15:50:57 : ################# RUNNING MIG BATCH ###################
MIG: 15:50:57 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 15:50:57 : synp_flow:  -- synthesis_mode: Other
MIG: 15:50:57 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 15:50:57 : vivado_mode: xpg_pa
MIG: 15:50:57 :  locked false  
MIG: 15:50:57 : HDL Language: VHDL
MIG: 15:50:57 : compInfo: false
MIG: 15:50:57 : Vivado Options xc7a100t fgg484 -1
MIG: 15:50:57 : 1: xc7a100t 2: fgg484 3: -1
MIG: 15:50:57 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 15:50:57 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 15:50:57 : I am in catch area
MIG: 15:50:57 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 15:51:10 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:51:10 : Component_Name: mig_7series_0
MIG: 15:51:10 : Moving mig_7series_0 ...
MIG: 15:51:10 : Moving mig_7series_0.vho ...
MIG: 15:51:10 : Moving mig_7series_0_xmdf.tcl ...
MIG: 16:02:06 : Running synthesis.xit
MIG: 16:02:06 : ################# RUNNING MIG BATCH ###################
MIG: 16:02:06 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 16:02:06 : synp_flow:  -- synthesis_mode: Other
MIG: 16:02:06 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 16:02:06 : vivado_mode: xpg_pa
MIG: 16:02:06 :  locked false  
MIG: 16:02:06 : HDL Language: VHDL
MIG: 16:02:06 : compInfo: false
MIG: 16:02:06 : Vivado Options xc7a100t fgg484 -1
MIG: 16:02:06 : 1: xc7a100t 2: fgg484 3: -1
MIG: 16:02:06 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 16:02:06 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 16:02:06 : I am in catch area
MIG: 16:02:06 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 16:02:19 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 16:02:19 : Component_Name: mig_7series_0
MIG: 16:02:19 : Moving mig_7series_0 ...
MIG: 16:02:19 : Moving mig_7series_0.vho ...
MIG: 16:02:19 : Moving mig_7series_0_xmdf.tcl ...
MIG: 16:02:19 : Running vhdl_synth_rpr.xit
MIG: 16:02:20 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 16:02:20 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 16:02:20 : Running simulation.xit
MIG: 16:02:20 : ################# RUNNING MIG BATCH ###################
MIG: 16:02:20 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 16:02:20 : synp_flow:  -- synthesis_mode: Other
MIG: 16:02:20 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 16:02:20 : vivado_mode: xpg_pa
MIG: 16:02:20 :  locked false  
MIG: 16:02:20 : HDL Language: VHDL
MIG: 16:02:20 : compInfo: false
MIG: 16:02:20 : Vivado Options xc7a100t fgg484 -1
MIG: 16:02:20 : 1: xc7a100t 2: fgg484 3: -1
MIG: 16:02:20 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 16:02:20 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 16:02:20 : I am in catch area
MIG: 16:02:20 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 16:02:34 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 16:02:34 : Component_Name: mig_7series_0
MIG: 16:02:34 : Moving mig_7series_0 ...
MIG: 16:02:34 : Moving mig_7series_0.vho ...
MIG: 16:02:34 : Moving mig_7series_0_xmdf.tcl ...
MIG: 16:02:35 : Running vhdl_sim_rpr.xit
MIG: 16:02:35 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 16:02:35 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 16:02:35 : Running implementation.xit
MIG: 16:02:36 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 16:02:36 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 17:08:57 : Running customizer.xit
MIG: 17:08:57 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 17:08:57 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0
MIG: 17:08:57 : synp_flow:  -- synthesis_mode: Other
MIG: 17:08:57 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/_tmp/
MIG: 17:08:57 : vivado_mode: xpg_pa
MIG: 17:08:57 :  locked false  
MIG: 17:08:57 : HDL Language: VHDL
MIG: 17:08:57 : compInfo: false
MIG: 17:08:57 : Vivado Options xc7a100t fgg484 -1
MIG: 17:08:57 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:08:57 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:08:57 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:08:57 : I am in catch area
MIG: 17:08:57 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 17:11:59 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 17:11:59 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 17:11:59 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/mig_b.prj
MIG: 17:11:59 : Component_Name: mig_7series_0
MIG: 17:11:59 : Moving mig_7series_0 ...
MIG: 17:11:59 : Moving mig_7series_0.vho ...
MIG: 17:11:59 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:11:59 : Sending back 0
MIG: 17:12:01 : xml_input_file: mig_b.prj
MIG: 17:12:01 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:12:01 : xml_input_file: mig_b.prj
MIG: 17:12:01 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:12:01 : In updateAllModelParams
MIG: 17:12:01 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:12:01 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 17:12:01 : XGUI hdlLanguage: VHDL
MIG: 17:12:01 : xgui vivado_mode: xpg_pa
MIG: 17:12:01 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 17:12:01 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 17:12:01 : 
MIG: 17:12:01 : Inside fn mem: DDR3
MIG: 17:12:01 : Inside fn detect_uiclk: 100000000
MIG: 17:12:01 : cntrl:  memtype: DDR3
MIG: 17:12:01 : 
MIG: 17:12:01 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 17:12:01 : 
MIG: 17:12:01 : 
MIG: 17:12:01 : 
MIG: 17:12:01 : 
MIG: 17:12:01 :  polarity_value: 1
MIG: 17:12:01 : 
MIG: 17:12:01 : 
MIG: 17:12:01 : cntrl:  memtype: DDR3
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 17:12:01 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 17:12:01 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 17:12:01 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 17:12:01 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: ECC ==> OFF
MIG: 17:12:01 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 17:12:01 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 17:12:01 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 17:12:01 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 17:12:01 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 17:12:01 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 17:12:01 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 17:12:01 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 17:12:01 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 17:12:01 :  Invalid Param: DDR3_AL ==> "0"
MIG: 17:12:01 :  Invalid Param: DDR3_nAL ==> 0
MIG: 17:12:01 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 17:12:01 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 17:12:01 :  Invalid Param: DDR3_CL ==> 6
MIG: 17:12:01 :  Invalid Param: DDR3_CWL ==> 5
MIG: 17:12:01 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 17:12:01 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 17:12:01 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 17:12:01 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 17:12:01 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 17:12:01 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 17:12:01 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 17:12:01 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 17:12:01 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 17:12:01 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 17:12:01 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 17:12:01 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 17:12:01 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 17:12:01 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 17:12:01 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 17:12:01 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 17:12:01 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 17:12:01 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 17:12:01 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 17:12:01 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 17:12:01 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 17:12:01 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 17:12:01 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 17:12:01 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 17:12:01 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 17:12:01 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 17:12:01 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 17:12:01 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 17:12:01 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 17:12:01 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 17:12:01 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 17:12:01 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 17:12:01 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 17:12:01 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 17:12:01 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 17:12:01 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 17:12:01 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 17:12:01 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 17:12:01 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 17:12:01 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 17:12:01 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 17:12:01 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 17:12:01 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 17:12:01 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 17:12:01 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 17:12:01 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 17:12:01 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 17:12:01 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 17:12:01 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 17:12:01 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 17:12:01 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 17:12:01 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 17:12:01 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 17:12:01 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 17:12:01 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 17:12:01 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 17:12:01 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 17:12:01 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 17:12:01 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 17:12:01 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 17:12:01 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 17:12:01 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 17:12:01 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 17:12:01 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 17:12:01 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 17:12:01 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 17:12:01 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 17:12:01 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 17:12:01 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 17:12:01 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 17:12:01 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 17:12:01 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 17:12:01 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 17:12:01 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 17:12:01 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 17:12:01 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 17:12:01 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 17:12:01 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 17:12:01 : 
MIG: 17:12:01 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 17:12:01 : 
MIG: 17:12:01 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 17:12:01 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 17:12:01 : 
MIG: 17:12:01 : 
MIG: 17:12:01 : 
MIG: 17:12:01 : Same Interface
MIG: 17:12:03 : ################# RUNNING MIG BATCH ###################
MIG: 17:12:03 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 17:12:03 : synp_flow:  -- synthesis_mode: Other
MIG: 17:12:03 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:12:03 : vivado_mode: xpg_pa
MIG: 17:12:03 :  locked false  
MIG: 17:12:03 : HDL Language: VHDL
MIG: 17:12:03 : compInfo: false
MIG: 17:12:03 : Vivado Options xc7a100t fgg484 -1
MIG: 17:12:03 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:12:03 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:12:03 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:12:03 : I am in catch area
MIG: 17:12:03 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 17:12:16 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:12:16 : Component_Name: mig_7series_0
MIG: 17:12:16 : Moving mig_7series_0 ...
MIG: 17:12:16 : Moving mig_7series_0.vho ...
MIG: 17:12:16 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:14:41 : Running synthesis.xit
MIG: 17:14:41 : ################# RUNNING MIG BATCH ###################
MIG: 17:14:41 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 17:14:41 : synp_flow:  -- synthesis_mode: Other
MIG: 17:14:41 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:14:41 : vivado_mode: xpg_pa
MIG: 17:14:41 :  locked false  
MIG: 17:14:41 : HDL Language: VHDL
MIG: 17:14:41 : compInfo: false
MIG: 17:14:41 : Vivado Options xc7a100t fgg484 -1
MIG: 17:14:41 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:14:41 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:14:41 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:14:41 : I am in catch area
MIG: 17:14:41 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 17:14:54 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:14:54 : Component_Name: mig_7series_0
MIG: 17:14:54 : Moving mig_7series_0 ...
MIG: 17:14:54 : Moving mig_7series_0.vho ...
MIG: 17:14:54 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:14:55 : Running vhdl_synth_rpr.xit
MIG: 17:14:55 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:14:55 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 17:14:56 : Running simulation.xit
MIG: 17:14:56 : ################# RUNNING MIG BATCH ###################
MIG: 17:14:56 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 17:14:56 : synp_flow:  -- synthesis_mode: Other
MIG: 17:14:56 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:14:56 : vivado_mode: xpg_pa
MIG: 17:14:56 :  locked false  
MIG: 17:14:56 : HDL Language: VHDL
MIG: 17:14:56 : compInfo: false
MIG: 17:14:56 : Vivado Options xc7a100t fgg484 -1
MIG: 17:14:56 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:14:56 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:14:56 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:14:56 : I am in catch area
MIG: 17:14:56 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 17:15:09 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:15:09 : Component_Name: mig_7series_0
MIG: 17:15:09 : Moving mig_7series_0 ...
MIG: 17:15:09 : Moving mig_7series_0.vho ...
MIG: 17:15:09 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:15:09 : Running vhdl_sim_rpr.xit
MIG: 17:15:10 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:15:10 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 17:15:10 : Running implementation.xit
MIG: 17:15:10 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:15:10 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 18:00:19 : Running customizer.xit
MIG: 18:00:19 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 18:00:19 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0
MIG: 18:00:19 : synp_flow:  -- synthesis_mode: Other
MIG: 18:00:19 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/_tmp/
MIG: 18:00:19 : vivado_mode: xpg_pa
MIG: 18:00:19 :  locked false  
MIG: 18:00:19 : HDL Language: VHDL
MIG: 18:00:19 : compInfo: false
MIG: 18:00:19 : Vivado Options xc7a100t fgg484 -1
MIG: 18:00:19 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:00:19 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:00:19 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:00:19 : I am in catch area
MIG: 18:00:19 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 18:01:54 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 18:01:54 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 18:01:54 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/.Xil/Vivado-4972-L1/coregen/mig_7series_0/mig_a.prj
MIG: 18:01:54 : Component_Name: mig_7series_0
MIG: 18:01:54 : Moving mig_7series_0 ...
MIG: 18:01:54 : Moving mig_7series_0.vho ...
MIG: 18:01:54 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:01:54 : Sending back 0
MIG: 18:01:56 : xml_input_file: mig_a.prj
MIG: 18:01:56 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:01:56 : xml_input_file: mig_a.prj
MIG: 18:01:56 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:01:56 : In updateAllModelParams
MIG: 18:01:56 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:01:56 : IGN:         <InputClkFreq>100</InputClkFreq> <==>         <InputClkFreq>100</InputClkFreq> 
MIG: 18:01:56 : XGUI hdlLanguage: VHDL
MIG: 18:01:56 : xgui vivado_mode: xpg_pa
MIG: 18:01:56 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 18:01:56 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 18:01:56 : 
MIG: 18:01:56 : Inside fn mem: DDR3
MIG: 18:01:56 : Inside fn detect_uiclk: 100000000
MIG: 18:01:56 : cntrl:  memtype: DDR3
MIG: 18:01:56 : 
MIG: 18:01:56 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 18:01:56 : 
MIG: 18:01:56 : 
MIG: 18:01:56 : 
MIG: 18:01:56 : 
MIG: 18:01:56 :  polarity_value: 1
MIG: 18:01:56 : 
MIG: 18:01:56 : 
MIG: 18:01:56 : cntrl:  memtype: DDR3
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 18:01:56 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 18:01:56 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 18:01:56 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 18:01:56 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: ECC ==> OFF
MIG: 18:01:56 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 18:01:56 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 18:01:56 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 18:01:56 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 18:01:56 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 18:01:56 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 18:01:56 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 18:01:56 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 18:01:56 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 18:01:56 :  Invalid Param: DDR3_AL ==> "0"
MIG: 18:01:56 :  Invalid Param: DDR3_nAL ==> 0
MIG: 18:01:56 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 18:01:56 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 18:01:56 :  Invalid Param: DDR3_CL ==> 6
MIG: 18:01:56 :  Invalid Param: DDR3_CWL ==> 5
MIG: 18:01:56 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 18:01:56 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 18:01:56 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 18:01:56 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 18:01:56 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 10000
MIG: 18:01:56 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 8
MIG: 18:01:56 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 18:01:56 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 18:01:56 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 18:01:56 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 18:01:56 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 18:01:56 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 18:01:56 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 18:01:56 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 18:01:56 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 18:01:56 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 18:01:56 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 18:01:56 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 18:01:56 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 18:01:56 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 18:01:56 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 18:01:56 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 18:01:56 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 18:01:56 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 18:01:56 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 18:01:56 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 18:01:56 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 18:01:56 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 18:01:56 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 18:01:56 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 18:01:56 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 18:01:56 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 18:01:56 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 18:01:56 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 18:01:56 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 18:01:56 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 18:01:56 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 18:01:56 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 18:01:56 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 18:01:56 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 18:01:56 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 18:01:56 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 18:01:56 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 18:01:56 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 18:01:56 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 18:01:56 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 18:01:56 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 18:01:56 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 18:01:56 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 18:01:56 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 18:01:56 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 18:01:56 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 18:01:56 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 18:01:56 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 18:01:56 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 18:01:56 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 18:01:56 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 18:01:56 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 18:01:56 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 18:01:56 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 18:01:56 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 18:01:56 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 18:01:56 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 18:01:56 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 18:01:56 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 18:01:56 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 18:01:56 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 18:01:56 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 18:01:56 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 18:01:56 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 18:01:56 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 18:01:56 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 18:01:56 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 18:01:56 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 18:01:56 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 18:01:56 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 18:01:56 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 18:01:56 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 18:01:56 : 
MIG: 18:01:56 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 18:01:56 : 
MIG: 18:01:56 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 18:01:56 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 18:01:56 : 
MIG: 18:01:56 : 
MIG: 18:01:56 : 
MIG: 18:01:56 : Same Interface
MIG: 18:01:58 : ################# RUNNING MIG BATCH ###################
MIG: 18:01:59 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 18:01:59 : synp_flow:  -- synthesis_mode: Other
MIG: 18:01:59 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 18:01:59 : vivado_mode: xpg_pa
MIG: 18:01:59 :  locked false  
MIG: 18:01:59 : HDL Language: VHDL
MIG: 18:01:59 : compInfo: false
MIG: 18:01:59 : Vivado Options xc7a100t fgg484 -1
MIG: 18:01:59 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:01:59 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:01:59 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:01:59 : I am in catch area
MIG: 18:01:59 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 18:02:11 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001p/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:02:11 : Component_Name: mig_7series_0
MIG: 18:02:11 : Moving mig_7series_0 ...
MIG: 18:02:11 : Moving mig_7series_0.vho ...
MIG: 18:02:11 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:31:00 : xml_input_file: mig_a.prj
MIG: 18:31:00 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:31:00 : xml_input_file: mig_a.prj
MIG: 18:31:00 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 18:31:22 : Running customizer.xit
MIG: 18:31:22 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 18:31:22 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/.Xil/Vivado-5360-L1/coregen/mig_7series_0
MIG: 18:31:22 : synp_flow:  -- synthesis_mode: Other
MIG: 18:31:22 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/.Xil/Vivado-5360-L1/coregen/mig_7series_0/_tmp/
MIG: 18:31:22 : vivado_mode: xpg_pa
MIG: 18:31:22 :  locked false  
MIG: 18:31:22 : HDL Language: VHDL
MIG: 18:31:22 : compInfo: false
MIG: 18:31:22 : Vivado Options xc7a100t fgg484 -1
MIG: 18:31:23 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:31:23 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:31:23 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:31:23 : I am in catch area
MIG: 18:31:23 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/.Xil/Vivado-5360-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/.Xil/Vivado-5360-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 18:33:34 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 18:33:34 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 18:33:34 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/.Xil/Vivado-5360-L1/coregen/mig_7series_0/mig_b.prj
MIG: 18:33:34 : Component_Name: mig_7series_0
MIG: 18:33:34 : Moving mig_7series_0 ...
MIG: 18:33:34 : Moving mig_7series_0.vho ...
MIG: 18:33:34 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:33:34 : Sending back 0
MIG: 18:33:36 : xml_input_file: mig_b.prj
MIG: 18:33:36 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:33:36 : xml_input_file: mig_b.prj
MIG: 18:33:36 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:33:36 : In updateAllModelParams
MIG: 18:33:36 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:33:36 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 18:33:36 : XGUI hdlLanguage: VHDL
MIG: 18:33:36 : xgui vivado_mode: xpg_pa
MIG: 18:33:36 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 18:33:36 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 18:33:36 : 
MIG: 18:33:36 : Inside fn mem: DDR3
MIG: 18:33:36 : Inside fn detect_uiclk: 76804916
MIG: 18:33:36 : cntrl:  memtype: DDR3
MIG: 18:33:36 : 614
MIG: 18:33:36 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 614 
MIG: 18:33:36 : 
MIG: 18:33:36 : 
MIG: 18:33:36 : 76804916
MIG: 18:33:36 : 
MIG: 18:33:36 :  polarity_value: 1
MIG: 18:33:36 : 
MIG: 18:33:36 : 
MIG: 18:33:36 : cntrl:  memtype: DDR3
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 18:33:36 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 18:33:36 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 18:33:36 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 18:33:36 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: ECC ==> OFF
MIG: 18:33:36 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 18:33:36 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 18:33:36 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 18:33:36 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 18:33:36 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 18:33:36 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 18:33:36 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 18:33:36 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 18:33:36 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 18:33:36 :  Invalid Param: DDR3_AL ==> "0"
MIG: 18:33:36 :  Invalid Param: DDR3_nAL ==> 0
MIG: 18:33:36 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 18:33:36 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 18:33:36 :  Invalid Param: DDR3_CL ==> 5
MIG: 18:33:36 :  Invalid Param: DDR3_CWL ==> 5
MIG: 18:33:36 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 18:33:36 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 18:33:36 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 18:33:36 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 18:33:36 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 13020
MIG: 18:33:36 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 16
MIG: 18:33:36 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 18:33:36 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 18:33:36 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 18:33:36 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 18:33:36 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 18:33:36 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 18:33:36 :  Invalid Param: DDR3_MMCM_VCO ==> 614
MIG: 18:33:36 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 18:33:36 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 18:33:36 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 18:33:36 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 18:33:36 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 18:33:36 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 18:33:36 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 18:33:36 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 18:33:36 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 18:33:36 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 18:33:36 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 18:33:36 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 18:33:36 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 18:33:36 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 18:33:36 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 18:33:36 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 18:33:36 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 18:33:36 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 18:33:36 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 18:33:36 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 18:33:36 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 18:33:36 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 18:33:36 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 18:33:36 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 18:33:36 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 18:33:36 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 18:33:36 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 18:33:36 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 18:33:36 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 18:33:36 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 18:33:36 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 18:33:36 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 18:33:36 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 18:33:36 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 18:33:36 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 18:33:36 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 18:33:36 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 18:33:36 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 18:33:36 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 18:33:36 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 18:33:36 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 18:33:36 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 18:33:36 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 18:33:36 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 18:33:36 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 18:33:36 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 18:33:36 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 18:33:36 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 18:33:36 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 18:33:36 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 18:33:36 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 18:33:36 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 18:33:36 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 18:33:36 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 18:33:36 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 18:33:36 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 18:33:36 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 18:33:36 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 18:33:36 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 18:33:36 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 18:33:36 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 18:33:36 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 18:33:36 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 18:33:36 :  Invalid Param: DDR3_tCK ==> 3255
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 18:33:36 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 18:33:36 : 
MIG: 18:33:36 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 18:33:36 : 
MIG: 18:33:36 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 18:33:36 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 18:33:36 : 
MIG: 18:33:36 : 
MIG: 18:33:36 : 
MIG: 18:33:36 : Same Interface
MIG: 18:33:38 : ################# RUNNING MIG BATCH ###################
MIG: 18:33:38 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 18:33:38 : synp_flow:  -- synthesis_mode: Other
MIG: 18:33:38 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 18:33:38 : vivado_mode: xpg_pa
MIG: 18:33:38 :  locked false  
MIG: 18:33:38 : HDL Language: VHDL
MIG: 18:33:38 : compInfo: false
MIG: 18:33:38 : Vivado Options xc7a100t fgg484 -1
MIG: 18:33:38 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:33:38 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:33:38 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:33:38 : I am in catch area
MIG: 18:33:38 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 18:33:50 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:33:50 : Component_Name: mig_7series_0
MIG: 18:33:50 : Moving mig_7series_0 ...
MIG: 18:33:50 : Moving mig_7series_0.vho ...
MIG: 18:33:50 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:37:13 : Running synthesis.xit
MIG: 18:37:13 : ################# RUNNING MIG BATCH ###################
MIG: 18:37:13 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 18:37:13 : synp_flow:  -- synthesis_mode: Other
MIG: 18:37:13 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 18:37:13 : vivado_mode: xpg_pa
MIG: 18:37:13 :  locked false  
MIG: 18:37:13 : HDL Language: VHDL
MIG: 18:37:13 : compInfo: false
MIG: 18:37:13 : Vivado Options xc7a100t fgg484 -1
MIG: 18:37:13 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:37:13 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:37:13 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:37:13 : I am in catch area
MIG: 18:37:13 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 18:37:26 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:37:26 : Component_Name: mig_7series_0
MIG: 18:37:26 : Moving mig_7series_0 ...
MIG: 18:37:26 : Moving mig_7series_0.vho ...
MIG: 18:37:26 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:37:26 : Running vhdl_synth_rpr.xit
MIG: 18:37:27 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:37:27 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 18:37:27 : Running simulation.xit
MIG: 18:37:27 : ################# RUNNING MIG BATCH ###################
MIG: 18:37:27 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 18:37:27 : synp_flow:  -- synthesis_mode: Other
MIG: 18:37:27 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 18:37:27 : vivado_mode: xpg_pa
MIG: 18:37:27 :  locked false  
MIG: 18:37:27 : HDL Language: VHDL
MIG: 18:37:27 : compInfo: false
MIG: 18:37:27 : Vivado Options xc7a100t fgg484 -1
MIG: 18:37:27 : 1: xc7a100t 2: fgg484 3: -1
MIG: 18:37:27 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 18:37:27 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 18:37:27 : I am in catch area
MIG: 18:37:27 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 18:37:40 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 18:37:40 : Component_Name: mig_7series_0
MIG: 18:37:40 : Moving mig_7series_0 ...
MIG: 18:37:40 : Moving mig_7series_0.vho ...
MIG: 18:37:40 : Moving mig_7series_0_xmdf.tcl ...
MIG: 18:37:40 : Running vhdl_sim_rpr.xit
MIG: 18:37:40 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:37:40 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 18:37:41 : Running implementation.xit
MIG: 18:37:41 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 18:37:41 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 08:56:28 : xml_input_file: mig_b.prj
MIG: 08:56:28 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 08:56:28 : xml_input_file: mig_b.prj
MIG: 08:56:28 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 08:56:49 : Running customizer.xit
MIG: 08:56:49 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 08:56:49 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0
MIG: 08:56:49 : synp_flow:  -- synthesis_mode: Other
MIG: 08:56:49 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/_tmp/
MIG: 08:56:49 : vivado_mode: xpg_pa
MIG: 08:56:49 :  locked false  
MIG: 08:56:49 : HDL Language: VHDL
MIG: 08:56:49 : compInfo: false
MIG: 08:56:49 : Vivado Options xc7a100t fgg484 -1
MIG: 08:56:49 : 1: xc7a100t 2: fgg484 3: -1
MIG: 08:56:49 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 08:56:49 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 08:56:49 : I am in catch area
MIG: 08:56:49 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 08:58:04 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 08:58:04 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 08:58:04 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/mig_a.prj
MIG: 08:58:04 : Component_Name: mig_7series_0
MIG: 08:58:04 : Moving mig_7series_0 ...
MIG: 08:58:04 : Moving mig_7series_0.vho ...
MIG: 08:58:04 : Moving mig_7series_0_xmdf.tcl ...
MIG: 08:58:04 : Sending back 0
MIG: 08:58:06 : xml_input_file: mig_a.prj
MIG: 08:58:06 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 08:58:06 : xml_input_file: mig_a.prj
MIG: 08:58:06 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 08:58:06 : In updateAllModelParams
MIG: 08:58:06 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 08:58:06 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 08:58:06 : XGUI hdlLanguage: VHDL
MIG: 08:58:06 : xgui vivado_mode: xpg_pa
MIG: 08:58:06 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 08:58:06 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 08:58:06 : 
MIG: 08:58:06 : Inside fn mem: DDR3
MIG: 08:58:06 : Inside fn detect_uiclk: 76804916
MIG: 08:58:06 : cntrl:  memtype: DDR3
MIG: 08:58:06 : 
MIG: 08:58:06 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 614 
MIG: 08:58:06 : 
MIG: 08:58:06 : 
MIG: 08:58:06 : 
MIG: 08:58:06 : 
MIG: 08:58:06 :  polarity_value: 1
MIG: 08:58:06 : 
MIG: 08:58:06 : 
MIG: 08:58:06 : cntrl:  memtype: DDR3
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 08:58:06 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 08:58:06 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 08:58:06 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 08:58:06 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 08:58:06 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: ECC ==> OFF
MIG: 08:58:06 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 08:58:06 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 08:58:06 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 08:58:06 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 08:58:06 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 08:58:06 : 14
MIG: 08:58:06 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 08:58:06 : 28
MIG: 08:58:06 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 08:58:06 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 08:58:06 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 08:58:06 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 08:58:06 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 08:58:06 :  Invalid Param: DDR3_AL ==> "0"
MIG: 08:58:06 :  Invalid Param: DDR3_nAL ==> 0
MIG: 08:58:06 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 08:58:06 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 08:58:06 :  Invalid Param: DDR3_CL ==> 5
MIG: 08:58:06 :  Invalid Param: DDR3_CWL ==> 5
MIG: 08:58:06 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 08:58:06 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 08:58:06 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 08:58:06 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 08:58:06 : 
MIG: 08:58:06 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 08:58:06 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 08:58:06 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 08:58:06 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 13020
MIG: 08:58:06 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 16
MIG: 08:58:06 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 08:58:06 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 08:58:06 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 08:58:06 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 08:58:06 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 08:58:06 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 08:58:06 :  Invalid Param: DDR3_MMCM_VCO ==> 614
MIG: 08:58:06 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 08:58:06 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 08:58:06 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 08:58:06 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 08:58:06 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 08:58:06 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 08:58:06 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 08:58:06 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 08:58:06 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 08:58:06 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 08:58:06 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 08:58:06 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 08:58:06 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 08:58:06 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 08:58:06 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 08:58:06 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 08:58:06 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 08:58:06 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 08:58:06 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 08:58:06 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 08:58:06 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 08:58:06 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 08:58:06 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 08:58:06 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 08:58:06 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 08:58:06 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 08:58:06 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 08:58:06 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 08:58:06 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 08:58:06 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 08:58:06 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 08:58:06 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 08:58:06 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 08:58:06 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 08:58:06 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 08:58:06 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 08:58:06 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 08:58:07 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 08:58:07 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 08:58:07 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 08:58:07 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 08:58:07 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 08:58:07 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 08:58:07 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 08:58:07 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 08:58:07 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 08:58:07 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 08:58:07 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 08:58:07 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 08:58:07 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 08:58:07 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 08:58:07 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 08:58:07 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 08:58:07 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 08:58:07 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 08:58:07 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 08:58:07 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 08:58:07 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 08:58:07 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 08:58:07 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 08:58:07 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 08:58:07 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 08:58:07 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 08:58:07 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 08:58:07 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 08:58:07 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 08:58:07 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 08:58:07 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 08:58:07 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 08:58:07 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 08:58:07 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 08:58:07 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 08:58:07 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 08:58:07 :  Invalid Param: DDR3_tCK ==> 3255
MIG: 08:58:07 : 
MIG: 08:58:07 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 08:58:07 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 08:58:07 : 
MIG: 08:58:07 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 08:58:07 : 
MIG: 08:58:07 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 08:58:07 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 08:58:07 : 
MIG: 08:58:07 : 
MIG: 08:58:07 : 
MIG: 08:58:07 : Same Interface
MIG: 08:58:09 : ################# RUNNING MIG BATCH ###################
MIG: 08:58:09 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 08:58:09 : synp_flow:  -- synthesis_mode: Other
MIG: 08:58:09 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 08:58:09 : vivado_mode: xpg_pa
MIG: 08:58:09 :  locked false  
MIG: 08:58:09 : HDL Language: VHDL
MIG: 08:58:09 : compInfo: false
MIG: 08:58:09 : Vivado Options xc7a100t fgg484 -1
MIG: 08:58:09 : 1: xc7a100t 2: fgg484 3: -1
MIG: 08:58:09 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 08:58:09 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 08:58:09 : I am in catch area
MIG: 08:58:09 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 08:58:21 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 08:58:21 : Component_Name: mig_7series_0
MIG: 08:58:21 : Moving mig_7series_0 ...
MIG: 08:58:21 : Moving mig_7series_0.vho ...
MIG: 08:58:21 : Moving mig_7series_0_xmdf.tcl ...
MIG: 08:58:28 : Running synthesis.xit
MIG: 08:58:29 : ################# RUNNING MIG BATCH ###################
MIG: 08:58:29 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 08:58:29 : synp_flow:  -- synthesis_mode: Other
MIG: 08:58:29 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 08:58:29 : vivado_mode: xpg_pa
MIG: 08:58:29 :  locked false  
MIG: 08:58:29 : HDL Language: VHDL
MIG: 08:58:29 : compInfo: false
MIG: 08:58:29 : Vivado Options xc7a100t fgg484 -1
MIG: 08:58:29 : 1: xc7a100t 2: fgg484 3: -1
MIG: 08:58:29 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 08:58:29 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 08:58:29 : I am in catch area
MIG: 08:58:29 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 08:58:40 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 08:58:41 : Component_Name: mig_7series_0
MIG: 08:58:41 : Moving mig_7series_0 ...
MIG: 08:58:41 : Moving mig_7series_0.vho ...
MIG: 08:58:41 : Moving mig_7series_0_xmdf.tcl ...
MIG: 08:58:41 : Running vhdl_synth_rpr.xit
MIG: 08:58:41 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 08:58:41 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 08:58:42 : Running simulation.xit
MIG: 08:58:42 : ################# RUNNING MIG BATCH ###################
MIG: 08:58:42 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 08:58:42 : synp_flow:  -- synthesis_mode: Other
MIG: 08:58:42 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 08:58:42 : vivado_mode: xpg_pa
MIG: 08:58:42 :  locked false  
MIG: 08:58:42 : HDL Language: VHDL
MIG: 08:58:42 : compInfo: false
MIG: 08:58:42 : Vivado Options xc7a100t fgg484 -1
MIG: 08:58:42 : 1: xc7a100t 2: fgg484 3: -1
MIG: 08:58:42 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 08:58:42 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 08:58:42 : I am in catch area
MIG: 08:58:42 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 08:58:54 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 08:58:54 : Component_Name: mig_7series_0
MIG: 08:58:54 : Moving mig_7series_0 ...
MIG: 08:58:54 : Moving mig_7series_0.vho ...
MIG: 08:58:54 : Moving mig_7series_0_xmdf.tcl ...
MIG: 08:58:55 : Running vhdl_sim_rpr.xit
MIG: 08:58:55 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 08:58:55 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 08:58:55 : Running implementation.xit
MIG: 08:58:56 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 08:58:56 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 10:55:30 : Running customizer.xit
MIG: 10:55:30 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 10:55:30 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0
MIG: 10:55:30 : synp_flow:  -- synthesis_mode: Other
MIG: 10:55:30 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/_tmp/
MIG: 10:55:30 : vivado_mode: xpg_pa
MIG: 10:55:30 :  locked false  
MIG: 10:55:30 : HDL Language: VHDL
MIG: 10:55:30 : compInfo: false
MIG: 10:55:30 : Vivado Options xc7a100t fgg484 -1
MIG: 10:55:30 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:55:30 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:55:30 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:55:30 : I am in catch area
MIG: 10:55:30 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 11:08:17 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 11:08:17 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 11:08:17 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2348-L1/coregen/mig_7series_0/mig_b.prj
MIG: 11:08:17 : Component_Name: mig_7series_0
MIG: 11:08:17 : Moving mig_7series_0 ...
MIG: 11:08:17 : Moving mig_7series_0.vho ...
MIG: 11:08:17 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:08:17 : Sending back 0
MIG: 11:08:19 : xml_input_file: mig_b.prj
MIG: 11:08:19 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:08:19 : xml_input_file: mig_b.prj
MIG: 11:08:19 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:08:19 : In updateAllModelParams
MIG: 11:08:20 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:08:20 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 11:08:20 : XGUI hdlLanguage: VHDL
MIG: 11:08:20 : xgui vivado_mode: xpg_pa
MIG: 11:08:20 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 11:08:20 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 11:08:20 : 
MIG: 11:08:20 : Inside fn mem: DDR3
MIG: 11:08:20 : Inside fn detect_uiclk: 76804916
MIG: 11:08:20 : cntrl:  memtype: DDR3
MIG: 11:08:20 : 
MIG: 11:08:20 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 614 
MIG: 11:08:20 : 
MIG: 11:08:20 : 
MIG: 11:08:20 : 
MIG: 11:08:20 : 
MIG: 11:08:20 :  polarity_value: 1
MIG: 11:08:20 : 
MIG: 11:08:20 : 
MIG: 11:08:20 : cntrl:  memtype: DDR3
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 11:08:20 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 11:08:20 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 11:08:20 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 11:08:20 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: ECC ==> OFF
MIG: 11:08:20 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 11:08:20 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 11:08:20 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 11:08:20 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 11:08:20 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 11:08:20 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 11:08:20 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 11:08:20 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 11:08:20 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 11:08:20 :  Invalid Param: DDR3_AL ==> "0"
MIG: 11:08:20 :  Invalid Param: DDR3_nAL ==> 0
MIG: 11:08:20 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 11:08:20 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 11:08:20 :  Invalid Param: DDR3_CL ==> 5
MIG: 11:08:20 :  Invalid Param: DDR3_CWL ==> 5
MIG: 11:08:20 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 11:08:20 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 11:08:20 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 11:08:20 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 11:08:20 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 13020
MIG: 11:08:20 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 16
MIG: 11:08:20 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 11:08:20 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 11:08:20 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 11:08:20 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 11:08:20 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 11:08:20 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 11:08:20 :  Invalid Param: DDR3_MMCM_VCO ==> 614
MIG: 11:08:20 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 11:08:20 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 11:08:20 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 11:08:20 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 11:08:20 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 11:08:20 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 11:08:20 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 11:08:20 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 11:08:20 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 11:08:20 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 11:08:20 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 11:08:20 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 11:08:20 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 11:08:20 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 11:08:20 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 11:08:20 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 11:08:20 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 11:08:20 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 11:08:20 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 11:08:20 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 11:08:20 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 11:08:20 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 11:08:20 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 11:08:20 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 11:08:20 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 11:08:20 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 11:08:20 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 11:08:20 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 11:08:20 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 11:08:20 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 11:08:20 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 11:08:20 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 11:08:20 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 11:08:20 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 11:08:20 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 11:08:20 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 11:08:20 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 11:08:20 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 11:08:20 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 11:08:20 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 11:08:20 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 11:08:20 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 11:08:20 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 11:08:20 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 11:08:20 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 11:08:20 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 11:08:20 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 11:08:20 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 11:08:20 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 11:08:20 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 11:08:20 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 11:08:20 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 11:08:20 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 11:08:20 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 11:08:20 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 11:08:20 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 11:08:20 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 11:08:20 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 11:08:20 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 11:08:20 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 11:08:20 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 11:08:20 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 11:08:20 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 11:08:20 :  Invalid Param: DDR3_tCK ==> 3255
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 11:08:20 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 11:08:20 : 
MIG: 11:08:20 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 11:08:20 : 
MIG: 11:08:20 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 11:08:20 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 11:08:20 : 
MIG: 11:08:20 : 
MIG: 11:08:20 : 
MIG: 11:08:20 : Same Interface
MIG: 11:08:22 : ################# RUNNING MIG BATCH ###################
MIG: 11:08:23 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:08:23 : synp_flow:  -- synthesis_mode: Other
MIG: 11:08:23 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:08:23 : vivado_mode: xpg_pa
MIG: 11:08:23 :  locked false  
MIG: 11:08:23 : HDL Language: VHDL
MIG: 11:08:23 : compInfo: false
MIG: 11:08:23 : Vivado Options xc7a100t fgg484 -1
MIG: 11:08:23 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:08:23 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:08:23 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:08:23 : I am in catch area
MIG: 11:08:23 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 11:08:36 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:08:36 : Component_Name: mig_7series_0
MIG: 11:08:36 : Moving mig_7series_0 ...
MIG: 11:08:36 : Moving mig_7series_0.vho ...
MIG: 11:08:36 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:10:03 : Running synthesis.xit
MIG: 11:10:03 : ################# RUNNING MIG BATCH ###################
MIG: 11:10:03 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:10:03 : synp_flow:  -- synthesis_mode: Other
MIG: 11:10:03 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:10:03 : vivado_mode: xpg_pa
MIG: 11:10:03 :  locked false  
MIG: 11:10:03 : HDL Language: VHDL
MIG: 11:10:03 : compInfo: false
MIG: 11:10:03 : Vivado Options xc7a100t fgg484 -1
MIG: 11:10:03 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:10:03 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:10:03 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:10:03 : I am in catch area
MIG: 11:10:03 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 11:10:18 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:10:18 : Component_Name: mig_7series_0
MIG: 11:10:18 : Moving mig_7series_0 ...
MIG: 11:10:18 : Moving mig_7series_0.vho ...
MIG: 11:10:18 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:10:19 : Running vhdl_synth_rpr.xit
MIG: 11:10:19 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:10:19 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 11:10:20 : Running simulation.xit
MIG: 11:10:20 : ################# RUNNING MIG BATCH ###################
MIG: 11:10:20 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:10:20 : synp_flow:  -- synthesis_mode: Other
MIG: 11:10:20 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:10:20 : vivado_mode: xpg_pa
MIG: 11:10:20 :  locked false  
MIG: 11:10:20 : HDL Language: VHDL
MIG: 11:10:20 : compInfo: false
MIG: 11:10:20 : Vivado Options xc7a100t fgg484 -1
MIG: 11:10:20 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:10:20 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:10:20 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:10:20 : I am in catch area
MIG: 11:10:20 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 11:10:35 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_001q/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:10:35 : Component_Name: mig_7series_0
MIG: 11:10:35 : Moving mig_7series_0 ...
MIG: 11:10:35 : Moving mig_7series_0.vho ...
MIG: 11:10:35 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:10:36 : Running vhdl_sim_rpr.xit
MIG: 11:10:36 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:10:36 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 11:10:37 : Running implementation.xit
MIG: 11:10:37 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:10:37 : IGN:         <InputClkFreq>76.804</InputClkFreq> <==>         <InputClkFreq>76.804</InputClkFreq> 
MIG: 10:45:49 : xml_input_file: mig_b.prj
MIG: 10:45:50 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:45:50 : xml_input_file: mig_b.prj
MIG: 10:45:50 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:05:13 : Running customizer.xit
MIG: 11:05:13 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 11:05:13 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-316-L1/coregen/mig_7series_0
MIG: 11:05:13 : synp_flow:  -- synthesis_mode: Other
MIG: 11:05:13 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-316-L1/coregen/mig_7series_0/_tmp/
MIG: 11:05:13 : vivado_mode: xpg_pa
MIG: 11:05:13 :  locked false  
MIG: 11:05:13 : HDL Language: VHDL
MIG: 11:05:13 : compInfo: false
MIG: 11:05:13 : Vivado Options xc7a100t fgg484 -1
MIG: 11:05:13 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:05:13 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:05:13 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:05:13 : I am in catch area
MIG: 11:05:13 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-316-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-316-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 11:08:01 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 11:08:01 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 11:08:02 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-316-L1/coregen/mig_7series_0/mig_a.prj
MIG: 11:08:02 : Component_Name: mig_7series_0
MIG: 11:08:02 : Moving mig_7series_0 ...
MIG: 11:08:02 : Moving mig_7series_0.vho ...
MIG: 11:08:02 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:08:02 : Sending back 0
MIG: 11:08:03 : xml_input_file: mig_a.prj
MIG: 11:08:03 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:08:03 : xml_input_file: mig_a.prj
MIG: 11:08:03 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:08:03 : In updateAllModelParams
MIG: 11:08:03 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:08:03 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:08:03 : XGUI hdlLanguage: VHDL
MIG: 11:08:03 : xgui vivado_mode: xpg_pa
MIG: 11:08:03 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 11:08:04 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 11:08:04 : 
MIG: 11:08:04 : Inside fn mem: DDR3
MIG: 11:08:04 : Inside fn detect_uiclk: 83333334
MIG: 11:08:04 : cntrl:  memtype: DDR3
MIG: 11:08:04 : 666
MIG: 11:08:04 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 11:08:04 : 
MIG: 11:08:04 : 
MIG: 11:08:04 : 83333334
MIG: 11:08:04 : 
MIG: 11:08:04 :  polarity_value: 1
MIG: 11:08:04 : 
MIG: 11:08:04 : 
MIG: 11:08:04 : cntrl:  memtype: DDR3
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 11:08:04 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 11:08:04 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 11:08:04 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 11:08:04 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: ECC ==> OFF
MIG: 11:08:04 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 11:08:04 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 11:08:04 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 11:08:04 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 11:08:04 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 11:08:04 : 16
MIG: 11:08:04 :  Valid Param: DDR3_ROW_WIDTH ==> 16
MIG: 11:08:04 : 30
MIG: 11:08:04 :  Valid Param: DDR3_ADDR_WIDTH ==> 30
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 11:08:04 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 11:08:04 :  Invalid Param: DDR3_MEM_DENSITY ==> "4Gb"
MIG: 11:08:04 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 11:08:04 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 11:08:04 :  Invalid Param: DDR3_AL ==> "0"
MIG: 11:08:04 :  Invalid Param: DDR3_nAL ==> 0
MIG: 11:08:04 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 11:08:04 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 11:08:04 :  Invalid Param: DDR3_CL ==> 5
MIG: 11:08:04 :  Invalid Param: DDR3_CWL ==> 5
MIG: 11:08:04 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 11:08:04 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 11:08:04 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 11:08:04 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 11:08:04 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 11:08:04 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 11:08:04 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 11:08:04 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 11:08:04 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 11:08:04 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 11:08:04 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 11:08:04 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 11:08:04 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 11:08:04 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 11:08:04 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 11:08:04 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 11:08:04 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 11:08:04 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 11:08:04 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 11:08:04 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 11:08:04 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 11:08:04 :  Invalid Param: DDR3_tRFC ==> 260000
MIG: 11:08:04 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 11:08:04 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 11:08:04 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 11:08:04 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 11:08:04 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 11:08:04 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 11:08:04 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 11:08:04 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 11:08:04 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 11:08:04 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 11:08:04 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 11:08:04 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 11:08:04 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 11:08:04 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"C3EFFFE2A2FF"
MIG: 11:08:04 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 11:08:04 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 11:08:04 :  Invalid Param: DDR3_ADDR_MAP ==> X"11913B13A13513413313213112912812712612B12A125124"
MIG: 11:08:04 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 11:08:04 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 11:08:04 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 11:08:04 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 11:08:04 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 11:08:04 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 11:08:04 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 11:08:04 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 11:08:04 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 11:08:04 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 11:08:04 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 11:08:04 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 11:08:04 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 11:08:04 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 11:08:04 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 11:08:04 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 11:08:04 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 11:08:04 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 11:08:04 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 11:08:04 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 11:08:04 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 11:08:04 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 11:08:04 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 11:08:04 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 11:08:04 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 11:08:04 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 11:08:04 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 11:08:04 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 11:08:04 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 11:08:04 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 11:08:04 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 11:08:04 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 11:08:04 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 11:08:04 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 11:08:04 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 11:08:04 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 11:08:04 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 11:08:04 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 11:08:04 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 11:08:04 : 
MIG: 11:08:04 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 11:08:04 : 
MIG: 11:08:04 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 11:08:04 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 11:08:04 : 
MIG: 11:08:04 : 
MIG: 11:08:04 : 
MIG: 11:08:04 : Same Interface
MIG: 11:08:06 : ################# RUNNING MIG BATCH ###################
MIG: 11:08:06 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:08:06 : synp_flow:  -- synthesis_mode: Other
MIG: 11:08:06 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:08:06 : vivado_mode: xpg_pa
MIG: 11:08:06 :  locked false  
MIG: 11:08:06 : HDL Language: VHDL
MIG: 11:08:06 : compInfo: false
MIG: 11:08:06 : Vivado Options xc7a100t fgg484 -1
MIG: 11:08:06 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:08:06 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:08:06 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:08:06 : I am in catch area
MIG: 11:08:06 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 11:08:18 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:08:18 : Component_Name: mig_7series_0
MIG: 11:08:18 : Moving mig_7series_0 ...
MIG: 11:08:18 : Moving mig_7series_0.vho ...
MIG: 11:08:18 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:08:31 : Running synthesis.xit
MIG: 11:08:31 : ################# RUNNING MIG BATCH ###################
MIG: 11:08:31 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:08:31 : synp_flow:  -- synthesis_mode: Other
MIG: 11:08:31 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:08:31 : vivado_mode: xpg_pa
MIG: 11:08:31 :  locked false  
MIG: 11:08:31 : HDL Language: VHDL
MIG: 11:08:31 : compInfo: false
MIG: 11:08:31 : Vivado Options xc7a100t fgg484 -1
MIG: 11:08:31 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:08:31 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:08:31 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:08:31 : I am in catch area
MIG: 11:08:31 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 11:08:43 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:08:43 : Component_Name: mig_7series_0
MIG: 11:08:43 : Moving mig_7series_0 ...
MIG: 11:08:43 : Moving mig_7series_0.vho ...
MIG: 11:08:43 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:08:44 : Running vhdl_synth_rpr.xit
MIG: 11:08:44 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:08:44 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:08:44 : Running simulation.xit
MIG: 11:08:45 : ################# RUNNING MIG BATCH ###################
MIG: 11:08:45 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:08:45 : synp_flow:  -- synthesis_mode: Other
MIG: 11:08:45 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:08:45 : vivado_mode: xpg_pa
MIG: 11:08:45 :  locked false  
MIG: 11:08:45 : HDL Language: VHDL
MIG: 11:08:45 : compInfo: false
MIG: 11:08:45 : Vivado Options xc7a100t fgg484 -1
MIG: 11:08:45 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:08:45 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:08:45 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:08:45 : I am in catch area
MIG: 11:08:45 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 11:08:56 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:08:56 : Component_Name: mig_7series_0
MIG: 11:08:56 : Moving mig_7series_0 ...
MIG: 11:08:57 : Moving mig_7series_0.vho ...
MIG: 11:08:57 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:08:57 : Running vhdl_sim_rpr.xit
MIG: 11:08:57 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:08:57 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:08:58 : Running implementation.xit
MIG: 11:08:58 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:08:58 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:30:37 : xml_input_file: mig_a.prj
MIG: 11:30:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:30:37 : xml_input_file: mig_a.prj
MIG: 11:30:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 14:22:11 : Running customizer.xit
MIG: 14:22:11 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 14:22:11 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/.Xil/Vivado-4176-L1/coregen/mig_7series_0
MIG: 14:22:11 : synp_flow:  -- synthesis_mode: Other
MIG: 14:22:11 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/.Xil/Vivado-4176-L1/coregen/mig_7series_0/_tmp/
MIG: 14:22:11 : vivado_mode: xpg_pa
MIG: 14:22:11 :  locked false  
MIG: 14:22:11 : HDL Language: VHDL
MIG: 14:22:11 : compInfo: false
MIG: 14:22:11 : Vivado Options xc7a100t fgg484 -1
MIG: 14:22:11 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:22:11 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:22:11 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:22:11 : I am in catch area
MIG: 14:22:11 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/.Xil/Vivado-4176-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/.Xil/Vivado-4176-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 14:27:49 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 14:27:49 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 14:27:49 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/.Xil/Vivado-4176-L1/coregen/mig_7series_0/mig_b.prj
MIG: 14:27:49 : Component_Name: mig_7series_0
MIG: 14:27:49 : Moving mig_7series_0 ...
MIG: 14:27:49 : Moving mig_7series_0.vho ...
MIG: 14:27:49 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:27:49 : Sending back 0
MIG: 14:27:51 : xml_input_file: mig_b.prj
MIG: 14:27:51 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:27:51 : xml_input_file: mig_b.prj
MIG: 14:27:51 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:27:51 : In updateAllModelParams
MIG: 14:27:51 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:27:51 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 14:27:51 : XGUI hdlLanguage: VHDL
MIG: 14:27:51 : xgui vivado_mode: xpg_pa
MIG: 14:27:51 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 14:27:51 : Reading C:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 14:27:51 : 
MIG: 14:27:51 : Inside fn mem: DDR3
MIG: 14:27:51 : Inside fn detect_uiclk: 83333334
MIG: 14:27:51 : cntrl:  memtype: DDR3
MIG: 14:27:51 : 
MIG: 14:27:51 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 14:27:51 : 
MIG: 14:27:51 : 
MIG: 14:27:51 : 
MIG: 14:27:51 : 
MIG: 14:27:51 :  polarity_value: 1
MIG: 14:27:51 : 
MIG: 14:27:51 : 
MIG: 14:27:51 : cntrl:  memtype: DDR3
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 14:27:51 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 14:27:51 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 14:27:51 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 14:27:51 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: ECC ==> OFF
MIG: 14:27:51 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 14:27:51 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 14:27:51 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 14:27:51 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 14:27:51 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 14:27:51 : 14
MIG: 14:27:51 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 14:27:51 : 28
MIG: 14:27:51 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 14:27:51 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 14:27:51 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 14:27:51 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 14:27:51 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 14:27:51 :  Invalid Param: DDR3_AL ==> "0"
MIG: 14:27:51 :  Invalid Param: DDR3_nAL ==> 0
MIG: 14:27:51 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 14:27:51 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 14:27:51 :  Invalid Param: DDR3_CL ==> 5
MIG: 14:27:51 :  Invalid Param: DDR3_CWL ==> 5
MIG: 14:27:51 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 14:27:51 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 14:27:51 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 14:27:51 : 
MIG: 14:27:51 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 14:27:51 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 14:27:51 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 14:27:51 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 14:27:51 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 14:27:51 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 14:27:51 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 14:27:51 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 14:27:51 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 14:27:51 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 14:27:51 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 14:27:51 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 14:27:51 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 14:27:51 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 14:27:51 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 14:27:51 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 14:27:51 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 14:27:51 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 14:27:51 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 14:27:51 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 14:27:51 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 14:27:51 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 14:27:51 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 14:27:51 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 14:27:51 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 14:27:51 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 14:27:51 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 14:27:51 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 14:27:51 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 14:27:51 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 14:27:51 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 14:27:51 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 14:27:51 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 14:27:51 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 14:27:51 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 14:27:51 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 14:27:51 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 14:27:51 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 14:27:51 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 14:27:51 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 14:27:51 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 14:27:51 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 14:27:51 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 14:27:51 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 14:27:51 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 14:27:51 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 14:27:51 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 14:27:51 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 14:27:51 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 14:27:51 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 14:27:51 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 14:27:51 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 14:27:51 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 14:27:51 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 14:27:51 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 14:27:51 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 14:27:51 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 14:27:51 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 14:27:51 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 14:27:51 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 14:27:51 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 14:27:51 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 14:27:51 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 14:27:51 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 14:27:51 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 14:27:51 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 14:27:51 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 14:27:52 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 14:27:52 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 14:27:52 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 14:27:52 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 14:27:52 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 14:27:52 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 14:27:52 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 14:27:52 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 14:27:52 : 
MIG: 14:27:52 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 14:27:52 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 14:27:52 : 
MIG: 14:27:52 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 14:27:52 : 
MIG: 14:27:52 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 14:27:52 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 14:27:52 : 
MIG: 14:27:52 : 
MIG: 14:27:52 : 
MIG: 14:27:52 : Same Interface
MIG: 14:27:54 : ################# RUNNING MIG BATCH ###################
MIG: 14:27:54 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 14:27:54 : synp_flow:  -- synthesis_mode: Other
MIG: 14:27:54 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 14:27:54 : vivado_mode: xpg_pa
MIG: 14:27:54 :  locked false  
MIG: 14:27:54 : HDL Language: VHDL
MIG: 14:27:54 : compInfo: false
MIG: 14:27:54 : Vivado Options xc7a100t fgg484 -1
MIG: 14:27:54 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:27:54 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:27:54 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:27:54 : I am in catch area
MIG: 14:27:54 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 14:28:06 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:28:06 : Component_Name: mig_7series_0
MIG: 14:28:06 : Moving mig_7series_0 ...
MIG: 14:28:06 : Moving mig_7series_0.vho ...
MIG: 14:28:06 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:28:17 : Running synthesis.xit
MIG: 14:28:17 : ################# RUNNING MIG BATCH ###################
MIG: 14:28:17 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 14:28:17 : synp_flow:  -- synthesis_mode: Other
MIG: 14:28:17 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 14:28:17 : vivado_mode: xpg_pa
MIG: 14:28:17 :  locked false  
MIG: 14:28:17 : HDL Language: VHDL
MIG: 14:28:17 : compInfo: false
MIG: 14:28:17 : Vivado Options xc7a100t fgg484 -1
MIG: 14:28:17 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:28:17 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:28:17 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:28:17 : I am in catch area
MIG: 14:28:17 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 14:28:30 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:28:30 : Component_Name: mig_7series_0
MIG: 14:28:30 : Moving mig_7series_0 ...
MIG: 14:28:30 : Moving mig_7series_0.vho ...
MIG: 14:28:30 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:28:30 : Running vhdl_synth_rpr.xit
MIG: 14:28:30 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:28:30 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 14:28:31 : Running simulation.xit
MIG: 14:28:31 : ################# RUNNING MIG BATCH ###################
MIG: 14:28:31 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 14:28:31 : synp_flow:  -- synthesis_mode: Other
MIG: 14:28:31 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 14:28:31 : vivado_mode: xpg_pa
MIG: 14:28:31 :  locked false  
MIG: 14:28:31 : HDL Language: VHDL
MIG: 14:28:31 : compInfo: false
MIG: 14:28:31 : Vivado Options xc7a100t fgg484 -1
MIG: 14:28:31 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:28:31 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:28:31 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:28:31 : I am in catch area
MIG: 14:28:31 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 14:28:43 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002a/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:28:43 : Component_Name: mig_7series_0
MIG: 14:28:43 : Moving mig_7series_0 ...
MIG: 14:28:43 : Moving mig_7series_0.vho ...
MIG: 14:28:43 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:28:44 : Running vhdl_sim_rpr.xit
MIG: 14:28:44 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:28:44 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 14:28:45 : Running implementation.xit
MIG: 14:28:45 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:28:45 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:51:03 : Running synthesis.xit
MIG: 13:51:04 : ################# RUNNING MIG BATCH ###################
MIG: 13:51:04 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1800_002fwork/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 13:51:04 : synp_flow:  -- synthesis_mode: Other
MIG: 13:51:04 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1800_002fwork/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:51:04 : vivado_mode: xpg_pa
MIG: 13:51:04 :  locked false  
MIG: 13:51:04 : HDL Language: VHDL
MIG: 13:51:04 : compInfo: false
MIG: 13:51:04 : Vivado Options xc7a100t fgg484 -1
MIG: 13:51:04 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:51:04 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:51:04 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:51:04 : I am in catch area
MIG: 13:51:04 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/Documents/1VHDL/com-1800_002fwork/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/Documents/1VHDL/com-1800_002fwork/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 13:51:21 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1800_002fwork/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 13:51:21 : Component_Name: mig_7series_0
MIG: 13:51:21 : Moving mig_7series_0 ...
MIG: 13:51:21 : Moving mig_7series_0.vho ...
MIG: 13:51:21 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:51:21 : Running vhdl_synth_rpr.xit
MIG: 13:51:22 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:51:22 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:51:22 : Running implementation.xit
MIG: 13:51:22 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:51:22 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 16:34:50 : xml_input_file: mig_b.prj
MIG: 16:34:50 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 16:34:50 : xml_input_file: mig_b.prj
MIG: 16:34:50 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 16:37:07 : Running customizer.xit
MIG: 16:37:07 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 16:37:07 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5324-L1/coregen/mig_7series_0
MIG: 16:37:07 : synp_flow:  -- synthesis_mode: Other
MIG: 16:37:07 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5324-L1/coregen/mig_7series_0/_tmp/
MIG: 16:37:07 : vivado_mode: xpg_pa
MIG: 16:37:07 :  locked false  
MIG: 16:37:07 : HDL Language: VHDL
MIG: 16:37:07 : compInfo: false
MIG: 16:37:07 : Vivado Options xc7a100t fgg484 -1
MIG: 16:37:07 : 1: xc7a100t 2: fgg484 3: -1
MIG: 16:37:07 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 16:37:07 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 16:37:07 : I am in catch area
MIG: 16:37:07 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5324-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5324-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 16:43:55 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 16:43:55 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 16:43:55 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5324-L1/coregen/mig_7series_0/mig_a.prj
MIG: 16:43:55 : Component_Name: mig_7series_0
MIG: 16:43:55 : Moving mig_7series_0 ...
MIG: 16:43:56 : Moving mig_7series_0.vho ...
MIG: 16:43:56 : Moving mig_7series_0_xmdf.tcl ...
MIG: 16:43:56 : Sending back 0
MIG: 16:43:57 : xml_input_file: mig_a.prj
MIG: 16:43:57 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 16:43:57 : xml_input_file: mig_a.prj
MIG: 16:43:57 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 16:43:57 : In updateAllModelParams
MIG: 16:43:57 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 16:43:57 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 16:43:57 : XGUI hdlLanguage: VHDL
MIG: 16:43:57 : xgui vivado_mode: xpg_pa
MIG: 16:43:57 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 16:43:57 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 16:43:57 : 
MIG: 16:43:57 : Inside fn mem: DDR3
MIG: 16:43:57 : Inside fn detect_uiclk: 83333334
MIG: 16:43:57 : cntrl:  memtype: DDR3
MIG: 16:43:57 : 
MIG: 16:43:57 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 16:43:57 : 
MIG: 16:43:57 : 
MIG: 16:43:57 : 
MIG: 16:43:57 : 
MIG: 16:43:57 :  polarity_value: 1
MIG: 16:43:57 : 
MIG: 16:43:57 : 
MIG: 16:43:57 : cntrl:  memtype: DDR3
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 16:43:57 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 16:43:57 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 16:43:57 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 16:43:57 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: ECC ==> OFF
MIG: 16:43:57 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 16:43:57 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 16:43:57 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 16:43:57 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 16:43:57 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 16:43:57 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 16:43:57 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 16:43:57 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 16:43:57 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 16:43:57 :  Invalid Param: DDR3_AL ==> "0"
MIG: 16:43:57 :  Invalid Param: DDR3_nAL ==> 0
MIG: 16:43:57 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 16:43:57 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 16:43:57 :  Invalid Param: DDR3_CL ==> 5
MIG: 16:43:57 :  Invalid Param: DDR3_CWL ==> 5
MIG: 16:43:57 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 16:43:57 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 16:43:57 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 16:43:57 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 16:43:57 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 16:43:57 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 16:43:57 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 16:43:57 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 16:43:57 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 16:43:57 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 16:43:57 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 16:43:57 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 16:43:57 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 16:43:57 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 16:43:57 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 16:43:57 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 16:43:57 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 16:43:57 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 16:43:57 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 16:43:57 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 16:43:57 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 16:43:57 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 16:43:57 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 16:43:57 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 16:43:57 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 16:43:57 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 16:43:57 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 16:43:57 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 16:43:57 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 16:43:57 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 16:43:57 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 16:43:57 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 16:43:57 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 16:43:57 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 16:43:57 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 16:43:57 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 16:43:57 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 16:43:57 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 16:43:57 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 16:43:57 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 16:43:57 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 16:43:57 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 16:43:57 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 16:43:57 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 16:43:57 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 16:43:57 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 16:43:57 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 16:43:57 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 16:43:57 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 16:43:57 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 16:43:57 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 16:43:57 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 16:43:57 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 16:43:57 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 16:43:57 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 16:43:57 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 16:43:57 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 16:43:57 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 16:43:57 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 16:43:57 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 16:43:57 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 16:43:57 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 16:43:57 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 16:43:57 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 16:43:57 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 16:43:57 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 16:43:57 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 16:43:57 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 16:43:57 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 16:43:57 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 16:43:57 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 16:43:57 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 16:43:57 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 16:43:57 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 16:43:57 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 16:43:57 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 16:43:57 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 16:43:57 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 16:43:57 : 
MIG: 16:43:57 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 16:43:57 : 
MIG: 16:43:57 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 16:43:57 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 16:43:57 : 
MIG: 16:43:57 : 
MIG: 16:43:57 : 
MIG: 16:43:57 : Same Interface
MIG: 16:43:59 : ################# RUNNING MIG BATCH ###################
MIG: 16:43:59 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 16:43:59 : synp_flow:  -- synthesis_mode: Other
MIG: 16:43:59 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 16:43:59 : vivado_mode: xpg_pa
MIG: 16:43:59 :  locked false  
MIG: 16:43:59 : HDL Language: VHDL
MIG: 16:43:59 : compInfo: false
MIG: 16:43:59 : Vivado Options xc7a100t fgg484 -1
MIG: 16:43:59 : 1: xc7a100t 2: fgg484 3: -1
MIG: 16:43:59 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 16:43:59 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 16:43:59 : I am in catch area
MIG: 16:43:59 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 16:44:12 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 16:44:12 : Component_Name: mig_7series_0
MIG: 16:44:12 : Moving mig_7series_0 ...
MIG: 16:44:12 : Moving mig_7series_0.vho ...
MIG: 16:44:12 : Moving mig_7series_0_xmdf.tcl ...
MIG: 16:44:35 : Running synthesis.xit
MIG: 16:44:35 : ################# RUNNING MIG BATCH ###################
MIG: 16:44:35 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 16:44:35 : synp_flow:  -- synthesis_mode: Other
MIG: 16:44:35 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 16:44:35 : vivado_mode: xpg_pa
MIG: 16:44:35 :  locked false  
MIG: 16:44:35 : HDL Language: VHDL
MIG: 16:44:35 : compInfo: false
MIG: 16:44:35 : Vivado Options xc7a100t fgg484 -1
MIG: 16:44:35 : 1: xc7a100t 2: fgg484 3: -1
MIG: 16:44:35 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 16:44:35 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 16:44:35 : I am in catch area
MIG: 16:44:35 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 16:44:47 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 16:44:47 : Component_Name: mig_7series_0
MIG: 16:44:47 : Moving mig_7series_0 ...
MIG: 16:44:47 : Moving mig_7series_0.vho ...
MIG: 16:44:47 : Moving mig_7series_0_xmdf.tcl ...
MIG: 16:44:47 : Running vhdl_synth_rpr.xit
MIG: 16:44:47 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 16:44:47 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 16:44:48 : Running simulation.xit
MIG: 16:44:48 : ################# RUNNING MIG BATCH ###################
MIG: 16:44:48 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 16:44:48 : synp_flow:  -- synthesis_mode: Other
MIG: 16:44:48 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 16:44:48 : vivado_mode: xpg_pa
MIG: 16:44:48 :  locked false  
MIG: 16:44:48 : HDL Language: VHDL
MIG: 16:44:48 : compInfo: false
MIG: 16:44:48 : Vivado Options xc7a100t fgg484 -1
MIG: 16:44:48 : 1: xc7a100t 2: fgg484 3: -1
MIG: 16:44:48 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 16:44:48 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 16:44:48 : I am in catch area
MIG: 16:44:48 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 16:45:00 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000k/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 16:45:00 : Component_Name: mig_7series_0
MIG: 16:45:00 : Moving mig_7series_0 ...
MIG: 16:45:00 : Moving mig_7series_0.vho ...
MIG: 16:45:00 : Moving mig_7series_0_xmdf.tcl ...
MIG: 16:45:00 : Running vhdl_sim_rpr.xit
MIG: 16:45:00 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 16:45:00 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 16:45:00 : Running implementation.xit
MIG: 16:45:01 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 16:45:01 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:49:35 : xml_input_file: mig_a.prj
MIG: 12:49:35 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 12:49:35 : xml_input_file: mig_a.prj
MIG: 12:49:35 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 12:49:58 : Running customizer.xit
MIG: 12:49:58 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 12:49:58 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0
MIG: 12:49:58 : synp_flow:  -- synthesis_mode: Other
MIG: 12:49:58 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/_tmp/
MIG: 12:49:58 : vivado_mode: xpg_pa
MIG: 12:49:58 :  locked false  
MIG: 12:49:58 : HDL Language: VHDL
MIG: 12:49:58 : compInfo: false
MIG: 12:49:58 : Vivado Options xc7a100t fgg484 -1
MIG: 12:49:58 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:49:58 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:49:58 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:49:58 : I am in catch area
MIG: 12:49:58 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 12:55:36 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 12:55:36 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 12:55:36 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/mig_b.prj
MIG: 12:55:36 : Component_Name: mig_7series_0
MIG: 12:55:36 : Moving mig_7series_0 ...
MIG: 12:55:36 : Moving mig_7series_0.vho ...
MIG: 12:55:36 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:55:36 : Sending back 0
MIG: 12:55:37 : xml_input_file: mig_b.prj
MIG: 12:55:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:55:37 : xml_input_file: mig_b.prj
MIG: 12:55:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:55:37 : In updateAllModelParams
MIG: 12:55:37 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:55:37 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:55:37 : XGUI hdlLanguage: VHDL
MIG: 12:55:37 : xgui vivado_mode: xpg_pa
MIG: 12:55:37 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 12:55:37 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 12:55:38 : 
MIG: 12:55:38 : Inside fn mem: DDR3
MIG: 12:55:38 : Inside fn detect_uiclk: 83333334
MIG: 12:55:38 : cntrl:  memtype: DDR3
MIG: 12:55:38 : 
MIG: 12:55:38 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 12:55:38 : 
MIG: 12:55:38 : 
MIG: 12:55:38 : 
MIG: 12:55:38 : 
MIG: 12:55:38 :  polarity_value: 1
MIG: 12:55:38 : 
MIG: 12:55:38 : 
MIG: 12:55:38 : cntrl:  memtype: DDR3
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 12:55:38 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 12:55:38 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 12:55:38 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 12:55:38 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: ECC ==> OFF
MIG: 12:55:38 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 12:55:38 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 12:55:38 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 12:55:38 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 12:55:38 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 12:55:38 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 12:55:38 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 12:55:38 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 12:55:38 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 12:55:38 :  Invalid Param: DDR3_AL ==> "0"
MIG: 12:55:38 :  Invalid Param: DDR3_nAL ==> 0
MIG: 12:55:38 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 12:55:38 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 12:55:38 :  Invalid Param: DDR3_CL ==> 5
MIG: 12:55:38 :  Invalid Param: DDR3_CWL ==> 5
MIG: 12:55:38 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 12:55:38 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 12:55:38 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 12:55:38 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 12:55:38 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 12:55:38 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 12:55:38 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 12:55:38 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 12:55:38 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 12:55:38 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 12:55:38 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 12:55:38 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 12:55:38 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 12:55:38 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 12:55:38 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 12:55:38 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 12:55:38 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 12:55:38 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 12:55:38 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 12:55:38 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 12:55:38 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 12:55:38 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 12:55:38 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 12:55:38 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 12:55:38 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 12:55:38 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 12:55:38 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 12:55:38 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 12:55:38 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 12:55:38 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 12:55:38 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 12:55:38 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 12:55:38 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 12:55:38 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 12:55:38 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 12:55:38 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 12:55:38 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 12:55:38 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 12:55:38 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 12:55:38 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 12:55:38 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 12:55:38 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 12:55:38 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 12:55:38 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 12:55:38 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 12:55:38 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 12:55:38 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 12:55:38 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 12:55:38 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 12:55:38 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 12:55:38 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 12:55:38 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 12:55:38 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 12:55:38 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 12:55:38 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 12:55:38 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 12:55:38 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 12:55:38 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 12:55:38 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 12:55:38 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 12:55:38 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 12:55:38 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 12:55:38 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 12:55:38 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 12:55:38 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 12:55:38 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 12:55:38 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 12:55:38 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 12:55:38 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 12:55:38 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 12:55:38 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 12:55:38 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 12:55:38 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 12:55:38 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 12:55:38 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 12:55:38 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 12:55:38 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 12:55:38 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 12:55:38 : 
MIG: 12:55:38 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 12:55:38 : 
MIG: 12:55:38 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 12:55:38 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 12:55:38 : 
MIG: 12:55:38 : 
MIG: 12:55:38 : 
MIG: 12:55:38 : Same Interface
MIG: 12:55:40 : ################# RUNNING MIG BATCH ###################
MIG: 12:55:40 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 12:55:40 : synp_flow:  -- synthesis_mode: Other
MIG: 12:55:40 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 12:55:40 : vivado_mode: xpg_pa
MIG: 12:55:40 :  locked false  
MIG: 12:55:40 : HDL Language: VHDL
MIG: 12:55:40 : compInfo: false
MIG: 12:55:40 : Vivado Options xc7a100t fgg484 -1
MIG: 12:55:40 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:55:40 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:55:40 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:55:40 : I am in catch area
MIG: 12:55:40 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 12:55:53 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:55:53 : Component_Name: mig_7series_0
MIG: 12:55:53 : Moving mig_7series_0 ...
MIG: 12:55:53 : Moving mig_7series_0.vho ...
MIG: 12:55:53 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:58:03 : Running synthesis.xit
MIG: 12:58:03 : ################# RUNNING MIG BATCH ###################
MIG: 12:58:03 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 12:58:03 : synp_flow:  -- synthesis_mode: Other
MIG: 12:58:03 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 12:58:03 : vivado_mode: xpg_pa
MIG: 12:58:03 :  locked false  
MIG: 12:58:03 : HDL Language: VHDL
MIG: 12:58:03 : compInfo: false
MIG: 12:58:03 : Vivado Options xc7a100t fgg484 -1
MIG: 12:58:03 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:58:03 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:58:03 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:58:03 : I am in catch area
MIG: 12:58:03 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 12:58:15 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:58:15 : Component_Name: mig_7series_0
MIG: 12:58:15 : Moving mig_7series_0 ...
MIG: 12:58:15 : Moving mig_7series_0.vho ...
MIG: 12:58:15 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:58:16 : Running vhdl_synth_rpr.xit
MIG: 12:58:16 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:58:16 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:58:16 : Running simulation.xit
MIG: 12:58:16 : ################# RUNNING MIG BATCH ###################
MIG: 12:58:16 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 12:58:16 : synp_flow:  -- synthesis_mode: Other
MIG: 12:58:16 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 12:58:16 : vivado_mode: xpg_pa
MIG: 12:58:16 :  locked false  
MIG: 12:58:16 : HDL Language: VHDL
MIG: 12:58:16 : compInfo: false
MIG: 12:58:16 : Vivado Options xc7a100t fgg484 -1
MIG: 12:58:16 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:58:16 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:58:16 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:58:16 : I am in catch area
MIG: 12:58:16 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 12:58:29 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:58:29 : Component_Name: mig_7series_0
MIG: 12:58:29 : Moving mig_7series_0 ...
MIG: 12:58:29 : Moving mig_7series_0.vho ...
MIG: 12:58:29 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:58:29 : Running vhdl_sim_rpr.xit
MIG: 12:58:29 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:58:29 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:58:30 : Running implementation.xit
MIG: 12:58:30 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:58:30 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:33:37 : Running customizer.xit
MIG: 13:33:38 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 13:33:38 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0
MIG: 13:33:38 : synp_flow:  -- synthesis_mode: Other
MIG: 13:33:38 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/_tmp/
MIG: 13:33:38 : vivado_mode: xpg_pa
MIG: 13:33:38 :  locked false  
MIG: 13:33:38 : HDL Language: VHDL
MIG: 13:33:38 : compInfo: false
MIG: 13:33:38 : Vivado Options xc7a100t fgg484 -1
MIG: 13:33:38 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:33:38 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:33:38 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:33:38 : I am in catch area
MIG: 13:33:38 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 13:37:53 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 13:37:53 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 13:37:53 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/mig_a.prj
MIG: 13:37:53 : Component_Name: mig_7series_0
MIG: 13:37:53 : Moving mig_7series_0 ...
MIG: 13:37:53 : Moving mig_7series_0.vho ...
MIG: 13:37:53 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:37:53 : Sending back 0
MIG: 13:37:55 : xml_input_file: mig_a.prj
MIG: 13:37:55 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:37:55 : xml_input_file: mig_a.prj
MIG: 13:37:55 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:37:55 : In updateAllModelParams
MIG: 13:37:55 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:37:55 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:37:55 : XGUI hdlLanguage: VHDL
MIG: 13:37:55 : xgui vivado_mode: xpg_pa
MIG: 13:37:55 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 13:37:55 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 13:37:55 : 
MIG: 13:37:55 : Inside fn mem: DDR3
MIG: 13:37:55 : Inside fn detect_uiclk: 83333334
MIG: 13:37:55 : cntrl:  memtype: DDR3
MIG: 13:37:55 : 
MIG: 13:37:55 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 13:37:55 : 
MIG: 13:37:55 : 
MIG: 13:37:55 : 
MIG: 13:37:55 : 
MIG: 13:37:55 :  polarity_value: 1
MIG: 13:37:55 : 
MIG: 13:37:55 : 
MIG: 13:37:55 : cntrl:  memtype: DDR3
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 13:37:55 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 13:37:55 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 13:37:55 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 13:37:55 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: ECC ==> OFF
MIG: 13:37:55 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 13:37:55 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 13:37:55 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 13:37:55 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 13:37:55 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 13:37:55 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 13:37:55 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 13:37:55 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 13:37:55 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 13:37:55 :  Invalid Param: DDR3_AL ==> "0"
MIG: 13:37:55 :  Invalid Param: DDR3_nAL ==> 0
MIG: 13:37:55 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 13:37:55 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 13:37:55 :  Invalid Param: DDR3_CL ==> 5
MIG: 13:37:55 :  Invalid Param: DDR3_CWL ==> 5
MIG: 13:37:55 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 13:37:55 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 13:37:55 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 13:37:55 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 13:37:55 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 13:37:55 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 13:37:55 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 13:37:55 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 13:37:55 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 13:37:55 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 13:37:55 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 13:37:55 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 13:37:55 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 13:37:55 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 13:37:55 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 13:37:55 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 13:37:55 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 13:37:55 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 13:37:55 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 13:37:55 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 13:37:55 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 13:37:55 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 13:37:55 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 13:37:55 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 13:37:55 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 13:37:55 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 13:37:55 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 13:37:55 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 13:37:55 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 13:37:55 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 13:37:55 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 13:37:55 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 13:37:55 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 13:37:55 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 13:37:55 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 13:37:55 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 13:37:55 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 13:37:55 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 13:37:55 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 13:37:55 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 13:37:55 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 13:37:55 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 13:37:55 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 13:37:55 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 13:37:55 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 13:37:55 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 13:37:55 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 13:37:55 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 13:37:55 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 13:37:55 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 13:37:55 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 13:37:55 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 13:37:55 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 13:37:55 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 13:37:55 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 13:37:55 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 13:37:55 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 13:37:55 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 13:37:55 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 13:37:55 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 13:37:55 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 13:37:55 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 13:37:55 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 13:37:55 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 13:37:55 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 13:37:55 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 13:37:55 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 13:37:55 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 13:37:55 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 13:37:55 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 13:37:55 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 13:37:55 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 13:37:55 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 13:37:55 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 13:37:55 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 13:37:55 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 13:37:55 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 13:37:55 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 13:37:55 : 
MIG: 13:37:55 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 13:37:55 : 
MIG: 13:37:55 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 13:37:55 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 13:37:55 : 
MIG: 13:37:55 : 
MIG: 13:37:55 : 
MIG: 13:37:55 : Same Interface
MIG: 13:37:57 : ################# RUNNING MIG BATCH ###################
MIG: 13:37:57 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 13:37:57 : synp_flow:  -- synthesis_mode: Other
MIG: 13:37:57 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:37:57 : vivado_mode: xpg_pa
MIG: 13:37:57 :  locked false  
MIG: 13:37:57 : HDL Language: VHDL
MIG: 13:37:57 : compInfo: false
MIG: 13:37:57 : Vivado Options xc7a100t fgg484 -1
MIG: 13:37:57 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:37:57 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:37:57 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:37:57 : I am in catch area
MIG: 13:37:57 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 13:38:09 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:38:09 : Component_Name: mig_7series_0
MIG: 13:38:09 : Moving mig_7series_0 ...
MIG: 13:38:09 : Moving mig_7series_0.vho ...
MIG: 13:38:09 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:38:59 : Running synthesis.xit
MIG: 13:38:59 : ################# RUNNING MIG BATCH ###################
MIG: 13:38:59 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 13:38:59 : synp_flow:  -- synthesis_mode: Other
MIG: 13:38:59 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:38:59 : vivado_mode: xpg_pa
MIG: 13:38:59 :  locked false  
MIG: 13:38:59 : HDL Language: VHDL
MIG: 13:38:59 : compInfo: false
MIG: 13:38:59 : Vivado Options xc7a100t fgg484 -1
MIG: 13:38:59 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:38:59 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:38:59 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:38:59 : I am in catch area
MIG: 13:38:59 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 13:39:11 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:39:11 : Component_Name: mig_7series_0
MIG: 13:39:11 : Moving mig_7series_0 ...
MIG: 13:39:11 : Moving mig_7series_0.vho ...
MIG: 13:39:11 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:39:12 : Running vhdl_synth_rpr.xit
MIG: 13:39:12 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:39:12 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:39:12 : Running simulation.xit
MIG: 13:39:12 : ################# RUNNING MIG BATCH ###################
MIG: 13:39:12 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 13:39:12 : synp_flow:  -- synthesis_mode: Other
MIG: 13:39:12 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:39:12 : vivado_mode: xpg_pa
MIG: 13:39:12 :  locked false  
MIG: 13:39:12 : HDL Language: VHDL
MIG: 13:39:12 : compInfo: false
MIG: 13:39:12 : Vivado Options xc7a100t fgg484 -1
MIG: 13:39:12 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:39:12 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:39:12 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:39:12 : I am in catch area
MIG: 13:39:12 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 13:39:24 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:39:24 : Component_Name: mig_7series_0
MIG: 13:39:24 : Moving mig_7series_0 ...
MIG: 13:39:24 : Moving mig_7series_0.vho ...
MIG: 13:39:24 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:39:24 : Running vhdl_sim_rpr.xit
MIG: 13:39:24 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:39:24 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:39:25 : Running implementation.xit
MIG: 13:39:25 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:39:25 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 14:02:12 : Running customizer.xit
MIG: 14:02:12 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 14:02:12 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0
MIG: 14:02:12 : synp_flow:  -- synthesis_mode: Other
MIG: 14:02:12 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/_tmp/
MIG: 14:02:12 : vivado_mode: xpg_pa
MIG: 14:02:12 :  locked false  
MIG: 14:02:12 : HDL Language: VHDL
MIG: 14:02:12 : compInfo: false
MIG: 14:02:12 : Vivado Options xc7a100t fgg484 -1
MIG: 14:02:12 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:02:12 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:02:12 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:02:12 : I am in catch area
MIG: 14:02:12 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 14:16:44 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 14:16:44 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 14:16:44 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5172-L1/coregen/mig_7series_0/mig_b.prj
MIG: 14:16:44 : Component_Name: mig_7series_0
MIG: 14:16:44 : Moving mig_7series_0 ...
MIG: 14:16:44 : Moving mig_7series_0.vho ...
MIG: 14:16:44 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:16:44 : Sending back 0
MIG: 14:16:46 : xml_input_file: mig_b.prj
MIG: 14:16:46 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:16:46 : xml_input_file: mig_b.prj
MIG: 14:16:46 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:16:46 : In updateAllModelParams
MIG: 14:16:46 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:16:46 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 14:16:46 : XGUI hdlLanguage: VHDL
MIG: 14:16:46 : xgui vivado_mode: xpg_pa
MIG: 14:16:46 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 14:16:46 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 14:16:46 : 
MIG: 14:16:46 : Inside fn mem: DDR3
MIG: 14:16:46 : Inside fn detect_uiclk: 83333334
MIG: 14:16:46 : cntrl:  memtype: DDR3
MIG: 14:16:46 : 
MIG: 14:16:46 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 14:16:46 : 
MIG: 14:16:46 : 
MIG: 14:16:46 : 
MIG: 14:16:46 : 
MIG: 14:16:46 :  polarity_value: 1
MIG: 14:16:46 : 
MIG: 14:16:46 : 
MIG: 14:16:46 : cntrl:  memtype: DDR3
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 14:16:46 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 14:16:46 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 14:16:46 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 14:16:46 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: ECC ==> OFF
MIG: 14:16:46 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 14:16:46 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 14:16:46 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 14:16:46 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 14:16:46 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 14:16:46 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 14:16:46 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 14:16:46 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 14:16:46 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 14:16:46 :  Invalid Param: DDR3_AL ==> "0"
MIG: 14:16:46 :  Invalid Param: DDR3_nAL ==> 0
MIG: 14:16:46 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 14:16:46 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 14:16:46 :  Invalid Param: DDR3_CL ==> 5
MIG: 14:16:46 :  Invalid Param: DDR3_CWL ==> 5
MIG: 14:16:46 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 14:16:46 :  Invalid Param: DDR3_RTT_NOM ==> "120"
MIG: 14:16:46 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 14:16:46 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 14:16:46 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 14:16:46 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 14:16:46 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 14:16:46 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 14:16:46 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 14:16:46 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 14:16:46 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 14:16:46 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 14:16:46 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 14:16:46 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 14:16:46 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 14:16:46 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 14:16:46 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 14:16:46 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 14:16:46 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 14:16:46 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 14:16:46 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 14:16:46 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 14:16:46 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 14:16:46 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 14:16:46 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 14:16:46 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 14:16:46 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 14:16:46 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 14:16:46 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 14:16:46 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 14:16:46 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 14:16:46 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 14:16:46 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 14:16:46 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 14:16:46 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 14:16:46 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 14:16:46 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 14:16:46 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 14:16:46 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 14:16:46 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 14:16:46 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 14:16:46 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 14:16:46 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 14:16:46 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 14:16:46 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 14:16:46 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 14:16:46 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 14:16:46 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 14:16:46 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 14:16:46 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 14:16:46 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 14:16:46 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 14:16:46 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 14:16:46 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 14:16:46 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 14:16:46 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 14:16:46 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 14:16:46 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 14:16:46 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 14:16:46 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 14:16:46 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 14:16:46 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 14:16:46 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 14:16:46 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 14:16:46 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 14:16:46 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 14:16:46 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 14:16:46 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 14:16:46 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 14:16:46 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 14:16:46 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 14:16:46 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 14:16:46 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 14:16:46 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 14:16:46 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 14:16:46 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 14:16:46 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 14:16:46 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 14:16:46 : 
MIG: 14:16:46 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 14:16:46 : 
MIG: 14:16:46 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 14:16:46 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 14:16:46 : 
MIG: 14:16:46 : 
MIG: 14:16:46 : 
MIG: 14:16:46 : Same Interface
MIG: 14:16:48 : ################# RUNNING MIG BATCH ###################
MIG: 14:16:48 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 14:16:48 : synp_flow:  -- synthesis_mode: Other
MIG: 14:16:48 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 14:16:48 : vivado_mode: xpg_pa
MIG: 14:16:48 :  locked false  
MIG: 14:16:48 : HDL Language: VHDL
MIG: 14:16:48 : compInfo: false
MIG: 14:16:48 : Vivado Options xc7a100t fgg484 -1
MIG: 14:16:48 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:16:48 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:16:48 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:16:48 : I am in catch area
MIG: 14:16:48 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 14:17:00 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:17:00 : Component_Name: mig_7series_0
MIG: 14:17:00 : Moving mig_7series_0 ...
MIG: 14:17:00 : Moving mig_7series_0.vho ...
MIG: 14:17:00 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:18:14 : Running synthesis.xit
MIG: 14:18:14 : ################# RUNNING MIG BATCH ###################
MIG: 14:18:14 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 14:18:14 : synp_flow:  -- synthesis_mode: Other
MIG: 14:18:14 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 14:18:14 : vivado_mode: xpg_pa
MIG: 14:18:14 :  locked false  
MIG: 14:18:14 : HDL Language: VHDL
MIG: 14:18:14 : compInfo: false
MIG: 14:18:14 : Vivado Options xc7a100t fgg484 -1
MIG: 14:18:14 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:18:14 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:18:14 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:18:14 : I am in catch area
MIG: 14:18:14 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 14:18:26 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:18:26 : Component_Name: mig_7series_0
MIG: 14:18:26 : Moving mig_7series_0 ...
MIG: 14:18:26 : Moving mig_7series_0.vho ...
MIG: 14:18:26 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:18:26 : Running vhdl_synth_rpr.xit
MIG: 14:18:27 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:18:27 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 14:18:27 : Running simulation.xit
MIG: 14:18:27 : ################# RUNNING MIG BATCH ###################
MIG: 14:18:27 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 14:18:27 : synp_flow:  -- synthesis_mode: Other
MIG: 14:18:27 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 14:18:27 : vivado_mode: xpg_pa
MIG: 14:18:27 :  locked false  
MIG: 14:18:27 : HDL Language: VHDL
MIG: 14:18:27 : compInfo: false
MIG: 14:18:27 : Vivado Options xc7a100t fgg484 -1
MIG: 14:18:27 : 1: xc7a100t 2: fgg484 3: -1
MIG: 14:18:27 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 14:18:27 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 14:18:27 : I am in catch area
MIG: 14:18:27 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 14:18:39 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000s/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 14:18:39 : Component_Name: mig_7series_0
MIG: 14:18:39 : Moving mig_7series_0 ...
MIG: 14:18:39 : Moving mig_7series_0.vho ...
MIG: 14:18:39 : Moving mig_7series_0_xmdf.tcl ...
MIG: 14:18:39 : Running vhdl_sim_rpr.xit
MIG: 14:18:39 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:18:39 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 14:18:40 : Running implementation.xit
MIG: 14:18:40 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 14:18:40 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 15:31:41 : xml_input_file: mig_b.prj
MIG: 15:31:42 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 15:31:42 : xml_input_file: mig_b.prj
MIG: 15:31:42 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 15:32:00 : Running customizer.xit
MIG: 15:32:00 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 15:32:00 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-940-L1/coregen/mig_7series_0
MIG: 15:32:00 : synp_flow:  -- synthesis_mode: Other
MIG: 15:32:00 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-940-L1/coregen/mig_7series_0/_tmp/
MIG: 15:32:00 : vivado_mode: xpg_pa
MIG: 15:32:00 :  locked false  
MIG: 15:32:00 : HDL Language: VHDL
MIG: 15:32:00 : compInfo: false
MIG: 15:32:00 : Vivado Options xc7a100t fgg484 -1
MIG: 15:32:00 : 1: xc7a100t 2: fgg484 3: -1
MIG: 15:32:00 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 15:32:00 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 15:32:00 : I am in catch area
MIG: 15:32:00 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-940-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-940-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 15:33:13 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 15:33:13 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 15:33:13 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-940-L1/coregen/mig_7series_0/mig_a.prj
MIG: 15:33:13 : Component_Name: mig_7series_0
MIG: 15:33:13 : Moving mig_7series_0 ...
MIG: 15:33:13 : Moving mig_7series_0.vho ...
MIG: 15:33:13 : Moving mig_7series_0_xmdf.tcl ...
MIG: 15:33:13 : Sending back 0
MIG: 15:33:15 : xml_input_file: mig_a.prj
MIG: 15:33:15 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:33:15 : xml_input_file: mig_a.prj
MIG: 15:33:15 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:33:15 : In updateAllModelParams
MIG: 15:33:15 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 15:33:15 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 15:33:15 : XGUI hdlLanguage: VHDL
MIG: 15:33:15 : xgui vivado_mode: xpg_pa
MIG: 15:33:15 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 15:33:15 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 15:33:15 : 
MIG: 15:33:15 : Inside fn mem: DDR3
MIG: 15:33:15 : Inside fn detect_uiclk: 83333334
MIG: 15:33:15 : cntrl:  memtype: DDR3
MIG: 15:33:15 : 
MIG: 15:33:15 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 15:33:15 : 
MIG: 15:33:15 : 
MIG: 15:33:15 : 
MIG: 15:33:15 : 
MIG: 15:33:15 :  polarity_value: 1
MIG: 15:33:15 : 
MIG: 15:33:15 : 
MIG: 15:33:15 : cntrl:  memtype: DDR3
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 15:33:15 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 15:33:15 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 15:33:15 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 15:33:15 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: ECC ==> OFF
MIG: 15:33:15 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 15:33:15 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 15:33:15 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 15:33:15 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 15:33:15 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 15:33:15 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 15:33:15 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 15:33:15 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 15:33:15 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 15:33:15 :  Invalid Param: DDR3_AL ==> "0"
MIG: 15:33:15 :  Invalid Param: DDR3_nAL ==> 0
MIG: 15:33:15 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 15:33:15 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 15:33:15 :  Invalid Param: DDR3_CL ==> 5
MIG: 15:33:15 :  Invalid Param: DDR3_CWL ==> 5
MIG: 15:33:15 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 15:33:15 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 15:33:15 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 15:33:15 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 15:33:15 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 15:33:15 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 15:33:15 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 15:33:15 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 15:33:15 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 15:33:15 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 15:33:15 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 15:33:15 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 15:33:15 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 15:33:15 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 15:33:15 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 15:33:15 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 15:33:15 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 15:33:15 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 15:33:15 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 15:33:15 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 15:33:15 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 15:33:15 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 15:33:15 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 15:33:15 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 15:33:15 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 15:33:15 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 15:33:15 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 15:33:15 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 15:33:15 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 15:33:15 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 15:33:15 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 15:33:15 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 15:33:15 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 15:33:15 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 15:33:15 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 15:33:15 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 15:33:15 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 15:33:15 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 15:33:15 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 15:33:15 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 15:33:15 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 15:33:15 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 15:33:15 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 15:33:15 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 15:33:15 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 15:33:15 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 15:33:15 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 15:33:15 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 15:33:15 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 15:33:15 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 15:33:15 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 15:33:15 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 15:33:15 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 15:33:15 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 15:33:15 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 15:33:15 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 15:33:15 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 15:33:15 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 15:33:15 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 15:33:15 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 15:33:15 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 15:33:15 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 15:33:15 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 15:33:15 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 15:33:15 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 15:33:15 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 15:33:15 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 15:33:15 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 15:33:15 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 15:33:15 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 15:33:15 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 15:33:15 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 15:33:15 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 15:33:15 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 15:33:15 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 15:33:15 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 15:33:15 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 15:33:15 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 15:33:15 : 
MIG: 15:33:15 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 15:33:15 : 
MIG: 15:33:15 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 15:33:15 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 15:33:15 : 
MIG: 15:33:15 : 
MIG: 15:33:15 : 
MIG: 15:33:15 : Same Interface
MIG: 15:33:17 : ################# RUNNING MIG BATCH ###################
MIG: 15:33:17 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 15:33:17 : synp_flow:  -- synthesis_mode: Other
MIG: 15:33:17 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 15:33:17 : vivado_mode: xpg_pa
MIG: 15:33:17 :  locked false  
MIG: 15:33:17 : HDL Language: VHDL
MIG: 15:33:17 : compInfo: false
MIG: 15:33:17 : Vivado Options xc7a100t fgg484 -1
MIG: 15:33:17 : 1: xc7a100t 2: fgg484 3: -1
MIG: 15:33:17 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 15:33:17 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 15:33:17 : I am in catch area
MIG: 15:33:17 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 15:33:29 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:33:29 : Component_Name: mig_7series_0
MIG: 15:33:29 : Moving mig_7series_0 ...
MIG: 15:33:29 : Moving mig_7series_0.vho ...
MIG: 15:33:29 : Moving mig_7series_0_xmdf.tcl ...
MIG: 15:33:41 : Running synthesis.xit
MIG: 15:33:41 : ################# RUNNING MIG BATCH ###################
MIG: 15:33:41 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 15:33:41 : synp_flow:  -- synthesis_mode: Other
MIG: 15:33:41 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 15:33:41 : vivado_mode: xpg_pa
MIG: 15:33:41 :  locked false  
MIG: 15:33:41 : HDL Language: VHDL
MIG: 15:33:41 : compInfo: false
MIG: 15:33:41 : Vivado Options xc7a100t fgg484 -1
MIG: 15:33:41 : 1: xc7a100t 2: fgg484 3: -1
MIG: 15:33:41 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 15:33:41 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 15:33:41 : I am in catch area
MIG: 15:33:41 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 15:33:53 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:33:53 : Component_Name: mig_7series_0
MIG: 15:33:53 : Moving mig_7series_0 ...
MIG: 15:33:53 : Moving mig_7series_0.vho ...
MIG: 15:33:53 : Moving mig_7series_0_xmdf.tcl ...
MIG: 15:33:53 : Running vhdl_synth_rpr.xit
MIG: 15:33:53 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 15:33:53 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 15:33:53 : Running simulation.xit
MIG: 15:33:53 : ################# RUNNING MIG BATCH ###################
MIG: 15:33:53 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 15:33:53 : synp_flow:  -- synthesis_mode: Other
MIG: 15:33:53 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 15:33:53 : vivado_mode: xpg_pa
MIG: 15:33:53 :  locked false  
MIG: 15:33:53 : HDL Language: VHDL
MIG: 15:33:53 : compInfo: false
MIG: 15:33:53 : Vivado Options xc7a100t fgg484 -1
MIG: 15:33:53 : 1: xc7a100t 2: fgg484 3: -1
MIG: 15:33:53 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 15:33:53 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 15:33:53 : I am in catch area
MIG: 15:33:53 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 15:34:05 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000t/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 15:34:05 : Component_Name: mig_7series_0
MIG: 15:34:05 : Moving mig_7series_0 ...
MIG: 15:34:06 : Moving mig_7series_0.vho ...
MIG: 15:34:06 : Moving mig_7series_0_xmdf.tcl ...
MIG: 15:34:06 : Running vhdl_sim_rpr.xit
MIG: 15:34:06 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 15:34:06 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 15:34:06 : Running implementation.xit
MIG: 15:34:06 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 15:34:06 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 10:39:01 : xml_input_file: mig_a.prj
MIG: 10:39:01 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 10:39:01 : xml_input_file: mig_a.prj
MIG: 10:39:01 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 10:39:22 : Running customizer.xit
MIG: 10:39:22 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 10:39:22 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0
MIG: 10:39:22 : synp_flow:  -- synthesis_mode: Other
MIG: 10:39:22 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/_tmp/
MIG: 10:39:22 : vivado_mode: xpg_pa
MIG: 10:39:22 :  locked false  
MIG: 10:39:22 : HDL Language: VHDL
MIG: 10:39:22 : compInfo: false
MIG: 10:39:22 : Vivado Options xc7a100t fgg484 -1
MIG: 10:39:22 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:39:22 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:39:22 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:39:22 : I am in catch area
MIG: 10:39:22 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 10:51:03 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 10:51:03 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 10:51:03 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/mig_b.prj
MIG: 10:51:03 : Component_Name: mig_7series_0
MIG: 10:51:03 : Moving mig_7series_0 ...
MIG: 10:51:03 : Moving mig_7series_0.vho ...
MIG: 10:51:03 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:51:03 : Sending back 0
MIG: 10:51:05 : xml_input_file: mig_b.prj
MIG: 10:51:05 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:51:05 : xml_input_file: mig_b.prj
MIG: 10:51:05 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:51:05 : In updateAllModelParams
MIG: 10:51:05 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:51:05 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 10:51:05 : XGUI hdlLanguage: VHDL
MIG: 10:51:05 : xgui vivado_mode: xpg_pa
MIG: 10:51:05 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 10:51:05 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 10:51:05 : 
MIG: 10:51:05 : Inside fn mem: DDR3
MIG: 10:51:05 : Inside fn detect_uiclk: 83333334
MIG: 10:51:05 : cntrl:  memtype: DDR3
MIG: 10:51:05 : 
MIG: 10:51:05 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 10:51:05 : 
MIG: 10:51:05 : 
MIG: 10:51:05 : 
MIG: 10:51:05 : 
MIG: 10:51:05 :  polarity_value: 1
MIG: 10:51:05 : 
MIG: 10:51:05 : 
MIG: 10:51:05 : cntrl:  memtype: DDR3
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 10:51:05 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 10:51:05 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 10:51:05 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 10:51:05 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: ECC ==> OFF
MIG: 10:51:05 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 10:51:05 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 10:51:05 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 10:51:05 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 10:51:05 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 10:51:05 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 10:51:05 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 10:51:05 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 10:51:05 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 10:51:05 :  Invalid Param: DDR3_AL ==> "0"
MIG: 10:51:05 :  Invalid Param: DDR3_nAL ==> 0
MIG: 10:51:05 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 10:51:05 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 10:51:05 :  Invalid Param: DDR3_CL ==> 5
MIG: 10:51:05 :  Invalid Param: DDR3_CWL ==> 5
MIG: 10:51:05 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 10:51:05 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 10:51:05 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 10:51:05 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 10:51:05 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 10:51:05 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 10:51:05 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 10:51:05 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 10:51:05 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 10:51:05 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 10:51:05 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 10:51:05 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 10:51:05 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 10:51:05 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 10:51:05 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 10:51:05 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 10:51:05 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 10:51:05 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 10:51:05 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 10:51:05 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 10:51:05 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 10:51:05 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 10:51:05 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 10:51:05 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 10:51:05 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 10:51:05 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 10:51:05 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 10:51:05 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 10:51:05 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 10:51:05 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 10:51:05 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 10:51:05 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 10:51:05 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 10:51:05 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 10:51:05 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 10:51:05 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 10:51:05 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 10:51:05 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 10:51:05 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 10:51:05 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 10:51:05 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 10:51:05 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 10:51:05 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 10:51:05 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 10:51:05 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 10:51:05 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 10:51:05 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 10:51:05 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 10:51:05 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 10:51:05 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 10:51:05 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 10:51:05 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 10:51:05 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 10:51:05 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 10:51:05 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 10:51:05 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 10:51:05 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 10:51:05 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 10:51:05 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 10:51:05 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 10:51:05 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 10:51:05 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 10:51:05 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 10:51:05 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 10:51:05 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 10:51:05 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 10:51:05 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 10:51:05 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 10:51:05 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 10:51:05 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 10:51:05 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 10:51:05 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 10:51:05 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 10:51:05 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 10:51:05 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 10:51:05 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 10:51:05 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 10:51:05 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 10:51:05 : 
MIG: 10:51:05 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 10:51:05 : 
MIG: 10:51:05 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 10:51:05 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 10:51:05 : 
MIG: 10:51:05 : 
MIG: 10:51:05 : 
MIG: 10:51:05 : Same Interface
MIG: 10:51:07 : ################# RUNNING MIG BATCH ###################
MIG: 10:51:07 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 10:51:07 : synp_flow:  -- synthesis_mode: Other
MIG: 10:51:07 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 10:51:07 : vivado_mode: xpg_pa
MIG: 10:51:07 :  locked false  
MIG: 10:51:07 : HDL Language: VHDL
MIG: 10:51:07 : compInfo: false
MIG: 10:51:07 : Vivado Options xc7a100t fgg484 -1
MIG: 10:51:07 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:51:07 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:51:07 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:51:07 : I am in catch area
MIG: 10:51:07 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 10:51:19 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:51:19 : Component_Name: mig_7series_0
MIG: 10:51:19 : Moving mig_7series_0 ...
MIG: 10:51:19 : Moving mig_7series_0.vho ...
MIG: 10:51:19 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:53:52 : Running synthesis.xit
MIG: 10:53:52 : ################# RUNNING MIG BATCH ###################
MIG: 10:53:52 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 10:53:52 : synp_flow:  -- synthesis_mode: Other
MIG: 10:53:52 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 10:53:52 : vivado_mode: xpg_pa
MIG: 10:53:52 :  locked false  
MIG: 10:53:52 : HDL Language: VHDL
MIG: 10:53:52 : compInfo: false
MIG: 10:53:52 : Vivado Options xc7a100t fgg484 -1
MIG: 10:53:52 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:53:52 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:53:52 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:53:52 : I am in catch area
MIG: 10:53:52 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 10:54:05 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:54:05 : Component_Name: mig_7series_0
MIG: 10:54:05 : Moving mig_7series_0 ...
MIG: 10:54:05 : Moving mig_7series_0.vho ...
MIG: 10:54:05 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:54:05 : Running vhdl_synth_rpr.xit
MIG: 10:54:05 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:54:05 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 10:54:05 : Running simulation.xit
MIG: 10:54:05 : ################# RUNNING MIG BATCH ###################
MIG: 10:54:05 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 10:54:05 : synp_flow:  -- synthesis_mode: Other
MIG: 10:54:05 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 10:54:05 : vivado_mode: xpg_pa
MIG: 10:54:05 :  locked false  
MIG: 10:54:05 : HDL Language: VHDL
MIG: 10:54:05 : compInfo: false
MIG: 10:54:05 : Vivado Options xc7a100t fgg484 -1
MIG: 10:54:05 : 1: xc7a100t 2: fgg484 3: -1
MIG: 10:54:06 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 10:54:06 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 10:54:06 : I am in catch area
MIG: 10:54:06 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 10:54:18 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 10:54:18 : Component_Name: mig_7series_0
MIG: 10:54:18 : Moving mig_7series_0 ...
MIG: 10:54:18 : Moving mig_7series_0.vho ...
MIG: 10:54:18 : Moving mig_7series_0_xmdf.tcl ...
MIG: 10:54:18 : Running vhdl_sim_rpr.xit
MIG: 10:54:18 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:54:18 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 10:54:18 : Running implementation.xit
MIG: 10:54:18 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 10:54:18 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:53:24 : Running customizer.xit
MIG: 11:53:24 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 11:53:24 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0
MIG: 11:53:24 : synp_flow:  -- synthesis_mode: Other
MIG: 11:53:24 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/_tmp/
MIG: 11:53:24 : vivado_mode: xpg_pa
MIG: 11:53:24 :  locked false  
MIG: 11:53:24 : HDL Language: VHDL
MIG: 11:53:24 : compInfo: false
MIG: 11:53:24 : Vivado Options xc7a100t fgg484 -1
MIG: 11:53:24 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:53:24 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:53:24 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:53:24 : I am in catch area
MIG: 11:53:24 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 11:55:13 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 11:55:13 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 11:55:13 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4276-L1/coregen/mig_7series_0/mig_a.prj
MIG: 11:55:13 : Component_Name: mig_7series_0
MIG: 11:55:13 : Moving mig_7series_0 ...
MIG: 11:55:13 : Moving mig_7series_0.vho ...
MIG: 11:55:13 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:55:13 : Sending back 0
MIG: 11:55:14 : xml_input_file: mig_a.prj
MIG: 11:55:14 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:55:14 : xml_input_file: mig_a.prj
MIG: 11:55:14 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:55:14 : In updateAllModelParams
MIG: 11:55:14 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:55:14 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:55:14 : XGUI hdlLanguage: VHDL
MIG: 11:55:14 : xgui vivado_mode: xpg_pa
MIG: 11:55:14 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 11:55:14 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 11:55:14 : 
MIG: 11:55:14 : Inside fn mem: DDR3
MIG: 11:55:14 : Inside fn detect_uiclk: 83333334
MIG: 11:55:14 : cntrl:  memtype: DDR3
MIG: 11:55:14 : 
MIG: 11:55:14 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 11:55:14 : 
MIG: 11:55:14 : 
MIG: 11:55:14 : 
MIG: 11:55:14 : 
MIG: 11:55:14 :  polarity_value: 1
MIG: 11:55:14 : 
MIG: 11:55:14 : 
MIG: 11:55:14 : cntrl:  memtype: DDR3
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 11:55:14 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 11:55:14 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 11:55:14 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 11:55:14 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 11:55:14 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: ECC ==> OFF
MIG: 11:55:14 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 11:55:14 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 11:55:14 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 11:55:14 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 11:55:14 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 11:55:14 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 11:55:14 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 11:55:14 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 11:55:14 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 11:55:14 :  Invalid Param: DDR3_AL ==> "0"
MIG: 11:55:14 :  Invalid Param: DDR3_nAL ==> 0
MIG: 11:55:14 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 11:55:14 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 11:55:14 :  Invalid Param: DDR3_CL ==> 5
MIG: 11:55:14 :  Invalid Param: DDR3_CWL ==> 5
MIG: 11:55:14 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 11:55:14 :  Invalid Param: DDR3_RTT_NOM ==> "60"
MIG: 11:55:14 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 11:55:14 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 11:55:14 : 
MIG: 11:55:14 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 11:55:14 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 11:55:14 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 11:55:14 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 11:55:14 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 11:55:14 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 11:55:14 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 11:55:14 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 11:55:14 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 11:55:14 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 11:55:14 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 11:55:14 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 11:55:14 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 11:55:14 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 11:55:14 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 11:55:14 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 11:55:14 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 11:55:14 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 11:55:14 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 11:55:14 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 11:55:14 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 11:55:14 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 11:55:14 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 11:55:14 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 11:55:14 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 11:55:14 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 11:55:14 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 11:55:14 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 11:55:14 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 11:55:14 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 11:55:14 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 11:55:14 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 11:55:14 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 11:55:14 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 11:55:14 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 11:55:14 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 11:55:14 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 11:55:14 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 11:55:14 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 11:55:14 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 11:55:14 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 11:55:14 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 11:55:14 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 11:55:14 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 11:55:14 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 11:55:14 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 11:55:14 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 11:55:14 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 11:55:14 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 11:55:14 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 11:55:15 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 11:55:15 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 11:55:15 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 11:55:15 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 11:55:15 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 11:55:15 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 11:55:15 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 11:55:15 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 11:55:15 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 11:55:15 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 11:55:15 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 11:55:15 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 11:55:15 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 11:55:15 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 11:55:15 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 11:55:15 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 11:55:15 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 11:55:15 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 11:55:15 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 11:55:15 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 11:55:15 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 11:55:15 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 11:55:15 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 11:55:15 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 11:55:15 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 11:55:15 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 11:55:15 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 11:55:15 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 11:55:15 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 11:55:15 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 11:55:15 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 11:55:15 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 11:55:15 : 
MIG: 11:55:15 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 11:55:15 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 11:55:15 : 
MIG: 11:55:15 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 11:55:15 : 
MIG: 11:55:15 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 11:55:15 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 11:55:15 : 
MIG: 11:55:15 : 
MIG: 11:55:15 : 
MIG: 11:55:15 : Same Interface
MIG: 11:55:17 : ################# RUNNING MIG BATCH ###################
MIG: 11:55:17 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:55:17 : synp_flow:  -- synthesis_mode: Other
MIG: 11:55:17 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:55:17 : vivado_mode: xpg_pa
MIG: 11:55:17 :  locked false  
MIG: 11:55:17 : HDL Language: VHDL
MIG: 11:55:17 : compInfo: false
MIG: 11:55:17 : Vivado Options xc7a100t fgg484 -1
MIG: 11:55:17 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:55:17 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:55:17 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:55:17 : I am in catch area
MIG: 11:55:17 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:55:29 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:55:29 : Component_Name: mig_7series_0
MIG: 11:55:29 : Moving mig_7series_0 ...
MIG: 11:55:29 : Moving mig_7series_0.vho ...
MIG: 11:55:29 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:58:00 : Running synthesis.xit
MIG: 11:58:00 : ################# RUNNING MIG BATCH ###################
MIG: 11:58:00 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:58:01 : synp_flow:  -- synthesis_mode: Other
MIG: 11:58:01 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:58:01 : vivado_mode: xpg_pa
MIG: 11:58:01 :  locked false  
MIG: 11:58:01 : HDL Language: VHDL
MIG: 11:58:01 : compInfo: false
MIG: 11:58:01 : Vivado Options xc7a100t fgg484 -1
MIG: 11:58:01 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:58:01 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:58:01 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:58:01 : I am in catch area
MIG: 11:58:01 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:58:13 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:58:13 : Component_Name: mig_7series_0
MIG: 11:58:13 : Moving mig_7series_0 ...
MIG: 11:58:13 : Moving mig_7series_0.vho ...
MIG: 11:58:13 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:58:13 : Running vhdl_synth_rpr.xit
MIG: 11:58:13 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:58:13 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:58:14 : Running simulation.xit
MIG: 11:58:14 : ################# RUNNING MIG BATCH ###################
MIG: 11:58:14 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 11:58:14 : synp_flow:  -- synthesis_mode: Other
MIG: 11:58:14 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:58:14 : vivado_mode: xpg_pa
MIG: 11:58:14 :  locked false  
MIG: 11:58:14 : HDL Language: VHDL
MIG: 11:58:14 : compInfo: false
MIG: 11:58:14 : Vivado Options xc7a100t fgg484 -1
MIG: 11:58:14 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:58:14 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:58:14 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:58:14 : I am in catch area
MIG: 11:58:14 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:58:26 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:58:26 : Component_Name: mig_7series_0
MIG: 11:58:26 : Moving mig_7series_0 ...
MIG: 11:58:26 : Moving mig_7series_0.vho ...
MIG: 11:58:26 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:58:26 : Running vhdl_sim_rpr.xit
MIG: 11:58:26 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:58:26 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:58:27 : Running implementation.xit
MIG: 11:58:27 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:58:27 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:40:01 : xml_input_file: mig_a.prj
MIG: 12:40:01 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 12:40:01 : xml_input_file: mig_a.prj
MIG: 12:40:01 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 12:40:20 : Running customizer.xit
MIG: 12:40:20 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 12:40:20 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2488-L1/coregen/mig_7series_0
MIG: 12:40:20 : synp_flow:  -- synthesis_mode: Other
MIG: 12:40:20 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2488-L1/coregen/mig_7series_0/_tmp/
MIG: 12:40:20 : vivado_mode: xpg_pa
MIG: 12:40:20 :  locked false  
MIG: 12:40:20 : HDL Language: VHDL
MIG: 12:40:20 : compInfo: false
MIG: 12:40:20 : Vivado Options xc7a100t fgg484 -1
MIG: 12:40:20 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:40:20 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:40:20 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:40:20 : I am in catch area
MIG: 12:40:20 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2488-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2488-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 12:47:22 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 12:47:22 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 12:47:22 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2488-L1/coregen/mig_7series_0/mig_b.prj
MIG: 12:47:22 : Component_Name: mig_7series_0
MIG: 12:47:22 : Moving mig_7series_0 ...
MIG: 12:47:22 : Moving mig_7series_0.vho ...
MIG: 12:47:22 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:47:22 : Sending back 0
MIG: 12:47:24 : xml_input_file: mig_b.prj
MIG: 12:47:24 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:47:24 : xml_input_file: mig_b.prj
MIG: 12:47:24 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:47:24 : In updateAllModelParams
MIG: 12:47:24 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:47:24 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:47:24 : XGUI hdlLanguage: VHDL
MIG: 12:47:24 : xgui vivado_mode: xpg_pa
MIG: 12:47:24 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 12:47:24 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 12:47:24 : 
MIG: 12:47:24 : Inside fn mem: DDR3
MIG: 12:47:24 : Inside fn detect_uiclk: 83333334
MIG: 12:47:24 : cntrl:  memtype: DDR3
MIG: 12:47:24 : 
MIG: 12:47:24 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 12:47:24 : 
MIG: 12:47:24 : 
MIG: 12:47:24 : 
MIG: 12:47:24 : 
MIG: 12:47:24 :  polarity_value: 1
MIG: 12:47:24 : 
MIG: 12:47:24 : 
MIG: 12:47:24 : cntrl:  memtype: DDR3
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 12:47:24 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 12:47:24 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 12:47:24 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 12:47:24 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: ECC ==> OFF
MIG: 12:47:24 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 12:47:24 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 12:47:24 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 12:47:24 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 12:47:24 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 12:47:24 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 12:47:24 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 12:47:24 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 12:47:24 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 12:47:24 :  Invalid Param: DDR3_AL ==> "0"
MIG: 12:47:24 :  Invalid Param: DDR3_nAL ==> 0
MIG: 12:47:24 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 12:47:24 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 12:47:24 :  Invalid Param: DDR3_CL ==> 5
MIG: 12:47:24 :  Invalid Param: DDR3_CWL ==> 5
MIG: 12:47:24 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 12:47:24 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 12:47:24 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 12:47:24 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 12:47:24 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 12:47:24 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 12:47:24 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 12:47:24 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 12:47:24 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 12:47:24 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 12:47:24 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 12:47:24 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 12:47:24 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 12:47:24 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 12:47:24 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 12:47:24 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 12:47:24 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 12:47:24 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 12:47:24 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 12:47:24 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 12:47:24 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 12:47:24 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 12:47:24 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 12:47:24 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 12:47:24 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 12:47:24 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 12:47:24 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 12:47:24 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 12:47:24 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 12:47:24 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 12:47:24 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 12:47:24 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 12:47:24 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 12:47:24 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 12:47:24 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 12:47:24 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 12:47:24 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 12:47:24 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 12:47:24 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 12:47:24 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 12:47:24 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 12:47:24 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 12:47:24 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 12:47:24 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 12:47:24 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 12:47:24 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 12:47:24 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 12:47:24 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 12:47:24 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 12:47:24 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 12:47:24 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 12:47:24 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 12:47:24 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 12:47:24 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 12:47:24 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 12:47:24 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 12:47:24 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 12:47:24 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 12:47:24 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 12:47:24 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 12:47:24 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 12:47:24 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 12:47:24 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 12:47:24 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 12:47:24 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 12:47:24 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 12:47:24 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 12:47:24 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 12:47:24 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 12:47:24 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 12:47:24 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 12:47:24 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 12:47:24 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 12:47:24 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 12:47:24 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 12:47:24 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 12:47:24 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 12:47:24 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 12:47:24 : 
MIG: 12:47:24 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 12:47:24 : 
MIG: 12:47:24 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 12:47:24 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 12:47:24 : 
MIG: 12:47:24 : 
MIG: 12:47:24 : 
MIG: 12:47:24 : Same Interface
MIG: 12:47:26 : ################# RUNNING MIG BATCH ###################
MIG: 12:47:26 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 12:47:26 : synp_flow:  -- synthesis_mode: Other
MIG: 12:47:26 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 12:47:26 : vivado_mode: xpg_pa
MIG: 12:47:26 :  locked false  
MIG: 12:47:26 : HDL Language: VHDL
MIG: 12:47:26 : compInfo: false
MIG: 12:47:26 : Vivado Options xc7a100t fgg484 -1
MIG: 12:47:26 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:47:26 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:47:26 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:47:26 : I am in catch area
MIG: 12:47:26 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 12:47:41 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:47:41 : Component_Name: mig_7series_0
MIG: 12:47:41 : Moving mig_7series_0 ...
MIG: 12:47:41 : Moving mig_7series_0.vho ...
MIG: 12:47:41 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:49:51 : Running synthesis.xit
MIG: 12:49:51 : ################# RUNNING MIG BATCH ###################
MIG: 12:49:51 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 12:49:51 : synp_flow:  -- synthesis_mode: Other
MIG: 12:49:51 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 12:49:51 : vivado_mode: xpg_pa
MIG: 12:49:51 :  locked false  
MIG: 12:49:51 : HDL Language: VHDL
MIG: 12:49:51 : compInfo: false
MIG: 12:49:51 : Vivado Options xc7a100t fgg484 -1
MIG: 12:49:51 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:49:51 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:49:51 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:49:51 : I am in catch area
MIG: 12:49:51 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 12:50:03 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:50:03 : Component_Name: mig_7series_0
MIG: 12:50:03 : Moving mig_7series_0 ...
MIG: 12:50:03 : Moving mig_7series_0.vho ...
MIG: 12:50:03 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:50:04 : Running vhdl_synth_rpr.xit
MIG: 12:50:04 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:50:04 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:50:04 : Running simulation.xit
MIG: 12:50:04 : ################# RUNNING MIG BATCH ###################
MIG: 12:50:04 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0
MIG: 12:50:04 : synp_flow:  -- synthesis_mode: Other
MIG: 12:50:04 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 12:50:04 : vivado_mode: xpg_pa
MIG: 12:50:04 :  locked false  
MIG: 12:50:04 : HDL Language: VHDL
MIG: 12:50:04 : compInfo: false
MIG: 12:50:04 : Vivado Options xc7a100t fgg484 -1
MIG: 12:50:04 : 1: xc7a100t 2: fgg484 3: -1
MIG: 12:50:04 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 12:50:04 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 12:50:04 : I am in catch area
MIG: 12:50:04 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 12:50:17 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000u/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 12:50:17 : Component_Name: mig_7series_0
MIG: 12:50:17 : Moving mig_7series_0 ...
MIG: 12:50:17 : Moving mig_7series_0.vho ...
MIG: 12:50:17 : Moving mig_7series_0_xmdf.tcl ...
MIG: 12:50:17 : Running vhdl_sim_rpr.xit
MIG: 12:50:17 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:50:17 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 12:50:17 : Running implementation.xit
MIG: 12:50:17 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 12:50:17 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 16:11:02 : xml_input_file: mig_b.prj
MIG: 16:11:02 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000z/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 16:11:02 : xml_input_file: mig_b.prj
MIG: 16:11:02 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 000z/project_1/project_1.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:39:51 : xml_input_file: mig_b.prj
MIG: 11:39:51 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:39:51 : xml_input_file: mig_b.prj
MIG: 11:39:51 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:40:09 : Running customizer.xit
MIG: 11:40:09 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 11:40:09 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2816-L1/coregen/mig_7series_0
MIG: 11:40:09 : synp_flow:  -- synthesis_mode: Other
MIG: 11:40:09 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2816-L1/coregen/mig_7series_0/_tmp/
MIG: 11:40:09 : vivado_mode: xpg_pa
MIG: 11:40:09 :  locked false  
MIG: 11:40:09 : HDL Language: VHDL
MIG: 11:40:09 : compInfo: false
MIG: 11:40:09 : Vivado Options xc7a100t fgg484 -1
MIG: 11:40:09 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:40:09 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:40:09 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:40:09 : I am in catch area
MIG: 11:40:09 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2816-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2816-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 11:44:45 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 11:44:45 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 11:44:45 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2816-L1/coregen/mig_7series_0/mig_a.prj
MIG: 11:44:45 : Component_Name: mig_7series_0
MIG: 11:44:45 : Moving mig_7series_0 ...
MIG: 11:44:45 : Moving mig_7series_0.vho ...
MIG: 11:44:45 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:44:45 : Sending back 0
MIG: 11:44:47 : xml_input_file: mig_a.prj
MIG: 11:44:47 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:44:47 : xml_input_file: mig_a.prj
MIG: 11:44:47 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:44:47 : In updateAllModelParams
MIG: 11:44:47 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:44:47 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:44:47 : XGUI hdlLanguage: VHDL
MIG: 11:44:47 : xgui vivado_mode: xpg_pa
MIG: 11:44:47 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 11:44:47 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 11:44:47 : 
MIG: 11:44:47 : Inside fn mem: DDR3
MIG: 11:44:47 : Inside fn detect_uiclk: 83333334
MIG: 11:44:47 : cntrl:  memtype: DDR3
MIG: 11:44:47 : 
MIG: 11:44:47 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 11:44:47 : 
MIG: 11:44:47 : 
MIG: 11:44:47 : 
MIG: 11:44:47 : 
MIG: 11:44:47 :  polarity_value: 1
MIG: 11:44:47 : 
MIG: 11:44:47 : 
MIG: 11:44:47 : cntrl:  memtype: DDR3
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 11:44:47 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 11:44:47 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 11:44:47 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 11:44:47 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: ECC ==> OFF
MIG: 11:44:47 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 11:44:47 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 11:44:47 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 11:44:47 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 11:44:47 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 11:44:47 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 11:44:47 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 11:44:47 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 11:44:47 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 11:44:47 :  Invalid Param: DDR3_AL ==> "0"
MIG: 11:44:47 :  Invalid Param: DDR3_nAL ==> 0
MIG: 11:44:47 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 11:44:47 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 11:44:47 :  Invalid Param: DDR3_CL ==> 5
MIG: 11:44:47 :  Invalid Param: DDR3_CWL ==> 5
MIG: 11:44:47 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 11:44:47 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 11:44:47 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 11:44:47 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 11:44:47 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 11:44:47 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 11:44:47 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 11:44:47 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 11:44:47 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 11:44:47 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 11:44:47 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 11:44:47 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 11:44:47 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 11:44:47 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 11:44:47 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 11:44:47 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 11:44:47 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 11:44:47 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 11:44:47 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 11:44:47 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 11:44:47 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 11:44:47 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 11:44:47 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 11:44:47 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 11:44:47 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 11:44:47 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 11:44:47 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 11:44:47 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 11:44:47 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 11:44:47 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 11:44:47 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 11:44:47 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 11:44:47 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 11:44:47 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 11:44:47 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 11:44:47 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 11:44:47 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 11:44:47 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 11:44:47 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 11:44:47 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 11:44:47 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 11:44:47 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 11:44:47 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 11:44:47 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 11:44:47 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 11:44:47 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 11:44:47 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 11:44:47 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 11:44:47 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 11:44:47 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 11:44:47 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 11:44:47 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 11:44:47 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 11:44:47 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 11:44:47 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 11:44:47 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 11:44:47 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 11:44:47 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 11:44:47 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 11:44:47 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 11:44:47 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 11:44:47 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 11:44:47 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 11:44:47 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 11:44:47 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 11:44:47 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 11:44:47 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 11:44:47 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 11:44:47 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 11:44:47 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 11:44:47 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 11:44:47 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 11:44:47 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 11:44:47 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 11:44:47 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 11:44:47 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 11:44:47 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 11:44:47 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 11:44:47 : 
MIG: 11:44:47 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 11:44:47 : 
MIG: 11:44:47 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 11:44:47 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 11:44:47 : 
MIG: 11:44:47 : 
MIG: 11:44:47 : 
MIG: 11:44:47 : Same Interface
MIG: 11:44:49 : ################# RUNNING MIG BATCH ###################
MIG: 11:44:49 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:44:49 : synp_flow:  -- synthesis_mode: Other
MIG: 11:44:49 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:44:49 : vivado_mode: xpg_pa
MIG: 11:44:49 :  locked false  
MIG: 11:44:49 : HDL Language: VHDL
MIG: 11:44:49 : compInfo: false
MIG: 11:44:49 : Vivado Options xc7a100t fgg484 -1
MIG: 11:44:49 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:44:49 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:44:49 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:44:49 : I am in catch area
MIG: 11:44:49 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:45:01 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:45:01 : Component_Name: mig_7series_0
MIG: 11:45:01 : Moving mig_7series_0 ...
MIG: 11:45:01 : Moving mig_7series_0.vho ...
MIG: 11:45:01 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:45:07 : Running synthesis.xit
MIG: 11:45:07 : ################# RUNNING MIG BATCH ###################
MIG: 11:45:07 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:45:07 : synp_flow:  -- synthesis_mode: Other
MIG: 11:45:07 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:45:07 : vivado_mode: xpg_pa
MIG: 11:45:07 :  locked false  
MIG: 11:45:07 : HDL Language: VHDL
MIG: 11:45:07 : compInfo: false
MIG: 11:45:07 : Vivado Options xc7a100t fgg484 -1
MIG: 11:45:07 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:45:07 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:45:07 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:45:07 : I am in catch area
MIG: 11:45:07 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:45:19 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:45:19 : Component_Name: mig_7series_0
MIG: 11:45:19 : Moving mig_7series_0 ...
MIG: 11:45:19 : Moving mig_7series_0.vho ...
MIG: 11:45:19 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:45:20 : Running vhdl_synth_rpr.xit
MIG: 11:45:20 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:45:20 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:45:20 : Running simulation.xit
MIG: 11:45:20 : ################# RUNNING MIG BATCH ###################
MIG: 11:45:20 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:45:20 : synp_flow:  -- synthesis_mode: Other
MIG: 11:45:20 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:45:20 : vivado_mode: xpg_pa
MIG: 11:45:20 :  locked false  
MIG: 11:45:20 : HDL Language: VHDL
MIG: 11:45:20 : compInfo: false
MIG: 11:45:20 : Vivado Options xc7a100t fgg484 -1
MIG: 11:45:20 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:45:20 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:45:20 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:45:20 : I am in catch area
MIG: 11:45:20 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:45:32 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:45:32 : Component_Name: mig_7series_0
MIG: 11:45:32 : Moving mig_7series_0 ...
MIG: 11:45:32 : Moving mig_7series_0.vho ...
MIG: 11:45:32 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:45:33 : Running vhdl_sim_rpr.xit
MIG: 11:45:33 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:45:33 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:45:33 : Running implementation.xit
MIG: 11:45:33 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:45:33 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:19:30 : xml_input_file: mig_a.prj
MIG: 17:19:30 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 17:19:30 : xml_input_file: mig_a.prj
MIG: 17:19:30 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 17:19:48 : Running customizer.xit
MIG: 17:19:49 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 17:19:49 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5076-L1/coregen/mig_7series_0
MIG: 17:19:49 : synp_flow:  -- synthesis_mode: Other
MIG: 17:19:49 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5076-L1/coregen/mig_7series_0/_tmp/
MIG: 17:19:49 : vivado_mode: xpg_pa
MIG: 17:19:49 :  locked false  
MIG: 17:19:49 : HDL Language: VHDL
MIG: 17:19:49 : compInfo: false
MIG: 17:19:49 : Vivado Options xc7a100t fgg484 -1
MIG: 17:19:49 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:19:49 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:19:49 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:19:49 : I am in catch area
MIG: 17:19:49 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5076-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5076-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 17:21:28 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 17:21:28 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 17:21:28 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5076-L1/coregen/mig_7series_0/mig_b.prj
MIG: 17:21:28 : Component_Name: mig_7series_0
MIG: 17:21:28 : Moving mig_7series_0 ...
MIG: 17:21:28 : Moving mig_7series_0.vho ...
MIG: 17:21:28 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:21:28 : Sending back 0
MIG: 17:21:30 : xml_input_file: mig_b.prj
MIG: 17:21:30 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:21:30 : xml_input_file: mig_b.prj
MIG: 17:21:30 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:21:30 : In updateAllModelParams
MIG: 17:21:30 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:21:30 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:21:30 : XGUI hdlLanguage: VHDL
MIG: 17:21:30 : xgui vivado_mode: xpg_pa
MIG: 17:21:30 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 17:21:30 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 17:21:30 : 
MIG: 17:21:30 : Inside fn mem: DDR3
MIG: 17:21:30 : Inside fn detect_uiclk: 83333334
MIG: 17:21:30 : cntrl:  memtype: DDR3
MIG: 17:21:30 : 
MIG: 17:21:30 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 17:21:30 : 
MIG: 17:21:30 : 
MIG: 17:21:30 : 
MIG: 17:21:30 : 
MIG: 17:21:30 :  polarity_value: 1
MIG: 17:21:30 : 
MIG: 17:21:30 : 
MIG: 17:21:30 : cntrl:  memtype: DDR3
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 17:21:30 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 17:21:30 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 17:21:30 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 17:21:30 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: ECC ==> OFF
MIG: 17:21:30 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 17:21:30 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 17:21:30 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 17:21:30 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 17:21:30 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 17:21:30 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 17:21:30 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 17:21:30 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 17:21:30 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 17:21:30 :  Invalid Param: DDR3_AL ==> "0"
MIG: 17:21:30 :  Invalid Param: DDR3_nAL ==> 0
MIG: 17:21:30 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 17:21:30 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 17:21:30 :  Invalid Param: DDR3_CL ==> 5
MIG: 17:21:30 :  Invalid Param: DDR3_CWL ==> 5
MIG: 17:21:30 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 17:21:30 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 17:21:30 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 17:21:30 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 17:21:30 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 17:21:30 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 17:21:30 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 17:21:30 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 17:21:30 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 17:21:30 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 17:21:30 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 17:21:30 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 17:21:30 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 17:21:30 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 17:21:30 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 17:21:30 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 17:21:30 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 17:21:30 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 17:21:30 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 17:21:30 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 17:21:30 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 17:21:30 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 17:21:30 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 17:21:30 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 17:21:30 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 17:21:30 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 17:21:30 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 17:21:30 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 17:21:30 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 17:21:30 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 17:21:30 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 17:21:30 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 17:21:30 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 17:21:30 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 17:21:30 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 17:21:30 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 17:21:30 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 17:21:30 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 17:21:30 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 17:21:30 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 17:21:30 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 17:21:30 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 17:21:30 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 17:21:30 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 17:21:30 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 17:21:30 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 17:21:30 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 17:21:30 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 17:21:30 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 17:21:30 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 17:21:30 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 17:21:30 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 17:21:30 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 17:21:30 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 17:21:30 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 17:21:30 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 17:21:30 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 17:21:30 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 17:21:30 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 17:21:30 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 17:21:30 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 17:21:30 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 17:21:30 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 17:21:30 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 17:21:30 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 17:21:30 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 17:21:30 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 17:21:30 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 17:21:30 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 17:21:30 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 17:21:30 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 17:21:30 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 17:21:30 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 17:21:30 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 17:21:30 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 17:21:30 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 17:21:30 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 17:21:30 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 17:21:30 : 
MIG: 17:21:30 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 17:21:30 : 
MIG: 17:21:30 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 17:21:30 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 17:21:30 : 
MIG: 17:21:30 : 
MIG: 17:21:30 : 
MIG: 17:21:30 : Same Interface
MIG: 17:21:32 : ################# RUNNING MIG BATCH ###################
MIG: 17:21:32 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 17:21:32 : synp_flow:  -- synthesis_mode: Other
MIG: 17:21:32 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:21:32 : vivado_mode: xpg_pa
MIG: 17:21:32 :  locked false  
MIG: 17:21:32 : HDL Language: VHDL
MIG: 17:21:32 : compInfo: false
MIG: 17:21:32 : Vivado Options xc7a100t fgg484 -1
MIG: 17:21:32 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:21:32 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:21:32 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:21:32 : I am in catch area
MIG: 17:21:32 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 17:21:44 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:21:44 : Component_Name: mig_7series_0
MIG: 17:21:44 : Moving mig_7series_0 ...
MIG: 17:21:44 : Moving mig_7series_0.vho ...
MIG: 17:21:44 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:21:49 : Running synthesis.xit
MIG: 17:21:49 : ################# RUNNING MIG BATCH ###################
MIG: 17:21:49 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 17:21:49 : synp_flow:  -- synthesis_mode: Other
MIG: 17:21:49 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:21:49 : vivado_mode: xpg_pa
MIG: 17:21:49 :  locked false  
MIG: 17:21:49 : HDL Language: VHDL
MIG: 17:21:49 : compInfo: false
MIG: 17:21:49 : Vivado Options xc7a100t fgg484 -1
MIG: 17:21:49 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:21:49 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:21:49 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:21:49 : I am in catch area
MIG: 17:21:49 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 17:22:01 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:22:01 : Component_Name: mig_7series_0
MIG: 17:22:01 : Moving mig_7series_0 ...
MIG: 17:22:01 : Moving mig_7series_0.vho ...
MIG: 17:22:01 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:22:01 : Running vhdl_synth_rpr.xit
MIG: 17:22:01 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:22:01 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:22:01 : Running simulation.xit
MIG: 17:22:01 : ################# RUNNING MIG BATCH ###################
MIG: 17:22:01 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 17:22:01 : synp_flow:  -- synthesis_mode: Other
MIG: 17:22:01 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:22:01 : vivado_mode: xpg_pa
MIG: 17:22:01 :  locked false  
MIG: 17:22:01 : HDL Language: VHDL
MIG: 17:22:01 : compInfo: false
MIG: 17:22:01 : Vivado Options xc7a100t fgg484 -1
MIG: 17:22:01 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:22:01 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:22:01 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:22:01 : I am in catch area
MIG: 17:22:01 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 17:22:13 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:22:13 : Component_Name: mig_7series_0
MIG: 17:22:13 : Moving mig_7series_0 ...
MIG: 17:22:13 : Moving mig_7series_0.vho ...
MIG: 17:22:13 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:22:14 : Running vhdl_sim_rpr.xit
MIG: 17:22:14 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:22:14 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:22:14 : Running implementation.xit
MIG: 17:22:14 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:22:14 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:41:45 : xml_input_file: mig_b.prj
MIG: 11:41:45 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:41:45 : xml_input_file: mig_b.prj
MIG: 11:41:45 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 11:42:04 : Running customizer.xit
MIG: 11:42:05 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 11:42:05 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3444-L1/coregen/mig_7series_0
MIG: 11:42:05 : synp_flow:  -- synthesis_mode: Other
MIG: 11:42:05 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3444-L1/coregen/mig_7series_0/_tmp/
MIG: 11:42:05 : vivado_mode: xpg_pa
MIG: 11:42:05 :  locked false  
MIG: 11:42:05 : HDL Language: VHDL
MIG: 11:42:05 : compInfo: false
MIG: 11:42:05 : Vivado Options xc7a100t fgg484 -1
MIG: 11:42:05 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:42:05 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:42:05 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:42:05 : I am in catch area
MIG: 11:42:05 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3444-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3444-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 11:43:05 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 11:43:05 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 11:43:05 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3444-L1/coregen/mig_7series_0/mig_a.prj
MIG: 11:43:05 : Component_Name: mig_7series_0
MIG: 11:43:05 : Moving mig_7series_0 ...
MIG: 11:43:05 : Moving mig_7series_0.vho ...
MIG: 11:43:05 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:43:05 : Sending back 0
MIG: 11:43:07 : xml_input_file: mig_a.prj
MIG: 11:43:07 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:43:07 : xml_input_file: mig_a.prj
MIG: 11:43:07 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:43:07 : In updateAllModelParams
MIG: 11:43:07 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:43:07 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:43:07 : XGUI hdlLanguage: VHDL
MIG: 11:43:07 : xgui vivado_mode: xpg_pa
MIG: 11:43:07 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 11:43:07 : Reading C:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 11:43:07 : 
MIG: 11:43:07 : Inside fn mem: DDR3
MIG: 11:43:07 : Inside fn detect_uiclk: 83333334
MIG: 11:43:07 : cntrl:  memtype: DDR3
MIG: 11:43:07 : 
MIG: 11:43:07 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 11:43:07 : 
MIG: 11:43:07 : 
MIG: 11:43:07 : 
MIG: 11:43:07 : 
MIG: 11:43:07 :  polarity_value: 1
MIG: 11:43:07 : 
MIG: 11:43:07 : 
MIG: 11:43:07 : cntrl:  memtype: DDR3
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 11:43:07 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 11:43:07 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 11:43:07 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 11:43:07 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: ECC ==> OFF
MIG: 11:43:07 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 11:43:07 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 11:43:07 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 11:43:07 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 11:43:07 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 11:43:07 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 11:43:07 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 11:43:07 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 11:43:07 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 11:43:07 :  Invalid Param: DDR3_AL ==> "0"
MIG: 11:43:07 :  Invalid Param: DDR3_nAL ==> 0
MIG: 11:43:07 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 11:43:07 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 11:43:07 :  Invalid Param: DDR3_CL ==> 5
MIG: 11:43:07 :  Invalid Param: DDR3_CWL ==> 5
MIG: 11:43:07 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 11:43:07 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 11:43:07 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 11:43:07 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 11:43:07 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 11:43:07 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 11:43:07 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 11:43:07 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 11:43:07 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 11:43:07 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 11:43:07 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 11:43:07 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 11:43:07 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 11:43:07 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 11:43:07 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 11:43:07 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 11:43:07 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 11:43:07 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 11:43:07 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 11:43:07 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 11:43:07 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 11:43:07 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 11:43:07 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 11:43:07 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 11:43:07 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 11:43:07 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 11:43:07 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 11:43:07 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 11:43:07 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 11:43:07 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 11:43:07 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 11:43:07 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 11:43:07 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 11:43:07 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 11:43:07 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 11:43:07 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 11:43:07 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 11:43:07 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 11:43:07 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 11:43:07 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 11:43:07 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 11:43:07 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 11:43:07 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 11:43:07 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 11:43:07 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 11:43:07 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 11:43:07 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 11:43:07 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 11:43:07 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 11:43:07 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 11:43:07 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 11:43:07 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 11:43:07 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 11:43:07 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 11:43:07 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 11:43:07 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 11:43:07 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 11:43:07 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 11:43:07 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 11:43:07 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 11:43:07 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 11:43:07 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 11:43:07 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 11:43:07 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 11:43:07 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 11:43:07 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 11:43:07 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 11:43:07 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 11:43:07 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 11:43:07 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 11:43:07 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 11:43:07 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 11:43:07 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 11:43:07 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 11:43:07 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 11:43:07 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 11:43:07 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 11:43:07 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 11:43:07 : 
MIG: 11:43:07 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 11:43:07 : 
MIG: 11:43:07 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 11:43:07 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 11:43:07 : 
MIG: 11:43:07 : 
MIG: 11:43:07 : 
MIG: 11:43:07 : Same Interface
MIG: 11:43:09 : ################# RUNNING MIG BATCH ###################
MIG: 11:43:09 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:43:09 : synp_flow:  -- synthesis_mode: Other
MIG: 11:43:09 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:43:09 : vivado_mode: xpg_pa
MIG: 11:43:09 :  locked false  
MIG: 11:43:09 : HDL Language: VHDL
MIG: 11:43:09 : compInfo: false
MIG: 11:43:09 : Vivado Options xc7a100t fgg484 -1
MIG: 11:43:09 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:43:09 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:43:09 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:43:09 : I am in catch area
MIG: 11:43:09 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:43:21 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:43:21 : Component_Name: mig_7series_0
MIG: 11:43:21 : Moving mig_7series_0 ...
MIG: 11:43:21 : Moving mig_7series_0.vho ...
MIG: 11:43:21 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:43:31 : Running synthesis.xit
MIG: 11:43:31 : ################# RUNNING MIG BATCH ###################
MIG: 11:43:31 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:43:31 : synp_flow:  -- synthesis_mode: Other
MIG: 11:43:31 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:43:31 : vivado_mode: xpg_pa
MIG: 11:43:31 :  locked false  
MIG: 11:43:31 : HDL Language: VHDL
MIG: 11:43:31 : compInfo: false
MIG: 11:43:31 : Vivado Options xc7a100t fgg484 -1
MIG: 11:43:31 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:43:31 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:43:31 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:43:31 : I am in catch area
MIG: 11:43:31 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:43:43 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:43:43 : Component_Name: mig_7series_0
MIG: 11:43:43 : Moving mig_7series_0 ...
MIG: 11:43:43 : Moving mig_7series_0.vho ...
MIG: 11:43:44 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:43:44 : Running vhdl_synth_rpr.xit
MIG: 11:43:44 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:43:44 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:43:44 : Running simulation.xit
MIG: 11:43:44 : ################# RUNNING MIG BATCH ###################
MIG: 11:43:44 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:43:44 : synp_flow:  -- synthesis_mode: Other
MIG: 11:43:44 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:43:44 : vivado_mode: xpg_pa
MIG: 11:43:44 :  locked false  
MIG: 11:43:44 : HDL Language: VHDL
MIG: 11:43:44 : compInfo: false
MIG: 11:43:44 : Vivado Options xc7a100t fgg484 -1
MIG: 11:43:44 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:43:44 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:43:44 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:43:44 : I am in catch area
MIG: 11:43:44 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:43:56 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001b/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:43:56 : Component_Name: mig_7series_0
MIG: 11:43:56 : Moving mig_7series_0 ...
MIG: 11:43:57 : Moving mig_7series_0.vho ...
MIG: 11:43:57 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:43:57 : Running vhdl_sim_rpr.xit
MIG: 11:43:57 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:43:57 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:43:57 : Running implementation.xit
MIG: 11:43:57 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:43:57 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:14:34 : Running synthesis.xit
MIG: 11:14:34 : ################# RUNNING MIG BATCH ###################
MIG: 11:14:34 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001e/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:14:34 : synp_flow:  -- synthesis_mode: Other
MIG: 11:14:34 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001e/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:14:34 : vivado_mode: xpg_pa
MIG: 11:14:34 :  locked false  
MIG: 11:14:34 : HDL Language: VHDL
MIG: 11:14:34 : compInfo: false
MIG: 11:14:34 : Vivado Options xc7a100t fgg484 -1
MIG: 11:14:34 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:14:34 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:14:34 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:14:34 : I am in catch area
MIG: 11:14:34 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001e/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001e/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:14:50 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001e/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:14:50 : Component_Name: mig_7series_0
MIG: 11:14:50 : Moving mig_7series_0 ...
MIG: 11:14:50 : Moving mig_7series_0.vho ...
MIG: 11:14:50 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:14:51 : Running vhdl_synth_rpr.xit
MIG: 11:14:51 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:14:51 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:14:51 : Running implementation.xit
MIG: 11:14:51 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:14:51 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:06:00 : Running synthesis.xit
MIG: 11:06:01 : ################# RUNNING MIG BATCH ###################
MIG: 11:06:01 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001h/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 11:06:01 : synp_flow:  -- synthesis_mode: Other
MIG: 11:06:01 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001h/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 11:06:01 : vivado_mode: xpg_pa
MIG: 11:06:01 :  locked false  
MIG: 11:06:01 : HDL Language: VHDL
MIG: 11:06:01 : compInfo: false
MIG: 11:06:01 : Vivado Options xc7a100t fgg484 -1
MIG: 11:06:01 : 1: xc7a100t 2: fgg484 3: -1
MIG: 11:06:01 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 11:06:01 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 11:06:01 : I am in catch area
MIG: 11:06:01 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001h/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001h/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 11:06:13 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1806 data acquisition playback 001h/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 11:06:13 : Component_Name: mig_7series_0
MIG: 11:06:13 : Moving mig_7series_0 ...
MIG: 11:06:13 : Moving mig_7series_0.vho ...
MIG: 11:06:13 : Moving mig_7series_0_xmdf.tcl ...
MIG: 11:06:13 : Running vhdl_synth_rpr.xit
MIG: 11:06:13 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:06:13 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 11:06:14 : Running implementation.xit
MIG: 11:06:14 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 11:06:14 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:33:50 : xml_input_file: mig_a.prj
MIG: 17:33:50 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 17:33:50 : xml_input_file: mig_a.prj
MIG: 17:33:50 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 17:34:18 : Running customizer.xit
MIG: 17:34:18 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 17:34:18 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5544-L1/coregen/mig_7series_0
MIG: 17:34:18 : synp_flow:  -- synthesis_mode: Other
MIG: 17:34:18 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5544-L1/coregen/mig_7series_0/_tmp/
MIG: 17:34:18 : vivado_mode: xpg_pa
MIG: 17:34:18 :  locked false  
MIG: 17:34:18 : HDL Language: VHDL
MIG: 17:34:18 : compInfo: false
MIG: 17:34:18 : Vivado Options xc7a100t fgg484 -1
MIG: 17:34:18 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:34:18 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:34:18 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:34:18 : I am in catch area
MIG: 17:34:18 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5544-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5544-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 17:36:43 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 17:36:43 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 17:36:43 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-5544-L1/coregen/mig_7series_0/mig_b.prj
MIG: 17:36:43 : Component_Name: mig_7series_0
MIG: 17:36:43 : Moving mig_7series_0 ...
MIG: 17:36:43 : Moving mig_7series_0.vho ...
MIG: 17:36:43 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:36:43 : Sending back 0
MIG: 17:36:44 : xml_input_file: mig_b.prj
MIG: 17:36:44 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:36:44 : xml_input_file: mig_b.prj
MIG: 17:36:44 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:36:44 : In updateAllModelParams
MIG: 17:36:44 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:36:44 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:36:44 : XGUI hdlLanguage: VHDL
MIG: 17:36:44 : xgui vivado_mode: xpg_pa
MIG: 17:36:44 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 17:36:44 : Reading C:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 17:36:45 : 
MIG: 17:36:45 : Inside fn mem: DDR3
MIG: 17:36:45 : Inside fn detect_uiclk: 83333334
MIG: 17:36:45 : cntrl:  memtype: DDR3
MIG: 17:36:45 : 
MIG: 17:36:45 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 17:36:45 : 
MIG: 17:36:45 : 
MIG: 17:36:45 : 
MIG: 17:36:45 : 
MIG: 17:36:45 :  polarity_value: 1
MIG: 17:36:45 : 
MIG: 17:36:45 : 
MIG: 17:36:45 : cntrl:  memtype: DDR3
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 17:36:45 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 17:36:45 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 17:36:45 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 17:36:45 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: ECC ==> OFF
MIG: 17:36:45 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 17:36:45 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 17:36:45 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 17:36:45 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 17:36:45 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 17:36:45 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 17:36:45 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 17:36:45 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 17:36:45 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 17:36:45 :  Invalid Param: DDR3_AL ==> "0"
MIG: 17:36:45 :  Invalid Param: DDR3_nAL ==> 0
MIG: 17:36:45 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 17:36:45 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 17:36:45 :  Invalid Param: DDR3_CL ==> 5
MIG: 17:36:45 :  Invalid Param: DDR3_CWL ==> 5
MIG: 17:36:45 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 17:36:45 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 17:36:45 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 17:36:45 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 17:36:45 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 17:36:45 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 17:36:45 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 17:36:45 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 17:36:45 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 17:36:45 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 17:36:45 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 17:36:45 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 17:36:45 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 17:36:45 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 17:36:45 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 17:36:45 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 17:36:45 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 17:36:45 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 17:36:45 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 17:36:45 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 17:36:45 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 17:36:45 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 17:36:45 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 17:36:45 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 17:36:45 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 17:36:45 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 17:36:45 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 17:36:45 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 17:36:45 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 17:36:45 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 17:36:45 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 17:36:45 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 17:36:45 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 17:36:45 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 17:36:45 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 17:36:45 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 17:36:45 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 17:36:45 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 17:36:45 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 17:36:45 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 17:36:45 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 17:36:45 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 17:36:45 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 17:36:45 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 17:36:45 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 17:36:45 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 17:36:45 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 17:36:45 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 17:36:45 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 17:36:45 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 17:36:45 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 17:36:45 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 17:36:45 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 17:36:45 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "DEFAULT"
MIG: 17:36:45 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 17:36:45 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 17:36:45 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 17:36:45 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 17:36:45 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 17:36:45 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 17:36:45 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 17:36:45 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 17:36:45 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 17:36:45 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 17:36:45 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 17:36:45 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 17:36:45 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 17:36:45 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 17:36:45 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 17:36:45 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 17:36:45 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 17:36:45 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 17:36:45 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 17:36:45 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 17:36:45 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 17:36:45 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 17:36:45 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 17:36:45 : 
MIG: 17:36:45 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 17:36:45 : 
MIG: 17:36:45 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 17:36:45 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 17:36:45 : 
MIG: 17:36:45 : 
MIG: 17:36:45 : 
MIG: 17:36:45 : Same Interface
MIG: 17:36:47 : ################# RUNNING MIG BATCH ###################
MIG: 17:36:47 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 17:36:47 : synp_flow:  -- synthesis_mode: Other
MIG: 17:36:47 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:36:47 : vivado_mode: xpg_pa
MIG: 17:36:47 :  locked false  
MIG: 17:36:47 : HDL Language: VHDL
MIG: 17:36:47 : compInfo: false
MIG: 17:36:47 : Vivado Options xc7a100t fgg484 -1
MIG: 17:36:47 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:36:47 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:36:47 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:36:47 : I am in catch area
MIG: 17:36:47 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 17:36:59 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:36:59 : Component_Name: mig_7series_0
MIG: 17:36:59 : Moving mig_7series_0 ...
MIG: 17:36:59 : Moving mig_7series_0.vho ...
MIG: 17:36:59 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:43:45 : Running synthesis.xit
MIG: 17:43:45 : ################# RUNNING MIG BATCH ###################
MIG: 17:43:45 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 17:43:45 : synp_flow:  -- synthesis_mode: Other
MIG: 17:43:45 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:43:45 : vivado_mode: xpg_pa
MIG: 17:43:45 :  locked false  
MIG: 17:43:45 : HDL Language: VHDL
MIG: 17:43:45 : compInfo: false
MIG: 17:43:45 : Vivado Options xc7a100t fgg484 -1
MIG: 17:43:45 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:43:45 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:43:45 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:43:45 : I am in catch area
MIG: 17:43:45 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 17:43:57 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:43:57 : Component_Name: mig_7series_0
MIG: 17:43:57 : Moving mig_7series_0 ...
MIG: 17:43:57 : Moving mig_7series_0.vho ...
MIG: 17:43:57 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:43:58 : Running vhdl_synth_rpr.xit
MIG: 17:43:58 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:43:58 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:43:58 : Running simulation.xit
MIG: 17:43:58 : ################# RUNNING MIG BATCH ###################
MIG: 17:43:58 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 17:43:58 : synp_flow:  -- synthesis_mode: Other
MIG: 17:43:58 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 17:43:58 : vivado_mode: xpg_pa
MIG: 17:43:58 :  locked false  
MIG: 17:43:58 : HDL Language: VHDL
MIG: 17:43:58 : compInfo: false
MIG: 17:43:58 : Vivado Options xc7a100t fgg484 -1
MIG: 17:43:58 : 1: xc7a100t 2: fgg484 3: -1
MIG: 17:43:58 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 17:43:58 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 17:43:58 : I am in catch area
MIG: 17:43:58 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 17:44:10 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 17:44:10 : Component_Name: mig_7series_0
MIG: 17:44:10 : Moving mig_7series_0 ...
MIG: 17:44:10 : Moving mig_7series_0.vho ...
MIG: 17:44:10 : Moving mig_7series_0_xmdf.tcl ...
MIG: 17:44:11 : Running vhdl_sim_rpr.xit
MIG: 17:44:11 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:44:11 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 17:44:11 : Running implementation.xit
MIG: 17:44:12 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 17:44:12 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:05:37 : xml_input_file: mig_b.prj
MIG: 13:05:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 13:05:37 : xml_input_file: mig_b.prj
MIG: 13:05:37 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 13:06:04 : Running customizer.xit
MIG: 13:06:04 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 13:06:04 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6076-L1/coregen/mig_7series_0
MIG: 13:06:04 : synp_flow:  -- synthesis_mode: Other
MIG: 13:06:04 : outputDirectory: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6076-L1/coregen/mig_7series_0/_tmp/
MIG: 13:06:04 : vivado_mode: xpg_pa
MIG: 13:06:04 :  locked false  
MIG: 13:06:04 : HDL Language: VHDL
MIG: 13:06:04 : compInfo: false
MIG: 13:06:04 : Vivado Options xc7a100t fgg484 -1
MIG: 13:06:04 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:06:04 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:06:04 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:06:04 : I am in catch area
MIG: 13:06:04 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6076-L1/coregen/mig_7series_0/xil_txt.in -cg_exc_out c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6076-L1/coregen/mig_7series_0/xil_txt.out ... 
MIG: 13:12:05 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 13:12:05 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 13:12:05 : XML_INPUT_FILE: c:/Users/Alain/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6076-L1/coregen/mig_7series_0/mig_a.prj
MIG: 13:12:05 : Component_Name: mig_7series_0
MIG: 13:12:05 : Moving mig_7series_0 ...
MIG: 13:12:05 : Moving mig_7series_0.vho ...
MIG: 13:12:05 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:12:05 : Sending back 0
MIG: 13:12:06 : xml_input_file: mig_a.prj
MIG: 13:12:06 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:12:06 : xml_input_file: mig_a.prj
MIG: 13:12:06 : Absolute path of xml_input_file: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:12:06 : In updateAllModelParams
MIG: 13:12:06 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:12:06 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:12:06 : XGUI hdlLanguage: VHDL
MIG: 13:12:06 : xgui vivado_mode: xpg_pa
MIG: 13:12:06 : xgui hdlLanguage: VHDL -- hdlExt: vhd
MIG: 13:12:06 : Reading C:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.vhd ...
MIG: 13:12:07 : 
MIG: 13:12:07 : Inside fn mem: DDR3
MIG: 13:12:07 : Inside fn detect_uiclk: 83333334
MIG: 13:12:07 : cntrl:  memtype: DDR3
MIG: 13:12:07 : 
MIG: 13:12:07 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 666 
MIG: 13:12:07 : 
MIG: 13:12:07 : 
MIG: 13:12:07 : 
MIG: 13:12:07 : 
MIG: 13:12:07 :  polarity_value: 1
MIG: 13:12:07 : 
MIG: 13:12:07 : 
MIG: 13:12:07 : cntrl:  memtype: DDR3
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 13:12:07 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 13:12:07 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 6
MIG: 13:12:07 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_DM_WIDTH ==> 8
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_DQ_WIDTH ==> 64
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_DQS_WIDTH ==> 8
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 3
MIG: 13:12:07 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: ECC ==> OFF
MIG: 13:12:07 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_DATA_WIDTH ==> 64
MIG: 13:12:07 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> 64
MIG: 13:12:07 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 13:12:07 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 13:12:07 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_USE_CS_PORT ==> 1
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 13:12:07 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 1
MIG: 13:12:07 :  Invalid Param: DDR3_MEM_DENSITY ==> "1Gb"
MIG: 13:12:07 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "15E"
MIG: 13:12:07 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 8
MIG: 13:12:07 :  Invalid Param: DDR3_AL ==> "0"
MIG: 13:12:07 :  Invalid Param: DDR3_nAL ==> 0
MIG: 13:12:07 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 13:12:07 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 13:12:07 :  Invalid Param: DDR3_CL ==> 5
MIG: 13:12:07 :  Invalid Param: DDR3_CWL ==> 5
MIG: 13:12:07 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 13:12:07 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 13:12:07 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 13:12:07 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 13:12:07 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 3000
MIG: 13:12:07 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 4
MIG: 13:12:07 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 13:12:07 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 0.0
MIG: 13:12:07 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 13:12:07 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 4
MIG: 13:12:07 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 64
MIG: 13:12:07 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 16
MIG: 13:12:07 :  Invalid Param: DDR3_MMCM_VCO ==> 666
MIG: 13:12:07 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 13:12:07 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 13:12:07 :  Invalid Param: DDR3_tCKE ==> 5625
MIG: 13:12:07 :  Invalid Param: DDR3_tFAW ==> 30000
MIG: 13:12:07 :  Invalid Param: DDR3_tPRDI ==> 1000000
MIG: 13:12:07 :  Invalid Param: DDR3_tRAS ==> 36000
MIG: 13:12:07 :  Invalid Param: DDR3_tRCD ==> 13500
MIG: 13:12:07 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 13:12:07 :  Invalid Param: DDR3_tRFC ==> 110000
MIG: 13:12:07 :  Invalid Param: DDR3_tRP ==> 13500
MIG: 13:12:07 :  Invalid Param: DDR3_tRRD ==> 6000
MIG: 13:12:07 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 13:12:07 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 13:12:07 :  Invalid Param: DDR3_tZQI ==> 128000000
MIG: 13:12:07 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 13:12:07 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 13:12:07 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> "1111"
MIG: 13:12:07 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> "1111"
MIG: 13:12:07 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> "0111"
MIG: 13:12:07 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> "0000"
MIG: 13:12:07 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> "0000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_CTL_B0 ==> "1111"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_CTL_B1 ==> "0001"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_CTL_B2 ==> "0111"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_CTL_B3 ==> "0000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_CTL_B4 ==> "0000"
MIG: 13:12:07 :  Invalid Param: DDR3_PHY_0_BITLANES ==> X"3FE3FE3FE2FF"
MIG: 13:12:07 :  Invalid Param: DDR3_PHY_1_BITLANES ==> X"43EFFFC2A2FF"
MIG: 13:12:07 :  Invalid Param: DDR3_PHY_2_BITLANES ==> X"0003FE3FE2FF"
MIG: 13:12:07 :  Invalid Param: DDR3_CK_BYTE_MAP ==> X"000000000000000000000000000000000013"
MIG: 13:12:07 :  Invalid Param: DDR3_ADDR_MAP ==> X"00000013A13513413313213112912812712612B12A125124"
MIG: 13:12:07 :  Invalid Param: DDR3_BANK_MAP ==> X"123122121"
MIG: 13:12:07 :  Invalid Param: DDR3_CAS_MAP ==> X"11B"
MIG: 13:12:07 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> X"00"
MIG: 13:12:07 :  Invalid Param: DDR3_CKE_MAP ==> X"000000000000000000000113"
MIG: 13:12:07 :  Invalid Param: DDR3_ODT_MAP ==> X"000000000000000000000111"
MIG: 13:12:07 :  Invalid Param: DDR3_CS_MAP ==> X"000000000000000000000000000115"
MIG: 13:12:07 :  Invalid Param: DDR3_PARITY_MAP ==> X"000"
MIG: 13:12:07 :  Invalid Param: DDR3_RAS_MAP ==> X"120"
MIG: 13:12:07 :  Invalid Param: DDR3_WE_MAP ==> X"11A"
MIG: 13:12:07 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> X"000000000000000000002021221000010203"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA0_MAP ==> X"031032033034035036037038"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA1_MAP ==> X"021022023024025026027028"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA2_MAP ==> X"011012013014016017018019"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA3_MAP ==> X"000001002003004005006007"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA4_MAP ==> X"100101102103104105106107"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA5_MAP ==> X"221222223224225226227228"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA6_MAP ==> X"211212213214216217218219"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA7_MAP ==> X"200201202203204205206207"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA8_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA9_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA10_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA11_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA12_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA13_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA14_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA15_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA16_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA17_MAP ==> X"000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_MASK0_MAP ==> X"000209215229109009015029039"
MIG: 13:12:07 :  Invalid Param: DDR3_MASK1_MAP ==> X"000000000000000000000000000"
MIG: 13:12:07 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> "00000001"
MIG: 13:12:07 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> "00000000"
MIG: 13:12:07 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 13:12:07 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 13:12:07 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 13:12:07 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 13:12:07 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 13:12:07 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 13:12:07 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> X"0000"
MIG: 13:12:07 :  Invalid Param: DDR3_CALIB_COL_ADD ==> X"000"
MIG: 13:12:07 :  Invalid Param: DDR3_CALIB_BA_ADD ==> "000"
MIG: 13:12:07 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 13:12:07 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 13:12:07 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 13:12:07 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 13:12:07 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 13:12:07 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 13:12:07 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 13:12:07 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 13:12:07 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 13:12:07 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 13:12:07 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 13:12:07 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 13:12:07 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 13:12:07 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 13:12:07 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 13:12:07 :  Invalid Param: DDR3_tCK ==> 3000
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 13:12:07 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 13:12:07 : 
MIG: 13:12:07 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 13:12:07 : 
MIG: 13:12:07 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
MIG: 13:12:07 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 13:12:07 : 
MIG: 13:12:07 : 
MIG: 13:12:07 : 
MIG: 13:12:07 : Same Interface
MIG: 13:12:09 : ################# RUNNING MIG BATCH ###################
MIG: 13:12:09 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 13:12:09 : synp_flow:  -- synthesis_mode: Other
MIG: 13:12:09 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:12:09 : vivado_mode: xpg_pa
MIG: 13:12:09 :  locked false  
MIG: 13:12:09 : HDL Language: VHDL
MIG: 13:12:09 : compInfo: false
MIG: 13:12:09 : Vivado Options xc7a100t fgg484 -1
MIG: 13:12:09 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:12:09 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:12:09 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:12:09 : I am in catch area
MIG: 13:12:09 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 13:12:21 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:12:21 : Component_Name: mig_7series_0
MIG: 13:12:21 : Moving mig_7series_0 ...
MIG: 13:12:21 : Moving mig_7series_0.vho ...
MIG: 13:12:21 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:12:29 : Running synthesis.xit
MIG: 13:12:29 : ################# RUNNING MIG BATCH ###################
MIG: 13:12:29 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 13:12:29 : synp_flow:  -- synthesis_mode: Other
MIG: 13:12:29 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:12:29 : vivado_mode: xpg_pa
MIG: 13:12:29 :  locked false  
MIG: 13:12:29 : HDL Language: VHDL
MIG: 13:12:29 : compInfo: false
MIG: 13:12:29 : Vivado Options xc7a100t fgg484 -1
MIG: 13:12:29 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:12:29 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:12:29 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:12:29 : I am in catch area
MIG: 13:12:29 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 13:12:41 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:12:41 : Component_Name: mig_7series_0
MIG: 13:12:41 : Moving mig_7series_0 ...
MIG: 13:12:41 : Moving mig_7series_0.vho ...
MIG: 13:12:41 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:12:42 : Running vhdl_synth_rpr.xit
MIG: 13:12:42 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:12:42 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:12:42 : Running simulation.xit
MIG: 13:12:42 : ################# RUNNING MIG BATCH ###################
MIG: 13:12:43 : Writing IN file for 'mig_7series_0'...compDirPath: c:/Xilinx/Vivado/2015.2/data/ip/xilinx/mig_7series_v2_3... instDirPath: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0
MIG: 13:12:43 : synp_flow:  -- synthesis_mode: Other
MIG: 13:12:43 : outputDirectory: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 13:12:43 : vivado_mode: xpg_pa
MIG: 13:12:43 :  locked false  
MIG: 13:12:43 : HDL Language: VHDL
MIG: 13:12:43 : compInfo: false
MIG: 13:12:43 : Vivado Options xc7a100t fgg484 -1
MIG: 13:12:43 : 1: xc7a100t 2: fgg484 3: -1
MIG: 13:12:43 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe
MIG: 13:12:43 : xilinx_path: C:/Xilinx/Vivado/2015.2/ids_lite/ISE
MIG: 13:12:43 : I am in catch area
MIG: 13:12:43 : Running C:/Xilinx/Vivado/2015.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/nt64/mig.exe -cg_exc_inp {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.in} -cg_exc_out {c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/xil_txt.out} ... 
MIG: 13:12:54 : XML_INPUT_FILE: c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 13:12:55 : Component_Name: mig_7series_0
MIG: 13:12:55 : Moving mig_7series_0 ...
MIG: 13:12:55 : Moving mig_7series_0.vho ...
MIG: 13:12:55 : Moving mig_7series_0_xmdf.tcl ...
MIG: 13:12:55 : Running vhdl_sim_rpr.xit
MIG: 13:12:55 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:12:55 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
MIG: 13:12:56 : Running implementation.xit
MIG: 13:12:56 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 13:12:56 : IGN:         <InputClkFreq>333.333</InputClkFreq> <==>         <InputClkFreq>333.333</InputClkFreq> 
