-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
-- Date        : Fri Dec 21 14:04:24 2018
-- Host        : L1 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               C:/Users/Alain/Documents/1VHDL/com1800template3btest/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/mig_7series_0_sim_netlist.vhdl
-- Design      : mig_7series_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a100tfgg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_arb_select is
  port (
    \col_mux.col_periodic_rd_r\ : out STD_LOGIC;
    col_rd_wr_r : out STD_LOGIC;
    \col_mux.col_data_buf_addr_r\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    cke_r : out STD_LOGIC;
    DIC : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    col_rd_wr : in STD_LOGIC;
    col_data_buf_addr : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke_ns : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_arb_select : entity is "mig_7series_v2_3_arb_select";
end mig_7series_0_mig_7series_v2_3_arb_select;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_arb_select is
begin
cke_r_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cke_ns(0),
      Q => cke_r,
      S => SR(0)
    );
\col_mux.col_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_data_buf_addr(0),
      Q => \col_mux.col_data_buf_addr_r\(0),
      R => '0'
    );
\col_mux.col_periodic_rd_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => DIC(0),
      Q => \col_mux.col_periodic_rd_r\,
      R => '0'
    );
\col_mux.col_rd_wr_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => col_rd_wr,
      Q => col_rd_wr_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_common is
  port (
    wait_for_maint_r_lcl_reg : out STD_LOGIC;
    req_wr_r_lcl_reg : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    was_wr : out STD_LOGIC;
    insert_maint_r1_lcl_reg : out STD_LOGIC;
    \maint_controller.maint_rdy_r1_reg_0\ : out STD_LOGIC;
    req_wr_r_lcl_reg_0 : out STD_LOGIC;
    was_priority : out STD_LOGIC;
    hi_priority : out STD_LOGIC;
    req_wr_r_lcl0 : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    head_r_lcl_reg_1 : out STD_LOGIC;
    ordered_r_lcl_reg_1 : out STD_LOGIC;
    periodic_rd_insert : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    p_7_in : in STD_LOGIC;
    CLK : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    \maint_controller.maint_rdy\ : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_2\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_read_request.periodic_rd_r_lcl_reg\ : in STD_LOGIC;
    periodic_rd_r : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    use_addr : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    head_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 1 downto 0 );
    maint_req_r : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\ : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    app_rdy_r_reg : in STD_LOGIC;
    idle_r_lcl_reg_2 : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \maint_controller.maint_hit_busies_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \generate_maint_cmds.insert_maint_r_lcl_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \maintenance_request.maint_srx_r_lcl_reg\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_common : entity is "mig_7series_v2_3_bank_common";
end mig_7series_0_mig_7series_v2_3_bank_common;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_common is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^accept_ns\ : STD_LOGIC;
  signal \generate_maint_cmds.insert_maint_ns\ : STD_LOGIC;
  signal \^hi_priority\ : STD_LOGIC;
  signal \^insert_maint_r1_lcl_reg\ : STD_LOGIC;
  signal \maint_controller.maint_rdy_r1\ : STD_LOGIC;
  signal \^maint_controller.maint_rdy_r1_reg_0\ : STD_LOGIC;
  signal \maint_controller.maint_srx_r1\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg_0\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg_1\ : STD_LOGIC;
  signal periodic_rd_ack_ns : STD_LOGIC;
  signal \^q_entry_r_reg[0]\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]\ : STD_LOGIC;
  signal \^req_wr_r_lcl_reg\ : STD_LOGIC;
  signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : STD_LOGIC;
  signal \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\ : STD_LOGIC;
  signal \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^wait_for_maint_r_lcl_reg\ : STD_LOGIC;
  signal \^was_priority\ : STD_LOGIC;
  signal was_wr0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of accept_r_i_1 : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of \i___28_i_2\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of \i___6_i_3\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of periodic_rd_ack_r_lcl_i_1 : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of req_periodic_rd_r_lcl_i_1 : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of req_wr_r_lcl_i_1 : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1\ : label is "soft_lutpair1008";
  attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2\ : label is "soft_lutpair1008";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
  accept_ns <= \^accept_ns\;
  hi_priority <= \^hi_priority\;
  insert_maint_r1_lcl_reg <= \^insert_maint_r1_lcl_reg\;
  \maint_controller.maint_rdy_r1_reg_0\ <= \^maint_controller.maint_rdy_r1_reg_0\;
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  ordered_r_lcl_reg_0 <= \^ordered_r_lcl_reg_0\;
  ordered_r_lcl_reg_1 <= \^ordered_r_lcl_reg_1\;
  \q_entry_r_reg[0]\ <= \^q_entry_r_reg[0]\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  \q_entry_r_reg[1]\ <= \^q_entry_r_reg[1]\;
  req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\;
  req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\;
  \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ <= \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\;
  \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\ <= \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\;
  \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\(0) <= \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\(0);
  wait_for_maint_r_lcl_reg <= \^wait_for_maint_r_lcl_reg\;
  was_priority <= \^was_priority\;
accept_internal_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_7_in,
      Q => \^wait_for_maint_r_lcl_reg\,
      R => '0'
    );
accept_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => p_7_in,
      I1 => \^req_wr_r_lcl_reg\,
      I2 => \^req_wr_r_lcl_reg_0\,
      I3 => periodic_rd_r,
      O => \^accept_ns\
    );
accept_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^accept_ns\,
      Q => \^q_entry_r_reg[1]\,
      R => '0'
    );
\bank_queue0/q_entry_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"330FAAAA33F0AAAA"
    )
        port map (
      I0 => idle_r_lcl_reg_2,
      I1 => rb_hit_busy_r_reg,
      I2 => \^q_entry_r_reg[0]\,
      I3 => \^q_entry_r_reg[0]_0\,
      I4 => pre_bm_end_r_reg,
      I5 => \q_entry_r_reg[0]_2\(0),
      O => \q_entry_r_reg[0]_1\
    );
\generate_maint_cmds.insert_maint_r_lcl_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maint_controller.maint_srx_r1\,
      I1 => maint_srx_r,
      I2 => \maint_controller.maint_rdy_r1\,
      I3 => \maint_controller.maint_rdy\,
      O => \generate_maint_cmds.insert_maint_ns\
    );
\generate_maint_cmds.insert_maint_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \generate_maint_cmds.insert_maint_ns\,
      Q => \^insert_maint_r1_lcl_reg\,
      R => '0'
    );
\i___0_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => \^req_wr_r_lcl_reg\,
      I1 => use_addr,
      I2 => \^wait_for_maint_r_lcl_reg\,
      I3 => head_r(0),
      I4 => idle_r_lcl_reg_0(0),
      O => \^q_entry_r_reg[0]_0\
    );
\i___28_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"15"
    )
        port map (
      I0 => \^req_wr_r_lcl_reg\,
      I1 => \^q_entry_r_reg[1]\,
      I2 => use_addr,
      O => \q_entry_r_reg[1]_0\
    );
\i___2_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => \^req_wr_r_lcl_reg\,
      I1 => use_addr,
      I2 => \^wait_for_maint_r_lcl_reg\,
      I3 => head_r(1),
      I4 => idle_r_lcl_reg_1(0),
      O => \^ordered_r_lcl_reg_1\
    );
\i___3_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3535353535050505"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      I1 => \^ordered_r_lcl_reg_1\,
      I2 => idle_r_lcl_reg_1(0),
      I3 => use_addr,
      I4 => \^q_entry_r_reg[1]\,
      I5 => \^req_wr_r_lcl_reg\,
      O => head_r_lcl_reg_1
    );
\i___4_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => \^req_wr_r_lcl_reg\,
      I1 => use_addr,
      I2 => \^wait_for_maint_r_lcl_reg\,
      I3 => head_r(2),
      I4 => idle_r_lcl_reg(0),
      O => \^ordered_r_lcl_reg_0\
    );
\i___4_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"07FF"
    )
        port map (
      I0 => use_addr,
      I1 => \^q_entry_r_reg[1]\,
      I2 => \^req_wr_r_lcl_reg\,
      I3 => rb_hit_busy_r(0),
      O => pass_open_bank_r_lcl_reg_0
    );
\i___5_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3535353535050505"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      I1 => \^ordered_r_lcl_reg_0\,
      I2 => idle_r_lcl_reg(0),
      I3 => use_addr,
      I4 => \^q_entry_r_reg[1]\,
      I5 => \^req_wr_r_lcl_reg\,
      O => head_r_lcl_reg_0
    );
\i___66_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555556"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\
    );
\i___6_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0000000"
    )
        port map (
      I0 => \^req_wr_r_lcl_reg\,
      I1 => use_addr,
      I2 => \^wait_for_maint_r_lcl_reg\,
      I3 => head_r(3),
      I4 => E(0),
      O => \^ordered_r_lcl_reg\
    );
\i___6_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"07FF"
    )
        port map (
      I0 => use_addr,
      I1 => \^q_entry_r_reg[1]\,
      I2 => \^req_wr_r_lcl_reg\,
      I3 => rb_hit_busy_r(1),
      O => pass_open_bank_r_lcl_reg
    );
\i___7_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3535353535050505"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      I1 => \^ordered_r_lcl_reg\,
      I2 => E(0),
      I3 => use_addr,
      I4 => \^q_entry_r_reg[1]\,
      I5 => \^req_wr_r_lcl_reg\,
      O => head_r_lcl_reg
    );
\i___80_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      I3 => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\(0),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      O => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\
    );
\maint_controller.maint_hit_busies_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(0),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(0),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(1),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(1),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(2),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(2),
      R => '0'
    );
\maint_controller.maint_hit_busies_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_controller.maint_hit_busies_r_reg[3]_1\(3),
      Q => \maint_controller.maint_hit_busies_r_reg[3]_0\(3),
      R => '0'
    );
\maint_controller.maint_rdy_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_controller.maint_rdy\,
      Q => \maint_controller.maint_rdy_r1\,
      R => '0'
    );
\maint_controller.maint_srx_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => maint_srx_r,
      Q => \maint_controller.maint_srx_r1\,
      R => '0'
    );
\maint_controller.maint_wip_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_2\,
      Q => \^maint_controller.maint_rdy_r1_reg_0\,
      R => \maintenance_request.maint_req_r_lcl_reg\
    );
\maintenance_request.upd_last_master_r_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^maint_controller.maint_rdy_r1_reg_0\,
      I1 => maint_req_r,
      O => auto_pre_r_lcl_reg
    );
periodic_rd_ack_r_lcl_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A00"
    )
        port map (
      I0 => p_7_in,
      I1 => \^req_wr_r_lcl_reg\,
      I2 => \^req_wr_r_lcl_reg_0\,
      I3 => periodic_rd_r,
      O => periodic_rd_ack_ns
    );
periodic_rd_ack_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => periodic_rd_ack_ns,
      Q => \^req_wr_r_lcl_reg\,
      R => '0'
    );
periodic_rd_cntr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.periodic_rd_r_lcl_reg\,
      Q => \^req_wr_r_lcl_reg_0\,
      R => SR(0)
    );
\q_entry_r[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3535353535050505"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => idle_r_lcl_reg_0(0),
      I3 => use_addr,
      I4 => \^q_entry_r_reg[1]\,
      I5 => \^req_wr_r_lcl_reg\,
      O => \^q_entry_r_reg[0]\
    );
req_periodic_rd_r_lcl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => \^req_wr_r_lcl_reg_0\,
      I2 => \^req_wr_r_lcl_reg\,
      O => periodic_rd_insert
    );
req_priority_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^was_priority\,
      I1 => app_rdy_r_reg,
      O => \^hi_priority\
    );
req_wr_r_lcl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D500D5D5"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => \^req_wr_r_lcl_reg_0\,
      I2 => \^req_wr_r_lcl_reg\,
      I3 => cmd(1),
      I4 => cmd(0),
      O => req_wr_r_lcl0
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \^insert_maint_r1_lcl_reg\,
      I2 => \^q\(0),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(0)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAAF909AAAA"
    )
        port map (
      I0 => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\,
      I1 => \^q\(0),
      I2 => \^insert_maint_r1_lcl_reg\,
      I3 => \maintenance_request.maint_srx_r_lcl_reg\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAAF606AAAA"
    )
        port map (
      I0 => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\(0),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0\,
      I2 => \^insert_maint_r1_lcl_reg\,
      I3 => \maintenance_request.maint_srx_r_lcl_reg\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F909"
    )
        port map (
      I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\,
      I2 => \^insert_maint_r1_lcl_reg\,
      I3 => maint_zq_r,
      I4 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100001"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \^insert_maint_r1_lcl_reg\,
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\,
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(5)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111000000001"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \^insert_maint_r1_lcl_reg\,
      I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\,
      I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(6)
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      I1 => \^insert_maint_r1_lcl_reg\,
      I2 => \rstdiv0_sync_r1_reg_rep__19\,
      I3 => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\,
      I4 => \^q\(0),
      I5 => \^q\(1),
      O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(0),
      Q => \^q\(0),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\,
      Q => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\,
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \generate_maint_cmds.insert_maint_r_lcl_reg_0\(0),
      Q => \^q\(1),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\,
      Q => \^rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\(0),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(5),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(6),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6),
      R => '0'
    );
\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\,
      D => \generate_maint_cmds.insert_maint_r_lcl_reg_0\(1),
      Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7),
      R => '0'
    );
was_priority_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^hi_priority\,
      Q => \^was_priority\,
      R => '0'
    );
was_wr_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => cmd(0),
      I1 => \^req_wr_r_lcl_reg\,
      I2 => periodic_rd_r,
      O => was_wr0
    );
was_wr_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => was_wr0,
      Q => was_wr,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_compare is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    req_priority_r : out STD_LOGIC;
    q_has_priority_r_reg : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    granted_col_r_reg : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_28_out : in STD_LOGIC;
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    override_demand_r_reg : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r : in STD_LOGIC;
    pre_passing_open_bank_r : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_r_reg : in STD_LOGIC;
    tail_r_21 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    pre_bm_end_r : in STD_LOGIC;
    order_q_r : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    idle_r_lcl_reg_0 : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_compare : entity is "mig_7series_v2_3_bank_compare";
end mig_7series_0_mig_7series_v2_3_bank_compare;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_compare is
  signal \^cmd_pipe_plus.mc_address_reg[41]\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \grant_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[3]\ : STD_LOGIC;
  signal \^grant_r_reg[3]_0\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal \pass_open_bank_r_lcl_i_2__2_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC;
  signal rd_wr_ns : STD_LOGIC;
  signal row_hit_ns : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__2_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__2_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal \^row_hit_r\ : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of ras_timer_zero_r_i_2 : label is "soft_lutpair999";
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__1\ : label is "soft_lutpair999";
begin
  \cmd_pipe_plus.mc_address_reg[41]\(13 downto 0) <= \^cmd_pipe_plus.mc_address_reg[41]\(13 downto 0);
  \grant_r_reg[3]\ <= \^grant_r_reg[3]\;
  \grant_r_reg[3]_0\ <= \^grant_r_reg[3]_0\;
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  \rd_this_rank_r_reg[0]\ <= \^rd_this_rank_r_reg[0]\;
  row_hit_r <= \^row_hit_r\;
act_wait_r_lcl_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => Q(1),
      I5 => pre_passing_open_bank_r,
      O => act_wait_r_lcl_reg
    );
\grant_r[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^grant_r_reg[3]\,
      I1 => rd_wr_r_lcl_reg_0,
      O => granted_col_r_reg
    );
\grant_r[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DF00DFDFDFDFDFDF"
    )
        port map (
      I0 => \^ordered_r_lcl_reg\,
      I1 => \^rd_this_rank_r_reg[0]\,
      I2 => Q(1),
      I3 => rd_wr_r(0),
      I4 => Q(0),
      I5 => req_wr_r(0),
      O => \^grant_r_reg[3]_0\
    );
\grant_r[3]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => Q(1),
      I5 => pre_passing_open_bank_r,
      O => \grant_r_reg[2]\
    );
\grant_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFEFEFE"
    )
        port map (
      I0 => col_wait_r_reg,
      I1 => override_demand_r_reg,
      I2 => \grant_r[3]_i_6_n_0\,
      I3 => \wtr_timer.wtr_cnt_r_reg[1]\,
      I4 => \^rd_this_rank_r_reg[0]\,
      I5 => rd_wr_r_lcl_reg_1,
      O => \^grant_r_reg[3]\
    );
\grant_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF44544444"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => rd_wr_r_lcl_reg_2,
      I4 => \^grant_r_reg[3]_0\,
      I5 => rnk_config_valid_r_lcl_reg,
      O => \grant_r[3]_i_6_n_0\
    );
\i___42_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => Q(1),
      I5 => pre_passing_open_bank_r,
      O => \grant_r_reg[1]\
    );
\i___49_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFAAAAAA"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => Q(1),
      I5 => pre_bm_end_r,
      O => \^pass_open_bank_r_lcl_reg\
    );
\ordered_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFBFB000"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => Q(1),
      I2 => \^ordered_r_lcl_reg\,
      I3 => periodic_rd_ack_r_lcl_reg,
      I4 => ordered_r_lcl_reg_1(0),
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => ordered_r_lcl_reg_0
    );
\pass_open_bank_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444454444444444"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg\,
      I1 => pass_open_bank_r,
      I2 => accept_r_reg,
      I3 => tail_r_21,
      I4 => pre_wait_r,
      I5 => \pass_open_bank_r_lcl_i_2__2_n_0\,
      O => pass_open_bank_ns
    );
\pass_open_bank_r_lcl_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA02"
    )
        port map (
      I0 => \^row_hit_r\,
      I1 => maint_req_r,
      I2 => \maint_controller.maint_wip_r_lcl_reg\,
      I3 => wait_for_maint_r_lcl_reg,
      O => \pass_open_bank_r_lcl_i_2__2_n_0\
    );
ras_timer_zero_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => Q(1),
      O => ras_timer_zero_r_reg
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_28_out,
      Q => q_has_priority_r_reg,
      R => '0'
    );
\rd_wr_r_lcl_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => Q(1),
      I2 => idle_r_lcl_reg,
      I3 => periodic_rd_ack_r_lcl_reg_0,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_this_rank_r_reg[0]\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(0),
      Q => \cmd_pipe_plus.mc_bank_reg[8]\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(1),
      Q => \cmd_pipe_plus.mc_bank_reg[8]\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(2),
      Q => \cmd_pipe_plus.mc_bank_reg[8]\(2),
      R => '0'
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(0),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(1),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(2),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(3),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(4),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(5),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(6),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(7),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(8),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(9),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(0),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(1),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(2),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(3),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(3),
      R => '0'
    );
\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(4),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(0),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(10),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(11),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(12),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(13),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(1),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(2),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(3),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(4),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(5),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(6),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(7),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(8),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(9),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^ordered_r_lcl_reg\,
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__2_n_0\,
      S(2) => \row_hit_ns_carry_i_2__2_n_0\,
      S(1) => \row_hit_ns_carry_i_3__2_n_0\,
      S(0) => \row_hit_ns_carry_i_4__2_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \app_addr_r1_reg[23]\(0)
    );
\row_hit_ns_carry_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(11),
      I1 => \app_addr_r1_reg[23]_0\(11),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(9),
      I3 => \app_addr_r1_reg[23]_0\(9),
      I4 => \app_addr_r1_reg[23]_0\(10),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(10),
      O => \row_hit_ns_carry_i_1__2_n_0\
    );
\row_hit_ns_carry_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(8),
      I1 => \app_addr_r1_reg[23]_0\(8),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(7),
      I3 => \app_addr_r1_reg[23]_0\(7),
      I4 => \app_addr_r1_reg[23]_0\(6),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(6),
      O => \row_hit_ns_carry_i_2__2_n_0\
    );
\row_hit_ns_carry_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(5),
      I1 => \app_addr_r1_reg[23]_0\(5),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(3),
      I3 => \app_addr_r1_reg[23]_0\(3),
      I4 => \app_addr_r1_reg[23]_0\(4),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(4),
      O => \row_hit_ns_carry_i_3__2_n_0\
    );
\row_hit_ns_carry_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(2),
      I1 => \app_addr_r1_reg[23]_0\(2),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(1),
      I3 => \app_addr_r1_reg[23]_0\(1),
      I4 => \app_addr_r1_reg[23]_0\(0),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(0),
      O => \row_hit_ns_carry_i_4__2_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => \^row_hit_r\,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_compare_0 is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    q_has_priority_r_reg : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    \order_q_r_reg[0]\ : out STD_LOGIC;
    req_bank_rdy_r_reg : out STD_LOGIC;
    \order_q_r_reg[1]\ : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \cmd_pipe_plus.mc_address_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_67_out : in STD_LOGIC;
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    idle_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r : in STD_LOGIC;
    pre_passing_open_bank_r : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_r_reg : in STD_LOGIC;
    tail_r_20 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    pre_bm_end_r : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    order_q_r : in STD_LOGIC_VECTOR ( 1 downto 0 );
    q_has_priority_10 : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_row_r_lcl_reg[10]_0\ : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    \grant_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_compare_0 : entity is "mig_7series_v2_3_bank_compare";
end mig_7series_0_mig_7series_v2_3_bank_compare_0;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_compare_0 is
  signal \^cmd_pipe_plus.mc_address_reg[41]\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal \pass_open_bank_r_lcl_i_2__1_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC;
  signal rd_wr_ns : STD_LOGIC;
  signal req_bank_rdy_r_i_3_n_0 : STD_LOGIC;
  signal \^req_bank_rdy_r_reg\ : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal row_hit_ns : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_3__1_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__1_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal \^row_hit_r\ : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \order_q_r[0]_i_2\ : label is "soft_lutpair990";
  attribute SOFT_HLUTNM of \order_q_r[1]_i_2__1\ : label is "soft_lutpair990";
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__0\ : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \req_bank_rdy_r_i_1__1\ : label is "soft_lutpair991";
  attribute SOFT_HLUTNM of req_bank_rdy_r_i_3 : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1__1\ : label is "soft_lutpair991";
begin
  \cmd_pipe_plus.mc_address_reg[41]\(13 downto 0) <= \^cmd_pipe_plus.mc_address_reg[41]\(13 downto 0);
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  \rd_this_rank_r_reg[0]\ <= \^rd_this_rank_r_reg[0]\;
  req_bank_rdy_r_reg <= \^req_bank_rdy_r_reg\;
  row_hit_r <= \^row_hit_r\;
\cmd_pipe_plus.mc_address[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000C055"
    )
        port map (
      I0 => \req_row_r_lcl_reg[10]_0\,
      I1 => \^cmd_pipe_plus.mc_address_reg[41]\(10),
      I2 => act_wait_r_lcl_reg_1,
      I3 => \grant_r_reg[3]_0\(0),
      I4 => \grant_r_reg[3]_0\(1),
      I5 => act_wait_r_lcl_reg_2,
      O => \cmd_pipe_plus.mc_address_reg[38]\(0)
    );
\demand_priority_r_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544454445444FFFF"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => \^req_bank_rdy_r_reg\,
      I4 => q_has_priority_10,
      I5 => req_priority_r,
      O => demand_priority_r_reg
    );
\grant_r[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => \grant_r_reg[3]\(0),
      I5 => pre_passing_open_bank_r,
      O => \grant_r_reg[0]\
    );
\i___23_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => Q(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => \grant_r_reg[3]\(0),
      I5 => pre_passing_open_bank_r,
      O => act_wait_r_lcl_reg_0
    );
\i___42_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => \grant_r_reg[3]\(0),
      I5 => pre_passing_open_bank_r,
      O => act_wait_r_lcl_reg
    );
\i___51_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFAAAAAA"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r,
      I4 => \grant_r_reg[3]\(0),
      I5 => pre_bm_end_r,
      O => \^pass_open_bank_r_lcl_reg\
    );
\order_q_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^req_bank_rdy_r_reg\,
      I1 => ordered_r_lcl_reg_1(2),
      I2 => ordered_r(0),
      I3 => ordered_r_lcl_reg_1(1),
      I4 => ordered_r_lcl_reg_1(0),
      O => \order_q_r_reg[0]\
    );
\order_q_r[1]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7EE8E881"
    )
        port map (
      I0 => \^req_bank_rdy_r_reg\,
      I1 => ordered_r_lcl_reg_1(0),
      I2 => ordered_r_lcl_reg_1(1),
      I3 => ordered_r(0),
      I4 => ordered_r_lcl_reg_1(2),
      O => \order_q_r_reg[1]\
    );
\ordered_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5400545450505050"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => periodic_rd_ack_r_lcl_reg_0,
      I2 => ordered_r(0),
      I3 => \^rd_this_rank_r_reg[0]\,
      I4 => \grant_r_reg[3]\(0),
      I5 => \^ordered_r_lcl_reg\,
      O => ordered_r_lcl_reg_0
    );
\pass_open_bank_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444454444444444"
    )
        port map (
      I0 => \^pass_open_bank_r_lcl_reg\,
      I1 => pass_open_bank_r,
      I2 => accept_r_reg,
      I3 => tail_r_20,
      I4 => pre_wait_r,
      I5 => \pass_open_bank_r_lcl_i_2__1_n_0\,
      O => pass_open_bank_ns
    );
\pass_open_bank_r_lcl_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA02"
    )
        port map (
      I0 => \^row_hit_r\,
      I1 => maint_req_r,
      I2 => \maint_controller.maint_wip_r_lcl_reg\,
      I3 => wait_for_maint_r_lcl_reg,
      O => \pass_open_bank_r_lcl_i_2__1_n_0\
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_67_out,
      Q => q_has_priority_r_reg,
      R => '0'
    );
\rd_wr_r_lcl_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => \grant_r_reg[3]\(0),
      I2 => idle_r_lcl_reg,
      I3 => periodic_rd_ack_r_lcl_reg,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_this_rank_r_reg[0]\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(0),
      Q => \cmd_pipe_plus.mc_bank_reg[2]\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(1),
      Q => \cmd_pipe_plus.mc_bank_reg[2]\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(2),
      Q => \cmd_pipe_plus.mc_bank_reg[2]\(2),
      R => '0'
    );
\req_bank_rdy_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8A8A"
    )
        port map (
      I0 => col_wait_r_reg,
      I1 => \^rd_this_rank_r_reg[0]\,
      I2 => order_q_r(1),
      I3 => order_q_r(0),
      I4 => \^req_bank_rdy_r_reg\,
      O => req_bank_rdy_ns
    );
req_bank_rdy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DD0DDDDD"
    )
        port map (
      I0 => \^ordered_r_lcl_reg\,
      I1 => req_bank_rdy_r_i_3_n_0,
      I2 => \grant_r_reg[3]\(1),
      I3 => rd_wr_r_lcl_reg_0(0),
      I4 => req_wr_r_lcl_reg_0,
      I5 => rd_wr_r_lcl_reg_1,
      O => \^req_bank_rdy_r_reg\
    );
req_bank_rdy_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => \grant_r_reg[3]\(0),
      O => req_bank_rdy_r_i_3_n_0
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(0),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(1),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(2),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(3),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(4),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(5),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(6),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(7),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(8),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(9),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(0),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(1),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(2),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(3),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(3),
      R => '0'
    );
\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(4),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(0),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(10),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(11),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(12),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(13),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(1),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(2),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(3),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(4),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(5),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(6),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(7),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(8),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(9),
      Q => \^cmd_pipe_plus.mc_address_reg[41]\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^ordered_r_lcl_reg\,
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__1_n_0\,
      S(2) => \row_hit_ns_carry_i_2__1_n_0\,
      S(1) => \row_hit_ns_carry_i_3__1_n_0\,
      S(0) => \row_hit_ns_carry_i_4__1_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \app_addr_r1_reg[23]\(0)
    );
\row_hit_ns_carry_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(11),
      I1 => \app_addr_r1_reg[23]_0\(11),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(10),
      I3 => \app_addr_r1_reg[23]_0\(10),
      I4 => \app_addr_r1_reg[23]_0\(9),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(9),
      O => \row_hit_ns_carry_i_1__1_n_0\
    );
\row_hit_ns_carry_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(8),
      I1 => \app_addr_r1_reg[23]_0\(8),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(7),
      I3 => \app_addr_r1_reg[23]_0\(7),
      I4 => \app_addr_r1_reg[23]_0\(6),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(6),
      O => \row_hit_ns_carry_i_2__1_n_0\
    );
\row_hit_ns_carry_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(5),
      I1 => \app_addr_r1_reg[23]_0\(5),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(4),
      I3 => \app_addr_r1_reg[23]_0\(4),
      I4 => \app_addr_r1_reg[23]_0\(3),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(3),
      O => \row_hit_ns_carry_i_3__1_n_0\
    );
\row_hit_ns_carry_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[41]\(2),
      I1 => \app_addr_r1_reg[23]_0\(2),
      I2 => \^cmd_pipe_plus.mc_address_reg[41]\(0),
      I3 => \app_addr_r1_reg[23]_0\(0),
      I4 => \app_addr_r1_reg[23]_0\(1),
      I5 => \^cmd_pipe_plus.mc_address_reg[41]\(1),
      O => \row_hit_ns_carry_i_4__1_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => \^row_hit_r\,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_compare_1 is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    req_priority_r : out STD_LOGIC;
    q_has_priority_r_reg : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    p_91_out : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    req_bank_rdy_r_reg : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \cmd_pipe_plus.mc_address_reg[38]\ : out STD_LOGIC;
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_106_out : in STD_LOGIC;
    \req_row_r_lcl_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pre_passing_open_bank_r : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    accept_r_reg : in STD_LOGIC;
    tail_r_19 : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r_lcl_reg_1 : in STD_LOGIC;
    order_q_r : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    req_wr_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[10]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_0 : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_compare_1 : entity is "mig_7series_v2_3_bank_compare";
end mig_7series_0_mig_7series_v2_3_bank_compare_1;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_compare_1 is
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_address_reg[13]\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \pass_open_bank_r_lcl_i_2__0_n_0\ : STD_LOGIC;
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC;
  signal rd_wr_ns : STD_LOGIC;
  signal \^req_bank_rdy_r_reg\ : STD_LOGIC;
  signal row_hit_ns : STD_LOGIC;
  signal \row_hit_ns_carry_i_1__0_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_2__0_n_0\ : STD_LOGIC;
  signal \row_hit_ns_carry_i_4__0_n_0\ : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal \^row_hit_r\ : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[1]_i_6\ : label is "soft_lutpair984";
  attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1__0\ : label is "soft_lutpair984";
begin
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  \cmd_pipe_plus.mc_address_reg[13]\(13 downto 0) <= \^cmd_pipe_plus.mc_address_reg[13]\(13 downto 0);
  \rd_this_rank_r_reg[0]\ <= \^rd_this_rank_r_reg[0]\;
  req_bank_rdy_r_reg <= \^req_bank_rdy_r_reg\;
  row_hit_r <= \^row_hit_r\;
bm_end_r1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7000"
    )
        port map (
      I0 => \^bm_end_r1_reg\,
      I1 => \^rd_this_rank_r_reg[0]\,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => \grant_r_reg[1]_0\(1),
      I4 => pre_bm_end_r_reg_0,
      O => p_91_out
    );
\cmd_pipe_plus.mc_address[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"707F7F7F7F7F7F7F"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(10),
      I1 => act_wait_r_lcl_reg_0,
      I2 => \grant_r_reg[1]_1\(1),
      I3 => \grant_r_reg[1]_1\(0),
      I4 => row_cmd_wr(0),
      I5 => \req_row_r_lcl_reg[10]_0\(0),
      O => \cmd_pipe_plus.mc_address_reg[38]\
    );
\grant_r[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FF20"
    )
        port map (
      I0 => req_wr_r_lcl_reg_1,
      I1 => \^req_bank_rdy_r_reg\,
      I2 => order_q_r(0),
      I3 => order_q_r(1),
      I4 => \^rd_this_rank_r_reg[0]\,
      O => \grant_r_reg[1]\
    );
\i___22_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0),
      I1 => \^bm_end_r1_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \grant_r_reg[1]_0\(1),
      I5 => pre_passing_open_bank_r,
      O => \ras_timer_r_reg[0]\
    );
\i___23_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => Q(0),
      I1 => \^bm_end_r1_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \grant_r_reg[1]_0\(1),
      I5 => pre_passing_open_bank_r,
      O => act_wait_r_lcl_reg
    );
\i___25_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(0),
      I1 => \^bm_end_r1_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \grant_r_reg[1]_0\(1),
      I5 => pre_passing_open_bank_r,
      O => \ras_timer_r_reg[0]_0\
    );
\i___5_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080AAAAAA"
    )
        port map (
      I0 => pre_bm_end_r_reg,
      I1 => \^bm_end_r1_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \grant_r_reg[1]_0\(1),
      I5 => pre_bm_end_r_reg_0,
      O => head_r_lcl_reg
    );
ordered_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5400545450505050"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => periodic_rd_ack_r_lcl_reg_0,
      I2 => ordered_r(0),
      I3 => \^rd_this_rank_r_reg[0]\,
      I4 => \grant_r_reg[1]_0\(1),
      I5 => \^bm_end_r1_reg\,
      O => ordered_r_lcl_reg
    );
pass_open_bank_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444454444444444"
    )
        port map (
      I0 => req_wr_r_lcl_reg_0,
      I1 => pass_open_bank_r_lcl_reg,
      I2 => accept_r_reg,
      I3 => tail_r_19,
      I4 => pre_wait_r,
      I5 => \pass_open_bank_r_lcl_i_2__0_n_0\,
      O => pass_open_bank_ns
    );
\pass_open_bank_r_lcl_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA02"
    )
        port map (
      I0 => \^row_hit_r\,
      I1 => maint_req_r,
      I2 => \maint_controller.maint_wip_r_lcl_reg\,
      I3 => wait_for_maint_r_lcl_reg,
      O => \pass_open_bank_r_lcl_i_2__0_n_0\
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_106_out,
      Q => q_has_priority_r_reg,
      R => '0'
    );
rd_wr_r_lcl_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => \grant_r_reg[1]_0\(1),
      I2 => idle_r_lcl_reg,
      I3 => periodic_rd_ack_r_lcl_reg,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_this_rank_r_reg[0]\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(0),
      Q => \cmd_pipe_plus.mc_bank_reg[2]\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(1),
      Q => \cmd_pipe_plus.mc_bank_reg[2]\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(2),
      Q => \cmd_pipe_plus.mc_bank_reg[2]\(2),
      R => '0'
    );
req_bank_rdy_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40FF404040404040"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => \grant_r_reg[1]_0\(1),
      I2 => \^bm_end_r1_reg\,
      I3 => rd_wr_r_lcl_reg_0,
      I4 => \grant_r_reg[1]_0\(0),
      I5 => req_wr_r_lcl_reg_2(0),
      O => \^req_bank_rdy_r_reg\
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(0),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(1),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(2),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(3),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(4),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(5),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(6),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(7),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(8),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(9),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(0),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(1),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(2),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(3),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(3),
      R => '0'
    );
\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(4),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(0),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(10),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(11),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(12),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(13),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(1),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(2),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(3),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(4),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(5),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(6),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(7),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(8),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]_0\(9),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^bm_end_r1_reg\,
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => \row_hit_ns_carry_i_1__0_n_0\,
      S(2) => \row_hit_ns_carry_i_2__0_n_0\,
      S(1) => \req_row_r_lcl_reg[3]_0\(0),
      S(0) => \row_hit_ns_carry_i_4__0_n_0\
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \app_addr_r1_reg[23]\(0)
    );
\row_hit_ns_carry_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(11),
      I1 => \app_addr_r1_reg[23]_0\(11),
      I2 => \^cmd_pipe_plus.mc_address_reg[13]\(9),
      I3 => \app_addr_r1_reg[23]_0\(9),
      I4 => \app_addr_r1_reg[23]_0\(10),
      I5 => \^cmd_pipe_plus.mc_address_reg[13]\(10),
      O => \row_hit_ns_carry_i_1__0_n_0\
    );
\row_hit_ns_carry_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(8),
      I1 => \app_addr_r1_reg[23]_0\(8),
      I2 => \^cmd_pipe_plus.mc_address_reg[13]\(7),
      I3 => \app_addr_r1_reg[23]_0\(7),
      I4 => \app_addr_r1_reg[23]_0\(6),
      I5 => \^cmd_pipe_plus.mc_address_reg[13]\(6),
      O => \row_hit_ns_carry_i_2__0_n_0\
    );
\row_hit_ns_carry_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(2),
      I1 => \app_addr_r1_reg[23]_0\(2),
      I2 => \^cmd_pipe_plus.mc_address_reg[13]\(1),
      I3 => \app_addr_r1_reg[23]_0\(1),
      I4 => \app_addr_r1_reg[23]_0\(0),
      I5 => \^cmd_pipe_plus.mc_address_reg[13]\(0),
      O => \row_hit_ns_carry_i_4__0_n_0\
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => \^row_hit_r\,
      R => '0'
    );
\wr_this_rank_r[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_compare_2 is
  port (
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    req_priority_r : out STD_LOGIC;
    q_has_priority_r_reg : out STD_LOGIC;
    row_hit_r : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    pass_open_bank_ns : out STD_LOGIC;
    p_130_out : out STD_LOGIC;
    start_wtp_timer0 : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    head_r_lcl_reg : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    periodic_rd_insert : in STD_LOGIC;
    CLK : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    p_145_out : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    pre_passing_open_bank_r : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    accept_r_reg : in STD_LOGIC;
    tail_r : in STD_LOGIC;
    pre_wait_r : in STD_LOGIC;
    pre_bm_end_r : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    rb_hit_busy_r_reg_3 : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_compare_2 : entity is "mig_7series_v2_3_bank_compare";
end mig_7series_0_mig_7series_v2_3_bank_compare_2;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_compare_2 is
  signal \^cmd_pipe_plus.mc_address_reg[13]\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^cmd_pipe_plus.mc_bank_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal pass_open_bank_r_lcl_i_2_n_0 : STD_LOGIC;
  signal \^q_has_priority_r_reg\ : STD_LOGIC;
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC;
  signal rd_wr_ns : STD_LOGIC;
  signal row_hit_ns : STD_LOGIC;
  signal row_hit_ns_carry_i_1_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_i_2_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_i_3_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_i_4_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_0 : STD_LOGIC;
  signal row_hit_ns_carry_n_1 : STD_LOGIC;
  signal row_hit_ns_carry_n_2 : STD_LOGIC;
  signal row_hit_ns_carry_n_3 : STD_LOGIC;
  signal \^row_hit_r\ : STD_LOGIC;
  signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \bm_end_r1_i_1__0\ : label is "soft_lutpair973";
  attribute SOFT_HLUTNM of \i___1_i_3\ : label is "soft_lutpair974";
  attribute SOFT_HLUTNM of \i___1_i_4\ : label is "soft_lutpair974";
  attribute SOFT_HLUTNM of ras_timer_zero_r_i_3 : label is "soft_lutpair973";
  attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__2\ : label is "soft_lutpair975";
  attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1\ : label is "soft_lutpair975";
begin
  \cmd_pipe_plus.mc_address_reg[13]\(13 downto 0) <= \^cmd_pipe_plus.mc_address_reg[13]\(13 downto 0);
  \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) <= \^cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0);
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  q_has_priority_r_reg <= \^q_has_priority_r_reg\;
  \rd_this_rank_r_reg[0]\ <= \^rd_this_rank_r_reg[0]\;
  row_hit_r <= \^row_hit_r\;
act_wait_r_lcl_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \grant_r_reg[0]\(0),
      I5 => pre_passing_open_bank_r,
      O => act_wait_r_lcl_reg_0
    );
\bm_end_r1_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7000"
    )
        port map (
      I0 => \^ordered_r_lcl_reg\,
      I1 => \^rd_this_rank_r_reg[0]\,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => \grant_r_reg[0]\(0),
      I4 => pre_bm_end_r,
      O => p_130_out
    );
\i___1_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^q_has_priority_r_reg\,
      I1 => rb_hit_busy_r_reg_3,
      I2 => rb_hit_busy_r_reg_2,
      I3 => rb_hit_busy_r_reg_1,
      O => head_r_lcl_reg_0
    );
\i___1_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => \^q_has_priority_r_reg\,
      I1 => rb_hit_busy_r_reg_1,
      I2 => rb_hit_busy_r_reg_2,
      I3 => rb_hit_busy_r_reg_3,
      O => head_r_lcl_reg
    );
\i___23_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => Q(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \grant_r_reg[0]\(0),
      I5 => pre_passing_open_bank_r,
      O => \grant_r_reg[3]\
    );
\i___42_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A000000"
    )
        port map (
      I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0),
      I1 => \^ordered_r_lcl_reg\,
      I2 => \^rd_this_rank_r_reg[0]\,
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \grant_r_reg[0]\(0),
      I5 => pre_passing_open_bank_r,
      O => act_wait_r_lcl_reg
    );
\ordered_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5400545450505050"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => periodic_rd_ack_r_lcl_reg_0,
      I2 => ordered_r(0),
      I3 => \^rd_this_rank_r_reg[0]\,
      I4 => \grant_r_reg[0]\(0),
      I5 => \^ordered_r_lcl_reg\,
      O => ordered_r_lcl_reg_0
    );
\pass_open_bank_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444454444444444"
    )
        port map (
      I0 => req_wr_r_lcl_reg_0,
      I1 => pass_open_bank_r_lcl_reg,
      I2 => accept_r_reg,
      I3 => tail_r,
      I4 => pre_wait_r,
      I5 => pass_open_bank_r_lcl_i_2_n_0,
      O => pass_open_bank_ns
    );
pass_open_bank_r_lcl_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA02"
    )
        port map (
      I0 => \^row_hit_r\,
      I1 => maint_req_r,
      I2 => \maint_controller.maint_wip_r_lcl_reg\,
      I3 => wait_for_maint_r_lcl_reg,
      O => pass_open_bank_r_lcl_i_2_n_0
    );
ras_timer_zero_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => \grant_r_reg[0]\(0),
      O => ras_timer_zero_r_reg
    );
rb_hit_busy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_bank_reg[2]\(2),
      I1 => \app_addr_r1_reg[26]\(2),
      I2 => \^cmd_pipe_plus.mc_bank_reg[2]\(0),
      I3 => \app_addr_r1_reg[26]\(0),
      I4 => \app_addr_r1_reg[26]\(1),
      I5 => \^cmd_pipe_plus.mc_bank_reg[2]\(1),
      O => rb_hit_busy_r_reg_0
    );
rb_hit_busy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_145_out,
      Q => \^q_has_priority_r_reg\,
      R => '0'
    );
\rd_wr_r_lcl_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      I1 => \grant_r_reg[0]\(0),
      I2 => idle_r_lcl_reg,
      I3 => periodic_rd_ack_r_lcl_reg,
      O => rd_wr_ns
    );
rd_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_ns,
      Q => \^rd_this_rank_r_reg[0]\,
      R => '0'
    );
\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(0),
      Q => \^cmd_pipe_plus.mc_bank_reg[2]\(0),
      R => '0'
    );
\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(1),
      Q => \^cmd_pipe_plus.mc_bank_reg[2]\(1),
      R => '0'
    );
\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[26]\(2),
      Q => \^cmd_pipe_plus.mc_bank_reg[2]\(2),
      R => '0'
    );
\req_col_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(0),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(0),
      R => '0'
    );
\req_col_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(1),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(1),
      R => '0'
    );
\req_col_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(2),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(2),
      R => '0'
    );
\req_col_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(3),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(3),
      R => '0'
    );
\req_col_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(4),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(4),
      R => '0'
    );
\req_col_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(5),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(5),
      R => '0'
    );
\req_col_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(6),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(6),
      R => '0'
    );
\req_col_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(7),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(7),
      R => '0'
    );
\req_col_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(8),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(8),
      R => '0'
    );
\req_col_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[9]\(9),
      Q => \cmd_pipe_plus.mc_address_reg[23]\(9),
      R => '0'
    );
\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(0),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(0),
      R => '0'
    );
\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(1),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(1),
      R => '0'
    );
\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(2),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(2),
      R => '0'
    );
\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(3),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(3),
      R => '0'
    );
\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => idle_r_lcl_reg_0,
      D => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4),
      Q => \col_mux.col_data_buf_addr_r_reg[4]\(4),
      R => '0'
    );
req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => periodic_rd_insert,
      Q => req_periodic_rd_r(0),
      R => '0'
    );
req_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => hi_priority,
      Q => req_priority_r,
      R => '0'
    );
\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(0),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(0),
      R => '0'
    );
\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(10),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(10),
      R => '0'
    );
\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(11),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(11),
      R => '0'
    );
\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(12),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(12),
      R => '0'
    );
\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(13),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(13),
      R => '0'
    );
\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(1),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(1),
      R => '0'
    );
\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(2),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(2),
      R => '0'
    );
\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(3),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(3),
      R => '0'
    );
\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(4),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(4),
      R => '0'
    );
\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(5),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(5),
      R => '0'
    );
\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(6),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(6),
      R => '0'
    );
\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(7),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(7),
      R => '0'
    );
\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(8),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(8),
      R => '0'
    );
\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \app_addr_r1_reg[23]\(9),
      Q => \^cmd_pipe_plus.mc_address_reg[13]\(9),
      R => '0'
    );
req_wr_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => req_wr_r_lcl0,
      Q => \^ordered_r_lcl_reg\,
      R => '0'
    );
row_hit_ns_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => row_hit_ns_carry_n_0,
      CO(2) => row_hit_ns_carry_n_1,
      CO(1) => row_hit_ns_carry_n_2,
      CO(0) => row_hit_ns_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0),
      S(3) => row_hit_ns_carry_i_1_n_0,
      S(2) => row_hit_ns_carry_i_2_n_0,
      S(1) => row_hit_ns_carry_i_3_n_0,
      S(0) => row_hit_ns_carry_i_4_n_0
    );
\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => row_hit_ns_carry_n_0,
      CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => row_hit_ns,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => S(0)
    );
row_hit_ns_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(11),
      I1 => \app_addr_r1_reg[23]\(11),
      I2 => \^cmd_pipe_plus.mc_address_reg[13]\(10),
      I3 => \app_addr_r1_reg[23]\(10),
      I4 => \app_addr_r1_reg[23]\(9),
      I5 => \^cmd_pipe_plus.mc_address_reg[13]\(9),
      O => row_hit_ns_carry_i_1_n_0
    );
row_hit_ns_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(8),
      I1 => \app_addr_r1_reg[23]\(8),
      I2 => \^cmd_pipe_plus.mc_address_reg[13]\(7),
      I3 => \app_addr_r1_reg[23]\(7),
      I4 => \app_addr_r1_reg[23]\(6),
      I5 => \^cmd_pipe_plus.mc_address_reg[13]\(6),
      O => row_hit_ns_carry_i_2_n_0
    );
row_hit_ns_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(5),
      I1 => \app_addr_r1_reg[23]\(5),
      I2 => \^cmd_pipe_plus.mc_address_reg[13]\(3),
      I3 => \app_addr_r1_reg[23]\(3),
      I4 => \app_addr_r1_reg[23]\(4),
      I5 => \^cmd_pipe_plus.mc_address_reg[13]\(4),
      O => row_hit_ns_carry_i_3_n_0
    );
row_hit_ns_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_address_reg[13]\(2),
      I1 => \app_addr_r1_reg[23]\(2),
      I2 => \^cmd_pipe_plus.mc_address_reg[13]\(1),
      I3 => \app_addr_r1_reg[23]\(1),
      I4 => \app_addr_r1_reg[23]\(0),
      I5 => \^cmd_pipe_plus.mc_address_reg[13]\(0),
      O => row_hit_ns_carry_i_4_n_0
    );
row_hit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => row_hit_ns,
      Q => \^row_hit_r\,
      R => '0'
    );
\wr_this_rank_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rd_this_rank_r_reg[0]\,
      O => start_wtp_timer0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_queue is
  port (
    \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    pre_passing_open_bank_r : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg_1 : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    accept_internal_r_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ras_timer_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    act_wait_ns : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_2\ : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]_3\ : out STD_LOGIC;
    q_entry_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_7_in : out STD_LOGIC;
    head_r_lcl_reg_1 : out STD_LOGIC;
    head_r_lcl_reg_2 : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    p_145_out : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    head_r_lcl_reg_3 : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_4 : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    \q_entry_r_reg[0]_2\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC;
    idle_r_lcl_reg_2 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_3 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_4 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg_1 : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    \q_entry_r_reg[1]_5\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    idle_r_lcl_reg_5 : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    rb_hit_busy_r_reg_3 : in STD_LOGIC;
    rb_hit_busy_r_reg_4 : in STD_LOGIC;
    pre_bm_end_r_reg_2 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg_0 : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    req_wr_r_lcl_reg_1 : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    req_wr_r_lcl_reg_2 : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    bm_end_r1_reg_3 : in STD_LOGIC;
    idle_r_lcl_reg_6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_7 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_8 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    ordered_r_lcl_reg_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_queue : entity is "mig_7series_v2_3_bank_queue";
end mig_7series_0_mig_7series_v2_3_bank_queue;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_queue is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^accept_internal_r_reg\ : STD_LOGIC;
  signal act_wait_r_lcl_i_2_n_0 : STD_LOGIC;
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC;
  signal \auto_pre_r_lcl_i_1__0_n_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_1\ : STD_LOGIC;
  signal \^head_r_lcl_reg_2\ : STD_LOGIC;
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^pre_bm_end_r\ : STD_LOGIC;
  signal \^pre_passing_open_bank_r\ : STD_LOGIC;
  signal q_entry_ns_0 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_1\ : STD_LOGIC;
  signal \^q_has_priority\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[0]\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_data_buf_addr_r_reg[4]\ : STD_LOGIC;
  signal set_order_q : STD_LOGIC;
  signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of accept_internal_r_i_1 : label is "soft_lutpair978";
  attribute SOFT_HLUTNM of \i___1_i_2\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \i___22_i_6\ : label is "soft_lutpair980";
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__2\ : label is "soft_lutpair978";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_1\ : label is "soft_lutpair980";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_2\ : label is "soft_lutpair976";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_4\ : label is "soft_lutpair976";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_4__1\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1\ : label is "soft_lutpair979";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1\ : label is "soft_lutpair979";
begin
  E(0) <= \^e\(0);
  accept_internal_r_reg <= \^accept_internal_r_reg\;
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\;
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  auto_pre_r_lcl_reg_1 <= \^auto_pre_r_lcl_reg_1\;
  head_r_lcl_reg_2 <= \^head_r_lcl_reg_2\;
  pre_bm_end_r <= \^pre_bm_end_r\;
  pre_passing_open_bank_r <= \^pre_passing_open_bank_r\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  \q_entry_r_reg[1]_1\ <= \^q_entry_r_reg[1]_1\;
  q_has_priority <= \^q_has_priority\;
  \ras_timer_r_reg[0]\ <= \^ras_timer_r_reg[0]\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2 downto 0) <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2 downto 0);
  \req_data_buf_addr_r_reg[4]\ <= \^req_data_buf_addr_r_reg[4]\;
  wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\;
accept_internal_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => \^accept_internal_r_reg\,
      I2 => idle_r_lcl_reg_4,
      I3 => idle_r_lcl_reg_3,
      I4 => idle_r_lcl_reg_2,
      O => p_7_in
    );
act_wait_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF44F4"
    )
        port map (
      I0 => act_wait_r_lcl_i_2_n_0,
      I1 => act_wait_r_lcl_reg_2,
      I2 => \^act_wait_r_lcl_reg\,
      I3 => \^act_wait_r_lcl_reg_0\,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      I5 => bm_end_r1_reg_0,
      O => act_wait_ns
    );
act_wait_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBABAA"
    )
        port map (
      I0 => act_wait_r_lcl_reg_3,
      I1 => \^act_wait_r_lcl_reg_1\,
      I2 => pre_passing_open_bank_r_reg_0,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1),
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\,
      O => act_wait_r_lcl_i_2_n_0
    );
\auto_pre_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAAEEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_1\,
      I1 => \compute_tail.tail_r_lcl_reg_0\,
      I2 => \^auto_pre_r_lcl_reg_0\,
      I3 => \maint_controller.maint_wip_r_lcl_reg\,
      I4 => row_hit_r,
      I5 => req_wr_r_lcl_reg,
      O => \auto_pre_r_lcl_i_1__0_n_0\
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \auto_pre_r_lcl_i_1__0_n_0\,
      Q => \^auto_pre_r_lcl_reg_1\,
      R => '0'
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => idle_r_lcl_reg_0,
      Q => tail_r,
      R => SR(0)
    );
demand_priority_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544454445444FFFF"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_0,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => req_wr_r_lcl_reg_1,
      I4 => \^q_has_priority\,
      I5 => req_priority_r,
      O => demand_priority_r_reg
    );
\grant_r[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF44544444"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_0,
      I1 => order_q_r(1),
      I2 => order_q_r(0),
      I3 => rd_wr_r_lcl_reg_1,
      I4 => req_wr_r_lcl_reg_2,
      I5 => rnk_config_valid_r_lcl_reg,
      O => \grant_r_reg[0]_0\
    );
head_r_lcl_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => head_r_lcl_reg_4,
      Q => \^wait_for_maint_r_lcl_reg_0\,
      S => SR(0)
    );
\i___0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55151515"
    )
        port map (
      I0 => \^pre_bm_end_r\,
      I1 => \grant_r_reg[0]_1\(0),
      I2 => \^act_wait_r_lcl_reg\,
      I3 => rd_wr_r_lcl_reg_0,
      I4 => req_wr_r_lcl_reg_0,
      O => \^act_wait_r_lcl_reg_0\
    );
\i___1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40404040404F4F40"
    )
        port map (
      I0 => q_entry_r(1),
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => idle_r_lcl_reg_5,
      I3 => rb_hit_busy_r_reg,
      I4 => \^head_r_lcl_reg_2\,
      I5 => rb_hit_busy_r_reg_0,
      O => head_r_lcl_reg_1
    );
\i___1_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80010116"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => idle_r_lcl_reg_6(0),
      I2 => idle_r_lcl_reg_7(0),
      I3 => idle_r_lcl_reg_8(0),
      I4 => periodic_rd_ack_r_lcl_reg,
      O => head_r_lcl_reg_3
    );
\i___22_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => pre_passing_open_bank_r_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2),
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1),
      I4 => pre_passing_open_bank_r_reg_0,
      I5 => \^act_wait_r_lcl_reg_1\,
      O => \^ras_timer_r_reg[0]\
    );
\i___22_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => q_entry_r(1),
      O => \^act_wait_r_lcl_reg_1\
    );
\i___24_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55151515"
    )
        port map (
      I0 => \^pre_passing_open_bank_r\,
      I1 => \grant_r_reg[0]_1\(0),
      I2 => \^act_wait_r_lcl_reg\,
      I3 => rd_wr_r_lcl_reg_0,
      I4 => req_wr_r_lcl_reg_0,
      O => \ras_timer_r_reg[0]_0\
    );
\i___26_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => idle_r_lcl_reg_6(0),
      I2 => idle_r_lcl_reg_7(0),
      I3 => idle_r_lcl_reg_8(0),
      O => \^q_entry_r_reg[1]_1\
    );
\i___33_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000DDD0DDD0DDD"
    )
        port map (
      I0 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0),
      I1 => pre_bm_end_r_reg_0,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2),
      I3 => pre_bm_end_r_reg_2,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1),
      I5 => pre_bm_end_r_reg_1,
      O => \^head_r_lcl_reg_2\
    );
\i___41_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => periodic_rd_ack_r_lcl_reg_1,
      I2 => use_addr,
      I3 => accept_internal_r_reg_0,
      I4 => \^wait_for_maint_r_lcl_reg_0\,
      I5 => req_wr_r_lcl_reg,
      O => \^accept_internal_r_reg\
    );
\i___59_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF7F"
    )
        port map (
      I0 => \^wait_for_maint_r_lcl_reg_0\,
      I1 => ras_timer_zero_r,
      I2 => act_wait_r_lcl_reg_2,
      I3 => \^req_data_buf_addr_r_reg[4]\,
      I4 => \^auto_pre_r_lcl_reg_0\,
      O => \grant_r_reg[0]\
    );
\i___6_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^act_wait_r_lcl_reg_0\,
      I1 => pre_bm_end_r_reg_0,
      I2 => pre_bm_end_r_reg_1,
      O => head_r_lcl_reg_0
    );
\idle_r_lcl_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^accept_internal_r_reg\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^req_data_buf_addr_r_reg[4]\,
      R => '0'
    );
\order_q_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"553100305531CC30"
    )
        port map (
      I0 => ordered_r_lcl_reg_2,
      I1 => order_q_r(0),
      I2 => order_q_r(1),
      I3 => req_wr_r_lcl_reg_1,
      I4 => set_order_q,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[0]_i_1_n_0\
    );
\order_q_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAC200C0AAC2F0C0"
    )
        port map (
      I0 => ordered_r_lcl_reg_1,
      I1 => order_q_r(0),
      I2 => order_q_r(1),
      I3 => req_wr_r_lcl_reg_1,
      I4 => set_order_q,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[1]_i_1_n_0\
    );
\order_q_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080000000"
    )
        port map (
      I0 => req_wr_r_lcl_reg_0,
      I1 => \^req_data_buf_addr_r_reg[4]\,
      I2 => \^wait_for_maint_r_lcl_reg_0\,
      I3 => accept_internal_r_reg_0,
      I4 => use_addr,
      I5 => periodic_rd_ack_r_lcl_reg_1,
      O => set_order_q
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1_n_0\,
      Q => order_q_r(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1_n_0\,
      Q => order_q_r(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ordered_r_lcl_reg_0,
      Q => ordered_r(0),
      R => '0'
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pass_open_bank_ns,
      Q => \^act_wait_r_lcl_reg\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => \^pre_bm_end_r\,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => \^pre_passing_open_bank_r\,
      R => '0'
    );
\q_entry_r[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^head_r_lcl_reg_2\,
      I1 => rb_hit_busy_r_reg_1,
      I2 => rb_hit_busy_r_reg_2,
      I3 => rb_hit_busy_r_reg_3,
      I4 => rb_hit_busy_r_reg_4,
      O => \q_entry_r_reg[0]_1\
    );
\q_entry_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => q_entry_ns_0(1),
      I1 => idle_r_lcl_reg_1,
      I2 => q_entry_r(1),
      O => \q_entry_r[1]_i_1_n_0\
    );
\q_entry_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9AA6599A"
    )
        port map (
      I0 => \q_entry_r[1]_i_4__1_n_0\,
      I1 => \^act_wait_r_lcl_reg_0\,
      I2 => \^q_entry_r_reg[1]_1\,
      I3 => pre_bm_end_r_reg_1,
      I4 => pre_bm_end_r_reg_0,
      O => \q_entry_r_reg[1]_2\
    );
\q_entry_r[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BB88B88B8BB8BB88"
    )
        port map (
      I0 => \q_entry_r_reg[1]_5\,
      I1 => pre_bm_end_r_reg_0,
      I2 => periodic_rd_ack_r_lcl_reg,
      I3 => \q_entry_r[1]_i_4__1_n_0\,
      I4 => \^q_entry_r_reg[1]_1\,
      I5 => \^act_wait_r_lcl_reg_0\,
      O => q_entry_ns(0)
    );
\q_entry_r[1]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"32FE01CD"
    )
        port map (
      I0 => \^q_entry_r_reg[1]_1\,
      I1 => \^act_wait_r_lcl_reg_0\,
      I2 => periodic_rd_ack_r_lcl_reg,
      I3 => \q_entry_r[1]_i_3__1_n_0\,
      I4 => \q_entry_r[1]_i_4__1_n_0\,
      O => q_entry_ns_0(1)
    );
\q_entry_r[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C3CC33C355555555"
    )
        port map (
      I0 => \q_entry_r_reg[1]_4\,
      I1 => \q_entry_r[1]_i_4__1_n_0\,
      I2 => pre_bm_end_r_reg_0,
      I3 => \^q_entry_r_reg[1]_1\,
      I4 => \^act_wait_r_lcl_reg_0\,
      I5 => pre_bm_end_r_reg_1,
      O => \q_entry_r_reg[1]_3\
    );
\q_entry_r[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1E001EFF1EFF1E00"
    )
        port map (
      I0 => rb_hit_busy_r_reg,
      I1 => \^head_r_lcl_reg_2\,
      I2 => rb_hit_busy_r_reg_0,
      I3 => periodic_rd_ack_r_lcl_reg_0,
      I4 => q_entry_r(1),
      I5 => \^q_entry_r_reg[0]_0\,
      O => \q_entry_r[1]_i_3__1_n_0\
    );
\q_entry_r[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6339C663"
    )
        port map (
      I0 => \^q_entry_r_reg[1]_1\,
      I1 => \q_entry_r[1]_i_4__1_n_0\,
      I2 => \^act_wait_r_lcl_reg_0\,
      I3 => pre_bm_end_r_reg_0,
      I4 => pre_bm_end_r_reg_1,
      O => \q_entry_r_reg[1]_0\
    );
\q_entry_r[1]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => idle_r_lcl_reg_8(0),
      I2 => idle_r_lcl_reg_7(0),
      I3 => idle_r_lcl_reg_6(0),
      O => \q_entry_r[1]_i_4__1_n_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r_reg[0]_2\,
      Q => \^q_entry_r_reg[0]_0\,
      R => SR(0)
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[1]_i_1_n_0\,
      Q => q_entry_r(1),
      R => SR(0)
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => \^q_has_priority\,
      R => '0'
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_r_reg_0,
      Q => q_has_rd,
      R => '0'
    );
\ras_timer_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__2_n_0\,
      I1 => \^ras_timer_r_reg[0]\,
      I2 => rd_wr_r_lcl_reg,
      O => \ras_timer_r_reg[1]\(0)
    );
\ras_timer_r[0]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB8888B888B888"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_2,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2),
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0),
      I3 => rd_wr_r_lcl_reg_3,
      I4 => rd_wr_r_lcl_reg_4,
      I5 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1),
      O => \ras_timer_r[0]_i_2__2_n_0\
    );
\ras_timer_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__2_n_0\,
      I1 => \^ras_timer_r_reg[0]\,
      I2 => bm_end_r1_reg,
      O => \ras_timer_r_reg[1]\(1)
    );
\ras_timer_r[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => bm_end_r1_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2),
      I2 => bm_end_r1_reg_2,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1),
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0),
      I5 => bm_end_r1_reg_3,
      O => \ras_timer_r[1]_i_2__2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2020000"
    )
        port map (
      I0 => \^accept_internal_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      I2 => idle_r_lcl_reg_2,
      I3 => Q(0),
      I4 => \^act_wait_r_lcl_reg_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => D(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2020000"
    )
        port map (
      I0 => \^accept_internal_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      I2 => idle_r_lcl_reg_3,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\(0),
      I4 => \^act_wait_r_lcl_reg_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2020000"
    )
        port map (
      I0 => \^accept_internal_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      I2 => idle_r_lcl_reg_4,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(0),
      I4 => \^act_wait_r_lcl_reg_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(1),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(2),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2),
      R => '0'
    );
\rb_hit_busy_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^accept_internal_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      O => p_145_out
    );
req_bank_rdy_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8A8A"
    )
        port map (
      I0 => col_wait_r_reg,
      I1 => rd_wr_r_lcl_reg_0,
      I2 => order_q_r(1),
      I3 => order_q_r(0),
      I4 => req_wr_r_lcl_reg_1,
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => \maintenance_request.maint_req_r_lcl_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized0\ is
  port (
    \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    pre_passing_open_bank_r : out STD_LOGIC;
    q_has_rd_4 : out STD_LOGIC;
    q_has_priority_5 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    tail_r_19 : out STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg_1 : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    \maint_controller.maint_rdy\ : out STD_LOGIC;
    p_106_out : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    act_wait_ns : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : out STD_LOGIC;
    \q_entry_r_reg[0]_2\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    granted_row_ns : out STD_LOGIC;
    granted_row_r_reg : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    order_q_r : out STD_LOGIC_VECTOR ( 1 downto 0 );
    req_bank_rdy_ns : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    \req_bank_r_lcl_reg[0]\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_3 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    idle_r_lcl_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_5 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    bm_end_r1_0 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    idle_r_lcl_reg_7 : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg_1 : in STD_LOGIC;
    pre_bm_end_r_reg_2 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_2 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    bm_end_r1_reg_3 : in STD_LOGIC;
    req_wr_r_lcl_reg_1 : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    q_entry_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_8 : in STD_LOGIC;
    idle_r_lcl_reg_9 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    ordered_r_lcl_reg_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized0\ : entity is "mig_7series_v2_3_bank_queue";
end \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized0\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \act_wait_r_lcl_i_2__2_n_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC;
  signal auto_pre_r_lcl_i_1_n_0 : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_1\ : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^grant_r_reg[1]\ : STD_LOGIC;
  signal \^granted_row_r_reg\ : STD_LOGIC;
  signal \^order_q_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_r\ : STD_LOGIC;
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \q_entry_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_2\ : STD_LOGIC;
  signal \^q_has_priority_5\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[0]_0\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^req_data_buf_addr_r_reg[4]\ : STD_LOGIC;
  signal set_order_q : STD_LOGIC;
  signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i___42_i_4\ : label is "soft_lutpair985";
  attribute SOFT_HLUTNM of idle_r_lcl_i_1 : label is "soft_lutpair987";
  attribute SOFT_HLUTNM of \q_entry_r[1]_i_1__0\ : label is "soft_lutpair985";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__2\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__2\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of rb_hit_busy_r_i_1 : label is "soft_lutpair987";
begin
  E(0) <= \^e\(0);
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\;
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  auto_pre_r_lcl_reg_1 <= \^auto_pre_r_lcl_reg_1\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  \grant_r_reg[1]\ <= \^grant_r_reg[1]\;
  granted_row_r_reg <= \^granted_row_r_reg\;
  order_q_r(1 downto 0) <= \^order_q_r\(1 downto 0);
  pre_passing_open_bank_r <= \^pre_passing_open_bank_r\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  \q_entry_r_reg[0]_2\ <= \^q_entry_r_reg[0]_2\;
  q_has_priority_5 <= \^q_has_priority_5\;
  \ras_timer_r_reg[0]_0\ <= \^ras_timer_r_reg[0]_0\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2 downto 0) <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2 downto 0);
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  \req_data_buf_addr_r_reg[4]\ <= \^req_data_buf_addr_r_reg[4]\;
  wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\;
\act_wait_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF44F4"
    )
        port map (
      I0 => \act_wait_r_lcl_i_2__2_n_0\,
      I1 => act_wait_r_lcl_reg_1,
      I2 => \^act_wait_r_lcl_reg\,
      I3 => \^q_entry_r_reg[0]_0\,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      I5 => bm_end_r1_0,
      O => act_wait_ns
    );
\act_wait_r_lcl_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBABAA"
    )
        port map (
      I0 => act_wait_r_lcl_reg_2,
      I1 => \^act_wait_r_lcl_reg_0\,
      I2 => pre_passing_open_bank_r_reg_0,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(1),
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\,
      O => \act_wait_r_lcl_i_2__2_n_0\
    );
auto_pre_r_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAAEEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_1\,
      I1 => \compute_tail.tail_r_lcl_reg_1\,
      I2 => \^auto_pre_r_lcl_reg_0\,
      I3 => \maint_controller.maint_wip_r_lcl_reg_0\,
      I4 => row_hit_r,
      I5 => req_wr_r_lcl_reg_0,
      O => auto_pre_r_lcl_i_1_n_0
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => auto_pre_r_lcl_i_1_n_0,
      Q => \^auto_pre_r_lcl_reg_1\,
      R => '0'
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => idle_r_lcl_reg_0,
      Q => tail_r_19,
      R => SR(0)
    );
\demand_priority_r_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544454445444FFFF"
    )
        port map (
      I0 => rd_wr_r_lcl_reg,
      I1 => \^order_q_r\(1),
      I2 => \^order_q_r\(0),
      I3 => req_wr_r_lcl_reg_1,
      I4 => \^q_has_priority_5\,
      I5 => req_priority_r,
      O => demand_priority_r_reg
    );
\grant_r[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEFFFFFFF"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_0\,
      I1 => \^req_data_buf_addr_r_reg[4]\,
      I2 => act_wait_r_lcl_reg_1,
      I3 => ras_timer_zero_r,
      I4 => \^wait_for_maint_r_lcl_reg_0\,
      I5 => \grant_r_reg[1]_1\,
      O => \^grant_r_reg[1]\
    );
\grant_r[3]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^grant_r_reg[1]\,
      I1 => act_wait_r_lcl_reg_3,
      O => \^granted_row_r_reg\
    );
granted_row_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^granted_row_r_reg\,
      I1 => wait_for_maint_r_lcl_reg_2,
      O => granted_row_ns
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => head_r_lcl_reg_1,
      Q => \^wait_for_maint_r_lcl_reg_0\,
      R => SR(0)
    );
\i___24_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55151515"
    )
        port map (
      I0 => \^pre_passing_open_bank_r\,
      I1 => \grant_r_reg[1]_0\(0),
      I2 => \^act_wait_r_lcl_reg\,
      I3 => rd_wr_r_lcl_reg,
      I4 => req_wr_r_lcl_reg,
      O => \ras_timer_r_reg[0]\
    );
\i___28_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => pre_bm_end_r_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(1),
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0),
      I3 => pre_bm_end_r_reg_2,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2),
      I5 => pre_bm_end_r_reg_0,
      O => \^q_entry_r_reg[0]_2\
    );
\i___29_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => periodic_rd_ack_r_lcl_reg,
      I2 => use_addr,
      I3 => accept_internal_r_reg,
      I4 => \^wait_for_maint_r_lcl_reg_0\,
      I5 => req_wr_r_lcl_reg_0,
      O => \^rb_hit_busy_r_reg\
    );
\i___2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55151515"
    )
        port map (
      I0 => \^bm_end_r1_reg\,
      I1 => \grant_r_reg[1]_0\(0),
      I2 => \^act_wait_r_lcl_reg\,
      I3 => rd_wr_r_lcl_reg,
      I4 => req_wr_r_lcl_reg,
      O => \^q_entry_r_reg[0]_0\
    );
\i___3_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000014141414"
    )
        port map (
      I0 => rb_hit_busy_r_reg_1,
      I1 => \^q_entry_r_reg[0]_2\,
      I2 => rb_hit_busy_r_reg_0,
      I3 => q_entry_r(1),
      I4 => q_entry_r(0),
      I5 => idle_r_lcl_reg_7,
      O => head_r_lcl_reg_0
    );
\i___42_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => q_entry_r(0),
      I2 => q_entry_r(1),
      O => \^act_wait_r_lcl_reg_0\
    );
\i___43_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => pre_passing_open_bank_r_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2),
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(1),
      I4 => pre_passing_open_bank_r_reg_0,
      I5 => \^act_wait_r_lcl_reg_0\,
      O => \^ras_timer_r_reg[0]_0\
    );
\i___4_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^q_entry_r_reg[0]_0\,
      I1 => pre_bm_end_r_reg_0,
      I2 => pre_bm_end_r_reg_1,
      O => \compute_tail.tail_r_lcl_reg_0\
    );
idle_r_lcl_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^req_data_buf_addr_r_reg[4]\,
      R => '0'
    );
\maint_controller.maint_rdy_r1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000054"
    )
        port map (
      I0 => \maint_controller.maint_hit_busies_r_reg[3]\(1),
      I1 => \maint_controller.maint_wip_r_lcl_reg\,
      I2 => maint_req_r,
      I3 => \maint_controller.maint_hit_busies_r_reg[3]\(3),
      I4 => \maint_controller.maint_hit_busies_r_reg[3]\(2),
      I5 => \maint_controller.maint_hit_busies_r_reg[3]\(0),
      O => \maint_controller.maint_rdy\
    );
\order_q_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"553100305531CC30"
    )
        port map (
      I0 => ordered_r_lcl_reg_2,
      I1 => \^order_q_r\(0),
      I2 => \^order_q_r\(1),
      I3 => req_wr_r_lcl_reg_1,
      I4 => set_order_q,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[0]_i_1__0_n_0\
    );
\order_q_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAC200C0AAC2F0C0"
    )
        port map (
      I0 => ordered_r_lcl_reg_1,
      I1 => \^order_q_r\(0),
      I2 => \^order_q_r\(1),
      I3 => req_wr_r_lcl_reg_1,
      I4 => set_order_q,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[1]_i_1__0_n_0\
    );
\order_q_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080000000"
    )
        port map (
      I0 => req_wr_r_lcl_reg,
      I1 => \^req_data_buf_addr_r_reg[4]\,
      I2 => \^wait_for_maint_r_lcl_reg_0\,
      I3 => accept_internal_r_reg,
      I4 => use_addr,
      I5 => periodic_rd_ack_r_lcl_reg,
      O => set_order_q
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1__0_n_0\,
      Q => \^order_q_r\(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1__0_n_0\,
      Q => \^order_q_r\(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ordered_r_lcl_reg_0,
      Q => ordered_r(0),
      R => '0'
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pass_open_bank_ns,
      Q => \^act_wait_r_lcl_reg\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => \^bm_end_r1_reg\,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => \^pre_passing_open_bank_r\,
      R => '0'
    );
\q_entry_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B88BFFFFB88B0000"
    )
        port map (
      I0 => \q_entry_r[0]_i_2__2_n_0\,
      I1 => \^q_entry_r_reg[0]_0\,
      I2 => idle_r_lcl_reg_9,
      I3 => periodic_rd_ack_r_lcl_reg_1,
      I4 => idle_r_lcl_reg_8,
      I5 => q_entry_r(0),
      O => \q_entry_r[0]_i_1__0_n_0\
    );
\q_entry_r[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \^q_entry_r_reg[0]_0\,
      I1 => idle_r_lcl_reg_4(0),
      I2 => \^req_data_buf_addr_r_reg[4]\,
      I3 => idle_r_lcl_reg_5(0),
      I4 => idle_r_lcl_reg_6(0),
      I5 => pre_bm_end_r_reg_0,
      O => \q_entry_r_reg[0]_1\
    );
\q_entry_r[0]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"909F"
    )
        port map (
      I0 => rb_hit_busy_r_reg_0,
      I1 => \^q_entry_r_reg[0]_2\,
      I2 => periodic_rd_ack_r_lcl_reg_0,
      I3 => q_entry_r(0),
      O => \q_entry_r[0]_i_2__2_n_0\
    );
\q_entry_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => q_entry_ns(0),
      I1 => idle_r_lcl_reg_8,
      I2 => q_entry_r(1),
      O => \q_entry_r[1]_i_1__0_n_0\
    );
\q_entry_r[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8EE7E771E7717118"
    )
        port map (
      I0 => \^q_entry_r_reg[0]_0\,
      I1 => pre_bm_end_r_reg_0,
      I2 => idle_r_lcl_reg_6(0),
      I3 => idle_r_lcl_reg_5(0),
      I4 => \^req_data_buf_addr_r_reg[4]\,
      I5 => idle_r_lcl_reg_4(0),
      O => \q_entry_r_reg[1]_0\
    );
\q_entry_r[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9FFA900A900A9FF"
    )
        port map (
      I0 => rb_hit_busy_r_reg_1,
      I1 => \^q_entry_r_reg[0]_2\,
      I2 => rb_hit_busy_r_reg_0,
      I3 => periodic_rd_ack_r_lcl_reg_0,
      I4 => q_entry_r(1),
      I5 => q_entry_r(0),
      O => \q_entry_r_reg[1]_1\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[0]_i_1__0_n_0\,
      Q => q_entry_r(0),
      S => SR(0)
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[1]_i_1__0_n_0\,
      Q => q_entry_r(1),
      R => SR(0)
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => \^q_has_priority_5\,
      R => '0'
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_r_reg_0,
      Q => q_has_rd_4,
      R => '0'
    );
\ras_timer_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__1_n_0\,
      I1 => \^ras_timer_r_reg[0]_0\,
      I2 => rd_wr_r_lcl_reg_0,
      O => \ras_timer_r_reg[1]\(0)
    );
\ras_timer_r[0]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBB8888888B888"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2),
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0),
      I3 => rd_wr_r_lcl_reg_2,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(1),
      I5 => rd_wr_r_lcl_reg_3,
      O => \ras_timer_r[0]_i_2__1_n_0\
    );
\ras_timer_r[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__1_n_0\,
      I1 => \^ras_timer_r_reg[0]_0\,
      I2 => bm_end_r1_reg_0,
      O => \ras_timer_r_reg[1]\(1)
    );
\ras_timer_r[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => bm_end_r1_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2),
      I2 => bm_end_r1_reg_2,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(1),
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0),
      I5 => bm_end_r1_reg_3,
      O => \ras_timer_r[1]_i_2__1_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2020000"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      I2 => idle_r_lcl_reg_3,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\(0),
      I4 => \^q_entry_r_reg[0]_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2020000"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      I2 => idle_r_lcl_reg_1,
      I3 => Q(0),
      I4 => \^q_entry_r_reg[0]_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => D(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2020000"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      I2 => idle_r_lcl_reg_2,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      I4 => \^q_entry_r_reg[0]_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(0),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(1),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(1),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(2),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2),
      R => '0'
    );
rb_hit_busy_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      O => p_106_out
    );
\req_bank_rdy_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8A8A"
    )
        port map (
      I0 => col_wait_r_reg,
      I1 => rd_wr_r_lcl_reg,
      I2 => \^order_q_r\(1),
      I3 => \^order_q_r\(0),
      I4 => req_wr_r_lcl_reg_1,
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => \maintenance_request.maint_req_r_lcl_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized1\ is
  port (
    \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    pre_passing_open_bank_r : out STD_LOGIC;
    q_has_rd_9 : out STD_LOGIC;
    q_has_priority_10 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    tail_r_20 : out STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg_1 : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ras_timer_r_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    act_wait_ns : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    head_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_2\ : out STD_LOGIC;
    p_67_out : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    order_q_r : out STD_LOGIC_VECTOR ( 1 downto 0 );
    granted_row_r_reg : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_3 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    bm_end_r1_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    idle_r_lcl_reg_4 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    pre_bm_end_r_reg_2 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    bm_end_r1_reg_3 : in STD_LOGIC;
    req_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    \grant_r_reg[3]\ : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \grant_r_reg[2]_2\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    idle_r_lcl_reg_5 : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    idle_r_lcl_reg_6 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    req_wr_r_lcl_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized1\ : entity is "mig_7series_v2_3_bank_queue";
end \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized1\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \act_wait_r_lcl_i_2__1_n_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \auto_pre_r_lcl_i_1__2_n_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_1\ : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^grant_r_reg[2]_0\ : STD_LOGIC;
  signal \^order_q_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_r\ : STD_LOGIC;
  signal \^pre_bm_end_r\ : STD_LOGIC;
  signal \^pre_passing_open_bank_r\ : STD_LOGIC;
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \q_entry_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_2\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[0]\ : STD_LOGIC;
  signal \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^req_data_buf_addr_r_reg[4]\ : STD_LOGIC;
  signal set_order_q : STD_LOGIC;
  signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__0\ : label is "soft_lutpair994";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__1\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__1\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \rb_hit_busy_r_i_1__0\ : label is "soft_lutpair994";
begin
  E(0) <= \^e\(0);
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  auto_pre_r_lcl_reg_1 <= \^auto_pre_r_lcl_reg_1\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  \grant_r_reg[2]_0\ <= \^grant_r_reg[2]_0\;
  order_q_r(1 downto 0) <= \^order_q_r\(1 downto 0);
  pass_open_bank_r <= \^pass_open_bank_r\;
  pre_bm_end_r <= \^pre_bm_end_r\;
  pre_passing_open_bank_r <= \^pre_passing_open_bank_r\;
  \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\;
  \q_entry_r_reg[1]_2\ <= \^q_entry_r_reg[1]_2\;
  \ras_timer_r_reg[0]\ <= \^ras_timer_r_reg[0]\;
  \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(2 downto 0) <= \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(2 downto 0);
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  \req_data_buf_addr_r_reg[4]\ <= \^req_data_buf_addr_r_reg[4]\;
  wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\;
\act_wait_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF444"
    )
        port map (
      I0 => \act_wait_r_lcl_i_2__1_n_0\,
      I1 => act_wait_r_lcl_reg_0,
      I2 => \^pass_open_bank_r\,
      I3 => \^bm_end_r1_reg\,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      I5 => bm_end_r1_1,
      O => act_wait_ns
    );
\act_wait_r_lcl_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBABAA"
    )
        port map (
      I0 => act_wait_r_lcl_reg_1,
      I1 => \^act_wait_r_lcl_reg\,
      I2 => pre_passing_open_bank_r_reg_0,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      O => \act_wait_r_lcl_i_2__1_n_0\
    );
\auto_pre_r_lcl_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAAEEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_1\,
      I1 => \compute_tail.tail_r_lcl_reg_0\,
      I2 => \^auto_pre_r_lcl_reg_0\,
      I3 => \maint_controller.maint_wip_r_lcl_reg\,
      I4 => row_hit_r,
      I5 => req_wr_r_lcl_reg,
      O => \auto_pre_r_lcl_i_1__2_n_0\
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \auto_pre_r_lcl_i_1__2_n_0\,
      Q => \^auto_pre_r_lcl_reg_1\,
      R => '0'
    );
\bm_end_r1_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEAEAEA"
    )
        port map (
      I0 => \^pre_bm_end_r\,
      I1 => \grant_r_reg[2]_1\(0),
      I2 => \^pass_open_bank_r\,
      I3 => rd_wr_r_lcl_reg_0,
      I4 => req_wr_r_lcl_reg_0,
      O => \^bm_end_r1_reg\
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => idle_r_lcl_reg_0,
      Q => tail_r_20,
      R => SR(0)
    );
\grant_r[1]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^grant_r_reg[2]_0\,
      I1 => \grant_r_reg[3]\,
      O => granted_row_r_reg
    );
\grant_r[3]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FF20"
    )
        port map (
      I0 => req_wr_r_lcl_reg_1,
      I1 => rd_wr_r_lcl_reg_4,
      I2 => \^order_q_r\(0),
      I3 => \^order_q_r\(1),
      I4 => rd_wr_r_lcl_reg_0,
      O => \grant_r_reg[2]\
    );
\grant_r[3]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEFFFFFFF"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_0\,
      I1 => \^req_data_buf_addr_r_reg[4]\,
      I2 => act_wait_r_lcl_reg_0,
      I3 => ras_timer_zero_r,
      I4 => \^wait_for_maint_r_lcl_reg_0\,
      I5 => \grant_r_reg[2]_2\,
      O => \^grant_r_reg[2]_0\
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => head_r_lcl_reg_1,
      Q => \^wait_for_maint_r_lcl_reg_0\,
      R => SR(0)
    );
\i___22_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55151515"
    )
        port map (
      I0 => \^pre_passing_open_bank_r\,
      I1 => \grant_r_reg[2]_1\(0),
      I2 => \^pass_open_bank_r\,
      I3 => rd_wr_r_lcl_reg_0,
      I4 => req_wr_r_lcl_reg_0,
      O => \ras_timer_r_reg[0]_0\
    );
\i___25_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => pre_passing_open_bank_r_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(1),
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      I4 => pre_passing_open_bank_r_reg_0,
      I5 => \^act_wait_r_lcl_reg\,
      O => \^ras_timer_r_reg[0]\
    );
\i___25_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => q_entry_r(0),
      I2 => q_entry_r(1),
      O => \^act_wait_r_lcl_reg\
    );
\i___36_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => periodic_rd_ack_r_lcl_reg_1,
      I2 => use_addr,
      I3 => accept_internal_r_reg,
      I4 => \^wait_for_maint_r_lcl_reg_0\,
      I5 => req_wr_r_lcl_reg,
      O => \^rb_hit_busy_r_reg\
    );
\i___5_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000014141414"
    )
        port map (
      I0 => rb_hit_busy_r_reg_0,
      I1 => \^q_entry_r_reg[1]_0\,
      I2 => rb_hit_busy_r_reg_1,
      I3 => q_entry_r(1),
      I4 => q_entry_r(0),
      I5 => idle_r_lcl_reg_4,
      O => head_r_lcl_reg_0
    );
\i___5_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF1D"
    )
        port map (
      I0 => \^q_entry_r_reg[1]_0\,
      I1 => \^req_data_buf_addr_r_reg[4]\,
      I2 => periodic_rd_ack_r_lcl_reg_0,
      I3 => periodic_rd_ack_r_lcl_reg,
      I4 => \^bm_end_r1_reg\,
      O => \^q_entry_r_reg[1]_2\
    );
\i___5_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDD0DDD00000DDD"
    )
        port map (
      I0 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(2),
      I1 => pre_bm_end_r_reg_0,
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      I3 => pre_bm_end_r_reg_1,
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(1),
      I5 => pre_bm_end_r_reg_2,
      O => \^q_entry_r_reg[1]_0\
    );
\idle_r_lcl_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^req_data_buf_addr_r_reg[4]\,
      R => '0'
    );
\order_q_r[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"553100305531CC30"
    )
        port map (
      I0 => ordered_r_lcl_reg_2,
      I1 => \^order_q_r\(0),
      I2 => \^order_q_r\(1),
      I3 => req_wr_r_lcl_reg_2,
      I4 => set_order_q,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[0]_i_1__1_n_0\
    );
\order_q_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAC200C0AAC2F0C0"
    )
        port map (
      I0 => ordered_r_lcl_reg_1,
      I1 => \^order_q_r\(0),
      I2 => \^order_q_r\(1),
      I3 => req_wr_r_lcl_reg_2,
      I4 => set_order_q,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[1]_i_1__1_n_0\
    );
\order_q_r[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080000000"
    )
        port map (
      I0 => req_wr_r_lcl_reg_0,
      I1 => \^req_data_buf_addr_r_reg[4]\,
      I2 => \^wait_for_maint_r_lcl_reg_0\,
      I3 => accept_internal_r_reg,
      I4 => use_addr,
      I5 => periodic_rd_ack_r_lcl_reg_1,
      O => set_order_q
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1__1_n_0\,
      Q => \^order_q_r\(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1__1_n_0\,
      Q => \^order_q_r\(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ordered_r_lcl_reg_0,
      Q => ordered_r(0),
      R => '0'
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pass_open_bank_ns,
      Q => \^pass_open_bank_r\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => \^pre_bm_end_r\,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => \^pre_passing_open_bank_r\,
      R => '0'
    );
\q_entry_r[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => periodic_rd_ack_r_lcl_reg_0,
      I1 => \^bm_end_r1_reg\,
      I2 => idle_r_lcl_reg_6,
      I3 => \q_entry_r[0]_i_3_n_0\,
      I4 => \^q_entry_r_reg[1]_2\,
      I5 => q_entry_r(0),
      O => \q_entry_r[0]_i_1__1_n_0\
    );
\q_entry_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0099000FFF99FF0F"
    )
        port map (
      I0 => rb_hit_busy_r_reg_1,
      I1 => \^q_entry_r_reg[1]_0\,
      I2 => q_entry_r(0),
      I3 => \^bm_end_r1_reg\,
      I4 => periodic_rd_ack_r_lcl_reg,
      I5 => periodic_rd_ack_r_lcl_reg_0,
      O => \q_entry_r[0]_i_3_n_0\
    );
\q_entry_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => idle_r_lcl_reg_5,
      I1 => \^bm_end_r1_reg\,
      I2 => periodic_rd_ack_r_lcl_reg_0,
      I3 => \q_entry_r_reg[1]_3\,
      I4 => \^q_entry_r_reg[1]_2\,
      I5 => q_entry_r(1),
      O => \q_entry_r[1]_i_1__1_n_0\
    );
\q_entry_r[1]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"560056FF56FF5600"
    )
        port map (
      I0 => rb_hit_busy_r_reg_0,
      I1 => \^q_entry_r_reg[1]_0\,
      I2 => rb_hit_busy_r_reg_1,
      I3 => periodic_rd_ack_r_lcl_reg,
      I4 => q_entry_r(1),
      I5 => q_entry_r(0),
      O => \q_entry_r_reg[1]_1\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[0]_i_1__1_n_0\,
      Q => q_entry_r(0),
      R => SR(0)
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[1]_i_1__1_n_0\,
      Q => q_entry_r(1),
      S => SR(0)
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => q_has_priority_10,
      R => '0'
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_r_reg_0,
      Q => q_has_rd_9,
      R => '0'
    );
\ras_timer_r[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2__0_n_0\,
      I1 => \^ras_timer_r_reg[0]\,
      I2 => rd_wr_r_lcl_reg,
      O => \ras_timer_r_reg[1]\(0)
    );
\ras_timer_r[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB8888B888B888"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(2),
      I2 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      I3 => rd_wr_r_lcl_reg_2,
      I4 => rd_wr_r_lcl_reg_3,
      I5 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(1),
      O => \ras_timer_r[0]_i_2__0_n_0\
    );
\ras_timer_r[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2__0_n_0\,
      I1 => \^ras_timer_r_reg[0]\,
      I2 => bm_end_r1_reg_0,
      O => \ras_timer_r_reg[1]\(1)
    );
\ras_timer_r[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => bm_end_r1_reg_1,
      I1 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(2),
      I2 => bm_end_r1_reg_2,
      I3 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(1),
      I4 => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      I5 => bm_end_r1_reg_3,
      O => \ras_timer_r[1]_i_2__0_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F202"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      I2 => idle_r_lcl_reg_2,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\(0),
      I4 => \^bm_end_r1_reg\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F202"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      I2 => idle_r_lcl_reg_3,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\(0),
      I4 => \^bm_end_r1_reg\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F202"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      I2 => idle_r_lcl_reg_1,
      I3 => Q(0),
      I4 => \^bm_end_r1_reg\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => D(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\(0),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\(1),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(1),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\(2),
      Q => \^rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(2),
      R => '0'
    );
\rb_hit_busy_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[2]\,
      O => p_67_out
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => \maintenance_request.maint_req_r_lcl_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized2\ is
  port (
    \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    pass_open_bank_r : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    pre_passing_open_bank_r : out STD_LOGIC;
    q_has_rd_14 : out STD_LOGIC;
    q_has_priority_15 : out STD_LOGIC;
    auto_pre_r_lcl_reg_0 : out STD_LOGIC;
    tail_r_21 : out STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : out STD_LOGIC;
    auto_pre_r_lcl_reg_1 : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    act_wait_ns : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    p_28_out : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    order_q_r : out STD_LOGIC_VECTOR ( 1 downto 0 );
    req_bank_rdy_ns : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    pre_bm_end_ns : in STD_LOGIC;
    pre_passing_open_bank_ns : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    \req_bank_r_lcl_reg[0]\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_3 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg_1 : in STD_LOGIC;
    idle_r_lcl_reg_4 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg_5 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rb_hit_busy_r_reg_2 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    pre_bm_end_r_reg_2 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    \grant_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    row_hit_r : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    bm_end_r1_reg_3 : in STD_LOGIC;
    bm_end_r1_reg_4 : in STD_LOGIC;
    req_wr_r_lcl_reg_1 : in STD_LOGIC;
    req_priority_r : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    ras_timer_zero_r : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    idle_r_lcl_reg_6 : in STD_LOGIC;
    pre_bm_end_r_reg_3 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    idle_r_lcl_reg_7 : in STD_LOGIC;
    ordered_r_lcl_reg_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized2\ : entity is "mig_7series_v2_3_bank_queue";
end \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_queue__parameterized2\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \act_wait_r_lcl_i_2__0_n_0\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \auto_pre_r_lcl_i_1__1_n_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg_1\ : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^order_q_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \order_q_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \order_q_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \^pass_open_bank_r\ : STD_LOGIC;
  signal \^pre_bm_end_r\ : STD_LOGIC;
  signal \^pre_passing_open_bank_r\ : STD_LOGIC;
  signal q_entry_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \q_entry_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \q_entry_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_1\ : STD_LOGIC;
  signal \^q_has_priority_15\ : STD_LOGIC;
  signal \ras_timer_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \ras_timer_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[0]\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^req_data_buf_addr_r_reg[4]\ : STD_LOGIC;
  signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \idle_r_lcl_i_1__1\ : label is "soft_lutpair1001";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_1__0\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \ras_timer_r[1]_i_1__0\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \rb_hit_busy_r_i_1__1\ : label is "soft_lutpair1001";
begin
  E(0) <= \^e\(0);
  Q(2 downto 0) <= \^q\(2 downto 0);
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\;
  auto_pre_r_lcl_reg_1 <= \^auto_pre_r_lcl_reg_1\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  order_q_r(1 downto 0) <= \^order_q_r\(1 downto 0);
  pass_open_bank_r <= \^pass_open_bank_r\;
  pre_bm_end_r <= \^pre_bm_end_r\;
  pre_passing_open_bank_r <= \^pre_passing_open_bank_r\;
  \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\;
  \q_entry_r_reg[1]_1\ <= \^q_entry_r_reg[1]_1\;
  q_has_priority_15 <= \^q_has_priority_15\;
  \ras_timer_r_reg[0]\ <= \^ras_timer_r_reg[0]\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  \req_data_buf_addr_r_reg[4]\ <= \^req_data_buf_addr_r_reg[4]\;
  wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\;
\act_wait_r_lcl_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF444"
    )
        port map (
      I0 => \act_wait_r_lcl_i_2__0_n_0\,
      I1 => act_wait_r_lcl_reg_0,
      I2 => \^pass_open_bank_r\,
      I3 => \^bm_end_r1_reg\,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      I5 => bm_end_r1_reg_1,
      O => act_wait_ns
    );
\act_wait_r_lcl_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBABAA"
    )
        port map (
      I0 => act_wait_r_lcl_reg_1,
      I1 => \^act_wait_r_lcl_reg\,
      I2 => pre_passing_open_bank_r_reg_0,
      I3 => \^q\(0),
      I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      O => \act_wait_r_lcl_i_2__0_n_0\
    );
\auto_pre_r_lcl_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AEAAEEEE"
    )
        port map (
      I0 => \^auto_pre_r_lcl_reg_1\,
      I1 => \compute_tail.tail_r_lcl_reg_0\,
      I2 => \^auto_pre_r_lcl_reg_0\,
      I3 => \maint_controller.maint_wip_r_lcl_reg\,
      I4 => row_hit_r,
      I5 => req_wr_r_lcl_reg,
      O => \auto_pre_r_lcl_i_1__1_n_0\
    );
auto_pre_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \auto_pre_r_lcl_i_1__1_n_0\,
      Q => \^auto_pre_r_lcl_reg_1\,
      R => '0'
    );
\bm_end_r1_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEAEAEA"
    )
        port map (
      I0 => \^pre_bm_end_r\,
      I1 => \grant_r_reg[3]_0\(0),
      I2 => \^pass_open_bank_r\,
      I3 => rd_wr_r_lcl_reg_1,
      I4 => req_wr_r_lcl_reg_0,
      O => \^bm_end_r1_reg\
    );
\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => idle_r_lcl_reg_0,
      Q => tail_r_21,
      R => SR(0)
    );
\demand_priority_r_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544454445444FFFF"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_1,
      I1 => \^order_q_r\(1),
      I2 => \^order_q_r\(0),
      I3 => req_wr_r_lcl_reg_1,
      I4 => \^q_has_priority_15\,
      I5 => req_priority_r,
      O => demand_priority_r_reg
    );
\grant_r[3]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF7F"
    )
        port map (
      I0 => \^wait_for_maint_r_lcl_reg_0\,
      I1 => ras_timer_zero_r,
      I2 => act_wait_r_lcl_reg_0,
      I3 => \^req_data_buf_addr_r_reg[4]\,
      I4 => \^auto_pre_r_lcl_reg_0\,
      O => \grant_r_reg[3]\
    );
head_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => head_r_lcl_reg_1,
      Q => \^wait_for_maint_r_lcl_reg_0\,
      R => SR(0)
    );
\i___22_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55151515"
    )
        port map (
      I0 => \^pre_passing_open_bank_r\,
      I1 => \grant_r_reg[3]_0\(0),
      I2 => \^pass_open_bank_r\,
      I3 => rd_wr_r_lcl_reg_1,
      I4 => req_wr_r_lcl_reg_0,
      O => \ras_timer_r_reg[0]_0\
    );
\i___23_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => q_entry_r(0),
      I2 => q_entry_r(1),
      O => \^act_wait_r_lcl_reg\
    );
\i___24_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4F4FFF4"
    )
        port map (
      I0 => pre_passing_open_bank_r_reg_1,
      I1 => \^q\(1),
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      I3 => \^q\(0),
      I4 => pre_passing_open_bank_r_reg_0,
      I5 => \^act_wait_r_lcl_reg\,
      O => \^ras_timer_r_reg[0]\
    );
\i___39_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FD555555"
    )
        port map (
      I0 => \^req_data_buf_addr_r_reg[4]\,
      I1 => periodic_rd_ack_r_lcl_reg_1,
      I2 => use_addr,
      I3 => accept_internal_r_reg,
      I4 => \^wait_for_maint_r_lcl_reg_0\,
      I5 => req_wr_r_lcl_reg,
      O => \^rb_hit_busy_r_reg\
    );
\i___7_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404F404F4040"
    )
        port map (
      I0 => q_entry_r(1),
      I1 => q_entry_r(0),
      I2 => idle_r_lcl_reg_5,
      I3 => rb_hit_busy_r_reg_1,
      I4 => \^q_entry_r_reg[1]_0\,
      I5 => rb_hit_busy_r_reg_0,
      O => head_r_lcl_reg_0
    );
\i___7_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAFBFFFB"
    )
        port map (
      I0 => \^bm_end_r1_reg\,
      I1 => \^q_entry_r_reg[1]_0\,
      I2 => periodic_rd_ack_r_lcl_reg,
      I3 => \^req_data_buf_addr_r_reg[4]\,
      I4 => periodic_rd_ack_r_lcl_reg_0,
      O => \^q_entry_r_reg[1]_1\
    );
\i___7_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDD0DDD00000DDD"
    )
        port map (
      I0 => \^q\(1),
      I1 => pre_bm_end_r_reg_0,
      I2 => \^q\(2),
      I3 => pre_bm_end_r_reg_1,
      I4 => \^q\(0),
      I5 => pre_bm_end_r_reg_2,
      O => \^q_entry_r_reg[1]_0\
    );
\idle_r_lcl_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      O => \^e\(0)
    );
idle_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => \^req_data_buf_addr_r_reg[4]\,
      R => '0'
    );
\order_q_r[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"553100305531CC30"
    )
        port map (
      I0 => ordered_r_lcl_reg_2,
      I1 => \^order_q_r\(0),
      I2 => \^order_q_r\(1),
      I3 => req_wr_r_lcl_reg_1,
      I4 => idle_r_lcl_reg_7,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[0]_i_1__2_n_0\
    );
\order_q_r[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAC200C0AAC2F0C0"
    )
        port map (
      I0 => ordered_r_lcl_reg_1,
      I1 => \^order_q_r\(0),
      I2 => \^order_q_r\(1),
      I3 => req_wr_r_lcl_reg_1,
      I4 => idle_r_lcl_reg_7,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \order_q_r[1]_i_1__2_n_0\
    );
\order_q_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[0]_i_1__2_n_0\,
      Q => \^order_q_r\(0),
      R => '0'
    );
\order_q_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \order_q_r[1]_i_1__2_n_0\,
      Q => \^order_q_r\(1),
      R => '0'
    );
ordered_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_r_lcl_reg,
      Q => ordered_r_lcl_reg_0(0),
      R => '0'
    );
pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pass_open_bank_ns,
      Q => \^pass_open_bank_r\,
      R => '0'
    );
pre_bm_end_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_ns,
      Q => \^pre_bm_end_r\,
      R => '0'
    );
pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_passing_open_bank_ns,
      Q => \^pre_passing_open_bank_r\,
      R => '0'
    );
\q_entry_r[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B874FFFFB8740000"
    )
        port map (
      I0 => pre_bm_end_r_reg_3,
      I1 => \^bm_end_r1_reg\,
      I2 => \q_entry_r[0]_i_2_n_0\,
      I3 => periodic_rd_ack_r_lcl_reg_0,
      I4 => \^q_entry_r_reg[1]_1\,
      I5 => q_entry_r(0),
      O => \q_entry_r[0]_i_1__2_n_0\
    );
\q_entry_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"909F"
    )
        port map (
      I0 => rb_hit_busy_r_reg_0,
      I1 => \^q_entry_r_reg[1]_0\,
      I2 => periodic_rd_ack_r_lcl_reg,
      I3 => q_entry_r(0),
      O => \q_entry_r[0]_i_2_n_0\
    );
\q_entry_r[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => idle_r_lcl_reg_6,
      I1 => \^bm_end_r1_reg\,
      I2 => periodic_rd_ack_r_lcl_reg_0,
      I3 => \q_entry_r[1]_i_3_n_0\,
      I4 => \^q_entry_r_reg[1]_1\,
      I5 => q_entry_r(1),
      O => \q_entry_r[1]_i_1__2_n_0\
    );
\q_entry_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B8BB"
    )
        port map (
      I0 => idle_r_lcl_reg_4,
      I1 => \^bm_end_r1_reg\,
      I2 => \q_entry_r[1]_i_5_n_0\,
      I3 => periodic_rd_ack_r_lcl_reg,
      I4 => q_entry_r(1),
      I5 => q_entry_r(0),
      O => \q_entry_r[1]_i_3_n_0\
    );
\q_entry_r[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7EE8E881"
    )
        port map (
      I0 => \^q_entry_r_reg[1]_0\,
      I1 => rb_hit_busy_r(0),
      I2 => rb_hit_busy_r(1),
      I3 => rb_hit_busy_r(2),
      I4 => rb_hit_busy_r_reg_2,
      O => \q_entry_r[1]_i_5_n_0\
    );
\q_entry_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[0]_i_1__2_n_0\,
      Q => q_entry_r(0),
      S => SR(0)
    );
\q_entry_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \q_entry_r[1]_i_1__2_n_0\,
      Q => q_entry_r(1),
      S => SR(0)
    );
q_has_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_priority_r_reg_0,
      Q => \^q_has_priority_15\,
      R => '0'
    );
q_has_rd_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => q_has_rd_r_reg_0,
      Q => q_has_rd_14,
      R => '0'
    );
\ras_timer_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[0]_i_2_n_0\,
      I1 => \^ras_timer_r_reg[0]\,
      I2 => rd_wr_r_lcl_reg_0,
      O => D(0)
    );
\ras_timer_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBB8888888B888"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_2,
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => rd_wr_r_lcl_reg_3,
      I4 => \^q\(1),
      I5 => rd_wr_r_lcl_reg_4,
      O => \ras_timer_r[0]_i_2_n_0\
    );
\ras_timer_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ras_timer_r[1]_i_2_n_0\,
      I1 => \^ras_timer_r_reg[0]\,
      I2 => bm_end_r1_reg_0,
      O => D(1)
    );
\ras_timer_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => bm_end_r1_reg_2,
      I1 => \^q\(2),
      I2 => bm_end_r1_reg_3,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => bm_end_r1_reg_4,
      O => \ras_timer_r[1]_i_2_n_0\
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F202"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      I2 => idle_r_lcl_reg_1,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0),
      I4 => \^bm_end_r1_reg\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F202"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      I2 => idle_r_lcl_reg_2,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\(0),
      I4 => \^bm_end_r1_reg\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F202"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      I2 => idle_r_lcl_reg_3,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\(0),
      I4 => \^bm_end_r1_reg\,
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(0)
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\(0),
      Q => \^q\(0),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\(1),
      Q => \^q\(1),
      R => '0'
    );
\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\(2),
      Q => \^q\(2),
      R => '0'
    );
\rb_hit_busy_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rb_hit_busy_r_reg\,
      I1 => \req_bank_r_lcl_reg[0]\,
      O => p_28_out
    );
\req_bank_rdy_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8A8A"
    )
        port map (
      I0 => col_wait_r_reg,
      I1 => rd_wr_r_lcl_reg_1,
      I2 => \^order_q_r\(1),
      I3 => \^order_q_r\(0),
      I4 => req_wr_r_lcl_reg_1,
      O => req_bank_rdy_ns
    );
wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wait_for_maint_r_lcl_reg_1,
      Q => \^auto_pre_r_lcl_reg_0\,
      R => \maintenance_request.maint_req_r_lcl_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_state is
  port (
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    \act_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]_0\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_ns : out STD_LOGIC;
    granted_col_r_reg : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    demanded_prior_r_reg_1 : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    p_130_out : in STD_LOGIC;
    CLK : in STD_LOGIC;
    act_wait_ns : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ofs_rdy_r0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    override_demand_r_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_5 : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    tail_r : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    demanded_prior_r_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_3 : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    q_has_rd : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_state : entity is "mig_7series_v2_3_bank_state";
end mig_7series_0_mig_7series_v2_3_bank_state;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_state is
  signal \^act_this_rank_r_reg[0]_0\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal demand_priority_r_i_3_n_0 : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \grant_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[0]\ : STD_LOGIC;
  signal \^granted_col_r_reg\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal pre_wait_r_i_2_n_0 : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_0\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_1\ : STD_LOGIC;
  signal \^req_bank_rdy_r\ : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[1]_i_4__0\ : label is "soft_lutpair982";
  attribute SOFT_HLUTNM of \grant_r[3]_i_16\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \i___60_i_4\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__0\ : label is "soft_lutpair982";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair981";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair981";
begin
  \act_this_rank_r_reg[0]_0\ <= \^act_this_rank_r_reg[0]_0\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  \grant_r_reg[0]\ <= \^grant_r_reg[0]\;
  granted_col_r_reg <= \^granted_col_r_reg\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
  ras_timer_zero_r_reg_0 <= \^ras_timer_zero_r_reg_0\;
  ras_timer_zero_r_reg_1 <= \^ras_timer_zero_r_reg_1\;
  req_bank_rdy_r <= \^req_bank_rdy_r\;
  \starve_limit_cntr_r_reg[2]_0\ <= \^starve_limit_cntr_r_reg[2]_0\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_this_rank_r_reg[0]_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_this_rank_r_reg[0]_0\,
      R => '0'
    );
\auto_pre_r_lcl_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202000002000"
    )
        port map (
      I0 => tail_r,
      I1 => periodic_rd_ack_r_lcl_reg,
      I2 => rb_hit_busy_r_reg,
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      I4 => \grant_r_reg[2]_0\(0),
      I5 => \^act_this_rank_r_reg[0]_0\,
      O => auto_pre_r_lcl_reg
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_130_out,
      Q => \^ras_timer_zero_r_reg_0\,
      R => '0'
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wait_r_reg_0,
      Q => \^starve_limit_cntr_r_reg[2]_0\,
      R => '0'
    );
demand_priority_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_0,
      I1 => idle_r_lcl_reg,
      I2 => rd_wr_r_lcl_reg_4,
      I3 => demand_priority_r_i_3_n_0,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
demand_priority_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080800080"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => req_wr_r_lcl_reg,
      I4 => q_has_rd,
      I5 => req_bank_rdy_r_reg_0,
      O => demand_priority_r_i_3_n_0
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0D0D0D0D0DDD0D0"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => demanded_prior_r_reg_2,
      I3 => \grant_r_reg[2]_0\(1),
      I4 => demand_priority_r_reg_1,
      I5 => demanded_prior_r_reg_3,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000020202"
    )
        port map (
      I0 => \grant_r[1]_i_8_n_0\,
      I1 => override_demand_r_reg,
      I2 => rd_wr_r_lcl_reg_2,
      I3 => \wtr_timer.wtr_cnt_r_reg[1]\,
      I4 => rd_wr_r_lcl_reg,
      I5 => rd_wr_r_lcl_reg_3,
      O => \^grant_r_reg[0]\
    );
\grant_r[1]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_0,
      I1 => \grant_r_reg[0]_0\(0),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => \grant_r_reg[1]\
    );
\grant_r[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAFFFE"
    )
        port map (
      I0 => \^starve_limit_cntr_r_reg[2]_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      I4 => idle_r_lcl_reg_0,
      I5 => \^ras_timer_zero_r_reg_1\,
      O => \grant_r[1]_i_8_n_0\
    );
\grant_r[3]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \grant_r_reg[2]_0\(0),
      I1 => \^demand_priority_r_reg_0\,
      I2 => \^demanded_prior_r_reg_0\,
      O => \grant_r_reg[2]\
    );
\grant_r[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^grant_r_reg[0]\,
      I1 => rd_wr_r_lcl_reg_1,
      O => \^granted_col_r_reg\
    );
granted_col_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^granted_col_r_reg\,
      I1 => rd_wr_r_lcl_reg_0,
      O => granted_col_ns
    );
\i___60_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBBBABB"
    )
        port map (
      I0 => demand_priority_r_reg_1,
      I1 => demanded_prior_r_reg_2,
      I2 => \grant_r_reg[2]_0\(0),
      I3 => \^demand_priority_r_reg_0\,
      I4 => \^demanded_prior_r_reg_0\,
      O => \rnk_config_strobe_r_reg[0]\
    );
\i___82_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFBFBFB00FBFB"
    )
        port map (
      I0 => \^demanded_prior_r_reg_0\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => \grant_r_reg[2]_0\(0),
      I3 => demanded_prior_r_reg_3,
      I4 => demand_priority_r_reg_1,
      I5 => \grant_r_reg[2]_0\(1),
      O => demanded_prior_r_reg_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => SR(0)
    );
\pre_bm_end_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[0]_0\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \grant_r_reg[2]_0\(0),
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => pre_wait_r_i_2_n_0,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
pre_wait_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[0]_0\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => pre_wait_r_i_2_n_0
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004444FFF4"
    )
        port map (
      I0 => rd_wr_r_lcl_reg,
      I1 => \grant_r_reg[2]_0\(0),
      I2 => \^ras_timer_zero_r_reg_1\,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => bm_end_r1_reg_0,
      O => \ras_timer_r_reg[0]_0\
    );
\ras_timer_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000111110001000"
    )
        port map (
      I0 => \^ras_timer_zero_r_reg_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => ras_timer_r(0),
      I3 => ras_timer_r(1),
      I4 => rd_wr_r_lcl_reg,
      I5 => \grant_r_reg[2]_0\(0),
      O => \ras_timer_r_reg[1]_0\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
ras_timer_zero_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0C04"
    )
        port map (
      I0 => \^ras_timer_zero_r_reg_1\,
      I1 => rd_wr_r_lcl_reg_5,
      I2 => ras_timer_r(1),
      I3 => ras_timer_r(0),
      I4 => \rstdiv0_sync_r1_reg_rep__20\,
      I5 => \^ras_timer_zero_r_reg_0\,
      O => ras_timer_zero_ns
    );
\ras_timer_zero_r_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^act_this_rank_r_reg[0]_0\,
      I1 => \grant_r_reg[0]_1\(0),
      O => \^ras_timer_zero_r_reg_1\
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_r_lcl_reg,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => \^req_bank_rdy_r\,
      R => '0'
    );
\rtp_timer_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => pass_open_bank_r_lcl_reg,
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      O => \rtp_timer_r[0]_i_1_n_0\
    );
\rtp_timer_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => \grant_r_reg[2]_0\(0),
      I1 => rtp_timer_r(1),
      I2 => rtp_timer_r(0),
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \rtp_timer_r[1]_i_1_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[1]_i_1_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[0]_i_1_n_0\
    );
\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[1]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[2]_i_1_n_0\
    );
\starve_limit_cntr_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F0000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => granted_col_r_reg_0,
      I4 => \grant_r_reg[2]_0\(0),
      I5 => \^req_bank_rdy_r\,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_state__parameterized0\ is
  port (
    bm_end_r1_0 : out STD_LOGIC;
    \act_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]_0\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[1]\ : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    ras_timer_zero_r_reg_2 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    p_91_out : in STD_LOGIC;
    CLK : in STD_LOGIC;
    act_wait_ns : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ofs_rdy_r0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    \grant_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pass_open_bank_r_lcl_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    \order_q_r_reg[0]\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    tail_r_19 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    \last_master_r_reg[0]\ : in STD_LOGIC;
    \grant_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_0\ : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    q_has_rd_4 : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_state__parameterized0\ : entity is "mig_7series_v2_3_bank_state";
end \mig_7series_0_mig_7series_v2_3_bank_state__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_state__parameterized0\ is
  signal \^act_this_rank_r_reg[0]_0\ : STD_LOGIC;
  signal \^bm_end_r1_0\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal \demand_priority_r_i_3__0_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \grant_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__0_n_0\ : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_0\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_1\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_2\ : STD_LOGIC;
  signal \^req_bank_rdy_r\ : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[1]_i_5__1\ : label is "soft_lutpair988";
  attribute SOFT_HLUTNM of pre_bm_end_r_i_1 : label is "soft_lutpair988";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1__0\ : label is "soft_lutpair989";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1__0\ : label is "soft_lutpair989";
begin
  \act_this_rank_r_reg[0]_0\ <= \^act_this_rank_r_reg[0]_0\;
  bm_end_r1_0 <= \^bm_end_r1_0\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
  ras_timer_zero_r_reg_0 <= \^ras_timer_zero_r_reg_0\;
  ras_timer_zero_r_reg_1 <= \^ras_timer_zero_r_reg_1\;
  ras_timer_zero_r_reg_2 <= \^ras_timer_zero_r_reg_2\;
  req_bank_rdy_r <= \^req_bank_rdy_r\;
  \starve_limit_cntr_r_reg[2]_0\ <= \^starve_limit_cntr_r_reg[2]_0\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_this_rank_r_reg[0]_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_this_rank_r_reg[0]_0\,
      R => '0'
    );
auto_pre_r_lcl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202000002000"
    )
        port map (
      I0 => tail_r_19,
      I1 => periodic_rd_ack_r_lcl_reg,
      I2 => rb_hit_busy_r_reg,
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      I4 => \grant_r_reg[3]\(0),
      I5 => \^act_this_rank_r_reg[0]_0\,
      O => auto_pre_r_lcl_reg
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_91_out,
      Q => \^bm_end_r1_0\,
      R => '0'
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wait_r_reg_0,
      Q => \^starve_limit_cntr_r_reg[2]_0\,
      R => '0'
    );
\demand_priority_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_0,
      I1 => idle_r_lcl_reg,
      I2 => rd_wr_r_lcl_reg_1,
      I3 => \demand_priority_r_i_3__0_n_0\,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080800080"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => req_wr_r_lcl_reg,
      I4 => q_has_rd_4,
      I5 => req_bank_rdy_r_reg_0,
      O => \demand_priority_r_i_3__0_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
demanded_prior_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000D00DDDDDDDD"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => \grant_r_reg[3]\(1),
      I3 => demand_priority_r_reg_1,
      I4 => demanded_prior_r_reg_2,
      I5 => demanded_prior_r_reg_1,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFEFEFE"
    )
        port map (
      I0 => col_wait_r_reg_1,
      I1 => \order_q_r_reg[0]\,
      I2 => \grant_r[1]_i_7_n_0\,
      I3 => \wtr_timer.wtr_cnt_r_reg[1]\,
      I4 => rd_wr_r_lcl_reg,
      I5 => rd_wr_r_lcl_reg_0,
      O => \grant_r_reg[1]\
    );
\grant_r[1]_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_0,
      I1 => \grant_r_reg[1]_1\(0),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => \grant_r_reg[1]_0\
    );
\grant_r[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0045"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \grant_r_reg[3]_0\,
      I2 => demanded_prior_r_reg_1,
      I3 => override_demand_r,
      I4 => rnk_config_valid_r_lcl_reg,
      O => \grant_r[1]_i_7_n_0\
    );
\grant_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \last_master_r_reg[0]\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[1]_1\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => \grant_r_reg[2]\
    );
\grant_r[2]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FFF7"
    )
        port map (
      I0 => \^ras_timer_zero_r\,
      I1 => \^pre_wait_r\,
      I2 => \grant_r_reg[1]_1\(0),
      I3 => auto_pre_r_lcl_reg_0,
      I4 => auto_pre_r_lcl_reg_1,
      O => \pre_4_1_1T_arb.granted_pre_r_reg\
    );
\i___42_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^act_this_rank_r_reg[0]_0\,
      I1 => \grant_r_reg[1]_2\(0),
      O => \^ras_timer_zero_r_reg_2\
    );
\i___60_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => demand_priority_r_reg_1,
      I1 => \grant_r_reg[3]\(0),
      I2 => \^demand_priority_r_reg_0\,
      I3 => \^demanded_prior_r_reg_0\,
      I4 => demanded_prior_r_reg_1,
      O => \rnk_config_strobe_r_reg[0]\
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => SR(0)
    );
pre_bm_end_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[1]_1\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => pre_bm_end_ns
    );
pre_passing_open_bank_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \grant_r_reg[3]\(0),
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
pre_wait_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \pre_wait_r_i_2__0_n_0\,
      I2 => pass_open_bank_r_lcl_reg,
      I3 => \rstdiv0_sync_r1_reg_rep__21\,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
\pre_wait_r_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[1]_1\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => \pre_wait_r_i_2__0_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004444FFF4"
    )
        port map (
      I0 => rd_wr_r_lcl_reg,
      I1 => \grant_r_reg[3]\(0),
      I2 => \^ras_timer_zero_r_reg_2\,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => bm_end_r1_reg_0,
      O => \^ras_timer_zero_r_reg_0\
    );
\ras_timer_r[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000111110001000"
    )
        port map (
      I0 => \^bm_end_r1_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => ras_timer_r(0),
      I3 => ras_timer_r(1),
      I4 => rd_wr_r_lcl_reg,
      I5 => \grant_r_reg[3]\(0),
      O => \^ras_timer_zero_r_reg_1\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
\ras_timer_zero_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ras_timer_zero_r_reg_0\,
      I1 => \^ras_timer_zero_r_reg_1\,
      O => ras_timer_zero_ns
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_r_lcl_reg,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => \^req_bank_rdy_r\,
      R => '0'
    );
\rtp_timer_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => pass_open_bank_r_lcl_reg,
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      O => \rtp_timer_r[0]_i_1__0_n_0\
    );
\rtp_timer_r[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => \grant_r_reg[3]\(0),
      I1 => rtp_timer_r(1),
      I2 => rtp_timer_r(0),
      I3 => pass_open_bank_r_lcl_reg,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \rtp_timer_r[1]_i_1__0_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__0_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[1]_i_1__0_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[0]_i_1__0_n_0\
    );
\starve_limit_cntr_r[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[1]_i_1__0_n_0\
    );
\starve_limit_cntr_r[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[2]_i_1__0_n_0\
    );
\starve_limit_cntr_r[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F0000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => granted_col_r_reg,
      I4 => \grant_r_reg[3]\(0),
      I5 => \^req_bank_rdy_r\,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1__0_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1__0_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1__0_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_state__parameterized1\ is
  port (
    bm_end_r1_1 : out STD_LOGIC;
    \act_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]_0\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[2]\ : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    ras_timer_zero_r_reg_2 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    ofs_rdy_r0 : out STD_LOGIC;
    ofs_rdy_r0_0 : out STD_LOGIC;
    ofs_rdy_r0_1 : out STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    CLK : in STD_LOGIC;
    act_wait_ns : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    start_wtp_timer0 : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_mc_ctl_full : in STD_LOGIC;
    \grant_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pass_open_bank_r : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    \order_q_r_reg[0]\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    tail_r_20 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_3 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    \grant_r_reg[0]_0\ : in STD_LOGIC;
    \grant_r_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r_lcl_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd_9 : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_state__parameterized1\ : entity is "mig_7series_v2_3_bank_state";
end \mig_7series_0_mig_7series_v2_3_bank_state__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_state__parameterized1\ is
  signal \^act_this_rank_r_reg[0]_0\ : STD_LOGIC;
  signal \^bm_end_r1_1\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal \demand_priority_r_i_3__1_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \grant_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_9_n_0\ : STD_LOGIC;
  signal ofs_rdy_r0_2 : STD_LOGIC;
  signal \^override_demand_r\ : STD_LOGIC;
  signal phy_mc_cmd_full_r : STD_LOGIC;
  signal phy_mc_ctl_full_r : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__1_n_0\ : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_0\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_1\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_2\ : STD_LOGIC;
  signal \^req_bank_rdy_r\ : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[3]_i_2__1\ : label is "soft_lutpair995";
  attribute SOFT_HLUTNM of ofs_rdy_r_i_1 : label is "soft_lutpair997";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__0\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__1\ : label is "soft_lutpair997";
  attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__2\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \pre_wait_r_i_2__1\ : label is "soft_lutpair995";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1__1\ : label is "soft_lutpair996";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1__1\ : label is "soft_lutpair996";
begin
  \act_this_rank_r_reg[0]_0\ <= \^act_this_rank_r_reg[0]_0\;
  bm_end_r1_1 <= \^bm_end_r1_1\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  override_demand_r <= \^override_demand_r\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
  ras_timer_zero_r_reg_0 <= \^ras_timer_zero_r_reg_0\;
  ras_timer_zero_r_reg_1 <= \^ras_timer_zero_r_reg_1\;
  ras_timer_zero_r_reg_2 <= \^ras_timer_zero_r_reg_2\;
  req_bank_rdy_r <= \^req_bank_rdy_r\;
  \starve_limit_cntr_r_reg[2]_0\ <= \^starve_limit_cntr_r_reg[2]_0\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_this_rank_r_reg[0]_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
\act_wait_r_lcl_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^act_this_rank_r_reg[0]_0\,
      I1 => \grant_r_reg[2]_2\(0),
      O => \^ras_timer_zero_r_reg_0\
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_this_rank_r_reg[0]_0\,
      R => '0'
    );
\auto_pre_r_lcl_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202000002000"
    )
        port map (
      I0 => tail_r_20,
      I1 => periodic_rd_ack_r_lcl_reg,
      I2 => rb_hit_busy_r_reg,
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      I4 => \grant_r_reg[2]_0\(1),
      I5 => \^act_this_rank_r_reg[0]_0\,
      O => auto_pre_r_lcl_reg
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_r_reg,
      Q => \^bm_end_r1_1\,
      R => '0'
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wait_r_reg_0,
      Q => \^starve_limit_cntr_r_reg[2]_0\,
      R => '0'
    );
\demand_priority_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_0,
      I1 => idle_r_lcl_reg,
      I2 => rd_wr_r_lcl_reg_1,
      I3 => \demand_priority_r_i_3__1_n_0\,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080800080"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => req_wr_r(0),
      I4 => q_has_rd_9,
      I5 => req_bank_rdy_r_reg_0,
      O => \demand_priority_r_i_3__1_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0D0D0D0D0DDD0D0"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => demanded_prior_r_reg_1,
      I3 => \grant_r_reg[2]_0\(0),
      I4 => demand_priority_r,
      I5 => demanded_prior_r,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[3]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAABABB"
    )
        port map (
      I0 => rnk_config_valid_r_lcl_reg,
      I1 => \^demand_priority_r_reg_0\,
      I2 => demanded_prior_r_reg_1,
      I3 => \grant_r_reg[0]_0\,
      I4 => \^override_demand_r\,
      O => \grant_r[3]_i_11_n_0\
    );
\grant_r[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_0,
      I1 => \grant_r_reg[2]_1\(0),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => \grant_r_reg[0]\
    );
\grant_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000020202"
    )
        port map (
      I0 => \grant_r[3]_i_9_n_0\,
      I1 => \order_q_r_reg[0]\,
      I2 => \grant_r[3]_i_11_n_0\,
      I3 => \wtr_timer.wtr_cnt_r_reg[1]\,
      I4 => rd_wr_r_lcl_reg,
      I5 => rd_wr_r_lcl_reg_0,
      O => \grant_r_reg[2]\
    );
\grant_r[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAFFFE"
    )
        port map (
      I0 => \^starve_limit_cntr_r_reg[2]_0\,
      I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      I4 => idle_r_lcl_reg_0,
      I5 => \^ras_timer_zero_r_reg_0\,
      O => \grant_r[3]_i_9_n_0\
    );
ofs_rdy_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => phy_mc_ctl_full_r,
      I1 => phy_mc_cmd_full_r,
      I2 => rd_wr_r_lcl_reg_2,
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0
    );
\ofs_rdy_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => phy_mc_ctl_full_r,
      I1 => phy_mc_cmd_full_r,
      I2 => rd_wr_r_lcl_reg_3(0),
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0_0
    );
\ofs_rdy_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => phy_mc_ctl_full_r,
      I1 => phy_mc_cmd_full_r,
      I2 => rd_wr_r_lcl_reg,
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0_2
    );
\ofs_rdy_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1011"
    )
        port map (
      I0 => phy_mc_ctl_full_r,
      I1 => phy_mc_cmd_full_r,
      I2 => rd_wr_r_lcl_reg_4(0),
      I3 => phy_mc_data_full,
      O => ofs_rdy_r0_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0_2,
      Q => ofs_rdy_r,
      R => SR(0)
    );
override_demand_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => override_demand_ns,
      Q => \^override_demand_r\,
      R => '0'
    );
phy_mc_cmd_full_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => of_ctl_full_v(0),
      Q => phy_mc_cmd_full_r,
      R => SR(0)
    );
phy_mc_ctl_full_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => phy_mc_ctl_full,
      Q => phy_mc_ctl_full_r,
      R => SR(0)
    );
\pre_4_1_1T_arb.granted_pre_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDFDDDDDDDDDDDD"
    )
        port map (
      I0 => ras_timer_zero_r_reg_3,
      I1 => auto_pre_r_lcl_reg_1,
      I2 => auto_pre_r_lcl_reg_0,
      I3 => \grant_r_reg[2]_1\(0),
      I4 => \^pre_wait_r\,
      I5 => \^ras_timer_zero_r\,
      O => \pre_4_1_1T_arb.granted_pre_ns\
    );
\pre_bm_end_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[2]_1\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \grant_r_reg[2]_0\(1),
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \pre_wait_r_i_2__1_n_0\,
      I2 => pass_open_bank_r,
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
\pre_wait_r_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[2]_1\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => \pre_wait_r_i_2__1_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004444FFF4"
    )
        port map (
      I0 => rd_wr_r_lcl_reg,
      I1 => \grant_r_reg[2]_0\(1),
      I2 => \^ras_timer_zero_r_reg_0\,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => bm_end_r1_reg_0,
      O => \^ras_timer_zero_r_reg_1\
    );
\ras_timer_r[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000111110001000"
    )
        port map (
      I0 => \^bm_end_r1_1\,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => ras_timer_r(0),
      I3 => ras_timer_r(1),
      I4 => rd_wr_r_lcl_reg,
      I5 => \grant_r_reg[2]_0\(1),
      O => \^ras_timer_zero_r_reg_2\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
\ras_timer_zero_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ras_timer_zero_r_reg_1\,
      I1 => \^ras_timer_zero_r_reg_2\,
      O => ras_timer_zero_ns
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_r_lcl_reg,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => \^req_bank_rdy_r\,
      R => '0'
    );
\rnk_config_strobe_r[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBBBABB"
    )
        port map (
      I0 => demand_priority_r,
      I1 => demanded_prior_r_reg_1,
      I2 => \grant_r_reg[2]_0\(1),
      I3 => \^demand_priority_r_reg_0\,
      I4 => \^demanded_prior_r_reg_0\,
      O => \rnk_config_strobe_r_reg[0]\
    );
\rtp_timer_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => pass_open_bank_r,
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      O => \rtp_timer_r[0]_i_1__1_n_0\
    );
\rtp_timer_r[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => \grant_r_reg[2]_0\(1),
      I1 => rtp_timer_r(1),
      I2 => rtp_timer_r(0),
      I3 => pass_open_bank_r,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \rtp_timer_r[1]_i_1__1_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__1_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[1]_i_1__1_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[0]_i_1__1_n_0\
    );
\starve_limit_cntr_r[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[1]_i_1__1_n_0\
    );
\starve_limit_cntr_r[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[2]_i_1__1_n_0\
    );
\starve_limit_cntr_r[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F0000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => granted_col_r_reg,
      I4 => \grant_r_reg[2]_0\(1),
      I5 => \^req_bank_rdy_r\,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1__1_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1__1_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1__1_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_state__parameterized2\ is
  port (
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    \act_this_rank_r_reg[0]_0\ : out STD_LOGIC;
    ras_timer_zero_r : out STD_LOGIC;
    pre_wait_r : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]_0\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_ns : out STD_LOGIC;
    pre_passing_open_bank_ns : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \ras_timer_r_reg[1]_0\ : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[10]\ : out STD_LOGIC;
    demanded_prior_r_reg_1 : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : out STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    CLK : in STD_LOGIC;
    act_wait_ns : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ofs_rdy_r0 : in STD_LOGIC;
    start_wtp_timer0 : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pass_open_bank_r : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    pass_open_bank_ns : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    tail_r_21 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    \grant_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[10]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_1\ : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demand_priority_r_reg_1 : in STD_LOGIC;
    demanded_prior_r_reg_2 : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    q_has_rd_14 : in STD_LOGIC;
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    cs_en2 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_state__parameterized2\ : entity is "mig_7series_v2_3_bank_state";
end \mig_7series_0_mig_7series_v2_3_bank_state__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_state__parameterized2\ is
  signal \^act_this_rank_r_reg[0]_0\ : STD_LOGIC;
  signal demand_priority_ns : STD_LOGIC;
  signal \demand_priority_r_i_3__2_n_0\ : STD_LOGIC;
  signal \^demand_priority_r_reg_0\ : STD_LOGIC;
  signal demanded_prior_ns : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal \^pre_passing_open_bank_ns\ : STD_LOGIC;
  signal pre_wait_ns : STD_LOGIC;
  signal \^pre_wait_r\ : STD_LOGIC;
  signal \pre_wait_r_i_2__2_n_0\ : STD_LOGIC;
  signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_ns : STD_LOGIC;
  signal \^ras_timer_zero_r\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_0\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_1\ : STD_LOGIC;
  signal \^req_bank_rdy_r\ : STD_LOGIC;
  signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rtp_timer_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rtp_timer_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal starve_limit_cntr_r0 : STD_LOGIC;
  signal \starve_limit_cntr_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \starve_limit_cntr_r[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[38]_i_3\ : label is "soft_lutpair1004";
  attribute SOFT_HLUTNM of \grant_r[3]_i_4__1\ : label is "soft_lutpair1002";
  attribute SOFT_HLUTNM of \i___23_i_5\ : label is "soft_lutpair1004";
  attribute SOFT_HLUTNM of \pre_wait_r_i_2__2\ : label is "soft_lutpair1002";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1__2\ : label is "soft_lutpair1003";
  attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1__2\ : label is "soft_lutpair1003";
begin
  \act_this_rank_r_reg[0]_0\ <= \^act_this_rank_r_reg[0]_0\;
  demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\;
  pre_wait_r <= \^pre_wait_r\;
  ras_timer_zero_r <= \^ras_timer_zero_r\;
  ras_timer_zero_r_reg_0 <= \^ras_timer_zero_r_reg_0\;
  ras_timer_zero_r_reg_1 <= \^ras_timer_zero_r_reg_1\;
  req_bank_rdy_r <= \^req_bank_rdy_r\;
  \starve_limit_cntr_r_reg[2]_0\ <= \^starve_limit_cntr_r_reg[2]_0\;
\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^act_this_rank_r_reg[0]_0\,
      Q => act_this_rank_r(0),
      R => '0'
    );
act_wait_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => act_wait_ns,
      Q => \^act_this_rank_r_reg[0]_0\,
      R => '0'
    );
\auto_pre_r_lcl_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202000002000"
    )
        port map (
      I0 => tail_r_21,
      I1 => periodic_rd_ack_r_lcl_reg,
      I2 => rb_hit_busy_r_reg,
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      I4 => Q(1),
      I5 => \^act_this_rank_r_reg[0]_0\,
      O => auto_pre_r_lcl_reg
    );
bm_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_bm_end_r_reg,
      Q => \^ras_timer_zero_r_reg_0\,
      R => '0'
    );
\cmd_pipe_plus.mc_address[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F7F7F7F007F7F7F"
    )
        port map (
      I0 => \^act_this_rank_r_reg[0]_0\,
      I1 => \grant_r_reg[3]_0\(0),
      I2 => \req_row_r_lcl_reg[10]\(0),
      I3 => \req_row_r_lcl_reg[10]_0\(0),
      I4 => row_cmd_wr(0),
      I5 => \grant_r_reg[3]_1\,
      O => \cmd_pipe_plus.mc_address_reg[10]\
    );
\cmd_pipe_plus.mc_address[38]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80FF"
    )
        port map (
      I0 => \^act_this_rank_r_reg[0]_0\,
      I1 => \grant_r_reg[3]\(0),
      I2 => \req_row_r_lcl_reg[10]\(0),
      I3 => cs_en2,
      O => \cmd_pipe_plus.mc_address_reg[38]\
    );
col_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_wait_r_reg_0,
      Q => \^starve_limit_cntr_r_reg[2]_0\,
      R => '0'
    );
\demand_priority_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => col_wait_r_reg_0,
      I1 => idle_r_lcl_reg,
      I2 => rd_wr_r_lcl_reg_0,
      I3 => \demand_priority_r_i_3__2_n_0\,
      I4 => \^demand_priority_r_reg_0\,
      O => demand_priority_ns
    );
\demand_priority_r_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080800080"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => req_wr_r_lcl_reg,
      I4 => q_has_rd_14,
      I5 => req_bank_rdy_r_reg_0,
      O => \demand_priority_r_i_3__2_n_0\
    );
demand_priority_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demand_priority_ns,
      Q => \^demand_priority_r_reg_0\,
      R => '0'
    );
\demanded_prior_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000D00DDDDDDDD"
    )
        port map (
      I0 => \^demand_priority_r_reg_0\,
      I1 => \^demanded_prior_r_reg_0\,
      I2 => Q(0),
      I3 => demand_priority_r_reg_1,
      I4 => demanded_prior_r,
      I5 => demanded_prior_r_reg_2,
      O => demanded_prior_ns
    );
demanded_prior_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => demanded_prior_ns,
      Q => \^demanded_prior_r_reg_0\,
      R => '0'
    );
\grant_r[3]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_0,
      I1 => \grant_r_reg[3]\(0),
      I2 => \^pre_wait_r\,
      I3 => \^ras_timer_zero_r\,
      O => \pre_4_1_1T_arb.granted_pre_r_reg\
    );
\i___23_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^act_this_rank_r_reg[0]_0\,
      I1 => \grant_r_reg[3]_0\(0),
      O => \^ras_timer_zero_r_reg_1\
    );
\i___81_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040404FF0404"
    )
        port map (
      I0 => \^demanded_prior_r_reg_0\,
      I1 => \^demand_priority_r_reg_0\,
      I2 => Q(1),
      I3 => demanded_prior_r,
      I4 => demand_priority_r_reg_1,
      I5 => Q(0),
      O => demanded_prior_r_reg_1
    );
ofs_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofs_rdy_r0,
      Q => ofs_rdy_r,
      R => SR(0)
    );
\pre_bm_end_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAAA"
    )
        port map (
      I0 => \^pre_passing_open_bank_ns\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[3]\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => pre_bm_end_ns
    );
\pre_passing_open_bank_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAA8AAA8"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => Q(1),
      I2 => rtp_timer_r(1),
      I3 => rtp_timer_r(0),
      I4 => \^ras_timer_zero_r\,
      I5 => \^pre_wait_r\,
      O => \^pre_passing_open_bank_ns\
    );
\pre_wait_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444454444"
    )
        port map (
      I0 => pass_open_bank_ns,
      I1 => \pre_wait_r_i_2__2_n_0\,
      I2 => pass_open_bank_r,
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      I4 => rtp_timer_r(0),
      I5 => rtp_timer_r(1),
      O => pre_wait_ns
    );
\pre_wait_r_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101050"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^ras_timer_zero_r\,
      I2 => \^pre_wait_r\,
      I3 => \grant_r_reg[3]\(0),
      I4 => auto_pre_r_lcl_reg_0,
      O => \pre_wait_r_i_2__2_n_0\
    );
pre_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pre_wait_ns,
      Q => \^pre_wait_r\,
      R => '0'
    );
\ras_timer_r[0]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004444FFF4"
    )
        port map (
      I0 => rd_wr_r_lcl_reg,
      I1 => Q(1),
      I2 => \^ras_timer_zero_r_reg_1\,
      I3 => ras_timer_r(1),
      I4 => ras_timer_r(0),
      I5 => bm_end_r1_reg_0,
      O => \ras_timer_r_reg[0]_0\
    );
\ras_timer_r[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000111110001000"
    )
        port map (
      I0 => \^ras_timer_zero_r_reg_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => ras_timer_r(0),
      I3 => ras_timer_r(1),
      I4 => rd_wr_r_lcl_reg,
      I5 => Q(1),
      O => \ras_timer_r_reg[1]_0\
    );
\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => ras_timer_r(0),
      R => '0'
    );
\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => ras_timer_r(1),
      R => '0'
    );
\ras_timer_zero_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0C04"
    )
        port map (
      I0 => \^ras_timer_zero_r_reg_1\,
      I1 => rd_wr_r_lcl_reg_1,
      I2 => ras_timer_r(1),
      I3 => ras_timer_r(0),
      I4 => \rstdiv0_sync_r1_reg_rep__20\,
      I5 => \^ras_timer_zero_r_reg_0\,
      O => ras_timer_zero_ns
    );
ras_timer_zero_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ras_timer_zero_ns,
      Q => \^ras_timer_zero_r\,
      R => '0'
    );
\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_wr_r_lcl_reg,
      Q => rd_this_rank_r(0),
      R => '0'
    );
req_bank_rdy_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => req_bank_rdy_ns,
      Q => \^req_bank_rdy_r\,
      R => '0'
    );
\rnk_config_strobe_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFAAAA"
    )
        port map (
      I0 => demand_priority_r_reg_1,
      I1 => Q(1),
      I2 => \^demand_priority_r_reg_0\,
      I3 => \^demanded_prior_r_reg_0\,
      I4 => demanded_prior_r_reg_2,
      O => \rnk_config_strobe_r_reg[0]\
    );
\rtp_timer_r[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => pass_open_bank_r,
      I2 => rtp_timer_r(0),
      I3 => rtp_timer_r(1),
      O => \rtp_timer_r[0]_i_1__2_n_0\
    );
\rtp_timer_r[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000C2"
    )
        port map (
      I0 => Q(1),
      I1 => rtp_timer_r(1),
      I2 => rtp_timer_r(0),
      I3 => pass_open_bank_r,
      I4 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \rtp_timer_r[1]_i_1__2_n_0\
    );
\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[0]_i_1__2_n_0\,
      Q => rtp_timer_r(0),
      R => '0'
    );
\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rtp_timer_r[1]_i_1__2_n_0\,
      Q => rtp_timer_r(1),
      R => '0'
    );
\starve_limit_cntr_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r0,
      I2 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[0]_i_1__2_n_0\
    );
\starve_limit_cntr_r[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => starve_limit_cntr_r(1),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[1]_i_1__2_n_0\
    );
\starve_limit_cntr_r[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => starve_limit_cntr_r(2),
      I1 => starve_limit_cntr_r0,
      I2 => starve_limit_cntr_r(0),
      I3 => starve_limit_cntr_r(1),
      I4 => \^starve_limit_cntr_r_reg[2]_0\,
      O => \starve_limit_cntr_r[2]_i_1__2_n_0\
    );
\starve_limit_cntr_r[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F0000000000"
    )
        port map (
      I0 => starve_limit_cntr_r(0),
      I1 => starve_limit_cntr_r(1),
      I2 => starve_limit_cntr_r(2),
      I3 => granted_col_r_reg,
      I4 => Q(1),
      I5 => \^req_bank_rdy_r\,
      O => starve_limit_cntr_r0
    );
\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[0]_i_1__2_n_0\,
      Q => starve_limit_cntr_r(0),
      R => '0'
    );
\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[1]_i_1__2_n_0\,
      Q => starve_limit_cntr_r(1),
      R => '0'
    );
\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \starve_limit_cntr_r[2]_i_1__2_n_0\,
      Q => starve_limit_cntr_r(2),
      R => '0'
    );
\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_wtp_timer0,
      Q => wr_this_rank_r(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_clk_ibuf is
  port (
    mmcm_clk : out STD_LOGIC;
    sys_clk_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_clk_ibuf : entity is "mig_7series_v2_3_clk_ibuf";
end mig_7series_0_mig_7series_v2_3_clk_ibuf;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_clk_ibuf is
  signal sys_clk_ibufg : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of sys_clk_ibufg : signal is "true";
  attribute syn_keep : string;
  attribute syn_keep of sys_clk_ibufg : signal is "true";
begin
  mmcm_clk <= sys_clk_ibufg;
  sys_clk_ibufg <= sys_clk_i;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_col_mach is
  port (
    col_rd_wr_r1 : out STD_LOGIC;
    col_rd_wr_r2 : out STD_LOGIC;
    sent_col_r2 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \not_strict_mode.bypass__0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    mc_read_idle_r_reg : out STD_LOGIC;
    \read_fifo.tail_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_ref_zq_wip_ns : out STD_LOGIC;
    \read_fifo.tail_r_reg[1]_0\ : out STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[7]_0\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_end_ns\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    col_data_buf_addr : in STD_LOGIC_VECTOR ( 4 downto 0 );
    ADDRA : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DIC : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    ram_init_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    maint_ref_zq_wip : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_buf_indx.rd_buf_indx_r_reg[4]\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.tail_r_reg[0]_0\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_col_mach : entity is "mig_7series_v2_3_col_mach";
end mig_7series_0_mig_7series_v2_3_col_mach;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_col_mach is
  signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^col_rd_wr_r1\ : STD_LOGIC;
  signal mc_ref_zq_wip_r_i_2_n_0 : STD_LOGIC;
  signal \not_strict_mode.app_rd_data[511]_i_3_n_0\ : STD_LOGIC;
  signal \not_strict_mode.app_rd_data[511]_i_4_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.bypass__0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_fifo.fifo_out_data_ns\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \read_fifo.head_r\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_fifo.tail_ns\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 4 downto 3 );
  signal \read_fifo.tail_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \read_fifo.tail_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \read_fifo.tail_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \read_fifo.tail_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \^read_fifo.tail_r_reg[1]_0\ : STD_LOGIC;
  signal \^read_fifo.tail_r_reg[2]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \read_fifo.fifo_ram[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \read_fifo.fifo_ram[1].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \read_fifo.head_r[1]_i_1\ : label is "soft_lutpair1011";
  attribute SOFT_HLUTNM of \read_fifo.head_r[2]_i_1\ : label is "soft_lutpair1011";
  attribute SOFT_HLUTNM of \read_fifo.head_r[3]_i_1\ : label is "soft_lutpair1009";
  attribute SOFT_HLUTNM of \read_fifo.head_r[4]_i_1\ : label is "soft_lutpair1009";
  attribute SOFT_HLUTNM of \read_fifo.tail_r[2]_i_1\ : label is "soft_lutpair1010";
  attribute SOFT_HLUTNM of \read_fifo.tail_r[3]_i_1\ : label is "soft_lutpair1010";
begin
  Q(7 downto 0) <= \^q\(7 downto 0);
  col_rd_wr_r1 <= \^col_rd_wr_r1\;
  \not_strict_mode.bypass__0\ <= \^not_strict_mode.bypass__0\;
  \read_fifo.tail_r_reg[1]_0\ <= \^read_fifo.tail_r_reg[1]_0\;
  \read_fifo.tail_r_reg[2]_0\(1 downto 0) <= \^read_fifo.tail_r_reg[2]_0\(1 downto 0);
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_data_buf_addr(0),
      Q => D(0),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_data_buf_addr(1),
      Q => D(1),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_data_buf_addr(2),
      Q => D(2),
      R => '0'
    );
\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_data_buf_addr(3),
      Q => D(3),
      R => '0'
    );
\i___85_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \read_fifo.tail_r\(4),
      I1 => \^read_fifo.tail_r_reg[2]_0\(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => \^read_fifo.tail_r_reg[1]_0\,
      I4 => \^read_fifo.tail_r_reg[2]_0\(1),
      I5 => \read_fifo.tail_r\(3),
      O => \read_fifo.fifo_out_data_r_reg[7]_0\
    );
mc_read_idle_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"09000009"
    )
        port map (
      I0 => \read_fifo.tail_r\(4),
      I1 => \read_fifo.head_r\(4),
      I2 => mc_ref_zq_wip_r_i_2_n_0,
      I3 => \read_fifo.head_r\(3),
      I4 => \read_fifo.tail_r\(3),
      O => mc_read_idle_r_reg
    );
mc_ref_zq_wip_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0082000000000082"
    )
        port map (
      I0 => maint_ref_zq_wip,
      I1 => \read_fifo.tail_r\(4),
      I2 => \read_fifo.head_r\(4),
      I3 => mc_ref_zq_wip_r_i_2_n_0,
      I4 => \read_fifo.head_r\(3),
      I5 => \read_fifo.tail_r\(3),
      O => mc_ref_zq_wip_ns
    );
mc_ref_zq_wip_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \read_fifo.head_r\(2),
      I1 => \^read_fifo.tail_r_reg[2]_0\(1),
      I2 => \read_fifo.head_r\(1),
      I3 => \^read_fifo.tail_r_reg[2]_0\(0),
      I4 => \^read_fifo.tail_r_reg[1]_0\,
      I5 => \read_fifo.head_r\(0),
      O => mc_ref_zq_wip_r_i_2_n_0
    );
\not_strict_mode.app_rd_data[511]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000002000"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \^q\(6),
      I2 => \not_strict_mode.app_rd_data[511]_i_3_n_0\,
      I3 => \not_strict_mode.app_rd_data[511]_i_4_n_0\,
      I4 => ram_init_addr(1),
      I5 => \^q\(2),
      O => \not_strict_mode.app_rd_data_reg[40]\
    );
\not_strict_mode.app_rd_data[511]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(5),
      I1 => \rd_buf_indx.rd_buf_indx_r_reg[4]\,
      I2 => \^q\(1),
      I3 => ram_init_addr(0),
      O => \not_strict_mode.app_rd_data[511]_i_3_n_0\
    );
\not_strict_mode.app_rd_data[511]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(3),
      I1 => ram_init_addr(2),
      I2 => \^q\(4),
      I3 => ram_init_addr(3),
      O => \not_strict_mode.app_rd_data[511]_i_4_n_0\
    );
\not_strict_mode.app_rd_data_end_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^not_strict_mode.bypass__0\,
      I2 => \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0),
      O => \not_strict_mode.app_rd_data_end_ns\
    );
\not_strict_mode.app_rd_data_end_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000002000"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \^q\(6),
      I2 => \not_strict_mode.app_rd_data[511]_i_3_n_0\,
      I3 => \not_strict_mode.app_rd_data[511]_i_4_n_0\,
      I4 => ram_init_addr(1),
      I5 => \^q\(2),
      O => \^not_strict_mode.bypass__0\
    );
\offset_pipe_0.col_rd_wr_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_rd_wr,
      Q => \^col_rd_wr_r1\,
      R => '0'
    );
\offset_pipe_1.col_rd_wr_r2_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^col_rd_wr_r1\,
      Q => col_rd_wr_r2,
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(0),
      Q => \^q\(0),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(1),
      Q => \^q\(1),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(2),
      Q => \^q\(2),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(3),
      Q => \^q\(3),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(4),
      Q => \^q\(4),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(5),
      Q => \^q\(5),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(6),
      Q => \^q\(6),
      R => '0'
    );
\read_fifo.fifo_out_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.fifo_out_data_ns\(7),
      Q => \^q\(7),
      R => '0'
    );
\read_fifo.fifo_ram[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => ADDRA(2),
      ADDRA(3) => \read_fifo.tail_ns\(3),
      ADDRA(2 downto 1) => ADDRA(1 downto 0),
      ADDRA(0) => \read_fifo.tail_ns\(0),
      ADDRB(4) => ADDRA(2),
      ADDRB(3) => \read_fifo.tail_ns\(3),
      ADDRB(2 downto 1) => ADDRA(1 downto 0),
      ADDRB(0) => \read_fifo.tail_ns\(0),
      ADDRC(4) => ADDRA(2),
      ADDRC(3) => \read_fifo.tail_ns\(3),
      ADDRC(2 downto 1) => ADDRA(1 downto 0),
      ADDRC(0) => \read_fifo.tail_ns\(0),
      ADDRD(4 downto 0) => \read_fifo.head_r\(4 downto 0),
      DIA(1 downto 0) => col_data_buf_addr(4 downto 3),
      DIB(1 downto 0) => col_data_buf_addr(2 downto 1),
      DIC(1) => col_data_buf_addr(0),
      DIC(0) => '0',
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \read_fifo.fifo_out_data_ns\(5 downto 4),
      DOB(1 downto 0) => \read_fifo.fifo_out_data_ns\(3 downto 2),
      DOC(1 downto 0) => \read_fifo.fifo_out_data_ns\(1 downto 0),
      DOD(1 downto 0) => \NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => '1'
    );
\read_fifo.fifo_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \^read_fifo.tail_r_reg[2]_0\(0),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => \^read_fifo.tail_r_reg[1]_0\,
      I3 => \^read_fifo.tail_r_reg[2]_0\(1),
      I4 => \read_fifo.tail_r\(3),
      I5 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \read_fifo.tail_ns\(3)
    );
\read_fifo.fifo_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \^read_fifo.tail_r_reg[1]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \read_fifo.tail_ns\(0)
    );
\read_fifo.fifo_ram[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => ADDRA(2),
      ADDRA(3) => \read_fifo.tail_ns\(3),
      ADDRA(2 downto 1) => ADDRA(1 downto 0),
      ADDRA(0) => \read_fifo.tail_ns\(0),
      ADDRB(4) => ADDRA(2),
      ADDRB(3) => \read_fifo.tail_ns\(3),
      ADDRB(2 downto 1) => ADDRA(1 downto 0),
      ADDRB(0) => \read_fifo.tail_ns\(0),
      ADDRC(4) => ADDRA(2),
      ADDRC(3) => \read_fifo.tail_ns\(3),
      ADDRC(2 downto 1) => ADDRA(1 downto 0),
      ADDRC(0) => \read_fifo.tail_ns\(0),
      ADDRD(4 downto 0) => \read_fifo.head_r\(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => '1',
      DIC(0) => DIC(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \read_fifo.fifo_out_data_ns\(7 downto 6),
      DOD(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => '1'
    );
\read_fifo.head_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \read_fifo.head_r\(0),
      O => p_0_in(0)
    );
\read_fifo.head_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \read_fifo.head_r\(0),
      I1 => \read_fifo.head_r\(1),
      O => p_0_in(1)
    );
\read_fifo.head_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \read_fifo.head_r\(2),
      I1 => \read_fifo.head_r\(1),
      I2 => \read_fifo.head_r\(0),
      O => p_0_in(2)
    );
\read_fifo.head_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \read_fifo.head_r\(3),
      I1 => \read_fifo.head_r\(0),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.head_r\(2),
      O => p_0_in(3)
    );
\read_fifo.head_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \read_fifo.head_r\(4),
      I1 => \read_fifo.head_r\(2),
      I2 => \read_fifo.head_r\(1),
      I3 => \read_fifo.head_r\(0),
      I4 => \read_fifo.head_r\(3),
      O => p_0_in(4)
    );
\read_fifo.head_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(0),
      Q => \read_fifo.head_r\(0),
      R => SR(0)
    );
\read_fifo.head_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(1),
      Q => \read_fifo.head_r\(1),
      R => SR(0)
    );
\read_fifo.head_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(2),
      Q => \read_fifo.head_r\(2),
      R => SR(0)
    );
\read_fifo.head_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(3),
      Q => \read_fifo.head_r\(3),
      R => SR(0)
    );
\read_fifo.head_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => p_0_in(4),
      Q => \read_fifo.head_r\(4),
      R => SR(0)
    );
\read_fifo.tail_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \^read_fifo.tail_r_reg[1]_0\,
      I2 => \^read_fifo.tail_r_reg[2]_0\(0),
      O => \read_fifo.tail_r[1]_i_1_n_0\
    );
\read_fifo.tail_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^read_fifo.tail_r_reg[1]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => \^read_fifo.tail_r_reg[2]_0\(0),
      I3 => \^read_fifo.tail_r_reg[2]_0\(1),
      O => \read_fifo.tail_r[2]_i_1_n_0\
    );
\read_fifo.tail_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \read_fifo.tail_r\(3),
      I1 => \^read_fifo.tail_r_reg[2]_0\(1),
      I2 => \^read_fifo.tail_r_reg[1]_0\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \^read_fifo.tail_r_reg[2]_0\(0),
      O => \read_fifo.tail_r[3]_i_1_n_0\
    );
\read_fifo.tail_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \read_fifo.tail_r\(3),
      I1 => \^read_fifo.tail_r_reg[2]_0\(1),
      I2 => \^read_fifo.tail_r_reg[1]_0\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \^read_fifo.tail_r_reg[2]_0\(0),
      I5 => \read_fifo.tail_r\(4),
      O => \read_fifo.tail_r[4]_i_1_n_0\
    );
\read_fifo.tail_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_r_reg[0]_0\,
      Q => \^read_fifo.tail_r_reg[1]_0\,
      R => SR(0)
    );
\read_fifo.tail_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_r[1]_i_1_n_0\,
      Q => \^read_fifo.tail_r_reg[2]_0\(0),
      R => SR(0)
    );
\read_fifo.tail_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_r[2]_i_1_n_0\,
      Q => \^read_fifo.tail_r_reg[2]_0\(1),
      R => SR(0)
    );
\read_fifo.tail_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_r[3]_i_1_n_0\,
      Q => \read_fifo.tail_r\(3),
      R => SR(0)
    );
\read_fifo.tail_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \read_fifo.tail_r[4]_i_1_n_0\,
      Q => \read_fifo.tail_r\(4),
      R => SR(0)
    );
sent_col_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cmd(0),
      Q => sent_col_r2,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_byte_group_io is
  port (
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_5 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    A_rst_primitives_reg_0 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_byte_group_io : entity is "mig_7series_v2_3_ddr_byte_group_io";
end mig_7series_0_mig_7series_v2_3_ddr_byte_group_io;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_byte_group_io is
  signal data_in_dly_0 : STD_LOGIC;
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal \^idelay_ld_rst_5\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__0_n_0\ : STD_LOGIC;
  signal rst_r3_reg_srl3_n_0 : STD_LOGIC;
  signal rst_r4 : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[0].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[0].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of rst_r3_reg_srl3 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 ";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_5 <= \^idelay_ld_rst_5\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_7,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_7,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => rst_r4,
      I1 => \^idelay_ld_rst_5\,
      I2 => A_rst_primitives_reg,
      O => \idelay_ld_rst_i_1__0_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \idelay_ld_rst_i_1__0_n_0\,
      Q => \^idelay_ld_rst_5\,
      R => '0'
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_0,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[0].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_0,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D0(3),
      Q2 => D0(2),
      Q3 => D0(1),
      Q4 => D0(0),
      Q5 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_10,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_11,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[0].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
rst_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => A_rst_primitives_reg,
      Q => rst_r3_reg_srl3_n_0
    );
rst_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_r3_reg_srl3_n_0,
      Q => rst_r4,
      R => '0'
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_13 is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    A_rst_primitives_reg_0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_13 : entity is "mig_7series_v2_3_ddr_byte_group_io";
end mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_13;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_13 is
  signal data_in_dly_0 : STD_LOGIC;
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal \^idelay_ld_rst\ : STD_LOGIC;
  signal idelay_ld_rst_i_1_n_0 : STD_LOGIC;
  signal rst_r3_reg_srl3_n_0 : STD_LOGIC;
  signal rst_r4 : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[0].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[0].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of rst_r3_reg_srl3 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 ";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst <= \^idelay_ld_rst\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_4,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_4,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
idelay_ld_rst_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => rst_r4,
      I1 => \^idelay_ld_rst\,
      I2 => A_rst_primitives_reg,
      O => idelay_ld_rst_i_1_n_0
    );
idelay_ld_rst_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ld_rst_i_1_n_0,
      Q => \^idelay_ld_rst\,
      R => '0'
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_0,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[0].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_0,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D0(3),
      Q2 => D0(2),
      Q3 => D0(1),
      Q4 => D0(0),
      Q5 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[0].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
rst_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => A_rst_primitives_reg,
      Q => rst_r3_reg_srl3_n_0
    );
rst_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_r3_reg_srl3_n_0,
      Q => rst_r4,
      R => '0'
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_28 is
  port (
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_0 : out STD_LOGIC;
    rst_r4 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_6 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_28 : entity is "mig_7series_v2_3_ddr_byte_group_io";
end mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_28;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_28 is
  signal data_in_dly_0 : STD_LOGIC;
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal \^idelay_ld_rst_0\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__1_n_0\ : STD_LOGIC;
  signal rst_r3_reg_srl3_n_0 : STD_LOGIC;
  signal \^rst_r4\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[0].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[0].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of rst_r3_reg_srl3 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 ";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_0 <= \^idelay_ld_rst_0\;
  rst_r4 <= \^rst_r4\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_3,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_3,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_0\,
      I1 => \^rst_r4\,
      O => \idelay_ld_rst_i_1__1_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \idelay_ld_rst_i_1__1_n_0\,
      Q => \^idelay_ld_rst_0\,
      S => A_rst_primitives
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_0,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[0].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_0,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D0(3),
      Q2 => D0(2),
      Q3 => D0(1),
      Q4 => D0(0),
      Q5 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_6,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_7,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[0].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
rst_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => A_rst_primitives,
      Q => rst_r3_reg_srl3_n_0
    );
rst_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_r3_reg_srl3_n_0,
      Q => \^rst_r4\,
      R => '0'
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0\ is
  port (
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    idelay_ce_r2_reg : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    A_rst_primitives_reg_0 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0\ is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_6,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_6,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_12,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_12,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0_25\ is
  port (
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_1 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0_25\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0_25\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0_25\ is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal data_in_dly_9 : STD_LOGIC;
  signal \^idelay_ld_rst_1\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__2_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_1 <= \^idelay_ld_rst_1\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_2,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_2,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_1\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__2_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \idelay_ld_rst_i_1__2_n_0\,
      Q => \^idelay_ld_rst_1\,
      S => A_rst_primitives
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_9,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_7,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_8,
      CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_9,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D9(3),
      Q2 => D9(2),
      Q3 => D9(1),
      Q4 => D9(0),
      Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1\ is
  port (
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_14 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    A_rst_primitives_reg_0 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1\ is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_5,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_5,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_14,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives_reg
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg_0,
      CLKB => CLKB0_13,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_19\ is
  port (
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_3 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    idelay_ce_r2_reg : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_19\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_19\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_19\ is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal \^idelay_ld_rst_3\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__4_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_3 <= \^idelay_ld_rst_3\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_0,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_0,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_3\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__4_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \idelay_ld_rst_i_1__4_n_0\,
      Q => \^idelay_ld_rst_3\,
      S => A_rst_primitives
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => idelay_ce_r2_reg,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_9,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_10,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_22\ is
  port (
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_2 : out STD_LOGIC;
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    po_oserdes_rst : in STD_LOGIC;
    DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oserdes_clk_delayed : in STD_LOGIC;
    DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    iserdes_clkdiv : in STD_LOGIC;
    of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 );
    rst_r4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_22\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_22\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_22\ is
  signal data_in_dly_1 : STD_LOGIC;
  signal data_in_dly_2 : STD_LOGIC;
  signal data_in_dly_3 : STD_LOGIC;
  signal data_in_dly_4 : STD_LOGIC;
  signal data_in_dly_5 : STD_LOGIC;
  signal data_in_dly_6 : STD_LOGIC;
  signal data_in_dly_7 : STD_LOGIC;
  signal data_in_dly_8 : STD_LOGIC;
  signal \^idelay_ld_rst_2\ : STD_LOGIC;
  signal \idelay_ld_rst_i_1__3_n_0\ : STD_LOGIC;
  signal tbyte_out : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE";
  attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE";
  attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE";
  attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D : integer;
  attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE";
  attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "MIG_7SERIES_0_IODELAY_MIG0";
  attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0;
  attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE";
begin
  idelay_ld_rst_2 <= \^idelay_ld_rst_2\;
\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => DQSBUS(0),
      D2 => DQSBUS(1),
      Q => out_dqs_1,
      R => '0',
      S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\
    );
\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk_delayed,
      CE => '1',
      D1 => CTSBUS(0),
      D2 => CTSBUS(0),
      Q => ts_dqs_1,
      R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\,
      S => '0'
    );
\idelay_ld_rst_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ld_rst_2\,
      I1 => rst_r4,
      O => \idelay_ld_rst_i_1__3_n_0\
    );
idelay_ld_rst_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \idelay_ld_rst_i_1__3_n_0\,
      Q => \^idelay_ld_rst_2\,
      S => A_rst_primitives
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_1,
      IDATAIN => mem_dq_in(0),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(0),
      DDLY => data_in_dly_1,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D1(3),
      Q2 => D1(2),
      Q3 => D1(1),
      Q4 => D1(0),
      Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_2,
      IDATAIN => mem_dq_in(1),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(1),
      DDLY => data_in_dly_2,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D2(3),
      Q2 => D2(2),
      Q3 => D2(1),
      Q4 => D2(0),
      Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_3,
      IDATAIN => mem_dq_in(2),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(2),
      DDLY => data_in_dly_3,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D3(3),
      Q2 => D3(2),
      Q3 => D3(1),
      Q4 => D3(0),
      Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_4,
      IDATAIN => mem_dq_in(3),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(3),
      DDLY => data_in_dly_4,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D4(3),
      Q2 => D4(2),
      Q3 => D4(1),
      Q4 => D4(0),
      Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_5,
      IDATAIN => mem_dq_in(4),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(4),
      DDLY => data_in_dly_5,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D5(3),
      Q2 => D5(2),
      Q3 => D5(1),
      Q4 => D5(0),
      Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_6,
      IDATAIN => mem_dq_in(5),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(5),
      DDLY => data_in_dly_6,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D6(3),
      Q2 => D6(2),
      Q3 => D6(1),
      Q4 => D6(0),
      Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_7,
      IDATAIN => mem_dq_in(6),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(6),
      DDLY => data_in_dly_7,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D7(3),
      Q2 => D7(2),
      Q3 => D7(1),
      Q4 => D7(0),
      Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2
    generic map(
      CINVCTRL_SEL => "FALSE",
      DELAY_SRC => "IDATAIN",
      HIGH_PERFORMANCE_MODE => "TRUE",
      IDELAY_TYPE => "VARIABLE",
      IDELAY_VALUE => 0,
      IS_C_INVERTED => '0',
      IS_DATAIN_INVERTED => '0',
      IS_IDATAIN_INVERTED => '0',
      PIPE_SEL => "FALSE",
      REFCLK_FREQUENCY => 200.000000,
      SIGNAL_PATTERN => "DATA"
    )
        port map (
      C => CLK,
      CE => \calib_sel_reg[1]\,
      CINVCTRL => '0',
      CNTVALUEIN(4 downto 0) => B"00000",
      CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0),
      DATAIN => '0',
      DATAOUT => data_in_dly_8,
      IDATAIN => mem_dq_in(7),
      INC => idelay_inc,
      LD => LD0_8,
      LDPIPEEN => '0',
      REGRST => A_rst_primitives
    );
\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2
    generic map(
      DATA_RATE => "DDR",
      DATA_WIDTH => 4,
      DYN_CLKDIV_INV_EN => "FALSE",
      DYN_CLK_INV_EN => "FALSE",
      INIT_Q1 => '0',
      INIT_Q2 => '0',
      INIT_Q3 => '0',
      INIT_Q4 => '0',
      INTERFACE_TYPE => "MEMORY_DDR3",
      IOBDELAY => "IFD",
      IS_CLKB_INVERTED => '1',
      IS_CLKDIVP_INVERTED => '0',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_OCLKB_INVERTED => '0',
      IS_OCLK_INVERTED => '0',
      NUM_CE => 2,
      OFB_USED => "FALSE",
      SERDES_MODE => "MASTER",
      SRVAL_Q1 => '0',
      SRVAL_Q2 => '0',
      SRVAL_Q3 => '0',
      SRVAL_Q4 => '0'
    )
        port map (
      BITSLIP => '0',
      CE1 => '1',
      CE2 => '1',
      CLK => A_rst_primitives_reg,
      CLKB => CLKB0_9,
      CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\,
      CLKDIVP => iserdes_clkdiv,
      D => mem_dq_in(7),
      DDLY => data_in_dly_8,
      DYNCLKDIVSEL => '0',
      DYNCLKSEL => '0',
      O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\,
      OCLK => oserdes_clk,
      OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\,
      OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\,
      Q1 => D8(3),
      Q2 => D8(2),
      Q3 => D8(1),
      Q4 => D8(0),
      Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\,
      Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\,
      Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\,
      Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\,
      RST => '0',
      SHIFTIN1 => '0',
      SHIFTIN2 => '0',
      SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\
    );
\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(0),
      D2 => of_dqbus(1),
      D3 => of_dqbus(2),
      D4 => of_dqbus(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(0)
    );
\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(4),
      D2 => of_dqbus(5),
      D3 => of_dqbus(6),
      D4 => of_dqbus(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(1)
    );
\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(8),
      D2 => of_dqbus(9),
      D3 => of_dqbus(10),
      D4 => of_dqbus(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(2)
    );
\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(12),
      D2 => of_dqbus(13),
      D3 => of_dqbus(14),
      D4 => of_dqbus(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(3)
    );
\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(16),
      D2 => of_dqbus(17),
      D3 => of_dqbus(18),
      D4 => of_dqbus(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(4)
    );
\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(20),
      D2 => of_dqbus(21),
      D3 => of_dqbus(22),
      D4 => of_dqbus(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(5)
    );
\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(24),
      D2 => of_dqbus(25),
      D3 => of_dqbus(26),
      D4 => of_dqbus(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(6)
    );
\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(28),
      D2 => of_dqbus(29),
      D3 => of_dqbus(30),
      D4 => of_dqbus(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(7)
    );
\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => of_dqbus(32),
      D2 => of_dqbus(33),
      D3 => of_dqbus(34),
      D4 => of_dqbus(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => tbyte_out,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => mem_dq_ts(8)
    );
\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 4,
      INIT_OQ => '1',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '1',
      SRVAL_TQ => '1',
      TBYTE_CTL => "TRUE",
      TBYTE_SRC => "TRUE",
      TRISTATE_WIDTH => 4
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => '0',
      D2 => '0',
      D3 => '0',
      D4 => '0',
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\,
      OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\,
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\,
      T1 => DTSBUS(0),
      T2 => DTSBUS(0),
      T3 => DTSBUS(1),
      T4 => DTSBUS(1),
      TBYTEIN => tbyte_out,
      TBYTEOUT => tbyte_out,
      TCE => '1',
      TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\,
      TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized2\ is
  port (
    mem_dq_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 19 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized2\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized2\ is
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[1].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized3\ is
  port (
    mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 47 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized3\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized3\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized3\ is
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[0].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[6].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[7].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[8].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[9].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[0].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(40),
      D2 => oserdes_dq(41),
      D3 => oserdes_dq(42),
      D4 => oserdes_dq(43),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(10),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(44),
      D2 => oserdes_dq(45),
      D3 => oserdes_dq(46),
      D4 => oserdes_dq(47),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(11),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[1].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(20),
      D2 => oserdes_dq(21),
      D3 => oserdes_dq(22),
      D4 => oserdes_dq(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[6].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(24),
      D2 => oserdes_dq(25),
      D3 => oserdes_dq(26),
      D4 => oserdes_dq(27),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(6),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[7].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(28),
      D2 => oserdes_dq(29),
      D3 => oserdes_dq(30),
      D4 => oserdes_dq(31),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(7),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[8].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(32),
      D2 => oserdes_dq(33),
      D3 => oserdes_dq(34),
      D4 => oserdes_dq(35),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(8),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[9].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(36),
      D2 => oserdes_dq(37),
      D3 => oserdes_dq(38),
      D4 => oserdes_dq(39),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(9),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized4\ is
  port (
    mem_dq_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
    oserdes_clk : in STD_LOGIC;
    oserdes_clkdiv : in STD_LOGIC;
    oserdes_dq : in STD_LOGIC_VECTOR ( 23 downto 0 );
    po_oserdes_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized4\ : entity is "mig_7series_v2_3_ddr_byte_group_io";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized4\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized4\ is
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[1].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE";
begin
\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(20),
      D2 => oserdes_dq(21),
      D3 => oserdes_dq(22),
      D4 => oserdes_dq(23),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(5),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[1].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(0),
      D2 => oserdes_dq(1),
      D3 => oserdes_dq(2),
      D4 => oserdes_dq(3),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(0),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(4),
      D2 => oserdes_dq(5),
      D3 => oserdes_dq(6),
      D4 => oserdes_dq(7),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(1),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(8),
      D2 => oserdes_dq(9),
      D3 => oserdes_dq(10),
      D4 => oserdes_dq(11),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(2),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(12),
      D2 => oserdes_dq(13),
      D3 => oserdes_dq(14),
      D4 => oserdes_dq(15),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(3),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2
    generic map(
      DATA_RATE_OQ => "SDR",
      DATA_RATE_TQ => "SDR",
      DATA_WIDTH => 4,
      INIT_OQ => '0',
      INIT_TQ => '1',
      IS_CLKDIV_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      IS_D3_INVERTED => '0',
      IS_D4_INVERTED => '0',
      IS_D5_INVERTED => '0',
      IS_D6_INVERTED => '0',
      IS_D7_INVERTED => '0',
      IS_D8_INVERTED => '0',
      IS_T1_INVERTED => '0',
      IS_T2_INVERTED => '0',
      IS_T3_INVERTED => '0',
      IS_T4_INVERTED => '0',
      SERDES_MODE => "MASTER",
      SRVAL_OQ => '0',
      SRVAL_TQ => '1',
      TBYTE_CTL => "FALSE",
      TBYTE_SRC => "FALSE",
      TRISTATE_WIDTH => 1
    )
        port map (
      CLK => oserdes_clk,
      CLKDIV => oserdes_clkdiv,
      D1 => oserdes_dq(16),
      D2 => oserdes_dq(17),
      D3 => oserdes_dq(18),
      D4 => oserdes_dq(19),
      D5 => '0',
      D6 => '0',
      D7 => '0',
      D8 => '0',
      OCE => '1',
      OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\,
      OQ => mem_dq_out(4),
      RST => po_oserdes_rst,
      SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\,
      SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\,
      SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\,
      SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\,
      T1 => '0',
      T2 => '0',
      T3 => '0',
      T4 => '0',
      TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\,
      TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\,
      TCE => '1',
      TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\,
      TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo is
  port (
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[42]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[44]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[46]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[104]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[106]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[108]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[110]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[168]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[170]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[172]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[174]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[232]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[234]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[236]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[238]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[296]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[298]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[300]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[302]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[360]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[362]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[364]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[366]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[424]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[426]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[428]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[430]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[488]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[490]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[492]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[494]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    if_empty_or_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    byte_rd_en_v_2 : out STD_LOGIC;
    C_byte_rd_en : out STD_LOGIC;
    if_empty_r_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \my_empty_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_0\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_1\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_2\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_3\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_4\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_5\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_6\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_7\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_8\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_9\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_10\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_11\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_12\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_13\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_14\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_15\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_16\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_17\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_18\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_19\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_20\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_21\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_22\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_23\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_24\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_25\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_26\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_27\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_28\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_29\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_30\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_31\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_32\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_33\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_34\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_35\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_36\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_37\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_38\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_39\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_40\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_41\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_42\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_43\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_44\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_45\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_46\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_47\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_48\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_49\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_50\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_51\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_52\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_53\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_54\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_55\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_56\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_57\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_58\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_59\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_60\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_61\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_62\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_63\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 65 downto 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo is
  signal \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 71 downto 8 );
  signal mem_reg_0_3_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_1 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \my_empty[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[104]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[105]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[106]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[107]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[108]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[109]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[110]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[111]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[168]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[169]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[170]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[171]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[172]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[173]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[174]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[175]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[232]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[233]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[234]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[235]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[236]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[237]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[238]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[239]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[296]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[297]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[298]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[299]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[300]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[301]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[302]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[303]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[360]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[361]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[362]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[363]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[364]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[365]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[366]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[367]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[40]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[41]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[424]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[425]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[426]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[427]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[428]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[429]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[42]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[430]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[431]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[43]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[44]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[45]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[46]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[47]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[488]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[489]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[490]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[491]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[492]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[493]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[494]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[495]\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__3_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__8_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_2__2_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__14_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__14_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_2__4_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[0]_i_1__4\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \my_empty[2]_i_1__4\ : label is "soft_lutpair938";
  attribute SOFT_HLUTNM of \my_empty[3]_i_1__4\ : label is "soft_lutpair938";
  attribute SOFT_HLUTNM of \my_empty[4]_i_1__4\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \my_empty[4]_i_2__4\ : label is "soft_lutpair905";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[0]_i_2__6\ : label is "soft_lutpair902";
  attribute SOFT_HLUTNM of \my_full[1]_i_3__0\ : label is "soft_lutpair903";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[104]_i_1\ : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[105]_i_1\ : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[106]_i_1\ : label is "soft_lutpair910";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[107]_i_1\ : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[108]_i_1\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[109]_i_1\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[110]_i_1\ : label is "soft_lutpair911";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[111]_i_1\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[168]_i_1\ : label is "soft_lutpair914";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[169]_i_1\ : label is "soft_lutpair914";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[170]_i_1\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[171]_i_1\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[172]_i_1\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[173]_i_1\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[174]_i_1\ : label is "soft_lutpair917";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[175]_i_1\ : label is "soft_lutpair917";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[232]_i_1\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[233]_i_1\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[234]_i_1\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[235]_i_1\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[236]_i_1\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[237]_i_1\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[238]_i_1\ : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[239]_i_1\ : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[296]_i_1\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[297]_i_1\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[298]_i_1\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[299]_i_1\ : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[300]_i_1\ : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[301]_i_1\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[302]_i_1\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[303]_i_1\ : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[360]_i_1\ : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[361]_i_1\ : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[362]_i_1\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[363]_i_1\ : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[364]_i_1\ : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[365]_i_1\ : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[366]_i_1\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[367]_i_1\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[40]_i_1\ : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[41]_i_1\ : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[424]_i_1\ : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[425]_i_1\ : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[426]_i_1\ : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[427]_i_1\ : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[428]_i_1\ : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[429]_i_1\ : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[42]_i_1\ : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[430]_i_1\ : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[431]_i_1\ : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[43]_i_1\ : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[44]_i_1\ : label is "soft_lutpair910";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[45]_i_1\ : label is "soft_lutpair911";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[46]_i_1\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[47]_i_1\ : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[488]_i_1\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[489]_i_1\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[490]_i_1\ : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[491]_i_1\ : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[492]_i_1\ : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[493]_i_1\ : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[494]_i_1\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[495]_i_1\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__2\ : label is "soft_lutpair905";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2__2\ : label is "soft_lutpair902";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_3__1\ : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_5\ : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_2__4\ : label is "soft_lutpair903";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \not_strict_mode.app_rd_data_reg[104]\ <= \^not_strict_mode.app_rd_data_reg[104]\;
  \not_strict_mode.app_rd_data_reg[105]\ <= \^not_strict_mode.app_rd_data_reg[105]\;
  \not_strict_mode.app_rd_data_reg[106]\ <= \^not_strict_mode.app_rd_data_reg[106]\;
  \not_strict_mode.app_rd_data_reg[107]\ <= \^not_strict_mode.app_rd_data_reg[107]\;
  \not_strict_mode.app_rd_data_reg[108]\ <= \^not_strict_mode.app_rd_data_reg[108]\;
  \not_strict_mode.app_rd_data_reg[109]\ <= \^not_strict_mode.app_rd_data_reg[109]\;
  \not_strict_mode.app_rd_data_reg[110]\ <= \^not_strict_mode.app_rd_data_reg[110]\;
  \not_strict_mode.app_rd_data_reg[111]\ <= \^not_strict_mode.app_rd_data_reg[111]\;
  \not_strict_mode.app_rd_data_reg[168]\ <= \^not_strict_mode.app_rd_data_reg[168]\;
  \not_strict_mode.app_rd_data_reg[169]\ <= \^not_strict_mode.app_rd_data_reg[169]\;
  \not_strict_mode.app_rd_data_reg[170]\ <= \^not_strict_mode.app_rd_data_reg[170]\;
  \not_strict_mode.app_rd_data_reg[171]\ <= \^not_strict_mode.app_rd_data_reg[171]\;
  \not_strict_mode.app_rd_data_reg[172]\ <= \^not_strict_mode.app_rd_data_reg[172]\;
  \not_strict_mode.app_rd_data_reg[173]\ <= \^not_strict_mode.app_rd_data_reg[173]\;
  \not_strict_mode.app_rd_data_reg[174]\ <= \^not_strict_mode.app_rd_data_reg[174]\;
  \not_strict_mode.app_rd_data_reg[175]\ <= \^not_strict_mode.app_rd_data_reg[175]\;
  \not_strict_mode.app_rd_data_reg[232]\ <= \^not_strict_mode.app_rd_data_reg[232]\;
  \not_strict_mode.app_rd_data_reg[233]\ <= \^not_strict_mode.app_rd_data_reg[233]\;
  \not_strict_mode.app_rd_data_reg[234]\ <= \^not_strict_mode.app_rd_data_reg[234]\;
  \not_strict_mode.app_rd_data_reg[235]\ <= \^not_strict_mode.app_rd_data_reg[235]\;
  \not_strict_mode.app_rd_data_reg[236]\ <= \^not_strict_mode.app_rd_data_reg[236]\;
  \not_strict_mode.app_rd_data_reg[237]\ <= \^not_strict_mode.app_rd_data_reg[237]\;
  \not_strict_mode.app_rd_data_reg[238]\ <= \^not_strict_mode.app_rd_data_reg[238]\;
  \not_strict_mode.app_rd_data_reg[239]\ <= \^not_strict_mode.app_rd_data_reg[239]\;
  \not_strict_mode.app_rd_data_reg[296]\ <= \^not_strict_mode.app_rd_data_reg[296]\;
  \not_strict_mode.app_rd_data_reg[297]\ <= \^not_strict_mode.app_rd_data_reg[297]\;
  \not_strict_mode.app_rd_data_reg[298]\ <= \^not_strict_mode.app_rd_data_reg[298]\;
  \not_strict_mode.app_rd_data_reg[299]\ <= \^not_strict_mode.app_rd_data_reg[299]\;
  \not_strict_mode.app_rd_data_reg[300]\ <= \^not_strict_mode.app_rd_data_reg[300]\;
  \not_strict_mode.app_rd_data_reg[301]\ <= \^not_strict_mode.app_rd_data_reg[301]\;
  \not_strict_mode.app_rd_data_reg[302]\ <= \^not_strict_mode.app_rd_data_reg[302]\;
  \not_strict_mode.app_rd_data_reg[303]\ <= \^not_strict_mode.app_rd_data_reg[303]\;
  \not_strict_mode.app_rd_data_reg[360]\ <= \^not_strict_mode.app_rd_data_reg[360]\;
  \not_strict_mode.app_rd_data_reg[361]\ <= \^not_strict_mode.app_rd_data_reg[361]\;
  \not_strict_mode.app_rd_data_reg[362]\ <= \^not_strict_mode.app_rd_data_reg[362]\;
  \not_strict_mode.app_rd_data_reg[363]\ <= \^not_strict_mode.app_rd_data_reg[363]\;
  \not_strict_mode.app_rd_data_reg[364]\ <= \^not_strict_mode.app_rd_data_reg[364]\;
  \not_strict_mode.app_rd_data_reg[365]\ <= \^not_strict_mode.app_rd_data_reg[365]\;
  \not_strict_mode.app_rd_data_reg[366]\ <= \^not_strict_mode.app_rd_data_reg[366]\;
  \not_strict_mode.app_rd_data_reg[367]\ <= \^not_strict_mode.app_rd_data_reg[367]\;
  \not_strict_mode.app_rd_data_reg[40]\ <= \^not_strict_mode.app_rd_data_reg[40]\;
  \not_strict_mode.app_rd_data_reg[41]\ <= \^not_strict_mode.app_rd_data_reg[41]\;
  \not_strict_mode.app_rd_data_reg[424]\ <= \^not_strict_mode.app_rd_data_reg[424]\;
  \not_strict_mode.app_rd_data_reg[425]\ <= \^not_strict_mode.app_rd_data_reg[425]\;
  \not_strict_mode.app_rd_data_reg[426]\ <= \^not_strict_mode.app_rd_data_reg[426]\;
  \not_strict_mode.app_rd_data_reg[427]\ <= \^not_strict_mode.app_rd_data_reg[427]\;
  \not_strict_mode.app_rd_data_reg[428]\ <= \^not_strict_mode.app_rd_data_reg[428]\;
  \not_strict_mode.app_rd_data_reg[429]\ <= \^not_strict_mode.app_rd_data_reg[429]\;
  \not_strict_mode.app_rd_data_reg[42]\ <= \^not_strict_mode.app_rd_data_reg[42]\;
  \not_strict_mode.app_rd_data_reg[430]\ <= \^not_strict_mode.app_rd_data_reg[430]\;
  \not_strict_mode.app_rd_data_reg[431]\ <= \^not_strict_mode.app_rd_data_reg[431]\;
  \not_strict_mode.app_rd_data_reg[43]\ <= \^not_strict_mode.app_rd_data_reg[43]\;
  \not_strict_mode.app_rd_data_reg[44]\ <= \^not_strict_mode.app_rd_data_reg[44]\;
  \not_strict_mode.app_rd_data_reg[45]\ <= \^not_strict_mode.app_rd_data_reg[45]\;
  \not_strict_mode.app_rd_data_reg[46]\ <= \^not_strict_mode.app_rd_data_reg[46]\;
  \not_strict_mode.app_rd_data_reg[47]\ <= \^not_strict_mode.app_rd_data_reg[47]\;
  \not_strict_mode.app_rd_data_reg[488]\ <= \^not_strict_mode.app_rd_data_reg[488]\;
  \not_strict_mode.app_rd_data_reg[489]\ <= \^not_strict_mode.app_rd_data_reg[489]\;
  \not_strict_mode.app_rd_data_reg[490]\ <= \^not_strict_mode.app_rd_data_reg[490]\;
  \not_strict_mode.app_rd_data_reg[491]\ <= \^not_strict_mode.app_rd_data_reg[491]\;
  \not_strict_mode.app_rd_data_reg[492]\ <= \^not_strict_mode.app_rd_data_reg[492]\;
  \not_strict_mode.app_rd_data_reg[493]\ <= \^not_strict_mode.app_rd_data_reg[493]\;
  \not_strict_mode.app_rd_data_reg[494]\ <= \^not_strict_mode.app_rd_data_reg[494]\;
  \not_strict_mode.app_rd_data_reg[495]\ <= \^not_strict_mode.app_rd_data_reg[495]\;
\gen_mux_rd[0].mux_rd_fall0_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[104]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      O => \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_23\,
      O => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[0].mux_rd_fall1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[232]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      O => \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_35\,
      O => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[0].mux_rd_fall2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[360]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      O => \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_47\,
      O => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[0].mux_rd_fall3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[488]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      O => \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_58\,
      O => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[0].mux_rd_rise0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[40]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      O => \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0\
    );
\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_0\,
      O => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[0].mux_rd_rise1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[168]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      O => \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_30\,
      O => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[0].mux_rd_rise2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[296]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      O => \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_41\,
      O => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[0].mux_rd_rise3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[424]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      O => \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\
    );
\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_13\,
      O => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_fall0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[105]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      O => \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_24\,
      O => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_fall1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[233]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      O => \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_36\,
      O => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_fall2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[361]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      O => \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_48\,
      O => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_fall3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[489]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      O => \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_59\,
      O => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_rise0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[41]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      O => \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_1\,
      O => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_rise1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[169]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      O => \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_31\,
      O => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_rise2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[297]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      O => \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_8\,
      O => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[1].mux_rd_rise3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[425]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      O => \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\
    );
\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_14\,
      O => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_fall0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[106]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      O => \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_25\,
      O => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_fall1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[234]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      O => \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_37\,
      O => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_fall2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[362]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      O => \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_49\,
      O => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_fall3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[490]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      O => \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_15\,
      O => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[42]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      O => \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_17\,
      O => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[170]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      O => \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_32\,
      O => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[298]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      O => \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_42\,
      O => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[426]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      O => \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\
    );
\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_52\,
      O => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_fall0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[107]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      O => \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_2\,
      O => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_fall1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[235]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      O => \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_6\,
      O => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_fall2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[363]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      O => \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_10\,
      O => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_fall3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[491]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      O => \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_60\,
      O => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_rise0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[43]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      O => \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_18\,
      O => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_rise1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[171]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      O => \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_33\,
      O => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_rise2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[299]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      O => \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_43\,
      O => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_rise3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[427]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      O => \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\
    );
\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_53\,
      O => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_fall0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[108]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      O => \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_26\,
      O => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_fall1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[236]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      O => \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_38\,
      O => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_fall2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[364]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      O => \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_50\,
      O => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_fall3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[492]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      O => \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_61\,
      O => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_rise0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[44]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      O => \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_19\,
      O => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_rise1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[172]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      O => \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_34\,
      O => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_rise2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[300]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      O => \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_44\,
      O => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[4].mux_rd_rise3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[428]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      O => \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\
    );
\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_54\,
      O => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_fall0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[109]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      O => \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_27\,
      O => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_fall1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[237]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      O => \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_39\,
      O => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_fall2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[365]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      O => \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_11\,
      O => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_fall3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[493]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      O => \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_62\,
      O => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_rise0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[45]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      O => \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_20\,
      O => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_rise1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[173]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      O => \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_3\,
      O => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_rise2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[301]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      O => \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_45\,
      O => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[5].mux_rd_rise3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[429]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      O => \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\
    );
\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_55\,
      O => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_fall0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[110]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      O => \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_28\,
      O => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_fall1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[238]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      O => \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_40\,
      O => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_fall2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[366]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      O => \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_51\,
      O => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_fall3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[494]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      O => \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_63\,
      O => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_rise0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[46]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      O => \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_21\,
      O => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_rise1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[174]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      O => \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_4\,
      O => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_rise2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[302]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      O => \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_9\,
      O => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[6].mux_rd_rise3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[430]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      O => \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\
    );
\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_56\,
      O => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_fall0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[111]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\,
      O => \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_29\,
      O => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_fall1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[239]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\,
      O => \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_7\,
      O => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_fall2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[367]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\,
      O => \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_12\,
      O => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_fall3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[495]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\,
      O => \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_16\,
      O => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_rise0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[47]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      O => \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_22\,
      O => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_rise1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[175]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\,
      O => \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_5\,
      O => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_rise2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[303]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\,
      O => \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_46\,
      O => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\gen_mux_rd[7].mux_rd_rise3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[431]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\,
      O => \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\
    );
\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\,
      I1 => \rd_mux_sel_r_reg[1]_57\,
      O => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      S => \rd_mux_sel_r_reg[2]\
    );
\i___84_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => my_empty(0),
      I1 => if_empty_r_1(0),
      I2 => if_empty_r(0),
      I3 => \my_empty_reg[3]_0\(0),
      I4 => if_empty_r_0(0),
      I5 => \my_empty_reg[3]_1\(0),
      O => if_empty_or_v(0)
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_6_11_n_0,
      DOA(0) => mem_reg_0_3_6_11_n_1,
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_3_6_11_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => if_empty_r_1(0),
      I1 => my_full(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(2),
      O => wr_en
    );
\my_empty[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(0),
      I1 => \my_empty[4]_i_2__4_n_0\,
      I2 => \my_empty[4]_i_3__1_n_0\,
      O => \my_empty[0]_i_1__4_n_0\
    );
\my_empty[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_empty[4]_i_2__4_n_0\,
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      I5 => my_empty(1),
      O => \my_empty[1]_i_1__4_n_0\
    );
\my_empty[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(2),
      I1 => \my_empty[4]_i_2__4_n_0\,
      I2 => \my_empty[4]_i_3__1_n_0\,
      O => \my_empty[2]_i_1__4_n_0\
    );
\my_empty[3]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(3),
      I1 => \my_empty[4]_i_2__4_n_0\,
      I2 => \my_empty[4]_i_3__1_n_0\,
      O => \my_empty[3]_i_1__4_n_0\
    );
\my_empty[4]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(4),
      I1 => \my_empty[4]_i_2__4_n_0\,
      I2 => \my_empty[4]_i_3__1_n_0\,
      O => \my_empty[4]_i_1__4_n_0\
    );
\my_empty[4]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEBF"
    )
        port map (
      I0 => my_full(1),
      I1 => if_empty_r_1(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(1),
      O => \my_empty[4]_i_2__4_n_0\
    );
\my_empty[4]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => wr_ptr(1),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => wr_ptr(0),
      I4 => my_empty(1),
      O => \my_empty[4]_i_3__1_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_empty[0]_i_1__4_n_0\,
      Q => my_empty(0),
      S => ififo_rst
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_empty[1]_i_1__4_n_0\,
      Q => my_empty(1),
      S => ififo_rst
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_empty[2]_i_1__4_n_0\,
      Q => my_empty(2),
      S => ififo_rst
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_empty[3]_i_1__4_n_0\,
      Q => my_empty(3),
      S => ififo_rst
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_empty[4]_i_1__4_n_0\,
      Q => my_empty(4),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_empty[4]_i_1__4_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => if_empty_r_1(0),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I5 => \my_full[0]_i_2__6_n_0\,
      O => \my_full[0]_i_1__4_n_0\
    );
\my_full[0]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => rd_ptr(1),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => rd_ptr(0),
      I4 => my_full(1),
      O => \my_full[0]_i_2__6_n_0\
    );
\my_full[1]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => if_empty_r_1(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      O => \my_full[1]_i_1__4_n_0\
    );
\my_full[1]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_full[1]_i_3__0_n_0\,
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      I5 => my_full(1),
      O => \my_full[1]_i_2__4_n_0\
    );
\my_full[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000077707770777"
    )
        port map (
      I0 => my_empty(3),
      I1 => if_empty_r_1(0),
      I2 => if_empty_r(0),
      I3 => \my_empty_reg[3]_0\(1),
      I4 => if_empty_r_0(0),
      I5 => \my_empty_reg[3]_1\(1),
      O => byte_rd_en_v_2
    );
\my_full[1]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => my_full(1),
      I2 => if_empty_r_1(0),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      O => \my_full[1]_i_3__0_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_full[0]_i_1__4_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \my_full[1]_i_2__4_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\not_strict_mode.app_rd_data[104]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[104]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(8)
    );
\not_strict_mode.app_rd_data[105]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[105]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(9)
    );
\not_strict_mode.app_rd_data[106]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[106]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(10)
    );
\not_strict_mode.app_rd_data[107]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[107]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(11)
    );
\not_strict_mode.app_rd_data[108]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[108]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(12)
    );
\not_strict_mode.app_rd_data[109]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[109]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(13)
    );
\not_strict_mode.app_rd_data[110]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[110]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(14)
    );
\not_strict_mode.app_rd_data[111]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[111]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(15)
    );
\not_strict_mode.app_rd_data[168]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[168]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(16)
    );
\not_strict_mode.app_rd_data[169]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[169]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(17)
    );
\not_strict_mode.app_rd_data[170]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[170]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(18)
    );
\not_strict_mode.app_rd_data[171]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[171]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(19)
    );
\not_strict_mode.app_rd_data[172]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[172]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(20)
    );
\not_strict_mode.app_rd_data[173]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[173]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(21)
    );
\not_strict_mode.app_rd_data[174]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[174]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(22)
    );
\not_strict_mode.app_rd_data[175]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[175]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(23)
    );
\not_strict_mode.app_rd_data[232]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[232]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(24)
    );
\not_strict_mode.app_rd_data[233]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[233]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(25)
    );
\not_strict_mode.app_rd_data[234]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[234]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(26)
    );
\not_strict_mode.app_rd_data[235]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[235]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(27)
    );
\not_strict_mode.app_rd_data[236]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[236]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(28)
    );
\not_strict_mode.app_rd_data[237]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[237]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(29)
    );
\not_strict_mode.app_rd_data[238]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[238]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(30)
    );
\not_strict_mode.app_rd_data[239]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[239]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(31)
    );
\not_strict_mode.app_rd_data[296]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[296]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(32)
    );
\not_strict_mode.app_rd_data[297]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[297]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(33)
    );
\not_strict_mode.app_rd_data[298]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[298]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(34)
    );
\not_strict_mode.app_rd_data[299]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[299]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(35)
    );
\not_strict_mode.app_rd_data[300]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[300]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(36)
    );
\not_strict_mode.app_rd_data[301]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[301]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(37)
    );
\not_strict_mode.app_rd_data[302]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[302]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(38)
    );
\not_strict_mode.app_rd_data[303]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[303]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(39)
    );
\not_strict_mode.app_rd_data[360]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[360]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(40)
    );
\not_strict_mode.app_rd_data[361]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[361]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(41)
    );
\not_strict_mode.app_rd_data[362]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[362]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(42)
    );
\not_strict_mode.app_rd_data[363]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[363]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(43)
    );
\not_strict_mode.app_rd_data[364]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[364]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(44)
    );
\not_strict_mode.app_rd_data[365]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[365]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(45)
    );
\not_strict_mode.app_rd_data[366]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[366]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(46)
    );
\not_strict_mode.app_rd_data[367]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[367]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(47)
    );
\not_strict_mode.app_rd_data[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[40]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(0)
    );
\not_strict_mode.app_rd_data[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[41]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(1)
    );
\not_strict_mode.app_rd_data[424]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[424]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(48)
    );
\not_strict_mode.app_rd_data[425]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[425]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(49)
    );
\not_strict_mode.app_rd_data[426]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[426]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(50)
    );
\not_strict_mode.app_rd_data[427]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[427]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(51)
    );
\not_strict_mode.app_rd_data[428]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[428]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(52)
    );
\not_strict_mode.app_rd_data[429]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[429]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(53)
    );
\not_strict_mode.app_rd_data[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[42]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(2)
    );
\not_strict_mode.app_rd_data[430]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[430]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(54)
    );
\not_strict_mode.app_rd_data[431]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[431]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(55)
    );
\not_strict_mode.app_rd_data[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[43]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(3)
    );
\not_strict_mode.app_rd_data[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[44]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(4)
    );
\not_strict_mode.app_rd_data[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[45]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(5)
    );
\not_strict_mode.app_rd_data[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[46]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(6)
    );
\not_strict_mode.app_rd_data[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[47]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(7)
    );
\not_strict_mode.app_rd_data[488]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[488]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(56)
    );
\not_strict_mode.app_rd_data[489]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[489]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(57)
    );
\not_strict_mode.app_rd_data[490]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[490]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(58)
    );
\not_strict_mode.app_rd_data[491]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[491]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(59)
    );
\not_strict_mode.app_rd_data[492]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[492]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(60)
    );
\not_strict_mode.app_rd_data[493]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[493]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(61)
    );
\not_strict_mode.app_rd_data[494]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[494]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(62)
    );
\not_strict_mode.app_rd_data[495]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[495]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1),
      O => \not_strict_mode.app_rd_data_reg[495]_0\(63)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(35),
      I1 => mem_out(41),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[107]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(43),
      I1 => mem_out(49),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[106]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(51),
      I1 => mem_out(57),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[105]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(59),
      I1 => mem_out(65),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[104]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(3),
      I1 => mem_out(9),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[111]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(11),
      I1 => mem_out(17),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[110]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(19),
      I1 => mem_out(25),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[109]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(27),
      I1 => mem_out(33),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[108]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(20),
      I1 => mem_out(26),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[173]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(28),
      I1 => mem_out(34),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[172]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(36),
      I1 => mem_out(42),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[171]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(44),
      I1 => mem_out(50),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[170]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(52),
      I1 => mem_out(58),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[169]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(60),
      I1 => mem_out(66),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[168]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(4),
      I1 => mem_out(10),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[175]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(12),
      I1 => mem_out(18),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[174]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(53),
      I1 => mem_out(59),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[233]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(61),
      I1 => mem_out(67),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[232]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(5),
      I1 => mem_out(11),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[239]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(13),
      I1 => mem_out(19),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[238]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(21),
      I1 => mem_out(27),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[237]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(29),
      I1 => mem_out(35),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[236]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(37),
      I1 => mem_out(43),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[235]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(45),
      I1 => mem_out(51),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[234]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(38),
      I1 => mem_out(44),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[299]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(46),
      I1 => mem_out(52),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[298]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(54),
      I1 => mem_out(60),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[297]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(62),
      I1 => mem_out(68),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[296]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(6),
      I1 => mem_out(12),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[303]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(14),
      I1 => mem_out(20),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[302]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(22),
      I1 => mem_out(28),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[301]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(30),
      I1 => mem_out(36),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[300]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(23),
      I1 => mem_out(29),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[365]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(31),
      I1 => mem_out(37),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[364]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(39),
      I1 => mem_out(45),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[363]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(47),
      I1 => mem_out(53),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[362]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(55),
      I1 => mem_out(61),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[361]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(63),
      I1 => mem_out(69),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[360]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(7),
      I1 => mem_out(13),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[367]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(15),
      I1 => mem_out(21),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[366]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(50),
      I1 => mem_out(56),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[41]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(58),
      I1 => mem_out(64),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[40]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(56),
      I1 => mem_out(62),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[425]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(64),
      I1 => mem_out(70),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[424]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(8),
      I1 => mem_out(14),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[431]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(16),
      I1 => mem_out(22),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[430]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(24),
      I1 => mem_out(30),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[429]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(32),
      I1 => mem_out(38),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[428]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(40),
      I1 => mem_out(46),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[427]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(48),
      I1 => mem_out(54),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[426]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(2),
      I1 => mem_out(8),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[47]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(10),
      I1 => mem_out(16),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[46]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(18),
      I1 => mem_out(24),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[45]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(26),
      I1 => mem_out(32),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[44]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(34),
      I1 => mem_out(40),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[43]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(42),
      I1 => mem_out(48),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[42]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(41),
      I1 => mem_out(47),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[491]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(49),
      I1 => mem_out(55),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[490]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(57),
      I1 => mem_out(63),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[489]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(65),
      I1 => mem_out(71),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[488]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(9),
      I1 => mem_out(15),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[495]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(17),
      I1 => mem_out(23),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[494]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(25),
      I1 => mem_out(31),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[493]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(33),
      I1 => mem_out(39),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[492]\
    );
\rd_ptr[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__2_n_0\
    );
\rd_ptr[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000B4F0"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => ififo_rst,
      O => \rd_ptr[1]_i_1__3_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1__2_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1__3_n_0\,
      Q => rd_ptr(1),
      R => '0'
    );
\rd_ptr_timing[0]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EF0F0000FFFF10F0"
    )
        port map (
      I0 => if_empty_r_1(0),
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(0),
      I5 => rd_ptr(0),
      O => \rd_ptr_timing[0]_i_1__8_n_0\
    );
\rd_ptr_timing[1]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10F0EF0F0000"
    )
        port map (
      I0 => if_empty_r_1(0),
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      I5 => \rd_ptr_timing[1]_i_2__2_n_0\,
      O => \rd_ptr_timing[1]_i_1__8_n_0\
    );
\rd_ptr_timing[1]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \rd_ptr_timing[1]_i_2__2_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \rd_ptr_timing[0]_i_1__8_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__4_n_0\,
      D => \rd_ptr_timing[1]_i_1__8_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAA965"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => if_empty_r_1(0),
      I5 => ififo_rst,
      O => \wr_ptr[0]_i_1__14_n_0\
    );
\wr_ptr[0]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => if_empty_r_1(0),
      I1 => my_empty(3),
      O => C_byte_rd_en
    );
\wr_ptr[0]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => my_empty(3),
      I1 => if_empty_r_1(0),
      I2 => \my_empty_reg[3]_0\(1),
      I3 => if_empty_r(0),
      O => \rd_ptr_timing_reg[0]_0\
    );
\wr_ptr[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => my_empty(3),
      I1 => if_empty_r_1(0),
      I2 => \my_empty_reg[3]_1\(1),
      I3 => if_empty_r_0(0),
      O => \rd_ptr_timing_reg[0]_1\
    );
\wr_ptr[1]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => wr_ptr(1),
      I1 => \wr_ptr[1]_i_2__4_n_0\,
      I2 => wr_ptr(0),
      I3 => ififo_rst,
      O => \wr_ptr[1]_i_1__14_n_0\
    );
\wr_ptr[1]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1105"
    )
        port map (
      I0 => if_empty_r_1(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      O => \wr_ptr[1]_i_2__4_n_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__14_n_0\,
      Q => wr_ptr(0),
      R => '0'
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__14_n_0\,
      Q => wr_ptr(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_14 is
  port (
    \not_strict_mode.rd_buf_we\ : out STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[32]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[34]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[36]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[38]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[96]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[98]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[100]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[102]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[160]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[162]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[164]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[166]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[224]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[226]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[228]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[230]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[288]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[290]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[292]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[294]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[352]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[354]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[356]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[358]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[416]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[418]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[420]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[422]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[480]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[482]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[484]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[486]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]_0\ : out STD_LOGIC;
    byte_rd_en_v_1 : out STD_LOGIC;
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    byte_rd_en_v_2 : in STD_LOGIC;
    byte_rd_en_v_0 : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_init_done_r : in STD_LOGIC;
    if_empty_or_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.fifo_out_data_r_reg[6]_0\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ififo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 65 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_14 : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_14;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_14 is
  signal mem_out : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal mem_reg_0_3_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_3_60_65_n_5 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \my_empty[0]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_2_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_5_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[100]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[101]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[102]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[103]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[160]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[161]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[162]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[163]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[164]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[165]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[166]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[167]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[224]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[225]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[226]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[227]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[228]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[229]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[230]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[231]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[288]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[289]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[290]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[291]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[292]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[293]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[294]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[295]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[32]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[33]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[34]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[352]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[353]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[354]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[355]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[356]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[357]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[358]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[359]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[35]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[36]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[37]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[38]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[39]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[416]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[417]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[418]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[419]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[420]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[421]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[422]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[423]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[480]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[481]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[482]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[483]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[484]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[485]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[486]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[487]_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[96]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[97]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[98]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[99]\ : STD_LOGIC;
  signal \^not_strict_mode.status_ram.rd_buf_we_r1_reg\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_2_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_2_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_full[0]_i_2\ : label is "soft_lutpair676";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[100]_i_1\ : label is "soft_lutpair689";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[101]_i_1\ : label is "soft_lutpair684";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[102]_i_1\ : label is "soft_lutpair683";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[103]_i_1\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[160]_i_1\ : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[161]_i_1\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[162]_i_1\ : label is "soft_lutpair682";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[163]_i_1\ : label is "soft_lutpair690";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[164]_i_1\ : label is "soft_lutpair688";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[165]_i_1\ : label is "soft_lutpair685";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[166]_i_1\ : label is "soft_lutpair686";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[167]_i_1\ : label is "soft_lutpair687";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[224]_i_1\ : label is "soft_lutpair691";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[225]_i_1\ : label is "soft_lutpair691";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[226]_i_1\ : label is "soft_lutpair692";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[227]_i_1\ : label is "soft_lutpair693";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[228]_i_1\ : label is "soft_lutpair692";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[229]_i_1\ : label is "soft_lutpair693";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[230]_i_1\ : label is "soft_lutpair694";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[231]_i_1\ : label is "soft_lutpair694";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[288]_i_1\ : label is "soft_lutpair695";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[289]_i_1\ : label is "soft_lutpair695";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[290]_i_1\ : label is "soft_lutpair696";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[291]_i_1\ : label is "soft_lutpair696";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[292]_i_1\ : label is "soft_lutpair697";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[293]_i_1\ : label is "soft_lutpair697";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[294]_i_1\ : label is "soft_lutpair698";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[295]_i_1\ : label is "soft_lutpair698";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[32]_i_1\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[33]_i_1\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[34]_i_1\ : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[352]_i_1\ : label is "soft_lutpair699";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[353]_i_1\ : label is "soft_lutpair700";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[354]_i_1\ : label is "soft_lutpair701";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[355]_i_1\ : label is "soft_lutpair699";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[356]_i_1\ : label is "soft_lutpair702";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[357]_i_1\ : label is "soft_lutpair700";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[358]_i_1\ : label is "soft_lutpair701";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[359]_i_1\ : label is "soft_lutpair702";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[35]_i_1\ : label is "soft_lutpair682";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[36]_i_1\ : label is "soft_lutpair683";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[37]_i_1\ : label is "soft_lutpair684";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[38]_i_1\ : label is "soft_lutpair685";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[39]_i_1\ : label is "soft_lutpair686";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[416]_i_1\ : label is "soft_lutpair703";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[417]_i_1\ : label is "soft_lutpair703";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[418]_i_1\ : label is "soft_lutpair704";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[419]_i_1\ : label is "soft_lutpair704";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[420]_i_1\ : label is "soft_lutpair705";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[421]_i_1\ : label is "soft_lutpair705";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[422]_i_1\ : label is "soft_lutpair706";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[423]_i_1\ : label is "soft_lutpair706";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[480]_i_1\ : label is "soft_lutpair707";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[481]_i_1\ : label is "soft_lutpair707";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[482]_i_1\ : label is "soft_lutpair708";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[483]_i_1\ : label is "soft_lutpair708";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[484]_i_1\ : label is "soft_lutpair709";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[485]_i_1\ : label is "soft_lutpair709";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[486]_i_1\ : label is "soft_lutpair710";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[487]_i_1\ : label is "soft_lutpair710";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[96]_i_1\ : label is "soft_lutpair687";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[97]_i_1\ : label is "soft_lutpair688";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[98]_i_1\ : label is "soft_lutpair689";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[99]_i_1\ : label is "soft_lutpair690";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1\ : label is "soft_lutpair677";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair677";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2\ : label is "soft_lutpair676";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_2\ : label is "soft_lutpair678";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_4\ : label is "soft_lutpair678";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \not_strict_mode.app_rd_data_reg[100]\ <= \^not_strict_mode.app_rd_data_reg[100]\;
  \not_strict_mode.app_rd_data_reg[101]\ <= \^not_strict_mode.app_rd_data_reg[101]\;
  \not_strict_mode.app_rd_data_reg[102]\ <= \^not_strict_mode.app_rd_data_reg[102]\;
  \not_strict_mode.app_rd_data_reg[103]\ <= \^not_strict_mode.app_rd_data_reg[103]\;
  \not_strict_mode.app_rd_data_reg[160]\ <= \^not_strict_mode.app_rd_data_reg[160]\;
  \not_strict_mode.app_rd_data_reg[161]\ <= \^not_strict_mode.app_rd_data_reg[161]\;
  \not_strict_mode.app_rd_data_reg[162]\ <= \^not_strict_mode.app_rd_data_reg[162]\;
  \not_strict_mode.app_rd_data_reg[163]\ <= \^not_strict_mode.app_rd_data_reg[163]\;
  \not_strict_mode.app_rd_data_reg[164]\ <= \^not_strict_mode.app_rd_data_reg[164]\;
  \not_strict_mode.app_rd_data_reg[165]\ <= \^not_strict_mode.app_rd_data_reg[165]\;
  \not_strict_mode.app_rd_data_reg[166]\ <= \^not_strict_mode.app_rd_data_reg[166]\;
  \not_strict_mode.app_rd_data_reg[167]\ <= \^not_strict_mode.app_rd_data_reg[167]\;
  \not_strict_mode.app_rd_data_reg[224]\ <= \^not_strict_mode.app_rd_data_reg[224]\;
  \not_strict_mode.app_rd_data_reg[225]\ <= \^not_strict_mode.app_rd_data_reg[225]\;
  \not_strict_mode.app_rd_data_reg[226]\ <= \^not_strict_mode.app_rd_data_reg[226]\;
  \not_strict_mode.app_rd_data_reg[227]\ <= \^not_strict_mode.app_rd_data_reg[227]\;
  \not_strict_mode.app_rd_data_reg[228]\ <= \^not_strict_mode.app_rd_data_reg[228]\;
  \not_strict_mode.app_rd_data_reg[229]\ <= \^not_strict_mode.app_rd_data_reg[229]\;
  \not_strict_mode.app_rd_data_reg[230]\ <= \^not_strict_mode.app_rd_data_reg[230]\;
  \not_strict_mode.app_rd_data_reg[231]\ <= \^not_strict_mode.app_rd_data_reg[231]\;
  \not_strict_mode.app_rd_data_reg[288]\ <= \^not_strict_mode.app_rd_data_reg[288]\;
  \not_strict_mode.app_rd_data_reg[289]\ <= \^not_strict_mode.app_rd_data_reg[289]\;
  \not_strict_mode.app_rd_data_reg[290]\ <= \^not_strict_mode.app_rd_data_reg[290]\;
  \not_strict_mode.app_rd_data_reg[291]\ <= \^not_strict_mode.app_rd_data_reg[291]\;
  \not_strict_mode.app_rd_data_reg[292]\ <= \^not_strict_mode.app_rd_data_reg[292]\;
  \not_strict_mode.app_rd_data_reg[293]\ <= \^not_strict_mode.app_rd_data_reg[293]\;
  \not_strict_mode.app_rd_data_reg[294]\ <= \^not_strict_mode.app_rd_data_reg[294]\;
  \not_strict_mode.app_rd_data_reg[295]\ <= \^not_strict_mode.app_rd_data_reg[295]\;
  \not_strict_mode.app_rd_data_reg[32]\ <= \^not_strict_mode.app_rd_data_reg[32]\;
  \not_strict_mode.app_rd_data_reg[33]\ <= \^not_strict_mode.app_rd_data_reg[33]\;
  \not_strict_mode.app_rd_data_reg[34]\ <= \^not_strict_mode.app_rd_data_reg[34]\;
  \not_strict_mode.app_rd_data_reg[352]\ <= \^not_strict_mode.app_rd_data_reg[352]\;
  \not_strict_mode.app_rd_data_reg[353]\ <= \^not_strict_mode.app_rd_data_reg[353]\;
  \not_strict_mode.app_rd_data_reg[354]\ <= \^not_strict_mode.app_rd_data_reg[354]\;
  \not_strict_mode.app_rd_data_reg[355]\ <= \^not_strict_mode.app_rd_data_reg[355]\;
  \not_strict_mode.app_rd_data_reg[356]\ <= \^not_strict_mode.app_rd_data_reg[356]\;
  \not_strict_mode.app_rd_data_reg[357]\ <= \^not_strict_mode.app_rd_data_reg[357]\;
  \not_strict_mode.app_rd_data_reg[358]\ <= \^not_strict_mode.app_rd_data_reg[358]\;
  \not_strict_mode.app_rd_data_reg[359]\ <= \^not_strict_mode.app_rd_data_reg[359]\;
  \not_strict_mode.app_rd_data_reg[35]\ <= \^not_strict_mode.app_rd_data_reg[35]\;
  \not_strict_mode.app_rd_data_reg[36]\ <= \^not_strict_mode.app_rd_data_reg[36]\;
  \not_strict_mode.app_rd_data_reg[37]\ <= \^not_strict_mode.app_rd_data_reg[37]\;
  \not_strict_mode.app_rd_data_reg[38]\ <= \^not_strict_mode.app_rd_data_reg[38]\;
  \not_strict_mode.app_rd_data_reg[39]\ <= \^not_strict_mode.app_rd_data_reg[39]\;
  \not_strict_mode.app_rd_data_reg[416]\ <= \^not_strict_mode.app_rd_data_reg[416]\;
  \not_strict_mode.app_rd_data_reg[417]\ <= \^not_strict_mode.app_rd_data_reg[417]\;
  \not_strict_mode.app_rd_data_reg[418]\ <= \^not_strict_mode.app_rd_data_reg[418]\;
  \not_strict_mode.app_rd_data_reg[419]\ <= \^not_strict_mode.app_rd_data_reg[419]\;
  \not_strict_mode.app_rd_data_reg[420]\ <= \^not_strict_mode.app_rd_data_reg[420]\;
  \not_strict_mode.app_rd_data_reg[421]\ <= \^not_strict_mode.app_rd_data_reg[421]\;
  \not_strict_mode.app_rd_data_reg[422]\ <= \^not_strict_mode.app_rd_data_reg[422]\;
  \not_strict_mode.app_rd_data_reg[423]\ <= \^not_strict_mode.app_rd_data_reg[423]\;
  \not_strict_mode.app_rd_data_reg[480]\ <= \^not_strict_mode.app_rd_data_reg[480]\;
  \not_strict_mode.app_rd_data_reg[481]\ <= \^not_strict_mode.app_rd_data_reg[481]\;
  \not_strict_mode.app_rd_data_reg[482]\ <= \^not_strict_mode.app_rd_data_reg[482]\;
  \not_strict_mode.app_rd_data_reg[483]\ <= \^not_strict_mode.app_rd_data_reg[483]\;
  \not_strict_mode.app_rd_data_reg[484]\ <= \^not_strict_mode.app_rd_data_reg[484]\;
  \not_strict_mode.app_rd_data_reg[485]\ <= \^not_strict_mode.app_rd_data_reg[485]\;
  \not_strict_mode.app_rd_data_reg[486]\ <= \^not_strict_mode.app_rd_data_reg[486]\;
  \not_strict_mode.app_rd_data_reg[487]_0\ <= \^not_strict_mode.app_rd_data_reg[487]_0\;
  \not_strict_mode.app_rd_data_reg[96]\ <= \^not_strict_mode.app_rd_data_reg[96]\;
  \not_strict_mode.app_rd_data_reg[97]\ <= \^not_strict_mode.app_rd_data_reg[97]\;
  \not_strict_mode.app_rd_data_reg[98]\ <= \^not_strict_mode.app_rd_data_reg[98]\;
  \not_strict_mode.app_rd_data_reg[99]\ <= \^not_strict_mode.app_rd_data_reg[99]\;
  \not_strict_mode.status_ram.rd_buf_we_r1_reg\ <= \^not_strict_mode.status_ram.rd_buf_we_r1_reg\;
\i___84_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000700000000"
    )
        port map (
      I0 => if_empty_r(0),
      I1 => my_empty(0),
      I2 => if_empty_or_v(0),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I5 => \out\,
      O => \^not_strict_mode.status_ram.rd_buf_we_r1_reg\
    );
mem_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(1 downto 0),
      DOB(1 downto 0) => mem_out(3 downto 2),
      DOC(1 downto 0) => mem_out(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_0_5_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001500D5"
    )
        port map (
      I0 => my_full(0),
      I1 => byte_rd_en_v_2,
      I2 => byte_rd_en_v_0,
      I3 => if_empty_r(0),
      I4 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1) => mem_reg_0_3_60_65_n_4,
      DOC(0) => mem_reg_0_3_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(7 downto 6),
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty(0),
      I1 => my_full(1),
      I2 => if_empty_r(0),
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[0]_i_1_n_0\
    );
\my_empty[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_empty[1]_i_2_n_0\,
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      I5 => my_empty(1),
      O => \my_empty[1]_i_1_n_0\
    );
\my_empty[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAFFEAFFFFBFFF"
    )
        port map (
      I0 => my_full(1),
      I1 => byte_rd_en_v_2,
      I2 => byte_rd_en_v_0,
      I3 => if_empty_r(0),
      I4 => my_empty(3),
      I5 => my_empty(1),
      O => \my_empty[1]_i_2_n_0\
    );
\my_empty[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty(2),
      I1 => my_full(1),
      I2 => if_empty_r(0),
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[2]_i_1_n_0\
    );
\my_empty[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty(3),
      I1 => my_full(1),
      I2 => if_empty_r(0),
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[3]_i_1_n_0\
    );
\my_empty[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBAAAAAA88AAA"
    )
        port map (
      I0 => my_empty(4),
      I1 => my_full(1),
      I2 => if_empty_r(0),
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => my_empty(1),
      I5 => \my_empty[4]_i_2_n_0\,
      O => \my_empty[4]_i_1_n_0\
    );
\my_empty[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => wr_ptr(1),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => wr_ptr(0),
      I4 => my_empty(1),
      O => \my_empty[4]_i_2_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[0]_i_1_n_0\,
      Q => my_empty(0),
      S => ififo_rst
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[1]_i_1_n_0\,
      Q => my_empty(1),
      S => ififo_rst
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[2]_i_1_n_0\,
      Q => my_empty(2),
      S => ififo_rst
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[3]_i_1_n_0\,
      Q => my_empty(3),
      S => ififo_rst
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[4]_i_1_n_0\,
      Q => my_empty(4),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_empty[4]_i_1_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => if_empty_r(0),
      I4 => \wr_ptr[1]_i_2_n_0\,
      I5 => \my_full[0]_i_2_n_0\,
      O => \my_full[0]_i_1_n_0\
    );
\my_full[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => rd_ptr(1),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => rd_ptr(0),
      I4 => my_full(1),
      O => \my_full[0]_i_2_n_0\
    );
\my_full[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => if_empty_r(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => byte_rd_en_v_2,
      I4 => byte_rd_en_v_0,
      O => \my_full[1]_i_1_n_0\
    );
\my_full[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_full[1]_i_5_n_0\,
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      I5 => my_full(1),
      O => \my_full[1]_i_2_n_0\
    );
\my_full[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFEFEBFFEFEFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => my_full(1),
      I2 => if_empty_r(0),
      I3 => byte_rd_en_v_2,
      I4 => byte_rd_en_v_0,
      I5 => my_empty(3),
      O => \my_full[1]_i_5_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_full[0]_i_1_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \my_full[1]_i_2_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\not_strict_mode.app_rd_data[100]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[100]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(12)
    );
\not_strict_mode.app_rd_data[101]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[101]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(13)
    );
\not_strict_mode.app_rd_data[102]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[102]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(14)
    );
\not_strict_mode.app_rd_data[103]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[103]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(15)
    );
\not_strict_mode.app_rd_data[160]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[160]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(16)
    );
\not_strict_mode.app_rd_data[161]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[161]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(17)
    );
\not_strict_mode.app_rd_data[162]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[162]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(18)
    );
\not_strict_mode.app_rd_data[163]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[163]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(19)
    );
\not_strict_mode.app_rd_data[164]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[164]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(20)
    );
\not_strict_mode.app_rd_data[165]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[165]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(21)
    );
\not_strict_mode.app_rd_data[166]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[166]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(22)
    );
\not_strict_mode.app_rd_data[167]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[167]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(23)
    );
\not_strict_mode.app_rd_data[224]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[224]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(24)
    );
\not_strict_mode.app_rd_data[225]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[225]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(25)
    );
\not_strict_mode.app_rd_data[226]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[226]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(26)
    );
\not_strict_mode.app_rd_data[227]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[227]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(27)
    );
\not_strict_mode.app_rd_data[228]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[228]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(28)
    );
\not_strict_mode.app_rd_data[229]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[229]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(29)
    );
\not_strict_mode.app_rd_data[230]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[230]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(30)
    );
\not_strict_mode.app_rd_data[231]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[231]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(31)
    );
\not_strict_mode.app_rd_data[288]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[288]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(32)
    );
\not_strict_mode.app_rd_data[289]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[289]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(33)
    );
\not_strict_mode.app_rd_data[290]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[290]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(34)
    );
\not_strict_mode.app_rd_data[291]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[291]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(35)
    );
\not_strict_mode.app_rd_data[292]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[292]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(36)
    );
\not_strict_mode.app_rd_data[293]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[293]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(37)
    );
\not_strict_mode.app_rd_data[294]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[294]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(38)
    );
\not_strict_mode.app_rd_data[295]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[295]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(39)
    );
\not_strict_mode.app_rd_data[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[32]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(0)
    );
\not_strict_mode.app_rd_data[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[33]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(1)
    );
\not_strict_mode.app_rd_data[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[34]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(2)
    );
\not_strict_mode.app_rd_data[352]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[352]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(40)
    );
\not_strict_mode.app_rd_data[353]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[353]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(41)
    );
\not_strict_mode.app_rd_data[354]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[354]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(42)
    );
\not_strict_mode.app_rd_data[355]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[355]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(43)
    );
\not_strict_mode.app_rd_data[356]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[356]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(44)
    );
\not_strict_mode.app_rd_data[357]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[357]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(45)
    );
\not_strict_mode.app_rd_data[358]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[358]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(46)
    );
\not_strict_mode.app_rd_data[359]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[359]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(47)
    );
\not_strict_mode.app_rd_data[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[35]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(3)
    );
\not_strict_mode.app_rd_data[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[36]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(4)
    );
\not_strict_mode.app_rd_data[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[37]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(5)
    );
\not_strict_mode.app_rd_data[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[38]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(6)
    );
\not_strict_mode.app_rd_data[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[39]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(7)
    );
\not_strict_mode.app_rd_data[416]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[416]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(48)
    );
\not_strict_mode.app_rd_data[417]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[417]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(49)
    );
\not_strict_mode.app_rd_data[418]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[418]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(50)
    );
\not_strict_mode.app_rd_data[419]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[419]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(51)
    );
\not_strict_mode.app_rd_data[420]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[420]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(52)
    );
\not_strict_mode.app_rd_data[421]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[421]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(53)
    );
\not_strict_mode.app_rd_data[422]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[422]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(54)
    );
\not_strict_mode.app_rd_data[423]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[423]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(55)
    );
\not_strict_mode.app_rd_data[480]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[480]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(56)
    );
\not_strict_mode.app_rd_data[481]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[481]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(57)
    );
\not_strict_mode.app_rd_data[482]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[482]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(58)
    );
\not_strict_mode.app_rd_data[483]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[483]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(59)
    );
\not_strict_mode.app_rd_data[484]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[484]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(60)
    );
\not_strict_mode.app_rd_data[485]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[485]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(61)
    );
\not_strict_mode.app_rd_data[486]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[486]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(62)
    );
\not_strict_mode.app_rd_data[487]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[487]_0\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(63)
    );
\not_strict_mode.app_rd_data[96]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[96]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(8)
    );
\not_strict_mode.app_rd_data[97]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[97]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(9)
    );
\not_strict_mode.app_rd_data[98]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[98]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[487]\(10)
    );
\not_strict_mode.app_rd_data[99]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[99]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]_0\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[487]\(11)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2F"
    )
        port map (
      I0 => \^not_strict_mode.status_ram.rd_buf_we_r1_reg\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\(0),
      I2 => ram_init_done_r,
      O => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(17),
      I1 => mem_out(17),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[101]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(25),
      I1 => mem_out(25),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[100]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(33),
      I1 => mem_out(33),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[99]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(41),
      I1 => mem_out(41),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[98]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(49),
      I1 => mem_out(49),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[97]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(57),
      I1 => mem_out(57),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[96]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(1),
      I1 => mem_out(1),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[103]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(9),
      I1 => mem_out(9),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[102]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(50),
      I1 => mem_out(50),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[161]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(58),
      I1 => mem_out(58),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[160]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(2),
      I1 => mem_out(2),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[167]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(10),
      I1 => mem_out(10),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[166]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(18),
      I1 => mem_out(18),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[165]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(26),
      I1 => mem_out(26),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[164]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(34),
      I1 => mem_out(34),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[163]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(42),
      I1 => mem_out(42),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[162]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(35),
      I1 => mem_out(35),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[227]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(43),
      I1 => mem_out(43),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[226]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(51),
      I1 => mem_out(51),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[225]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(59),
      I1 => mem_out(59),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[224]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(3),
      I1 => mem_out(3),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[231]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(11),
      I1 => mem_out(11),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[230]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(19),
      I1 => mem_out(19),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[229]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(27),
      I1 => mem_out(27),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[228]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(20),
      I1 => mem_out(20),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[293]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(28),
      I1 => mem_out(28),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[292]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(36),
      I1 => mem_out(36),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[291]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(44),
      I1 => mem_out(44),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[290]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(52),
      I1 => mem_out(52),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[289]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(60),
      I1 => mem_out(60),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[288]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(4),
      I1 => mem_out(4),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[295]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(12),
      I1 => mem_out(12),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[294]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(53),
      I1 => mem_out(53),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[353]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(61),
      I1 => mem_out(61),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[352]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(5),
      I1 => mem_out(5),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[359]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(13),
      I1 => mem_out(13),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[358]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(21),
      I1 => mem_out(21),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[357]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(29),
      I1 => mem_out(29),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[356]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(37),
      I1 => mem_out(37),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[355]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(45),
      I1 => mem_out(45),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[354]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(32),
      I1 => mem_out(32),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[35]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(40),
      I1 => mem_out(40),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[34]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(48),
      I1 => mem_out(48),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[33]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(56),
      I1 => mem_out(56),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[32]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(38),
      I1 => mem_out(38),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[419]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(46),
      I1 => mem_out(46),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[418]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(54),
      I1 => mem_out(54),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[417]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(62),
      I1 => mem_out(62),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[416]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(0),
      I1 => mem_out(0),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[39]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(8),
      I1 => mem_out(8),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[38]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(16),
      I1 => mem_out(16),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[37]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(24),
      I1 => mem_out(24),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[36]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(6),
      I1 => mem_out(6),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[423]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(14),
      I1 => mem_out(14),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[422]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(22),
      I1 => mem_out(22),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[421]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(30),
      I1 => mem_out(30),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[420]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(23),
      I1 => mem_out(23),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[485]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(31),
      I1 => mem_out(31),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[484]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(39),
      I1 => mem_out(39),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[483]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(47),
      I1 => mem_out(47),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[482]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(55),
      I1 => mem_out(55),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[481]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(63),
      I1 => mem_out(63),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[480]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(7),
      I1 => mem_out(7),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[487]_0\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(15),
      I1 => mem_out(15),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[486]\
    );
rd_active_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000007"
    )
        port map (
      I0 => if_empty_r(0),
      I1 => my_empty(0),
      I2 => if_empty_or_v(0),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => phy_rddata_en
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => my_empty(1),
      I1 => \wr_ptr[1]_i_2_n_0\,
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1_n_0\
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => my_empty(1),
      I2 => \wr_ptr[1]_i_2_n_0\,
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1_n_0\,
      Q => rd_ptr(1),
      R => ififo_rst
    );
\rd_ptr_timing[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EF0F0000FFFF10F0"
    )
        port map (
      I0 => if_empty_r(0),
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2_n_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(0),
      I5 => rd_ptr(0),
      O => \rd_ptr_timing[0]_i_1__0_n_0\
    );
\rd_ptr_timing[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10F0EF0F0000"
    )
        port map (
      I0 => if_empty_r(0),
      I1 => my_full(1),
      I2 => \wr_ptr[1]_i_2_n_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      I5 => \rd_ptr_timing[1]_i_2_n_0\,
      O => \rd_ptr_timing[1]_i_1__0_n_0\
    );
\rd_ptr_timing[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \rd_ptr_timing[1]_i_2_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \rd_ptr_timing[0]_i_1__0_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1_n_0\,
      D => \rd_ptr_timing[1]_i_1__0_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\read_fifo.tail_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^not_strict_mode.status_ram.rd_buf_we_r1_reg\,
      I1 => \read_fifo.tail_r\(0),
      O => \read_fifo.tail_r_reg[0]\
    );
\wr_ptr[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEFA1105"
    )
        port map (
      I0 => if_empty_r(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \wr_ptr[1]_i_2_n_0\,
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__0_n_0\
    );
\wr_ptr[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFDFFDD02020022"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => if_empty_r(0),
      I2 => my_empty(1),
      I3 => my_full(1),
      I4 => \wr_ptr[1]_i_2_n_0\,
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__0_n_0\
    );
\wr_ptr[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => my_empty(3),
      I1 => if_empty_r(0),
      I2 => byte_rd_en_v_0,
      I3 => byte_rd_en_v_2,
      O => \wr_ptr[1]_i_2_n_0\
    );
\wr_ptr[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => if_empty_r(0),
      I1 => my_empty(3),
      O => byte_rd_en_v_1
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__0_n_0\,
      Q => wr_ptr(0),
      R => ififo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__0_n_0\,
      Q => wr_ptr(1),
      R => ififo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_20 is
  port (
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[64]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[66]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[68]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[70]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[128]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[130]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[132]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[134]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[192]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[194]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[196]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[198]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[256]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[258]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[260]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[262]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[320]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[322]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[324]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[326]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[384]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[386]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[388]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[390]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[448]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[450]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[452]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[454]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_2\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    rd_active_r_reg : out STD_LOGIC;
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    DOC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    C_byte_rd_en : in STD_LOGIC;
    byte_rd_en_v_1 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \my_empty_reg[3]_0\ : in STD_LOGIC;
    A_byte_rd_en : in STD_LOGIC;
    \my_empty_reg[3]_1\ : in STD_LOGIC;
    B_byte_rd_en : in STD_LOGIC;
    \my_empty_reg[3]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC_VECTOR ( 65 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_20 : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_20;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_20 is
  signal mem_out : STD_LOGIC_VECTOR ( 71 downto 8 );
  signal mem_reg_0_3_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_1 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \my_empty[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_3__5_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_4__2_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[0]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[128]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[129]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[130]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[131]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[132]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[133]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[134]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[135]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[192]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[193]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[194]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[195]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[196]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[197]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[198]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[199]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[1]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[256]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[257]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[258]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[259]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[260]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[261]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[262]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[263]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[2]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[320]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[321]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[322]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[323]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[324]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[325]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[326]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[327]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[384]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[385]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[386]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[387]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[388]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[389]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[390]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[391]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[3]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[448]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[449]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[450]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[451]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[452]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[453]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[454]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[455]_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[4]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[5]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[64]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[65]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[66]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[67]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[68]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[69]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[6]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[70]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[71]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[7]\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__2_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__17_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__17_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \wr_ptr[0]_i_4_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__10_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i___84_i_4\ : label is "soft_lutpair626";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute SOFT_HLUTNM of \my_empty[1]_i_1__3\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \my_empty[1]_i_2__3\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \my_empty[4]_i_2__3\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \my_empty[4]_i_3__5\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \my_empty[4]_i_4__2\ : label is "soft_lutpair624";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[0]_i_2__3\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \my_full[1]_i_2__3\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \my_full[1]_i_7\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[0]_i_1\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[128]_i_1\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[129]_i_1\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[130]_i_1\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[131]_i_1\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[132]_i_1\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[133]_i_1\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[134]_i_1\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[135]_i_1\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[192]_i_1\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[193]_i_1\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[194]_i_1\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[195]_i_1\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[196]_i_1\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[197]_i_1\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[198]_i_1\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[199]_i_1\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[1]_i_1\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[256]_i_1\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[257]_i_1\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[258]_i_1\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[259]_i_1\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[260]_i_1\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[261]_i_1\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[262]_i_1\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[263]_i_1\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[2]_i_1\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[320]_i_1\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[321]_i_1\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[322]_i_1\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[323]_i_1\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[324]_i_1\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[325]_i_1\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[326]_i_1\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[327]_i_1\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[384]_i_1\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[385]_i_1\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[386]_i_1\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[387]_i_1\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[388]_i_1\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[389]_i_1\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[390]_i_1\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[391]_i_1\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[3]_i_1\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[448]_i_1\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[449]_i_1\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[450]_i_1\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[451]_i_1\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[452]_i_1\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[453]_i_1\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[454]_i_1\ : label is "soft_lutpair659";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[455]_i_1\ : label is "soft_lutpair659";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[4]_i_1\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[5]_i_1\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[64]_i_1\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[65]_i_1\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[66]_i_1\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[67]_i_1\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[68]_i_1\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[69]_i_1\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[6]_i_1\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[70]_i_1\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[71]_i_1\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[7]_i_1\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__2\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__2\ : label is "soft_lutpair627";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__10\ : label is "soft_lutpair624";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \not_strict_mode.app_rd_data_reg[0]\ <= \^not_strict_mode.app_rd_data_reg[0]\;
  \not_strict_mode.app_rd_data_reg[128]\ <= \^not_strict_mode.app_rd_data_reg[128]\;
  \not_strict_mode.app_rd_data_reg[129]\ <= \^not_strict_mode.app_rd_data_reg[129]\;
  \not_strict_mode.app_rd_data_reg[130]\ <= \^not_strict_mode.app_rd_data_reg[130]\;
  \not_strict_mode.app_rd_data_reg[131]\ <= \^not_strict_mode.app_rd_data_reg[131]\;
  \not_strict_mode.app_rd_data_reg[132]\ <= \^not_strict_mode.app_rd_data_reg[132]\;
  \not_strict_mode.app_rd_data_reg[133]\ <= \^not_strict_mode.app_rd_data_reg[133]\;
  \not_strict_mode.app_rd_data_reg[134]\ <= \^not_strict_mode.app_rd_data_reg[134]\;
  \not_strict_mode.app_rd_data_reg[135]\ <= \^not_strict_mode.app_rd_data_reg[135]\;
  \not_strict_mode.app_rd_data_reg[192]\ <= \^not_strict_mode.app_rd_data_reg[192]\;
  \not_strict_mode.app_rd_data_reg[193]\ <= \^not_strict_mode.app_rd_data_reg[193]\;
  \not_strict_mode.app_rd_data_reg[194]\ <= \^not_strict_mode.app_rd_data_reg[194]\;
  \not_strict_mode.app_rd_data_reg[195]\ <= \^not_strict_mode.app_rd_data_reg[195]\;
  \not_strict_mode.app_rd_data_reg[196]\ <= \^not_strict_mode.app_rd_data_reg[196]\;
  \not_strict_mode.app_rd_data_reg[197]\ <= \^not_strict_mode.app_rd_data_reg[197]\;
  \not_strict_mode.app_rd_data_reg[198]\ <= \^not_strict_mode.app_rd_data_reg[198]\;
  \not_strict_mode.app_rd_data_reg[199]\ <= \^not_strict_mode.app_rd_data_reg[199]\;
  \not_strict_mode.app_rd_data_reg[1]\ <= \^not_strict_mode.app_rd_data_reg[1]\;
  \not_strict_mode.app_rd_data_reg[256]\ <= \^not_strict_mode.app_rd_data_reg[256]\;
  \not_strict_mode.app_rd_data_reg[257]\ <= \^not_strict_mode.app_rd_data_reg[257]\;
  \not_strict_mode.app_rd_data_reg[258]\ <= \^not_strict_mode.app_rd_data_reg[258]\;
  \not_strict_mode.app_rd_data_reg[259]\ <= \^not_strict_mode.app_rd_data_reg[259]\;
  \not_strict_mode.app_rd_data_reg[260]\ <= \^not_strict_mode.app_rd_data_reg[260]\;
  \not_strict_mode.app_rd_data_reg[261]\ <= \^not_strict_mode.app_rd_data_reg[261]\;
  \not_strict_mode.app_rd_data_reg[262]\ <= \^not_strict_mode.app_rd_data_reg[262]\;
  \not_strict_mode.app_rd_data_reg[263]\ <= \^not_strict_mode.app_rd_data_reg[263]\;
  \not_strict_mode.app_rd_data_reg[2]\ <= \^not_strict_mode.app_rd_data_reg[2]\;
  \not_strict_mode.app_rd_data_reg[320]\ <= \^not_strict_mode.app_rd_data_reg[320]\;
  \not_strict_mode.app_rd_data_reg[321]\ <= \^not_strict_mode.app_rd_data_reg[321]\;
  \not_strict_mode.app_rd_data_reg[322]\ <= \^not_strict_mode.app_rd_data_reg[322]\;
  \not_strict_mode.app_rd_data_reg[323]\ <= \^not_strict_mode.app_rd_data_reg[323]\;
  \not_strict_mode.app_rd_data_reg[324]\ <= \^not_strict_mode.app_rd_data_reg[324]\;
  \not_strict_mode.app_rd_data_reg[325]\ <= \^not_strict_mode.app_rd_data_reg[325]\;
  \not_strict_mode.app_rd_data_reg[326]\ <= \^not_strict_mode.app_rd_data_reg[326]\;
  \not_strict_mode.app_rd_data_reg[327]\ <= \^not_strict_mode.app_rd_data_reg[327]\;
  \not_strict_mode.app_rd_data_reg[384]\ <= \^not_strict_mode.app_rd_data_reg[384]\;
  \not_strict_mode.app_rd_data_reg[385]\ <= \^not_strict_mode.app_rd_data_reg[385]\;
  \not_strict_mode.app_rd_data_reg[386]\ <= \^not_strict_mode.app_rd_data_reg[386]\;
  \not_strict_mode.app_rd_data_reg[387]\ <= \^not_strict_mode.app_rd_data_reg[387]\;
  \not_strict_mode.app_rd_data_reg[388]\ <= \^not_strict_mode.app_rd_data_reg[388]\;
  \not_strict_mode.app_rd_data_reg[389]\ <= \^not_strict_mode.app_rd_data_reg[389]\;
  \not_strict_mode.app_rd_data_reg[390]\ <= \^not_strict_mode.app_rd_data_reg[390]\;
  \not_strict_mode.app_rd_data_reg[391]\ <= \^not_strict_mode.app_rd_data_reg[391]\;
  \not_strict_mode.app_rd_data_reg[3]\ <= \^not_strict_mode.app_rd_data_reg[3]\;
  \not_strict_mode.app_rd_data_reg[448]\ <= \^not_strict_mode.app_rd_data_reg[448]\;
  \not_strict_mode.app_rd_data_reg[449]\ <= \^not_strict_mode.app_rd_data_reg[449]\;
  \not_strict_mode.app_rd_data_reg[450]\ <= \^not_strict_mode.app_rd_data_reg[450]\;
  \not_strict_mode.app_rd_data_reg[451]\ <= \^not_strict_mode.app_rd_data_reg[451]\;
  \not_strict_mode.app_rd_data_reg[452]\ <= \^not_strict_mode.app_rd_data_reg[452]\;
  \not_strict_mode.app_rd_data_reg[453]\ <= \^not_strict_mode.app_rd_data_reg[453]\;
  \not_strict_mode.app_rd_data_reg[454]\ <= \^not_strict_mode.app_rd_data_reg[454]\;
  \not_strict_mode.app_rd_data_reg[455]_0\ <= \^not_strict_mode.app_rd_data_reg[455]_0\;
  \not_strict_mode.app_rd_data_reg[4]\ <= \^not_strict_mode.app_rd_data_reg[4]\;
  \not_strict_mode.app_rd_data_reg[5]\ <= \^not_strict_mode.app_rd_data_reg[5]\;
  \not_strict_mode.app_rd_data_reg[64]\ <= \^not_strict_mode.app_rd_data_reg[64]\;
  \not_strict_mode.app_rd_data_reg[65]\ <= \^not_strict_mode.app_rd_data_reg[65]\;
  \not_strict_mode.app_rd_data_reg[66]\ <= \^not_strict_mode.app_rd_data_reg[66]\;
  \not_strict_mode.app_rd_data_reg[67]\ <= \^not_strict_mode.app_rd_data_reg[67]\;
  \not_strict_mode.app_rd_data_reg[68]\ <= \^not_strict_mode.app_rd_data_reg[68]\;
  \not_strict_mode.app_rd_data_reg[69]\ <= \^not_strict_mode.app_rd_data_reg[69]\;
  \not_strict_mode.app_rd_data_reg[6]\ <= \^not_strict_mode.app_rd_data_reg[6]\;
  \not_strict_mode.app_rd_data_reg[70]\ <= \^not_strict_mode.app_rd_data_reg[70]\;
  \not_strict_mode.app_rd_data_reg[71]\ <= \^not_strict_mode.app_rd_data_reg[71]\;
  \not_strict_mode.app_rd_data_reg[7]\ <= \^not_strict_mode.app_rd_data_reg[7]\;
\i___84_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_empty(0),
      I2 => if_empty_r(0),
      I3 => Q(0),
      O => rd_active_r_reg
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(7 downto 6),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(9 downto 8),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(13 downto 12),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(15 downto 14),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(19 downto 18),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(21 downto 20),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(25 downto 24),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(27 downto 26),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(31 downto 30),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(33 downto 32),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(37 downto 36),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(39 downto 38),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(43 downto 42),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(45 downto 44),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(49 downto 48),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(51 downto 50),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(55 downto 54),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(57 downto 56),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(61 downto 60),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(63 downto 62),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(3 downto 2),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_6_11_n_0,
      DOA(0) => mem_reg_0_3_6_11_n_1,
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_3_6_11_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_full(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(2),
      O => wr_en
    );
\my_empty[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__3_n_0\,
      I3 => \my_empty[4]_i_3__5_n_0\,
      I4 => \my_empty[4]_i_4__2_n_0\,
      I5 => my_empty(0),
      O => \my_empty[0]_i_1__3_n_0\
    );
\my_empty[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0400"
    )
        port map (
      I0 => \my_empty[1]_i_2__3_n_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => my_full(1),
      I3 => if_empty_r_0(0),
      I4 => my_empty(1),
      O => \my_empty[1]_i_1__3_n_0\
    );
\my_empty[1]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBEEBFF"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[1]_i_2__3_n_0\
    );
\my_empty[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__3_n_0\,
      I3 => \my_empty[4]_i_3__5_n_0\,
      I4 => \my_empty[4]_i_4__2_n_0\,
      I5 => my_empty(2),
      O => \my_empty[2]_i_1__3_n_0\
    );
\my_empty[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__3_n_0\,
      I3 => \my_empty[4]_i_3__5_n_0\,
      I4 => \my_empty[4]_i_4__2_n_0\,
      I5 => my_empty(3),
      O => \my_empty[3]_i_1__3_n_0\
    );
\my_empty[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00003003AAAAAAAA"
    )
        port map (
      I0 => my_empty(4),
      I1 => my_empty(1),
      I2 => wr_ptr(1),
      I3 => \my_empty[4]_i_2__3_n_0\,
      I4 => \my_empty[4]_i_3__5_n_0\,
      I5 => \my_empty[4]_i_4__2_n_0\,
      O => \my_empty[4]_i_1__3_n_0\
    );
\my_empty[4]_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \my_empty[4]_i_2__3_n_0\
    );
\my_empty[4]_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => wr_ptr(0),
      O => \my_empty[4]_i_3__5_n_0\
    );
\my_empty[4]_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => if_empty_r_0(0),
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_4__2_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[0]_i_1__3_n_0\,
      Q => my_empty(0),
      S => SR(0)
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__3_n_0\,
      Q => my_empty(1),
      S => SR(0)
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[2]_i_1__3_n_0\,
      Q => my_empty(2),
      S => SR(0)
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[3]_i_1__3_n_0\,
      Q => my_empty(3),
      S => SR(0)
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__3_n_0\,
      Q => my_empty(4),
      S => SR(0)
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__3_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => SR(0)
    );
\my_full[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => if_empty_r_0(0),
      I3 => my_full(1),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I5 => \my_full[0]_i_2__3_n_0\,
      O => \my_full[0]_i_1__3_n_0\
    );
\my_full[0]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[0]_i_2__3_n_0\
    );
\my_full[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888988989988888"
    )
        port map (
      I0 => \my_full[1]_i_2__3_n_0\,
      I1 => my_full(1),
      I2 => rd_ptr(1),
      I3 => wr_ptr(1),
      I4 => wr_ptr(0),
      I5 => rd_ptr(0),
      O => \my_full[1]_i_1__3_n_0\
    );
\my_full[1]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => if_empty_r_0(0),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      O => \my_full[1]_i_2__3_n_0\
    );
\my_full[1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => if_empty_r_0(0),
      I1 => my_empty(3),
      O => \rd_ptr_reg[1]_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[0]_i_1__3_n_0\,
      Q => my_full(0),
      R => SR(0)
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[1]_i_1__3_n_0\,
      Q => my_full(1),
      R => SR(0)
    );
\not_strict_mode.app_rd_data[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[0]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => DOC(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(0)
    );
\not_strict_mode.app_rd_data[128]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[128]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(16)
    );
\not_strict_mode.app_rd_data[129]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[129]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(17)
    );
\not_strict_mode.app_rd_data[130]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[130]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(18)
    );
\not_strict_mode.app_rd_data[131]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[131]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(19)
    );
\not_strict_mode.app_rd_data[132]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[132]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(20)
    );
\not_strict_mode.app_rd_data[133]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[133]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(21)
    );
\not_strict_mode.app_rd_data[134]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[134]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(22)
    );
\not_strict_mode.app_rd_data[135]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[135]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(23)
    );
\not_strict_mode.app_rd_data[192]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[192]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(24)
    );
\not_strict_mode.app_rd_data[193]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[193]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(25)
    );
\not_strict_mode.app_rd_data[194]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[194]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(26)
    );
\not_strict_mode.app_rd_data[195]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[195]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(27)
    );
\not_strict_mode.app_rd_data[196]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[196]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(28)
    );
\not_strict_mode.app_rd_data[197]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[197]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(29)
    );
\not_strict_mode.app_rd_data[198]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[198]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(30)
    );
\not_strict_mode.app_rd_data[199]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[199]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(31)
    );
\not_strict_mode.app_rd_data[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[1]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => DOC(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(1)
    );
\not_strict_mode.app_rd_data[256]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[256]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(32)
    );
\not_strict_mode.app_rd_data[257]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[257]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(33)
    );
\not_strict_mode.app_rd_data[258]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[258]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(34)
    );
\not_strict_mode.app_rd_data[259]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[259]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(35)
    );
\not_strict_mode.app_rd_data[260]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[260]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(36)
    );
\not_strict_mode.app_rd_data[261]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[261]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(37)
    );
\not_strict_mode.app_rd_data[262]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[262]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(38)
    );
\not_strict_mode.app_rd_data[263]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[263]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(39)
    );
\not_strict_mode.app_rd_data[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[2]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => DOB(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(2)
    );
\not_strict_mode.app_rd_data[320]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[320]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(40)
    );
\not_strict_mode.app_rd_data[321]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[321]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(41)
    );
\not_strict_mode.app_rd_data[322]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[322]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(42)
    );
\not_strict_mode.app_rd_data[323]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[323]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(43)
    );
\not_strict_mode.app_rd_data[324]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[324]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(44)
    );
\not_strict_mode.app_rd_data[325]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[325]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(45)
    );
\not_strict_mode.app_rd_data[326]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[326]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(46)
    );
\not_strict_mode.app_rd_data[327]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[327]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(47)
    );
\not_strict_mode.app_rd_data[384]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[384]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(48)
    );
\not_strict_mode.app_rd_data[385]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[385]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(49)
    );
\not_strict_mode.app_rd_data[386]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[386]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(50)
    );
\not_strict_mode.app_rd_data[387]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[387]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(51)
    );
\not_strict_mode.app_rd_data[388]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[388]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(52)
    );
\not_strict_mode.app_rd_data[389]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[389]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(53)
    );
\not_strict_mode.app_rd_data[390]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[390]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(54)
    );
\not_strict_mode.app_rd_data[391]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[391]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(55)
    );
\not_strict_mode.app_rd_data[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[3]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => DOB(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(3)
    );
\not_strict_mode.app_rd_data[448]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[448]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(56)
    );
\not_strict_mode.app_rd_data[449]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[449]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(57)
    );
\not_strict_mode.app_rd_data[450]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[450]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(58)
    );
\not_strict_mode.app_rd_data[451]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[451]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(59)
    );
\not_strict_mode.app_rd_data[452]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[452]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(60)
    );
\not_strict_mode.app_rd_data[453]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[453]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(61)
    );
\not_strict_mode.app_rd_data[454]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[454]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(62)
    );
\not_strict_mode.app_rd_data[455]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[455]_0\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(63)
    );
\not_strict_mode.app_rd_data[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[4]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => DOA(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(4)
    );
\not_strict_mode.app_rd_data[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[5]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => DOA(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(5)
    );
\not_strict_mode.app_rd_data[64]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[64]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(8)
    );
\not_strict_mode.app_rd_data[65]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[65]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(9)
    );
\not_strict_mode.app_rd_data[66]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[66]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(10)
    );
\not_strict_mode.app_rd_data[67]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[67]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(11)
    );
\not_strict_mode.app_rd_data[68]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[68]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(12)
    );
\not_strict_mode.app_rd_data[69]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[69]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(13)
    );
\not_strict_mode.app_rd_data[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[6]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(6)
    );
\not_strict_mode.app_rd_data[70]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[70]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[455]\(14)
    );
\not_strict_mode.app_rd_data[71]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[71]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(15)
    );
\not_strict_mode.app_rd_data[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[7]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[455]\(7)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(18),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(24),
      O => \^not_strict_mode.app_rd_data_reg[5]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(26),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(32),
      O => \^not_strict_mode.app_rd_data_reg[4]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(34),
      I1 => my_empty(4),
      I2 => mem_out(40),
      O => \^not_strict_mode.app_rd_data_reg[3]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(42),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \^not_strict_mode.app_rd_data_reg[2]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(50),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \^not_strict_mode.app_rd_data_reg[1]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(58),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \^not_strict_mode.app_rd_data_reg[0]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(51),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \^not_strict_mode.app_rd_data_reg[65]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(59),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \^not_strict_mode.app_rd_data_reg[64]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(3),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(9),
      O => \^not_strict_mode.app_rd_data_reg[71]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(11),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(17),
      O => \^not_strict_mode.app_rd_data_reg[70]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(19),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(25),
      O => \^not_strict_mode.app_rd_data_reg[69]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(27),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(33),
      O => \^not_strict_mode.app_rd_data_reg[68]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(35),
      I1 => my_empty(4),
      I2 => mem_out(41),
      O => \^not_strict_mode.app_rd_data_reg[67]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(43),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \^not_strict_mode.app_rd_data_reg[66]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(2),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(8),
      O => \^not_strict_mode.app_rd_data_reg[7]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(10),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(16),
      O => \^not_strict_mode.app_rd_data_reg[6]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(36),
      I1 => my_empty(4),
      I2 => mem_out(42),
      O => \^not_strict_mode.app_rd_data_reg[131]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(44),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \^not_strict_mode.app_rd_data_reg[130]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(52),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \^not_strict_mode.app_rd_data_reg[129]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(60),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \^not_strict_mode.app_rd_data_reg[128]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(4),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(10),
      O => \^not_strict_mode.app_rd_data_reg[135]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(12),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(18),
      O => \^not_strict_mode.app_rd_data_reg[134]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(20),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(26),
      O => \^not_strict_mode.app_rd_data_reg[133]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(28),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(34),
      O => \^not_strict_mode.app_rd_data_reg[132]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(21),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(27),
      O => \^not_strict_mode.app_rd_data_reg[197]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(29),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(35),
      O => \^not_strict_mode.app_rd_data_reg[196]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(37),
      I1 => my_empty(4),
      I2 => mem_out(43),
      O => \^not_strict_mode.app_rd_data_reg[195]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(45),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \^not_strict_mode.app_rd_data_reg[194]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(53),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \^not_strict_mode.app_rd_data_reg[193]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(61),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \^not_strict_mode.app_rd_data_reg[192]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(5),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(11),
      O => \^not_strict_mode.app_rd_data_reg[199]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(13),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(19),
      O => \^not_strict_mode.app_rd_data_reg[198]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(54),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \^not_strict_mode.app_rd_data_reg[257]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(62),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \^not_strict_mode.app_rd_data_reg[256]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(6),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(12),
      O => \^not_strict_mode.app_rd_data_reg[263]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(14),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(20),
      O => \^not_strict_mode.app_rd_data_reg[262]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(22),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(28),
      O => \^not_strict_mode.app_rd_data_reg[261]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(30),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(36),
      O => \^not_strict_mode.app_rd_data_reg[260]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(38),
      I1 => my_empty(4),
      I2 => mem_out(44),
      O => \^not_strict_mode.app_rd_data_reg[259]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(46),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \^not_strict_mode.app_rd_data_reg[258]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(39),
      I1 => my_empty(4),
      I2 => mem_out(45),
      O => \^not_strict_mode.app_rd_data_reg[323]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(47),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \^not_strict_mode.app_rd_data_reg[322]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(55),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \^not_strict_mode.app_rd_data_reg[321]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(63),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \^not_strict_mode.app_rd_data_reg[320]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(7),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(13),
      O => \^not_strict_mode.app_rd_data_reg[327]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(15),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(21),
      O => \^not_strict_mode.app_rd_data_reg[326]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(23),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(29),
      O => \^not_strict_mode.app_rd_data_reg[325]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(31),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(37),
      O => \^not_strict_mode.app_rd_data_reg[324]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(24),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(30),
      O => \^not_strict_mode.app_rd_data_reg[389]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(32),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(38),
      O => \^not_strict_mode.app_rd_data_reg[388]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(40),
      I1 => my_empty(4),
      I2 => mem_out(46),
      O => \^not_strict_mode.app_rd_data_reg[387]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(48),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \^not_strict_mode.app_rd_data_reg[386]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(56),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \^not_strict_mode.app_rd_data_reg[385]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(64),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \^not_strict_mode.app_rd_data_reg[384]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(8),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(14),
      O => \^not_strict_mode.app_rd_data_reg[391]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(16),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(22),
      O => \^not_strict_mode.app_rd_data_reg[390]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(57),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \^not_strict_mode.app_rd_data_reg[449]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \^not_strict_mode.app_rd_data_reg[448]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(9),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(15),
      O => \^not_strict_mode.app_rd_data_reg[455]_0\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(17),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(23),
      O => \^not_strict_mode.app_rd_data_reg[454]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(25),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(31),
      O => \^not_strict_mode.app_rd_data_reg[453]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(33),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(39),
      O => \^not_strict_mode.app_rd_data_reg[452]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(41),
      I1 => my_empty(4),
      I2 => mem_out(47),
      O => \^not_strict_mode.app_rd_data_reg[451]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(49),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \^not_strict_mode.app_rd_data_reg[450]\
    );
\rd_ptr[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__2_n_0\
    );
\rd_ptr[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__2_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1__2_n_0\,
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1__2_n_0\,
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1__17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF02"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__17_n_0\
    );
\rd_ptr_timing[1]_i_1__17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFD0220"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__17_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__17_n_0\,
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__17_n_0\,
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr[0]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFCA0035"
    )
        port map (
      I0 => my_full(1),
      I1 => my_empty(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => if_empty_r_0(0),
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__10_n_0\
    );
\wr_ptr[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => C_byte_rd_en,
      I1 => byte_rd_en_v_1,
      I2 => \wr_ptr[0]_i_4_n_0\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      I5 => \my_empty_reg[3]_0\,
      O => \rd_ptr_timing_reg[0]_0\
    );
\wr_ptr[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => A_byte_rd_en,
      I1 => byte_rd_en_v_1,
      I2 => \wr_ptr[0]_i_4_n_0\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      I5 => \my_empty_reg[3]_1\,
      O => \rd_ptr_timing_reg[0]_1\
    );
\wr_ptr[0]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => B_byte_rd_en,
      I1 => byte_rd_en_v_1,
      I2 => \wr_ptr[0]_i_4_n_0\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      I5 => \my_empty_reg[3]_2\,
      O => \rd_ptr_timing_reg[0]_2\
    );
\wr_ptr[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => my_empty(3),
      I1 => if_empty_r_0(0),
      I2 => Q(1),
      I3 => if_empty_r(0),
      O => \wr_ptr[0]_i_4_n_0\
    );
\wr_ptr[1]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF5DD00000A22"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => my_empty(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => if_empty_r_0(0),
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__10_n_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__10_n_0\,
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__10_n_0\,
      Q => wr_ptr(1),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_23 is
  port (
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[8]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[10]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[12]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[14]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[72]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[74]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[76]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[78]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[136]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[138]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[140]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[142]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[200]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[202]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[204]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[206]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[264]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[266]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[268]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[270]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[328]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[330]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[332]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[334]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[392]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[394]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[396]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[398]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[456]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[458]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[460]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[462]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    rd_active_r_reg : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : in STD_LOGIC_VECTOR ( 65 downto 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_23 : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_23;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_23 is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mem_out : STD_LOGIC_VECTOR ( 71 downto 8 );
  signal mem_reg_0_3_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_1 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \my_empty[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_4__1_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[10]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[11]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[12]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[136]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[137]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[138]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[139]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[13]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[140]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[141]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[142]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[143]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[14]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[15]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[200]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[201]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[202]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[203]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[204]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[205]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[206]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[207]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[264]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[265]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[266]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[267]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[268]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[269]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[270]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[271]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[328]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[329]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[330]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[331]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[332]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[333]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[334]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[335]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[392]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[393]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[394]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[395]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[396]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[397]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[398]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[399]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[456]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[457]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[458]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[459]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[460]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[461]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[462]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[463]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[72]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[73]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[74]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[75]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[76]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[77]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[78]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[79]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[8]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[9]\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__1_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__16_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__16_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__8_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i___84_i_3\ : label is "soft_lutpair573";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute SOFT_HLUTNM of \my_empty[1]_i_1__2\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \my_empty[1]_i_2__2\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \my_empty[4]_i_2__2\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \my_empty[4]_i_3__4\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \my_empty[4]_i_4__1\ : label is "soft_lutpair568";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[0]_i_2__2\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \my_full[1]_i_2__2\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[10]_i_1\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[11]_i_1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[12]_i_1\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[136]_i_1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[137]_i_1\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[138]_i_1\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[139]_i_1\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[13]_i_1\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[140]_i_1\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[141]_i_1\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[142]_i_1\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[143]_i_1\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[14]_i_1\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[15]_i_1\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[200]_i_1\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[201]_i_1\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[202]_i_1\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[203]_i_1\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[204]_i_1\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[205]_i_1\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[206]_i_1\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[207]_i_1\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[264]_i_1\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[265]_i_1\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[266]_i_1\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[267]_i_1\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[268]_i_1\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[269]_i_1\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[270]_i_1\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[271]_i_1\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[328]_i_1\ : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[329]_i_1\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[330]_i_1\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[331]_i_1\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[332]_i_1\ : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[333]_i_1\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[334]_i_1\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[335]_i_1\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[392]_i_1\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[393]_i_1\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[394]_i_1\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[395]_i_1\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[396]_i_1\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[397]_i_1\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[398]_i_1\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[399]_i_1\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[456]_i_1\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[457]_i_1\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[458]_i_1\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[459]_i_1\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[460]_i_1\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[461]_i_1\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[462]_i_1\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[463]_i_1\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[72]_i_1\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[73]_i_1\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[74]_i_1\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[75]_i_1\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[76]_i_1\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[77]_i_1\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[78]_i_1\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[79]_i_1\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[8]_i_1\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[9]_i_1\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__1\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__1\ : label is "soft_lutpair572";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__8\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_5\ : label is "soft_lutpair573";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  Q(0) <= \^q\(0);
  \not_strict_mode.app_rd_data_reg[10]\ <= \^not_strict_mode.app_rd_data_reg[10]\;
  \not_strict_mode.app_rd_data_reg[11]\ <= \^not_strict_mode.app_rd_data_reg[11]\;
  \not_strict_mode.app_rd_data_reg[12]\ <= \^not_strict_mode.app_rd_data_reg[12]\;
  \not_strict_mode.app_rd_data_reg[136]\ <= \^not_strict_mode.app_rd_data_reg[136]\;
  \not_strict_mode.app_rd_data_reg[137]\ <= \^not_strict_mode.app_rd_data_reg[137]\;
  \not_strict_mode.app_rd_data_reg[138]\ <= \^not_strict_mode.app_rd_data_reg[138]\;
  \not_strict_mode.app_rd_data_reg[139]\ <= \^not_strict_mode.app_rd_data_reg[139]\;
  \not_strict_mode.app_rd_data_reg[13]\ <= \^not_strict_mode.app_rd_data_reg[13]\;
  \not_strict_mode.app_rd_data_reg[140]\ <= \^not_strict_mode.app_rd_data_reg[140]\;
  \not_strict_mode.app_rd_data_reg[141]\ <= \^not_strict_mode.app_rd_data_reg[141]\;
  \not_strict_mode.app_rd_data_reg[142]\ <= \^not_strict_mode.app_rd_data_reg[142]\;
  \not_strict_mode.app_rd_data_reg[143]\ <= \^not_strict_mode.app_rd_data_reg[143]\;
  \not_strict_mode.app_rd_data_reg[14]\ <= \^not_strict_mode.app_rd_data_reg[14]\;
  \not_strict_mode.app_rd_data_reg[15]\ <= \^not_strict_mode.app_rd_data_reg[15]\;
  \not_strict_mode.app_rd_data_reg[200]\ <= \^not_strict_mode.app_rd_data_reg[200]\;
  \not_strict_mode.app_rd_data_reg[201]\ <= \^not_strict_mode.app_rd_data_reg[201]\;
  \not_strict_mode.app_rd_data_reg[202]\ <= \^not_strict_mode.app_rd_data_reg[202]\;
  \not_strict_mode.app_rd_data_reg[203]\ <= \^not_strict_mode.app_rd_data_reg[203]\;
  \not_strict_mode.app_rd_data_reg[204]\ <= \^not_strict_mode.app_rd_data_reg[204]\;
  \not_strict_mode.app_rd_data_reg[205]\ <= \^not_strict_mode.app_rd_data_reg[205]\;
  \not_strict_mode.app_rd_data_reg[206]\ <= \^not_strict_mode.app_rd_data_reg[206]\;
  \not_strict_mode.app_rd_data_reg[207]\ <= \^not_strict_mode.app_rd_data_reg[207]\;
  \not_strict_mode.app_rd_data_reg[264]\ <= \^not_strict_mode.app_rd_data_reg[264]\;
  \not_strict_mode.app_rd_data_reg[265]\ <= \^not_strict_mode.app_rd_data_reg[265]\;
  \not_strict_mode.app_rd_data_reg[266]\ <= \^not_strict_mode.app_rd_data_reg[266]\;
  \not_strict_mode.app_rd_data_reg[267]\ <= \^not_strict_mode.app_rd_data_reg[267]\;
  \not_strict_mode.app_rd_data_reg[268]\ <= \^not_strict_mode.app_rd_data_reg[268]\;
  \not_strict_mode.app_rd_data_reg[269]\ <= \^not_strict_mode.app_rd_data_reg[269]\;
  \not_strict_mode.app_rd_data_reg[270]\ <= \^not_strict_mode.app_rd_data_reg[270]\;
  \not_strict_mode.app_rd_data_reg[271]\ <= \^not_strict_mode.app_rd_data_reg[271]\;
  \not_strict_mode.app_rd_data_reg[328]\ <= \^not_strict_mode.app_rd_data_reg[328]\;
  \not_strict_mode.app_rd_data_reg[329]\ <= \^not_strict_mode.app_rd_data_reg[329]\;
  \not_strict_mode.app_rd_data_reg[330]\ <= \^not_strict_mode.app_rd_data_reg[330]\;
  \not_strict_mode.app_rd_data_reg[331]\ <= \^not_strict_mode.app_rd_data_reg[331]\;
  \not_strict_mode.app_rd_data_reg[332]\ <= \^not_strict_mode.app_rd_data_reg[332]\;
  \not_strict_mode.app_rd_data_reg[333]\ <= \^not_strict_mode.app_rd_data_reg[333]\;
  \not_strict_mode.app_rd_data_reg[334]\ <= \^not_strict_mode.app_rd_data_reg[334]\;
  \not_strict_mode.app_rd_data_reg[335]\ <= \^not_strict_mode.app_rd_data_reg[335]\;
  \not_strict_mode.app_rd_data_reg[392]\ <= \^not_strict_mode.app_rd_data_reg[392]\;
  \not_strict_mode.app_rd_data_reg[393]\ <= \^not_strict_mode.app_rd_data_reg[393]\;
  \not_strict_mode.app_rd_data_reg[394]\ <= \^not_strict_mode.app_rd_data_reg[394]\;
  \not_strict_mode.app_rd_data_reg[395]\ <= \^not_strict_mode.app_rd_data_reg[395]\;
  \not_strict_mode.app_rd_data_reg[396]\ <= \^not_strict_mode.app_rd_data_reg[396]\;
  \not_strict_mode.app_rd_data_reg[397]\ <= \^not_strict_mode.app_rd_data_reg[397]\;
  \not_strict_mode.app_rd_data_reg[398]\ <= \^not_strict_mode.app_rd_data_reg[398]\;
  \not_strict_mode.app_rd_data_reg[399]\ <= \^not_strict_mode.app_rd_data_reg[399]\;
  \not_strict_mode.app_rd_data_reg[456]\ <= \^not_strict_mode.app_rd_data_reg[456]\;
  \not_strict_mode.app_rd_data_reg[457]\ <= \^not_strict_mode.app_rd_data_reg[457]\;
  \not_strict_mode.app_rd_data_reg[458]\ <= \^not_strict_mode.app_rd_data_reg[458]\;
  \not_strict_mode.app_rd_data_reg[459]\ <= \^not_strict_mode.app_rd_data_reg[459]\;
  \not_strict_mode.app_rd_data_reg[460]\ <= \^not_strict_mode.app_rd_data_reg[460]\;
  \not_strict_mode.app_rd_data_reg[461]\ <= \^not_strict_mode.app_rd_data_reg[461]\;
  \not_strict_mode.app_rd_data_reg[462]\ <= \^not_strict_mode.app_rd_data_reg[462]\;
  \not_strict_mode.app_rd_data_reg[463]\ <= \^not_strict_mode.app_rd_data_reg[463]\;
  \not_strict_mode.app_rd_data_reg[72]\ <= \^not_strict_mode.app_rd_data_reg[72]\;
  \not_strict_mode.app_rd_data_reg[73]\ <= \^not_strict_mode.app_rd_data_reg[73]\;
  \not_strict_mode.app_rd_data_reg[74]\ <= \^not_strict_mode.app_rd_data_reg[74]\;
  \not_strict_mode.app_rd_data_reg[75]\ <= \^not_strict_mode.app_rd_data_reg[75]\;
  \not_strict_mode.app_rd_data_reg[76]\ <= \^not_strict_mode.app_rd_data_reg[76]\;
  \not_strict_mode.app_rd_data_reg[77]\ <= \^not_strict_mode.app_rd_data_reg[77]\;
  \not_strict_mode.app_rd_data_reg[78]\ <= \^not_strict_mode.app_rd_data_reg[78]\;
  \not_strict_mode.app_rd_data_reg[79]\ <= \^not_strict_mode.app_rd_data_reg[79]\;
  \not_strict_mode.app_rd_data_reg[8]\ <= \^not_strict_mode.app_rd_data_reg[8]\;
  \not_strict_mode.app_rd_data_reg[9]\ <= \^not_strict_mode.app_rd_data_reg[9]\;
\gen_mux_rd[0].mux_rd_fall0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[72]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      O => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_fall1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[200]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      O => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_fall2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[328]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      O => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_fall3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[456]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      O => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_rise0_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[8]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      O => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_rise1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[136]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      O => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_rise2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[264]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      O => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\
    );
\gen_mux_rd[0].mux_rd_rise3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[392]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      O => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\
    );
\gen_mux_rd[1].mux_rd_fall0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[73]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      O => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\
    );
\gen_mux_rd[1].mux_rd_fall1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[201]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      O => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\
    );
\gen_mux_rd[1].mux_rd_fall2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[329]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      O => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\
    );
\gen_mux_rd[1].mux_rd_fall3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[457]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      O => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\
    );
\gen_mux_rd[1].mux_rd_rise0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[9]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      O => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\
    );
\gen_mux_rd[1].mux_rd_rise1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[137]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      O => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\
    );
\gen_mux_rd[1].mux_rd_rise2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[265]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      O => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\
    );
\gen_mux_rd[1].mux_rd_rise3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[393]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      O => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\
    );
\gen_mux_rd[2].mux_rd_fall0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[74]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      O => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_fall1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[202]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      O => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_fall2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[330]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      O => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_fall3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[458]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      O => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[10]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      O => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[138]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      O => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[266]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      O => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\
    );
\gen_mux_rd[2].mux_rd_rise3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[394]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      O => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\
    );
\gen_mux_rd[3].mux_rd_fall0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[75]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      O => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\
    );
\gen_mux_rd[3].mux_rd_fall1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[203]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      O => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\
    );
\gen_mux_rd[3].mux_rd_fall2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[331]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      O => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\
    );
\gen_mux_rd[3].mux_rd_fall3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[459]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      O => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\
    );
\gen_mux_rd[3].mux_rd_rise0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[11]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      O => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\
    );
\gen_mux_rd[3].mux_rd_rise1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[139]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      O => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\
    );
\gen_mux_rd[3].mux_rd_rise2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[267]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      O => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\
    );
\gen_mux_rd[3].mux_rd_rise3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[395]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      O => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\
    );
\gen_mux_rd[4].mux_rd_fall0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[76]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      O => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\
    );
\gen_mux_rd[4].mux_rd_fall1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[204]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      O => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\
    );
\gen_mux_rd[4].mux_rd_fall2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[332]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      O => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\
    );
\gen_mux_rd[4].mux_rd_fall3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[460]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      O => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\
    );
\gen_mux_rd[4].mux_rd_rise0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[12]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      O => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\
    );
\gen_mux_rd[4].mux_rd_rise1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[140]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      O => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\
    );
\gen_mux_rd[4].mux_rd_rise2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[268]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      O => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\
    );
\gen_mux_rd[4].mux_rd_rise3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[396]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      O => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\
    );
\gen_mux_rd[5].mux_rd_fall0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[77]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      O => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_fall1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[205]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      O => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_fall2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[333]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      O => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_fall3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[461]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      O => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_rise0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[13]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      O => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_rise1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[141]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      O => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_rise2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[269]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      O => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\
    );
\gen_mux_rd[5].mux_rd_rise3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[397]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      O => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\
    );
\gen_mux_rd[6].mux_rd_fall0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[78]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      O => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_fall1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[206]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      O => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_fall2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[334]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      O => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_fall3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[462]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      O => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_rise0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[14]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      O => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_rise1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[142]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      O => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_rise2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[270]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      O => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\
    );
\gen_mux_rd[6].mux_rd_rise3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[398]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      O => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\
    );
\gen_mux_rd[7].mux_rd_fall0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[79]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      O => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\
    );
\gen_mux_rd[7].mux_rd_fall1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[207]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      O => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\
    );
\gen_mux_rd[7].mux_rd_fall2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[335]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      O => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\
    );
\gen_mux_rd[7].mux_rd_fall3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[463]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      O => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\
    );
\gen_mux_rd[7].mux_rd_rise0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[15]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      O => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\
    );
\gen_mux_rd[7].mux_rd_rise1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[143]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      O => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\
    );
\gen_mux_rd[7].mux_rd_rise2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[271]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      O => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\
    );
\gen_mux_rd[7].mux_rd_rise3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBD97351EAC86240"
    )
        port map (
      I0 => \rd_mux_sel_r_reg[1]\(1),
      I1 => \rd_mux_sel_r_reg[1]\(0),
      I2 => \^not_strict_mode.app_rd_data_reg[399]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      O => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\
    );
\i___84_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => my_empty(0),
      I2 => if_empty_r_0(0),
      I3 => \my_empty_reg[0]_0\(0),
      O => rd_active_r_reg
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(7 downto 6),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(9 downto 8),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(13 downto 12),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(15 downto 14),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(19 downto 18),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(21 downto 20),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(25 downto 24),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(27 downto 26),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(31 downto 30),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(33 downto 32),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(37 downto 36),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(39 downto 38),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(43 downto 42),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(45 downto 44),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(49 downto 48),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(51 downto 50),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(55 downto 54),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(57 downto 56),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(61 downto 60),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(63 downto 62),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(3 downto 2),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_6_11_n_0,
      DOA(0) => mem_reg_0_3_6_11_n_1,
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_3_6_11_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => my_full(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(2),
      O => wr_en
    );
\my_empty[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__2_n_0\,
      I3 => \my_empty[4]_i_3__4_n_0\,
      I4 => \my_empty[4]_i_4__1_n_0\,
      I5 => my_empty(0),
      O => \my_empty[0]_i_1__2_n_0\
    );
\my_empty[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0400"
    )
        port map (
      I0 => \my_empty[1]_i_2__2_n_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => my_empty(1),
      O => \my_empty[1]_i_1__2_n_0\
    );
\my_empty[1]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBEEBFF"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[1]_i_2__2_n_0\
    );
\my_empty[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__2_n_0\,
      I3 => \my_empty[4]_i_3__4_n_0\,
      I4 => \my_empty[4]_i_4__1_n_0\,
      I5 => my_empty(2),
      O => \my_empty[2]_i_1__2_n_0\
    );
\my_empty[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__2_n_0\,
      I3 => \my_empty[4]_i_3__4_n_0\,
      I4 => \my_empty[4]_i_4__1_n_0\,
      I5 => \^q\(0),
      O => \my_empty[3]_i_1__2_n_0\
    );
\my_empty[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00003003AAAAAAAA"
    )
        port map (
      I0 => my_empty(4),
      I1 => my_empty(1),
      I2 => wr_ptr(1),
      I3 => \my_empty[4]_i_2__2_n_0\,
      I4 => \my_empty[4]_i_3__4_n_0\,
      I5 => \my_empty[4]_i_4__1_n_0\,
      O => \my_empty[4]_i_1__2_n_0\
    );
\my_empty[4]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \my_empty[4]_i_2__2_n_0\
    );
\my_empty[4]_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => wr_ptr(0),
      O => \my_empty[4]_i_3__4_n_0\
    );
\my_empty[4]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_4__1_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[0]_i_1__2_n_0\,
      Q => my_empty(0),
      S => SR(0)
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__2_n_0\,
      Q => my_empty(1),
      S => SR(0)
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[2]_i_1__2_n_0\,
      Q => my_empty(2),
      S => SR(0)
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[3]_i_1__2_n_0\,
      Q => \^q\(0),
      S => SR(0)
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__2_n_0\,
      Q => my_empty(4),
      S => SR(0)
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__2_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => SR(0)
    );
\my_full[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_full(1),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I5 => \my_full[0]_i_2__2_n_0\,
      O => \my_full[0]_i_1__2_n_0\
    );
\my_full[0]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[0]_i_2__2_n_0\
    );
\my_full[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888988989988888"
    )
        port map (
      I0 => \my_full[1]_i_2__2_n_0\,
      I1 => my_full(1),
      I2 => rd_ptr(1),
      I3 => wr_ptr(1),
      I4 => wr_ptr(0),
      I5 => rd_ptr(0),
      O => \my_full[1]_i_1__2_n_0\
    );
\my_full[1]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      O => \my_full[1]_i_2__2_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[0]_i_1__2_n_0\,
      Q => my_full(0),
      R => SR(0)
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[1]_i_1__2_n_0\,
      Q => my_full(1),
      R => SR(0)
    );
\not_strict_mode.app_rd_data[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[10]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(2)
    );
\not_strict_mode.app_rd_data[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[11]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(3)
    );
\not_strict_mode.app_rd_data[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[12]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(4)
    );
\not_strict_mode.app_rd_data[136]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[136]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(16)
    );
\not_strict_mode.app_rd_data[137]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[137]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(17)
    );
\not_strict_mode.app_rd_data[138]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[138]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(18)
    );
\not_strict_mode.app_rd_data[139]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[139]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(19)
    );
\not_strict_mode.app_rd_data[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[13]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(5)
    );
\not_strict_mode.app_rd_data[140]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[140]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(20)
    );
\not_strict_mode.app_rd_data[141]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[141]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(21)
    );
\not_strict_mode.app_rd_data[142]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[142]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(22)
    );
\not_strict_mode.app_rd_data[143]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[143]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(23)
    );
\not_strict_mode.app_rd_data[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[14]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(6)
    );
\not_strict_mode.app_rd_data[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[15]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(7)
    );
\not_strict_mode.app_rd_data[200]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[200]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(24)
    );
\not_strict_mode.app_rd_data[201]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[201]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(25)
    );
\not_strict_mode.app_rd_data[202]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[202]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(26)
    );
\not_strict_mode.app_rd_data[203]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[203]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(27)
    );
\not_strict_mode.app_rd_data[204]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[204]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(28)
    );
\not_strict_mode.app_rd_data[205]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[205]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(29)
    );
\not_strict_mode.app_rd_data[206]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[206]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(30)
    );
\not_strict_mode.app_rd_data[207]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[207]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(31)
    );
\not_strict_mode.app_rd_data[264]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[264]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(32)
    );
\not_strict_mode.app_rd_data[265]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[265]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(33)
    );
\not_strict_mode.app_rd_data[266]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[266]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(34)
    );
\not_strict_mode.app_rd_data[267]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[267]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(35)
    );
\not_strict_mode.app_rd_data[268]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[268]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(36)
    );
\not_strict_mode.app_rd_data[269]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[269]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(37)
    );
\not_strict_mode.app_rd_data[270]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[270]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(38)
    );
\not_strict_mode.app_rd_data[271]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[271]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(39)
    );
\not_strict_mode.app_rd_data[328]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[328]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(40)
    );
\not_strict_mode.app_rd_data[329]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[329]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(41)
    );
\not_strict_mode.app_rd_data[330]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[330]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(42)
    );
\not_strict_mode.app_rd_data[331]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[331]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(43)
    );
\not_strict_mode.app_rd_data[332]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[332]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(44)
    );
\not_strict_mode.app_rd_data[333]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[333]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(45)
    );
\not_strict_mode.app_rd_data[334]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[334]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(46)
    );
\not_strict_mode.app_rd_data[335]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[335]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(47)
    );
\not_strict_mode.app_rd_data[392]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[392]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(48)
    );
\not_strict_mode.app_rd_data[393]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[393]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(49)
    );
\not_strict_mode.app_rd_data[394]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[394]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(50)
    );
\not_strict_mode.app_rd_data[395]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[395]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(51)
    );
\not_strict_mode.app_rd_data[396]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[396]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(52)
    );
\not_strict_mode.app_rd_data[397]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[397]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(53)
    );
\not_strict_mode.app_rd_data[398]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[398]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(54)
    );
\not_strict_mode.app_rd_data[399]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[399]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(55)
    );
\not_strict_mode.app_rd_data[456]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[456]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(56)
    );
\not_strict_mode.app_rd_data[457]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[457]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(57)
    );
\not_strict_mode.app_rd_data[458]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[458]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(58)
    );
\not_strict_mode.app_rd_data[459]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[459]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(59)
    );
\not_strict_mode.app_rd_data[460]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[460]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(60)
    );
\not_strict_mode.app_rd_data[461]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[461]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(61)
    );
\not_strict_mode.app_rd_data[462]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[462]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(62)
    );
\not_strict_mode.app_rd_data[463]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[463]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(63)
    );
\not_strict_mode.app_rd_data[72]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[72]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(8)
    );
\not_strict_mode.app_rd_data[73]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[73]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(9)
    );
\not_strict_mode.app_rd_data[74]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[74]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(10)
    );
\not_strict_mode.app_rd_data[75]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[75]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(11)
    );
\not_strict_mode.app_rd_data[76]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[76]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(12)
    );
\not_strict_mode.app_rd_data[77]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[77]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(13)
    );
\not_strict_mode.app_rd_data[78]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[78]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(14)
    );
\not_strict_mode.app_rd_data[79]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[79]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(15)
    );
\not_strict_mode.app_rd_data[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[8]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(0)
    );
\not_strict_mode.app_rd_data[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[9]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[463]_0\(1)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(19),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(25),
      O => \^not_strict_mode.app_rd_data_reg[77]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(27),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(33),
      O => \^not_strict_mode.app_rd_data_reg[76]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(35),
      I1 => my_empty(4),
      I2 => mem_out(41),
      O => \^not_strict_mode.app_rd_data_reg[75]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(43),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \^not_strict_mode.app_rd_data_reg[74]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(51),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \^not_strict_mode.app_rd_data_reg[73]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(59),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \^not_strict_mode.app_rd_data_reg[72]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(3),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(9),
      O => \^not_strict_mode.app_rd_data_reg[79]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(11),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(17),
      O => \^not_strict_mode.app_rd_data_reg[78]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(34),
      I1 => my_empty(4),
      I2 => mem_out(40),
      O => \^not_strict_mode.app_rd_data_reg[11]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(42),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \^not_strict_mode.app_rd_data_reg[10]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(50),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \^not_strict_mode.app_rd_data_reg[9]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(58),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \^not_strict_mode.app_rd_data_reg[8]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(52),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \^not_strict_mode.app_rd_data_reg[137]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(60),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \^not_strict_mode.app_rd_data_reg[136]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(4),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(10),
      O => \^not_strict_mode.app_rd_data_reg[143]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(12),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(18),
      O => \^not_strict_mode.app_rd_data_reg[142]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(20),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(26),
      O => \^not_strict_mode.app_rd_data_reg[141]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(28),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(34),
      O => \^not_strict_mode.app_rd_data_reg[140]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(36),
      I1 => my_empty(4),
      I2 => mem_out(42),
      O => \^not_strict_mode.app_rd_data_reg[139]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(44),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \^not_strict_mode.app_rd_data_reg[138]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(2),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(8),
      O => \^not_strict_mode.app_rd_data_reg[15]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(10),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(16),
      O => \^not_strict_mode.app_rd_data_reg[14]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(18),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(24),
      O => \^not_strict_mode.app_rd_data_reg[13]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(26),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(32),
      O => \^not_strict_mode.app_rd_data_reg[12]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(37),
      I1 => my_empty(4),
      I2 => mem_out(43),
      O => \^not_strict_mode.app_rd_data_reg[203]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(45),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \^not_strict_mode.app_rd_data_reg[202]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(53),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \^not_strict_mode.app_rd_data_reg[201]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(61),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \^not_strict_mode.app_rd_data_reg[200]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(5),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(11),
      O => \^not_strict_mode.app_rd_data_reg[207]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(13),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(19),
      O => \^not_strict_mode.app_rd_data_reg[206]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(21),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(27),
      O => \^not_strict_mode.app_rd_data_reg[205]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(29),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(35),
      O => \^not_strict_mode.app_rd_data_reg[204]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(22),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(28),
      O => \^not_strict_mode.app_rd_data_reg[269]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(30),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(36),
      O => \^not_strict_mode.app_rd_data_reg[268]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(38),
      I1 => my_empty(4),
      I2 => mem_out(44),
      O => \^not_strict_mode.app_rd_data_reg[267]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(46),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \^not_strict_mode.app_rd_data_reg[266]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(54),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \^not_strict_mode.app_rd_data_reg[265]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(62),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \^not_strict_mode.app_rd_data_reg[264]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(6),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(12),
      O => \^not_strict_mode.app_rd_data_reg[271]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(14),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(20),
      O => \^not_strict_mode.app_rd_data_reg[270]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(55),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \^not_strict_mode.app_rd_data_reg[329]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(63),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \^not_strict_mode.app_rd_data_reg[328]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(7),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(13),
      O => \^not_strict_mode.app_rd_data_reg[335]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(15),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(21),
      O => \^not_strict_mode.app_rd_data_reg[334]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(23),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(29),
      O => \^not_strict_mode.app_rd_data_reg[333]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(31),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(37),
      O => \^not_strict_mode.app_rd_data_reg[332]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(39),
      I1 => my_empty(4),
      I2 => mem_out(45),
      O => \^not_strict_mode.app_rd_data_reg[331]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(47),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \^not_strict_mode.app_rd_data_reg[330]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(40),
      I1 => my_empty(4),
      I2 => mem_out(46),
      O => \^not_strict_mode.app_rd_data_reg[395]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(48),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \^not_strict_mode.app_rd_data_reg[394]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(56),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \^not_strict_mode.app_rd_data_reg[393]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(64),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \^not_strict_mode.app_rd_data_reg[392]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(8),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(14),
      O => \^not_strict_mode.app_rd_data_reg[399]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(16),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(22),
      O => \^not_strict_mode.app_rd_data_reg[398]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(24),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(30),
      O => \^not_strict_mode.app_rd_data_reg[397]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(32),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(38),
      O => \^not_strict_mode.app_rd_data_reg[396]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(25),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(31),
      O => \^not_strict_mode.app_rd_data_reg[461]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(33),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(39),
      O => \^not_strict_mode.app_rd_data_reg[460]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(41),
      I1 => my_empty(4),
      I2 => mem_out(47),
      O => \^not_strict_mode.app_rd_data_reg[459]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(49),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \^not_strict_mode.app_rd_data_reg[458]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(57),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \^not_strict_mode.app_rd_data_reg[457]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(65),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \^not_strict_mode.app_rd_data_reg[456]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(9),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(15),
      O => \^not_strict_mode.app_rd_data_reg[463]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(17),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(23),
      O => \^not_strict_mode.app_rd_data_reg[462]\
    );
\rd_ptr[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__1_n_0\
    );
\rd_ptr[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__1_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1__1_n_0\,
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1__1_n_0\,
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1__16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF02"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__16_n_0\
    );
\rd_ptr_timing[1]_i_1__16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFD0220"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__16_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__16_n_0\,
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__16_n_0\,
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr[0]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFCA0035"
    )
        port map (
      I0 => my_full(1),
      I1 => my_empty(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__8_n_0\
    );
\wr_ptr[1]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF5DD00000A22"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => my_empty(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__8_n_0\
    );
\wr_ptr[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => \^q\(0),
      O => \rd_ptr_timing_reg[0]_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__8_n_0\,
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__8_n_0\,
      Q => wr_ptr(1),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_26 is
  port (
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[16]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[18]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[20]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[22]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[80]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[82]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[84]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[86]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[144]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[146]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[148]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[150]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[208]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[210]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[212]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[214]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[272]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[274]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[276]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[278]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[336]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[338]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[340]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[342]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[400]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[402]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[404]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[406]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[464]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[466]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[468]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[470]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[471]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]_1\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    byte_rd_en_v_0 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    byte_rd_en_v_1 : in STD_LOGIC;
    byte_rd_en_v_2 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC_VECTOR ( 67 downto 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_26 : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_26;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_26 is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 8 );
  signal mem_reg_0_3_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_3_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_1 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[144]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[145]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[146]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[147]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[148]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[149]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[150]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[151]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[16]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[17]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[18]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[19]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[208]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[209]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[20]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[210]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[211]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[212]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[213]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[214]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[215]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[21]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[22]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[23]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[272]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[273]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[274]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[275]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[276]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[277]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[278]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[279]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[336]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[337]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[338]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[339]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[340]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[341]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[342]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[343]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[400]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[401]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[402]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[403]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[404]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[405]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[406]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[407]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[464]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[465]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[466]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[467]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[468]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[469]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[470]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[471]_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[80]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[81]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[82]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[83]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[84]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[85]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[86]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[87]\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[1]_1\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__15_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__15_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__6_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[1]_i_1__1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \my_empty[1]_i_2__1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \my_empty[4]_i_2__1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \my_empty[4]_i_3__3\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \my_empty[4]_i_4__0\ : label is "soft_lutpair517";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[0]_i_2__1\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \my_full[1]_i_2__1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[144]_i_1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[145]_i_1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[146]_i_1\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[147]_i_1\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[148]_i_1\ : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[149]_i_1\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[150]_i_1\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[151]_i_1\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[16]_i_1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[17]_i_1\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[18]_i_1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[19]_i_1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[208]_i_1\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[209]_i_1\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[20]_i_1\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[210]_i_1\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[211]_i_1\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[212]_i_1\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[213]_i_1\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[214]_i_1\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[215]_i_1\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[21]_i_1\ : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[22]_i_1\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[23]_i_1\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[272]_i_1\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[273]_i_1\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[274]_i_1\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[275]_i_1\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[276]_i_1\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[277]_i_1\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[278]_i_1\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[279]_i_1\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[336]_i_1\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[337]_i_1\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[338]_i_1\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[339]_i_1\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[340]_i_1\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[341]_i_1\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[342]_i_1\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[343]_i_1\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[400]_i_1\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[401]_i_1\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[402]_i_1\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[403]_i_1\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[404]_i_1\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[405]_i_1\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[406]_i_1\ : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[407]_i_1\ : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[464]_i_1\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[465]_i_1\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[466]_i_1\ : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[467]_i_1\ : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[468]_i_1\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[469]_i_1\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[470]_i_1\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[471]_i_1\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[80]_i_1\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[81]_i_1\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[82]_i_1\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[83]_i_1\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[84]_i_1\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[85]_i_1\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[86]_i_1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[87]_i_1\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__0\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__0\ : label is "soft_lutpair519";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__6\ : label is "soft_lutpair517";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  Q(0) <= \^q\(0);
  \not_strict_mode.app_rd_data_reg[144]\ <= \^not_strict_mode.app_rd_data_reg[144]\;
  \not_strict_mode.app_rd_data_reg[145]\ <= \^not_strict_mode.app_rd_data_reg[145]\;
  \not_strict_mode.app_rd_data_reg[146]\ <= \^not_strict_mode.app_rd_data_reg[146]\;
  \not_strict_mode.app_rd_data_reg[147]\ <= \^not_strict_mode.app_rd_data_reg[147]\;
  \not_strict_mode.app_rd_data_reg[148]\ <= \^not_strict_mode.app_rd_data_reg[148]\;
  \not_strict_mode.app_rd_data_reg[149]\ <= \^not_strict_mode.app_rd_data_reg[149]\;
  \not_strict_mode.app_rd_data_reg[150]\ <= \^not_strict_mode.app_rd_data_reg[150]\;
  \not_strict_mode.app_rd_data_reg[151]\ <= \^not_strict_mode.app_rd_data_reg[151]\;
  \not_strict_mode.app_rd_data_reg[16]\ <= \^not_strict_mode.app_rd_data_reg[16]\;
  \not_strict_mode.app_rd_data_reg[17]\ <= \^not_strict_mode.app_rd_data_reg[17]\;
  \not_strict_mode.app_rd_data_reg[18]\ <= \^not_strict_mode.app_rd_data_reg[18]\;
  \not_strict_mode.app_rd_data_reg[19]\ <= \^not_strict_mode.app_rd_data_reg[19]\;
  \not_strict_mode.app_rd_data_reg[208]\ <= \^not_strict_mode.app_rd_data_reg[208]\;
  \not_strict_mode.app_rd_data_reg[209]\ <= \^not_strict_mode.app_rd_data_reg[209]\;
  \not_strict_mode.app_rd_data_reg[20]\ <= \^not_strict_mode.app_rd_data_reg[20]\;
  \not_strict_mode.app_rd_data_reg[210]\ <= \^not_strict_mode.app_rd_data_reg[210]\;
  \not_strict_mode.app_rd_data_reg[211]\ <= \^not_strict_mode.app_rd_data_reg[211]\;
  \not_strict_mode.app_rd_data_reg[212]\ <= \^not_strict_mode.app_rd_data_reg[212]\;
  \not_strict_mode.app_rd_data_reg[213]\ <= \^not_strict_mode.app_rd_data_reg[213]\;
  \not_strict_mode.app_rd_data_reg[214]\ <= \^not_strict_mode.app_rd_data_reg[214]\;
  \not_strict_mode.app_rd_data_reg[215]\ <= \^not_strict_mode.app_rd_data_reg[215]\;
  \not_strict_mode.app_rd_data_reg[21]\ <= \^not_strict_mode.app_rd_data_reg[21]\;
  \not_strict_mode.app_rd_data_reg[22]\ <= \^not_strict_mode.app_rd_data_reg[22]\;
  \not_strict_mode.app_rd_data_reg[23]\ <= \^not_strict_mode.app_rd_data_reg[23]\;
  \not_strict_mode.app_rd_data_reg[272]\ <= \^not_strict_mode.app_rd_data_reg[272]\;
  \not_strict_mode.app_rd_data_reg[273]\ <= \^not_strict_mode.app_rd_data_reg[273]\;
  \not_strict_mode.app_rd_data_reg[274]\ <= \^not_strict_mode.app_rd_data_reg[274]\;
  \not_strict_mode.app_rd_data_reg[275]\ <= \^not_strict_mode.app_rd_data_reg[275]\;
  \not_strict_mode.app_rd_data_reg[276]\ <= \^not_strict_mode.app_rd_data_reg[276]\;
  \not_strict_mode.app_rd_data_reg[277]\ <= \^not_strict_mode.app_rd_data_reg[277]\;
  \not_strict_mode.app_rd_data_reg[278]\ <= \^not_strict_mode.app_rd_data_reg[278]\;
  \not_strict_mode.app_rd_data_reg[279]\ <= \^not_strict_mode.app_rd_data_reg[279]\;
  \not_strict_mode.app_rd_data_reg[336]\ <= \^not_strict_mode.app_rd_data_reg[336]\;
  \not_strict_mode.app_rd_data_reg[337]\ <= \^not_strict_mode.app_rd_data_reg[337]\;
  \not_strict_mode.app_rd_data_reg[338]\ <= \^not_strict_mode.app_rd_data_reg[338]\;
  \not_strict_mode.app_rd_data_reg[339]\ <= \^not_strict_mode.app_rd_data_reg[339]\;
  \not_strict_mode.app_rd_data_reg[340]\ <= \^not_strict_mode.app_rd_data_reg[340]\;
  \not_strict_mode.app_rd_data_reg[341]\ <= \^not_strict_mode.app_rd_data_reg[341]\;
  \not_strict_mode.app_rd_data_reg[342]\ <= \^not_strict_mode.app_rd_data_reg[342]\;
  \not_strict_mode.app_rd_data_reg[343]\ <= \^not_strict_mode.app_rd_data_reg[343]\;
  \not_strict_mode.app_rd_data_reg[400]\ <= \^not_strict_mode.app_rd_data_reg[400]\;
  \not_strict_mode.app_rd_data_reg[401]\ <= \^not_strict_mode.app_rd_data_reg[401]\;
  \not_strict_mode.app_rd_data_reg[402]\ <= \^not_strict_mode.app_rd_data_reg[402]\;
  \not_strict_mode.app_rd_data_reg[403]\ <= \^not_strict_mode.app_rd_data_reg[403]\;
  \not_strict_mode.app_rd_data_reg[404]\ <= \^not_strict_mode.app_rd_data_reg[404]\;
  \not_strict_mode.app_rd_data_reg[405]\ <= \^not_strict_mode.app_rd_data_reg[405]\;
  \not_strict_mode.app_rd_data_reg[406]\ <= \^not_strict_mode.app_rd_data_reg[406]\;
  \not_strict_mode.app_rd_data_reg[407]\ <= \^not_strict_mode.app_rd_data_reg[407]\;
  \not_strict_mode.app_rd_data_reg[464]\ <= \^not_strict_mode.app_rd_data_reg[464]\;
  \not_strict_mode.app_rd_data_reg[465]\ <= \^not_strict_mode.app_rd_data_reg[465]\;
  \not_strict_mode.app_rd_data_reg[466]\ <= \^not_strict_mode.app_rd_data_reg[466]\;
  \not_strict_mode.app_rd_data_reg[467]\ <= \^not_strict_mode.app_rd_data_reg[467]\;
  \not_strict_mode.app_rd_data_reg[468]\ <= \^not_strict_mode.app_rd_data_reg[468]\;
  \not_strict_mode.app_rd_data_reg[469]\ <= \^not_strict_mode.app_rd_data_reg[469]\;
  \not_strict_mode.app_rd_data_reg[470]\ <= \^not_strict_mode.app_rd_data_reg[470]\;
  \not_strict_mode.app_rd_data_reg[471]_0\ <= \^not_strict_mode.app_rd_data_reg[471]_0\;
  \not_strict_mode.app_rd_data_reg[80]\ <= \^not_strict_mode.app_rd_data_reg[80]\;
  \not_strict_mode.app_rd_data_reg[81]\ <= \^not_strict_mode.app_rd_data_reg[81]\;
  \not_strict_mode.app_rd_data_reg[82]\ <= \^not_strict_mode.app_rd_data_reg[82]\;
  \not_strict_mode.app_rd_data_reg[83]\ <= \^not_strict_mode.app_rd_data_reg[83]\;
  \not_strict_mode.app_rd_data_reg[84]\ <= \^not_strict_mode.app_rd_data_reg[84]\;
  \not_strict_mode.app_rd_data_reg[85]\ <= \^not_strict_mode.app_rd_data_reg[85]\;
  \not_strict_mode.app_rd_data_reg[86]\ <= \^not_strict_mode.app_rd_data_reg[86]\;
  \not_strict_mode.app_rd_data_reg[87]\ <= \^not_strict_mode.app_rd_data_reg[87]\;
  \rd_ptr_reg[1]_1\ <= \^rd_ptr_reg[1]_1\;
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(7 downto 6),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(9 downto 8),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(13 downto 12),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(15 downto 14),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(19 downto 18),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(21 downto 20),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(25 downto 24),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(27 downto 26),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(31 downto 30),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(33 downto 32),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1) => mem_reg_0_3_36_41_n_4,
      DOC(0) => mem_reg_0_3_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(37 downto 36),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(39 downto 38),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(43 downto 42),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(45 downto 44),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(49 downto 48),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(51 downto 50),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(55 downto 54),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(57 downto 56),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(3 downto 2),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_6_11_n_0,
      DOA(0) => mem_reg_0_3_6_11_n_1,
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I1 => my_full(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(61 downto 60),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(63 downto 62),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__1_n_0\,
      I3 => \my_empty[4]_i_3__3_n_0\,
      I4 => \my_empty[4]_i_4__0_n_0\,
      I5 => \^q\(0),
      O => \my_empty[0]_i_1__1_n_0\
    );
\my_empty[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0400"
    )
        port map (
      I0 => \my_empty[1]_i_2__1_n_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I4 => my_empty(1),
      O => \my_empty[1]_i_1__1_n_0\
    );
\my_empty[1]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBEEBFF"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[1]_i_2__1_n_0\
    );
\my_empty[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__1_n_0\,
      I3 => \my_empty[4]_i_3__3_n_0\,
      I4 => \my_empty[4]_i_4__0_n_0\,
      I5 => my_empty(2),
      O => \my_empty[2]_i_1__1_n_0\
    );
\my_empty[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__1_n_0\,
      I3 => \my_empty[4]_i_3__3_n_0\,
      I4 => \my_empty[4]_i_4__0_n_0\,
      I5 => my_empty(3),
      O => \my_empty[3]_i_1__1_n_0\
    );
\my_empty[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00003003AAAAAAAA"
    )
        port map (
      I0 => my_empty(4),
      I1 => my_empty(1),
      I2 => wr_ptr(1),
      I3 => \my_empty[4]_i_2__1_n_0\,
      I4 => \my_empty[4]_i_3__3_n_0\,
      I5 => \my_empty[4]_i_4__0_n_0\,
      O => \my_empty[4]_i_1__1_n_0\
    );
\my_empty[4]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \my_empty[4]_i_2__1_n_0\
    );
\my_empty[4]_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => wr_ptr(0),
      O => \my_empty[4]_i_3__3_n_0\
    );
\my_empty[4]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_4__0_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[0]_i_1__1_n_0\,
      Q => \^q\(0),
      S => SR(0)
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__1_n_0\,
      Q => my_empty(1),
      S => SR(0)
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[2]_i_1__1_n_0\,
      Q => my_empty(2),
      S => SR(0)
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[3]_i_1__1_n_0\,
      Q => my_empty(3),
      S => SR(0)
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__1_n_0\,
      Q => my_empty(4),
      S => SR(0)
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__1_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => SR(0)
    );
\my_full[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I3 => my_full(1),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I5 => \my_full[0]_i_2__1_n_0\,
      O => \my_full[0]_i_1__1_n_0\
    );
\my_full[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[0]_i_2__1_n_0\
    );
\my_full[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888988989988888"
    )
        port map (
      I0 => \my_full[1]_i_2__1_n_0\,
      I1 => my_full(1),
      I2 => rd_ptr(1),
      I3 => wr_ptr(1),
      I4 => wr_ptr(0),
      I5 => rd_ptr(0),
      O => \my_full[1]_i_1__1_n_0\
    );
\my_full[1]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      O => \my_full[1]_i_2__1_n_0\
    );
\my_full[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000777"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I1 => my_empty(3),
      I2 => if_empty_r_0(0),
      I3 => \my_empty_reg[3]_0\(0),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      I5 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => byte_rd_en_v_0
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[0]_i_1__1_n_0\,
      Q => my_full(0),
      R => SR(0)
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[1]_i_1__1_n_0\,
      Q => my_full(1),
      R => SR(0)
    );
\not_strict_mode.app_rd_data[144]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[144]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(16)
    );
\not_strict_mode.app_rd_data[145]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[145]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(17)
    );
\not_strict_mode.app_rd_data[146]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[146]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(18)
    );
\not_strict_mode.app_rd_data[147]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[147]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(19)
    );
\not_strict_mode.app_rd_data[148]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[148]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(20)
    );
\not_strict_mode.app_rd_data[149]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[149]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(21)
    );
\not_strict_mode.app_rd_data[150]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[150]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(22)
    );
\not_strict_mode.app_rd_data[151]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[151]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(23)
    );
\not_strict_mode.app_rd_data[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[16]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(0)
    );
\not_strict_mode.app_rd_data[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[17]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(1)
    );
\not_strict_mode.app_rd_data[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[18]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(2)
    );
\not_strict_mode.app_rd_data[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[19]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(3)
    );
\not_strict_mode.app_rd_data[208]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[208]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(24)
    );
\not_strict_mode.app_rd_data[209]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[209]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(25)
    );
\not_strict_mode.app_rd_data[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[20]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(4)
    );
\not_strict_mode.app_rd_data[210]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[210]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(26)
    );
\not_strict_mode.app_rd_data[211]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[211]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(27)
    );
\not_strict_mode.app_rd_data[212]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[212]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(28)
    );
\not_strict_mode.app_rd_data[213]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[213]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(29)
    );
\not_strict_mode.app_rd_data[214]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[214]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(30)
    );
\not_strict_mode.app_rd_data[215]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[215]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(31)
    );
\not_strict_mode.app_rd_data[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[21]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(5)
    );
\not_strict_mode.app_rd_data[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[22]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(6)
    );
\not_strict_mode.app_rd_data[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[23]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(7)
    );
\not_strict_mode.app_rd_data[272]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[272]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(32)
    );
\not_strict_mode.app_rd_data[273]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[273]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(33)
    );
\not_strict_mode.app_rd_data[274]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[274]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(34)
    );
\not_strict_mode.app_rd_data[275]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[275]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(35)
    );
\not_strict_mode.app_rd_data[276]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[276]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(36)
    );
\not_strict_mode.app_rd_data[277]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[277]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(37)
    );
\not_strict_mode.app_rd_data[278]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[278]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(38)
    );
\not_strict_mode.app_rd_data[279]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[279]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(39)
    );
\not_strict_mode.app_rd_data[336]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[336]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(40)
    );
\not_strict_mode.app_rd_data[337]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[337]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(41)
    );
\not_strict_mode.app_rd_data[338]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[338]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(42)
    );
\not_strict_mode.app_rd_data[339]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[339]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(43)
    );
\not_strict_mode.app_rd_data[340]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[340]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(44)
    );
\not_strict_mode.app_rd_data[341]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[341]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(45)
    );
\not_strict_mode.app_rd_data[342]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[342]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(46)
    );
\not_strict_mode.app_rd_data[343]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[343]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(47)
    );
\not_strict_mode.app_rd_data[400]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[400]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(48)
    );
\not_strict_mode.app_rd_data[401]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[401]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(49)
    );
\not_strict_mode.app_rd_data[402]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[402]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(50)
    );
\not_strict_mode.app_rd_data[403]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[403]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(51)
    );
\not_strict_mode.app_rd_data[404]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[404]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(52)
    );
\not_strict_mode.app_rd_data[405]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[405]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(53)
    );
\not_strict_mode.app_rd_data[406]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[406]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(54)
    );
\not_strict_mode.app_rd_data[407]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[407]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(55)
    );
\not_strict_mode.app_rd_data[464]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[464]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(56)
    );
\not_strict_mode.app_rd_data[465]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[465]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(57)
    );
\not_strict_mode.app_rd_data[466]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[466]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(58)
    );
\not_strict_mode.app_rd_data[467]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[467]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(59)
    );
\not_strict_mode.app_rd_data[468]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[468]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(60)
    );
\not_strict_mode.app_rd_data[469]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[469]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(61)
    );
\not_strict_mode.app_rd_data[470]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[470]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(62)
    );
\not_strict_mode.app_rd_data[471]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[471]_0\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(63)
    );
\not_strict_mode.app_rd_data[80]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[80]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(8)
    );
\not_strict_mode.app_rd_data[81]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[81]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(9)
    );
\not_strict_mode.app_rd_data[82]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[82]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(10)
    );
\not_strict_mode.app_rd_data[83]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[83]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(11)
    );
\not_strict_mode.app_rd_data[84]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[84]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(12)
    );
\not_strict_mode.app_rd_data[85]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[85]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(13)
    );
\not_strict_mode.app_rd_data[86]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[86]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[471]\(14)
    );
\not_strict_mode.app_rd_data[87]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[87]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[471]\(15)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(37),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \^not_strict_mode.app_rd_data_reg[83]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(45),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \^not_strict_mode.app_rd_data_reg[82]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(53),
      I1 => my_empty(4),
      I2 => mem_out(65),
      O => \^not_strict_mode.app_rd_data_reg[81]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(61),
      I1 => my_empty(4),
      I2 => mem_out(73),
      O => \^not_strict_mode.app_rd_data_reg[80]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(3),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(9),
      O => \^not_strict_mode.app_rd_data_reg[87]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(11),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(17),
      O => \^not_strict_mode.app_rd_data_reg[86]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(19),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(25),
      O => \^not_strict_mode.app_rd_data_reg[85]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(27),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(33),
      O => \^not_strict_mode.app_rd_data_reg[84]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(20),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(26),
      O => \^not_strict_mode.app_rd_data_reg[149]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(28),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(34),
      O => \^not_strict_mode.app_rd_data_reg[148]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(38),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \^not_strict_mode.app_rd_data_reg[147]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(46),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \^not_strict_mode.app_rd_data_reg[146]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(54),
      I1 => my_empty(4),
      I2 => mem_out(66),
      O => \^not_strict_mode.app_rd_data_reg[145]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(62),
      I1 => my_empty(4),
      I2 => mem_out(74),
      O => \^not_strict_mode.app_rd_data_reg[144]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(4),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(10),
      O => \^not_strict_mode.app_rd_data_reg[151]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(12),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(18),
      O => \^not_strict_mode.app_rd_data_reg[150]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(52),
      I1 => my_empty(4),
      I2 => mem_out(64),
      O => \^not_strict_mode.app_rd_data_reg[17]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(60),
      I1 => my_empty(4),
      I2 => mem_out(72),
      O => \^not_strict_mode.app_rd_data_reg[16]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(55),
      I1 => my_empty(4),
      I2 => mem_out(67),
      O => \^not_strict_mode.app_rd_data_reg[209]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(63),
      I1 => my_empty(4),
      I2 => mem_out(75),
      O => \^not_strict_mode.app_rd_data_reg[208]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(5),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(11),
      O => \^not_strict_mode.app_rd_data_reg[215]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(13),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(19),
      O => \^not_strict_mode.app_rd_data_reg[214]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(21),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(27),
      O => \^not_strict_mode.app_rd_data_reg[213]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(29),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(35),
      O => \^not_strict_mode.app_rd_data_reg[212]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(39),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \^not_strict_mode.app_rd_data_reg[211]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(47),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \^not_strict_mode.app_rd_data_reg[210]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(2),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(8),
      O => \^not_strict_mode.app_rd_data_reg[23]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(10),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(16),
      O => \^not_strict_mode.app_rd_data_reg[22]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(18),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(24),
      O => \^not_strict_mode.app_rd_data_reg[21]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(26),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(32),
      O => \^not_strict_mode.app_rd_data_reg[20]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(36),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \^not_strict_mode.app_rd_data_reg[19]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(44),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \^not_strict_mode.app_rd_data_reg[18]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(40),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \^not_strict_mode.app_rd_data_reg[275]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(48),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \^not_strict_mode.app_rd_data_reg[274]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(56),
      I1 => my_empty(4),
      I2 => mem_out(68),
      O => \^not_strict_mode.app_rd_data_reg[273]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(64),
      I1 => my_empty(4),
      I2 => mem_out(76),
      O => \^not_strict_mode.app_rd_data_reg[272]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(6),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(12),
      O => \^not_strict_mode.app_rd_data_reg[279]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(14),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(20),
      O => \^not_strict_mode.app_rd_data_reg[278]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(22),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(28),
      O => \^not_strict_mode.app_rd_data_reg[277]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(30),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(36),
      O => \^not_strict_mode.app_rd_data_reg[276]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(23),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(29),
      O => \^not_strict_mode.app_rd_data_reg[341]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(31),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(37),
      O => \^not_strict_mode.app_rd_data_reg[340]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(41),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \^not_strict_mode.app_rd_data_reg[339]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(49),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \^not_strict_mode.app_rd_data_reg[338]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(57),
      I1 => my_empty(4),
      I2 => mem_out(69),
      O => \^not_strict_mode.app_rd_data_reg[337]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(65),
      I1 => my_empty(4),
      I2 => mem_out(77),
      O => \^not_strict_mode.app_rd_data_reg[336]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(7),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(13),
      O => \^not_strict_mode.app_rd_data_reg[343]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(15),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(21),
      O => \^not_strict_mode.app_rd_data_reg[342]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(58),
      I1 => my_empty(4),
      I2 => mem_out(70),
      O => \^not_strict_mode.app_rd_data_reg[401]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(66),
      I1 => my_empty(4),
      I2 => mem_out(78),
      O => \^not_strict_mode.app_rd_data_reg[400]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(8),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(14),
      O => \^not_strict_mode.app_rd_data_reg[407]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(16),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(22),
      O => \^not_strict_mode.app_rd_data_reg[406]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(24),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(30),
      O => \^not_strict_mode.app_rd_data_reg[405]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(32),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(38),
      O => \^not_strict_mode.app_rd_data_reg[404]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(42),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \^not_strict_mode.app_rd_data_reg[403]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(50),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \^not_strict_mode.app_rd_data_reg[402]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(43),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \^not_strict_mode.app_rd_data_reg[467]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(51),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \^not_strict_mode.app_rd_data_reg[466]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(59),
      I1 => my_empty(4),
      I2 => mem_out(71),
      O => \^not_strict_mode.app_rd_data_reg[465]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67),
      I1 => my_empty(4),
      I2 => mem_out(79),
      O => \^not_strict_mode.app_rd_data_reg[464]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(9),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(15),
      O => \^not_strict_mode.app_rd_data_reg[471]_0\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(17),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(23),
      O => \^not_strict_mode.app_rd_data_reg[470]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(25),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(31),
      O => \^not_strict_mode.app_rd_data_reg[469]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(33),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(39),
      O => \^not_strict_mode.app_rd_data_reg[468]\
    );
\rd_ptr[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__0_n_0\
    );
\rd_ptr[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1__0_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1__0_n_0\,
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1__0_n_0\,
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1__15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF02"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__15_n_0\
    );
\rd_ptr_timing[1]_i_1__15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFD0220"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__15_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__15_n_0\,
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__15_n_0\,
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFCA0035"
    )
        port map (
      I0 => my_full(1),
      I1 => my_empty(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__6_n_0\
    );
\wr_ptr[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF5DD00000A22"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => my_empty(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__6_n_0\
    );
\wr_ptr[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^rd_ptr_reg[1]_1\,
      I1 => byte_rd_en_v_1,
      I2 => byte_rd_en_v_2,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      I5 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      O => \rd_ptr_reg[1]_0\
    );
\wr_ptr[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I1 => my_empty(3),
      O => \^rd_ptr_reg[1]_1\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__6_n_0\,
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__6_n_0\,
      Q => wr_ptr(1),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_29 is
  port (
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[24]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[26]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[28]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[30]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[88]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[90]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[92]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[94]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[152]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[154]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[156]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[158]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[216]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[218]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[220]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[222]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[280]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[282]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[284]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[286]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[344]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[346]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[348]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[350]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[408]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[410]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[412]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[414]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[472]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[474]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[476]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[478]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]_0\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[0]_2\ : out STD_LOGIC;
    \rd_ptr_reg[0]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \po_stg2_wrcal_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_7\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_8\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_9\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_10\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_11\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_12\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_13\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_14\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_15\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_16\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_17\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_18\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_19\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_20\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_21\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_22\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_23\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_24\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_25\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_26\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_27\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_28\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_29\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_30\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_31\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_32\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_33\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_34\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_35\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_36\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_37\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_38\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_39\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_40\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_41\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_42\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_43\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_44\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_45\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_46\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_47\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_48\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_49\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_50\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_51\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_52\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_53\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_54\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_55\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_56\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_57\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_58\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_59\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_60\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_61\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_62\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : in STD_LOGIC_VECTOR ( 65 downto 0 );
    byte_rd_en_v_1 : in STD_LOGIC;
    byte_rd_en_v_2 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_29 : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_29;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_29 is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\ : STD_LOGIC;
  signal mem_out : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal mem_reg_0_3_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_3_60_65_n_5 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_4_n_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[152]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[153]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[154]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[155]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[156]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[157]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[158]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[159]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[216]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[217]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[218]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[219]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[220]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[221]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[222]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[223]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[24]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[25]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[26]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[27]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[280]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[281]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[282]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[283]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[284]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[285]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[286]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[287]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[28]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[29]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[30]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[31]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[344]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[345]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[346]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[347]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[348]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[349]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[350]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[351]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[408]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[409]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[410]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[411]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[412]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[413]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[414]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[415]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[472]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[473]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[474]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[475]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[476]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[477]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[478]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[479]_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[88]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[89]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[90]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[91]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[92]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[93]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[94]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[95]\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1_n_0\ : STD_LOGIC;
  signal \^rd_ptr_reg[0]_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__14_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__14_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__4_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[1]_i_1__0\ : label is "soft_lutpair465";
  attribute SOFT_HLUTNM of \my_empty[1]_i_2__0\ : label is "soft_lutpair462";
  attribute SOFT_HLUTNM of \my_empty[4]_i_2__0\ : label is "soft_lutpair462";
  attribute SOFT_HLUTNM of \my_empty[4]_i_3__2\ : label is "soft_lutpair464";
  attribute SOFT_HLUTNM of \my_empty[4]_i_4\ : label is "soft_lutpair463";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[0]_i_2__0\ : label is "soft_lutpair464";
  attribute SOFT_HLUTNM of \my_full[1]_i_2__0\ : label is "soft_lutpair465";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[152]_i_1\ : label is "soft_lutpair470";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[153]_i_1\ : label is "soft_lutpair471";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[154]_i_1\ : label is "soft_lutpair473";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[155]_i_1\ : label is "soft_lutpair472";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[156]_i_1\ : label is "soft_lutpair474";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[157]_i_1\ : label is "soft_lutpair475";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[158]_i_1\ : label is "soft_lutpair476";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[159]_i_1\ : label is "soft_lutpair477";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[216]_i_1\ : label is "soft_lutpair478";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[217]_i_1\ : label is "soft_lutpair480";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[218]_i_1\ : label is "soft_lutpair479";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[219]_i_1\ : label is "soft_lutpair480";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[220]_i_1\ : label is "soft_lutpair481";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[221]_i_1\ : label is "soft_lutpair481";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[222]_i_1\ : label is "soft_lutpair482";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[223]_i_1\ : label is "soft_lutpair482";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[24]_i_1\ : label is "soft_lutpair467";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[25]_i_1\ : label is "soft_lutpair468";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[26]_i_1\ : label is "soft_lutpair469";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[27]_i_1\ : label is "soft_lutpair470";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[280]_i_1\ : label is "soft_lutpair483";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[281]_i_1\ : label is "soft_lutpair483";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[282]_i_1\ : label is "soft_lutpair484";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[283]_i_1\ : label is "soft_lutpair484";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[284]_i_1\ : label is "soft_lutpair485";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[285]_i_1\ : label is "soft_lutpair485";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[286]_i_1\ : label is "soft_lutpair486";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[287]_i_1\ : label is "soft_lutpair487";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[28]_i_1\ : label is "soft_lutpair471";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[29]_i_1\ : label is "soft_lutpair472";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[30]_i_1\ : label is "soft_lutpair473";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[31]_i_1\ : label is "soft_lutpair474";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[344]_i_1\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[345]_i_1\ : label is "soft_lutpair486";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[346]_i_1\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[347]_i_1\ : label is "soft_lutpair487";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[348]_i_1\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[349]_i_1\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[350]_i_1\ : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[351]_i_1\ : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[408]_i_1\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[409]_i_1\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[410]_i_1\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[411]_i_1\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[412]_i_1\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[413]_i_1\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[414]_i_1\ : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[415]_i_1\ : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[472]_i_1\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[473]_i_1\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[474]_i_1\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[475]_i_1\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[476]_i_1\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[477]_i_1\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[478]_i_1\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[479]_i_1\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[88]_i_1\ : label is "soft_lutpair475";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[89]_i_1\ : label is "soft_lutpair476";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[90]_i_1\ : label is "soft_lutpair477";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[91]_i_1\ : label is "soft_lutpair478";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[92]_i_1\ : label is "soft_lutpair479";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[93]_i_1\ : label is "soft_lutpair467";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[94]_i_1\ : label is "soft_lutpair468";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[95]_i_1\ : label is "soft_lutpair469";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1\ : label is "soft_lutpair466";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair466";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__4\ : label is "soft_lutpair463";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
  \not_strict_mode.app_rd_data_reg[152]\ <= \^not_strict_mode.app_rd_data_reg[152]\;
  \not_strict_mode.app_rd_data_reg[153]\ <= \^not_strict_mode.app_rd_data_reg[153]\;
  \not_strict_mode.app_rd_data_reg[154]\ <= \^not_strict_mode.app_rd_data_reg[154]\;
  \not_strict_mode.app_rd_data_reg[155]\ <= \^not_strict_mode.app_rd_data_reg[155]\;
  \not_strict_mode.app_rd_data_reg[156]\ <= \^not_strict_mode.app_rd_data_reg[156]\;
  \not_strict_mode.app_rd_data_reg[157]\ <= \^not_strict_mode.app_rd_data_reg[157]\;
  \not_strict_mode.app_rd_data_reg[158]\ <= \^not_strict_mode.app_rd_data_reg[158]\;
  \not_strict_mode.app_rd_data_reg[159]\ <= \^not_strict_mode.app_rd_data_reg[159]\;
  \not_strict_mode.app_rd_data_reg[216]\ <= \^not_strict_mode.app_rd_data_reg[216]\;
  \not_strict_mode.app_rd_data_reg[217]\ <= \^not_strict_mode.app_rd_data_reg[217]\;
  \not_strict_mode.app_rd_data_reg[218]\ <= \^not_strict_mode.app_rd_data_reg[218]\;
  \not_strict_mode.app_rd_data_reg[219]\ <= \^not_strict_mode.app_rd_data_reg[219]\;
  \not_strict_mode.app_rd_data_reg[220]\ <= \^not_strict_mode.app_rd_data_reg[220]\;
  \not_strict_mode.app_rd_data_reg[221]\ <= \^not_strict_mode.app_rd_data_reg[221]\;
  \not_strict_mode.app_rd_data_reg[222]\ <= \^not_strict_mode.app_rd_data_reg[222]\;
  \not_strict_mode.app_rd_data_reg[223]\ <= \^not_strict_mode.app_rd_data_reg[223]\;
  \not_strict_mode.app_rd_data_reg[24]\ <= \^not_strict_mode.app_rd_data_reg[24]\;
  \not_strict_mode.app_rd_data_reg[25]\ <= \^not_strict_mode.app_rd_data_reg[25]\;
  \not_strict_mode.app_rd_data_reg[26]\ <= \^not_strict_mode.app_rd_data_reg[26]\;
  \not_strict_mode.app_rd_data_reg[27]\ <= \^not_strict_mode.app_rd_data_reg[27]\;
  \not_strict_mode.app_rd_data_reg[280]\ <= \^not_strict_mode.app_rd_data_reg[280]\;
  \not_strict_mode.app_rd_data_reg[281]\ <= \^not_strict_mode.app_rd_data_reg[281]\;
  \not_strict_mode.app_rd_data_reg[282]\ <= \^not_strict_mode.app_rd_data_reg[282]\;
  \not_strict_mode.app_rd_data_reg[283]\ <= \^not_strict_mode.app_rd_data_reg[283]\;
  \not_strict_mode.app_rd_data_reg[284]\ <= \^not_strict_mode.app_rd_data_reg[284]\;
  \not_strict_mode.app_rd_data_reg[285]\ <= \^not_strict_mode.app_rd_data_reg[285]\;
  \not_strict_mode.app_rd_data_reg[286]\ <= \^not_strict_mode.app_rd_data_reg[286]\;
  \not_strict_mode.app_rd_data_reg[287]\ <= \^not_strict_mode.app_rd_data_reg[287]\;
  \not_strict_mode.app_rd_data_reg[28]\ <= \^not_strict_mode.app_rd_data_reg[28]\;
  \not_strict_mode.app_rd_data_reg[29]\ <= \^not_strict_mode.app_rd_data_reg[29]\;
  \not_strict_mode.app_rd_data_reg[30]\ <= \^not_strict_mode.app_rd_data_reg[30]\;
  \not_strict_mode.app_rd_data_reg[31]\ <= \^not_strict_mode.app_rd_data_reg[31]\;
  \not_strict_mode.app_rd_data_reg[344]\ <= \^not_strict_mode.app_rd_data_reg[344]\;
  \not_strict_mode.app_rd_data_reg[345]\ <= \^not_strict_mode.app_rd_data_reg[345]\;
  \not_strict_mode.app_rd_data_reg[346]\ <= \^not_strict_mode.app_rd_data_reg[346]\;
  \not_strict_mode.app_rd_data_reg[347]\ <= \^not_strict_mode.app_rd_data_reg[347]\;
  \not_strict_mode.app_rd_data_reg[348]\ <= \^not_strict_mode.app_rd_data_reg[348]\;
  \not_strict_mode.app_rd_data_reg[349]\ <= \^not_strict_mode.app_rd_data_reg[349]\;
  \not_strict_mode.app_rd_data_reg[350]\ <= \^not_strict_mode.app_rd_data_reg[350]\;
  \not_strict_mode.app_rd_data_reg[351]\ <= \^not_strict_mode.app_rd_data_reg[351]\;
  \not_strict_mode.app_rd_data_reg[408]\ <= \^not_strict_mode.app_rd_data_reg[408]\;
  \not_strict_mode.app_rd_data_reg[409]\ <= \^not_strict_mode.app_rd_data_reg[409]\;
  \not_strict_mode.app_rd_data_reg[410]\ <= \^not_strict_mode.app_rd_data_reg[410]\;
  \not_strict_mode.app_rd_data_reg[411]\ <= \^not_strict_mode.app_rd_data_reg[411]\;
  \not_strict_mode.app_rd_data_reg[412]\ <= \^not_strict_mode.app_rd_data_reg[412]\;
  \not_strict_mode.app_rd_data_reg[413]\ <= \^not_strict_mode.app_rd_data_reg[413]\;
  \not_strict_mode.app_rd_data_reg[414]\ <= \^not_strict_mode.app_rd_data_reg[414]\;
  \not_strict_mode.app_rd_data_reg[415]\ <= \^not_strict_mode.app_rd_data_reg[415]\;
  \not_strict_mode.app_rd_data_reg[472]\ <= \^not_strict_mode.app_rd_data_reg[472]\;
  \not_strict_mode.app_rd_data_reg[473]\ <= \^not_strict_mode.app_rd_data_reg[473]\;
  \not_strict_mode.app_rd_data_reg[474]\ <= \^not_strict_mode.app_rd_data_reg[474]\;
  \not_strict_mode.app_rd_data_reg[475]\ <= \^not_strict_mode.app_rd_data_reg[475]\;
  \not_strict_mode.app_rd_data_reg[476]\ <= \^not_strict_mode.app_rd_data_reg[476]\;
  \not_strict_mode.app_rd_data_reg[477]\ <= \^not_strict_mode.app_rd_data_reg[477]\;
  \not_strict_mode.app_rd_data_reg[478]\ <= \^not_strict_mode.app_rd_data_reg[478]\;
  \not_strict_mode.app_rd_data_reg[479]_0\ <= \^not_strict_mode.app_rd_data_reg[479]_0\;
  \not_strict_mode.app_rd_data_reg[88]\ <= \^not_strict_mode.app_rd_data_reg[88]\;
  \not_strict_mode.app_rd_data_reg[89]\ <= \^not_strict_mode.app_rd_data_reg[89]\;
  \not_strict_mode.app_rd_data_reg[90]\ <= \^not_strict_mode.app_rd_data_reg[90]\;
  \not_strict_mode.app_rd_data_reg[91]\ <= \^not_strict_mode.app_rd_data_reg[91]\;
  \not_strict_mode.app_rd_data_reg[92]\ <= \^not_strict_mode.app_rd_data_reg[92]\;
  \not_strict_mode.app_rd_data_reg[93]\ <= \^not_strict_mode.app_rd_data_reg[93]\;
  \not_strict_mode.app_rd_data_reg[94]\ <= \^not_strict_mode.app_rd_data_reg[94]\;
  \not_strict_mode.app_rd_data_reg[95]\ <= \^not_strict_mode.app_rd_data_reg[95]\;
  \rd_ptr_reg[0]_0\ <= \^rd_ptr_reg[0]_0\;
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[88]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_15\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[216]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_55\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[344]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_31\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[472]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_7\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[24]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_47\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[152]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]\,
      O => p_0_out,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[280]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_23\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[408]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_39\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[89]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_16\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[217]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_56\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[345]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_32\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[473]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_8\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[25]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_48\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[153]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[281]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_24\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[409]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_40\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[90]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_17\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[218]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_57\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[346]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_33\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[474]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_9\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[26]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_49\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[154]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[282]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_25\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[410]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_41\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[91]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_18\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[219]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_58\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[347]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_34\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[475]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_10\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[27]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_50\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[155]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_2\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[283]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_26\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[411]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_42\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[92]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_19\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[220]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_59\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[348]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_35\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[476]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_11\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[28]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_51\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[156]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_3\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[284]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_27\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[412]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_43\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[93]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_20\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[221]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_60\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[349]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_36\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[477]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_12\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[29]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_52\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[157]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_4\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[285]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_28\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[413]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_44\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[94]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_21\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[222]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_61\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[350]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_37\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[478]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_13\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[30]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_53\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[158]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_5\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[286]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_29\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[414]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_45\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[95]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_22\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[223]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_62\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[351]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_38\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[479]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_14\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[31]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_54\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[159]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_6\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[287]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_30\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[415]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      I2 => \po_stg2_wrcal_cnt_reg[2]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[2]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[1]_46\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      S => \po_stg2_wrcal_cnt_reg[2]\(2)
    );
mem_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(3 downto 2),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(1 downto 0),
      DOB(1 downto 0) => mem_out(3 downto 2),
      DOC(1 downto 0) => mem_out(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_3_0_5_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => my_full(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(13 downto 12),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(15 downto 14),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(19 downto 18),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(21 downto 20),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(25 downto 24),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(27 downto 26),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(31 downto 30),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(33 downto 32),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(37 downto 36),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(39 downto 38),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(43 downto 42),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(45 downto 44),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(49 downto 48),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(51 downto 50),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(55 downto 54),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(57 downto 56),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(61 downto 60),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(63 downto 62),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1) => mem_reg_0_3_60_65_n_4,
      DOC(0) => mem_reg_0_3_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(7 downto 6),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(9 downto 8),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(7 downto 6),
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__0_n_0\,
      I3 => \my_empty[4]_i_3__2_n_0\,
      I4 => \my_empty[4]_i_4_n_0\,
      I5 => \^q\(0),
      O => \my_empty[0]_i_1__0_n_0\
    );
\my_empty[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFD0400"
    )
        port map (
      I0 => \my_empty[1]_i_2__0_n_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => my_empty(1),
      O => \my_empty[1]_i_1__0_n_0\
    );
\my_empty[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBEEBFF"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      O => \my_empty[1]_i_2__0_n_0\
    );
\my_empty[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__0_n_0\,
      I3 => \my_empty[4]_i_3__2_n_0\,
      I4 => \my_empty[4]_i_4_n_0\,
      I5 => my_empty(2),
      O => \my_empty[2]_i_1__0_n_0\
    );
\my_empty[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041FFFF00410000"
    )
        port map (
      I0 => my_empty(1),
      I1 => wr_ptr(1),
      I2 => \my_empty[4]_i_2__0_n_0\,
      I3 => \my_empty[4]_i_3__2_n_0\,
      I4 => \my_empty[4]_i_4_n_0\,
      I5 => \^q\(1),
      O => \my_empty[3]_i_1__0_n_0\
    );
\my_empty[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00003003AAAAAAAA"
    )
        port map (
      I0 => my_empty(4),
      I1 => my_empty(1),
      I2 => wr_ptr(1),
      I3 => \my_empty[4]_i_2__0_n_0\,
      I4 => \my_empty[4]_i_3__2_n_0\,
      I5 => \my_empty[4]_i_4_n_0\,
      O => \my_empty[4]_i_1__0_n_0\
    );
\my_empty[4]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \my_empty[4]_i_2__0_n_0\
    );
\my_empty[4]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => wr_ptr(0),
      O => \my_empty[4]_i_3__2_n_0\
    );
\my_empty[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => my_empty(1),
      I3 => my_full(1),
      O => \my_empty[4]_i_4_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[0]_i_1__0_n_0\,
      Q => \^q\(0),
      S => SR(0)
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__0_n_0\,
      Q => my_empty(1),
      S => SR(0)
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[2]_i_1__0_n_0\,
      Q => my_empty(2),
      S => SR(0)
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[3]_i_1__0_n_0\,
      Q => \^q\(1),
      S => SR(0)
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__0_n_0\,
      Q => my_empty(4),
      S => SR(0)
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[4]_i_1__0_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => SR(0)
    );
\my_full[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_full(1),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I5 => \my_full[0]_i_2__0_n_0\,
      O => \my_full[0]_i_1__0_n_0\
    );
\my_full[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00411400"
    )
        port map (
      I0 => my_full(1),
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      O => \my_full[0]_i_2__0_n_0\
    );
\my_full[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888988989988888"
    )
        port map (
      I0 => \my_full[1]_i_2__0_n_0\,
      I1 => my_full(1),
      I2 => rd_ptr(1),
      I3 => wr_ptr(1),
      I4 => wr_ptr(0),
      I5 => rd_ptr(0),
      O => \my_full[1]_i_1__0_n_0\
    );
\my_full[1]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      O => \my_full[1]_i_2__0_n_0\
    );
\my_full[1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I1 => \^q\(1),
      O => \^rd_ptr_reg[0]_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[0]_i_1__0_n_0\,
      Q => my_full(0),
      R => SR(0)
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[1]_i_1__0_n_0\,
      Q => my_full(1),
      R => SR(0)
    );
\not_strict_mode.app_rd_data[152]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[152]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(16)
    );
\not_strict_mode.app_rd_data[153]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[153]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(17)
    );
\not_strict_mode.app_rd_data[154]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[154]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(18)
    );
\not_strict_mode.app_rd_data[155]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[155]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(19)
    );
\not_strict_mode.app_rd_data[156]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[156]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(20)
    );
\not_strict_mode.app_rd_data[157]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[157]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(21)
    );
\not_strict_mode.app_rd_data[158]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[158]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(22)
    );
\not_strict_mode.app_rd_data[159]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[159]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(23)
    );
\not_strict_mode.app_rd_data[216]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[216]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(24)
    );
\not_strict_mode.app_rd_data[217]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[217]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(25)
    );
\not_strict_mode.app_rd_data[218]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[218]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(26)
    );
\not_strict_mode.app_rd_data[219]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[219]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(27)
    );
\not_strict_mode.app_rd_data[220]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[220]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(28)
    );
\not_strict_mode.app_rd_data[221]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[221]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(29)
    );
\not_strict_mode.app_rd_data[222]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[222]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(30)
    );
\not_strict_mode.app_rd_data[223]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[223]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(31)
    );
\not_strict_mode.app_rd_data[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[24]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(0)
    );
\not_strict_mode.app_rd_data[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[25]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(1)
    );
\not_strict_mode.app_rd_data[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[26]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(2)
    );
\not_strict_mode.app_rd_data[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[27]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(3)
    );
\not_strict_mode.app_rd_data[280]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[280]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(32)
    );
\not_strict_mode.app_rd_data[281]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[281]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(33)
    );
\not_strict_mode.app_rd_data[282]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[282]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(34)
    );
\not_strict_mode.app_rd_data[283]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[283]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(35)
    );
\not_strict_mode.app_rd_data[284]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[284]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(36)
    );
\not_strict_mode.app_rd_data[285]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[285]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(37)
    );
\not_strict_mode.app_rd_data[286]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[286]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(38)
    );
\not_strict_mode.app_rd_data[287]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[287]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(39)
    );
\not_strict_mode.app_rd_data[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[28]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(4)
    );
\not_strict_mode.app_rd_data[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[29]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(5)
    );
\not_strict_mode.app_rd_data[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[30]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(6)
    );
\not_strict_mode.app_rd_data[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[31]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(7)
    );
\not_strict_mode.app_rd_data[344]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[344]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(40)
    );
\not_strict_mode.app_rd_data[345]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[345]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(41)
    );
\not_strict_mode.app_rd_data[346]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[346]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(42)
    );
\not_strict_mode.app_rd_data[347]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[347]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(43)
    );
\not_strict_mode.app_rd_data[348]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[348]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(44)
    );
\not_strict_mode.app_rd_data[349]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[349]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(45)
    );
\not_strict_mode.app_rd_data[350]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[350]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(46)
    );
\not_strict_mode.app_rd_data[351]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[351]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(47)
    );
\not_strict_mode.app_rd_data[408]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[408]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(48)
    );
\not_strict_mode.app_rd_data[409]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[409]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(49)
    );
\not_strict_mode.app_rd_data[410]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[410]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(50)
    );
\not_strict_mode.app_rd_data[411]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[411]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(51)
    );
\not_strict_mode.app_rd_data[412]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[412]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(52)
    );
\not_strict_mode.app_rd_data[413]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[413]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(53)
    );
\not_strict_mode.app_rd_data[414]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[414]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(54)
    );
\not_strict_mode.app_rd_data[415]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[415]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(55)
    );
\not_strict_mode.app_rd_data[472]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[472]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(56)
    );
\not_strict_mode.app_rd_data[473]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[473]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(57)
    );
\not_strict_mode.app_rd_data[474]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[474]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(58)
    );
\not_strict_mode.app_rd_data[475]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[475]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(59)
    );
\not_strict_mode.app_rd_data[476]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[476]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(60)
    );
\not_strict_mode.app_rd_data[477]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[477]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(61)
    );
\not_strict_mode.app_rd_data[478]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[478]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(62)
    );
\not_strict_mode.app_rd_data[479]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[479]_0\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(63)
    );
\not_strict_mode.app_rd_data[88]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[88]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(8)
    );
\not_strict_mode.app_rd_data[89]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[89]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(9)
    );
\not_strict_mode.app_rd_data[90]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[90]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(10)
    );
\not_strict_mode.app_rd_data[91]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[91]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(11)
    );
\not_strict_mode.app_rd_data[92]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[92]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(12)
    );
\not_strict_mode.app_rd_data[93]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[93]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(13)
    );
\not_strict_mode.app_rd_data[94]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[94]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[479]\(14)
    );
\not_strict_mode.app_rd_data[95]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[95]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[479]\(15)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(49),
      I1 => my_empty(4),
      I2 => mem_out(49),
      O => \^not_strict_mode.app_rd_data_reg[89]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(57),
      I1 => my_empty(4),
      I2 => mem_out(57),
      O => \^not_strict_mode.app_rd_data_reg[88]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(1),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(1),
      O => \^not_strict_mode.app_rd_data_reg[95]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(9),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(9),
      O => \^not_strict_mode.app_rd_data_reg[94]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(17),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(17),
      O => \^not_strict_mode.app_rd_data_reg[93]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(25),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(25),
      O => \^not_strict_mode.app_rd_data_reg[92]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(33),
      I1 => my_empty(4),
      I2 => mem_out(33),
      O => \^not_strict_mode.app_rd_data_reg[91]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(41),
      I1 => my_empty(4),
      I2 => mem_out(41),
      O => \^not_strict_mode.app_rd_data_reg[90]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(34),
      I1 => my_empty(4),
      I2 => mem_out(34),
      O => \^not_strict_mode.app_rd_data_reg[155]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(42),
      I1 => my_empty(4),
      I2 => mem_out(42),
      O => \^not_strict_mode.app_rd_data_reg[154]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(50),
      I1 => my_empty(4),
      I2 => mem_out(50),
      O => \^not_strict_mode.app_rd_data_reg[153]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(58),
      I1 => my_empty(4),
      I2 => mem_out(58),
      O => \^not_strict_mode.app_rd_data_reg[152]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(2),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(2),
      O => \^not_strict_mode.app_rd_data_reg[159]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(10),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(10),
      O => \^not_strict_mode.app_rd_data_reg[158]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(18),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(18),
      O => \^not_strict_mode.app_rd_data_reg[157]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(26),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(26),
      O => \^not_strict_mode.app_rd_data_reg[156]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(19),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(19),
      O => \^not_strict_mode.app_rd_data_reg[221]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(27),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(27),
      O => \^not_strict_mode.app_rd_data_reg[220]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(35),
      I1 => my_empty(4),
      I2 => mem_out(35),
      O => \^not_strict_mode.app_rd_data_reg[219]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(43),
      I1 => my_empty(4),
      I2 => mem_out(43),
      O => \^not_strict_mode.app_rd_data_reg[218]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(51),
      I1 => my_empty(4),
      I2 => mem_out(51),
      O => \^not_strict_mode.app_rd_data_reg[217]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(59),
      I1 => my_empty(4),
      I2 => mem_out(59),
      O => \^not_strict_mode.app_rd_data_reg[216]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(3),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(3),
      O => \^not_strict_mode.app_rd_data_reg[223]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(11),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(11),
      O => \^not_strict_mode.app_rd_data_reg[222]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(52),
      I1 => my_empty(4),
      I2 => mem_out(52),
      O => \^not_strict_mode.app_rd_data_reg[281]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(60),
      I1 => my_empty(4),
      I2 => mem_out(60),
      O => \^not_strict_mode.app_rd_data_reg[280]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(4),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(4),
      O => \^not_strict_mode.app_rd_data_reg[287]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(12),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(12),
      O => \^not_strict_mode.app_rd_data_reg[286]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(20),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(20),
      O => \^not_strict_mode.app_rd_data_reg[285]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(28),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(28),
      O => \^not_strict_mode.app_rd_data_reg[284]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(36),
      I1 => my_empty(4),
      I2 => mem_out(36),
      O => \^not_strict_mode.app_rd_data_reg[283]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(44),
      I1 => my_empty(4),
      I2 => mem_out(44),
      O => \^not_strict_mode.app_rd_data_reg[282]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(16),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(16),
      O => \^not_strict_mode.app_rd_data_reg[29]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(24),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(24),
      O => \^not_strict_mode.app_rd_data_reg[28]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(32),
      I1 => my_empty(4),
      I2 => mem_out(32),
      O => \^not_strict_mode.app_rd_data_reg[27]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(40),
      I1 => my_empty(4),
      I2 => mem_out(40),
      O => \^not_strict_mode.app_rd_data_reg[26]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(48),
      I1 => my_empty(4),
      I2 => mem_out(48),
      O => \^not_strict_mode.app_rd_data_reg[25]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(56),
      I1 => my_empty(4),
      I2 => mem_out(56),
      O => \^not_strict_mode.app_rd_data_reg[24]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(37),
      I1 => my_empty(4),
      I2 => mem_out(37),
      O => \^not_strict_mode.app_rd_data_reg[347]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(45),
      I1 => my_empty(4),
      I2 => mem_out(45),
      O => \^not_strict_mode.app_rd_data_reg[346]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(53),
      I1 => my_empty(4),
      I2 => mem_out(53),
      O => \^not_strict_mode.app_rd_data_reg[345]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(61),
      I1 => my_empty(4),
      I2 => mem_out(61),
      O => \^not_strict_mode.app_rd_data_reg[344]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(5),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(5),
      O => \^not_strict_mode.app_rd_data_reg[351]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(13),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(13),
      O => \^not_strict_mode.app_rd_data_reg[350]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(21),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(21),
      O => \^not_strict_mode.app_rd_data_reg[349]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(29),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(29),
      O => \^not_strict_mode.app_rd_data_reg[348]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(0),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(0),
      O => \^not_strict_mode.app_rd_data_reg[31]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(8),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(8),
      O => \^not_strict_mode.app_rd_data_reg[30]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(22),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(22),
      O => \^not_strict_mode.app_rd_data_reg[413]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(30),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(30),
      O => \^not_strict_mode.app_rd_data_reg[412]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(38),
      I1 => my_empty(4),
      I2 => mem_out(38),
      O => \^not_strict_mode.app_rd_data_reg[411]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(46),
      I1 => my_empty(4),
      I2 => mem_out(46),
      O => \^not_strict_mode.app_rd_data_reg[410]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(54),
      I1 => my_empty(4),
      I2 => mem_out(54),
      O => \^not_strict_mode.app_rd_data_reg[409]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(62),
      I1 => my_empty(4),
      I2 => mem_out(62),
      O => \^not_strict_mode.app_rd_data_reg[408]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(6),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(6),
      O => \^not_strict_mode.app_rd_data_reg[415]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(14),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(14),
      O => \^not_strict_mode.app_rd_data_reg[414]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(55),
      I1 => my_empty(4),
      I2 => mem_out(55),
      O => \^not_strict_mode.app_rd_data_reg[473]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(63),
      I1 => my_empty(4),
      I2 => mem_out(63),
      O => \^not_strict_mode.app_rd_data_reg[472]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(7),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(7),
      O => \^not_strict_mode.app_rd_data_reg[479]_0\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(15),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(15),
      O => \^not_strict_mode.app_rd_data_reg[478]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(23),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(23),
      O => \^not_strict_mode.app_rd_data_reg[477]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(31),
      I1 => \my_empty_reg[4]_rep_n_0\,
      I2 => mem_out(31),
      O => \^not_strict_mode.app_rd_data_reg[476]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(39),
      I1 => my_empty(4),
      I2 => mem_out(39),
      O => \^not_strict_mode.app_rd_data_reg[475]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(47),
      I1 => my_empty(4),
      I2 => mem_out(47),
      O => \^not_strict_mode.app_rd_data_reg[474]\
    );
\rd_ptr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1_n_0\
    );
\rd_ptr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      O => \rd_ptr[1]_i_1_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1_n_0\,
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1_n_0\,
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF02"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr_timing(0),
      O => \rd_ptr_timing[0]_i_1__14_n_0\
    );
\rd_ptr_timing[1]_i_1__14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFD0220"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr_timing(1),
      O => \rd_ptr_timing[1]_i_1__14_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[0]_i_1__14_n_0\,
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr_timing[1]_i_1__14_n_0\,
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFCA0035"
    )
        port map (
      I0 => my_full(1),
      I1 => my_empty(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I4 => wr_ptr(0),
      O => \wr_ptr[0]_i_1__4_n_0\
    );
\wr_ptr[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF5DD00000A22"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => my_full(1),
      I2 => my_empty(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I5 => wr_ptr(1),
      O => \wr_ptr[1]_i_1__4_n_0\
    );
\wr_ptr[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^rd_ptr_reg[0]_0\,
      I1 => byte_rd_en_v_1,
      I2 => byte_rd_en_v_2,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      I5 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      O => \rd_ptr_reg[0]_1\
    );
\wr_ptr[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^rd_ptr_reg[0]_0\,
      I1 => byte_rd_en_v_1,
      I2 => byte_rd_en_v_2,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I5 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      O => \rd_ptr_reg[0]_2\
    );
\wr_ptr[1]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^rd_ptr_reg[0]_0\,
      I1 => byte_rd_en_v_1,
      I2 => byte_rd_en_v_2,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      I5 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      O => \rd_ptr_reg[0]_3\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__4_n_0\,
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__4_n_0\,
      Q => wr_ptr(1),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_6 is
  port (
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[48]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[50]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[52]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[54]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[112]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[114]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[116]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[118]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[176]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[178]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[180]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[182]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[240]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[242]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[244]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[246]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[304]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[306]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[308]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[310]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[368]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[370]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[372]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[374]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[432]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[434]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[436]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[438]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[496]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[498]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[500]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[502]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]_0\ : out STD_LOGIC;
    \my_empty_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    B_byte_rd_en : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    \my_empty_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    ififo_rst : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 67 downto 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_6 : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_6;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_6 is
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 8 );
  signal mem_reg_0_3_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_3_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_3_6_11_n_1 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^my_empty_reg[3]_0\ : STD_LOGIC;
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__6_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_3__2_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[112]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[113]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[114]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[115]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[116]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[117]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[118]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[119]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[176]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[177]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[178]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[179]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[180]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[181]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[182]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[183]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[240]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[241]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[242]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[243]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[244]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[245]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[246]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[247]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[304]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[305]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[306]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[307]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[308]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[309]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[310]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[311]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[368]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[369]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[370]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[371]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[372]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[373]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[374]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[375]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[432]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[433]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[434]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[435]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[436]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[437]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[438]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[439]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[48]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[496]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[497]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[498]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[499]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[49]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[500]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[501]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[502]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[503]_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[50]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[51]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[52]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[53]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[54]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[55]\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__5_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__10_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_2__1_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__13_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__13_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_2__6_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_78_79 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[0]_i_1__6\ : label is "soft_lutpair885";
  attribute SOFT_HLUTNM of \my_empty[2]_i_1__6\ : label is "soft_lutpair884";
  attribute SOFT_HLUTNM of \my_empty[3]_i_1__6\ : label is "soft_lutpair884";
  attribute SOFT_HLUTNM of \my_empty[4]_i_1__6\ : label is "soft_lutpair885";
  attribute SOFT_HLUTNM of \my_empty[4]_i_2__6\ : label is "soft_lutpair851";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[1]_i_3__2\ : label is "soft_lutpair849";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[112]_i_1\ : label is "soft_lutpair852";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[113]_i_1\ : label is "soft_lutpair853";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[114]_i_1\ : label is "soft_lutpair854";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[115]_i_1\ : label is "soft_lutpair855";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[116]_i_1\ : label is "soft_lutpair856";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[117]_i_1\ : label is "soft_lutpair857";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[118]_i_1\ : label is "soft_lutpair858";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[119]_i_1\ : label is "soft_lutpair859";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[176]_i_1\ : label is "soft_lutpair860";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[177]_i_1\ : label is "soft_lutpair860";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[178]_i_1\ : label is "soft_lutpair861";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[179]_i_1\ : label is "soft_lutpair861";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[180]_i_1\ : label is "soft_lutpair862";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[181]_i_1\ : label is "soft_lutpair862";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[182]_i_1\ : label is "soft_lutpair863";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[183]_i_1\ : label is "soft_lutpair863";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[240]_i_1\ : label is "soft_lutpair864";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[241]_i_1\ : label is "soft_lutpair864";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[242]_i_1\ : label is "soft_lutpair865";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[243]_i_1\ : label is "soft_lutpair865";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[244]_i_1\ : label is "soft_lutpair866";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[245]_i_1\ : label is "soft_lutpair866";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[246]_i_1\ : label is "soft_lutpair867";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[247]_i_1\ : label is "soft_lutpair867";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[304]_i_1\ : label is "soft_lutpair868";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[305]_i_1\ : label is "soft_lutpair868";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[306]_i_1\ : label is "soft_lutpair869";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[307]_i_1\ : label is "soft_lutpair869";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[308]_i_1\ : label is "soft_lutpair870";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[309]_i_1\ : label is "soft_lutpair871";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[310]_i_1\ : label is "soft_lutpair872";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[311]_i_1\ : label is "soft_lutpair870";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[368]_i_1\ : label is "soft_lutpair873";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[369]_i_1\ : label is "soft_lutpair871";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[370]_i_1\ : label is "soft_lutpair872";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[371]_i_1\ : label is "soft_lutpair873";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[372]_i_1\ : label is "soft_lutpair874";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[373]_i_1\ : label is "soft_lutpair874";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[374]_i_1\ : label is "soft_lutpair875";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[375]_i_1\ : label is "soft_lutpair875";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[432]_i_1\ : label is "soft_lutpair876";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[433]_i_1\ : label is "soft_lutpair876";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[434]_i_1\ : label is "soft_lutpair877";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[435]_i_1\ : label is "soft_lutpair877";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[436]_i_1\ : label is "soft_lutpair878";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[437]_i_1\ : label is "soft_lutpair878";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[438]_i_1\ : label is "soft_lutpair879";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[439]_i_1\ : label is "soft_lutpair879";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[48]_i_1\ : label is "soft_lutpair852";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[496]_i_1\ : label is "soft_lutpair880";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[497]_i_1\ : label is "soft_lutpair880";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[498]_i_1\ : label is "soft_lutpair881";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[499]_i_1\ : label is "soft_lutpair881";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[49]_i_1\ : label is "soft_lutpair853";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[500]_i_1\ : label is "soft_lutpair882";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[501]_i_1\ : label is "soft_lutpair882";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[502]_i_1\ : label is "soft_lutpair883";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[503]_i_1\ : label is "soft_lutpair883";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[50]_i_1\ : label is "soft_lutpair854";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[51]_i_1\ : label is "soft_lutpair855";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[52]_i_1\ : label is "soft_lutpair856";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[53]_i_1\ : label is "soft_lutpair857";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[54]_i_1\ : label is "soft_lutpair858";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[55]_i_1\ : label is "soft_lutpair859";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__1\ : label is "soft_lutpair851";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__5\ : label is "soft_lutpair848";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2__1\ : label is "soft_lutpair848";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_3__0\ : label is "soft_lutpair850";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_4__0\ : label is "soft_lutpair850";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_2__6\ : label is "soft_lutpair849";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \my_empty_reg[0]_0\(0) <= \^my_empty_reg[0]_0\(0);
  \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\;
  \not_strict_mode.app_rd_data_reg[112]\ <= \^not_strict_mode.app_rd_data_reg[112]\;
  \not_strict_mode.app_rd_data_reg[113]\ <= \^not_strict_mode.app_rd_data_reg[113]\;
  \not_strict_mode.app_rd_data_reg[114]\ <= \^not_strict_mode.app_rd_data_reg[114]\;
  \not_strict_mode.app_rd_data_reg[115]\ <= \^not_strict_mode.app_rd_data_reg[115]\;
  \not_strict_mode.app_rd_data_reg[116]\ <= \^not_strict_mode.app_rd_data_reg[116]\;
  \not_strict_mode.app_rd_data_reg[117]\ <= \^not_strict_mode.app_rd_data_reg[117]\;
  \not_strict_mode.app_rd_data_reg[118]\ <= \^not_strict_mode.app_rd_data_reg[118]\;
  \not_strict_mode.app_rd_data_reg[119]\ <= \^not_strict_mode.app_rd_data_reg[119]\;
  \not_strict_mode.app_rd_data_reg[176]\ <= \^not_strict_mode.app_rd_data_reg[176]\;
  \not_strict_mode.app_rd_data_reg[177]\ <= \^not_strict_mode.app_rd_data_reg[177]\;
  \not_strict_mode.app_rd_data_reg[178]\ <= \^not_strict_mode.app_rd_data_reg[178]\;
  \not_strict_mode.app_rd_data_reg[179]\ <= \^not_strict_mode.app_rd_data_reg[179]\;
  \not_strict_mode.app_rd_data_reg[180]\ <= \^not_strict_mode.app_rd_data_reg[180]\;
  \not_strict_mode.app_rd_data_reg[181]\ <= \^not_strict_mode.app_rd_data_reg[181]\;
  \not_strict_mode.app_rd_data_reg[182]\ <= \^not_strict_mode.app_rd_data_reg[182]\;
  \not_strict_mode.app_rd_data_reg[183]\ <= \^not_strict_mode.app_rd_data_reg[183]\;
  \not_strict_mode.app_rd_data_reg[240]\ <= \^not_strict_mode.app_rd_data_reg[240]\;
  \not_strict_mode.app_rd_data_reg[241]\ <= \^not_strict_mode.app_rd_data_reg[241]\;
  \not_strict_mode.app_rd_data_reg[242]\ <= \^not_strict_mode.app_rd_data_reg[242]\;
  \not_strict_mode.app_rd_data_reg[243]\ <= \^not_strict_mode.app_rd_data_reg[243]\;
  \not_strict_mode.app_rd_data_reg[244]\ <= \^not_strict_mode.app_rd_data_reg[244]\;
  \not_strict_mode.app_rd_data_reg[245]\ <= \^not_strict_mode.app_rd_data_reg[245]\;
  \not_strict_mode.app_rd_data_reg[246]\ <= \^not_strict_mode.app_rd_data_reg[246]\;
  \not_strict_mode.app_rd_data_reg[247]\ <= \^not_strict_mode.app_rd_data_reg[247]\;
  \not_strict_mode.app_rd_data_reg[304]\ <= \^not_strict_mode.app_rd_data_reg[304]\;
  \not_strict_mode.app_rd_data_reg[305]\ <= \^not_strict_mode.app_rd_data_reg[305]\;
  \not_strict_mode.app_rd_data_reg[306]\ <= \^not_strict_mode.app_rd_data_reg[306]\;
  \not_strict_mode.app_rd_data_reg[307]\ <= \^not_strict_mode.app_rd_data_reg[307]\;
  \not_strict_mode.app_rd_data_reg[308]\ <= \^not_strict_mode.app_rd_data_reg[308]\;
  \not_strict_mode.app_rd_data_reg[309]\ <= \^not_strict_mode.app_rd_data_reg[309]\;
  \not_strict_mode.app_rd_data_reg[310]\ <= \^not_strict_mode.app_rd_data_reg[310]\;
  \not_strict_mode.app_rd_data_reg[311]\ <= \^not_strict_mode.app_rd_data_reg[311]\;
  \not_strict_mode.app_rd_data_reg[368]\ <= \^not_strict_mode.app_rd_data_reg[368]\;
  \not_strict_mode.app_rd_data_reg[369]\ <= \^not_strict_mode.app_rd_data_reg[369]\;
  \not_strict_mode.app_rd_data_reg[370]\ <= \^not_strict_mode.app_rd_data_reg[370]\;
  \not_strict_mode.app_rd_data_reg[371]\ <= \^not_strict_mode.app_rd_data_reg[371]\;
  \not_strict_mode.app_rd_data_reg[372]\ <= \^not_strict_mode.app_rd_data_reg[372]\;
  \not_strict_mode.app_rd_data_reg[373]\ <= \^not_strict_mode.app_rd_data_reg[373]\;
  \not_strict_mode.app_rd_data_reg[374]\ <= \^not_strict_mode.app_rd_data_reg[374]\;
  \not_strict_mode.app_rd_data_reg[375]\ <= \^not_strict_mode.app_rd_data_reg[375]\;
  \not_strict_mode.app_rd_data_reg[432]\ <= \^not_strict_mode.app_rd_data_reg[432]\;
  \not_strict_mode.app_rd_data_reg[433]\ <= \^not_strict_mode.app_rd_data_reg[433]\;
  \not_strict_mode.app_rd_data_reg[434]\ <= \^not_strict_mode.app_rd_data_reg[434]\;
  \not_strict_mode.app_rd_data_reg[435]\ <= \^not_strict_mode.app_rd_data_reg[435]\;
  \not_strict_mode.app_rd_data_reg[436]\ <= \^not_strict_mode.app_rd_data_reg[436]\;
  \not_strict_mode.app_rd_data_reg[437]\ <= \^not_strict_mode.app_rd_data_reg[437]\;
  \not_strict_mode.app_rd_data_reg[438]\ <= \^not_strict_mode.app_rd_data_reg[438]\;
  \not_strict_mode.app_rd_data_reg[439]\ <= \^not_strict_mode.app_rd_data_reg[439]\;
  \not_strict_mode.app_rd_data_reg[48]\ <= \^not_strict_mode.app_rd_data_reg[48]\;
  \not_strict_mode.app_rd_data_reg[496]\ <= \^not_strict_mode.app_rd_data_reg[496]\;
  \not_strict_mode.app_rd_data_reg[497]\ <= \^not_strict_mode.app_rd_data_reg[497]\;
  \not_strict_mode.app_rd_data_reg[498]\ <= \^not_strict_mode.app_rd_data_reg[498]\;
  \not_strict_mode.app_rd_data_reg[499]\ <= \^not_strict_mode.app_rd_data_reg[499]\;
  \not_strict_mode.app_rd_data_reg[49]\ <= \^not_strict_mode.app_rd_data_reg[49]\;
  \not_strict_mode.app_rd_data_reg[500]\ <= \^not_strict_mode.app_rd_data_reg[500]\;
  \not_strict_mode.app_rd_data_reg[501]\ <= \^not_strict_mode.app_rd_data_reg[501]\;
  \not_strict_mode.app_rd_data_reg[502]\ <= \^not_strict_mode.app_rd_data_reg[502]\;
  \not_strict_mode.app_rd_data_reg[503]_0\ <= \^not_strict_mode.app_rd_data_reg[503]_0\;
  \not_strict_mode.app_rd_data_reg[50]\ <= \^not_strict_mode.app_rd_data_reg[50]\;
  \not_strict_mode.app_rd_data_reg[51]\ <= \^not_strict_mode.app_rd_data_reg[51]\;
  \not_strict_mode.app_rd_data_reg[52]\ <= \^not_strict_mode.app_rd_data_reg[52]\;
  \not_strict_mode.app_rd_data_reg[53]\ <= \^not_strict_mode.app_rd_data_reg[53]\;
  \not_strict_mode.app_rd_data_reg[54]\ <= \^not_strict_mode.app_rd_data_reg[54]\;
  \not_strict_mode.app_rd_data_reg[55]\ <= \^not_strict_mode.app_rd_data_reg[55]\;
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1) => mem_reg_0_3_36_41_n_4,
      DOC(0) => mem_reg_0_3_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => mem_out(65 downto 64),
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(67 downto 66),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_3_6_11_n_0,
      DOA(0) => mem_reg_0_3_6_11_n_1,
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_3_6_11_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_full(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(73 downto 72),
      DOB(1 downto 0) => mem_out(75 downto 74),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(67 downto 66),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[0]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^my_empty_reg[0]_0\(0),
      I1 => \my_empty[4]_i_2__6_n_0\,
      I2 => \my_empty[4]_i_3__0_n_0\,
      O => \my_empty[0]_i_1__6_n_0\
    );
\my_empty[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_empty[4]_i_2__6_n_0\,
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      I5 => my_empty(1),
      O => \my_empty[1]_i_1__6_n_0\
    );
\my_empty[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(2),
      I1 => \my_empty[4]_i_2__6_n_0\,
      I2 => \my_empty[4]_i_3__0_n_0\,
      O => \my_empty[2]_i_1__6_n_0\
    );
\my_empty[3]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\,
      I1 => \my_empty[4]_i_2__6_n_0\,
      I2 => \my_empty[4]_i_3__0_n_0\,
      O => \my_empty[3]_i_1__6_n_0\
    );
\my_empty[4]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(4),
      I1 => \my_empty[4]_i_2__6_n_0\,
      I2 => \my_empty[4]_i_3__0_n_0\,
      O => \my_empty[4]_i_1__6_n_0\
    );
\my_empty[4]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEBF"
    )
        port map (
      I0 => my_full(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(1),
      O => \my_empty[4]_i_2__6_n_0\
    );
\my_empty[4]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => wr_ptr(1),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => wr_ptr(0),
      I4 => my_empty(1),
      O => \my_empty[4]_i_3__0_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_empty[0]_i_1__6_n_0\,
      Q => \^my_empty_reg[0]_0\(0),
      S => ififo_rst
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_empty[1]_i_1__6_n_0\,
      Q => my_empty(1),
      S => ififo_rst
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_empty[2]_i_1__6_n_0\,
      Q => my_empty(2),
      S => ififo_rst
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_empty[3]_i_1__6_n_0\,
      Q => \^my_empty_reg[3]_0\,
      S => ififo_rst
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_empty[4]_i_1__6_n_0\,
      Q => my_empty(4),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_empty[4]_i_1__6_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I5 => \my_full[0]_i_2__5_n_0\,
      O => \my_full[0]_i_1__6_n_0\
    );
\my_full[0]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => rd_ptr(1),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => rd_ptr(0),
      I4 => my_full(1),
      O => \my_full[0]_i_2__5_n_0\
    );
\my_full[1]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => \my_full[1]_i_1__6_n_0\
    );
\my_full[1]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_full[1]_i_3__2_n_0\,
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      I5 => my_full(1),
      O => \my_full[1]_i_2__6_n_0\
    );
\my_full[1]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => \my_full[1]_i_3__2_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_full[0]_i_1__6_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \my_full[1]_i_2__6_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\not_strict_mode.app_rd_data[112]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[112]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(8)
    );
\not_strict_mode.app_rd_data[113]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[113]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(9)
    );
\not_strict_mode.app_rd_data[114]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[114]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(10)
    );
\not_strict_mode.app_rd_data[115]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[115]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(11)
    );
\not_strict_mode.app_rd_data[116]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[116]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(12)
    );
\not_strict_mode.app_rd_data[117]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[117]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(13)
    );
\not_strict_mode.app_rd_data[118]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[118]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(14)
    );
\not_strict_mode.app_rd_data[119]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[119]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(15)
    );
\not_strict_mode.app_rd_data[176]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[176]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(16)
    );
\not_strict_mode.app_rd_data[177]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[177]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(17)
    );
\not_strict_mode.app_rd_data[178]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[178]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(18)
    );
\not_strict_mode.app_rd_data[179]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[179]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(19)
    );
\not_strict_mode.app_rd_data[180]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[180]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(20)
    );
\not_strict_mode.app_rd_data[181]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[181]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(21)
    );
\not_strict_mode.app_rd_data[182]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[182]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(22)
    );
\not_strict_mode.app_rd_data[183]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[183]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(23)
    );
\not_strict_mode.app_rd_data[240]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[240]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(24)
    );
\not_strict_mode.app_rd_data[241]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[241]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(25)
    );
\not_strict_mode.app_rd_data[242]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[242]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(26)
    );
\not_strict_mode.app_rd_data[243]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[243]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(27)
    );
\not_strict_mode.app_rd_data[244]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[244]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(28)
    );
\not_strict_mode.app_rd_data[245]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[245]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(29)
    );
\not_strict_mode.app_rd_data[246]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[246]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(30)
    );
\not_strict_mode.app_rd_data[247]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[247]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(31)
    );
\not_strict_mode.app_rd_data[304]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[304]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(32)
    );
\not_strict_mode.app_rd_data[305]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[305]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(33)
    );
\not_strict_mode.app_rd_data[306]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[306]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(34)
    );
\not_strict_mode.app_rd_data[307]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[307]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(35)
    );
\not_strict_mode.app_rd_data[308]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[308]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(36)
    );
\not_strict_mode.app_rd_data[309]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[309]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(37)
    );
\not_strict_mode.app_rd_data[310]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[310]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(38)
    );
\not_strict_mode.app_rd_data[311]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[311]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(39)
    );
\not_strict_mode.app_rd_data[368]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[368]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(40)
    );
\not_strict_mode.app_rd_data[369]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[369]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(41)
    );
\not_strict_mode.app_rd_data[370]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[370]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(42)
    );
\not_strict_mode.app_rd_data[371]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[371]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(43)
    );
\not_strict_mode.app_rd_data[372]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[372]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(44)
    );
\not_strict_mode.app_rd_data[373]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[373]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(45)
    );
\not_strict_mode.app_rd_data[374]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[374]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(46)
    );
\not_strict_mode.app_rd_data[375]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[375]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(47)
    );
\not_strict_mode.app_rd_data[432]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[432]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(48)
    );
\not_strict_mode.app_rd_data[433]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[433]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(49)
    );
\not_strict_mode.app_rd_data[434]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[434]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(50)
    );
\not_strict_mode.app_rd_data[435]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[435]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(51)
    );
\not_strict_mode.app_rd_data[436]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[436]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(52)
    );
\not_strict_mode.app_rd_data[437]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[437]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(53)
    );
\not_strict_mode.app_rd_data[438]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[438]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(54)
    );
\not_strict_mode.app_rd_data[439]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[439]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(55)
    );
\not_strict_mode.app_rd_data[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[48]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(0)
    );
\not_strict_mode.app_rd_data[496]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[496]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(56)
    );
\not_strict_mode.app_rd_data[497]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[497]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(57)
    );
\not_strict_mode.app_rd_data[498]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[498]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(58)
    );
\not_strict_mode.app_rd_data[499]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[499]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(59)
    );
\not_strict_mode.app_rd_data[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[49]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(1)
    );
\not_strict_mode.app_rd_data[500]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[500]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(60)
    );
\not_strict_mode.app_rd_data[501]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[501]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(61)
    );
\not_strict_mode.app_rd_data[502]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[502]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(62)
    );
\not_strict_mode.app_rd_data[503]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[503]_0\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(63)
    );
\not_strict_mode.app_rd_data[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[50]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(2)
    );
\not_strict_mode.app_rd_data[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[51]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(3)
    );
\not_strict_mode.app_rd_data[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[52]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(4)
    );
\not_strict_mode.app_rd_data[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[53]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(5)
    );
\not_strict_mode.app_rd_data[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[54]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[503]\(6)
    );
\not_strict_mode.app_rd_data[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[55]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[503]\(7)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(53),
      I1 => mem_out(65),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[113]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(61),
      I1 => mem_out(73),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[112]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(3),
      I1 => mem_out(9),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[119]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(11),
      I1 => mem_out(17),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[118]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(19),
      I1 => mem_out(25),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[117]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(27),
      I1 => mem_out(33),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[116]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(37),
      I1 => mem_out(49),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[115]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(45),
      I1 => mem_out(57),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[114]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(38),
      I1 => mem_out(50),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[179]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(46),
      I1 => mem_out(58),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[178]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(54),
      I1 => mem_out(66),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[177]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(62),
      I1 => mem_out(74),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[176]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(4),
      I1 => mem_out(10),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[183]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(12),
      I1 => mem_out(18),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[182]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(20),
      I1 => mem_out(26),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[181]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(28),
      I1 => mem_out(34),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[180]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(21),
      I1 => mem_out(27),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[245]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(29),
      I1 => mem_out(35),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[244]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(39),
      I1 => mem_out(51),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[243]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(47),
      I1 => mem_out(59),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[242]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(55),
      I1 => mem_out(67),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[241]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(63),
      I1 => mem_out(75),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[240]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(5),
      I1 => mem_out(11),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[247]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(13),
      I1 => mem_out(19),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[246]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(56),
      I1 => mem_out(68),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[305]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(64),
      I1 => mem_out(76),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[304]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(6),
      I1 => mem_out(12),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[311]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(14),
      I1 => mem_out(20),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[310]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(22),
      I1 => mem_out(28),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[309]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(30),
      I1 => mem_out(36),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[308]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(40),
      I1 => mem_out(52),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[307]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(48),
      I1 => mem_out(60),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[306]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(41),
      I1 => mem_out(53),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[371]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(49),
      I1 => mem_out(61),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[370]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(57),
      I1 => mem_out(69),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[369]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(65),
      I1 => mem_out(77),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[368]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(7),
      I1 => mem_out(13),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[375]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(15),
      I1 => mem_out(21),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[374]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(23),
      I1 => mem_out(29),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[373]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(31),
      I1 => mem_out(37),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[372]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(24),
      I1 => mem_out(30),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[437]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(32),
      I1 => mem_out(38),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[436]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(42),
      I1 => mem_out(54),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[435]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(50),
      I1 => mem_out(62),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[434]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(58),
      I1 => mem_out(70),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[433]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(66),
      I1 => mem_out(78),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[432]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(8),
      I1 => mem_out(14),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[439]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(16),
      I1 => mem_out(22),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[438]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(59),
      I1 => mem_out(71),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[497]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(67),
      I1 => mem_out(79),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[496]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(9),
      I1 => mem_out(15),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[503]_0\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(17),
      I1 => mem_out(23),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[502]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(25),
      I1 => mem_out(31),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[501]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(33),
      I1 => mem_out(39),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[500]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(43),
      I1 => mem_out(55),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[499]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(51),
      I1 => mem_out(63),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[498]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(18),
      I1 => mem_out(24),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[53]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(26),
      I1 => mem_out(32),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[52]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(36),
      I1 => mem_out(48),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[51]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(44),
      I1 => mem_out(56),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[50]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(52),
      I1 => mem_out(64),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[49]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(60),
      I1 => mem_out(72),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[48]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(2),
      I1 => mem_out(8),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[55]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(10),
      I1 => mem_out(16),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[54]\
    );
\rd_ptr[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__1_n_0\
    );
\rd_ptr[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000B4F0"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => ififo_rst,
      O => \rd_ptr[1]_i_1__5_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1__1_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1__5_n_0\,
      Q => rd_ptr(1),
      R => '0'
    );
\rd_ptr_timing[0]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EF0F0000FFFF10F0"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(0),
      I5 => rd_ptr(0),
      O => \rd_ptr_timing[0]_i_1__10_n_0\
    );
\rd_ptr_timing[1]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10F0EF0F0000"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      I5 => \rd_ptr_timing[1]_i_2__1_n_0\,
      O => \rd_ptr_timing[1]_i_1__10_n_0\
    );
\rd_ptr_timing[1]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \rd_ptr_timing[1]_i_2__1_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \rd_ptr_timing[0]_i_1__10_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__6_n_0\,
      D => \rd_ptr_timing[1]_i_1__10_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAA965"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I5 => ififo_rst,
      O => \wr_ptr[0]_i_1__13_n_0\
    );
\wr_ptr[0]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \^my_empty_reg[3]_0\,
      O => B_byte_rd_en
    );
\wr_ptr[0]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => \my_empty_reg[3]_1\(0),
      I3 => if_empty_r_0(0),
      O => \rd_ptr_timing_reg[0]_0\
    );
\wr_ptr[1]_i_1__13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => wr_ptr(1),
      I1 => \wr_ptr[1]_i_2__6_n_0\,
      I2 => wr_ptr(0),
      I3 => ififo_rst,
      O => \wr_ptr[1]_i_1__13_n_0\
    );
\wr_ptr[1]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1105"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => \wr_ptr[1]_i_2__6_n_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__13_n_0\,
      Q => wr_ptr(0),
      R => '0'
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__13_n_0\,
      Q => wr_ptr(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_8 is
  port (
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[56]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[58]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[60]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[62]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[120]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[122]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[124]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[126]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[184]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[186]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[188]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[190]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[248]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[250]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[252]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[254]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[312]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[314]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[316]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[318]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[376]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[378]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[380]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[382]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[440]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[442]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[444]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[446]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[504]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[506]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[508]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[510]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC;
    \my_empty_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    A_byte_rd_en : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    ififo_rst : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 65 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_8 : entity is "mig_7series_v2_3_ddr_if_post_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_8;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_8 is
  signal mem_out : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal mem_reg_0_3_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_3_60_65_n_5 : STD_LOGIC;
  signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \my_empty[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \my_empty[4]_i_3_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[3]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC;
  signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \my_full[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_full[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \my_full[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[120]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[121]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[122]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[123]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[124]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[125]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[126]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[127]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[184]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[185]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[186]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[187]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[188]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[189]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[190]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[191]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[248]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[249]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[250]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[251]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[252]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[253]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[254]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[255]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[312]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[313]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[314]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[315]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[316]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[317]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[318]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[319]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[376]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[377]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[378]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[379]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[380]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[381]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[382]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[383]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[440]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[441]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[442]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[443]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[444]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[445]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[446]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[447]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[504]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[505]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[506]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[507]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[508]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[509]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[510]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[511]_0\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[56]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[57]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[58]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[59]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[60]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[61]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[62]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[63]\ : STD_LOGIC;
  signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rd_ptr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rd_ptr[1]_i_1__4_n_0\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal \rd_ptr_timing[0]_i_1__9_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_1__9_n_0\ : STD_LOGIC;
  signal \rd_ptr_timing[1]_i_2__0_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "40";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  attribute syn_maxfan of wr_en : signal is "10";
  signal wr_ptr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wr_ptr[0]_i_1__12_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_1__12_n_0\ : STD_LOGIC;
  signal \wr_ptr[1]_i_2__5_n_0\ : STD_LOGIC;
  signal NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_3_6_11 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[0]_i_1__5\ : label is "soft_lutpair831";
  attribute SOFT_HLUTNM of \my_empty[2]_i_1__5\ : label is "soft_lutpair830";
  attribute SOFT_HLUTNM of \my_empty[3]_i_1__5\ : label is "soft_lutpair830";
  attribute SOFT_HLUTNM of \my_empty[4]_i_1__5\ : label is "soft_lutpair831";
  attribute SOFT_HLUTNM of \my_empty[4]_i_2__5\ : label is "soft_lutpair797";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1;
  attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]";
  attribute SOFT_HLUTNM of \my_full[1]_i_3__1\ : label is "soft_lutpair796";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[120]_i_1\ : label is "soft_lutpair798";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[121]_i_1\ : label is "soft_lutpair799";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[122]_i_1\ : label is "soft_lutpair800";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[123]_i_1\ : label is "soft_lutpair801";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[124]_i_1\ : label is "soft_lutpair802";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[125]_i_1\ : label is "soft_lutpair804";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[126]_i_1\ : label is "soft_lutpair805";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[127]_i_1\ : label is "soft_lutpair805";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[184]_i_1\ : label is "soft_lutpair806";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[185]_i_1\ : label is "soft_lutpair806";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[186]_i_1\ : label is "soft_lutpair807";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[187]_i_1\ : label is "soft_lutpair807";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[188]_i_1\ : label is "soft_lutpair808";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[189]_i_1\ : label is "soft_lutpair809";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[190]_i_1\ : label is "soft_lutpair808";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[191]_i_1\ : label is "soft_lutpair809";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[248]_i_1\ : label is "soft_lutpair810";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[249]_i_1\ : label is "soft_lutpair810";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[250]_i_1\ : label is "soft_lutpair811";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[251]_i_1\ : label is "soft_lutpair811";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[252]_i_1\ : label is "soft_lutpair812";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[253]_i_1\ : label is "soft_lutpair812";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[254]_i_1\ : label is "soft_lutpair813";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[255]_i_1\ : label is "soft_lutpair813";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[312]_i_1\ : label is "soft_lutpair814";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[313]_i_1\ : label is "soft_lutpair814";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[314]_i_1\ : label is "soft_lutpair815";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[315]_i_1\ : label is "soft_lutpair815";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[316]_i_1\ : label is "soft_lutpair816";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[317]_i_1\ : label is "soft_lutpair817";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[318]_i_1\ : label is "soft_lutpair818";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[319]_i_1\ : label is "soft_lutpair816";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[376]_i_1\ : label is "soft_lutpair817";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[377]_i_1\ : label is "soft_lutpair818";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[378]_i_1\ : label is "soft_lutpair819";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[379]_i_1\ : label is "soft_lutpair819";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[380]_i_1\ : label is "soft_lutpair820";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[381]_i_1\ : label is "soft_lutpair820";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[382]_i_1\ : label is "soft_lutpair821";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[383]_i_1\ : label is "soft_lutpair821";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[440]_i_1\ : label is "soft_lutpair822";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[441]_i_1\ : label is "soft_lutpair822";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[442]_i_1\ : label is "soft_lutpair823";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[443]_i_1\ : label is "soft_lutpair823";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[444]_i_1\ : label is "soft_lutpair824";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[445]_i_1\ : label is "soft_lutpair824";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[446]_i_1\ : label is "soft_lutpair825";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[447]_i_1\ : label is "soft_lutpair825";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[504]_i_1\ : label is "soft_lutpair826";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[505]_i_1\ : label is "soft_lutpair826";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[506]_i_1\ : label is "soft_lutpair827";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[507]_i_1\ : label is "soft_lutpair827";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[508]_i_1\ : label is "soft_lutpair828";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[509]_i_1\ : label is "soft_lutpair828";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[510]_i_1\ : label is "soft_lutpair829";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[511]_i_1\ : label is "soft_lutpair829";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[56]_i_1\ : label is "soft_lutpair798";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[57]_i_1\ : label is "soft_lutpair799";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[58]_i_1\ : label is "soft_lutpair800";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[59]_i_1\ : label is "soft_lutpair801";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[60]_i_1\ : label is "soft_lutpair802";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[61]_i_1\ : label is "soft_lutpair803";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[62]_i_1\ : label is "soft_lutpair804";
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data[63]_i_1\ : label is "soft_lutpair803";
  attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__0\ : label is "soft_lutpair797";
  attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__4\ : label is "soft_lutpair795";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2__0\ : label is "soft_lutpair795";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_2__5\ : label is "soft_lutpair796";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
begin
  \my_empty_reg[3]_0\(1 downto 0) <= \^my_empty_reg[3]_0\(1 downto 0);
  \not_strict_mode.app_rd_data_reg[120]\ <= \^not_strict_mode.app_rd_data_reg[120]\;
  \not_strict_mode.app_rd_data_reg[121]\ <= \^not_strict_mode.app_rd_data_reg[121]\;
  \not_strict_mode.app_rd_data_reg[122]\ <= \^not_strict_mode.app_rd_data_reg[122]\;
  \not_strict_mode.app_rd_data_reg[123]\ <= \^not_strict_mode.app_rd_data_reg[123]\;
  \not_strict_mode.app_rd_data_reg[124]\ <= \^not_strict_mode.app_rd_data_reg[124]\;
  \not_strict_mode.app_rd_data_reg[125]\ <= \^not_strict_mode.app_rd_data_reg[125]\;
  \not_strict_mode.app_rd_data_reg[126]\ <= \^not_strict_mode.app_rd_data_reg[126]\;
  \not_strict_mode.app_rd_data_reg[127]\ <= \^not_strict_mode.app_rd_data_reg[127]\;
  \not_strict_mode.app_rd_data_reg[184]\ <= \^not_strict_mode.app_rd_data_reg[184]\;
  \not_strict_mode.app_rd_data_reg[185]\ <= \^not_strict_mode.app_rd_data_reg[185]\;
  \not_strict_mode.app_rd_data_reg[186]\ <= \^not_strict_mode.app_rd_data_reg[186]\;
  \not_strict_mode.app_rd_data_reg[187]\ <= \^not_strict_mode.app_rd_data_reg[187]\;
  \not_strict_mode.app_rd_data_reg[188]\ <= \^not_strict_mode.app_rd_data_reg[188]\;
  \not_strict_mode.app_rd_data_reg[189]\ <= \^not_strict_mode.app_rd_data_reg[189]\;
  \not_strict_mode.app_rd_data_reg[190]\ <= \^not_strict_mode.app_rd_data_reg[190]\;
  \not_strict_mode.app_rd_data_reg[191]\ <= \^not_strict_mode.app_rd_data_reg[191]\;
  \not_strict_mode.app_rd_data_reg[248]\ <= \^not_strict_mode.app_rd_data_reg[248]\;
  \not_strict_mode.app_rd_data_reg[249]\ <= \^not_strict_mode.app_rd_data_reg[249]\;
  \not_strict_mode.app_rd_data_reg[250]\ <= \^not_strict_mode.app_rd_data_reg[250]\;
  \not_strict_mode.app_rd_data_reg[251]\ <= \^not_strict_mode.app_rd_data_reg[251]\;
  \not_strict_mode.app_rd_data_reg[252]\ <= \^not_strict_mode.app_rd_data_reg[252]\;
  \not_strict_mode.app_rd_data_reg[253]\ <= \^not_strict_mode.app_rd_data_reg[253]\;
  \not_strict_mode.app_rd_data_reg[254]\ <= \^not_strict_mode.app_rd_data_reg[254]\;
  \not_strict_mode.app_rd_data_reg[255]\ <= \^not_strict_mode.app_rd_data_reg[255]\;
  \not_strict_mode.app_rd_data_reg[312]\ <= \^not_strict_mode.app_rd_data_reg[312]\;
  \not_strict_mode.app_rd_data_reg[313]\ <= \^not_strict_mode.app_rd_data_reg[313]\;
  \not_strict_mode.app_rd_data_reg[314]\ <= \^not_strict_mode.app_rd_data_reg[314]\;
  \not_strict_mode.app_rd_data_reg[315]\ <= \^not_strict_mode.app_rd_data_reg[315]\;
  \not_strict_mode.app_rd_data_reg[316]\ <= \^not_strict_mode.app_rd_data_reg[316]\;
  \not_strict_mode.app_rd_data_reg[317]\ <= \^not_strict_mode.app_rd_data_reg[317]\;
  \not_strict_mode.app_rd_data_reg[318]\ <= \^not_strict_mode.app_rd_data_reg[318]\;
  \not_strict_mode.app_rd_data_reg[319]\ <= \^not_strict_mode.app_rd_data_reg[319]\;
  \not_strict_mode.app_rd_data_reg[376]\ <= \^not_strict_mode.app_rd_data_reg[376]\;
  \not_strict_mode.app_rd_data_reg[377]\ <= \^not_strict_mode.app_rd_data_reg[377]\;
  \not_strict_mode.app_rd_data_reg[378]\ <= \^not_strict_mode.app_rd_data_reg[378]\;
  \not_strict_mode.app_rd_data_reg[379]\ <= \^not_strict_mode.app_rd_data_reg[379]\;
  \not_strict_mode.app_rd_data_reg[380]\ <= \^not_strict_mode.app_rd_data_reg[380]\;
  \not_strict_mode.app_rd_data_reg[381]\ <= \^not_strict_mode.app_rd_data_reg[381]\;
  \not_strict_mode.app_rd_data_reg[382]\ <= \^not_strict_mode.app_rd_data_reg[382]\;
  \not_strict_mode.app_rd_data_reg[383]\ <= \^not_strict_mode.app_rd_data_reg[383]\;
  \not_strict_mode.app_rd_data_reg[440]\ <= \^not_strict_mode.app_rd_data_reg[440]\;
  \not_strict_mode.app_rd_data_reg[441]\ <= \^not_strict_mode.app_rd_data_reg[441]\;
  \not_strict_mode.app_rd_data_reg[442]\ <= \^not_strict_mode.app_rd_data_reg[442]\;
  \not_strict_mode.app_rd_data_reg[443]\ <= \^not_strict_mode.app_rd_data_reg[443]\;
  \not_strict_mode.app_rd_data_reg[444]\ <= \^not_strict_mode.app_rd_data_reg[444]\;
  \not_strict_mode.app_rd_data_reg[445]\ <= \^not_strict_mode.app_rd_data_reg[445]\;
  \not_strict_mode.app_rd_data_reg[446]\ <= \^not_strict_mode.app_rd_data_reg[446]\;
  \not_strict_mode.app_rd_data_reg[447]\ <= \^not_strict_mode.app_rd_data_reg[447]\;
  \not_strict_mode.app_rd_data_reg[504]\ <= \^not_strict_mode.app_rd_data_reg[504]\;
  \not_strict_mode.app_rd_data_reg[505]\ <= \^not_strict_mode.app_rd_data_reg[505]\;
  \not_strict_mode.app_rd_data_reg[506]\ <= \^not_strict_mode.app_rd_data_reg[506]\;
  \not_strict_mode.app_rd_data_reg[507]\ <= \^not_strict_mode.app_rd_data_reg[507]\;
  \not_strict_mode.app_rd_data_reg[508]\ <= \^not_strict_mode.app_rd_data_reg[508]\;
  \not_strict_mode.app_rd_data_reg[509]\ <= \^not_strict_mode.app_rd_data_reg[509]\;
  \not_strict_mode.app_rd_data_reg[510]\ <= \^not_strict_mode.app_rd_data_reg[510]\;
  \not_strict_mode.app_rd_data_reg[511]_0\ <= \^not_strict_mode.app_rd_data_reg[511]_0\;
  \not_strict_mode.app_rd_data_reg[56]\ <= \^not_strict_mode.app_rd_data_reg[56]\;
  \not_strict_mode.app_rd_data_reg[57]\ <= \^not_strict_mode.app_rd_data_reg[57]\;
  \not_strict_mode.app_rd_data_reg[58]\ <= \^not_strict_mode.app_rd_data_reg[58]\;
  \not_strict_mode.app_rd_data_reg[59]\ <= \^not_strict_mode.app_rd_data_reg[59]\;
  \not_strict_mode.app_rd_data_reg[60]\ <= \^not_strict_mode.app_rd_data_reg[60]\;
  \not_strict_mode.app_rd_data_reg[61]\ <= \^not_strict_mode.app_rd_data_reg[61]\;
  \not_strict_mode.app_rd_data_reg[62]\ <= \^not_strict_mode.app_rd_data_reg[62]\;
  \not_strict_mode.app_rd_data_reg[63]\ <= \^not_strict_mode.app_rd_data_reg[63]\;
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[120]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[248]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[376]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[504]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[56]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[184]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[312]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[440]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[121]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[249]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[377]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[505]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[57]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[185]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[313]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[441]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[122]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[250]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[378]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[506]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[58]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[186]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[314]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[442]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[123]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[251]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[379]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[507]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[59]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[187]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[315]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[443]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[124]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[252]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[380]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[508]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[60]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[188]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[316]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[444]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[125]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[253]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[381]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[509]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[61]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[189]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[317]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[445]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[126]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[254]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[382]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[510]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[62]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[190]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[318]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[446]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[127]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[255]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[383]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[511]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[63]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[191]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[319]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[447]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      I2 => \po_stg2_wrcal_cnt_reg[1]\(1),
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      I4 => \po_stg2_wrcal_cnt_reg[1]\(0),
      I5 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\
    );
mem_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(1 downto 0),
      DIB(1 downto 0) => Q(3 downto 2),
      DIC(1 downto 0) => Q(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(1 downto 0),
      DOB(1 downto 0) => mem_out(3 downto 2),
      DOC(1 downto 0) => mem_out(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_3_0_5_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_full(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(2),
      O => wr_en
    );
mem_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(13 downto 12),
      DIB(1 downto 0) => Q(15 downto 14),
      DIC(1 downto 0) => Q(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => mem_out(17 downto 16),
      DOD(1 downto 0) => NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(19 downto 18),
      DIB(1 downto 0) => Q(21 downto 20),
      DIC(1 downto 0) => Q(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(19 downto 18),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(25 downto 24),
      DIB(1 downto 0) => Q(27 downto 26),
      DIC(1 downto 0) => Q(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(25 downto 24),
      DOB(1 downto 0) => mem_out(27 downto 26),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(31 downto 30),
      DIB(1 downto 0) => Q(33 downto 32),
      DIC(1 downto 0) => Q(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(37 downto 36),
      DIB(1 downto 0) => Q(39 downto 38),
      DIC(1 downto 0) => Q(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => mem_out(41 downto 40),
      DOD(1 downto 0) => NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(43 downto 42),
      DIB(1 downto 0) => Q(45 downto 44),
      DIC(1 downto 0) => Q(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(43 downto 42),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(49 downto 48),
      DIB(1 downto 0) => Q(51 downto 50),
      DIC(1 downto 0) => Q(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(49 downto 48),
      DOB(1 downto 0) => mem_out(51 downto 50),
      DOC(1 downto 0) => mem_out(53 downto 52),
      DOD(1 downto 0) => NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(55 downto 54),
      DIB(1 downto 0) => Q(57 downto 56),
      DIC(1 downto 0) => Q(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(55 downto 54),
      DOB(1 downto 0) => mem_out(57 downto 56),
      DOC(1 downto 0) => mem_out(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(61 downto 60),
      DIB(1 downto 0) => Q(63 downto 62),
      DIC(1 downto 0) => Q(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1) => mem_reg_0_3_60_65_n_4,
      DOC(0) => mem_reg_0_3_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => rd_ptr_timing(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => wr_ptr(1 downto 0),
      DIA(1 downto 0) => Q(7 downto 6),
      DIB(1 downto 0) => Q(9 downto 8),
      DIC(1 downto 0) => Q(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(7 downto 6),
      DOB(1 downto 0) => mem_out(9 downto 8),
      DOC(1 downto 0) => mem_out(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[0]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\(0),
      I1 => \my_empty[4]_i_2__5_n_0\,
      I2 => \my_empty[4]_i_3_n_0\,
      O => \my_empty[0]_i_1__5_n_0\
    );
\my_empty[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_empty[4]_i_2__5_n_0\,
      I1 => wr_ptr(1),
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => wr_ptr(0),
      I5 => my_empty(1),
      O => \my_empty[1]_i_1__5_n_0\
    );
\my_empty[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(2),
      I1 => \my_empty[4]_i_2__5_n_0\,
      I2 => \my_empty[4]_i_3_n_0\,
      O => \my_empty[2]_i_1__5_n_0\
    );
\my_empty[3]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^my_empty_reg[3]_0\(1),
      I1 => \my_empty[4]_i_2__5_n_0\,
      I2 => \my_empty[4]_i_3_n_0\,
      O => \my_empty[3]_i_1__5_n_0\
    );
\my_empty[4]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => my_empty(4),
      I1 => \my_empty[4]_i_2__5_n_0\,
      I2 => \my_empty[4]_i_3_n_0\,
      O => \my_empty[4]_i_1__5_n_0\
    );
\my_empty[4]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEBF"
    )
        port map (
      I0 => my_full(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(1),
      O => \my_empty[4]_i_2__5_n_0\
    );
\my_empty[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => wr_ptr(1),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => wr_ptr(0),
      I4 => my_empty(1),
      O => \my_empty[4]_i_3_n_0\
    );
\my_empty_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_empty[0]_i_1__5_n_0\,
      Q => \^my_empty_reg[3]_0\(0),
      S => ififo_rst
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_empty[1]_i_1__5_n_0\,
      Q => my_empty(1),
      S => ififo_rst
    );
\my_empty_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_empty[2]_i_1__5_n_0\,
      Q => my_empty(2),
      S => ififo_rst
    );
\my_empty_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_empty[3]_i_1__5_n_0\,
      Q => \^my_empty_reg[3]_0\(1),
      S => ififo_rst
    );
\my_empty_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_empty[4]_i_1__5_n_0\,
      Q => my_empty(4),
      S => ififo_rst
    );
\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_empty[4]_i_1__5_n_0\,
      Q => \my_empty_reg[4]_rep_n_0\,
      S => ififo_rst
    );
\my_full[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAB8AAAAAA8"
    )
        port map (
      I0 => my_full(0),
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I5 => \my_full[0]_i_2__4_n_0\,
      O => \my_full[0]_i_1__5_n_0\
    );
\my_full[0]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000960"
    )
        port map (
      I0 => rd_ptr(1),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => rd_ptr(0),
      I4 => my_full(1),
      O => \my_full[0]_i_2__4_n_0\
    );
\my_full[1]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => \my_full[1]_i_1__5_n_0\
    );
\my_full[1]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00411400"
    )
        port map (
      I0 => \my_full[1]_i_3__1_n_0\,
      I1 => rd_ptr(1),
      I2 => wr_ptr(1),
      I3 => wr_ptr(0),
      I4 => rd_ptr(0),
      I5 => my_full(1),
      O => \my_full[1]_i_2__5_n_0\
    );
\my_full[1]_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFE"
    )
        port map (
      I0 => my_empty(1),
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => \my_full[1]_i_3__1_n_0\
    );
\my_full_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_full[0]_i_1__5_n_0\,
      Q => my_full(0),
      R => ififo_rst
    );
\my_full_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \my_full[1]_i_2__5_n_0\,
      Q => my_full(1),
      R => ififo_rst
    );
\not_strict_mode.app_rd_data[120]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[120]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(8)
    );
\not_strict_mode.app_rd_data[121]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[121]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(9)
    );
\not_strict_mode.app_rd_data[122]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[122]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(10)
    );
\not_strict_mode.app_rd_data[123]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[123]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(11)
    );
\not_strict_mode.app_rd_data[124]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[124]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(12)
    );
\not_strict_mode.app_rd_data[125]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[125]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(13)
    );
\not_strict_mode.app_rd_data[126]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[126]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(14)
    );
\not_strict_mode.app_rd_data[127]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[127]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(15)
    );
\not_strict_mode.app_rd_data[184]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[184]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(16)
    );
\not_strict_mode.app_rd_data[185]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[185]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(17)
    );
\not_strict_mode.app_rd_data[186]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[186]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(18)
    );
\not_strict_mode.app_rd_data[187]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[187]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(19)
    );
\not_strict_mode.app_rd_data[188]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[188]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(20)
    );
\not_strict_mode.app_rd_data[189]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[189]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(21)
    );
\not_strict_mode.app_rd_data[190]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[190]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(22)
    );
\not_strict_mode.app_rd_data[191]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[191]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(23)
    );
\not_strict_mode.app_rd_data[248]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[248]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(24)
    );
\not_strict_mode.app_rd_data[249]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[249]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(25)
    );
\not_strict_mode.app_rd_data[250]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[250]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(26)
    );
\not_strict_mode.app_rd_data[251]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[251]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(27)
    );
\not_strict_mode.app_rd_data[252]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[252]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(28)
    );
\not_strict_mode.app_rd_data[253]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[253]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(29)
    );
\not_strict_mode.app_rd_data[254]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[254]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(30)
    );
\not_strict_mode.app_rd_data[255]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[255]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(31)
    );
\not_strict_mode.app_rd_data[312]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[312]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(32)
    );
\not_strict_mode.app_rd_data[313]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[313]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(33)
    );
\not_strict_mode.app_rd_data[314]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[314]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(34)
    );
\not_strict_mode.app_rd_data[315]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[315]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(35)
    );
\not_strict_mode.app_rd_data[316]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[316]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(36)
    );
\not_strict_mode.app_rd_data[317]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[317]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(37)
    );
\not_strict_mode.app_rd_data[318]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[318]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(38)
    );
\not_strict_mode.app_rd_data[319]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[319]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(39)
    );
\not_strict_mode.app_rd_data[376]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[376]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(40)
    );
\not_strict_mode.app_rd_data[377]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[377]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(41)
    );
\not_strict_mode.app_rd_data[378]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[378]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(42)
    );
\not_strict_mode.app_rd_data[379]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[379]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(43)
    );
\not_strict_mode.app_rd_data[380]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[380]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(44)
    );
\not_strict_mode.app_rd_data[381]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[381]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(45)
    );
\not_strict_mode.app_rd_data[382]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[382]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(46)
    );
\not_strict_mode.app_rd_data[383]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[383]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(47)
    );
\not_strict_mode.app_rd_data[440]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[440]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(48)
    );
\not_strict_mode.app_rd_data[441]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[441]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(49)
    );
\not_strict_mode.app_rd_data[442]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[442]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(50)
    );
\not_strict_mode.app_rd_data[443]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[443]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(51)
    );
\not_strict_mode.app_rd_data[444]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[444]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(52)
    );
\not_strict_mode.app_rd_data[445]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[445]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(53)
    );
\not_strict_mode.app_rd_data[446]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[446]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(54)
    );
\not_strict_mode.app_rd_data[447]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[447]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(55)
    );
\not_strict_mode.app_rd_data[504]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[504]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(56)
    );
\not_strict_mode.app_rd_data[505]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[505]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(57)
    );
\not_strict_mode.app_rd_data[506]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[506]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(58)
    );
\not_strict_mode.app_rd_data[507]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[507]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(59)
    );
\not_strict_mode.app_rd_data[508]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[508]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(60)
    );
\not_strict_mode.app_rd_data[509]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[509]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(61)
    );
\not_strict_mode.app_rd_data[510]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[510]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(62)
    );
\not_strict_mode.app_rd_data[511]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[511]_0\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(63)
    );
\not_strict_mode.app_rd_data[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[56]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(0)
    );
\not_strict_mode.app_rd_data[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[57]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(1)
    );
\not_strict_mode.app_rd_data[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[58]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(2)
    );
\not_strict_mode.app_rd_data[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[59]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(3)
    );
\not_strict_mode.app_rd_data[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[60]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(4)
    );
\not_strict_mode.app_rd_data[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[61]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(5)
    );
\not_strict_mode.app_rd_data[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[62]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0),
      O => \not_strict_mode.app_rd_data_reg[511]\(6)
    );
\not_strict_mode.app_rd_data[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^not_strict_mode.app_rd_data_reg[63]\,
      I1 => \read_fifo.fifo_out_data_r_reg[6]\,
      I2 => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1),
      O => \not_strict_mode.app_rd_data_reg[511]\(7)
    );
\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(0),
      I1 => mem_out(0),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[63]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(8),
      I1 => mem_out(8),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[62]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(16),
      I1 => mem_out(16),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[61]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(24),
      I1 => mem_out(24),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[60]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(17),
      I1 => mem_out(17),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[125]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(25),
      I1 => mem_out(25),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[124]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(33),
      I1 => mem_out(33),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[123]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(41),
      I1 => mem_out(41),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[122]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(49),
      I1 => mem_out(49),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[121]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(57),
      I1 => mem_out(57),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[120]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(1),
      I1 => mem_out(1),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[127]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(9),
      I1 => mem_out(9),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[126]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(50),
      I1 => mem_out(50),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[185]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(58),
      I1 => mem_out(58),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[184]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(2),
      I1 => mem_out(2),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[191]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(10),
      I1 => mem_out(10),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[190]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(18),
      I1 => mem_out(18),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[189]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(26),
      I1 => mem_out(26),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[188]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(34),
      I1 => mem_out(34),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[187]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(42),
      I1 => mem_out(42),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[186]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(35),
      I1 => mem_out(35),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[251]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(43),
      I1 => mem_out(43),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[250]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(51),
      I1 => mem_out(51),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[249]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(59),
      I1 => mem_out(59),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[248]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(3),
      I1 => mem_out(3),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[255]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(11),
      I1 => mem_out(11),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[254]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(19),
      I1 => mem_out(19),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[253]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(27),
      I1 => mem_out(27),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[252]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(20),
      I1 => mem_out(20),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[317]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(28),
      I1 => mem_out(28),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[316]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(36),
      I1 => mem_out(36),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[315]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(44),
      I1 => mem_out(44),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[314]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(52),
      I1 => mem_out(52),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[313]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(60),
      I1 => mem_out(60),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[312]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(4),
      I1 => mem_out(4),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[319]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(12),
      I1 => mem_out(12),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[318]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(53),
      I1 => mem_out(53),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[377]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(61),
      I1 => mem_out(61),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[376]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(5),
      I1 => mem_out(5),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[383]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(13),
      I1 => mem_out(13),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[382]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(21),
      I1 => mem_out(21),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[381]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(29),
      I1 => mem_out(29),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[380]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(37),
      I1 => mem_out(37),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[379]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(45),
      I1 => mem_out(45),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[378]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(38),
      I1 => mem_out(38),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[443]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(46),
      I1 => mem_out(46),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[442]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(54),
      I1 => mem_out(54),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[441]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(62),
      I1 => mem_out(62),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[440]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(6),
      I1 => mem_out(6),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[447]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(14),
      I1 => mem_out(14),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[446]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(22),
      I1 => mem_out(22),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[445]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(30),
      I1 => mem_out(30),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[444]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(23),
      I1 => mem_out(23),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[509]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(31),
      I1 => mem_out(31),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[508]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(39),
      I1 => mem_out(39),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[507]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(47),
      I1 => mem_out(47),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[506]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(55),
      I1 => mem_out(55),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[505]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(63),
      I1 => mem_out(63),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[504]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(7),
      I1 => mem_out(7),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[511]_0\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(15),
      I1 => mem_out(15),
      I2 => my_empty(4),
      O => \^not_strict_mode.app_rd_data_reg[510]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(32),
      I1 => mem_out(32),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[59]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(40),
      I1 => mem_out(40),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[58]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(48),
      I1 => mem_out(48),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[57]\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => Q(56),
      I1 => mem_out(56),
      I2 => \my_empty_reg[4]_rep_n_0\,
      O => \^not_strict_mode.app_rd_data_reg[56]\
    );
\rd_ptr[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => rd_ptr(0),
      O => \rd_ptr[0]_i_1__0_n_0\
    );
\rd_ptr[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000B4F0"
    )
        port map (
      I0 => my_empty(1),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => rd_ptr(1),
      I3 => rd_ptr(0),
      I4 => ififo_rst,
      O => \rd_ptr[1]_i_1__4_n_0\
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[0]_i_1__0_n_0\,
      Q => rd_ptr(0),
      R => ififo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_ptr[1]_i_1__4_n_0\,
      Q => rd_ptr(1),
      R => '0'
    );
\rd_ptr_timing[0]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EF0F0000FFFF10F0"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(0),
      I5 => rd_ptr(0),
      O => \rd_ptr_timing[0]_i_1__9_n_0\
    );
\rd_ptr_timing[1]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10F0EF0F0000"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_full(1),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I3 => my_empty(1),
      I4 => rd_ptr_timing(1),
      I5 => \rd_ptr_timing[1]_i_2__0_n_0\,
      O => \rd_ptr_timing[1]_i_1__9_n_0\
    );
\rd_ptr_timing[1]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rd_ptr(0),
      I1 => rd_ptr(1),
      O => \rd_ptr_timing[1]_i_2__0_n_0\
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \rd_ptr_timing[0]_i_1__9_n_0\,
      Q => rd_ptr_timing(0),
      R => ififo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \my_full[1]_i_1__5_n_0\,
      D => \rd_ptr_timing[1]_i_1__9_n_0\,
      Q => rd_ptr_timing(1),
      R => ififo_rst
    );
\wr_ptr[0]_i_1__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAA965"
    )
        port map (
      I0 => wr_ptr(0),
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      I2 => my_full(1),
      I3 => my_empty(1),
      I4 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I5 => ififo_rst,
      O => \wr_ptr[0]_i_1__12_n_0\
    );
\wr_ptr[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => \^my_empty_reg[3]_0\(1),
      O => A_byte_rd_en
    );
\wr_ptr[1]_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => wr_ptr(1),
      I1 => \wr_ptr[1]_i_2__5_n_0\,
      I2 => wr_ptr(0),
      I3 => ififo_rst,
      O => \wr_ptr[1]_i_1__12_n_0\
    );
\wr_ptr[1]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1105"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I1 => my_empty(1),
      I2 => my_full(1),
      I3 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      O => \wr_ptr[1]_i_2__5_n_0\
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[0]_i_1__12_n_0\,
      Q => wr_ptr(0),
      R => '0'
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_ptr[1]_i_1__12_n_0\,
      Q => wr_ptr(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo is
  port (
    in0 : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo is
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT of wr_ptr_timing : signal is "50";
  attribute RTL_KEEP of wr_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT of wr_ptr_timing : signal is "found";
  attribute syn_maxfan of wr_ptr_timing : signal is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[2]\ : label is "10";
begin
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => wr_en
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '1',
      Q => rd_ptr_timing(0),
      R => in0
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(1),
      R => in0
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(2),
      R => in0
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '1',
      Q => wr_ptr_timing(0),
      R => in0
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(1),
      R => in0
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(2),
      R => in0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0\ is
  port (
    in0 : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0\ is
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT of wr_ptr_timing : signal is "50";
  attribute RTL_KEEP of wr_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT of wr_ptr_timing : signal is "found";
  attribute syn_maxfan of wr_ptr_timing : signal is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[2]\ : label is "10";
begin
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => wr_en
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '1',
      Q => rd_ptr_timing(0),
      R => in0
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(1),
      R => in0
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(2),
      R => in0
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '1',
      Q => wr_ptr_timing(0),
      R => in0
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(1),
      R => in0
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(2),
      R => in0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0_5\ is
  port (
    in0 : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0_5\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0_5\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0_5\ is
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rd_ptr_timing : signal is "50";
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of rd_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rd_ptr_timing : signal is "10";
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute MAX_FANOUT of wr_ptr_timing : signal is "50";
  attribute RTL_KEEP of wr_ptr_timing : signal is "true";
  attribute RTL_MAX_FANOUT of wr_ptr_timing : signal is "found";
  attribute syn_maxfan of wr_ptr_timing : signal is "10";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[0]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[0]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[1]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[1]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute RTL_MAX_FANOUT of \wr_ptr_timing_reg[2]\ : label is "found";
  attribute syn_maxfan of \wr_ptr_timing_reg[2]\ : label is "10";
begin
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => wr_en
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '1',
      Q => rd_ptr_timing(0),
      R => in0
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(1),
      R => in0
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => rd_ptr_timing(2),
      R => in0
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '1',
      Q => wr_ptr_timing(0),
      R => in0
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(1),
      R => in0
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '0',
      D => '0',
      Q => wr_ptr_timing(2),
      R => in0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_mc_data_full : out STD_LOGIC;
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    C_of_full : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[573]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    pre_data_a_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    \entry_cnt_reg[2]_0\ : in STD_LOGIC;
    \entry_cnt_reg[2]_1\ : in STD_LOGIC;
    \entry_cnt_reg[2]_2\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1\ is
  signal C_pre_fifo_a_full : STD_LOGIC;
  signal \entry_cnt[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3__6_n_0\ : STD_LOGIC;
  signal entry_cnt_reg : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_4 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_0 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_5 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_2 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_2 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_0 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_2 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_5 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_5 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_1 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_0 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_2 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_5 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__9_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__7_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__7_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__7_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__7_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__7_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__7_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__9_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__6\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__6\ : label is "soft_lutpair942";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__6\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__6\ : label is "soft_lutpair942";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__7\ : label is "soft_lutpair940";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__7\ : label is "soft_lutpair940";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__7\ : label is "soft_lutpair941";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__7\ : label is "soft_lutpair941";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_22__4\ : label is "soft_lutpair947";
  attribute SOFT_HLUTNM of \out_fifo_i_24__4\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \out_fifo_i_2__6\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \out_fifo_i_31__4\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \out_fifo_i_3__6\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \out_fifo_i_41__4\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \out_fifo_i_49__2\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \out_fifo_i_4__6\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \out_fifo_i_5__6\ : label is "soft_lutpair947";
  attribute SOFT_HLUTNM of \out_fifo_i_61__2\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \out_fifo_i_6__6\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \out_fifo_i_79__3\ : label is "soft_lutpair946";
  attribute SOFT_HLUTNM of \out_fifo_i_7__5\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \out_fifo_i_81__3\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \out_fifo_i_8__5\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \out_fifo_i_9__5\ : label is "soft_lutpair946";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__13\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__13\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__9\ : label is "soft_lutpair953";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__9\ : label is "soft_lutpair953";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__17\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__17\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__9\ : label is "soft_lutpair952";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__6\ : label is "soft_lutpair952";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__6_n_0\
    );
\entry_cnt[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => C_of_full,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__6_n_0\
    );
\entry_cnt[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => C_of_full,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => entry_cnt_reg(2),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__6_n_0\
    );
\entry_cnt[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3__6_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => entry_cnt_reg(3),
      I4 => entry_cnt_reg(2),
      O => \entry_cnt[3]_i_1__6_n_0\
    );
\entry_cnt[4]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => C_of_full,
      O => \entry_cnt[4]_i_1__6_n_0\
    );
\entry_cnt[4]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3__6_n_0\,
      I3 => entry_cnt_reg(2),
      I4 => entry_cnt_reg(4),
      I5 => entry_cnt_reg(3),
      O => \entry_cnt[4]_i_2__6_n_0\
    );
\entry_cnt[4]_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => C_of_full,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3__6_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[0]_i_1__6_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[1]_i_1__6_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[2]_i_1__6_n_0\,
      Q => entry_cnt_reg(2),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[3]_i_1__6_n_0\,
      Q => entry_cnt_reg(3),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__6_n_0\,
      D => \entry_cnt[4]_i_2__6_n_0\,
      Q => entry_cnt_reg(4),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => C_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(5 downto 4),
      DIB(1 downto 0) => phy_dout(7 downto 6),
      DIC(1 downto 0) => phy_dout(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => \my_empty_reg[7]_1\(2),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOC(1) => mem_reg_0_15_12_17_n_4,
      DOC(0) => \my_empty_reg[7]_1\(5),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(11 downto 10),
      DIB(1 downto 0) => phy_dout(13 downto 12),
      DIC(1 downto 0) => phy_dout(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_18_23_n_0,
      DOA(0) => \my_empty_reg[7]_1\(6),
      DOB(1) => \my_empty_reg[7]_1\(7),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(17 downto 16),
      DIB(1 downto 0) => phy_dout(19 downto 18),
      DIC(1 downto 0) => phy_dout(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOB(1) => \my_empty_reg[7]_1\(12),
      DOB(0) => mem_reg_0_15_24_29_n_3,
      DOC(1) => \my_empty_reg[7]_1\(13),
      DOC(0) => mem_reg_0_15_24_29_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(23 downto 22),
      DIB(1 downto 0) => phy_dout(25 downto 24),
      DIC(1 downto 0) => phy_dout(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOB(1) => \my_empty_reg[7]_1\(16),
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(29 downto 28),
      DIB(1 downto 0) => phy_dout(31 downto 30),
      DIC(1 downto 0) => phy_dout(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOB(1) => mem_reg_0_15_36_41_n_2,
      DOB(0) => \my_empty_reg[7]_1\(21),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => mem_reg_0_15_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(35 downto 34),
      DIB(1 downto 0) => phy_dout(37 downto 36),
      DIC(1 downto 0) => phy_dout(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOB(1) => mem_reg_0_15_42_47_n_2,
      DOB(0) => \my_empty_reg[7]_1\(24),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(41 downto 40),
      DIB(1 downto 0) => phy_dout(43 downto 42),
      DIC(1 downto 0) => phy_dout(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_48_53_n_0,
      DOA(0) => \my_empty_reg[7]_1\(27),
      DOB(1) => mem_reg_0_15_48_53_n_2,
      DOB(0) => \my_empty_reg[7]_1\(28),
      DOC(1) => \my_empty_reg[7]_1\(29),
      DOC(0) => mem_reg_0_15_48_53_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(47 downto 46),
      DIB(1 downto 0) => phy_dout(49 downto 48),
      DIC(1 downto 0) => phy_dout(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOC(1) => \my_empty_reg[7]_1\(34),
      DOC(0) => mem_reg_0_15_54_59_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(53 downto 52),
      DIB(1 downto 0) => phy_dout(55 downto 54),
      DIC(1 downto 0) => phy_dout(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(35),
      DOA(0) => mem_reg_0_15_60_65_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOC(1) => \my_empty_reg[7]_1\(38),
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(59 downto 58),
      DIB(1 downto 0) => phy_dout(61 downto 60),
      DIC(1 downto 0) => phy_dout(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => \my_empty_reg[7]_1\(43),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(1 downto 0),
      DIC(1 downto 0) => phy_dout(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_72_77_n_0,
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1) => mem_reg_0_15_72_77_n_2,
      DOB(0) => mem_reg_0_15_72_77_n_3,
      DOC(1) => mem_reg_0_15_72_77_n_4,
      DOC(0) => mem_reg_0_15_72_77_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => mem_reg_0_15_78_79_n_1,
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => C_of_full,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__9_n_0\
    );
\my_empty[7]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => C_of_full,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__7_n_0\
    );
\my_empty[7]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__7_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__7_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__7_n_0\
    );
\my_empty[7]_i_4__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__7_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__9_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__7_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => C_of_full,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__7_n_0\
    );
\my_full[4]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__7_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__7_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__7_n_0\
    );
\my_full[4]_i_4__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__7_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__7_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
ofs_rdy_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => pre_data_a_full_v(0),
      I1 => C_pre_fifo_a_full,
      I2 => \entry_cnt_reg[2]_0\,
      I3 => \entry_cnt_reg[2]_1\,
      I4 => \entry_cnt_reg[2]_2\,
      O => phy_mc_data_full
    );
ofs_rdy_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => entry_cnt_reg(3),
      I1 => entry_cnt_reg(4),
      I2 => entry_cnt_reg(2),
      O => C_pre_fifo_a_full
    );
\out_fifo_i_12__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(17),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_16__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(7),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_17__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(3),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => C_of_full,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(15),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_22__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(11),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_18_23_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_24__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(6),
      I2 => mem_reg_0_15_12_17_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_29__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(14),
      I2 => mem_reg_0_15_24_29_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
\out_fifo_i_31__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(9),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_24_29_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_34__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(19),
      I2 => mem_reg_0_15_36_41_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
\out_fifo_i_41__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(2),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_44__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(16),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_42_47_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_48__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(5),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_49__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(1),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_36_41_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_53__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(13),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_48_53_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
\out_fifo_i_54__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(10),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_48_53_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_56__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(4),
      I2 => mem_reg_0_15_48_53_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
\out_fifo_i_61__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(12),
      I2 => mem_reg_0_15_60_65_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_63__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(8),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_54_59_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(18),
      I2 => mem_reg_0_15_66_71_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
\out_fifo_i_73__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[573]\(0),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_60_65_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(27),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(7)
    );
\out_fifo_i_75__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(26),
      I2 => mem_reg_0_15_78_79_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(6)
    );
\out_fifo_i_76__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(25),
      I2 => mem_reg_0_15_72_77_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(5)
    );
\out_fifo_i_77__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(24),
      I2 => mem_reg_0_15_72_77_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(4)
    );
\out_fifo_i_78__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(23),
      I2 => mem_reg_0_15_72_77_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_79__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(22),
      I2 => mem_reg_0_15_72_77_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_7__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_80__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(21),
      I2 => mem_reg_0_15_72_77_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_81__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[573]\(20),
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => C_of_full,
      O => \rd_ptr_timing[3]_i_1__9_n_0\
    );
\rd_ptr_timing[3]_i_2__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__9_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => C_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_10\ is
  port (
    D5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D4 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \init_calib_complete_reg_rep__11\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    D_of_full : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    init_calib_complete_reg : in STD_LOGIC_VECTOR ( 21 downto 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_10\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_10\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_10\ is
  signal mem_out : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[7]_i_3\ : label is "soft_lutpair773";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4\ : label is "soft_lutpair773";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3\ : label is "soft_lutpair774";
  attribute SOFT_HLUTNM of \my_full[4]_i_4\ : label is "soft_lutpair774";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of out_fifo_i_1 : label is "soft_lutpair782";
  attribute SOFT_HLUTNM of out_fifo_i_10 : label is "soft_lutpair789";
  attribute SOFT_HLUTNM of out_fifo_i_11 : label is "soft_lutpair779";
  attribute SOFT_HLUTNM of out_fifo_i_12 : label is "soft_lutpair793";
  attribute SOFT_HLUTNM of out_fifo_i_13 : label is "soft_lutpair782";
  attribute SOFT_HLUTNM of out_fifo_i_18 : label is "soft_lutpair788";
  attribute SOFT_HLUTNM of out_fifo_i_19 : label is "soft_lutpair789";
  attribute SOFT_HLUTNM of out_fifo_i_2 : label is "soft_lutpair790";
  attribute SOFT_HLUTNM of out_fifo_i_20 : label is "soft_lutpair786";
  attribute SOFT_HLUTNM of out_fifo_i_21 : label is "soft_lutpair787";
  attribute SOFT_HLUTNM of out_fifo_i_27 : label is "soft_lutpair794";
  attribute SOFT_HLUTNM of out_fifo_i_28 : label is "soft_lutpair791";
  attribute SOFT_HLUTNM of out_fifo_i_29 : label is "soft_lutpair790";
  attribute SOFT_HLUTNM of out_fifo_i_3 : label is "soft_lutpair780";
  attribute SOFT_HLUTNM of out_fifo_i_34 : label is "soft_lutpair792";
  attribute SOFT_HLUTNM of out_fifo_i_35 : label is "soft_lutpair794";
  attribute SOFT_HLUTNM of out_fifo_i_36 : label is "soft_lutpair793";
  attribute SOFT_HLUTNM of out_fifo_i_37 : label is "soft_lutpair787";
  attribute SOFT_HLUTNM of out_fifo_i_38 : label is "soft_lutpair783";
  attribute SOFT_HLUTNM of \out_fifo_i_39__0\ : label is "soft_lutpair780";
  attribute SOFT_HLUTNM of out_fifo_i_4 : label is "soft_lutpair791";
  attribute SOFT_HLUTNM of \out_fifo_i_40__0\ : label is "soft_lutpair775";
  attribute SOFT_HLUTNM of \out_fifo_i_41__0\ : label is "soft_lutpair781";
  attribute SOFT_HLUTNM of out_fifo_i_42 : label is "soft_lutpair783";
  attribute SOFT_HLUTNM of \out_fifo_i_43__0\ : label is "soft_lutpair779";
  attribute SOFT_HLUTNM of out_fifo_i_44 : label is "soft_lutpair775";
  attribute SOFT_HLUTNM of out_fifo_i_45 : label is "soft_lutpair778";
  attribute SOFT_HLUTNM of out_fifo_i_5 : label is "soft_lutpair786";
  attribute SOFT_HLUTNM of out_fifo_i_6 : label is "soft_lutpair788";
  attribute SOFT_HLUTNM of out_fifo_i_7 : label is "soft_lutpair778";
  attribute SOFT_HLUTNM of out_fifo_i_8 : label is "soft_lutpair792";
  attribute SOFT_HLUTNM of out_fifo_i_9 : label is "soft_lutpair781";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1\ : label is "soft_lutpair784";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1\ : label is "soft_lutpair784";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1\ : label is "soft_lutpair777";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2\ : label is "soft_lutpair777";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1\ : label is "soft_lutpair785";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair785";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1\ : label is "soft_lutpair776";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1\ : label is "soft_lutpair776";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(1 downto 0),
      DOB(1 downto 0) => mem_out(3 downto 2),
      DOC(1 downto 0) => mem_out(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => init_calib_complete_reg(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => init_calib_complete_reg(7 downto 6),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(7 downto 6),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => init_calib_complete_reg(9 downto 8),
      DIB(1 downto 0) => init_calib_complete_reg(11 downto 10),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(9 downto 8),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(11 downto 10),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => init_calib_complete_reg(19),
      DIB(0) => init_calib_complete_reg(12),
      DIC(1) => init_calib_complete_reg(21),
      DIC(0) => init_calib_complete_reg(13),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => mem_out(33 downto 32),
      DOC(1 downto 0) => mem_out(35 downto 34),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => init_calib_complete_reg(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(13 downto 12),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => init_calib_complete_reg(17 downto 16),
      DIB(1 downto 0) => init_calib_complete_reg(19 downto 18),
      DIC(1 downto 0) => init_calib_complete_reg(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(15 downto 14),
      DOB(1 downto 0) => mem_out(45 downto 44),
      DOC(1 downto 0) => mem_out(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => init_calib_complete_reg(1 downto 0),
      DIC(1 downto 0) => init_calib_complete_reg(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(7 downto 6),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(1 downto 0),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(3 downto 2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => D_of_full,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => SR(0),
      O => \my_empty[1]_i_1_n_0\
    );
\my_empty[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => D_of_full,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => SR(0),
      O => \my_empty[7]_i_1_n_0\
    );
\my_empty[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4_n_0\,
      I4 => rd_ptr(2),
      O => my_empty0
    );
\my_empty[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3_n_0\
    );
\my_empty[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr(3),
      O => \my_empty[7]_i_4_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_cmd_wr_en,
      I2 => D_of_full,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => SR(0),
      O => \my_full[4]_i_1_n_0\
    );
\my_full[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3_n_0\
    );
\my_full[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
out_fifo_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_cmd_wr_en,
      I2 => D_of_full,
      O => \rd_ptr_timing_reg[0]_0\
    );
out_fifo_i_10: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(15),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(3)
    );
out_fifo_i_11: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(14),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
out_fifo_i_12: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(13),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
out_fifo_i_13: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(12),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
out_fifo_i_18: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(23),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(3)
    );
out_fifo_i_19: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(22),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
out_fifo_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(7),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
out_fifo_i_20: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(21),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
out_fifo_i_21: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(20),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
out_fifo_i_26: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(31),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(3)
    );
out_fifo_i_27: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(30),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(2)
    );
out_fifo_i_28: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(29),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
out_fifo_i_29: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(28),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
out_fifo_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(6),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
out_fifo_i_34: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(39),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(7)
    );
out_fifo_i_35: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(38),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(6)
    );
out_fifo_i_36: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(37),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(5)
    );
out_fifo_i_37: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(36),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(4)
    );
out_fifo_i_38: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => mem_out(35),
      I2 => \^my_empty_reg[1]_0\,
      O => D4(3)
    );
\out_fifo_i_39__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => mc_address(2),
      I2 => mem_out(34),
      I3 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
out_fifo_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(5),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_40__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => mc_cas_n(0),
      I2 => mem_out(33),
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_41__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => mc_address(0),
      I2 => mem_out(32),
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
out_fifo_i_42: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => mem_out(47),
      I2 => \^my_empty_reg[1]_0\,
      O => D5(3)
    );
\out_fifo_i_43__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => mc_address(3),
      I2 => mem_out(46),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
out_fifo_i_44: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => mc_cas_n(0),
      I2 => mem_out(45),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
out_fifo_i_45: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => mc_address(1),
      I2 => mem_out(44),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
out_fifo_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(4),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
out_fifo_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(3),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
out_fifo_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(2),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
out_fifo_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(1),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
out_fifo_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(0),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
p_17_out: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => D_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr(2),
      R => SR(0)
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr(3),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => rd_ptr(2),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => D_of_full,
      O => \rd_ptr_timing[3]_i_1_n_0\
    );
\rd_ptr_timing[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(2),
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => SR(0)
    );
wr_ptr0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => D_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => SR(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => SR(0)
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_11\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 46 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_11\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_11\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_11\ is
  signal mem_out : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_4__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__2_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[1]_i_1__2\ : label is "soft_lutpair751";
  attribute SOFT_HLUTNM of \my_empty[6]_i_3__0\ : label is "soft_lutpair749";
  attribute SOFT_HLUTNM of \my_empty[6]_i_4__0\ : label is "soft_lutpair749";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[3]_i_3__0\ : label is "soft_lutpair750";
  attribute SOFT_HLUTNM of \my_full[3]_i_4__0\ : label is "soft_lutpair750";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_10__0\ : label is "soft_lutpair762";
  attribute SOFT_HLUTNM of \out_fifo_i_11__0\ : label is "soft_lutpair752";
  attribute SOFT_HLUTNM of \out_fifo_i_12__0\ : label is "soft_lutpair765";
  attribute SOFT_HLUTNM of \out_fifo_i_13__0\ : label is "soft_lutpair758";
  attribute SOFT_HLUTNM of \out_fifo_i_18__0\ : label is "soft_lutpair761";
  attribute SOFT_HLUTNM of \out_fifo_i_19__0\ : label is "soft_lutpair763";
  attribute SOFT_HLUTNM of \out_fifo_i_1__2\ : label is "soft_lutpair751";
  attribute SOFT_HLUTNM of \out_fifo_i_20__1\ : label is "soft_lutpair762";
  attribute SOFT_HLUTNM of \out_fifo_i_21__1\ : label is "soft_lutpair760";
  attribute SOFT_HLUTNM of \out_fifo_i_26__0\ : label is "soft_lutpair769";
  attribute SOFT_HLUTNM of \out_fifo_i_27__0\ : label is "soft_lutpair766";
  attribute SOFT_HLUTNM of \out_fifo_i_28__1\ : label is "soft_lutpair770";
  attribute SOFT_HLUTNM of \out_fifo_i_29__0\ : label is "soft_lutpair767";
  attribute SOFT_HLUTNM of \out_fifo_i_2__1\ : label is "soft_lutpair764";
  attribute SOFT_HLUTNM of \out_fifo_i_34__0\ : label is "soft_lutpair768";
  attribute SOFT_HLUTNM of \out_fifo_i_35__0\ : label is "soft_lutpair766";
  attribute SOFT_HLUTNM of \out_fifo_i_36__1\ : label is "soft_lutpair772";
  attribute SOFT_HLUTNM of \out_fifo_i_37__1\ : label is "soft_lutpair760";
  attribute SOFT_HLUTNM of \out_fifo_i_3__1\ : label is "soft_lutpair753";
  attribute SOFT_HLUTNM of \out_fifo_i_4__1\ : label is "soft_lutpair765";
  attribute SOFT_HLUTNM of out_fifo_i_58 : label is "soft_lutpair769";
  attribute SOFT_HLUTNM of out_fifo_i_59 : label is "soft_lutpair758";
  attribute SOFT_HLUTNM of \out_fifo_i_5__1\ : label is "soft_lutpair759";
  attribute SOFT_HLUTNM of out_fifo_i_60 : label is "soft_lutpair770";
  attribute SOFT_HLUTNM of out_fifo_i_61 : label is "soft_lutpair763";
  attribute SOFT_HLUTNM of \out_fifo_i_66__0\ : label is "soft_lutpair771";
  attribute SOFT_HLUTNM of \out_fifo_i_67__0\ : label is "soft_lutpair767";
  attribute SOFT_HLUTNM of \out_fifo_i_68__0\ : label is "soft_lutpair771";
  attribute SOFT_HLUTNM of \out_fifo_i_69__0\ : label is "soft_lutpair759";
  attribute SOFT_HLUTNM of \out_fifo_i_6__0\ : label is "soft_lutpair761";
  attribute SOFT_HLUTNM of out_fifo_i_74 : label is "soft_lutpair772";
  attribute SOFT_HLUTNM of out_fifo_i_75 : label is "soft_lutpair768";
  attribute SOFT_HLUTNM of out_fifo_i_77 : label is "soft_lutpair764";
  attribute SOFT_HLUTNM of \out_fifo_i_7__6\ : label is "soft_lutpair753";
  attribute SOFT_HLUTNM of \out_fifo_i_9__6\ : label is "soft_lutpair752";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__3\ : label is "soft_lutpair756";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__3\ : label is "soft_lutpair756";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__2\ : label is "soft_lutpair755";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__2\ : label is "soft_lutpair755";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__3\ : label is "soft_lutpair757";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__3\ : label is "soft_lutpair757";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__2\ : label is "soft_lutpair754";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1__2\ : label is "soft_lutpair754";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(1 downto 0),
      DIB(1) => '1',
      DIB(0) => phy_dout(2),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => \rd_ptr_timing_reg[0]_1\(0),
      DOA(0) => mem_out(0),
      DOB(1 downto 0) => mem_out(3 downto 2),
      DOC(1 downto 0) => mem_out(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(8 downto 7),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(13 downto 12),
      DOB(1 downto 0) => mem_out(15 downto 14),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(6 downto 5),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(10 downto 9),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(8 downto 7),
      DOB(1 downto 0) => mem_out(21 downto 20),
      DOC(1 downto 0) => mem_out(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(12 downto 11),
      DIB(1 downto 0) => phy_dout(14 downto 13),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(10 downto 9),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(12 downto 11),
      DOC(1 downto 0) => mem_out(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(16 downto 15),
      DIC(1 downto 0) => phy_dout(18 downto 17),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(31 downto 30),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(14 downto 13),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(16 downto 15),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(20 downto 19),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(37 downto 36),
      DOB(1 downto 0) => mem_out(39 downto 38),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(18 downto 17),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(22 downto 21),
      DIB(1 downto 0) => phy_dout(24 downto 23),
      DIC(1 downto 0) => phy_dout(26 downto 25),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(20 downto 19),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(22 downto 21),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(24 downto 23),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(28 downto 27),
      DIB(1 downto 0) => phy_dout(30 downto 29),
      DIC(1 downto 0) => phy_dout(32 downto 31),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(26 downto 25),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(28 downto 27),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(30 downto 29),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(34 downto 33),
      DIB(1 downto 0) => phy_dout(36 downto 35),
      DIC(1 downto 0) => phy_dout(38 downto 37),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(32 downto 31),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(34 downto 33),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(36 downto 35),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => phy_dout(40 downto 39),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(61 downto 60),
      DOB(1 downto 0) => mem_out(63 downto 62),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(38 downto 37),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(42 downto 41),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(40 downto 39),
      DOB(1 downto 0) => mem_out(69 downto 68),
      DOC(1 downto 0) => mem_out(71 downto 70),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(4 downto 3),
      DIC(1 downto 0) => phy_dout(6 downto 5),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(7 downto 6),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(2 downto 1),
      DOC(1 downto 0) => \rd_ptr_timing_reg[0]_1\(4 downto 3),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(44 downto 43),
      DIB(1 downto 0) => phy_dout(46 downto 45),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \rd_ptr_timing_reg[0]_1\(42 downto 41),
      DOB(1 downto 0) => \rd_ptr_timing_reg[0]_1\(44 downto 43),
      DOC(1 downto 0) => mem_out(77 downto 76),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(79 downto 78),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0F0F0F2"
    )
        port map (
      I0 => my_empty0,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \^my_empty_reg[1]_0\,
      I3 => ofifo_rst_reg,
      I4 => phy_cmd_wr_en,
      O => \my_empty[1]_i_1__2_n_0\
    );
\my_empty[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0F0F0F2"
    )
        port map (
      I0 => my_empty0,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => ofifo_rst_reg,
      I4 => phy_cmd_wr_en,
      O => \my_empty[6]_i_1__0_n_0\
    );
\my_empty[6]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[6]_i_3__0_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[6]_i_4__0_n_0\,
      I4 => rd_ptr(2),
      O => my_empty0
    );
\my_empty[6]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      I4 => wr_ptr_timing(0),
      O => \my_empty[6]_i_3__0_n_0\
    );
\my_empty[6]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr(3),
      O => \my_empty[6]_i_4__0_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__2_n_0\,
      Q => \^my_empty_reg[1]_0\,
      S => SR(0)
    );
\my_empty_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[6]_i_1__0_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      S => SR(0)
    );
\my_full[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_cmd_wr_en,
      I2 => ofifo_rst_reg,
      I3 => \my_full_reg_n_0_[3]\,
      I4 => \my_empty_reg_n_0_[6]\,
      I5 => SR(0),
      O => \my_full[3]_i_1__0_n_0\
    );
\my_full[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[3]_i_3__0_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[3]_i_4__0_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[3]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[3]_i_3__0_n_0\
    );
\my_full[3]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[3]_i_4__0_n_0\
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[3]_i_1__0_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
\out_fifo_i_10__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(15),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(3)
    );
\out_fifo_i_11__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(14),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_12__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(13),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_13__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(12),
      I1 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_18__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(23),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(3)
    );
\out_fifo_i_19__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(22),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_cmd_wr_en,
      I2 => ofifo_rst_reg,
      O => \rd_ptr_timing_reg[0]_0\
    );
\out_fifo_i_20__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(21),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_21__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(20),
      I1 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_26__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(31),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(3)
    );
\out_fifo_i_27__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(30),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(2)
    );
\out_fifo_i_28__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(29),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_29__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(28),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(7),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
\out_fifo_i_34__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(39),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(3)
    );
\out_fifo_i_35__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(38),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_36__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(37),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_37__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(36),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(6),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(5),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
out_fifo_i_58: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(63),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(3)
    );
out_fifo_i_59: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(62),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(2)
    );
\out_fifo_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(4),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
out_fifo_i_60: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(61),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
out_fifo_i_61: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(60),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(71),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(3)
    );
\out_fifo_i_67__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(70),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(2)
    );
\out_fifo_i_68__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(69),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_69__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(68),
      I1 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out(3),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
out_fifo_i_74: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(79),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
out_fifo_i_75: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(78),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
out_fifo_i_76: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(77),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
out_fifo_i_77: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out(76),
      I1 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_7__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(1),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out(2),
      I3 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out(0),
      I3 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
p_17_out: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr(2),
      R => SR(0)
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr(3),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => rd_ptr(2),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[6]\,
      I1 => ofifo_rst_reg,
      O => \rd_ptr_timing[3]_i_1__2_n_0\
    );
\rd_ptr_timing[3]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(2),
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__2_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => SR(0)
    );
wr_ptr0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \my_empty_reg_n_0_[6]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => SR(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => SR(0)
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_12\ is
  port (
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D5 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 10 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[2]\ : in STD_LOGIC_VECTOR ( 10 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_12\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_12\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_12\ is
  signal mem_out_0 : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_1_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_3_n_0\ : STD_LOGIC;
  signal \my_empty[6]_i_4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[6]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[3]_i_1_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_3_n_0\ : STD_LOGIC;
  signal \my_full[3]_i_4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[3]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__1_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_ptr0__0\ : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \my_empty[1]_i_1__1\ : label is "soft_lutpair729";
  attribute SOFT_HLUTNM of \my_empty[6]_i_3\ : label is "soft_lutpair727";
  attribute SOFT_HLUTNM of \my_empty[6]_i_4\ : label is "soft_lutpair727";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[6]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[3]_i_3\ : label is "soft_lutpair728";
  attribute SOFT_HLUTNM of \my_full[3]_i_4\ : label is "soft_lutpair728";
  attribute syn_maxfan of \my_full_reg[3]\ : label is "3";
  attribute SOFT_HLUTNM of out_fifo_i_14 : label is "soft_lutpair747";
  attribute SOFT_HLUTNM of out_fifo_i_15 : label is "soft_lutpair742";
  attribute SOFT_HLUTNM of \out_fifo_i_1__1\ : label is "soft_lutpair729";
  attribute SOFT_HLUTNM of \out_fifo_i_20__0\ : label is "soft_lutpair744";
  attribute SOFT_HLUTNM of \out_fifo_i_21__0\ : label is "soft_lutpair743";
  attribute SOFT_HLUTNM of out_fifo_i_22 : label is "soft_lutpair747";
  attribute SOFT_HLUTNM of out_fifo_i_23 : label is "soft_lutpair746";
  attribute SOFT_HLUTNM of out_fifo_i_24 : label is "soft_lutpair742";
  attribute SOFT_HLUTNM of out_fifo_i_25 : label is "soft_lutpair733";
  attribute SOFT_HLUTNM of \out_fifo_i_27__1\ : label is "soft_lutpair734";
  attribute SOFT_HLUTNM of \out_fifo_i_28__0\ : label is "soft_lutpair740";
  attribute SOFT_HLUTNM of \out_fifo_i_29__1\ : label is "soft_lutpair735";
  attribute SOFT_HLUTNM of \out_fifo_i_2__0\ : label is "soft_lutpair737";
  attribute SOFT_HLUTNM of out_fifo_i_31 : label is "soft_lutpair732";
  attribute SOFT_HLUTNM of out_fifo_i_32 : label is "soft_lutpair746";
  attribute SOFT_HLUTNM of out_fifo_i_33 : label is "soft_lutpair737";
  attribute SOFT_HLUTNM of \out_fifo_i_35__1\ : label is "soft_lutpair736";
  attribute SOFT_HLUTNM of \out_fifo_i_36__0\ : label is "soft_lutpair748";
  attribute SOFT_HLUTNM of \out_fifo_i_37__0\ : label is "soft_lutpair744";
  attribute SOFT_HLUTNM of out_fifo_i_38 : label is "soft_lutpair748";
  attribute SOFT_HLUTNM of out_fifo_i_39 : label is "soft_lutpair741";
  attribute SOFT_HLUTNM of \out_fifo_i_3__0\ : label is "soft_lutpair733";
  attribute SOFT_HLUTNM of out_fifo_i_41 : label is "soft_lutpair743";
  attribute SOFT_HLUTNM of out_fifo_i_42 : label is "soft_lutpair745";
  attribute SOFT_HLUTNM of out_fifo_i_43 : label is "soft_lutpair745";
  attribute SOFT_HLUTNM of \out_fifo_i_4__0\ : label is "soft_lutpair740";
  attribute SOFT_HLUTNM of \out_fifo_i_5__0\ : label is "soft_lutpair735";
  attribute SOFT_HLUTNM of \out_fifo_i_6__1\ : label is "soft_lutpair736";
  attribute SOFT_HLUTNM of \out_fifo_i_7__0\ : label is "soft_lutpair732";
  attribute SOFT_HLUTNM of \out_fifo_i_8__0\ : label is "soft_lutpair741";
  attribute SOFT_HLUTNM of \out_fifo_i_9__0\ : label is "soft_lutpair734";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__2\ : label is "soft_lutpair739";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__2\ : label is "soft_lutpair739";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__1\ : label is "soft_lutpair731";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__1\ : label is "soft_lutpair731";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__2\ : label is "soft_lutpair738";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__2\ : label is "soft_lutpair738";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__1\ : label is "soft_lutpair730";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_1__1\ : label is "soft_lutpair730";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(1 downto 0),
      DOB(1 downto 0) => mem_out_0(3 downto 2),
      DOC(1 downto 0) => mem_out_0(5 downto 4),
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => \cmd_pipe_plus.mc_cas_n_reg[2]\(1),
      DIA(0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(1),
      DIB(1) => \cmd_pipe_plus.mc_cas_n_reg[2]\(1),
      DIB(0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(1),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out(5 downto 4),
      DOB(1 downto 0) => mem_out(7 downto 6),
      DOC(1 downto 0) => mem_out_0(29 downto 28),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(37 downto 36),
      DOB(1 downto 0) => mem_out_0(39 downto 38),
      DOC(1) => mem_out(8),
      DOC(0) => mem_out_0(40),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => '1',
      DIA(0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(4),
      DIB(1 downto 0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(6 downto 5),
      DIC(1) => '1',
      DIC(0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(7),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(43 downto 42),
      DOB(1) => mem_out(9),
      DOB(0) => mem_out_0(44),
      DOC(1 downto 0) => mem_out_0(47 downto 46),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(49 downto 48),
      DOB(1 downto 0) => mem_out_0(51 downto 50),
      DOC(1) => mem_out(10),
      DOC(0) => mem_out_0(52),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1) => '1',
      DIA(0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(10),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(55 downto 54),
      DOB(1 downto 0) => mem_out_0(57 downto 56),
      DOC(1 downto 0) => mem_out_0(59 downto 58),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => rd_ptr(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => rd_ptr(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => rd_ptr(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => \cmd_pipe_plus.mc_cas_n_reg[2]\(0),
      DIB(0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(0),
      DIC(1) => \cmd_pipe_plus.mc_cas_n_reg[2]\(0),
      DIC(0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => mem_out_0(7 downto 6),
      DOB(1 downto 0) => mem_out(1 downto 0),
      DOC(1 downto 0) => mem_out(3 downto 2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0F0F0F2"
    )
        port map (
      I0 => my_empty0,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \^my_empty_reg[1]_0\,
      I3 => ofifo_rst_reg,
      I4 => phy_cmd_wr_en,
      O => \my_empty[1]_i_1__1_n_0\
    );
\my_empty[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0F0F0F2"
    )
        port map (
      I0 => my_empty0,
      I1 => \my_full_reg_n_0_[3]\,
      I2 => \my_empty_reg_n_0_[6]\,
      I3 => ofifo_rst_reg,
      I4 => phy_cmd_wr_en,
      O => \my_empty[6]_i_1_n_0\
    );
\my_empty[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[6]_i_3_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[6]_i_4_n_0\,
      I4 => rd_ptr(2),
      O => my_empty0
    );
\my_empty[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      I4 => wr_ptr_timing(0),
      O => \my_empty[6]_i_3_n_0\
    );
\my_empty[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(1),
      I4 => rd_ptr(3),
      O => \my_empty[6]_i_4_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__1_n_0\,
      Q => \^my_empty_reg[1]_0\,
      S => SR(0)
    );
\my_empty_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[6]_i_1_n_0\,
      Q => \my_empty_reg_n_0_[6]\,
      S => SR(0)
    );
\my_full[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_cmd_wr_en,
      I2 => ofifo_rst_reg,
      I3 => \my_full_reg_n_0_[3]\,
      I4 => \my_empty_reg_n_0_[6]\,
      I5 => SR(0),
      O => \my_full[3]_i_1_n_0\
    );
\my_full[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[3]_i_3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[3]_i_4_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[3]_i_3_n_0\
    );
\my_full[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[3]_i_4_n_0\
    );
\my_full_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[3]_i_1_n_0\,
      Q => \my_full_reg_n_0_[3]\,
      R => '0'
    );
out_fifo_i_14: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(29),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
out_fifo_i_15: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(28),
      I1 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_cmd_wr_en,
      I2 => ofifo_rst_reg,
      O => \rd_ptr_timing_reg[0]_0\
    );
\out_fifo_i_20__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(39),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(3)
    );
\out_fifo_i_21__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(38),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
out_fifo_i_22: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(37),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
out_fifo_i_23: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(36),
      I1 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
out_fifo_i_24: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(47),
      I1 => \^my_empty_reg[1]_0\,
      O => D5(5)
    );
out_fifo_i_25: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[2]\(1),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out_0(46),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(4)
    );
\out_fifo_i_27__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[2]\(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out_0(44),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(3)
    );
\out_fifo_i_28__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(43),
      I1 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_29__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out_0(42),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(7),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
out_fifo_i_31: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cs_n(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out_0(40),
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
out_fifo_i_32: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => mem_out_0(55),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(6)
    );
out_fifo_i_33: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cas_n(1),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out_0(54),
      I3 => \^my_empty_reg[1]_0\,
      O => D6(5)
    );
\out_fifo_i_35__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => mem_out_0(52),
      I3 => \^my_empty_reg[1]_0\,
      O => D6(4)
    );
\out_fifo_i_36__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(51),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(3)
    );
\out_fifo_i_37__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(50),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
out_fifo_i_38: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(49),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
out_fifo_i_39: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(48),
      I1 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(6),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
out_fifo_i_40: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(59),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(3)
    );
out_fifo_i_41: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(58),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(2)
    );
out_fifo_i_42: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(57),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
out_fifo_i_43: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(56),
      I1 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(5),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(4),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
\out_fifo_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(3),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
\out_fifo_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(2),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_8__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(1),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_out_0(0),
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
p_17_out: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr(0),
      R => SR(0)
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr(1),
      R => SR(0)
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr(2),
      R => SR(0)
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr(3),
      R => SR(0)
    );
\rd_ptr_timing[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => rd_ptr(2),
      I1 => rd_ptr(0),
      I2 => rd_ptr(1),
      I3 => rd_ptr(3),
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[6]\,
      I1 => ofifo_rst_reg,
      O => \rd_ptr_timing[3]_i_1__1_n_0\
    );
\rd_ptr_timing[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => rd_ptr(3),
      I1 => rd_ptr(1),
      I2 => rd_ptr(0),
      I3 => rd_ptr(2),
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => SR(0)
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => SR(0)
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => SR(0)
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__1_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => SR(0)
    );
wr_ptr0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_cmd_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[3]\,
      I3 => \my_empty_reg_n_0_[6]\,
      O => \wr_ptr0__0\
    );
\wr_ptr[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => SR(0)
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => SR(0)
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => SR(0)
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => SR(0)
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => SR(0)
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => SR(0)
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => SR(0)
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wr_ptr0__0\,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_15\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    pre_data_a_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[572]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_15\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_15\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_15\ is
  signal \entry_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_1 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_1 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_0 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_2 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_0 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_0 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_3 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_3 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_5 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_3 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_2 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_0 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_2 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_5 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_0 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_2 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_5 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__0_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1\ : label is "soft_lutpair713";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1\ : label is "soft_lutpair714";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1\ : label is "soft_lutpair713";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3\ : label is "soft_lutpair714";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__0\ : label is "soft_lutpair711";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__0\ : label is "soft_lutpair711";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__0\ : label is "soft_lutpair712";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__0\ : label is "soft_lutpair712";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_33__5\ : label is "soft_lutpair717";
  attribute SOFT_HLUTNM of \out_fifo_i_41__5\ : label is "soft_lutpair716";
  attribute SOFT_HLUTNM of \out_fifo_i_45__3\ : label is "soft_lutpair722";
  attribute SOFT_HLUTNM of \out_fifo_i_4__8\ : label is "soft_lutpair721";
  attribute SOFT_HLUTNM of \out_fifo_i_55__3\ : label is "soft_lutpair715";
  attribute SOFT_HLUTNM of \out_fifo_i_65__3\ : label is "soft_lutpair718";
  attribute SOFT_HLUTNM of out_fifo_i_66 : label is "soft_lutpair720";
  attribute SOFT_HLUTNM of out_fifo_i_67 : label is "soft_lutpair717";
  attribute SOFT_HLUTNM of out_fifo_i_68 : label is "soft_lutpair719";
  attribute SOFT_HLUTNM of out_fifo_i_69 : label is "soft_lutpair715";
  attribute SOFT_HLUTNM of out_fifo_i_70 : label is "soft_lutpair721";
  attribute SOFT_HLUTNM of out_fifo_i_71 : label is "soft_lutpair716";
  attribute SOFT_HLUTNM of out_fifo_i_72 : label is "soft_lutpair722";
  attribute SOFT_HLUTNM of out_fifo_i_73 : label is "soft_lutpair718";
  attribute SOFT_HLUTNM of \out_fifo_i_79__4\ : label is "soft_lutpair720";
  attribute SOFT_HLUTNM of \out_fifo_i_81__4\ : label is "soft_lutpair719";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__1\ : label is "soft_lutpair726";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__1\ : label is "soft_lutpair726";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__0\ : label is "soft_lutpair724";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__0\ : label is "soft_lutpair724";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__1\ : label is "soft_lutpair725";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__1\ : label is "soft_lutpair725";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__0\ : label is "soft_lutpair723";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2\ : label is "soft_lutpair723";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1_n_0\
    );
\entry_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1_n_0\
    );
\entry_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg__0\(2),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1_n_0\
    );
\entry_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \entry_cnt_reg__0\(3),
      I4 => \entry_cnt_reg__0\(2),
      O => \entry_cnt[3]_i_1_n_0\
    );
\entry_cnt[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => ofifo_rst_reg,
      O => \entry_cnt[4]_i_1_n_0\
    );
\entry_cnt[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3_n_0\,
      I3 => \entry_cnt_reg__0\(2),
      I4 => \entry_cnt_reg__0\(4),
      I5 => \entry_cnt_reg__0\(3),
      O => \entry_cnt[4]_i_2_n_0\
    );
\entry_cnt[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ofifo_rst_reg,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[0]_i_1_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[1]_i_1_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[2]_i_1_n_0\,
      Q => \entry_cnt_reg__0\(2),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[3]_i_1_n_0\,
      Q => \entry_cnt_reg__0\(3),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1_n_0\,
      D => \entry_cnt[4]_i_2_n_0\,
      Q => \entry_cnt_reg__0\(4),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(1 downto 0),
      DIB(1 downto 0) => phy_dout(3 downto 2),
      DIC(1 downto 0) => phy_dout(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => \my_empty_reg[7]_1\(2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_0_5_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(13 downto 12),
      DIB(1 downto 0) => phy_dout(15 downto 14),
      DIC(1 downto 0) => phy_dout(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(7),
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(19 downto 18),
      DIB(1 downto 0) => phy_dout(21 downto 20),
      DIC(1 downto 0) => phy_dout(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(12),
      DOA(0) => mem_reg_0_15_18_23_n_1,
      DOB(1) => \my_empty_reg[7]_1\(13),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(25 downto 24),
      DIB(1 downto 0) => phy_dout(27 downto 26),
      DIC(1 downto 0) => phy_dout(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(16),
      DOA(0) => mem_reg_0_15_24_29_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(31 downto 30),
      DIB(1 downto 0) => phy_dout(33 downto 32),
      DIC(1 downto 0) => phy_dout(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_30_35_n_0,
      DOA(0) => \my_empty_reg[7]_1\(21),
      DOB(1) => mem_reg_0_15_30_35_n_2,
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(37 downto 36),
      DIB(1 downto 0) => phy_dout(39 downto 38),
      DIC(1 downto 0) => phy_dout(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_36_41_n_0,
      DOA(0) => \my_empty_reg[7]_1\(24),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => \my_empty_reg[7]_1\(27),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(43 downto 42),
      DIB(1 downto 0) => phy_dout(45 downto 44),
      DIC(1 downto 0) => phy_dout(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_42_47_n_0,
      DOA(0) => \my_empty_reg[7]_1\(28),
      DOB(1) => \my_empty_reg[7]_1\(29),
      DOB(0) => mem_reg_0_15_42_47_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(49 downto 48),
      DIB(1 downto 0) => phy_dout(51 downto 50),
      DIC(1 downto 0) => phy_dout(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOB(1) => \my_empty_reg[7]_1\(34),
      DOB(0) => mem_reg_0_15_48_53_n_3,
      DOC(1) => \my_empty_reg[7]_1\(35),
      DOC(0) => mem_reg_0_15_48_53_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(55 downto 54),
      DIB(1 downto 0) => phy_dout(57 downto 56),
      DIC(1 downto 0) => phy_dout(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOB(1) => \my_empty_reg[7]_1\(38),
      DOB(0) => mem_reg_0_15_54_59_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(61 downto 60),
      DIB(1 downto 0) => phy_dout(63 downto 62),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOB(1) => mem_reg_0_15_60_65_n_2,
      DOB(0) => \my_empty_reg[7]_1\(43),
      DOC(1) => mem_reg_0_15_60_65_n_4,
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_66_71_n_0,
      DOA(0) => mem_reg_0_15_66_71_n_1,
      DOB(1) => mem_reg_0_15_66_71_n_2,
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => mem_reg_0_15_66_71_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(7 downto 6),
      DIB(1 downto 0) => phy_dout(9 downto 8),
      DIC(1 downto 0) => phy_dout(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => \my_empty_reg[7]_1\(5),
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => \my_empty_reg[7]_1\(6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_72_77_n_0,
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1) => mem_reg_0_15_72_77_n_2,
      DOB(0) => mem_reg_0_15_72_77_n_3,
      DOC(1) => mem_reg_0_15_72_77_n_4,
      DOC(0) => mem_reg_0_15_72_77_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => mem_reg_0_15_78_79_n_1,
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__0_n_0\
    );
\my_empty[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__0_n_0\
    );
\my_empty[7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__0_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__0_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__0_n_0\
    );
\my_empty[7]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__0_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__0_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__0_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__0_n_0\
    );
\my_full[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__0_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__0_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__0_n_0\
    );
\my_full[4]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__0_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__0_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
ofs_rdy_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \entry_cnt_reg__0\(3),
      I1 => \entry_cnt_reg__0\(4),
      I2 => \entry_cnt_reg__0\(2),
      O => pre_data_a_full_v(0)
    );
\out_fifo_i_13__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(15),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_14__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(11),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_16__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(6),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(14),
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_23__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(9),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_18_23_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_26__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(19),
      I2 => mem_reg_0_15_30_35_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_33__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(2),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_24_29_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_36__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(16),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_36_41_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_40__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(5),
      I2 => mem_reg_0_15_30_35_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_41__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(1),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_45__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(13),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_42_47_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_46__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(10),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_42_47_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_48__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(4),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(17),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_0_5_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_53__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(12),
      I2 => mem_reg_0_15_48_53_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_55__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(8),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_48_53_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_58__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(18),
      I2 => mem_reg_0_15_60_65_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_65__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(0),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_54_59_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
out_fifo_i_66: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(7)
    );
out_fifo_i_67: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(6)
    );
out_fifo_i_68: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(5)
    );
out_fifo_i_69: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(4)
    );
out_fifo_i_70: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(3)
    );
out_fifo_i_71: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(2)
    );
out_fifo_i_72: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
out_fifo_i_73: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(27),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(7)
    );
\out_fifo_i_75__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(26),
      I2 => mem_reg_0_15_78_79_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(6)
    );
\out_fifo_i_76__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(25),
      I2 => mem_reg_0_15_72_77_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(5)
    );
\out_fifo_i_77__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(24),
      I2 => mem_reg_0_15_72_77_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(4)
    );
\out_fifo_i_78__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(23),
      I2 => mem_reg_0_15_72_77_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_79__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(22),
      I2 => mem_reg_0_15_72_77_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_80__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(21),
      I2 => mem_reg_0_15_72_77_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_81__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(20),
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[572]\(7),
      I2 => mem_reg_0_15_0_5_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[572]\(3),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_0_5_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => ofifo_rst_reg,
      O => \rd_ptr_timing[3]_i_1__0_n_0\
    );
\rd_ptr_timing[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__0_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_21\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[568]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_21\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_21\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_21\ is
  signal \entry_cnt[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \^entry_cnt_reg[4]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_4 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_0 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_5 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_2 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_2 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_0 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_2 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_5 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_5 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_1 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_0 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_2 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_5 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__4_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__4_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__4_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__6_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__3\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__3\ : label is "soft_lutpair663";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__3\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__3\ : label is "soft_lutpair663";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__4\ : label is "soft_lutpair660";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__4\ : label is "soft_lutpair660";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__4\ : label is "soft_lutpair661";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__4\ : label is "soft_lutpair661";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_16__9\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \out_fifo_i_22__9\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \out_fifo_i_24__9\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \out_fifo_i_29__9\ : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of \out_fifo_i_2__4\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \out_fifo_i_3__4\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \out_fifo_i_41__9\ : label is "soft_lutpair666";
  attribute SOFT_HLUTNM of \out_fifo_i_49__6\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \out_fifo_i_4__4\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \out_fifo_i_5__4\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \out_fifo_i_61__7\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \out_fifo_i_6__4\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \out_fifo_i_79__7\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \out_fifo_i_7__3\ : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of \out_fifo_i_8__3\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \out_fifo_i_9__3\ : label is "soft_lutpair666";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__7\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__7\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__6\ : label is "soft_lutpair673";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__6\ : label is "soft_lutpair673";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__11\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__11\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__6\ : label is "soft_lutpair672";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__3\ : label is "soft_lutpair672";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \entry_cnt_reg[4]_0\(2 downto 0) <= \^entry_cnt_reg[4]_0\(2 downto 0);
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__3_n_0\
    );
\entry_cnt[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__3_n_0\
    );
\entry_cnt[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^entry_cnt_reg[4]_0\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__3_n_0\
    );
\entry_cnt[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3__3_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^entry_cnt_reg[4]_0\(1),
      I4 => \^entry_cnt_reg[4]_0\(0),
      O => \entry_cnt[3]_i_1__3_n_0\
    );
\entry_cnt[4]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => ofifo_rst_reg,
      O => \entry_cnt[4]_i_1__3_n_0\
    );
\entry_cnt[4]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3__3_n_0\,
      I3 => \^entry_cnt_reg[4]_0\(0),
      I4 => \^entry_cnt_reg[4]_0\(2),
      I5 => \^entry_cnt_reg[4]_0\(1),
      O => \entry_cnt[4]_i_2__3_n_0\
    );
\entry_cnt[4]_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ofifo_rst_reg,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3__3_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[0]_i_1__3_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[1]_i_1__3_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[2]_i_1__3_n_0\,
      Q => \^entry_cnt_reg[4]_0\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[3]_i_1__3_n_0\,
      Q => \^entry_cnt_reg[4]_0\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__3_n_0\,
      D => \entry_cnt[4]_i_2__3_n_0\,
      Q => \^entry_cnt_reg[4]_0\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(5 downto 4),
      DIB(1 downto 0) => phy_dout(7 downto 6),
      DIC(1 downto 0) => phy_dout(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => \my_empty_reg[7]_1\(2),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOC(1) => mem_reg_0_15_12_17_n_4,
      DOC(0) => \my_empty_reg[7]_1\(5),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(11 downto 10),
      DIB(1 downto 0) => phy_dout(13 downto 12),
      DIC(1 downto 0) => phy_dout(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_18_23_n_0,
      DOA(0) => \my_empty_reg[7]_1\(6),
      DOB(1) => \my_empty_reg[7]_1\(7),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(17 downto 16),
      DIB(1 downto 0) => phy_dout(19 downto 18),
      DIC(1 downto 0) => phy_dout(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOB(1) => \my_empty_reg[7]_1\(12),
      DOB(0) => mem_reg_0_15_24_29_n_3,
      DOC(1) => \my_empty_reg[7]_1\(13),
      DOC(0) => mem_reg_0_15_24_29_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(23 downto 22),
      DIB(1 downto 0) => phy_dout(25 downto 24),
      DIC(1 downto 0) => phy_dout(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOB(1) => \my_empty_reg[7]_1\(16),
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(29 downto 28),
      DIB(1 downto 0) => phy_dout(31 downto 30),
      DIC(1 downto 0) => phy_dout(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOB(1) => mem_reg_0_15_36_41_n_2,
      DOB(0) => \my_empty_reg[7]_1\(21),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => mem_reg_0_15_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(35 downto 34),
      DIB(1 downto 0) => phy_dout(37 downto 36),
      DIC(1 downto 0) => phy_dout(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOB(1) => mem_reg_0_15_42_47_n_2,
      DOB(0) => \my_empty_reg[7]_1\(24),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(41 downto 40),
      DIB(1 downto 0) => phy_dout(43 downto 42),
      DIC(1 downto 0) => phy_dout(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_48_53_n_0,
      DOA(0) => \my_empty_reg[7]_1\(27),
      DOB(1) => mem_reg_0_15_48_53_n_2,
      DOB(0) => \my_empty_reg[7]_1\(28),
      DOC(1) => \my_empty_reg[7]_1\(29),
      DOC(0) => mem_reg_0_15_48_53_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(47 downto 46),
      DIB(1 downto 0) => phy_dout(49 downto 48),
      DIC(1 downto 0) => phy_dout(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOC(1) => \my_empty_reg[7]_1\(34),
      DOC(0) => mem_reg_0_15_54_59_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(53 downto 52),
      DIB(1 downto 0) => phy_dout(55 downto 54),
      DIC(1 downto 0) => phy_dout(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(35),
      DOA(0) => mem_reg_0_15_60_65_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOC(1) => \my_empty_reg[7]_1\(38),
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(59 downto 58),
      DIB(1 downto 0) => phy_dout(61 downto 60),
      DIC(1 downto 0) => phy_dout(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => \my_empty_reg[7]_1\(43),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(1 downto 0),
      DIC(1 downto 0) => phy_dout(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_72_77_n_0,
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1) => mem_reg_0_15_72_77_n_2,
      DOB(0) => mem_reg_0_15_72_77_n_3,
      DOC(1) => mem_reg_0_15_72_77_n_4,
      DOC(0) => mem_reg_0_15_72_77_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => mem_reg_0_15_78_79_n_1,
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__6_n_0\
    );
\my_empty[7]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__4_n_0\
    );
\my_empty[7]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__4_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__4_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__4_n_0\
    );
\my_empty[7]_i_4__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__4_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__6_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__4_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__4_n_0\
    );
\my_full[4]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__4_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__4_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__4_n_0\
    );
\my_full[4]_i_4__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__4_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__4_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_12__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(17),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_16__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(7),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_17__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(3),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(15),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_22__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(11),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_18_23_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_24__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(6),
      I2 => mem_reg_0_15_12_17_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_29__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__5\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(14),
      I2 => mem_reg_0_15_24_29_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
\out_fifo_i_31__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(9),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_24_29_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_34__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__9\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(19),
      I2 => mem_reg_0_15_36_41_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
\out_fifo_i_41__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(2),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_44__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(16),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_42_47_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_48__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(5),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_49__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(1),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_36_41_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_53__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(13),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_48_53_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
\out_fifo_i_54__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(10),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_48_53_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_56__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(4),
      I2 => mem_reg_0_15_48_53_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
\out_fifo_i_61__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__5\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(12),
      I2 => mem_reg_0_15_60_65_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_63__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(8),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => mem_reg_0_15_54_59_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__9\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(18),
      I2 => mem_reg_0_15_66_71_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_6__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
\out_fifo_i_73__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[568]\(0),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_60_65_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(27),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(7)
    );
\out_fifo_i_75__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(26),
      I2 => mem_reg_0_15_78_79_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(6)
    );
\out_fifo_i_76__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(25),
      I2 => mem_reg_0_15_72_77_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(5)
    );
\out_fifo_i_77__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(24),
      I2 => mem_reg_0_15_72_77_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(4)
    );
\out_fifo_i_78__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(23),
      I2 => mem_reg_0_15_72_77_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_79__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(22),
      I2 => mem_reg_0_15_72_77_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_7__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_80__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(21),
      I2 => mem_reg_0_15_72_77_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_81__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[568]\(20),
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => ofifo_rst_reg,
      O => \rd_ptr_timing[3]_i_1__6_n_0\
    );
\rd_ptr_timing[3]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__6_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_24\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[569]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_24\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_24\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_24\ is
  signal \entry_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \^entry_cnt_reg[4]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_4 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_0 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_5 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_2 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_2 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_0 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_2 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_5 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_5 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_1 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_0 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_2 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_5 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__3_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__3_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__5_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__2\ : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__2\ : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__2\ : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__2\ : label is "soft_lutpair609";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__3\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__3\ : label is "soft_lutpair606";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__3\ : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__3\ : label is "soft_lutpair607";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_16__8\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \out_fifo_i_22__8\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \out_fifo_i_24__8\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \out_fifo_i_29__8\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \out_fifo_i_2__3\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \out_fifo_i_3__3\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \out_fifo_i_41__8\ : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of \out_fifo_i_49__5\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \out_fifo_i_4__3\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \out_fifo_i_5__3\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \out_fifo_i_61__6\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \out_fifo_i_6__3\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \out_fifo_i_79__6\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \out_fifo_i_7__2\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \out_fifo_i_8__2\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \out_fifo_i_9__2\ : label is "soft_lutpair612";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__6\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__6\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__5\ : label is "soft_lutpair619";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__5\ : label is "soft_lutpair619";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__9\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__9\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__5\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__2\ : label is "soft_lutpair618";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \entry_cnt_reg[4]_0\(2 downto 0) <= \^entry_cnt_reg[4]_0\(2 downto 0);
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__2_n_0\
    );
\entry_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__2_n_0\
    );
\entry_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^entry_cnt_reg[4]_0\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__2_n_0\
    );
\entry_cnt[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3__2_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^entry_cnt_reg[4]_0\(1),
      I4 => \^entry_cnt_reg[4]_0\(0),
      O => \entry_cnt[3]_i_1__2_n_0\
    );
\entry_cnt[4]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => ofifo_rst_reg,
      O => \entry_cnt[4]_i_1__2_n_0\
    );
\entry_cnt[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3__2_n_0\,
      I3 => \^entry_cnt_reg[4]_0\(0),
      I4 => \^entry_cnt_reg[4]_0\(2),
      I5 => \^entry_cnt_reg[4]_0\(1),
      O => \entry_cnt[4]_i_2__2_n_0\
    );
\entry_cnt[4]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ofifo_rst_reg,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3__2_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[0]_i_1__2_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[1]_i_1__2_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[2]_i_1__2_n_0\,
      Q => \^entry_cnt_reg[4]_0\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[3]_i_1__2_n_0\,
      Q => \^entry_cnt_reg[4]_0\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__2_n_0\,
      D => \entry_cnt[4]_i_2__2_n_0\,
      Q => \^entry_cnt_reg[4]_0\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(5 downto 4),
      DIB(1 downto 0) => phy_dout(7 downto 6),
      DIC(1 downto 0) => phy_dout(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => \my_empty_reg[7]_1\(2),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOC(1) => mem_reg_0_15_12_17_n_4,
      DOC(0) => \my_empty_reg[7]_1\(5),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(11 downto 10),
      DIB(1 downto 0) => phy_dout(13 downto 12),
      DIC(1 downto 0) => phy_dout(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_18_23_n_0,
      DOA(0) => \my_empty_reg[7]_1\(6),
      DOB(1) => \my_empty_reg[7]_1\(7),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(17 downto 16),
      DIB(1 downto 0) => phy_dout(19 downto 18),
      DIC(1 downto 0) => phy_dout(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOB(1) => \my_empty_reg[7]_1\(12),
      DOB(0) => mem_reg_0_15_24_29_n_3,
      DOC(1) => \my_empty_reg[7]_1\(13),
      DOC(0) => mem_reg_0_15_24_29_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(23 downto 22),
      DIB(1 downto 0) => phy_dout(25 downto 24),
      DIC(1 downto 0) => phy_dout(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOB(1) => \my_empty_reg[7]_1\(16),
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(29 downto 28),
      DIB(1 downto 0) => phy_dout(31 downto 30),
      DIC(1 downto 0) => phy_dout(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOB(1) => mem_reg_0_15_36_41_n_2,
      DOB(0) => \my_empty_reg[7]_1\(21),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => mem_reg_0_15_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(35 downto 34),
      DIB(1 downto 0) => phy_dout(37 downto 36),
      DIC(1 downto 0) => phy_dout(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOB(1) => mem_reg_0_15_42_47_n_2,
      DOB(0) => \my_empty_reg[7]_1\(24),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(41 downto 40),
      DIB(1 downto 0) => phy_dout(43 downto 42),
      DIC(1 downto 0) => phy_dout(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_48_53_n_0,
      DOA(0) => \my_empty_reg[7]_1\(27),
      DOB(1) => mem_reg_0_15_48_53_n_2,
      DOB(0) => \my_empty_reg[7]_1\(28),
      DOC(1) => \my_empty_reg[7]_1\(29),
      DOC(0) => mem_reg_0_15_48_53_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(47 downto 46),
      DIB(1 downto 0) => phy_dout(49 downto 48),
      DIC(1 downto 0) => phy_dout(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOC(1) => \my_empty_reg[7]_1\(34),
      DOC(0) => mem_reg_0_15_54_59_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(53 downto 52),
      DIB(1 downto 0) => phy_dout(55 downto 54),
      DIC(1 downto 0) => phy_dout(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(35),
      DOA(0) => mem_reg_0_15_60_65_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOC(1) => \my_empty_reg[7]_1\(38),
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(59 downto 58),
      DIB(1 downto 0) => phy_dout(61 downto 60),
      DIC(1 downto 0) => phy_dout(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => \my_empty_reg[7]_1\(43),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(1 downto 0),
      DIC(1 downto 0) => phy_dout(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_72_77_n_0,
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1) => mem_reg_0_15_72_77_n_2,
      DOB(0) => mem_reg_0_15_72_77_n_3,
      DOC(1) => mem_reg_0_15_72_77_n_4,
      DOC(0) => mem_reg_0_15_72_77_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => mem_reg_0_15_78_79_n_1,
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__5_n_0\
    );
\my_empty[7]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__3_n_0\
    );
\my_empty[7]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__3_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__3_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__3_n_0\
    );
\my_empty[7]_i_4__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__3_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__5_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__3_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__3_n_0\
    );
\my_full[4]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__3_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__3_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__3_n_0\
    );
\my_full[4]_i_4__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__3_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__3_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_12__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(17),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_16__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(7),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_17__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(3),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(15),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_22__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(11),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_18_23_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_24__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(6),
      I2 => mem_reg_0_15_12_17_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_29__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__5\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(14),
      I2 => mem_reg_0_15_24_29_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
\out_fifo_i_31__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(9),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_24_29_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_34__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__9\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(19),
      I2 => mem_reg_0_15_36_41_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
\out_fifo_i_41__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(2),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_44__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(16),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_42_47_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_48__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(5),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_49__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(1),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_36_41_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_53__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(13),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_48_53_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
\out_fifo_i_54__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(10),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_48_53_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_56__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(4),
      I2 => mem_reg_0_15_48_53_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
\out_fifo_i_61__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__5\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(12),
      I2 => mem_reg_0_15_60_65_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_63__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(8),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_54_59_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__9\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(18),
      I2 => mem_reg_0_15_66_71_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_6__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
\out_fifo_i_73__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[569]\(0),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_60_65_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(27),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(7)
    );
\out_fifo_i_75__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(26),
      I2 => mem_reg_0_15_78_79_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(6)
    );
\out_fifo_i_76__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(25),
      I2 => mem_reg_0_15_72_77_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(5)
    );
\out_fifo_i_77__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(24),
      I2 => mem_reg_0_15_72_77_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(4)
    );
\out_fifo_i_78__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(23),
      I2 => mem_reg_0_15_72_77_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_79__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(22),
      I2 => mem_reg_0_15_72_77_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_7__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_80__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(21),
      I2 => mem_reg_0_15_72_77_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_81__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[569]\(20),
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => ofifo_rst_reg,
      O => \rd_ptr_timing[3]_i_1__5_n_0\
    );
\rd_ptr_timing[3]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__5_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_27\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[570]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_27\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_27\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_27\ is
  signal \entry_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \^entry_cnt_reg[4]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_4 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_0 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_5 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_2 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_0 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_1 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_2 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_3 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_4 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_5 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_0 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_1 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_4 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_2 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_4 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__2_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__2_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__2_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__4_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__1\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__1\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__1\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__1\ : label is "soft_lutpair555";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__2\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__2\ : label is "soft_lutpair552";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__2\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__2\ : label is "soft_lutpair553";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_16__7\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \out_fifo_i_29__7\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of \out_fifo_i_2__2\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \out_fifo_i_3__2\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \out_fifo_i_41__7\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \out_fifo_i_43__9\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \out_fifo_i_45__8\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \out_fifo_i_47__8\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \out_fifo_i_49__8\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \out_fifo_i_4__2\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \out_fifo_i_5__2\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \out_fifo_i_69__5\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \out_fifo_i_6__2\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \out_fifo_i_7__1\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \out_fifo_i_8__1\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \out_fifo_i_9__1\ : label is "soft_lutpair558";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__5\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__5\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__4\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__4\ : label is "soft_lutpair565";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__7\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__7\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__4\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__1\ : label is "soft_lutpair564";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \entry_cnt_reg[4]_0\(2 downto 0) <= \^entry_cnt_reg[4]_0\(2 downto 0);
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__1_n_0\
    );
\entry_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__1_n_0\
    );
\entry_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^entry_cnt_reg[4]_0\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__1_n_0\
    );
\entry_cnt[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3__1_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^entry_cnt_reg[4]_0\(1),
      I4 => \^entry_cnt_reg[4]_0\(0),
      O => \entry_cnt[3]_i_1__1_n_0\
    );
\entry_cnt[4]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => ofifo_rst_reg,
      O => \entry_cnt[4]_i_1__1_n_0\
    );
\entry_cnt[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3__1_n_0\,
      I3 => \^entry_cnt_reg[4]_0\(0),
      I4 => \^entry_cnt_reg[4]_0\(2),
      I5 => \^entry_cnt_reg[4]_0\(1),
      O => \entry_cnt[4]_i_2__1_n_0\
    );
\entry_cnt[4]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ofifo_rst_reg,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3__1_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[0]_i_1__1_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[1]_i_1__1_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[2]_i_1__1_n_0\,
      Q => \^entry_cnt_reg[4]_0\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[3]_i_1__1_n_0\,
      Q => \^entry_cnt_reg[4]_0\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__1_n_0\,
      D => \entry_cnt[4]_i_2__1_n_0\,
      Q => \^entry_cnt_reg[4]_0\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(5 downto 4),
      DIB(1 downto 0) => phy_dout(7 downto 6),
      DIC(1 downto 0) => phy_dout(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => \my_empty_reg[7]_1\(2),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOC(1) => mem_reg_0_15_12_17_n_4,
      DOC(0) => \my_empty_reg[7]_1\(5),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(11 downto 10),
      DIB(1 downto 0) => phy_dout(13 downto 12),
      DIC(1 downto 0) => phy_dout(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_18_23_n_0,
      DOA(0) => \my_empty_reg[7]_1\(6),
      DOB(1) => \my_empty_reg[7]_1\(7),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(17 downto 16),
      DIB(1 downto 0) => phy_dout(19 downto 18),
      DIC(1 downto 0) => phy_dout(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOB(1) => \my_empty_reg[7]_1\(12),
      DOB(0) => mem_reg_0_15_24_29_n_3,
      DOC(1) => \my_empty_reg[7]_1\(13),
      DOC(0) => mem_reg_0_15_24_29_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(23 downto 22),
      DIB(1 downto 0) => phy_dout(25 downto 24),
      DIC(1 downto 0) => phy_dout(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOB(1) => \my_empty_reg[7]_1\(16),
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(29 downto 28),
      DIB(1 downto 0) => phy_dout(31 downto 30),
      DIC(1 downto 0) => phy_dout(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOB(1) => mem_reg_0_15_36_41_n_2,
      DOB(0) => \my_empty_reg[7]_1\(21),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => mem_reg_0_15_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(35 downto 34),
      DIB(1 downto 0) => phy_dout(37 downto 36),
      DIC(1 downto 0) => phy_dout(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_42_47_n_0,
      DOA(0) => mem_reg_0_15_42_47_n_1,
      DOB(1) => mem_reg_0_15_42_47_n_2,
      DOB(0) => mem_reg_0_15_42_47_n_3,
      DOC(1) => mem_reg_0_15_42_47_n_4,
      DOC(0) => mem_reg_0_15_42_47_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(41 downto 40),
      DIB(1 downto 0) => phy_dout(43 downto 42),
      DIC(1 downto 0) => phy_dout(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_48_53_n_0,
      DOA(0) => mem_reg_0_15_48_53_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOC(1) => mem_reg_0_15_48_53_n_4,
      DOC(0) => \my_empty_reg[7]_1\(24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(47 downto 46),
      DIB(1 downto 0) => phy_dout(49 downto 48),
      DIC(1 downto 0) => phy_dout(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOB(1) => mem_reg_0_15_54_59_n_2,
      DOB(0) => \my_empty_reg[7]_1\(27),
      DOC(1) => mem_reg_0_15_54_59_n_4,
      DOC(0) => \my_empty_reg[7]_1\(28),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(53 downto 52),
      DIB(1 downto 0) => phy_dout(55 downto 54),
      DIC(1 downto 0) => phy_dout(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(29),
      DOA(0) => mem_reg_0_15_60_65_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(59 downto 58),
      DIB(1 downto 0) => phy_dout(61 downto 60),
      DIC(1 downto 0) => phy_dout(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(34),
      DOA(0) => mem_reg_0_15_66_71_n_1,
      DOB(1) => \my_empty_reg[7]_1\(35),
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(1 downto 0),
      DIC(1 downto 0) => phy_dout(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(38),
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => \my_empty_reg[7]_1\(43),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__4_n_0\
    );
\my_empty[7]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__2_n_0\
    );
\my_empty[7]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__2_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__2_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__2_n_0\
    );
\my_empty[7]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__2_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__4_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__2_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__2_n_0\
    );
\my_full[4]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__2_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__2_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__2_n_0\
    );
\my_full[4]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__2_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__2_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_12__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(17),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_16__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(7),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_17__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(3),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(15),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_22__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(11),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_18_23_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_24__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(6),
      I2 => mem_reg_0_15_12_17_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_29__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__5\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(14),
      I2 => mem_reg_0_15_24_29_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
\out_fifo_i_31__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(9),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_24_29_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_34__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__9\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(19),
      I2 => mem_reg_0_15_36_41_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
\out_fifo_i_41__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(2),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_42__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(27),
      I2 => mem_reg_0_15_42_47_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(7)
    );
\out_fifo_i_43__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(26),
      I2 => mem_reg_0_15_42_47_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(6)
    );
\out_fifo_i_44__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(25),
      I2 => mem_reg_0_15_42_47_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(5)
    );
\out_fifo_i_45__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(24),
      I2 => mem_reg_0_15_42_47_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(4)
    );
\out_fifo_i_46__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(23),
      I2 => mem_reg_0_15_42_47_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(3)
    );
\out_fifo_i_47__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(22),
      I2 => mem_reg_0_15_42_47_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_48__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(21),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_49__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(20),
      I2 => mem_reg_0_15_36_41_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_52__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(16),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_48_53_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
\out_fifo_i_56__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(5),
      I2 => mem_reg_0_15_48_53_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_57__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(1),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_48_53_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
\out_fifo_i_61__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(13),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_60_65_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(2)
    );
\out_fifo_i_62__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(10),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_54_59_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_64__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__1\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(4),
      I2 => mem_reg_0_15_54_59_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_69__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__5\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(12),
      I2 => mem_reg_0_15_66_71_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
\out_fifo_i_71__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(8),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_66_71_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__9\,
      I1 => \write_buffer.wr_buf_out_data_reg[570]\(18),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_7__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_81__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[570]\(0),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => ofifo_rst_reg,
      O => \rd_ptr_timing[3]_i_1__4_n_0\
    );
\rd_ptr_timing[3]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__4_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_30\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    ofifo_rst_reg : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[571]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_30\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_30\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_30\ is
  signal \entry_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \^entry_cnt_reg[4]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_1 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_1 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_0 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_2 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_0 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_0 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_3 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_3 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_5 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_3 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_2 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_0 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_2 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_5 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_0 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_2 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_5 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__1_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__1_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__1_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__3_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__0\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__0\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__0\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__0\ : label is "soft_lutpair502";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__1\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__1\ : label is "soft_lutpair499";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__1\ : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__1\ : label is "soft_lutpair500";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_33__6\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \out_fifo_i_41__6\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \out_fifo_i_45__4\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \out_fifo_i_4__9\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \out_fifo_i_55__4\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \out_fifo_i_65__4\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \out_fifo_i_66__1\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \out_fifo_i_67__1\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \out_fifo_i_68__1\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \out_fifo_i_69__1\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \out_fifo_i_70__0\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \out_fifo_i_71__0\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \out_fifo_i_72__0\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \out_fifo_i_73__0\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \out_fifo_i_79__5\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \out_fifo_i_81__5\ : label is "soft_lutpair507";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__4\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__4\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__3\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__3\ : label is "soft_lutpair512";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__5\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__5\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__3\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__0\ : label is "soft_lutpair511";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \entry_cnt_reg[4]_0\(2 downto 0) <= \^entry_cnt_reg[4]_0\(2 downto 0);
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__0_n_0\
    );
\entry_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__0_n_0\
    );
\entry_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => ofifo_rst_reg,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^entry_cnt_reg[4]_0\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__0_n_0\
    );
\entry_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3__0_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^entry_cnt_reg[4]_0\(1),
      I4 => \^entry_cnt_reg[4]_0\(0),
      O => \entry_cnt[3]_i_1__0_n_0\
    );
\entry_cnt[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => ofifo_rst_reg,
      O => \entry_cnt[4]_i_1__0_n_0\
    );
\entry_cnt[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3__0_n_0\,
      I3 => \^entry_cnt_reg[4]_0\(0),
      I4 => \^entry_cnt_reg[4]_0\(2),
      I5 => \^entry_cnt_reg[4]_0\(1),
      O => \entry_cnt[4]_i_2__0_n_0\
    );
\entry_cnt[4]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ofifo_rst_reg,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3__0_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[0]_i_1__0_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[1]_i_1__0_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[2]_i_1__0_n_0\,
      Q => \^entry_cnt_reg[4]_0\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[3]_i_1__0_n_0\,
      Q => \^entry_cnt_reg[4]_0\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__0_n_0\,
      D => \entry_cnt[4]_i_2__0_n_0\,
      Q => \^entry_cnt_reg[4]_0\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(1 downto 0),
      DIB(1 downto 0) => phy_dout(3 downto 2),
      DIC(1 downto 0) => phy_dout(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => \my_empty_reg[7]_1\(2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(13 downto 12),
      DIB(1 downto 0) => phy_dout(15 downto 14),
      DIC(1 downto 0) => phy_dout(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(7),
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(19 downto 18),
      DIB(1 downto 0) => phy_dout(21 downto 20),
      DIC(1 downto 0) => phy_dout(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(12),
      DOA(0) => mem_reg_0_15_18_23_n_1,
      DOB(1) => \my_empty_reg[7]_1\(13),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(25 downto 24),
      DIB(1 downto 0) => phy_dout(27 downto 26),
      DIC(1 downto 0) => phy_dout(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(16),
      DOA(0) => mem_reg_0_15_24_29_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(31 downto 30),
      DIB(1 downto 0) => phy_dout(33 downto 32),
      DIC(1 downto 0) => phy_dout(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_30_35_n_0,
      DOA(0) => \my_empty_reg[7]_1\(21),
      DOB(1) => mem_reg_0_15_30_35_n_2,
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(37 downto 36),
      DIB(1 downto 0) => phy_dout(39 downto 38),
      DIC(1 downto 0) => phy_dout(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_36_41_n_0,
      DOA(0) => \my_empty_reg[7]_1\(24),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => \my_empty_reg[7]_1\(27),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(43 downto 42),
      DIB(1 downto 0) => phy_dout(45 downto 44),
      DIC(1 downto 0) => phy_dout(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_42_47_n_0,
      DOA(0) => \my_empty_reg[7]_1\(28),
      DOB(1) => \my_empty_reg[7]_1\(29),
      DOB(0) => mem_reg_0_15_42_47_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(49 downto 48),
      DIB(1 downto 0) => phy_dout(51 downto 50),
      DIC(1 downto 0) => phy_dout(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOB(1) => \my_empty_reg[7]_1\(34),
      DOB(0) => mem_reg_0_15_48_53_n_3,
      DOC(1) => \my_empty_reg[7]_1\(35),
      DOC(0) => mem_reg_0_15_48_53_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(55 downto 54),
      DIB(1 downto 0) => phy_dout(57 downto 56),
      DIC(1 downto 0) => phy_dout(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOB(1) => \my_empty_reg[7]_1\(38),
      DOB(0) => mem_reg_0_15_54_59_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(61 downto 60),
      DIB(1 downto 0) => phy_dout(63 downto 62),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOB(1) => mem_reg_0_15_60_65_n_2,
      DOB(0) => \my_empty_reg[7]_1\(43),
      DOC(1) => mem_reg_0_15_60_65_n_4,
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_66_71_n_0,
      DOA(0) => mem_reg_0_15_66_71_n_1,
      DOB(1) => mem_reg_0_15_66_71_n_2,
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => mem_reg_0_15_66_71_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(7 downto 6),
      DIB(1 downto 0) => phy_dout(9 downto 8),
      DIC(1 downto 0) => phy_dout(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => \my_empty_reg[7]_1\(5),
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => \my_empty_reg[7]_1\(6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_72_77_n_0,
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1) => mem_reg_0_15_72_77_n_2,
      DOB(0) => mem_reg_0_15_72_77_n_3,
      DOC(1) => mem_reg_0_15_72_77_n_4,
      DOC(0) => mem_reg_0_15_72_77_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => mem_reg_0_15_78_79_n_1,
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__3_n_0\
    );
\my_empty[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__1_n_0\
    );
\my_empty[7]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__1_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__1_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__1_n_0\
    );
\my_empty[7]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__1_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__3_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__1_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__1_n_0\
    );
\my_full[4]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__1_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__1_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__1_n_0\
    );
\my_full[4]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__1_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__1_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_13__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(15),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_14__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(11),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_16__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(6),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => ofifo_rst_reg,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(14),
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_23__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(9),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_18_23_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_26__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(19),
      I2 => mem_reg_0_15_30_35_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_33__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(2),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_24_29_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_36__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(16),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_36_41_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_40__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(5),
      I2 => mem_reg_0_15_30_35_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_41__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(1),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_45__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(13),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_42_47_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_46__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(10),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_42_47_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_48__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(4),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(17),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_0_5_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_53__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(12),
      I2 => mem_reg_0_15_48_53_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_55__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(8),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_48_53_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_58__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__9\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(18),
      I2 => mem_reg_0_15_60_65_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_65__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(0),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_54_59_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(7)
    );
\out_fifo_i_67__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(6)
    );
\out_fifo_i_68__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(5)
    );
\out_fifo_i_69__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(4)
    );
\out_fifo_i_70__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(3)
    );
\out_fifo_i_71__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(2)
    );
\out_fifo_i_72__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_73__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(27),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(7)
    );
\out_fifo_i_75__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(26),
      I2 => mem_reg_0_15_78_79_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(6)
    );
\out_fifo_i_76__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(25),
      I2 => mem_reg_0_15_72_77_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(5)
    );
\out_fifo_i_77__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(24),
      I2 => mem_reg_0_15_72_77_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(4)
    );
\out_fifo_i_78__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(23),
      I2 => mem_reg_0_15_72_77_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_79__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(22),
      I2 => mem_reg_0_15_72_77_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_80__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(21),
      I2 => mem_reg_0_15_72_77_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_81__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(20),
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[571]\(7),
      I2 => mem_reg_0_15_0_5_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[571]\(3),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => mem_reg_0_15_0_5_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => ofifo_rst_reg,
      O => \rd_ptr_timing[3]_i_1__3_n_0\
    );
\rd_ptr_timing[3]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__3_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => ofifo_rst_reg,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_7\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ofs_rdy_r_reg : out STD_LOGIC;
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    B_of_full : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[574]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_7\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_7\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_7\ is
  signal \entry_cnt[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3__5_n_0\ : STD_LOGIC;
  signal entry_cnt_reg : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_2 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_3 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_5 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_0 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_4 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_0 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_5 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_2 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_5 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_0 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_1 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_2 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_3 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_4 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_5 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_0 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_1 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_4 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_2 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_4 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_0 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_1 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__8_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__6_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__6_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__6_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__6_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__8_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__5\ : label is "soft_lutpair889";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__5\ : label is "soft_lutpair888";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__5\ : label is "soft_lutpair889";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__5\ : label is "soft_lutpair888";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__6\ : label is "soft_lutpair886";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__6\ : label is "soft_lutpair886";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__6\ : label is "soft_lutpair887";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__6\ : label is "soft_lutpair887";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_12__3\ : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of \out_fifo_i_24__3\ : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of \out_fifo_i_29__3\ : label is "soft_lutpair891";
  attribute SOFT_HLUTNM of \out_fifo_i_2__5\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \out_fifo_i_3__5\ : label is "soft_lutpair891";
  attribute SOFT_HLUTNM of \out_fifo_i_41__3\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \out_fifo_i_43__8\ : label is "soft_lutpair892";
  attribute SOFT_HLUTNM of \out_fifo_i_47__7\ : label is "soft_lutpair890";
  attribute SOFT_HLUTNM of \out_fifo_i_49__7\ : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of \out_fifo_i_4__5\ : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of \out_fifo_i_5__5\ : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of \out_fifo_i_69__3\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \out_fifo_i_6__5\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \out_fifo_i_7__4\ : label is "soft_lutpair890";
  attribute SOFT_HLUTNM of \out_fifo_i_8__4\ : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of \out_fifo_i_9__4\ : label is "soft_lutpair892";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__12\ : label is "soft_lutpair901";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__12\ : label is "soft_lutpair901";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__8\ : label is "soft_lutpair899";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__8\ : label is "soft_lutpair899";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__16\ : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__16\ : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__8\ : label is "soft_lutpair898";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__5\ : label is "soft_lutpair898";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__5_n_0\
    );
\entry_cnt[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => B_of_full,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__5_n_0\
    );
\entry_cnt[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => B_of_full,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => entry_cnt_reg(2),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__5_n_0\
    );
\entry_cnt[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3__5_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => entry_cnt_reg(3),
      I4 => entry_cnt_reg(2),
      O => \entry_cnt[3]_i_1__5_n_0\
    );
\entry_cnt[4]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => B_of_full,
      O => \entry_cnt[4]_i_1__5_n_0\
    );
\entry_cnt[4]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3__5_n_0\,
      I3 => entry_cnt_reg(2),
      I4 => entry_cnt_reg(4),
      I5 => entry_cnt_reg(3),
      O => \entry_cnt[4]_i_2__5_n_0\
    );
\entry_cnt[4]_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => B_of_full,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3__5_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[0]_i_1__5_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[1]_i_1__5_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[2]_i_1__5_n_0\,
      Q => entry_cnt_reg(2),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[3]_i_1__5_n_0\,
      Q => entry_cnt_reg(3),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__5_n_0\,
      D => \entry_cnt[4]_i_2__5_n_0\,
      Q => entry_cnt_reg(4),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1) => mem_reg_0_15_0_5_n_2,
      DOB(0) => mem_reg_0_15_0_5_n_3,
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => mem_reg_0_15_0_5_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => B_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(5 downto 4),
      DIB(1 downto 0) => phy_dout(7 downto 6),
      DIC(1 downto 0) => phy_dout(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_12_17_n_0,
      DOA(0) => \my_empty_reg[7]_1\(2),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOC(1) => mem_reg_0_15_12_17_n_4,
      DOC(0) => \my_empty_reg[7]_1\(5),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(11 downto 10),
      DIB(1 downto 0) => phy_dout(13 downto 12),
      DIC(1 downto 0) => phy_dout(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_18_23_n_0,
      DOA(0) => \my_empty_reg[7]_1\(6),
      DOB(1) => \my_empty_reg[7]_1\(7),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(17 downto 16),
      DIB(1 downto 0) => phy_dout(19 downto 18),
      DIC(1 downto 0) => phy_dout(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOB(1) => \my_empty_reg[7]_1\(12),
      DOB(0) => mem_reg_0_15_24_29_n_3,
      DOC(1) => \my_empty_reg[7]_1\(13),
      DOC(0) => mem_reg_0_15_24_29_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(23 downto 22),
      DIB(1 downto 0) => phy_dout(25 downto 24),
      DIC(1 downto 0) => phy_dout(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOB(1) => \my_empty_reg[7]_1\(16),
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(29 downto 28),
      DIB(1 downto 0) => phy_dout(31 downto 30),
      DIC(1 downto 0) => phy_dout(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOB(1) => mem_reg_0_15_36_41_n_2,
      DOB(0) => \my_empty_reg[7]_1\(21),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => mem_reg_0_15_36_41_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(35 downto 34),
      DIB(1 downto 0) => phy_dout(37 downto 36),
      DIC(1 downto 0) => phy_dout(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_42_47_n_0,
      DOA(0) => mem_reg_0_15_42_47_n_1,
      DOB(1) => mem_reg_0_15_42_47_n_2,
      DOB(0) => mem_reg_0_15_42_47_n_3,
      DOC(1) => mem_reg_0_15_42_47_n_4,
      DOC(0) => mem_reg_0_15_42_47_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(41 downto 40),
      DIB(1 downto 0) => phy_dout(43 downto 42),
      DIC(1 downto 0) => phy_dout(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_48_53_n_0,
      DOA(0) => mem_reg_0_15_48_53_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOC(1) => mem_reg_0_15_48_53_n_4,
      DOC(0) => \my_empty_reg[7]_1\(24),
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(47 downto 46),
      DIB(1 downto 0) => phy_dout(49 downto 48),
      DIC(1 downto 0) => phy_dout(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOB(1) => mem_reg_0_15_54_59_n_2,
      DOB(0) => \my_empty_reg[7]_1\(27),
      DOC(1) => mem_reg_0_15_54_59_n_4,
      DOC(0) => \my_empty_reg[7]_1\(28),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(53 downto 52),
      DIB(1 downto 0) => phy_dout(55 downto 54),
      DIC(1 downto 0) => phy_dout(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(29),
      DOA(0) => mem_reg_0_15_60_65_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(59 downto 58),
      DIB(1 downto 0) => phy_dout(61 downto 60),
      DIC(1 downto 0) => phy_dout(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(34),
      DOA(0) => mem_reg_0_15_66_71_n_1,
      DOB(1) => \my_empty_reg[7]_1\(35),
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => phy_dout(1 downto 0),
      DIC(1 downto 0) => phy_dout(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_6_11_n_0,
      DOA(0) => mem_reg_0_15_6_11_n_1,
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => mem_reg_0_15_6_11_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(38),
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => \my_empty_reg[7]_1\(43),
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => B_of_full,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__8_n_0\
    );
\my_empty[7]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => B_of_full,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__6_n_0\
    );
\my_empty[7]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__6_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__6_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__6_n_0\
    );
\my_empty[7]_i_4__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__6_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__8_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__6_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => B_of_full,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__6_n_0\
    );
\my_full[4]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__6_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__6_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__6_n_0\
    );
\my_full[4]_i_4__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__6_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__6_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
ofs_rdy_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => entry_cnt_reg(2),
      I1 => entry_cnt_reg(4),
      I2 => entry_cnt_reg(3),
      I3 => Q(0),
      I4 => Q(2),
      I5 => Q(1),
      O => ofs_rdy_r_reg
    );
\out_fifo_i_12__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(17),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_12_17_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_16__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(7),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_17__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(3),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_6_11_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => B_of_full,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(15),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(2)
    );
\out_fifo_i_22__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(11),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_18_23_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_24__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(6),
      I2 => mem_reg_0_15_12_17_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_29__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(14),
      I2 => mem_reg_0_15_24_29_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(7)
    );
\out_fifo_i_31__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(9),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_24_29_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_34__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(19),
      I2 => mem_reg_0_15_36_41_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_6_11_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(6)
    );
\out_fifo_i_41__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(2),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_42__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(27),
      I2 => mem_reg_0_15_42_47_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(7)
    );
\out_fifo_i_43__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(26),
      I2 => mem_reg_0_15_42_47_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(6)
    );
\out_fifo_i_44__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(25),
      I2 => mem_reg_0_15_42_47_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(5)
    );
\out_fifo_i_45__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(24),
      I2 => mem_reg_0_15_42_47_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(4)
    );
\out_fifo_i_46__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(23),
      I2 => mem_reg_0_15_42_47_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(3)
    );
\out_fifo_i_47__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(22),
      I2 => mem_reg_0_15_42_47_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_48__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(21),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_49__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(20),
      I2 => mem_reg_0_15_36_41_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(5)
    );
\out_fifo_i_52__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(16),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => mem_reg_0_15_48_53_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(2)
    );
\out_fifo_i_56__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(5),
      I2 => mem_reg_0_15_48_53_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_57__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(1),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_48_53_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(4)
    );
\out_fifo_i_61__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(13),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_60_65_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(2)
    );
\out_fifo_i_62__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(10),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_54_59_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_64__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(4),
      I2 => mem_reg_0_15_54_59_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_69__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(12),
      I2 => mem_reg_0_15_66_71_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_6__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(3)
    );
\out_fifo_i_71__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(8),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => mem_reg_0_15_66_71_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[574]\(18),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_7__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_81__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[574]\(0),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_0_5_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => B_of_full,
      O => \rd_ptr_timing[3]_i_1__8_n_0\
    );
\rd_ptr_timing[3]_i_2__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__8_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => B_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_9\ is
  port (
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    D8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D5 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    ofifo_rst : in STD_LOGIC;
    CLK : in STD_LOGIC;
    A_of_full : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__8\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_9\ : entity is "mig_7series_v2_3_ddr_of_pre_fifo";
end \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_9\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_9\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \entry_cnt[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \entry_cnt[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_0 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_1 : STD_LOGIC;
  signal mem_reg_0_15_0_5_n_4 : STD_LOGIC;
  signal mem_reg_0_15_12_17_n_1 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_1 : STD_LOGIC;
  signal mem_reg_0_15_18_23_n_3 : STD_LOGIC;
  signal mem_reg_0_15_24_29_n_1 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_0 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_2 : STD_LOGIC;
  signal mem_reg_0_15_30_35_n_3 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_0 : STD_LOGIC;
  signal mem_reg_0_15_36_41_n_4 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_0 : STD_LOGIC;
  signal mem_reg_0_15_42_47_n_3 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_3 : STD_LOGIC;
  signal mem_reg_0_15_48_53_n_5 : STD_LOGIC;
  signal mem_reg_0_15_54_59_n_3 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_2 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_4 : STD_LOGIC;
  signal mem_reg_0_15_60_65_n_5 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_0 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_1 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_2 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_3 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_4 : STD_LOGIC;
  signal mem_reg_0_15_66_71_n_5 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_2 : STD_LOGIC;
  signal mem_reg_0_15_6_11_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_0 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_1 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_2 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_3 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_4 : STD_LOGIC;
  signal mem_reg_0_15_72_77_n_5 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_0 : STD_LOGIC;
  signal mem_reg_0_15_78_79_n_1 : STD_LOGIC;
  signal my_empty0 : STD_LOGIC;
  signal \my_empty[1]_i_1__7_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_3__5_n_0\ : STD_LOGIC;
  signal \my_empty[7]_i_4__5_n_0\ : STD_LOGIC;
  signal \^my_empty_reg[1]_0\ : STD_LOGIC;
  signal \my_empty_reg_n_0_[7]\ : STD_LOGIC;
  signal my_full0 : STD_LOGIC;
  signal \my_full[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_3__5_n_0\ : STD_LOGIC;
  signal \my_full[4]_i_4__5_n_0\ : STD_LOGIC;
  signal \my_full_reg_n_0_[4]\ : STD_LOGIC;
  signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_ptr_reg_n_0_[3]\ : STD_LOGIC;
  signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rd_ptr_timing[3]_i_1__7_n_0\ : STD_LOGIC;
  signal wr_en : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of wr_en : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of wr_en : signal is "found";
  signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_ptr0 : STD_LOGIC;
  signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__4\ : label is "soft_lutpair834";
  attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__4\ : label is "soft_lutpair835";
  attribute SOFT_HLUTNM of \entry_cnt[3]_i_1__4\ : label is "soft_lutpair834";
  attribute SOFT_HLUTNM of \entry_cnt[4]_i_3__4\ : label is "soft_lutpair835";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is "";
  attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_78_79 : label is "";
  attribute SOFT_HLUTNM of \my_empty[7]_i_3__5\ : label is "soft_lutpair832";
  attribute SOFT_HLUTNM of \my_empty[7]_i_4__5\ : label is "soft_lutpair832";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \my_empty_reg[1]\ : label is "3";
  attribute syn_maxfan of \my_empty_reg[7]\ : label is "3";
  attribute SOFT_HLUTNM of \my_full[4]_i_3__5\ : label is "soft_lutpair833";
  attribute SOFT_HLUTNM of \my_full[4]_i_4__5\ : label is "soft_lutpair833";
  attribute syn_maxfan of \my_full_reg[4]\ : label is "3";
  attribute SOFT_HLUTNM of \out_fifo_i_33__2\ : label is "soft_lutpair838";
  attribute SOFT_HLUTNM of \out_fifo_i_41__2\ : label is "soft_lutpair837";
  attribute SOFT_HLUTNM of \out_fifo_i_45__1\ : label is "soft_lutpair843";
  attribute SOFT_HLUTNM of \out_fifo_i_4__7\ : label is "soft_lutpair842";
  attribute SOFT_HLUTNM of \out_fifo_i_55__0\ : label is "soft_lutpair836";
  attribute SOFT_HLUTNM of \out_fifo_i_65__0\ : label is "soft_lutpair839";
  attribute SOFT_HLUTNM of \out_fifo_i_66__2\ : label is "soft_lutpair841";
  attribute SOFT_HLUTNM of \out_fifo_i_67__2\ : label is "soft_lutpair838";
  attribute SOFT_HLUTNM of \out_fifo_i_68__2\ : label is "soft_lutpair840";
  attribute SOFT_HLUTNM of \out_fifo_i_69__2\ : label is "soft_lutpair836";
  attribute SOFT_HLUTNM of \out_fifo_i_70__1\ : label is "soft_lutpair842";
  attribute SOFT_HLUTNM of \out_fifo_i_71__1\ : label is "soft_lutpair837";
  attribute SOFT_HLUTNM of \out_fifo_i_72__1\ : label is "soft_lutpair843";
  attribute SOFT_HLUTNM of \out_fifo_i_73__1\ : label is "soft_lutpair839";
  attribute SOFT_HLUTNM of \out_fifo_i_79__2\ : label is "soft_lutpair841";
  attribute SOFT_HLUTNM of \out_fifo_i_81__2\ : label is "soft_lutpair840";
  attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10";
  attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__11\ : label is "soft_lutpair847";
  attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__11\ : label is "soft_lutpair847";
  attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__7\ : label is "soft_lutpair845";
  attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__7\ : label is "soft_lutpair845";
  attribute KEEP : string;
  attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__15\ : label is "soft_lutpair846";
  attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__15\ : label is "soft_lutpair846";
  attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__7\ : label is "soft_lutpair844";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__4\ : label is "soft_lutpair844";
  attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10";
  attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10";
  attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes";
  attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\;
\entry_cnt[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      O => \entry_cnt[0]_i_1__4_n_0\
    );
\entry_cnt[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A5595"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => A_of_full,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[1]_i_1__4_n_0\
    );
\entry_cnt[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F0080AAEA5515"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[0]\,
      I1 => A_of_full,
      I2 => phy_data_wr_en,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \^q\(0),
      I5 => \entry_cnt_reg_n_0_[1]\,
      O => \entry_cnt[2]_i_1__4_n_0\
    );
\entry_cnt[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => \entry_cnt[4]_i_3__4_n_0\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt_reg_n_0_[1]\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \entry_cnt[3]_i_1__4_n_0\
    );
\entry_cnt[4]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5003"
    )
        port map (
      I0 => \my_full_reg_n_0_[4]\,
      I1 => \my_empty_reg_n_0_[7]\,
      I2 => phy_data_wr_en,
      I3 => A_of_full,
      O => \entry_cnt[4]_i_1__4_n_0\
    );
\entry_cnt[4]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF8000FFFE0001"
    )
        port map (
      I0 => \entry_cnt_reg_n_0_[1]\,
      I1 => \entry_cnt_reg_n_0_[0]\,
      I2 => \entry_cnt[4]_i_3__4_n_0\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(1),
      O => \entry_cnt[4]_i_2__4_n_0\
    );
\entry_cnt[4]_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => A_of_full,
      I1 => phy_data_wr_en,
      I2 => \my_full_reg_n_0_[4]\,
      O => \entry_cnt[4]_i_3__4_n_0\
    );
\entry_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[0]_i_1__4_n_0\,
      Q => \entry_cnt_reg_n_0_[0]\,
      R => ofifo_rst
    );
\entry_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[1]_i_1__4_n_0\,
      Q => \entry_cnt_reg_n_0_[1]\,
      R => ofifo_rst
    );
\entry_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[2]_i_1__4_n_0\,
      Q => \^q\(0),
      R => ofifo_rst
    );
\entry_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[3]_i_1__4_n_0\,
      Q => \^q\(1),
      R => ofifo_rst
    );
\entry_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \entry_cnt[4]_i_1__4_n_0\,
      D => \entry_cnt[4]_i_2__4_n_0\,
      Q => \^q\(2),
      R => ofifo_rst
    );
mem_reg_0_15_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(1 downto 0),
      DIB(1 downto 0) => phy_dout(3 downto 2),
      DIC(1 downto 0) => phy_dout(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_0_5_n_0,
      DOA(0) => mem_reg_0_15_0_5_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(1 downto 0),
      DOC(1) => mem_reg_0_15_0_5_n_4,
      DOC(0) => \my_empty_reg[7]_1\(2),
      DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\mem_reg_0_15_0_5_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => A_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \^my_empty_reg[1]_0\,
      O => wr_en
    );
mem_reg_0_15_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(13 downto 12),
      DIB(1 downto 0) => phy_dout(15 downto 14),
      DIC(1 downto 0) => phy_dout(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(7),
      DOA(0) => mem_reg_0_15_12_17_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(9 downto 8),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(11 downto 10),
      DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(19 downto 18),
      DIB(1 downto 0) => phy_dout(21 downto 20),
      DIC(1 downto 0) => phy_dout(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(12),
      DOA(0) => mem_reg_0_15_18_23_n_1,
      DOB(1) => \my_empty_reg[7]_1\(13),
      DOB(0) => mem_reg_0_15_18_23_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(15 downto 14),
      DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(25 downto 24),
      DIB(1 downto 0) => phy_dout(27 downto 26),
      DIC(1 downto 0) => phy_dout(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1) => \my_empty_reg[7]_1\(16),
      DOA(0) => mem_reg_0_15_24_29_n_1,
      DOB(1 downto 0) => \my_empty_reg[7]_1\(18 downto 17),
      DOC(1 downto 0) => \my_empty_reg[7]_1\(20 downto 19),
      DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(31 downto 30),
      DIB(1 downto 0) => phy_dout(33 downto 32),
      DIC(1 downto 0) => phy_dout(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_30_35_n_0,
      DOA(0) => \my_empty_reg[7]_1\(21),
      DOB(1) => mem_reg_0_15_30_35_n_2,
      DOB(0) => mem_reg_0_15_30_35_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(23 downto 22),
      DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(37 downto 36),
      DIB(1 downto 0) => phy_dout(39 downto 38),
      DIC(1 downto 0) => phy_dout(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_36_41_n_0,
      DOA(0) => \my_empty_reg[7]_1\(24),
      DOB(1 downto 0) => \my_empty_reg[7]_1\(26 downto 25),
      DOC(1) => mem_reg_0_15_36_41_n_4,
      DOC(0) => \my_empty_reg[7]_1\(27),
      DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(43 downto 42),
      DIB(1 downto 0) => phy_dout(45 downto 44),
      DIC(1 downto 0) => phy_dout(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_42_47_n_0,
      DOA(0) => \my_empty_reg[7]_1\(28),
      DOB(1) => \my_empty_reg[7]_1\(29),
      DOB(0) => mem_reg_0_15_42_47_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(31 downto 30),
      DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(49 downto 48),
      DIB(1 downto 0) => phy_dout(51 downto 50),
      DIC(1 downto 0) => phy_dout(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(33 downto 32),
      DOB(1) => \my_empty_reg[7]_1\(34),
      DOB(0) => mem_reg_0_15_48_53_n_3,
      DOC(1) => \my_empty_reg[7]_1\(35),
      DOC(0) => mem_reg_0_15_48_53_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(55 downto 54),
      DIB(1 downto 0) => phy_dout(57 downto 56),
      DIC(1 downto 0) => phy_dout(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(37 downto 36),
      DOB(1) => \my_empty_reg[7]_1\(38),
      DOB(0) => mem_reg_0_15_54_59_n_3,
      DOC(1 downto 0) => \my_empty_reg[7]_1\(40 downto 39),
      DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(61 downto 60),
      DIB(1 downto 0) => phy_dout(63 downto 62),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(42 downto 41),
      DOB(1) => mem_reg_0_15_60_65_n_2,
      DOB(0) => \my_empty_reg[7]_1\(43),
      DOC(1) => mem_reg_0_15_60_65_n_4,
      DOC(0) => mem_reg_0_15_60_65_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_66_71_n_0,
      DOA(0) => mem_reg_0_15_66_71_n_1,
      DOB(1) => mem_reg_0_15_66_71_n_2,
      DOB(0) => mem_reg_0_15_66_71_n_3,
      DOC(1) => mem_reg_0_15_66_71_n_4,
      DOC(0) => mem_reg_0_15_66_71_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(7 downto 6),
      DIB(1 downto 0) => phy_dout(9 downto 8),
      DIC(1 downto 0) => phy_dout(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \my_empty_reg[7]_1\(4 downto 3),
      DOB(1) => mem_reg_0_15_6_11_n_2,
      DOB(0) => \my_empty_reg[7]_1\(5),
      DOC(1) => mem_reg_0_15_6_11_n_4,
      DOC(0) => \my_empty_reg[7]_1\(6),
      DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(65 downto 64),
      DIB(1 downto 0) => phy_dout(67 downto 66),
      DIC(1 downto 0) => phy_dout(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_72_77_n_0,
      DOA(0) => mem_reg_0_15_72_77_n_1,
      DOB(1) => mem_reg_0_15_72_77_n_2,
      DOB(0) => mem_reg_0_15_72_77_n_3,
      DOC(1) => mem_reg_0_15_72_77_n_4,
      DOC(0) => mem_reg_0_15_72_77_n_5,
      DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
mem_reg_0_15_78_79: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4) => '0',
      ADDRA(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRA(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRA(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRA(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRB(4) => '0',
      ADDRB(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRB(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRB(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRB(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRC(4) => '0',
      ADDRC(3) => \rd_ptr_reg_n_0_[3]\,
      ADDRC(2) => \rd_ptr_reg_n_0_[2]\,
      ADDRC(1) => \rd_ptr_reg_n_0_[1]\,
      ADDRC(0) => \rd_ptr_reg_n_0_[0]\,
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => wr_ptr(3 downto 0),
      DIA(1 downto 0) => phy_dout(71 downto 70),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => mem_reg_0_15_78_79_n_0,
      DOA(0) => mem_reg_0_15_78_79_n_1,
      DOB(1 downto 0) => NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED(1 downto 0),
      WCLK => CLK,
      WE => wr_en
    );
\my_empty[1]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => A_of_full,
      I2 => \^my_empty_reg[1]_0\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[1]_i_1__7_n_0\
    );
\my_empty[7]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF071F070"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => A_of_full,
      I2 => \my_empty_reg_n_0_[7]\,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => my_empty0,
      I5 => ofifo_rst,
      O => \my_empty[7]_i_1__5_n_0\
    );
\my_empty[7]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => wr_ptr_timing(2),
      I1 => \my_empty[7]_i_3__5_n_0\,
      I2 => wr_ptr_timing(3),
      I3 => \my_empty[7]_i_4__5_n_0\,
      I4 => \rd_ptr_reg_n_0_[2]\,
      O => my_empty0
    );
\my_empty[7]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => wr_ptr_timing(1),
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      I4 => wr_ptr_timing(0),
      O => \my_empty[7]_i_3__5_n_0\
    );
\my_empty[7]_i_4__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => wr_ptr_timing(0),
      I1 => wr_ptr_timing(1),
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[1]\,
      I4 => \rd_ptr_reg_n_0_[3]\,
      O => \my_empty[7]_i_4__5_n_0\
    );
\my_empty_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[1]_i_1__7_n_0\,
      Q => \^my_empty_reg[1]_0\,
      R => '0'
    );
\my_empty_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_empty[7]_i_1__5_n_0\,
      Q => \my_empty_reg_n_0_[7]\,
      R => '0'
    );
\my_full[4]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00FC80"
    )
        port map (
      I0 => my_full0,
      I1 => phy_data_wr_en,
      I2 => A_of_full,
      I3 => \my_full_reg_n_0_[4]\,
      I4 => \my_empty_reg_n_0_[7]\,
      I5 => ofifo_rst,
      O => \my_full[4]_i_1__5_n_0\
    );
\my_full[4]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4A400D08"
    )
        port map (
      I0 => rd_ptr_timing(2),
      I1 => \my_full[4]_i_3__5_n_0\,
      I2 => rd_ptr_timing(3),
      I3 => \my_full[4]_i_4__5_n_0\,
      I4 => wr_ptr(2),
      O => my_full0
    );
\my_full[4]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => rd_ptr_timing(1),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      I4 => rd_ptr_timing(0),
      O => \my_full[4]_i_3__5_n_0\
    );
\my_full[4]_i_4__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"84210842"
    )
        port map (
      I0 => rd_ptr_timing(0),
      I1 => rd_ptr_timing(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(1),
      I4 => wr_ptr(3),
      O => \my_full[4]_i_4__5_n_0\
    );
\my_full_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \my_full[4]_i_1__5_n_0\,
      Q => \my_full_reg_n_0_[4]\,
      R => '0'
    );
\out_fifo_i_13__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(15),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_12_17_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(2)
    );
\out_fifo_i_14__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(11),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_6_11_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(1)
    );
\out_fifo_i_16__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(6),
      I2 => mem_reg_0_15_6_11_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D1(0)
    );
\out_fifo_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^my_empty_reg[1]_0\,
      I1 => phy_data_wr_en,
      I2 => A_of_full,
      O => \my_empty_reg[7]_0\
    );
\out_fifo_i_21__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(14),
      I2 => mem_reg_0_15_18_23_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(1)
    );
\out_fifo_i_23__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(9),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_18_23_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D2(0)
    );
\out_fifo_i_26__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(19),
      I2 => mem_reg_0_15_30_35_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(1)
    );
\out_fifo_i_33__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(2),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_24_29_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D3(0)
    );
\out_fifo_i_36__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(16),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => mem_reg_0_15_36_41_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_40__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(5),
      I2 => mem_reg_0_15_30_35_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_41__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(1),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_30_35_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_45__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(13),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => mem_reg_0_15_42_47_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(2)
    );
\out_fifo_i_46__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(10),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => mem_reg_0_15_42_47_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(1)
    );
\out_fifo_i_48__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(4),
      I2 => mem_reg_0_15_36_41_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D5(0)
    );
\out_fifo_i_4__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(17),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => mem_reg_0_15_0_5_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(2)
    );
\out_fifo_i_53__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__6\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(12),
      I2 => mem_reg_0_15_48_53_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(1)
    );
\out_fifo_i_55__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(8),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => mem_reg_0_15_48_53_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D6(0)
    );
\out_fifo_i_58__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(18),
      I2 => mem_reg_0_15_60_65_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_65__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(0),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_54_59_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_66__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(7)
    );
\out_fifo_i_67__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(6)
    );
\out_fifo_i_68__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_2,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(5)
    );
\out_fifo_i_69__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_3,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(4)
    );
\out_fifo_i_70__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_0,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(3)
    );
\out_fifo_i_71__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_66_71_n_1,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(2)
    );
\out_fifo_i_72__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_4,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_73__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => mem_reg_0_15_60_65_n_5,
      I1 => \^my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_74__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(27),
      I2 => mem_reg_0_15_78_79_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(7)
    );
\out_fifo_i_75__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(26),
      I2 => mem_reg_0_15_78_79_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(6)
    );
\out_fifo_i_76__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(25),
      I2 => mem_reg_0_15_72_77_n_4,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(5)
    );
\out_fifo_i_77__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(24),
      I2 => mem_reg_0_15_72_77_n_5,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(4)
    );
\out_fifo_i_78__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(23),
      I2 => mem_reg_0_15_72_77_n_2,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_79__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(22),
      I2 => mem_reg_0_15_72_77_n_3,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_80__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(21),
      I2 => mem_reg_0_15_72_77_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_81__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => init_calib_complete_reg_rep,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(20),
      I2 => mem_reg_0_15_72_77_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__2\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(7),
      I2 => mem_reg_0_15_0_5_n_0,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(1)
    );
\out_fifo_i_9__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBF0"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[575]\(3),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => mem_reg_0_15_0_5_n_1,
      I3 => \^my_empty_reg[1]_0\,
      O => D0(0)
    );
\rd_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(0),
      Q => \rd_ptr_reg_n_0_[0]\,
      R => ofifo_rst
    );
\rd_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(1),
      Q => \rd_ptr_reg_n_0_[1]\,
      R => ofifo_rst
    );
\rd_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(2),
      Q => \rd_ptr_reg_n_0_[2]\,
      R => ofifo_rst
    );
\rd_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(3),
      Q => \rd_ptr_reg_n_0_[3]\,
      R => ofifo_rst
    );
\rd_ptr_timing[0]_i_1__11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      O => nxt_rd_ptr(0)
    );
\rd_ptr_timing[1]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      O => nxt_rd_ptr(1)
    );
\rd_ptr_timing[2]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[2]\,
      I1 => \rd_ptr_reg_n_0_[0]\,
      I2 => \rd_ptr_reg_n_0_[1]\,
      I3 => \rd_ptr_reg_n_0_[3]\,
      O => nxt_rd_ptr(2)
    );
\rd_ptr_timing[3]_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \my_empty_reg_n_0_[7]\,
      I1 => A_of_full,
      O => \rd_ptr_timing[3]_i_1__7_n_0\
    );
\rd_ptr_timing[3]_i_2__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rd_ptr_reg_n_0_[3]\,
      I1 => \rd_ptr_reg_n_0_[1]\,
      I2 => \rd_ptr_reg_n_0_[0]\,
      I3 => \rd_ptr_reg_n_0_[2]\,
      O => nxt_rd_ptr(3)
    );
\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(0),
      Q => rd_ptr_timing(0),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(1),
      Q => rd_ptr_timing(1),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(2),
      Q => rd_ptr_timing(2),
      R => ofifo_rst
    );
\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_ptr_timing[3]_i_1__7_n_0\,
      D => nxt_rd_ptr(3),
      Q => rd_ptr_timing(3),
      R => ofifo_rst
    );
\wr_ptr[0]_i_1__15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      O => nxt_wr_ptr(0)
    );
\wr_ptr[1]_i_1__15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      O => nxt_wr_ptr(1)
    );
\wr_ptr[2]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA6A"
    )
        port map (
      I0 => wr_ptr(2),
      I1 => wr_ptr(0),
      I2 => wr_ptr(1),
      I3 => wr_ptr(3),
      O => nxt_wr_ptr(2)
    );
\wr_ptr[3]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"082A"
    )
        port map (
      I0 => phy_data_wr_en,
      I1 => A_of_full,
      I2 => \my_full_reg_n_0_[4]\,
      I3 => \my_empty_reg_n_0_[7]\,
      O => wr_ptr0
    );
\wr_ptr[3]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => wr_ptr(3),
      I1 => wr_ptr(1),
      I2 => wr_ptr(0),
      I3 => wr_ptr(2),
      O => nxt_wr_ptr(3)
    );
\wr_ptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr(0),
      R => ofifo_rst
    );
\wr_ptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr(1),
      R => ofifo_rst
    );
\wr_ptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr(2),
      R => ofifo_rst
    );
\wr_ptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr(3),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(0),
      Q => wr_ptr_timing(0),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(1),
      Q => wr_ptr_timing(1),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(2),
      Q => wr_ptr_timing(2),
      R => ofifo_rst
    );
\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_ptr0,
      D => nxt_wr_ptr(3),
      Q => wr_ptr_timing(3),
      R => ofifo_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay is
  port (
    ck_addr_cmd_delay_done : out STD_LOGIC;
    cmd_po_en_stg2_f : out STD_LOGIC;
    \po_counter_read_val_reg[8]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : out STD_LOGIC;
    D_po_fine_enable102_out : out STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_4\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_7\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_8\ : out STD_LOGIC;
    \init_state_r_reg[0]\ : out STD_LOGIC;
    ctl_lane_cnt : out STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    po_enstg2_f : in STD_LOGIC_VECTOR ( 0 to 0 );
    calib_in_common : in STD_LOGIC;
    \calib_zero_inputs_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_mc_go : in STD_LOGIC;
    cnt_pwron_cke_done_r_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC;
    p_1_in : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    dqs_po_dec_done : in STD_LOGIC;
    cmd_delay_start0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay : entity is "mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay";
end mig_7series_0_mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay is
  signal \^ck_addr_cmd_delay_done\ : STD_LOGIC;
  signal \^ctl_lane_cnt\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ctl_lane_cnt1 : STD_LOGIC;
  signal \ctl_lane_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal delay_dec_done : STD_LOGIC;
  signal delay_dec_done_i_1_n_0 : STD_LOGIC;
  signal delay_done_r3_reg_srl3_n_0 : STD_LOGIC;
  signal delaydec_cnt_r0 : STD_LOGIC;
  signal delaydec_cnt_r10_in : STD_LOGIC;
  signal \delaydec_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \delaydec_cnt_r_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal po_cnt_dec : STD_LOGIC;
  signal \po_cnt_dec_i_1__0_n_0\ : STD_LOGIC;
  signal wait_cnt_r0 : STD_LOGIC;
  signal \wait_cnt_r0__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \wait_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wait_cnt_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \wait_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \wait_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \wait_cnt_r_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute srl_name : string;
  attribute srl_name of delay_done_r3_reg_srl3 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 ";
  attribute syn_maxfan : string;
  attribute syn_maxfan of delay_done_r4_reg : label is "10";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \delaydec_cnt_r[0]_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \delaydec_cnt_r[2]_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \delaydec_cnt_r[3]_i_1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \delaydec_cnt_r[4]_i_1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of phaser_out_i_2 : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \phaser_out_i_2__3\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \phaser_out_i_2__4\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \phaser_out_i_2__5\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \phaser_out_i_2__6\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \phaser_out_i_2__7\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \phaser_out_i_2__8\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of phaser_out_i_3 : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \phaser_out_i_3__0\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \phaser_out_i_3__1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \wait_cnt_r[1]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \wait_cnt_r[2]_i_1__0\ : label is "soft_lutpair79";
begin
  ck_addr_cmd_delay_done <= \^ck_addr_cmd_delay_done\;
  ctl_lane_cnt(2 downto 0) <= \^ctl_lane_cnt\(2 downto 0);
\ctl_lane_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000006000000"
    )
        port map (
      I0 => \^ctl_lane_cnt\(0),
      I1 => delaydec_cnt_r10_in,
      I2 => \rstdiv0_sync_r1_reg_rep__23\,
      I3 => dqs_po_dec_done,
      I4 => pi_fine_dly_dec_done,
      I5 => ctl_lane_cnt1,
      O => \ctl_lane_cnt[0]_i_1_n_0\
    );
\ctl_lane_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DEEE0000"
    )
        port map (
      I0 => \^ctl_lane_cnt\(1),
      I1 => ctl_lane_cnt1,
      I2 => delaydec_cnt_r10_in,
      I3 => \^ctl_lane_cnt\(0),
      I4 => cmd_delay_start0,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \ctl_lane_cnt[1]_i_1_n_0\
    );
\ctl_lane_cnt[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EF"
    )
        port map (
      I0 => \^ctl_lane_cnt\(0),
      I1 => \^ctl_lane_cnt\(2),
      I2 => \^ctl_lane_cnt\(1),
      I3 => \ctl_lane_cnt[2]_i_2_n_0\,
      O => delaydec_cnt_r10_in
    );
\ctl_lane_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000B4F0"
    )
        port map (
      I0 => \ctl_lane_cnt[2]_i_2_n_0\,
      I1 => \^ctl_lane_cnt\(1),
      I2 => \^ctl_lane_cnt\(2),
      I3 => \^ctl_lane_cnt\(0),
      I4 => p_1_in,
      I5 => ctl_lane_cnt1,
      O => \ctl_lane_cnt[2]_i_1_n_0\
    );
\ctl_lane_cnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(5),
      I1 => \delaydec_cnt_r_reg__0\(3),
      I2 => \delaydec_cnt_r_reg__0\(1),
      I3 => \delaydec_cnt_r_reg__0\(2),
      I4 => \delaydec_cnt_r_reg__0\(4),
      I5 => \delaydec_cnt_r_reg__0\(0),
      O => \ctl_lane_cnt[2]_i_2_n_0\
    );
\ctl_lane_cnt[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => \^ctl_lane_cnt\(1),
      I1 => \^ctl_lane_cnt\(2),
      I2 => \^ctl_lane_cnt\(0),
      I3 => \delaydec_cnt_r_reg__0\(0),
      I4 => delay_dec_done,
      I5 => \ctl_lane_cnt[2]_i_5_n_0\,
      O => ctl_lane_cnt1
    );
\ctl_lane_cnt[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(4),
      I1 => \delaydec_cnt_r_reg__0\(2),
      I2 => \delaydec_cnt_r_reg__0\(1),
      I3 => \delaydec_cnt_r_reg__0\(3),
      I4 => \delaydec_cnt_r_reg__0\(5),
      O => \ctl_lane_cnt[2]_i_5_n_0\
    );
\ctl_lane_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ctl_lane_cnt[0]_i_1_n_0\,
      Q => \^ctl_lane_cnt\(0),
      R => '0'
    );
\ctl_lane_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ctl_lane_cnt[1]_i_1_n_0\,
      Q => \^ctl_lane_cnt\(1),
      R => '0'
    );
\ctl_lane_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ctl_lane_cnt[2]_i_1_n_0\,
      Q => \^ctl_lane_cnt\(2),
      R => '0'
    );
delay_dec_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAABAA"
    )
        port map (
      I0 => delay_dec_done,
      I1 => \^ctl_lane_cnt\(0),
      I2 => \^ctl_lane_cnt\(2),
      I3 => \^ctl_lane_cnt\(1),
      I4 => \ctl_lane_cnt[2]_i_2_n_0\,
      I5 => p_1_in,
      O => delay_dec_done_i_1_n_0
    );
delay_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => delay_dec_done_i_1_n_0,
      Q => delay_dec_done,
      R => '0'
    );
delay_done_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => delay_dec_done,
      Q => delay_done_r3_reg_srl3_n_0
    );
delay_done_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => delay_done_r3_reg_srl3_n_0,
      Q => \^ck_addr_cmd_delay_done\,
      R => '0'
    );
\delaydec_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(0),
      O => \delaydec_cnt_r[0]_i_1_n_0\
    );
\delaydec_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(0),
      I1 => \delaydec_cnt_r_reg__0\(1),
      O => \delaydec_cnt_r[1]_i_1_n_0\
    );
\delaydec_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(0),
      I1 => \delaydec_cnt_r_reg__0\(1),
      I2 => \delaydec_cnt_r_reg__0\(2),
      O => \delaydec_cnt_r[2]_i_1_n_0\
    );
\delaydec_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(0),
      I1 => \delaydec_cnt_r_reg__0\(1),
      I2 => \delaydec_cnt_r_reg__0\(2),
      I3 => \delaydec_cnt_r_reg__0\(3),
      O => \delaydec_cnt_r[3]_i_1_n_0\
    );
\delaydec_cnt_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(0),
      I1 => \delaydec_cnt_r_reg__0\(2),
      I2 => \delaydec_cnt_r_reg__0\(1),
      I3 => \delaydec_cnt_r_reg__0\(3),
      I4 => \delaydec_cnt_r_reg__0\(4),
      O => \delaydec_cnt_r[4]_i_1_n_0\
    );
\delaydec_cnt_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFBF"
    )
        port map (
      I0 => delaydec_cnt_r10_in,
      I1 => pi_fine_dly_dec_done,
      I2 => dqs_po_dec_done,
      I3 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \delaydec_cnt_r[5]_i_1_n_0\
    );
\delaydec_cnt_r[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ctl_lane_cnt[2]_i_2_n_0\,
      I1 => po_cnt_dec,
      O => delaydec_cnt_r0
    );
\delaydec_cnt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => \delaydec_cnt_r_reg__0\(0),
      I1 => \delaydec_cnt_r_reg__0\(3),
      I2 => \delaydec_cnt_r_reg__0\(1),
      I3 => \delaydec_cnt_r_reg__0\(2),
      I4 => \delaydec_cnt_r_reg__0\(4),
      I5 => \delaydec_cnt_r_reg__0\(5),
      O => \delaydec_cnt_r[5]_i_3_n_0\
    );
\delaydec_cnt_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[0]_i_1_n_0\,
      Q => \delaydec_cnt_r_reg__0\(0),
      S => \delaydec_cnt_r[5]_i_1_n_0\
    );
\delaydec_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[1]_i_1_n_0\,
      Q => \delaydec_cnt_r_reg__0\(1),
      R => \delaydec_cnt_r[5]_i_1_n_0\
    );
\delaydec_cnt_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[2]_i_1_n_0\,
      Q => \delaydec_cnt_r_reg__0\(2),
      S => \delaydec_cnt_r[5]_i_1_n_0\
    );
\delaydec_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[3]_i_1_n_0\,
      Q => \delaydec_cnt_r_reg__0\(3),
      S => \delaydec_cnt_r[5]_i_1_n_0\
    );
\delaydec_cnt_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[4]_i_1_n_0\,
      Q => \delaydec_cnt_r_reg__0\(4),
      S => \delaydec_cnt_r[5]_i_1_n_0\
    );
\delaydec_cnt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => delaydec_cnt_r0,
      D => \delaydec_cnt_r[5]_i_3_n_0\,
      Q => \delaydec_cnt_r_reg__0\(5),
      R => \delaydec_cnt_r[5]_i_1_n_0\
    );
\init_state_r[0]_i_37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^ck_addr_cmd_delay_done\,
      I1 => phy_mc_go,
      I2 => cnt_pwron_cke_done_r_reg,
      O => \init_state_r_reg[0]\
    );
phaser_out_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => po_enstg2_f(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]\
    );
\phaser_out_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => po_enstg2_f(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_2\
    );
\phaser_out_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => po_enstg2_f(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_3\
    );
\phaser_out_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => po_enstg2_f(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_4\
    );
\phaser_out_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => po_enstg2_f(0),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_5\
    );
\phaser_out_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => po_enstg2_f(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_6\
    );
\phaser_out_i_2__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => po_enstg2_f(0),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_7\
    );
\phaser_out_i_2__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => po_enstg2_f(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_8\
    );
phaser_out_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => calib_in_common,
      I1 => Q(0),
      I2 => po_enstg2_f(0),
      I3 => Q(1),
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]_0\
    );
\phaser_out_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => calib_in_common,
      I1 => Q(0),
      I2 => po_enstg2_f(0),
      I3 => Q(1),
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]_1\
    );
\phaser_out_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => calib_in_common,
      I1 => Q(1),
      I2 => Q(0),
      I3 => po_enstg2_f(0),
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => D_po_fine_enable102_out
    );
\po_cnt_dec_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \wait_cnt_r_reg__0\(2),
      I1 => \wait_cnt_r_reg__0\(1),
      I2 => \wait_cnt_r_reg__0\(3),
      I3 => \wait_cnt_r_reg__0\(0),
      I4 => p_1_in,
      I5 => \ctl_lane_cnt[2]_i_2_n_0\,
      O => \po_cnt_dec_i_1__0_n_0\
    );
po_cnt_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_cnt_dec_i_1__0_n_0\,
      Q => po_cnt_dec,
      R => '0'
    );
po_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_cnt_dec,
      Q => cmd_po_en_stg2_f,
      R => SR(0)
    );
\wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wait_cnt_r_reg__0\(0),
      O => \wait_cnt_r0__0\(0)
    );
\wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \wait_cnt_r_reg__0\(0),
      I1 => \wait_cnt_r_reg__0\(1),
      O => \wait_cnt_r[1]_i_1_n_0\
    );
\wait_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \wait_cnt_r_reg__0\(1),
      I1 => \wait_cnt_r_reg__0\(0),
      I2 => \wait_cnt_r_reg__0\(2),
      O => \wait_cnt_r[2]_i_1__0_n_0\
    );
\wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => po_cnt_dec,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \wait_cnt_r[3]_i_1_n_0\
    );
\wait_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C0C0C0C0C0C0C080"
    )
        port map (
      I0 => \wait_cnt_r_reg__0\(0),
      I1 => pi_fine_dly_dec_done,
      I2 => dqs_po_dec_done,
      I3 => \wait_cnt_r_reg__0\(2),
      I4 => \wait_cnt_r_reg__0\(1),
      I5 => \wait_cnt_r_reg__0\(3),
      O => wait_cnt_r0
    );
\wait_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \wait_cnt_r_reg__0\(0),
      I1 => \wait_cnt_r_reg__0\(1),
      I2 => \wait_cnt_r_reg__0\(2),
      I3 => \wait_cnt_r_reg__0\(3),
      O => \wait_cnt_r[3]_i_3__0_n_0\
    );
\wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(0),
      Q => \wait_cnt_r_reg__0\(0),
      R => \wait_cnt_r[3]_i_1_n_0\
    );
\wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[1]_i_1_n_0\,
      Q => \wait_cnt_r_reg__0\(1),
      R => \wait_cnt_r[3]_i_1_n_0\
    );
\wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[2]_i_1__0_n_0\,
      Q => \wait_cnt_r_reg__0\(2),
      R => \wait_cnt_r[3]_i_1_n_0\
    );
\wait_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[3]_i_3__0_n_0\,
      Q => \wait_cnt_r_reg__0\(3),
      S => \wait_cnt_r[3]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_dqs_found_cal_hr is
  port (
    init_dqsfound_done_r2 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]_0\ : out STD_LOGIC;
    ififo_rst_reg : out STD_LOGIC;
    ififo_rst_reg_0 : out STD_LOGIC;
    ififo_rst_reg_1 : out STD_LOGIC;
    ififo_rst_reg_2 : out STD_LOGIC;
    ififo_rst_reg_3 : out STD_LOGIC;
    ififo_rst_reg_4 : out STD_LOGIC;
    ififo_rst_reg_5 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_4\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_7\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_8\ : out STD_LOGIC;
    D_po_fine_inc108_out : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : out STD_LOGIC;
    \calib_data_offset_0_reg[5]\ : out STD_LOGIC;
    \calib_data_offset_0_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_0_reg[4]\ : out STD_LOGIC;
    \calib_data_offset_0_reg[2]\ : out STD_LOGIC;
    \calib_data_offset_0_reg[1]\ : out STD_LOGIC;
    \calib_data_offset_0_reg[0]\ : out STD_LOGIC;
    \calib_data_offset_1_reg[5]\ : out STD_LOGIC;
    \calib_data_offset_1_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_1_reg[4]\ : out STD_LOGIC;
    \calib_data_offset_1_reg[2]\ : out STD_LOGIC;
    \calib_data_offset_1_reg[1]\ : out STD_LOGIC;
    \calib_data_offset_1_reg[0]\ : out STD_LOGIC;
    \calib_data_offset_2_reg[5]\ : out STD_LOGIC;
    \calib_data_offset_2_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_data_offset_2_reg[4]\ : out STD_LOGIC;
    \calib_data_offset_2_reg[2]\ : out STD_LOGIC;
    \calib_data_offset_2_reg[1]\ : out STD_LOGIC;
    \calib_data_offset_2_reg[0]\ : out STD_LOGIC;
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\ : out STD_LOGIC;
    pi_dqs_found_done : out STD_LOGIC;
    \init_state_r_reg[1]\ : out STD_LOGIC;
    pi_dqs_found_rank_done : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg\ : out STD_LOGIC;
    ififo_rst_reg0 : out STD_LOGIC;
    ofifo_rst_reg0 : out STD_LOGIC;
    ofifo_rst_reg0_5 : out STD_LOGIC;
    ofifo_rst_reg0_7 : out STD_LOGIC;
    ofifo_rst_reg0_9 : out STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]\ : out STD_LOGIC;
    ctl_lane_sel : out STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ : out STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.calib_in_common_reg_0\ : out STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ck_po_stg2_f_en : out STD_LOGIC;
    dqs_found_prech_req : out STD_LOGIC;
    CLK : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    calib_in_common : in STD_LOGIC;
    \calib_zero_inputs_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    dqs_po_dec_done : in STD_LOGIC;
    pi_f_inc_reg : in STD_LOGIC;
    cmd_delay_start0 : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dqs_po_stg2_f_incdec : in STD_LOGIC;
    sent_col : in STD_LOGIC;
    \grant_r_reg[3]\ : in STD_LOGIC;
    pi_dqs_found_done_r1 : in STD_LOGIC;
    rdlvl_stg1_done_reg : in STD_LOGIC;
    prech_req_posedge_r_reg : in STD_LOGIC;
    ck_addr_cmd_delay_done : in STD_LOGIC;
    rdlvl_stg1_done_reg_0 : in STD_LOGIC;
    phy_if_reset : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    A_rst_primitives_15 : in STD_LOGIC;
    ctl_lane_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0\ : in STD_LOGIC;
    pi_f_dec_reg : in STD_LOGIC;
    pi_calib_done : in STD_LOGIC;
    tempmon_pi_f_inc : in STD_LOGIC;
    tempmon_pi_f_dec : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    pi_dqs_found_lanes : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rstdiv0_sync_r1_reg_rep__17\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    prech_done : in STD_LOGIC;
    detect_pi_found_dqs : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pi_dqs_found_start_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_dqs_found_cal_hr : entity is "mig_7series_v2_3_ddr_phy_dqs_found_cal_hr";
end mig_7series_0_mig_7series_v2_3_ddr_phy_dqs_found_cal_hr;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_dqs_found_cal_hr is
  signal \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fine_adj_state_r_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \calib_zero_inputs[2]_i_2_n_0\ : STD_LOGIC;
  signal \calib_zero_inputs[2]_i_3_n_0\ : STD_LOGIC;
  signal \^ck_po_stg2_f_en\ : STD_LOGIC;
  signal ck_po_stg2_f_en_i_1_n_0 : STD_LOGIC;
  signal ck_po_stg2_f_indec : STD_LOGIC;
  signal ck_po_stg2_f_indec_i_1_n_0 : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_data_offset_1_reg[5]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^cmd_pipe_plus.mc_data_offset_2_reg[5]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^cmd_pipe_plus.mc_data_offset_reg[5]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \ctl_lane_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \ctl_lane_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
  signal ctl_lane_cnt_0 : STD_LOGIC;
  signal \^ctl_lane_sel\ : STD_LOGIC;
  signal dec_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \dec_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[1]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[2]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[4]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_6_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_7_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \dec_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \dec_cnt_reg[1]_i_5_n_0\ : STD_LOGIC;
  signal \dec_cnt_reg[1]_i_5_n_1\ : STD_LOGIC;
  signal \dec_cnt_reg[1]_i_5_n_2\ : STD_LOGIC;
  signal \dec_cnt_reg[1]_i_5_n_3\ : STD_LOGIC;
  signal \dec_cnt_reg[1]_i_5_n_4\ : STD_LOGIC;
  signal \dec_cnt_reg[1]_i_5_n_5\ : STD_LOGIC;
  signal \dec_cnt_reg[1]_i_5_n_6\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_6_n_3\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_6_n_6\ : STD_LOGIC;
  signal \dec_cnt_reg[4]_i_6_n_7\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \dec_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal detect_rd_cnt0 : STD_LOGIC;
  signal \detect_rd_cnt0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \detect_rd_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \detect_rd_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal dqs_found_done_r0 : STD_LOGIC;
  signal dqs_found_done_r_i_2_n_0 : STD_LOGIC;
  signal dqs_found_done_r_i_3_n_0 : STD_LOGIC;
  signal \^dqs_found_prech_req\ : STD_LOGIC;
  signal dqs_found_prech_req_i_1_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_2_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_4_n_0 : STD_LOGIC;
  signal dqs_found_prech_req_i_8_n_0 : STD_LOGIC;
  signal dqs_found_start_r : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_0\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_1\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_2\ : STD_LOGIC;
  signal final_data_offset_mc : STD_LOGIC;
  signal final_dec_done_i_1_n_0 : STD_LOGIC;
  signal final_dec_done_reg_n_0 : STD_LOGIC;
  signal fine_adj_state_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of fine_adj_state_r : signal is "yes";
  signal fine_adj_state_r034_out : STD_LOGIC;
  signal fine_adj_state_r1 : STD_LOGIC;
  signal fine_adj_state_r112_out : STD_LOGIC;
  signal fine_adj_state_r114_out : STD_LOGIC;
  signal fine_adj_state_r144_out : STD_LOGIC;
  signal fine_adj_state_r147_out : STD_LOGIC;
  signal fine_adj_state_r185_out : STD_LOGIC;
  signal fine_adj_state_r18_out : STD_LOGIC;
  signal fine_adj_state_r19_out : STD_LOGIC;
  signal fine_adj_state_r3 : STD_LOGIC;
  signal fine_adjust_done_r_i_1_n_0 : STD_LOGIC;
  signal fine_adjust_done_r_reg_n_0 : STD_LOGIC;
  signal fine_adjust_i_1_n_0 : STD_LOGIC;
  signal fine_adjust_lane_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal fine_adjust_reg_n_0 : STD_LOGIC;
  signal first_fail_detect : STD_LOGIC;
  signal first_fail_detect_i_1_n_0 : STD_LOGIC;
  signal first_fail_detect_reg_n_0 : STD_LOGIC;
  signal \first_fail_taps[0]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[1]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[2]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[3]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[4]_i_1_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_2_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_3_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_4_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_6_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_7_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_8_n_0\ : STD_LOGIC;
  signal \first_fail_taps[5]_i_9_n_0\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[0]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[1]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[2]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[3]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[4]\ : STD_LOGIC;
  signal \first_fail_taps_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \gen_byte_sel_div2.calib_in_common_i_3_n_0\ : STD_LOGIC;
  signal \gen_byte_sel_div2.ctl_lane_sel[2]_i_2_n_0\ : STD_LOGIC;
  signal inc_cnt : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \inc_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal init_dec_cnt : STD_LOGIC;
  signal init_dec_cnt0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \init_dec_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal init_dec_done_i_1_n_0 : STD_LOGIC;
  signal init_dec_done_i_2_n_0 : STD_LOGIC;
  signal init_dec_done_i_3_n_0 : STD_LOGIC;
  signal init_dec_done_reg_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r1_reg_n_0 : STD_LOGIC;
  signal \^init_dqsfound_done_r2\ : STD_LOGIC;
  signal init_dqsfound_done_r4_reg_srl2_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r5 : STD_LOGIC;
  signal init_dqsfound_done_r_i_1_n_0 : STD_LOGIC;
  signal init_dqsfound_done_r_i_2_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_0_in24_in : STD_LOGIC;
  signal p_0_in29_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal p_1_in30_in : STD_LOGIC;
  signal p_1_in58_in : STD_LOGIC;
  signal p_1_in63_in : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \p_1_in__1\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal p_22_out : STD_LOGIC;
  signal p_2_in79_in : STD_LOGIC;
  signal p_2_in80_in : STD_LOGIC;
  signal p_8_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pi_dqs_found_all_bank : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pi_dqs_found_all_bank_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pi_dqs_found_any_bank : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \pi_dqs_found_any_bank[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_dqs_found_any_bank[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_dqs_found_any_bank_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \^pi_dqs_found_done\ : STD_LOGIC;
  signal pi_dqs_found_lanes_r1 : STD_LOGIC_VECTOR ( 10 downto 0 );
  attribute async_reg : string;
  attribute async_reg of pi_dqs_found_lanes_r1 : signal is "true";
  signal pi_dqs_found_lanes_r2 : STD_LOGIC_VECTOR ( 10 downto 0 );
  attribute async_reg of pi_dqs_found_lanes_r2 : signal is "true";
  signal pi_dqs_found_lanes_r3 : STD_LOGIC_VECTOR ( 10 downto 0 );
  attribute async_reg of pi_dqs_found_lanes_r3 : signal is "true";
  signal \^pi_dqs_found_rank_done\ : STD_LOGIC;
  signal \pi_rst_stg1_cal[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal[2]_i_1_n_0\ : STD_LOGIC;
  signal pi_rst_stg1_cal_r1_reg0 : STD_LOGIC;
  signal pi_rst_stg1_cal_r1_reg019_out : STD_LOGIC;
  signal pi_rst_stg1_cal_r1_reg022_out : STD_LOGIC;
  signal \pi_rst_stg1_cal_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rst_stg1_cal_r_reg_n_0_[0]\ : STD_LOGIC;
  signal rank_done_r1 : STD_LOGIC;
  signal rank_done_r_i_1_n_0 : STD_LOGIC;
  signal rank_done_r_i_2_n_0 : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\ : STD_LOGIC;
  signal \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1_n_0\ : STD_LOGIC;
  signal \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0\ : STD_LOGIC;
  signal \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0\ : STD_LOGIC;
  signal \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rd_byte_data_offset : STD_LOGIC;
  signal \rd_byte_data_offset[0][11]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][11]_i_2_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][11]_i_4_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][13]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][17]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][17]_i_2_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][17]_i_4_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_5_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][5]_i_6_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset[0][7]_i_1_n_0\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][12]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][13]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][14]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][16]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][17]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \rd_byte_data_offset_reg_n_0_[0][5]\ : STD_LOGIC;
  signal rd_data_offset_cal_done : STD_LOGIC;
  signal rd_data_offset_ranks_0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_data_offset_ranks_1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_data_offset_ranks_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rnk_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rst_dqs_find : STD_LOGIC;
  signal rst_dqs_find_i_1_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_3_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_4_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_5_n_0 : STD_LOGIC;
  signal rst_dqs_find_i_6_n_0 : STD_LOGIC;
  signal rst_dqs_find_r1 : STD_LOGIC;
  signal rst_dqs_find_r2 : STD_LOGIC;
  signal rst_dqs_find_reg_n_0 : STD_LOGIC;
  signal rst_stg1_cal : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal stable_pass_cnt : STD_LOGIC;
  signal \stable_pass_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \stable_pass_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \stable_pass_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \NLW_dec_cnt_reg[1]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_dec_cnt_reg[4]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_dec_cnt_reg[4]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_2\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[3]_i_11\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[3]_i_9\ : label is "soft_lutpair30";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[0]\ : label is "FINE_ADJ_IDLE:0000,RST_WAIT:0001,RST_POSTWAIT:0011,RST_POSTWAIT1:0100,FINE_ADJ_INIT:0101,FINE_INC:0110,FINE_INC_WAIT:0111,FINE_INC_PREWAIT:1000,DETECT_PREWAIT:1001,DETECT_DQSFOUND:1010,PRECH_WAIT:1111,FINE_DEC:1011,FINE_DEC_WAIT:1100,FINE_DEC_PREWAIT:1101,FINAL_WAIT:1110,FINE_ADJ_DONE:0010";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_fine_adj_state_r_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[1]\ : label is "FINE_ADJ_IDLE:0000,RST_WAIT:0001,RST_POSTWAIT:0011,RST_POSTWAIT1:0100,FINE_ADJ_INIT:0101,FINE_INC:0110,FINE_INC_WAIT:0111,FINE_INC_PREWAIT:1000,DETECT_PREWAIT:1001,DETECT_DQSFOUND:1010,PRECH_WAIT:1111,FINE_DEC:1011,FINE_DEC_WAIT:1100,FINE_DEC_PREWAIT:1101,FINAL_WAIT:1110,FINE_ADJ_DONE:0010";
  attribute KEEP of \FSM_sequential_fine_adj_state_r_reg[1]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[2]\ : label is "FINE_ADJ_IDLE:0000,RST_WAIT:0001,RST_POSTWAIT:0011,RST_POSTWAIT1:0100,FINE_ADJ_INIT:0101,FINE_INC:0110,FINE_INC_WAIT:0111,FINE_INC_PREWAIT:1000,DETECT_PREWAIT:1001,DETECT_DQSFOUND:1010,PRECH_WAIT:1111,FINE_DEC:1011,FINE_DEC_WAIT:1100,FINE_DEC_PREWAIT:1101,FINAL_WAIT:1110,FINE_ADJ_DONE:0010";
  attribute KEEP of \FSM_sequential_fine_adj_state_r_reg[2]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[3]\ : label is "FINE_ADJ_IDLE:0000,RST_WAIT:0001,RST_POSTWAIT:0011,RST_POSTWAIT1:0100,FINE_ADJ_INIT:0101,FINE_INC:0110,FINE_INC_WAIT:0111,FINE_INC_PREWAIT:1000,DETECT_PREWAIT:1001,DETECT_DQSFOUND:1010,PRECH_WAIT:1111,FINE_DEC:1011,FINE_DEC_WAIT:1100,FINE_DEC_PREWAIT:1101,FINAL_WAIT:1110,FINE_ADJ_DONE:0010";
  attribute KEEP of \FSM_sequential_fine_adj_state_r_reg[3]\ : label is "yes";
  attribute SOFT_HLUTNM of \calib_data_offset_0[0]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \calib_data_offset_0[1]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \calib_data_offset_1[0]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \calib_data_offset_1[1]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \calib_data_offset_2[0]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \calib_data_offset_2[1]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[1]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[4]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset_1[1]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset_1[4]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset_2[1]_i_1\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset_2[4]_i_1\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \ctl_lane_cnt[0]_i_1__0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \ctl_lane_cnt[1]_i_1__0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \dec_cnt[1]_i_3\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_4\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_7\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \dec_cnt[5]_i_8\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \detect_rd_cnt[1]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \detect_rd_cnt[2]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \detect_rd_cnt[3]_i_3\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of dqs_found_done_r_i_4 : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of dqs_found_prech_req_i_6 : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of first_fail_detect_i_1 : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \first_fail_taps[0]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \first_fail_taps[1]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \first_fail_taps[2]_i_1\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \first_fail_taps[3]_i_1\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \first_fail_taps[4]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_3\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_4\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_5\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \first_fail_taps[5]_i_8\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[3]_i_4\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.calib_in_common_i_4\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.ctl_lane_sel[2]_i_3\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \inc_cnt[1]_i_1\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \inc_cnt[2]_i_1\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \inc_cnt[3]_i_1\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \inc_cnt[4]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \init_dec_cnt[1]_i_1\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \init_dec_cnt[2]_i_1\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \init_dec_cnt[3]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \init_dec_cnt[4]_i_1\ : label is "soft_lutpair41";
  attribute srl_name : string;
  attribute srl_name of init_dqsfound_done_r4_reg_srl2 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r4_reg_srl2 ";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_29\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__0\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__1\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__2\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__3\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__4\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__5\ : label is "soft_lutpair29";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r1_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r2_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[10]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[8]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[9]\ : label is std.standard.true;
  attribute KEEP of \pi_dqs_found_lanes_r3_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \pi_rst_stg1_cal[0]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \pi_rst_stg1_cal[2]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \pi_rst_stg1_cal_r[2]_i_1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of rank_done_r_i_1 : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][10]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][13]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][15]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][16]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][1]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][3]_i_1\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][4]_i_1\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][5]_i_5\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][5]_i_6\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][5]_i_7\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][7]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][8]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \rd_byte_data_offset[0][9]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \rnk_cnt_r[0]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \rnk_cnt_r[1]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \stable_pass_cnt[0]_i_1\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \stable_pass_cnt[1]_i_1\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \stable_pass_cnt[3]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \stable_pass_cnt[5]_i_3\ : label is "soft_lutpair35";
begin
  ck_po_stg2_f_en <= \^ck_po_stg2_f_en\;
  \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) <= \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0);
  \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) <= \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0);
  \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) <= \^cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0);
  ctl_lane_sel <= \^ctl_lane_sel\;
  dqs_found_prech_req <= \^dqs_found_prech_req\;
  init_dqsfound_done_r2 <= \^init_dqsfound_done_r2\;
  pi_dqs_found_done <= \^pi_dqs_found_done\;
  pi_dqs_found_rank_done <= \^pi_dqs_found_rank_done\;
  \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0) <= \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0);
  \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0) <= \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0);
  \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0) <= \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0);
\FSM_sequential_fine_adj_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3B0FFFFF3B00000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(1),
      I5 => \FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0\,
      O => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => fine_adjust_lane_cnt(1),
      I1 => fine_adjust_lane_cnt(2),
      I2 => fine_adjust_lane_cnt(0),
      O => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAFFFFFFFF"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r1,
      I2 => fine_adjust_lane_cnt(0),
      I3 => fine_adjust_lane_cnt(2),
      I4 => fine_adjust_lane_cnt(1),
      I5 => fine_adj_state_r(3),
      O => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCC7477"
    )
        port map (
      I0 => fine_adj_state_r185_out,
      I1 => fine_adj_state_r(3),
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I3 => final_dec_done_reg_n_0,
      I4 => fine_adj_state_r(2),
      O => \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FBFFFFF8FB0000"
    )
        port map (
      I0 => fine_adj_state_r185_out,
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I4 => fine_adj_state_r(0),
      I5 => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\,
      O => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FE0E"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => p_1_in30_in,
      I2 => fine_adj_state_r(3),
      I3 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I4 => fine_adj_state_r(0),
      O => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555575500000000"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adjust_lane_cnt(0),
      I2 => fine_adjust_lane_cnt(2),
      I3 => fine_adjust_lane_cnt(1),
      I4 => fine_adj_state_r1,
      I5 => fine_adj_state_r(3),
      O => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033CCBB33FFFC00"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\,
      I1 => fine_adj_state_r(1),
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I3 => fine_adj_state_r(0),
      I4 => fine_adj_state_r(2),
      I5 => fine_adj_state_r(3),
      O => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E0FFFF00E00000"
    )
        port map (
      I0 => fine_adj_state_r3,
      I1 => first_fail_detect_reg_n_0,
      I2 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\,
      I3 => fine_adj_state_r144_out,
      I4 => fine_adj_state_r147_out,
      I5 => fine_adj_state_r18_out,
      O => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\
    );
\FSM_sequential_fine_adj_state_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80AA80AA8CAA80AA"
    )
        port map (
      I0 => fine_adj_state_r112_out,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_9_n_0\,
      I3 => first_fail_detect_reg_n_0,
      I4 => fine_adj_state_r19_out,
      I5 => \first_fail_taps[5]_i_8_n_0\,
      O => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE0EFE0EFE0EFFFF"
    )
        port map (
      I0 => fine_adj_state_r19_out,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_11_n_0\,
      I2 => fine_adj_state_r114_out,
      I3 => fine_adj_state_r112_out,
      I4 => first_fail_detect_reg_n_0,
      I5 => fine_adj_state_r3,
      O => \FSM_sequential_fine_adj_state_r[3]_i_10_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \first_fail_taps[5]_i_7_n_0\,
      I1 => \first_fail_taps[5]_i_8_n_0\,
      I2 => \first_fail_taps[5]_i_9_n_0\,
      O => \FSM_sequential_fine_adj_state_r[3]_i_11_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33BBFF88CC003000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\,
      I1 => fine_adj_state_r(1),
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I3 => fine_adj_state_r(0),
      I4 => fine_adj_state_r(2),
      I5 => fine_adj_state_r(3),
      O => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFBFFF8"
    )
        port map (
      I0 => fine_adj_state_r034_out,
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(2),
      I4 => init_dqsfound_done_r5,
      O => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFFBBFFFCFFFCCC"
    )
        port map (
      I0 => prech_done,
      I1 => fine_adj_state_r(0),
      I2 => detect_pi_found_dqs,
      I3 => fine_adj_state_r(3),
      I4 => p_1_in30_in,
      I5 => fine_adj_state_r(2),
      O => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFDFD0D"
    )
        port map (
      I0 => fine_adj_state_r3,
      I1 => fine_adj_state_r18_out,
      I2 => fine_adj_state_r147_out,
      I3 => fine_adj_state_r144_out,
      I4 => \FSM_sequential_fine_adj_state_r[3]_i_10_n_0\,
      I5 => fine_adj_state_r(2),
      O => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \init_dec_cnt_reg__0\(4),
      I1 => \init_dec_cnt_reg__0\(2),
      I2 => \init_dec_cnt_reg__0\(0),
      I3 => \init_dec_cnt_reg__0\(1),
      I4 => \init_dec_cnt_reg__0\(3),
      I5 => \init_dec_cnt_reg__0\(5),
      O => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\
    );
\FSM_sequential_fine_adj_state_r[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => pi_dqs_found_any_bank(0),
      I1 => rst_dqs_find_r2,
      I2 => pi_dqs_found_all_bank(1),
      I3 => pi_dqs_found_any_bank(2),
      O => fine_adj_state_r034_out
    );
\FSM_sequential_fine_adj_state_r[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1110"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_8_n_0\,
      I3 => \inc_cnt_reg_n_0_[5]\,
      O => fine_adj_state_r144_out
    );
\FSM_sequential_fine_adj_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r_reg[3]_i_2_n_0\,
      D => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\,
      Q => fine_adj_state_r(0),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\FSM_sequential_fine_adj_state_r_reg[0]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\,
      O => \FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0\,
      S => fine_adj_state_r(0)
    );
\FSM_sequential_fine_adj_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r_reg[3]_i_2_n_0\,
      D => \FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0\,
      Q => fine_adj_state_r(1),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\FSM_sequential_fine_adj_state_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\,
      O => \FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0\,
      S => fine_adj_state_r(1)
    );
\FSM_sequential_fine_adj_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r_reg[3]_i_2_n_0\,
      D => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\,
      Q => fine_adj_state_r(2),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\FSM_sequential_fine_adj_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_fine_adj_state_r_reg[3]_i_2_n_0\,
      D => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\,
      Q => fine_adj_state_r(3),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\FSM_sequential_fine_adj_state_r_reg[3]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\,
      O => \FSM_sequential_fine_adj_state_r_reg[3]_i_2_n_0\,
      S => fine_adj_state_r(1)
    );
\calib_data_offset_0[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(0),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      O => \calib_data_offset_0_reg[0]\
    );
\calib_data_offset_0[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(1),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => \calib_data_offset_0_reg[1]\
    );
\calib_data_offset_0[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(2),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      O => \calib_data_offset_0_reg[2]\
    );
\calib_data_offset_0[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(4),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      O => \calib_data_offset_0_reg[4]\
    );
\calib_data_offset_0[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_0(5),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      O => \calib_data_offset_0_reg[5]\
    );
\calib_data_offset_1[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(0),
      I2 => \^init_dqsfound_done_r2\,
      I3 => p_0_in(0),
      O => \calib_data_offset_1_reg[0]\
    );
\calib_data_offset_1[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(1),
      I2 => \^init_dqsfound_done_r2\,
      I3 => p_0_in(1),
      O => \calib_data_offset_1_reg[1]\
    );
\calib_data_offset_1[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(2),
      I2 => \^init_dqsfound_done_r2\,
      I3 => p_0_in(2),
      O => \calib_data_offset_1_reg[2]\
    );
\calib_data_offset_1[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(4),
      I2 => \^init_dqsfound_done_r2\,
      I3 => p_0_in(4),
      O => \calib_data_offset_1_reg[4]\
    );
\calib_data_offset_1[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_1(5),
      I2 => \^init_dqsfound_done_r2\,
      I3 => p_0_in(5),
      O => \calib_data_offset_1_reg[5]\
    );
\calib_data_offset_2[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(0),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      O => \calib_data_offset_2_reg[0]\
    );
\calib_data_offset_2[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(1),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => \calib_data_offset_2_reg[1]\
    );
\calib_data_offset_2[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(2),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      O => \calib_data_offset_2_reg[2]\
    );
\calib_data_offset_2[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(4),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      O => \calib_data_offset_2_reg[4]\
    );
\calib_data_offset_2[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDC8"
    )
        port map (
      I0 => pi_dqs_found_done_r1,
      I1 => rd_data_offset_ranks_2(5),
      I2 => \^init_dqsfound_done_r2\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      O => \calib_data_offset_2_reg[5]\
    );
\calib_zero_inputs[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"57550000FFFFFFFF"
    )
        port map (
      I0 => \calib_zero_inputs[2]_i_2_n_0\,
      I1 => \calib_zero_inputs[2]_i_3_n_0\,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(3),
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(2),
      I4 => cmd_delay_start0,
      I5 => pi_f_inc_reg,
      O => D(0)
    );
\calib_zero_inputs[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44444440FFFFFFFF"
    )
        port map (
      I0 => \calib_zero_inputs[2]_i_3_n_0\,
      I1 => cmd_delay_start0,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]\,
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(1),
      I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(0),
      I5 => pi_f_inc_reg,
      O => D(1)
    );
\calib_zero_inputs[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"75000000FFFFFFFF"
    )
        port map (
      I0 => \calib_zero_inputs[2]_i_2_n_0\,
      I1 => \calib_zero_inputs[2]_i_3_n_0\,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I3 => pi_fine_dly_dec_done,
      I4 => dqs_po_dec_done,
      I5 => pi_f_inc_reg,
      O => D(2)
    );
\calib_zero_inputs[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFD0"
    )
        port map (
      I0 => rd_data_offset_cal_done,
      I1 => fine_adjust_done_r_reg_n_0,
      I2 => ck_addr_cmd_delay_done,
      I3 => rst_stg1_cal(2),
      I4 => rst_stg1_cal(0),
      I5 => rst_stg1_cal(1),
      O => \calib_zero_inputs[2]_i_2_n_0\
    );
\calib_zero_inputs[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF5D"
    )
        port map (
      I0 => ck_addr_cmd_delay_done,
      I1 => rd_data_offset_cal_done,
      I2 => fine_adjust_done_r_reg_n_0,
      I3 => calib_in_common,
      I4 => tempmon_pi_f_inc,
      I5 => tempmon_pi_f_dec,
      O => \calib_zero_inputs[2]_i_3_n_0\
    );
ck_po_stg2_f_en_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFBF0820"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(0),
      I4 => \^ck_po_stg2_f_en\,
      O => ck_po_stg2_f_en_i_1_n_0
    );
ck_po_stg2_f_en_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ck_po_stg2_f_en_i_1_n_0,
      Q => \^ck_po_stg2_f_en\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
ck_po_stg2_f_indec_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D7BF0020"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(0),
      I4 => ck_po_stg2_f_indec,
      O => ck_po_stg2_f_indec_i_1_n_0
    );
ck_po_stg2_f_indec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ck_po_stg2_f_indec_i_1_n_0,
      Q => ck_po_stg2_f_indec,
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
\cmd_pipe_plus.mc_data_offset[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(0),
      O => \cmd_pipe_plus.mc_data_offset_reg[0]\
    );
\cmd_pipe_plus.mc_data_offset[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(0),
      I1 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(1),
      O => \cmd_pipe_plus.mc_data_offset_reg[1]\
    );
\cmd_pipe_plus.mc_data_offset[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA28888888"
    )
        port map (
      I0 => sent_col,
      I1 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(3),
      I2 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(2),
      I3 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(0),
      I4 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(1),
      I5 => \grant_r_reg[3]\,
      O => \cmd_pipe_plus.mc_data_offset_reg[3]\(0)
    );
\cmd_pipe_plus.mc_data_offset[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(4),
      I1 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(1),
      I2 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(0),
      I3 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(2),
      I4 => \^cmd_pipe_plus.mc_data_offset_reg[5]\(3),
      O => \cmd_pipe_plus.mc_data_offset_reg[4]\
    );
\cmd_pipe_plus.mc_data_offset_1[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(0),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[0]\
    );
\cmd_pipe_plus.mc_data_offset_1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(0),
      I1 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(1),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[1]\
    );
\cmd_pipe_plus.mc_data_offset_1[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA28888888"
    )
        port map (
      I0 => sent_col,
      I1 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(3),
      I2 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(2),
      I3 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(0),
      I4 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(1),
      I5 => \grant_r_reg[3]\,
      O => \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0)
    );
\cmd_pipe_plus.mc_data_offset_1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(4),
      I1 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(1),
      I2 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(0),
      I3 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(2),
      I4 => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(3),
      O => \cmd_pipe_plus.mc_data_offset_1_reg[4]\
    );
\cmd_pipe_plus.mc_data_offset_2[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(0),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[0]\
    );
\cmd_pipe_plus.mc_data_offset_2[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(0),
      I1 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(1),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[1]\
    );
\cmd_pipe_plus.mc_data_offset_2[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA28888888"
    )
        port map (
      I0 => sent_col,
      I1 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(3),
      I2 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(2),
      I3 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(0),
      I4 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(1),
      I5 => \grant_r_reg[3]\,
      O => \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0)
    );
\cmd_pipe_plus.mc_data_offset_2[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(4),
      I1 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(1),
      I2 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(0),
      I3 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(2),
      I4 => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(3),
      O => \cmd_pipe_plus.mc_data_offset_2_reg[4]\
    );
\ctl_lane_cnt[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0FD0"
    )
        port map (
      I0 => fine_adjust_lane_cnt(1),
      I1 => fine_adjust_lane_cnt(2),
      I2 => ctl_lane_cnt_0,
      I3 => fine_adjust_lane_cnt(0),
      O => \ctl_lane_cnt[0]_i_1__0_n_0\
    );
\ctl_lane_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2FC0"
    )
        port map (
      I0 => fine_adjust_lane_cnt(2),
      I1 => fine_adjust_lane_cnt(0),
      I2 => ctl_lane_cnt_0,
      I3 => fine_adjust_lane_cnt(1),
      O => \ctl_lane_cnt[1]_i_1__0_n_0\
    );
\ctl_lane_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => fine_adjust_lane_cnt(1),
      I1 => fine_adjust_lane_cnt(0),
      I2 => ctl_lane_cnt_0,
      I3 => fine_adjust_lane_cnt(2),
      O => \ctl_lane_cnt[2]_i_1__0_n_0\
    );
\ctl_lane_cnt[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2040"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(0),
      O => ctl_lane_cnt_0
    );
\ctl_lane_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ctl_lane_cnt[0]_i_1__0_n_0\,
      Q => fine_adjust_lane_cnt(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\ctl_lane_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ctl_lane_cnt[1]_i_1__0_n_0\,
      Q => fine_adjust_lane_cnt(1),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\ctl_lane_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ctl_lane_cnt[2]_i_1__0_n_0\,
      Q => fine_adjust_lane_cnt(2),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\dec_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"74777474"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[0]\,
      I1 => fine_adj_state_r(0),
      I2 => \dec_cnt[0]_i_2_n_0\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt[1]_i_3_n_0\,
      O => dec_cnt(0)
    );
\dec_cnt[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[1]\,
      I1 => \dec_cnt[4]_i_7_n_0\,
      I2 => \dec_cnt_reg[1]_i_5_n_6\,
      I3 => \dec_cnt[4]_i_5_n_0\,
      O => \dec_cnt[0]_i_2_n_0\
    );
\dec_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB8BB88888"
    )
        port map (
      I0 => \dec_cnt[1]_i_2_n_0\,
      I1 => fine_adj_state_r(0),
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt[1]_i_3_n_0\,
      I5 => \dec_cnt[1]_i_4_n_0\,
      O => dec_cnt(1)
    );
\dec_cnt[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[1]\,
      I1 => \dec_cnt_reg_n_0_[0]\,
      O => \dec_cnt[1]_i_2_n_0\
    );
\dec_cnt[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA0000"
    )
        port map (
      I0 => fine_adj_state_r144_out,
      I1 => pi_dqs_found_all_bank(2),
      I2 => pi_dqs_found_all_bank(1),
      I3 => pi_dqs_found_all_bank(0),
      I4 => detect_pi_found_dqs,
      O => \dec_cnt[1]_i_3_n_0\
    );
\dec_cnt[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[2]\,
      I1 => \dec_cnt[4]_i_7_n_0\,
      I2 => \dec_cnt_reg[1]_i_5_n_5\,
      I3 => \dec_cnt[4]_i_5_n_0\,
      O => \dec_cnt[1]_i_4_n_0\
    );
\dec_cnt[1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \first_fail_taps_reg_n_0_[3]\,
      O => \dec_cnt[1]_i_6_n_0\
    );
\dec_cnt[1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \first_fail_taps_reg_n_0_[2]\,
      O => \dec_cnt[1]_i_7_n_0\
    );
\dec_cnt[1]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \first_fail_taps_reg_n_0_[1]\,
      O => \dec_cnt[1]_i_8_n_0\
    );
\dec_cnt[1]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \first_fail_taps_reg_n_0_[0]\,
      O => \dec_cnt[1]_i_9_n_0\
    );
\dec_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[2]\,
      I1 => \dec_cnt_reg_n_0_[0]\,
      I2 => \dec_cnt_reg_n_0_[1]\,
      I3 => fine_adj_state_r(0),
      I4 => \dec_cnt[2]_i_2_n_0\,
      O => dec_cnt(2)
    );
\dec_cnt[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEEAEAEA"
    )
        port map (
      I0 => \dec_cnt[2]_i_3_n_0\,
      I1 => \dec_cnt[1]_i_3_n_0\,
      I2 => \inc_cnt_reg_n_0_[3]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      O => \dec_cnt[2]_i_2_n_0\
    );
\dec_cnt[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[3]\,
      I1 => \dec_cnt[4]_i_7_n_0\,
      I2 => \dec_cnt_reg[1]_i_5_n_4\,
      I3 => \dec_cnt[4]_i_5_n_0\,
      O => \dec_cnt[2]_i_3_n_0\
    );
\dec_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA9FFFFAAA90000"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[3]\,
      I1 => \dec_cnt_reg_n_0_[1]\,
      I2 => \dec_cnt_reg_n_0_[0]\,
      I3 => \dec_cnt_reg_n_0_[2]\,
      I4 => fine_adj_state_r(0),
      I5 => \dec_cnt[3]_i_2_n_0\,
      O => dec_cnt(3)
    );
\dec_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF6AAA0000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      I4 => \dec_cnt[1]_i_3_n_0\,
      I5 => \dec_cnt[3]_i_3_n_0\,
      O => \dec_cnt[3]_i_2_n_0\
    );
\dec_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[4]\,
      I1 => \dec_cnt[4]_i_7_n_0\,
      I2 => \dec_cnt_reg[4]_i_6_n_7\,
      I3 => \dec_cnt[4]_i_5_n_0\,
      O => \dec_cnt[3]_i_3_n_0\
    );
\dec_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \dec_cnt[4]_i_4_n_0\,
      I1 => \dec_cnt[4]_i_5_n_0\,
      I2 => \dec_cnt_reg[4]_i_6_n_6\,
      I3 => \dec_cnt[4]_i_7_n_0\,
      I4 => \first_fail_taps_reg_n_0_[5]\,
      O => \dec_cnt[4]_i_2_n_0\
    );
\dec_cnt[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[4]\,
      I1 => \dec_cnt_reg_n_0_[2]\,
      I2 => \dec_cnt_reg_n_0_[0]\,
      I3 => \dec_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt_reg_n_0_[3]\,
      O => \dec_cnt[4]_i_3_n_0\
    );
\dec_cnt[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \dec_cnt[1]_i_3_n_0\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[3]\,
      I5 => \inc_cnt_reg_n_0_[5]\,
      O => \dec_cnt[4]_i_4_n_0\
    );
\dec_cnt[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EEF00000EEFFFFF"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_8_n_0\,
      I3 => \inc_cnt_reg_n_0_[5]\,
      I4 => fine_adj_state_r147_out,
      I5 => \dec_cnt[5]_i_9_n_0\,
      O => \dec_cnt[4]_i_5_n_0\
    );
\dec_cnt[4]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \first_fail_taps[5]_i_7_n_0\,
      I1 => first_fail_detect_reg_n_0,
      I2 => \inc_cnt_reg_n_0_[5]\,
      I3 => \first_fail_taps[5]_i_8_n_0\,
      I4 => fine_adj_state_r147_out,
      O => \dec_cnt[4]_i_7_n_0\
    );
\dec_cnt[4]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[5]\,
      O => \dec_cnt[4]_i_8_n_0\
    );
\dec_cnt[4]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \first_fail_taps_reg_n_0_[4]\,
      O => \dec_cnt[4]_i_9_n_0\
    );
\dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C08000800000000"
    )
        port map (
      I0 => \dec_cnt[5]_i_3_n_0\,
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(0),
      I4 => \dec_cnt[5]_i_4_n_0\,
      I5 => fine_adj_state_r(1),
      O => \dec_cnt[5]_i_1_n_0\
    );
\dec_cnt[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11000F00"
    )
        port map (
      I0 => fine_adj_state_r18_out,
      I1 => fine_adj_state_r3,
      I2 => \dec_cnt[5]_i_7_n_0\,
      I3 => detect_pi_found_dqs,
      I4 => p_1_in30_in,
      O => \dec_cnt[5]_i_3_n_0\
    );
\dec_cnt[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I1 => fine_adjust_lane_cnt(1),
      I2 => fine_adjust_lane_cnt(2),
      I3 => fine_adjust_lane_cnt(0),
      I4 => init_dec_done_i_2_n_0,
      O => \dec_cnt[5]_i_4_n_0\
    );
\dec_cnt[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF6060FF60"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \dec_cnt[5]_i_8_n_0\,
      I2 => \dec_cnt[1]_i_3_n_0\,
      I3 => \dec_cnt[5]_i_9_n_0\,
      I4 => fine_adj_state_r147_out,
      I5 => \first_fail_taps[5]_i_3_n_0\,
      O => \dec_cnt[5]_i_5_n_0\
    );
\dec_cnt[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[5]\,
      I1 => \dec_cnt_reg_n_0_[3]\,
      I2 => \dec_cnt_reg_n_0_[1]\,
      I3 => \dec_cnt_reg_n_0_[0]\,
      I4 => \dec_cnt_reg_n_0_[2]\,
      I5 => \dec_cnt_reg_n_0_[4]\,
      O => \dec_cnt[5]_i_6_n_0\
    );
\dec_cnt[5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AEEF"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_8_n_0\,
      I3 => \inc_cnt_reg_n_0_[5]\,
      I4 => \first_fail_taps[5]_i_4_n_0\,
      O => \dec_cnt[5]_i_7_n_0\
    );
\dec_cnt[5]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[1]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[4]\,
      O => \dec_cnt[5]_i_8_n_0\
    );
\dec_cnt[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFF0FFF0FEF0F"
    )
        port map (
      I0 => \first_fail_taps_reg_n_0_[3]\,
      I1 => \first_fail_taps_reg_n_0_[2]\,
      I2 => first_fail_detect_reg_n_0,
      I3 => \first_fail_taps_reg_n_0_[5]\,
      I4 => \first_fail_taps_reg_n_0_[1]\,
      I5 => \first_fail_taps_reg_n_0_[4]\,
      O => \dec_cnt[5]_i_9_n_0\
    );
\dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(0),
      Q => \dec_cnt_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(1),
      Q => \dec_cnt_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\dec_cnt_reg[1]_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \dec_cnt_reg[1]_i_5_n_0\,
      CO(2) => \dec_cnt_reg[1]_i_5_n_1\,
      CO(1) => \dec_cnt_reg[1]_i_5_n_2\,
      CO(0) => \dec_cnt_reg[1]_i_5_n_3\,
      CYINIT => '1',
      DI(3) => \inc_cnt_reg_n_0_[3]\,
      DI(2) => \inc_cnt_reg_n_0_[2]\,
      DI(1) => \inc_cnt_reg_n_0_[1]\,
      DI(0) => \inc_cnt_reg_n_0_[0]\,
      O(3) => \dec_cnt_reg[1]_i_5_n_4\,
      O(2) => \dec_cnt_reg[1]_i_5_n_5\,
      O(1) => \dec_cnt_reg[1]_i_5_n_6\,
      O(0) => \NLW_dec_cnt_reg[1]_i_5_O_UNCONNECTED\(0),
      S(3) => \dec_cnt[1]_i_6_n_0\,
      S(2) => \dec_cnt[1]_i_7_n_0\,
      S(1) => \dec_cnt[1]_i_8_n_0\,
      S(0) => \dec_cnt[1]_i_9_n_0\
    );
\dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(2),
      Q => \dec_cnt_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(3),
      Q => \dec_cnt_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(4),
      Q => \dec_cnt_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\dec_cnt_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \dec_cnt[4]_i_2_n_0\,
      I1 => \dec_cnt[4]_i_3_n_0\,
      O => dec_cnt(4),
      S => fine_adj_state_r(0)
    );
\dec_cnt_reg[4]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \dec_cnt_reg[1]_i_5_n_0\,
      CO(3 downto 1) => \NLW_dec_cnt_reg[4]_i_6_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \dec_cnt_reg[4]_i_6_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \inc_cnt_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_dec_cnt_reg[4]_i_6_O_UNCONNECTED\(3 downto 2),
      O(1) => \dec_cnt_reg[4]_i_6_n_6\,
      O(0) => \dec_cnt_reg[4]_i_6_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \dec_cnt[4]_i_8_n_0\,
      S(0) => \dec_cnt[4]_i_9_n_0\
    );
\dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dec_cnt[5]_i_1_n_0\,
      D => dec_cnt(5),
      Q => \dec_cnt_reg_n_0_[5]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\dec_cnt_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \dec_cnt[5]_i_5_n_0\,
      I1 => \dec_cnt[5]_i_6_n_0\,
      O => dec_cnt(5),
      S => fine_adj_state_r(0)
    );
\detect_rd_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \detect_rd_cnt_reg__0\(0),
      O => \detect_rd_cnt0__0\(0)
    );
\detect_rd_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \detect_rd_cnt_reg__0\(1),
      I1 => \detect_rd_cnt_reg__0\(0),
      O => \detect_rd_cnt0__0\(1)
    );
\detect_rd_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C9"
    )
        port map (
      I0 => \detect_rd_cnt_reg__0\(0),
      I1 => \detect_rd_cnt_reg__0\(2),
      I2 => \detect_rd_cnt_reg__0\(1),
      O => \detect_rd_cnt0__0\(2)
    );
\detect_rd_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0001"
    )
        port map (
      I0 => \detect_rd_cnt_reg__0\(0),
      I1 => \detect_rd_cnt_reg__0\(1),
      I2 => \detect_rd_cnt_reg__0\(2),
      I3 => \detect_rd_cnt_reg__0\(3),
      I4 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \detect_rd_cnt_reg__0\(1),
      I1 => \detect_rd_cnt_reg__0\(2),
      I2 => \detect_rd_cnt_reg__0\(3),
      I3 => \detect_rd_cnt_reg__0\(0),
      I4 => detect_pi_found_dqs,
      O => detect_rd_cnt0
    );
\detect_rd_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \detect_rd_cnt_reg__0\(0),
      I1 => \detect_rd_cnt_reg__0\(1),
      I2 => \detect_rd_cnt_reg__0\(2),
      I3 => \detect_rd_cnt_reg__0\(3),
      O => \detect_rd_cnt0__0\(3)
    );
\detect_rd_cnt_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(0),
      Q => \detect_rd_cnt_reg__0\(0),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(1),
      Q => \detect_rd_cnt_reg__0\(1),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(2),
      Q => \detect_rd_cnt_reg__0\(2),
      S => \detect_rd_cnt[3]_i_1_n_0\
    );
\detect_rd_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => detect_rd_cnt0,
      D => \detect_rd_cnt0__0\(3),
      Q => \detect_rd_cnt_reg__0\(3),
      R => \detect_rd_cnt[3]_i_1_n_0\
    );
dqs_found_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040000000000000"
    )
        port map (
      I0 => dqs_found_done_r_i_2_n_0,
      I1 => fine_adj_state_r(1),
      I2 => dqs_found_done_r_i_3_n_0,
      I3 => fine_adj_state_r(0),
      I4 => init_dqsfound_done_r1_reg_n_0,
      I5 => p_1_in30_in,
      O => dqs_found_done_r0
    );
dqs_found_done_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[1]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      O => dqs_found_done_r_i_2_n_0
    );
dqs_found_done_r_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fine_adj_state_r(2),
      I1 => fine_adj_state_r(3),
      O => dqs_found_done_r_i_3_n_0
    );
dqs_found_done_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pi_dqs_found_all_bank(2),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(0),
      O => p_1_in30_in
    );
dqs_found_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_found_done_r0,
      Q => \^pi_dqs_found_done\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
dqs_found_prech_req_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AEFFFF00AE0000"
    )
        port map (
      I0 => dqs_found_prech_req_i_2_n_0,
      I1 => fine_adj_state_r18_out,
      I2 => fine_adj_state_r147_out,
      I3 => fine_adj_state_r(2),
      I4 => dqs_found_prech_req_i_4_n_0,
      I5 => \^dqs_found_prech_req\,
      O => dqs_found_prech_req_i_1_n_0
    );
dqs_found_prech_req_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => fine_adj_state_r112_out,
      I1 => fine_adj_state_r114_out,
      I2 => fine_adj_state_r19_out,
      O => dqs_found_prech_req_i_2_n_0
    );
dqs_found_prech_req_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000600060000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \inc_cnt_reg_n_0_[2]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[0]\,
      I4 => \inc_cnt_reg_n_0_[5]\,
      I5 => \inc_cnt_reg_n_0_[3]\,
      O => fine_adj_state_r18_out
    );
dqs_found_prech_req_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C008000800000000"
    )
        port map (
      I0 => dqs_found_prech_req_i_8_n_0,
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(0),
      I4 => prech_done,
      I5 => fine_adj_state_r(1),
      O => dqs_found_prech_req_i_4_n_0
    );
dqs_found_prech_req_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200020000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[5]\,
      I2 => \inc_cnt_reg_n_0_[0]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[2]\,
      I5 => \inc_cnt_reg_n_0_[4]\,
      O => fine_adj_state_r112_out
    );
dqs_found_prech_req_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \first_fail_taps[5]_i_7_n_0\,
      I1 => \first_fail_taps[5]_i_9_n_0\,
      I2 => first_fail_detect_reg_n_0,
      O => fine_adj_state_r114_out
    );
dqs_found_prech_req_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400000000040400"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[5]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      I4 => \inc_cnt_reg_n_0_[4]\,
      I5 => \inc_cnt_reg_n_0_[3]\,
      O => fine_adj_state_r19_out
    );
dqs_found_prech_req_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCA80800000000"
    )
        port map (
      I0 => \dec_cnt[5]_i_7_n_0\,
      I1 => fine_adj_state_r19_out,
      I2 => fine_adj_state_r114_out,
      I3 => fine_adj_state_r112_out,
      I4 => p_1_in30_in,
      I5 => detect_pi_found_dqs,
      O => dqs_found_prech_req_i_8_n_0
    );
dqs_found_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_found_prech_req_i_1_n_0,
      Q => \^dqs_found_prech_req\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
dqs_found_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_start_reg,
      Q => dqs_found_start_r,
      R => '0'
    );
\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hri_0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_0\
    );
\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hri_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_1\
    );
\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hri_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_2\
    );
final_dec_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF04000000"
    )
        port map (
      I0 => fine_adj_state_r(1),
      I1 => init_dec_done_i_3_n_0,
      I2 => fine_adj_state_r1,
      I3 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      I4 => init_dec_done_reg_n_0,
      I5 => final_dec_done_reg_n_0,
      O => final_dec_done_i_1_n_0
    );
final_dec_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => init_dec_done_i_2_n_0,
      I1 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      O => fine_adj_state_r1
    );
final_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => final_dec_done_i_1_n_0,
      Q => final_dec_done_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
fine_adjust_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(2),
      I2 => p_1_in30_in,
      I3 => fine_adj_state_r(3),
      I4 => fine_adj_state_r(1),
      I5 => fine_adjust_done_r_reg_n_0,
      O => fine_adjust_done_r_i_1_n_0
    );
fine_adjust_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_adjust_done_r_i_1_n_0,
      Q => fine_adjust_done_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
fine_adjust_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000100"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => init_dqsfound_done_r5,
      I4 => fine_adj_state_r(1),
      I5 => fine_adjust_reg_n_0,
      O => fine_adjust_i_1_n_0
    );
fine_adjust_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_adjust_i_1_n_0,
      Q => fine_adjust_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
first_fail_detect_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"45FF"
    )
        port map (
      I0 => fine_adj_state_r3,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => first_fail_detect_reg_n_0,
      I3 => \first_fail_taps[5]_i_4_n_0\,
      O => first_fail_detect_i_1_n_0
    );
first_fail_detect_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      I4 => \inc_cnt_reg_n_0_[4]\,
      I5 => \inc_cnt_reg_n_0_[0]\,
      O => fine_adj_state_r3
    );
first_fail_detect_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => first_fail_detect_i_1_n_0,
      Q => first_fail_detect_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__1\(0)
    );
\first_fail_taps[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_4_n_0\,
      O => \first_fail_taps[0]_i_1_n_0\
    );
\first_fail_taps[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_4_n_0\,
      O => \first_fail_taps[1]_i_1_n_0\
    );
\first_fail_taps[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_4_n_0\,
      O => \first_fail_taps[2]_i_1_n_0\
    );
\first_fail_taps[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_4_n_0\,
      O => \first_fail_taps[3]_i_1_n_0\
    );
\first_fail_taps[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[4]\,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_4_n_0\,
      O => \first_fail_taps[4]_i_1_n_0\
    );
\first_fail_taps[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000BA0000000000"
    )
        port map (
      I0 => \first_fail_taps[5]_i_3_n_0\,
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => fine_adj_state_r147_out,
      I3 => \first_fail_taps[5]_i_6_n_0\,
      I4 => fine_adj_state_r(0),
      I5 => fine_adj_state_r(1),
      O => first_fail_detect
    );
\first_fail_taps[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => \first_fail_taps[5]_i_4_n_0\,
      O => \first_fail_taps[5]_i_2_n_0\
    );
\first_fail_taps[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D00"
    )
        port map (
      I0 => first_fail_detect_reg_n_0,
      I1 => \first_fail_taps[5]_i_7_n_0\,
      I2 => fine_adj_state_r3,
      I3 => fine_adj_state_r147_out,
      O => \first_fail_taps[5]_i_3_n_0\
    );
\first_fail_taps[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08CC"
    )
        port map (
      I0 => \first_fail_taps[5]_i_8_n_0\,
      I1 => first_fail_detect_reg_n_0,
      I2 => \first_fail_taps[5]_i_9_n_0\,
      I3 => \first_fail_taps[5]_i_7_n_0\,
      O => \first_fail_taps[5]_i_4_n_0\
    );
\first_fail_taps[5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAA"
    )
        port map (
      I0 => detect_pi_found_dqs,
      I1 => pi_dqs_found_all_bank(0),
      I2 => pi_dqs_found_all_bank(1),
      I3 => pi_dqs_found_all_bank(2),
      O => fine_adj_state_r147_out
    );
\first_fail_taps[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => fine_adj_state_r(2),
      O => \first_fail_taps[5]_i_6_n_0\
    );
\first_fail_taps[5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"070F0F0F"
    )
        port map (
      I0 => \stable_pass_cnt_reg__0\(2),
      I1 => \stable_pass_cnt_reg__0\(1),
      I2 => \stable_pass_cnt_reg__0\(5),
      I3 => \stable_pass_cnt_reg__0\(4),
      I4 => \stable_pass_cnt_reg__0\(3),
      O => \first_fail_taps[5]_i_7_n_0\
    );
\first_fail_taps[5]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[3]\,
      O => \first_fail_taps[5]_i_8_n_0\
    );
\first_fail_taps[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000001FFFFFFFF"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[3]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[0]\,
      I5 => \inc_cnt_reg_n_0_[5]\,
      O => \first_fail_taps[5]_i_9_n_0\
    );
\first_fail_taps_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[0]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\first_fail_taps_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[1]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\first_fail_taps_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[2]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\first_fail_taps_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[3]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\first_fail_taps_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[4]_i_1_n_0\,
      Q => \first_fail_taps_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\first_fail_taps_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => first_fail_detect,
      D => \first_fail_taps[5]_i_2_n_0\,
      Q => \first_fail_taps_reg_n_0_[5]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8AAAFFFF"
    )
        port map (
      I0 => ck_addr_cmd_delay_done,
      I1 => \gen_byte_sel_div2.byte_sel_cnt[3]_i_4_n_0\,
      I2 => pi_calib_done,
      I3 => \^pi_dqs_found_done\,
      I4 => cmd_delay_start0,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => SR(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rd_data_offset_cal_done,
      I1 => fine_adjust_done_r_reg_n_0,
      O => \gen_byte_sel_div2.byte_sel_cnt[3]_i_4_n_0\
    );
\gen_byte_sel_div2.calib_in_common_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80FFFFFF80FF0000"
    )
        port map (
      I0 => ck_addr_cmd_delay_done,
      I1 => \calib_zero_inputs[2]_i_2_n_0\,
      I2 => rdlvl_stg1_done_reg_0,
      I3 => cmd_delay_start0,
      I4 => \gen_byte_sel_div2.calib_in_common_i_3_n_0\,
      I5 => calib_in_common,
      O => \gen_byte_sel_div2.calib_in_common_reg\
    );
\gen_byte_sel_div2.calib_in_common_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBFFFFFFFFFFF"
    )
        port map (
      I0 => pi_f_dec_reg,
      I1 => pi_calib_done,
      I2 => \^pi_dqs_found_done\,
      I3 => cmd_delay_start0,
      I4 => \gen_byte_sel_div2.byte_sel_cnt[3]_i_4_n_0\,
      I5 => ck_addr_cmd_delay_done,
      O => \gen_byte_sel_div2.calib_in_common_i_3_n_0\
    );
\gen_byte_sel_div2.calib_in_common_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4FFF"
    )
        port map (
      I0 => fine_adjust_done_r_reg_n_0,
      I1 => rd_data_offset_cal_done,
      I2 => pi_calib_done,
      I3 => \^pi_dqs_found_done\,
      O => \gen_byte_sel_div2.calib_in_common_reg_0\
    );
\gen_byte_sel_div2.ctl_lane_sel[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F20FFFF2F200000"
    )
        port map (
      I0 => fine_adjust_lane_cnt(0),
      I1 => \gen_byte_sel_div2.ctl_lane_sel[2]_i_2_n_0\,
      I2 => ck_addr_cmd_delay_done,
      I3 => ctl_lane_cnt(0),
      I4 => \^ctl_lane_sel\,
      I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0\,
      O => \gen_byte_sel_div2.ctl_lane_sel_reg[0]\
    );
\gen_byte_sel_div2.ctl_lane_sel[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F20FFFF2F200000"
    )
        port map (
      I0 => fine_adjust_lane_cnt(1),
      I1 => \gen_byte_sel_div2.ctl_lane_sel[2]_i_2_n_0\,
      I2 => ck_addr_cmd_delay_done,
      I3 => ctl_lane_cnt(1),
      I4 => \^ctl_lane_sel\,
      I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0\,
      O => \gen_byte_sel_div2.ctl_lane_sel_reg[1]\
    );
\gen_byte_sel_div2.ctl_lane_sel[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F20FFFF2F200000"
    )
        port map (
      I0 => fine_adjust_lane_cnt(2),
      I1 => \gen_byte_sel_div2.ctl_lane_sel[2]_i_2_n_0\,
      I2 => ck_addr_cmd_delay_done,
      I3 => ctl_lane_cnt(2),
      I4 => \^ctl_lane_sel\,
      I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0\,
      O => \gen_byte_sel_div2.ctl_lane_sel_reg[2]\
    );
\gen_byte_sel_div2.ctl_lane_sel[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rst_stg1_cal(1),
      I1 => rst_stg1_cal(0),
      I2 => rst_stg1_cal(2),
      O => \gen_byte_sel_div2.ctl_lane_sel[2]_i_2_n_0\
    );
\gen_byte_sel_div2.ctl_lane_sel[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808888"
    )
        port map (
      I0 => dqs_po_dec_done,
      I1 => pi_fine_dly_dec_done,
      I2 => rd_data_offset_cal_done,
      I3 => fine_adjust_done_r_reg_n_0,
      I4 => ck_addr_cmd_delay_done,
      O => \^ctl_lane_sel\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pi_dqs_found_done\,
      I1 => rdlvl_stg1_done_reg,
      O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\
    );
ififo_rst_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => \calib_zero_inputs_reg[2]\(1),
      I1 => calib_in_common,
      I2 => rst_stg1_cal(1),
      I3 => Q(0),
      I4 => Q(1),
      I5 => phy_if_reset,
      O => ififo_rst_reg0
    );
\inc_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(0)
    );
\inc_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[1]\,
      O => \p_0_in__0\(1)
    );
\inc_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[1]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      O => \p_0_in__0\(2)
    );
\inc_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[2]\,
      I1 => \inc_cnt_reg_n_0_[0]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[3]\,
      O => \p_0_in__0\(3)
    );
\inc_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[0]\,
      I1 => \inc_cnt_reg_n_0_[4]\,
      I2 => \inc_cnt_reg_n_0_[2]\,
      I3 => \inc_cnt_reg_n_0_[1]\,
      I4 => \inc_cnt_reg_n_0_[3]\,
      O => \p_0_in__0\(4)
    );
\inc_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      I1 => fine_adj_state_r(3),
      I2 => fine_adj_state_r(2),
      I3 => fine_adj_state_r(0),
      I4 => fine_adj_state_r(1),
      O => inc_cnt
    );
\inc_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \inc_cnt_reg_n_0_[5]\,
      I1 => \inc_cnt_reg_n_0_[3]\,
      I2 => \inc_cnt_reg_n_0_[1]\,
      I3 => \inc_cnt_reg_n_0_[2]\,
      I4 => \inc_cnt_reg_n_0_[4]\,
      I5 => \inc_cnt_reg_n_0_[0]\,
      O => \p_0_in__0\(5)
    );
\inc_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(0),
      Q => \inc_cnt_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\inc_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(1),
      Q => \inc_cnt_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\inc_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(2),
      Q => \inc_cnt_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\inc_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(3),
      Q => \inc_cnt_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\inc_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(4),
      Q => \inc_cnt_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\inc_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => inc_cnt,
      D => \p_0_in__0\(5),
      Q => \inc_cnt_reg_n_0_[5]\,
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\init_dec_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \init_dec_cnt_reg__0\(0),
      O => init_dec_cnt0(0)
    );
\init_dec_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \init_dec_cnt_reg__0\(1),
      I1 => \init_dec_cnt_reg__0\(0),
      O => init_dec_cnt0(1)
    );
\init_dec_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \init_dec_cnt_reg__0\(2),
      I1 => \init_dec_cnt_reg__0\(0),
      I2 => \init_dec_cnt_reg__0\(1),
      O => init_dec_cnt0(2)
    );
\init_dec_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \init_dec_cnt_reg__0\(3),
      I1 => \init_dec_cnt_reg__0\(1),
      I2 => \init_dec_cnt_reg__0\(0),
      I3 => \init_dec_cnt_reg__0\(2),
      O => init_dec_cnt0(3)
    );
\init_dec_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \init_dec_cnt_reg__0\(4),
      I1 => \init_dec_cnt_reg__0\(2),
      I2 => \init_dec_cnt_reg__0\(0),
      I3 => \init_dec_cnt_reg__0\(1),
      I4 => \init_dec_cnt_reg__0\(3),
      O => init_dec_cnt0(4)
    );
\init_dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000000000"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(2),
      I2 => fine_adj_state_r(3),
      I3 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      I4 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I5 => fine_adj_state_r(1),
      O => init_dec_cnt
    );
\init_dec_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \init_dec_cnt_reg__0\(5),
      I1 => \init_dec_cnt_reg__0\(3),
      I2 => \init_dec_cnt_reg__0\(1),
      I3 => \init_dec_cnt_reg__0\(0),
      I4 => \init_dec_cnt_reg__0\(2),
      I5 => \init_dec_cnt_reg__0\(4),
      O => init_dec_cnt0(5)
    );
\init_dec_cnt_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(0),
      Q => \init_dec_cnt_reg__0\(0),
      S => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\init_dec_cnt_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(1),
      Q => \init_dec_cnt_reg__0\(1),
      S => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\init_dec_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(2),
      Q => \init_dec_cnt_reg__0\(2),
      S => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\init_dec_cnt_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(3),
      Q => \init_dec_cnt_reg__0\(3),
      S => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\init_dec_cnt_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(4),
      Q => \init_dec_cnt_reg__0\(4),
      S => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\init_dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => init_dec_cnt,
      D => init_dec_cnt0(5),
      Q => \init_dec_cnt_reg__0\(5),
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
init_dec_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAEAAAA"
    )
        port map (
      I0 => init_dec_done_reg_n_0,
      I1 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\,
      I2 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\,
      I3 => init_dec_done_i_2_n_0,
      I4 => init_dec_done_i_3_n_0,
      I5 => fine_adj_state_r(1),
      O => init_dec_done_i_1_n_0
    );
init_dec_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \dec_cnt_reg_n_0_[4]\,
      I1 => \dec_cnt_reg_n_0_[2]\,
      I2 => \dec_cnt_reg_n_0_[0]\,
      I3 => \dec_cnt_reg_n_0_[1]\,
      I4 => \dec_cnt_reg_n_0_[3]\,
      I5 => \dec_cnt_reg_n_0_[5]\,
      O => init_dec_done_i_2_n_0
    );
init_dec_done_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => fine_adj_state_r(2),
      I2 => fine_adj_state_r(0),
      O => init_dec_done_i_3_n_0
    );
init_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dec_done_i_1_n_0,
      Q => init_dec_done_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
init_dqsfound_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data_offset_cal_done,
      Q => init_dqsfound_done_r1_reg_n_0,
      R => '0'
    );
init_dqsfound_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dqsfound_done_r1_reg_n_0,
      Q => \^init_dqsfound_done_r2\,
      R => '0'
    );
init_dqsfound_done_r4_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => \^init_dqsfound_done_r2\,
      Q => init_dqsfound_done_r4_reg_srl2_n_0
    );
init_dqsfound_done_r5_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dqsfound_done_r4_reg_srl2_n_0,
      Q => init_dqsfound_done_r5,
      R => '0'
    );
init_dqsfound_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      I1 => p_1_in63_in,
      I2 => p_1_in58_in,
      I3 => \rstdiv0_sync_r1_reg_rep__23\,
      I4 => init_dqsfound_done_r_i_2_n_0,
      O => init_dqsfound_done_r_i_1_n_0
    );
init_dqsfound_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFFFFFF10000000"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => pi_dqs_found_all_bank(2),
      I3 => pi_dqs_found_all_bank(1),
      I4 => pi_dqs_found_all_bank(0),
      I5 => rd_data_offset_cal_done,
      O => init_dqsfound_done_r_i_2_n_0
    );
init_dqsfound_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_dqsfound_done_r_i_1_n_0,
      Q => rd_data_offset_cal_done,
      R => '0'
    );
\init_state_r[1]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => prech_req_posedge_r_reg,
      I1 => \^pi_dqs_found_rank_done\,
      I2 => \^pi_dqs_found_done\,
      O => \init_state_r_reg[1]\
    );
ofifo_rst_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => \calib_zero_inputs_reg[2]\(1),
      I1 => calib_in_common,
      I2 => rst_stg1_cal(1),
      I3 => Q(0),
      I4 => Q(1),
      I5 => A_rst_primitives,
      O => ofifo_rst_reg0
    );
\ofifo_rst_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => \calib_zero_inputs_reg[2]\(2),
      I1 => calib_in_common,
      I2 => rst_stg1_cal(2),
      I3 => Q(0),
      I4 => Q(1),
      I5 => A_rst_primitives_15,
      O => ofifo_rst_reg0_5
    );
\ofifo_rst_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45440000"
    )
        port map (
      I0 => \calib_zero_inputs_reg[2]\(2),
      I1 => calib_in_common,
      I2 => Q(1),
      I3 => Q(0),
      I4 => rst_stg1_cal(2),
      I5 => A_rst_primitives_15,
      O => ofifo_rst_reg0_7
    );
\ofifo_rst_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45004400"
    )
        port map (
      I0 => \calib_zero_inputs_reg[2]\(2),
      I1 => calib_in_common,
      I2 => Q(0),
      I3 => rst_stg1_cal(2),
      I4 => Q(1),
      I5 => A_rst_primitives_15,
      O => ofifo_rst_reg0_9
    );
\phaser_in_gen.phaser_in_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => rst_stg1_cal(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \pi_dqs_found_lanes_r1_reg[4]_0\
    );
\phaser_in_gen.phaser_in_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => rst_stg1_cal(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => ififo_rst_reg
    );
\phaser_in_gen.phaser_in_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => rst_stg1_cal(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => ififo_rst_reg_0
    );
\phaser_in_gen.phaser_in_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => rst_stg1_cal(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => ififo_rst_reg_1
    );
\phaser_in_gen.phaser_in_i_5__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => rst_stg1_cal(0),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => ififo_rst_reg_2
    );
\phaser_in_gen.phaser_in_i_5__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => rst_stg1_cal(2),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => ififo_rst_reg_3
    );
\phaser_in_gen.phaser_in_i_5__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => rst_stg1_cal(2),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => ififo_rst_reg_4
    );
\phaser_in_gen.phaser_in_i_5__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => rst_stg1_cal(2),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => ififo_rst_reg_5
    );
\phaser_out_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]\
    );
\phaser_out_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE0E00"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_0\
    );
\phaser_out_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_1\
    );
\phaser_out_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEE000"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(0),
      I3 => Q(1),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_2\
    );
\phaser_out_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_3\
    );
\phaser_out_i_3__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(0),
      I3 => Q(1),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_4\
    );
\phaser_out_i_3__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_5\
    );
\phaser_out_i_3__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]_6\
    );
phaser_out_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000E0000"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => calib_in_common,
      I3 => Q(0),
      I4 => Q(1),
      I5 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]_7\
    );
\phaser_out_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000E00"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => calib_in_common,
      I3 => Q(0),
      I4 => Q(1),
      I5 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]_8\
    );
\phaser_out_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E000000"
    )
        port map (
      I0 => ck_po_stg2_f_indec,
      I1 => dqs_po_stg2_f_incdec,
      I2 => calib_in_common,
      I3 => Q(1),
      I4 => Q(0),
      I5 => \calib_zero_inputs_reg[2]\(1),
      O => D_po_fine_inc108_out
    );
\pi_dqs_found_all_bank[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(2),
      I1 => pi_dqs_found_lanes_r3(3),
      I2 => pi_dqs_found_lanes_r3(1),
      I3 => pi_dqs_found_lanes_r3(0),
      O => p_8_out(0)
    );
\pi_dqs_found_all_bank[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(8),
      I1 => pi_dqs_found_lanes_r3(10),
      I2 => pi_dqs_found_lanes_r3(9),
      O => p_8_out(2)
    );
\pi_dqs_found_all_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_all_bank(0),
      Q => pi_dqs_found_all_bank_r(0),
      R => '0'
    );
\pi_dqs_found_all_bank_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_all_bank(2),
      Q => pi_dqs_found_all_bank_r(2),
      R => '0'
    );
\pi_dqs_found_all_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pi_dqs_found_start_reg,
      D => p_8_out(0),
      Q => pi_dqs_found_all_bank(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\pi_dqs_found_all_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pi_dqs_found_start_reg,
      D => pi_dqs_found_lanes_r3(4),
      Q => pi_dqs_found_all_bank(1),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\pi_dqs_found_all_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pi_dqs_found_start_reg,
      D => p_8_out(2),
      Q => pi_dqs_found_all_bank(2),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\pi_dqs_found_any_bank[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(2),
      I1 => pi_dqs_found_lanes_r3(0),
      I2 => pi_dqs_found_lanes_r3(3),
      I3 => pi_dqs_found_lanes_r3(1),
      O => \pi_dqs_found_any_bank[0]_i_1_n_0\
    );
\pi_dqs_found_any_bank[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => pi_dqs_found_lanes_r3(8),
      I1 => pi_dqs_found_lanes_r3(10),
      I2 => pi_dqs_found_lanes_r3(9),
      O => \pi_dqs_found_any_bank[2]_i_1_n_0\
    );
\pi_dqs_found_any_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_any_bank(0),
      Q => \pi_dqs_found_any_bank_r_reg_n_0_[0]\,
      R => '0'
    );
\pi_dqs_found_any_bank_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_all_bank(1),
      Q => p_2_in80_in,
      R => '0'
    );
\pi_dqs_found_any_bank_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_any_bank(2),
      Q => p_2_in79_in,
      R => '0'
    );
\pi_dqs_found_any_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pi_dqs_found_start_reg,
      D => \pi_dqs_found_any_bank[0]_i_1_n_0\,
      Q => pi_dqs_found_any_bank(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\pi_dqs_found_any_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pi_dqs_found_start_reg,
      D => \pi_dqs_found_any_bank[2]_i_1_n_0\,
      Q => pi_dqs_found_any_bank(2),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\pi_dqs_found_lanes_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(0),
      Q => pi_dqs_found_lanes_r1(0),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(7),
      Q => pi_dqs_found_lanes_r1(10),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(1),
      Q => pi_dqs_found_lanes_r1(1),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(2),
      Q => pi_dqs_found_lanes_r1(2),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(3),
      Q => pi_dqs_found_lanes_r1(3),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(4),
      Q => pi_dqs_found_lanes_r1(4),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_2\,
      Q => pi_dqs_found_lanes_r1(5),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_1\,
      Q => pi_dqs_found_lanes_r1(6),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hrn_0_0\,
      Q => pi_dqs_found_lanes_r1(7),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(5),
      Q => pi_dqs_found_lanes_r1(8),
      R => '0'
    );
\pi_dqs_found_lanes_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes(6),
      Q => pi_dqs_found_lanes_r1(9),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(0),
      Q => pi_dqs_found_lanes_r2(0),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(10),
      Q => pi_dqs_found_lanes_r2(10),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(1),
      Q => pi_dqs_found_lanes_r2(1),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(2),
      Q => pi_dqs_found_lanes_r2(2),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(3),
      Q => pi_dqs_found_lanes_r2(3),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(4),
      Q => pi_dqs_found_lanes_r2(4),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(5),
      Q => pi_dqs_found_lanes_r2(5),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(6),
      Q => pi_dqs_found_lanes_r2(6),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(7),
      Q => pi_dqs_found_lanes_r2(7),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(8),
      Q => pi_dqs_found_lanes_r2(8),
      R => '0'
    );
\pi_dqs_found_lanes_r2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r1(9),
      Q => pi_dqs_found_lanes_r2(9),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(0),
      Q => pi_dqs_found_lanes_r3(0),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(10),
      Q => pi_dqs_found_lanes_r3(10),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(1),
      Q => pi_dqs_found_lanes_r3(1),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(2),
      Q => pi_dqs_found_lanes_r3(2),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(3),
      Q => pi_dqs_found_lanes_r3(3),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(4),
      Q => pi_dqs_found_lanes_r3(4),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(5),
      Q => pi_dqs_found_lanes_r3(5),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(6),
      Q => pi_dqs_found_lanes_r3(6),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(7),
      Q => pi_dqs_found_lanes_r3(7),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(8),
      Q => pi_dqs_found_lanes_r3(8),
      R => '0'
    );
\pi_dqs_found_lanes_r3_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_lanes_r2(9),
      Q => pi_dqs_found_lanes_r3(9),
      R => '0'
    );
\pi_rst_stg1_cal[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      I1 => rst_dqs_find_reg_n_0,
      O => \pi_rst_stg1_cal[0]_i_1_n_0\
    );
\pi_rst_stg1_cal[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_1_in63_in,
      I1 => rst_dqs_find_reg_n_0,
      O => \pi_rst_stg1_cal[1]_i_1_n_0\
    );
\pi_rst_stg1_cal[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_1_in58_in,
      I1 => rst_dqs_find_reg_n_0,
      O => \pi_rst_stg1_cal[2]_i_1_n_0\
    );
\pi_rst_stg1_cal_r1[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFE0"
    )
        port map (
      I0 => pi_dqs_found_all_bank(0),
      I1 => \pi_dqs_found_any_bank_r_reg_n_0_[0]\,
      I2 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      I3 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      I4 => fine_adjust_reg_n_0,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => pi_rst_stg1_cal_r1_reg022_out
    );
\pi_rst_stg1_cal_r1[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFE0"
    )
        port map (
      I0 => pi_dqs_found_all_bank(1),
      I1 => p_2_in80_in,
      I2 => p_0_in29_in,
      I3 => p_1_in63_in,
      I4 => fine_adjust_reg_n_0,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => pi_rst_stg1_cal_r1_reg019_out
    );
\pi_rst_stg1_cal_r1[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFE0"
    )
        port map (
      I0 => pi_dqs_found_all_bank(2),
      I1 => p_2_in79_in,
      I2 => p_0_in24_in,
      I3 => p_1_in58_in,
      I4 => fine_adjust_reg_n_0,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => pi_rst_stg1_cal_r1_reg0
    );
\pi_rst_stg1_cal_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_rst_stg1_cal_r1_reg022_out,
      Q => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      R => '0'
    );
\pi_rst_stg1_cal_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_rst_stg1_cal_r1_reg019_out,
      Q => p_0_in29_in,
      R => '0'
    );
\pi_rst_stg1_cal_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_rst_stg1_cal_r1_reg0,
      Q => p_0_in24_in,
      R => '0'
    );
\pi_rst_stg1_cal_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\,
      I1 => \pi_rst_stg1_cal_r[0]_i_2_n_0\,
      I2 => \rstdiv0_sync_r1_reg_rep__23\,
      I3 => fine_adjust_reg_n_0,
      O => \pi_rst_stg1_cal_r[0]_i_1_n_0\
    );
\pi_rst_stg1_cal_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF2F22"
    )
        port map (
      I0 => \pi_dqs_found_any_bank_r_reg_n_0_[0]\,
      I1 => pi_dqs_found_all_bank(0),
      I2 => dqs_found_start_r,
      I3 => pi_dqs_found_start_reg,
      I4 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I5 => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      O => \pi_rst_stg1_cal_r[0]_i_2_n_0\
    );
\pi_rst_stg1_cal_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => p_0_in29_in,
      I1 => \pi_rst_stg1_cal_r[1]_i_2_n_0\,
      I2 => \rstdiv0_sync_r1_reg_rep__23\,
      I3 => fine_adjust_reg_n_0,
      O => \pi_rst_stg1_cal_r[1]_i_1_n_0\
    );
\pi_rst_stg1_cal_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF2F22"
    )
        port map (
      I0 => p_2_in80_in,
      I1 => pi_dqs_found_all_bank(1),
      I2 => dqs_found_start_r,
      I3 => pi_dqs_found_start_reg,
      I4 => \rd_byte_data_offset[0][11]_i_4_n_0\,
      I5 => p_1_in63_in,
      O => \pi_rst_stg1_cal_r[1]_i_2_n_0\
    );
\pi_rst_stg1_cal_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => p_0_in24_in,
      I1 => \pi_rst_stg1_cal_r[2]_i_2_n_0\,
      I2 => \rstdiv0_sync_r1_reg_rep__23\,
      I3 => fine_adjust_reg_n_0,
      O => \pi_rst_stg1_cal_r[2]_i_1_n_0\
    );
\pi_rst_stg1_cal_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF2F22"
    )
        port map (
      I0 => p_2_in79_in,
      I1 => pi_dqs_found_all_bank(2),
      I2 => dqs_found_start_r,
      I3 => pi_dqs_found_start_reg,
      I4 => \rd_byte_data_offset[0][17]_i_4_n_0\,
      I5 => p_1_in58_in,
      O => \pi_rst_stg1_cal_r[2]_i_2_n_0\
    );
\pi_rst_stg1_cal_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_r[0]_i_1_n_0\,
      Q => \pi_rst_stg1_cal_r_reg_n_0_[0]\,
      R => '0'
    );
\pi_rst_stg1_cal_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_r[1]_i_1_n_0\,
      Q => p_1_in63_in,
      R => '0'
    );
\pi_rst_stg1_cal_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_r[2]_i_1_n_0\,
      Q => p_1_in58_in,
      R => '0'
    );
\pi_rst_stg1_cal_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal[0]_i_1_n_0\,
      Q => rst_stg1_cal(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\pi_rst_stg1_cal_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal[1]_i_1_n_0\,
      Q => rst_stg1_cal(1),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\pi_rst_stg1_cal_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal[2]_i_1_n_0\,
      Q => rst_stg1_cal(2),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
rank_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^pi_dqs_found_rank_done\,
      Q => rank_done_r1,
      R => '0'
    );
rank_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20000000"
    )
        port map (
      I0 => rank_done_r_i_2_n_0,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      I2 => pi_dqs_found_all_bank(2),
      I3 => pi_dqs_found_all_bank(1),
      I4 => pi_dqs_found_all_bank(0),
      O => rank_done_r_i_1_n_0
    );
rank_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FDFDFDFDFDFDFD"
    )
        port map (
      I0 => rd_data_offset_cal_done,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => p_2_in80_in,
      I4 => pi_dqs_found_all_bank_r(2),
      I5 => pi_dqs_found_all_bank_r(0),
      O => rank_done_r_i_2_n_0
    );
rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rank_done_r_i_1_n_0,
      Q => \^pi_dqs_found_rank_done\,
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rd_data_offset_cal_done,
      I1 => init_dqsfound_done_r1_reg_n_0,
      O => p_22_out
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I4 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23\,
      I1 => rd_data_offset_cal_done,
      I2 => init_dqsfound_done_r1_reg_n_0,
      O => final_data_offset_mc
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I4 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      I5 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_reg[5]\(0),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_reg[5]\(1),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_reg[5]\(2),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_reg[5]\(3),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_reg[5]\(4),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_reg[5]\(5),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][0]\,
      Q => rd_data_offset_ranks_0(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][1]\,
      Q => rd_data_offset_ranks_0(1),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][2]\,
      Q => rd_data_offset_ranks_0(2),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      Q => \calib_data_offset_0_reg[3]\(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][4]\,
      Q => rd_data_offset_ranks_0(4),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][5]\,
      Q => rd_data_offset_ranks_0(5),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => p_0_in(4),
      I1 => p_0_in(2),
      I2 => p_0_in(0),
      I3 => p_0_in(1),
      I4 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => p_0_in(4),
      I1 => p_0_in(2),
      I2 => p_0_in(0),
      I3 => p_0_in(1),
      I4 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      I5 => p_0_in(5),
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in(0),
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_0_in(0),
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(0),
      I2 => p_0_in(1),
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      I1 => p_0_in(1),
      I2 => p_0_in(0),
      I3 => p_0_in(2),
      O => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][10]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(4),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(5),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(0),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][7]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(1),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][8]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(2),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][9]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_1_reg[5]\(3),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => p_0_in(4),
      Q => rd_data_offset_ranks_1(4),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => p_0_in(5),
      Q => rd_data_offset_ranks_1(5),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => p_0_in(0),
      Q => rd_data_offset_ranks_1(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => p_0_in(1),
      Q => rd_data_offset_ranks_1(1),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => p_0_in(2),
      Q => rd_data_offset_ranks_1(2),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      Q => \calib_data_offset_1_reg[3]\(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I4 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I4 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      I5 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      O => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0\
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(0),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(1),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(2),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(3),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(4),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => final_data_offset_mc,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0\,
      Q => \^cmd_pipe_plus.mc_data_offset_2_reg[5]\(5),
      R => '0'
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][12]\,
      Q => rd_data_offset_ranks_2(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][13]\,
      Q => rd_data_offset_ranks_2(1),
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][14]\,
      Q => rd_data_offset_ranks_2(2),
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      Q => \calib_data_offset_2_reg[3]\(0),
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][16]\,
      Q => rd_data_offset_ranks_2(4),
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_22_out,
      D => \rd_byte_data_offset_reg_n_0_[0][17]\,
      Q => rd_data_offset_ranks_2(5),
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rd_byte_data_offset[0][10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      I1 => p_0_in(1),
      I2 => p_0_in(0),
      I3 => p_0_in(2),
      I4 => p_0_in(4),
      O => \p_1_in__0\(4)
    );
\rd_byte_data_offset[0][11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCECCCECCCFCCCE"
    )
        port map (
      I0 => \rd_byte_data_offset[0][11]_i_4_n_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      I4 => rank_done_r1,
      I5 => rd_data_offset_cal_done,
      O => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset[0][11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000080000"
    )
        port map (
      I0 => fine_adj_state_r185_out,
      I1 => \rd_byte_data_offset[0][5]_i_5_n_0\,
      I2 => pi_dqs_found_all_bank(1),
      I3 => rd_data_offset_cal_done,
      I4 => \rd_byte_data_offset[0][5]_i_6_n_0\,
      I5 => \rd_byte_data_offset[0][11]_i_4_n_0\,
      O => \rd_byte_data_offset[0][11]_i_2_n_0\
    );
\rd_byte_data_offset[0][11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => p_0_in(4),
      I1 => p_0_in(2),
      I2 => p_0_in(0),
      I3 => p_0_in(1),
      I4 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      I5 => p_0_in(5),
      O => \p_1_in__0\(5)
    );
\rd_byte_data_offset[0][11]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF0FEF0"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      I1 => p_0_in(1),
      I2 => p_0_in(5),
      I3 => p_0_in(4),
      I4 => p_0_in(2),
      O => \rd_byte_data_offset[0][11]_i_4_n_0\
    );
\rd_byte_data_offset[0][13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      O => \rd_byte_data_offset[0][13]_i_1_n_0\
    );
\rd_byte_data_offset[0][14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      O => \p_1_in__1\(2)
    );
\rd_byte_data_offset[0][15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I3 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      O => \p_1_in__1\(3)
    );
\rd_byte_data_offset[0][16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      O => \p_1_in__1\(4)
    );
\rd_byte_data_offset[0][17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCECCCECCCFCCCE"
    )
        port map (
      I0 => \rd_byte_data_offset[0][17]_i_4_n_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      I4 => rank_done_r1,
      I5 => rd_data_offset_cal_done,
      O => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset[0][17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000080000"
    )
        port map (
      I0 => fine_adj_state_r185_out,
      I1 => \rd_byte_data_offset[0][5]_i_5_n_0\,
      I2 => pi_dqs_found_all_bank(2),
      I3 => rd_data_offset_cal_done,
      I4 => \rd_byte_data_offset[0][5]_i_6_n_0\,
      I5 => \rd_byte_data_offset[0][17]_i_4_n_0\,
      O => \rd_byte_data_offset[0][17]_i_2_n_0\
    );
\rd_byte_data_offset[0][17]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][12]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I4 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      I5 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      O => \p_1_in__1\(5)
    );
\rd_byte_data_offset[0][17]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF0FEF0"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][13]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][17]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][16]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][14]\,
      O => \rd_byte_data_offset[0][17]_i_4_n_0\
    );
\rd_byte_data_offset[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      O => \rd_byte_data_offset[0][1]_i_1_n_0\
    );
\rd_byte_data_offset[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      O => p_1_in(2)
    );
\rd_byte_data_offset[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I3 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      O => p_1_in(3)
    );
\rd_byte_data_offset[0][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      O => p_1_in(4)
    );
\rd_byte_data_offset[0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCECCCECCCFCCCE"
    )
        port map (
      I0 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      I4 => rank_done_r1,
      I5 => rd_data_offset_cal_done,
      O => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => \rd_byte_data_offset[0][5]_i_4_n_0\,
      I1 => \rd_byte_data_offset[0][5]_i_5_n_0\,
      I2 => pi_dqs_found_all_bank(0),
      I3 => rd_data_offset_cal_done,
      I4 => \rd_byte_data_offset[0][5]_i_6_n_0\,
      I5 => fine_adj_state_r185_out,
      O => rd_byte_data_offset
    );
\rd_byte_data_offset[0][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      I1 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][0]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I4 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      I5 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      O => p_1_in(5)
    );
\rd_byte_data_offset[0][5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF0FEF0"
    )
        port map (
      I0 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      I1 => \rd_byte_data_offset_reg_n_0_[0][1]\,
      I2 => \rd_byte_data_offset_reg_n_0_[0][5]\,
      I3 => \rd_byte_data_offset_reg_n_0_[0][4]\,
      I4 => \rd_byte_data_offset_reg_n_0_[0][2]\,
      O => \rd_byte_data_offset[0][5]_i_4_n_0\
    );
\rd_byte_data_offset[0][5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000D"
    )
        port map (
      I0 => rank_done_r1,
      I1 => rd_data_offset_cal_done,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rd_byte_data_offset[0][5]_i_5_n_0\
    );
\rd_byte_data_offset[0][5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dqs_found_start_r,
      I1 => fine_adjust_reg_n_0,
      O => \rd_byte_data_offset[0][5]_i_6_n_0\
    );
\rd_byte_data_offset[0][5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \detect_rd_cnt_reg__0\(0),
      I1 => detect_pi_found_dqs,
      I2 => \detect_rd_cnt_reg__0\(3),
      I3 => \detect_rd_cnt_reg__0\(2),
      I4 => \detect_rd_cnt_reg__0\(1),
      O => fine_adj_state_r185_out
    );
\rd_byte_data_offset[0][7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => p_0_in(0),
      I1 => p_0_in(1),
      O => \rd_byte_data_offset[0][7]_i_1_n_0\
    );
\rd_byte_data_offset[0][8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_0_in(0),
      I2 => p_0_in(2),
      O => \p_1_in__0\(2)
    );
\rd_byte_data_offset[0][9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(0),
      I2 => p_0_in(1),
      I3 => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      O => \p_1_in__0\(3)
    );
\rd_byte_data_offset_reg[0][0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][0]\,
      S => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => \p_1_in__0\(4),
      Q => p_0_in(4),
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => \p_1_in__0\(5),
      Q => p_0_in(5),
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][12]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][12]\,
      S => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][13]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \rd_byte_data_offset[0][13]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][13]\,
      S => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__1\(2),
      Q => \rd_byte_data_offset_reg_n_0_[0][14]\,
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__1\(3),
      Q => \^rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0),
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__1\(4),
      Q => \rd_byte_data_offset_reg_n_0_[0][16]\,
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][17]_i_2_n_0\,
      D => \p_1_in__1\(5),
      Q => \rd_byte_data_offset_reg_n_0_[0][17]\,
      R => \rd_byte_data_offset[0][17]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => \rd_byte_data_offset[0][1]_i_1_n_0\,
      Q => \rd_byte_data_offset_reg_n_0_[0][1]\,
      S => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_1_in(2),
      Q => \rd_byte_data_offset_reg_n_0_[0][2]\,
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_1_in(3),
      Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0),
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_1_in(4),
      Q => \rd_byte_data_offset_reg_n_0_[0][4]\,
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_byte_data_offset,
      D => p_1_in(5),
      Q => \rd_byte_data_offset_reg_n_0_[0][5]\,
      R => \rd_byte_data_offset[0][5]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][6]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][6]_i_1_n_0\,
      Q => p_0_in(0),
      S => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][7]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => \rd_byte_data_offset[0][7]_i_1_n_0\,
      Q => p_0_in(1),
      S => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => \p_1_in__0\(2),
      Q => p_0_in(2),
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rd_byte_data_offset_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_byte_data_offset[0][11]_i_2_n_0\,
      D => \p_1_in__0\(3),
      Q => \^rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0),
      R => \rd_byte_data_offset[0][11]_i_1_n_0\
    );
\rnk_cnt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \^pi_dqs_found_rank_done\,
      I1 => rd_data_offset_cal_done,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      O => \rnk_cnt_r[0]_i_1_n_0\
    );
\rnk_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => \rnk_cnt_r_reg_n_0_[0]\,
      I1 => \^pi_dqs_found_rank_done\,
      I2 => rd_data_offset_cal_done,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \rnk_cnt_r[1]_i_1_n_0\
    );
\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[0]_i_1_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[1]_i_1_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
rst_dqs_find_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BABF8A80"
    )
        port map (
      I0 => rst_dqs_find,
      I1 => rst_dqs_find_i_3_n_0,
      I2 => fine_adj_state_r(1),
      I3 => rst_dqs_find_i_4_n_0,
      I4 => rst_dqs_find_reg_n_0,
      O => rst_dqs_find_i_1_n_0
    );
rst_dqs_find_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8800FF30"
    )
        port map (
      I0 => prech_done,
      I1 => fine_adj_state_r(1),
      I2 => init_dqsfound_done_r5,
      I3 => rst_dqs_find_i_5_n_0,
      I4 => fine_adj_state_r(0),
      O => rst_dqs_find
    );
rst_dqs_find_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800B80030333000"
    )
        port map (
      I0 => prech_done,
      I1 => fine_adj_state_r(0),
      I2 => rst_dqs_find_i_6_n_0,
      I3 => fine_adj_state_r(3),
      I4 => p_1_in30_in,
      I5 => fine_adj_state_r(2),
      O => rst_dqs_find_i_3_n_0
    );
rst_dqs_find_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000B0008"
    )
        port map (
      I0 => fine_adj_state_r034_out,
      I1 => fine_adj_state_r(0),
      I2 => fine_adj_state_r(3),
      I3 => fine_adj_state_r(2),
      I4 => init_dqsfound_done_r5,
      O => rst_dqs_find_i_4_n_0
    );
rst_dqs_find_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF2A20"
    )
        port map (
      I0 => fine_adj_state_r(3),
      I1 => \first_fail_taps[5]_i_4_n_0\,
      I2 => fine_adj_state_r147_out,
      I3 => fine_adj_state_r3,
      I4 => fine_adj_state_r(2),
      O => rst_dqs_find_i_5_n_0
    );
rst_dqs_find_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF2020E020"
    )
        port map (
      I0 => \dec_cnt[5]_i_7_n_0\,
      I1 => p_1_in30_in,
      I2 => detect_pi_found_dqs,
      I3 => fine_adj_state_r3,
      I4 => fine_adj_state_r18_out,
      I5 => fine_adj_state_r(2),
      O => rst_dqs_find_i_6_n_0
    );
rst_dqs_find_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_dqs_find_reg_n_0,
      Q => rst_dqs_find_r1,
      R => '0'
    );
rst_dqs_find_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_dqs_find_r1,
      Q => rst_dqs_find_r2,
      R => '0'
    );
rst_dqs_find_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_dqs_find_i_1_n_0,
      Q => rst_dqs_find_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__12\(1)
    );
\stable_pass_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \stable_pass_cnt_reg_n_0_[0]\,
      I1 => pi_dqs_found_all_bank(2),
      I2 => pi_dqs_found_all_bank(1),
      I3 => pi_dqs_found_all_bank(0),
      O => \p_0_in__1\(0)
    );
\stable_pass_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => pi_dqs_found_all_bank(0),
      I1 => pi_dqs_found_all_bank(1),
      I2 => pi_dqs_found_all_bank(2),
      I3 => \stable_pass_cnt_reg_n_0_[0]\,
      I4 => \stable_pass_cnt_reg__0\(1),
      O => \p_0_in__1\(1)
    );
\stable_pass_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1540"
    )
        port map (
      I0 => fine_adj_state_r147_out,
      I1 => \stable_pass_cnt_reg__0\(1),
      I2 => \stable_pass_cnt_reg_n_0_[0]\,
      I3 => \stable_pass_cnt_reg__0\(2),
      O => \p_0_in__1\(2)
    );
\stable_pass_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \stable_pass_cnt_reg__0\(2),
      I1 => \stable_pass_cnt_reg__0\(1),
      I2 => \stable_pass_cnt_reg_n_0_[0]\,
      I3 => \stable_pass_cnt_reg__0\(3),
      I4 => fine_adj_state_r147_out,
      O => \p_0_in__1\(3)
    );
\stable_pass_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007FFF00008000"
    )
        port map (
      I0 => \stable_pass_cnt_reg_n_0_[0]\,
      I1 => \stable_pass_cnt_reg__0\(1),
      I2 => \stable_pass_cnt_reg__0\(2),
      I3 => \stable_pass_cnt_reg__0\(3),
      I4 => fine_adj_state_r147_out,
      I5 => \stable_pass_cnt_reg__0\(4),
      O => \p_0_in__1\(4)
    );
\stable_pass_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10000000"
    )
        port map (
      I0 => fine_adj_state_r(0),
      I1 => fine_adj_state_r(2),
      I2 => fine_adj_state_r(3),
      I3 => detect_pi_found_dqs,
      I4 => fine_adj_state_r(1),
      O => stable_pass_cnt
    );
\stable_pass_cnt[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B04"
    )
        port map (
      I0 => \stable_pass_cnt[5]_i_3_n_0\,
      I1 => \stable_pass_cnt_reg__0\(4),
      I2 => fine_adj_state_r147_out,
      I3 => \stable_pass_cnt_reg__0\(5),
      O => \p_0_in__1\(5)
    );
\stable_pass_cnt[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \stable_pass_cnt_reg_n_0_[0]\,
      I1 => \stable_pass_cnt_reg__0\(1),
      I2 => \stable_pass_cnt_reg__0\(2),
      I3 => \stable_pass_cnt_reg__0\(3),
      O => \stable_pass_cnt[5]_i_3_n_0\
    );
\stable_pass_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(0),
      Q => \stable_pass_cnt_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\stable_pass_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(1),
      Q => \stable_pass_cnt_reg__0\(1),
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\stable_pass_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(2),
      Q => \stable_pass_cnt_reg__0\(2),
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\stable_pass_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(3),
      Q => \stable_pass_cnt_reg__0\(3),
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\stable_pass_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(4),
      Q => \stable_pass_cnt_reg__0\(4),
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
\stable_pass_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_pass_cnt,
      D => \p_0_in__1\(5),
      Q => \stable_pass_cnt_reg__0\(5),
      R => \rstdiv0_sync_r1_reg_rep__1\(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_init is
  port (
    prech_done : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    wrlvl_done_r1 : out STD_LOGIC;
    \complex_row1_rd_cnt_reg[1]_0\ : out STD_LOGIC;
    prech_pending_r_reg_0 : out STD_LOGIC;
    pi_calib_done : out STD_LOGIC;
    wl_sm_start : out STD_LOGIC;
    wrcal_rd_wait : out STD_LOGIC;
    wrcal_sanity_chk : out STD_LOGIC;
    detect_pi_found_dqs : out STD_LOGIC;
    calib_complete : out STD_LOGIC;
    \calib_cke_reg[0]_0\ : out STD_LOGIC;
    pi_dqs_found_done_r1 : out STD_LOGIC;
    \one_rank.stg1_wr_done_reg_0\ : out STD_LOGIC;
    wrlvl_final_if_rst : out STD_LOGIC;
    wr_level_start_r_reg : out STD_LOGIC;
    rdlvl_stg1_start_r_reg : out STD_LOGIC;
    phy_write_calib : out STD_LOGIC;
    phy_read_calib : out STD_LOGIC;
    first_wrcal_pat_r : out STD_LOGIC;
    first_rdlvl_pat_r : out STD_LOGIC;
    rdlvl_stg1_done_r1 : out STD_LOGIC;
    stg1_wr_done : out STD_LOGIC;
    ddr3_lm_done_r : out STD_LOGIC;
    D5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 0 to 0 );
    D0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_2\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_timing_reg[0]_3\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_4\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_5\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_6\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_2\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_3\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_4\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_5\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_6\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_7\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_8\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_9\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_10\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_11\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_12\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_13\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_14\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_15\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_16\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_17\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_18\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_19\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_20\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_21\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_22\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_23\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_24\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_25\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_26\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_27\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_28\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_29\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_30\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_31\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_32\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_33\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_34\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_35\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_36\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_37\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_38\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_39\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_40\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_41\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_42\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_43\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_44\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_45\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_46\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_47\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_48\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_49\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_50\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_51\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_52\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_53\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_54\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_55\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_56\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_57\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_58\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_59\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_60\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_61\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_62\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    mem_init_done_r : out STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\ : out STD_LOGIC;
    cal1_state_r1536_out : out STD_LOGIC;
    mpr_rdlvl_start_r_reg : out STD_LOGIC;
    phy_data_wr_en : out STD_LOGIC;
    phy_cmd_wr_en : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_7\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    mux_reset_n : out STD_LOGIC;
    \data_offset_1_i1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \data_offset_2_i1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_ptr_timing_reg[0]_8\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    \phy_ctl_wd_i1_reg[24]\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    phy_dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
    mux_wrdata : out STD_LOGIC_VECTOR ( 351 downto 0 );
    reset_if_reg : out STD_LOGIC;
    wrcal_start_reg_0 : out STD_LOGIC;
    dqs_found_start_r_reg : out STD_LOGIC;
    CLK : in STD_LOGIC;
    in0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_level_done_reg : in STD_LOGIC;
    wrlvl_rank_done : in STD_LOGIC;
    prbs_rdlvl_done_pulse0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__4\ : in STD_LOGIC;
    wrcal_resume_w : in STD_LOGIC;
    rdlvl_stg1_done_reg : in STD_LOGIC;
    rdlvl_last_byte_done : in STD_LOGIC;
    p_110_in : in STD_LOGIC;
    pi_dqs_found_done : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC;
    wrlvl_byte_redo : in STD_LOGIC;
    wrcal_done_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__22\ : in STD_LOGIC;
    rdlvl_stg1_done_reg_0 : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    mem_out : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \my_empty_reg[1]\ : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]\ : in STD_LOGIC_VECTOR ( 44 downto 0 );
    \my_empty_reg[1]_0\ : in STD_LOGIC;
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_calib_complete_reg_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \my_empty_reg[1]_1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__11\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 34 downto 0 );
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \write_buffer.wr_buf_out_data_reg[511]\ : in STD_LOGIC_VECTOR ( 351 downto 0 );
    \rd_ptr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_2\ : in STD_LOGIC;
    \rd_ptr_reg[3]_1\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_3\ : in STD_LOGIC;
    \rd_ptr_reg[3]_2\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_4\ : in STD_LOGIC;
    \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_5\ : in STD_LOGIC;
    \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_7\ : in STD_LOGIC;
    \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_8\ : in STD_LOGIC;
    \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_9\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__8\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_dqsfound_done_r2 : in STD_LOGIC;
    \rd_byte_data_offset_reg[0][3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_byte_data_offset_reg[0][9]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_byte_data_offset_reg[0][15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    delay_done_r4_reg : in STD_LOGIC;
    ck_addr_cmd_delay_done : in STD_LOGIC;
    phy_mc_go : in STD_LOGIC;
    dqs_found_done_r_reg : in STD_LOGIC;
    done_dqs_tap_inc : in STD_LOGIC;
    rdlvl_stg1_done_reg_1 : in STD_LOGIC;
    prech_req_posedge_r_reg_0 : in STD_LOGIC;
    wrcal_prech_req : in STD_LOGIC;
    rdlvl_stg1_done_reg_2 : in STD_LOGIC;
    wrcal_done_reg_0 : in STD_LOGIC;
    rdlvl_stg1_done_reg_3 : in STD_LOGIC;
    wrlvl_byte_redo_reg : in STD_LOGIC;
    wrcal_sanity_chk_done_reg : in STD_LOGIC;
    wrcal_sanity_chk_done_reg_0 : in STD_LOGIC;
    wrcal_done_reg_1 : in STD_LOGIC;
    rdlvl_last_byte_done_reg : in STD_LOGIC;
    rdlvl_prech_req : in STD_LOGIC;
    dqs_found_prech_req : in STD_LOGIC;
    rdlvl_stg1_rank_done : in STD_LOGIC;
    pi_dqs_found_rank_done : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    mpr_rdlvl_start_r : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__26\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[4]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[1]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[4]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[1]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[5]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[4]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[1]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]\ : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__25\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__24\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__23\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__22\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__21\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__20\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__19\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__18\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__17\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__16\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__15\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__14\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    reset_if : in STD_LOGIC;
    reset_if_r9 : in STD_LOGIC;
    prbs_rdlvl_done_pulse_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__22_0\ : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_0 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_1 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_2 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_3 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_4 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_5 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_6 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_7 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_8 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_9 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_10 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_11 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_12 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_13 : in STD_LOGIC;
    pi_dqs_found_done_r1_reg_14 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rdlvl_stg1_done_reg_4 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__18\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_init : entity is "mig_7series_v2_3_ddr_phy_init";
end mig_7series_0_mig_7series_v2_3_ddr_phy_init;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_init is
  signal \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_11_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0\ : STD_LOGIC;
  signal \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0\ : STD_LOGIC;
  signal \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal \back_to_back_reads_4_1.num_reads[2]_i_1_n_0\ : STD_LOGIC;
  signal bank_w : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal burst_addr_r_i_1_n_0 : STD_LOGIC;
  signal burst_addr_r_i_2_n_0 : STD_LOGIC;
  signal burst_addr_r_i_3_n_0 : STD_LOGIC;
  signal burst_addr_r_reg_n_0 : STD_LOGIC;
  signal calib_cke : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^calib_cke_reg[0]_0\ : STD_LOGIC;
  signal calib_cmd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \calib_cmd[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[1]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_1_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_2_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_3_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_4_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_5_n_0\ : STD_LOGIC;
  signal \calib_cmd[2]_i_6_n_0\ : STD_LOGIC;
  signal calib_cmd_wren : STD_LOGIC;
  signal calib_data_offset_0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \calib_data_offset_0[3]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[3]_i_2_n_0\ : STD_LOGIC;
  signal \calib_data_offset_0[5]_i_1_n_0\ : STD_LOGIC;
  signal calib_data_offset_1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \calib_data_offset_1[3]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_1[3]_i_2_n_0\ : STD_LOGIC;
  signal calib_data_offset_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \calib_data_offset_2[3]_i_1_n_0\ : STD_LOGIC;
  signal \calib_data_offset_2[3]_i_2_n_0\ : STD_LOGIC;
  signal calib_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \calib_odt[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_2_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_3_n_0\ : STD_LOGIC;
  signal \calib_odt[0]_i_4_n_0\ : STD_LOGIC;
  signal \calib_seq[0]_i_1_n_0\ : STD_LOGIC;
  signal \calib_seq[1]_i_1_n_0\ : STD_LOGIC;
  signal calib_wrdata_en : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal cnt_cmd_done_m7_r : STD_LOGIC;
  signal cnt_cmd_done_m7_r_i_1_n_0 : STD_LOGIC;
  signal cnt_cmd_done_m7_r_i_2_n_0 : STD_LOGIC;
  signal cnt_cmd_done_r : STD_LOGIC;
  signal cnt_cmd_done_r_i_1_n_0 : STD_LOGIC;
  signal \cnt_cmd_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r[6]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \cnt_cmd_r_reg_n_0_[6]\ : STD_LOGIC;
  signal cnt_dllk_zqinit_done_r : STD_LOGIC;
  signal cnt_dllk_zqinit_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_dllk_zqinit_r : STD_LOGIC;
  signal \cnt_dllk_zqinit_r_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal cnt_init_af_done_r : STD_LOGIC;
  signal cnt_init_af_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_init_af_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \cnt_init_af_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_af_r[1]_i_1_n_0\ : STD_LOGIC;
  signal cnt_init_mr_done_r : STD_LOGIC;
  signal cnt_init_mr_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_init_mr_done_r_i_2_n_0 : STD_LOGIC;
  signal cnt_init_mr_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal cnt_init_mr_r1 : STD_LOGIC;
  signal \cnt_init_mr_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_init_mr_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_pwron_ce_r_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cnt_pwron_cke_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_pwron_cke_done_r_i_2_n_0 : STD_LOGIC;
  signal cnt_pwron_cke_done_r_i_3_n_0 : STD_LOGIC;
  signal \cnt_pwron_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_pwron_r[8]_i_2_n_0\ : STD_LOGIC;
  signal \cnt_pwron_r_reg__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal cnt_pwron_reset_done_r : STD_LOGIC;
  signal cnt_pwron_reset_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_pwron_reset_done_r_i_2_n_0 : STD_LOGIC;
  signal cnt_txpr_done_r : STD_LOGIC;
  signal cnt_txpr_done_r_i_1_n_0 : STD_LOGIC;
  signal cnt_txpr_done_r_i_2_n_0 : STD_LOGIC;
  signal \cnt_txpr_r[7]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_txpr_r_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal complex_address0 : STD_LOGIC;
  signal \complex_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \complex_address[9]_i_3_n_0\ : STD_LOGIC;
  signal \complex_address[9]_i_4_n_0\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[4]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[5]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[6]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[7]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[8]\ : STD_LOGIC;
  signal \complex_address_reg_n_0_[9]\ : STD_LOGIC;
  signal complex_byte_rd_done : STD_LOGIC;
  signal complex_byte_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_byte_rd_done_i_2_n_0 : STD_LOGIC;
  signal \complex_num_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[1]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_reads[2]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_reads[3]_i_7_n_0\ : STD_LOGIC;
  signal complex_num_reads_dec : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \complex_num_reads_dec[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_reads_dec[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_num_reads_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[0]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[1]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_10_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_7_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_8_n_0\ : STD_LOGIC;
  signal \complex_num_writes[2]_i_9_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_10_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_11_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_12_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_13_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_14_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_15_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_16_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_7_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_8_n_0\ : STD_LOGIC;
  signal \complex_num_writes[4]_i_9_n_0\ : STD_LOGIC;
  signal complex_num_writes_dec : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \complex_num_writes_dec[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[2]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_2_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_3_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_4_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_5_n_0\ : STD_LOGIC;
  signal \complex_num_writes_dec[4]_i_6_n_0\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[0]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[1]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[2]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[3]\ : STD_LOGIC;
  signal \complex_num_writes_reg_n_0_[4]\ : STD_LOGIC;
  signal complex_ocal_odt_ext : STD_LOGIC;
  signal complex_ocal_odt_ext_i_1_n_0 : STD_LOGIC;
  signal complex_ocal_odt_ext_i_2_n_0 : STD_LOGIC;
  signal complex_ocal_reset_rd_addr0 : STD_LOGIC;
  signal complex_ocal_reset_rd_addr_i_2_n_0 : STD_LOGIC;
  signal complex_ocal_reset_rd_addr_reg_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_done_r1 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int_i_1_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_int_i_2_n_0 : STD_LOGIC;
  signal complex_oclkdelay_calib_start_r1 : STD_LOGIC;
  signal complex_odt_ext : STD_LOGIC;
  signal complex_odt_ext_i_1_n_0 : STD_LOGIC;
  signal complex_row0_rd_done : STD_LOGIC;
  signal complex_row0_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_row0_wr_done : STD_LOGIC;
  signal complex_row0_wr_done0 : STD_LOGIC;
  signal complex_row1_rd_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \complex_row1_rd_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \complex_row1_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \complex_row1_rd_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \^complex_row1_rd_cnt_reg[1]_0\ : STD_LOGIC;
  signal complex_row1_rd_done : STD_LOGIC;
  signal complex_row1_rd_done_i_1_n_0 : STD_LOGIC;
  signal complex_row1_rd_done_i_2_n_0 : STD_LOGIC;
  signal complex_row1_rd_done_r1 : STD_LOGIC;
  signal complex_row1_wr_done : STD_LOGIC;
  signal complex_row1_wr_done0 : STD_LOGIC;
  signal complex_row_cnt : STD_LOGIC;
  signal \complex_row_cnt0__1\ : STD_LOGIC;
  signal complex_row_cnt_ocal : STD_LOGIC;
  signal complex_row_cnt_ocal0 : STD_LOGIC;
  signal \complex_row_cnt_ocal[7]_i_4_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[7]_i_5_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[7]_i_6_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[7]_i_7_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[7]_i_8_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal[7]_i_9_n_0\ : STD_LOGIC;
  signal \complex_row_cnt_ocal_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal complex_sample_cnt_inc0 : STD_LOGIC;
  signal complex_sample_cnt_inc_i_2_n_0 : STD_LOGIC;
  signal complex_sample_cnt_inc_i_3_n_0 : STD_LOGIC;
  signal complex_sample_cnt_inc_r1 : STD_LOGIC;
  signal complex_sample_cnt_inc_r2 : STD_LOGIC;
  signal complex_sample_cnt_inc_reg_n_0 : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_5_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt[3]_i_6_n_0\ : STD_LOGIC;
  signal \complex_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ddr2_pre_flag_r : STD_LOGIC;
  signal ddr2_pre_flag_r_i_1_n_0 : STD_LOGIC;
  signal ddr2_pre_flag_r_i_2_n_0 : STD_LOGIC;
  signal ddr2_pre_flag_r_reg_n_0 : STD_LOGIC;
  signal ddr2_refresh_flag_r : STD_LOGIC;
  signal ddr2_refresh_flag_r_i_1_n_0 : STD_LOGIC;
  signal ddr2_refresh_flag_r_i_2_n_0 : STD_LOGIC;
  signal \^ddr3_lm_done_r\ : STD_LOGIC;
  signal ddr3_lm_done_r_i_1_n_0 : STD_LOGIC;
  signal detect_pi_found_dqs0 : STD_LOGIC;
  signal dqs_asrt_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \dqs_asrt_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_asrt_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \^dqs_found_start_r_reg\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \^en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\ : STD_LOGIC;
  signal \en_cnt_div4.wrlvl_odt_i_1_n_0\ : STD_LOGIC;
  signal \en_cnt_div4.wrlvl_odt_i_2_n_0\ : STD_LOGIC;
  signal enable_wrlvl_cnt : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal enable_wrlvl_cnt0 : STD_LOGIC;
  signal \^first_rdlvl_pat_r\ : STD_LOGIC;
  signal first_rdlvl_pat_r_i_1_n_0 : STD_LOGIC;
  signal \^first_wrcal_pat_r\ : STD_LOGIC;
  signal first_wrcal_pat_r_i_1_n_0 : STD_LOGIC;
  signal first_wrcal_pat_r_i_2_n_0 : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_rnk[0].mr1_r_reg[0]_46\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal init_complete_r1 : STD_LOGIC;
  signal init_complete_r1_timing : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of init_complete_r1_timing : signal is "true";
  signal init_complete_r2 : STD_LOGIC;
  signal init_complete_r_i_1_n_0 : STD_LOGIC;
  signal init_complete_r_reg_n_0 : STD_LOGIC;
  signal init_complete_r_timing : STD_LOGIC;
  attribute RTL_KEEP of init_complete_r_timing : signal is "true";
  signal init_complete_r_timing_i_1_n_0 : STD_LOGIC;
  signal init_next_state193_out : STD_LOGIC;
  signal init_state_r : STD_LOGIC_VECTOR ( 6 to 6 );
  signal init_state_r1 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \init_state_r[0]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_28_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_33_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_35_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_36_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[0]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_28_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_33_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[1]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_28_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_35_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_36_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_37_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[4]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_10_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_11_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_12_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_13_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_14_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_15_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_16_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_17_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_18_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_19_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_20_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_21_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_22_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_23_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_24_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_25_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_26_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_27_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_28_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_29_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_30_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_31_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_32_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_33_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_34_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_35_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_36_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_37_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_38_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_39_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_40_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_41_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_42_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_43_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_44_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_45_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_46_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_47_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_7_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_8_n_0\ : STD_LOGIC;
  signal \init_state_r[5]_i_9_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \init_state_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \init_state_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \^mem_init_done_r\ : STD_LOGIC;
  signal mem_init_done_r_i_1_n_0 : STD_LOGIC;
  signal mem_init_done_r_i_2_n_0 : STD_LOGIC;
  signal mpr_rdlvl_start_i_1_n_0 : STD_LOGIC;
  signal mpr_rdlvl_start_i_2_n_0 : STD_LOGIC;
  signal mpr_rdlvl_start_i_3_n_0 : STD_LOGIC;
  signal \^mpr_rdlvl_start_r_reg\ : STD_LOGIC;
  signal num_reads : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal num_refresh0 : STD_LOGIC;
  signal \num_refresh[3]_i_1_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_4_n_0\ : STD_LOGIC;
  signal \num_refresh[3]_i_5_n_0\ : STD_LOGIC;
  signal \num_refresh_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \ocal_act_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \ocal_act_wait_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \ocal_act_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oclk_wr_cnt0 : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \oclk_wr_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt[3]_i_5_n_0\ : STD_LOGIC;
  signal \oclk_wr_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \odd_cwl.phy_cas_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \odd_cwl.phy_ras_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \odd_cwl.phy_we_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \one_rank.stg1_wr_done_i_1_n_0\ : STD_LOGIC;
  signal \^one_rank.stg1_wr_done_reg_0\ : STD_LOGIC;
  signal p_0_in0_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_94_out : STD_LOGIC;
  signal phy_bank : STD_LOGIC_VECTOR ( 11 downto 9 );
  signal phy_cas_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal phy_cs_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^phy_ctl_wd_i1_reg[24]\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal phy_ras_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^phy_read_calib\ : STD_LOGIC;
  signal phy_reset_n : STD_LOGIC;
  signal phy_we_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal phy_wrdata : STD_LOGIC_VECTOR ( 511 downto 61 );
  signal phy_wrdata_en : STD_LOGIC;
  signal \^phy_write_calib\ : STD_LOGIC;
  signal \^pi_calib_done\ : STD_LOGIC;
  signal pi_calib_done_r : STD_LOGIC;
  signal pi_calib_done_r_i_1_n_0 : STD_LOGIC;
  signal pi_calib_rank_done_r : STD_LOGIC;
  signal \^pi_dqs_found_done_r1\ : STD_LOGIC;
  signal pi_dqs_found_start_i_1_n_0 : STD_LOGIC;
  signal pi_dqs_found_start_i_2_n_0 : STD_LOGIC;
  signal pi_phase_locked_all_r1 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of pi_phase_locked_all_r1 : signal is "true";
  signal pi_phase_locked_all_r2 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r2 : signal is "true";
  signal pi_phase_locked_all_r3 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r3 : signal is "true";
  signal pi_phase_locked_all_r4 : STD_LOGIC;
  attribute async_reg of pi_phase_locked_all_r4 : signal is "true";
  signal \prech_done_dly_r_reg[15]_srl16_n_0\ : STD_LOGIC;
  signal prech_done_pre : STD_LOGIC;
  signal prech_pending_r : STD_LOGIC;
  signal prech_pending_r_i_1_n_0 : STD_LOGIC;
  signal prech_pending_r_i_2_n_0 : STD_LOGIC;
  signal prech_pending_r_i_3_n_0 : STD_LOGIC;
  signal prech_pending_r_i_4_n_0 : STD_LOGIC;
  signal prech_pending_r_i_5_n_0 : STD_LOGIC;
  signal prech_pending_r_i_6_n_0 : STD_LOGIC;
  signal prech_pending_r_i_7_n_0 : STD_LOGIC;
  signal prech_pending_r_i_8_n_0 : STD_LOGIC;
  signal \^prech_pending_r_reg_0\ : STD_LOGIC;
  signal prech_req : STD_LOGIC;
  signal prech_req_posedge_r0 : STD_LOGIC;
  signal prech_req_posedge_r_i_2_n_0 : STD_LOGIC;
  signal prech_req_r : STD_LOGIC;
  signal prech_req_r_i_2_n_0 : STD_LOGIC;
  signal prech_req_r_i_3_n_0 : STD_LOGIC;
  signal pwron_ce_r : STD_LOGIC;
  signal pwron_ce_r_i_2_n_0 : STD_LOGIC;
  signal pwron_ce_r_i_3_n_0 : STD_LOGIC;
  signal rdlvl_last_byte_done_r : STD_LOGIC;
  signal rdlvl_start_dly0_r : STD_LOGIC_VECTOR ( 14 to 14 );
  signal \rdlvl_start_dly0_r_reg[13]_srl14_n_0\ : STD_LOGIC;
  signal rdlvl_start_pre : STD_LOGIC;
  signal rdlvl_start_pre_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_done_r1\ : STD_LOGIC;
  signal rdlvl_stg1_start_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_start_r_reg\ : STD_LOGIC;
  signal read_calib_i_1_n_0 : STD_LOGIC;
  signal reg_ctrl_cnt_r : STD_LOGIC;
  signal \reg_ctrl_cnt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \reg_ctrl_cnt_r_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal reset_rd_addr_r1 : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_11_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_12_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_13_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_14_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_7_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_8_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_0\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_1\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_2\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_3\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_1\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_2\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_3\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \^stg1_wr_done\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[6]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_1_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_2_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_3_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_4_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt[8]_i_5_n_0\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \stg1_wr_rd_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\ : STD_LOGIC;
  signal \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\ : STD_LOGIC;
  signal wr_level_dqs_asrt : STD_LOGIC;
  signal wr_level_dqs_asrt_i_1_n_0 : STD_LOGIC;
  signal wr_level_dqs_asrt_r1 : STD_LOGIC;
  signal \^wr_level_start_r_reg\ : STD_LOGIC;
  signal wr_lvl_start_i_1_n_0 : STD_LOGIC;
  signal wr_victim_inc : STD_LOGIC;
  signal wr_victim_inc0 : STD_LOGIC;
  signal wr_victim_inc_i_2_n_0 : STD_LOGIC;
  signal wrcal_final_chk : STD_LOGIC;
  signal wrcal_final_chk_i_1_n_0 : STD_LOGIC;
  signal wrcal_final_chk_i_2_n_0 : STD_LOGIC;
  signal wrcal_final_chk_i_3_n_0 : STD_LOGIC;
  signal wrcal_final_chk_i_4_n_0 : STD_LOGIC;
  signal wrcal_rd_wait_i_1_n_0 : STD_LOGIC;
  signal wrcal_reads : STD_LOGIC;
  signal wrcal_reads05_out : STD_LOGIC;
  signal \wrcal_reads[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[4]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[5]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[6]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_3_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_5_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_6_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_7_n_0\ : STD_LOGIC;
  signal \wrcal_reads[7]_i_9_n_0\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[0]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[1]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[2]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[3]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[4]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[5]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[6]\ : STD_LOGIC;
  signal \wrcal_reads_reg_n_0_[7]\ : STD_LOGIC;
  signal wrcal_resume_r : STD_LOGIC;
  signal wrcal_start_dly_r : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \wrcal_start_dly_r_reg[4]_srl5_n_0\ : STD_LOGIC;
  signal wrcal_start_i_1_n_0 : STD_LOGIC;
  signal wrcal_start_pre : STD_LOGIC;
  signal \^wrcal_start_reg_0\ : STD_LOGIC;
  signal wrcal_wr_cnt0 : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \wrcal_wr_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \wrcal_wr_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1_n_0\ : STD_LOGIC;
  signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1_n_0\ : STD_LOGIC;
  signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1_n_0\ : STD_LOGIC;
  signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\ : STD_LOGIC;
  signal write_calib_i_1_n_0 : STD_LOGIC;
  signal wrlvl_active : STD_LOGIC;
  signal wrlvl_active_i_1_n_0 : STD_LOGIC;
  signal wrlvl_active_r1 : STD_LOGIC;
  signal wrlvl_done_r : STD_LOGIC;
  signal \^wrlvl_done_r1\ : STD_LOGIC;
  signal \^wrlvl_final_if_rst\ : STD_LOGIC;
  signal wrlvl_final_if_rst_i_1_n_0 : STD_LOGIC;
  signal wrlvl_final_if_rst_i_2_n_0 : STD_LOGIC;
  signal wrlvl_odt : STD_LOGIC;
  signal wrlvl_odt_ctl : STD_LOGIC;
  signal wrlvl_odt_ctl_i_1_n_0 : STD_LOGIC;
  signal wrlvl_odt_ctl_i_2_n_0 : STD_LOGIC;
  signal wrlvl_odt_ctl_i_3_n_0 : STD_LOGIC;
  signal wrlvl_odt_ctl_i_4_n_0 : STD_LOGIC;
  signal wrlvl_rank_done_r1 : STD_LOGIC;
  signal wrlvl_rank_done_r6_reg_srl5_n_0 : STD_LOGIC;
  signal wrlvl_rank_done_r7 : STD_LOGIC;
  signal \NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[1]_i_11\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[1]_i_5\ : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[1]_i_7\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \DDR3_1rank.phy_int_cs_n[1]_i_8\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \back_to_back_reads_4_1.num_reads[2]_i_1\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of burst_addr_r_i_3 : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \calib_cmd[0]_i_1\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of \calib_cmd[1]_i_1\ : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of \calib_cmd[2]_i_2\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \calib_data_offset_0[3]_i_1\ : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \calib_data_offset_1[3]_i_1\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of \calib_data_offset_2[3]_i_1\ : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \calib_odt[0]_i_4\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \calib_seq[0]_i_1\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of \calib_seq[1]_i_1\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of cnt_cmd_done_m7_r_i_2 : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of \cnt_cmd_r[1]_i_1\ : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of \cnt_cmd_r[2]_i_1\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \cnt_cmd_r[3]_i_1\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \cnt_cmd_r[4]_i_1\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of \cnt_cmd_r[6]_i_5\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of cnt_dllk_zqinit_done_r_i_1 : label is "soft_lutpair211";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[1]_i_1\ : label is "soft_lutpair251";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[2]_i_1\ : label is "soft_lutpair251";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[3]_i_1\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[4]_i_1\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[7]_i_2\ : label is "soft_lutpair211";
  attribute SOFT_HLUTNM of cnt_init_af_done_r_i_1 : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of \cnt_init_af_r[1]_i_1\ : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of \cnt_init_mr_r[0]_i_1\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \cnt_init_mr_r[1]_i_2\ : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \cnt_init_mr_r[1]_i_4\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[1]_i_1\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[2]_i_1\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[3]_i_1\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[4]_i_1\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[6]_i_1\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[7]_i_1\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[8]_i_1\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \cnt_pwron_ce_r[9]_i_2\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \cnt_pwron_r[0]_i_1\ : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of \cnt_pwron_r[1]_i_1\ : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of \cnt_pwron_r[2]_i_1\ : label is "soft_lutpair256";
  attribute SOFT_HLUTNM of \cnt_pwron_r[3]_i_1\ : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \cnt_pwron_r[4]_i_1\ : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \cnt_pwron_r[6]_i_2\ : label is "soft_lutpair256";
  attribute SOFT_HLUTNM of \cnt_pwron_r[7]_i_1\ : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of \cnt_pwron_r[8]_i_1\ : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of cnt_txpr_done_r_i_2 : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of \cnt_txpr_r[0]_i_1\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \cnt_txpr_r[1]_i_1\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \cnt_txpr_r[2]_i_1\ : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of \cnt_txpr_r[3]_i_1\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \cnt_txpr_r[4]_i_1\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \cnt_txpr_r[6]_i_1\ : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of \cnt_txpr_r[7]_i_2\ : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of complex_byte_rd_done_i_1 : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \complex_num_reads[1]_i_2\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \complex_num_reads[2]_i_5\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \complex_num_reads[3]_i_6\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \complex_num_reads[3]_i_7\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \complex_num_reads_dec[3]_i_3\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \complex_num_writes[0]_i_2\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \complex_num_writes[0]_i_3\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_10\ : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_7\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \complex_num_writes[2]_i_8\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \complex_num_writes[3]_i_2\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_10\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_14\ : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_16\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_2\ : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_3\ : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_6\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \complex_num_writes[4]_i_7\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \complex_num_writes_dec[2]_i_1\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \complex_num_writes_dec[4]_i_4\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \complex_num_writes_dec[4]_i_5\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of complex_oclkdelay_calib_start_int_i_1 : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of complex_oclkdelay_calib_start_int_i_2 : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of complex_row0_rd_done_i_2 : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[0]_i_1\ : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[1]_i_1\ : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[2]_i_1\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_1\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[4]_i_1\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[7]_i_3\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[7]_i_4\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[7]_i_5\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[7]_i_6\ : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \complex_row_cnt_ocal[7]_i_9\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of complex_sample_cnt_inc_i_3 : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \complex_wait_cnt[1]_i_1\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \complex_wait_cnt[2]_i_1\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \complex_wait_cnt[3]_i_2\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \complex_wait_cnt[3]_i_4\ : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \complex_wait_cnt[3]_i_6\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \data_offset_1_i1[0]_i_1\ : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of \data_offset_1_i1[1]_i_1\ : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of \data_offset_1_i1[2]_i_1\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of \data_offset_1_i1[3]_i_1\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \data_offset_1_i1[4]_i_1\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \data_offset_1_i1[5]_i_1\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \data_offset_2_i1[0]_i_1\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \data_offset_2_i1[1]_i_1\ : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \data_offset_2_i1[2]_i_1\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \data_offset_2_i1[3]_i_1\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \data_offset_2_i1[4]_i_1\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \data_offset_2_i1[5]_i_1\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of ddr2_pre_flag_r_i_1 : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of ddr2_refresh_flag_r_i_2 : label is "soft_lutpair165";
  attribute SOFT_HLUTNM of ddr3_lm_done_r_i_1 : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \en_cnt_div4.enable_wrlvl_cnt[3]_i_3\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \en_cnt_div4.wrlvl_odt_i_2\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of first_wrcal_pat_r_i_2 : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6\ : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_10\ : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5\ : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8\ : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9\ : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9\ : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6\ : label is "soft_lutpair157";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1\ : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of \gen_reset_obuf.u_reset_obuf_i_1\ : label is "soft_lutpair257";
  attribute KEEP : string;
  attribute KEEP of init_complete_r1_timing_reg : label is "yes";
  attribute KEEP of init_complete_r_timing_reg : label is "yes";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_18\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_19\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_21\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_25\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_3\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_30\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_33\ : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_34\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_35\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \init_state_r[0]_i_36\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_16\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_2\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_21\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_27\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_30\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_32\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \init_state_r[1]_i_34\ : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_12\ : label is "soft_lutpair165";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_19\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_22\ : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_27\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_29\ : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_30\ : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_32\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_4\ : label is "soft_lutpair157";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_5\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_6\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_7\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_13\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_15\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_18\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_19\ : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_2\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_25\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_7\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_14\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_17\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_18\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_2\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_22\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_23\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_24\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_29\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_30\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_34\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_35\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_6\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_12\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_2\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_20\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_23\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_25\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_26\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_27\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_28\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_29\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_3\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_31\ : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_32\ : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_33\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_34\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_35\ : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_36\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_37\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_38\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_42\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_43\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_47\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \init_state_r[5]_i_7\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \init_state_r[6]_i_2\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of mpr_rdlvl_start_i_2 : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of mpr_rdlvl_start_i_3 : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of \num_refresh[1]_i_1\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of \num_refresh[2]_i_1\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of \num_refresh[3]_i_3\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \num_refresh[3]_i_4\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[0]_i_1\ : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[1]_i_1\ : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[2]_i_1\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_2\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[0]_i_1\ : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[1]_i_1\ : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[3]_i_3\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \oclk_wr_cnt[3]_i_5\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \odd_cwl.phy_we_n[1]_i_1\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of out_fifo_i_50 : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[0]_i_1\ : label is "soft_lutpair257";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[17]_i_1\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[18]_i_1\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[19]_i_1\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[1]_i_1\ : label is "soft_lutpair255";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[20]_i_1\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[21]_i_1\ : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[22]_i_1\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \phy_ctl_wd_i1[2]_i_1\ : label is "soft_lutpair255";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r1_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r1_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r2_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r2_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r3_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r3_reg : label is "yes";
  attribute ASYNC_REG_boolean of pi_phase_locked_all_r4_reg : label is std.standard.true;
  attribute KEEP of pi_phase_locked_all_r4_reg : label is "yes";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 ";
  attribute SOFT_HLUTNM of \prech_done_dly_r_reg[15]_srl16_i_1\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of prech_pending_r_i_8 : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of prech_req_r_i_2 : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of prech_req_r_i_3 : label is "soft_lutpair183";
  attribute srl_bus_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg ";
  attribute srl_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 ";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[0]_i_1\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[1]_i_1\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[2]_i_1\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[3]_i_3\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[3]_i_4\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of reset_if_i_1 : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[0]_i_1\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[1]_i_1\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[2]_i_1\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[3]_i_1\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[6]_i_1\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[7]_i_5\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[7]_i_7\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[0]_i_1\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[2]_i_1\ : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[4]_i_4\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[5]_i_2\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[6]_i_1\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[6]_i_2\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[7]_i_1\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_2\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_4\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_1\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row1_wr_done_i_1\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of wr_ptr0_i_1 : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \wr_ptr[3]_i_3\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of wr_victim_inc_i_1 : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \wrcal_reads[1]_i_1\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \wrcal_reads[2]_i_1\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \wrcal_reads[3]_i_1\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \wrcal_reads[5]_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \wrcal_reads[6]_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_6\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \wrcal_reads[7]_i_7\ : label is "soft_lutpair136";
  attribute srl_bus_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg ";
  attribute srl_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 ";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[1]_i_1\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \wrcal_wr_cnt[3]_i_3\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1\ : label is "soft_lutpair201";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]\ : label is "wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]";
  attribute ORIG_CELL_NAME of \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep\ : label is "wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]";
  attribute srl_name of wrlvl_rank_done_r6_reg_srl5 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 ";
begin
  \calib_cke_reg[0]_0\ <= \^calib_cke_reg[0]_0\;
  \complex_row1_rd_cnt_reg[1]_0\ <= \^complex_row1_rd_cnt_reg[1]_0\;
  ddr3_lm_done_r <= \^ddr3_lm_done_r\;
  dqs_found_start_r_reg <= \^dqs_found_start_r_reg\;
  \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\ <= \^en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\;
  first_rdlvl_pat_r <= \^first_rdlvl_pat_r\;
  first_wrcal_pat_r <= \^first_wrcal_pat_r\;
  mem_init_done_r <= \^mem_init_done_r\;
  mpr_rdlvl_start_r_reg <= \^mpr_rdlvl_start_r_reg\;
  \one_rank.stg1_wr_done_reg_0\ <= \^one_rank.stg1_wr_done_reg_0\;
  \out\ <= init_complete_r1_timing;
  \phy_ctl_wd_i1_reg[24]\(10 downto 0) <= \^phy_ctl_wd_i1_reg[24]\(10 downto 0);
  phy_read_calib <= \^phy_read_calib\;
  phy_write_calib <= \^phy_write_calib\;
  pi_calib_done <= \^pi_calib_done\;
  pi_dqs_found_done_r1 <= \^pi_dqs_found_done_r1\;
  prech_pending_r_reg_0 <= \^prech_pending_r_reg_0\;
  rdlvl_stg1_done_r1 <= \^rdlvl_stg1_done_r1\;
  rdlvl_stg1_start_r_reg <= \^rdlvl_stg1_start_r_reg\;
  stg1_wr_done <= \^stg1_wr_done\;
  wr_level_start_r_reg <= \^wr_level_start_r_reg\;
  wrcal_start_reg_0 <= \^wrcal_start_reg_0\;
  wrlvl_done_r1 <= \^wrlvl_done_r1\;
  wrlvl_final_if_rst <= \^wrlvl_final_if_rst\;
\DDR3_1rank.phy_int_cs_n[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001010100"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\,
      I1 => \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\,
      I2 => \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\,
      I3 => \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\,
      I4 => \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\,
      I5 => cnt_dllk_zqinit_r,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABBAAAAAAAAAAAAA"
    )
        port map (
      I0 => cnt_init_mr_done_r_i_2_n_0,
      I1 => mpr_rdlvl_start_i_3_n_0,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_11_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00AAE00A"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0\,
      I1 => \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000020001"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r[4]_i_14_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAABA"
    )
        port map (
      I0 => wrlvl_odt_ctl_i_3_n_0,
      I1 => \oclk_wr_cnt[3]_i_5_n_0\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \cnt_init_mr_r[1]_i_4_n_0\,
      I5 => \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => phy_wrdata_en,
      I1 => \calib_cmd[2]_i_3_n_0\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \cnt_init_mr_r[1]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      O => \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0\
    );
\DDR3_1rank.phy_int_cs_n[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000004000000004"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_11_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0\
    );
\DDR3_1rank.phy_int_cs_n_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0\,
      Q => phy_cs_n(1),
      S => \rstdiv0_sync_r1_reg_rep__4\
    );
\FSM_onehot_cal1_state_r[32]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^mpr_rdlvl_start_r_reg\,
      I1 => mpr_rdlvl_start_r,
      O => cal1_state_r1536_out
    );
\back_to_back_reads_4_1.num_reads[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000FE0000"
    )
        port map (
      I0 => pi_dqs_found_start_i_2_n_0,
      I1 => num_reads(1),
      I2 => num_reads(2),
      I3 => num_reads(0),
      I4 => prech_req_posedge_r_i_2_n_0,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\
    );
\back_to_back_reads_4_1.num_reads[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CC320000"
    )
        port map (
      I0 => pi_dqs_found_start_i_2_n_0,
      I1 => num_reads(1),
      I2 => num_reads(2),
      I3 => num_reads(0),
      I4 => prech_req_posedge_r_i_2_n_0,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\
    );
\back_to_back_reads_4_1.num_reads[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44004000"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => prech_req_posedge_r_i_2_n_0,
      I2 => num_reads(0),
      I3 => num_reads(2),
      I4 => num_reads(1),
      O => \back_to_back_reads_4_1.num_reads[2]_i_1_n_0\
    );
\back_to_back_reads_4_1.num_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\,
      Q => num_reads(0),
      R => '0'
    );
\back_to_back_reads_4_1.num_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\,
      Q => num_reads(1),
      R => '0'
    );
\back_to_back_reads_4_1.num_reads_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \back_to_back_reads_4_1.num_reads[2]_i_1_n_0\,
      Q => num_reads(2),
      R => '0'
    );
burst_addr_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AB"
    )
        port map (
      I0 => burst_addr_r_i_2_n_0,
      I1 => burst_addr_r_reg_n_0,
      I2 => \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\,
      I3 => wrcal_done_reg,
      I4 => \rstdiv0_sync_r1_reg_rep__23\,
      O => burst_addr_r_i_1_n_0
    );
burst_addr_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04F4040F040404FF"
    )
        port map (
      I0 => burst_addr_r_i_3_n_0,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => mpr_rdlvl_start_i_3_n_0,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => burst_addr_r_i_2_n_0
    );
burst_addr_r_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      O => burst_addr_r_i_3_n_0
    );
burst_addr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => burst_addr_r_i_1_n_0,
      Q => burst_addr_r_reg_n_0,
      R => '0'
    );
\calib_cke_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^calib_cke_reg[0]_0\,
      Q => calib_cke(3),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\calib_cmd[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      O => \calib_cmd[0]_i_1_n_0\
    );
\calib_cmd[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \calib_cmd[2]_i_3_n_0\,
      I1 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_cmd[1]_i_1_n_0\
    );
\calib_cmd[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      O => \calib_cmd[2]_i_1_n_0\
    );
\calib_cmd[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wr_level_dqs_asrt,
      I1 => phy_wrdata_en,
      O => \calib_cmd[2]_i_2_n_0\
    );
\calib_cmd[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFEFEFF"
    )
        port map (
      I0 => \calib_cmd[2]_i_4_n_0\,
      I1 => \complex_num_reads_dec[3]_i_4_n_0\,
      I2 => pi_dqs_found_start_i_2_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \calib_cmd[2]_i_5_n_0\,
      I5 => \calib_cmd[2]_i_6_n_0\,
      O => \calib_cmd[2]_i_3_n_0\
    );
\calib_cmd[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAAAAAAAAAAAAAA"
    )
        port map (
      I0 => wrcal_start_pre,
      I1 => \init_state_r[5]_i_32_n_0\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r[0]_i_3_n_0\,
      O => \calib_cmd[2]_i_4_n_0\
    );
\calib_cmd[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \calib_cmd[2]_i_5_n_0\
    );
\calib_cmd[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAEAAAAAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \wrcal_reads[7]_i_5_n_0\,
      I5 => prech_req_r_i_2_n_0,
      O => \calib_cmd[2]_i_6_n_0\
    );
\calib_cmd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_cmd[0]_i_1_n_0\,
      Q => calib_cmd(0),
      R => '0'
    );
\calib_cmd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_cmd[1]_i_1_n_0\,
      Q => calib_cmd(1),
      R => '0'
    );
\calib_cmd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_cmd[2]_i_1_n_0\,
      Q => calib_cmd(2),
      R => '0'
    );
calib_ctl_wren_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_110_in,
      Q => calib_cmd_wren,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\calib_data_offset_0[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      I2 => \calib_data_offset_0[3]_i_2_n_0\,
      O => \calib_data_offset_0[3]_i_1_n_0\
    );
\calib_data_offset_0[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]\(0),
      I3 => init_dqsfound_done_r2,
      I4 => \rd_byte_data_offset_reg[0][3]\(0),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_0[3]_i_2_n_0\
    );
\calib_data_offset_0[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \calib_cmd[2]_i_3_n_0\,
      I1 => \calib_cmd[2]_i_2_n_0\,
      I2 => \^pi_calib_done\,
      O => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_4,
      Q => calib_data_offset_0(0),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_3,
      Q => calib_data_offset_0(1),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_2,
      Q => calib_data_offset_0(2),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_0[3]_i_1_n_0\,
      Q => calib_data_offset_0(3),
      R => '0'
    );
\calib_data_offset_0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_1,
      Q => calib_data_offset_0(4),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_0,
      Q => calib_data_offset_0(5),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      I2 => \calib_data_offset_1[3]_i_2_n_0\,
      O => \calib_data_offset_1[3]_i_1_n_0\
    );
\calib_data_offset_1[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]\(0),
      I3 => init_dqsfound_done_r2,
      I4 => \rd_byte_data_offset_reg[0][9]\(0),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_1[3]_i_2_n_0\
    );
\calib_data_offset_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_9,
      Q => calib_data_offset_1(0),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_8,
      Q => calib_data_offset_1(1),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_7,
      Q => calib_data_offset_1(2),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_1[3]_i_1_n_0\,
      Q => calib_data_offset_1(3),
      R => '0'
    );
\calib_data_offset_1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_6,
      Q => calib_data_offset_1(4),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_5,
      Q => calib_data_offset_1(5),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \calib_cmd[2]_i_2_n_0\,
      I1 => \calib_cmd[2]_i_3_n_0\,
      I2 => \calib_data_offset_2[3]_i_2_n_0\,
      O => \calib_data_offset_2[3]_i_1_n_0\
    );
\calib_data_offset_2[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A2A080FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \^pi_dqs_found_done_r1\,
      I2 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]\(0),
      I3 => init_dqsfound_done_r2,
      I4 => \rd_byte_data_offset_reg[0][15]\(0),
      I5 => \calib_cmd[2]_i_2_n_0\,
      O => \calib_data_offset_2[3]_i_2_n_0\
    );
\calib_data_offset_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_14,
      Q => calib_data_offset_2(0),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_13,
      Q => calib_data_offset_2(1),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_12,
      Q => calib_data_offset_2(2),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_data_offset_2[3]_i_1_n_0\,
      Q => calib_data_offset_2(3),
      R => '0'
    );
\calib_data_offset_2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_11,
      Q => calib_data_offset_2(4),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_data_offset_2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done_r1_reg_10,
      Q => calib_data_offset_2(5),
      R => \calib_data_offset_0[5]_i_1_n_0\
    );
\calib_odt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FE00"
    )
        port map (
      I0 => \calib_odt[0]_i_2_n_0\,
      I1 => \calib_odt[0]_i_3_n_0\,
      I2 => phy_wrdata_en,
      I3 => \gen_rnk[0].mr1_r_reg[0]_46\(1),
      I4 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \calib_odt[0]_i_1_n_0\
    );
\calib_odt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF04"
    )
        port map (
      I0 => prech_req_r_i_3_n_0,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \wrcal_reads[7]_i_6_n_0\,
      I3 => complex_odt_ext,
      I4 => complex_ocal_odt_ext,
      I5 => \^stg1_wr_done\,
      O => \calib_odt[0]_i_2_n_0\
    );
\calib_odt[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F0F0F0FFF0F0"
    )
        port map (
      I0 => \calib_odt[0]_i_4_n_0\,
      I1 => wrlvl_odt,
      I2 => \complex_address[9]_i_3_n_0\,
      I3 => first_wrcal_pat_r_i_2_n_0,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \calib_odt[0]_i_3_n_0\
    );
\calib_odt[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      O => \calib_odt[0]_i_4_n_0\
    );
\calib_odt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_odt[0]_i_1_n_0\,
      Q => calib_odt(0),
      R => '0'
    );
\calib_seq[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => phy_mc_go,
      I1 => \^calib_cke_reg[0]_0\,
      I2 => \^phy_ctl_wd_i1_reg[24]\(9),
      O => \calib_seq[0]_i_1_n_0\
    );
\calib_seq[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^phy_ctl_wd_i1_reg[24]\(9),
      I1 => phy_mc_go,
      I2 => \^calib_cke_reg[0]_0\,
      I3 => \^phy_ctl_wd_i1_reg[24]\(10),
      O => \calib_seq[1]_i_1_n_0\
    );
\calib_seq_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq[0]_i_1_n_0\,
      Q => \^phy_ctl_wd_i1_reg[24]\(9),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\calib_seq_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq[1]_i_1_n_0\,
      Q => \^phy_ctl_wd_i1_reg[24]\(10),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
calib_wrdata_en_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFB"
    )
        port map (
      I0 => \wrcal_wr_cnt[3]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I2 => p_0_in0_in,
      I3 => \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\,
      O => phy_wrdata_en
    );
calib_wrdata_en_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_wrdata_en,
      Q => calib_wrdata_en,
      R => '0'
    );
cnt_cmd_done_m7_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[6]\,
      I1 => \cnt_cmd_r_reg_n_0_[5]\,
      I2 => \cnt_cmd_r_reg_n_0_[4]\,
      I3 => \cnt_cmd_r_reg_n_0_[3]\,
      I4 => cnt_cmd_done_m7_r_i_2_n_0,
      I5 => \cnt_cmd_r_reg_n_0_[2]\,
      O => cnt_cmd_done_m7_r_i_1_n_0
    );
cnt_cmd_done_m7_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[0]\,
      I1 => \cnt_cmd_r_reg_n_0_[1]\,
      O => cnt_cmd_done_m7_r_i_2_n_0
    );
cnt_cmd_done_m7_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_cmd_done_m7_r_i_1_n_0,
      Q => cnt_cmd_done_m7_r,
      R => '0'
    );
cnt_cmd_done_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \cnt_cmd_r[6]_i_5_n_0\,
      I1 => \cnt_cmd_r_reg_n_0_[5]\,
      I2 => \cnt_cmd_r_reg_n_0_[6]\,
      O => cnt_cmd_done_r_i_1_n_0
    );
cnt_cmd_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_cmd_done_r_i_1_n_0,
      Q => cnt_cmd_done_r,
      R => '0'
    );
\cnt_cmd_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[0]\,
      O => \cnt_cmd_r[0]_i_1_n_0\
    );
\cnt_cmd_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[1]\,
      I1 => \cnt_cmd_r_reg_n_0_[0]\,
      O => \cnt_cmd_r[1]_i_1_n_0\
    );
\cnt_cmd_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[2]\,
      I1 => \cnt_cmd_r_reg_n_0_[1]\,
      I2 => \cnt_cmd_r_reg_n_0_[0]\,
      O => \cnt_cmd_r[2]_i_1_n_0\
    );
\cnt_cmd_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[3]\,
      I1 => \cnt_cmd_r_reg_n_0_[2]\,
      I2 => \cnt_cmd_r_reg_n_0_[0]\,
      I3 => \cnt_cmd_r_reg_n_0_[1]\,
      O => \cnt_cmd_r[3]_i_1_n_0\
    );
\cnt_cmd_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[4]\,
      I1 => \cnt_cmd_r_reg_n_0_[3]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      I3 => \cnt_cmd_r_reg_n_0_[0]\,
      I4 => \cnt_cmd_r_reg_n_0_[2]\,
      O => \cnt_cmd_r[4]_i_1_n_0\
    );
\cnt_cmd_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[5]\,
      I1 => \cnt_cmd_r_reg_n_0_[4]\,
      I2 => \cnt_cmd_r_reg_n_0_[3]\,
      I3 => \cnt_cmd_r_reg_n_0_[1]\,
      I4 => \cnt_cmd_r_reg_n_0_[0]\,
      I5 => \cnt_cmd_r_reg_n_0_[2]\,
      O => \cnt_cmd_r[5]_i_1_n_0\
    );
\cnt_cmd_r[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \cnt_cmd_r[6]_i_3_n_0\,
      I1 => \cnt_cmd_r[6]_i_4_n_0\,
      I2 => init_state_r(6),
      O => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[6]\,
      I1 => \cnt_cmd_r_reg_n_0_[5]\,
      I2 => \cnt_cmd_r[6]_i_5_n_0\,
      O => \cnt_cmd_r[6]_i_2_n_0\
    );
\cnt_cmd_r[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5444554111115111"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \cnt_cmd_r[6]_i_3_n_0\
    );
\cnt_cmd_r[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8A8A8AA20A2AA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \cnt_cmd_r[6]_i_4_n_0\
    );
\cnt_cmd_r[6]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[2]\,
      I1 => \cnt_cmd_r_reg_n_0_[0]\,
      I2 => \cnt_cmd_r_reg_n_0_[1]\,
      I3 => \cnt_cmd_r_reg_n_0_[3]\,
      I4 => \cnt_cmd_r_reg_n_0_[4]\,
      O => \cnt_cmd_r[6]_i_5_n_0\
    );
\cnt_cmd_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[0]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[0]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[1]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[1]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[2]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[2]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[3]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[3]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[4]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[4]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[5]_i_1_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[5]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
\cnt_cmd_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_cmd_r[6]_i_2_n_0\,
      Q => \cnt_cmd_r_reg_n_0_[6]\,
      R => \cnt_cmd_r[6]_i_1_n_0\
    );
cnt_dllk_zqinit_done_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => cnt_dllk_zqinit_done_r,
      I1 => \cnt_dllk_zqinit_r_reg__0\(6),
      I2 => mem_init_done_r_i_2_n_0,
      I3 => \cnt_dllk_zqinit_r_reg__0\(7),
      O => cnt_dllk_zqinit_done_r_i_1_n_0
    );
cnt_dllk_zqinit_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_dllk_zqinit_done_r_i_1_n_0,
      Q => cnt_dllk_zqinit_done_r,
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(0),
      O => \p_0_in__4\(0)
    );
\cnt_dllk_zqinit_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(1),
      I1 => \cnt_dllk_zqinit_r_reg__0\(0),
      O => \p_0_in__4\(1)
    );
\cnt_dllk_zqinit_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(2),
      I1 => \cnt_dllk_zqinit_r_reg__0\(0),
      I2 => \cnt_dllk_zqinit_r_reg__0\(1),
      O => \p_0_in__4\(2)
    );
\cnt_dllk_zqinit_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(3),
      I1 => \cnt_dllk_zqinit_r_reg__0\(1),
      I2 => \cnt_dllk_zqinit_r_reg__0\(0),
      I3 => \cnt_dllk_zqinit_r_reg__0\(2),
      O => \p_0_in__4\(3)
    );
\cnt_dllk_zqinit_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(4),
      I1 => \cnt_dllk_zqinit_r_reg__0\(2),
      I2 => \cnt_dllk_zqinit_r_reg__0\(0),
      I3 => \cnt_dllk_zqinit_r_reg__0\(1),
      I4 => \cnt_dllk_zqinit_r_reg__0\(3),
      O => \p_0_in__4\(4)
    );
\cnt_dllk_zqinit_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(5),
      I1 => \cnt_dllk_zqinit_r_reg__0\(3),
      I2 => \cnt_dllk_zqinit_r_reg__0\(1),
      I3 => \cnt_dllk_zqinit_r_reg__0\(0),
      I4 => \cnt_dllk_zqinit_r_reg__0\(2),
      I5 => \cnt_dllk_zqinit_r_reg__0\(4),
      O => \p_0_in__4\(5)
    );
\cnt_dllk_zqinit_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(6),
      I1 => mem_init_done_r_i_2_n_0,
      O => \p_0_in__4\(6)
    );
\cnt_dllk_zqinit_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(7),
      I1 => mem_init_done_r_i_2_n_0,
      I2 => \cnt_dllk_zqinit_r_reg__0\(6),
      O => \p_0_in__4\(7)
    );
\cnt_dllk_zqinit_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(0),
      Q => \cnt_dllk_zqinit_r_reg__0\(0),
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(1),
      Q => \cnt_dllk_zqinit_r_reg__0\(1),
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(2),
      Q => \cnt_dllk_zqinit_r_reg__0\(2),
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(3),
      Q => \cnt_dllk_zqinit_r_reg__0\(3),
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(4),
      Q => \cnt_dllk_zqinit_r_reg__0\(4),
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(5),
      Q => \cnt_dllk_zqinit_r_reg__0\(5),
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(6),
      Q => \cnt_dllk_zqinit_r_reg__0\(6),
      R => cnt_dllk_zqinit_r
    );
\cnt_dllk_zqinit_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__4\(7),
      Q => \cnt_dllk_zqinit_r_reg__0\(7),
      R => cnt_dllk_zqinit_r
    );
cnt_init_af_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E222"
    )
        port map (
      I0 => cnt_init_af_done_r,
      I1 => cnt_init_mr_r1,
      I2 => cnt_init_af_r(1),
      I3 => cnt_init_af_r(0),
      I4 => ddr2_pre_flag_r,
      O => cnt_init_af_done_r_i_1_n_0
    );
cnt_init_af_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_init_af_done_r_i_1_n_0,
      Q => cnt_init_af_done_r,
      R => '0'
    );
\cnt_init_af_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => cnt_init_af_r(0),
      I1 => cnt_init_mr_r1,
      I2 => ddr2_pre_flag_r,
      O => \cnt_init_af_r[0]_i_1_n_0\
    );
\cnt_init_af_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => cnt_init_af_r(1),
      I1 => cnt_init_mr_r1,
      I2 => cnt_init_af_r(0),
      I3 => ddr2_pre_flag_r,
      O => \cnt_init_af_r[1]_i_1_n_0\
    );
\cnt_init_af_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_af_r[0]_i_1_n_0\,
      Q => cnt_init_af_r(0),
      R => '0'
    );
\cnt_init_af_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_af_r[1]_i_1_n_0\,
      Q => cnt_init_af_r(1),
      R => '0'
    );
cnt_init_mr_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000E222"
    )
        port map (
      I0 => cnt_init_mr_done_r,
      I1 => cnt_init_mr_done_r_i_2_n_0,
      I2 => cnt_init_mr_r(0),
      I3 => cnt_init_mr_r(1),
      I4 => ddr2_pre_flag_r,
      I5 => cnt_init_mr_r1,
      O => cnt_init_mr_done_r_i_1_n_0
    );
cnt_init_mr_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => prech_req_r_i_2_n_0,
      O => cnt_init_mr_done_r_i_2_n_0
    );
cnt_init_mr_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_init_mr_done_r_i_1_n_0,
      Q => cnt_init_mr_done_r,
      R => '0'
    );
\cnt_init_mr_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000A6A2"
    )
        port map (
      I0 => cnt_init_mr_r(0),
      I1 => \cnt_init_mr_r[1]_i_2_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => cnt_init_mr_r1,
      O => \cnt_init_mr_r[0]_i_1_n_0\
    );
\cnt_init_mr_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA6AAA0A"
    )
        port map (
      I0 => cnt_init_mr_r(1),
      I1 => cnt_init_mr_r(0),
      I2 => \cnt_init_mr_r[1]_i_2_n_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => cnt_init_mr_r1,
      O => \cnt_init_mr_r[1]_i_1_n_0\
    );
\cnt_init_mr_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      O => \cnt_init_mr_r[1]_i_2_n_0\
    );
\cnt_init_mr_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r[0]_i_3_n_0\,
      I3 => init_state_r(6),
      I4 => \cnt_init_mr_r[1]_i_4_n_0\,
      I5 => \^mem_init_done_r\,
      O => cnt_init_mr_r1
    );
\cnt_init_mr_r[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \cnt_init_mr_r[1]_i_4_n_0\
    );
\cnt_init_mr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_mr_r[0]_i_1_n_0\,
      Q => cnt_init_mr_r(0),
      R => '0'
    );
\cnt_init_mr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cnt_init_mr_r[1]_i_1_n_0\,
      Q => cnt_init_mr_r(1),
      R => '0'
    );
\cnt_pwron_ce_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(0),
      O => \p_0_in__0\(0)
    );
\cnt_pwron_ce_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(1),
      I1 => \cnt_pwron_ce_r_reg__0\(0),
      O => \p_0_in__0\(1)
    );
\cnt_pwron_ce_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(2),
      I1 => \cnt_pwron_ce_r_reg__0\(0),
      I2 => \cnt_pwron_ce_r_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\cnt_pwron_ce_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(3),
      I1 => \cnt_pwron_ce_r_reg__0\(1),
      I2 => \cnt_pwron_ce_r_reg__0\(0),
      I3 => \cnt_pwron_ce_r_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\cnt_pwron_ce_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(4),
      I1 => \cnt_pwron_ce_r_reg__0\(2),
      I2 => \cnt_pwron_ce_r_reg__0\(0),
      I3 => \cnt_pwron_ce_r_reg__0\(1),
      I4 => \cnt_pwron_ce_r_reg__0\(3),
      O => \p_0_in__0\(4)
    );
\cnt_pwron_ce_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(5),
      I1 => \cnt_pwron_ce_r_reg__0\(3),
      I2 => \cnt_pwron_ce_r_reg__0\(1),
      I3 => \cnt_pwron_ce_r_reg__0\(0),
      I4 => \cnt_pwron_ce_r_reg__0\(2),
      I5 => \cnt_pwron_ce_r_reg__0\(4),
      O => \p_0_in__0\(5)
    );
\cnt_pwron_ce_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(6),
      I1 => pwron_ce_r_i_3_n_0,
      O => \p_0_in__0\(6)
    );
\cnt_pwron_ce_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(7),
      I1 => pwron_ce_r_i_3_n_0,
      I2 => \cnt_pwron_ce_r_reg__0\(6),
      O => \p_0_in__0\(7)
    );
\cnt_pwron_ce_r[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(8),
      I1 => \cnt_pwron_ce_r_reg__0\(6),
      I2 => pwron_ce_r_i_3_n_0,
      I3 => \cnt_pwron_ce_r_reg__0\(7),
      O => \p_0_in__0\(8)
    );
\cnt_pwron_ce_r[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(9),
      I1 => \cnt_pwron_ce_r_reg__0\(7),
      I2 => pwron_ce_r_i_3_n_0,
      I3 => \cnt_pwron_ce_r_reg__0\(6),
      I4 => \cnt_pwron_ce_r_reg__0\(8),
      O => \p_0_in__0\(9)
    );
\cnt_pwron_ce_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \cnt_pwron_ce_r_reg__0\(0),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \cnt_pwron_ce_r_reg__0\(1),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \cnt_pwron_ce_r_reg__0\(2),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \cnt_pwron_ce_r_reg__0\(3),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(4),
      Q => \cnt_pwron_ce_r_reg__0\(4),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(5),
      Q => \cnt_pwron_ce_r_reg__0\(5),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(6),
      Q => \cnt_pwron_ce_r_reg__0\(6),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(7),
      Q => \cnt_pwron_ce_r_reg__0\(7),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(8),
      Q => \cnt_pwron_ce_r_reg__0\(8),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_ce_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(9),
      Q => \cnt_pwron_ce_r_reg__0\(9),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
cnt_pwron_cke_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA00"
    )
        port map (
      I0 => \^calib_cke_reg[0]_0\,
      I1 => cnt_pwron_cke_done_r_i_2_n_0,
      I2 => cnt_pwron_cke_done_r_i_3_n_0,
      I3 => phy_mc_go,
      I4 => \rstdiv0_sync_r1_reg_rep__22\,
      O => cnt_pwron_cke_done_r_i_1_n_0
    );
cnt_pwron_cke_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(4),
      I1 => \cnt_pwron_r_reg__0\(2),
      I2 => \cnt_pwron_r_reg__0\(3),
      I3 => \cnt_pwron_r_reg__0\(5),
      I4 => \cnt_pwron_r_reg__0\(1),
      I5 => \cnt_pwron_r_reg__0\(0),
      O => cnt_pwron_cke_done_r_i_2_n_0
    );
cnt_pwron_cke_done_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(6),
      I1 => \cnt_pwron_r_reg__0\(7),
      I2 => \cnt_pwron_r_reg__0\(8),
      O => cnt_pwron_cke_done_r_i_3_n_0
    );
cnt_pwron_cke_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_pwron_cke_done_r_i_1_n_0,
      Q => \^calib_cke_reg[0]_0\,
      R => '0'
    );
\cnt_pwron_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(0),
      O => \p_0_in__1\(0)
    );
\cnt_pwron_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(1),
      I1 => \cnt_pwron_r_reg__0\(0),
      O => \p_0_in__1\(1)
    );
\cnt_pwron_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(2),
      I1 => \cnt_pwron_r_reg__0\(0),
      I2 => \cnt_pwron_r_reg__0\(1),
      O => \p_0_in__1\(2)
    );
\cnt_pwron_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(3),
      I1 => \cnt_pwron_r_reg__0\(1),
      I2 => \cnt_pwron_r_reg__0\(0),
      I3 => \cnt_pwron_r_reg__0\(2),
      O => \p_0_in__1\(3)
    );
\cnt_pwron_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(4),
      I1 => \cnt_pwron_r_reg__0\(2),
      I2 => \cnt_pwron_r_reg__0\(0),
      I3 => \cnt_pwron_r_reg__0\(1),
      I4 => \cnt_pwron_r_reg__0\(3),
      O => \p_0_in__1\(4)
    );
\cnt_pwron_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(5),
      I1 => \cnt_pwron_r_reg__0\(3),
      I2 => \cnt_pwron_r_reg__0\(1),
      I3 => \cnt_pwron_r_reg__0\(0),
      I4 => \cnt_pwron_r_reg__0\(2),
      I5 => \cnt_pwron_r_reg__0\(4),
      O => \p_0_in__1\(5)
    );
\cnt_pwron_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(6),
      I1 => \cnt_pwron_r_reg__0\(4),
      I2 => \cnt_pwron_r_reg__0\(2),
      I3 => \cnt_pwron_r[6]_i_2_n_0\,
      I4 => \cnt_pwron_r_reg__0\(3),
      I5 => \cnt_pwron_r_reg__0\(5),
      O => \p_0_in__1\(6)
    );
\cnt_pwron_r[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(1),
      I1 => \cnt_pwron_r_reg__0\(0),
      O => \cnt_pwron_r[6]_i_2_n_0\
    );
\cnt_pwron_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(7),
      I1 => \cnt_pwron_r[8]_i_2_n_0\,
      I2 => \cnt_pwron_r_reg__0\(6),
      O => \p_0_in__1\(7)
    );
\cnt_pwron_r[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(8),
      I1 => \cnt_pwron_r_reg__0\(6),
      I2 => \cnt_pwron_r[8]_i_2_n_0\,
      I3 => \cnt_pwron_r_reg__0\(7),
      O => \p_0_in__1\(8)
    );
\cnt_pwron_r[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(5),
      I1 => \cnt_pwron_r_reg__0\(3),
      I2 => \cnt_pwron_r_reg__0\(1),
      I3 => \cnt_pwron_r_reg__0\(0),
      I4 => \cnt_pwron_r_reg__0\(2),
      I5 => \cnt_pwron_r_reg__0\(4),
      O => \cnt_pwron_r[8]_i_2_n_0\
    );
\cnt_pwron_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(0),
      Q => \cnt_pwron_r_reg__0\(0),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(1),
      Q => \cnt_pwron_r_reg__0\(1),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(2),
      Q => \cnt_pwron_r_reg__0\(2),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(3),
      Q => \cnt_pwron_r_reg__0\(3),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(4),
      Q => \cnt_pwron_r_reg__0\(4),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(5),
      Q => \cnt_pwron_r_reg__0\(5),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(6),
      Q => \cnt_pwron_r_reg__0\(6),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(7),
      Q => \cnt_pwron_r_reg__0\(7),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
\cnt_pwron_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pwron_ce_r,
      D => \p_0_in__1\(8),
      Q => \cnt_pwron_r_reg__0\(8),
      R => \rstdiv0_sync_r1_reg_rep__18\(0)
    );
cnt_pwron_reset_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F200"
    )
        port map (
      I0 => cnt_pwron_cke_done_r_i_3_n_0,
      I1 => cnt_pwron_reset_done_r_i_2_n_0,
      I2 => cnt_pwron_reset_done_r,
      I3 => phy_mc_go,
      I4 => \rstdiv0_sync_r1_reg_rep__22\,
      O => cnt_pwron_reset_done_r_i_1_n_0
    );
cnt_pwron_reset_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \cnt_pwron_r_reg__0\(0),
      I1 => \cnt_pwron_r_reg__0\(1),
      I2 => \cnt_pwron_r_reg__0\(3),
      I3 => \cnt_pwron_r_reg__0\(5),
      I4 => \cnt_pwron_r_reg__0\(2),
      I5 => \cnt_pwron_r_reg__0\(4),
      O => cnt_pwron_reset_done_r_i_2_n_0
    );
cnt_pwron_reset_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_pwron_reset_done_r_i_1_n_0,
      Q => cnt_pwron_reset_done_r,
      R => '0'
    );
cnt_txpr_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAABAA"
    )
        port map (
      I0 => cnt_txpr_done_r,
      I1 => cnt_txpr_done_r_i_2_n_0,
      I2 => \cnt_txpr_r_reg__0\(7),
      I3 => \cnt_txpr_r_reg__0\(4),
      I4 => \cnt_txpr_r_reg__0\(6),
      I5 => \cnt_txpr_r_reg__0\(3),
      O => cnt_txpr_done_r_i_1_n_0
    );
cnt_txpr_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(0),
      I1 => \cnt_txpr_r_reg__0\(1),
      I2 => \cnt_txpr_r_reg__0\(2),
      I3 => \cnt_txpr_r_reg__0\(5),
      O => cnt_txpr_done_r_i_2_n_0
    );
cnt_txpr_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cnt_txpr_done_r_i_1_n_0,
      Q => cnt_txpr_done_r,
      R => clear
    );
\cnt_txpr_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(0),
      O => \p_0_in__2\(0)
    );
\cnt_txpr_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(1),
      I1 => \cnt_txpr_r_reg__0\(0),
      O => \p_0_in__2\(1)
    );
\cnt_txpr_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(2),
      I1 => \cnt_txpr_r_reg__0\(0),
      I2 => \cnt_txpr_r_reg__0\(1),
      O => \p_0_in__2\(2)
    );
\cnt_txpr_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(3),
      I1 => \cnt_txpr_r_reg__0\(1),
      I2 => \cnt_txpr_r_reg__0\(0),
      I3 => \cnt_txpr_r_reg__0\(2),
      O => \p_0_in__2\(3)
    );
\cnt_txpr_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(4),
      I1 => \cnt_txpr_r_reg__0\(2),
      I2 => \cnt_txpr_r_reg__0\(0),
      I3 => \cnt_txpr_r_reg__0\(1),
      I4 => \cnt_txpr_r_reg__0\(3),
      O => \p_0_in__2\(4)
    );
\cnt_txpr_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(5),
      I1 => \cnt_txpr_r_reg__0\(3),
      I2 => \cnt_txpr_r_reg__0\(1),
      I3 => \cnt_txpr_r_reg__0\(0),
      I4 => \cnt_txpr_r_reg__0\(2),
      I5 => \cnt_txpr_r_reg__0\(4),
      O => \p_0_in__2\(5)
    );
\cnt_txpr_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(6),
      I1 => \cnt_txpr_r[7]_i_3_n_0\,
      O => \p_0_in__2\(6)
    );
\cnt_txpr_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^calib_cke_reg[0]_0\,
      O => clear
    );
\cnt_txpr_r[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(7),
      I1 => \cnt_txpr_r[7]_i_3_n_0\,
      I2 => \cnt_txpr_r_reg__0\(6),
      O => \p_0_in__2\(7)
    );
\cnt_txpr_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \cnt_txpr_r_reg__0\(5),
      I1 => \cnt_txpr_r_reg__0\(3),
      I2 => \cnt_txpr_r_reg__0\(1),
      I3 => \cnt_txpr_r_reg__0\(0),
      I4 => \cnt_txpr_r_reg__0\(2),
      I5 => \cnt_txpr_r_reg__0\(4),
      O => \cnt_txpr_r[7]_i_3_n_0\
    );
\cnt_txpr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(0),
      Q => \cnt_txpr_r_reg__0\(0),
      R => clear
    );
\cnt_txpr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(1),
      Q => \cnt_txpr_r_reg__0\(1),
      R => clear
    );
\cnt_txpr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(2),
      Q => \cnt_txpr_r_reg__0\(2),
      R => clear
    );
\cnt_txpr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(3),
      Q => \cnt_txpr_r_reg__0\(3),
      R => clear
    );
\cnt_txpr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(4),
      Q => \cnt_txpr_r_reg__0\(4),
      R => clear
    );
\cnt_txpr_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(5),
      Q => \cnt_txpr_r_reg__0\(5),
      R => clear
    );
\cnt_txpr_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(6),
      Q => \cnt_txpr_r_reg__0\(6),
      R => clear
    );
\cnt_txpr_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(7),
      Q => \cnt_txpr_r_reg__0\(7),
      R => clear
    );
\complex_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF7F070F0F0"
    )
        port map (
      I0 => init_state_r1(0),
      I1 => \complex_address[9]_i_2_n_0\,
      I2 => \complex_address[9]_i_3_n_0\,
      I3 => init_state_r1(6),
      I4 => init_state_r1(2),
      I5 => \complex_address[9]_i_4_n_0\,
      O => complex_address0
    );
\complex_address[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => init_state_r1(1),
      I1 => init_state_r1(5),
      I2 => init_state_r1(3),
      I3 => init_state_r1(4),
      O => \complex_address[9]_i_2_n_0\
    );
\complex_address[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => \init_state_r[0]_i_3_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \complex_address[9]_i_3_n_0\
    );
\complex_address[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \init_state_r[0]_i_3_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \complex_address[9]_i_4_n_0\
    );
\complex_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      Q => \complex_address_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      Q => \complex_address_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      Q => \complex_address_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      Q => \complex_address_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      Q => \complex_address_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      Q => \complex_address_reg_n_0_[5]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      Q => \complex_address_reg_n_0_[6]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      Q => \complex_address_reg_n_0_[7]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      Q => \complex_address_reg_n_0_[8]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\complex_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_address0,
      D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      Q => \complex_address_reg_n_0_[9]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
complex_byte_rd_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02020200"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \^complex_row1_rd_cnt_reg[1]_0\,
      I2 => \rstdiv0_sync_r1_reg_rep__22\,
      I3 => complex_byte_rd_done_i_2_n_0,
      I4 => complex_byte_rd_done,
      O => complex_byte_rd_done_i_1_n_0
    );
complex_byte_rd_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => complex_row1_rd_cnt(0),
      I1 => complex_row1_rd_cnt(1),
      I2 => complex_row1_rd_cnt(2),
      I3 => complex_row1_rd_done,
      I4 => complex_row1_rd_done_r1,
      I5 => rdlvl_stg1_done_reg,
      O => complex_byte_rd_done_i_2_n_0
    );
complex_byte_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_byte_rd_done_i_1_n_0,
      Q => complex_byte_rd_done,
      R => '0'
    );
\complex_num_reads[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6E2E"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[0]\,
      I1 => \complex_num_reads[3]_i_2_n_0\,
      I2 => \complex_num_reads[2]_i_3_n_0\,
      I3 => \complex_num_writes[0]_i_2_n_0\,
      I4 => \complex_num_reads[3]_i_4_n_0\,
      O => \complex_num_reads[0]_i_1_n_0\
    );
\complex_num_reads[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000002AF0EA"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[1]\,
      I1 => \complex_num_writes[2]_i_6_n_0\,
      I2 => \complex_num_reads[2]_i_3_n_0\,
      I3 => \complex_num_reads[2]_i_5_n_0\,
      I4 => \complex_num_reads[1]_i_2_n_0\,
      I5 => \complex_num_reads[2]_i_2_n_0\,
      O => \complex_num_reads[1]_i_1_n_0\
    );
\complex_num_reads[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"82AA"
    )
        port map (
      I0 => \complex_num_writes[4]_i_7_n_0\,
      I1 => \complex_num_reads_reg_n_0_[0]\,
      I2 => \complex_num_reads_reg_n_0_[1]\,
      I3 => \complex_num_writes[0]_i_2_n_0\,
      O => \complex_num_reads[1]_i_2_n_0\
    );
\complex_num_reads[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010151500100000"
    )
        port map (
      I0 => \complex_num_reads[2]_i_2_n_0\,
      I1 => \complex_num_writes[2]_i_6_n_0\,
      I2 => \complex_num_reads[2]_i_3_n_0\,
      I3 => \complex_num_reads[2]_i_4_n_0\,
      I4 => \complex_num_reads[2]_i_5_n_0\,
      I5 => \complex_num_reads_reg_n_0_[2]\,
      O => \complex_num_reads[2]_i_1_n_0\
    );
\complex_num_reads[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23\,
      I1 => \complex_num_reads_reg_n_0_[2]\,
      I2 => \complex_num_reads_reg_n_0_[1]\,
      I3 => \complex_num_reads_reg_n_0_[3]\,
      I4 => \complex_num_reads[2]_i_3_n_0\,
      I5 => \complex_num_writes[4]_i_11_n_0\,
      O => \complex_num_reads[2]_i_2_n_0\
    );
\complex_num_reads[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \complex_address[9]_i_4_n_0\,
      I1 => \complex_wait_cnt_reg__0\(3),
      I2 => \complex_wait_cnt_reg__0\(2),
      I3 => \complex_wait_cnt_reg__0\(1),
      I4 => \complex_wait_cnt_reg__0\(0),
      I5 => complex_row0_rd_done,
      O => \complex_num_reads[2]_i_3_n_0\
    );
\complex_num_reads[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"802A"
    )
        port map (
      I0 => \complex_num_writes[2]_i_8_n_0\,
      I1 => \complex_num_reads_reg_n_0_[1]\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      I3 => \complex_num_reads_reg_n_0_[2]\,
      O => \complex_num_reads[2]_i_4_n_0\
    );
\complex_num_reads[2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \complex_num_reads[3]_i_2_n_0\,
      I1 => \complex_num_reads[2]_i_3_n_0\,
      I2 => \complex_num_reads[2]_i_6_n_0\,
      O => \complex_num_reads[2]_i_5_n_0\
    );
\complex_num_reads[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \complex_num_writes[2]_i_9_n_0\,
      I1 => \complex_num_writes[4]_i_14_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \complex_num_reads[2]_i_6_n_0\
    );
\complex_num_reads[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[3]\,
      I1 => \complex_num_reads[3]_i_2_n_0\,
      I2 => \complex_num_reads[3]_i_3_n_0\,
      I3 => \complex_num_reads[3]_i_4_n_0\,
      O => \complex_num_reads[3]_i_1_n_0\
    );
\complex_num_reads[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEE2EEEE"
    )
        port map (
      I0 => \complex_num_writes_dec[4]_i_6_n_0\,
      I1 => \complex_num_reads[2]_i_3_n_0\,
      I2 => \complex_num_writes[4]_i_11_n_0\,
      I3 => \complex_num_reads[3]_i_5_n_0\,
      I4 => \complex_num_reads[3]_i_6_n_0\,
      O => \complex_num_reads[3]_i_2_n_0\
    );
\complex_num_reads[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28888888AAAAAAAA"
    )
        port map (
      I0 => \complex_num_reads[2]_i_3_n_0\,
      I1 => \complex_num_reads_reg_n_0_[3]\,
      I2 => \complex_num_reads_reg_n_0_[2]\,
      I3 => \complex_num_reads_reg_n_0_[1]\,
      I4 => \complex_num_reads_reg_n_0_[0]\,
      I5 => \complex_num_writes[0]_i_2_n_0\,
      O => \complex_num_reads[3]_i_3_n_0\
    );
\complex_num_reads[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEF0F0F0FEFFF0F0"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[3]\,
      I1 => \complex_num_reads[3]_i_7_n_0\,
      I2 => \rstdiv0_sync_r1_reg_rep__23\,
      I3 => \complex_num_writes[4]_i_11_n_0\,
      I4 => \complex_num_reads[2]_i_3_n_0\,
      I5 => \complex_num_writes[4]_i_7_n_0\,
      O => \complex_num_reads[3]_i_4_n_0\
    );
\complex_num_reads[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000777F"
    )
        port map (
      I0 => \complex_num_writes[4]_i_9_n_0\,
      I1 => \complex_num_reads_reg_n_0_[2]\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      I3 => \complex_num_reads_reg_n_0_[1]\,
      I4 => \complex_num_reads_reg_n_0_[3]\,
      O => \complex_num_reads[3]_i_5_n_0\
    );
\complex_num_reads[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFECC0"
    )
        port map (
      I0 => \complex_num_writes[0]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_13_n_0\,
      I2 => \complex_num_reads_reg_n_0_[1]\,
      I3 => \complex_num_reads_reg_n_0_[2]\,
      I4 => \complex_num_writes[4]_i_9_n_0\,
      O => \complex_num_reads[3]_i_6_n_0\
    );
\complex_num_reads[3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \complex_num_reads_reg_n_0_[2]\,
      I1 => \complex_num_reads_reg_n_0_[1]\,
      O => \complex_num_reads[3]_i_7_n_0\
    );
\complex_num_reads_dec[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => complex_num_reads_dec(0),
      I1 => \complex_num_reads_dec[3]_i_3_n_0\,
      I2 => \complex_num_reads_reg_n_0_[0]\,
      O => \complex_num_reads_dec[0]_i_1_n_0\
    );
\complex_num_reads_dec[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => complex_num_reads_dec(1),
      I1 => complex_num_reads_dec(0),
      I2 => \complex_num_reads_dec[3]_i_3_n_0\,
      I3 => \complex_num_reads_reg_n_0_[1]\,
      O => \complex_num_reads_dec[1]_i_1_n_0\
    );
\complex_num_reads_dec[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => complex_num_reads_dec(2),
      I1 => complex_num_reads_dec(0),
      I2 => complex_num_reads_dec(1),
      I3 => \complex_num_reads_dec[3]_i_3_n_0\,
      I4 => \complex_num_reads_reg_n_0_[2]\,
      O => \complex_num_reads_dec[2]_i_1_n_0\
    );
\complex_num_reads_dec[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDDDDD5"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_3_n_0\,
      I1 => \complex_num_reads_dec[3]_i_4_n_0\,
      I2 => complex_num_reads_dec(0),
      I3 => complex_num_reads_dec(1),
      I4 => complex_num_reads_dec(3),
      I5 => complex_num_reads_dec(2),
      O => \complex_num_reads_dec[3]_i_1_n_0\
    );
\complex_num_reads_dec[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA9FFFFAAA90000"
    )
        port map (
      I0 => complex_num_reads_dec(3),
      I1 => complex_num_reads_dec(2),
      I2 => complex_num_reads_dec(1),
      I3 => complex_num_reads_dec(0),
      I4 => \complex_num_reads_dec[3]_i_3_n_0\,
      I5 => \complex_num_reads_reg_n_0_[3]\,
      O => \complex_num_reads_dec[3]_i_2_n_0\
    );
\complex_num_reads_dec[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5515"
    )
        port map (
      I0 => \complex_num_writes_dec[4]_i_6_n_0\,
      I1 => \complex_address[9]_i_4_n_0\,
      I2 => \complex_wait_cnt[3]_i_6_n_0\,
      I3 => complex_row0_rd_done,
      O => \complex_num_reads_dec[3]_i_3_n_0\
    );
\complex_num_reads_dec[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \complex_num_reads_dec[3]_i_4_n_0\
    );
\complex_num_reads_dec_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[0]_i_1_n_0\,
      Q => complex_num_reads_dec(0),
      S => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\complex_num_reads_dec_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[1]_i_1_n_0\,
      Q => complex_num_reads_dec(1),
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\complex_num_reads_dec_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[2]_i_1_n_0\,
      Q => complex_num_reads_dec(2),
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\complex_num_reads_dec_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_reads_dec[3]_i_1_n_0\,
      D => \complex_num_reads_dec[3]_i_2_n_0\,
      Q => complex_num_reads_dec(3),
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\complex_num_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[0]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[0]\,
      R => '0'
    );
\complex_num_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[1]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[1]\,
      R => '0'
    );
\complex_num_reads_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[2]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[2]\,
      R => '0'
    );
\complex_num_reads_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_reads[3]_i_1_n_0\,
      Q => \complex_num_reads_reg_n_0_[3]\,
      R => '0'
    );
\complex_num_writes[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7D5D5D5D7DFD5DFD"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes_reg_n_0_[0]\,
      I2 => \complex_num_writes[3]_i_2_n_0\,
      I3 => \complex_num_writes[2]_i_5_n_0\,
      I4 => \complex_num_writes[0]_i_2_n_0\,
      I5 => \complex_num_writes[3]_i_4_n_0\,
      O => \complex_num_writes[0]_i_1_n_0\
    );
\complex_num_writes[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFFFFFF"
    )
        port map (
      I0 => \complex_num_writes[0]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      O => \complex_num_writes[0]_i_2_n_0\
    );
\complex_num_writes[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \complex_num_writes[0]_i_3_n_0\
    );
\complex_num_writes[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEE022200000000"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[1]\,
      I1 => \complex_num_writes[2]_i_4_n_0\,
      I2 => \complex_num_writes[2]_i_5_n_0\,
      I3 => \complex_num_writes[2]_i_6_n_0\,
      I4 => \complex_num_writes[1]_i_2_n_0\,
      I5 => \complex_num_writes[2]_i_2_n_0\,
      O => \complex_num_writes[1]_i_1_n_0\
    );
\complex_num_writes[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CEECCCCCEEEEEEEE"
    )
        port map (
      I0 => \complex_num_writes[2]_i_5_n_0\,
      I1 => \complex_num_writes[3]_i_4_n_0\,
      I2 => \complex_num_writes_reg_n_0_[0]\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      I4 => \complex_num_writes[0]_i_2_n_0\,
      I5 => \complex_num_writes[4]_i_7_n_0\,
      O => \complex_num_writes[1]_i_2_n_0\
    );
\complex_num_writes[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A808A808A80"
    )
        port map (
      I0 => \complex_num_writes[2]_i_2_n_0\,
      I1 => \complex_num_writes[2]_i_3_n_0\,
      I2 => \complex_num_writes[2]_i_4_n_0\,
      I3 => \complex_num_writes_reg_n_0_[2]\,
      I4 => \complex_num_writes[2]_i_5_n_0\,
      I5 => \complex_num_writes[2]_i_6_n_0\,
      O => \complex_num_writes[2]_i_1_n_0\
    );
\complex_num_writes[2]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \complex_num_writes[2]_i_10_n_0\
    );
\complex_num_writes[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002AAAAAAAAAAAA"
    )
        port map (
      I0 => \complex_row_cnt_ocal[7]_i_6_n_0\,
      I1 => \complex_num_writes[2]_i_7_n_0\,
      I2 => \complex_num_writes_reg_n_0_[4]\,
      I3 => \complex_num_writes_reg_n_0_[3]\,
      I4 => \complex_num_writes[4]_i_11_n_0\,
      I5 => \complex_num_writes[4]_i_12_n_0\,
      O => \complex_num_writes[2]_i_2_n_0\
    );
\complex_num_writes[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CEEEECCCEEEEEEEE"
    )
        port map (
      I0 => \complex_num_writes[2]_i_5_n_0\,
      I1 => \complex_num_writes[3]_i_4_n_0\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      I3 => \complex_num_writes_reg_n_0_[0]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      I5 => \complex_num_writes[2]_i_8_n_0\,
      O => \complex_num_writes[2]_i_3_n_0\
    );
\complex_num_writes[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \complex_num_writes[4]_i_5_n_0\,
      I1 => \complex_num_writes[2]_i_8_n_0\,
      I2 => \complex_num_writes[2]_i_5_n_0\,
      O => \complex_num_writes[2]_i_4_n_0\
    );
\complex_num_writes[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \complex_address[9]_i_3_n_0\,
      I1 => \complex_wait_cnt_reg__0\(3),
      I2 => \complex_wait_cnt_reg__0\(2),
      I3 => \complex_wait_cnt_reg__0\(1),
      I4 => \complex_wait_cnt_reg__0\(0),
      I5 => complex_row0_wr_done,
      O => \complex_num_writes[2]_i_5_n_0\
    );
\complex_num_writes[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => \complex_num_writes[2]_i_9_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I5 => \complex_num_writes[2]_i_10_n_0\,
      O => \complex_num_writes[2]_i_6_n_0\
    );
\complex_num_writes[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[2]\,
      I1 => \complex_num_writes_reg_n_0_[1]\,
      O => \complex_num_writes[2]_i_7_n_0\
    );
\complex_num_writes[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \complex_num_writes[0]_i_2_n_0\,
      I1 => \complex_num_reads[2]_i_6_n_0\,
      O => \complex_num_writes[2]_i_8_n_0\
    );
\complex_num_writes[2]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \complex_num_writes[2]_i_9_n_0\
    );
\complex_num_writes[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8A8A808"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes_reg_n_0_[3]\,
      I2 => \complex_num_writes[3]_i_2_n_0\,
      I3 => \complex_num_writes[3]_i_3_n_0\,
      I4 => \complex_num_writes[3]_i_4_n_0\,
      O => \complex_num_writes[3]_i_1_n_0\
    );
\complex_num_writes[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \complex_num_writes[0]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_12_n_0\,
      I2 => \complex_num_writes[4]_i_5_n_0\,
      O => \complex_num_writes[3]_i_2_n_0\
    );
\complex_num_writes[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28888888AAAAAAAA"
    )
        port map (
      I0 => \complex_num_writes[2]_i_5_n_0\,
      I1 => \complex_num_writes_reg_n_0_[3]\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      I3 => \complex_num_writes_reg_n_0_[0]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      I5 => \complex_num_writes[0]_i_2_n_0\,
      O => \complex_num_writes[3]_i_3_n_0\
    );
\complex_num_writes[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \wrcal_reads[7]_i_5_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => init_state_r(6),
      I5 => complex_row0_wr_done,
      O => \complex_num_writes[3]_i_4_n_0\
    );
\complex_num_writes[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008AA0800"
    )
        port map (
      I0 => \complex_num_writes[4]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_3_n_0\,
      I2 => \complex_num_writes[4]_i_4_n_0\,
      I3 => \complex_num_writes[4]_i_5_n_0\,
      I4 => \complex_num_writes_reg_n_0_[4]\,
      I5 => \complex_num_writes[4]_i_6_n_0\,
      O => \complex_num_writes[4]_i_1_n_0\
    );
\complex_num_writes[4]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEEEEE"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[3]\,
      I1 => \complex_num_writes_reg_n_0_[4]\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      I3 => \complex_num_writes_reg_n_0_[0]\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_10_n_0\
    );
\complex_num_writes[4]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF00D000"
    )
        port map (
      I0 => \complex_num_writes[4]_i_15_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0\,
      O => \complex_num_writes[4]_i_11_n_0\
    );
\complex_num_writes[4]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \complex_num_writes[4]_i_16_n_0\,
      I2 => \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \complex_num_writes[4]_i_12_n_0\
    );
\complex_num_writes[4]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFA8"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \complex_num_writes[4]_i_13_n_0\
    );
\complex_num_writes[4]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \complex_num_writes[4]_i_14_n_0\
    );
\complex_num_writes[4]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \complex_num_writes[4]_i_15_n_0\
    );
\complex_num_writes[4]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(3),
      I1 => \complex_wait_cnt_reg__0\(2),
      I2 => \complex_wait_cnt_reg__0\(1),
      I3 => \complex_wait_cnt_reg__0\(0),
      O => \complex_num_writes[4]_i_16_n_0\
    );
\complex_num_writes[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \complex_num_writes[2]_i_2_n_0\,
      I1 => \complex_num_writes[4]_i_7_n_0\,
      I2 => \complex_num_writes[2]_i_5_n_0\,
      O => \complex_num_writes[4]_i_2_n_0\
    );
\complex_num_writes[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \complex_num_writes[2]_i_5_n_0\,
      I1 => \complex_num_writes[3]_i_4_n_0\,
      O => \complex_num_writes[4]_i_3_n_0\
    );
\complex_num_writes[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080007FFF"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[3]\,
      I1 => \complex_num_writes_reg_n_0_[1]\,
      I2 => \complex_num_writes_reg_n_0_[0]\,
      I3 => \complex_num_writes_reg_n_0_[2]\,
      I4 => \complex_num_writes_reg_n_0_[4]\,
      I5 => \complex_num_writes[3]_i_4_n_0\,
      O => \complex_num_writes[4]_i_4_n_0\
    );
\complex_num_writes[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFABFBAAAAAAAA"
    )
        port map (
      I0 => \complex_wait_cnt[3]_i_3_n_0\,
      I1 => \complex_num_writes[4]_i_8_n_0\,
      I2 => \complex_num_writes[4]_i_9_n_0\,
      I3 => \complex_num_writes[4]_i_10_n_0\,
      I4 => \complex_num_writes[4]_i_11_n_0\,
      I5 => \complex_num_writes[4]_i_12_n_0\,
      O => \complex_num_writes[4]_i_5_n_0\
    );
\complex_num_writes[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \complex_num_writes[4]_i_12_n_0\,
      I1 => \complex_num_writes[0]_i_2_n_0\,
      O => \complex_num_writes[4]_i_6_n_0\
    );
\complex_num_writes[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \complex_num_writes[2]_i_6_n_0\,
      I1 => \complex_num_reads[2]_i_6_n_0\,
      O => \complex_num_writes[4]_i_7_n_0\
    );
\complex_num_writes[4]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEAEAAA"
    )
        port map (
      I0 => \complex_num_writes_reg_n_0_[4]\,
      I1 => \complex_num_writes_reg_n_0_[3]\,
      I2 => \complex_num_writes_reg_n_0_[1]\,
      I3 => \complex_num_writes_reg_n_0_[2]\,
      I4 => \complex_num_writes[4]_i_13_n_0\,
      O => \complex_num_writes[4]_i_8_n_0\
    );
\complex_num_writes[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEECECECECEC"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0\,
      I2 => \complex_num_writes[4]_i_14_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \complex_num_writes[4]_i_9_n_0\
    );
\complex_num_writes_dec[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => complex_num_writes_dec(0),
      I1 => \complex_num_writes_dec[4]_i_5_n_0\,
      I2 => \complex_num_writes_reg_n_0_[0]\,
      O => \complex_num_writes_dec[0]_i_1_n_0\
    );
\complex_num_writes_dec[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => complex_num_writes_dec(0),
      I1 => complex_num_writes_dec(1),
      I2 => \complex_num_writes_dec[4]_i_5_n_0\,
      I3 => \complex_num_writes_reg_n_0_[1]\,
      O => \complex_num_writes_dec[1]_i_1_n_0\
    );
\complex_num_writes_dec[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => complex_num_writes_dec(2),
      I1 => complex_num_writes_dec(1),
      I2 => complex_num_writes_dec(0),
      I3 => \complex_num_writes_dec[4]_i_5_n_0\,
      I4 => \complex_num_writes_reg_n_0_[2]\,
      O => \complex_num_writes_dec[2]_i_1_n_0\
    );
\complex_num_writes_dec[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA9FFFFAAA90000"
    )
        port map (
      I0 => complex_num_writes_dec(3),
      I1 => complex_num_writes_dec(2),
      I2 => complex_num_writes_dec(0),
      I3 => complex_num_writes_dec(1),
      I4 => \complex_num_writes_dec[4]_i_5_n_0\,
      I5 => \complex_num_writes_reg_n_0_[3]\,
      O => \complex_num_writes_dec[3]_i_1_n_0\
    );
\complex_num_writes_dec[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFEFFFFFFFFF"
    )
        port map (
      I0 => complex_num_writes_dec(3),
      I1 => complex_num_writes_dec(2),
      I2 => \complex_num_writes_dec[4]_i_4_n_0\,
      I3 => complex_num_writes_dec(4),
      I4 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I5 => \complex_num_writes_dec[4]_i_5_n_0\,
      O => \complex_num_writes_dec[4]_i_2_n_0\
    );
\complex_num_writes_dec[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9AAFFFFA9AA0000"
    )
        port map (
      I0 => complex_num_writes_dec(4),
      I1 => complex_num_writes_dec(3),
      I2 => complex_num_writes_dec(2),
      I3 => \complex_num_writes_dec[4]_i_4_n_0\,
      I4 => \complex_num_writes_dec[4]_i_5_n_0\,
      I5 => \complex_num_writes_reg_n_0_[4]\,
      O => \complex_num_writes_dec[4]_i_3_n_0\
    );
\complex_num_writes_dec[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => complex_num_writes_dec(0),
      I1 => complex_num_writes_dec(1),
      O => \complex_num_writes_dec[4]_i_4_n_0\
    );
\complex_num_writes_dec[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5515"
    )
        port map (
      I0 => \complex_num_writes_dec[4]_i_6_n_0\,
      I1 => \complex_address[9]_i_3_n_0\,
      I2 => \complex_wait_cnt[3]_i_6_n_0\,
      I3 => complex_row0_rd_done,
      O => \complex_num_writes_dec[4]_i_5_n_0\
    );
\complex_num_writes_dec[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00004000"
    )
        port map (
      I0 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \wrcal_reads[7]_i_5_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => init_state_r(6),
      I5 => \^stg1_wr_done\,
      O => \complex_num_writes_dec[4]_i_6_n_0\
    );
\complex_num_writes_dec_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[0]_i_1_n_0\,
      Q => complex_num_writes_dec(0),
      S => prbs_rdlvl_done_pulse_reg_0(0)
    );
\complex_num_writes_dec_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[1]_i_1_n_0\,
      Q => complex_num_writes_dec(1),
      R => prbs_rdlvl_done_pulse_reg_0(0)
    );
\complex_num_writes_dec_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[2]_i_1_n_0\,
      Q => complex_num_writes_dec(2),
      R => prbs_rdlvl_done_pulse_reg_0(0)
    );
\complex_num_writes_dec_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[3]_i_1_n_0\,
      Q => complex_num_writes_dec(3),
      R => prbs_rdlvl_done_pulse_reg_0(0)
    );
\complex_num_writes_dec_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \complex_num_writes_dec[4]_i_2_n_0\,
      D => \complex_num_writes_dec[4]_i_3_n_0\,
      Q => complex_num_writes_dec(4),
      R => prbs_rdlvl_done_pulse_reg_0(0)
    );
\complex_num_writes_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[0]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[0]\,
      R => '0'
    );
\complex_num_writes_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[1]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[1]\,
      R => '0'
    );
\complex_num_writes_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[2]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[2]\,
      R => '0'
    );
\complex_num_writes_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[3]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[3]\,
      R => '0'
    );
\complex_num_writes_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_num_writes[4]_i_1_n_0\,
      Q => \complex_num_writes_reg_n_0_[4]\,
      R => '0'
    );
complex_ocal_odt_ext_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333303331333333"
    )
        port map (
      I0 => cnt_cmd_done_m7_r,
      I1 => complex_ocal_odt_ext_i_2_n_0,
      I2 => prech_req_r_i_3_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => complex_ocal_odt_ext_i_1_n_0
    );
complex_ocal_odt_ext_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBBBBA"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23\,
      I1 => complex_ocal_odt_ext,
      I2 => \cnt_init_mr_r[1]_i_4_n_0\,
      I3 => \init_state_r[2]_i_6_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => complex_ocal_odt_ext_i_2_n_0
    );
complex_ocal_odt_ext_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_ocal_odt_ext_i_1_n_0,
      Q => complex_ocal_odt_ext,
      R => '0'
    );
complex_ocal_reset_rd_addr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAEAAAAAAAAAA"
    )
        port map (
      I0 => prbs_rdlvl_done_pulse0,
      I1 => \complex_wait_cnt_reg__0\(0),
      I2 => \complex_wait_cnt_reg__0\(1),
      I3 => \complex_wait_cnt_reg__0\(3),
      I4 => \complex_wait_cnt_reg__0\(2),
      I5 => complex_ocal_reset_rd_addr_i_2_n_0,
      O => complex_ocal_reset_rd_addr0
    );
complex_ocal_reset_rd_addr_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => \wrcal_reads[7]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[4]\,
      O => complex_ocal_reset_rd_addr_i_2_n_0
    );
complex_ocal_reset_rd_addr_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_ocal_reset_rd_addr0,
      Q => complex_ocal_reset_rd_addr_reg_n_0,
      R => '0'
    );
complex_oclkdelay_calib_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_done_reg,
      Q => complex_oclkdelay_calib_done_r1,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
complex_oclkdelay_calib_start_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \^rdlvl_stg1_done_r1\,
      I4 => complex_oclkdelay_calib_start_int,
      O => complex_oclkdelay_calib_start_int_i_1_n_0
    );
complex_oclkdelay_calib_start_int_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF7F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[2]\,
      O => complex_oclkdelay_calib_start_int_i_2_n_0
    );
complex_oclkdelay_calib_start_int_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_oclkdelay_calib_start_int_i_1_n_0,
      Q => complex_oclkdelay_calib_start_int,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
complex_oclkdelay_calib_start_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_oclkdelay_calib_start_int,
      Q => complex_oclkdelay_calib_start_r1,
      R => '0'
    );
complex_odt_ext_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAA0020"
    )
        port map (
      I0 => complex_row1_rd_done_i_2_n_0,
      I1 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => complex_sample_cnt_inc_i_2_n_0,
      I4 => complex_odt_ext,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => complex_odt_ext_i_1_n_0
    );
complex_odt_ext_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_odt_ext_i_1_n_0,
      Q => complex_odt_ext,
      R => '0'
    );
complex_row0_rd_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAA8000"
    )
        port map (
      I0 => \complex_row_cnt_ocal[7]_i_6_n_0\,
      I1 => complex_row1_wr_done,
      I2 => complex_oclkdelay_calib_start_int,
      I3 => complex_row1_wr_done0,
      I4 => complex_row0_rd_done,
      I5 => complex_sample_cnt_inc_reg_n_0,
      O => complex_row0_rd_done_i_1_n_0
    );
complex_row0_rd_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => wr_victim_inc_i_2_n_0,
      O => complex_row1_wr_done0
    );
complex_row0_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_row0_rd_done_i_1_n_0,
      Q => complex_row0_rd_done,
      R => '0'
    );
\complex_row1_rd_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000009A"
    )
        port map (
      I0 => complex_row1_rd_cnt(0),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => \^complex_row1_rd_cnt_reg[1]_0\,
      I4 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \complex_row1_rd_cnt[0]_i_1_n_0\
    );
\complex_row1_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000009AAA"
    )
        port map (
      I0 => complex_row1_rd_cnt(1),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => complex_row1_rd_cnt(0),
      I4 => \^complex_row1_rd_cnt_reg[1]_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \complex_row1_rd_cnt[1]_i_1_n_0\
    );
\complex_row1_rd_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000009AAAAAAA"
    )
        port map (
      I0 => complex_row1_rd_cnt(2),
      I1 => complex_row1_rd_done_r1,
      I2 => complex_row1_rd_done,
      I3 => complex_row1_rd_cnt(0),
      I4 => complex_row1_rd_cnt(1),
      I5 => prbs_rdlvl_done_pulse_reg_0(0),
      O => \complex_row1_rd_cnt[2]_i_1_n_0\
    );
\complex_row1_rd_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_row1_rd_cnt[0]_i_1_n_0\,
      Q => complex_row1_rd_cnt(0),
      R => '0'
    );
\complex_row1_rd_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_row1_rd_cnt[1]_i_1_n_0\,
      Q => complex_row1_rd_cnt(1),
      R => '0'
    );
\complex_row1_rd_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \complex_row1_rd_cnt[2]_i_1_n_0\,
      Q => complex_row1_rd_cnt(2),
      R => '0'
    );
complex_row1_rd_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0202020200020000"
    )
        port map (
      I0 => complex_row1_rd_done_i_2_n_0,
      I1 => \^complex_row1_rd_cnt_reg[1]_0\,
      I2 => \rstdiv0_sync_r1_reg_rep__22\,
      I3 => wr_victim_inc_i_2_n_0,
      I4 => complex_row0_rd_done,
      I5 => complex_row1_rd_done,
      O => complex_row1_rd_done_i_1_n_0
    );
complex_row1_rd_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => complex_row1_rd_done_i_2_n_0
    );
complex_row1_rd_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_row1_rd_done,
      Q => complex_row1_rd_done_r1,
      R => '0'
    );
complex_row1_rd_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_row1_rd_done_i_1_n_0,
      Q => complex_row1_rd_done,
      R => '0'
    );
\complex_row_cnt_ocal[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(0),
      O => \p_0_in__6\(0)
    );
\complex_row_cnt_ocal[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(1),
      I1 => \complex_row_cnt_ocal_reg__0\(0),
      O => \p_0_in__6\(1)
    );
\complex_row_cnt_ocal[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(2),
      I1 => \complex_row_cnt_ocal_reg__0\(0),
      I2 => \complex_row_cnt_ocal_reg__0\(1),
      O => \p_0_in__6\(2)
    );
\complex_row_cnt_ocal[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(3),
      I1 => \complex_row_cnt_ocal_reg__0\(1),
      I2 => \complex_row_cnt_ocal_reg__0\(0),
      I3 => \complex_row_cnt_ocal_reg__0\(2),
      O => \p_0_in__6\(3)
    );
\complex_row_cnt_ocal[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(4),
      I1 => \complex_row_cnt_ocal_reg__0\(2),
      I2 => \complex_row_cnt_ocal_reg__0\(0),
      I3 => \complex_row_cnt_ocal_reg__0\(1),
      I4 => \complex_row_cnt_ocal_reg__0\(3),
      O => \p_0_in__6\(4)
    );
\complex_row_cnt_ocal[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(5),
      I1 => \complex_row_cnt_ocal_reg__0\(3),
      I2 => \complex_row_cnt_ocal_reg__0\(1),
      I3 => \complex_row_cnt_ocal_reg__0\(0),
      I4 => \complex_row_cnt_ocal_reg__0\(2),
      I5 => \complex_row_cnt_ocal_reg__0\(4),
      O => \p_0_in__6\(5)
    );
\complex_row_cnt_ocal[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(6),
      I1 => \complex_row_cnt_ocal_reg__0\(5),
      I2 => \complex_row_cnt_ocal_reg__0\(4),
      I3 => \complex_row_cnt_ocal[7]_i_5_n_0\,
      O => \p_0_in__6\(6)
    );
\complex_row_cnt_ocal[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF40FFFFFFFFFF"
    )
        port map (
      I0 => \complex_row_cnt_ocal[7]_i_4_n_0\,
      I1 => wr_victim_inc,
      I2 => \complex_row_cnt_ocal[7]_i_5_n_0\,
      I3 => \^rdlvl_stg1_done_r1\,
      I4 => complex_byte_rd_done,
      I5 => \complex_row_cnt_ocal[7]_i_6_n_0\,
      O => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFF08"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \complex_row_cnt_ocal[7]_i_7_n_0\,
      I3 => wr_victim_inc,
      I4 => complex_sample_cnt_inc_r2,
      I5 => \complex_row_cnt_ocal[7]_i_8_n_0\,
      O => complex_row_cnt_ocal
    );
\complex_row_cnt_ocal[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(7),
      I1 => \complex_row_cnt_ocal[7]_i_5_n_0\,
      I2 => \complex_row_cnt_ocal_reg__0\(4),
      I3 => \complex_row_cnt_ocal_reg__0\(5),
      I4 => \complex_row_cnt_ocal_reg__0\(6),
      O => \p_0_in__6\(7)
    );
\complex_row_cnt_ocal[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(6),
      I1 => \complex_row_cnt_ocal_reg__0\(7),
      I2 => \complex_row_cnt_ocal_reg__0\(4),
      I3 => \complex_row_cnt_ocal_reg__0\(5),
      O => \complex_row_cnt_ocal[7]_i_4_n_0\
    );
\complex_row_cnt_ocal[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(3),
      I1 => \complex_row_cnt_ocal_reg__0\(1),
      I2 => \complex_row_cnt_ocal_reg__0\(0),
      I3 => \complex_row_cnt_ocal_reg__0\(2),
      O => \complex_row_cnt_ocal[7]_i_5_n_0\
    );
\complex_row_cnt_ocal[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^complex_row1_rd_cnt_reg[1]_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \complex_row_cnt_ocal[7]_i_6_n_0\
    );
\complex_row_cnt_ocal[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFBFFFFFFFFFF"
    )
        port map (
      I0 => \complex_row_cnt_ocal[7]_i_9_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \complex_row_cnt_ocal[7]_i_7_n_0\
    );
\complex_row_cnt_ocal[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \complex_row_cnt_ocal[7]_i_5_n_0\,
      I1 => rdlvl_stg1_done_reg,
      I2 => \complex_row_cnt_ocal_reg__0\(6),
      I3 => \complex_row_cnt_ocal_reg__0\(7),
      I4 => \complex_row_cnt_ocal_reg__0\(4),
      I5 => \complex_row_cnt_ocal_reg__0\(5),
      O => \complex_row_cnt_ocal[7]_i_8_n_0\
    );
\complex_row_cnt_ocal[7]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \complex_row_cnt_ocal[7]_i_9_n_0\
    );
\complex_row_cnt_ocal_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(0),
      Q => \complex_row_cnt_ocal_reg__0\(0),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(1),
      Q => \complex_row_cnt_ocal_reg__0\(1),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(2),
      Q => \complex_row_cnt_ocal_reg__0\(2),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(3),
      Q => \complex_row_cnt_ocal_reg__0\(3),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(4),
      Q => \complex_row_cnt_ocal_reg__0\(4),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(5),
      Q => \complex_row_cnt_ocal_reg__0\(5),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(6),
      Q => \complex_row_cnt_ocal_reg__0\(6),
      R => complex_row_cnt_ocal0
    );
\complex_row_cnt_ocal_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt_ocal,
      D => \p_0_in__6\(7),
      Q => \complex_row_cnt_ocal_reg__0\(7),
      R => complex_row_cnt_ocal0
    );
complex_sample_cnt_inc_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => complex_row1_rd_done,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      O => complex_sample_cnt_inc0
    );
complex_sample_cnt_inc_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_3_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => complex_sample_cnt_inc_i_2_n_0
    );
complex_sample_cnt_inc_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      O => complex_sample_cnt_inc_i_3_n_0
    );
complex_sample_cnt_inc_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_sample_cnt_inc_reg_n_0,
      Q => complex_sample_cnt_inc_r1,
      R => '0'
    );
complex_sample_cnt_inc_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_sample_cnt_inc_r1,
      Q => complex_sample_cnt_inc_r2,
      R => '0'
    );
complex_sample_cnt_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_sample_cnt_inc0,
      Q => complex_sample_cnt_inc_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\complex_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(0),
      O => \p_0_in__7\(0)
    );
\complex_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(1),
      I1 => \complex_wait_cnt_reg__0\(0),
      O => \p_0_in__7\(1)
    );
\complex_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(2),
      I1 => \complex_wait_cnt_reg__0\(0),
      I2 => \complex_wait_cnt_reg__0\(1),
      O => \p_0_in__7\(2)
    );
\complex_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF1110"
    )
        port map (
      I0 => \complex_wait_cnt[3]_i_3_n_0\,
      I1 => complex_ocal_reset_rd_addr_i_2_n_0,
      I2 => \complex_wait_cnt[3]_i_4_n_0\,
      I3 => \complex_wait_cnt[3]_i_5_n_0\,
      I4 => \complex_wait_cnt[3]_i_6_n_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(3),
      I1 => \complex_wait_cnt_reg__0\(1),
      I2 => \complex_wait_cnt_reg__0\(0),
      I3 => \complex_wait_cnt_reg__0\(2),
      O => \p_0_in__7\(3)
    );
\complex_wait_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \wrcal_reads[7]_i_5_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \complex_wait_cnt[3]_i_3_n_0\
    );
\complex_wait_cnt[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      O => \complex_wait_cnt[3]_i_4_n_0\
    );
\complex_wait_cnt[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFCFDFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \complex_wait_cnt[3]_i_5_n_0\
    );
\complex_wait_cnt[3]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(0),
      I1 => \complex_wait_cnt_reg__0\(1),
      I2 => \complex_wait_cnt_reg__0\(3),
      I3 => \complex_wait_cnt_reg__0\(2),
      O => \complex_wait_cnt[3]_i_6_n_0\
    );
\complex_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__7\(0),
      Q => \complex_wait_cnt_reg__0\(0),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__7\(1),
      Q => \complex_wait_cnt_reg__0\(1),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__7\(2),
      Q => \complex_wait_cnt_reg__0\(2),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\complex_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__7\(3),
      Q => \complex_wait_cnt_reg__0\(3),
      R => \complex_wait_cnt[3]_i_1_n_0\
    );
\data_offset_1_i1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_1_reg[0]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_1(0),
      O => \data_offset_1_i1_reg[5]\(0)
    );
\data_offset_1_i1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_1_reg[1]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_1(1),
      O => \data_offset_1_i1_reg[5]\(1)
    );
\data_offset_1_i1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_1_reg[2]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_1(2),
      O => \data_offset_1_i1_reg[5]\(2)
    );
\data_offset_1_i1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_1(3),
      O => \data_offset_1_i1_reg[5]\(3)
    );
\data_offset_1_i1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_1_reg[4]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_1(4),
      O => \data_offset_1_i1_reg[5]\(4)
    );
\data_offset_1_i1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_1_reg[5]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_1(5),
      O => \data_offset_1_i1_reg[5]\(5)
    );
\data_offset_2_i1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_2(0),
      O => \data_offset_2_i1_reg[5]\(0)
    );
\data_offset_2_i1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[1]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_2(1),
      O => \data_offset_2_i1_reg[5]\(1)
    );
\data_offset_2_i1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[2]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_2(2),
      O => \data_offset_2_i1_reg[5]\(2)
    );
\data_offset_2_i1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_2(3),
      O => \data_offset_2_i1_reg[5]\(3)
    );
\data_offset_2_i1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[4]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_2(4),
      O => \data_offset_2_i1_reg[5]\(4)
    );
\data_offset_2_i1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_2_reg[5]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_2(5),
      O => \data_offset_2_i1_reg[5]\(5)
    );
ddr2_pre_flag_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22F02222"
    )
        port map (
      I0 => ddr2_pre_flag_r_reg_n_0,
      I1 => ddr2_pre_flag_r_i_2_n_0,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \cnt_init_mr_r[1]_i_2_n_0\,
      O => ddr2_pre_flag_r_i_1_n_0
    );
ddr2_pre_flag_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \cnt_init_mr_r[1]_i_2_n_0\,
      I1 => ddr2_refresh_flag_r,
      I2 => cnt_init_mr_done_r,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => cnt_cmd_done_r,
      O => ddr2_pre_flag_r_i_2_n_0
    );
ddr2_pre_flag_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr2_pre_flag_r_i_1_n_0,
      Q => ddr2_pre_flag_r_reg_n_0,
      R => '0'
    );
ddr2_refresh_flag_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFA20000FFAAFFAA"
    )
        port map (
      I0 => ddr2_refresh_flag_r,
      I1 => cnt_init_mr_done_r,
      I2 => ddr2_refresh_flag_r_i_2_n_0,
      I3 => cnt_init_mr_r1,
      I4 => \wrcal_reads[7]_i_6_n_0\,
      I5 => \cnt_init_mr_r[1]_i_2_n_0\,
      O => ddr2_refresh_flag_r_i_1_n_0
    );
ddr2_refresh_flag_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      O => ddr2_refresh_flag_r_i_2_n_0
    );
ddr2_refresh_flag_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr2_refresh_flag_r_i_1_n_0,
      Q => ddr2_refresh_flag_r,
      R => '0'
    );
ddr3_lm_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF8000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => wrcal_done_reg,
      I3 => \cnt_init_mr_r[1]_i_2_n_0\,
      I4 => \^ddr3_lm_done_r\,
      O => ddr3_lm_done_r_i_1_n_0
    );
ddr3_lm_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr3_lm_done_r_i_1_n_0,
      Q => \^ddr3_lm_done_r\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
detect_pi_found_dqs_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000080000"
    )
        port map (
      I0 => \cnt_cmd_r_reg_n_0_[5]\,
      I1 => \cnt_cmd_r[6]_i_5_n_0\,
      I2 => prech_req_r_i_3_n_0,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => prech_req_r_i_2_n_0,
      I5 => \cnt_cmd_r_reg_n_0_[6]\,
      O => detect_pi_found_dqs0
    );
detect_pi_found_dqs_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => detect_pi_found_dqs0,
      Q => detect_pi_found_dqs,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\dqs_asrt_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DADA00DA"
    )
        port map (
      I0 => dqs_asrt_cnt(0),
      I1 => dqs_asrt_cnt(1),
      I2 => wr_level_dqs_asrt,
      I3 => wrlvl_done_r,
      I4 => \^wrlvl_done_r1\,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \dqs_asrt_cnt[0]_i_1_n_0\
    );
\dqs_asrt_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000ECEC00EC"
    )
        port map (
      I0 => dqs_asrt_cnt(0),
      I1 => dqs_asrt_cnt(1),
      I2 => wr_level_dqs_asrt,
      I3 => wrlvl_done_r,
      I4 => \^wrlvl_done_r1\,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \dqs_asrt_cnt[1]_i_1_n_0\
    );
\dqs_asrt_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqs_asrt_cnt[0]_i_1_n_0\,
      Q => dqs_asrt_cnt(0),
      R => '0'
    );
\dqs_asrt_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqs_asrt_cnt[1]_i_1_n_0\,
      Q => dqs_asrt_cnt(1),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000F0F0F0E"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => enable_wrlvl_cnt(4),
      I5 => \rstdiv0_sync_r1_reg_rep__22_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000C3C3C3C2"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => enable_wrlvl_cnt(4),
      I5 => \rstdiv0_sync_r1_reg_rep__22_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFA9A9A9A8"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => enable_wrlvl_cnt(4),
      I5 => \^en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFE01FE00"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => enable_wrlvl_cnt(4),
      I5 => \^en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080008"
    )
        port map (
      I0 => prech_req_r_i_2_n_0,
      I1 => \wrcal_reads[7]_i_5_n_0\,
      I2 => \oclk_wr_cnt[3]_i_5_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => enable_wrlvl_cnt0,
      I5 => wrlvl_odt,
      O => \^en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\
    );
\en_cnt_div4.enable_wrlvl_cnt[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => enable_wrlvl_cnt(4),
      I1 => enable_wrlvl_cnt(3),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(1),
      I4 => enable_wrlvl_cnt(2),
      O => enable_wrlvl_cnt0
    );
\en_cnt_div4.enable_wrlvl_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFE0000"
    )
        port map (
      I0 => enable_wrlvl_cnt(2),
      I1 => enable_wrlvl_cnt(1),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(3),
      I4 => enable_wrlvl_cnt(4),
      I5 => \rstdiv0_sync_r1_reg_rep__22_0\,
      O => \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0\
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\,
      Q => enable_wrlvl_cnt(0),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\,
      Q => enable_wrlvl_cnt(1),
      R => '0'
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\,
      Q => enable_wrlvl_cnt(2),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\,
      Q => enable_wrlvl_cnt(3),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\en_cnt_div4.enable_wrlvl_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0\,
      Q => enable_wrlvl_cnt(4),
      R => '0'
    );
\en_cnt_div4.wrlvl_odt_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0054"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => \en_cnt_div4.wrlvl_odt_i_2_n_0\,
      I2 => wrlvl_odt,
      I3 => wrlvl_odt_ctl,
      O => \en_cnt_div4.wrlvl_odt_i_1_n_0\
    );
\en_cnt_div4.wrlvl_odt_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => enable_wrlvl_cnt(4),
      I1 => enable_wrlvl_cnt(3),
      I2 => enable_wrlvl_cnt(0),
      I3 => enable_wrlvl_cnt(2),
      I4 => enable_wrlvl_cnt(1),
      O => \en_cnt_div4.wrlvl_odt_i_2_n_0\
    );
\en_cnt_div4.wrlvl_odt_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \en_cnt_div4.wrlvl_odt_i_1_n_0\,
      Q => wrlvl_odt,
      R => '0'
    );
first_rdlvl_pat_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => \^first_rdlvl_pat_r\,
      I2 => rdlvl_stg1_rank_done,
      I3 => \rstdiv0_sync_r1_reg_rep__22\,
      O => first_rdlvl_pat_r_i_1_n_0
    );
first_rdlvl_pat_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => first_rdlvl_pat_r_i_1_n_0,
      Q => \^first_rdlvl_pat_r\,
      R => '0'
    );
first_wrcal_pat_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEFAAAB"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => first_wrcal_pat_r_i_2_n_0,
      I4 => \^first_wrcal_pat_r\,
      I5 => wrcal_resume_w,
      O => first_wrcal_pat_r_i_1_n_0
    );
first_wrcal_pat_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => init_state_r(6),
      O => first_wrcal_pat_r_i_2_n_0
    );
first_wrcal_pat_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => first_wrcal_pat_r_i_1_n_0,
      Q => \^first_wrcal_pat_r\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF77470000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I3 => \complex_address_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8FF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F88888888888"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      I1 => \complex_address_reg_n_0_[0]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000000000"
    )
        port map (
      I0 => \reg_ctrl_cnt_r_reg__0\(0),
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I2 => \reg_ctrl_cnt_r_reg__0\(3),
      I3 => init_state_r(6),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(0),
      I1 => rdlvl_stg1_done_reg,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFDDD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000043000100"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => init_state_r(6),
      O => p_94_out
    );
\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001002000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[0]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF100"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAAA0000FBFBFBFB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF222000200020"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      I5 => \complex_address_reg_n_0_[1]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F11"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0\,
      I1 => init_state_r(6),
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0\,
      I3 => \reg_ctrl_cnt_r_reg__0\(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \complex_row_cnt_ocal_reg__0\(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF7"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0\,
      I2 => init_state_r(6),
      I3 => \reg_ctrl_cnt_r_reg__0\(3),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFD0D0FFD0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFBAAFBFBBBAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF222000200020"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      I5 => \complex_address_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011111511"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I2 => \reg_ctrl_cnt_r_reg__0\(3),
      I3 => \reg_ctrl_cnt_r_reg__0\(2),
      I4 => \reg_ctrl_cnt_r_reg__0\(1),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFEF7EFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BABFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\,
      I1 => \complex_row_cnt_ocal_reg__0\(2),
      I2 => rdlvl_stg1_done_reg,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A88AAAA8A88"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\,
      I2 => \complex_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"040404040555FFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4555000000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0\,
      I1 => \complex_row_cnt_ocal[7]_i_7_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I3 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABFBFFFFABFB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \complex_row_cnt_ocal_reg__0\(3),
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0\,
      I5 => burst_addr_r_reg_n_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFFBFFFFF"
    )
        port map (
      I0 => complex_row0_rd_done,
      I1 => wrlvl_odt_ctl_i_2_n_0,
      I2 => init_state_r1(3),
      I3 => init_state_r1(0),
      I4 => init_state_r1(1),
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0002AAAA"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I4 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBFBABFAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEBAAEBAAEBFFEB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I4 => \complex_address_reg_n_0_[4]\,
      I5 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F90909F9FFFFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\,
      I3 => \complex_address_reg_n_0_[4]\,
      I4 => \complex_address_reg_n_0_[3]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080C080FF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(4),
      I1 => rdlvl_stg1_done_reg,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFBFFFF"
    )
        port map (
      I0 => \init_state_r[5]_i_32_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0E000E0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08A8A8A8A8080808"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\,
      I3 => \complex_address_reg_n_0_[4]\,
      I4 => \complex_address_reg_n_0_[3]\,
      I5 => \complex_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EE0C"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0454545454040404"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I3 => \complex_address_reg_n_0_[4]\,
      I4 => \complex_address_reg_n_0_[3]\,
      I5 => \complex_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA2A"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \complex_row_cnt_ocal[7]_i_7_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"51555555"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => init_state_r1(1),
      I2 => init_state_r1(0),
      I3 => init_state_r1(3),
      I4 => wrlvl_odt_ctl_i_2_n_0,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \complex_row_cnt_ocal_reg__0\(5),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF77470000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"66666666FFFFFFDF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0\,
      I2 => cnt_init_mr_r(1),
      I3 => cnt_init_mr_r(0),
      I4 => dqs_found_done_r_reg,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBABABABABFBFBFB"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\,
      I4 => \complex_address_reg_n_0_[5]\,
      I5 => \complex_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8FF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F4F44444444444"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA28A8A8AAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => init_state_r(6),
      I1 => p_94_out,
      I2 => \gen_rnk[0].mr1_r_reg[0]_46\(1),
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9555"
    )
        port map (
      I0 => \complex_address_reg_n_0_[6]\,
      I1 => \complex_address_reg_n_0_[5]\,
      I2 => \complex_address_reg_n_0_[4]\,
      I3 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(6),
      I1 => rdlvl_stg1_done_reg,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A8A8A888A88"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA2AAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\,
      I3 => \oclk_wr_cnt_reg__0\(3),
      I4 => \oclk_wr_cnt_reg__0\(2),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \oclk_wr_cnt_reg__0\(0),
      I1 => \oclk_wr_cnt_reg__0\(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5504"
    )
        port map (
      I0 => p_94_out,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I3 => init_state_r(6),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F2F2F2F0F2F0F0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555545445555"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      I2 => \num_refresh[3]_i_4_n_0\,
      I3 => prech_req_r_i_2_n_0,
      I4 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I5 => \complex_num_reads_dec[3]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F4F44444444444"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95555555"
    )
        port map (
      I0 => \complex_address_reg_n_0_[7]\,
      I1 => \complex_address_reg_n_0_[6]\,
      I2 => \complex_address_reg_n_0_[3]\,
      I3 => \complex_address_reg_n_0_[4]\,
      I4 => \complex_address_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \wrcal_reads[7]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \complex_row_cnt_ocal_reg__0\(7),
      I1 => rdlvl_stg1_done_reg,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF2AFF2AFFFFFF2A"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      I1 => dqs_found_done_r_reg,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6_n_0\,
      I4 => cnt_init_mr_r(0),
      I5 => cnt_init_mr_r(1),
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \complex_address_reg_n_0_[8]\,
      I1 => \complex_address_reg_n_0_[7]\,
      I2 => \complex_address_reg_n_0_[5]\,
      I3 => \complex_address_reg_n_0_[4]\,
      I4 => \complex_address_reg_n_0_[3]\,
      I5 => \complex_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAEAEAAAAAFA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \wrcal_reads[7]_i_5_n_0\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEAEAEFFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000001110"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBFFFFFF7FEF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \complex_address_reg_n_0_[4]\,
      I1 => \complex_address_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEFEEEE"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \complex_row_cnt_ocal[7]_i_7_n_0\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA8AAAA"
    )
        port map (
      I0 => \complex_num_reads_dec[3]_i_4_n_0\,
      I1 => init_state_r1(0),
      I2 => init_state_r1(2),
      I3 => init_state_r1(6),
      I4 => \complex_address[9]_i_2_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAEAAAAAAAA"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\,
      I1 => \oclk_wr_cnt_reg__0\(2),
      I2 => \oclk_wr_cnt_reg__0\(3),
      I3 => \oclk_wr_cnt_reg__0\(1),
      I4 => \oclk_wr_cnt_reg__0\(0),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010055555555"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\,
      I1 => \wrcal_wr_cnt_reg__0\(1),
      I2 => \wrcal_wr_cnt_reg__0\(0),
      I3 => \wrcal_wr_cnt_reg__0\(2),
      I4 => \wrcal_wr_cnt_reg__0\(3),
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEFFFFFFFF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0\,
      I2 => \complex_row_cnt_ocal[7]_i_7_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \complex_num_writes[0]_i_3_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA800000"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\,
      I1 => cnt_init_mr_r(1),
      I2 => cnt_init_mr_r(0),
      I3 => dqs_found_done_r_reg,
      I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0040"
    )
        port map (
      I0 => prech_req_r_i_3_n_0,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0\,
      I5 => p_0_in0_in,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \complex_address_reg_n_0_[9]\,
      I1 => \complex_address_reg_n_0_[6]\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\,
      I3 => \complex_address_reg_n_0_[5]\,
      I4 => \complex_address_reg_n_0_[7]\,
      I5 => \complex_address_reg_n_0_[8]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00DF"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040000000000444"
    )
        port map (
      I0 => \oclk_wr_cnt[3]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_94_out,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0\,
      Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\,
      I1 => p_94_out,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      O => bank_w(0)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CC0000022320300"
    )
        port map (
      I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000666"
    )
        port map (
      I0 => cnt_init_mr_r(0),
      I1 => cnt_init_mr_r(1),
      I2 => pi_dqs_found_done,
      I3 => rdlvl_stg1_done_reg,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\,
      O => bank_w(1)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFFFFFF55FFFF54"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => dqs_found_done_r_reg,
      I2 => cnt_init_mr_r(1),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\
    );
\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => reg_ctrl_cnt_r,
      I1 => \reg_ctrl_cnt_r_reg__0\(1),
      I2 => \reg_ctrl_cnt_r_reg__0\(3),
      I3 => \reg_ctrl_cnt_r_reg__0\(2),
      O => bank_w(2)
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => bank_w(0),
      Q => phy_bank(9),
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => bank_w(1),
      Q => phy_bank(10),
      R => '0'
    );
\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => bank_w(2),
      Q => phy_bank(11),
      R => '0'
    );
\gen_reset_obuf.u_reset_obuf_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__26\,
      I1 => phy_reset_n,
      O => mux_reset_n
    );
\gen_rnk[0].mr1_r_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '1',
      Q => \gen_rnk[0].mr1_r_reg[0]_46\(1),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
init_calib_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r2,
      Q => calib_complete,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
init_complete_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_reg_n_0,
      Q => init_complete_r1,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
init_complete_r1_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_timing,
      Q => init_complete_r1_timing,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
init_complete_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r1,
      Q => init_complete_r2,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
init_complete_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF04000000"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => prech_req_r_i_2_n_0,
      I5 => init_complete_r_reg_n_0,
      O => init_complete_r_i_1_n_0
    );
init_complete_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_i_1_n_0,
      Q => init_complete_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
init_complete_r_timing_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF04000000"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => prech_req_r_i_2_n_0,
      I5 => init_complete_r_timing,
      O => init_complete_r_timing_i_1_n_0
    );
init_complete_r_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_complete_r_timing_i_1_n_0,
      Q => init_complete_r_timing,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[0]\,
      Q => init_state_r1(0),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[1]\,
      Q => init_state_r1(1),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[2]\,
      Q => init_state_r1(2),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[3]\,
      Q => init_state_r1(3),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[4]\,
      Q => init_state_r1(4),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r_reg_n_0_[5]\,
      Q => init_state_r1(5),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_state_r(6),
      Q => init_state_r1(6),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\init_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F744F7F7F7444444"
    )
        port map (
      I0 => \init_state_r[0]_i_2_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r[0]_i_3_n_0\,
      I3 => \init_state_r[0]_i_4_n_0\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r[0]_i_5_n_0\,
      O => \init_state_r[0]_i_1_n_0\
    );
\init_state_r[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEFEEEEEEEFEEEE"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => burst_addr_r_reg_n_0,
      O => \init_state_r[0]_i_10_n_0\
    );
\init_state_r[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAFB"
    )
        port map (
      I0 => \init_state_r[1]_i_25_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => wrcal_prech_req,
      I3 => \wrcal_reads[7]_i_6_n_0\,
      I4 => \^prech_pending_r_reg_0\,
      I5 => wrcal_done_reg,
      O => \init_state_r[0]_i_11_n_0\
    );
\init_state_r[0]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF45"
    )
        port map (
      I0 => \init_state_r[0]_i_25_n_0\,
      I1 => wrcal_sanity_chk_done_reg_0,
      I2 => \init_state_r[1]_i_16_n_0\,
      I3 => \init_state_r[0]_i_27_n_0\,
      I4 => \init_state_r[0]_i_28_n_0\,
      I5 => \init_state_r[0]_i_29_n_0\,
      O => \init_state_r[0]_i_12_n_0\
    );
\init_state_r[0]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000004000550040"
    )
        port map (
      I0 => mpr_rdlvl_start_i_2_n_0,
      I1 => ddr2_pre_flag_r_reg_n_0,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[4]_i_15_n_0\,
      O => \init_state_r[0]_i_13_n_0\
    );
\init_state_r[0]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFABAA"
    )
        port map (
      I0 => \init_state_r[0]_i_30_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_dllk_zqinit_done_r,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => \init_state_r[0]_i_31_n_0\,
      I5 => \init_state_r[0]_i_32_n_0\,
      O => \init_state_r[0]_i_14_n_0\
    );
\init_state_r[0]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AAA8"
    )
        port map (
      I0 => \init_state_r[0]_i_33_n_0\,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r[2]_i_23_n_0\,
      O => \init_state_r[0]_i_15_n_0\
    );
\init_state_r[0]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080888800808888"
    )
        port map (
      I0 => \init_state_r[0]_i_3_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => pi_dqs_found_done,
      I3 => rdlvl_last_byte_done,
      I4 => \^pi_calib_done\,
      I5 => rdlvl_stg1_done_reg,
      O => \init_state_r[0]_i_16_n_0\
    );
\init_state_r[0]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DCDCDCDC0000D000"
    )
        port map (
      I0 => \init_state_r[0]_i_34_n_0\,
      I1 => \init_state_r[4]_i_18_n_0\,
      I2 => \complex_wait_cnt[3]_i_6_n_0\,
      I3 => complex_row1_wr_done,
      I4 => \^one_rank.stg1_wr_done_reg_0\,
      I5 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      O => \init_state_r[0]_i_17_n_0\
    );
\init_state_r[0]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF3F7F3F"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[0]_i_18_n_0\
    );
\init_state_r[0]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8000FFFF"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(2),
      I1 => \complex_wait_cnt_reg__0\(3),
      I2 => \complex_wait_cnt_reg__0\(1),
      I3 => \complex_wait_cnt_reg__0\(0),
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[0]_i_19_n_0\
    );
\init_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444444444444444"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \ocal_act_wait_cnt_reg__0\(2),
      I3 => \ocal_act_wait_cnt_reg__0\(0),
      I4 => \ocal_act_wait_cnt_reg__0\(1),
      I5 => \ocal_act_wait_cnt_reg__0\(3),
      O => \init_state_r[0]_i_2_n_0\
    );
\init_state_r[0]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0000"
    )
        port map (
      I0 => \init_state_r[0]_i_35_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I3 => complex_sample_cnt_inc_i_3_n_0,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \complex_wait_cnt[3]_i_6_n_0\,
      O => \init_state_r[0]_i_20_n_0\
    );
\init_state_r[0]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[1]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \wrcal_reads_reg_n_0_[5]\,
      I3 => \wrcal_reads_reg_n_0_[4]\,
      I4 => \init_state_r[5]_i_30_n_0\,
      O => \init_state_r[0]_i_21_n_0\
    );
\init_state_r[0]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => wrcal_resume_r,
      I3 => wrlvl_byte_redo,
      I4 => \^prech_pending_r_reg_0\,
      I5 => wrcal_done_reg,
      O => \init_state_r[0]_i_22_n_0\
    );
\init_state_r[0]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => pi_phase_locked_all_r4,
      I3 => pi_phase_locked_all_r3,
      O => \init_state_r[0]_i_23_n_0\
    );
\init_state_r[0]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAABABABAAABAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r[3]_i_25_n_0\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r[2]_i_4_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[0]_i_24_n_0\
    );
\init_state_r[0]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[0]_i_25_n_0\
    );
\init_state_r[0]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \init_state_r[0]_i_30_n_0\,
      I1 => \^prech_pending_r_reg_0\,
      I2 => pi_dqs_found_rank_done,
      I3 => pi_dqs_found_done,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[0]_i_27_n_0\
    );
\init_state_r[0]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F0F0F0FFF0F4F"
    )
        port map (
      I0 => \init_state_r[0]_i_36_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[4]_i_14_n_0\,
      O => \init_state_r[0]_i_28_n_0\
    );
\init_state_r[0]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FE0E"
    )
        port map (
      I0 => rdlvl_stg1_rank_done,
      I1 => \init_state_r[1]_i_21_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r[1]_i_30_n_0\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[5]_i_32_n_0\,
      O => \init_state_r[0]_i_29_n_0\
    );
\init_state_r[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[0]_i_3_n_0\
    );
\init_state_r[0]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000002A"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[0]_i_30_n_0\
    );
\init_state_r[0]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2030003030303030"
    )
        port map (
      I0 => \^wrlvl_done_r1\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[0]_i_31_n_0\
    );
\init_state_r[0]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABABABAAABAAAA"
    )
        port map (
      I0 => \init_state_r[2]_i_25_n_0\,
      I1 => \init_state_r[5]_i_32_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => cnt_txpr_done_r,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => delay_done_r4_reg,
      O => \init_state_r[0]_i_32_n_0\
    );
\init_state_r[0]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CC8C"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => reset_rd_addr_r1,
      O => \init_state_r[0]_i_33_n_0\
    );
\init_state_r[0]_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rdlvl_stg1_done_r1\,
      I1 => rdlvl_stg1_done_reg,
      O => \init_state_r[0]_i_34_n_0\
    );
\init_state_r[0]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      O => \init_state_r[0]_i_35_n_0\
    );
\init_state_r[0]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \reg_ctrl_cnt_r_reg__0\(0),
      I1 => \reg_ctrl_cnt_r_reg__0\(1),
      I2 => \reg_ctrl_cnt_r_reg__0\(3),
      I3 => \reg_ctrl_cnt_r_reg__0\(2),
      O => \init_state_r[0]_i_36_n_0\
    );
\init_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FE00FE00FEFE"
    )
        port map (
      I0 => \init_state_r[0]_i_6_n_0\,
      I1 => \init_state_r[0]_i_7_n_0\,
      I2 => \init_state_r[0]_i_8_n_0\,
      I3 => \init_state_r[0]_i_9_n_0\,
      I4 => \init_state_r[0]_i_10_n_0\,
      I5 => \init_state_r[0]_i_11_n_0\,
      O => \init_state_r[0]_i_4_n_0\
    );
\init_state_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E0E0E0E0E0E0E0EE"
    )
        port map (
      I0 => \init_state_r[0]_i_12_n_0\,
      I1 => \init_state_r[0]_i_13_n_0\,
      I2 => \init_state_r[0]_i_14_n_0\,
      I3 => \init_state_r[0]_i_15_n_0\,
      I4 => \init_state_r[0]_i_16_n_0\,
      I5 => \init_state_r[4]_i_14_n_0\,
      O => \init_state_r[0]_i_5_n_0\
    );
\init_state_r[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F88CFCF8F88CFCC"
    )
        port map (
      I0 => \init_state_r[0]_i_17_n_0\,
      I1 => \wrcal_reads[7]_i_5_n_0\,
      I2 => \init_state_r[0]_i_18_n_0\,
      I3 => \init_state_r[3]_i_15_n_0\,
      I4 => \init_state_r[0]_i_19_n_0\,
      I5 => complex_sample_cnt_inc_i_2_n_0,
      O => \init_state_r[0]_i_6_n_0\
    );
\init_state_r[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0505070705000707"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => mpr_rdlvl_start_i_2_n_0,
      I3 => \init_state_r[0]_i_20_n_0\,
      I4 => \init_state_r[5]_i_23_n_0\,
      I5 => \init_state_r[1]_i_22_n_0\,
      O => \init_state_r[0]_i_7_n_0\
    );
\init_state_r[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01110010FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[0]_i_8_n_0\
    );
\init_state_r[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFF20000"
    )
        port map (
      I0 => \init_state_r[0]_i_3_n_0\,
      I1 => \init_state_r[0]_i_21_n_0\,
      I2 => \init_state_r[0]_i_22_n_0\,
      I3 => \init_state_r[0]_i_23_n_0\,
      I4 => \wrcal_reads[7]_i_5_n_0\,
      I5 => \init_state_r[0]_i_24_n_0\,
      O => \init_state_r[0]_i_9_n_0\
    );
\init_state_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAFBAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[1]_i_2_n_0\,
      I1 => \init_state_r[1]_i_3_n_0\,
      I2 => \init_state_r[1]_i_4_n_0\,
      I3 => \init_state_r[5]_i_7_n_0\,
      I4 => \init_state_r[2]_i_5_n_0\,
      I5 => \init_state_r[2]_i_6_n_0\,
      O => \init_state_r[1]_i_1_n_0\
    );
\init_state_r[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFF1"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_2_n_0,
      I1 => \init_state_r[1]_i_22_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r[1]_i_21_n_0\,
      I4 => \init_state_r[1]_i_23_n_0\,
      I5 => mpr_rdlvl_start_i_2_n_0,
      O => \init_state_r[1]_i_10_n_0\
    );
\init_state_r[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000FFF2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => \init_state_r[3]_i_15_n_0\,
      I3 => \complex_wait_cnt[3]_i_6_n_0\,
      I4 => \init_state_r[4]_i_14_n_0\,
      I5 => \init_state_r[1]_i_24_n_0\,
      O => \init_state_r[1]_i_11_n_0\
    );
\init_state_r[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAFFAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[5]_i_32_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => burst_addr_r_reg_n_0,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r[1]_i_25_n_0\,
      I5 => \init_state_r[4]_i_26_n_0\,
      O => \init_state_r[1]_i_12_n_0\
    );
\init_state_r[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF6F660000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r[3]_i_25_n_0\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r[1]_i_26_n_0\,
      O => \init_state_r[1]_i_13_n_0\
    );
\init_state_r[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000040F0F0F0F0"
    )
        port map (
      I0 => rdlvl_last_byte_done,
      I1 => pi_dqs_found_done,
      I2 => \init_state_r[1]_i_27_n_0\,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => rdlvl_stg1_done_reg,
      I5 => \^pi_calib_done\,
      O => \init_state_r[1]_i_14_n_0\
    );
\init_state_r[1]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FB0B0F0F"
    )
        port map (
      I0 => \^mem_init_done_r\,
      I1 => cnt_dllk_zqinit_done_r,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => wrlvl_rank_done_r7,
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[1]_i_15_n_0\
    );
\init_state_r[1]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => cnt_cmd_done_r,
      O => \init_state_r[1]_i_16_n_0\
    );
\init_state_r[1]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2820202028202820"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => cnt_cmd_done_r,
      I4 => wrcal_sanity_chk_done_reg,
      I5 => wrcal_done_reg_1,
      O => \init_state_r[1]_i_17_n_0\
    );
\init_state_r[1]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAFAAEFAA"
    )
        port map (
      I0 => \init_state_r[1]_i_28_n_0\,
      I1 => prech_req_posedge_r_reg_0,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r[5]_i_32_n_0\,
      O => \init_state_r[1]_i_18_n_0\
    );
\init_state_r[1]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000FEE"
    )
        port map (
      I0 => rdlvl_stg1_rank_done,
      I1 => \init_state_r[1]_i_21_n_0\,
      I2 => \init_state_r[1]_i_30_n_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[5]_i_32_n_0\,
      O => \init_state_r[1]_i_19_n_0\
    );
\init_state_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => init_state_r(6),
      I3 => \^prech_pending_r_reg_0\,
      O => \init_state_r[1]_i_2_n_0\
    );
\init_state_r[1]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"004E00FF000000FF"
    )
        port map (
      I0 => \init_state_r[4]_i_35_n_0\,
      I1 => \init_state_r[4]_i_34_n_0\,
      I2 => \init_state_r[1]_i_31_n_0\,
      I3 => \init_state_r[1]_i_32_n_0\,
      I4 => prech_req_r_i_2_n_0,
      I5 => \init_state_r[3]_i_17_n_0\,
      O => \init_state_r[1]_i_20_n_0\
    );
\init_state_r[1]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^prech_pending_r_reg_0\,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => rdlvl_stg1_done_reg,
      O => \init_state_r[1]_i_21_n_0\
    );
\init_state_r[1]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => complex_num_reads_dec(0),
      I2 => complex_num_reads_dec(1),
      I3 => \init_state_r[1]_i_33_n_0\,
      I4 => rdlvl_stg1_done_reg,
      I5 => complex_row0_rd_done,
      O => \init_state_r[1]_i_22_n_0\
    );
\init_state_r[1]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C0C0C0C0E0E0C0E0"
    )
        port map (
      I0 => \complex_wait_cnt[3]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => rdlvl_stg1_done_reg,
      I4 => \^rdlvl_stg1_done_r1\,
      I5 => \^prech_pending_r_reg_0\,
      O => \init_state_r[1]_i_23_n_0\
    );
\init_state_r[1]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01101110FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[1]_i_24_n_0\
    );
\init_state_r[1]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \wrcal_wr_cnt_reg__0\(1),
      I3 => \wrcal_wr_cnt_reg__0\(0),
      I4 => \wrcal_wr_cnt_reg__0\(2),
      I5 => \wrcal_wr_cnt_reg__0\(3),
      O => \init_state_r[1]_i_25_n_0\
    );
\init_state_r[1]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFBBBAAAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r[5]_i_28_n_0\,
      I2 => wrcal_resume_r,
      I3 => wrcal_final_chk,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[1]_i_34_n_0\,
      O => \init_state_r[1]_i_26_n_0\
    );
\init_state_r[1]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[1]_i_27_n_0\
    );
\init_state_r[1]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3E000000FFFFFFFF"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[1]_i_28_n_0\
    );
\init_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00BF00BC"
    )
        port map (
      I0 => \init_state_r[1]_i_5_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r[1]_i_6_n_0\,
      I4 => \init_state_r[1]_i_7_n_0\,
      I5 => \init_state_r[1]_i_8_n_0\,
      O => \init_state_r[1]_i_3_n_0\
    );
\init_state_r[1]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => num_reads(2),
      I1 => num_reads(1),
      I2 => num_reads(0),
      O => \init_state_r[1]_i_30_n_0\
    );
\init_state_r[1]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000CC44C000C000"
    )
        port map (
      I0 => \^wrlvl_done_r1\,
      I1 => pi_dqs_found_done,
      I2 => \^mem_init_done_r\,
      I3 => rdlvl_stg1_done_reg,
      I4 => wrcal_done_reg,
      I5 => wrlvl_byte_redo,
      O => \init_state_r[1]_i_31_n_0\
    );
\init_state_r[1]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5504"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => cnt_cmd_done_r,
      I2 => ddr2_pre_flag_r_reg_n_0,
      I3 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[1]_i_32_n_0\
    );
\init_state_r[1]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => complex_num_reads_dec(2),
      I1 => complex_num_reads_dec(3),
      O => \init_state_r[1]_i_33_n_0\
    );
\init_state_r[1]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[1]_i_34_n_0\
    );
\init_state_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FE000000FE00"
    )
        port map (
      I0 => \init_state_r[1]_i_9_n_0\,
      I1 => \init_state_r[1]_i_10_n_0\,
      I2 => \init_state_r[1]_i_11_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r[1]_i_12_n_0\,
      I5 => \init_state_r[1]_i_13_n_0\,
      O => \init_state_r[1]_i_4_n_0\
    );
\init_state_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF20FF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => reset_rd_addr_r1,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r[2]_i_23_n_0\,
      I5 => \init_state_r[1]_i_14_n_0\,
      O => \init_state_r[1]_i_5_n_0\
    );
\init_state_r[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF1C1C1C10"
    )
        port map (
      I0 => \init_state_r[1]_i_15_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r[1]_i_16_n_0\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[1]_i_6_n_0\
    );
\init_state_r[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EE0F00FF000F00FF"
    )
        port map (
      I0 => cnt_init_mr_done_r,
      I1 => dqs_found_done_r_reg,
      I2 => cnt_txpr_done_r,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[1]_i_7_n_0\
    );
\init_state_r[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABAAABAAABAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r[1]_i_17_n_0\,
      I2 => \init_state_r[1]_i_18_n_0\,
      I3 => \init_state_r[1]_i_19_n_0\,
      I4 => mpr_rdlvl_start_i_2_n_0,
      I5 => \init_state_r[1]_i_20_n_0\,
      O => \init_state_r[1]_i_8_n_0\
    );
\init_state_r[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88AAA200AAAAA200"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r[5]_i_27_n_0\,
      I2 => \init_state_r[1]_i_21_n_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \init_state_r[1]_i_9_n_0\
    );
\init_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F111FFFFF1110000"
    )
        port map (
      I0 => \init_state_r[2]_i_2_n_0\,
      I1 => \init_state_r[2]_i_3_n_0\,
      I2 => \init_state_r[2]_i_4_n_0\,
      I3 => \init_state_r[2]_i_5_n_0\,
      I4 => \init_state_r[2]_i_6_n_0\,
      I5 => \init_state_r[2]_i_7_n_0\,
      O => \init_state_r[2]_i_1_n_0\
    );
\init_state_r[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEAA00FFFFAA00"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^prech_pending_r_reg_0\,
      I2 => complex_oclkdelay_calib_done_r1,
      I3 => rdlvl_stg1_done_reg,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => complex_sample_cnt_inc_i_2_n_0,
      O => \init_state_r[2]_i_10_n_0\
    );
\init_state_r[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEEFEE"
    )
        port map (
      I0 => \init_state_r[2]_i_18_n_0\,
      I1 => \init_state_r[2]_i_19_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r[2]_i_20_n_0\,
      I5 => \init_state_r[2]_i_21_n_0\,
      O => \init_state_r[2]_i_11_n_0\
    );
\init_state_r[2]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^wrlvl_done_r1\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => cnt_cmd_done_r,
      O => \init_state_r[2]_i_12_n_0\
    );
\init_state_r[2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFF4FFF5"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => complex_sample_cnt_inc_i_2_n_0,
      I2 => \init_state_r[2]_i_22_n_0\,
      I3 => \init_state_r[2]_i_23_n_0\,
      I4 => \^rdlvl_stg1_done_r1\,
      I5 => \init_state_r[2]_i_24_n_0\,
      O => \init_state_r[2]_i_13_n_0\
    );
\init_state_r[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEFFEFEEEE"
    )
        port map (
      I0 => \init_state_r[2]_i_25_n_0\,
      I1 => \init_state_r[2]_i_26_n_0\,
      I2 => cnt_dllk_zqinit_done_r,
      I3 => \^mem_init_done_r\,
      I4 => \wrcal_reads[7]_i_5_n_0\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[2]_i_14_n_0\
    );
\init_state_r[2]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFEFEFAFAFAFAF"
    )
        port map (
      I0 => \init_state_r[0]_i_22_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \wrcal_reads[7]_i_5_n_0\,
      I3 => pi_phase_locked_all_r4,
      I4 => pi_phase_locked_all_r3,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[2]_i_15_n_0\
    );
\init_state_r[2]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => burst_addr_r_reg_n_0,
      I2 => \init_state_r[5]_i_32_n_0\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[2]_i_16_n_0\
    );
\init_state_r[2]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEFAAAAAFEFAAAA"
    )
        port map (
      I0 => \init_state_r[2]_i_27_n_0\,
      I1 => \init_state_r[5]_i_23_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \wrcal_reads[7]_i_5_n_0\,
      I5 => \init_state_r[2]_i_28_n_0\,
      O => \init_state_r[2]_i_17_n_0\
    );
\init_state_r[2]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA20200020"
    )
        port map (
      I0 => \init_state_r[2]_i_29_n_0\,
      I1 => wrcal_sanity_chk_done_reg,
      I2 => cnt_cmd_done_r,
      I3 => \^ddr3_lm_done_r\,
      I4 => wrcal_done_reg_1,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[2]_i_18_n_0\
    );
\init_state_r[2]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF55007F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[2]_i_19_n_0\
    );
\init_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABABAABBBBBBBB"
    )
        port map (
      I0 => \init_state_r[5]_i_7_n_0\,
      I1 => \init_state_r[2]_i_8_n_0\,
      I2 => \init_state_r[2]_i_9_n_0\,
      I3 => \init_state_r[4]_i_14_n_0\,
      I4 => \init_state_r[2]_i_10_n_0\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[2]_i_2_n_0\
    );
\init_state_r[2]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8888888A888AAAA"
    )
        port map (
      I0 => \init_state_r[2]_i_30_n_0\,
      I1 => wrlvl_byte_redo_reg,
      I2 => \^mem_init_done_r\,
      I3 => wrcal_done_reg_0,
      I4 => \init_state_r[2]_i_32_n_0\,
      I5 => \init_state_r[4]_i_34_n_0\,
      O => \init_state_r[2]_i_20_n_0\
    );
\init_state_r[2]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0AA20000FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[2]_i_21_n_0\
    );
\init_state_r[2]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF20FF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => reset_rd_addr_r1,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => cnt_cmd_done_r,
      O => \init_state_r[2]_i_22_n_0\
    );
\init_state_r[2]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[5]_i_46_n_0\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \^rdlvl_stg1_done_r1\,
      I4 => complex_num_writes_dec(4),
      I5 => complex_row0_wr_done,
      O => \init_state_r[2]_i_23_n_0\
    );
\init_state_r[2]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000FFFFFFFF"
    )
        port map (
      I0 => \^pi_calib_done\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => cnt_cmd_done_r,
      I4 => rdlvl_stg1_done_reg_0,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_24_n_0\
    );
\init_state_r[2]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF10301010"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => wrlvl_rank_done_r7,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[2]_i_25_n_0\
    );
\init_state_r[2]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000F80000"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => pi_dqs_found_done,
      I2 => cnt_init_mr_done_r,
      I3 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r[5]_i_32_n_0\,
      O => \init_state_r[2]_i_26_n_0\
    );
\init_state_r[2]_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[2]_i_27_n_0\
    );
\init_state_r[2]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAAEAAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \complex_wait_cnt_reg__0\(3),
      I2 => \complex_wait_cnt_reg__0\(2),
      I3 => \complex_wait_cnt_reg__0\(0),
      I4 => \complex_wait_cnt_reg__0\(1),
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \init_state_r[2]_i_28_n_0\
    );
\init_state_r[2]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[2]_i_29_n_0\
    );
\init_state_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444545555"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r[2]_i_11_n_0\,
      I2 => \init_state_r[2]_i_12_n_0\,
      I3 => \init_state_r[2]_i_13_n_0\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r[2]_i_14_n_0\,
      O => \init_state_r[2]_i_3_n_0\
    );
\init_state_r[2]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \^mem_init_done_r\,
      I2 => cnt_init_af_done_r,
      O => \init_state_r[2]_i_30_n_0\
    );
\init_state_r[2]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CC04CC44"
    )
        port map (
      I0 => \^wrlvl_done_r1\,
      I1 => pi_dqs_found_done,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => rdlvl_stg1_done_reg,
      I4 => \^mem_init_done_r\,
      O => \init_state_r[2]_i_32_n_0\
    );
\init_state_r[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[2]_i_4_n_0\
    );
\init_state_r[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \ocal_act_wait_cnt_reg__0\(2),
      I2 => \ocal_act_wait_cnt_reg__0\(0),
      I3 => \ocal_act_wait_cnt_reg__0\(1),
      I4 => \ocal_act_wait_cnt_reg__0\(3),
      O => \init_state_r[2]_i_5_n_0\
    );
\init_state_r[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => init_state_r(6),
      O => \init_state_r[2]_i_6_n_0\
    );
\init_state_r[2]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404444"
    )
        port map (
      I0 => \^prech_pending_r_reg_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => init_state_r(6),
      O => \init_state_r[2]_i_7_n_0\
    );
\init_state_r[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF000055F7"
    )
        port map (
      I0 => \init_state_r[2]_i_15_n_0\,
      I1 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r[3]_i_16_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[2]_i_16_n_0\,
      O => \init_state_r[2]_i_8_n_0\
    );
\init_state_r[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF50504000"
    )
        port map (
      I0 => mpr_rdlvl_start_i_2_n_0,
      I1 => \init_state_r[5]_i_23_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \complex_wait_cnt[3]_i_6_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r[2]_i_17_n_0\,
      O => \init_state_r[2]_i_9_n_0\
    );
\init_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAEEEEFEFF"
    )
        port map (
      I0 => \init_state_r[3]_i_2_n_0\,
      I1 => \init_state_r[3]_i_3_n_0\,
      I2 => \init_state_r[3]_i_4_n_0\,
      I3 => \init_state_r[3]_i_5_n_0\,
      I4 => \init_state_r[3]_i_6_n_0\,
      I5 => \init_state_r[3]_i_7_n_0\,
      O => \init_state_r[3]_i_1_n_0\
    );
\init_state_r[3]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0E00000000000000"
    )
        port map (
      I0 => \^ddr3_lm_done_r\,
      I1 => wrcal_done_reg_1,
      I2 => wrcal_sanity_chk_done_reg,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => cnt_cmd_done_r,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \init_state_r[3]_i_10_n_0\
    );
\init_state_r[3]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101010100000100"
    )
        port map (
      I0 => \init_state_r[3]_i_21_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r[3]_i_22_n_0\,
      I3 => \init_state_r[3]_i_23_n_0\,
      I4 => \init_state_r[3]_i_24_n_0\,
      I5 => \init_state_r[4]_i_14_n_0\,
      O => \init_state_r[3]_i_11_n_0\
    );
\init_state_r[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFC00000"
    )
        port map (
      I0 => \complex_wait_cnt[3]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r[5]_i_23_n_0\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[3]_i_12_n_0\
    );
\init_state_r[3]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[3]_i_13_n_0\
    );
\init_state_r[3]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040404000"
    )
        port map (
      I0 => \init_state_r[4]_i_18_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \complex_wait_cnt[3]_i_6_n_0\,
      I3 => rdlvl_stg1_done_reg,
      I4 => \^rdlvl_stg1_done_r1\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_14_n_0\
    );
\init_state_r[3]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \^prech_pending_r_reg_0\,
      I2 => complex_oclkdelay_calib_done_r1,
      I3 => rdlvl_stg1_done_reg,
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[3]_i_15_n_0\
    );
\init_state_r[3]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BB130000FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r[3]_i_25_n_0\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_16_n_0\
    );
\init_state_r[3]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0D0D0D0D000D0D0"
    )
        port map (
      I0 => cnt_init_af_done_r,
      I1 => \^mem_init_done_r\,
      I2 => cnt_cmd_done_r,
      I3 => \^wrlvl_done_r1\,
      I4 => pi_dqs_found_done,
      I5 => wrlvl_byte_redo,
      O => \init_state_r[3]_i_17_n_0\
    );
\init_state_r[3]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_18_n_0\
    );
\init_state_r[3]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => cnt_cmd_done_r,
      O => \init_state_r[3]_i_19_n_0\
    );
\init_state_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => init_state_r(6),
      I4 => \^prech_pending_r_reg_0\,
      O => \init_state_r[3]_i_2_n_0\
    );
\init_state_r[3]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"340C0C0C040C0C0C"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => wrlvl_rank_done_r7,
      O => \init_state_r[3]_i_21_n_0\
    );
\init_state_r[3]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040000000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \^mem_init_done_r\,
      I5 => cnt_dllk_zqinit_done_r,
      O => \init_state_r[3]_i_22_n_0\
    );
\init_state_r[3]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF4FFFFF"
    )
        port map (
      I0 => rdlvl_last_byte_done,
      I1 => \^one_rank.stg1_wr_done_reg_0\,
      I2 => pi_dqs_found_done,
      I3 => rdlvl_stg1_done_reg,
      I4 => \^pi_calib_done\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[3]_i_23_n_0\
    );
\init_state_r[3]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFF00FFEEFFFFFF"
    )
        port map (
      I0 => reset_rd_addr_r1,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[3]_i_24_n_0\
    );
\init_state_r[3]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \oclk_wr_cnt_reg__0\(1),
      I2 => \oclk_wr_cnt_reg__0\(0),
      I3 => \oclk_wr_cnt_reg__0\(2),
      I4 => \oclk_wr_cnt_reg__0\(3),
      O => \init_state_r[3]_i_25_n_0\
    );
\init_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAFFFB"
    )
        port map (
      I0 => \init_state_r[5]_i_7_n_0\,
      I1 => \init_state_r[3]_i_8_n_0\,
      I2 => \init_state_r[3]_i_9_n_0\,
      I3 => \init_state_r[3]_i_10_n_0\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r[3]_i_11_n_0\,
      O => \init_state_r[3]_i_3_n_0\
    );
\init_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEAAFFFF"
    )
        port map (
      I0 => \init_state_r[3]_i_12_n_0\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \complex_wait_cnt[3]_i_6_n_0\,
      I3 => \init_state_r[3]_i_13_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[3]_i_14_n_0\,
      O => \init_state_r[3]_i_4_n_0\
    );
\init_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFFFF3333FFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r[3]_i_15_n_0\,
      O => \init_state_r[3]_i_5_n_0\
    );
\init_state_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"15550000FFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => \init_state_r[3]_i_16_n_0\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[3]_i_6_n_0\
    );
\init_state_r[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8AAA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r[4]_i_6_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[3]_i_7_n_0\
    );
\init_state_r[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAFBBAAAAAAAA"
    )
        port map (
      I0 => mpr_rdlvl_start_i_2_n_0,
      I1 => ddr2_pre_flag_r_reg_n_0,
      I2 => \init_state_r[3]_i_17_n_0\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[3]_i_8_n_0\
    );
\init_state_r[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF5455FFFF"
    )
        port map (
      I0 => \init_state_r[3]_i_18_n_0\,
      I1 => \init_state_r[3]_i_19_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r[4]_i_22_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[3]_i_13_n_0\,
      O => \init_state_r[3]_i_9_n_0\
    );
\init_state_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEFAAEFAAEFEFEF"
    )
        port map (
      I0 => \init_state_r[4]_i_2_n_0\,
      I1 => \init_state_r[4]_i_3_n_0\,
      I2 => \init_state_r[4]_i_4_n_0\,
      I3 => init_state_r(6),
      I4 => \init_state_r[4]_i_5_n_0\,
      I5 => \init_state_r[4]_i_6_n_0\,
      O => \init_state_r[4]_i_1_n_0\
    );
\init_state_r[4]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFEFEFEFEF"
    )
        port map (
      I0 => \init_state_r[4]_i_21_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r[5]_i_32_n_0\,
      I3 => \init_state_r[4]_i_22_n_0\,
      I4 => \init_state_r[4]_i_23_n_0\,
      I5 => \init_state_r[4]_i_24_n_0\,
      O => \init_state_r[4]_i_10_n_0\
    );
\init_state_r[4]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEFAAAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[4]_i_25_n_0\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r[4]_i_26_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r[4]_i_27_n_0\,
      I5 => \init_state_r[3]_i_16_n_0\,
      O => \init_state_r[4]_i_11_n_0\
    );
\init_state_r[4]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20002000FF000000"
    )
        port map (
      I0 => rdlvl_last_byte_done_reg,
      I1 => dqs_found_done_r_reg,
      I2 => \^pi_calib_done\,
      I3 => \init_state_r[0]_i_3_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[4]_i_12_n_0\
    );
\init_state_r[4]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAAAAAAABBBAAAA"
    )
        port map (
      I0 => \init_state_r[4]_i_29_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => complex_sample_cnt_inc_i_2_n_0,
      I4 => \init_state_r[4]_i_30_n_0\,
      I5 => \^rdlvl_stg1_done_r1\,
      O => \init_state_r[4]_i_13_n_0\
    );
\init_state_r[4]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[4]_i_14_n_0\
    );
\init_state_r[4]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"707F0000FFFFFFFF"
    )
        port map (
      I0 => rdlvl_stg1_done_reg_2,
      I1 => wrcal_done_reg_0,
      I2 => rdlvl_stg1_done_reg_3,
      I3 => \init_state_r[4]_i_34_n_0\,
      I4 => \init_state_r[4]_i_35_n_0\,
      I5 => \init_state_r[3]_i_17_n_0\,
      O => \init_state_r[4]_i_15_n_0\
    );
\init_state_r[4]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDFDDDDDDFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => cnt_cmd_done_r,
      I3 => ddr2_pre_flag_r_reg_n_0,
      I4 => \wrcal_reads[7]_i_6_n_0\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_16_n_0\
    );
\init_state_r[4]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => rdlvl_stg1_done_reg,
      I2 => complex_oclkdelay_calib_done_r1,
      I3 => \^prech_pending_r_reg_0\,
      O => \init_state_r[4]_i_17_n_0\
    );
\init_state_r[4]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF2FFFF"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => \^prech_pending_r_reg_0\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[4]_i_18_n_0\
    );
\init_state_r[4]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555555555555"
    )
        port map (
      I0 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I1 => \complex_wait_cnt_reg__0\(3),
      I2 => \complex_wait_cnt_reg__0\(2),
      I3 => \complex_wait_cnt_reg__0\(0),
      I4 => \complex_wait_cnt_reg__0\(1),
      I5 => \^one_rank.stg1_wr_done_reg_0\,
      O => \init_state_r[4]_i_19_n_0\
    );
\init_state_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => init_state_r(6),
      I3 => \^prech_pending_r_reg_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_2_n_0\
    );
\init_state_r[4]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFBFFFBFBFBF"
    )
        port map (
      I0 => \init_state_r[4]_i_36_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => mpr_rdlvl_start_i_2_n_0,
      I3 => \init_state_r[5]_i_20_n_0\,
      I4 => rdlvl_stg1_done_reg,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_20_n_0\
    );
\init_state_r[4]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2AAA200AAAAAAAA"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r[4]_i_37_n_0\,
      I2 => wrcal_sanity_chk_done_reg,
      I3 => cnt_cmd_done_r,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r[0]_i_3_n_0\,
      O => \init_state_r[4]_i_21_n_0\
    );
\init_state_r[4]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0004FFFF"
    )
        port map (
      I0 => \reg_ctrl_cnt_r_reg__0\(2),
      I1 => \reg_ctrl_cnt_r_reg__0\(3),
      I2 => \reg_ctrl_cnt_r_reg__0\(1),
      I3 => \reg_ctrl_cnt_r_reg__0\(0),
      I4 => cnt_cmd_done_r,
      O => \init_state_r[4]_i_22_n_0\
    );
\init_state_r[4]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFEE"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => cnt_cmd_done_r,
      I3 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_23_n_0\
    );
\init_state_r[4]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[4]_i_24_n_0\
    );
\init_state_r[4]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010111000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \^wrlvl_done_r1\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => dqs_found_done_r_reg,
      I5 => ddr2_refresh_flag_r_i_2_n_0,
      O => \init_state_r[4]_i_25_n_0\
    );
\init_state_r[4]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFABFFFFFFABFFAB"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => wrcal_done_reg,
      I2 => \^prech_pending_r_reg_0\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => wrcal_prech_req,
      I5 => cnt_cmd_done_r,
      O => \init_state_r[4]_i_26_n_0\
    );
\init_state_r[4]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCC8C0C8CCC8CCC8"
    )
        port map (
      I0 => \init_state_r[5]_i_28_n_0\,
      I1 => \wrcal_reads[7]_i_5_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => pi_phase_locked_all_r4,
      I5 => pi_phase_locked_all_r3,
      O => \init_state_r[4]_i_27_n_0\
    );
\init_state_r[4]_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF10FF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => reset_rd_addr_r1,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => cnt_cmd_done_r,
      O => \init_state_r[4]_i_29_n_0\
    );
\init_state_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBBAAAAAAAA"
    )
        port map (
      I0 => \init_state_r[5]_i_7_n_0\,
      I1 => \init_state_r[4]_i_7_n_0\,
      I2 => \init_state_r[4]_i_8_n_0\,
      I3 => \init_state_r[4]_i_9_n_0\,
      I4 => \init_state_r[4]_i_10_n_0\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_3_n_0\
    );
\init_state_r[4]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => complex_num_writes_dec(4),
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => rdlvl_stg1_done_reg,
      I4 => \init_state_r[5]_i_46_n_0\,
      O => \init_state_r[4]_i_30_n_0\
    );
\init_state_r[4]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \num_refresh_reg__0\(3),
      I1 => \num_refresh_reg__0\(2),
      I2 => \num_refresh_reg__0\(0),
      I3 => \num_refresh_reg__0\(1),
      O => \init_state_r[4]_i_34_n_0\
    );
\init_state_r[4]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \^mem_init_done_r\,
      I1 => rdlvl_stg1_done_reg,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => pi_dqs_found_done,
      O => \init_state_r[4]_i_35_n_0\
    );
\init_state_r[4]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1110111111111110"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => cnt_cmd_done_r,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[4]_i_36_n_0\
    );
\init_state_r[4]_i_37\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^ddr3_lm_done_r\,
      I1 => pi_dqs_found_done,
      I2 => rdlvl_stg1_done_reg,
      I3 => \^wrlvl_done_r1\,
      I4 => wrcal_done_reg,
      O => \init_state_r[4]_i_37_n_0\
    );
\init_state_r[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBABAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r[4]_i_11_n_0\,
      I2 => \init_state_r[4]_i_12_n_0\,
      I3 => \init_state_r[4]_i_13_n_0\,
      I4 => \init_state_r[4]_i_14_n_0\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[4]_i_4_n_0\
    );
\init_state_r[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[4]_i_5_n_0\
    );
\init_state_r[4]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \ocal_act_wait_cnt_reg__0\(3),
      I1 => \ocal_act_wait_cnt_reg__0\(1),
      I2 => \ocal_act_wait_cnt_reg__0\(0),
      I3 => \ocal_act_wait_cnt_reg__0\(2),
      O => \init_state_r[4]_i_6_n_0\
    );
\init_state_r[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0B000000"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r[4]_i_15_n_0\,
      I5 => \init_state_r[4]_i_16_n_0\,
      O => \init_state_r[4]_i_7_n_0\
    );
\init_state_r[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEFEEEEEEEFEEEF"
    )
        port map (
      I0 => \init_state_r[4]_i_14_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r[5]_i_27_n_0\,
      I3 => \init_state_r[4]_i_17_n_0\,
      I4 => complex_sample_cnt_inc_i_2_n_0,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[4]_i_8_n_0\
    );
\init_state_r[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0C00FE00"
    )
        port map (
      I0 => \init_state_r[4]_i_18_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \complex_wait_cnt[3]_i_6_n_0\,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => \init_state_r[4]_i_19_n_0\,
      I5 => \init_state_r[4]_i_20_n_0\,
      O => \init_state_r[4]_i_9_n_0\
    );
\init_state_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDD555D"
    )
        port map (
      I0 => \init_state_r[5]_i_2_n_0\,
      I1 => \init_state_r[5]_i_3_n_0\,
      I2 => \init_state_r[5]_i_4_n_0\,
      I3 => \init_state_r[5]_i_5_n_0\,
      I4 => \init_state_r[5]_i_6_n_0\,
      I5 => \init_state_r[5]_i_7_n_0\,
      O => \init_state_r[5]_i_1_n_0\
    );
\init_state_r[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF00EF"
    )
        port map (
      I0 => \init_state_r[5]_i_25_n_0\,
      I1 => complex_sample_cnt_inc_i_3_n_0,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r[5]_i_26_n_0\,
      I4 => \init_state_r[3]_i_15_n_0\,
      I5 => \init_state_r[4]_i_14_n_0\,
      O => \init_state_r[5]_i_10_n_0\
    );
\init_state_r[5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D000D0DFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \complex_wait_cnt[3]_i_6_n_0\,
      I2 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I3 => \init_state_r[5]_i_27_n_0\,
      I4 => \^one_rank.stg1_wr_done_reg_0\,
      I5 => \wrcal_reads[7]_i_5_n_0\,
      O => \init_state_r[5]_i_11_n_0\
    );
\init_state_r[5]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0D0D0D00"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => \^prech_pending_r_reg_0\,
      I3 => \complex_wait_cnt[3]_i_6_n_0\,
      I4 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_12_n_0\
    );
\init_state_r[5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0F444400004444"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r[5]_i_28_n_0\,
      I2 => pi_phase_locked_all_r3,
      I3 => pi_phase_locked_all_r4,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_13_n_0\
    );
\init_state_r[5]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBF0000FFFFFFFF"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[1]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \init_state_r[5]_i_29_n_0\,
      I3 => \init_state_r[5]_i_30_n_0\,
      I4 => \init_state_r[5]_i_31_n_0\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[5]_i_14_n_0\
    );
\init_state_r[5]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBBAABA"
    )
        port map (
      I0 => \init_state_r[5]_i_32_n_0\,
      I1 => \init_state_r[5]_i_33_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => burst_addr_r_reg_n_0,
      I4 => \init_state_r[5]_i_34_n_0\,
      I5 => \init_state_r[5]_i_35_n_0\,
      O => \init_state_r[5]_i_15_n_0\
    );
\init_state_r[5]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54005454"
    )
        port map (
      I0 => \init_state_r[4]_i_14_n_0\,
      I1 => \init_state_r[5]_i_36_n_0\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r[5]_i_37_n_0\,
      I4 => \init_state_r[5]_i_38_n_0\,
      I5 => \init_state_r[5]_i_39_n_0\,
      O => \init_state_r[5]_i_16_n_0\
    );
\init_state_r[5]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400005004500"
    )
        port map (
      I0 => \init_state_r[5]_i_32_n_0\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => cnt_cmd_done_r,
      I5 => \init_state_r[5]_i_40_n_0\,
      O => \init_state_r[5]_i_17_n_0\
    );
\init_state_r[5]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5155FFFF51555155"
    )
        port map (
      I0 => \init_state_r[5]_i_41_n_0\,
      I1 => cnt_cmd_done_r,
      I2 => dqs_found_done_r_reg,
      I3 => \^pi_calib_done\,
      I4 => \init_state_r[5]_i_42_n_0\,
      I5 => \init_state_r[5]_i_43_n_0\,
      O => \init_state_r[5]_i_18_n_0\
    );
\init_state_r[5]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF04040044"
    )
        port map (
      I0 => \init_state_r[5]_i_44_n_0\,
      I1 => \wrcal_reads[7]_i_5_n_0\,
      I2 => wrlvl_rank_done_r7,
      I3 => cnt_dllk_zqinit_done_r,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r[5]_i_45_n_0\,
      O => \init_state_r[5]_i_19_n_0\
    );
\init_state_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => init_state_r(6),
      I4 => \^prech_pending_r_reg_0\,
      O => \init_state_r[5]_i_2_n_0\
    );
\init_state_r[5]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[5]_i_20_n_0\
    );
\init_state_r[5]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEE0EEEEEEEE"
    )
        port map (
      I0 => \init_state_r[5]_i_46_n_0\,
      I1 => \init_state_r[5]_i_47_n_0\,
      I2 => \complex_row_cnt_ocal[7]_i_9_n_0\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I4 => \init_state_r[5]_i_25_n_0\,
      I5 => \^rdlvl_stg1_done_r1\,
      O => \init_state_r[5]_i_21_n_0\
    );
\init_state_r[5]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFFAAAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[4]\,
      O => \init_state_r[5]_i_22_n_0\
    );
\init_state_r[5]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \^prech_pending_r_reg_0\,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => rdlvl_stg1_done_reg,
      O => \init_state_r[5]_i_23_n_0\
    );
\init_state_r[5]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0007000300030002"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_24_n_0\
    );
\init_state_r[5]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \init_state_r[5]_i_25_n_0\
    );
\init_state_r[5]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \complex_wait_cnt_reg__0\(2),
      I2 => \complex_wait_cnt_reg__0\(3),
      I3 => \complex_wait_cnt_reg__0\(1),
      I4 => \complex_wait_cnt_reg__0\(0),
      O => \init_state_r[5]_i_26_n_0\
    );
\init_state_r[5]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \complex_wait_cnt_reg__0\(3),
      I1 => \complex_wait_cnt_reg__0\(2),
      I2 => \complex_wait_cnt_reg__0\(0),
      I3 => \complex_wait_cnt_reg__0\(1),
      O => \init_state_r[5]_i_27_n_0\
    );
\init_state_r[5]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => wrcal_resume_r,
      I1 => wrcal_done_reg,
      I2 => \^prech_pending_r_reg_0\,
      I3 => wrlvl_byte_redo,
      O => \init_state_r[5]_i_28_n_0\
    );
\init_state_r[5]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[5]\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      O => \init_state_r[5]_i_29_n_0\
    );
\init_state_r[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"40FF"
    )
        port map (
      I0 => \init_state_r[4]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => init_state_r(6),
      O => \init_state_r[5]_i_3_n_0\
    );
\init_state_r[5]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[7]\,
      I1 => \wrcal_reads_reg_n_0_[3]\,
      I2 => \wrcal_reads_reg_n_0_[6]\,
      I3 => \wrcal_reads_reg_n_0_[2]\,
      O => \init_state_r[5]_i_30_n_0\
    );
\init_state_r[5]_i_31\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_31_n_0\
    );
\init_state_r[5]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[5]_i_32_n_0\
    );
\init_state_r[5]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F2F2F2FF"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => wrcal_prech_req,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \^prech_pending_r_reg_0\,
      I4 => wrcal_done_reg,
      O => \init_state_r[5]_i_33_n_0\
    );
\init_state_r[5]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => cnt_cmd_done_r,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_34_n_0\
    );
\init_state_r[5]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_35_n_0\
    );
\init_state_r[5]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => cnt_cmd_done_r,
      O => \init_state_r[5]_i_36_n_0\
    );
\init_state_r[5]_i_37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_37_n_0\
    );
\init_state_r[5]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \oclk_wr_cnt_reg__0\(3),
      I1 => \oclk_wr_cnt_reg__0\(2),
      I2 => \oclk_wr_cnt_reg__0\(0),
      I3 => \oclk_wr_cnt_reg__0\(1),
      O => \init_state_r[5]_i_38_n_0\
    );
\init_state_r[5]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFFEAAAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \init_state_r[5]_i_39_n_0\
    );
\init_state_r[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000101010001000"
    )
        port map (
      I0 => \init_state_r[5]_i_8_n_0\,
      I1 => \init_state_r[5]_i_9_n_0\,
      I2 => \init_state_r[5]_i_10_n_0\,
      I3 => \init_state_r[5]_i_11_n_0\,
      I4 => \init_state_r[5]_i_12_n_0\,
      I5 => \init_state_r[0]_i_3_n_0\,
      O => \init_state_r[5]_i_4_n_0\
    );
\init_state_r[5]_i_40\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8888888"
    )
        port map (
      I0 => cnt_txpr_done_r,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => ck_addr_cmd_delay_done,
      I3 => phy_mc_go,
      I4 => \^calib_cke_reg[0]_0\,
      O => \init_state_r[5]_i_40_n_0\
    );
\init_state_r[5]_i_41\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF57FFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_41_n_0\
    );
\init_state_r[5]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"001D"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => cnt_cmd_done_r,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => reset_rd_addr_r1,
      O => \init_state_r[5]_i_42_n_0\
    );
\init_state_r[5]_i_43\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      O => \init_state_r[5]_i_43_n_0\
    );
\init_state_r[5]_i_44\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_44_n_0\
    );
\init_state_r[5]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABAAAAAAA"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => cnt_cmd_done_r,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \init_state_r[5]_i_45_n_0\
    );
\init_state_r[5]_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => complex_num_writes_dec(2),
      I1 => complex_num_writes_dec(3),
      I2 => complex_num_writes_dec(0),
      I3 => complex_num_writes_dec(1),
      O => \init_state_r[5]_i_46_n_0\
    );
\init_state_r[5]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => complex_num_writes_dec(4),
      I3 => complex_row0_wr_done,
      O => \init_state_r[5]_i_47_n_0\
    );
\init_state_r[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007500FFFFFFFF"
    )
        port map (
      I0 => \wrcal_reads[7]_i_5_n_0\,
      I1 => \init_state_r[5]_i_13_n_0\,
      I2 => \init_state_r[5]_i_14_n_0\,
      I3 => \init_state_r[5]_i_15_n_0\,
      I4 => \init_state_r[5]_i_16_n_0\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[5]_i_5_n_0\
    );
\init_state_r[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEFEFFFE"
    )
        port map (
      I0 => \init_state_r[5]_i_17_n_0\,
      I1 => \init_state_r[5]_i_18_n_0\,
      I2 => \init_state_r[5]_i_19_n_0\,
      I3 => \init_state_r[5]_i_20_n_0\,
      I4 => \init_state_r[5]_i_21_n_0\,
      I5 => \init_state_r[5]_i_22_n_0\,
      O => \init_state_r[5]_i_6_n_0\
    );
\init_state_r[5]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      O => \init_state_r[5]_i_7_n_0\
    );
\init_state_r[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEFFAA00"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \complex_wait_cnt[3]_i_6_n_0\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r[5]_i_23_n_0\,
      I5 => mpr_rdlvl_start_i_2_n_0,
      O => \init_state_r[5]_i_8_n_0\
    );
\init_state_r[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBFBBBBB"
    )
        port map (
      I0 => \init_state_r[5]_i_24_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r[4]_i_14_n_0\,
      I4 => prech_req_r_i_2_n_0,
      I5 => rdlvl_stg1_done_reg,
      O => \init_state_r[5]_i_9_n_0\
    );
\init_state_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F000F0F4F0F0F0"
    )
        port map (
      I0 => \init_state_r[6]_i_2_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \^prech_pending_r_reg_0\,
      O => \init_state_r[6]_i_1_n_0\
    );
\init_state_r[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      O => \init_state_r[6]_i_2_n_0\
    );
\init_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r[0]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\init_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r[1]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\init_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r[2]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\init_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r[3]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\init_state_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r[4]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\init_state_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r[5]_i_1_n_0\,
      Q => \init_state_r_reg_n_0_[5]\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\init_state_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_state_r[6]_i_1_n_0\,
      Q => init_state_r(6),
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
mem_init_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4000"
    )
        port map (
      I0 => cnt_dllk_zqinit_done_r,
      I1 => \cnt_dllk_zqinit_r_reg__0\(7),
      I2 => mem_init_done_r_i_2_n_0,
      I3 => \cnt_dllk_zqinit_r_reg__0\(6),
      I4 => \^mem_init_done_r\,
      O => mem_init_done_r_i_1_n_0
    );
mem_init_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \cnt_dllk_zqinit_r_reg__0\(5),
      I1 => \cnt_dllk_zqinit_r_reg__0\(3),
      I2 => \cnt_dllk_zqinit_r_reg__0\(1),
      I3 => \cnt_dllk_zqinit_r_reg__0\(0),
      I4 => \cnt_dllk_zqinit_r_reg__0\(2),
      I5 => \cnt_dllk_zqinit_r_reg__0\(4),
      O => mem_init_done_r_i_2_n_0
    );
mem_init_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mem_init_done_r_i_1_n_0,
      Q => \^mem_init_done_r\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\mem_reg_0_15_0_5_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => phy_ras_n(1),
      O => \rd_ptr_timing_reg[0]_8\(0)
    );
mem_reg_0_15_0_5_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(159),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(159)
    );
\mem_reg_0_15_0_5_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(141),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(141)
    );
\mem_reg_0_15_0_5_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(135),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(135)
    );
mem_reg_0_15_0_5_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(111),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(111)
    );
\mem_reg_0_15_0_5_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(93),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(93)
    );
\mem_reg_0_15_0_5_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(87),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(87)
    );
mem_reg_0_15_0_5_i_7: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(191),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(191)
    );
\mem_reg_0_15_0_5_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(179),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(179)
    );
\mem_reg_0_15_0_5_i_7__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(175),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(175)
    );
mem_reg_0_15_12_17_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(21),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      O => phy_dout(5)
    );
\mem_reg_0_15_12_17_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(4),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(10),
      O => \rd_ptr_timing_reg[0]_8\(6)
    );
\mem_reg_0_15_12_17_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(239),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(239)
    );
\mem_reg_0_15_12_17_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(221),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(221)
    );
\mem_reg_0_15_12_17_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(215),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(215)
    );
mem_reg_0_15_12_17_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(9),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      O => phy_dout(4)
    );
\mem_reg_0_15_12_17_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(1),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(10),
      O => \rd_ptr_timing_reg[0]_8\(5)
    );
\mem_reg_0_15_12_17_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(187),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(187)
    );
\mem_reg_0_15_12_17_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(183),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(183)
    );
\mem_reg_0_15_12_17_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(171),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(171)
    );
\mem_reg_0_15_12_17_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(167),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(167)
    );
\mem_reg_0_15_12_17_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(163),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(163)
    );
mem_reg_0_15_12_17_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(350),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(350)
    );
\mem_reg_0_15_12_17_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(345),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(345)
    );
\mem_reg_0_15_12_17_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(339),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(339)
    );
\mem_reg_0_15_12_17_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(332),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(332)
    );
\mem_reg_0_15_12_17_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(326),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(326)
    );
\mem_reg_0_15_12_17_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(321),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(321)
    );
\mem_reg_0_15_12_17_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(315),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(315)
    );
\mem_reg_0_15_12_17_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(309),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(309)
    );
mem_reg_0_15_12_17_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(302),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(302)
    );
\mem_reg_0_15_12_17_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(295),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(295)
    );
\mem_reg_0_15_12_17_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(287),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(287)
    );
\mem_reg_0_15_12_17_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(278),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(278)
    );
\mem_reg_0_15_12_17_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(270),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(270)
    );
\mem_reg_0_15_12_17_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(263),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(263)
    );
\mem_reg_0_15_12_17_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(255),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(255)
    );
\mem_reg_0_15_12_17_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(247),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(247)
    );
mem_reg_0_15_12_17_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(63),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(63)
    );
\mem_reg_0_15_12_17_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(51),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(51)
    );
\mem_reg_0_15_12_17_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(47),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(47)
    );
mem_reg_0_15_12_17_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(30),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(30)
    );
\mem_reg_0_15_12_17_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(27),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(27)
    );
\mem_reg_0_15_12_17_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(23),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(23)
    );
\mem_reg_0_15_12_17_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(18),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(18)
    );
\mem_reg_0_15_12_17_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(14),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(14)
    );
\mem_reg_0_15_12_17_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(11),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(11)
    );
\mem_reg_0_15_12_17_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(7),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(7)
    );
\mem_reg_0_15_12_17_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(3),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(3)
    );
mem_reg_0_15_18_23_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      O => phy_dout(7)
    );
\mem_reg_0_15_18_23_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24\,
      I1 => phy_bank(10),
      O => \rd_ptr_timing_reg[0]_8\(8)
    );
\mem_reg_0_15_18_23_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(158),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(158)
    );
\mem_reg_0_15_18_23_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(140),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(140)
    );
\mem_reg_0_15_18_23_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(134),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(134)
    );
mem_reg_0_15_18_23_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(32),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      O => phy_dout(6)
    );
\mem_reg_0_15_18_23_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(7),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(10),
      O => \rd_ptr_timing_reg[0]_8\(7)
    );
\mem_reg_0_15_18_23_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(104),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(104)
    );
\mem_reg_0_15_18_23_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(98),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(98)
    );
\mem_reg_0_15_18_23_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(80),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(80)
    );
\mem_reg_0_15_18_23_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(74),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(74)
    );
\mem_reg_0_15_18_23_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(68),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(68)
    );
mem_reg_0_15_18_23_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(238),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(238)
    );
\mem_reg_0_15_18_23_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(233),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(233)
    );
\mem_reg_0_15_18_23_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(227),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(227)
    );
\mem_reg_0_15_18_23_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(220),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(220)
    );
\mem_reg_0_15_18_23_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(214),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(214)
    );
\mem_reg_0_15_18_23_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(209),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(209)
    );
\mem_reg_0_15_18_23_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(203),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(203)
    );
\mem_reg_0_15_18_23_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(197),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(197)
    );
mem_reg_0_15_18_23_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(349),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(349)
    );
\mem_reg_0_15_18_23_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(344),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(344)
    );
\mem_reg_0_15_18_23_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(338),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(338)
    );
\mem_reg_0_15_18_23_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(331),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(331)
    );
\mem_reg_0_15_18_23_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(325),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(325)
    );
\mem_reg_0_15_18_23_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(320),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(320)
    );
\mem_reg_0_15_18_23_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(314),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(314)
    );
\mem_reg_0_15_18_23_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(308),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(308)
    );
mem_reg_0_15_18_23_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(301),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(301)
    );
\mem_reg_0_15_18_23_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(294),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(294)
    );
\mem_reg_0_15_18_23_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(286),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(286)
    );
\mem_reg_0_15_18_23_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(277),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(277)
    );
\mem_reg_0_15_18_23_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(269),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(269)
    );
\mem_reg_0_15_18_23_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(262),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(262)
    );
\mem_reg_0_15_18_23_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(254),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(254)
    );
\mem_reg_0_15_18_23_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(246),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(246)
    );
mem_reg_0_15_24_29_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cke(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_cke(3),
      O => \rd_ptr_timing_reg[0]_7\(1)
    );
\mem_reg_0_15_24_29_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(22),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      O => phy_dout(9)
    );
\mem_reg_0_15_24_29_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(5),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(11),
      O => \rd_ptr_timing_reg[0]_8\(10)
    );
\mem_reg_0_15_24_29_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(62),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(62)
    );
\mem_reg_0_15_24_29_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(59),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(59)
    );
\mem_reg_0_15_24_29_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(55),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(55)
    );
\mem_reg_0_15_24_29_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(50),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(50)
    );
\mem_reg_0_15_24_29_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(46),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(46)
    );
\mem_reg_0_15_24_29_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(43),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(43)
    );
\mem_reg_0_15_24_29_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(39),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(39)
    );
\mem_reg_0_15_24_29_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(35),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(35)
    );
mem_reg_0_15_24_29_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(10),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      O => phy_dout(8)
    );
\mem_reg_0_15_24_29_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(2),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(11),
      O => \rd_ptr_timing_reg[0]_8\(9)
    );
\mem_reg_0_15_24_29_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(26),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(26)
    );
\mem_reg_0_15_24_29_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(22),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(22)
    );
\mem_reg_0_15_24_29_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(10),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(10)
    );
\mem_reg_0_15_24_29_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(6),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(6)
    );
\mem_reg_0_15_24_29_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(2),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(2)
    );
mem_reg_0_15_24_29_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      O => phy_dout(11)
    );
\mem_reg_0_15_24_29_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24\,
      I1 => phy_bank(11),
      O => \rd_ptr_timing_reg[0]_8\(12)
    );
\mem_reg_0_15_24_29_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(157),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(157)
    );
\mem_reg_0_15_24_29_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(152),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(152)
    );
\mem_reg_0_15_24_29_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(146),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(146)
    );
\mem_reg_0_15_24_29_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(139),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(139)
    );
\mem_reg_0_15_24_29_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(133),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(133)
    );
\mem_reg_0_15_24_29_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(128),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(128)
    );
\mem_reg_0_15_24_29_i_3__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(122),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(122)
    );
\mem_reg_0_15_24_29_i_3__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(116),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(116)
    );
mem_reg_0_15_24_29_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(33),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      O => phy_dout(10)
    );
\mem_reg_0_15_24_29_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(8),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(11),
      O => \rd_ptr_timing_reg[0]_8\(11)
    );
\mem_reg_0_15_24_29_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(109),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(109)
    );
\mem_reg_0_15_24_29_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(91),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(91)
    );
\mem_reg_0_15_24_29_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(85),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(85)
    );
mem_reg_0_15_24_29_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(237),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(237)
    );
\mem_reg_0_15_24_29_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(232),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(232)
    );
\mem_reg_0_15_24_29_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(226),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(226)
    );
\mem_reg_0_15_24_29_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(219),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(219)
    );
\mem_reg_0_15_24_29_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(213),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(213)
    );
\mem_reg_0_15_24_29_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(208),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(208)
    );
\mem_reg_0_15_24_29_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(202),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(202)
    );
\mem_reg_0_15_24_29_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(196),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(196)
    );
mem_reg_0_15_24_29_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(190),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(190)
    );
\mem_reg_0_15_24_29_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(178),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(178)
    );
\mem_reg_0_15_24_29_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(174),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(174)
    );
\mem_reg_0_15_30_35_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(12),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      O => \rd_ptr_timing_reg[0]_8\(14)
    );
\mem_reg_0_15_30_35_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(343),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(343)
    );
\mem_reg_0_15_30_35_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(337),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(337)
    );
\mem_reg_0_15_30_35_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(319),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(319)
    );
\mem_reg_0_15_30_35_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(313),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(313)
    );
\mem_reg_0_15_30_35_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(307),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(307)
    );
\mem_reg_0_15_30_35_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(0),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      O => \rd_ptr_timing_reg[0]_8\(13)
    );
\mem_reg_0_15_30_35_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(300),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(300)
    );
\mem_reg_0_15_30_35_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(293),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(293)
    );
\mem_reg_0_15_30_35_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(285),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(285)
    );
\mem_reg_0_15_30_35_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(276),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(276)
    );
\mem_reg_0_15_30_35_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(268),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(268)
    );
\mem_reg_0_15_30_35_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(261),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(261)
    );
\mem_reg_0_15_30_35_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(253),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(253)
    );
\mem_reg_0_15_30_35_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(245),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(245)
    );
mem_reg_0_15_30_35_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      O => \rd_ptr_timing_reg[0]_8\(16)
    );
\mem_reg_0_15_30_35_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(58),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(58)
    );
\mem_reg_0_15_30_35_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(54),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(54)
    );
\mem_reg_0_15_30_35_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(42),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(42)
    );
\mem_reg_0_15_30_35_i_3__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(38),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(38)
    );
\mem_reg_0_15_30_35_i_3__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(34),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(34)
    );
mem_reg_0_15_30_35_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(23),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      O => \rd_ptr_timing_reg[0]_8\(15)
    );
mem_reg_0_15_30_35_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(156),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(156)
    );
\mem_reg_0_15_30_35_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(151),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(151)
    );
\mem_reg_0_15_30_35_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(145),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(145)
    );
\mem_reg_0_15_30_35_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(138),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(138)
    );
\mem_reg_0_15_30_35_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(132),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(132)
    );
\mem_reg_0_15_30_35_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(127),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(127)
    );
\mem_reg_0_15_30_35_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(121),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(121)
    );
\mem_reg_0_15_30_35_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(115),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(115)
    );
mem_reg_0_15_30_35_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(108),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(108)
    );
\mem_reg_0_15_30_35_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(103),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(103)
    );
\mem_reg_0_15_30_35_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(97),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(97)
    );
\mem_reg_0_15_30_35_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(90),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(90)
    );
\mem_reg_0_15_30_35_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(84),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(84)
    );
\mem_reg_0_15_30_35_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(79),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(79)
    );
\mem_reg_0_15_30_35_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(73),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(73)
    );
\mem_reg_0_15_30_35_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(67),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(67)
    );
mem_reg_0_15_36_41_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => phy_cs_n(1),
      O => \rd_ptr_timing_reg[0]_7\(2)
    );
\mem_reg_0_15_36_41_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      O => phy_dout(13)
    );
\mem_reg_0_15_36_41_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(13),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      O => \rd_ptr_timing_reg[0]_8\(18)
    );
\mem_reg_0_15_36_41_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(231),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(231)
    );
\mem_reg_0_15_36_41_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(225),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(225)
    );
\mem_reg_0_15_36_41_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(207),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(207)
    );
\mem_reg_0_15_36_41_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(201),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(201)
    );
\mem_reg_0_15_36_41_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(195),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(195)
    );
\mem_reg_0_15_36_41_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(11),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      O => phy_dout(12)
    );
\mem_reg_0_15_36_41_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(1),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      O => \rd_ptr_timing_reg[0]_8\(17)
    );
\mem_reg_0_15_36_41_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(189),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(189)
    );
\mem_reg_0_15_36_41_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(186),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(186)
    );
\mem_reg_0_15_36_41_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(182),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(182)
    );
\mem_reg_0_15_36_41_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(177),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(177)
    );
\mem_reg_0_15_36_41_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(173),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(173)
    );
\mem_reg_0_15_36_41_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(170),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(170)
    );
\mem_reg_0_15_36_41_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(166),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(166)
    );
\mem_reg_0_15_36_41_i_2__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(162),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(162)
    );
mem_reg_0_15_36_41_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(348),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(348)
    );
\mem_reg_0_15_36_41_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(330),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(330)
    );
\mem_reg_0_15_36_41_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(324),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(324)
    );
mem_reg_0_15_36_41_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(299),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(299)
    );
\mem_reg_0_15_36_41_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(292),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(292)
    );
\mem_reg_0_15_36_41_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(284),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(284)
    );
\mem_reg_0_15_36_41_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(275),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(275)
    );
\mem_reg_0_15_36_41_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(267),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(267)
    );
\mem_reg_0_15_36_41_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(260),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(260)
    );
\mem_reg_0_15_36_41_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(252),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(252)
    );
\mem_reg_0_15_36_41_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(244),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(244)
    );
mem_reg_0_15_36_41_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(29),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(29)
    );
\mem_reg_0_15_36_41_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(17),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(17)
    );
\mem_reg_0_15_36_41_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(13),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(13)
    );
\mem_reg_0_15_42_47_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      O => phy_dout(15)
    );
\mem_reg_0_15_42_47_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      O => \rd_ptr_timing_reg[0]_8\(20)
    );
\mem_reg_0_15_42_47_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(144),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(144)
    );
\mem_reg_0_15_42_47_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(120),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(120)
    );
\mem_reg_0_15_42_47_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(114),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(114)
    );
mem_reg_0_15_42_47_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[1]\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => phy_we_n(1),
      O => \rd_ptr_timing_reg[0]_7\(3)
    );
\mem_reg_0_15_42_47_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(34),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      O => phy_dout(14)
    );
\mem_reg_0_15_42_47_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(24),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      O => \rd_ptr_timing_reg[0]_8\(19)
    );
\mem_reg_0_15_42_47_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(107),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(107)
    );
\mem_reg_0_15_42_47_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(96),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(96)
    );
\mem_reg_0_15_42_47_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(89),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(89)
    );
\mem_reg_0_15_42_47_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(83),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(83)
    );
\mem_reg_0_15_42_47_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(72),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(72)
    );
\mem_reg_0_15_42_47_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(66),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(66)
    );
\mem_reg_0_15_42_47_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(14),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      O => \rd_ptr_timing_reg[0]_8\(22)
    );
\mem_reg_0_15_42_47_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(236),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(236)
    );
\mem_reg_0_15_42_47_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(218),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(218)
    );
\mem_reg_0_15_42_47_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(212),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(212)
    );
\mem_reg_0_15_42_47_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(2),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      O => \rd_ptr_timing_reg[0]_8\(21)
    );
\mem_reg_0_15_42_47_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(181),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(181)
    );
\mem_reg_0_15_42_47_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(165),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(165)
    );
\mem_reg_0_15_42_47_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(161),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(161)
    );
mem_reg_0_15_42_47_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      O => \rd_ptr_timing_reg[0]_8\(24)
    );
\mem_reg_0_15_42_47_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(347),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(347)
    );
\mem_reg_0_15_42_47_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(336),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(336)
    );
\mem_reg_0_15_42_47_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(329),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(329)
    );
\mem_reg_0_15_42_47_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(323),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(323)
    );
\mem_reg_0_15_42_47_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(312),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(312)
    );
\mem_reg_0_15_42_47_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(306),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(306)
    );
mem_reg_0_15_42_47_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(25),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      O => \rd_ptr_timing_reg[0]_8\(23)
    );
\mem_reg_0_15_42_47_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(298),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(298)
    );
\mem_reg_0_15_42_47_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(283),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(283)
    );
\mem_reg_0_15_42_47_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(274),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(274)
    );
\mem_reg_0_15_42_47_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(266),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(266)
    );
\mem_reg_0_15_42_47_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(251),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(251)
    );
\mem_reg_0_15_42_47_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(243),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(243)
    );
mem_reg_0_15_48_53_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => phy_cas_n(1),
      O => \rd_ptr_timing_reg[0]_7\(4)
    );
\mem_reg_0_15_48_53_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(16),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \rd_ptr_timing_reg[0]_8\(26)
    );
\mem_reg_0_15_48_53_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(61),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(61)
    );
\mem_reg_0_15_48_53_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(49),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(49)
    );
\mem_reg_0_15_48_53_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(45),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(45)
    );
\mem_reg_0_15_48_53_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(4),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \rd_ptr_timing_reg[0]_8\(25)
    );
\mem_reg_0_15_48_53_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(28),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(28)
    );
\mem_reg_0_15_48_53_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(21),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(21)
    );
\mem_reg_0_15_48_53_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(16),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(16)
    );
\mem_reg_0_15_48_53_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(12),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(12)
    );
\mem_reg_0_15_48_53_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(5),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(5)
    );
\mem_reg_0_15_48_53_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(1),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(1)
    );
mem_reg_0_15_48_53_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \rd_ptr_timing_reg[0]_8\(28)
    );
\mem_reg_0_15_48_53_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(155),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(155)
    );
\mem_reg_0_15_48_53_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(150),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(150)
    );
\mem_reg_0_15_48_53_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(137),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(137)
    );
\mem_reg_0_15_48_53_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(131),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(131)
    );
\mem_reg_0_15_48_53_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(126),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(126)
    );
mem_reg_0_15_48_53_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(27),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      O => \rd_ptr_timing_reg[0]_8\(27)
    );
\mem_reg_0_15_48_53_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(102),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(102)
    );
\mem_reg_0_15_48_53_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(95),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(95)
    );
\mem_reg_0_15_48_53_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(78),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(78)
    );
\mem_reg_0_15_48_53_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(71),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(71)
    );
\mem_reg_0_15_48_53_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(65),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(65)
    );
mem_reg_0_15_48_53_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(15),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \rd_ptr_timing_reg[0]_8\(30)
    );
\mem_reg_0_15_48_53_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(235),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(235)
    );
\mem_reg_0_15_48_53_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(224),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(224)
    );
\mem_reg_0_15_48_53_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(217),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(217)
    );
\mem_reg_0_15_48_53_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(211),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(211)
    );
\mem_reg_0_15_48_53_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(200),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(200)
    );
\mem_reg_0_15_48_53_i_5__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(194),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(194)
    );
mem_reg_0_15_48_53_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(3),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \rd_ptr_timing_reg[0]_8\(29)
    );
\mem_reg_0_15_48_53_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(185),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(185)
    );
\mem_reg_0_15_48_53_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(169),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(169)
    );
\mem_reg_0_15_54_59_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \rd_ptr_timing_reg[0]_8\(32)
    );
\mem_reg_0_15_54_59_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(346),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(346)
    );
\mem_reg_0_15_54_59_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(342),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(342)
    );
\mem_reg_0_15_54_59_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(335),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(335)
    );
\mem_reg_0_15_54_59_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(328),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(328)
    );
\mem_reg_0_15_54_59_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(322),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(322)
    );
\mem_reg_0_15_54_59_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(318),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(318)
    );
\mem_reg_0_15_54_59_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(311),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(311)
    );
\mem_reg_0_15_54_59_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(305),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(305)
    );
mem_reg_0_15_54_59_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(26),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      O => \rd_ptr_timing_reg[0]_8\(31)
    );
\mem_reg_0_15_54_59_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(297),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(297)
    );
\mem_reg_0_15_54_59_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(291),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(291)
    );
\mem_reg_0_15_54_59_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(282),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(282)
    );
\mem_reg_0_15_54_59_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(273),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(273)
    );
\mem_reg_0_15_54_59_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(265),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(265)
    );
\mem_reg_0_15_54_59_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(259),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(259)
    );
\mem_reg_0_15_54_59_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(250),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(250)
    );
\mem_reg_0_15_54_59_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(242),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(242)
    );
mem_reg_0_15_54_59_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(17),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      O => \rd_ptr_timing_reg[0]_8\(34)
    );
\mem_reg_0_15_54_59_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(60),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(60)
    );
\mem_reg_0_15_54_59_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(53),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(53)
    );
\mem_reg_0_15_54_59_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(48),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(48)
    );
\mem_reg_0_15_54_59_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(44),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(44)
    );
\mem_reg_0_15_54_59_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(37),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(37)
    );
\mem_reg_0_15_54_59_i_3__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(33),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(33)
    );
mem_reg_0_15_54_59_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(5),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      O => \rd_ptr_timing_reg[0]_8\(33)
    );
\mem_reg_0_15_54_59_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(25),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(25)
    );
\mem_reg_0_15_54_59_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(20),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(20)
    );
\mem_reg_0_15_54_59_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(9),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(9)
    );
\mem_reg_0_15_54_59_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(4),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(4)
    );
\mem_reg_0_15_54_59_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(0),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(0)
    );
mem_reg_0_15_54_59_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      O => \rd_ptr_timing_reg[0]_8\(36)
    );
\mem_reg_0_15_54_59_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(154),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(154)
    );
\mem_reg_0_15_54_59_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(143),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(143)
    );
\mem_reg_0_15_54_59_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(136),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(136)
    );
\mem_reg_0_15_54_59_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(130),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(130)
    );
\mem_reg_0_15_54_59_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(119),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(119)
    );
\mem_reg_0_15_54_59_i_5__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(113),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(113)
    );
mem_reg_0_15_54_59_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(28),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      O => \rd_ptr_timing_reg[0]_8\(35)
    );
\mem_reg_0_15_54_59_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(106),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(106)
    );
\mem_reg_0_15_54_59_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(101),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(101)
    );
\mem_reg_0_15_54_59_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(88),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(88)
    );
\mem_reg_0_15_54_59_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(82),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(82)
    );
\mem_reg_0_15_54_59_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(77),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(77)
    );
mem_reg_0_15_60_65_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(18),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      O => \rd_ptr_timing_reg[0]_8\(38)
    );
\mem_reg_0_15_60_65_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(234),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(234)
    );
\mem_reg_0_15_60_65_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(230),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(230)
    );
\mem_reg_0_15_60_65_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(223),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(223)
    );
\mem_reg_0_15_60_65_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(216),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(216)
    );
\mem_reg_0_15_60_65_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(210),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(210)
    );
\mem_reg_0_15_60_65_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(206),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(206)
    );
\mem_reg_0_15_60_65_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(199),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(199)
    );
\mem_reg_0_15_60_65_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(193),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(193)
    );
mem_reg_0_15_60_65_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(6),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      O => \rd_ptr_timing_reg[0]_8\(37)
    );
\mem_reg_0_15_60_65_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(188),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(188)
    );
\mem_reg_0_15_60_65_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(176),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(176)
    );
\mem_reg_0_15_60_65_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(172),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(172)
    );
\mem_reg_0_15_60_65_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(341),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(341)
    );
\mem_reg_0_15_60_65_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(334),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(334)
    );
\mem_reg_0_15_60_65_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(317),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(510),
      O => mux_wrdata(317)
    );
\mem_reg_0_15_60_65_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(310),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(310)
    );
\mem_reg_0_15_60_65_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(304),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(304)
    );
mem_reg_0_15_60_65_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(296),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(296)
    );
\mem_reg_0_15_60_65_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(290),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(290)
    );
\mem_reg_0_15_60_65_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(281),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(281)
    );
\mem_reg_0_15_60_65_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(272),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(272)
    );
\mem_reg_0_15_60_65_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(264),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(264)
    );
\mem_reg_0_15_60_65_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(258),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(258)
    );
\mem_reg_0_15_60_65_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(249),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(249)
    );
\mem_reg_0_15_60_65_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(241),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(241)
    );
mem_reg_0_15_60_65_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(57),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(57)
    );
\mem_reg_0_15_60_65_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(52),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(52)
    );
\mem_reg_0_15_60_65_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(41),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(125),
      O => mux_wrdata(41)
    );
\mem_reg_0_15_60_65_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(36),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(36)
    );
\mem_reg_0_15_60_65_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(32),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(32)
    );
mem_reg_0_15_60_65_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(24),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(24)
    );
\mem_reg_0_15_60_65_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(8),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(61),
      O => mux_wrdata(8)
    );
mem_reg_0_15_66_71_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      O => \rd_ptr_timing_reg[0]_8\(40)
    );
\mem_reg_0_15_66_71_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(149),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(149)
    );
\mem_reg_0_15_66_71_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(142),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(142)
    );
\mem_reg_0_15_66_71_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(125),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(125)
    );
\mem_reg_0_15_66_71_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(118),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(118)
    );
\mem_reg_0_15_66_71_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(112),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(112)
    );
mem_reg_0_15_66_71_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(29),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      O => \rd_ptr_timing_reg[0]_8\(39)
    );
\mem_reg_0_15_66_71_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(94),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(94)
    );
\mem_reg_0_15_66_71_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(70),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(70)
    );
\mem_reg_0_15_66_71_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(64),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(64)
    );
mem_reg_0_15_66_71_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(229),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(229)
    );
\mem_reg_0_15_66_71_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(222),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(222)
    );
\mem_reg_0_15_66_71_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(205),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(205)
    );
\mem_reg_0_15_66_71_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(198),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(198)
    );
\mem_reg_0_15_66_71_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(192),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(192)
    );
\mem_reg_0_15_66_71_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(180),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(180)
    );
\mem_reg_0_15_66_71_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(164),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(164)
    );
\mem_reg_0_15_66_71_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(160),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(160)
    );
mem_reg_0_15_66_71_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(340),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(340)
    );
\mem_reg_0_15_66_71_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(316),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(316)
    );
mem_reg_0_15_66_71_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(289),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(289)
    );
\mem_reg_0_15_66_71_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(280),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(280)
    );
\mem_reg_0_15_66_71_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(257),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(257)
    );
\mem_reg_0_15_66_71_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(248),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(248)
    );
\mem_reg_0_15_66_71_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(240),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(240)
    );
mem_reg_0_15_6_11_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_odt(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_odt(0),
      O => \rd_ptr_timing_reg[0]_7\(0)
    );
\mem_reg_0_15_6_11_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(20),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      O => phy_dout(1)
    );
\mem_reg_0_15_6_11_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(3),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(9),
      O => \rd_ptr_timing_reg[0]_8\(2)
    );
\mem_reg_0_15_6_11_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(351),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(351)
    );
\mem_reg_0_15_6_11_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(333),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(333)
    );
\mem_reg_0_15_6_11_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(327),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_wrdata(511),
      O => mux_wrdata(327)
    );
mem_reg_0_15_6_11_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(8),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      O => phy_dout(0)
    );
\mem_reg_0_15_6_11_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(0),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(9),
      O => \rd_ptr_timing_reg[0]_8\(1)
    );
\mem_reg_0_15_6_11_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(303),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(303)
    );
\mem_reg_0_15_6_11_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(279),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(279)
    );
\mem_reg_0_15_6_11_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(271),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(271)
    );
mem_reg_0_15_6_11_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      O => phy_dout(3)
    );
\mem_reg_0_15_6_11_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24\,
      I1 => phy_bank(9),
      O => \rd_ptr_timing_reg[0]_8\(4)
    );
\mem_reg_0_15_6_11_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(153),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(153)
    );
\mem_reg_0_15_6_11_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(147),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(147)
    );
\mem_reg_0_15_6_11_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(129),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(129)
    );
\mem_reg_0_15_6_11_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(123),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(123)
    );
\mem_reg_0_15_6_11_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(117),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(117)
    );
mem_reg_0_15_6_11_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(31),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      O => phy_dout(2)
    );
\mem_reg_0_15_6_11_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_bank(6),
      I1 => \init_calib_complete_reg_rep__24\,
      I2 => phy_bank(9),
      O => \rd_ptr_timing_reg[0]_8\(3)
    );
\mem_reg_0_15_6_11_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(105),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(105)
    );
\mem_reg_0_15_6_11_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(99),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(99)
    );
\mem_reg_0_15_6_11_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(81),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(81)
    );
\mem_reg_0_15_6_11_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(75),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(75)
    );
\mem_reg_0_15_6_11_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(69),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(69)
    );
\mem_reg_0_15_6_11_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(31),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(31)
    );
\mem_reg_0_15_6_11_i_4__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(19),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(19)
    );
\mem_reg_0_15_6_11_i_4__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(15),
      I1 => \init_calib_complete_reg_rep__14\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(15)
    );
mem_reg_0_15_6_11_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(110),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(110)
    );
\mem_reg_0_15_6_11_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(92),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(92)
    );
\mem_reg_0_15_6_11_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(86),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(86)
    );
mem_reg_0_15_72_77_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(19),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      O => \rd_ptr_timing_reg[0]_8\(42)
    );
\mem_reg_0_15_72_77_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(56),
      I1 => \init_calib_complete_reg_rep__16\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(56)
    );
\mem_reg_0_15_72_77_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(40),
      I1 => \init_calib_complete_reg_rep__15\,
      I2 => phy_wrdata(190),
      O => mux_wrdata(40)
    );
mem_reg_0_15_72_77_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(7),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      O => \rd_ptr_timing_reg[0]_8\(41)
    );
mem_reg_0_15_72_77_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      O => \rd_ptr_timing_reg[0]_8\(44)
    );
\mem_reg_0_15_72_77_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(148),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(148)
    );
\mem_reg_0_15_72_77_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(124),
      I1 => \init_calib_complete_reg_rep__18\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(124)
    );
mem_reg_0_15_72_77_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_address(30),
      I1 => \init_calib_complete_reg_rep__25\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      O => \rd_ptr_timing_reg[0]_8\(43)
    );
\mem_reg_0_15_72_77_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(100),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(100)
    );
\mem_reg_0_15_72_77_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(76),
      I1 => \init_calib_complete_reg_rep__17\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(76)
    );
mem_reg_0_15_72_77_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(228),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      O => mux_wrdata(228)
    );
\mem_reg_0_15_72_77_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(204),
      I1 => \init_calib_complete_reg_rep__21\,
      I2 => phy_wrdata(445),
      O => mux_wrdata(204)
    );
mem_reg_0_15_72_77_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(184),
      I1 => \init_calib_complete_reg_rep__20\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(184)
    );
\mem_reg_0_15_72_77_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(168),
      I1 => \init_calib_complete_reg_rep__19\,
      I2 => phy_wrdata(505),
      O => mux_wrdata(168)
    );
mem_reg_0_15_78_79_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(288),
      I1 => \init_calib_complete_reg_rep__23\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(288)
    );
\mem_reg_0_15_78_79_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(256),
      I1 => \init_calib_complete_reg_rep__22\,
      I2 => phy_wrdata(447),
      O => mux_wrdata(256)
    );
mpr_rdlvl_start_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000020"
    )
        port map (
      I0 => pi_dqs_found_done,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => mpr_rdlvl_start_i_2_n_0,
      I4 => mpr_rdlvl_start_i_3_n_0,
      I5 => \^mpr_rdlvl_start_r_reg\,
      O => mpr_rdlvl_start_i_1_n_0
    );
mpr_rdlvl_start_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => mpr_rdlvl_start_i_2_n_0
    );
mpr_rdlvl_start_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      O => mpr_rdlvl_start_i_3_n_0
    );
mpr_rdlvl_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mpr_rdlvl_start_i_1_n_0,
      Q => \^mpr_rdlvl_start_r_reg\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\num_refresh[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \num_refresh_reg__0\(0),
      O => \p_0_in__5\(0)
    );
\num_refresh[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \num_refresh_reg__0\(1),
      I1 => \num_refresh_reg__0\(0),
      O => \p_0_in__5\(1)
    );
\num_refresh[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \num_refresh_reg__0\(2),
      I1 => \num_refresh_reg__0\(0),
      I2 => \num_refresh_reg__0\(1),
      O => \p_0_in__5\(2)
    );
\num_refresh[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEFFEEFFEE"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      I2 => \num_refresh[3]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => complex_oclkdelay_calib_start_int_i_2_n_0,
      O => \num_refresh[3]_i_1_n_0\
    );
\num_refresh[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0A8A"
    )
        port map (
      I0 => \num_refresh[3]_i_5_n_0\,
      I1 => \^wrlvl_done_r1\,
      I2 => pi_dqs_found_done,
      I3 => rdlvl_stg1_done_reg,
      O => num_refresh0
    );
\num_refresh[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \num_refresh_reg__0\(3),
      I1 => \num_refresh_reg__0\(1),
      I2 => \num_refresh_reg__0\(0),
      I3 => \num_refresh_reg__0\(2),
      O => \p_0_in__5\(3)
    );
\num_refresh[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFDFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      O => \num_refresh[3]_i_4_n_0\
    );
\num_refresh[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \init_state_r[0]_i_3_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \num_refresh[3]_i_5_n_0\
    );
\num_refresh_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__5\(0),
      Q => \num_refresh_reg__0\(0),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__5\(1),
      Q => \num_refresh_reg__0\(1),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__5\(2),
      Q => \num_refresh_reg__0\(2),
      R => \num_refresh[3]_i_1_n_0\
    );
\num_refresh_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => num_refresh0,
      D => \p_0_in__5\(3),
      Q => \num_refresh_reg__0\(3),
      R => \num_refresh[3]_i_1_n_0\
    );
\ocal_act_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ocal_act_wait_cnt_reg__0\(0),
      O => \p_0_in__8\(0)
    );
\ocal_act_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ocal_act_wait_cnt_reg__0\(1),
      I1 => \ocal_act_wait_cnt_reg__0\(0),
      O => \p_0_in__8\(1)
    );
\ocal_act_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \ocal_act_wait_cnt_reg__0\(2),
      I1 => \ocal_act_wait_cnt_reg__0\(0),
      I2 => \ocal_act_wait_cnt_reg__0\(1),
      O => \p_0_in__8\(2)
    );
\ocal_act_wait_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \init_state_r[4]_i_6_n_0\,
      I1 => init_state_r(6),
      I2 => \rstdiv0_sync_r1_reg_rep__22\,
      I3 => \ocal_act_wait_cnt[3]_i_3_n_0\,
      O => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \ocal_act_wait_cnt_reg__0\(3),
      I1 => \ocal_act_wait_cnt_reg__0\(1),
      I2 => \ocal_act_wait_cnt_reg__0\(0),
      I3 => \ocal_act_wait_cnt_reg__0\(2),
      O => \p_0_in__8\(3)
    );
\ocal_act_wait_cnt[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \init_state_r_reg_n_0_[3]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \ocal_act_wait_cnt[3]_i_3_n_0\
    );
\ocal_act_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__8\(0),
      Q => \ocal_act_wait_cnt_reg__0\(0),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__8\(1),
      Q => \ocal_act_wait_cnt_reg__0\(1),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__8\(2),
      Q => \ocal_act_wait_cnt_reg__0\(2),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\ocal_act_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__8\(3),
      Q => \ocal_act_wait_cnt_reg__0\(3),
      R => \ocal_act_wait_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \oclk_wr_cnt_reg__0\(0),
      O => \oclk_wr_cnt[0]_i_1_n_0\
    );
\oclk_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \oclk_wr_cnt_reg__0\(0),
      I1 => \oclk_wr_cnt_reg__0\(1),
      O => \oclk_wr_cnt[1]_i_1_n_0\
    );
\oclk_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \oclk_wr_cnt_reg__0\(2),
      I1 => \oclk_wr_cnt_reg__0\(1),
      I2 => \oclk_wr_cnt_reg__0\(0),
      O => oclk_wr_cnt0(2)
    );
\oclk_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAAB"
    )
        port map (
      I0 => \oclk_wr_cnt[3]_i_4_n_0\,
      I1 => \oclk_wr_cnt_reg__0\(1),
      I2 => \oclk_wr_cnt_reg__0\(0),
      I3 => \oclk_wr_cnt_reg__0\(3),
      I4 => \oclk_wr_cnt_reg__0\(2),
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => \oclk_wr_cnt[3]_i_5_n_0\,
      O => p_0_in0_in
    );
\oclk_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \oclk_wr_cnt_reg__0\(3),
      I1 => \oclk_wr_cnt_reg__0\(2),
      I2 => \oclk_wr_cnt_reg__0\(0),
      I3 => \oclk_wr_cnt_reg__0\(1),
      O => oclk_wr_cnt0(3)
    );
\oclk_wr_cnt[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \wrcal_reads[7]_i_6_n_0\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => \oclk_wr_cnt[3]_i_4_n_0\
    );
\oclk_wr_cnt[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      O => \oclk_wr_cnt[3]_i_5_n_0\
    );
\oclk_wr_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in0_in,
      D => \oclk_wr_cnt[0]_i_1_n_0\,
      Q => \oclk_wr_cnt_reg__0\(0),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in0_in,
      D => \oclk_wr_cnt[1]_i_1_n_0\,
      Q => \oclk_wr_cnt_reg__0\(1),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => p_0_in0_in,
      D => oclk_wr_cnt0(2),
      Q => \oclk_wr_cnt_reg__0\(2),
      S => \oclk_wr_cnt[3]_i_1_n_0\
    );
\oclk_wr_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_0_in0_in,
      D => oclk_wr_cnt0(3),
      Q => \oclk_wr_cnt_reg__0\(3),
      R => \oclk_wr_cnt[3]_i_1_n_0\
    );
\odd_cwl.phy_cas_n[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\,
      I1 => reg_ctrl_cnt_r,
      I2 => \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0\,
      I3 => \num_refresh[3]_i_5_n_0\,
      O => \odd_cwl.phy_cas_n[1]_i_1_n_0\
    );
\odd_cwl.phy_cas_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \odd_cwl.phy_cas_n[1]_i_1_n_0\,
      Q => phy_cas_n(1),
      R => '0'
    );
\odd_cwl.phy_ras_n[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0\,
      I1 => \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0\,
      I2 => \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\,
      I3 => reg_ctrl_cnt_r,
      O => \odd_cwl.phy_ras_n[1]_i_1_n_0\
    );
\odd_cwl.phy_ras_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \odd_cwl.phy_ras_n[1]_i_1_n_0\,
      Q => phy_ras_n(1),
      R => '0'
    );
\odd_cwl.phy_we_n[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0\,
      I1 => reg_ctrl_cnt_r,
      I2 => phy_wrdata_en,
      I3 => p_94_out,
      O => \odd_cwl.phy_we_n[1]_i_1_n_0\
    );
\odd_cwl.phy_we_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \odd_cwl.phy_we_n[1]_i_1_n_0\,
      Q => phy_we_n(1),
      R => '0'
    );
\one_rank.stg1_wr_done_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000054"
    )
        port map (
      I0 => rdlvl_last_byte_done,
      I1 => \^one_rank.stg1_wr_done_reg_0\,
      I2 => \^stg1_wr_done\,
      I3 => \^complex_row1_rd_cnt_reg[1]_0\,
      I4 => complex_byte_rd_done,
      I5 => ddr2_pre_flag_r,
      O => \one_rank.stg1_wr_done_i_1_n_0\
    );
\one_rank.stg1_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \one_rank.stg1_wr_done_i_1_n_0\,
      Q => \^one_rank.stg1_wr_done_reg_0\,
      R => '0'
    );
\out_fifo_i_10__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_odt(0),
      I3 => mem_out(3),
      I4 => \my_empty_reg[1]\,
      O => D1(3)
    );
\out_fifo_i_10__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(350),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_0\(9),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_0\(4)
    );
\out_fifo_i_10__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(345),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_1\(4),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_5\(4)
    );
\out_fifo_i_10__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(339),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_2\(4),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_11\(4)
    );
\out_fifo_i_10__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(332),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_3\(9),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_18\(4)
    );
\out_fifo_i_10__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(326),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_4\(9),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_24\(4)
    );
\out_fifo_i_10__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(321),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_5\(4),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_29\(4)
    );
\out_fifo_i_10__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(315),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_6\(4),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_35\(4)
    );
\out_fifo_i_10__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(309),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_7\(4),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_41\(4)
    );
\out_fifo_i_11__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_odt(0),
      I3 => mem_out(2),
      I4 => \my_empty_reg[1]\,
      O => D1(2)
    );
\out_fifo_i_11__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(302),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_0\(8),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_0\(3)
    );
\out_fifo_i_11__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(295),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(3),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_5\(3)
    );
\out_fifo_i_11__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(287),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(3),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_11\(3)
    );
\out_fifo_i_11__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(278),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_3\(8),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_18\(3)
    );
\out_fifo_i_11__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(270),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_4\(8),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_24\(3)
    );
\out_fifo_i_11__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(263),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(3),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_29\(3)
    );
\out_fifo_i_11__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(255),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(3),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_35\(3)
    );
\out_fifo_i_11__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(247),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(3),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_41\(3)
    );
\out_fifo_i_12__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_odt(0),
      I3 => mem_out(1),
      I4 => \my_empty_reg[1]\,
      O => D1(1)
    );
\out_fifo_i_12__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(239),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_0\(7),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_0\(2)
    );
\out_fifo_i_12__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(221),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_3\(7),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_18\(2)
    );
\out_fifo_i_12__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(215),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_4\(7),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_24\(2)
    );
\out_fifo_i_13__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_odt(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_odt(0),
      I3 => mem_out(0),
      I4 => \my_empty_reg[1]\,
      O => D1(0)
    );
\out_fifo_i_13__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(187),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(2),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_5\(2)
    );
\out_fifo_i_13__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(183),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(2),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_11\(2)
    );
\out_fifo_i_13__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(171),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(2),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_29\(2)
    );
\out_fifo_i_13__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(167),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(2),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_35\(2)
    );
\out_fifo_i_13__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(163),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(2),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_41\(2)
    );
\out_fifo_i_14__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I2 => init_calib_complete_reg_0(3),
      I3 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_1\(3)
    );
\out_fifo_i_14__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => phy_bank(9),
      I2 => \rd_ptr_reg[3]\(4),
      I3 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_6\(3)
    );
\out_fifo_i_14__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(153),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(1),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_5\(1)
    );
\out_fifo_i_14__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(147),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(1),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_11\(1)
    );
\out_fifo_i_14__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(129),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(1),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_29\(1)
    );
\out_fifo_i_14__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(123),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(1),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_35\(1)
    );
\out_fifo_i_14__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(117),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(1),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_41\(1)
    );
\out_fifo_i_15__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(31),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I3 => init_calib_complete_reg_0(2),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_1\(2)
    );
\out_fifo_i_15__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(6),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(9),
      I3 => \rd_ptr_reg[3]\(3),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_6\(2)
    );
\out_fifo_i_15__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(110),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_0\(6),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_0\(1)
    );
\out_fifo_i_15__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(105),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(0),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_5\(0)
    );
\out_fifo_i_15__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(99),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(0),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_11\(0)
    );
\out_fifo_i_15__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(92),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_3\(6),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_18\(1)
    );
\out_fifo_i_15__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(86),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_4\(6),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_24\(1)
    );
\out_fifo_i_15__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(81),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(0),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_29\(0)
    );
\out_fifo_i_15__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(75),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(0),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_35\(0)
    );
\out_fifo_i_15__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(69),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(0),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_41\(0)
    );
out_fifo_i_16: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_cke(3),
      I3 => mem_out(7),
      I4 => \my_empty_reg[1]\,
      O => D3(3)
    );
\out_fifo_i_16__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(20),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I3 => init_calib_complete_reg_0(1),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_1\(1)
    );
\out_fifo_i_16__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(3),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(9),
      I3 => \rd_ptr_reg[3]\(2),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_6\(1)
    );
out_fifo_i_17: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_cke(3),
      I3 => mem_out(6),
      I4 => \my_empty_reg[1]\,
      O => D3(2)
    );
\out_fifo_i_17__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(8),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\,
      I3 => init_calib_complete_reg_0(0),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_1\(0)
    );
\out_fifo_i_17__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(0),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(9),
      I3 => \rd_ptr_reg[3]\(1),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_6\(0)
    );
\out_fifo_i_17__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(31),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(5),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_0\(0)
    );
\out_fifo_i_17__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(19),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(5),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_18\(0)
    );
\out_fifo_i_17__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(15),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(5),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_24\(0)
    );
\out_fifo_i_18__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_cke(3),
      I3 => mem_out(5),
      I4 => \my_empty_reg[1]\,
      O => D3(1)
    );
\out_fifo_i_18__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(349),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(15),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_1\(5)
    );
\out_fifo_i_18__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(344),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_1\(9),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_6\(4)
    );
\out_fifo_i_18__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(338),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_2\(9),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_12\(4)
    );
\out_fifo_i_18__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(331),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(15),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_19\(5)
    );
\out_fifo_i_18__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(325),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(15),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_25\(5)
    );
\out_fifo_i_18__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(320),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_5\(9),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_30\(4)
    );
\out_fifo_i_18__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(314),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_6\(9),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_36\(4)
    );
\out_fifo_i_18__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(308),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_7\(9),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_42\(4)
    );
\out_fifo_i_19__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cke(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => calib_cke(3),
      I3 => mem_out(4),
      I4 => \my_empty_reg[1]\,
      O => D3(0)
    );
\out_fifo_i_19__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(301),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(14),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_1\(4)
    );
\out_fifo_i_19__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(294),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_1\(8),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_6\(3)
    );
\out_fifo_i_19__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(286),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_2\(8),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_12\(3)
    );
\out_fifo_i_19__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(277),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(14),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_19\(4)
    );
\out_fifo_i_19__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(269),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(14),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_25\(4)
    );
\out_fifo_i_19__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(262),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_5\(8),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_30\(3)
    );
\out_fifo_i_19__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(254),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_6\(8),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_36\(3)
    );
\out_fifo_i_19__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(246),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_7\(8),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_42\(3)
    );
\out_fifo_i_20__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(238),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(13),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_1\(3)
    );
\out_fifo_i_20__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(233),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_1\(7),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_6\(2)
    );
\out_fifo_i_20__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(227),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_2\(7),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_12\(2)
    );
\out_fifo_i_20__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(220),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(13),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_19\(3)
    );
\out_fifo_i_20__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(214),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(13),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_25\(3)
    );
\out_fifo_i_20__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(209),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_5\(7),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_30\(2)
    );
\out_fifo_i_20__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(203),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_6\(7),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_36\(2)
    );
\out_fifo_i_20__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(197),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_7\(7),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_42\(2)
    );
\out_fifo_i_22__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I2 => init_calib_complete_reg_0(7),
      I3 => \my_empty_reg[1]_1\,
      O => D2(3)
    );
\out_fifo_i_22__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => phy_bank(10),
      I2 => \rd_ptr_reg[3]\(8),
      I3 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_5\(3)
    );
\out_fifo_i_22__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(158),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(12),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_1\(2)
    );
\out_fifo_i_22__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(140),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(12),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_19\(2)
    );
\out_fifo_i_22__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(134),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(12),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_25\(2)
    );
\out_fifo_i_23__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(32),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I3 => init_calib_complete_reg_0(6),
      I4 => \my_empty_reg[1]_1\,
      O => D2(2)
    );
\out_fifo_i_23__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(7),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(10),
      I3 => \rd_ptr_reg[3]\(7),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_5\(2)
    );
\out_fifo_i_23__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(104),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_1\(6),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_6\(1)
    );
\out_fifo_i_23__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(98),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_2\(6),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_12\(1)
    );
\out_fifo_i_23__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(80),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_5\(6),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_30\(1)
    );
\out_fifo_i_23__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(74),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_6\(6),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_36\(1)
    );
\out_fifo_i_23__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(68),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_7\(6),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_42\(1)
    );
\out_fifo_i_24__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(21),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I3 => init_calib_complete_reg_0(5),
      I4 => \my_empty_reg[1]_1\,
      O => D2(1)
    );
\out_fifo_i_24__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(4),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(10),
      I3 => \rd_ptr_reg[3]\(6),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_5\(1)
    );
\out_fifo_i_24__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(63),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_0\(11),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_1\(1)
    );
\out_fifo_i_24__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(51),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_3\(11),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_19\(1)
    );
\out_fifo_i_24__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(47),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_4\(11),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_25\(1)
    );
\out_fifo_i_25__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(9),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\,
      I3 => init_calib_complete_reg_0(4),
      I4 => \my_empty_reg[1]_1\,
      O => D2(0)
    );
\out_fifo_i_25__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(1),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(10),
      I3 => \rd_ptr_reg[3]\(5),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_5\(0)
    );
\out_fifo_i_25__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(30),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_0\(10),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_1\(0)
    );
\out_fifo_i_25__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(27),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(5),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_6\(0)
    );
\out_fifo_i_25__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(23),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(5),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_12\(0)
    );
\out_fifo_i_25__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(18),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_3\(10),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_19\(0)
    );
\out_fifo_i_25__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(14),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_4\(10),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_25\(0)
    );
\out_fifo_i_25__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(11),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(5),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_30\(0)
    );
\out_fifo_i_25__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(7),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(5),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_36\(0)
    );
\out_fifo_i_25__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(3),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(5),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_42\(0)
    );
\out_fifo_i_26__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n_reg[1]\(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => phy_we_n(1),
      I3 => mem_out(9),
      I4 => \my_empty_reg[1]\,
      O => D5(1)
    );
\out_fifo_i_26__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(343),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(15),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_7\(5)
    );
\out_fifo_i_26__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(337),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(15),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_13\(5)
    );
\out_fifo_i_26__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(319),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(15),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_31\(5)
    );
\out_fifo_i_26__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(313),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(15),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_37\(5)
    );
\out_fifo_i_26__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(307),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(15),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_43\(5)
    );
\out_fifo_i_27__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(300),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(21),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_47\(5)
    );
\out_fifo_i_27__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(293),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(14),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_7\(4)
    );
\out_fifo_i_27__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(285),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(14),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_13\(4)
    );
\out_fifo_i_27__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(276),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(21),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_53\(5)
    );
\out_fifo_i_27__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(268),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(21),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_55\(5)
    );
\out_fifo_i_27__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(261),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(14),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_31\(4)
    );
\out_fifo_i_27__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(253),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(14),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_37\(4)
    );
\out_fifo_i_27__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(245),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(14),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_43\(4)
    );
\out_fifo_i_28__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(237),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(20),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_47\(4)
    );
\out_fifo_i_28__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(232),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(13),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_7\(3)
    );
\out_fifo_i_28__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(226),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(13),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_13\(3)
    );
\out_fifo_i_28__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(219),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(20),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_53\(4)
    );
\out_fifo_i_28__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(213),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(20),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_55\(4)
    );
\out_fifo_i_28__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(208),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(13),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_31\(3)
    );
\out_fifo_i_28__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(202),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(13),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_37\(3)
    );
\out_fifo_i_28__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(196),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(13),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_43\(3)
    );
\out_fifo_i_29__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(190),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(19),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_47\(3)
    );
\out_fifo_i_29__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(178),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(19),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_53\(3)
    );
\out_fifo_i_29__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(174),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(19),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_55\(3)
    );
\out_fifo_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(351),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_0\(4),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]\(4)
    );
\out_fifo_i_2__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(333),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_3\(4),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_17\(4)
    );
\out_fifo_i_2__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(327),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_4\(4),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_23\(4)
    );
out_fifo_i_30: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => phy_cs_n(1),
      I3 => mem_out(8),
      I4 => \my_empty_reg[1]\,
      O => D5(0)
    );
\out_fifo_i_30__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I2 => init_calib_complete_reg_0(11),
      I3 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_0\(3)
    );
\out_fifo_i_30__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__10\,
      I1 => phy_bank(11),
      I2 => \rd_ptr_reg[3]\(12),
      I3 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_4\(3)
    );
\out_fifo_i_30__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(157),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(18),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_47\(2)
    );
\out_fifo_i_30__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(152),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(12),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_7\(2)
    );
\out_fifo_i_30__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(146),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(12),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_13\(2)
    );
\out_fifo_i_30__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(139),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(18),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_53\(2)
    );
\out_fifo_i_30__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(133),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(18),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_55\(2)
    );
\out_fifo_i_30__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(128),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(12),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_31\(2)
    );
\out_fifo_i_30__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(122),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(12),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_37\(2)
    );
\out_fifo_i_30__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(116),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(12),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_43\(2)
    );
\out_fifo_i_31__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(33),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I3 => init_calib_complete_reg_0(10),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_0\(2)
    );
\out_fifo_i_31__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(8),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(11),
      I3 => \rd_ptr_reg[3]\(11),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_4\(2)
    );
\out_fifo_i_31__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(109),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(17),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_47\(1)
    );
\out_fifo_i_31__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(91),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(17),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_53\(1)
    );
\out_fifo_i_31__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(85),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(17),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_55\(1)
    );
\out_fifo_i_32__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(22),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I3 => init_calib_complete_reg_0(9),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_0\(1)
    );
\out_fifo_i_32__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(5),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(11),
      I3 => \rd_ptr_reg[3]\(10),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_4\(1)
    );
\out_fifo_i_32__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(62),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_0\(16),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_47\(0)
    );
\out_fifo_i_32__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(59),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_1\(11),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_7\(1)
    );
\out_fifo_i_32__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(55),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_2\(11),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_13\(1)
    );
\out_fifo_i_32__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(50),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_3\(16),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_53\(0)
    );
\out_fifo_i_32__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(46),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_4\(16),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_55\(0)
    );
\out_fifo_i_32__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(43),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_5\(11),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_31\(1)
    );
\out_fifo_i_32__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(39),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_6\(11),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_37\(1)
    );
\out_fifo_i_32__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(35),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_7\(11),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_43\(1)
    );
\out_fifo_i_33__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(10),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\,
      I3 => init_calib_complete_reg_0(8),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]_0\(0)
    );
\out_fifo_i_33__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_bank(2),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_bank(11),
      I3 => \rd_ptr_reg[3]\(9),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_4\(0)
    );
\out_fifo_i_33__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(26),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_1\(10),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_7\(0)
    );
\out_fifo_i_33__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(22),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_2\(10),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_13\(0)
    );
\out_fifo_i_33__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(10),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_5\(10),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_31\(0)
    );
\out_fifo_i_33__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(6),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_6\(10),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_37\(0)
    );
\out_fifo_i_33__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(2),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_7\(10),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_43\(0)
    );
\out_fifo_i_34__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => phy_cas_n(1),
      I3 => mem_out(10),
      I4 => \my_empty_reg[1]\,
      O => D6(0)
    );
\out_fifo_i_34__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(348),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_0\(26),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_2\(4)
    );
\out_fifo_i_34__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(330),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_3\(26),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_20\(4)
    );
\out_fifo_i_34__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(324),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_4\(26),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_26\(4)
    );
\out_fifo_i_35__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(299),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(25),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_2\(3)
    );
\out_fifo_i_35__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(292),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(21),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_49\(5)
    );
\out_fifo_i_35__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(284),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(21),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_51\(5)
    );
\out_fifo_i_35__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(275),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(25),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_20\(3)
    );
\out_fifo_i_35__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(267),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(25),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_26\(3)
    );
\out_fifo_i_35__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(260),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(21),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_57\(5)
    );
\out_fifo_i_35__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(252),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(21),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_59\(5)
    );
\out_fifo_i_35__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(244),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(21),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_61\(5)
    );
\out_fifo_i_36__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(231),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(20),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_49\(4)
    );
\out_fifo_i_36__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(225),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(20),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_51\(4)
    );
\out_fifo_i_36__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(207),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(20),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_57\(4)
    );
\out_fifo_i_36__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(201),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(20),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_59\(4)
    );
\out_fifo_i_36__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(195),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(20),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_61\(4)
    );
\out_fifo_i_37__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(189),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(24),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_2\(2)
    );
\out_fifo_i_37__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(186),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(19),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_49\(3)
    );
\out_fifo_i_37__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(182),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(19),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_51\(3)
    );
\out_fifo_i_37__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(177),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(24),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_20\(2)
    );
\out_fifo_i_37__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(173),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(24),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_26\(2)
    );
\out_fifo_i_37__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(170),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(19),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_57\(3)
    );
\out_fifo_i_37__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(166),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(19),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_59\(3)
    );
\out_fifo_i_37__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(162),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(19),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_61\(3)
    );
\out_fifo_i_38__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I2 => \rd_ptr_reg[3]\(16),
      I3 => \my_empty_reg[1]_0\,
      O => D4(3)
    );
\out_fifo_i_38__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(156),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(23),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_2\(1)
    );
\out_fifo_i_38__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(151),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(18),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_49\(2)
    );
\out_fifo_i_38__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(145),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(18),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_51\(2)
    );
\out_fifo_i_38__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(138),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(23),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_20\(1)
    );
\out_fifo_i_38__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(132),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(23),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_26\(1)
    );
\out_fifo_i_38__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(127),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(18),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_57\(2)
    );
\out_fifo_i_38__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(121),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(18),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_59\(2)
    );
\out_fifo_i_38__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(115),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(18),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_61\(2)
    );
\out_fifo_i_39__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(23),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I3 => \rd_ptr_reg[3]\(15),
      I4 => \my_empty_reg[1]_0\,
      O => D4(2)
    );
\out_fifo_i_39__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(108),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(22),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_2\(0)
    );
\out_fifo_i_39__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(103),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(17),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_49\(1)
    );
\out_fifo_i_39__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(97),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(17),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_51\(1)
    );
\out_fifo_i_39__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(90),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(22),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_20\(0)
    );
\out_fifo_i_39__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(84),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(22),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_26\(0)
    );
\out_fifo_i_39__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(79),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(17),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_57\(1)
    );
\out_fifo_i_39__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(73),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(17),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_59\(1)
    );
\out_fifo_i_39__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(67),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(17),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_61\(1)
    );
\out_fifo_i_3__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(303),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(3),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]\(3)
    );
\out_fifo_i_3__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(279),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(3),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_17\(3)
    );
\out_fifo_i_3__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(271),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(3),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_23\(3)
    );
\out_fifo_i_40__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(12),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I3 => \rd_ptr_reg[3]\(14),
      I4 => \my_empty_reg[1]_0\,
      O => D4(1)
    );
\out_fifo_i_40__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(58),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_1\(16),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_49\(0)
    );
\out_fifo_i_40__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(54),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_2\(16),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_51\(0)
    );
\out_fifo_i_40__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(42),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_5\(16),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_57\(0)
    );
\out_fifo_i_40__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(38),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_6\(16),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_59\(0)
    );
\out_fifo_i_40__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(34),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_7\(16),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_61\(0)
    );
\out_fifo_i_41__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(0),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\,
      I3 => \rd_ptr_reg[3]\(13),
      I4 => \my_empty_reg[1]_0\,
      O => D4(0)
    );
\out_fifo_i_42__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I2 => \rd_ptr_reg[3]\(24),
      I3 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(7)
    );
\out_fifo_i_42__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(347),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_0\(31),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_3\(4)
    );
\out_fifo_i_42__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(336),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_2\(26),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_14\(4)
    );
\out_fifo_i_42__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(329),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_3\(31),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_21\(4)
    );
\out_fifo_i_42__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(323),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_4\(31),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_27\(4)
    );
\out_fifo_i_42__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(312),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_6\(26),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_38\(4)
    );
\out_fifo_i_42__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(306),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_7\(26),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_44\(4)
    );
\out_fifo_i_43__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(25),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I3 => \rd_ptr_reg[3]\(23),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(6)
    );
\out_fifo_i_43__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(298),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_0\(30),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_3\(3)
    );
\out_fifo_i_43__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(283),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(25),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_14\(3)
    );
\out_fifo_i_43__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(274),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_3\(30),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_21\(3)
    );
\out_fifo_i_43__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(266),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_4\(30),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_27\(3)
    );
\out_fifo_i_43__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(251),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(25),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_38\(3)
    );
\out_fifo_i_43__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(243),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(25),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_44\(3)
    );
\out_fifo_i_44__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(14),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I3 => \rd_ptr_reg[3]\(22),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(5)
    );
\out_fifo_i_44__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(236),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_0\(29),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_3\(2)
    );
\out_fifo_i_44__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(218),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_3\(29),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_21\(2)
    );
\out_fifo_i_44__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(212),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_4\(29),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_27\(2)
    );
\out_fifo_i_45__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(2),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\,
      I3 => \rd_ptr_reg[3]\(21),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(4)
    );
\out_fifo_i_45__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(181),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(24),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_14\(2)
    );
\out_fifo_i_45__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(165),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(24),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_38\(2)
    );
\out_fifo_i_45__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(161),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(24),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_44\(2)
    );
out_fifo_i_46: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I2 => init_calib_complete_reg_0(15),
      I3 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]\(3)
    );
\out_fifo_i_46__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I2 => \rd_ptr_reg[3]\(20),
      I3 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(3)
    );
\out_fifo_i_46__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(144),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(23),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_14\(1)
    );
\out_fifo_i_46__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(120),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(23),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_38\(1)
    );
\out_fifo_i_46__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(114),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(23),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_44\(1)
    );
out_fifo_i_47: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(34),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I3 => init_calib_complete_reg_0(14),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]\(2)
    );
\out_fifo_i_47__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(24),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I3 => \rd_ptr_reg[3]\(19),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(2)
    );
\out_fifo_i_47__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(107),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_0\(28),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_3\(1)
    );
\out_fifo_i_47__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(96),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(22),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_14\(0)
    );
\out_fifo_i_47__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(89),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_3\(28),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_21\(1)
    );
\out_fifo_i_47__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(83),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_4\(28),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_27\(1)
    );
\out_fifo_i_47__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(72),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(22),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_38\(0)
    );
\out_fifo_i_47__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(66),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(22),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_44\(0)
    );
out_fifo_i_48: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I3 => init_calib_complete_reg_0(13),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]\(1)
    );
\out_fifo_i_48__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(13),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I3 => \rd_ptr_reg[3]\(18),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(1)
    );
out_fifo_i_49: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(11),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\,
      I3 => init_calib_complete_reg_0(12),
      I4 => \my_empty_reg[1]_1\,
      O => \rd_ptr_timing_reg[0]\(0)
    );
\out_fifo_i_49__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(1),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\,
      I3 => \rd_ptr_reg[3]\(17),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_3\(0)
    );
\out_fifo_i_49__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(29),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(27),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_3\(0)
    );
\out_fifo_i_49__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(17),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(27),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_21\(0)
    );
\out_fifo_i_49__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(13),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(27),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_27\(0)
    );
out_fifo_i_50: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I2 => \rd_ptr_reg[3]\(32),
      I3 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(7)
    );
\out_fifo_i_50__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(346),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(37),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_4\(5)
    );
\out_fifo_i_50__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(342),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_1\(26),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_8\(4)
    );
\out_fifo_i_50__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(335),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_2\(31),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_15\(4)
    );
\out_fifo_i_50__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(328),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(37),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_22\(5)
    );
\out_fifo_i_50__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(322),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(37),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_28\(5)
    );
\out_fifo_i_50__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(318),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_5\(26),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_32\(4)
    );
\out_fifo_i_50__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(311),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_6\(31),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_39\(4)
    );
\out_fifo_i_50__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(305),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_7\(31),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_45\(4)
    );
out_fifo_i_51: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(26),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \rd_ptr_reg[3]\(31),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(6)
    );
\out_fifo_i_51__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(297),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(36),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_4\(4)
    );
\out_fifo_i_51__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(291),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(25),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_8\(3)
    );
\out_fifo_i_51__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(282),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_2\(30),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_15\(3)
    );
\out_fifo_i_51__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(273),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(36),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_22\(4)
    );
\out_fifo_i_51__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(265),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(36),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_28\(4)
    );
\out_fifo_i_51__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(259),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(25),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_32\(3)
    );
\out_fifo_i_51__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(250),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_6\(30),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_39\(3)
    );
\out_fifo_i_51__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(242),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_7\(30),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_45\(3)
    );
out_fifo_i_52: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(15),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \rd_ptr_reg[3]\(30),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(5)
    );
\out_fifo_i_52__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(235),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(35),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_4\(3)
    );
\out_fifo_i_52__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(224),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_2\(29),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_15\(2)
    );
\out_fifo_i_52__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(217),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(35),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_22\(3)
    );
\out_fifo_i_52__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(211),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(35),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_28\(3)
    );
\out_fifo_i_52__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(200),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_6\(29),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_39\(2)
    );
\out_fifo_i_52__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(194),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_7\(29),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_45\(2)
    );
out_fifo_i_53: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(3),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\,
      I3 => \rd_ptr_reg[3]\(29),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(4)
    );
\out_fifo_i_53__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(185),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(24),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_8\(2)
    );
\out_fifo_i_53__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(169),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(24),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_32\(2)
    );
out_fifo_i_54: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I2 => \rd_ptr_reg[3]\(28),
      I3 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(3)
    );
\out_fifo_i_54__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(155),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(34),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_4\(2)
    );
\out_fifo_i_54__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(150),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(23),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_8\(1)
    );
\out_fifo_i_54__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(137),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(34),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_22\(2)
    );
\out_fifo_i_54__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(131),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(34),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_28\(2)
    );
\out_fifo_i_54__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(126),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(23),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_32\(1)
    );
out_fifo_i_55: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(27),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I3 => \rd_ptr_reg[3]\(27),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(2)
    );
\out_fifo_i_55__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(102),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(22),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_8\(0)
    );
\out_fifo_i_55__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(95),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_2\(28),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_15\(1)
    );
\out_fifo_i_55__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(78),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(22),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_32\(0)
    );
\out_fifo_i_55__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(71),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_6\(28),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_39\(1)
    );
\out_fifo_i_55__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(65),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_7\(28),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_45\(1)
    );
out_fifo_i_56: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(16),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I3 => \rd_ptr_reg[3]\(26),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(1)
    );
\out_fifo_i_56__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(61),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_0\(33),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_4\(1)
    );
\out_fifo_i_56__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(49),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_3\(33),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_22\(1)
    );
\out_fifo_i_56__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(45),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_4\(33),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_28\(1)
    );
out_fifo_i_57: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(4),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\,
      I3 => \rd_ptr_reg[3]\(25),
      I4 => \my_empty_reg[1]_0\,
      O => \rd_ptr_timing_reg[0]_2\(0)
    );
\out_fifo_i_57__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(28),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_0\(32),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_4\(0)
    );
\out_fifo_i_57__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(21),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(27),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_15\(0)
    );
\out_fifo_i_57__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(16),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_3\(32),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_22\(0)
    );
\out_fifo_i_57__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(12),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_4\(32),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_28\(0)
    );
\out_fifo_i_57__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(5),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(27),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_39\(0)
    );
\out_fifo_i_57__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(1),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(27),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_45\(0)
    );
\out_fifo_i_58__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(341),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_1\(31),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_9\(4)
    );
\out_fifo_i_58__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(334),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(37),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_16\(5)
    );
\out_fifo_i_58__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(317),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(510),
      I3 => \rd_ptr_reg[3]_5\(31),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_33\(4)
    );
\out_fifo_i_58__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(310),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(37),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_40\(5)
    );
\out_fifo_i_58__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(304),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(37),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_46\(5)
    );
\out_fifo_i_59__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(296),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(43),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_48\(5)
    );
\out_fifo_i_59__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(290),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_1\(30),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_9\(3)
    );
\out_fifo_i_59__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(281),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(36),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_16\(4)
    );
\out_fifo_i_59__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(272),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(43),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_54\(5)
    );
\out_fifo_i_59__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(264),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(43),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_56\(5)
    );
\out_fifo_i_59__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(258),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_5\(30),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_33\(3)
    );
\out_fifo_i_59__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(249),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(36),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_40\(4)
    );
\out_fifo_i_59__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(241),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(36),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_46\(4)
    );
\out_fifo_i_5__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(191),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(2),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]\(2)
    );
\out_fifo_i_5__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(179),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(2),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_17\(2)
    );
\out_fifo_i_5__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(175),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(2),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_23\(2)
    );
\out_fifo_i_60__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(234),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(42),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_48\(4)
    );
\out_fifo_i_60__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(230),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_1\(29),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_9\(2)
    );
\out_fifo_i_60__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(223),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(35),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_16\(3)
    );
\out_fifo_i_60__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(216),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(42),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_54\(4)
    );
\out_fifo_i_60__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(210),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(42),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_56\(4)
    );
\out_fifo_i_60__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(206),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(511),
      I3 => \rd_ptr_reg[3]_5\(29),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_33\(2)
    );
\out_fifo_i_60__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(199),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(35),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_40\(3)
    );
\out_fifo_i_60__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(193),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(35),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_46\(3)
    );
\out_fifo_i_61__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(188),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(41),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_48\(3)
    );
\out_fifo_i_61__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(176),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(41),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_54\(3)
    );
\out_fifo_i_61__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(172),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(41),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_56\(3)
    );
out_fifo_i_62: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I2 => \rd_ptr_reg[3]\(36),
      I3 => \my_empty_reg[1]_0\,
      O => D7(3)
    );
\out_fifo_i_62__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(154),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_0\(40),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_48\(2)
    );
\out_fifo_i_62__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(143),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(34),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_16\(2)
    );
\out_fifo_i_62__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(136),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_3\(40),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_54\(2)
    );
\out_fifo_i_62__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(130),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_4\(40),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_56\(2)
    );
\out_fifo_i_62__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(119),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(34),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_40\(2)
    );
\out_fifo_i_62__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(113),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(34),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_46\(2)
    );
out_fifo_i_63: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(28),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I3 => \rd_ptr_reg[3]\(35),
      I4 => \my_empty_reg[1]_0\,
      O => D7(2)
    );
\out_fifo_i_63__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(106),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(39),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_48\(1)
    );
\out_fifo_i_63__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(101),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_1\(28),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_9\(1)
    );
\out_fifo_i_63__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(88),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(39),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_54\(1)
    );
\out_fifo_i_63__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(82),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(39),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_56\(1)
    );
\out_fifo_i_63__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(77),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_5\(28),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_33\(1)
    );
out_fifo_i_64: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(17),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I3 => \rd_ptr_reg[3]\(34),
      I4 => \my_empty_reg[1]_0\,
      O => D7(1)
    );
\out_fifo_i_64__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(60),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_0\(38),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]_48\(0)
    );
\out_fifo_i_64__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(53),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_2\(33),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_16\(1)
    );
\out_fifo_i_64__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(48),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_3\(38),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_54\(0)
    );
\out_fifo_i_64__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(44),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_4\(38),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_56\(0)
    );
\out_fifo_i_64__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(37),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_6\(33),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_40\(1)
    );
\out_fifo_i_64__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(33),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_7\(33),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_46\(1)
    );
out_fifo_i_65: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(5),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\,
      I3 => \rd_ptr_reg[3]\(33),
      I4 => \my_empty_reg[1]_0\,
      O => D7(0)
    );
\out_fifo_i_65__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(25),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(27),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_9\(0)
    );
\out_fifo_i_65__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(20),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_2\(32),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_16\(0)
    );
\out_fifo_i_65__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(9),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(27),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_33\(0)
    );
\out_fifo_i_65__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(4),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_6\(32),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_40\(0)
    );
\out_fifo_i_65__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(0),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_7\(32),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_46\(0)
    );
\out_fifo_i_66__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(340),
      I1 => \init_calib_complete_reg_rep__10\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(37),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_10\(5)
    );
\out_fifo_i_66__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(316),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(37),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_34\(5)
    );
\out_fifo_i_67__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(289),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(36),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_10\(4)
    );
\out_fifo_i_67__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(280),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_2\(43),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_52\(5)
    );
\out_fifo_i_67__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(257),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(36),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_34\(4)
    );
\out_fifo_i_67__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(248),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_6\(43),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_60\(5)
    );
\out_fifo_i_67__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(240),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_7\(43),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_62\(5)
    );
\out_fifo_i_68__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(229),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(35),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_10\(3)
    );
\out_fifo_i_68__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(222),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(42),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_52\(4)
    );
\out_fifo_i_68__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(205),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(35),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_34\(3)
    );
\out_fifo_i_68__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(198),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(42),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_60\(4)
    );
\out_fifo_i_68__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(192),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(42),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_62\(4)
    );
\out_fifo_i_69__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(180),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(41),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_52\(3)
    );
\out_fifo_i_69__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(164),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(41),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_60\(3)
    );
\out_fifo_i_69__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(160),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(41),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_62\(3)
    );
\out_fifo_i_6__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(159),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_0\(1),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]\(1)
    );
\out_fifo_i_6__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(141),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_3\(1),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_17\(1)
    );
\out_fifo_i_6__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(135),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_4\(1),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_23\(1)
    );
\out_fifo_i_70__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__11\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I2 => \rd_ptr_reg[3]\(40),
      I3 => \my_empty_reg[1]_0\,
      O => D8(3)
    );
\out_fifo_i_70__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(149),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(34),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_10\(2)
    );
\out_fifo_i_70__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(142),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_2\(40),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_52\(2)
    );
\out_fifo_i_70__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(125),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(34),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_34\(2)
    );
\out_fifo_i_70__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(118),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_6\(40),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_60\(2)
    );
\out_fifo_i_70__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(112),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_7\(40),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_62\(2)
    );
\out_fifo_i_71__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(29),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I3 => \rd_ptr_reg[3]\(39),
      I4 => \my_empty_reg[1]_0\,
      O => D8(2)
    );
\out_fifo_i_71__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(94),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_2\(39),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_52\(1)
    );
\out_fifo_i_71__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(70),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_6\(39),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_60\(1)
    );
\out_fifo_i_71__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(64),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_7\(39),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_62\(1)
    );
\out_fifo_i_72__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(18),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I3 => \rd_ptr_reg[3]\(38),
      I4 => \my_empty_reg[1]_0\,
      O => D8(1)
    );
\out_fifo_i_72__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(57),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_1\(33),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_10\(1)
    );
\out_fifo_i_72__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(52),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_2\(38),
      I4 => \my_empty_reg[1]_4\,
      O => \my_empty_reg[7]_52\(0)
    );
\out_fifo_i_72__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(41),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(125),
      I3 => \rd_ptr_reg[3]_5\(33),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_34\(1)
    );
\out_fifo_i_72__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(36),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_6\(38),
      I4 => \my_empty_reg[1]_8\,
      O => \my_empty_reg[7]_60\(0)
    );
\out_fifo_i_72__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(32),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_7\(38),
      I4 => \my_empty_reg[1]_9\,
      O => \my_empty_reg[7]_62\(0)
    );
\out_fifo_i_73__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(6),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\,
      I3 => \rd_ptr_reg[3]\(37),
      I4 => \my_empty_reg[1]_0\,
      O => D8(0)
    );
\out_fifo_i_73__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(24),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_1\(32),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_10\(0)
    );
\out_fifo_i_73__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(8),
      I1 => \init_calib_complete_reg_rep__0\,
      I2 => phy_wrdata(61),
      I3 => \rd_ptr_reg[3]_5\(32),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_34\(0)
    );
\out_fifo_i_75__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(288),
      I1 => \init_calib_complete_reg_rep__9\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_1\(43),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_50\(5)
    );
\out_fifo_i_75__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(256),
      I1 => \init_calib_complete_reg_rep__8\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_5\(43),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_58\(5)
    );
\out_fifo_i_76__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(228),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(42),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_50\(4)
    );
\out_fifo_i_76__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(204),
      I1 => \init_calib_complete_reg_rep__7\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(42),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_58\(4)
    );
\out_fifo_i_77__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(184),
      I1 => \init_calib_complete_reg_rep__6\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(41),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_50\(3)
    );
\out_fifo_i_77__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(168),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(41),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_58\(3)
    );
out_fifo_i_78: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEF0"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12\,
      I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I2 => \rd_ptr_reg[3]\(44),
      I3 => \my_empty_reg[1]_0\,
      O => D9(3)
    );
\out_fifo_i_78__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(148),
      I1 => \init_calib_complete_reg_rep__5\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_1\(40),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_50\(2)
    );
\out_fifo_i_78__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(124),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(505),
      I3 => \rd_ptr_reg[3]_5\(40),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_58\(2)
    );
out_fifo_i_79: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(30),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I3 => \rd_ptr_reg[3]\(43),
      I4 => \my_empty_reg[1]_0\,
      O => D9(2)
    );
\out_fifo_i_79__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(100),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      I3 => \rd_ptr_reg[3]_1\(39),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_50\(1)
    );
\out_fifo_i_79__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(76),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(445),
      I3 => \rd_ptr_reg[3]_5\(39),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_58\(1)
    );
\out_fifo_i_7__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(111),
      I1 => \init_calib_complete_reg_rep__4\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_0\(0),
      I4 => \my_empty_reg[1]_2\,
      O => \my_empty_reg[7]\(0)
    );
\out_fifo_i_7__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(93),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_3\(0),
      I4 => \my_empty_reg[1]_5\,
      O => \my_empty_reg[7]_17\(0)
    );
\out_fifo_i_7__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(87),
      I1 => \init_calib_complete_reg_rep__3\,
      I2 => phy_wrdata(447),
      I3 => \rd_ptr_reg[3]_4\(0),
      I4 => \my_empty_reg[1]_6\,
      O => \my_empty_reg[7]_23\(0)
    );
out_fifo_i_80: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(19),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I3 => \rd_ptr_reg[3]\(42),
      I4 => \my_empty_reg[1]_0\,
      O => D9(1)
    );
\out_fifo_i_80__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(56),
      I1 => \init_calib_complete_reg_rep__2\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_1\(38),
      I4 => \my_empty_reg[1]_3\,
      O => \my_empty_reg[7]_50\(0)
    );
\out_fifo_i_80__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => \write_buffer.wr_buf_out_data_reg[511]\(40),
      I1 => \init_calib_complete_reg_rep__1\,
      I2 => phy_wrdata(190),
      I3 => \rd_ptr_reg[3]_5\(38),
      I4 => \my_empty_reg[1]_7\,
      O => \my_empty_reg[7]_58\(0)
    );
out_fifo_i_81: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_address(7),
      I1 => \init_calib_complete_reg_rep__11\,
      I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\,
      I3 => \rd_ptr_reg[3]\(41),
      I4 => \my_empty_reg[1]_0\,
      O => D9(0)
    );
\out_fifo_i_8__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8FF00"
    )
        port map (
      I0 => mc_ras_n(0),
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => phy_ras_n(1),
      I3 => \rd_ptr_reg[3]\(0),
      I4 => \my_empty_reg[1]_0\,
      O => D0(0)
    );
\phy_ctl_wd_i1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cmd(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_cmd(0),
      O => \^phy_ctl_wd_i1_reg[24]\(0)
    );
\phy_ctl_wd_i1[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_reg[0]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_0(0),
      O => \^phy_ctl_wd_i1_reg[24]\(3)
    );
\phy_ctl_wd_i1[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_reg[1]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_0(1),
      O => \^phy_ctl_wd_i1_reg[24]\(4)
    );
\phy_ctl_wd_i1[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_reg[2]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_0(2),
      O => \^phy_ctl_wd_i1_reg[24]\(5)
    );
\phy_ctl_wd_i1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cmd(1),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_cmd(1),
      O => \^phy_ctl_wd_i1_reg[24]\(1)
    );
\phy_ctl_wd_i1[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_reg[3]\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_0(3),
      O => \^phy_ctl_wd_i1_reg[24]\(6)
    );
\phy_ctl_wd_i1[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_reg[4]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_0(4),
      O => \^phy_ctl_wd_i1_reg[24]\(7)
    );
\phy_ctl_wd_i1[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_data_offset_reg[5]\,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_data_offset_0(5),
      O => \^phy_ctl_wd_i1_reg[24]\(8)
    );
\phy_ctl_wd_i1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_cas_n(0),
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_cmd(2),
      O => \^phy_ctl_wd_i1_reg[24]\(2)
    );
phy_reset_n_reg: unisim.vcomponents.FDCE
     port map (
      C => CLK,
      CE => '1',
      CLR => \rstdiv0_sync_r1_reg_rep__3\(0),
      D => cnt_pwron_reset_done_r,
      Q => phy_reset_n
    );
pi_calib_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_calib_done_r,
      Q => \^pi_calib_done\,
      R => '0'
    );
pi_calib_done_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => pi_calib_rank_done_r,
      I1 => pi_calib_done_r,
      O => pi_calib_done_r_i_1_n_0
    );
pi_calib_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_calib_done_r_i_1_n_0,
      Q => pi_calib_done_r,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
pi_calib_rank_done_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => pi_phase_locked_all_r3,
      I1 => pi_phase_locked_all_r4,
      O => init_next_state193_out
    );
pi_calib_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => init_next_state193_out,
      Q => pi_calib_rank_done_r,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
pi_dqs_found_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_done,
      Q => \^pi_dqs_found_done_r1\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
pi_dqs_found_start_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000AE"
    )
        port map (
      I0 => \^dqs_found_start_r_reg\,
      I1 => pi_dqs_found_start_i_2_n_0,
      I2 => pi_dqs_found_done,
      I3 => wrlvl_byte_redo,
      I4 => \rstdiv0_sync_r1_reg_rep__23\,
      O => pi_dqs_found_start_i_1_n_0
    );
pi_dqs_found_start_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \init_state_r[0]_i_3_n_0\,
      I1 => \init_state_r_reg_n_0_[4]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => pi_dqs_found_start_i_2_n_0
    );
pi_dqs_found_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_dqs_found_start_i_1_n_0,
      Q => \^dqs_found_start_r_reg\,
      R => '0'
    );
pi_phase_locked_all_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => in0,
      Q => pi_phase_locked_all_r1,
      R => '0'
    );
pi_phase_locked_all_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_phase_locked_all_r1,
      Q => pi_phase_locked_all_r2,
      R => '0'
    );
pi_phase_locked_all_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_phase_locked_all_r2,
      Q => pi_phase_locked_all_r3,
      R => '0'
    );
pi_phase_locked_all_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_phase_locked_all_r3,
      Q => pi_phase_locked_all_r4,
      R => '0'
    );
prbs_rdlvl_done_pulse_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prbs_rdlvl_done_pulse0,
      Q => \^complex_row1_rd_cnt_reg[1]_0\,
      R => '0'
    );
\prech_done_dly_r_reg[15]_srl16\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => prech_done_pre,
      Q => \prech_done_dly_r_reg[15]_srl16_n_0\
    );
\prech_done_dly_r_reg[15]_srl16_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => prech_pending_r_i_2_n_0,
      I1 => \^prech_pending_r_reg_0\,
      O => prech_done_pre
    );
prech_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \prech_done_dly_r_reg[15]_srl16_n_0\,
      Q => prech_done,
      R => '0'
    );
prech_pending_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^prech_pending_r_reg_0\,
      I1 => prech_pending_r_i_2_n_0,
      I2 => prech_pending_r,
      O => prech_pending_r_i_1_n_0
    );
prech_pending_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => prech_pending_r,
      I1 => prech_pending_r_i_3_n_0,
      I2 => cnt_cmd_done_r,
      I3 => prech_pending_r_i_4_n_0,
      I4 => complex_oclkdelay_calib_start_r1,
      I5 => prech_pending_r_i_5_n_0,
      O => prech_pending_r_i_2_n_0
    );
prech_pending_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF7FFFEF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \oclk_wr_cnt[3]_i_5_n_0\,
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => prech_pending_r_i_3_n_0
    );
prech_pending_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => prech_req_r_i_2_n_0,
      O => prech_pending_r_i_4_n_0
    );
prech_pending_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000015"
    )
        port map (
      I0 => prech_pending_r_i_6_n_0,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0\,
      I3 => prech_pending_r_i_7_n_0,
      I4 => \^stg1_wr_done\,
      I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\,
      O => prech_pending_r_i_5_n_0
    );
prech_pending_r_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888008000"
    )
        port map (
      I0 => prech_pending_r_i_8_n_0,
      I1 => \init_state_r[0]_i_3_n_0\,
      I2 => \^rdlvl_stg1_done_r1\,
      I3 => cnt_cmd_done_r,
      I4 => rdlvl_last_byte_done_r,
      I5 => dqs_found_prech_req,
      O => prech_pending_r_i_6_n_0
    );
prech_pending_r_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020100000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      O => prech_pending_r_i_7_n_0
    );
prech_pending_r_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[5]\,
      O => prech_pending_r_i_8_n_0
    );
prech_pending_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prech_pending_r_i_1_n_0,
      Q => prech_pending_r,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
prech_req_posedge_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54545554"
    )
        port map (
      I0 => prech_req_r,
      I1 => rdlvl_prech_req,
      I2 => wrcal_prech_req,
      I3 => dqs_found_prech_req,
      I4 => prech_req_posedge_r_i_2_n_0,
      O => prech_req_posedge_r0
    );
prech_req_posedge_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => prech_req_r_i_2_n_0,
      O => prech_req_posedge_r_i_2_n_0
    );
prech_req_posedge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prech_req_posedge_r0,
      Q => \^prech_pending_r_reg_0\,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
prech_req_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEFEEE"
    )
        port map (
      I0 => rdlvl_prech_req,
      I1 => wrcal_prech_req,
      I2 => dqs_found_prech_req,
      I3 => prech_req_r_i_2_n_0,
      I4 => \init_state_r_reg_n_0_[5]\,
      I5 => prech_req_r_i_3_n_0,
      O => prech_req
    );
prech_req_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      O => prech_req_r_i_2_n_0
    );
prech_req_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[2]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      O => prech_req_r_i_3_n_0
    );
prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => prech_req,
      Q => prech_req_r,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
pwron_ce_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(9),
      I1 => \cnt_pwron_ce_r_reg__0\(7),
      I2 => pwron_ce_r_i_3_n_0,
      I3 => \cnt_pwron_ce_r_reg__0\(6),
      I4 => \cnt_pwron_ce_r_reg__0\(8),
      O => pwron_ce_r_i_2_n_0
    );
pwron_ce_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \cnt_pwron_ce_r_reg__0\(5),
      I1 => \cnt_pwron_ce_r_reg__0\(3),
      I2 => \cnt_pwron_ce_r_reg__0\(1),
      I3 => \cnt_pwron_ce_r_reg__0\(0),
      I4 => \cnt_pwron_ce_r_reg__0\(2),
      I5 => \cnt_pwron_ce_r_reg__0\(4),
      O => pwron_ce_r_i_3_n_0
    );
pwron_ce_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pwron_ce_r_i_2_n_0,
      Q => pwron_ce_r,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
rdlvl_last_byte_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_last_byte_done,
      Q => rdlvl_last_byte_done_r,
      R => '0'
    );
\rdlvl_start_dly0_r_reg[13]_srl14\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => rdlvl_start_pre,
      Q => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\
    );
\rdlvl_start_dly0_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\,
      Q => rdlvl_start_dly0_r(14),
      R => '0'
    );
rdlvl_start_pre_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => prech_req_r_i_3_n_0,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => pi_dqs_found_done,
      I5 => rdlvl_start_pre,
      O => rdlvl_start_pre_i_1_n_0
    );
rdlvl_start_pre_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_start_pre_i_1_n_0,
      Q => rdlvl_start_pre,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
rdlvl_stg1_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_done_reg,
      Q => \^rdlvl_stg1_done_r1\,
      R => '0'
    );
rdlvl_stg1_start_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00020000"
    )
        port map (
      I0 => rdlvl_start_dly0_r(14),
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => prech_req_r_i_3_n_0,
      I3 => \wrcal_reads[7]_i_6_n_0\,
      I4 => pi_dqs_found_done,
      I5 => \^rdlvl_stg1_start_r_reg\,
      O => rdlvl_stg1_start_i_1_n_0
    );
rdlvl_stg1_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_start_i_1_n_0,
      Q => \^rdlvl_stg1_start_r_reg\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
read_calib_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550010"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => \num_refresh[3]_i_4_n_0\,
      I2 => \init_state_r_reg_n_0_[1]\,
      I3 => \init_state_r_reg_n_0_[0]\,
      I4 => \^phy_read_calib\,
      I5 => \^pi_calib_done\,
      O => read_calib_i_1_n_0
    );
read_calib_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => read_calib_i_1_n_0,
      Q => \^phy_read_calib\,
      R => '0'
    );
\reg_ctrl_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \reg_ctrl_cnt_r_reg__0\(0),
      O => \p_0_in__3\(0)
    );
\reg_ctrl_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \reg_ctrl_cnt_r_reg__0\(1),
      I1 => \reg_ctrl_cnt_r_reg__0\(0),
      O => \p_0_in__3\(1)
    );
\reg_ctrl_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \reg_ctrl_cnt_r_reg__0\(2),
      I1 => \reg_ctrl_cnt_r_reg__0\(0),
      I2 => \reg_ctrl_cnt_r_reg__0\(1),
      O => \p_0_in__3\(2)
    );
\reg_ctrl_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => init_state_r(6),
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => \wrcal_reads[7]_i_6_n_0\,
      O => ddr2_pre_flag_r
    );
\reg_ctrl_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => init_state_r(6),
      I3 => \reg_ctrl_cnt_r[3]_i_4_n_0\,
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[3]\,
      O => reg_ctrl_cnt_r
    );
\reg_ctrl_cnt_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \reg_ctrl_cnt_r_reg__0\(3),
      I1 => \reg_ctrl_cnt_r_reg__0\(1),
      I2 => \reg_ctrl_cnt_r_reg__0\(0),
      I3 => \reg_ctrl_cnt_r_reg__0\(2),
      O => \p_0_in__3\(3)
    );
\reg_ctrl_cnt_r[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      O => \reg_ctrl_cnt_r[3]_i_4_n_0\
    );
\reg_ctrl_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(0),
      Q => \reg_ctrl_cnt_r_reg__0\(0),
      R => ddr2_pre_flag_r
    );
\reg_ctrl_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(1),
      Q => \reg_ctrl_cnt_r_reg__0\(1),
      R => ddr2_pre_flag_r
    );
\reg_ctrl_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(2),
      Q => \reg_ctrl_cnt_r_reg__0\(2),
      R => ddr2_pre_flag_r
    );
\reg_ctrl_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => reg_ctrl_cnt_r,
      D => \p_0_in__3\(3),
      Q => \reg_ctrl_cnt_r_reg__0\(3),
      R => ddr2_pre_flag_r
    );
reset_if_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005510"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => rdlvl_stg1_done_reg,
      I3 => reset_if,
      I4 => reset_if_r9,
      O => reset_if_reg
    );
reset_rd_addr_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => complex_ocal_reset_rd_addr_reg_n_0,
      Q => reset_rd_addr_r1,
      R => '0'
    );
\row_cnt_victim_rotate.complex_row_cnt[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE00FEFE"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_1\,
      I1 => complex_sample_cnt_inc_r2,
      I2 => reset_rd_addr_r1,
      I3 => \^one_rank.stg1_wr_done_reg_0\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[6]_i_3_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF40FFFF"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I1 => wr_victim_inc,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0\,
      I3 => \rstdiv0_sync_r1_reg_rep__22\,
      I4 => \^rdlvl_stg1_done_r1\,
      I5 => rdlvl_stg1_done_reg,
      O => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_11\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_11_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_12_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_13_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_14\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_14_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEE00E0"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0\,
      I1 => \^one_rank.stg1_wr_done_reg_0\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0\,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_7_n_0\,
      I4 => reset_rd_addr_r1,
      I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_8_n_0\,
      O => complex_row_cnt
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010100"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_1\,
      I1 => complex_sample_cnt_inc_r2,
      I2 => reset_rd_addr_r1,
      I3 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0\,
      I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_4_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"15"
    )
        port map (
      I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      I2 => \row_cnt_victim_rotate.complex_row_cnt[6]_i_2_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => \wrcal_reads[7]_i_5_n_0\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[1]\,
      I5 => \init_state_r_reg_n_0_[0]\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_6_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \complex_row_cnt_ocal[7]_i_7_n_0\,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_7_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => wr_victim_inc,
      I1 => complex_sample_cnt_inc_r2,
      O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_8_n_0\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => complex_row_cnt,
      D => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\,
      Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      R => \complex_row_cnt0__1\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_0\,
      CO(2) => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_1\,
      CO(1) => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_2\,
      CO(0) => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_3\,
      CYINIT => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\,
      DI(3) => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\,
      DI(2 downto 0) => B"000",
      O(3 downto 0) => \NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_O_UNCONNECTED\(3 downto 0),
      S(3) => \row_cnt_victim_rotate.complex_row_cnt[7]_i_14_n_0\,
      S(2) => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\,
      S(1) => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\,
      S(0) => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\
    );
\row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9\: unisim.vcomponents.CARRY4
     port map (
      CI => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_10_n_0\,
      CO(3) => \NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_CO_UNCONNECTED\(3),
      CO(2) => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_1\,
      CO(1) => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_2\,
      CO(0) => \row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\,
      DI(1) => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\,
      DI(0) => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\,
      O(3 downto 0) => \NLW_row_cnt_victim_rotate.complex_row_cnt_reg[7]_i_9_O_UNCONNECTED\(3 downto 0),
      S(3) => '0',
      S(2) => \row_cnt_victim_rotate.complex_row_cnt[7]_i_11_n_0\,
      S(1) => \row_cnt_victim_rotate.complex_row_cnt[7]_i_12_n_0\,
      S(0) => \row_cnt_victim_rotate.complex_row_cnt[7]_i_13_n_0\
    );
\stg1_wr_rd_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      O => \stg1_wr_rd_cnt[0]_i_1_n_0\
    );
\stg1_wr_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D00000D0D0D0D0D"
    )
        port map (
      I0 => \^stg1_wr_done\,
      I1 => rdlvl_stg1_done_reg,
      I2 => \rstdiv0_sync_r1_reg_rep__22\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[1]_i_1_n_0\
    );
\stg1_wr_rd_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[2]\,
      I4 => \oclk_wr_cnt[3]_i_5_n_0\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \^stg1_wr_done\
    );
\stg1_wr_rd_cnt[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FD57"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      O => \stg1_wr_rd_cnt[2]_i_1_n_0\
    );
\stg1_wr_rd_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8AAA8AAA800A8"
    )
        port map (
      I0 => rdlvl_stg1_done_reg_1,
      I1 => \stg1_wr_rd_cnt[3]_i_2_n_0\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      O => \stg1_wr_rd_cnt[3]_i_1_n_0\
    );
\stg1_wr_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFD0FF"
    )
        port map (
      I0 => complex_row0_rd_done,
      I1 => complex_row1_rd_done,
      I2 => complex_row1_wr_done,
      I3 => complex_row0_wr_done,
      I4 => wr_victim_inc,
      O => \stg1_wr_rd_cnt[3]_i_2_n_0\
    );
\stg1_wr_rd_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8288AAAA"
    )
        port map (
      I0 => rdlvl_stg1_done_reg_1,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[4]_i_1_n_0\
    );
\stg1_wr_rd_cnt[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAA8AA"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_2_n_0,
      I1 => \wrcal_reads[7]_i_6_n_0\,
      I2 => \init_state_r[4]_i_14_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \stg1_wr_rd_cnt[4]_i_4_n_0\,
      I5 => rdlvl_last_byte_done,
      O => \stg1_wr_rd_cnt[4]_i_3_n_0\
    );
\stg1_wr_rd_cnt[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \init_state_r_reg_n_0_[4]\,
      O => \stg1_wr_rd_cnt[4]_i_4_n_0\
    );
\stg1_wr_rd_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEBEEEEAAAAAAAA"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\,
      I5 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      O => \stg1_wr_rd_cnt[5]_i_1_n_0\
    );
\stg1_wr_rd_cnt[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => \stg1_wr_rd_cnt[5]_i_2_n_0\
    );
\stg1_wr_rd_cnt[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF60"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I1 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I3 => \stg1_wr_rd_cnt[6]_i_2_n_0\,
      O => \stg1_wr_rd_cnt[6]_i_1_n_0\
    );
\stg1_wr_rd_cnt[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002022"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[3]_i_2_n_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \^stg1_wr_done\,
      I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      O => \stg1_wr_rd_cnt[6]_i_2_n_0\
    );
\stg1_wr_rd_cnt[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A208"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I1 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      O => \stg1_wr_rd_cnt[7]_i_1_n_0\
    );
\stg1_wr_rd_cnt[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555DFFFFFFFF"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\,
      I1 => rdlvl_stg1_done_reg,
      I2 => \init_state_r_reg_n_0_[0]\,
      I3 => \init_state_r_reg_n_0_[1]\,
      I4 => complex_oclkdelay_calib_start_int_i_2_n_0,
      I5 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      O => \stg1_wr_rd_cnt[8]_i_1_n_0\
    );
\stg1_wr_rd_cnt[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8AA0200"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[8]_i_4_n_0\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      O => \stg1_wr_rd_cnt[8]_i_2_n_0\
    );
\stg1_wr_rd_cnt[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[4]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r_reg_n_0_[3]\,
      I4 => \init_state_r_reg_n_0_[2]\,
      I5 => prech_req_r_i_2_n_0,
      O => \stg1_wr_rd_cnt[8]_i_3_n_0\
    );
\stg1_wr_rd_cnt[8]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => \stg1_wr_rd_cnt[4]_i_3_n_0\,
      I1 => \^stg1_wr_done\,
      I2 => rdlvl_stg1_done_reg,
      I3 => \rstdiv0_sync_r1_reg_rep__23\,
      O => \stg1_wr_rd_cnt[8]_i_4_n_0\
    );
\stg1_wr_rd_cnt[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      O => \stg1_wr_rd_cnt[8]_i_5_n_0\
    );
\stg1_wr_rd_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[0]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[1]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[2]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[3]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[4]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[5]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[5]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[6]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[6]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[7]_i_1_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[7]\,
      R => '0'
    );
\stg1_wr_rd_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \stg1_wr_rd_cnt[8]_i_1_n_0\,
      D => \stg1_wr_rd_cnt[8]_i_2_n_0\,
      Q => \stg1_wr_rd_cnt_reg_n_0_[8]\,
      R => '0'
    );
wl_sm_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_dqs_asrt_r1,
      Q => wl_sm_start,
      R => \rstdiv0_sync_r1_reg_rep__3\(0)
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => complex_row0_wr_done,
      I1 => \^rdlvl_stg1_done_r1\,
      I2 => wr_victim_inc_i_2_n_0,
      I3 => complex_row0_wr_done0,
      O => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\
    );
\wr_done_victim_rotate.complex_row0_wr_done_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFDFDFDDDDDDDD"
    )
        port map (
      I0 => \complex_row_cnt_ocal[7]_i_6_n_0\,
      I1 => complex_byte_rd_done,
      I2 => \complex_row_cnt_ocal[7]_i_8_n_0\,
      I3 => rdlvl_stg1_done_reg,
      I4 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_5_n_0\,
      I5 => wr_victim_inc,
      O => complex_row0_wr_done0
    );
\wr_done_victim_rotate.complex_row0_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\,
      Q => complex_row0_wr_done,
      R => '0'
    );
\wr_done_victim_rotate.complex_row1_wr_done_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => complex_row1_wr_done,
      I1 => complex_row0_wr_done,
      I2 => wr_victim_inc_i_2_n_0,
      I3 => complex_row0_wr_done0,
      O => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\
    );
\wr_done_victim_rotate.complex_row1_wr_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\,
      Q => complex_row1_wr_done,
      R => '0'
    );
wr_level_dqs_asrt_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => \en_cnt_div4.wrlvl_odt_i_2_n_0\,
      I1 => wrlvl_active_r1,
      I2 => wr_level_dqs_asrt,
      I3 => \rstdiv0_sync_r1_reg_rep__22\,
      O => wr_level_dqs_asrt_i_1_n_0
    );
wr_level_dqs_asrt_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_dqs_asrt,
      Q => wr_level_dqs_asrt_r1,
      R => '0'
    );
wr_level_dqs_asrt_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_dqs_asrt_i_1_n_0,
      Q => wr_level_dqs_asrt,
      R => '0'
    );
wr_lvl_start_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55400000"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => dqs_asrt_cnt(1),
      I2 => dqs_asrt_cnt(0),
      I3 => \^wr_level_start_r_reg\,
      I4 => wrlvl_active,
      O => wr_lvl_start_i_1_n_0
    );
wr_lvl_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_lvl_start_i_1_n_0,
      Q => \^wr_level_start_r_reg\,
      R => '0'
    );
wr_ptr0_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__26\,
      I1 => calib_cmd_wren,
      O => phy_cmd_wr_en
    );
\wr_ptr[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mc_wrdata_en,
      I1 => \init_calib_complete_reg_rep__26\,
      I2 => calib_wrdata_en,
      O => phy_data_wr_en
    );
wr_victim_inc_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => wr_victim_inc_i_2_n_0,
      I1 => complex_row0_wr_done,
      I2 => \^one_rank.stg1_wr_done_reg_0\,
      O => wr_victim_inc0
    );
wr_victim_inc_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => complex_sample_cnt_inc_i_3_n_0,
      I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\,
      I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\,
      I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\,
      I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\,
      I5 => \stg1_wr_rd_cnt_reg_n_0_[1]\,
      O => wr_victim_inc_i_2_n_0
    );
wr_victim_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_victim_inc0,
      Q => wr_victim_inc,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
wrcal_final_chk_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF10000000"
    )
        port map (
      I0 => wrcal_final_chk_i_2_n_0,
      I1 => wrcal_final_chk_i_3_n_0,
      I2 => \init_state_r[1]_i_1_n_0\,
      I3 => \init_state_r[4]_i_1_n_0\,
      I4 => \init_state_r[2]_i_1_n_0\,
      I5 => wrcal_final_chk,
      O => wrcal_final_chk_i_1_n_0
    );
wrcal_final_chk_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFFFFABFB"
    )
        port map (
      I0 => \init_state_r[5]_i_1_n_0\,
      I1 => \init_state_r[0]_i_5_n_0\,
      I2 => \init_state_r_reg_n_0_[5]\,
      I3 => \init_state_r[0]_i_4_n_0\,
      I4 => \init_state_r[5]_i_7_n_0\,
      I5 => wrcal_final_chk_i_4_n_0,
      O => wrcal_final_chk_i_2_n_0
    );
wrcal_final_chk_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \init_state_r[3]_i_1_n_0\,
      I1 => \init_state_r[6]_i_1_n_0\,
      I2 => wrcal_done_reg,
      O => wrcal_final_chk_i_3_n_0
    );
wrcal_final_chk_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000AAAAAAAA"
    )
        port map (
      I0 => init_state_r(6),
      I1 => \ocal_act_wait_cnt_reg__0\(3),
      I2 => \ocal_act_wait_cnt_reg__0\(1),
      I3 => \ocal_act_wait_cnt_reg__0\(0),
      I4 => \ocal_act_wait_cnt_reg__0\(2),
      I5 => prech_req_r_i_2_n_0,
      O => wrcal_final_chk_i_4_n_0
    );
wrcal_final_chk_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_final_chk_i_1_n_0,
      Q => wrcal_final_chk,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
wrcal_rd_wait_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[0]\,
      I1 => \init_state_r_reg_n_0_[1]\,
      I2 => \wrcal_reads[7]_i_5_n_0\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => wrcal_rd_wait_i_1_n_0
    );
wrcal_rd_wait_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_rd_wait_i_1_n_0,
      Q => wrcal_rd_wait,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\wrcal_reads[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wrcal_reads,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      O => \wrcal_reads[0]_i_1_n_0\
    );
\wrcal_reads[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F9"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => wrcal_reads,
      O => \wrcal_reads[1]_i_1_n_0\
    );
\wrcal_reads[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFE1"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[1]\,
      I1 => \wrcal_reads_reg_n_0_[0]\,
      I2 => \wrcal_reads_reg_n_0_[2]\,
      I3 => wrcal_reads,
      O => \wrcal_reads[2]_i_1_n_0\
    );
\wrcal_reads[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFE01"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[0]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => \wrcal_reads_reg_n_0_[2]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      I4 => wrcal_reads,
      O => \wrcal_reads[3]_i_1_n_0\
    );
\wrcal_reads[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFE0001"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[2]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => \wrcal_reads_reg_n_0_[0]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      I4 => \wrcal_reads_reg_n_0_[4]\,
      I5 => wrcal_reads,
      O => \wrcal_reads[4]_i_1_n_0\
    );
\wrcal_reads[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFD2"
    )
        port map (
      I0 => \wrcal_reads[7]_i_7_n_0\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads_reg_n_0_[5]\,
      I3 => wrcal_reads,
      O => \wrcal_reads[5]_i_1_n_0\
    );
\wrcal_reads[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFD02"
    )
        port map (
      I0 => \wrcal_reads[7]_i_7_n_0\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads_reg_n_0_[5]\,
      I3 => \wrcal_reads_reg_n_0_[6]\,
      I4 => wrcal_reads,
      O => \wrcal_reads[6]_i_1_n_0\
    );
\wrcal_reads[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAEAAAA"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => \init_state_r_reg_n_0_[5]\,
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => init_state_r(6),
      I4 => \wrcal_reads[7]_i_5_n_0\,
      I5 => \wrcal_reads[7]_i_6_n_0\,
      O => wrcal_reads05_out
    );
\wrcal_reads[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[5]\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads[7]_i_7_n_0\,
      I3 => \wrcal_reads_reg_n_0_[6]\,
      I4 => \wrcal_reads_reg_n_0_[7]\,
      I5 => wrcal_reads,
      O => \wrcal_reads[7]_i_2_n_0\
    );
\wrcal_reads[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEF0010"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[5]\,
      I1 => \wrcal_reads_reg_n_0_[4]\,
      I2 => \wrcal_reads[7]_i_7_n_0\,
      I3 => \wrcal_reads_reg_n_0_[6]\,
      I4 => \wrcal_reads_reg_n_0_[7]\,
      I5 => wrcal_reads,
      O => \wrcal_reads[7]_i_3_n_0\
    );
\wrcal_reads[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[2]\,
      I1 => \init_state_r_reg_n_0_[3]\,
      O => \wrcal_reads[7]_i_5_n_0\
    );
\wrcal_reads[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      O => \wrcal_reads[7]_i_6_n_0\
    );
\wrcal_reads[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \wrcal_reads_reg_n_0_[2]\,
      I1 => \wrcal_reads_reg_n_0_[1]\,
      I2 => \wrcal_reads_reg_n_0_[0]\,
      I3 => \wrcal_reads_reg_n_0_[3]\,
      O => \wrcal_reads[7]_i_7_n_0\
    );
\wrcal_reads[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => \wrcal_reads[7]_i_9_n_0\,
      I1 => \wrcal_reads_reg_n_0_[5]\,
      I2 => \wrcal_reads_reg_n_0_[4]\,
      I3 => \wrcal_reads[7]_i_7_n_0\,
      I4 => \wrcal_reads_reg_n_0_[6]\,
      I5 => \wrcal_reads_reg_n_0_[7]\,
      O => wrcal_reads
    );
\wrcal_reads[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000004000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \wrcal_reads[7]_i_5_n_0\,
      I3 => init_state_r(6),
      I4 => \init_state_r_reg_n_0_[4]\,
      I5 => \init_state_r_reg_n_0_[5]\,
      O => \wrcal_reads[7]_i_9_n_0\
    );
\wrcal_reads_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[0]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[0]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[1]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[1]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[2]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[2]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[3]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[3]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[4]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[4]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[5]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[5]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[6]_i_1_n_0\,
      Q => \wrcal_reads_reg_n_0_[6]\,
      R => wrcal_reads05_out
    );
\wrcal_reads_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_reads[7]_i_2_n_0\,
      D => \wrcal_reads[7]_i_3_n_0\,
      Q => \wrcal_reads_reg_n_0_[7]\,
      R => wrcal_reads05_out
    );
wrcal_resume_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_resume_w,
      Q => wrcal_resume_r,
      R => '0'
    );
wrcal_sanity_chk_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_final_chk,
      Q => wrcal_sanity_chk,
      R => '0'
    );
\wrcal_start_dly_r_reg[4]_srl5\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '0',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => wrcal_start_pre,
      Q => \wrcal_start_dly_r_reg[4]_srl5_n_0\
    );
\wrcal_start_dly_r_reg[4]_srl5_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040000000800"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[1]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \oclk_wr_cnt[3]_i_5_n_0\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => wrcal_start_pre
    );
\wrcal_start_dly_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_start_dly_r_reg[4]_srl5_n_0\,
      Q => wrcal_start_dly_r(5),
      R => '0'
    );
wrcal_start_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \^wrcal_start_reg_0\,
      I1 => wrcal_start_dly_r(5),
      I2 => wrlvl_byte_redo,
      I3 => \rstdiv0_sync_r1_reg_rep__23\,
      O => wrcal_start_i_1_n_0
    );
wrcal_start_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_start_i_1_n_0,
      Q => \^wrcal_start_reg_0\,
      R => '0'
    );
\wrcal_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wrcal_wr_cnt_reg__0\(0),
      O => \wrcal_wr_cnt[0]_i_1_n_0\
    );
\wrcal_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \wrcal_wr_cnt_reg__0\(0),
      I1 => \wrcal_wr_cnt_reg__0\(1),
      O => \wrcal_wr_cnt[1]_i_1_n_0\
    );
\wrcal_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \wrcal_wr_cnt_reg__0\(2),
      I1 => \wrcal_wr_cnt_reg__0\(1),
      I2 => \wrcal_wr_cnt_reg__0\(0),
      O => wrcal_wr_cnt0(2)
    );
\wrcal_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAAB"
    )
        port map (
      I0 => \wrcal_wr_cnt[3]_i_4_n_0\,
      I1 => \wrcal_wr_cnt_reg__0\(1),
      I2 => \wrcal_wr_cnt_reg__0\(0),
      I3 => \wrcal_wr_cnt_reg__0\(3),
      I4 => \wrcal_wr_cnt_reg__0\(2),
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => \init_state_r[0]_i_3_n_0\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \wrcal_wr_cnt[3]_i_2_n_0\
    );
\wrcal_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCC9"
    )
        port map (
      I0 => \wrcal_wr_cnt_reg__0\(2),
      I1 => \wrcal_wr_cnt_reg__0\(3),
      I2 => \wrcal_wr_cnt_reg__0\(0),
      I3 => \wrcal_wr_cnt_reg__0\(1),
      O => wrcal_wr_cnt0(3)
    );
\wrcal_wr_cnt[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => prech_req_r_i_2_n_0,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \init_state_r_reg_n_0_[5]\,
      I4 => \init_state_r_reg_n_0_[3]\,
      I5 => \init_state_r_reg_n_0_[2]\,
      O => \wrcal_wr_cnt[3]_i_4_n_0\
    );
\wrcal_wr_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => \wrcal_wr_cnt[0]_i_1_n_0\,
      Q => \wrcal_wr_cnt_reg__0\(0),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => \wrcal_wr_cnt[1]_i_1_n_0\,
      Q => \wrcal_wr_cnt_reg__0\(1),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => wrcal_wr_cnt0(2),
      Q => \wrcal_wr_cnt_reg__0\(2),
      S => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrcal_wr_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_wr_cnt[3]_i_2_n_0\,
      D => wrcal_wr_cnt0(3),
      Q => \wrcal_wr_cnt_reg__0\(3),
      R => \wrcal_wr_cnt[3]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^first_rdlvl_pat_r\,
      I1 => rdlvl_stg1_done_reg,
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^first_wrcal_pat_r\,
      I1 => rdlvl_stg1_done_reg,
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^first_wrcal_pat_r\,
      I1 => rdlvl_stg1_done_reg,
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1_n_0\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[125]_i_1_n_0\,
      Q => phy_wrdata(125),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[190]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[190]_i_1_n_0\,
      Q => phy_wrdata(190),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => D(1),
      Q => phy_wrdata(445),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => rdlvl_stg1_done_reg_4,
      Q => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep_n_0\,
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => rdlvl_stg1_done_reg,
      Q => phy_wrdata(447),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[505]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => D(2),
      Q => phy_wrdata(505),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[510]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[510]_i_1_n_0\,
      Q => phy_wrdata(510),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => D(3),
      Q => phy_wrdata(511),
      R => '0'
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => D(0),
      Q => phy_wrdata(61),
      R => '0'
    );
write_calib_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DDD0"
    )
        port map (
      I0 => done_dqs_tap_inc,
      I1 => wrlvl_final_if_rst_i_2_n_0,
      I2 => wrlvl_active_r1,
      I3 => \^phy_write_calib\,
      I4 => \rstdiv0_sync_r1_reg_rep__23\,
      O => write_calib_i_1_n_0
    );
write_calib_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => write_calib_i_1_n_0,
      Q => \^phy_write_calib\,
      R => '0'
    );
wrlvl_active_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000005540"
    )
        port map (
      I0 => wrlvl_rank_done,
      I1 => wrlvl_odt,
      I2 => \en_cnt_div4.wrlvl_odt_i_2_n_0\,
      I3 => wrlvl_active,
      I4 => done_dqs_tap_inc,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => wrlvl_active_i_1_n_0
    );
wrlvl_active_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_active,
      Q => wrlvl_active_r1,
      R => '0'
    );
wrlvl_active_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_active_i_1_n_0,
      Q => wrlvl_active,
      R => '0'
    );
wrlvl_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_done_r,
      Q => \^wrlvl_done_r1\,
      R => '0'
    );
wrlvl_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_reg,
      Q => wrlvl_done_r,
      R => '0'
    );
wrlvl_final_if_rst_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010101110"
    )
        port map (
      I0 => \wrcal_wr_cnt[3]_i_2_n_0\,
      I1 => \rstdiv0_sync_r1_reg_rep__23\,
      I2 => \^wrlvl_final_if_rst\,
      I3 => wrlvl_done_r,
      I4 => wrlvl_final_if_rst_i_2_n_0,
      I5 => \num_refresh[3]_i_5_n_0\,
      O => wrlvl_final_if_rst_i_1_n_0
    );
wrlvl_final_if_rst_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[3]\,
      I1 => \init_state_r_reg_n_0_[0]\,
      I2 => \cnt_init_mr_r[1]_i_4_n_0\,
      I3 => \init_state_r_reg_n_0_[4]\,
      I4 => init_state_r(6),
      I5 => \init_state_r_reg_n_0_[1]\,
      O => wrlvl_final_if_rst_i_2_n_0
    );
wrlvl_final_if_rst_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_final_if_rst_i_1_n_0,
      Q => \^wrlvl_final_if_rst\,
      R => '0'
    );
wrlvl_odt_ctl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000400FFFF"
    )
        port map (
      I0 => init_state_r1(0),
      I1 => init_state_r1(1),
      I2 => init_state_r1(3),
      I3 => wrlvl_odt_ctl_i_2_n_0,
      I4 => wrlvl_odt_ctl_i_3_n_0,
      I5 => wrlvl_odt_ctl_i_4_n_0,
      O => wrlvl_odt_ctl_i_1_n_0
    );
wrlvl_odt_ctl_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => init_state_r1(6),
      I1 => init_state_r1(2),
      I2 => init_state_r1(4),
      I3 => init_state_r1(5),
      O => wrlvl_odt_ctl_i_2_n_0
    );
wrlvl_odt_ctl_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \init_state_r_reg_n_0_[5]\,
      I1 => init_state_r(6),
      I2 => \init_state_r_reg_n_0_[4]\,
      I3 => \wrcal_reads[7]_i_5_n_0\,
      I4 => \init_state_r_reg_n_0_[0]\,
      I5 => \init_state_r_reg_n_0_[1]\,
      O => wrlvl_odt_ctl_i_3_n_0
    );
wrlvl_odt_ctl_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBAB"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => wrlvl_odt_ctl,
      I2 => wrlvl_rank_done,
      I3 => wrlvl_rank_done_r1,
      O => wrlvl_odt_ctl_i_4_n_0
    );
wrlvl_odt_ctl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_odt_ctl_i_1_n_0,
      Q => wrlvl_odt_ctl,
      R => '0'
    );
wrlvl_rank_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_rank_done,
      Q => wrlvl_rank_done_r1,
      R => '0'
    );
wrlvl_rank_done_r6_reg_srl5: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '0',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => wrlvl_rank_done_r1,
      Q => wrlvl_rank_done_r6_reg_srl5_n_0
    );
wrlvl_rank_done_r7_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_rank_done_r6_reg_srl5_n_0,
      Q => wrlvl_rank_done_r7,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_rdlvl is
  port (
    idelay_tap_limit_r_reg_0 : out STD_LOGIC;
    mpr_rdlvl_start_r : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    idelay_ce_int : out STD_LOGIC;
    idelay_inc_int : out STD_LOGIC;
    rdlvl_prech_req : out STD_LOGIC;
    pi_fine_dly_dec_done : out STD_LOGIC;
    fine_dly_dec_done_r1_reg_0 : out STD_LOGIC;
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\ : out STD_LOGIC;
    rdlvl_stg1_rank_done : out STD_LOGIC;
    rdlvl_last_byte_done : out STD_LOGIC;
    COUNTERLOADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[4]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[0]_0\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[8]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[8]_0\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[10]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \stg1_wr_rd_cnt_reg[3]\ : out STD_LOGIC;
    \init_state_r_reg[4]\ : out STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][3][4]_0\ : out STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][0][4]_0\ : out STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][2][4]_0\ : out STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][1][4]_0\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ : out STD_LOGIC;
    \rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[0]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]_0\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]_1\ : out STD_LOGIC;
    \init_state_r_reg[4]_0\ : out STD_LOGIC;
    prbs_rdlvl_done_pulse0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_state_r_reg[2]\ : out STD_LOGIC;
    \init_state_r_reg[4]_1\ : out STD_LOGIC;
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep\ : out STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][7][4]_0\ : out STD_LOGIC;
    \cal1_cnt_cpt_r_reg[1]_0\ : out STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]\ : out STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[2]\ : out STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : out STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : out STD_LOGIC;
    cmd_delay_start0 : out STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CLK : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_63\ : in STD_LOGIC;
    mpr_rdlvl_start_reg : in STD_LOGIC;
    rdlvl_stg1_start_reg : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    dqs_po_dec_done : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    calib_in_common : in STD_LOGIC;
    \calib_zero_inputs_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rstdiv0_sync_r1_reg_rep__22\ : in STD_LOGIC;
    stg1_wr_done : in STD_LOGIC;
    \one_rank.stg1_wr_done_reg\ : in STD_LOGIC;
    pi_dqs_found_done : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    tempmon_pi_f_en_r : in STD_LOGIC;
    tempmon_pi_f_inc_r : in STD_LOGIC;
    wrlvl_done_r1 : in STD_LOGIC;
    rdlvl_stg1_done_r1 : in STD_LOGIC;
    mem_init_done_r : in STD_LOGIC;
    wrcal_done_reg : in STD_LOGIC;
    first_rdlvl_pat_r : in STD_LOGIC;
    first_wrcal_pat_r : in STD_LOGIC;
    \pi_counter_read_val_reg[2]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[3]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[4]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[5]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[0]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[1]\ : in STD_LOGIC;
    prech_done : in STD_LOGIC;
    \pi_counter_read_val_reg[2]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \po_stg2_wrcal_cnt_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    new_cnt_cpt_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_start_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    clear : in STD_LOGIC;
    pi_cnt_dec_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cal1_state_r1536_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_rdlvl : entity is "mig_7series_v2_3_ddr_phy_rdlvl";
end mig_7series_0_mig_7series_v2_3_ddr_phy_rdlvl;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_rdlvl is
  signal \FSM_onehot_cal1_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[17]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[17]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[18]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[19]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[19]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[19]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[19]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[20]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[21]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[22]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[23]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[23]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[23]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[24]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[24]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[25]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[26]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[27]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[27]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[27]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[28]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[29]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[29]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[29]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[30]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[31]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_15_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[32]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_cal1_state_r_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[10]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[10]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[11]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[11]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[14]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[14]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[15]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[15]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[18]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[18]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[21]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[21]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[22]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[22]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[23]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[23]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[25]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[25]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[26]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[26]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[29]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[29]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[30]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[30]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[31]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[31]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[7]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[7]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[8]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[8]\ : signal is "yes";
  signal \FSM_onehot_cal1_state_r_reg_n_0_[9]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_cal1_state_r_reg_n_0_[9]\ : signal is "yes";
  signal \cal1_cnt_cpt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \^cal1_cnt_cpt_r_reg[1]_0\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal1_cnt_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal cal1_dlyce_cpt_r : STD_LOGIC;
  signal cal1_dlyce_cpt_r_reg_n_0 : STD_LOGIC;
  signal cal1_dlyinc_cpt_r_i_1_n_0 : STD_LOGIC;
  signal cal1_dlyinc_cpt_r_reg_n_0 : STD_LOGIC;
  signal cal1_dq_idel_ce : STD_LOGIC;
  signal cal1_dq_idel_inc : STD_LOGIC;
  attribute RTL_KEEP of cal1_dq_idel_inc : signal is "yes";
  signal cal1_prech_req_r_reg_n_0 : STD_LOGIC;
  signal cal1_state_r1 : STD_LOGIC;
  signal \cal1_state_r1[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[0]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[1]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[1]_i_3_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[2]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[3]_i_2_n_0\ : STD_LOGIC;
  signal \cal1_state_r1[4]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal \cal1_state_r1_reg_n_0_[5]\ : STD_LOGIC;
  signal cal1_state_r2 : STD_LOGIC;
  signal cal1_wait_cnt_en_r : STD_LOGIC;
  signal cal1_wait_cnt_en_r0 : STD_LOGIC;
  signal cal1_wait_cnt_en_r_i_2_n_0 : STD_LOGIC;
  signal cal1_wait_cnt_en_r_i_3_n_0 : STD_LOGIC;
  signal \cal1_wait_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \cal1_wait_cnt_r_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal cal1_wait_r : STD_LOGIC;
  signal cal1_wait_r_i_1_n_0 : STD_LOGIC;
  signal cnt_idel_dec_cpt_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal cnt_idel_dec_cpt_r2 : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \cnt_idel_dec_cpt_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_10_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_8_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[4]_i_9_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_10_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_11_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_12_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_13_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_7_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r[5]_i_8_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_6_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_6_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_6_n_2\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_6_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_6_n_4\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_6_n_5\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[2]_i_6_n_6\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[3]_i_5_n_0\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[3]_i_5_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[3]_i_5_n_2\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[3]_i_5_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_6_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_6_n_6\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[4]_i_6_n_7\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[5]_i_9_n_1\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg[5]_i_9_n_3\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \cnt_idel_dec_cpt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \cnt_shift_r_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal detect_edge_done_r : STD_LOGIC;
  signal detect_edge_done_r_i_1_n_0 : STD_LOGIC;
  signal detect_edge_done_r_i_2_n_0 : STD_LOGIC;
  signal done_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal done_cnt1 : STD_LOGIC;
  signal \done_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \done_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal dqs_po_dec_done_r1 : STD_LOGIC;
  signal dqs_po_dec_done_r2 : STD_LOGIC;
  signal fine_dly_dec_done_r1 : STD_LOGIC;
  signal fine_dly_dec_done_r1_i_1_n_0 : STD_LOGIC;
  signal fine_dly_dec_done_r1_i_2_n_0 : STD_LOGIC;
  signal \^fine_dly_dec_done_r1_reg_0\ : STD_LOGIC;
  signal fine_dly_dec_done_r2 : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \first_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal found_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_edge_r_i_2_n_0 : STD_LOGIC;
  signal found_edge_r_reg_n_0 : STD_LOGIC;
  signal found_first_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_first_edge_r_reg_n_0 : STD_LOGIC;
  signal found_second_edge_r_i_1_n_0 : STD_LOGIC;
  signal found_second_edge_r_reg_n_0 : STD_LOGIC;
  signal found_stable_eye_last_r : STD_LOGIC;
  signal found_stable_eye_last_r_i_1_n_0 : STD_LOGIC;
  signal found_stable_eye_r_i_1_n_0 : STD_LOGIC;
  signal found_stable_eye_r_i_2_n_0 : STD_LOGIC;
  signal found_stable_eye_r_reg_n_0 : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_255\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_239\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_279\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_287\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_247\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_263\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_271\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_295\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_207\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_175\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_231\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_191\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_223\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_215\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_183\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_199\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_256\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_240\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_280\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_288\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_248\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_264\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_272\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_296\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_208\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_176\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_232\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_192\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_224\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_216\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_184\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_200\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_257\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_241\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_281\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_289\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_249\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_265\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_273\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_297\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_209\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_177\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_233\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_193\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_225\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_217\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_185\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_201\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_258\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_242\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_282\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_290\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_250\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_266\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_274\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_298\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_210\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_178\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_234\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_194\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_226\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_218\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_186\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_202\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_259\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_243\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_283\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_291\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_251\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_267\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_275\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_299\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_211\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_179\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_235\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_195\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_227\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_219\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_187\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_203\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_260\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_244\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_284\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_292\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_252\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_268\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_276\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_300\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_212\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_180\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_236\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_196\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_228\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_220\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_188\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_204\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_261\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_245\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_285\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_293\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_253\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_269\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_277\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_301\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_213\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_181\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_237\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_197\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_229\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_221\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_189\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_205\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_262\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_246\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_286\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_294\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_254\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_270\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_278\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_302\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_214\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_182\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_238\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_198\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_230\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_222\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_190\ : STD_LOGIC;
  signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_206\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4_n_0\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_found_stable_eye_r_reg\ : STD_LOGIC;
  signal \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\ : STD_LOGIC;
  signal idel_adj_inc_i_1_n_0 : STD_LOGIC;
  signal idel_adj_inc_i_2_n_0 : STD_LOGIC;
  signal idel_adj_inc_reg_n_0 : STD_LOGIC;
  signal idel_dec_cnt : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idel_dec_cnt[0]_i_3_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[0]_i_4_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_4_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_6_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt[4]_i_7_n_0\ : STD_LOGIC;
  signal \idel_dec_cnt__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idel_dec_cnt_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal idel_mpr_pat_detect_r : STD_LOGIC;
  signal \idel_pat0_data_match_r0__0\ : STD_LOGIC;
  signal idel_pat0_match_fall0_and_r : STD_LOGIC;
  signal idel_pat0_match_fall1_and_r : STD_LOGIC;
  signal idel_pat0_match_fall2_and_r : STD_LOGIC;
  signal idel_pat0_match_fall3_and_r : STD_LOGIC;
  signal idel_pat0_match_rise0_and_r : STD_LOGIC;
  signal idel_pat0_match_rise1_and_r : STD_LOGIC;
  signal idel_pat0_match_rise2_and_r : STD_LOGIC;
  signal idel_pat0_match_rise3_and_r : STD_LOGIC;
  signal \idel_pat1_data_match_r0__0\ : STD_LOGIC;
  signal idel_pat1_match_fall0_and_r : STD_LOGIC;
  signal idel_pat1_match_fall1_and_r : STD_LOGIC;
  signal idel_pat1_match_fall2_and_r : STD_LOGIC;
  signal idel_pat1_match_fall3_and_r : STD_LOGIC;
  signal idel_pat1_match_rise0_and_r : STD_LOGIC;
  signal idel_pat1_match_rise1_and_r : STD_LOGIC;
  signal idel_pat1_match_rise2_and_r : STD_LOGIC;
  signal idel_pat1_match_rise3_and_r : STD_LOGIC;
  signal idel_pat_detect_valid_r_i_1_n_0 : STD_LOGIC;
  signal idel_pat_detect_valid_r_reg_n_0 : STD_LOGIC;
  signal \^idelay_ce_int\ : STD_LOGIC;
  signal \^idelay_inc_int\ : STD_LOGIC;
  signal idelay_tap_cnt_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idelay_tap_cnt_r[0][0][0]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][1]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][2]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][3]_i_1_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][3]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][4]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][4]_i_6_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][2][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][3][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][4][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][5][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][6][4]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][0]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][1]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][2]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][3]\ : STD_LOGIC;
  signal \idelay_tap_cnt_r_reg_n_0_[0][7][4]\ : STD_LOGIC;
  signal idelay_tap_cnt_slice_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \idelay_tap_cnt_slice_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_slice_r[4]_i_3_n_0\ : STD_LOGIC;
  signal idelay_tap_limit_r_i_1_n_0 : STD_LOGIC;
  signal idelay_tap_limit_r_i_2_n_0 : STD_LOGIC;
  signal \^idelay_tap_limit_r_reg_0\ : STD_LOGIC;
  signal idelay_tap_limit_r_reg_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\ : STD_LOGIC;
  signal \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\ : STD_LOGIC;
  signal \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal mpr_dec_cpt_r : STD_LOGIC;
  signal mpr_dec_cpt_r_i_1_n_0 : STD_LOGIC;
  signal mpr_dec_cpt_r_reg_n_0 : STD_LOGIC;
  signal mpr_rd_fall0_prev_r : STD_LOGIC;
  signal mpr_rd_fall1_prev_r : STD_LOGIC;
  signal mpr_rd_fall2_prev_r : STD_LOGIC;
  signal mpr_rd_fall3_prev_r : STD_LOGIC;
  signal mpr_rd_rise0_prev_r : STD_LOGIC;
  signal mpr_rd_rise0_prev_r0 : STD_LOGIC;
  signal mpr_rd_rise1_prev_r : STD_LOGIC;
  signal mpr_rd_rise2_prev_r : STD_LOGIC;
  signal mpr_rd_rise3_prev_r : STD_LOGIC;
  signal \^mpr_rdlvl_start_r\ : STD_LOGIC;
  signal new_cnt_cpt_r : STD_LOGIC;
  signal new_cnt_cpt_r_i_2_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in102_in : STD_LOGIC;
  signal p_0_in10_in : STD_LOGIC;
  signal p_0_in134_in : STD_LOGIC;
  signal p_0_in13_in : STD_LOGIC;
  signal p_0_in156_in : STD_LOGIC;
  signal p_0_in16_in : STD_LOGIC;
  signal p_0_in181_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in206_in : STD_LOGIC;
  signal p_0_in231_in : STD_LOGIC;
  signal p_0_in256_in : STD_LOGIC;
  signal p_0_in281_in : STD_LOGIC;
  signal p_0_in306_in : STD_LOGIC;
  signal p_0_in331_in : STD_LOGIC;
  signal p_0_in356_in : STD_LOGIC;
  signal p_0_in381_in : STD_LOGIC;
  signal p_0_in406_in : STD_LOGIC;
  signal p_0_in431_in : STD_LOGIC;
  signal p_0_in456_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_0_in540_in : STD_LOGIC;
  attribute RTL_KEEP of p_0_in540_in : signal is "yes";
  signal p_0_in7_in : STD_LOGIC;
  signal p_0_in87_in : STD_LOGIC;
  signal p_0_in90_in : STD_LOGIC;
  signal p_0_in93_in : STD_LOGIC;
  signal p_0_in96_in : STD_LOGIC;
  signal p_0_in99_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__10\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal p_12_in : STD_LOGIC;
  attribute RTL_KEEP of p_12_in : signal is "yes";
  signal \p_138_out__0\ : STD_LOGIC;
  signal \p_164_out__0\ : STD_LOGIC;
  signal \p_189_out__0\ : STD_LOGIC;
  signal p_1_in11_in : STD_LOGIC;
  signal p_1_in137_in : STD_LOGIC;
  signal p_1_in14_in : STD_LOGIC;
  signal p_1_in163_in : STD_LOGIC;
  signal p_1_in17_in : STD_LOGIC;
  signal p_1_in188_in : STD_LOGIC;
  signal p_1_in213_in : STD_LOGIC;
  signal p_1_in238_in : STD_LOGIC;
  signal p_1_in263_in : STD_LOGIC;
  signal p_1_in26_in : STD_LOGIC;
  attribute RTL_KEEP of p_1_in26_in : signal is "yes";
  signal p_1_in288_in : STD_LOGIC;
  signal p_1_in2_in : STD_LOGIC;
  signal p_1_in313_in : STD_LOGIC;
  signal p_1_in338_in : STD_LOGIC;
  signal p_1_in363_in : STD_LOGIC;
  signal p_1_in388_in : STD_LOGIC;
  signal p_1_in413_in : STD_LOGIC;
  signal p_1_in438_in : STD_LOGIC;
  signal p_1_in463_in : STD_LOGIC;
  signal p_1_in5_in : STD_LOGIC;
  signal p_1_in8_in : STD_LOGIC;
  signal \p_214_out__0\ : STD_LOGIC;
  signal \p_239_out__0\ : STD_LOGIC;
  signal \p_264_out__0\ : STD_LOGIC;
  signal p_27_in : STD_LOGIC;
  attribute RTL_KEEP of p_27_in : signal is "yes";
  signal \p_289_out__0\ : STD_LOGIC;
  signal p_2_in157_in : STD_LOGIC;
  signal p_2_in182_in : STD_LOGIC;
  signal p_2_in207_in : STD_LOGIC;
  signal p_2_in232_in : STD_LOGIC;
  signal p_2_in257_in : STD_LOGIC;
  signal p_2_in282_in : STD_LOGIC;
  signal p_2_in307_in : STD_LOGIC;
  signal p_2_in332_in : STD_LOGIC;
  signal p_2_in33_in : STD_LOGIC;
  attribute RTL_KEEP of p_2_in33_in : signal is "yes";
  signal p_2_in357_in : STD_LOGIC;
  signal p_2_in382_in : STD_LOGIC;
  signal p_2_in407_in : STD_LOGIC;
  signal p_2_in432_in : STD_LOGIC;
  signal p_2_in457_in : STD_LOGIC;
  signal \p_314_out__0\ : STD_LOGIC;
  signal \p_339_out__0\ : STD_LOGIC;
  signal p_34_in : STD_LOGIC;
  attribute RTL_KEEP of p_34_in : signal is "yes";
  signal \p_364_out__0\ : STD_LOGIC;
  signal \p_389_out__0\ : STD_LOGIC;
  signal p_3_in135_in : STD_LOGIC;
  signal p_3_in158_in : STD_LOGIC;
  signal p_3_in183_in : STD_LOGIC;
  signal p_3_in208_in : STD_LOGIC;
  signal p_3_in233_in : STD_LOGIC;
  signal p_3_in258_in : STD_LOGIC;
  signal p_3_in283_in : STD_LOGIC;
  signal p_3_in308_in : STD_LOGIC;
  signal p_3_in333_in : STD_LOGIC;
  signal p_3_in358_in : STD_LOGIC;
  signal p_3_in383_in : STD_LOGIC;
  signal p_3_in408_in : STD_LOGIC;
  signal p_3_in433_in : STD_LOGIC;
  signal p_3_in458_in : STD_LOGIC;
  signal \p_414_out__0\ : STD_LOGIC;
  signal \p_439_out__0\ : STD_LOGIC;
  signal \p_464_out__0\ : STD_LOGIC;
  signal \p_489_out__0\ : STD_LOGIC;
  signal p_4_in159_in : STD_LOGIC;
  signal p_4_in184_in : STD_LOGIC;
  signal p_4_in209_in : STD_LOGIC;
  signal p_4_in234_in : STD_LOGIC;
  signal p_4_in259_in : STD_LOGIC;
  signal p_4_in284_in : STD_LOGIC;
  signal p_4_in309_in : STD_LOGIC;
  signal p_4_in334_in : STD_LOGIC;
  signal p_4_in359_in : STD_LOGIC;
  signal p_4_in384_in : STD_LOGIC;
  signal p_4_in409_in : STD_LOGIC;
  signal p_4_in434_in : STD_LOGIC;
  signal p_4_in459_in : STD_LOGIC;
  signal \p_514_out__0\ : STD_LOGIC;
  signal p_5_in : STD_LOGIC;
  attribute RTL_KEEP of p_5_in : signal is "yes";
  signal p_5_in160_in : STD_LOGIC;
  signal p_5_in185_in : STD_LOGIC;
  signal p_5_in210_in : STD_LOGIC;
  signal p_5_in235_in : STD_LOGIC;
  signal p_5_in260_in : STD_LOGIC;
  signal p_5_in285_in : STD_LOGIC;
  signal p_5_in310_in : STD_LOGIC;
  signal p_5_in335_in : STD_LOGIC;
  signal p_5_in360_in : STD_LOGIC;
  signal p_5_in385_in : STD_LOGIC;
  signal p_5_in410_in : STD_LOGIC;
  signal p_5_in435_in : STD_LOGIC;
  signal p_5_in460_in : STD_LOGIC;
  signal p_6_in136_in : STD_LOGIC;
  signal p_6_in161_in : STD_LOGIC;
  signal p_6_in186_in : STD_LOGIC;
  signal p_6_in211_in : STD_LOGIC;
  signal p_6_in236_in : STD_LOGIC;
  signal p_6_in261_in : STD_LOGIC;
  signal p_6_in286_in : STD_LOGIC;
  signal p_6_in311_in : STD_LOGIC;
  signal p_6_in336_in : STD_LOGIC;
  signal p_6_in361_in : STD_LOGIC;
  signal p_6_in386_in : STD_LOGIC;
  signal p_6_in411_in : STD_LOGIC;
  signal p_6_in436_in : STD_LOGIC;
  signal p_6_in461_in : STD_LOGIC;
  signal p_7_in : STD_LOGIC;
  attribute RTL_KEEP of p_7_in : signal is "yes";
  signal p_7_in162_in : STD_LOGIC;
  signal p_7_in187_in : STD_LOGIC;
  signal p_7_in212_in : STD_LOGIC;
  signal p_7_in237_in : STD_LOGIC;
  signal p_7_in262_in : STD_LOGIC;
  signal p_7_in287_in : STD_LOGIC;
  signal p_7_in312_in : STD_LOGIC;
  signal p_7_in337_in : STD_LOGIC;
  signal p_7_in362_in : STD_LOGIC;
  signal p_7_in387_in : STD_LOGIC;
  signal p_7_in412_in : STD_LOGIC;
  signal p_7_in437_in : STD_LOGIC;
  signal p_7_in462_in : STD_LOGIC;
  signal p_8_in : STD_LOGIC;
  attribute RTL_KEEP of p_8_in : signal is "yes";
  signal p_9_in : STD_LOGIC;
  attribute RTL_KEEP of p_9_in : signal is "yes";
  signal \pat0_data_match_r0__0\ : STD_LOGIC;
  signal pat0_match_fall0_and_r : STD_LOGIC;
  signal pat0_match_fall1_and_r : STD_LOGIC;
  signal pat0_match_fall2_and_r : STD_LOGIC;
  signal pat0_match_fall3_and_r : STD_LOGIC;
  signal pat0_match_rise0_and_r : STD_LOGIC;
  signal pat0_match_rise1_and_r : STD_LOGIC;
  signal pat0_match_rise2_and_r : STD_LOGIC;
  signal pat0_match_rise3_and_r : STD_LOGIC;
  signal \pat1_data_match_r0__0\ : STD_LOGIC;
  signal pat1_match_fall0_and_r : STD_LOGIC;
  signal pat1_match_fall1_and_r : STD_LOGIC;
  signal pat1_match_fall2_and_r : STD_LOGIC;
  signal pat1_match_fall3_and_r : STD_LOGIC;
  signal pat1_match_rise0_and_r : STD_LOGIC;
  signal pat1_match_rise1_and_r : STD_LOGIC;
  signal pat1_match_rise2_and_r : STD_LOGIC;
  signal pat1_match_rise3_and_r : STD_LOGIC;
  signal pb_cnt_eye_size_r : STD_LOGIC;
  signal pb_detect_edge : STD_LOGIC;
  signal pb_detect_edge_done_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pb_detect_edge_setup : STD_LOGIC;
  signal pb_found_stable_eye_r53_out : STD_LOGIC;
  signal pb_found_stable_eye_r57_out : STD_LOGIC;
  signal pb_found_stable_eye_r61_out : STD_LOGIC;
  signal pb_found_stable_eye_r65_out : STD_LOGIC;
  signal pb_found_stable_eye_r69_out : STD_LOGIC;
  signal pb_found_stable_eye_r73_out : STD_LOGIC;
  signal pb_found_stable_eye_r77_out : STD_LOGIC;
  signal pi_cnt_dec_i_1_n_0 : STD_LOGIC;
  signal pi_cnt_dec_i_2_n_0 : STD_LOGIC;
  signal pi_counter_load_en : STD_LOGIC;
  signal pi_counter_load_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal pi_en_stg2_f_timing : STD_LOGIC;
  signal pi_en_stg2_f_timing_i_1_n_0 : STD_LOGIC;
  signal \^pi_fine_dly_dec_done\ : STD_LOGIC;
  signal pi_rdval_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pi_rdval_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \pi_rdval_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal pi_stg2_f_incdec_timing : STD_LOGIC;
  signal pi_stg2_f_incdec_timing0 : STD_LOGIC;
  signal pi_stg2_load_timing : STD_LOGIC;
  signal pi_stg2_load_timing_i_1_n_0 : STD_LOGIC;
  signal pi_stg2_reg_l_timing : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pi_stg2_reg_l_timing[0]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[0]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[1]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[1]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[2]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[2]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[3]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[3]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[4]_i_2_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[4]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_1_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_3_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_4_n_0\ : STD_LOGIC;
  signal \pi_stg2_reg_l_timing[5]_i_5_n_0\ : STD_LOGIC;
  signal \rd_mux_sel_r_reg_n_0_[2]\ : STD_LOGIC;
  signal rdlvl_dqs_tap_cnt_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\ : STD_LOGIC;
  signal \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4]\ : STD_LOGIC;
  signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5]\ : STD_LOGIC;
  signal \^rdlvl_last_byte_done\ : STD_LOGIC;
  signal rdlvl_last_byte_done_i_1_n_0 : STD_LOGIC;
  signal rdlvl_pi_stg2_f_en : STD_LOGIC;
  signal rdlvl_pi_stg2_f_incdec : STD_LOGIC;
  signal rdlvl_rank_done_r : STD_LOGIC;
  signal rdlvl_rank_done_r_i_1_n_0 : STD_LOGIC;
  signal rdlvl_rank_done_r_i_2_n_0 : STD_LOGIC;
  signal rdlvl_stg1_done_i_1_n_0 : STD_LOGIC;
  signal \^rdlvl_stg1_rank_done\ : STD_LOGIC;
  signal rdlvl_stg1_start_r : STD_LOGIC;
  signal regl_dqs_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \regl_dqs_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \regl_dqs_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal regl_dqs_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal regl_rank_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal regl_rank_cnt0 : STD_LOGIC;
  signal \regl_rank_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \regl_rank_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \regl_rank_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal right_edge_taps_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \right_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \right_edge_taps_r__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rnk_cnt_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal samp_cnt_done_r_i_1_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_2_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_3_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_i_4_n_0 : STD_LOGIC;
  signal samp_cnt_done_r_reg_n_0 : STD_LOGIC;
  signal \^samp_edge_cnt0_en_r\ : STD_LOGIC;
  signal \samp_edge_cnt0_r[0]_i_3_n_0\ : STD_LOGIC;
  signal samp_edge_cnt0_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt0_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal samp_edge_cnt1_en_r : STD_LOGIC;
  signal samp_edge_cnt1_en_r0 : STD_LOGIC;
  signal samp_edge_cnt1_en_r_i_2_n_0 : STD_LOGIC;
  signal samp_edge_cnt1_en_r_i_3_n_0 : STD_LOGIC;
  signal \samp_edge_cnt1_r[0]_i_2_n_0\ : STD_LOGIC;
  signal samp_edge_cnt1_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[0]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \samp_edge_cnt1_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \second_edge_taps_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \second_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC;
  signal sr_valid_r1 : STD_LOGIC;
  signal sr_valid_r2 : STD_LOGIC;
  signal sr_valid_r_i_1_n_0 : STD_LOGIC;
  signal sr_valid_r_reg_n_0 : STD_LOGIC;
  signal stable_idel_cnt : STD_LOGIC;
  signal stable_idel_cnt0 : STD_LOGIC;
  signal stable_idel_cnt23_in : STD_LOGIC;
  signal store_sr_r0 : STD_LOGIC;
  signal store_sr_r_i_1_n_0 : STD_LOGIC;
  signal store_sr_r_reg_n_0 : STD_LOGIC;
  signal store_sr_req_pulsed_r : STD_LOGIC;
  attribute RTL_KEEP of store_sr_req_pulsed_r : signal is "yes";
  signal \store_sr_req_pulsed_r__0\ : STD_LOGIC;
  signal store_sr_req_r : STD_LOGIC;
  signal store_sr_req_r_reg_n_0 : STD_LOGIC;
  signal tap_cnt_cpt_r : STD_LOGIC;
  signal \tap_cnt_cpt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \tap_cnt_cpt_r_reg_n_0_[5]\ : STD_LOGIC;
  signal tap_limit_cpt_r : STD_LOGIC;
  signal tap_limit_cpt_r_i_1_n_0 : STD_LOGIC;
  signal tap_limit_cpt_r_i_2_n_0 : STD_LOGIC;
  signal wait_cnt_r0 : STD_LOGIC;
  signal \wait_cnt_r0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wait_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal wait_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\ : STD_LOGIC;
  signal \NLW_cnt_idel_dec_cpt_r_reg[2]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[3]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[0]_i_1\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[23]_i_2\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[28]_i_1\ : label is "soft_lutpair411";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[29]_i_1\ : label is "soft_lutpair411";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[32]_i_14\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[32]_i_15\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[32]_i_8\ : label is "soft_lutpair325";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[0]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[10]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[10]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[11]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[11]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[12]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[12]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[13]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[13]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[14]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[14]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[15]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[15]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[16]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[16]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[17]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[17]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[18]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[18]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[19]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[19]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[1]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[1]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[20]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[20]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[21]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[21]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[22]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[22]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[23]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[23]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[24]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[24]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[25]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[25]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[26]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[26]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[27]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[27]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[28]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[28]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[29]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[29]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[2]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[2]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[30]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[30]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[31]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[31]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[32]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[32]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[3]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[3]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[4]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[4]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[5]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[5]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[6]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[6]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[7]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[7]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[8]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[8]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[9]\ : label is "CAL1_IDLE:000000000000000000000000000000001,CAL1_MPR_NEW_DQS_WAIT:000000000000000000000000000000010,CAL1_NEW_DQS_WAIT:000000000000000000000000000000100,CAL1_PB_STORE_FIRST_WAIT:000000000000000000000000001000000,CAL1_PB_DETECT_EDGE:000000000000000000000000010000000,CAL1_PB_INC_CPT:000000000000000000000001000000000,CAL1_PB_INC_CPT_WAIT:000000000000000000000100000000000,CAL1_PB_DEC_CPT_LEFT:000000000000000000000000100000000,CAL1_PB_DEC_CPT_LEFT_WAIT:000000000000000000001000000000000,CAL1_PB_DETECT_EDGE_DQ:000000000000000000010000000000000,CAL1_PB_INC_DQ:000000000000000000100000000000000,CAL1_PB_INC_DQ_WAIT:000000000000000001000000000000000,CAL1_PB_DEC_CPT:000000000000000000000010000000000,CAL1_PB_DEC_CPT_WAIT:000000000000000010000000000000000,CAL1_STORE_FIRST_WAIT:000000000000000000000000000100000,CAL1_VALID_WAIT:000000000000001000000000000000000,CAL1_MPR_PAT_DETECT:000000000000000000000000000001000,CAL1_PAT_DETECT:000000000000000100000000000000000,CAL1_DQ_IDEL_TAP_INC:000000000000100000000000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:000000000010000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:000000000100000000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:000000001000000000000000000000000,CAL1_DETECT_EDGE:000000000000010000000000000000000,CAL1_IDEL_INC_CPT:000000100000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:000001000000000000000000000000000,CAL1_CALC_IDEL:000000010000000000000000000000000,CAL1_IDEL_DEC_CPT:000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:000010000000000000000000000000000,CAL1_NEXT_DQS:000100000000000000000000000000000,CAL1_NEW_DQS_PREWAIT:001000000000000000000000000000000,CAL1_REGL_LOAD:100000000000000000000000000000000,CAL1_RDLVL_ERR:000000000001000000000000000000000,CAL1_DONE:010000000000000000000000000000000";
  attribute KEEP of \FSM_onehot_cal1_state_r_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \cal1_cnt_cpt_r[1]_i_2\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[1]_i_1\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[2]_i_1\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[3]_i_1\ : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of \cal1_wait_cnt_r[4]_i_2\ : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[1]_i_5\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_11\ : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_3\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_7\ : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of \cnt_shift_r[2]_i_1\ : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \cnt_shift_r[3]_i_2\ : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \done_cnt[1]_i_1\ : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \done_cnt[3]_i_1\ : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \first_edge_taps_r[5]_i_3\ : label is "soft_lutpair405";
  attribute SOFT_HLUTNM of found_stable_eye_last_r_i_1 : label is "soft_lutpair405";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2\ : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair400";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\ : label is "soft_lutpair406";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_fall0_and_r_i_1\ : label is "soft_lutpair406";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_fall2_and_r_i_1\ : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair400";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair389";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair380";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair360";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair397";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair388";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair389";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair380";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair360";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair397";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair388";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair355";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair372";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair368";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair359";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair349";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair355";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair372";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair368";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair359";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair349";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair379";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair398";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair387";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair383";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair379";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair398";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair387";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair383";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair375";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair354";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair371";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair358";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair348";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair375";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair354";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair371";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair358";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair348";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair393";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair378";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair339";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair396";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair393";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair378";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair339";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair396";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair374";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair363";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair353";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair370";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair357";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair345";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair374";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair363";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair353";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair370";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair357";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair345";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair376";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair377";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair395";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair385";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair381";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair376";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair377";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair395";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair385";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair381";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair373";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair362";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair350";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair356";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair344";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair373";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair362";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair350";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair356";
  attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair344";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4\ : label is "soft_lutpair399";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\ : label is "soft_lutpair420";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\ : label is "soft_lutpair420";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\ : label is "soft_lutpair390";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\ : label is "soft_lutpair390";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4\ : label is "soft_lutpair401";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\ : label is "soft_lutpair422";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\ : label is "soft_lutpair422";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\ : label is "soft_lutpair391";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\ : label is "soft_lutpair391";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4\ : label is "soft_lutpair407";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\ : label is "soft_lutpair361";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\ : label is "soft_lutpair361";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4\ : label is "soft_lutpair407";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\ : label is "soft_lutpair352";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\ : label is "soft_lutpair352";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4\ : label is "soft_lutpair408";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\ : label is "soft_lutpair425";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\ : label is "soft_lutpair425";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\ : label is "soft_lutpair351";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\ : label is "soft_lutpair351";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4\ : label is "soft_lutpair408";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\ : label is "soft_lutpair421";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\ : label is "soft_lutpair421";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\ : label is "soft_lutpair347";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\ : label is "soft_lutpair347";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4\ : label is "soft_lutpair399";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\ : label is "soft_lutpair423";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\ : label is "soft_lutpair423";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\ : label is "soft_lutpair346";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\ : label is "soft_lutpair346";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4\ : label is "soft_lutpair401";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_5\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_6\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_7\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][0]_i_1\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][1]_i_1\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][3]_i_2\ : label is "soft_lutpair404";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][4]_i_4\ : label is "soft_lutpair402";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][4]_i_2\ : label is "soft_lutpair403";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][2][4]_i_2\ : label is "soft_lutpair403";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][3][4]_i_2\ : label is "soft_lutpair404";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[0]_i_1\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of idelay_tap_limit_r_i_1 : label is "soft_lutpair410";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_33\ : label is "soft_lutpair320";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_28\ : label is "soft_lutpair320";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_31\ : label is "soft_lutpair413";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_33\ : label is "soft_lutpair413";
  attribute SOFT_HLUTNM of \mpr_4to1.inhibit_edge_detect_r_i_2\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \mpr_4to1.inhibit_edge_detect_r_i_6\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[1]_i_1\ : label is "soft_lutpair282";
  attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[2]_i_1\ : label is "soft_lutpair282";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__0\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__1\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__2\ : label is "soft_lutpair308";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__3\ : label is "soft_lutpair308";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__4\ : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__5\ : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__0\ : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__1\ : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__2\ : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__3\ : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__4\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__5\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__0\ : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__1\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__2\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__3\ : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__4\ : label is "soft_lutpair272";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__5\ : label is "soft_lutpair272";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__0\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__1\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__2\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__3\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__4\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__5\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__0\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__1\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__2\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__3\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__4\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__5\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__0\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__1\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__2\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__3\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__4\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__5\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__0\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__1\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__2\ : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__3\ : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__4\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__5\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[0]_i_1\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \pi_rdval_cnt[5]_i_5\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of prbs_rdlvl_done_pulse_i_1 : label is "soft_lutpair415";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rdlvl_stg1_done_reg : label is "30";
  attribute SOFT_HLUTNM of \regl_dqs_cnt[2]_i_2\ : label is "soft_lutpair325";
  attribute SOFT_HLUTNM of \regl_rank_cnt[0]_i_1\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of \regl_rank_cnt[1]_i_1\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of \regl_rank_cnt[1]_i_2\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \regl_rank_cnt[1]_i_3\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \rnk_cnt_r[1]_i_2\ : label is "soft_lutpair402";
  attribute SOFT_HLUTNM of \second_edge_taps_r[1]_i_1\ : label is "soft_lutpair409";
  attribute SOFT_HLUTNM of \second_edge_taps_r[2]_i_1\ : label is "soft_lutpair409";
  attribute SOFT_HLUTNM of \second_edge_taps_r[3]_i_1\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \second_edge_taps_r[4]_i_1\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[4]_i_2\ : label is "soft_lutpair410";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[1]_i_1\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[2]_i_1\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[3]_i_1\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_4\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_5\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \wait_cnt_r[1]_i_1__0\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \wait_cnt_r[2]_i_1\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[445]_i_1\ : label is "soft_lutpair417";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[505]_i_1\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[511]_i_1\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[511]_i_2\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[61]_i_1\ : label is "soft_lutpair417";
begin
  \cal1_cnt_cpt_r_reg[1]_0\ <= \^cal1_cnt_cpt_r_reg[1]_0\;
  fine_dly_dec_done_r1_reg_0 <= \^fine_dly_dec_done_r1_reg_0\;
  idelay_ce_int <= \^idelay_ce_int\;
  idelay_inc_int <= \^idelay_inc_int\;
  idelay_tap_limit_r_reg_0 <= \^idelay_tap_limit_r_reg_0\;
  mpr_rdlvl_start_r <= \^mpr_rdlvl_start_r\;
  pi_fine_dly_dec_done <= \^pi_fine_dly_dec_done\;
  \rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1 downto 0) <= \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1 downto 0);
  rdlvl_last_byte_done <= \^rdlvl_last_byte_done\;
  rdlvl_stg1_rank_done <= \^rdlvl_stg1_rank_done\;
  samp_edge_cnt0_en_r <= \^samp_edge_cnt0_en_r\;
  \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\ <= \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\;
\FSM_onehot_cal1_state_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_6_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => rdlvl_rank_done_r,
      O => \FSM_onehot_cal1_state_r[0]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002300000022"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I1 => p_1_in26_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      I4 => p_27_in,
      I5 => \FSM_onehot_cal1_state_r[17]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[17]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I1 => cal1_dq_idel_inc,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I3 => p_34_in,
      I4 => idel_adj_inc_reg_n_0,
      O => \FSM_onehot_cal1_state_r[17]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => idel_pat_detect_valid_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => \FSM_onehot_cal1_state_r[24]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[18]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF10FF10FFFFFF10"
    )
        port map (
      I0 => mpr_dec_cpt_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[23]_i_4_n_0\,
      I2 => \FSM_onehot_cal1_state_r[23]_i_3_n_0\,
      I3 => \FSM_onehot_cal1_state_r[19]_i_2_n_0\,
      I4 => \FSM_onehot_cal1_state_r[27]_i_2_n_0\,
      I5 => \FSM_onehot_cal1_state_r[19]_i_3_n_0\,
      O => \FSM_onehot_cal1_state_r[19]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"200020002000FFFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I1 => cal1_dq_idel_inc,
      I2 => idel_adj_inc_reg_n_0,
      I3 => \FSM_onehot_cal1_state_r[27]_i_3_n_0\,
      I4 => \FSM_onehot_cal1_state_r[19]_i_4_n_0\,
      I5 => \FSM_onehot_cal1_state_r[24]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[19]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[19]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I1 => store_sr_req_pulsed_r,
      I2 => p_8_in,
      O => \FSM_onehot_cal1_state_r[19]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[19]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"001FFF1FFF1FFF1F"
    )
        port map (
      I0 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      I2 => p_34_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I4 => idel_pat_detect_valid_r_reg_n_0,
      I5 => idel_mpr_pat_detect_r,
      O => \FSM_onehot_cal1_state_r[19]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      I1 => \^mpr_rdlvl_start_r\,
      I2 => mpr_rdlvl_start_reg,
      O => \FSM_onehot_cal1_state_r[1]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[20]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => idelay_tap_limit_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[20]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => idelay_tap_limit_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[21]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFAAEFFFEFFFEFFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[24]_i_2_n_0\,
      I1 => idel_mpr_pat_detect_r,
      I2 => idel_pat_detect_valid_r_reg_n_0,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I4 => p_34_in,
      I5 => idel_adj_inc_i_2_n_0,
      O => \FSM_onehot_cal1_state_r[21]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => cal1_dq_idel_inc,
      I1 => \FSM_onehot_cal1_state_r[24]_i_2_n_0\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I3 => p_34_in,
      O => \FSM_onehot_cal1_state_r[22]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF200020002000"
    )
        port map (
      I0 => mpr_dec_cpt_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r[29]_i_3_n_0\,
      I2 => stable_idel_cnt23_in,
      I3 => \FSM_onehot_cal1_state_r[29]_i_2_n_0\,
      I4 => \FSM_onehot_cal1_state_r[23]_i_3_n_0\,
      I5 => \FSM_onehot_cal1_state_r[23]_i_4_n_0\,
      O => \FSM_onehot_cal1_state_r[23]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\,
      I1 => \idel_dec_cnt_reg[0]_i_2_n_0\,
      O => stable_idel_cnt23_in
    );
\FSM_onehot_cal1_state_r[23]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[27]_i_3_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I2 => p_12_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I4 => cal1_dq_idel_inc,
      O => \FSM_onehot_cal1_state_r[23]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[23]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \pi_rdval_cnt[5]_i_3_n_0\,
      I1 => \idel_dec_cnt__0\(2),
      I2 => \idel_dec_cnt__0\(1),
      I3 => \idel_dec_cnt__0\(0),
      I4 => \idel_dec_cnt__0\(3),
      I5 => \idel_dec_cnt__0\(4),
      O => \FSM_onehot_cal1_state_r[23]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[24]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => p_34_in,
      I3 => cal1_dq_idel_inc,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      O => \FSM_onehot_cal1_state_r[24]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      I4 => p_1_in26_in,
      O => \FSM_onehot_cal1_state_r[24]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF80000000000000"
    )
        port map (
      I0 => found_edge_r_reg_n_0,
      I1 => found_stable_eye_last_r,
      I2 => found_first_edge_r_reg_n_0,
      I3 => tap_limit_cpt_r,
      I4 => \FSM_onehot_cal1_state_r[27]_i_2_n_0\,
      I5 => store_sr_req_pulsed_r,
      O => \FSM_onehot_cal1_state_r[25]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"007F000000000000"
    )
        port map (
      I0 => found_edge_r_reg_n_0,
      I1 => found_stable_eye_last_r,
      I2 => found_first_edge_r_reg_n_0,
      I3 => tap_limit_cpt_r,
      I4 => \FSM_onehot_cal1_state_r[27]_i_2_n_0\,
      I5 => store_sr_req_pulsed_r,
      O => \FSM_onehot_cal1_state_r[26]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[27]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I2 => store_sr_req_pulsed_r,
      O => \FSM_onehot_cal1_state_r[27]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[27]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[27]_i_3_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I2 => p_12_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I4 => cal1_dq_idel_inc,
      O => \FSM_onehot_cal1_state_r[27]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[27]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_34_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => \FSM_onehot_cal1_state_r[24]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[27]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[29]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r[29]_i_3_n_0\,
      O => \FSM_onehot_cal1_state_r[28]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[29]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r[29]_i_3_n_0\,
      I2 => mpr_dec_cpt_r_reg_n_0,
      O => \FSM_onehot_cal1_state_r[29]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I1 => \FSM_onehot_cal1_state_r[27]_i_2_n_0\,
      I2 => store_sr_req_pulsed_r,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I4 => p_8_in,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      O => \FSM_onehot_cal1_state_r[29]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[29]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      O => \FSM_onehot_cal1_state_r[29]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0FFD0D0D0D0D0D0"
    )
        port map (
      I0 => mpr_rdlvl_start_reg,
      I1 => \^mpr_rdlvl_start_r\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      I5 => \FSM_onehot_cal1_state_r[32]_i_6_n_0\,
      O => \FSM_onehot_cal1_state_r[2]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08888888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_6_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      O => \FSM_onehot_cal1_state_r[30]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_6_n_0\,
      I1 => cal1_state_r1,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      O => \FSM_onehot_cal1_state_r[31]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_3_n_0\,
      I1 => store_sr_req_pulsed_r,
      I2 => p_34_in,
      I3 => detect_edge_done_r,
      I4 => \FSM_onehot_cal1_state_r[32]_i_4_n_0\,
      I5 => \FSM_onehot_cal1_state_r[32]_i_5_n_0\,
      O => \FSM_onehot_cal1_state_r[32]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      O => \FSM_onehot_cal1_state_r[32]_i_10_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in540_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      O => \FSM_onehot_cal1_state_r[32]_i_11_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I1 => p_8_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I3 => store_sr_req_pulsed_r,
      I4 => \FSM_onehot_cal1_state_r[27]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[32]_i_13_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => regl_dqs_cnt(3),
      I1 => regl_dqs_cnt(2),
      I2 => regl_dqs_cnt(0),
      I3 => regl_dqs_cnt(1),
      O => \FSM_onehot_cal1_state_r[32]_i_14_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => done_cnt(0),
      I1 => done_cnt(1),
      I2 => done_cnt(3),
      I3 => done_cnt(2),
      O => \FSM_onehot_cal1_state_r[32]_i_15_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000800080008AAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_6_n_0\,
      I1 => rdlvl_rank_done_r,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rnk_cnt_r_reg_n_0_[1]\,
      I4 => cal1_state_r1,
      I5 => \FSM_onehot_cal1_state_r[32]_i_9_n_0\,
      O => \FSM_onehot_cal1_state_r[32]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555554"
    )
        port map (
      I0 => cal1_wait_r,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      I2 => \cal1_state_r1[0]_i_2_n_0\,
      I3 => p_8_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      O => \FSM_onehot_cal1_state_r[32]_i_3_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEEAEEEAEEEAE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_10_n_0\,
      I1 => p_27_in,
      I2 => cal1_wait_r,
      I3 => \pi_counter_read_val_reg[2]_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I5 => prech_done,
      O => \FSM_onehot_cal1_state_r[32]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEEEAAEA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_11_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      I2 => rdlvl_stg1_start_reg,
      I3 => rdlvl_stg1_start_r,
      I4 => cal1_state_r1536_out,
      I5 => cal1_dq_idel_ce,
      O => \FSM_onehot_cal1_state_r[32]_i_5_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I1 => p_9_in,
      I2 => \FSM_onehot_cal1_state_r[32]_i_13_n_0\,
      O => \FSM_onehot_cal1_state_r[32]_i_6_n_0\
    );
\FSM_onehot_cal1_state_r[32]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      O => rdlvl_rank_done_r
    );
\FSM_onehot_cal1_state_r[32]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_14_n_0\,
      I1 => regl_rank_cnt(1),
      I2 => regl_rank_cnt(0),
      I3 => \FSM_onehot_cal1_state_r[32]_i_15_n_0\,
      O => cal1_state_r1
    );
\FSM_onehot_cal1_state_r[32]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      O => \FSM_onehot_cal1_state_r[32]_i_9_n_0\
    );
\FSM_onehot_cal1_state_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0A0A0B0A"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      O => \FSM_onehot_cal1_state_r[3]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FFF8F888888888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[4]_i_2_n_0\,
      I1 => mpr_dec_cpt_r,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I4 => p_9_in,
      I5 => \FSM_onehot_cal1_state_r[4]_i_4_n_0\,
      O => \FSM_onehot_cal1_state_r[4]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      O => \FSM_onehot_cal1_state_r[4]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_27_in,
      I1 => \pi_counter_read_val_reg[2]_0\,
      O => mpr_dec_cpt_r
    );
\FSM_onehot_cal1_state_r[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[27]_i_2_n_0\,
      I1 => store_sr_req_pulsed_r,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I3 => p_8_in,
      O => \FSM_onehot_cal1_state_r[4]_i_4_n_0\
    );
\FSM_onehot_cal1_state_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0400"
    )
        port map (
      I0 => stable_idel_cnt23_in,
      I1 => mpr_dec_cpt_r_reg_n_0,
      I2 => \FSM_onehot_cal1_state_r[29]_i_3_n_0\,
      I3 => \FSM_onehot_cal1_state_r[29]_i_2_n_0\,
      I4 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\,
      O => \FSM_onehot_cal1_state_r[5]_i_1_n_0\
    );
\FSM_onehot_cal1_state_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40FF404040404040"
    )
        port map (
      I0 => \pi_counter_read_val_reg[2]_0\,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r[4]_i_2_n_0\,
      I3 => \FSM_onehot_cal1_state_r[23]_i_4_n_0\,
      I4 => mpr_dec_cpt_r_reg_n_0,
      I5 => \FSM_onehot_cal1_state_r[23]_i_3_n_0\,
      O => \FSM_onehot_cal1_state_r[5]_i_2_n_0\
    );
\FSM_onehot_cal1_state_r_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[0]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      S => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[10]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[11]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => p_5_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => p_2_in33_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[14]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\FSM_onehot_cal1_state_r_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => p_7_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\FSM_onehot_cal1_state_r_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[17]_i_1_n_0\,
      Q => p_34_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\FSM_onehot_cal1_state_r_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[18]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\FSM_onehot_cal1_state_r_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[19]_i_1_n_0\,
      Q => store_sr_req_pulsed_r,
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\FSM_onehot_cal1_state_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[1]_i_1_n_0\,
      Q => p_1_in26_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[20]_i_2_n_0\,
      Q => cal1_dq_idel_inc,
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\FSM_onehot_cal1_state_r_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[21]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[21]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\FSM_onehot_cal1_state_r_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[22]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\FSM_onehot_cal1_state_r_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[23]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\FSM_onehot_cal1_state_r_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[24]_i_1_n_0\,
      Q => p_12_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\FSM_onehot_cal1_state_r_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[25]_i_2_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\FSM_onehot_cal1_state_r_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[26]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[27]_i_1_n_0\,
      Q => p_8_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[28]_i_1_n_0\,
      Q => p_9_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[29]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[2]_i_1_n_0\,
      Q => p_27_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[30]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[31]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[31]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[32]_i_2_n_0\,
      Q => p_0_in540_in,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\FSM_onehot_cal1_state_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[3]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[4]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => \FSM_onehot_cal1_state_r[5]_i_1_n_0\,
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[8]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\FSM_onehot_cal1_state_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \FSM_onehot_cal1_state_r[32]_i_1_n_0\,
      D => '0',
      Q => \FSM_onehot_cal1_state_r_reg_n_0_[9]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\cal1_cnt_cpt_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5111EEEE55550000"
    )
        port map (
      I0 => p_0_in540_in,
      I1 => prech_done,
      I2 => \^cal1_cnt_cpt_r_reg[1]_0\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \cal1_cnt_cpt_r[0]_i_1_n_0\
    );
\cal1_cnt_cpt_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"51EEFF0055005500"
    )
        port map (
      I0 => p_0_in540_in,
      I1 => prech_done,
      I2 => \^cal1_cnt_cpt_r_reg[1]_0\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \cal1_cnt_cpt_r[1]_i_1_n_0\
    );
\cal1_cnt_cpt_r[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \^cal1_cnt_cpt_r_reg[1]_0\
    );
\cal1_cnt_cpt_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AFF8000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \cal1_cnt_cpt_r[2]_i_3_n_0\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      O => \cal1_cnt_cpt_r[2]_i_2_n_0\
    );
\cal1_cnt_cpt_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEEEEEEEAAAAAAAA"
    )
        port map (
      I0 => p_0_in540_in,
      I1 => prech_done,
      I2 => \^cal1_cnt_cpt_r_reg[1]_0\,
      I3 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \cal1_cnt_cpt_r[2]_i_3_n_0\
    );
\cal1_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r[0]_i_1_n_0\,
      Q => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\cal1_cnt_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r[1]_i_1_n_0\,
      Q => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\cal1_cnt_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r[2]_i_2_n_0\,
      Q => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
cal1_dlyce_cpt_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I1 => tap_limit_cpt_r,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      O => cal1_dlyce_cpt_r
    );
cal1_dlyce_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dlyce_cpt_r,
      Q => cal1_dlyce_cpt_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
cal1_dlyinc_cpt_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I1 => tap_limit_cpt_r,
      O => cal1_dlyinc_cpt_r_i_1_n_0
    );
cal1_dlyinc_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dlyinc_cpt_r_i_1_n_0,
      Q => cal1_dlyinc_cpt_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
cal1_dq_idel_ce_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I1 => cal1_dq_idel_inc,
      O => cal1_dq_idel_ce
    );
cal1_dq_idel_ce_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dq_idel_ce,
      Q => \^idelay_ce_int\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
cal1_dq_idel_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_dq_idel_inc,
      Q => \^idelay_inc_int\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
cal1_prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      Q => cal1_prech_req_r_reg_n_0,
      R => SR(1)
    );
\cal1_state_r1[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[0]_i_2_n_0\,
      I1 => p_1_in26_in,
      I2 => p_27_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\,
      I5 => \cal1_state_r1[1]_i_2_n_0\,
      O => \cal1_state_r1[0]_i_1_n_0\
    );
\cal1_state_r1[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => p_9_in,
      I1 => p_12_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      O => \cal1_state_r1[0]_i_2_n_0\
    );
\cal1_state_r1[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \cal1_state_r1[1]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\,
      I3 => p_12_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I5 => \cal1_state_r1[1]_i_3_n_0\,
      O => \cal1_state_r1[1]_i_1_n_0\
    );
\cal1_state_r1[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I1 => p_0_in540_in,
      I2 => p_34_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      O => \cal1_state_r1[1]_i_2_n_0\
    );
\cal1_state_r1[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_8_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      O => \cal1_state_r1[1]_i_3_n_0\
    );
\cal1_state_r1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[3]_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I2 => p_12_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I4 => cal1_dq_idel_inc,
      O => \cal1_state_r1[2]_i_1_n_0\
    );
\cal1_state_r1[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[3]_i_2_n_0\,
      I1 => p_0_in540_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I3 => p_8_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[26]\,
      I5 => store_sr_req_pulsed_r,
      O => \cal1_state_r1[3]_i_1_n_0\
    );
\cal1_state_r1[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \cal1_state_r1[4]_i_1_n_0\,
      I1 => p_9_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \cal1_state_r1[3]_i_2_n_0\
    );
\cal1_state_r1[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[21]\,
      O => \cal1_state_r1[4]_i_1_n_0\
    );
\cal1_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[0]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[0]\,
      R => '0'
    );
\cal1_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[1]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[1]\,
      R => '0'
    );
\cal1_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[2]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[2]\,
      R => '0'
    );
\cal1_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[3]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[3]\,
      R => '0'
    );
\cal1_state_r1_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_state_r1[4]_i_1_n_0\,
      Q => \cal1_state_r1_reg_n_0_[4]\,
      S => p_0_in540_in
    );
\cal1_state_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      Q => \cal1_state_r1_reg_n_0_[5]\,
      R => '0'
    );
cal1_wait_cnt_en_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => cal1_wait_cnt_en_r_i_2_n_0,
      I1 => p_7_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      I3 => p_12_in,
      I4 => p_8_in,
      I5 => cal1_wait_cnt_en_r_i_3_n_0,
      O => cal1_wait_cnt_en_r0
    );
cal1_wait_cnt_en_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\,
      I1 => p_1_in26_in,
      I2 => p_27_in,
      I3 => p_9_in,
      O => cal1_wait_cnt_en_r_i_2_n_0
    );
cal1_wait_cnt_en_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[11]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[18]\,
      O => cal1_wait_cnt_en_r_i_3_n_0
    );
cal1_wait_cnt_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_wait_cnt_en_r0,
      Q => cal1_wait_cnt_en_r,
      R => '0'
    );
\cal1_wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cal1_wait_cnt_r_reg__0\(0),
      O => \p_0_in__1\(0)
    );
\cal1_wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cal1_wait_cnt_r_reg__0\(1),
      I1 => \cal1_wait_cnt_r_reg__0\(0),
      O => \p_0_in__1\(1)
    );
\cal1_wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cal1_wait_cnt_r_reg__0\(2),
      I1 => \cal1_wait_cnt_r_reg__0\(0),
      I2 => \cal1_wait_cnt_r_reg__0\(1),
      O => \p_0_in__1\(2)
    );
\cal1_wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cal1_wait_cnt_r_reg__0\(3),
      I1 => \cal1_wait_cnt_r_reg__0\(1),
      I2 => \cal1_wait_cnt_r_reg__0\(0),
      I3 => \cal1_wait_cnt_r_reg__0\(2),
      O => \p_0_in__1\(3)
    );
\cal1_wait_cnt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40000000FFFFFFFF"
    )
        port map (
      I0 => \cal1_wait_cnt_r_reg__0\(4),
      I1 => \cal1_wait_cnt_r_reg__0\(3),
      I2 => \cal1_wait_cnt_r_reg__0\(1),
      I3 => \cal1_wait_cnt_r_reg__0\(0),
      I4 => \cal1_wait_cnt_r_reg__0\(2),
      I5 => cal1_wait_cnt_en_r,
      O => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \cal1_wait_cnt_r_reg__0\(4),
      I1 => \cal1_wait_cnt_r_reg__0\(2),
      I2 => \cal1_wait_cnt_r_reg__0\(0),
      I3 => \cal1_wait_cnt_r_reg__0\(1),
      I4 => \cal1_wait_cnt_r_reg__0\(3),
      O => \p_0_in__1\(4)
    );
\cal1_wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(0),
      Q => \cal1_wait_cnt_r_reg__0\(0),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(1),
      Q => \cal1_wait_cnt_r_reg__0\(1),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(2),
      Q => \cal1_wait_cnt_r_reg__0\(2),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(3),
      Q => \cal1_wait_cnt_r_reg__0\(3),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
\cal1_wait_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__1\(4),
      Q => \cal1_wait_cnt_r_reg__0\(4),
      R => \cal1_wait_cnt_r[4]_i_1_n_0\
    );
cal1_wait_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => cal1_wait_cnt_en_r,
      I1 => \cal1_wait_cnt_r_reg__0\(4),
      I2 => \cal1_wait_cnt_r_reg__0\(3),
      I3 => \cal1_wait_cnt_r_reg__0\(1),
      I4 => \cal1_wait_cnt_r_reg__0\(0),
      I5 => \cal1_wait_cnt_r_reg__0\(2),
      O => cal1_wait_r_i_1_n_0
    );
cal1_wait_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_wait_r_i_1_n_0,
      Q => cal1_wait_r,
      R => '0'
    );
\cnt_idel_dec_cpt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \pi_counter_read_val_reg[0]\,
      I1 => p_27_in,
      I2 => \cnt_idel_dec_cpt_r[0]_i_3_n_0\,
      O => cnt_idel_dec_cpt_r(0)
    );
\cnt_idel_dec_cpt_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7400FFFF74007400"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r2(1),
      I1 => found_second_edge_r_reg_n_0,
      I2 => \cnt_idel_dec_cpt_r[0]_i_4_n_0\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[0]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800B8FFB8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_6\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_8_n_0\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \right_edge_taps_r__0\(1),
      O => \cnt_idel_dec_cpt_r[0]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF88888F8"
    )
        port map (
      I0 => \pi_counter_read_val_reg[1]\,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I5 => \cnt_idel_dec_cpt_r[1]_i_3_n_0\,
      O => cnt_idel_dec_cpt_r(1)
    );
\cnt_idel_dec_cpt_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08A8A808"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I1 => \cnt_idel_dec_cpt_r[1]_i_4_n_0\,
      I2 => found_second_edge_r_reg_n_0,
      I3 => cnt_idel_dec_cpt_r2(1),
      I4 => cnt_idel_dec_cpt_r2(2),
      O => \cnt_idel_dec_cpt_r[1]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_5\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_8_n_0\,
      I4 => \cnt_idel_dec_cpt_r[1]_i_5_n_0\,
      O => \cnt_idel_dec_cpt_r[1]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4BB4"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \right_edge_taps_r__0\(1),
      I2 => \right_edge_taps_r__0\(2),
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[1]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF88F8F888"
    )
        port map (
      I0 => \pi_counter_read_val_reg[2]\,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[2]_i_3_n_0\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I5 => \cnt_idel_dec_cpt_r[2]_i_4_n_0\,
      O => cnt_idel_dec_cpt_r(2)
    );
\cnt_idel_dec_cpt_r[2]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \first_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_10_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \first_edge_taps_r_reg_n_0_[0]\,
      O => \cnt_idel_dec_cpt_r[2]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[2]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08A8A8A8A8080808"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I1 => \cnt_idel_dec_cpt_r[2]_i_5_n_0\,
      I2 => found_second_edge_r_reg_n_0,
      I3 => cnt_idel_dec_cpt_r2(2),
      I4 => cnt_idel_dec_cpt_r2(1),
      I5 => cnt_idel_dec_cpt_r2(3),
      O => \cnt_idel_dec_cpt_r[2]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_4\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_8_n_0\,
      I4 => \cnt_idel_dec_cpt_r[2]_i_7_n_0\,
      O => \cnt_idel_dec_cpt_r[2]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40F4BF0BBF0B40F4"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \right_edge_taps_r__0\(1),
      I2 => \right_edge_taps_r__0\(2),
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \right_edge_taps_r__0\(3),
      I5 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \first_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[2]_i_8_n_0\
    );
\cnt_idel_dec_cpt_r[2]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \first_edge_taps_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[2]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
        port map (
      I0 => \pi_counter_read_val_reg[3]\,
      I1 => p_27_in,
      I2 => \cnt_idel_dec_cpt_r[3]_i_3_n_0\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I4 => \cnt_idel_dec_cpt_r[3]_i_4_n_0\,
      O => cnt_idel_dec_cpt_r(3)
    );
\cnt_idel_dec_cpt_r[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[0]\,
      I1 => \first_edge_taps_r_reg_n_0_[0]\,
      O => \cnt_idel_dec_cpt_r[3]_i_10_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[5]_i_11_n_0\,
      I1 => \right_edge_taps_r__0\(4),
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[3]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80002"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[3]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAFFFF6AAA0000"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r2(4),
      I1 => cnt_idel_dec_cpt_r2(2),
      I2 => cnt_idel_dec_cpt_r2(1),
      I3 => cnt_idel_dec_cpt_r2(3),
      I4 => found_second_edge_r_reg_n_0,
      I5 => \cnt_idel_dec_cpt_r[3]_i_6_n_0\,
      O => \cnt_idel_dec_cpt_r[3]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[4]_i_6_n_7\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_8_n_0\,
      I4 => \cnt_idel_dec_cpt_r[3]_i_11_n_0\,
      O => \cnt_idel_dec_cpt_r[3]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[3]\,
      I1 => \first_edge_taps_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[3]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[2]\,
      I1 => \first_edge_taps_r_reg_n_0_[2]\,
      O => \cnt_idel_dec_cpt_r[3]_i_8_n_0\
    );
\cnt_idel_dec_cpt_r[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[1]\,
      I1 => \first_edge_taps_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[3]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF88F8F888"
    )
        port map (
      I0 => \pi_counter_read_val_reg[4]\,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[4]_i_3_n_0\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I5 => \cnt_idel_dec_cpt_r[4]_i_4_n_0\,
      O => cnt_idel_dec_cpt_r(4)
    );
\cnt_idel_dec_cpt_r[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[4]_i_3_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08A8A808"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I1 => \cnt_idel_dec_cpt_r[4]_i_5_n_0\,
      I2 => found_second_edge_r_reg_n_0,
      I3 => \cnt_idel_dec_cpt_r[5]_i_10_n_0\,
      I4 => cnt_idel_dec_cpt_r2(5),
      O => \cnt_idel_dec_cpt_r[4]_i_4_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg[4]_i_6_n_6\,
      I1 => found_first_edge_r_reg_n_0,
      I2 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_8_n_0\,
      I4 => \cnt_idel_dec_cpt_r[4]_i_7_n_0\,
      O => \cnt_idel_dec_cpt_r[4]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B24D4DB2"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[5]_i_11_n_0\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \right_edge_taps_r__0\(4),
      I3 => \right_edge_taps_r__0\(5),
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \first_edge_taps_r_reg_n_0_[5]\,
      O => \cnt_idel_dec_cpt_r[4]_i_8_n_0\
    );
\cnt_idel_dec_cpt_r[4]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I1 => \first_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[4]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => \pi_counter_read_val_reg[2]_0\,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[5]_i_1_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => cnt_idel_dec_cpt_r2(4),
      I1 => cnt_idel_dec_cpt_r2(2),
      I2 => cnt_idel_dec_cpt_r2(1),
      I3 => cnt_idel_dec_cpt_r2(3),
      O => \cnt_idel_dec_cpt_r[5]_i_10_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2B222222BBBB2B22"
    )
        port map (
      I0 => \right_edge_taps_r__0\(3),
      I1 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \right_edge_taps_r__0\(1),
      I4 => \right_edge_taps_r__0\(2),
      I5 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \cnt_idel_dec_cpt_r[5]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[5]\,
      I1 => \first_edge_taps_r_reg_n_0_[5]\,
      O => \cnt_idel_dec_cpt_r[5]_i_12_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \second_edge_taps_r_reg_n_0_[4]\,
      I1 => \first_edge_taps_r_reg_n_0_[4]\,
      O => \cnt_idel_dec_cpt_r[5]_i_13_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \pi_counter_read_val_reg[5]\,
      I1 => p_27_in,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_5_n_0\,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[25]\,
      I5 => \cnt_idel_dec_cpt_r[5]_i_6_n_0\,
      O => cnt_idel_dec_cpt_r(5)
    );
\cnt_idel_dec_cpt_r[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I5 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      O => \cnt_idel_dec_cpt_r[5]_i_5_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F00F0F0F11111111"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r[5]_i_7_n_0\,
      I1 => \cnt_idel_dec_cpt_r[5]_i_8_n_0\,
      I2 => \cnt_idel_dec_cpt_r_reg[5]_i_9_n_1\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_10_n_0\,
      I4 => cnt_idel_dec_cpt_r2(5),
      I5 => found_second_edge_r_reg_n_0,
      O => \cnt_idel_dec_cpt_r[5]_i_6_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9A59AAAA55559A59"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \right_edge_taps_r__0\(4),
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I3 => \cnt_idel_dec_cpt_r[5]_i_11_n_0\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I5 => \right_edge_taps_r__0\(5),
      O => \cnt_idel_dec_cpt_r[5]_i_7_n_0\
    );
\cnt_idel_dec_cpt_r[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \right_edge_taps_r__0\(2),
      I1 => \right_edge_taps_r__0\(3),
      I2 => \right_edge_taps_r__0\(1),
      I3 => \right_edge_taps_r__0\(0),
      I4 => \right_edge_taps_r__0\(5),
      I5 => \right_edge_taps_r__0\(4),
      O => \cnt_idel_dec_cpt_r[5]_i_8_n_0\
    );
\cnt_idel_dec_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(0),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(1),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(2),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[2]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_0\,
      CO(2) => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_1\,
      CO(1) => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_2\,
      CO(0) => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_3\,
      CYINIT => '1',
      DI(3) => \tap_cnt_cpt_r_reg_n_0_[3]\,
      DI(2) => \tap_cnt_cpt_r_reg_n_0_[2]\,
      DI(1) => \tap_cnt_cpt_r_reg_n_0_[1]\,
      DI(0) => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O(3) => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_4\,
      O(2) => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_5\,
      O(1) => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_6\,
      O(0) => \NLW_cnt_idel_dec_cpt_r_reg[2]_i_6_O_UNCONNECTED\(0),
      S(3) => \cnt_idel_dec_cpt_r[2]_i_8_n_0\,
      S(2) => \cnt_idel_dec_cpt_r[2]_i_9_n_0\,
      S(1) => \cnt_idel_dec_cpt_r[2]_i_10_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[2]_i_11_n_0\
    );
\cnt_idel_dec_cpt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(3),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[3]_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \cnt_idel_dec_cpt_r_reg[3]_i_5_n_0\,
      CO(2) => \cnt_idel_dec_cpt_r_reg[3]_i_5_n_1\,
      CO(1) => \cnt_idel_dec_cpt_r_reg[3]_i_5_n_2\,
      CO(0) => \cnt_idel_dec_cpt_r_reg[3]_i_5_n_3\,
      CYINIT => '1',
      DI(3) => \second_edge_taps_r_reg_n_0_[3]\,
      DI(2) => \second_edge_taps_r_reg_n_0_[2]\,
      DI(1) => \second_edge_taps_r_reg_n_0_[1]\,
      DI(0) => \second_edge_taps_r_reg_n_0_[0]\,
      O(3 downto 1) => cnt_idel_dec_cpt_r2(3 downto 1),
      O(0) => \NLW_cnt_idel_dec_cpt_r_reg[3]_i_5_O_UNCONNECTED\(0),
      S(3) => \cnt_idel_dec_cpt_r[3]_i_7_n_0\,
      S(2) => \cnt_idel_dec_cpt_r[3]_i_8_n_0\,
      S(1) => \cnt_idel_dec_cpt_r[3]_i_9_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[3]_i_10_n_0\
    );
\cnt_idel_dec_cpt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(4),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[4]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \cnt_idel_dec_cpt_r_reg[2]_i_6_n_0\,
      CO(3 downto 1) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \cnt_idel_dec_cpt_r_reg[4]_i_6_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED\(3 downto 2),
      O(1) => \cnt_idel_dec_cpt_r_reg[4]_i_6_n_6\,
      O(0) => \cnt_idel_dec_cpt_r_reg[4]_i_6_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \cnt_idel_dec_cpt_r[4]_i_8_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[4]_i_9_n_0\
    );
\cnt_idel_dec_cpt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\,
      D => cnt_idel_dec_cpt_r(5),
      Q => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      R => '0'
    );
\cnt_idel_dec_cpt_r_reg[5]_i_9\: unisim.vcomponents.CARRY4
     port map (
      CI => \cnt_idel_dec_cpt_r_reg[3]_i_5_n_0\,
      CO(3) => \NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED\(3),
      CO(2) => \cnt_idel_dec_cpt_r_reg[5]_i_9_n_1\,
      CO(1) => \NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED\(1),
      CO(0) => \cnt_idel_dec_cpt_r_reg[5]_i_9_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \second_edge_taps_r_reg_n_0_[5]\,
      DI(0) => \second_edge_taps_r_reg_n_0_[4]\,
      O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => cnt_idel_dec_cpt_r2(5 downto 4),
      S(3 downto 2) => B"01",
      S(1) => \cnt_idel_dec_cpt_r[5]_i_12_n_0\,
      S(0) => \cnt_idel_dec_cpt_r[5]_i_13_n_0\
    );
\cnt_shift_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \cnt_shift_r_reg__0\(0),
      I1 => \cnt_shift_r_reg__0\(1),
      I2 => \cnt_shift_r_reg__0\(3),
      I3 => \cnt_shift_r_reg__0\(2),
      O => \p_0_in__2\(0)
    );
\cnt_shift_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \cnt_shift_r_reg__0\(1),
      I1 => \cnt_shift_r_reg__0\(0),
      O => \p_0_in__2\(1)
    );
\cnt_shift_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \cnt_shift_r_reg__0\(2),
      I1 => \cnt_shift_r_reg__0\(0),
      I2 => \cnt_shift_r_reg__0\(1),
      O => \p_0_in__2\(2)
    );
\cnt_shift_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \cnt_shift_r_reg__0\(3),
      I1 => \cnt_shift_r_reg__0\(1),
      I2 => \cnt_shift_r_reg__0\(0),
      I3 => \cnt_shift_r_reg__0\(2),
      O => \p_0_in__2\(3)
    );
\cnt_shift_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__2\(0),
      Q => \cnt_shift_r_reg__0\(0),
      S => rdlvl_stg1_start_reg_0(0)
    );
\cnt_shift_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__2\(1),
      Q => \cnt_shift_r_reg__0\(1),
      R => rdlvl_stg1_start_reg_0(0)
    );
\cnt_shift_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__2\(2),
      Q => \cnt_shift_r_reg__0\(2),
      R => rdlvl_stg1_start_reg_0(0)
    );
\cnt_shift_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__2\(3),
      Q => \cnt_shift_r_reg__0\(3),
      R => rdlvl_stg1_start_reg_0(0)
    );
\ctl_lane_cnt[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pi_fine_dly_dec_done\,
      I1 => dqs_po_dec_done,
      O => cmd_delay_start0
    );
detect_edge_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pb_detect_edge_done_r(6),
      I1 => pb_detect_edge_done_r(7),
      I2 => pb_detect_edge_done_r(4),
      I3 => pb_detect_edge_done_r(5),
      I4 => detect_edge_done_r_i_2_n_0,
      O => detect_edge_done_r_i_1_n_0
    );
detect_edge_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pb_detect_edge_done_r(1),
      I1 => pb_detect_edge_done_r(0),
      I2 => pb_detect_edge_done_r(3),
      I3 => pb_detect_edge_done_r(2),
      O => detect_edge_done_r_i_2_n_0
    );
detect_edge_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => detect_edge_done_r_i_1_n_0,
      Q => detect_edge_done_r,
      R => '0'
    );
\done_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000005554"
    )
        port map (
      I0 => done_cnt(0),
      I1 => done_cnt(1),
      I2 => done_cnt(3),
      I3 => done_cnt(2),
      I4 => done_cnt1,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \done_cnt[0]_i_1_n_0\
    );
\done_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAAAAFE"
    )
        port map (
      I0 => done_cnt1,
      I1 => done_cnt(2),
      I2 => done_cnt(3),
      I3 => done_cnt(1),
      I4 => done_cnt(0),
      O => \done_cnt[1]_i_1_n_0\
    );
\done_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000EE10"
    )
        port map (
      I0 => done_cnt(0),
      I1 => done_cnt(1),
      I2 => done_cnt(3),
      I3 => done_cnt(2),
      I4 => done_cnt1,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \done_cnt[2]_i_1_n_0\
    );
\done_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAFAFAEA"
    )
        port map (
      I0 => done_cnt1,
      I1 => done_cnt(2),
      I2 => done_cnt(3),
      I3 => done_cnt(1),
      I4 => done_cnt(0),
      O => \done_cnt[3]_i_1_n_0\
    );
\done_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F11"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r[32]_i_15_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\,
      I2 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I3 => p_0_in540_in,
      O => done_cnt1
    );
\done_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[0]_i_1_n_0\,
      Q => done_cnt(0),
      R => '0'
    );
\done_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[1]_i_1_n_0\,
      Q => done_cnt(1),
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\done_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[2]_i_1_n_0\,
      Q => done_cnt(2),
      R => '0'
    );
\done_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \done_cnt[3]_i_1_n_0\,
      Q => done_cnt(3),
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
dqs_po_dec_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_po_dec_done,
      Q => dqs_po_dec_done_r1,
      R => '0'
    );
dqs_po_dec_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_po_dec_done_r1,
      Q => dqs_po_dec_done_r2,
      R => '0'
    );
fine_dly_dec_done_r1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00005404"
    )
        port map (
      I0 => pi_rdval_cnt(1),
      I1 => dqs_po_dec_done_r2,
      I2 => pi_rdval_cnt(0),
      I3 => \^fine_dly_dec_done_r1_reg_0\,
      I4 => fine_dly_dec_done_r1_i_2_n_0,
      I5 => fine_dly_dec_done_r1,
      O => fine_dly_dec_done_r1_i_1_n_0
    );
fine_dly_dec_done_r1_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => pi_rdval_cnt(3),
      I1 => pi_rdval_cnt(4),
      I2 => pi_rdval_cnt(5),
      I3 => pi_rdval_cnt(2),
      O => fine_dly_dec_done_r1_i_2_n_0
    );
fine_dly_dec_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_dly_dec_done_r1_i_1_n_0,
      Q => fine_dly_dec_done_r1,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
fine_dly_dec_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_dly_dec_done_r1,
      Q => fine_dly_dec_done_r2,
      R => '0'
    );
\first_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => store_sr_req_pulsed_r,
      O => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEEEAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => store_sr_req_pulsed_r,
      O => \first_edge_taps_r[5]_i_2_n_0\
    );
\first_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => detect_edge_done_r,
      I1 => found_edge_r_reg_n_0,
      I2 => tap_limit_cpt_r,
      O => \first_edge_taps_r[5]_i_3_n_0\
    );
\first_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \first_edge_taps_r_reg_n_0_[0]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \first_edge_taps_r_reg_n_0_[1]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \first_edge_taps_r_reg_n_0_[2]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \first_edge_taps_r_reg_n_0_[3]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \first_edge_taps_r_reg_n_0_[4]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
\first_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \first_edge_taps_r[5]_i_2_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \first_edge_taps_r_reg_n_0_[5]\,
      R => \first_edge_taps_r[5]_i_1_n_0\
    );
found_edge_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I1 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I3 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I4 => found_edge_r_i_2_n_0,
      O => found_edge_r_i_1_n_0
    );
found_edge_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I1 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I3 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      O => found_edge_r_i_2_n_0
    );
found_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_edge_r_i_1_n_0,
      Q => found_edge_r_reg_n_0,
      R => '0'
    );
found_first_edge_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5F55555A0E00000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => detect_edge_done_r,
      I2 => found_edge_r_reg_n_0,
      I3 => tap_limit_cpt_r,
      I4 => store_sr_req_pulsed_r,
      I5 => found_first_edge_r_reg_n_0,
      O => found_first_edge_r_i_1_n_0
    );
found_first_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_first_edge_r_i_1_n_0,
      Q => found_first_edge_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
found_second_edge_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5555555E0000000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => store_sr_req_pulsed_r,
      I5 => found_second_edge_r_reg_n_0,
      O => found_second_edge_r_i_1_n_0
    );
found_second_edge_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_second_edge_r_i_1_n_0,
      Q => found_second_edge_r_reg_n_0,
      R => SR(0)
    );
found_stable_eye_last_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => found_stable_eye_r_reg_n_0,
      I1 => detect_edge_done_r,
      I2 => found_stable_eye_last_r,
      O => found_stable_eye_last_r_i_1_n_0
    );
found_stable_eye_last_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_stable_eye_last_r_i_1_n_0,
      Q => found_stable_eye_last_r,
      R => pb_detect_edge_setup
    );
found_stable_eye_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_found_stable_eye_r_reg\,
      I1 => \gen_track_left_edge[6].pb_found_stable_eye_r_reg\,
      I2 => \gen_track_left_edge[4].pb_found_stable_eye_r_reg\,
      I3 => \gen_track_left_edge[5].pb_found_stable_eye_r_reg\,
      I4 => found_stable_eye_r_i_2_n_0,
      O => found_stable_eye_r_i_1_n_0
    );
found_stable_eye_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_found_stable_eye_r_reg\,
      I1 => \gen_track_left_edge[0].pb_found_stable_eye_r_reg\,
      I2 => \gen_track_left_edge[3].pb_found_stable_eye_r_reg\,
      I3 => \gen_track_left_edge[2].pb_found_stable_eye_r_reg\,
      O => found_stable_eye_r_i_2_n_0
    );
found_stable_eye_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => found_stable_eye_r_i_1_n_0,
      Q => found_stable_eye_r_reg_n_0,
      R => '0'
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F202F2F2F202020"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I1 => wrcal_done_reg,
      I2 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I3 => regl_dqs_cnt_r(0),
      I4 => p_0_in540_in,
      I5 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      O => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F202F2F2F202020"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I1 => wrcal_done_reg,
      I2 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I3 => regl_dqs_cnt_r(1),
      I4 => p_0_in540_in,
      I5 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\
    );
\gen_byte_sel_div2.byte_sel_cnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F202F2F2F202020"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[3]\(2),
      I1 => wrcal_done_reg,
      I2 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I3 => regl_dqs_cnt_r(2),
      I4 => p_0_in540_in,
      I5 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      O => \gen_byte_sel_div2.byte_sel_cnt_reg[2]\
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2F202020"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[3]\(3),
      I1 => wrcal_done_reg,
      I2 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I3 => p_0_in540_in,
      I4 => regl_dqs_cnt_r(3),
      O => \gen_byte_sel_div2.byte_sel_cnt_reg[3]\
    );
\gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_8\,
      Q => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_24\,
      Q => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_40\,
      Q => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_56\,
      Q => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise0_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      I2 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      O => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\
    );
\gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_0\,
      Q => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_16\,
      Q => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_32\,
      Q => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_48\,
      Q => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_9\,
      Q => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_25\,
      Q => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_41\,
      Q => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_57\,
      Q => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_1\,
      Q => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_17\,
      Q => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_33\,
      Q => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_49\,
      Q => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_10\,
      Q => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_26\,
      Q => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_42\,
      Q => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_58\,
      Q => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_2\,
      Q => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_18\,
      Q => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_34\,
      Q => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_50\,
      Q => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_11\,
      Q => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_27\,
      Q => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_43\,
      Q => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_59\,
      Q => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_3\,
      Q => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_19\,
      Q => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_35\,
      Q => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[3].mux_rd_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_51\,
      Q => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_12\,
      Q => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_28\,
      Q => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_44\,
      Q => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_60\,
      Q => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_4\,
      Q => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_20\,
      Q => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_36\,
      Q => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_52\,
      Q => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_13\,
      Q => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_29\,
      Q => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_45\,
      Q => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_61\,
      Q => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_5\,
      Q => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_21\,
      Q => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_37\,
      Q => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_53\,
      Q => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_14\,
      Q => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_30\,
      Q => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_46\,
      Q => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_62\,
      Q => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_6\,
      Q => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_22\,
      Q => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_38\,
      Q => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_54\,
      Q => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_15\,
      Q => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_31\,
      Q => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_47\,
      Q => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_63\,
      Q => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_7\,
      Q => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_23\,
      Q => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_39\,
      Q => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd[7].mux_rd_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_mux_sel_r_reg[2]_55\,
      Q => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_255\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r[0][0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_r_reg_n_0,
      I1 => sr_valid_r_reg_n_0,
      O => store_sr_r0
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_239\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_279\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_287\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_247\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_263\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_271\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\,
      Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_295\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_207\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_175\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_231\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_191\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_223\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_215\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_183\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\,
      Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_199\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_256\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_240\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_280\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_288\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_248\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_264\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_272\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\,
      Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_296\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_208\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_176\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_232\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_192\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_224\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_216\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_184\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\,
      Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_200\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_257\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_241\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_281\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_289\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_249\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_265\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_273\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\,
      Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_297\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_209\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_177\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_233\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_193\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_225\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_217\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_185\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\,
      Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_201\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_258\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_242\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_282\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_290\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_250\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_266\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_274\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\,
      Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_298\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_210\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_178\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_234\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_194\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_226\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_218\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_186\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\,
      Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_202\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_259\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_243\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_283\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_291\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_251\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_267\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_275\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\,
      Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_299\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_211\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_179\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_235\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_195\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_227\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_219\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_187\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\,
      Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_203\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_260\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_244\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_284\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_292\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_252\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_268\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_276\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\,
      Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_300\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_212\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_180\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_236\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_196\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_228\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_220\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_188\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\,
      Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_204\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_261\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_245\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_285\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_293\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_253\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_269\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_277\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\,
      Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_301\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_213\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_181\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_237\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_197\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_229\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_221\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_189\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\,
      Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_205\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_262\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_246\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_286\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_294\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_254\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_270\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_278\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => store_sr_r0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\,
      Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_302\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_214\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_182\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_238\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_198\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_230\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_222\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_190\,
      R => '0'
    );
\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r_reg_n_0,
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\,
      Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_206\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\,
      O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\,
      Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\,
      O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\,
      Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\,
      O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\,
      O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\,
      Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\,
      O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\,
      Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\,
      O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\,
      Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\,
      O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\,
      O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\,
      Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => idel_pat0_match_rise0_and_r,
      I1 => idel_pat0_match_rise2_and_r,
      I2 => idel_pat0_match_fall2_and_r,
      I3 => idel_pat0_match_fall3_and_r,
      I4 => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\,
      O => \idel_pat0_data_match_r0__0\
    );
\gen_pat_match_div4.idel_pat0_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => idel_pat0_match_fall0_and_r,
      I1 => idel_pat0_match_rise1_and_r,
      I2 => idel_pat0_match_rise3_and_r,
      I3 => idel_pat0_match_fall1_and_r,
      O => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \idel_pat0_data_match_r0__0\,
      Q => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\,
      Q => idel_pat0_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg\,
      O => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\,
      Q => idel_pat0_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => idel_pat1_match_fall2_and_r,
      I1 => idel_pat1_match_fall1_and_r,
      I2 => idel_pat1_match_fall3_and_r,
      I3 => idel_pat1_match_rise0_and_r,
      I4 => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\,
      O => \idel_pat1_data_match_r0__0\
    );
\gen_pat_match_div4.idel_pat1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => idel_pat1_match_rise1_and_r,
      I1 => idel_pat1_match_rise2_and_r,
      I2 => idel_pat1_match_rise3_and_r,
      I3 => idel_pat1_match_fall0_and_r,
      O => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \idel_pat1_data_match_r0__0\,
      Q => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\,
      Q => idel_pat1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg\,
      O => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\,
      Q => idel_pat1_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat0_match_rise2_and_r,
      I1 => pat0_match_fall1_and_r,
      I2 => pat0_match_fall3_and_r,
      I3 => pat0_match_rise0_and_r,
      I4 => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\,
      O => \pat0_data_match_r0__0\
    );
\gen_pat_match_div4.pat0_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat0_match_fall0_and_r,
      I1 => pat0_match_rise1_and_r,
      I2 => pat0_match_rise3_and_r,
      I3 => pat0_match_fall2_and_r,
      O => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pat0_data_match_r0__0\,
      Q => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\,
      Q => pat0_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\,
      Q => pat0_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg\,
      O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\,
      Q => pat0_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg\,
      O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg\,
      O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\,
      Q => pat0_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\,
      Q => pat0_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg\,
      O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg\,
      O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\,
      Q => pat0_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\,
      Q => pat0_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg\,
      O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\,
      Q => pat0_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat1_match_fall2_and_r,
      I1 => pat1_match_rise2_and_r,
      I2 => pat1_match_fall3_and_r,
      I3 => pat1_match_rise0_and_r,
      I4 => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\,
      O => \pat1_data_match_r0__0\
    );
\gen_pat_match_div4.pat1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat1_match_rise1_and_r,
      I1 => pat1_match_fall1_and_r,
      I2 => pat1_match_rise3_and_r,
      I3 => pat1_match_fall0_and_r,
      O => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pat1_data_match_r0__0\,
      Q => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\,
      Q => pat1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\,
      Q => pat1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\,
      Q => pat1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\,
      Q => pat1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\,
      Q => pat1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\,
      Q => pat1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\,
      I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\,
      Q => pat1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg\,
      O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\,
      Q => pat1_match_rise3_and_r,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\,
      R => '0'
    );
\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\,
      O => \p_489_out__0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_489_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_255\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_239\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_279\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_287\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_247\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_263\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_271\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_295\,
      O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sr_valid_r2,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\,
      I4 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\,
      O => \p_514_out__0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_514_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_151\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_207\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_135\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_175\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_159\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_231\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_119\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_191\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_111\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_223\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_143\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_215\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_127\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_183\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_167\,
      I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_199\,
      O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\,
      Q => p_1_in17_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_2_in432_in,
      I1 => p_4_in434_in,
      I2 => p_0_in431_in,
      I3 => p_3_in433_in,
      I4 => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\,
      O => \p_439_out__0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in437_in,
      I1 => p_5_in435_in,
      I2 => p_6_in436_in,
      I3 => p_1_in438_in,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_439_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_256\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\,
      Q => p_0_in431_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_240\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\,
      Q => p_3_in433_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_280\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\,
      Q => p_5_in435_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_288\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\,
      Q => p_7_in437_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_248\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\,
      Q => p_1_in438_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_264\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\,
      Q => p_2_in432_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_272\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\,
      Q => p_4_in434_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_296\,
      O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\,
      Q => p_6_in436_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\,
      Q => p_0_in102_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_2_in457_in,
      I1 => p_4_in459_in,
      I2 => p_0_in456_in,
      I3 => p_3_in458_in,
      I4 => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\,
      O => \p_464_out__0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in462_in,
      I1 => p_6_in461_in,
      I2 => p_5_in460_in,
      I3 => p_1_in463_in,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_464_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_152\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_208\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\,
      Q => p_0_in456_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_136\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_176\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\,
      Q => p_3_in458_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_160\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_232\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\,
      Q => p_5_in460_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_120\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_192\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\,
      Q => p_7_in462_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_112\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_224\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\,
      Q => p_1_in463_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_144\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_216\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\,
      Q => p_2_in457_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_128\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_184\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\,
      Q => p_4_in459_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_168\,
      I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_200\,
      O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\,
      Q => p_6_in461_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\,
      Q => p_1_in14_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_3_in383_in,
      I1 => p_4_in384_in,
      I2 => p_2_in382_in,
      I3 => p_0_in381_in,
      I4 => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\,
      O => \p_389_out__0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in387_in,
      I1 => p_5_in385_in,
      I2 => p_6_in386_in,
      I3 => p_1_in388_in,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_389_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_257\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\,
      Q => p_0_in381_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_241\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\,
      Q => p_3_in383_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_281\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\,
      Q => p_5_in385_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_289\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\,
      Q => p_7_in387_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_249\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\,
      Q => p_1_in388_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_265\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\,
      Q => p_2_in382_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_273\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\,
      Q => p_4_in384_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_297\,
      O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\,
      Q => p_6_in386_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\,
      Q => p_0_in99_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_2_in407_in,
      I1 => p_4_in409_in,
      I2 => p_0_in406_in,
      I3 => p_3_in408_in,
      I4 => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\,
      O => \p_414_out__0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in412_in,
      I1 => p_5_in410_in,
      I2 => p_6_in411_in,
      I3 => p_1_in413_in,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_414_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_153\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_209\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\,
      Q => p_0_in406_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_137\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_177\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\,
      Q => p_3_in408_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_161\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_233\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\,
      Q => p_5_in410_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_121\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_193\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\,
      Q => p_7_in412_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_113\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_225\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\,
      Q => p_1_in413_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_145\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_217\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\,
      Q => p_2_in407_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_129\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_185\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\,
      Q => p_4_in409_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_169\,
      I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_201\,
      O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\,
      Q => p_6_in411_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\,
      Q => p_1_in11_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_3_in333_in,
      I1 => p_4_in334_in,
      I2 => p_2_in332_in,
      I3 => p_0_in331_in,
      I4 => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\,
      O => \p_339_out__0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_6_in336_in,
      I1 => p_5_in335_in,
      I2 => p_7_in337_in,
      I3 => p_1_in338_in,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_339_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_258\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\,
      Q => p_0_in331_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_242\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\,
      Q => p_3_in333_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_282\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\,
      Q => p_5_in335_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_290\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\,
      Q => p_7_in337_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_250\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\,
      Q => p_1_in338_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_266\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\,
      Q => p_2_in332_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_274\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\,
      Q => p_4_in334_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_298\,
      O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\,
      Q => p_6_in336_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\,
      Q => p_0_in96_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in359_in,
      I1 => p_5_in360_in,
      I2 => p_3_in358_in,
      I3 => p_0_in356_in,
      I4 => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\,
      O => \p_364_out__0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in362_in,
      I1 => p_6_in361_in,
      I2 => p_2_in357_in,
      I3 => p_1_in363_in,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_364_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_154\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_210\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\,
      Q => p_0_in356_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_138\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_178\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\,
      Q => p_3_in358_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_162\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_234\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\,
      Q => p_5_in360_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_122\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_194\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\,
      Q => p_7_in362_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_114\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_226\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\,
      Q => p_1_in363_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_146\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_218\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\,
      Q => p_2_in357_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_130\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_186\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\,
      Q => p_4_in359_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_170\,
      I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_202\,
      O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\,
      Q => p_6_in361_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\,
      Q => p_1_in8_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in284_in,
      I1 => p_5_in285_in,
      I2 => p_3_in283_in,
      I3 => p_2_in282_in,
      I4 => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\,
      O => \p_289_out__0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in287_in,
      I1 => p_6_in286_in,
      I2 => p_0_in281_in,
      I3 => p_1_in288_in,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_289_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_259\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\,
      Q => p_0_in281_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_243\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\,
      Q => p_3_in283_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_283\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\,
      Q => p_5_in285_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_291\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\,
      Q => p_7_in287_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_251\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\,
      Q => p_1_in288_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_267\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\,
      Q => p_2_in282_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_275\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\,
      Q => p_4_in284_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_299\,
      O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\,
      Q => p_6_in286_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\,
      Q => p_0_in93_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in309_in,
      I1 => p_5_in310_in,
      I2 => p_3_in308_in,
      I3 => p_2_in307_in,
      I4 => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\,
      O => \p_314_out__0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in312_in,
      I1 => p_6_in311_in,
      I2 => p_0_in306_in,
      I3 => p_1_in313_in,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_314_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_155\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_211\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\,
      Q => p_0_in306_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_139\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_179\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\,
      Q => p_3_in308_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_163\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_235\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\,
      Q => p_5_in310_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_123\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_195\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\,
      Q => p_7_in312_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_115\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_227\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\,
      Q => p_1_in313_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_147\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_219\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\,
      Q => p_2_in307_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_131\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_187\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\,
      Q => p_4_in309_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_171\,
      I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_203\,
      O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\,
      Q => p_6_in311_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\,
      Q => p_1_in5_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in234_in,
      I1 => p_5_in235_in,
      I2 => p_3_in233_in,
      I3 => p_2_in232_in,
      I4 => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\,
      O => \p_239_out__0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in237_in,
      I1 => p_6_in236_in,
      I2 => p_0_in231_in,
      I3 => p_1_in238_in,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_239_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_260\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\,
      Q => p_0_in231_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_244\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\,
      Q => p_3_in233_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_284\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\,
      Q => p_5_in235_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_292\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\,
      Q => p_7_in237_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_252\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\,
      Q => p_1_in238_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_268\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\,
      Q => p_2_in232_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_276\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\,
      Q => p_4_in234_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_300\,
      O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\,
      Q => p_6_in236_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\,
      Q => p_0_in90_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in259_in,
      I1 => p_5_in260_in,
      I2 => p_3_in258_in,
      I3 => p_2_in257_in,
      I4 => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\,
      O => \p_264_out__0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in262_in,
      I1 => p_6_in261_in,
      I2 => p_0_in256_in,
      I3 => p_1_in263_in,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_264_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_156\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_212\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\,
      Q => p_0_in256_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_140\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_180\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\,
      Q => p_3_in258_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_164\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_236\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\,
      Q => p_5_in260_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_124\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_196\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\,
      Q => p_7_in262_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_116\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_228\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\,
      Q => p_1_in263_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_148\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_220\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\,
      Q => p_2_in257_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_132\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_188\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\,
      Q => p_4_in259_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_172\,
      I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_204\,
      O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\,
      Q => p_6_in261_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\,
      Q => p_1_in2_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in184_in,
      I1 => p_5_in185_in,
      I2 => p_3_in183_in,
      I3 => p_2_in182_in,
      I4 => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\,
      O => \p_189_out__0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in187_in,
      I1 => p_6_in186_in,
      I2 => p_0_in181_in,
      I3 => p_1_in188_in,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_189_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_261\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\,
      Q => p_0_in181_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_245\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\,
      Q => p_3_in183_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_285\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\,
      Q => p_5_in185_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_293\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\,
      Q => p_7_in187_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_253\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\,
      Q => p_1_in188_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_269\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\,
      Q => p_2_in182_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_277\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\,
      Q => p_4_in184_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_301\,
      O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\,
      Q => p_6_in186_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\,
      Q => p_0_in87_in,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in209_in,
      I1 => p_5_in210_in,
      I2 => p_3_in208_in,
      I3 => p_2_in207_in,
      I4 => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\,
      O => \p_214_out__0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in212_in,
      I1 => p_6_in211_in,
      I2 => p_0_in206_in,
      I3 => p_1_in213_in,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_214_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_157\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_213\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\,
      Q => p_0_in206_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_141\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_181\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\,
      Q => p_3_in208_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_165\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_237\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\,
      Q => p_5_in210_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_125\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_197\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\,
      Q => p_7_in212_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_117\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_229\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\,
      Q => p_1_in213_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_149\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_221\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\,
      Q => p_2_in207_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_133\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_189\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\,
      Q => p_4_in209_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_173\,
      I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_205\,
      O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\,
      Q => p_6_in211_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\,
      I1 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\,
      I2 => p_3_in135_in,
      I3 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\,
      I4 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\,
      O => \p_138_out__0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg_n_0_[7]\,
      I1 => p_6_in136_in,
      I2 => p_0_in134_in,
      I3 => p_1_in137_in,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_138_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_262\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\,
      Q => p_0_in134_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_246\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\,
      Q => p_3_in135_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_286\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_294\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_254\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\,
      Q => p_1_in137_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_270\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_278\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_302\,
      O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\,
      Q => p_6_in136_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => p_4_in159_in,
      I1 => p_5_in160_in,
      I2 => p_3_in158_in,
      I3 => p_2_in157_in,
      I4 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\,
      O => \p_164_out__0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_7_in162_in,
      I1 => p_6_in161_in,
      I2 => p_0_in156_in,
      I3 => p_1_in163_in,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_164_out__0\,
      Q => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0\,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_158\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_214\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\,
      Q => p_0_in156_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_142\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_182\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\,
      Q => p_3_in158_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_166\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_238\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\,
      Q => p_5_in160_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_126\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_198\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\,
      Q => p_7_in162_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_118\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_230\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\,
      Q => p_1_in163_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_150\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_222\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\,
      Q => p_2_in157_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_134\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_190\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\,
      Q => p_4_in159_in,
      R => '0'
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E00E"
    )
        port map (
      I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\,
      I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_174\,
      I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_206\,
      O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\
    );
\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\,
      Q => p_6_in161_in,
      R => '0'
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      O => \p_0_in__3\(0)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(1),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      O => \p_0_in__3\(1)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(2),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(1),
      O => \p_0_in__3\(2)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(3),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(1),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(2),
      O => \p_0_in__3\(3)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(0),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(4),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(3),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(1),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(2),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6_n_0\,
      O => pb_cnt_eye_size_r
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(4),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(2),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(1),
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(3),
      O => \p_0_in__3\(4)
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010F01"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I1 => store_sr_req_pulsed_r,
      I2 => p_34_in,
      I3 => p_2_in33_in,
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(0),
      O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_6_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(0),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(1),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(1),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(2),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(2),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(3),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(3),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pb_cnt_eye_size_r,
      D => \p_0_in__3\(4),
      Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(4),
      R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(0),
      O => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\,
      Q => pb_detect_edge_done_r(0),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[0].pb_found_edge_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555000055551011"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2_n_0\,
      I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I5 => pb_detect_edge_done_r(0),
      O => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_found_edge_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\,
      Q => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\,
      I4 => pb_found_stable_eye_r77_out,
      I5 => \gen_track_left_edge[0].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\,
      I3 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2_n_0\
    );
\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(2),
      I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(1),
      I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(3),
      I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_303\(4),
      O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\
    );
\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      O => pb_found_stable_eye_r77_out
    );
\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\,
      Q => \gen_track_left_edge[0].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(0),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\,
      I4 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\
    );
\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\,
      Q => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      O => \p_0_in__4\(0)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(1),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      O => \p_0_in__4\(1)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(2),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(1),
      O => \p_0_in__4\(2)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(3),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(1),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(2),
      O => \p_0_in__4\(3)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(1),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(4),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(3),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(1),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(2),
      I5 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(4),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(2),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(1),
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(3),
      O => \p_0_in__4\(4)
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F11"
    )
        port map (
      I0 => p_1_in17_in,
      I1 => p_0_in102_in,
      I2 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in16_in,
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(1),
      O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(0),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(1),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(1),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(2),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(2),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(3),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(3),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\,
      D => \p_0_in__4\(4),
      Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(4),
      R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => p_0_in102_in,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(1),
      O => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\,
      Q => pb_detect_edge_done_r(1),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[1].pb_found_edge_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050505051515051"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2_n_0\,
      I2 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in16_in,
      I5 => pb_detect_edge_done_r(1),
      O => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_found_edge_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\,
      Q => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(1),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0\,
      I4 => pb_found_stable_eye_r73_out,
      I5 => \gen_track_left_edge[1].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in102_in,
      I2 => p_1_in17_in,
      I3 => p_0_in16_in,
      O => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2_n_0\
    );
\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(2),
      I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(0),
      I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(1),
      I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(3),
      I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_304\(4),
      O => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0\
    );
\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_0_in16_in,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\,
      O => pb_found_stable_eye_r73_out
    );
\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\,
      Q => \gen_track_left_edge[1].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(1),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => p_0_in102_in,
      I4 => p_0_in16_in,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\
    );
\gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\,
      Q => p_0_in16_in,
      R => '0'
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      O => \p_0_in__5\(0)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(1),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      O => \p_0_in__5\(1)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(2),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(1),
      O => \p_0_in__5\(2)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(3),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(1),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(2),
      O => \p_0_in__5\(3)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(2),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(4),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(3),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(1),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(2),
      I5 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(4),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(2),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(1),
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(3),
      O => \p_0_in__5\(4)
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F11"
    )
        port map (
      I0 => p_1_in14_in,
      I1 => p_0_in99_in,
      I2 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in13_in,
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(2),
      O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(0),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(1),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(1),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(2),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(2),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(3),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(3),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\,
      D => \p_0_in__5\(4),
      Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(4),
      R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => p_0_in99_in,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(2),
      O => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\,
      Q => pb_detect_edge_done_r(2),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[2].pb_found_edge_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050505051515051"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2_n_0\,
      I2 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in13_in,
      I5 => pb_detect_edge_done_r(2),
      O => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_found_edge_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\,
      Q => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(2),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0\,
      I4 => pb_found_stable_eye_r69_out,
      I5 => \gen_track_left_edge[2].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in99_in,
      I2 => p_1_in14_in,
      I3 => p_0_in13_in,
      O => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2_n_0\
    );
\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(2),
      I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(0),
      I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(1),
      I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(3),
      I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_305\(4),
      O => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0\
    );
\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_0_in13_in,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\,
      O => pb_found_stable_eye_r69_out
    );
\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\,
      Q => \gen_track_left_edge[2].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(2),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => p_0_in99_in,
      I4 => p_0_in13_in,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\
    );
\gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\,
      Q => p_0_in13_in,
      R => '0'
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      O => \p_0_in__6\(0)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(1),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      O => \p_0_in__6\(1)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(2),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(1),
      O => \p_0_in__6\(2)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(3),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(1),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(2),
      O => \p_0_in__6\(3)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(3),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(4),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(3),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(1),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(2),
      I5 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(4),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(2),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(1),
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(3),
      O => \p_0_in__6\(4)
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F11"
    )
        port map (
      I0 => p_1_in11_in,
      I1 => p_0_in96_in,
      I2 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in10_in,
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(3),
      O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(0),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(1),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(1),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(2),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(2),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(3),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(3),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\,
      D => \p_0_in__6\(4),
      Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(4),
      R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => p_0_in96_in,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(3),
      O => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\,
      Q => pb_detect_edge_done_r(3),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[3].pb_found_edge_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050505051515051"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2_n_0\,
      I2 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in10_in,
      I5 => pb_detect_edge_done_r(3),
      O => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_found_edge_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\,
      Q => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(3),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0\,
      I4 => pb_found_stable_eye_r65_out,
      I5 => \gen_track_left_edge[3].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in96_in,
      I2 => p_1_in11_in,
      I3 => p_0_in10_in,
      O => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2_n_0\
    );
\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(2),
      I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(0),
      I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(1),
      I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(3),
      I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_306\(4),
      O => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0\
    );
\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_0_in10_in,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\,
      O => pb_found_stable_eye_r65_out
    );
\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\,
      Q => \gen_track_left_edge[3].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(3),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => p_0_in96_in,
      I4 => p_0_in10_in,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\
    );
\gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\,
      Q => p_0_in10_in,
      R => '0'
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      O => \p_0_in__7\(0)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(1),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      O => \p_0_in__7\(1)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(2),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(1),
      O => \p_0_in__7\(2)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(3),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(1),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(2),
      O => \p_0_in__7\(3)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(4),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(4),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(3),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(1),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(2),
      I5 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(4),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(2),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(1),
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(3),
      O => \p_0_in__7\(4)
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F11"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in93_in,
      I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in7_in,
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(4),
      O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(0),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(1),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(1),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(2),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(2),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(3),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(3),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\,
      D => \p_0_in__7\(4),
      Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(4),
      R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => p_0_in93_in,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(4),
      O => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\,
      Q => pb_detect_edge_done_r(4),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[4].pb_found_edge_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050505051515051"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2_n_0\,
      I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in7_in,
      I5 => pb_detect_edge_done_r(4),
      O => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_found_edge_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\,
      Q => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(4),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0\,
      I4 => pb_found_stable_eye_r61_out,
      I5 => \gen_track_left_edge[4].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in93_in,
      I2 => p_1_in8_in,
      I3 => p_0_in7_in,
      O => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2_n_0\
    );
\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(2),
      I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(0),
      I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(1),
      I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(3),
      I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_307\(4),
      O => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0\
    );
\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\,
      O => pb_found_stable_eye_r61_out
    );
\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\,
      Q => \gen_track_left_edge[4].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(4),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => p_0_in93_in,
      I4 => p_0_in7_in,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\
    );
\gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\,
      Q => p_0_in7_in,
      R => '0'
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      O => \p_0_in__8\(0)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(1),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      O => \p_0_in__8\(1)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(2),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(1),
      O => \p_0_in__8\(2)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(3),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(1),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(2),
      O => \p_0_in__8\(3)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(5),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(4),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(3),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(1),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(2),
      I5 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(4),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(2),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(1),
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(3),
      O => \p_0_in__8\(4)
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F11"
    )
        port map (
      I0 => p_1_in5_in,
      I1 => p_0_in90_in,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in4_in,
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(5),
      O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(0),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(1),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(1),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(2),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(2),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(3),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(3),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\,
      D => \p_0_in__8\(4),
      Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(4),
      R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => p_0_in90_in,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(5),
      O => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\,
      Q => pb_detect_edge_done_r(5),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[5].pb_found_edge_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050505051515051"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2_n_0\,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in4_in,
      I5 => pb_detect_edge_done_r(5),
      O => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_found_edge_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\,
      Q => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(5),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0\,
      I4 => pb_found_stable_eye_r57_out,
      I5 => \gen_track_left_edge[5].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in90_in,
      I2 => p_1_in5_in,
      I3 => p_0_in4_in,
      O => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2_n_0\
    );
\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(2),
      I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(0),
      I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(1),
      I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(3),
      I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_308\(4),
      O => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0\
    );
\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_0_in4_in,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\,
      O => pb_found_stable_eye_r57_out
    );
\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\,
      Q => \gen_track_left_edge[5].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(5),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => p_0_in90_in,
      I4 => p_0_in4_in,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\
    );
\gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\,
      Q => p_0_in4_in,
      R => '0'
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      O => \p_0_in__9\(0)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(1),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      O => \p_0_in__9\(1)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(2),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(1),
      O => \p_0_in__9\(2)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(3),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(1),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(2),
      O => \p_0_in__9\(3)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(6),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(4),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(3),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(1),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(2),
      I5 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(4),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(2),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(1),
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(3),
      O => \p_0_in__9\(4)
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F11"
    )
        port map (
      I0 => p_1_in2_in,
      I1 => p_0_in87_in,
      I2 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in1_in,
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(6),
      O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(0),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(1),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(1),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(2),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(2),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(3),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(3),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\,
      D => \p_0_in__9\(4),
      Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(4),
      R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => p_0_in87_in,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(6),
      O => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\,
      Q => pb_detect_edge_done_r(6),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[6].pb_found_edge_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050505051515051"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2_n_0\,
      I2 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in1_in,
      I5 => pb_detect_edge_done_r(6),
      O => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_found_edge_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\,
      Q => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(6),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0\,
      I4 => pb_found_stable_eye_r53_out,
      I5 => \gen_track_left_edge[6].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => p_0_in87_in,
      I2 => p_1_in2_in,
      I3 => p_0_in1_in,
      O => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2_n_0\
    );
\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(2),
      I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(0),
      I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(1),
      I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(3),
      I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_309\(4),
      O => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0\
    );
\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\,
      O => pb_found_stable_eye_r53_out
    );
\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\,
      Q => \gen_track_left_edge[6].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(6),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => p_0_in87_in,
      I4 => p_0_in1_in,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\
    );
\gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\,
      Q => p_0_in1_in,
      R => '0'
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      O => \p_0_in__10\(0)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(1),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      O => \p_0_in__10\(1)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(2),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(1),
      O => \p_0_in__10\(2)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(3),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(1),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(2),
      O => \p_0_in__10\(3)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => p_5_in,
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\,
      I4 => pb_detect_edge_done_r(7),
      I5 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFFFFFFF"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(4),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(3),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(1),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(2),
      I5 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(4),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(2),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(1),
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(3),
      O => \p_0_in__10\(4)
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F11"
    )
        port map (
      I0 => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      I1 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I2 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in,
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      I2 => store_sr_req_pulsed_r,
      I3 => p_34_in,
      I4 => p_2_in33_in,
      I5 => pb_detect_edge_done_r(7),
      O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(0),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(1),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(1),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(2),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(2),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(3),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(3),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\,
      D => \p_0_in__10\(4),
      Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(4),
      R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => p_5_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[6]\,
      O => pb_detect_edge_setup
    );
\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I2 => samp_cnt_done_r_reg_n_0,
      I3 => pb_detect_edge_done_r(7),
      O => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0\
    );
\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0\,
      Q => pb_detect_edge_done_r(7),
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[7].pb_found_edge_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5050505051515051"
    )
        port map (
      I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I1 => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0\,
      I2 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      I3 => samp_cnt_done_r_reg_n_0,
      I4 => p_0_in,
      I5 => pb_detect_edge_done_r(7),
      O => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_found_edge_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\,
      Q => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFE01000000"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0\,
      I1 => pb_detect_edge_done_r(7),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0\,
      I4 => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4_n_0\,
      I5 => \gen_track_left_edge[7].pb_found_stable_eye_r_reg\,
      O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I2 => \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7]\,
      I3 => p_0_in,
      O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(2),
      I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(0),
      I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(1),
      I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(3),
      I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_310\(4),
      O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_0_in,
      I1 => samp_cnt_done_r_reg_n_0,
      I2 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\,
      O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4_n_0\
    );
\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\,
      Q => \gen_track_left_edge[7].pb_found_stable_eye_r_reg\,
      R => pb_detect_edge_setup
    );
\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFD0100"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => pb_detect_edge_done_r(7),
      I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\,
      I3 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7]\,
      I4 => p_0_in,
      I5 => pb_detect_edge_setup,
      O => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\
    );
\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
idel_adj_inc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00DFDF20000000"
    )
        port map (
      I0 => detect_edge_done_r,
      I1 => idel_adj_inc_i_2_n_0,
      I2 => p_34_in,
      I3 => cal1_wait_r,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\,
      I5 => idel_adj_inc_reg_n_0,
      O => idel_adj_inc_i_1_n_0
    );
idel_adj_inc_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\,
      O => idel_adj_inc_i_2_n_0
    );
idel_adj_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idel_adj_inc_i_1_n_0,
      Q => idel_adj_inc_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idel_dec_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \idel_dec_cnt__0\(0),
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I2 => \idel_dec_cnt_reg[0]_i_2_n_0\,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      O => idel_dec_cnt(0)
    );
\idel_dec_cnt[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][3][0]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][2][0]\,
      O => \idel_dec_cnt[0]_i_3_n_0\
    );
\idel_dec_cnt[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][5][0]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][4][0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][7][0]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][6][0]\,
      O => \idel_dec_cnt[0]_i_4_n_0\
    );
\idel_dec_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF909090"
    )
        port map (
      I0 => \idel_dec_cnt__0\(1),
      I1 => \idel_dec_cnt__0\(0),
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I3 => idelay_tap_cnt_r(1),
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      O => idel_dec_cnt(1)
    );
\idel_dec_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFA900A900A900"
    )
        port map (
      I0 => \idel_dec_cnt__0\(2),
      I1 => \idel_dec_cnt__0\(0),
      I2 => \idel_dec_cnt__0\(1),
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I4 => idelay_tap_cnt_r(2),
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      O => idel_dec_cnt(2)
    );
\idel_dec_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF606060"
    )
        port map (
      I0 => \idel_dec_cnt__0\(3),
      I1 => \idel_dec_cnt[3]_i_2_n_0\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I3 => idelay_tap_cnt_r(3),
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      O => idel_dec_cnt(3)
    );
\idel_dec_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \idel_dec_cnt__0\(0),
      I1 => \idel_dec_cnt__0\(1),
      I2 => \idel_dec_cnt__0\(2),
      O => \idel_dec_cnt[3]_i_2_n_0\
    );
\idel_dec_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAEAAAEAAAEAA"
    )
        port map (
      I0 => \idel_dec_cnt[4]_i_3_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      I2 => \idel_dec_cnt[4]_i_4_n_0\,
      I3 => stable_idel_cnt23_in,
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I5 => cal1_state_r2,
      O => \idel_dec_cnt[4]_i_1_n_0\
    );
\idel_dec_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF606060"
    )
        port map (
      I0 => \idel_dec_cnt__0\(4),
      I1 => \idel_dec_cnt[4]_i_6_n_0\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[23]\,
      I3 => idelay_tap_cnt_r(4),
      I4 => \FSM_onehot_cal1_state_r_reg_n_0_[4]\,
      O => idel_dec_cnt(4)
    );
\idel_dec_cnt[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20202020202020"
    )
        port map (
      I0 => detect_edge_done_r,
      I1 => idel_adj_inc_i_2_n_0,
      I2 => p_34_in,
      I3 => idel_pat_detect_valid_r_reg_n_0,
      I4 => idel_mpr_pat_detect_r,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      O => \idel_dec_cnt[4]_i_3_n_0\
    );
\idel_dec_cnt[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\,
      I1 => mpr_dec_cpt_r_reg_n_0,
      I2 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\,
      I3 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\,
      I4 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\,
      I5 => \idel_dec_cnt[4]_i_7_n_0\,
      O => \idel_dec_cnt[4]_i_4_n_0\
    );
\idel_dec_cnt[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \idel_dec_cnt__0\(4),
      I1 => \idel_dec_cnt__0\(3),
      I2 => \idel_dec_cnt__0\(0),
      I3 => \idel_dec_cnt__0\(1),
      I4 => \idel_dec_cnt__0\(2),
      O => cal1_state_r2
    );
\idel_dec_cnt[4]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \idel_dec_cnt__0\(2),
      I1 => \idel_dec_cnt__0\(1),
      I2 => \idel_dec_cnt__0\(0),
      I3 => \idel_dec_cnt__0\(3),
      O => \idel_dec_cnt[4]_i_6_n_0\
    );
\idel_dec_cnt[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\,
      I1 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\,
      O => \idel_dec_cnt[4]_i_7_n_0\
    );
\idel_dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(0),
      Q => \idel_dec_cnt__0\(0),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idel_dec_cnt_reg[0]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idel_dec_cnt[0]_i_3_n_0\,
      I1 => \idel_dec_cnt[0]_i_4_n_0\,
      O => \idel_dec_cnt_reg[0]_i_2_n_0\,
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idel_dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(1),
      Q => \idel_dec_cnt__0\(1),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idel_dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(2),
      Q => \idel_dec_cnt__0\(2),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idel_dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(3),
      Q => \idel_dec_cnt__0\(3),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idel_dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \idel_dec_cnt[4]_i_1_n_0\,
      D => idel_dec_cnt(4),
      Q => \idel_dec_cnt__0\(4),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
idel_pat_detect_valid_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCCE"
    )
        port map (
      I0 => idel_pat_detect_valid_r_reg_n_0,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => store_sr_req_pulsed_r,
      I3 => cal1_dq_idel_inc,
      O => idel_pat_detect_valid_r_i_1_n_0
    );
idel_pat_detect_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idel_pat_detect_valid_r_i_1_n_0,
      Q => idel_pat_detect_valid_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idelay_tap_cnt_r[0][0][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^idelay_ce_int\,
      I2 => idelay_tap_cnt_slice_r(0),
      O => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404004"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^idelay_ce_int\,
      I2 => idelay_tap_cnt_slice_r(0),
      I3 => idelay_tap_cnt_slice_r(1),
      I4 => \^idelay_inc_int\,
      O => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444400044400004"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^idelay_ce_int\,
      I2 => \^idelay_inc_int\,
      I3 => idelay_tap_cnt_slice_r(0),
      I4 => idelay_tap_cnt_slice_r(2),
      I5 => idelay_tap_cnt_slice_r(1),
      O => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28A0A0A0A0A0A082"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][0][3]_i_2_n_0\,
      I1 => idelay_tap_cnt_slice_r(2),
      I2 => idelay_tap_cnt_slice_r(3),
      I3 => idelay_tap_cnt_slice_r(0),
      I4 => \^idelay_inc_int\,
      I5 => idelay_tap_cnt_slice_r(1),
      O => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\
    );
\idelay_tap_cnt_r[0][0][3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \idelay_tap_cnt_r[0][0][3]_i_2_n_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^idelay_ce_int\,
      I2 => \idelay_tap_cnt_r[0][0][4]_i_6_n_0\,
      O => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \^idelay_ce_int\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      O => \idelay_tap_cnt_r_reg[0][0][4]_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      O => \idelay_tap_cnt_r_reg[0][3][4]_0\
    );
\idelay_tap_cnt_r[0][0][4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555556"
    )
        port map (
      I0 => idelay_tap_cnt_slice_r(4),
      I1 => idelay_tap_cnt_slice_r(0),
      I2 => \^idelay_inc_int\,
      I3 => idelay_tap_cnt_slice_r(1),
      I4 => idelay_tap_cnt_slice_r(3),
      I5 => idelay_tap_cnt_slice_r(2),
      O => \idelay_tap_cnt_r[0][0][4]_i_6_n_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \^idelay_ce_int\,
      O => \idelay_tap_cnt_r_reg[0][1][4]_0\
    );
\idelay_tap_cnt_r[0][2][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => \idelay_tap_cnt_r_reg[0][2][4]_0\
    );
\idelay_tap_cnt_r[0][3][4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \^idelay_ce_int\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      O => \idelay_tap_cnt_r_reg[0][7][4]_0\
    );
\idelay_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][2][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_1\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_1\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_1\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_1\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_1\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][3][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_2\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_2\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_2\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_2\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_2\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][4][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]_0\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]_0\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]_0\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]_0\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[0]_0\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][5][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_3\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_3\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_3\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_3\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_3\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][6][4]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_4\(0),
      D => \idelay_tap_cnt_r[0][0][0]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][0]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_4\(0),
      D => \idelay_tap_cnt_r[0][0][1]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][1]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_4\(0),
      D => \idelay_tap_cnt_r[0][0][2]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][2]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_4\(0),
      D => \idelay_tap_cnt_r[0][0][3]_i_1_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][3]\,
      R => '0'
    );
\idelay_tap_cnt_r_reg[0][7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_stg2_wrcal_cnt_reg[1]_4\(0),
      D => \idelay_tap_cnt_r[0][0][4]_i_2_n_0\,
      Q => \idelay_tap_cnt_r_reg_n_0_[0][7][4]\,
      R => '0'
    );
\idelay_tap_cnt_slice_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \idel_dec_cnt_reg[0]_i_2_n_0\,
      O => idelay_tap_cnt_r(0)
    );
\idelay_tap_cnt_slice_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][1]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\,
      O => \idelay_tap_cnt_slice_r[1]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][1]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][1]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][1]\,
      O => \idelay_tap_cnt_slice_r[1]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][2]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][2]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\,
      O => \idelay_tap_cnt_slice_r[2]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][2]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][2]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][2]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][2]\,
      O => \idelay_tap_cnt_slice_r[2]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][3]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][3]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\,
      O => \idelay_tap_cnt_slice_r[3]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][3]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][3]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][3]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][3]\,
      O => \idelay_tap_cnt_slice_r[3]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][3][4]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][2][4]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\,
      O => \idelay_tap_cnt_slice_r[4]_i_2_n_0\
    );
\idelay_tap_cnt_slice_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \idelay_tap_cnt_r_reg_n_0_[0][7][4]\,
      I1 => \idelay_tap_cnt_r_reg_n_0_[0][6][4]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \idelay_tap_cnt_r_reg_n_0_[0][5][4]\,
      I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \idelay_tap_cnt_r_reg_n_0_[0][4][4]\,
      O => \idelay_tap_cnt_slice_r[4]_i_3_n_0\
    );
\idelay_tap_cnt_slice_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(0),
      Q => idelay_tap_cnt_slice_r(0),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idelay_tap_cnt_slice_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(1),
      Q => idelay_tap_cnt_slice_r(1),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idelay_tap_cnt_slice_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[1]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[1]_i_3_n_0\,
      O => idelay_tap_cnt_r(1),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idelay_tap_cnt_slice_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(2),
      Q => idelay_tap_cnt_slice_r(2),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idelay_tap_cnt_slice_r_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[2]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[2]_i_3_n_0\,
      O => idelay_tap_cnt_r(2),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idelay_tap_cnt_slice_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(3),
      Q => idelay_tap_cnt_slice_r(3),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idelay_tap_cnt_slice_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[3]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[3]_i_3_n_0\,
      O => idelay_tap_cnt_r(3),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
\idelay_tap_cnt_slice_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_cnt_r(4),
      Q => idelay_tap_cnt_slice_r(4),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\idelay_tap_cnt_slice_r_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \idelay_tap_cnt_slice_r[4]_i_2_n_0\,
      I1 => \idelay_tap_cnt_slice_r[4]_i_3_n_0\,
      O => idelay_tap_cnt_r(4),
      S => \cal1_cnt_cpt_r_reg_n_0_[2]\
    );
idelay_tap_limit_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => idelay_tap_limit_r_i_2_n_0,
      I1 => \^idelay_tap_limit_r_reg_0\,
      I2 => \rstdiv0_sync_r1_reg_rep__22\,
      O => idelay_tap_limit_r_i_1_n_0
    );
idelay_tap_limit_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF20000000"
    )
        port map (
      I0 => idelay_tap_cnt_r(3),
      I1 => \idel_dec_cnt_reg[0]_i_2_n_0\,
      I2 => idelay_tap_cnt_r(1),
      I3 => idelay_tap_cnt_r(2),
      I4 => idelay_tap_cnt_r(4),
      I5 => idelay_tap_limit_r_reg_n_0,
      O => idelay_tap_limit_r_i_2_n_0
    );
idelay_tap_limit_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_tap_limit_r_i_1_n_0,
      Q => idelay_tap_limit_r_reg_n_0,
      R => '0'
    );
\init_state_r[2]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBFB"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => pi_dqs_found_done,
      I2 => \one_rank.stg1_wr_done_reg\,
      I3 => \^rdlvl_last_byte_done\,
      O => \init_state_r_reg[2]\
    );
\init_state_r[4]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => \^rdlvl_last_byte_done\,
      I1 => \one_rank.stg1_wr_done_reg\,
      I2 => pi_dqs_found_done,
      O => \init_state_r_reg[4]\
    );
\init_state_r[4]_i_31\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => mem_init_done_r,
      O => \init_state_r_reg[4]_1\
    );
\init_state_r[4]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8C"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => pi_dqs_found_done,
      I2 => wrlvl_done_r1,
      O => \init_state_r_reg[4]_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\,
      I1 => p_1_in26_in,
      I2 => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\,
      I3 => inhibit_edge_detect_r,
      I4 => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\,
      I1 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I4 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I5 => idel_mpr_pat_detect_r,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I1 => idel_pat_detect_valid_r_reg_n_0,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      O => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\
    );
\mpr_4to1.idel_mpr_pat_detect_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\,
      Q => idel_mpr_pat_detect_r,
      R => '0'
    );
\mpr_4to1.inhibit_edge_detect_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FB00FFFF"
    )
        port map (
      I0 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\,
      I3 => inhibit_edge_detect_r,
      I4 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\,
      O => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => mpr_rd_rise0_prev_r,
      I1 => mpr_rd_rise2_prev_r,
      I2 => mpr_rd_rise3_prev_r,
      I3 => mpr_rd_rise1_prev_r,
      I4 => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\,
      O => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => idelay_tap_cnt_r(1),
      I1 => idelay_tap_cnt_r(2),
      I2 => idelay_tap_cnt_r(3),
      I3 => idelay_tap_cnt_r(4),
      O => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555554"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\,
      I2 => mpr_rd_fall2_prev_r,
      I3 => mpr_rd_fall1_prev_r,
      I4 => mpr_rd_fall3_prev_r,
      I5 => mpr_rd_fall0_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => mpr_rd_fall2_prev_r,
      I1 => mpr_rd_fall3_prev_r,
      I2 => mpr_rd_fall0_prev_r,
      I3 => mpr_rd_fall1_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => mpr_rd_rise1_prev_r,
      I1 => mpr_rd_rise0_prev_r,
      I2 => mpr_rd_rise2_prev_r,
      I3 => mpr_rd_rise3_prev_r,
      O => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\
    );
\mpr_4to1.inhibit_edge_detect_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\,
      Q => inhibit_edge_detect_r,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I1 => stable_idel_cnt,
      I2 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I1 => stable_idel_cnt,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I3 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I1 => stable_idel_cnt,
      I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      I4 => stable_idel_cnt0,
      O => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => stable_idel_cnt23_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => idel_pat_detect_valid_r_reg_n_0,
      I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      I4 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      I5 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      O => stable_idel_cnt
    );
\mpr_4to1.stable_idel_cnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[30]\,
      I2 => \rstdiv0_sync_r1_reg_rep__21\,
      O => stable_idel_cnt0
    );
\mpr_4to1.stable_idel_cnt[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\,
      I1 => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      I2 => mpr_rd_fall0_prev_r,
      I3 => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      I4 => mpr_rd_fall2_prev_r,
      I5 => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\,
      O => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      I1 => mpr_rd_rise3_prev_r,
      I2 => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      I3 => mpr_rd_rise0_prev_r,
      O => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
        port map (
      I0 => mpr_rd_rise1_prev_r,
      I1 => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      I2 => mpr_rd_rise2_prev_r,
      I3 => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      I4 => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\,
      O => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\
    );
\mpr_4to1.stable_idel_cnt[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      I1 => mpr_rd_fall1_prev_r,
      I2 => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      I3 => mpr_rd_fall3_prev_r,
      O => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\
    );
\mpr_4to1.stable_idel_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\,
      R => '0'
    );
\mpr_4to1.stable_idel_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\,
      Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\,
      R => '0'
    );
mpr_dec_cpt_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D5C0"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[5]\,
      I1 => \pi_counter_read_val_reg[2]_0\,
      I2 => p_27_in,
      I3 => mpr_dec_cpt_r_reg_n_0,
      O => mpr_dec_cpt_r_i_1_n_0
    );
mpr_dec_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mpr_dec_cpt_r_i_1_n_0,
      Q => mpr_dec_cpt_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
mpr_rd_fall0_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => mpr_rd_fall0_prev_r,
      R => '0'
    );
mpr_rd_fall1_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => mpr_rd_fall1_prev_r,
      R => '0'
    );
mpr_rd_fall2_prev_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => p_1_in26_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\,
      I2 => idel_pat_detect_valid_r_reg_n_0,
      O => mpr_rd_rise0_prev_r0
    );
mpr_rd_fall2_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => mpr_rd_fall2_prev_r,
      R => '0'
    );
mpr_rd_fall3_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => mpr_rd_fall3_prev_r,
      R => '0'
    );
mpr_rd_rise0_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => mpr_rd_rise0_prev_r,
      R => '0'
    );
mpr_rd_rise1_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => mpr_rd_rise1_prev_r,
      R => '0'
    );
mpr_rd_rise2_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => mpr_rd_rise2_prev_r,
      R => '0'
    );
mpr_rd_rise3_prev_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => mpr_rd_rise0_prev_r0,
      D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => mpr_rd_rise3_prev_r,
      R => '0'
    );
mpr_rdlvl_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mpr_rdlvl_start_reg,
      Q => \^mpr_rdlvl_start_r\,
      R => '0'
    );
new_cnt_cpt_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAABABAAAAAAAAA"
    )
        port map (
      I0 => new_cnt_cpt_r_i_2_n_0,
      I1 => rdlvl_stg1_start_r,
      I2 => rdlvl_stg1_start_reg,
      I3 => \^mpr_rdlvl_start_r\,
      I4 => mpr_rdlvl_start_reg,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      O => new_cnt_cpt_r
    );
new_cnt_cpt_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA0000"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \^cal1_cnt_cpt_r_reg[1]_0\,
      I4 => prech_done,
      O => new_cnt_cpt_r_i_2_n_0
    );
new_cnt_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => new_cnt_cpt_r,
      Q => \^idelay_tap_limit_r_reg_0\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\phaser_in_gen.phaser_in_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_en,
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \pi_dqs_found_lanes_r1_reg[4]\
    );
\phaser_in_gen.phaser_in_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => COUNTERLOADVAL(1)
    );
\phaser_in_gen.phaser_in_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]\(1)
    );
\phaser_in_gen.phaser_in_i_10__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(1),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_0\(1)
    );
\phaser_in_gen.phaser_in_i_10__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(1),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_0\(1)
    );
\phaser_in_gen.phaser_in_i_10__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => pi_counter_load_val(1),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_0\(1)
    );
\phaser_in_gen.phaser_in_i_10__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]\(1)
    );
\phaser_in_gen.phaser_in_i_10__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => pi_counter_load_val(1),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_0\(1)
    );
\phaser_in_gen.phaser_in_i_10__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(1),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_0\(1)
    );
\phaser_in_gen.phaser_in_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => COUNTERLOADVAL(0)
    );
\phaser_in_gen.phaser_in_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]\(0)
    );
\phaser_in_gen.phaser_in_i_11__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_0\(0)
    );
\phaser_in_gen.phaser_in_i_11__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_0\(0)
    );
\phaser_in_gen.phaser_in_i_11__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => pi_counter_load_val(0),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_0\(0)
    );
\phaser_in_gen.phaser_in_i_11__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]\(0)
    );
\phaser_in_gen.phaser_in_i_11__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => pi_counter_load_val(0),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_0\(0)
    );
\phaser_in_gen.phaser_in_i_11__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(0),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_0\(0)
    );
\phaser_in_gen.phaser_in_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_en,
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]_0\
    );
\phaser_in_gen.phaser_in_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_en,
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]\
    );
\phaser_in_gen.phaser_in_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_en,
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]\
    );
\phaser_in_gen.phaser_in_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => pi_counter_load_en,
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]\
    );
\phaser_in_gen.phaser_in_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_en,
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]_0\
    );
\phaser_in_gen.phaser_in_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => pi_counter_load_en,
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]\
    );
\phaser_in_gen.phaser_in_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_en,
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]\
    );
\phaser_in_gen.phaser_in_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]_1\
    );
\phaser_in_gen.phaser_in_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE0E00"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_1\
    );
\phaser_in_gen.phaser_in_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_1\
    );
\phaser_in_gen.phaser_in_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEE000"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(0),
      I3 => Q(1),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_1\
    );
\phaser_in_gen.phaser_in_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]_1\
    );
\phaser_in_gen.phaser_in_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(0),
      I3 => Q(1),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_1\
    );
\phaser_in_gen.phaser_in_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_1\
    );
\phaser_in_gen.phaser_in_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => tempmon_pi_f_en_r,
      I1 => rdlvl_pi_stg2_f_en,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(1),
      O => \pi_dqs_found_lanes_r1_reg[4]_0\
    );
\phaser_in_gen.phaser_in_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]_2\
    );
\phaser_in_gen.phaser_in_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE0E00"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_2\
    );
\phaser_in_gen.phaser_in_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_2\
    );
\phaser_in_gen.phaser_in_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEE000"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(0),
      I3 => Q(1),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_2\
    );
\phaser_in_gen.phaser_in_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]_2\
    );
\phaser_in_gen.phaser_in_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(0),
      I3 => Q(1),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_2\
    );
\phaser_in_gen.phaser_in_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE00E0"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_2\
    );
\phaser_in_gen.phaser_in_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEE000E"
    )
        port map (
      I0 => tempmon_pi_f_inc_r,
      I1 => rdlvl_pi_stg2_f_incdec,
      I2 => Q(1),
      I3 => Q(0),
      I4 => calib_in_common,
      I5 => \calib_zero_inputs_reg[2]\(1),
      O => \pi_dqs_found_lanes_r1_reg[4]_1\
    );
\phaser_in_gen.phaser_in_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(5),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => COUNTERLOADVAL(5)
    );
\phaser_in_gen.phaser_in_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(5),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]\(5)
    );
\phaser_in_gen.phaser_in_i_6__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(5),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_0\(5)
    );
\phaser_in_gen.phaser_in_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(5),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_0\(5)
    );
\phaser_in_gen.phaser_in_i_6__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => pi_counter_load_val(5),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_0\(5)
    );
\phaser_in_gen.phaser_in_i_6__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(5),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]\(5)
    );
\phaser_in_gen.phaser_in_i_6__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => pi_counter_load_val(5),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_0\(5)
    );
\phaser_in_gen.phaser_in_i_6__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(5),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_0\(5)
    );
\phaser_in_gen.phaser_in_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(4),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => COUNTERLOADVAL(4)
    );
\phaser_in_gen.phaser_in_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(4),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]\(4)
    );
\phaser_in_gen.phaser_in_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(4),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_0\(4)
    );
\phaser_in_gen.phaser_in_i_7__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(4),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_0\(4)
    );
\phaser_in_gen.phaser_in_i_7__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => pi_counter_load_val(4),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_0\(4)
    );
\phaser_in_gen.phaser_in_i_7__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(4),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]\(4)
    );
\phaser_in_gen.phaser_in_i_7__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => pi_counter_load_val(4),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_0\(4)
    );
\phaser_in_gen.phaser_in_i_7__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(4),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_0\(4)
    );
\phaser_in_gen.phaser_in_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(3),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => COUNTERLOADVAL(3)
    );
\phaser_in_gen.phaser_in_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(3),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]\(3)
    );
\phaser_in_gen.phaser_in_i_8__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(3),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_0\(3)
    );
\phaser_in_gen.phaser_in_i_8__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(3),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_0\(3)
    );
\phaser_in_gen.phaser_in_i_8__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => pi_counter_load_val(3),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_0\(3)
    );
\phaser_in_gen.phaser_in_i_8__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(3),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]\(3)
    );
\phaser_in_gen.phaser_in_i_8__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => pi_counter_load_val(3),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_0\(3)
    );
\phaser_in_gen.phaser_in_i_8__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(3),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_0\(3)
    );
\phaser_in_gen.phaser_in_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(2),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => COUNTERLOADVAL(2)
    );
\phaser_in_gen.phaser_in_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(2),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[0]\(2)
    );
\phaser_in_gen.phaser_in_i_9__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(2),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[1]_0\(2)
    );
\phaser_in_gen.phaser_in_i_9__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(2),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[2]_0\(2)
    );
\phaser_in_gen.phaser_in_i_9__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => pi_counter_load_val(2),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \pi_dqs_found_lanes_r1_reg[3]_0\(2)
    );
\phaser_in_gen.phaser_in_i_9__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => pi_counter_load_val(2),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[8]\(2)
    );
\phaser_in_gen.phaser_in_i_9__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => pi_counter_load_val(2),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[9]_0\(2)
    );
\phaser_in_gen.phaser_in_i_9__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => pi_counter_load_val(2),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \pi_dqs_found_lanes_r1_reg[10]_0\(2)
    );
pi_cnt_dec_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \pi_rdval_cnt[5]_i_3_n_0\,
      I1 => pi_cnt_dec_i_2_n_0,
      O => pi_cnt_dec_i_1_n_0
    );
pi_cnt_dec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFFFFF"
    )
        port map (
      I0 => wait_cnt_r_reg(3),
      I1 => wait_cnt_r_reg(2),
      I2 => wait_cnt_r_reg(1),
      I3 => dqs_po_dec_done_r2,
      I4 => \rstdiv0_sync_r1_reg_rep__22\,
      I5 => wait_cnt_r_reg(0),
      O => pi_cnt_dec_i_2_n_0
    );
pi_cnt_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_cnt_dec_i_1_n_0,
      Q => \^fine_dly_dec_done_r1_reg_0\,
      R => '0'
    );
pi_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_en_stg2_f_timing,
      Q => rdlvl_pi_stg2_f_en,
      R => '0'
    );
pi_en_stg2_f_timing_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => \^fine_dly_dec_done_r1_reg_0\,
      O => pi_en_stg2_f_timing_i_1_n_0
    );
pi_en_stg2_f_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_en_stg2_f_timing_i_1_n_0,
      Q => pi_en_stg2_f_timing,
      R => SR(1)
    );
pi_fine_dly_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fine_dly_dec_done_r2,
      Q => \^pi_fine_dly_dec_done\,
      R => '0'
    );
\pi_rdval_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \pi_counter_read_val_reg[0]\,
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      I4 => pi_rdval_cnt(0),
      O => \pi_rdval_cnt[0]_i_1_n_0\
    );
\pi_rdval_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB0808080808FB08"
    )
        port map (
      I0 => \pi_counter_read_val_reg[1]\,
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      I4 => pi_rdval_cnt(1),
      I5 => pi_rdval_cnt(0),
      O => \pi_rdval_cnt[1]_i_1_n_0\
    );
\pi_rdval_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B888888888B8"
    )
        port map (
      I0 => \pi_counter_read_val_reg[2]\,
      I1 => \pi_rdval_cnt[5]_i_5_n_0\,
      I2 => \pi_rdval_cnt[5]_i_3_n_0\,
      I3 => pi_rdval_cnt(0),
      I4 => pi_rdval_cnt(1),
      I5 => pi_rdval_cnt(2),
      O => \pi_rdval_cnt[2]_i_1_n_0\
    );
\pi_rdval_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808FB08FB080808"
    )
        port map (
      I0 => \pi_counter_read_val_reg[3]\,
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      I4 => \pi_rdval_cnt[5]_i_4_n_0\,
      I5 => pi_rdval_cnt(3),
      O => \pi_rdval_cnt[3]_i_1_n_0\
    );
\pi_rdval_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF9A0000009A00"
    )
        port map (
      I0 => pi_rdval_cnt(4),
      I1 => pi_rdval_cnt(3),
      I2 => \pi_rdval_cnt[5]_i_4_n_0\,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      I4 => \pi_rdval_cnt[5]_i_5_n_0\,
      I5 => \pi_counter_read_val_reg[4]\,
      O => \pi_rdval_cnt[4]_i_1_n_0\
    );
\pi_rdval_cnt[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AEFF"
    )
        port map (
      I0 => \^fine_dly_dec_done_r1_reg_0\,
      I1 => dqs_po_dec_done_r1,
      I2 => dqs_po_dec_done_r2,
      I3 => \pi_rdval_cnt[5]_i_3_n_0\,
      O => \pi_rdval_cnt[5]_i_1_n_0\
    );
\pi_rdval_cnt[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFA8AA0000A8AA"
    )
        port map (
      I0 => pi_rdval_cnt(5),
      I1 => pi_rdval_cnt(3),
      I2 => pi_rdval_cnt(4),
      I3 => \pi_rdval_cnt[5]_i_4_n_0\,
      I4 => \pi_rdval_cnt[5]_i_5_n_0\,
      I5 => \pi_counter_read_val_reg[5]\,
      O => \pi_rdval_cnt[5]_i_2_n_0\
    );
\pi_rdval_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => pi_rdval_cnt(2),
      I1 => pi_rdval_cnt(5),
      I2 => pi_rdval_cnt(4),
      I3 => pi_rdval_cnt(3),
      I4 => pi_rdval_cnt(1),
      I5 => pi_rdval_cnt(0),
      O => \pi_rdval_cnt[5]_i_3_n_0\
    );
\pi_rdval_cnt[5]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => pi_rdval_cnt(1),
      I1 => pi_rdval_cnt(0),
      I2 => pi_rdval_cnt(2),
      O => \pi_rdval_cnt[5]_i_4_n_0\
    );
\pi_rdval_cnt[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dqs_po_dec_done_r1,
      I1 => dqs_po_dec_done_r2,
      O => \pi_rdval_cnt[5]_i_5_n_0\
    );
\pi_rdval_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[0]_i_1_n_0\,
      Q => pi_rdval_cnt(0),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\pi_rdval_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[1]_i_1_n_0\,
      Q => pi_rdval_cnt(1),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\pi_rdval_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[2]_i_1_n_0\,
      Q => pi_rdval_cnt(2),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\pi_rdval_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[3]_i_1_n_0\,
      Q => pi_rdval_cnt(3),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\pi_rdval_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[4]_i_1_n_0\,
      Q => pi_rdval_cnt(4),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\pi_rdval_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \pi_rdval_cnt[5]_i_1_n_0\,
      D => \pi_rdval_cnt[5]_i_2_n_0\,
      Q => pi_rdval_cnt(5),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
pi_stg2_f_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_f_incdec_timing,
      Q => rdlvl_pi_stg2_f_incdec,
      R => '0'
    );
pi_stg2_f_incdec_timing_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => cal1_dlyinc_cpt_r_reg_n_0,
      I2 => \^fine_dly_dec_done_r1_reg_0\,
      I3 => \rstdiv0_sync_r1_reg_rep__22\,
      O => pi_stg2_f_incdec_timing0
    );
pi_stg2_f_incdec_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_f_incdec_timing0,
      Q => pi_stg2_f_incdec_timing,
      R => '0'
    );
pi_stg2_load_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_load_timing,
      Q => pi_counter_load_en,
      R => '0'
    );
pi_stg2_load_timing_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => regl_dqs_cnt(3),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => \regl_rank_cnt[1]_i_3_n_0\,
      O => pi_stg2_load_timing_i_1_n_0
    );
pi_stg2_load_timing_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_load_timing_i_1_n_0,
      Q => pi_stg2_load_timing,
      R => '0'
    );
\pi_stg2_reg_l_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(0),
      Q => pi_counter_load_val(0),
      R => '0'
    );
\pi_stg2_reg_l_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(1),
      Q => pi_counter_load_val(1),
      R => '0'
    );
\pi_stg2_reg_l_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(2),
      Q => pi_counter_load_val(2),
      R => '0'
    );
\pi_stg2_reg_l_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(3),
      Q => pi_counter_load_val(3),
      R => '0'
    );
\pi_stg2_reg_l_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(4),
      Q => pi_counter_load_val(4),
      R => '0'
    );
\pi_stg2_reg_l_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_stg2_reg_l_timing(5),
      Q => pi_counter_load_val(5),
      R => '0'
    );
\pi_stg2_reg_l_timing[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\,
      O => \pi_stg2_reg_l_timing[0]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0]\,
      O => \pi_stg2_reg_l_timing[0]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\,
      O => \pi_stg2_reg_l_timing[1]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1]\,
      O => \pi_stg2_reg_l_timing[1]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\,
      O => \pi_stg2_reg_l_timing[2]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2]\,
      O => \pi_stg2_reg_l_timing[2]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\,
      O => \pi_stg2_reg_l_timing[3]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3]\,
      O => \pi_stg2_reg_l_timing[3]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\,
      O => \pi_stg2_reg_l_timing[4]_i_2_n_0\
    );
\pi_stg2_reg_l_timing[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4]\,
      O => \pi_stg2_reg_l_timing[4]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \regl_rank_cnt[1]_i_3_n_0\,
      I1 => regl_dqs_cnt(3),
      I2 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      O => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => p_0_in540_in,
      I1 => done_cnt(2),
      I2 => done_cnt(3),
      I3 => done_cnt(1),
      I4 => done_cnt(0),
      O => \pi_stg2_reg_l_timing[5]_i_3_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\,
      O => \pi_stg2_reg_l_timing[5]_i_4_n_0\
    );
\pi_stg2_reg_l_timing[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5]\,
      I1 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5]\,
      I2 => regl_dqs_cnt(1),
      I3 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5]\,
      I4 => regl_dqs_cnt(0),
      I5 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5]\,
      O => \pi_stg2_reg_l_timing[5]_i_5_n_0\
    );
\pi_stg2_reg_l_timing_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(0),
      Q => pi_stg2_reg_l_timing(0),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[0]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[0]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(0),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(1),
      Q => pi_stg2_reg_l_timing(1),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[1]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[1]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(1),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(2),
      Q => pi_stg2_reg_l_timing(2),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[2]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[2]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(2),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(3),
      Q => pi_stg2_reg_l_timing(3),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[3]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[3]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(3),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(4),
      Q => pi_stg2_reg_l_timing(4),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[4]_i_2_n_0\,
      I1 => \pi_stg2_reg_l_timing[4]_i_3_n_0\,
      O => rdlvl_dqs_tap_cnt_r(4),
      S => regl_dqs_cnt(2)
    );
\pi_stg2_reg_l_timing_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_dqs_tap_cnt_r(5),
      Q => pi_stg2_reg_l_timing(5),
      R => \pi_stg2_reg_l_timing[5]_i_1_n_0\
    );
\pi_stg2_reg_l_timing_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \pi_stg2_reg_l_timing[5]_i_4_n_0\,
      I1 => \pi_stg2_reg_l_timing[5]_i_5_n_0\,
      O => rdlvl_dqs_tap_cnt_r(5),
      S => regl_dqs_cnt(2)
    );
prbs_rdlvl_done_pulse_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => rdlvl_stg1_done_r1,
      O => prbs_rdlvl_done_pulse0
    );
\rd_mux_sel_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      Q => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      R => '0'
    );
\rd_mux_sel_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      Q => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      R => '0'
    );
\rd_mux_sel_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rd_mux_sel_r_reg_n_0_[2]\,
      R => '0'
    );
\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \cal1_state_r1_reg_n_0_[0]\,
      I1 => \cal1_state_r1_reg_n_0_[4]\,
      I2 => \cal1_state_r1_reg_n_0_[5]\,
      I3 => \cal1_state_r1_reg_n_0_[2]\,
      I4 => \cal1_state_r1_reg_n_0_[3]\,
      I5 => \cal1_state_r1_reg_n_0_[1]\,
      O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      O => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      O => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => \rd_mux_sel_r_reg_n_0_[2]\,
      I1 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rnk_cnt_r_reg_n_0_[0]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      O => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rd_mux_sel_r_reg_n_0_[2]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      O => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rd_mux_sel_r_reg_n_0_[2]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      O => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rd_mux_sel_r_reg_n_0_[2]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      O => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\,
      I1 => \rnk_cnt_r_reg_n_0_[1]\,
      I2 => \rnk_cnt_r_reg_n_0_[0]\,
      I3 => \rd_mux_sel_r_reg_n_0_[2]\,
      I4 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(0),
      I5 => \^rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1),
      O => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][1][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][2][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][3][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][4][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][5][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][6][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[0]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0]\,
      R => SR(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[1]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1]\,
      R => SR(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[2]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2]\,
      R => SR(0)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[3]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[4]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4]\,
      R => SR(1)
    );
\rdlvl_dqs_tap_cnt_r_reg[0][7][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0\,
      D => \tap_cnt_cpt_r_reg_n_0_[5]\,
      Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5]\,
      R => SR(1)
    );
rdlvl_last_byte_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABBBAAAAA888"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => rdlvl_rank_done_r,
      I2 => p_0_in540_in,
      I3 => cal1_state_r1,
      I4 => rdlvl_rank_done_r_i_2_n_0,
      I5 => \^rdlvl_last_byte_done\,
      O => rdlvl_last_byte_done_i_1_n_0
    );
rdlvl_last_byte_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_last_byte_done_i_1_n_0,
      Q => \^rdlvl_last_byte_done\,
      R => SR(1)
    );
rdlvl_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal1_prech_req_r_reg_n_0,
      Q => rdlvl_prech_req,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
rdlvl_rank_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C0C0C0FFC0C0C080"
    )
        port map (
      I0 => prech_done,
      I1 => \rnk_cnt_r[1]_i_2_n_0\,
      I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I3 => rdlvl_rank_done_r_i_2_n_0,
      I4 => p_0_in540_in,
      I5 => \^rdlvl_stg1_rank_done\,
      O => rdlvl_rank_done_r_i_1_n_0
    );
rdlvl_rank_done_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_27_in,
      I1 => \FSM_onehot_cal1_state_r_reg_n_0_[0]\,
      O => rdlvl_rank_done_r_i_2_n_0
    );
rdlvl_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_rank_done_r_i_1_n_0,
      Q => \^rdlvl_stg1_rank_done\,
      R => SR(1)
    );
rdlvl_stg1_done_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\,
      I1 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      O => rdlvl_stg1_done_i_1_n_0
    );
rdlvl_stg1_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_done_i_1_n_0,
      Q => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
rdlvl_stg1_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdlvl_stg1_start_reg,
      Q => rdlvl_stg1_start_r,
      R => '0'
    );
\regl_dqs_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000666666E6"
    )
        port map (
      I0 => regl_dqs_cnt(0),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => regl_rank_cnt0,
      I3 => regl_rank_cnt(0),
      I4 => regl_rank_cnt(1),
      I5 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_dqs_cnt[0]_i_1_n_0\
    );
\regl_dqs_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EE6A"
    )
        port map (
      I0 => regl_dqs_cnt(1),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => regl_dqs_cnt(0),
      I3 => \regl_dqs_cnt[2]_i_2_n_0\,
      I4 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_dqs_cnt[1]_i_1_n_0\
    );
\regl_dqs_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E6EAEAEA"
    )
        port map (
      I0 => regl_dqs_cnt(2),
      I1 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I2 => \regl_dqs_cnt[2]_i_2_n_0\,
      I3 => regl_dqs_cnt(1),
      I4 => regl_dqs_cnt(0),
      I5 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_dqs_cnt[2]_i_1_n_0\
    );
\regl_dqs_cnt[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => regl_rank_cnt0,
      I1 => regl_rank_cnt(0),
      I2 => regl_rank_cnt(1),
      O => \regl_dqs_cnt[2]_i_2_n_0\
    );
\regl_dqs_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444444444444444"
    )
        port map (
      I0 => \regl_rank_cnt[1]_i_3_n_0\,
      I1 => regl_dqs_cnt(3),
      I2 => regl_dqs_cnt(2),
      I3 => regl_dqs_cnt(0),
      I4 => regl_dqs_cnt(1),
      I5 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      O => \regl_dqs_cnt[3]_i_1_n_0\
    );
\regl_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => regl_dqs_cnt(0),
      Q => regl_dqs_cnt_r(0),
      R => '0'
    );
\regl_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => regl_dqs_cnt(1),
      Q => regl_dqs_cnt_r(1),
      R => '0'
    );
\regl_dqs_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => regl_dqs_cnt(2),
      Q => regl_dqs_cnt_r(2),
      R => '0'
    );
\regl_dqs_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => regl_dqs_cnt(3),
      Q => regl_dqs_cnt_r(3),
      R => '0'
    );
\regl_dqs_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt[0]_i_1_n_0\,
      Q => regl_dqs_cnt(0),
      R => '0'
    );
\regl_dqs_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt[1]_i_1_n_0\,
      Q => regl_dqs_cnt(1),
      R => '0'
    );
\regl_dqs_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt[2]_i_1_n_0\,
      Q => regl_dqs_cnt(2),
      R => '0'
    );
\regl_dqs_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_dqs_cnt[3]_i_1_n_0\,
      Q => regl_dqs_cnt(3),
      R => '0'
    );
\regl_rank_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0062"
    )
        port map (
      I0 => regl_rank_cnt(0),
      I1 => regl_rank_cnt0,
      I2 => regl_rank_cnt(1),
      I3 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_rank_cnt[0]_i_1_n_0\
    );
\regl_rank_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => regl_rank_cnt(1),
      I1 => regl_rank_cnt0,
      I2 => regl_rank_cnt(0),
      I3 => \regl_rank_cnt[1]_i_3_n_0\,
      O => \regl_rank_cnt[1]_i_1_n_0\
    );
\regl_rank_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \pi_stg2_reg_l_timing[5]_i_3_n_0\,
      I1 => regl_dqs_cnt(1),
      I2 => regl_dqs_cnt(0),
      I3 => regl_dqs_cnt(2),
      I4 => regl_dqs_cnt(3),
      O => regl_rank_cnt0
    );
\regl_rank_cnt[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => done_cnt(2),
      I2 => done_cnt(3),
      I3 => done_cnt(1),
      I4 => done_cnt(0),
      O => \regl_rank_cnt[1]_i_3_n_0\
    );
\regl_rank_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_rank_cnt[0]_i_1_n_0\,
      Q => regl_rank_cnt(0),
      R => '0'
    );
\regl_rank_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \regl_rank_cnt[1]_i_1_n_0\,
      Q => regl_rank_cnt(1),
      R => '0'
    );
\right_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => right_edge_taps_r(0)
    );
\right_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => right_edge_taps_r(1)
    );
\right_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => right_edge_taps_r(2)
    );
\right_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => right_edge_taps_r(3)
    );
\right_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => right_edge_taps_r(4)
    );
\right_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEAAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => store_sr_req_pulsed_r,
      O => \right_edge_taps_r[5]_i_1_n_0\
    );
\right_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => store_sr_req_pulsed_r,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      O => right_edge_taps_r(5)
    );
\right_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(0),
      Q => \right_edge_taps_r__0\(0),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\right_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(1),
      Q => \right_edge_taps_r__0\(1),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\right_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(2),
      Q => \right_edge_taps_r__0\(2),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\right_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(3),
      Q => \right_edge_taps_r__0\(3),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\right_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(4),
      Q => \right_edge_taps_r__0\(4),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\right_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \right_edge_taps_r[5]_i_1_n_0\,
      D => right_edge_taps_r(5),
      Q => \right_edge_taps_r__0\(5),
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\rnk_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3266666644444444"
    )
        port map (
      I0 => p_0_in540_in,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rnk_cnt_r[1]_i_2_n_0\,
      I4 => prech_done,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \rnk_cnt_r[0]_i_1__0_n_0\
    );
\rnk_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3C78787850505050"
    )
        port map (
      I0 => p_0_in540_in,
      I1 => \rnk_cnt_r_reg_n_0_[0]\,
      I2 => \rnk_cnt_r_reg_n_0_[1]\,
      I3 => \rnk_cnt_r[1]_i_2_n_0\,
      I4 => prech_done,
      I5 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      O => \rnk_cnt_r[1]_i_1__0_n_0\
    );
\rnk_cnt_r[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\,
      I1 => \cal1_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \cal1_cnt_cpt_r_reg_n_0_[2]\,
      O => \rnk_cnt_r[1]_i_2_n_0\
    );
\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[0]_i_1__0_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rnk_cnt_r[1]_i_1__0_n_0\,
      Q => \rnk_cnt_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
samp_cnt_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAE0000"
    )
        port map (
      I0 => samp_cnt_done_r_reg_n_0,
      I1 => samp_cnt_done_r_i_2_n_0,
      I2 => samp_cnt_done_r_i_3_n_0,
      I3 => samp_cnt_done_r_i_4_n_0,
      I4 => \^samp_edge_cnt0_en_r\,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => samp_cnt_done_r_i_1_n_0
    );
samp_cnt_done_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(11),
      I1 => samp_edge_cnt1_r_reg(7),
      I2 => samp_edge_cnt1_r_reg(0),
      I3 => samp_edge_cnt1_r_reg(6),
      O => samp_cnt_done_r_i_2_n_0
    );
samp_cnt_done_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(1),
      I1 => samp_edge_cnt1_r_reg(10),
      I2 => samp_edge_cnt1_r_reg(8),
      I3 => samp_edge_cnt1_r_reg(3),
      O => samp_cnt_done_r_i_3_n_0
    );
samp_cnt_done_r_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(4),
      I1 => samp_edge_cnt1_r_reg(9),
      I2 => samp_edge_cnt1_r_reg(2),
      I3 => samp_edge_cnt1_r_reg(5),
      O => samp_cnt_done_r_i_4_n_0
    );
samp_cnt_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => samp_cnt_done_r_i_1_n_0,
      Q => samp_cnt_done_r_reg_n_0,
      R => '0'
    );
samp_edge_cnt0_en_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_2_in33_in,
      I1 => p_34_in,
      I2 => store_sr_req_pulsed_r,
      I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\,
      O => pb_detect_edge
    );
samp_edge_cnt0_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pb_detect_edge,
      Q => \^samp_edge_cnt0_en_r\,
      R => '0'
    );
\samp_edge_cnt0_r[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(0),
      O => \samp_edge_cnt0_r[0]_i_3_n_0\
    );
\samp_edge_cnt0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_7\,
      Q => samp_edge_cnt0_r_reg(0),
      R => clear
    );
\samp_edge_cnt0_r_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_0\,
      CO(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_7\,
      S(3 downto 1) => samp_edge_cnt0_r_reg(3 downto 1),
      S(0) => \samp_edge_cnt0_r[0]_i_3_n_0\
    );
\samp_edge_cnt0_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_5\,
      Q => samp_edge_cnt0_r_reg(10),
      R => clear
    );
\samp_edge_cnt0_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_4\,
      Q => samp_edge_cnt0_r_reg(11),
      R => clear
    );
\samp_edge_cnt0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_6\,
      Q => samp_edge_cnt0_r_reg(1),
      R => clear
    );
\samp_edge_cnt0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_5\,
      Q => samp_edge_cnt0_r_reg(2),
      R => clear
    );
\samp_edge_cnt0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[0]_i_2_n_4\,
      Q => samp_edge_cnt0_r_reg(3),
      R => clear
    );
\samp_edge_cnt0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_7\,
      Q => samp_edge_cnt0_r_reg(4),
      R => clear
    );
\samp_edge_cnt0_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt0_r_reg[0]_i_2_n_0\,
      CO(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_0\,
      CO(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt0_r_reg(7 downto 4)
    );
\samp_edge_cnt0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_6\,
      Q => samp_edge_cnt0_r_reg(5),
      R => clear
    );
\samp_edge_cnt0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_5\,
      Q => samp_edge_cnt0_r_reg(6),
      R => clear
    );
\samp_edge_cnt0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[4]_i_1_n_4\,
      Q => samp_edge_cnt0_r_reg(7),
      R => clear
    );
\samp_edge_cnt0_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_7\,
      Q => samp_edge_cnt0_r_reg(8),
      R => clear
    );
\samp_edge_cnt0_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt0_r_reg[4]_i_1_n_0\,
      CO(3) => \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_1\,
      CO(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_2\,
      CO(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt0_r_reg[8]_i_1_n_4\,
      O(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_5\,
      O(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_6\,
      O(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt0_r_reg(11 downto 8)
    );
\samp_edge_cnt0_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sr_valid_r2,
      D => \samp_edge_cnt0_r_reg[8]_i_1_n_6\,
      Q => samp_edge_cnt0_r_reg(9),
      R => clear
    );
samp_edge_cnt1_en_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => samp_edge_cnt1_en_r_i_2_n_0,
      I1 => samp_edge_cnt1_en_r_i_3_n_0,
      I2 => samp_edge_cnt0_r_reg(3),
      I3 => sr_valid_r2,
      I4 => samp_edge_cnt0_r_reg(4),
      O => samp_edge_cnt1_en_r0
    );
samp_edge_cnt1_en_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(10),
      I1 => samp_edge_cnt0_r_reg(5),
      I2 => samp_edge_cnt0_r_reg(9),
      I3 => samp_edge_cnt0_r_reg(2),
      I4 => samp_edge_cnt0_r_reg(11),
      I5 => samp_edge_cnt0_r_reg(6),
      O => samp_edge_cnt1_en_r_i_2_n_0
    );
samp_edge_cnt1_en_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => samp_edge_cnt0_r_reg(8),
      I1 => samp_edge_cnt0_r_reg(1),
      I2 => samp_edge_cnt0_r_reg(0),
      I3 => samp_edge_cnt0_r_reg(7),
      O => samp_edge_cnt1_en_r_i_3_n_0
    );
samp_edge_cnt1_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => samp_edge_cnt1_en_r0,
      Q => samp_edge_cnt1_en_r,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\samp_edge_cnt1_r[0]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => samp_edge_cnt1_r_reg(0),
      O => \samp_edge_cnt1_r[0]_i_2_n_0\
    );
\samp_edge_cnt1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(0),
      R => clear
    );
\samp_edge_cnt1_r_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_0\,
      CO(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_7\,
      S(3 downto 1) => samp_edge_cnt1_r_reg(3 downto 1),
      S(0) => \samp_edge_cnt1_r[0]_i_2_n_0\
    );
\samp_edge_cnt1_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(10),
      R => clear
    );
\samp_edge_cnt1_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(11),
      R => clear
    );
\samp_edge_cnt1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(1),
      R => clear
    );
\samp_edge_cnt1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(2),
      R => clear
    );
\samp_edge_cnt1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[0]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(3),
      R => clear
    );
\samp_edge_cnt1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(4),
      R => clear
    );
\samp_edge_cnt1_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt1_r_reg[0]_i_1_n_0\,
      CO(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_0\,
      CO(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt1_r_reg(7 downto 4)
    );
\samp_edge_cnt1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(5),
      R => clear
    );
\samp_edge_cnt1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_5\,
      Q => samp_edge_cnt1_r_reg(6),
      R => clear
    );
\samp_edge_cnt1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[4]_i_1_n_4\,
      Q => samp_edge_cnt1_r_reg(7),
      R => clear
    );
\samp_edge_cnt1_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_7\,
      Q => samp_edge_cnt1_r_reg(8),
      R => clear
    );
\samp_edge_cnt1_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \samp_edge_cnt1_r_reg[4]_i_1_n_0\,
      CO(3) => \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_1\,
      CO(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_2\,
      CO(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \samp_edge_cnt1_r_reg[8]_i_1_n_4\,
      O(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_5\,
      O(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_6\,
      O(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_7\,
      S(3 downto 0) => samp_edge_cnt1_r_reg(11 downto 8)
    );
\samp_edge_cnt1_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => samp_edge_cnt1_en_r,
      D => \samp_edge_cnt1_r_reg[8]_i_1_n_6\,
      Q => samp_edge_cnt1_r_reg(9),
      R => clear
    );
\second_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \second_edge_taps_r[0]_i_1_n_0\
    );
\second_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \second_edge_taps_r[1]_i_1_n_0\
    );
\second_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \second_edge_taps_r[2]_i_1_n_0\
    );
\second_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \second_edge_taps_r[3]_i_1_n_0\
    );
\second_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \second_edge_taps_r[4]_i_1_n_0\
    );
\second_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => store_sr_req_pulsed_r,
      O => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\,
      I1 => \first_edge_taps_r[5]_i_3_n_0\,
      I2 => found_stable_eye_last_r,
      I3 => found_first_edge_r_reg_n_0,
      I4 => store_sr_req_pulsed_r,
      O => \second_edge_taps_r[5]_i_2_n_0\
    );
\second_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      O => \second_edge_taps_r[5]_i_3_n_0\
    );
\second_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[0]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[0]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[1]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[1]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[2]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[2]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[3]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[3]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[4]_i_1_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[4]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
\second_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \second_edge_taps_r[5]_i_2_n_0\,
      D => \second_edge_taps_r[5]_i_3_n_0\,
      Q => \second_edge_taps_r_reg_n_0_[5]\,
      R => \second_edge_taps_r[5]_i_1_n_0\
    );
sr_valid_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sr_valid_r_reg_n_0,
      Q => sr_valid_r1,
      R => '0'
    );
sr_valid_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sr_valid_r1,
      Q => sr_valid_r2,
      R => '0'
    );
sr_valid_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => E(0),
      I1 => rdlvl_stg1_start_reg,
      I2 => \cnt_shift_r_reg__0\(2),
      I3 => \cnt_shift_r_reg__0\(3),
      I4 => \cnt_shift_r_reg__0\(1),
      I5 => \cnt_shift_r_reg__0\(0),
      O => sr_valid_r_i_1_n_0
    );
sr_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sr_valid_r_i_1_n_0,
      Q => sr_valid_r_reg_n_0,
      R => SR(0)
    );
\stg1_wr_rd_cnt[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I2 => stg1_wr_done,
      O => \stg1_wr_rd_cnt_reg[3]\
    );
store_sr_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => store_sr_req_r_reg_n_0,
      I1 => sr_valid_r_reg_n_0,
      I2 => store_sr_r_reg_n_0,
      O => store_sr_r_i_1_n_0
    );
store_sr_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => store_sr_r_i_1_n_0,
      Q => store_sr_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
store_sr_req_pulsed_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => store_sr_req_pulsed_r,
      Q => \store_sr_req_pulsed_r__0\,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
store_sr_req_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"444F4444"
    )
        port map (
      I0 => \store_sr_req_pulsed_r__0\,
      I1 => store_sr_req_pulsed_r,
      I2 => cal1_wait_r,
      I3 => \pi_counter_read_val_reg[2]_0\,
      I4 => p_27_in,
      O => store_sr_req_r
    );
store_sr_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => store_sr_req_r,
      Q => store_sr_req_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__2\(1)
    );
\tap_cnt_cpt_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \tap_cnt_cpt_r[1]_i_1_n_0\
    );
\tap_cnt_cpt_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6CC9"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      O => \p_0_in__0\(2)
    );
\tap_cnt_cpt_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6CCCCCC9"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      O => \p_0_in__0\(3)
    );
\tap_cnt_cpt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCC9"
    )
        port map (
      I0 => cal1_dlyinc_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I5 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      O => \p_0_in__0\(4)
    );
\tap_cnt_cpt_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => cal1_dlyce_cpt_r_reg_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \tap_cnt_cpt_r[5]_i_4_n_0\,
      I3 => cal1_dlyinc_cpt_r_reg_n_0,
      O => tap_cnt_cpt_r
    );
\tap_cnt_cpt_r[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I1 => \tap_cnt_cpt_r[5]_i_5_n_0\,
      I2 => cal1_dlyinc_cpt_r_reg_n_0,
      I3 => \second_edge_taps_r[5]_i_3_n_0\,
      O => \p_0_in__0\(5)
    );
\tap_cnt_cpt_r[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \tap_cnt_cpt_r[5]_i_4_n_0\
    );
\tap_cnt_cpt_r[5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \tap_cnt_cpt_r_reg_n_0_[3]\,
      I1 => \tap_cnt_cpt_r_reg_n_0_[1]\,
      I2 => \tap_cnt_cpt_r_reg_n_0_[0]\,
      I3 => \tap_cnt_cpt_r_reg_n_0_[2]\,
      I4 => \tap_cnt_cpt_r_reg_n_0_[4]\,
      O => \tap_cnt_cpt_r[5]_i_5_n_0\
    );
\tap_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \second_edge_taps_r[0]_i_1_n_0\,
      Q => \tap_cnt_cpt_r_reg_n_0_[0]\,
      R => new_cnt_cpt_r_reg_0(0)
    );
\tap_cnt_cpt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \tap_cnt_cpt_r[1]_i_1_n_0\,
      Q => \tap_cnt_cpt_r_reg_n_0_[1]\,
      R => new_cnt_cpt_r_reg_0(0)
    );
\tap_cnt_cpt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(2),
      Q => \tap_cnt_cpt_r_reg_n_0_[2]\,
      R => new_cnt_cpt_r_reg_0(0)
    );
\tap_cnt_cpt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(3),
      Q => \tap_cnt_cpt_r_reg_n_0_[3]\,
      R => new_cnt_cpt_r_reg_0(0)
    );
\tap_cnt_cpt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(4),
      Q => \tap_cnt_cpt_r_reg_n_0_[4]\,
      R => new_cnt_cpt_r_reg_0(0)
    );
\tap_cnt_cpt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tap_cnt_cpt_r,
      D => \p_0_in__0\(5),
      Q => \tap_cnt_cpt_r_reg_n_0_[5]\,
      R => new_cnt_cpt_r_reg_0(0)
    );
tap_limit_cpt_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AA80"
    )
        port map (
      I0 => tap_limit_cpt_r_i_2_n_0,
      I1 => \tap_cnt_cpt_r_reg_n_0_[5]\,
      I2 => \tap_cnt_cpt_r[5]_i_5_n_0\,
      I3 => tap_limit_cpt_r,
      I4 => \rstdiv0_sync_r1_reg_rep__22\,
      I5 => \^idelay_tap_limit_r_reg_0\,
      O => tap_limit_cpt_r_i_1_n_0
    );
tap_limit_cpt_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \cal1_state_r1_reg_n_0_[0]\,
      I1 => \cal1_state_r1_reg_n_0_[4]\,
      I2 => \cal1_state_r1_reg_n_0_[5]\,
      I3 => \cal1_state_r1_reg_n_0_[2]\,
      I4 => \cal1_state_r1_reg_n_0_[3]\,
      I5 => \cal1_state_r1_reg_n_0_[1]\,
      O => tap_limit_cpt_r_i_2_n_0
    );
tap_limit_cpt_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tap_limit_cpt_r_i_1_n_0,
      Q => tap_limit_cpt_r,
      R => '0'
    );
\wait_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_cnt_r_reg(0),
      O => \wait_cnt_r0__0\(0)
    );
\wait_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_cnt_r_reg(1),
      I1 => wait_cnt_r_reg(0),
      O => \wait_cnt_r[1]_i_1__0_n_0\
    );
\wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_cnt_r_reg(2),
      I1 => wait_cnt_r_reg(0),
      I2 => wait_cnt_r_reg(1),
      O => \wait_cnt_r0__0\(2)
    );
\wait_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => dqs_po_dec_done_r2,
      I1 => wait_cnt_r_reg(3),
      I2 => wait_cnt_r_reg(0),
      I3 => wait_cnt_r_reg(1),
      I4 => wait_cnt_r_reg(2),
      O => wait_cnt_r0
    );
\wait_cnt_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_cnt_r_reg(3),
      I1 => wait_cnt_r_reg(2),
      I2 => wait_cnt_r_reg(1),
      I3 => wait_cnt_r_reg(0),
      O => \wait_cnt_r0__0\(3)
    );
\wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(0),
      Q => wait_cnt_r_reg(0),
      R => pi_cnt_dec_reg_0(0)
    );
\wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r[1]_i_1__0_n_0\,
      Q => wait_cnt_r_reg(1),
      R => pi_cnt_dec_reg_0(0)
    );
\wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(2),
      Q => wait_cnt_r_reg(2),
      R => pi_cnt_dec_reg_0(0)
    );
\wait_cnt_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => wait_cnt_r0,
      D => \wait_cnt_r0__0\(3),
      Q => wait_cnt_r_reg(3),
      S => pi_cnt_dec_reg_0(0)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[445]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      O => D(1)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[445]_rep_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep\
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[505]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => first_wrcal_pat_r,
      O => D(2)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[511]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => wrcal_done_reg,
      O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511]\(0)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[511]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => first_wrcal_pat_r,
      O => D(3)
    );
\wrdq_div2_4to1_rdlvl_first.phy_wrdata[61]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\,
      I1 => first_rdlvl_pat_r,
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_tempmon is
  port (
    tempmon_pi_f_inc : out STD_LOGIC;
    tempmon_pi_f_dec : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    tempmon_pi_f_en_r0 : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg\ : out STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \calib_sel_reg[0]\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tempmon_sample_en : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__15\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__17\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_done_reg : in STD_LOGIC;
    wrcal_done_reg : in STD_LOGIC;
    wr_level_done_reg : in STD_LOGIC;
    ck_addr_cmd_delay_done : in STD_LOGIC;
    fine_adjust_done_r_reg : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : in STD_LOGIC;
    ctl_lane_sel : in STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]\ : in STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ : in STD_LOGIC;
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC;
    \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    calib_complete : in STD_LOGIC;
    \device_temp_r_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_tempmon : entity is "mig_7series_v2_3_ddr_phy_tempmon";
end mig_7series_0_mig_7series_v2_3_ddr_phy_tempmon;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_tempmon is
  signal \^calib_sel_reg[0]\ : STD_LOGIC;
  signal device_temp_101 : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal device_temp_init : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \device_temp_init[11]_i_2_n_0\ : STD_LOGIC;
  signal \device_temp_init[11]_i_3_n_0\ : STD_LOGIC;
  signal four_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \four_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal four_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \four_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal four_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[4]_i_5_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal four_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \four_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \four_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal neutral_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal neutral_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal neutral_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \neutral_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \neutral_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal neutral_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \neutral_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \neutral_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal one_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal one_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal one_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal one_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \one_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal one_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal one_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal one_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal one_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \one_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \one_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal pi_f_dec_i_2_n_0 : STD_LOGIC;
  signal pi_f_dec_nxt : STD_LOGIC;
  signal pi_f_inc_i_10_n_0 : STD_LOGIC;
  signal pi_f_inc_i_2_n_0 : STD_LOGIC;
  signal pi_f_inc_i_3_n_0 : STD_LOGIC;
  signal pi_f_inc_i_5_n_0 : STD_LOGIC;
  signal pi_f_inc_i_6_n_0 : STD_LOGIC;
  signal pi_f_inc_i_7_n_0 : STD_LOGIC;
  signal pi_f_inc_i_8_n_0 : STD_LOGIC;
  signal pi_f_inc_i_9_n_0 : STD_LOGIC;
  signal pi_f_inc_nxt : STD_LOGIC;
  signal temp_cmp_four_dec_min_101 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_four_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_four_inc_max_101 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_four_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_max_101 : STD_LOGIC;
  signal temp_cmp_neutral_max_102 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_neutral_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_min_101 : STD_LOGIC;
  signal temp_cmp_neutral_min_102 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_neutral_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_max_101 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_min_101 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_max_101 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_min_101 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_one_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_max_101 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_min_101 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_max_101 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_min_101 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_three_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_max_101 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_dec_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_min_101 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_dec_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_max_101 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_inc_max_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_min_101 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_10_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_11_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_12_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_13_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_14_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_3_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_4_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_5_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_6_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_7_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_8_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_i_9_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_1_n_3 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_0 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_1 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_2 : STD_LOGIC;
  signal temp_cmp_two_inc_min_102_reg_i_2_n_3 : STD_LOGIC;
  signal temp_gte_three_dec_max : STD_LOGIC;
  signal tempmon_init_complete : STD_LOGIC;
  signal \^tempmon_pi_f_dec\ : STD_LOGIC;
  signal \^tempmon_pi_f_inc\ : STD_LOGIC;
  signal tempmon_sample_en_101 : STD_LOGIC;
  signal tempmon_sample_en_102 : STD_LOGIC;
  signal tempmon_state : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \tempmon_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_10_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_11_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_12_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_13_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_14_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_15_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_16_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_17_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_3_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_4_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_5_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_6_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_7_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_8_n_0\ : STD_LOGIC;
  signal \tempmon_state[10]_i_9_n_0\ : STD_LOGIC;
  signal \tempmon_state[1]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[2]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[3]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[4]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[5]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[6]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[6]_i_2_n_0\ : STD_LOGIC;
  signal \tempmon_state[7]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[8]_i_1_n_0\ : STD_LOGIC;
  signal \tempmon_state[9]_i_1_n_0\ : STD_LOGIC;
  signal tempmon_state_init : STD_LOGIC;
  signal tempmon_state_nxt : STD_LOGIC;
  signal three_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \three_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[10]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[11]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[1]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[2]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[3]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[4]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[6]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[7]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[11]_i_2_n_7\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_4\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[4]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \three_dec_max_limit_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal three_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \three_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal three_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \three_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal three_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \three_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit[8]_i_4_n_0\ : STD_LOGIC;
  signal three_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \three_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal three_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \three_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal three_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \three_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \three_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal two_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \two_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal two_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \two_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal two_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal two_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \two_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal two_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal \two_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[1]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal two_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal two_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC;
  signal two_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \two_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \two_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal \update_temp_101__0\ : STD_LOGIC;
  signal update_temp_102 : STD_LOGIC;
  signal \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.calib_in_common_i_5\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of pi_f_inc_i_10 : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of pi_f_inc_i_3 : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of pi_f_inc_i_4 : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of pi_f_inc_i_5 : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of pi_f_inc_i_8 : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of pi_f_inc_i_9 : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of tempmon_pi_f_en_r_i_1 : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \tempmon_state[0]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_14\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_15\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_3\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_5\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \tempmon_state[10]_i_9\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \tempmon_state[1]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \tempmon_state[2]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \tempmon_state[3]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \tempmon_state[6]_i_2\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \three_dec_max_limit[0]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \three_dec_max_limit[10]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \three_dec_max_limit[11]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \three_dec_max_limit[1]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \three_dec_max_limit[2]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \three_dec_max_limit[3]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \three_dec_max_limit[4]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \three_dec_max_limit[5]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \three_dec_max_limit[6]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \three_dec_max_limit[7]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \three_dec_max_limit[8]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \three_dec_max_limit[9]_i_1\ : label is "soft_lutpair22";
begin
  \calib_sel_reg[0]\ <= \^calib_sel_reg[0]\;
  tempmon_pi_f_dec <= \^tempmon_pi_f_dec\;
  tempmon_pi_f_inc <= \^tempmon_pi_f_inc\;
\calib_sel[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"020202A2"
    )
        port map (
      I0 => \^calib_sel_reg[0]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\,
      I2 => ctl_lane_sel,
      I3 => \gen_byte_sel_div2.ctl_lane_sel_reg[2]\,
      I4 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]\,
      O => D(0)
    );
\calib_sel[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0202020202A2A202"
    )
        port map (
      I0 => \^calib_sel_reg[0]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\,
      I2 => ctl_lane_sel,
      I3 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]\,
      I4 => \gen_byte_sel_div2.ctl_lane_sel_reg[1]\,
      I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[2]\,
      O => D(1)
    );
\calib_sel[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000200"
    )
        port map (
      I0 => \^calib_sel_reg[0]\,
      I1 => Q(0),
      I2 => Q(1),
      I3 => Q(2),
      I4 => Q(3),
      I5 => ctl_lane_sel,
      O => D(2)
    );
\calib_sel[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000E00000"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => Q(2),
      I3 => Q(3),
      I4 => \^calib_sel_reg[0]\,
      I5 => ctl_lane_sel,
      O => D(3)
    );
\calib_sel[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5455"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^tempmon_pi_f_inc\,
      I2 => \^tempmon_pi_f_dec\,
      I3 => calib_complete,
      O => \^calib_sel_reg[0]\
    );
\device_temp_101_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(0),
      Q => device_temp_101(0),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(10),
      Q => device_temp_101(10),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(11),
      Q => device_temp_101(11),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(1),
      Q => device_temp_101(1),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(2),
      Q => device_temp_101(2),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(3),
      Q => device_temp_101(3),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(4),
      Q => device_temp_101(4),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(5),
      Q => device_temp_101(5),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(6),
      Q => device_temp_101(6),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(7),
      Q => device_temp_101(7),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(8),
      Q => device_temp_101(8),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_101_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \device_temp_r_reg[11]\(9),
      Q => device_temp_101(9),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \device_temp_init[11]_i_2_n_0\,
      I1 => \device_temp_init[11]_i_3_n_0\,
      I2 => tempmon_state(0),
      I3 => tempmon_state(1),
      I4 => tempmon_state(2),
      O => tempmon_state_init
    );
\device_temp_init[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => tempmon_state(6),
      I1 => tempmon_state(5),
      I2 => tempmon_state(4),
      I3 => tempmon_state(3),
      O => \device_temp_init[11]_i_2_n_0\
    );
\device_temp_init[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => tempmon_state(10),
      I1 => tempmon_state(9),
      I2 => tempmon_state(8),
      I3 => tempmon_state(7),
      O => \device_temp_init[11]_i_3_n_0\
    );
\device_temp_init_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(0),
      Q => device_temp_init(0),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(10),
      Q => device_temp_init(10),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(11),
      Q => device_temp_init(11),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(1),
      Q => device_temp_init(1),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(2),
      Q => device_temp_init(2),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(3),
      Q => device_temp_init(3),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(4),
      Q => device_temp_init(4),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(5),
      Q => device_temp_init(5),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(6),
      Q => device_temp_init(6),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(7),
      Q => device_temp_init(7),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(8),
      Q => device_temp_init(8),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\device_temp_init_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => device_temp_101(9),
      Q => device_temp_init(9),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\four_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(11),
      O => \four_dec_min_limit[11]_i_2_n_0\
    );
\four_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(10),
      O => \four_dec_min_limit[11]_i_3_n_0\
    );
\four_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(5),
      O => \four_dec_min_limit[5]_i_2_n_0\
    );
\four_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(4),
      O => \four_dec_min_limit[5]_i_3_n_0\
    );
\four_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(3),
      O => \four_dec_min_limit[5]_i_4_n_0\
    );
\four_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(9),
      O => \four_dec_min_limit[9]_i_2_n_0\
    );
\four_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(8),
      O => \four_dec_min_limit[9]_i_3_n_0\
    );
\four_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(7),
      O => \four_dec_min_limit[9]_i_4_n_0\
    );
\four_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_dec_max_limit(6),
      O => \four_dec_min_limit[9]_i_5_n_0\
    );
\four_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_max_limit(0),
      Q => four_dec_min_limit(0),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(10),
      Q => four_dec_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(11),
      Q => four_dec_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \four_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => three_dec_max_limit(10),
      O(3 downto 2) => \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => four_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \four_dec_min_limit[11]_i_2_n_0\,
      S(0) => \four_dec_min_limit[11]_i_3_n_0\
    );
\four_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_max_limit(1),
      Q => four_dec_min_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(2),
      Q => four_dec_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(3),
      Q => four_dec_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(4),
      Q => four_dec_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(5),
      Q => four_dec_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \four_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \four_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \four_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \four_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => three_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => four_dec_min_limit_nxt(5 downto 2),
      S(3) => \four_dec_min_limit[5]_i_2_n_0\,
      S(2) => \four_dec_min_limit[5]_i_3_n_0\,
      S(1) => \four_dec_min_limit[5]_i_4_n_0\,
      S(0) => three_dec_max_limit(2)
    );
\four_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(6),
      Q => four_dec_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(7),
      Q => four_dec_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(8),
      Q => four_dec_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_dec_min_limit_nxt(9),
      Q => four_dec_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\four_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \four_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \four_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \four_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \four_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => three_dec_max_limit(9 downto 6),
      O(3 downto 0) => four_dec_min_limit_nxt(9 downto 6),
      S(3) => \four_dec_min_limit[9]_i_2_n_0\,
      S(2) => \four_dec_min_limit[9]_i_3_n_0\,
      S(1) => \four_dec_min_limit[9]_i_4_n_0\,
      S(0) => \four_dec_min_limit[9]_i_5_n_0\
    );
\four_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \four_inc_max_limit[11]_i_2_n_0\
    );
\four_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \four_inc_max_limit[11]_i_3_n_0\
    );
\four_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \four_inc_max_limit[4]_i_2_n_0\
    );
\four_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \four_inc_max_limit[4]_i_3_n_0\
    );
\four_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \four_inc_max_limit[4]_i_4_n_0\
    );
\four_inc_max_limit[4]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \four_inc_max_limit[4]_i_5_n_0\
    );
\four_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \four_inc_max_limit[8]_i_2_n_0\
    );
\four_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \four_inc_max_limit[8]_i_3_n_0\
    );
\four_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(10),
      Q => four_inc_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(11),
      Q => four_inc_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \four_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(10),
      DI(0) => '0',
      O(3) => \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => four_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \four_inc_max_limit[11]_i_2_n_0\,
      S(1) => \four_inc_max_limit[11]_i_3_n_0\,
      S(0) => device_temp_init(9)
    );
\four_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(2),
      Q => four_inc_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(3),
      Q => four_inc_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(4),
      Q => four_inc_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \four_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \four_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \four_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 0) => device_temp_init(4 downto 1),
      O(3 downto 1) => four_inc_max_limit_nxt(4 downto 2),
      O(0) => two_dec_max_limit_nxt(1),
      S(3) => \four_inc_max_limit[4]_i_2_n_0\,
      S(2) => \four_inc_max_limit[4]_i_3_n_0\,
      S(1) => \four_inc_max_limit[4]_i_4_n_0\,
      S(0) => \four_inc_max_limit[4]_i_5_n_0\
    );
\four_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(5),
      Q => four_inc_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(6),
      Q => four_inc_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(7),
      Q => four_inc_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(8),
      Q => four_inc_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\four_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \four_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \four_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \four_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \four_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \four_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => device_temp_init(7),
      DI(1) => '0',
      DI(0) => device_temp_init(5),
      O(3 downto 0) => four_inc_max_limit_nxt(8 downto 5),
      S(3) => device_temp_init(8),
      S(2) => \four_inc_max_limit[8]_i_2_n_0\,
      S(1) => device_temp_init(6),
      S(0) => \four_inc_max_limit[8]_i_3_n_0\
    );
\four_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => four_inc_max_limit_nxt(9),
      Q => four_inc_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7F00000000"
    )
        port map (
      I0 => rdlvl_stg1_done_reg,
      I1 => wrcal_done_reg,
      I2 => wr_level_done_reg,
      I3 => \^tempmon_pi_f_inc\,
      I4 => \^tempmon_pi_f_dec\,
      I5 => ck_addr_cmd_delay_done,
      O => E(0)
    );
\gen_byte_sel_div2.calib_in_common_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => fine_adjust_done_r_reg,
      I1 => rdlvl_stg1_done_reg,
      I2 => wrcal_done_reg,
      I3 => wr_level_done_reg,
      I4 => \^tempmon_pi_f_inc\,
      I5 => \^tempmon_pi_f_dec\,
      O => \gen_byte_sel_div2.calib_in_common_reg_0\
    );
\gen_byte_sel_div2.calib_in_common_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFFFFFF"
    )
        port map (
      I0 => \^tempmon_pi_f_dec\,
      I1 => \^tempmon_pi_f_inc\,
      I2 => wr_level_done_reg,
      I3 => wrcal_done_reg,
      I4 => rdlvl_stg1_done_reg,
      O => \gen_byte_sel_div2.calib_in_common_reg\
    );
\neutral_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \neutral_max_limit[4]_i_2_n_0\
    );
\neutral_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \neutral_max_limit[4]_i_3_n_0\
    );
\neutral_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \neutral_max_limit[4]_i_4_n_0\
    );
\neutral_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \neutral_max_limit[8]_i_2_n_0\
    );
\neutral_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \neutral_max_limit[8]_i_3_n_0\
    );
\neutral_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(10),
      Q => neutral_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(11),
      Q => neutral_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \neutral_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => neutral_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 0) => device_temp_init(11 downto 9)
    );
\neutral_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(2),
      Q => neutral_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(3),
      Q => neutral_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(4),
      Q => neutral_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \neutral_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \neutral_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \neutral_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => device_temp_init(4),
      DI(2) => '0',
      DI(1 downto 0) => device_temp_init(2 downto 1),
      O(3 downto 1) => neutral_max_limit_nxt(4 downto 2),
      O(0) => \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \neutral_max_limit[4]_i_2_n_0\,
      S(2) => device_temp_init(3),
      S(1) => \neutral_max_limit[4]_i_3_n_0\,
      S(0) => \neutral_max_limit[4]_i_4_n_0\
    );
\neutral_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(5),
      Q => neutral_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(6),
      Q => neutral_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(7),
      Q => neutral_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(8),
      Q => neutral_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \neutral_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \neutral_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \neutral_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \neutral_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(6 downto 5),
      O(3 downto 0) => neutral_max_limit_nxt(8 downto 5),
      S(3 downto 2) => device_temp_init(8 downto 7),
      S(1) => \neutral_max_limit[8]_i_2_n_0\,
      S(0) => \neutral_max_limit[8]_i_3_n_0\
    );
\neutral_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_max_limit_nxt(9),
      Q => neutral_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\neutral_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(11),
      O => \neutral_min_limit[11]_i_2_n_0\
    );
\neutral_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(10),
      O => \neutral_min_limit[11]_i_3_n_0\
    );
\neutral_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(5),
      O => \neutral_min_limit[5]_i_2_n_0\
    );
\neutral_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(4),
      O => \neutral_min_limit[5]_i_3_n_0\
    );
\neutral_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(3),
      O => \neutral_min_limit[5]_i_4_n_0\
    );
\neutral_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(9),
      O => \neutral_min_limit[9]_i_2_n_0\
    );
\neutral_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(8),
      O => \neutral_min_limit[9]_i_3_n_0\
    );
\neutral_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(7),
      O => \neutral_min_limit[9]_i_4_n_0\
    );
\neutral_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_inc_max_limit(6),
      O => \neutral_min_limit[9]_i_5_n_0\
    );
\neutral_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(10),
      Q => neutral_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(11),
      Q => neutral_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \neutral_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => one_inc_max_limit(10),
      O(3 downto 2) => \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => neutral_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \neutral_min_limit[11]_i_2_n_0\,
      S(0) => \neutral_min_limit[11]_i_3_n_0\
    );
\neutral_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit(1),
      Q => neutral_min_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(2),
      Q => neutral_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(3),
      Q => neutral_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(4),
      Q => neutral_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(5),
      Q => neutral_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \neutral_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \neutral_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \neutral_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \neutral_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => one_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => neutral_min_limit_nxt(5 downto 2),
      S(3) => \neutral_min_limit[5]_i_2_n_0\,
      S(2) => \neutral_min_limit[5]_i_3_n_0\,
      S(1) => \neutral_min_limit[5]_i_4_n_0\,
      S(0) => one_inc_max_limit(2)
    );
\neutral_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(6),
      Q => neutral_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(7),
      Q => neutral_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(8),
      Q => neutral_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => neutral_min_limit_nxt(9),
      Q => neutral_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\neutral_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \neutral_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \neutral_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \neutral_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \neutral_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \neutral_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => one_inc_max_limit(9 downto 6),
      O(3 downto 0) => neutral_min_limit_nxt(9 downto 6),
      S(3) => \neutral_min_limit[9]_i_2_n_0\,
      S(2) => \neutral_min_limit[9]_i_3_n_0\,
      S(1) => \neutral_min_limit[9]_i_4_n_0\,
      S(0) => \neutral_min_limit[9]_i_5_n_0\
    );
\one_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \one_dec_max_limit[4]_i_2_n_0\
    );
\one_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \one_dec_max_limit[8]_i_2_n_0\
    );
\one_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \one_dec_max_limit[8]_i_3_n_0\
    );
\one_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \one_dec_max_limit[8]_i_4_n_0\
    );
\one_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(10),
      Q => one_dec_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(11),
      Q => one_dec_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \one_dec_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => one_dec_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 0) => device_temp_init(11 downto 9)
    );
\one_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(2),
      Q => one_dec_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(3),
      Q => one_dec_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(4),
      Q => one_dec_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_dec_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \one_dec_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \one_dec_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(2),
      DI(0) => '0',
      O(3 downto 1) => one_dec_max_limit_nxt(4 downto 2),
      O(0) => \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3 downto 2) => device_temp_init(4 downto 3),
      S(1) => \one_dec_max_limit[4]_i_2_n_0\,
      S(0) => device_temp_init(1)
    );
\one_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(5),
      Q => one_dec_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(6),
      Q => one_dec_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(7),
      Q => one_dec_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(8),
      Q => one_dec_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \one_dec_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \one_dec_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \one_dec_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \one_dec_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => device_temp_init(8),
      DI(2) => '0',
      DI(1 downto 0) => device_temp_init(6 downto 5),
      O(3 downto 0) => one_dec_max_limit_nxt(8 downto 5),
      S(3) => \one_dec_max_limit[8]_i_2_n_0\,
      S(2) => device_temp_init(7),
      S(1) => \one_dec_max_limit[8]_i_3_n_0\,
      S(0) => \one_dec_max_limit[8]_i_4_n_0\
    );
\one_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_max_limit_nxt(9),
      Q => one_dec_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\one_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(11),
      O => \one_dec_min_limit[11]_i_2_n_0\
    );
\one_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(10),
      O => \one_dec_min_limit[11]_i_3_n_0\
    );
\one_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(5),
      O => \one_dec_min_limit[5]_i_2_n_0\
    );
\one_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(4),
      O => \one_dec_min_limit[5]_i_3_n_0\
    );
\one_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(3),
      O => \one_dec_min_limit[5]_i_4_n_0\
    );
\one_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(9),
      O => \one_dec_min_limit[9]_i_2_n_0\
    );
\one_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(8),
      O => \one_dec_min_limit[9]_i_3_n_0\
    );
\one_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(7),
      O => \one_dec_min_limit[9]_i_4_n_0\
    );
\one_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => neutral_max_limit(6),
      O => \one_dec_min_limit[9]_i_5_n_0\
    );
\one_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(10),
      Q => one_dec_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(11),
      Q => one_dec_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \one_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => neutral_max_limit(10),
      O(3 downto 2) => \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => one_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \one_dec_min_limit[11]_i_2_n_0\,
      S(0) => \one_dec_min_limit[11]_i_3_n_0\
    );
\one_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(2),
      Q => one_dec_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(3),
      Q => one_dec_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(4),
      Q => one_dec_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(5),
      Q => one_dec_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \one_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \one_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \one_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => neutral_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => one_dec_min_limit_nxt(5 downto 2),
      S(3) => \one_dec_min_limit[5]_i_2_n_0\,
      S(2) => \one_dec_min_limit[5]_i_3_n_0\,
      S(1) => \one_dec_min_limit[5]_i_4_n_0\,
      S(0) => neutral_max_limit(2)
    );
\one_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(6),
      Q => one_dec_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(7),
      Q => one_dec_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(8),
      Q => one_dec_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_dec_min_limit_nxt(9),
      Q => one_dec_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \one_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \one_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \one_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \one_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => neutral_max_limit(9 downto 6),
      O(3 downto 0) => one_dec_min_limit_nxt(9 downto 6),
      S(3) => \one_dec_min_limit[9]_i_2_n_0\,
      S(2) => \one_dec_min_limit[9]_i_3_n_0\,
      S(1) => \one_dec_min_limit[9]_i_4_n_0\,
      S(0) => \one_dec_min_limit[9]_i_5_n_0\
    );
\one_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \one_inc_max_limit[11]_i_2_n_0\
    );
\one_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \one_inc_max_limit[11]_i_3_n_0\
    );
\one_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \one_inc_max_limit[11]_i_4_n_0\
    );
\one_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \one_inc_max_limit[4]_i_2_n_0\
    );
\one_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \one_inc_max_limit[8]_i_2_n_0\
    );
\one_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \one_inc_max_limit[8]_i_3_n_0\
    );
\one_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(10),
      Q => one_inc_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(11),
      Q => one_inc_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \one_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(10 downto 9),
      O(3) => \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => one_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \one_inc_max_limit[11]_i_2_n_0\,
      S(1) => \one_inc_max_limit[11]_i_3_n_0\,
      S(0) => \one_inc_max_limit[11]_i_4_n_0\
    );
\one_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(2),
      Q => one_inc_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(3),
      Q => one_inc_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(4),
      Q => one_inc_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \one_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \one_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => '0',
      DI(2) => device_temp_init(3),
      DI(1 downto 0) => B"00",
      O(3 downto 1) => one_inc_max_limit_nxt(4 downto 2),
      O(0) => \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => device_temp_init(4),
      S(2) => \one_inc_max_limit[4]_i_2_n_0\,
      S(1 downto 0) => device_temp_init(2 downto 1)
    );
\one_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(5),
      Q => one_inc_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(6),
      Q => one_inc_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(7),
      Q => one_inc_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(8),
      Q => one_inc_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \one_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \one_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \one_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \one_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => device_temp_init(8 downto 7),
      DI(1 downto 0) => B"00",
      O(3 downto 0) => one_inc_max_limit_nxt(8 downto 5),
      S(3) => \one_inc_max_limit[8]_i_2_n_0\,
      S(2) => \one_inc_max_limit[8]_i_3_n_0\,
      S(1 downto 0) => device_temp_init(6 downto 5)
    );
\one_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_max_limit_nxt(9),
      Q => one_inc_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\one_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(11),
      O => \one_inc_min_limit[11]_i_2_n_0\
    );
\one_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(10),
      O => \one_inc_min_limit[11]_i_3_n_0\
    );
\one_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(5),
      O => \one_inc_min_limit[5]_i_2_n_0\
    );
\one_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(4),
      O => \one_inc_min_limit[5]_i_3_n_0\
    );
\one_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(3),
      O => \one_inc_min_limit[5]_i_4_n_0\
    );
\one_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(9),
      O => \one_inc_min_limit[9]_i_2_n_0\
    );
\one_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(8),
      O => \one_inc_min_limit[9]_i_3_n_0\
    );
\one_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(7),
      O => \one_inc_min_limit[9]_i_4_n_0\
    );
\one_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_inc_max_limit(6),
      O => \one_inc_min_limit[9]_i_5_n_0\
    );
\one_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(10),
      Q => one_inc_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(11),
      Q => one_inc_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \one_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => two_inc_max_limit(10),
      O(3 downto 2) => \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => one_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \one_inc_min_limit[11]_i_2_n_0\,
      S(0) => \one_inc_min_limit[11]_i_3_n_0\
    );
\one_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(2),
      Q => one_inc_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(3),
      Q => one_inc_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(4),
      Q => one_inc_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(5),
      Q => one_inc_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \one_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \one_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \one_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \one_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => two_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => one_inc_min_limit_nxt(5 downto 2),
      S(3) => \one_inc_min_limit[5]_i_2_n_0\,
      S(2) => \one_inc_min_limit[5]_i_3_n_0\,
      S(1) => \one_inc_min_limit[5]_i_4_n_0\,
      S(0) => two_inc_max_limit(2)
    );
\one_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(6),
      Q => one_inc_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(7),
      Q => one_inc_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(8),
      Q => one_inc_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => one_inc_min_limit_nxt(9),
      Q => one_inc_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\one_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \one_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \one_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \one_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \one_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \one_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => two_inc_max_limit(9 downto 6),
      O(3 downto 0) => one_inc_min_limit_nxt(9 downto 6),
      S(3) => \one_inc_min_limit[9]_i_2_n_0\,
      S(2) => \one_inc_min_limit[9]_i_3_n_0\,
      S(1) => \one_inc_min_limit[9]_i_4_n_0\,
      S(0) => \one_inc_min_limit[9]_i_5_n_0\
    );
pi_f_dec_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F080"
    )
        port map (
      I0 => update_temp_102,
      I1 => pi_f_dec_i_2_n_0,
      I2 => \tempmon_state[10]_i_8_n_0\,
      I3 => \tempmon_state[10]_i_4_n_0\,
      O => pi_f_dec_nxt
    );
pi_f_dec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => temp_cmp_three_inc_max_102,
      I1 => tempmon_state(3),
      I2 => tempmon_state(5),
      I3 => temp_cmp_one_inc_max_102,
      I4 => tempmon_state(4),
      I5 => temp_cmp_two_inc_max_102,
      O => pi_f_dec_i_2_n_0
    );
pi_f_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_f_dec_nxt,
      Q => \^tempmon_pi_f_dec\,
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
pi_f_inc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEEEEEEEEE"
    )
        port map (
      I0 => pi_f_inc_i_2_n_0,
      I1 => pi_f_inc_i_3_n_0,
      I2 => temp_gte_three_dec_max,
      I3 => tempmon_state(9),
      I4 => temp_cmp_three_dec_min_102,
      I5 => pi_f_inc_i_5_n_0,
      O => pi_f_inc_nxt
    );
pi_f_inc_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => update_temp_102,
      I2 => temp_cmp_one_inc_max_102,
      I3 => temp_cmp_one_inc_min_102,
      O => pi_f_inc_i_10_n_0
    );
pi_f_inc_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAEAEAEAEAEAEAEA"
    )
        port map (
      I0 => pi_f_inc_i_6_n_0,
      I1 => pi_f_inc_i_7_n_0,
      I2 => \tempmon_state[10]_i_8_n_0\,
      I3 => tempmon_state(10),
      I4 => temp_cmp_four_dec_min_102,
      I5 => update_temp_102,
      O => pi_f_inc_i_2_n_0
    );
pi_f_inc_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => temp_cmp_two_dec_max_102,
      I1 => tempmon_state(8),
      I2 => temp_cmp_two_dec_min_102,
      I3 => update_temp_102,
      I4 => \tempmon_state[10]_i_8_n_0\,
      O => pi_f_inc_i_3_n_0
    );
pi_f_inc_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => update_temp_102,
      I1 => temp_cmp_three_dec_max_102,
      O => temp_gte_three_dec_max
    );
pi_f_inc_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tempmon_state[10]_i_8_n_0\,
      I1 => update_temp_102,
      O => pi_f_inc_i_5_n_0
    );
pi_f_inc_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00008000"
    )
        port map (
      I0 => \tempmon_state[10]_i_8_n_0\,
      I1 => update_temp_102,
      I2 => temp_cmp_one_dec_min_102,
      I3 => tempmon_state(7),
      I4 => temp_cmp_one_dec_max_102,
      I5 => pi_f_inc_i_8_n_0,
      O => pi_f_inc_i_6_n_0
    );
pi_f_inc_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAEAAAAA"
    )
        port map (
      I0 => pi_f_inc_i_9_n_0,
      I1 => tempmon_state(4),
      I2 => update_temp_102,
      I3 => temp_cmp_two_inc_max_102,
      I4 => temp_cmp_two_inc_min_102,
      I5 => pi_f_inc_i_10_n_0,
      O => pi_f_inc_i_7_n_0
    );
pi_f_inc_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => temp_cmp_neutral_max_102,
      I1 => tempmon_state(6),
      I2 => temp_cmp_neutral_min_102,
      I3 => update_temp_102,
      I4 => \tempmon_state[10]_i_8_n_0\,
      O => pi_f_inc_i_8_n_0
    );
pi_f_inc_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => tempmon_state(3),
      I1 => update_temp_102,
      I2 => temp_cmp_three_inc_max_102,
      I3 => temp_cmp_three_inc_min_102,
      O => pi_f_inc_i_9_n_0
    );
pi_f_inc_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pi_f_inc_nxt,
      Q => \^tempmon_pi_f_inc\,
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
temp_cmp_four_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => four_dec_min_limit(1),
      O => temp_cmp_four_dec_min_102_i_10_n_0
    );
temp_cmp_four_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => four_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_four_dec_min_102_i_11_n_0
    );
temp_cmp_four_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => four_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_four_dec_min_102_i_12_n_0
    );
temp_cmp_four_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => four_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_four_dec_min_102_i_13_n_0
    );
temp_cmp_four_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => four_dec_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_four_dec_min_102_i_14_n_0
    );
temp_cmp_four_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => four_dec_min_limit(11),
      O => temp_cmp_four_dec_min_102_i_3_n_0
    );
temp_cmp_four_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => four_dec_min_limit(9),
      O => temp_cmp_four_dec_min_102_i_4_n_0
    );
temp_cmp_four_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => four_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_four_dec_min_102_i_5_n_0
    );
temp_cmp_four_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => four_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => four_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_four_dec_min_102_i_6_n_0
    );
temp_cmp_four_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => four_dec_min_limit(7),
      O => temp_cmp_four_dec_min_102_i_7_n_0
    );
temp_cmp_four_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => four_dec_min_limit(5),
      O => temp_cmp_four_dec_min_102_i_8_n_0
    );
temp_cmp_four_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => four_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => four_dec_min_limit(3),
      O => temp_cmp_four_dec_min_102_i_9_n_0
    );
temp_cmp_four_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_four_dec_min_101,
      Q => temp_cmp_four_dec_min_102,
      R => '0'
    );
temp_cmp_four_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_four_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_four_dec_min_101,
      CO(0) => temp_cmp_four_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_four_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_four_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_four_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_four_dec_min_102_i_6_n_0
    );
temp_cmp_four_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_four_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_four_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_four_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_four_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_four_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_four_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_four_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_four_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_four_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_four_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_four_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_four_dec_min_102_i_14_n_0
    );
temp_cmp_four_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_four_inc_max_102_i_10_n_0
    );
temp_cmp_four_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => four_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => four_inc_max_limit(7),
      O => temp_cmp_four_inc_max_102_i_11_n_0
    );
temp_cmp_four_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => four_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => four_inc_max_limit(5),
      O => temp_cmp_four_inc_max_102_i_12_n_0
    );
temp_cmp_four_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => four_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => four_inc_max_limit(3),
      O => temp_cmp_four_inc_max_102_i_13_n_0
    );
temp_cmp_four_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_inc_max_limit(1),
      O => temp_cmp_four_inc_max_102_i_14_n_0
    );
temp_cmp_four_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => four_inc_max_limit(10),
      I2 => four_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_four_inc_max_102_i_3_n_0
    );
temp_cmp_four_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => four_inc_max_limit(8),
      I2 => four_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_four_inc_max_102_i_4_n_0
    );
temp_cmp_four_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => four_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => four_inc_max_limit(11),
      O => temp_cmp_four_inc_max_102_i_5_n_0
    );
temp_cmp_four_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => four_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => four_inc_max_limit(9),
      O => temp_cmp_four_inc_max_102_i_6_n_0
    );
temp_cmp_four_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => four_inc_max_limit(6),
      I2 => four_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_four_inc_max_102_i_7_n_0
    );
temp_cmp_four_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => four_inc_max_limit(4),
      I2 => four_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_four_inc_max_102_i_8_n_0
    );
temp_cmp_four_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => four_inc_max_limit(2),
      I2 => four_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_four_inc_max_102_i_9_n_0
    );
temp_cmp_four_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_four_inc_max_101,
      Q => temp_cmp_four_inc_max_102,
      R => '0'
    );
temp_cmp_four_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_four_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_four_inc_max_101,
      CO(0) => temp_cmp_four_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_four_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_four_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_four_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_four_inc_max_102_i_6_n_0
    );
temp_cmp_four_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_four_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_four_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_four_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_four_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_four_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_four_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_four_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_four_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_four_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_four_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_four_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_four_inc_max_102_i_14_n_0
    );
temp_cmp_neutral_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_neutral_max_102_i_10_n_0
    );
temp_cmp_neutral_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => neutral_max_limit(6),
      I2 => device_temp_101(7),
      I3 => neutral_max_limit(7),
      O => temp_cmp_neutral_max_102_i_11_n_0
    );
temp_cmp_neutral_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => neutral_max_limit(4),
      I2 => device_temp_101(5),
      I3 => neutral_max_limit(5),
      O => temp_cmp_neutral_max_102_i_12_n_0
    );
temp_cmp_neutral_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => neutral_max_limit(2),
      I2 => device_temp_101(3),
      I3 => neutral_max_limit(3),
      O => temp_cmp_neutral_max_102_i_13_n_0
    );
temp_cmp_neutral_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_inc_max_limit(1),
      O => temp_cmp_neutral_max_102_i_14_n_0
    );
temp_cmp_neutral_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => neutral_max_limit(10),
      I2 => neutral_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_neutral_max_102_i_3_n_0
    );
temp_cmp_neutral_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => neutral_max_limit(8),
      I2 => neutral_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_neutral_max_102_i_4_n_0
    );
temp_cmp_neutral_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => neutral_max_limit(10),
      I2 => device_temp_101(11),
      I3 => neutral_max_limit(11),
      O => temp_cmp_neutral_max_102_i_5_n_0
    );
temp_cmp_neutral_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => neutral_max_limit(8),
      I2 => device_temp_101(9),
      I3 => neutral_max_limit(9),
      O => temp_cmp_neutral_max_102_i_6_n_0
    );
temp_cmp_neutral_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => neutral_max_limit(6),
      I2 => neutral_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_neutral_max_102_i_7_n_0
    );
temp_cmp_neutral_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => neutral_max_limit(4),
      I2 => neutral_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_neutral_max_102_i_8_n_0
    );
temp_cmp_neutral_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => neutral_max_limit(2),
      I2 => neutral_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_neutral_max_102_i_9_n_0
    );
temp_cmp_neutral_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_neutral_max_101,
      Q => temp_cmp_neutral_max_102,
      R => '0'
    );
temp_cmp_neutral_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_neutral_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_neutral_max_101,
      CO(0) => temp_cmp_neutral_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_neutral_max_102_i_3_n_0,
      DI(0) => temp_cmp_neutral_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_neutral_max_102_i_5_n_0,
      S(0) => temp_cmp_neutral_max_102_i_6_n_0
    );
temp_cmp_neutral_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_neutral_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_neutral_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_neutral_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_neutral_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_neutral_max_102_i_7_n_0,
      DI(2) => temp_cmp_neutral_max_102_i_8_n_0,
      DI(1) => temp_cmp_neutral_max_102_i_9_n_0,
      DI(0) => temp_cmp_neutral_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_neutral_max_102_i_11_n_0,
      S(2) => temp_cmp_neutral_max_102_i_12_n_0,
      S(1) => temp_cmp_neutral_max_102_i_13_n_0,
      S(0) => temp_cmp_neutral_max_102_i_14_n_0
    );
temp_cmp_neutral_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => neutral_min_limit(1),
      O => temp_cmp_neutral_min_102_i_10_n_0
    );
temp_cmp_neutral_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(6),
      I1 => device_temp_101(6),
      I2 => neutral_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_neutral_min_102_i_11_n_0
    );
temp_cmp_neutral_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(4),
      I1 => device_temp_101(4),
      I2 => neutral_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_neutral_min_102_i_12_n_0
    );
temp_cmp_neutral_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(2),
      I1 => device_temp_101(2),
      I2 => neutral_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_neutral_min_102_i_13_n_0
    );
temp_cmp_neutral_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => neutral_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_neutral_min_102_i_14_n_0
    );
temp_cmp_neutral_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => neutral_min_limit(11),
      O => temp_cmp_neutral_min_102_i_3_n_0
    );
temp_cmp_neutral_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => neutral_min_limit(9),
      O => temp_cmp_neutral_min_102_i_4_n_0
    );
temp_cmp_neutral_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(10),
      I1 => device_temp_101(10),
      I2 => neutral_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_neutral_min_102_i_5_n_0
    );
temp_cmp_neutral_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => neutral_min_limit(8),
      I1 => device_temp_101(8),
      I2 => neutral_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_neutral_min_102_i_6_n_0
    );
temp_cmp_neutral_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => neutral_min_limit(7),
      O => temp_cmp_neutral_min_102_i_7_n_0
    );
temp_cmp_neutral_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => neutral_min_limit(5),
      O => temp_cmp_neutral_min_102_i_8_n_0
    );
temp_cmp_neutral_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => neutral_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => neutral_min_limit(3),
      O => temp_cmp_neutral_min_102_i_9_n_0
    );
temp_cmp_neutral_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_neutral_min_101,
      Q => temp_cmp_neutral_min_102,
      R => '0'
    );
temp_cmp_neutral_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_neutral_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_neutral_min_101,
      CO(0) => temp_cmp_neutral_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_neutral_min_102_i_3_n_0,
      DI(0) => temp_cmp_neutral_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_neutral_min_102_i_5_n_0,
      S(0) => temp_cmp_neutral_min_102_i_6_n_0
    );
temp_cmp_neutral_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_neutral_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_neutral_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_neutral_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_neutral_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_neutral_min_102_i_7_n_0,
      DI(2) => temp_cmp_neutral_min_102_i_8_n_0,
      DI(1) => temp_cmp_neutral_min_102_i_9_n_0,
      DI(0) => temp_cmp_neutral_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_neutral_min_102_i_11_n_0,
      S(2) => temp_cmp_neutral_min_102_i_12_n_0,
      S(1) => temp_cmp_neutral_min_102_i_13_n_0,
      S(0) => temp_cmp_neutral_min_102_i_14_n_0
    );
temp_cmp_one_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => three_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_dec_max_102_i_10_n_0
    );
temp_cmp_one_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => one_dec_max_limit(7),
      O => temp_cmp_one_dec_max_102_i_11_n_0
    );
temp_cmp_one_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => one_dec_max_limit(5),
      O => temp_cmp_one_dec_max_102_i_12_n_0
    );
temp_cmp_one_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => one_dec_max_limit(3),
      O => temp_cmp_one_dec_max_102_i_13_n_0
    );
temp_cmp_one_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => three_inc_max_limit(1),
      O => temp_cmp_one_dec_max_102_i_14_n_0
    );
temp_cmp_one_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_dec_max_limit(10),
      I2 => one_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_dec_max_102_i_3_n_0
    );
temp_cmp_one_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_dec_max_limit(8),
      I2 => one_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_dec_max_102_i_4_n_0
    );
temp_cmp_one_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => one_dec_max_limit(11),
      O => temp_cmp_one_dec_max_102_i_5_n_0
    );
temp_cmp_one_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => one_dec_max_limit(9),
      O => temp_cmp_one_dec_max_102_i_6_n_0
    );
temp_cmp_one_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_dec_max_limit(6),
      I2 => one_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_dec_max_102_i_7_n_0
    );
temp_cmp_one_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_dec_max_limit(4),
      I2 => one_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_dec_max_102_i_8_n_0
    );
temp_cmp_one_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_dec_max_limit(2),
      I2 => one_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_dec_max_102_i_9_n_0
    );
temp_cmp_one_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_dec_max_101,
      Q => temp_cmp_one_dec_max_102,
      R => '0'
    );
temp_cmp_one_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_dec_max_101,
      CO(0) => temp_cmp_one_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_one_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_one_dec_max_102_i_6_n_0
    );
temp_cmp_one_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_one_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_one_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_one_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_one_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_one_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_one_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_one_dec_max_102_i_14_n_0
    );
temp_cmp_one_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_inc_min_limit(1),
      O => temp_cmp_one_dec_min_102_i_10_n_0
    );
temp_cmp_one_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => one_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_dec_min_102_i_11_n_0
    );
temp_cmp_one_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => one_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_dec_min_102_i_12_n_0
    );
temp_cmp_one_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => one_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_dec_min_102_i_13_n_0
    );
temp_cmp_one_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_dec_min_102_i_14_n_0
    );
temp_cmp_one_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => one_dec_min_limit(11),
      O => temp_cmp_one_dec_min_102_i_3_n_0
    );
temp_cmp_one_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => one_dec_min_limit(9),
      O => temp_cmp_one_dec_min_102_i_4_n_0
    );
temp_cmp_one_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => one_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_dec_min_102_i_5_n_0
    );
temp_cmp_one_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => one_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_dec_min_102_i_6_n_0
    );
temp_cmp_one_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => one_dec_min_limit(7),
      O => temp_cmp_one_dec_min_102_i_7_n_0
    );
temp_cmp_one_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => one_dec_min_limit(5),
      O => temp_cmp_one_dec_min_102_i_8_n_0
    );
temp_cmp_one_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => one_dec_min_limit(3),
      O => temp_cmp_one_dec_min_102_i_9_n_0
    );
temp_cmp_one_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_dec_min_101,
      Q => temp_cmp_one_dec_min_102,
      R => '0'
    );
temp_cmp_one_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_dec_min_101,
      CO(0) => temp_cmp_one_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_one_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_one_dec_min_102_i_6_n_0
    );
temp_cmp_one_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_one_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_one_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_one_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_one_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_one_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_one_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_one_dec_min_102_i_14_n_0
    );
temp_cmp_one_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => three_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_inc_max_102_i_10_n_0
    );
temp_cmp_one_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => one_inc_max_limit(7),
      O => temp_cmp_one_inc_max_102_i_11_n_0
    );
temp_cmp_one_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => one_inc_max_limit(5),
      O => temp_cmp_one_inc_max_102_i_12_n_0
    );
temp_cmp_one_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => one_inc_max_limit(3),
      O => temp_cmp_one_inc_max_102_i_13_n_0
    );
temp_cmp_one_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => three_inc_max_limit(1),
      O => temp_cmp_one_inc_max_102_i_14_n_0
    );
temp_cmp_one_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_inc_max_limit(10),
      I2 => one_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_inc_max_102_i_3_n_0
    );
temp_cmp_one_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_inc_max_limit(8),
      I2 => one_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_inc_max_102_i_4_n_0
    );
temp_cmp_one_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => one_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => one_inc_max_limit(11),
      O => temp_cmp_one_inc_max_102_i_5_n_0
    );
temp_cmp_one_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => one_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => one_inc_max_limit(9),
      O => temp_cmp_one_inc_max_102_i_6_n_0
    );
temp_cmp_one_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => one_inc_max_limit(6),
      I2 => one_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_inc_max_102_i_7_n_0
    );
temp_cmp_one_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => one_inc_max_limit(4),
      I2 => one_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_inc_max_102_i_8_n_0
    );
temp_cmp_one_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => one_inc_max_limit(2),
      I2 => one_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_inc_max_102_i_9_n_0
    );
temp_cmp_one_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_inc_max_101,
      Q => temp_cmp_one_inc_max_102,
      R => '0'
    );
temp_cmp_one_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_inc_max_101,
      CO(0) => temp_cmp_one_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_one_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_one_inc_max_102_i_6_n_0
    );
temp_cmp_one_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_one_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_one_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_one_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_one_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_one_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_one_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_one_inc_max_102_i_14_n_0
    );
temp_cmp_one_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_inc_min_limit(1),
      O => temp_cmp_one_inc_min_102_i_10_n_0
    );
temp_cmp_one_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => one_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_one_inc_min_102_i_11_n_0
    );
temp_cmp_one_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => one_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_one_inc_min_102_i_12_n_0
    );
temp_cmp_one_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => one_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_one_inc_min_102_i_13_n_0
    );
temp_cmp_one_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_one_inc_min_102_i_14_n_0
    );
temp_cmp_one_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => one_inc_min_limit(11),
      O => temp_cmp_one_inc_min_102_i_3_n_0
    );
temp_cmp_one_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => one_inc_min_limit(9),
      O => temp_cmp_one_inc_min_102_i_4_n_0
    );
temp_cmp_one_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => one_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_one_inc_min_102_i_5_n_0
    );
temp_cmp_one_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => one_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => one_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_one_inc_min_102_i_6_n_0
    );
temp_cmp_one_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => one_inc_min_limit(7),
      O => temp_cmp_one_inc_min_102_i_7_n_0
    );
temp_cmp_one_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => one_inc_min_limit(5),
      O => temp_cmp_one_inc_min_102_i_8_n_0
    );
temp_cmp_one_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => one_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => one_inc_min_limit(3),
      O => temp_cmp_one_inc_min_102_i_9_n_0
    );
temp_cmp_one_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_one_inc_min_101,
      Q => temp_cmp_one_inc_min_102,
      R => '0'
    );
temp_cmp_one_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_one_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_one_inc_min_101,
      CO(0) => temp_cmp_one_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_one_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_one_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_one_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_one_inc_min_102_i_6_n_0
    );
temp_cmp_one_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_one_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_one_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_one_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_one_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_one_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_one_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_one_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_one_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_one_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_one_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_one_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_one_inc_min_102_i_14_n_0
    );
temp_cmp_three_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => three_dec_max_limit(0),
      I2 => three_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_dec_max_102_i_10_n_0
    );
temp_cmp_three_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => three_dec_max_limit(7),
      O => temp_cmp_three_dec_max_102_i_11_n_0
    );
temp_cmp_three_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => three_dec_max_limit(5),
      O => temp_cmp_three_dec_max_102_i_12_n_0
    );
temp_cmp_three_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => three_dec_max_limit(3),
      O => temp_cmp_three_dec_max_102_i_13_n_0
    );
temp_cmp_three_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => three_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => three_dec_max_limit(1),
      O => temp_cmp_three_dec_max_102_i_14_n_0
    );
temp_cmp_three_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_dec_max_limit(10),
      I2 => three_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_dec_max_102_i_3_n_0
    );
temp_cmp_three_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_dec_max_limit(8),
      I2 => three_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_dec_max_102_i_4_n_0
    );
temp_cmp_three_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => three_dec_max_limit(11),
      O => temp_cmp_three_dec_max_102_i_5_n_0
    );
temp_cmp_three_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => three_dec_max_limit(9),
      O => temp_cmp_three_dec_max_102_i_6_n_0
    );
temp_cmp_three_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_dec_max_limit(6),
      I2 => three_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_dec_max_102_i_7_n_0
    );
temp_cmp_three_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_dec_max_limit(4),
      I2 => three_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_dec_max_102_i_8_n_0
    );
temp_cmp_three_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_dec_max_limit(2),
      I2 => three_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_dec_max_102_i_9_n_0
    );
temp_cmp_three_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_dec_max_101,
      Q => temp_cmp_three_dec_max_102,
      R => '0'
    );
temp_cmp_three_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_dec_max_101,
      CO(0) => temp_cmp_three_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_three_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_three_dec_max_102_i_6_n_0
    );
temp_cmp_three_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_three_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_three_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_three_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_three_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_three_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_three_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_three_dec_max_102_i_14_n_0
    );
temp_cmp_three_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_dec_min_limit(1),
      O => temp_cmp_three_dec_min_102_i_10_n_0
    );
temp_cmp_three_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => three_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_dec_min_102_i_11_n_0
    );
temp_cmp_three_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => three_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_dec_min_102_i_12_n_0
    );
temp_cmp_three_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => three_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_dec_min_102_i_13_n_0
    );
temp_cmp_three_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_dec_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_dec_min_102_i_14_n_0
    );
temp_cmp_three_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => three_dec_min_limit(11),
      O => temp_cmp_three_dec_min_102_i_3_n_0
    );
temp_cmp_three_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => three_dec_min_limit(9),
      O => temp_cmp_three_dec_min_102_i_4_n_0
    );
temp_cmp_three_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => three_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_dec_min_102_i_5_n_0
    );
temp_cmp_three_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => three_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_dec_min_102_i_6_n_0
    );
temp_cmp_three_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => three_dec_min_limit(7),
      O => temp_cmp_three_dec_min_102_i_7_n_0
    );
temp_cmp_three_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => three_dec_min_limit(5),
      O => temp_cmp_three_dec_min_102_i_8_n_0
    );
temp_cmp_three_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => three_dec_min_limit(3),
      O => temp_cmp_three_dec_min_102_i_9_n_0
    );
temp_cmp_three_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_dec_min_101,
      Q => temp_cmp_three_dec_min_102,
      R => '0'
    );
temp_cmp_three_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_dec_min_101,
      CO(0) => temp_cmp_three_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_three_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_three_dec_min_102_i_6_n_0
    );
temp_cmp_three_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_three_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_three_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_three_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_three_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_three_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_three_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_three_dec_min_102_i_14_n_0
    );
temp_cmp_three_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => three_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_inc_max_102_i_10_n_0
    );
temp_cmp_three_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => three_inc_max_limit(7),
      O => temp_cmp_three_inc_max_102_i_11_n_0
    );
temp_cmp_three_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => three_inc_max_limit(5),
      O => temp_cmp_three_inc_max_102_i_12_n_0
    );
temp_cmp_three_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => three_inc_max_limit(3),
      O => temp_cmp_three_inc_max_102_i_13_n_0
    );
temp_cmp_three_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => three_inc_max_limit(1),
      O => temp_cmp_three_inc_max_102_i_14_n_0
    );
temp_cmp_three_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_inc_max_limit(10),
      I2 => three_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_inc_max_102_i_3_n_0
    );
temp_cmp_three_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_inc_max_limit(8),
      I2 => three_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_inc_max_102_i_4_n_0
    );
temp_cmp_three_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => three_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => three_inc_max_limit(11),
      O => temp_cmp_three_inc_max_102_i_5_n_0
    );
temp_cmp_three_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => three_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => three_inc_max_limit(9),
      O => temp_cmp_three_inc_max_102_i_6_n_0
    );
temp_cmp_three_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => three_inc_max_limit(6),
      I2 => three_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_inc_max_102_i_7_n_0
    );
temp_cmp_three_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => three_inc_max_limit(4),
      I2 => three_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_inc_max_102_i_8_n_0
    );
temp_cmp_three_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => three_inc_max_limit(2),
      I2 => three_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_inc_max_102_i_9_n_0
    );
temp_cmp_three_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_inc_max_101,
      Q => temp_cmp_three_inc_max_102,
      R => '0'
    );
temp_cmp_three_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_inc_max_101,
      CO(0) => temp_cmp_three_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_three_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_three_inc_max_102_i_6_n_0
    );
temp_cmp_three_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_three_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_three_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_three_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_three_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_three_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_three_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_three_inc_max_102_i_14_n_0
    );
temp_cmp_three_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => three_inc_min_limit(1),
      O => temp_cmp_three_inc_min_102_i_10_n_0
    );
temp_cmp_three_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => three_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_three_inc_min_102_i_11_n_0
    );
temp_cmp_three_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => three_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_three_inc_min_102_i_12_n_0
    );
temp_cmp_three_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => three_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_three_inc_min_102_i_13_n_0
    );
temp_cmp_three_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => three_inc_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_three_inc_min_102_i_14_n_0
    );
temp_cmp_three_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => three_inc_min_limit(11),
      O => temp_cmp_three_inc_min_102_i_3_n_0
    );
temp_cmp_three_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => three_inc_min_limit(9),
      O => temp_cmp_three_inc_min_102_i_4_n_0
    );
temp_cmp_three_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => three_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_three_inc_min_102_i_5_n_0
    );
temp_cmp_three_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => three_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_three_inc_min_102_i_6_n_0
    );
temp_cmp_three_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => three_inc_min_limit(7),
      O => temp_cmp_three_inc_min_102_i_7_n_0
    );
temp_cmp_three_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => three_inc_min_limit(5),
      O => temp_cmp_three_inc_min_102_i_8_n_0
    );
temp_cmp_three_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => three_inc_min_limit(3),
      O => temp_cmp_three_inc_min_102_i_9_n_0
    );
temp_cmp_three_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_three_inc_min_101,
      Q => temp_cmp_three_inc_min_102,
      R => '0'
    );
temp_cmp_three_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_three_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_three_inc_min_101,
      CO(0) => temp_cmp_three_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_three_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_three_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_three_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_three_inc_min_102_i_6_n_0
    );
temp_cmp_three_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_three_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_three_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_three_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_three_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_three_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_three_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_three_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_three_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_three_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_three_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_three_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_three_inc_min_102_i_14_n_0
    );
temp_cmp_two_dec_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_dec_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_dec_max_102_i_10_n_0
    );
temp_cmp_two_dec_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_dec_max_limit(6),
      I2 => device_temp_101(7),
      I3 => two_dec_max_limit(7),
      O => temp_cmp_two_dec_max_102_i_11_n_0
    );
temp_cmp_two_dec_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_dec_max_limit(4),
      I2 => device_temp_101(5),
      I3 => two_dec_max_limit(5),
      O => temp_cmp_two_dec_max_102_i_12_n_0
    );
temp_cmp_two_dec_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_dec_max_limit(2),
      I2 => device_temp_101(3),
      I3 => two_dec_max_limit(3),
      O => temp_cmp_two_dec_max_102_i_13_n_0
    );
temp_cmp_two_dec_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_dec_max_limit(1),
      O => temp_cmp_two_dec_max_102_i_14_n_0
    );
temp_cmp_two_dec_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_dec_max_limit(10),
      I2 => two_dec_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_dec_max_102_i_3_n_0
    );
temp_cmp_two_dec_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_dec_max_limit(8),
      I2 => two_dec_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_dec_max_102_i_4_n_0
    );
temp_cmp_two_dec_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_dec_max_limit(10),
      I2 => device_temp_101(11),
      I3 => two_dec_max_limit(11),
      O => temp_cmp_two_dec_max_102_i_5_n_0
    );
temp_cmp_two_dec_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_dec_max_limit(8),
      I2 => device_temp_101(9),
      I3 => two_dec_max_limit(9),
      O => temp_cmp_two_dec_max_102_i_6_n_0
    );
temp_cmp_two_dec_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_dec_max_limit(6),
      I2 => two_dec_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_dec_max_102_i_7_n_0
    );
temp_cmp_two_dec_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_dec_max_limit(4),
      I2 => two_dec_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_dec_max_102_i_8_n_0
    );
temp_cmp_two_dec_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_dec_max_limit(2),
      I2 => two_dec_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_dec_max_102_i_9_n_0
    );
temp_cmp_two_dec_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_dec_max_101,
      Q => temp_cmp_two_dec_max_102,
      R => '0'
    );
temp_cmp_two_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_dec_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_dec_max_101,
      CO(0) => temp_cmp_two_dec_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_dec_max_102_i_3_n_0,
      DI(0) => temp_cmp_two_dec_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_dec_max_102_i_5_n_0,
      S(0) => temp_cmp_two_dec_max_102_i_6_n_0
    );
temp_cmp_two_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_dec_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_dec_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_dec_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_dec_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_two_dec_max_102_i_7_n_0,
      DI(2) => temp_cmp_two_dec_max_102_i_8_n_0,
      DI(1) => temp_cmp_two_dec_max_102_i_9_n_0,
      DI(0) => temp_cmp_two_dec_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_dec_max_102_i_11_n_0,
      S(2) => temp_cmp_two_dec_max_102_i_12_n_0,
      S(1) => temp_cmp_two_dec_max_102_i_13_n_0,
      S(0) => temp_cmp_two_dec_max_102_i_14_n_0
    );
temp_cmp_two_dec_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => neutral_min_limit(1),
      O => temp_cmp_two_dec_min_102_i_10_n_0
    );
temp_cmp_two_dec_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => two_dec_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_dec_min_102_i_11_n_0
    );
temp_cmp_two_dec_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => two_dec_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_dec_min_102_i_12_n_0
    );
temp_cmp_two_dec_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => two_dec_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_dec_min_102_i_13_n_0
    );
temp_cmp_two_dec_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => neutral_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_dec_min_102_i_14_n_0
    );
temp_cmp_two_dec_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => two_dec_min_limit(11),
      O => temp_cmp_two_dec_min_102_i_3_n_0
    );
temp_cmp_two_dec_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => two_dec_min_limit(9),
      O => temp_cmp_two_dec_min_102_i_4_n_0
    );
temp_cmp_two_dec_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(10),
      I1 => device_temp_101(10),
      I2 => two_dec_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_dec_min_102_i_5_n_0
    );
temp_cmp_two_dec_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_dec_min_limit(8),
      I1 => device_temp_101(8),
      I2 => two_dec_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_dec_min_102_i_6_n_0
    );
temp_cmp_two_dec_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => two_dec_min_limit(7),
      O => temp_cmp_two_dec_min_102_i_7_n_0
    );
temp_cmp_two_dec_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => two_dec_min_limit(5),
      O => temp_cmp_two_dec_min_102_i_8_n_0
    );
temp_cmp_two_dec_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_dec_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => two_dec_min_limit(3),
      O => temp_cmp_two_dec_min_102_i_9_n_0
    );
temp_cmp_two_dec_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_dec_min_101,
      Q => temp_cmp_two_dec_min_102,
      R => '0'
    );
temp_cmp_two_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_dec_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_dec_min_101,
      CO(0) => temp_cmp_two_dec_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_dec_min_102_i_3_n_0,
      DI(0) => temp_cmp_two_dec_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_dec_min_102_i_5_n_0,
      S(0) => temp_cmp_two_dec_min_102_i_6_n_0
    );
temp_cmp_two_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_dec_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_dec_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_dec_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_dec_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_two_dec_min_102_i_7_n_0,
      DI(2) => temp_cmp_two_dec_min_102_i_8_n_0,
      DI(1) => temp_cmp_two_dec_min_102_i_9_n_0,
      DI(0) => temp_cmp_two_dec_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_dec_min_102_i_11_n_0,
      S(2) => temp_cmp_two_dec_min_102_i_12_n_0,
      S(1) => temp_cmp_two_dec_min_102_i_13_n_0,
      S(0) => temp_cmp_two_dec_min_102_i_14_n_0
    );
temp_cmp_two_inc_max_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => two_inc_max_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_inc_max_102_i_10_n_0
    );
temp_cmp_two_inc_max_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_inc_max_limit(6),
      I2 => device_temp_101(7),
      I3 => two_inc_max_limit(7),
      O => temp_cmp_two_inc_max_102_i_11_n_0
    );
temp_cmp_two_inc_max_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_inc_max_limit(4),
      I2 => device_temp_101(5),
      I3 => two_inc_max_limit(5),
      O => temp_cmp_two_inc_max_102_i_12_n_0
    );
temp_cmp_two_inc_max_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_inc_max_limit(2),
      I2 => device_temp_101(3),
      I3 => two_inc_max_limit(3),
      O => temp_cmp_two_inc_max_102_i_13_n_0
    );
temp_cmp_two_inc_max_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(0),
      I1 => two_dec_max_limit(0),
      I2 => device_temp_101(1),
      I3 => two_inc_max_limit(1),
      O => temp_cmp_two_inc_max_102_i_14_n_0
    );
temp_cmp_two_inc_max_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_inc_max_limit(10),
      I2 => two_inc_max_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_inc_max_102_i_3_n_0
    );
temp_cmp_two_inc_max_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_inc_max_limit(8),
      I2 => two_inc_max_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_inc_max_102_i_4_n_0
    );
temp_cmp_two_inc_max_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(10),
      I1 => two_inc_max_limit(10),
      I2 => device_temp_101(11),
      I3 => two_inc_max_limit(11),
      O => temp_cmp_two_inc_max_102_i_5_n_0
    );
temp_cmp_two_inc_max_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => device_temp_101(8),
      I1 => two_inc_max_limit(8),
      I2 => device_temp_101(9),
      I3 => two_inc_max_limit(9),
      O => temp_cmp_two_inc_max_102_i_6_n_0
    );
temp_cmp_two_inc_max_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(6),
      I1 => two_inc_max_limit(6),
      I2 => two_inc_max_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_inc_max_102_i_7_n_0
    );
temp_cmp_two_inc_max_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(4),
      I1 => two_inc_max_limit(4),
      I2 => two_inc_max_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_inc_max_102_i_8_n_0
    );
temp_cmp_two_inc_max_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => device_temp_101(2),
      I1 => two_inc_max_limit(2),
      I2 => two_inc_max_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_inc_max_102_i_9_n_0
    );
temp_cmp_two_inc_max_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_inc_max_101,
      Q => temp_cmp_two_inc_max_102,
      R => '0'
    );
temp_cmp_two_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_inc_max_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_inc_max_101,
      CO(0) => temp_cmp_two_inc_max_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_inc_max_102_i_3_n_0,
      DI(0) => temp_cmp_two_inc_max_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_inc_max_102_i_5_n_0,
      S(0) => temp_cmp_two_inc_max_102_i_6_n_0
    );
temp_cmp_two_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_inc_max_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_inc_max_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_inc_max_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_inc_max_102_reg_i_2_n_3,
      CYINIT => '1',
      DI(3) => temp_cmp_two_inc_max_102_i_7_n_0,
      DI(2) => temp_cmp_two_inc_max_102_i_8_n_0,
      DI(1) => temp_cmp_two_inc_max_102_i_9_n_0,
      DI(0) => temp_cmp_two_inc_max_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_inc_max_102_i_11_n_0,
      S(2) => temp_cmp_two_inc_max_102_i_12_n_0,
      S(1) => temp_cmp_two_inc_max_102_i_13_n_0,
      S(0) => temp_cmp_two_inc_max_102_i_14_n_0
    );
temp_cmp_two_inc_min_102_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => device_temp_101(1),
      I3 => neutral_min_limit(1),
      O => temp_cmp_two_inc_min_102_i_10_n_0
    );
temp_cmp_two_inc_min_102_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => two_inc_min_limit(7),
      I3 => device_temp_101(7),
      O => temp_cmp_two_inc_min_102_i_11_n_0
    );
temp_cmp_two_inc_min_102_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => two_inc_min_limit(5),
      I3 => device_temp_101(5),
      O => temp_cmp_two_inc_min_102_i_12_n_0
    );
temp_cmp_two_inc_min_102_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => two_inc_min_limit(3),
      I3 => device_temp_101(3),
      O => temp_cmp_two_inc_min_102_i_13_n_0
    );
temp_cmp_two_inc_min_102_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => three_dec_min_limit(0),
      I1 => device_temp_101(0),
      I2 => neutral_min_limit(1),
      I3 => device_temp_101(1),
      O => temp_cmp_two_inc_min_102_i_14_n_0
    );
temp_cmp_two_inc_min_102_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => device_temp_101(11),
      I3 => two_inc_min_limit(11),
      O => temp_cmp_two_inc_min_102_i_3_n_0
    );
temp_cmp_two_inc_min_102_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => device_temp_101(9),
      I3 => two_inc_min_limit(9),
      O => temp_cmp_two_inc_min_102_i_4_n_0
    );
temp_cmp_two_inc_min_102_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(10),
      I1 => device_temp_101(10),
      I2 => two_inc_min_limit(11),
      I3 => device_temp_101(11),
      O => temp_cmp_two_inc_min_102_i_5_n_0
    );
temp_cmp_two_inc_min_102_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => two_inc_min_limit(8),
      I1 => device_temp_101(8),
      I2 => two_inc_min_limit(9),
      I3 => device_temp_101(9),
      O => temp_cmp_two_inc_min_102_i_6_n_0
    );
temp_cmp_two_inc_min_102_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(6),
      I1 => device_temp_101(6),
      I2 => device_temp_101(7),
      I3 => two_inc_min_limit(7),
      O => temp_cmp_two_inc_min_102_i_7_n_0
    );
temp_cmp_two_inc_min_102_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(4),
      I1 => device_temp_101(4),
      I2 => device_temp_101(5),
      I3 => two_inc_min_limit(5),
      O => temp_cmp_two_inc_min_102_i_8_n_0
    );
temp_cmp_two_inc_min_102_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F02"
    )
        port map (
      I0 => two_inc_min_limit(2),
      I1 => device_temp_101(2),
      I2 => device_temp_101(3),
      I3 => two_inc_min_limit(3),
      O => temp_cmp_two_inc_min_102_i_9_n_0
    );
temp_cmp_two_inc_min_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => temp_cmp_two_inc_min_101,
      Q => temp_cmp_two_inc_min_102,
      R => '0'
    );
temp_cmp_two_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => temp_cmp_two_inc_min_102_reg_i_2_n_0,
      CO(3 downto 2) => NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2),
      CO(1) => temp_cmp_two_inc_min_101,
      CO(0) => temp_cmp_two_inc_min_102_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => temp_cmp_two_inc_min_102_i_3_n_0,
      DI(0) => temp_cmp_two_inc_min_102_i_4_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => temp_cmp_two_inc_min_102_i_5_n_0,
      S(0) => temp_cmp_two_inc_min_102_i_6_n_0
    );
temp_cmp_two_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => temp_cmp_two_inc_min_102_reg_i_2_n_0,
      CO(2) => temp_cmp_two_inc_min_102_reg_i_2_n_1,
      CO(1) => temp_cmp_two_inc_min_102_reg_i_2_n_2,
      CO(0) => temp_cmp_two_inc_min_102_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => temp_cmp_two_inc_min_102_i_7_n_0,
      DI(2) => temp_cmp_two_inc_min_102_i_8_n_0,
      DI(1) => temp_cmp_two_inc_min_102_i_9_n_0,
      DI(0) => temp_cmp_two_inc_min_102_i_10_n_0,
      O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3) => temp_cmp_two_inc_min_102_i_11_n_0,
      S(2) => temp_cmp_two_inc_min_102_i_12_n_0,
      S(1) => temp_cmp_two_inc_min_102_i_13_n_0,
      S(0) => temp_cmp_two_inc_min_102_i_14_n_0
    );
tempmon_init_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_init,
      D => tempmon_state_init,
      Q => tempmon_init_complete,
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
tempmon_pi_f_en_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^tempmon_pi_f_inc\,
      I1 => \^tempmon_pi_f_dec\,
      O => tempmon_pi_f_en_r0
    );
tempmon_sample_en_101_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tempmon_sample_en,
      Q => tempmon_sample_en_101,
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
tempmon_sample_en_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tempmon_sample_en_101,
      Q => tempmon_sample_en_102,
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tempmon_state[10]_i_8_n_0\,
      O => \tempmon_state[0]_i_1_n_0\
    );
\tempmon_state[10]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0808080"
    )
        port map (
      I0 => temp_cmp_neutral_max_102,
      I1 => tempmon_state(6),
      I2 => update_temp_102,
      I3 => temp_cmp_one_dec_max_102,
      I4 => tempmon_state(7),
      O => \tempmon_state[10]_i_10_n_0\
    );
\tempmon_state[10]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => update_temp_102,
      I1 => temp_cmp_four_dec_min_102,
      I2 => tempmon_state(10),
      O => \tempmon_state[10]_i_11_n_0\
    );
\tempmon_state[10]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0808080"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => temp_cmp_one_inc_min_102,
      I2 => update_temp_102,
      I3 => tempmon_state(4),
      I4 => temp_cmp_two_inc_min_102,
      O => \tempmon_state[10]_i_12_n_0\
    );
\tempmon_state[10]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAEAEAEAEAEAEA"
    )
        port map (
      I0 => tempmon_state(1),
      I1 => calib_complete,
      I2 => tempmon_state(0),
      I3 => update_temp_102,
      I4 => tempmon_state(9),
      I5 => temp_cmp_three_dec_min_102,
      O => \tempmon_state[10]_i_13_n_0\
    );
\tempmon_state[10]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(1),
      I2 => tempmon_state(2),
      I3 => tempmon_state(3),
      I4 => tempmon_state(4),
      O => \tempmon_state[10]_i_14_n_0\
    );
\tempmon_state[10]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEE8"
    )
        port map (
      I0 => tempmon_state(0),
      I1 => tempmon_state(1),
      I2 => tempmon_state(2),
      I3 => tempmon_state(3),
      I4 => tempmon_state(4),
      O => \tempmon_state[10]_i_15_n_0\
    );
\tempmon_state[10]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => tempmon_state(6),
      I2 => tempmon_state(7),
      I3 => tempmon_state(8),
      I4 => tempmon_state(9),
      I5 => tempmon_state(10),
      O => \tempmon_state[10]_i_16_n_0\
    );
\tempmon_state[10]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFEE8"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => tempmon_state(6),
      I2 => tempmon_state(7),
      I3 => tempmon_state(8),
      I4 => tempmon_state(9),
      I5 => tempmon_state(10),
      O => \tempmon_state[10]_i_17_n_0\
    );
\tempmon_state[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEAFFFFFFFF"
    )
        port map (
      I0 => \tempmon_state[10]_i_4_n_0\,
      I1 => \tempmon_state[10]_i_5_n_0\,
      I2 => update_temp_102,
      I3 => \tempmon_state[10]_i_6_n_0\,
      I4 => \tempmon_state[10]_i_7_n_0\,
      I5 => \tempmon_state[10]_i_8_n_0\,
      O => tempmon_state_nxt
    );
\tempmon_state[10]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => tempmon_state(9),
      I1 => \tempmon_state[10]_i_8_n_0\,
      I2 => temp_cmp_three_dec_max_102,
      I3 => update_temp_102,
      O => \tempmon_state[10]_i_3_n_0\
    );
\tempmon_state[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF80"
    )
        port map (
      I0 => temp_cmp_four_inc_max_102,
      I1 => update_temp_102,
      I2 => tempmon_state(2),
      I3 => \tempmon_state[10]_i_9_n_0\,
      I4 => \tempmon_state[10]_i_10_n_0\,
      O => \tempmon_state[10]_i_4_n_0\
    );
\tempmon_state[10]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => tempmon_state(6),
      I1 => temp_cmp_neutral_min_102,
      O => \tempmon_state[10]_i_5_n_0\
    );
\tempmon_state[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFAAEAAA"
    )
        port map (
      I0 => \tempmon_state[10]_i_11_n_0\,
      I1 => tempmon_state(3),
      I2 => temp_cmp_three_inc_min_102,
      I3 => update_temp_102,
      I4 => pi_f_dec_i_2_n_0,
      I5 => \tempmon_state[10]_i_12_n_0\,
      O => \tempmon_state[10]_i_6_n_0\
    );
\tempmon_state[10]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAEAAAEAAAEAAA"
    )
        port map (
      I0 => \tempmon_state[10]_i_13_n_0\,
      I1 => temp_cmp_one_dec_min_102,
      I2 => tempmon_state(7),
      I3 => update_temp_102,
      I4 => temp_cmp_two_dec_min_102,
      I5 => tempmon_state(8),
      O => \tempmon_state[10]_i_7_n_0\
    );
\tempmon_state[10]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0012"
    )
        port map (
      I0 => \tempmon_state[10]_i_14_n_0\,
      I1 => \tempmon_state[10]_i_15_n_0\,
      I2 => \tempmon_state[10]_i_16_n_0\,
      I3 => \tempmon_state[10]_i_17_n_0\,
      O => \tempmon_state[10]_i_8_n_0\
    );
\tempmon_state[10]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0808080"
    )
        port map (
      I0 => temp_cmp_two_dec_max_102,
      I1 => tempmon_state(8),
      I2 => update_temp_102,
      I3 => temp_cmp_three_dec_max_102,
      I4 => tempmon_state(9),
      O => \tempmon_state[10]_i_9_n_0\
    );
\tempmon_state[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tempmon_state[10]_i_8_n_0\,
      I1 => tempmon_state(0),
      O => \tempmon_state[1]_i_1_n_0\
    );
\tempmon_state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => tempmon_state(3),
      I1 => \tempmon_state[10]_i_8_n_0\,
      I2 => update_temp_102,
      I3 => temp_cmp_three_inc_max_102,
      O => \tempmon_state[2]_i_1_n_0\
    );
\tempmon_state[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF007000"
    )
        port map (
      I0 => temp_cmp_two_inc_max_102,
      I1 => update_temp_102,
      I2 => tempmon_state(4),
      I3 => \tempmon_state[10]_i_8_n_0\,
      I4 => tempmon_state(2),
      O => \tempmon_state[3]_i_1_n_0\
    );
\tempmon_state[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8FFF000088000000"
    )
        port map (
      I0 => tempmon_state(3),
      I1 => temp_cmp_three_inc_max_102,
      I2 => temp_cmp_one_inc_max_102,
      I3 => update_temp_102,
      I4 => \tempmon_state[10]_i_8_n_0\,
      I5 => tempmon_state(5),
      O => \tempmon_state[4]_i_1_n_0\
    );
\tempmon_state[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8FFF000080800000"
    )
        port map (
      I0 => tempmon_state(4),
      I1 => temp_cmp_two_inc_max_102,
      I2 => update_temp_102,
      I3 => temp_cmp_neutral_max_102,
      I4 => \tempmon_state[10]_i_8_n_0\,
      I5 => tempmon_state(6),
      O => \tempmon_state[5]_i_1_n_0\
    );
\tempmon_state[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EE00AE00EE00"
    )
        port map (
      I0 => tempmon_state(1),
      I1 => tempmon_state(7),
      I2 => temp_cmp_one_dec_max_102,
      I3 => \tempmon_state[10]_i_8_n_0\,
      I4 => update_temp_102,
      I5 => \tempmon_state[6]_i_2_n_0\,
      O => \tempmon_state[6]_i_1_n_0\
    );
\tempmon_state[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => tempmon_state(5),
      I1 => temp_cmp_one_inc_max_102,
      O => \tempmon_state[6]_i_2_n_0\
    );
\tempmon_state[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FC4C00004C4C0000"
    )
        port map (
      I0 => temp_cmp_two_dec_max_102,
      I1 => tempmon_state(8),
      I2 => update_temp_102,
      I3 => temp_cmp_neutral_max_102,
      I4 => \tempmon_state[10]_i_8_n_0\,
      I5 => tempmon_state(6),
      O => \tempmon_state[7]_i_1_n_0\
    );
\tempmon_state[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FC4C00004C4C0000"
    )
        port map (
      I0 => temp_cmp_three_dec_max_102,
      I1 => tempmon_state(9),
      I2 => update_temp_102,
      I3 => temp_cmp_one_dec_max_102,
      I4 => \tempmon_state[10]_i_8_n_0\,
      I5 => tempmon_state(7),
      O => \tempmon_state[8]_i_1_n_0\
    );
\tempmon_state[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF800000"
    )
        port map (
      I0 => update_temp_102,
      I1 => temp_cmp_two_dec_max_102,
      I2 => tempmon_state(8),
      I3 => tempmon_state(10),
      I4 => \tempmon_state[10]_i_8_n_0\,
      O => \tempmon_state[9]_i_1_n_0\
    );
\tempmon_state_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[0]_i_1_n_0\,
      Q => tempmon_state(0),
      S => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[10]_i_3_n_0\,
      Q => tempmon_state(10),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[1]_i_1_n_0\,
      Q => tempmon_state(1),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[2]_i_1_n_0\,
      Q => tempmon_state(2),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[3]_i_1_n_0\,
      Q => tempmon_state(3),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[4]_i_1_n_0\,
      Q => tempmon_state(4),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[5]_i_1_n_0\,
      Q => tempmon_state(5),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[6]_i_1_n_0\,
      Q => tempmon_state(6),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[7]_i_1_n_0\,
      Q => tempmon_state(7),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[8]_i_1_n_0\,
      Q => tempmon_state(8),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\tempmon_state_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => tempmon_state_nxt,
      D => \tempmon_state[9]_i_1_n_0\,
      Q => tempmon_state(9),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\three_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => p_0_in,
      I1 => device_temp_init(0),
      O => \three_dec_max_limit[0]_i_1_n_0\
    );
\three_dec_max_limit[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[10]_i_1_n_0\
    );
\three_dec_max_limit[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[11]_i_1_n_0\
    );
\three_dec_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \three_dec_max_limit[11]_i_3_n_0\
    );
\three_dec_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_inc_max_limit_reg[4]_i_1_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[1]_i_1_n_0\
    );
\three_dec_max_limit[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[2]_i_1_n_0\
    );
\three_dec_max_limit[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[3]_i_1_n_0\
    );
\three_dec_max_limit[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[4]_i_2_n_4\,
      I1 => p_0_in,
      O => \three_dec_max_limit[4]_i_1_n_0\
    );
\three_dec_max_limit[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[5]_i_1_n_0\
    );
\three_dec_max_limit[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_6\,
      I1 => p_0_in,
      O => \three_dec_max_limit[6]_i_1_n_0\
    );
\three_dec_max_limit[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_5\,
      I1 => p_0_in,
      O => \three_dec_max_limit[7]_i_1_n_0\
    );
\three_dec_max_limit[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[8]_i_2_n_4\,
      I1 => p_0_in,
      O => \three_dec_max_limit[8]_i_1_n_0\
    );
\three_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \three_dec_max_limit[8]_i_3_n_0\
    );
\three_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \three_dec_max_limit[8]_i_4_n_0\
    );
\three_dec_max_limit[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \three_dec_max_limit_reg[11]_i_2_n_7\,
      I1 => p_0_in,
      O => \three_dec_max_limit[9]_i_1_n_0\
    );
\three_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[0]_i_1_n_0\,
      Q => three_dec_max_limit(0),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[10]_i_1_n_0\,
      Q => three_dec_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[11]_i_1_n_0\,
      Q => three_dec_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_max_limit_reg[8]_i_2_n_0\,
      CO(3) => p_0_in,
      CO(2) => \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\(2),
      CO(1) => \three_dec_max_limit_reg[11]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => device_temp_init(9),
      O(3) => \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\(3),
      O(2) => \three_dec_max_limit_reg[11]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[11]_i_2_n_6\,
      O(0) => \three_dec_max_limit_reg[11]_i_2_n_7\,
      S(3) => '1',
      S(2 downto 1) => device_temp_init(11 downto 10),
      S(0) => \three_dec_max_limit[11]_i_3_n_0\
    );
\three_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[1]_i_1_n_0\,
      Q => three_dec_max_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[2]_i_1_n_0\,
      Q => three_dec_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[3]_i_1_n_0\,
      Q => three_dec_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[4]_i_1_n_0\,
      Q => three_dec_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_dec_max_limit_reg[4]_i_2_n_0\,
      CO(2) => \three_dec_max_limit_reg[4]_i_2_n_1\,
      CO(1) => \three_dec_max_limit_reg[4]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[4]_i_2_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 0) => B"0000",
      O(3) => \three_dec_max_limit_reg[4]_i_2_n_4\,
      O(2) => \three_dec_max_limit_reg[4]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[4]_i_2_n_6\,
      O(0) => \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\(0),
      S(3 downto 0) => device_temp_init(4 downto 1)
    );
\three_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[5]_i_1_n_0\,
      Q => three_dec_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[6]_i_1_n_0\,
      Q => three_dec_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[7]_i_1_n_0\,
      Q => three_dec_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[8]_i_1_n_0\,
      Q => three_dec_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_max_limit_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_max_limit_reg[4]_i_2_n_0\,
      CO(3) => \three_dec_max_limit_reg[8]_i_2_n_0\,
      CO(2) => \three_dec_max_limit_reg[8]_i_2_n_1\,
      CO(1) => \three_dec_max_limit_reg[8]_i_2_n_2\,
      CO(0) => \three_dec_max_limit_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => device_temp_init(8),
      DI(2) => '0',
      DI(1) => device_temp_init(6),
      DI(0) => '0',
      O(3) => \three_dec_max_limit_reg[8]_i_2_n_4\,
      O(2) => \three_dec_max_limit_reg[8]_i_2_n_5\,
      O(1) => \three_dec_max_limit_reg[8]_i_2_n_6\,
      O(0) => \three_dec_max_limit_reg[8]_i_2_n_7\,
      S(3) => \three_dec_max_limit[8]_i_3_n_0\,
      S(2) => device_temp_init(7),
      S(1) => \three_dec_max_limit[8]_i_4_n_0\,
      S(0) => device_temp_init(5)
    );
\three_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \three_dec_max_limit[9]_i_1_n_0\,
      Q => three_dec_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\three_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(11),
      O => \three_dec_min_limit[11]_i_2_n_0\
    );
\three_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(10),
      O => \three_dec_min_limit[11]_i_3_n_0\
    );
\three_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(5),
      O => \three_dec_min_limit[5]_i_2_n_0\
    );
\three_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(4),
      O => \three_dec_min_limit[5]_i_3_n_0\
    );
\three_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(3),
      O => \three_dec_min_limit[5]_i_4_n_0\
    );
\three_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(9),
      O => \three_dec_min_limit[9]_i_2_n_0\
    );
\three_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(8),
      O => \three_dec_min_limit[9]_i_3_n_0\
    );
\three_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(7),
      O => \three_dec_min_limit[9]_i_4_n_0\
    );
\three_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => two_dec_max_limit(6),
      O => \three_dec_min_limit[9]_i_5_n_0\
    );
\three_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit(0),
      Q => three_dec_min_limit(0),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(10),
      Q => three_dec_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(11),
      Q => three_dec_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \three_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => two_dec_max_limit(10),
      O(3 downto 2) => \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => three_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \three_dec_min_limit[11]_i_2_n_0\,
      S(0) => \three_dec_min_limit[11]_i_3_n_0\
    );
\three_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit(1),
      Q => three_dec_min_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(2),
      Q => three_dec_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(3),
      Q => three_dec_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(4),
      Q => three_dec_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(5),
      Q => three_dec_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \three_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \three_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \three_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => two_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => three_dec_min_limit_nxt(5 downto 2),
      S(3) => \three_dec_min_limit[5]_i_2_n_0\,
      S(2) => \three_dec_min_limit[5]_i_3_n_0\,
      S(1) => \three_dec_min_limit[5]_i_4_n_0\,
      S(0) => two_dec_max_limit(2)
    );
\three_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(6),
      Q => three_dec_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(7),
      Q => three_dec_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(8),
      Q => three_dec_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_dec_min_limit_nxt(9),
      Q => three_dec_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\three_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \three_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \three_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \three_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \three_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => two_dec_max_limit(9 downto 6),
      O(3 downto 0) => three_dec_min_limit_nxt(9 downto 6),
      S(3) => \three_dec_min_limit[9]_i_2_n_0\,
      S(2) => \three_dec_min_limit[9]_i_3_n_0\,
      S(1) => \three_dec_min_limit[9]_i_4_n_0\,
      S(0) => \three_dec_min_limit[9]_i_5_n_0\
    );
\three_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \three_inc_max_limit[11]_i_2_n_0\
    );
\three_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \three_inc_max_limit[11]_i_3_n_0\
    );
\three_inc_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => device_temp_init(0),
      I1 => device_temp_init(1),
      O => three_inc_max_limit_nxt(1)
    );
\three_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \three_inc_max_limit[4]_i_2_n_0\
    );
\three_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(2),
      O => \three_inc_max_limit[4]_i_3_n_0\
    );
\three_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(8),
      O => \three_inc_max_limit[8]_i_2_n_0\
    );
\three_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \three_inc_max_limit[8]_i_3_n_0\
    );
\three_inc_max_limit[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(5),
      O => \three_inc_max_limit[8]_i_4_n_0\
    );
\three_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(10),
      Q => three_inc_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(11),
      Q => three_inc_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \three_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(10),
      DI(0) => '0',
      O(3) => \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => three_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \three_inc_max_limit[11]_i_2_n_0\,
      S(1) => \three_inc_max_limit[11]_i_3_n_0\,
      S(0) => device_temp_init(9)
    );
\three_inc_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(1),
      Q => three_inc_max_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(2),
      Q => three_inc_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(3),
      Q => three_inc_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(4),
      Q => three_inc_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \three_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \three_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => '0',
      DI(2 downto 1) => device_temp_init(3 downto 2),
      DI(0) => '0',
      O(3 downto 1) => three_inc_max_limit_nxt(4 downto 2),
      O(0) => \three_inc_max_limit_reg[4]_i_1_n_7\,
      S(3) => device_temp_init(4),
      S(2) => \three_inc_max_limit[4]_i_2_n_0\,
      S(1) => \three_inc_max_limit[4]_i_3_n_0\,
      S(0) => device_temp_init(1)
    );
\three_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(5),
      Q => three_inc_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(6),
      Q => three_inc_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(7),
      Q => three_inc_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(8),
      Q => three_inc_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \three_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \three_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \three_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \three_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => device_temp_init(8 downto 7),
      DI(1) => '0',
      DI(0) => device_temp_init(5),
      O(3 downto 0) => three_inc_max_limit_nxt(8 downto 5),
      S(3) => \three_inc_max_limit[8]_i_2_n_0\,
      S(2) => \three_inc_max_limit[8]_i_3_n_0\,
      S(1) => device_temp_init(6),
      S(0) => \three_inc_max_limit[8]_i_4_n_0\
    );
\three_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_max_limit_nxt(9),
      Q => three_inc_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(11),
      O => \three_inc_min_limit[11]_i_2_n_0\
    );
\three_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(10),
      O => \three_inc_min_limit[11]_i_3_n_0\
    );
\three_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(5),
      O => \three_inc_min_limit[5]_i_2_n_0\
    );
\three_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(4),
      O => \three_inc_min_limit[5]_i_3_n_0\
    );
\three_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(3),
      O => \three_inc_min_limit[5]_i_4_n_0\
    );
\three_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(9),
      O => \three_inc_min_limit[9]_i_2_n_0\
    );
\three_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(8),
      O => \three_inc_min_limit[9]_i_3_n_0\
    );
\three_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(7),
      O => \three_inc_min_limit[9]_i_4_n_0\
    );
\three_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => four_inc_max_limit(6),
      O => \three_inc_min_limit[9]_i_5_n_0\
    );
\three_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(10),
      Q => three_inc_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(11),
      Q => three_inc_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \three_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => four_inc_max_limit(10),
      O(3 downto 2) => \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => three_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \three_inc_min_limit[11]_i_2_n_0\,
      S(0) => \three_inc_min_limit[11]_i_3_n_0\
    );
\three_inc_min_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit(1),
      Q => three_inc_min_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(2),
      Q => three_inc_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(3),
      Q => three_inc_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(4),
      Q => three_inc_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(5),
      Q => three_inc_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \three_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \three_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \three_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \three_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => four_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => three_inc_min_limit_nxt(5 downto 2),
      S(3) => \three_inc_min_limit[5]_i_2_n_0\,
      S(2) => \three_inc_min_limit[5]_i_3_n_0\,
      S(1) => \three_inc_min_limit[5]_i_4_n_0\,
      S(0) => four_inc_max_limit(2)
    );
\three_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(6),
      Q => three_inc_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(7),
      Q => three_inc_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(8),
      Q => three_inc_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => three_inc_min_limit_nxt(9),
      Q => three_inc_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(1)
    );
\three_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \three_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \three_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \three_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \three_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \three_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => four_inc_max_limit(9 downto 6),
      O(3 downto 0) => three_inc_min_limit_nxt(9 downto 6),
      S(3) => \three_inc_min_limit[9]_i_2_n_0\,
      S(2) => \three_inc_min_limit[9]_i_3_n_0\,
      S(1) => \three_inc_min_limit[9]_i_4_n_0\,
      S(0) => \three_inc_min_limit[9]_i_5_n_0\
    );
\two_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(0),
      O => \two_dec_max_limit[0]_i_1_n_0\
    );
\two_dec_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \two_dec_max_limit[11]_i_2_n_0\
    );
\two_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \two_dec_max_limit[4]_i_2_n_0\
    );
\two_dec_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \two_dec_max_limit[4]_i_3_n_0\
    );
\two_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(6),
      O => \two_dec_max_limit[8]_i_2_n_0\
    );
\two_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \two_dec_max_limit[0]_i_1_n_0\,
      Q => two_dec_max_limit(0),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(10),
      Q => two_dec_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(11),
      Q => two_dec_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \two_dec_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => device_temp_init(9),
      O(3) => \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => two_dec_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2 downto 1) => device_temp_init(11 downto 10),
      S(0) => \two_dec_max_limit[11]_i_2_n_0\
    );
\two_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(1),
      Q => two_dec_max_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(2),
      Q => two_dec_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(3),
      Q => two_dec_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(4),
      Q => two_dec_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_dec_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \two_dec_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \two_dec_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3) => device_temp_init(4),
      DI(2 downto 1) => B"00",
      DI(0) => device_temp_init(1),
      O(3 downto 1) => two_dec_max_limit_nxt(4 downto 2),
      O(0) => \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \two_dec_max_limit[4]_i_2_n_0\,
      S(2 downto 1) => device_temp_init(3 downto 2),
      S(0) => \two_dec_max_limit[4]_i_3_n_0\
    );
\two_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(5),
      Q => two_dec_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(6),
      Q => two_dec_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(7),
      Q => two_dec_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(8),
      Q => two_dec_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \two_dec_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \two_dec_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \two_dec_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \two_dec_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => device_temp_init(6),
      DI(0) => '0',
      O(3 downto 0) => two_dec_max_limit_nxt(8 downto 5),
      S(3 downto 2) => device_temp_init(8 downto 7),
      S(1) => \two_dec_max_limit[8]_i_2_n_0\,
      S(0) => device_temp_init(5)
    );
\two_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_max_limit_nxt(9),
      Q => two_dec_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__17\(0)
    );
\two_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(11),
      O => \two_dec_min_limit[11]_i_2_n_0\
    );
\two_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(10),
      O => \two_dec_min_limit[11]_i_3_n_0\
    );
\two_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(5),
      O => \two_dec_min_limit[5]_i_2_n_0\
    );
\two_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(4),
      O => \two_dec_min_limit[5]_i_3_n_0\
    );
\two_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(3),
      O => \two_dec_min_limit[5]_i_4_n_0\
    );
\two_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(9),
      O => \two_dec_min_limit[9]_i_2_n_0\
    );
\two_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(8),
      O => \two_dec_min_limit[9]_i_3_n_0\
    );
\two_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(7),
      O => \two_dec_min_limit[9]_i_4_n_0\
    );
\two_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => one_dec_max_limit(6),
      O => \two_dec_min_limit[9]_i_5_n_0\
    );
\two_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(10),
      Q => two_dec_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(11),
      Q => two_dec_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \two_dec_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => one_dec_max_limit(10),
      O(3 downto 2) => \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => two_dec_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \two_dec_min_limit[11]_i_2_n_0\,
      S(0) => \two_dec_min_limit[11]_i_3_n_0\
    );
\two_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(2),
      Q => two_dec_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(3),
      Q => two_dec_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(4),
      Q => two_dec_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(5),
      Q => two_dec_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_dec_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \two_dec_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \two_dec_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \two_dec_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => one_dec_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => two_dec_min_limit_nxt(5 downto 2),
      S(3) => \two_dec_min_limit[5]_i_2_n_0\,
      S(2) => \two_dec_min_limit[5]_i_3_n_0\,
      S(1) => \two_dec_min_limit[5]_i_4_n_0\,
      S(0) => one_dec_max_limit(2)
    );
\two_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(6),
      Q => two_dec_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(7),
      Q => two_dec_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(8),
      Q => two_dec_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_dec_min_limit_nxt(9),
      Q => two_dec_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(3)
    );
\two_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_dec_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \two_dec_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \two_dec_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \two_dec_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \two_dec_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => one_dec_max_limit(9 downto 6),
      O(3 downto 0) => two_dec_min_limit_nxt(9 downto 6),
      S(3) => \two_dec_min_limit[9]_i_2_n_0\,
      S(2) => \two_dec_min_limit[9]_i_3_n_0\,
      S(1) => \two_dec_min_limit[9]_i_4_n_0\,
      S(0) => \two_dec_min_limit[9]_i_5_n_0\
    );
\two_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(11),
      O => \two_inc_max_limit[11]_i_2_n_0\
    );
\two_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(10),
      O => \two_inc_max_limit[11]_i_3_n_0\
    );
\two_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(9),
      O => \two_inc_max_limit[11]_i_4_n_0\
    );
\two_inc_max_limit[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => device_temp_init(0),
      I1 => device_temp_init(1),
      O => \two_inc_max_limit[1]_i_1_n_0\
    );
\two_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(4),
      O => \two_inc_max_limit[4]_i_2_n_0\
    );
\two_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(3),
      O => \two_inc_max_limit[4]_i_3_n_0\
    );
\two_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(1),
      O => \two_inc_max_limit[4]_i_4_n_0\
    );
\two_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_init(7),
      O => \two_inc_max_limit[8]_i_2_n_0\
    );
\two_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(10),
      Q => two_inc_max_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(11),
      Q => two_inc_max_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_max_limit_reg[8]_i_1_n_0\,
      CO(3 downto 2) => \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \two_inc_max_limit_reg[11]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => device_temp_init(10 downto 9),
      O(3) => \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => two_inc_max_limit_nxt(11 downto 9),
      S(3) => '0',
      S(2) => \two_inc_max_limit[11]_i_2_n_0\,
      S(1) => \two_inc_max_limit[11]_i_3_n_0\,
      S(0) => \two_inc_max_limit[11]_i_4_n_0\
    );
\two_inc_max_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \two_inc_max_limit[1]_i_1_n_0\,
      Q => two_inc_max_limit(1),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(2),
      Q => two_inc_max_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(3),
      Q => two_inc_max_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(4),
      Q => two_inc_max_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_inc_max_limit_reg[4]_i_1_n_0\,
      CO(2) => \two_inc_max_limit_reg[4]_i_1_n_1\,
      CO(1) => \two_inc_max_limit_reg[4]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[4]_i_1_n_3\,
      CYINIT => device_temp_init(0),
      DI(3 downto 2) => device_temp_init(4 downto 3),
      DI(1) => '0',
      DI(0) => device_temp_init(1),
      O(3 downto 1) => two_inc_max_limit_nxt(4 downto 2),
      O(0) => \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \two_inc_max_limit[4]_i_2_n_0\,
      S(2) => \two_inc_max_limit[4]_i_3_n_0\,
      S(1) => device_temp_init(2),
      S(0) => \two_inc_max_limit[4]_i_4_n_0\
    );
\two_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(5),
      Q => two_inc_max_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(6),
      Q => two_inc_max_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(7),
      Q => two_inc_max_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(8),
      Q => two_inc_max_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_max_limit_reg[4]_i_1_n_0\,
      CO(3) => \two_inc_max_limit_reg[8]_i_1_n_0\,
      CO(2) => \two_inc_max_limit_reg[8]_i_1_n_1\,
      CO(1) => \two_inc_max_limit_reg[8]_i_1_n_2\,
      CO(0) => \two_inc_max_limit_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => device_temp_init(7),
      DI(1 downto 0) => B"00",
      O(3 downto 0) => two_inc_max_limit_nxt(8 downto 5),
      S(3) => device_temp_init(8),
      S(2) => \two_inc_max_limit[8]_i_2_n_0\,
      S(1 downto 0) => device_temp_init(6 downto 5)
    );
\two_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_max_limit_nxt(9),
      Q => two_inc_max_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__15\(0)
    );
\two_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(11),
      O => \two_inc_min_limit[11]_i_2_n_0\
    );
\two_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(10),
      O => \two_inc_min_limit[11]_i_3_n_0\
    );
\two_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(5),
      O => \two_inc_min_limit[5]_i_2_n_0\
    );
\two_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(4),
      O => \two_inc_min_limit[5]_i_3_n_0\
    );
\two_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(3),
      O => \two_inc_min_limit[5]_i_4_n_0\
    );
\two_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(9),
      O => \two_inc_min_limit[9]_i_2_n_0\
    );
\two_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(8),
      O => \two_inc_min_limit[9]_i_3_n_0\
    );
\two_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(7),
      O => \two_inc_min_limit[9]_i_4_n_0\
    );
\two_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => three_inc_max_limit(6),
      O => \two_inc_min_limit[9]_i_5_n_0\
    );
\two_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(10),
      Q => two_inc_min_limit(10),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(11),
      Q => two_inc_min_limit(11),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_min_limit_reg[9]_i_1_n_0\,
      CO(3 downto 1) => \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \two_inc_min_limit_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => three_inc_max_limit(10),
      O(3 downto 2) => \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => two_inc_min_limit_nxt(11 downto 10),
      S(3 downto 2) => B"00",
      S(1) => \two_inc_min_limit[11]_i_2_n_0\,
      S(0) => \two_inc_min_limit[11]_i_3_n_0\
    );
\two_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(2),
      Q => two_inc_min_limit(2),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(3),
      Q => two_inc_min_limit(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(4),
      Q => two_inc_min_limit(4),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(5),
      Q => two_inc_min_limit(5),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \two_inc_min_limit_reg[5]_i_1_n_0\,
      CO(2) => \two_inc_min_limit_reg[5]_i_1_n_1\,
      CO(1) => \two_inc_min_limit_reg[5]_i_1_n_2\,
      CO(0) => \two_inc_min_limit_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => three_inc_max_limit(5 downto 3),
      DI(0) => '0',
      O(3 downto 0) => two_inc_min_limit_nxt(5 downto 2),
      S(3) => \two_inc_min_limit[5]_i_2_n_0\,
      S(2) => \two_inc_min_limit[5]_i_3_n_0\,
      S(1) => \two_inc_min_limit[5]_i_4_n_0\,
      S(0) => three_inc_max_limit(2)
    );
\two_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(6),
      Q => two_inc_min_limit(6),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(7),
      Q => two_inc_min_limit(7),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(8),
      Q => two_inc_min_limit(8),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => two_inc_min_limit_nxt(9),
      Q => two_inc_min_limit(9),
      R => \rstdiv0_sync_r1_reg_rep__13\(2)
    );
\two_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \two_inc_min_limit_reg[5]_i_1_n_0\,
      CO(3) => \two_inc_min_limit_reg[9]_i_1_n_0\,
      CO(2) => \two_inc_min_limit_reg[9]_i_1_n_1\,
      CO(1) => \two_inc_min_limit_reg[9]_i_1_n_2\,
      CO(0) => \two_inc_min_limit_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => three_inc_max_limit(9 downto 6),
      O(3 downto 0) => two_inc_min_limit_nxt(9 downto 6),
      S(3) => \two_inc_min_limit[9]_i_2_n_0\,
      S(2) => \two_inc_min_limit[9]_i_3_n_0\,
      S(1) => \two_inc_min_limit[9]_i_4_n_0\,
      S(0) => \two_inc_min_limit[9]_i_5_n_0\
    );
update_temp_101: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => tempmon_sample_en_102,
      I1 => tempmon_init_complete,
      I2 => tempmon_sample_en_101,
      O => \update_temp_101__0\
    );
update_temp_102_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \update_temp_101__0\,
      Q => update_temp_102,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_wrcal is
  port (
    wrcal_resume_w : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wrcal_prech_req : out STD_LOGIC;
    wrcal_done_reg_0 : out STD_LOGIC;
    wrcal_sanity_chk_done_reg_0 : out STD_LOGIC;
    wrlvl_byte_redo : out STD_LOGIC;
    early1_data_reg_0 : out STD_LOGIC;
    early2_data_reg_0 : out STD_LOGIC;
    phy_if_reset_w : out STD_LOGIC;
    LD0 : out STD_LOGIC;
    LD0_0 : out STD_LOGIC;
    LD0_1 : out STD_LOGIC;
    LD0_2 : out STD_LOGIC;
    \corse_cnt_reg[0][2]\ : out STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][2][4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \corse_cnt_reg[1][2]\ : out STD_LOGIC;
    \corse_cnt_reg[2][2]\ : out STD_LOGIC;
    \init_state_r_reg[2]\ : out STD_LOGIC;
    \corse_cnt_reg[3][2]\ : out STD_LOGIC;
    \corse_cnt_reg[6][2]\ : out STD_LOGIC;
    \corse_cnt_reg[7][2]\ : out STD_LOGIC;
    \corse_cnt_reg[5][2]\ : out STD_LOGIC;
    \corse_cnt_reg[4][2]\ : out STD_LOGIC;
    done_dqs_dec239_out : out STD_LOGIC;
    \dqs_count_r_reg[2]_rep__0\ : out STD_LOGIC;
    \init_state_r_reg[0]\ : out STD_LOGIC;
    \init_state_r_reg[3]\ : out STD_LOGIC;
    \init_state_r_reg[4]\ : out STD_LOGIC;
    \idelay_tap_cnt_r_reg[0][7][4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][3][4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][0][4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][1][4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][2][4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][6][4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][5][4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \idelay_tap_cnt_r_reg[0][4][4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    LD0_3 : out STD_LOGIC;
    LD0_4 : out STD_LOGIC;
    LD0_6 : out STD_LOGIC;
    LD0_8 : out STD_LOGIC;
    \FSM_sequential_wl_state_r_reg[2]\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    phy_rddata_en : in STD_LOGIC;
    wrcal_sanity_chk : in STD_LOGIC;
    p_0_out : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_3\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_4\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_5\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_6\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_7\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_8\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_9\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_10\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_11\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_12\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_13\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_14\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_15\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_16\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_17\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_18\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_19\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_20\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_21\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_22\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_23\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_24\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_25\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_26\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_27\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_28\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_29\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_30\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_31\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_32\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_33\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_34\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_35\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_36\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_37\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_38\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_39\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_40\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_41\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_42\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_43\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_44\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_45\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_46\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_47\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_48\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_49\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_50\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_51\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_52\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_53\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_54\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_55\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_56\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_57\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_58\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_59\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_60\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_61\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_62\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__13\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrlvl_byte_done : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    calib_in_common : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    idelay_ld_rst : in STD_LOGIC;
    idelay_ld_rst_10 : in STD_LOGIC;
    idelay_ld_rst_11 : in STD_LOGIC;
    idelay_ld_rst_12 : in STD_LOGIC;
    wrlvl_byte_redo_r : in STD_LOGIC;
    pi_dqs_found_done : in STD_LOGIC;
    wrlvl_done_r1 : in STD_LOGIC;
    idelay_ce_int : in STD_LOGIC;
    p_0_in : in STD_LOGIC;
    rdlvl_stg1_done_reg : in STD_LOGIC;
    ddr3_lm_done_r : in STD_LOGIC;
    \cal1_cnt_cpt_r_reg[2]\ : in STD_LOGIC;
    cal1_dq_idel_ce_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__22\ : in STD_LOGIC;
    \cal1_cnt_cpt_r_reg[2]_0\ : in STD_LOGIC;
    \cal1_cnt_cpt_r_reg[1]\ : in STD_LOGIC;
    \cal1_cnt_cpt_r_reg[0]\ : in STD_LOGIC;
    cal1_dq_idel_ce_reg_0 : in STD_LOGIC;
    idelay_ld_rst_13 : in STD_LOGIC;
    idelay_ld_rst_14 : in STD_LOGIC;
    wr_level_done_r5 : in STD_LOGIC;
    wl_sm_start : in STD_LOGIC;
    wrcal_rd_wait : in STD_LOGIC;
    prech_done : in STD_LOGIC;
    wrcal_start_reg : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_wrcal : entity is "mig_7series_v2_3_ddr_phy_wrcal";
end mig_7series_0_mig_7series_v2_3_ddr_phy_wrcal;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_wrcal is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cal2_done_r : STD_LOGIC;
  signal cal2_done_r_i_1_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_1_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_2_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_3_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_4_n_0 : STD_LOGIC;
  signal cal2_if_reset_i_5_n_0 : STD_LOGIC;
  signal cal2_prech_req_r : STD_LOGIC;
  signal cal2_prech_req_r_i_1_n_0 : STD_LOGIC;
  signal cal2_prech_req_r_i_2_n_0 : STD_LOGIC;
  signal cal2_state_r : STD_LOGIC;
  signal \cal2_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \cal2_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg[1]_i_1_n_0\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \cal2_state_r_reg_n_0_[3]\ : STD_LOGIC;
  signal early1_data_i_1_n_0 : STD_LOGIC;
  signal early1_data_i_2_n_0 : STD_LOGIC;
  signal early1_data_i_3_n_0 : STD_LOGIC;
  signal \early1_data_match_r0__0\ : STD_LOGIC;
  signal \^early1_data_reg_0\ : STD_LOGIC;
  signal early1_match_fall0_and_r : STD_LOGIC;
  signal early1_match_fall1_and_r : STD_LOGIC;
  signal early1_match_fall2_and_r : STD_LOGIC;
  signal early1_match_fall3_and_r : STD_LOGIC;
  signal early1_match_rise0_and_r : STD_LOGIC;
  signal early1_match_rise1_and_r : STD_LOGIC;
  signal early1_match_rise2_and_r : STD_LOGIC;
  signal early1_match_rise3_and_r : STD_LOGIC;
  signal early2_data_i_1_n_0 : STD_LOGIC;
  signal \early2_data_match_r0__0\ : STD_LOGIC;
  signal \^early2_data_reg_0\ : STD_LOGIC;
  signal early2_match_fall0_and_r : STD_LOGIC;
  signal early2_match_fall1_and_r : STD_LOGIC;
  signal early2_match_fall2_and_r : STD_LOGIC;
  signal early2_match_fall3_and_r : STD_LOGIC;
  signal early2_match_rise0_and_r : STD_LOGIC;
  signal early2_match_rise1_and_r : STD_LOGIC;
  signal early2_match_rise2_and_r : STD_LOGIC;
  signal early2_match_rise3_and_r : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_r_i_2_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_63\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_103\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_79\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_55\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_95\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_47\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_71\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_87\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_64\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_104\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_80\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_56\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_96\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_48\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_72\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_88\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_65\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_105\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_81\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_57\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_97\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_49\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_73\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_89\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_66\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_106\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_82\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_58\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_98\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_50\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_74\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_90\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_67\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_107\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_83\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_59\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_99\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_51\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_75\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_91\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_68\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_108\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_84\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_60\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_100\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_52\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_76\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_92\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_69\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_109\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_85\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_61\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_101\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_53\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_77\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_93\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_70\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_110\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_86\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_62\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_102\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_54\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_78\ : STD_LOGIC;
  signal \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_94\ : STD_LOGIC;
  signal idelay_ld : STD_LOGIC;
  signal idelay_ld_done_i_1_n_0 : STD_LOGIC;
  signal idelay_ld_done_i_2_n_0 : STD_LOGIC;
  signal idelay_ld_done_reg_n_0 : STD_LOGIC;
  signal idelay_ld_i_1_n_0 : STD_LOGIC;
  signal idelay_ld_i_2_n_0 : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][0][4]_i_3_n_0\ : STD_LOGIC;
  signal \idelay_tap_cnt_r[0][4][4]_i_2_n_0\ : STD_LOGIC;
  signal \^idelay_tap_cnt_r_reg[0][2][4]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \not_empty_wait_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \not_empty_wait_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal p_0_in_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_1_in : STD_LOGIC;
  signal \pat_data_match_r0__0\ : STD_LOGIC;
  signal pat_match_fall0_and_r : STD_LOGIC;
  signal pat_match_fall1_and_r : STD_LOGIC;
  signal pat_match_fall2_and_r : STD_LOGIC;
  signal pat_match_fall3_and_r : STD_LOGIC;
  signal pat_match_rise0_and_r : STD_LOGIC;
  signal pat_match_rise1_and_r : STD_LOGIC;
  signal pat_match_rise2_and_r : STD_LOGIC;
  signal pat_match_rise3_and_r : STD_LOGIC;
  signal \^phy_if_reset_w\ : STD_LOGIC;
  signal rd_active_r1 : STD_LOGIC;
  signal rd_active_r3_reg_srl2_n_0 : STD_LOGIC;
  signal \tap_inc_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \tap_inc_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrcal_done_i_1_n_0 : STD_LOGIC;
  signal \^wrcal_done_reg_0\ : STD_LOGIC;
  signal wrcal_dqs_cnt_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \wrcal_dqs_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \wrcal_dqs_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
  signal wrcal_pat_resume_r : STD_LOGIC;
  signal wrcal_pat_resume_r2_reg_srl2_n_0 : STD_LOGIC;
  signal wrcal_pat_resume_r_i_1_n_0 : STD_LOGIC;
  signal wrcal_pat_resume_r_i_2_n_0 : STD_LOGIC;
  signal wrcal_pat_resume_r_i_3_n_0 : STD_LOGIC;
  signal wrcal_sanity_chk_done_i_1_n_0 : STD_LOGIC;
  signal \^wrcal_sanity_chk_done_reg_0\ : STD_LOGIC;
  signal wrcal_sanity_chk_r_reg_n_0 : STD_LOGIC;
  signal wrlvl_byte_done_r : STD_LOGIC;
  signal \^wrlvl_byte_redo\ : STD_LOGIC;
  signal wrlvl_byte_redo_i_1_n_0 : STD_LOGIC;
  signal wrlvl_byte_redo_i_2_n_0 : STD_LOGIC;
  signal wrlvl_byte_redo_i_3_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_9\ : label is "soft_lutpair444";
  attribute SOFT_HLUTNM of cal2_done_r_i_2 : label is "soft_lutpair427";
  attribute SOFT_HLUTNM of cal2_prech_req_r_i_2 : label is "soft_lutpair436";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_10\ : label is "soft_lutpair431";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_6\ : label is "soft_lutpair427";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_7\ : label is "soft_lutpair438";
  attribute SOFT_HLUTNM of \cal2_state_r[3]_i_9\ : label is "soft_lutpair437";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_11\ : label is "soft_lutpair445";
  attribute SOFT_HLUTNM of early1_data_i_3 : label is "soft_lutpair437";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall1_and_r_i_2\ : label is "soft_lutpair432";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall3_and_r_i_2\ : label is "soft_lutpair428";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise1_and_r_i_2\ : label is "soft_lutpair435";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise2_and_r_i_1\ : label is "soft_lutpair434";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall0_and_r_i_2\ : label is "soft_lutpair433";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall1_and_r_i_1\ : label is "soft_lutpair432";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall3_and_r_i_1\ : label is "soft_lutpair428";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise0_and_r_i_2\ : label is "soft_lutpair429";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise1_and_r_i_1\ : label is "soft_lutpair435";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise2_and_r_i_2\ : label is "soft_lutpair434";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_fall0_and_r_i_1\ : label is "soft_lutpair433";
  attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_rise0_and_r_i_1\ : label is "soft_lutpair429";
  attribute SOFT_HLUTNM of idelay_ld_done_i_2 : label is "soft_lutpair438";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][0][4]_i_3\ : label is "soft_lutpair439";
  attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][4][4]_i_2\ : label is "soft_lutpair439";
  attribute SOFT_HLUTNM of \init_state_r[2]_i_31\ : label is "soft_lutpair440";
  attribute SOFT_HLUTNM of \init_state_r[3]_i_20\ : label is "soft_lutpair440";
  attribute SOFT_HLUTNM of \init_state_r[4]_i_32\ : label is "soft_lutpair444";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[0]_i_1\ : label is "soft_lutpair447";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[1]_i_1\ : label is "soft_lutpair447";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[2]_i_1\ : label is "soft_lutpair441";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[3]_i_1\ : label is "soft_lutpair441";
  attribute SOFT_HLUTNM of \not_empty_wait_cnt[4]_i_2\ : label is "soft_lutpair431";
  attribute srl_name : string;
  attribute srl_name of rd_active_r3_reg_srl2 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3_reg_srl2 ";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[0]_i_1\ : label is "soft_lutpair446";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[1]_i_1\ : label is "soft_lutpair446";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[2]_i_1\ : label is "soft_lutpair442";
  attribute SOFT_HLUTNM of \tap_inc_wait_cnt[3]_i_2\ : label is "soft_lutpair442";
  attribute SOFT_HLUTNM of \wl_tap_count_r[5]_i_3\ : label is "soft_lutpair445";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[0]_i_1\ : label is "soft_lutpair443";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[1]_i_1\ : label is "soft_lutpair443";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[2]_i_1\ : label is "soft_lutpair436";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[3]_i_3\ : label is "soft_lutpair430";
  attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[3]_i_5\ : label is "soft_lutpair430";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[0]\ : label is "10";
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[1]\ : label is "10";
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[2]\ : label is "10";
  attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[3]\ : label is "10";
  attribute srl_name of wrcal_pat_resume_r2_reg_srl2 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 ";
begin
  E(0) <= \^e\(0);
  early1_data_reg_0 <= \^early1_data_reg_0\;
  early2_data_reg_0 <= \^early2_data_reg_0\;
  \idelay_tap_cnt_r_reg[0][2][4]\(3 downto 0) <= \^idelay_tap_cnt_r_reg[0][2][4]\(3 downto 0);
  phy_if_reset_w <= \^phy_if_reset_w\;
  wrcal_done_reg_0 <= \^wrcal_done_reg_0\;
  wrcal_sanity_chk_done_reg_0 <= \^wrcal_sanity_chk_done_reg_0\;
  wrlvl_byte_redo <= \^wrlvl_byte_redo\;
\FSM_sequential_wl_state_r[2]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^wrlvl_byte_redo\,
      I1 => wr_level_done_r5,
      I2 => wl_sm_start,
      O => \FSM_sequential_wl_state_r_reg[2]\
    );
cal2_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => p_1_in,
      I1 => \cal2_state_r_reg_n_0_[3]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => cal2_done_r,
      O => cal2_done_r_i_1_n_0
    );
cal2_done_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wrcal_sanity_chk_r_reg_n_0,
      I1 => wrcal_sanity_chk,
      O => p_1_in
    );
cal2_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_done_r_i_1_n_0,
      Q => cal2_done_r,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
cal2_if_reset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBABF00008A80"
    )
        port map (
      I0 => cal2_if_reset_i_2_n_0,
      I1 => cal2_if_reset_i_3_n_0,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      I3 => cal2_if_reset_i_4_n_0,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      I5 => \^phy_if_reset_w\,
      O => cal2_if_reset_i_1_n_0
    );
cal2_if_reset_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"004F0040F000F000"
    )
        port map (
      I0 => \^e\(0),
      I1 => rd_active_r1,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => cal2_if_reset_i_2_n_0
    );
cal2_if_reset_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000008FF08FF"
    )
        port map (
      I0 => wrlvl_byte_done,
      I1 => rd_active_r1,
      I2 => \^e\(0),
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => idelay_ld_done_i_2_n_0,
      I5 => \cal2_state_r_reg_n_0_[2]\,
      O => cal2_if_reset_i_3_n_0
    );
cal2_if_reset_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF80FFFFFF800000"
    )
        port map (
      I0 => wrcal_sanity_chk_r_reg_n_0,
      I1 => cal2_prech_req_r_i_2_n_0,
      I2 => prech_done,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => cal2_if_reset_i_5_n_0,
      O => cal2_if_reset_i_4_n_0
    );
cal2_if_reset_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(2),
      I1 => \tap_inc_wait_cnt_reg__0\(0),
      I2 => \tap_inc_wait_cnt_reg__0\(1),
      I3 => \tap_inc_wait_cnt_reg__0\(3),
      I4 => \cal2_state_r_reg_n_0_[2]\,
      I5 => wrcal_start_reg,
      O => cal2_if_reset_i_5_n_0
    );
cal2_if_reset_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_if_reset_i_1_n_0,
      Q => \^phy_if_reset_w\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
cal2_prech_req_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010110000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => cal2_prech_req_r_i_2_n_0,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => \cal2_state_r_reg_n_0_[0]\,
      O => cal2_prech_req_r_i_1_n_0
    );
cal2_prech_req_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I3 => wrcal_dqs_cnt_r(3),
      O => cal2_prech_req_r_i_2_n_0
    );
cal2_prech_req_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_prech_req_r_i_1_n_0,
      Q => cal2_prech_req_r,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\cal2_state_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF5D005D"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r[0]_i_4_n_0\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[0]_i_2_n_0\
    );
\cal2_state_r[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CCE2"
    )
        port map (
      I0 => \cal2_state_r[0]_i_5_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \tap_inc_wait_cnt_reg__0\(0),
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[0]_i_3_n_0\
    );
\cal2_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF7FFF"
    )
        port map (
      I0 => prech_done,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I3 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I4 => wrcal_dqs_cnt_r(3),
      I5 => \cal2_state_r_reg_n_0_[2]\,
      O => \cal2_state_r[0]_i_4_n_0\
    );
\cal2_state_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000555100000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      O => \cal2_state_r[0]_i_5_n_0\
    );
\cal2_state_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F0050D0"
    )
        port map (
      I0 => prech_done,
      I1 => cal2_prech_req_r_i_2_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      I4 => \cal2_state_r_reg_n_0_[2]\,
      O => \cal2_state_r[1]_i_2_n_0\
    );
\cal2_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFA800A8"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I1 => \cal2_state_r[1]_i_4_n_0\,
      I2 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => \tap_inc_wait_cnt_reg__0\(1),
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => \cal2_state_r[1]_i_3_n_0\
    );
\cal2_state_r[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      O => \cal2_state_r[1]_i_4_n_0\
    );
\cal2_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4AFFFF4F4A0000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[1]\,
      I1 => \tap_inc_wait_cnt_reg__0\(2),
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r[2]_i_2_n_0\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r[2]_i_3_n_0\,
      O => \cal2_state_r[2]_i_1_n_0\
    );
\cal2_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      O => \cal2_state_r[2]_i_2_n_0\
    );
\cal2_state_r[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F00D0D0"
    )
        port map (
      I0 => prech_done,
      I1 => cal2_prech_req_r_i_2_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      I4 => \cal2_state_r_reg_n_0_[2]\,
      O => \cal2_state_r[2]_i_3_n_0\
    );
\cal2_state_r[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[3]\,
      O => \cal2_state_r[3]_i_10_n_0\
    );
\cal2_state_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E2FFFF00E20000"
    )
        port map (
      I0 => \cal2_state_r[3]_i_5_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \tap_inc_wait_cnt_reg__0\(3),
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[3]_i_2_n_0\
    );
\cal2_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45404F4F45404A4A"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r[3]_i_6_n_0\,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => \cal2_state_r[3]_i_7_n_0\,
      I4 => \cal2_state_r_reg_n_0_[2]\,
      I5 => wrcal_start_reg,
      O => \cal2_state_r[3]_i_3_n_0\
    );
\cal2_state_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \cal2_state_r[3]_i_8_n_0\,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => \cal2_state_r[3]_i_9_n_0\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => \cal2_state_r[3]_i_7_n_0\,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => \cal2_state_r[3]_i_4_n_0\
    );
\cal2_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55550004FFFFFFFF"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      O => \cal2_state_r[3]_i_5_n_0\
    );
\cal2_state_r[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"33BB3088"
    )
        port map (
      I0 => wrcal_sanity_chk,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \wrcal_dqs_cnt_r[3]_i_5_n_0\,
      I3 => wrcal_sanity_chk_r_reg_n_0,
      I4 => prech_done,
      O => \cal2_state_r[3]_i_6_n_0\
    );
\cal2_state_r[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(2),
      I1 => \tap_inc_wait_cnt_reg__0\(0),
      I2 => \tap_inc_wait_cnt_reg__0\(1),
      I3 => \tap_inc_wait_cnt_reg__0\(3),
      O => \cal2_state_r[3]_i_7_n_0\
    );
\cal2_state_r[3]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBBB888"
    )
        port map (
      I0 => idelay_ld_done_i_2_n_0,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[4]\,
      I3 => \cal2_state_r[3]_i_10_n_0\,
      I4 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      O => \cal2_state_r[3]_i_8_n_0\
    );
\cal2_state_r[3]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^e\(0),
      I1 => rd_active_r1,
      I2 => wrlvl_byte_done,
      O => \cal2_state_r[3]_i_9_n_0\
    );
\cal2_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r_reg[0]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\cal2_state_r_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[0]_i_2_n_0\,
      I1 => \cal2_state_r[0]_i_3_n_0\,
      O => \cal2_state_r_reg[0]_i_1_n_0\,
      S => \cal2_state_r_reg_n_0_[0]\
    );
\cal2_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r_reg[1]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\cal2_state_r_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[1]_i_2_n_0\,
      I1 => \cal2_state_r[1]_i_3_n_0\,
      O => \cal2_state_r_reg[1]_i_1_n_0\,
      S => \cal2_state_r_reg_n_0_[0]\
    );
\cal2_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r[2]_i_1_n_0\,
      Q => \cal2_state_r_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\cal2_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => cal2_state_r,
      D => \cal2_state_r[3]_i_2_n_0\,
      Q => \cal2_state_r_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\cal2_state_r_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \cal2_state_r[3]_i_3_n_0\,
      I1 => \cal2_state_r[3]_i_4_n_0\,
      O => cal2_state_r,
      S => \cal2_state_r_reg_n_0_[0]\
    );
\corse_cnt[0][2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I1 => wrlvl_byte_redo_r,
      I2 => \^wrlvl_byte_redo\,
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I4 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      I5 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      O => \corse_cnt_reg[0][2]\
    );
\corse_cnt[1][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      I2 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I4 => wrlvl_byte_redo_r,
      I5 => \^wrlvl_byte_redo\,
      O => \corse_cnt_reg[1][2]\
    );
\corse_cnt[2][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I1 => wrlvl_byte_redo_r,
      I2 => \^wrlvl_byte_redo\,
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I4 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      I5 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      O => \corse_cnt_reg[2][2]\
    );
\corse_cnt[3][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      I2 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I4 => wrlvl_byte_redo_r,
      I5 => \^wrlvl_byte_redo\,
      O => \corse_cnt_reg[3][2]\
    );
\corse_cnt[4][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I1 => wrlvl_byte_redo_r,
      I2 => \^wrlvl_byte_redo\,
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I4 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      I5 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      O => \corse_cnt_reg[4][2]\
    );
\corse_cnt[5][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040000000000"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I1 => \^wrlvl_byte_redo\,
      I2 => wrlvl_byte_redo_r,
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I4 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      I5 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      O => \corse_cnt_reg[5][2]\
    );
\corse_cnt[6][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I1 => wrlvl_byte_redo_r,
      I2 => \^wrlvl_byte_redo\,
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I4 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      I5 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      O => \corse_cnt_reg[6][2]\
    );
\corse_cnt[7][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I1 => \^wrlvl_byte_redo\,
      I2 => wrlvl_byte_redo_r,
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I4 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      I5 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      O => \corse_cnt_reg[7][2]\
    );
\dqs_count_r[2]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^wrlvl_byte_redo\,
      I1 => p_0_in,
      O => \dqs_count_r_reg[2]_rep__0\
    );
early1_data_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => early1_data_i_2_n_0,
      I3 => \^early1_data_reg_0\,
      O => early1_data_i_1_n_0
    );
early1_data_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45400000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => early1_data_i_3_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrlvl_byte_redo_i_3_n_0,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      O => early1_data_i_2_n_0
    );
early1_data_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => wrlvl_byte_done,
      I1 => rd_active_r1,
      I2 => \^e\(0),
      I3 => \cal2_state_r_reg_n_0_[2]\,
      O => early1_data_i_3_n_0
    );
early1_data_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => early1_data_i_1_n_0,
      Q => \^early1_data_reg_0\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
early2_data_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => early1_data_i_2_n_0,
      I4 => \^early2_data_reg_0\,
      O => early2_data_i_1_n_0
    );
early2_data_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => early2_data_i_1_n_0,
      Q => \^early2_data_reg_0\,
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_15\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_55\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_31\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_7\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_47\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_out,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_23\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_39\,
      Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_16\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_56\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_32\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_8\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_48\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_0\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_24\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_40\,
      Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_17\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_57\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_33\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_9\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_49\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_1\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_25\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_41\,
      Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_18\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_58\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_34\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_10\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_50\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_2\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_26\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_42\,
      Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_19\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_59\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_35\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_11\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_51\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_3\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_27\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_43\,
      Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_20\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_60\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_36\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_12\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_52\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_4\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_28\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_44\,
      Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_21\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_61\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_37\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_13\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_53\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_5\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_29\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_45\,
      Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_22\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_62\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_38\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_14\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_54\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_6\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_30\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_stg2_wrcal_cnt_reg[2]_46\,
      Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      R => '0'
    );
\gen_pat_match_div4.early1_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early1_match_rise2_and_r,
      I1 => early1_match_rise3_and_r,
      I2 => early1_match_fall1_and_r,
      I3 => early1_match_rise1_and_r,
      I4 => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\,
      O => \early1_data_match_r0__0\
    );
\gen_pat_match_div4.early1_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early1_match_rise0_and_r,
      I1 => early1_match_fall3_and_r,
      I2 => early1_match_fall0_and_r,
      I3 => early1_match_fall2_and_r,
      O => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \early1_data_match_r0__0\,
      Q => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\,
      Q => early1_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\,
      Q => early1_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\,
      Q => early1_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg\,
      O => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\,
      Q => early1_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\,
      Q => early1_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\,
      Q => early1_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\,
      Q => early1_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\,
      Q => early1_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => early2_match_fall0_and_r,
      I1 => early2_match_rise2_and_r,
      I2 => early2_match_fall3_and_r,
      I3 => early2_match_rise1_and_r,
      I4 => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\,
      O => \early2_data_match_r0__0\
    );
\gen_pat_match_div4.early2_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => early2_match_rise3_and_r,
      I1 => early2_match_fall2_and_r,
      I2 => early2_match_fall1_and_r,
      I3 => early2_match_rise0_and_r,
      O => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \early2_data_match_r0__0\,
      Q => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg\,
      O => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg\,
      O => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\,
      Q => early2_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg\,
      O => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\,
      Q => early2_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg\,
      O => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\,
      Q => early2_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg\,
      O => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\,
      Q => early2_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg\,
      O => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg\,
      O => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\,
      Q => early2_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg\,
      O => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\,
      Q => early2_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg\,
      O => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg\,
      O => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\,
      Q => early2_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.early2_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.early2_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg\,
      O => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\
    );
\gen_pat_match_div4.early2_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\,
      Q => early2_match_rise3_and_r,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_63\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_103\,
      O => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_55\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_95\,
      O => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_47\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_79\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_87\,
      O => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_63\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_103\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_79\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_55\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_95\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_47\,
      O => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_71\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_87\,
      Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_104\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_56\,
      O => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_48\,
      O => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_88\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_64\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_80\,
      O => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_96\,
      O => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_72\,
      Q => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_64\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_104\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_80\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_56\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_96\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_48\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_72\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_88\,
      O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_65\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_105\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_81\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_57\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_97\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_49\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_73\,
      O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_89\,
      Q => \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_65\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_105\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_81\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_57\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_97\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_49\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_73\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_89\,
      O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_106\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_82\,
      O => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_50\,
      O => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_74\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_66\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_98\,
      O => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_66\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_106\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_82\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_58\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_98\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_50\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_74\,
      O => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_90\,
      Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_67\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_107\,
      O => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_59\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_99\,
      O => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_51\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_83\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_91\,
      O => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_67\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_107\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_83\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_59\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_99\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_51\,
      O => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_75\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_91\,
      Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_108\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_60\,
      O => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_52\,
      O => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_92\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_68\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_84\,
      O => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_100\,
      O => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_76\,
      Q => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_68\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_108\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_84\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_60\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_100\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_52\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_76\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_92\,
      O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_69\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_109\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_85\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_61\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_101\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_53\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_77\,
      O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_93\,
      Q => \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_69\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_109\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_85\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_61\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_101\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_53\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_77\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_93\,
      O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_110\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_86\,
      O => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_54\,
      O => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_78\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_70\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_102\,
      O => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_70\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_110\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_86\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_62\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_102\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_54\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_78\,
      O => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_94\,
      Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg\,
      R => '0'
    );
\gen_pat_match_div4.pat_data_match_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => pat_match_rise0_and_r,
      I1 => pat_match_rise3_and_r,
      I2 => pat_match_fall2_and_r,
      I3 => pat_match_fall3_and_r,
      I4 => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\,
      O => \pat_data_match_r0__0\
    );
\gen_pat_match_div4.pat_data_match_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => pat_match_fall0_and_r,
      I1 => pat_match_rise2_and_r,
      I2 => pat_match_rise1_and_r,
      I3 => pat_match_fall1_and_r,
      O => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\
    );
\gen_pat_match_div4.pat_data_match_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pat_data_match_r0__0\,
      Q => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat_data_match_valid_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_active_r3_reg_srl2_n_0,
      Q => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg\,
      I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\,
      Q => pat_match_fall0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\,
      O => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\,
      Q => pat_match_fall1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg\,
      O => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\,
      Q => pat_match_fall2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg\,
      O => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_fall3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\,
      Q => pat_match_fall3_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg\,
      I1 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg\,
      I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\,
      O => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise0_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\,
      Q => pat_match_rise0_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise1_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\,
      Q => pat_match_rise1_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise2_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\,
      Q => pat_match_rise2_and_r,
      R => '0'
    );
\gen_pat_match_div4.pat_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\,
      I1 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\,
      I2 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\,
      I3 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\,
      I4 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\,
      O => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\
    );
\gen_pat_match_div4.pat_match_rise3_and_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\,
      Q => pat_match_rise3_and_r,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_63\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_103\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_79\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_55\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_95\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_47\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_71\,
      R => '0'
    );
\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\,
      Q => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_87\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_64\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_104\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_80\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_56\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_96\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_48\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_72\,
      R => '0'
    );
\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\,
      Q => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_88\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_65\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_105\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_81\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_57\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_97\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_49\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_73\,
      R => '0'
    );
\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\,
      Q => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_89\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_66\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_106\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_82\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_58\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_98\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_50\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_74\,
      R => '0'
    );
\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\,
      Q => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_90\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_67\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_107\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_83\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_59\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_99\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_51\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_75\,
      R => '0'
    );
\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\,
      Q => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_91\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_68\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_108\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_84\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_60\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_100\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_52\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_76\,
      R => '0'
    );
\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\,
      Q => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_92\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_69\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_109\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_85\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_61\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_101\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_53\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_77\,
      R => '0'
    );
\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\,
      Q => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_93\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_70\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_110\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_86\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_62\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_102\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_54\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_78\,
      R => '0'
    );
\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\,
      Q => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_94\,
      R => '0'
    );
idelay_ld_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFCFF00000080"
    )
        port map (
      I0 => idelay_ld_done_i_2_n_0,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[3]\,
      I5 => idelay_ld_done_reg_n_0,
      O => idelay_ld_done_i_1_n_0
    );
idelay_ld_done_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(2),
      I1 => \tap_inc_wait_cnt_reg__0\(0),
      I2 => \tap_inc_wait_cnt_reg__0\(1),
      I3 => \tap_inc_wait_cnt_reg__0\(3),
      O => idelay_ld_done_i_2_n_0
    );
idelay_ld_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ld_done_i_1_n_0,
      Q => idelay_ld_done_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
idelay_ld_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => idelay_ld_i_2_n_0,
      I3 => idelay_ld,
      O => idelay_ld_i_1_n_0
    );
idelay_ld_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000540400000000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r[2]_i_2_n_0\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => idelay_ld_done_i_2_n_0,
      I4 => \cal2_state_r_reg_n_0_[1]\,
      I5 => \cal2_state_r_reg_n_0_[0]\,
      O => idelay_ld_i_2_n_0
    );
idelay_ld_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ld_i_1_n_0,
      Q => idelay_ld,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\idelay_tap_cnt_r[0][0][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF101010"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I2 => \idelay_tap_cnt_r[0][0][4]_i_3_n_0\,
      I3 => \cal1_cnt_cpt_r_reg[1]\,
      I4 => \cal1_cnt_cpt_r_reg[2]_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][0][4]\(0)
    );
\idelay_tap_cnt_r[0][0][4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      I2 => idelay_ld,
      I3 => idelay_ce_int,
      O => \idelay_tap_cnt_r[0][0][4]_i_3_n_0\
    );
\idelay_tap_cnt_r[0][1][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF2020FF20"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I2 => \idelay_tap_cnt_r[0][0][4]_i_3_n_0\,
      I3 => \cal1_cnt_cpt_r_reg[2]_0\,
      I4 => \cal1_cnt_cpt_r_reg[0]\,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][1][4]\(0)
    );
\idelay_tap_cnt_r[0][2][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF2020FF20"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I2 => \idelay_tap_cnt_r[0][0][4]_i_3_n_0\,
      I3 => \cal1_cnt_cpt_r_reg[2]_0\,
      I4 => cal1_dq_idel_ce_reg_0,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][2][4]_0\(0)
    );
\idelay_tap_cnt_r[0][3][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8080FF80"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I2 => \idelay_tap_cnt_r[0][0][4]_i_3_n_0\,
      I3 => \cal1_cnt_cpt_r_reg[2]_0\,
      I4 => cal1_dq_idel_ce_reg,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][3][4]\(0)
    );
\idelay_tap_cnt_r[0][4][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF010101"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][4][4]_i_2_n_0\,
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I2 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I3 => \cal1_cnt_cpt_r_reg[2]\,
      I4 => \cal1_cnt_cpt_r_reg[1]\,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][4][4]\(0)
    );
\idelay_tap_cnt_r[0][4][4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      I1 => idelay_ld,
      I2 => idelay_ce_int,
      I3 => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      O => \idelay_tap_cnt_r[0][4][4]_i_2_n_0\
    );
\idelay_tap_cnt_r[0][5][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0404FF04"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][4][4]_i_2_n_0\,
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I2 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I3 => \cal1_cnt_cpt_r_reg[2]\,
      I4 => \cal1_cnt_cpt_r_reg[0]\,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][5][4]\(0)
    );
\idelay_tap_cnt_r[0][6][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0404FF04"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][4][4]_i_2_n_0\,
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I2 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I3 => \cal1_cnt_cpt_r_reg[2]\,
      I4 => cal1_dq_idel_ce_reg_0,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][6][4]\(0)
    );
\idelay_tap_cnt_r[0][7][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF4040FF40"
    )
        port map (
      I0 => \idelay_tap_cnt_r[0][4][4]_i_2_n_0\,
      I1 => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      I2 => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      I3 => \cal1_cnt_cpt_r_reg[2]\,
      I4 => cal1_dq_idel_ce_reg,
      I5 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \idelay_tap_cnt_r_reg[0][7][4]\(0)
    );
\init_state_r[0]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555515555555"
    )
        port map (
      I0 => \^wrcal_sanity_chk_done_reg_0\,
      I1 => \^wrcal_done_reg_0\,
      I2 => wrlvl_done_r1,
      I3 => rdlvl_stg1_done_reg,
      I4 => pi_dqs_found_done,
      I5 => ddr3_lm_done_r,
      O => \init_state_r_reg[0]\
    );
\init_state_r[2]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^wrlvl_byte_redo\,
      I1 => pi_dqs_found_done,
      I2 => wrlvl_done_r1,
      O => \init_state_r_reg[2]\
    );
\init_state_r[3]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^wrcal_done_reg_0\,
      I1 => wrlvl_done_r1,
      I2 => rdlvl_stg1_done_reg,
      I3 => pi_dqs_found_done,
      O => \init_state_r_reg[3]\
    );
\init_state_r[4]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^wrcal_done_reg_0\,
      I1 => \^wrlvl_byte_redo\,
      O => \init_state_r_reg[4]\
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => Q(1),
      I1 => calib_in_common,
      I2 => idelay_ld,
      I3 => \calib_sel_reg[1]\(0),
      I4 => \calib_sel_reg[1]\(1),
      I5 => idelay_ld_rst_13,
      O => LD0_3
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => Q(0),
      I1 => calib_in_common,
      I2 => idelay_ld,
      I3 => \calib_sel_reg[1]\(0),
      I4 => \calib_sel_reg[1]\(1),
      I5 => idelay_ld_rst,
      O => LD0
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40404050"
    )
        port map (
      I0 => Q(2),
      I1 => calib_in_common,
      I2 => idelay_ld,
      I3 => \calib_sel_reg[1]\(0),
      I4 => \calib_sel_reg[1]\(1),
      I5 => idelay_ld_rst_14,
      O => LD0_4
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF44005400"
    )
        port map (
      I0 => Q(0),
      I1 => calib_in_common,
      I2 => \calib_sel_reg[1]\(0),
      I3 => idelay_ld,
      I4 => \calib_sel_reg[1]\(1),
      I5 => idelay_ld_rst_10,
      O => LD0_0
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45004400"
    )
        port map (
      I0 => Q(0),
      I1 => calib_in_common,
      I2 => \calib_sel_reg[1]\(0),
      I3 => idelay_ld,
      I4 => \calib_sel_reg[1]\(1),
      I5 => idelay_ld_rst_11,
      O => LD0_1
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54440000"
    )
        port map (
      I0 => Q(0),
      I1 => calib_in_common,
      I2 => \calib_sel_reg[1]\(1),
      I3 => \calib_sel_reg[1]\(0),
      I4 => idelay_ld,
      I5 => idelay_ld_rst_12,
      O => LD0_2
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45440000"
    )
        port map (
      I0 => Q(2),
      I1 => calib_in_common,
      I2 => \calib_sel_reg[1]\(1),
      I3 => \calib_sel_reg[1]\(0),
      I4 => idelay_ld,
      I5 => idelay_ld_rst_14,
      O => LD0_6
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45004400"
    )
        port map (
      I0 => Q(2),
      I1 => calib_in_common,
      I2 => \calib_sel_reg[1]\(0),
      I3 => idelay_ld,
      I4 => \calib_sel_reg[1]\(1),
      I5 => idelay_ld_rst_14,
      O => LD0_8
    );
\not_empty_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[0]\,
      O => p_0_in_0(0)
    );
\not_empty_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      O => p_0_in_0(1)
    );
\not_empty_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[0]\,
      O => p_0_in_0(2)
    );
\not_empty_wait_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[3]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[2]\,
      O => p_0_in_0(3)
    );
\not_empty_wait_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => \cal2_state_r_reg_n_0_[3]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => wrcal_rd_wait,
      O => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \not_empty_wait_cnt_reg_n_0_[4]\,
      I1 => \not_empty_wait_cnt_reg_n_0_[2]\,
      I2 => \not_empty_wait_cnt_reg_n_0_[1]\,
      I3 => \not_empty_wait_cnt_reg_n_0_[0]\,
      I4 => \not_empty_wait_cnt_reg_n_0_[3]\,
      O => p_0_in_0(4)
    );
\not_empty_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in_0(0),
      Q => \not_empty_wait_cnt_reg_n_0_[0]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in_0(1),
      Q => \not_empty_wait_cnt_reg_n_0_[1]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in_0(2),
      Q => \not_empty_wait_cnt_reg_n_0_[2]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in_0(3),
      Q => \not_empty_wait_cnt_reg_n_0_[3]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\not_empty_wait_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_0_in_0(4),
      Q => \not_empty_wait_cnt_reg_n_0_[4]\,
      R => \not_empty_wait_cnt[4]_i_1_n_0\
    );
\po_stg2_wrcal_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      Q => \^idelay_tap_cnt_r_reg[0][2][4]\(0),
      R => '0'
    );
\po_stg2_wrcal_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      Q => \^idelay_tap_cnt_r_reg[0][2][4]\(1),
      R => '0'
    );
\po_stg2_wrcal_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      Q => \^idelay_tap_cnt_r_reg[0][2][4]\(2),
      R => '0'
    );
\po_stg2_wrcal_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_dqs_cnt_r(3),
      Q => \^idelay_tap_cnt_r_reg[0][2][4]\(3),
      R => '0'
    );
rd_active_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^e\(0),
      Q => rd_active_r1,
      R => '0'
    );
rd_active_r3_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => rd_active_r1,
      Q => rd_active_r3_reg_srl2_n_0
    );
rd_active_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_rddata_en,
      Q => \^e\(0),
      R => '0'
    );
\tap_inc_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(0),
      O => \p_0_in__0\(0)
    );
\tap_inc_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(1),
      I1 => \tap_inc_wait_cnt_reg__0\(0),
      O => \p_0_in__0\(1)
    );
\tap_inc_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(2),
      I1 => \tap_inc_wait_cnt_reg__0\(0),
      I2 => \tap_inc_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\tap_inc_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAFEF"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[0]\,
      I4 => \rstdiv0_sync_r1_reg_rep__22\,
      O => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(3),
      I1 => \tap_inc_wait_cnt_reg__0\(1),
      I2 => \tap_inc_wait_cnt_reg__0\(0),
      I3 => \tap_inc_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\tap_inc_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \tap_inc_wait_cnt_reg__0\(0),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \tap_inc_wait_cnt_reg__0\(1),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \tap_inc_wait_cnt_reg__0\(2),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\tap_inc_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \tap_inc_wait_cnt_reg__0\(3),
      R => \tap_inc_wait_cnt[3]_i_1_n_0\
    );
\wl_tap_count_r[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^wrlvl_byte_redo\,
      I1 => wrlvl_byte_redo_r,
      O => done_dqs_dec239_out
    );
wrcal_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45454500"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22\,
      I1 => wrcal_sanity_chk_r_reg_n_0,
      I2 => wrcal_sanity_chk,
      I3 => \^wrcal_done_reg_0\,
      I4 => cal2_done_r,
      O => wrcal_done_i_1_n_0
    );
wrcal_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_done_i_1_n_0,
      Q => \^wrcal_done_reg_0\,
      R => '0'
    );
\wrcal_dqs_cnt_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[0]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[1]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[2]_i_1_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \wrcal_dqs_cnt_r[3]_i_4_n_0\,
      I2 => \cal2_state_r_reg_n_0_[0]\,
      O => \wrcal_dqs_cnt_r[3]_i_2_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I3 => wrcal_dqs_cnt_r(3),
      I4 => \cal2_state_r_reg_n_0_[2]\,
      O => \wrcal_dqs_cnt_r[3]_i_3_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FC800C800000000"
    )
        port map (
      I0 => prech_done,
      I1 => \wrcal_dqs_cnt_r[3]_i_5_n_0\,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => wrcal_sanity_chk,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => \wrcal_dqs_cnt_r[3]_i_4_n_0\
    );
\wrcal_dqs_cnt_r[3]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      I2 => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      I3 => wrcal_dqs_cnt_r(3),
      O => \wrcal_dqs_cnt_r[3]_i_5_n_0\
    );
\wrcal_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_dqs_cnt_r[3]_i_2_n_0\,
      D => \wrcal_dqs_cnt_r[0]_i_1_n_0\,
      Q => \wrcal_dqs_cnt_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\wrcal_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_dqs_cnt_r[3]_i_2_n_0\,
      D => \wrcal_dqs_cnt_r[1]_i_1_n_0\,
      Q => \wrcal_dqs_cnt_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\wrcal_dqs_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_dqs_cnt_r[3]_i_2_n_0\,
      D => \wrcal_dqs_cnt_r[2]_i_1_n_0\,
      Q => \wrcal_dqs_cnt_r_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
\wrcal_dqs_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wrcal_dqs_cnt_r[3]_i_2_n_0\,
      D => \wrcal_dqs_cnt_r[3]_i_3_n_0\,
      Q => wrcal_dqs_cnt_r(3),
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
wrcal_pat_resume_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => wrcal_pat_resume_r,
      Q => wrcal_pat_resume_r2_reg_srl2_n_0
    );
wrcal_pat_resume_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8FFF800"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[2]\,
      I1 => idelay_ld_done_reg_n_0,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrcal_pat_resume_r_i_2_n_0,
      I4 => wrcal_pat_resume_r,
      O => wrcal_pat_resume_r_i_1_n_0
    );
wrcal_pat_resume_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000800033C003C"
    )
        port map (
      I0 => \cal2_state_r[3]_i_7_n_0\,
      I1 => \cal2_state_r_reg_n_0_[0]\,
      I2 => \cal2_state_r_reg_n_0_[3]\,
      I3 => \cal2_state_r_reg_n_0_[2]\,
      I4 => wrcal_pat_resume_r_i_3_n_0,
      I5 => \cal2_state_r_reg_n_0_[1]\,
      O => wrcal_pat_resume_r_i_2_n_0
    );
wrcal_pat_resume_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => \tap_inc_wait_cnt_reg__0\(2),
      I1 => idelay_ld_done_reg_n_0,
      I2 => \tap_inc_wait_cnt_reg__0\(0),
      I3 => \tap_inc_wait_cnt_reg__0\(1),
      I4 => wrcal_sanity_chk_r_reg_n_0,
      I5 => \tap_inc_wait_cnt_reg__0\(3),
      O => wrcal_pat_resume_r_i_3_n_0
    );
wrcal_pat_resume_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_pat_resume_r_i_1_n_0,
      Q => wrcal_pat_resume_r,
      R => \rstdiv0_sync_r1_reg_rep__12\(0)
    );
wrcal_pat_resume_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_pat_resume_r2_reg_srl2_n_0,
      Q => wrcal_resume_w,
      R => '0'
    );
wrcal_prech_req_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cal2_prech_req_r,
      Q => wrcal_prech_req,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
wrcal_sanity_chk_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00004000"
    )
        port map (
      I0 => \cal2_state_r_reg_n_0_[3]\,
      I1 => \cal2_state_r_reg_n_0_[2]\,
      I2 => wrcal_sanity_chk_r_reg_n_0,
      I3 => \cal2_state_r_reg_n_0_[1]\,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \^wrcal_sanity_chk_done_reg_0\,
      O => wrcal_sanity_chk_done_i_1_n_0
    );
wrcal_sanity_chk_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_sanity_chk_done_i_1_n_0,
      Q => \^wrcal_sanity_chk_done_reg_0\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
wrcal_sanity_chk_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrcal_sanity_chk,
      Q => wrcal_sanity_chk_r_reg_n_0,
      R => '0'
    );
wrlvl_byte_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_byte_done,
      Q => wrlvl_byte_done_r,
      R => '0'
    );
wrlvl_byte_redo_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EFFFFFF0E000000"
    )
        port map (
      I0 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I2 => \cal2_state_r_reg_n_0_[1]\,
      I3 => wrlvl_byte_redo_i_2_n_0,
      I4 => \cal2_state_r_reg_n_0_[0]\,
      I5 => \^wrlvl_byte_redo\,
      O => wrlvl_byte_redo_i_1_n_0
    );
wrlvl_byte_redo_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022222E22"
    )
        port map (
      I0 => wrlvl_byte_redo_i_3_n_0,
      I1 => \cal2_state_r_reg_n_0_[1]\,
      I2 => \cal2_state_r_reg_n_0_[2]\,
      I3 => wrlvl_byte_done,
      I4 => wrlvl_byte_done_r,
      I5 => \cal2_state_r_reg_n_0_[3]\,
      O => wrlvl_byte_redo_i_2_n_0
    );
wrlvl_byte_redo_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002220"
    )
        port map (
      I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\,
      I1 => wrcal_sanity_chk_r_reg_n_0,
      I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\,
      I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\,
      I4 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\,
      I5 => \cal2_state_r_reg_n_0_[2]\,
      O => wrlvl_byte_redo_i_3_n_0
    );
wrlvl_byte_redo_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_byte_redo_i_1_n_0,
      Q => \^wrlvl_byte_redo\,
      R => \rstdiv0_sync_r1_reg_rep__13\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_wrlvl is
  port (
    wr_level_done_r5 : out STD_LOGIC;
    wrlvl_byte_redo_r : out STD_LOGIC;
    dqs_po_dec_done : out STD_LOGIC;
    dqs_po_stg2_f_incdec : out STD_LOGIC;
    dqs_po_en_stg2_f : out STD_LOGIC;
    p_0_in : out STD_LOGIC;
    dqs_po_en_stg2_f_reg_0 : out STD_LOGIC;
    wrlvl_done_r_reg : out STD_LOGIC;
    wrlvl_rank_done : out STD_LOGIC;
    \po_counter_read_val_reg[8]\ : out STD_LOGIC;
    D_po_coarse_enable105_out : out STD_LOGIC;
    \po_counter_read_val_reg[8]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_4\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_7\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_8\ : out STD_LOGIC;
    done_dqs_tap_inc : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    p_1_in : out STD_LOGIC;
    wrlvl_byte_done : out STD_LOGIC;
    phy_mc_go : in STD_LOGIC;
    CLK : in STD_LOGIC;
    wrlvl_byte_redo : in STD_LOGIC;
    wr_lvl_start_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__4\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__5\ : in STD_LOGIC;
    calib_in_common : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \calib_zero_inputs_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wrlvl_byte_redo_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC;
    wl_sm_start : in STD_LOGIC;
    early1_data_reg : in STD_LOGIC;
    early2_data_reg : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \po_counter_read_val_reg[0]\ : in STD_LOGIC;
    \po_counter_read_val_reg[1]\ : in STD_LOGIC;
    \po_counter_read_val_reg[2]\ : in STD_LOGIC;
    \po_counter_read_val_reg[3]\ : in STD_LOGIC;
    \po_counter_read_val_reg[4]\ : in STD_LOGIC;
    \po_counter_read_val_reg[5]\ : in STD_LOGIC;
    \po_counter_read_val_reg[6]\ : in STD_LOGIC;
    \po_counter_read_val_reg[7]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_9\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[3]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]\ : in STD_LOGIC;
    done_dqs_dec239_out : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[0]_3\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_3\ : in STD_LOGIC;
    wrlvl_byte_redo_reg_0 : in STD_LOGIC;
    pi_fine_dly_dec_done : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rstdiv0_sync_r1_reg_rep : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_wrlvl : entity is "mig_7series_v2_3_ddr_phy_wrlvl";
end mig_7series_0_mig_7series_v2_3_ddr_phy_wrlvl;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_wrlvl is
  signal \FSM_sequential_wl_state_r[0]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[0]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[1]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_15_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_16_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_17_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_wl_state_r[4]_i_9_n_0\ : STD_LOGIC;
  signal corse_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_cnt[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_6_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_7_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_8_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][0]_i_9_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_6_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_7_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_8_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][1]_i_9_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_11_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_12_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_13_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_6_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_8_n_0\ : STD_LOGIC;
  signal \corse_cnt[0][2]_i_9_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[1][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[2][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[3][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[4][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[5][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[6][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_cnt[7][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_cnt__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_cnt_reg[0][0]_i_5_n_0\ : STD_LOGIC;
  signal \corse_cnt_reg[0][1]_i_5_n_0\ : STD_LOGIC;
  signal \corse_cnt_reg[0][2]_i_10_n_0\ : STD_LOGIC;
  signal \corse_cnt_reg[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[7][0]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[7][1]\ : STD_LOGIC;
  signal \corse_cnt_reg_n_0_[7][2]\ : STD_LOGIC;
  signal corse_dec : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \corse_dec[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_dec[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[0][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_dec[0][1]_i_4_n_0\ : STD_LOGIC;
  signal \corse_dec[0][1]_i_5_n_0\ : STD_LOGIC;
  signal \corse_dec[0][1]_i_6_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_6_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_7_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_8_n_0\ : STD_LOGIC;
  signal \corse_dec[0][2]_i_9_n_0\ : STD_LOGIC;
  signal \corse_dec[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \corse_dec_reg[0]_30\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[1]_31\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[2]_32\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[3]_33\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[4]_34\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[5]_35\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[6]_36\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_dec_reg[7]_37\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \corse_inc[0][0]_i_4_n_0\ : STD_LOGIC;
  signal \corse_inc[0][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[0][1]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_10_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_6_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_7_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_8_n_0\ : STD_LOGIC;
  signal \corse_inc[0][2]_i_9_n_0\ : STD_LOGIC;
  signal \corse_inc[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[1][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[2][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[3][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[4][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[5][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[6][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \corse_inc[7][2]_i_2_n_0\ : STD_LOGIC;
  signal \corse_inc_reg[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \corse_inc_reg[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \corse_inc_reg[0]_38\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[1]_39\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[2]_40\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[3]_41\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[4]_42\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[5]_43\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[6]_44\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \corse_inc_reg[7]_45\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^done_dqs_tap_inc\ : STD_LOGIC;
  signal dq_cnt_inc_i_1_n_0 : STD_LOGIC;
  signal dq_cnt_inc_i_2_n_0 : STD_LOGIC;
  signal dq_cnt_inc_i_3_n_0 : STD_LOGIC;
  signal dqs_count_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal dqs_count_r140_out : STD_LOGIC;
  signal \dqs_count_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[0]_rep_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_10_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_6_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_7_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_8_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_i_9_n_0\ : STD_LOGIC;
  signal \dqs_count_r[1]_rep_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_10_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_6_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_7_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_8_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_i_9_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_rep__0_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[2]_rep_i_1_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_10_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_11_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_6_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_7_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_8_n_0\ : STD_LOGIC;
  signal \dqs_count_r[3]_i_9_n_0\ : STD_LOGIC;
  signal \dqs_count_r_reg[0]_rep_n_0\ : STD_LOGIC;
  signal \dqs_count_r_reg[1]_rep_n_0\ : STD_LOGIC;
  signal \dqs_count_r_reg[2]_rep__0_n_0\ : STD_LOGIC;
  signal \dqs_count_r_reg[2]_rep_n_0\ : STD_LOGIC;
  signal \^dqs_po_dec_done\ : STD_LOGIC;
  signal dqs_po_en_stg2_f_i_1_n_0 : STD_LOGIC;
  signal \^dqs_po_en_stg2_f_reg_0\ : STD_LOGIC;
  signal dqs_po_stg2_f_incdec0 : STD_LOGIC;
  signal dqs_po_stg2_f_incdec_i_2_n_0 : STD_LOGIC;
  signal final_coarse_tap : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \final_coarse_tap_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[7][0]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[7][1]\ : STD_LOGIC;
  signal \final_coarse_tap_reg_n_0_[7][2]\ : STD_LOGIC;
  signal fine_dec_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_dec_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_10_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_11_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_4_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_5_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_6_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_7_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_8_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt[5]_i_9_n_0\ : STD_LOGIC;
  signal \fine_dec_cnt__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fine_inc : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc[0][2]_i_10_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_5_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_6_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_7_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_8_n_0\ : STD_LOGIC;
  signal \fine_inc[0][2]_i_9_n_0\ : STD_LOGIC;
  signal \fine_inc[0][3]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_11_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_12_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_13_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_14_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_15_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_16_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_5_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_6_n_0\ : STD_LOGIC;
  signal \fine_inc[0][5]_i_9_n_0\ : STD_LOGIC;
  signal \fine_inc[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[1][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[1][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[2][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[2][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[3][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[3][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[4][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[4][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[5][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[5][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[6][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[6][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][1]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][2]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][3]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][4]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][5]_i_1_n_0\ : STD_LOGIC;
  signal \fine_inc[7][5]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc[7][5]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][5]_i_10_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][5]_i_7_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0][5]_i_8_n_0\ : STD_LOGIC;
  signal \fine_inc_reg[0]_6\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[1]_7\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[2]_8\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[3]_9\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[4]_10\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[5]_11\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[6]_12\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \fine_inc_reg[7]_13\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal flag_ck_negedge09_out : STD_LOGIC;
  signal flag_ck_negedge_i_1_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_2_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_3_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_4_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_5_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_6_n_0 : STD_LOGIC;
  signal flag_ck_negedge_i_8_n_0 : STD_LOGIC;
  signal flag_ck_negedge_reg_n_0 : STD_LOGIC;
  signal flag_init : STD_LOGIC;
  signal flag_init_i_1_n_0 : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \gen_final_tap[0].final_val_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][3]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][4]\ : STD_LOGIC;
  signal \gen_final_tap[1].final_val_reg_n_0_[1][5]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][3]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][4]\ : STD_LOGIC;
  signal \gen_final_tap[2].final_val_reg_n_0_[2][5]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][3]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][4]\ : STD_LOGIC;
  signal \gen_final_tap[3].final_val_reg_n_0_[3][5]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][3]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][4]\ : STD_LOGIC;
  signal \gen_final_tap[4].final_val_reg_n_0_[4][5]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][3]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][4]\ : STD_LOGIC;
  signal \gen_final_tap[5].final_val_reg_n_0_[5][5]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][3]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][4]\ : STD_LOGIC;
  signal \gen_final_tap[6].final_val_reg_n_0_[6][5]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][0]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][1]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][2]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][3]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][4]\ : STD_LOGIC;
  signal \gen_final_tap[7].final_val_reg_n_0_[7][5]\ : STD_LOGIC;
  signal \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \incdec_wait_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \incdec_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal inhibit_edge_detect_r : STD_LOGIC;
  signal inhibit_edge_detect_r_i_1_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_3_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_4_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_5_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_i_6_n_0 : STD_LOGIC;
  signal inhibit_edge_detect_r_reg_n_0 : STD_LOGIC;
  signal largest : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^p_0_in\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC;
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0\ : STD_LOGIC;
  signal p_1_in28_in : STD_LOGIC;
  signal p_21_out : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal phy_ctl_ready_r4_reg_srl4_n_0 : STD_LOGIC;
  signal phy_ctl_ready_r5 : STD_LOGIC;
  signal phy_ctl_ready_r6_reg_n_0 : STD_LOGIC;
  signal po_cnt_dec_i_1_n_0 : STD_LOGIC;
  signal po_cnt_dec_i_2_n_0 : STD_LOGIC;
  signal po_dec_done : STD_LOGIC;
  signal po_dec_done_i_1_n_0 : STD_LOGIC;
  signal po_dec_done_i_2_n_0 : STD_LOGIC;
  signal po_dec_done_i_3_n_0 : STD_LOGIC;
  signal po_rdval_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \po_rdval_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[6]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[6]_i_4_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_1_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_2_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_3_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_5_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_6_n_0\ : STD_LOGIC;
  signal \po_rdval_cnt[8]_i_7_n_0\ : STD_LOGIC;
  signal po_stg2_cincdec : STD_LOGIC_VECTOR ( 2 to 2 );
  signal rank_cnt_r : STD_LOGIC;
  signal \rank_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rank_cnt_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \rank_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rank_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rd_data_edge_detect_r0 : STD_LOGIC;
  signal \rd_data_edge_detect_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_10_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_11_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_3_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_4_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_6_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_7_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r[7]_i_8_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg[7]_i_5_n_0\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \rd_data_edge_detect_r_reg_n_0_[7]\ : STD_LOGIC;
  signal rd_data_previous_r0 : STD_LOGIC;
  signal \rd_data_previous_r[7]_i_2_n_0\ : STD_LOGIC;
  signal \rd_data_previous_r[7]_i_3_n_0\ : STD_LOGIC;
  signal \rd_data_previous_r[7]_i_4_n_0\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \rd_data_previous_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \single_rank.done_dqs_dec_i_1_n_0\ : STD_LOGIC;
  signal smallest : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][1]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \smallest[0][3]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[0][3]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][4]_i_2_n_0\ : STD_LOGIC;
  signal \smallest[0][4]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_3_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \smallest[0][5]_i_5_n_0\ : STD_LOGIC;
  signal \smallest[1][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[2][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[3][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[4][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[5][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[6][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest[7][5]_i_1_n_0\ : STD_LOGIC;
  signal \smallest_reg[0]_14\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[1]_15\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[2]_16\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[3]_17\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[4]_18\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[5]_19\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[6]_20\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \smallest_reg[7]_21\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal stable_cnt : STD_LOGIC;
  signal stable_cnt0 : STD_LOGIC;
  signal stable_cnt227_in : STD_LOGIC;
  signal \stable_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_5_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_6_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_7_n_0\ : STD_LOGIC;
  signal \stable_cnt[3]_i_8_n_0\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \stable_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal wait_cnt0 : STD_LOGIC;
  signal \wait_cnt0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wait_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wl_corse_cnt : STD_LOGIC;
  signal \wl_corse_cnt[0][0][0]_i_2_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][0]_i_3_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][1]_i_2_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][1]_i_3_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][2]_i_3_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][2]_i_4_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][2]_i_5_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][0][2]_i_6_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][1][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][2][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][3][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][4][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][5][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][6][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt[0][7][2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_corse_cnt_reg[0][0]_22\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][1]_23\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][2]_24\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][3]_25\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][4]_26\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][5]_27\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][6]_28\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_corse_cnt_reg[0][7]_29\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][0][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][2][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][3][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][4][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][5][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][6][5]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][0]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][1]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][2]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][3]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][4]\ : STD_LOGIC;
  signal \wl_dqs_tap_count_r_reg_n_0_[0][7][5]\ : STD_LOGIC;
  signal wl_edge_detect_valid_r_i_1_n_0 : STD_LOGIC;
  signal wl_edge_detect_valid_r_reg_n_0 : STD_LOGIC;
  signal wl_state_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of wl_state_r : signal is "yes";
  signal wl_state_r1 : STD_LOGIC;
  signal \wl_state_r1[0]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[1]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[2]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[3]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1[4]_i_1_n_0\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \wl_state_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal wl_tap_count_r : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \wl_tap_count_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[1]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[2]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[2]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[3]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[3]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_10_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_6_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_7_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_8_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r[5]_i_9_n_0\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \wl_tap_count_r_reg_n_0_[5]\ : STD_LOGIC;
  signal wr_level_done_i_1_n_0 : STD_LOGIC;
  signal wr_level_done_r1 : STD_LOGIC;
  signal wr_level_done_r2 : STD_LOGIC;
  signal wr_level_done_r3 : STD_LOGIC;
  signal wr_level_done_r4 : STD_LOGIC;
  signal \^wr_level_done_r5\ : STD_LOGIC;
  signal wr_level_done_r_i_1_n_0 : STD_LOGIC;
  signal wr_level_done_r_i_2_n_0 : STD_LOGIC;
  signal wr_level_done_r_i_3_n_0 : STD_LOGIC;
  signal wr_level_done_r_reg_n_0 : STD_LOGIC;
  signal wr_level_start_r : STD_LOGIC;
  signal \^wrlvl_byte_done\ : STD_LOGIC;
  signal wrlvl_byte_done_i_1_n_0 : STD_LOGIC;
  signal \^wrlvl_byte_redo_r\ : STD_LOGIC;
  signal \^wrlvl_done_r_reg\ : STD_LOGIC;
  signal \^wrlvl_rank_done\ : STD_LOGIC;
  signal wrlvl_rank_done_r_i_1_n_0 : STD_LOGIC;
  signal wrlvl_rank_done_r_i_2_n_0 : STD_LOGIC;
  signal wrlvl_redo_corse_inc : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \wrlvl_redo_corse_inc[0]_i_1_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[1]_i_1_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[1]_i_2_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_1_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_2_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_3_n_0\ : STD_LOGIC;
  signal \wrlvl_redo_corse_inc[2]_i_4_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_12\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_14\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_10\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_7\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_12\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_13\ : label is "soft_lutpair89";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[0]\ : label is "WL_IDLE:00000,WL_INIT:00001,WL_INIT_FINE_INC:00010,WL_INIT_FINE_INC_WAIT1:00101,WL_INIT_FINE_INC_WAIT:00110,WL_INIT_FINE_DEC:01000,WL_INIT_FINE_DEC_WAIT1:01001,WL_INIT_FINE_DEC_WAIT:01010,WL_FINE_INC:01011,WL_FINE_INC_WAIT:01100,WL_FINE_DEC:00011,WL_FINE_DEC_WAIT1:01110,WL_FINE_DEC_WAIT:01111,WL_CORSE_DEC:10000,WL_CORSE_DEC_WAIT:10010,WL_CORSE_DEC_WAIT1:10011,WL_CORSE_INC:00100,WL_CORSE_INC_WAIT_TMP:10100,WL_CORSE_INC_WAIT:10101,WL_CORSE_INC_WAIT1:10110,WL_CORSE_INC_WAIT2:10111,WL_WAIT:00111,WL_EDGE_CHECK:11000,WL_2RANK_TAP_DEC:11010,WL_DQS_CNT:11001,WL_2RANK_DQS_CNT:10001,WL_DQS_CHECK:11011,WL_2RANK_FINAL_TAP:01101";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_wl_state_r_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[1]\ : label is "WL_IDLE:00000,WL_INIT:00001,WL_INIT_FINE_INC:00010,WL_INIT_FINE_INC_WAIT1:00101,WL_INIT_FINE_INC_WAIT:00110,WL_INIT_FINE_DEC:01000,WL_INIT_FINE_DEC_WAIT1:01001,WL_INIT_FINE_DEC_WAIT:01010,WL_FINE_INC:01011,WL_FINE_INC_WAIT:01100,WL_FINE_DEC:00011,WL_FINE_DEC_WAIT1:01110,WL_FINE_DEC_WAIT:01111,WL_CORSE_DEC:10000,WL_CORSE_DEC_WAIT:10010,WL_CORSE_DEC_WAIT1:10011,WL_CORSE_INC:00100,WL_CORSE_INC_WAIT_TMP:10100,WL_CORSE_INC_WAIT:10101,WL_CORSE_INC_WAIT1:10110,WL_CORSE_INC_WAIT2:10111,WL_WAIT:00111,WL_EDGE_CHECK:11000,WL_2RANK_TAP_DEC:11010,WL_DQS_CNT:11001,WL_2RANK_DQS_CNT:10001,WL_DQS_CHECK:11011,WL_2RANK_FINAL_TAP:01101";
  attribute KEEP of \FSM_sequential_wl_state_r_reg[1]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[2]\ : label is "WL_IDLE:00000,WL_INIT:00001,WL_INIT_FINE_INC:00010,WL_INIT_FINE_INC_WAIT1:00101,WL_INIT_FINE_INC_WAIT:00110,WL_INIT_FINE_DEC:01000,WL_INIT_FINE_DEC_WAIT1:01001,WL_INIT_FINE_DEC_WAIT:01010,WL_FINE_INC:01011,WL_FINE_INC_WAIT:01100,WL_FINE_DEC:00011,WL_FINE_DEC_WAIT1:01110,WL_FINE_DEC_WAIT:01111,WL_CORSE_DEC:10000,WL_CORSE_DEC_WAIT:10010,WL_CORSE_DEC_WAIT1:10011,WL_CORSE_INC:00100,WL_CORSE_INC_WAIT_TMP:10100,WL_CORSE_INC_WAIT:10101,WL_CORSE_INC_WAIT1:10110,WL_CORSE_INC_WAIT2:10111,WL_WAIT:00111,WL_EDGE_CHECK:11000,WL_2RANK_TAP_DEC:11010,WL_DQS_CNT:11001,WL_2RANK_DQS_CNT:10001,WL_DQS_CHECK:11011,WL_2RANK_FINAL_TAP:01101";
  attribute KEEP of \FSM_sequential_wl_state_r_reg[2]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[3]\ : label is "WL_IDLE:00000,WL_INIT:00001,WL_INIT_FINE_INC:00010,WL_INIT_FINE_INC_WAIT1:00101,WL_INIT_FINE_INC_WAIT:00110,WL_INIT_FINE_DEC:01000,WL_INIT_FINE_DEC_WAIT1:01001,WL_INIT_FINE_DEC_WAIT:01010,WL_FINE_INC:01011,WL_FINE_INC_WAIT:01100,WL_FINE_DEC:00011,WL_FINE_DEC_WAIT1:01110,WL_FINE_DEC_WAIT:01111,WL_CORSE_DEC:10000,WL_CORSE_DEC_WAIT:10010,WL_CORSE_DEC_WAIT1:10011,WL_CORSE_INC:00100,WL_CORSE_INC_WAIT_TMP:10100,WL_CORSE_INC_WAIT:10101,WL_CORSE_INC_WAIT1:10110,WL_CORSE_INC_WAIT2:10111,WL_WAIT:00111,WL_EDGE_CHECK:11000,WL_2RANK_TAP_DEC:11010,WL_DQS_CNT:11001,WL_2RANK_DQS_CNT:10001,WL_DQS_CHECK:11011,WL_2RANK_FINAL_TAP:01101";
  attribute KEEP of \FSM_sequential_wl_state_r_reg[3]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[4]\ : label is "WL_IDLE:00000,WL_INIT:00001,WL_INIT_FINE_INC:00010,WL_INIT_FINE_INC_WAIT1:00101,WL_INIT_FINE_INC_WAIT:00110,WL_INIT_FINE_DEC:01000,WL_INIT_FINE_DEC_WAIT1:01001,WL_INIT_FINE_DEC_WAIT:01010,WL_FINE_INC:01011,WL_FINE_INC_WAIT:01100,WL_FINE_DEC:00011,WL_FINE_DEC_WAIT1:01110,WL_FINE_DEC_WAIT:01111,WL_CORSE_DEC:10000,WL_CORSE_DEC_WAIT:10010,WL_CORSE_DEC_WAIT1:10011,WL_CORSE_INC:00100,WL_CORSE_INC_WAIT_TMP:10100,WL_CORSE_INC_WAIT:10101,WL_CORSE_INC_WAIT1:10110,WL_CORSE_INC_WAIT2:10111,WL_WAIT:00111,WL_EDGE_CHECK:11000,WL_2RANK_TAP_DEC:11010,WL_DQS_CNT:11001,WL_2RANK_DQS_CNT:10001,WL_DQS_CHECK:11011,WL_2RANK_FINAL_TAP:01101";
  attribute KEEP of \FSM_sequential_wl_state_r_reg[4]\ : label is "yes";
  attribute SOFT_HLUTNM of \corse_cnt[0][0]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \corse_cnt[0][1]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \corse_cnt[1][0]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \corse_cnt[1][1]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \corse_cnt[1][2]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \corse_cnt[2][0]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \corse_cnt[2][1]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \corse_cnt[2][2]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \corse_cnt[3][0]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \corse_cnt[3][1]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \corse_cnt[3][2]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \corse_cnt[4][0]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \corse_cnt[4][1]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \corse_cnt[4][2]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \corse_cnt[5][0]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \corse_cnt[5][1]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \corse_cnt[5][2]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \corse_cnt[6][0]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \corse_cnt[6][1]_i_1\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \corse_cnt[6][2]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \corse_cnt[7][0]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \corse_cnt[7][1]_i_1\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \corse_cnt[7][2]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \corse_inc[0][0]_i_2\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \dqs_count_r[1]_i_11\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \dqs_count_r[1]_i_6\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \dqs_count_r[1]_i_8\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_10\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_7\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \dqs_count_r[2]_i_9\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_10\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \dqs_count_r[3]_i_7\ : label is "soft_lutpair109";
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \dqs_count_r_reg[0]\ : label is "50";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[0]\ : label is "dqs_count_r_reg[0]";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[0]_rep\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[0]_rep\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[0]_rep\ : label is "dqs_count_r_reg[0]";
  attribute MAX_FANOUT of \dqs_count_r_reg[1]\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[1]\ : label is "dqs_count_r_reg[1]";
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[1]_rep\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[1]_rep\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[1]_rep\ : label is "dqs_count_r_reg[1]";
  attribute MAX_FANOUT of \dqs_count_r_reg[2]\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[2]\ : label is "dqs_count_r_reg[2]";
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[2]_rep\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[2]_rep\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[2]_rep\ : label is "dqs_count_r_reg[2]";
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[2]_rep__0\ : label is 1;
  attribute MAX_FANOUT of \dqs_count_r_reg[2]_rep__0\ : label is "50";
  attribute ORIG_CELL_NAME of \dqs_count_r_reg[2]_rep__0\ : label is "dqs_count_r_reg[2]";
  attribute MAX_FANOUT of \dqs_count_r_reg[3]\ : label is "50";
  attribute syn_maxfan : string;
  attribute syn_maxfan of dqs_po_dec_done_reg : label is "2";
  attribute SOFT_HLUTNM of \fine_dec_cnt[4]_i_2\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_11\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_6\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_9\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \fine_inc[0][5]_i_6\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \fine_inc[1][5]_i_3\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \fine_inc[2][5]_i_3\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \fine_inc[3][5]_i_3\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \fine_inc[4][5]_i_3\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \fine_inc[5][5]_i_3\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \fine_inc[6][5]_i_3\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \fine_inc[7][5]_i_3\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of flag_ck_negedge_i_6 : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[0]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[1]_i_1\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[2]_i_1\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[3]_i_3\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \incdec_wait_cnt[1]_i_1\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \incdec_wait_cnt[2]_i_1\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \incdec_wait_cnt[3]_i_2\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of phaser_out_i_1 : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \phaser_out_i_1__0\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \phaser_out_i_1__1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \phaser_out_i_1__2\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \phaser_out_i_1__3\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \phaser_out_i_1__4\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \phaser_out_i_1__5\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \phaser_out_i_1__6\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \phaser_out_i_1__7\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \phaser_out_i_1__8\ : label is "soft_lutpair86";
  attribute srl_name : string;
  attribute srl_name of phy_ctl_ready_r4_reg_srl4 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 ";
  attribute SOFT_HLUTNM of po_cnt_dec_i_2 : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of po_dec_done_i_2 : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \po_rdval_cnt[0]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \po_rdval_cnt[6]_i_3\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \po_rdval_cnt[7]_i_3\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \po_rdval_cnt[8]_i_6\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \po_rdval_cnt[8]_i_7\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \rank_cnt_r[0]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \rank_cnt_r[1]_i_2\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \rd_data_edge_detect_r[7]_i_6\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \rd_data_previous_r[7]_i_4\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \stable_cnt[0]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \stable_cnt[1]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \stable_cnt[2]_i_1\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \stable_cnt[3]_i_3\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \stable_cnt[3]_i_6\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \wait_cnt[1]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \wait_cnt[2]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \wait_cnt[3]_i_3\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \wl_corse_cnt[0][0][0]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \wl_tap_count_r[1]_i_3\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \wl_tap_count_r[2]_i_3\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \wl_tap_count_r[3]_i_3\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \wl_tap_count_r[4]_i_3\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of wr_level_done_i_1 : label is "soft_lutpair124";
  attribute syn_maxfan of wr_level_done_reg : label is "2";
  attribute SOFT_HLUTNM of \wrlvl_redo_corse_inc[1]_i_2\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \wrlvl_redo_corse_inc[2]_i_3\ : label is "soft_lutpair80";
begin
  done_dqs_tap_inc <= \^done_dqs_tap_inc\;
  dqs_po_dec_done <= \^dqs_po_dec_done\;
  dqs_po_en_stg2_f_reg_0 <= \^dqs_po_en_stg2_f_reg_0\;
  p_0_in <= \^p_0_in\;
  wr_level_done_r5 <= \^wr_level_done_r5\;
  wrlvl_byte_done <= \^wrlvl_byte_done\;
  wrlvl_byte_redo_r <= \^wrlvl_byte_redo_r\;
  wrlvl_done_r_reg <= \^wrlvl_done_r_reg\;
  wrlvl_rank_done <= \^wrlvl_rank_done\;
\FSM_sequential_wl_state_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEFEFFFE"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[0]_i_2_n_0\,
      I1 => \FSM_sequential_wl_state_r[0]_i_3_n_0\,
      I2 => \FSM_sequential_wl_state_r[3]_i_6_n_0\,
      I3 => \FSM_sequential_wl_state_r[0]_i_4_n_0\,
      I4 => \FSM_sequential_wl_state_r[0]_i_5_n_0\,
      I5 => \FSM_sequential_wl_state_r[0]_i_6_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => \^p_0_in\,
      O => \FSM_sequential_wl_state_r[0]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(0),
      I2 => wl_state_r(1),
      O => \FSM_sequential_wl_state_r[0]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[5]\,
      I1 => \wl_tap_count_r_reg_n_0_[3]\,
      I2 => \wl_tap_count_r_reg_n_0_[4]\,
      I3 => wl_state_r(4),
      I4 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => wr_level_start_r,
      I1 => wl_sm_start,
      I2 => wr_level_done_r_reg_n_0,
      O => wl_state_r1
    );
\FSM_sequential_wl_state_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0035"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[0]_i_7_n_0\,
      I1 => \FSM_sequential_wl_state_r[0]_i_8_n_0\,
      I2 => wl_state_r(0),
      I3 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[0]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF404000000000"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I1 => wl_state_r(3),
      I2 => wl_state_r(0),
      I3 => \FSM_sequential_wl_state_r[0]_i_9_n_0\,
      I4 => wl_state_r(1),
      I5 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[0]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF1110FFFF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I1 => wrlvl_byte_redo_reg,
      I2 => \fine_inc[0][5]_i_3_n_0\,
      I3 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      I4 => wl_state_r(0),
      I5 => \FSM_sequential_wl_state_r[0]_i_10_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"07FF"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => \^p_0_in\,
      I2 => wl_state_r(2),
      I3 => wl_state_r(4),
      O => \FSM_sequential_wl_state_r[0]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[0]_i_11_n_0\,
      I1 => \corse_cnt__0\(1),
      I2 => \corse_cnt__0\(0),
      I3 => \corse_cnt__0\(2),
      I4 => wl_edge_detect_valid_r_reg_n_0,
      I5 => \FSM_sequential_wl_state_r[0]_i_12_n_0\,
      O => \FSM_sequential_wl_state_r[0]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000FC005"
    )
        port map (
      I0 => wl_state_r1,
      I1 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(3),
      I4 => wl_state_r(4),
      O => \FSM_sequential_wl_state_r[0]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCBFBFBCBF"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(3),
      I3 => wrlvl_byte_redo,
      I4 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I5 => wl_state_r(4),
      O => \FSM_sequential_wl_state_r[0]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FB00FB00FB"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => flag_ck_negedge_i_6_n_0,
      I2 => stable_cnt227_in,
      I3 => wl_state_r(4),
      I4 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I5 => wl_state_r(3),
      O => \FSM_sequential_wl_state_r[0]_i_9_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF40FF73"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[1]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => \FSM_sequential_wl_state_r[1]_i_3_n_0\,
      I3 => \FSM_sequential_wl_state_r[1]_i_4_n_0\,
      I4 => \FSM_sequential_wl_state_r[1]_i_5_n_0\,
      I5 => \FSM_sequential_wl_state_r[1]_i_6_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"666F6F6F"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I4 => wl_state_r(3),
      O => \FSM_sequential_wl_state_r[1]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F020F020F0202020"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \corse_dec_reg[0][2]_i_4_n_0\,
      I5 => \corse_dec[0][1]_i_4_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \corse_cnt__0\(1),
      I1 => \corse_cnt__0\(0),
      I2 => \corse_cnt__0\(2),
      I3 => wl_edge_detect_valid_r_reg_n_0,
      O => \FSM_sequential_wl_state_r[1]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[4]\,
      I1 => \wl_tap_count_r_reg_n_0_[3]\,
      I2 => \wl_tap_count_r_reg_n_0_[5]\,
      O => \FSM_sequential_wl_state_r[1]_i_13_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I1 => wrlvl_byte_redo,
      O => \FSM_sequential_wl_state_r[1]_i_14_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080808080808000"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => wl_state_r(2),
      I2 => wl_state_r(4),
      I3 => wrlvl_redo_corse_inc(1),
      I4 => wrlvl_redo_corse_inc(0),
      I5 => wrlvl_redo_corse_inc(2),
      O => \FSM_sequential_wl_state_r[1]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAFB"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[1]_i_7_n_0\,
      I1 => wl_state_r(4),
      I2 => \fine_inc[0][5]_i_3_n_0\,
      I3 => \FSM_sequential_wl_state_r[1]_i_8_n_0\,
      I4 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I5 => \FSM_sequential_wl_state_r[1]_i_9_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000004EEEEEEE"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(2),
      I2 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I3 => wl_edge_detect_valid_r_reg_n_0,
      I4 => wl_state_r(3),
      I5 => \FSM_sequential_wl_state_r[1]_i_10_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000F7F5F7F"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => wl_state_r(2),
      I3 => wl_state_r(1),
      I4 => \FSM_sequential_wl_state_r[3]_i_10_n_0\,
      I5 => \FSM_sequential_wl_state_r[1]_i_11_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(2),
      I2 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      I3 => \FSM_sequential_wl_state_r[1]_i_12_n_0\,
      I4 => \FSM_sequential_wl_state_r[1]_i_13_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000F0B0B000F0B00"
    )
        port map (
      I0 => wrlvl_byte_redo_reg,
      I1 => wl_state_r(4),
      I2 => wl_state_r(1),
      I3 => wl_state_r(2),
      I4 => wl_state_r(3),
      I5 => \FSM_sequential_wl_state_r[1]_i_14_n_0\,
      O => \FSM_sequential_wl_state_r[1]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[1]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000070"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => wl_state_r(3),
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[1]_i_9_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FB00FF000000FF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[2]_i_2_n_0\,
      I1 => \FSM_sequential_wl_state_r[2]_i_3_n_0\,
      I2 => \FSM_sequential_wl_state_r[2]_i_4_n_0\,
      I3 => \FSM_sequential_wl_state_r[2]_i_5_n_0\,
      I4 => \FSM_sequential_wl_state_r[2]_i_6_n_0\,
      I5 => \FSM_sequential_wl_state_r[2]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(0),
      O => \FSM_sequential_wl_state_r[2]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000077F077FFFFF"
    )
        port map (
      I0 => \corse_cnt__0\(0),
      I1 => wrlvl_redo_corse_inc(0),
      I2 => \corse_cnt__0\(1),
      I3 => wrlvl_redo_corse_inc(1),
      I4 => wrlvl_redo_corse_inc(2),
      I5 => \corse_cnt__0\(2),
      O => \FSM_sequential_wl_state_r[2]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => wrlvl_redo_corse_inc(2),
      I1 => wrlvl_redo_corse_inc(0),
      I2 => wrlvl_redo_corse_inc(1),
      I3 => wl_state_r(4),
      I4 => wl_state_r(0),
      I5 => wl_state_r(1),
      O => \FSM_sequential_wl_state_r[2]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(4),
      O => \FSM_sequential_wl_state_r[2]_i_13_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"101000001010F000"
    )
        port map (
      I0 => wl_edge_detect_valid_r_reg_n_0,
      I1 => wl_state_r(0),
      I2 => wl_state_r(3),
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_14_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C0C9D9D0C0CBF9D"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(1),
      I2 => \FSM_sequential_wl_state_r[2]_i_8_n_0\,
      I3 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      I4 => wl_state_r(0),
      I5 => \fine_inc[0][5]_i_3_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FC55FC55FFFFFCFF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I1 => wl_state_r(2),
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => wl_state_r(3),
      I5 => wl_state_r(0),
      O => \FSM_sequential_wl_state_r[2]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5141515151415141"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => wrlvl_byte_redo_reg,
      I4 => \fine_inc[0][5]_i_3_n_0\,
      I5 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000082AAAAAAAA"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => wl_state_r(2),
      I2 => wl_state_r(1),
      I3 => \FSM_sequential_wl_state_r[2]_i_10_n_0\,
      I4 => \FSM_sequential_wl_state_r[2]_i_11_n_0\,
      I5 => \FSM_sequential_wl_state_r[2]_i_12_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFBFFFFF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[2]_i_13_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I3 => wl_state_r(3),
      I4 => wl_state_r(0),
      I5 => \FSM_sequential_wl_state_r[2]_i_14_n_0\,
      O => \FSM_sequential_wl_state_r[2]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF30503030"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(1),
      I3 => wl_state_r(0),
      I4 => wl_state_r(3),
      I5 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[2]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[2]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFBFFF"
    )
        port map (
      I0 => stable_cnt227_in,
      I1 => \stable_cnt_reg_n_0_[3]\,
      I2 => \stable_cnt_reg_n_0_[2]\,
      I3 => \stable_cnt_reg_n_0_[1]\,
      I4 => wl_state_r(0),
      O => \FSM_sequential_wl_state_r[2]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF5510"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => \FSM_sequential_wl_state_r[3]_i_3_n_0\,
      I3 => \FSM_sequential_wl_state_r[3]_i_4_n_0\,
      I4 => \FSM_sequential_wl_state_r[3]_i_5_n_0\,
      I5 => \FSM_sequential_wl_state_r[3]_i_6_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_1_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[1]\,
      I1 => \stable_cnt_reg_n_0_[2]\,
      I2 => \stable_cnt_reg_n_0_[3]\,
      I3 => stable_cnt227_in,
      O => \FSM_sequential_wl_state_r[3]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \fine_dec_cnt__0\(5),
      I1 => \fine_dec_cnt__0\(4),
      I2 => \fine_dec_cnt__0\(2),
      I3 => \fine_dec_cnt__0\(1),
      I4 => \fine_dec_cnt__0\(0),
      I5 => \fine_dec_cnt__0\(3),
      O => \FSM_sequential_wl_state_r[3]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F02FF025FFFFFFFF"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => \^wr_level_done_r5\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I5 => wl_state_r(0),
      O => \FSM_sequential_wl_state_r[3]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E000E0E"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => wrlvl_byte_redo,
      I3 => \^wr_level_done_r5\,
      I4 => wl_sm_start,
      I5 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6F"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(3),
      I2 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[3]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF44044404440444"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_8_n_0\,
      I1 => \FSM_sequential_wl_state_r[3]_i_9_n_0\,
      I2 => \FSM_sequential_wl_state_r[3]_i_10_n_0\,
      I3 => wl_state_r(1),
      I4 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I5 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FE0000000000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_3_n_0\,
      I1 => \FSM_sequential_wl_state_r[3]_i_7_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(3),
      I4 => wl_state_r(0),
      I5 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[3]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(3),
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I3 => dqs_count_r(0),
      O => \FSM_sequential_wl_state_r[3]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDBBFFFF"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(3),
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \FSM_sequential_wl_state_r[0]_i_12_n_0\,
      O => \FSM_sequential_wl_state_r[3]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wl_edge_detect_valid_r_reg_n_0,
      I1 => wl_state_r(4),
      O => \FSM_sequential_wl_state_r[3]_i_9_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001FFFFFF"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => wl_sm_start,
      I2 => wrlvl_byte_redo,
      I3 => wl_state_r(4),
      I4 => wl_state_r(0),
      I5 => \FSM_sequential_wl_state_r[4]_i_17_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_10_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08FF080808080808"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc[2]_i_3_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => \^wrlvl_byte_redo_r\,
      I3 => wr_level_done_r_reg_n_0,
      I4 => wl_sm_start,
      I5 => wr_level_start_r,
      O => \FSM_sequential_wl_state_r[4]_i_11_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \incdec_wait_cnt_reg__0\(1),
      I1 => \incdec_wait_cnt_reg__0\(0),
      I2 => \incdec_wait_cnt_reg__0\(3),
      I3 => \incdec_wait_cnt_reg__0\(2),
      O => \FSM_sequential_wl_state_r[4]_i_12_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_4_n_0\,
      I1 => \corse_inc[0][0]_i_2_n_0\,
      I2 => \corse_inc_reg[0][2]_i_5_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_13_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[4]_i_14_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555545"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => \incdec_wait_cnt_reg__0\(2),
      I2 => \incdec_wait_cnt_reg__0\(3),
      I3 => \incdec_wait_cnt_reg__0\(0),
      I4 => \incdec_wait_cnt_reg__0\(1),
      O => \FSM_sequential_wl_state_r[4]_i_15_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(0),
      O => \FSM_sequential_wl_state_r[4]_i_16_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500000200"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => \incdec_wait_cnt_reg__0\(1),
      I2 => \incdec_wait_cnt_reg__0\(0),
      I3 => \incdec_wait_cnt_reg__0\(3),
      I4 => \incdec_wait_cnt_reg__0\(2),
      I5 => wl_state_r(0),
      O => \FSM_sequential_wl_state_r[4]_i_17_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDCDFDFD"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_4_n_0\,
      I1 => \FSM_sequential_wl_state_r[4]_i_5_n_0\,
      I2 => wl_state_r(3),
      I3 => \FSM_sequential_wl_state_r[4]_i_6_n_0\,
      I4 => \FSM_sequential_wl_state_r[4]_i_7_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_2_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00505040"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_8_n_0\,
      I1 => wl_edge_detect_valid_r_reg_n_0,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => wl_state_r(0),
      I5 => \FSM_sequential_wl_state_r[4]_i_9_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_3_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00CCFFCC000CFFDD"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => \FSM_sequential_wl_state_r[4]_i_10_n_0\,
      I2 => wl_state_r(2),
      I3 => wl_state_r(1),
      I4 => wl_sm_start,
      I5 => wl_state_r(4),
      O => \FSM_sequential_wl_state_r[4]_i_4_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"015B015A"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => wl_state_r(2),
      I4 => \FSM_sequential_wl_state_r[4]_i_11_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_5_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00CB"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_12_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(1),
      I3 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[4]_i_6_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0037"
    )
        port map (
      I0 => \fine_inc[0][5]_i_3_n_0\,
      I1 => \^wr_level_done_r5\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => wl_state_r(1),
      I4 => \FSM_sequential_wl_state_r[4]_i_14_n_0\,
      I5 => \FSM_sequential_wl_state_r[4]_i_15_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_7_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FBFFFF00FB00FB"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => wl_sm_start,
      I2 => wrlvl_byte_redo,
      I3 => \wl_tap_count_r[5]_i_6_n_0\,
      I4 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I5 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      O => \FSM_sequential_wl_state_r[4]_i_8_n_0\
    );
\FSM_sequential_wl_state_r[4]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04115050"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => wl_state_r(2),
      O => \FSM_sequential_wl_state_r[4]_i_9_n_0\
    );
\FSM_sequential_wl_state_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_wl_state_r[4]_i_2_n_0\,
      D => \FSM_sequential_wl_state_r[0]_i_1_n_0\,
      Q => wl_state_r(0),
      R => SR(0)
    );
\FSM_sequential_wl_state_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_wl_state_r[4]_i_2_n_0\,
      D => \FSM_sequential_wl_state_r[1]_i_1_n_0\,
      Q => wl_state_r(1),
      R => SR(0)
    );
\FSM_sequential_wl_state_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_wl_state_r[4]_i_2_n_0\,
      D => \FSM_sequential_wl_state_r[2]_i_1_n_0\,
      Q => wl_state_r(2),
      R => SR(0)
    );
\FSM_sequential_wl_state_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_wl_state_r[4]_i_2_n_0\,
      D => \FSM_sequential_wl_state_r[3]_i_1_n_0\,
      Q => wl_state_r(3),
      R => SR(0)
    );
\FSM_sequential_wl_state_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \FSM_sequential_wl_state_r[4]_i_2_n_0\,
      D => \FSM_sequential_wl_state_r[4]_i_3_n_0\,
      Q => wl_state_r(4),
      R => SR(0)
    );
\corse_cnt[0][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[0][2]_i_3_n_0\,
      I2 => \corse_cnt_reg_n_0_[0][0]\,
      O => \corse_cnt[0][0]_i_1_n_0\
    );
\corse_cnt[0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCEECCCCFC"
    )
        port map (
      I0 => \^p_0_in\,
      I1 => \corse_cnt[0][0]_i_3_n_0\,
      I2 => final_coarse_tap(0),
      I3 => wl_state_r(1),
      I4 => wl_state_r(0),
      I5 => wl_state_r(2),
      O => corse_cnt(0)
    );
\corse_cnt[0][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008F88"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => \corse_cnt_reg[0][0]_i_5_n_0\,
      I2 => \corse_cnt__0\(0),
      I3 => wl_state_r(2),
      I4 => wl_state_r(3),
      O => \corse_cnt[0][0]_i_3_n_0\
    );
\corse_cnt[0][0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][0]\,
      I1 => \final_coarse_tap_reg_n_0_[2][0]\,
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \final_coarse_tap_reg_n_0_[1][0]\,
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \final_coarse_tap_reg_n_0_[0][0]\,
      O => \corse_cnt[0][0]_i_6_n_0\
    );
\corse_cnt[0][0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][0]\,
      I1 => \final_coarse_tap_reg_n_0_[6][0]\,
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \final_coarse_tap_reg_n_0_[5][0]\,
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \final_coarse_tap_reg_n_0_[4][0]\,
      O => \corse_cnt[0][0]_i_7_n_0\
    );
\corse_cnt[0][0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][0]\,
      I1 => \final_coarse_tap_reg_n_0_[2][0]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \final_coarse_tap_reg_n_0_[1][0]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \final_coarse_tap_reg_n_0_[0][0]\,
      O => \corse_cnt[0][0]_i_8_n_0\
    );
\corse_cnt[0][0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][0]\,
      I1 => \final_coarse_tap_reg_n_0_[6][0]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \final_coarse_tap_reg_n_0_[5][0]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \final_coarse_tap_reg_n_0_[4][0]\,
      O => \corse_cnt[0][0]_i_9_n_0\
    );
\corse_cnt[0][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[0][2]_i_3_n_0\,
      I2 => \corse_cnt_reg_n_0_[0][1]\,
      O => \corse_cnt[0][1]_i_1_n_0\
    );
\corse_cnt[0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCEECCCCFC"
    )
        port map (
      I0 => \^p_0_in\,
      I1 => \corse_cnt[0][1]_i_3_n_0\,
      I2 => final_coarse_tap(1),
      I3 => wl_state_r(1),
      I4 => wl_state_r(0),
      I5 => wl_state_r(2),
      O => corse_cnt(1)
    );
\corse_cnt[0][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF002800280028"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => \corse_cnt__0\(1),
      I2 => \corse_cnt__0\(0),
      I3 => wl_state_r(3),
      I4 => wl_state_r(0),
      I5 => \corse_cnt_reg[0][1]_i_5_n_0\,
      O => \corse_cnt[0][1]_i_3_n_0\
    );
\corse_cnt[0][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][1]\,
      I1 => \final_coarse_tap_reg_n_0_[2][1]\,
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \final_coarse_tap_reg_n_0_[1][1]\,
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \final_coarse_tap_reg_n_0_[0][1]\,
      O => \corse_cnt[0][1]_i_6_n_0\
    );
\corse_cnt[0][1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][1]\,
      I1 => \final_coarse_tap_reg_n_0_[6][1]\,
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \final_coarse_tap_reg_n_0_[5][1]\,
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \final_coarse_tap_reg_n_0_[4][1]\,
      O => \corse_cnt[0][1]_i_7_n_0\
    );
\corse_cnt[0][1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][1]\,
      I1 => \final_coarse_tap_reg_n_0_[2][1]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \final_coarse_tap_reg_n_0_[1][1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \final_coarse_tap_reg_n_0_[0][1]\,
      O => \corse_cnt[0][1]_i_8_n_0\
    );
\corse_cnt[0][1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][1]\,
      I1 => \final_coarse_tap_reg_n_0_[6][1]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \final_coarse_tap_reg_n_0_[5][1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \final_coarse_tap_reg_n_0_[4][1]\,
      O => \corse_cnt[0][1]_i_9_n_0\
    );
\corse_cnt[0][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[0][2]_i_3_n_0\,
      I2 => \corse_cnt_reg_n_0_[0][2]\,
      O => \corse_cnt[0][2]_i_1_n_0\
    );
\corse_cnt[0][2]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \corse_cnt__0\(1),
      I1 => \corse_cnt__0\(0),
      O => \corse_cnt[0][2]_i_11_n_0\
    );
\corse_cnt[0][2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][2]\,
      I1 => \final_coarse_tap_reg_n_0_[2][2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \final_coarse_tap_reg_n_0_[1][2]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \final_coarse_tap_reg_n_0_[0][2]\,
      O => \corse_cnt[0][2]_i_12_n_0\
    );
\corse_cnt[0][2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][2]\,
      I1 => \final_coarse_tap_reg_n_0_[6][2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \final_coarse_tap_reg_n_0_[5][2]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \final_coarse_tap_reg_n_0_[4][2]\,
      O => \corse_cnt[0][2]_i_13_n_0\
    );
\corse_cnt[0][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCFCCCCCDD"
    )
        port map (
      I0 => \corse_cnt_reg[0][2]_i_4_n_0\,
      I1 => \corse_cnt[0][2]_i_5_n_0\,
      I2 => \^p_0_in\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(0),
      I5 => wl_state_r(2),
      O => corse_cnt(2)
    );
\corse_cnt[0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[0][5]_i_6_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[0]_0\,
      O => \corse_cnt[0][2]_i_3_n_0\
    );
\corse_cnt[0][2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008800F800F80088"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => \corse_cnt_reg[0][2]_i_10_n_0\,
      I2 => wl_state_r(2),
      I3 => wl_state_r(3),
      I4 => \corse_cnt__0\(2),
      I5 => \corse_cnt[0][2]_i_11_n_0\,
      O => \corse_cnt[0][2]_i_5_n_0\
    );
\corse_cnt[0][2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(3),
      I2 => wl_state_r(0),
      I3 => wl_state_r(4),
      O => \corse_cnt[0][2]_i_6_n_0\
    );
\corse_cnt[0][2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[3][2]\,
      I1 => \final_coarse_tap_reg_n_0_[2][2]\,
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \final_coarse_tap_reg_n_0_[1][2]\,
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \final_coarse_tap_reg_n_0_[0][2]\,
      O => \corse_cnt[0][2]_i_8_n_0\
    );
\corse_cnt[0][2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \final_coarse_tap_reg_n_0_[7][2]\,
      I1 => \final_coarse_tap_reg_n_0_[6][2]\,
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \final_coarse_tap_reg_n_0_[5][2]\,
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \final_coarse_tap_reg_n_0_[4][2]\,
      O => \corse_cnt[0][2]_i_9_n_0\
    );
\corse_cnt[1][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[1][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[1][0]\,
      O => \corse_cnt[1][0]_i_1_n_0\
    );
\corse_cnt[1][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[1][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[1][1]\,
      O => \corse_cnt[1][1]_i_1_n_0\
    );
\corse_cnt[1][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[1][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[1][2]\,
      O => \corse_cnt[1][2]_i_1_n_0\
    );
\corse_cnt[1][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[1][5]_i_3_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[1]_0\,
      O => \corse_cnt[1][2]_i_2_n_0\
    );
\corse_cnt[2][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[2][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[2][0]\,
      O => \corse_cnt[2][0]_i_1_n_0\
    );
\corse_cnt[2][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[2][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[2][1]\,
      O => \corse_cnt[2][1]_i_1_n_0\
    );
\corse_cnt[2][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[2][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[2][2]\,
      O => \corse_cnt[2][2]_i_1_n_0\
    );
\corse_cnt[2][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[2][5]_i_3_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[0]_1\,
      O => \corse_cnt[2][2]_i_2_n_0\
    );
\corse_cnt[3][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[3][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[3][0]\,
      O => \corse_cnt[3][0]_i_1_n_0\
    );
\corse_cnt[3][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[3][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[3][1]\,
      O => \corse_cnt[3][1]_i_1_n_0\
    );
\corse_cnt[3][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[3][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[3][2]\,
      O => \corse_cnt[3][2]_i_1_n_0\
    );
\corse_cnt[3][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[3][5]_i_3_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[1]_1\,
      O => \corse_cnt[3][2]_i_2_n_0\
    );
\corse_cnt[4][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[4][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[4][0]\,
      O => \corse_cnt[4][0]_i_1_n_0\
    );
\corse_cnt[4][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[4][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[4][1]\,
      O => \corse_cnt[4][1]_i_1_n_0\
    );
\corse_cnt[4][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[4][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[4][2]\,
      O => \corse_cnt[4][2]_i_1_n_0\
    );
\corse_cnt[4][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[4][5]_i_3_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[0]_2\,
      O => \corse_cnt[4][2]_i_2_n_0\
    );
\corse_cnt[5][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[5][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[5][0]\,
      O => \corse_cnt[5][0]_i_1_n_0\
    );
\corse_cnt[5][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[5][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[5][1]\,
      O => \corse_cnt[5][1]_i_1_n_0\
    );
\corse_cnt[5][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[5][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[5][2]\,
      O => \corse_cnt[5][2]_i_1_n_0\
    );
\corse_cnt[5][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[5][5]_i_3_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[1]_2\,
      O => \corse_cnt[5][2]_i_2_n_0\
    );
\corse_cnt[6][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[6][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[6][0]\,
      O => \corse_cnt[6][0]_i_1_n_0\
    );
\corse_cnt[6][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[6][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[6][1]\,
      O => \corse_cnt[6][1]_i_1_n_0\
    );
\corse_cnt[6][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[6][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[6][2]\,
      O => \corse_cnt[6][2]_i_1_n_0\
    );
\corse_cnt[6][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[6][5]_i_3_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[0]_3\,
      O => \corse_cnt[6][2]_i_2_n_0\
    );
\corse_cnt[7][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(0),
      I1 => \corse_cnt[7][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[7][0]\,
      O => \corse_cnt[7][0]_i_1_n_0\
    );
\corse_cnt[7][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(1),
      I1 => \corse_cnt[7][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[7][1]\,
      O => \corse_cnt[7][1]_i_1_n_0\
    );
\corse_cnt[7][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => corse_cnt(2),
      I1 => \corse_cnt[7][2]_i_2_n_0\,
      I2 => \corse_cnt_reg_n_0_[7][2]\,
      O => \corse_cnt[7][2]_i_1_n_0\
    );
\corse_cnt[7][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABABBBBAABAAAAA"
    )
        port map (
      I0 => rank_cnt_r,
      I1 => \corse_cnt[0][2]_i_6_n_0\,
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => wl_state_r(2),
      I5 => \po_stg2_wrcal_cnt_reg[1]_3\,
      O => \corse_cnt[7][2]_i_2_n_0\
    );
\corse_cnt_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[0][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[0][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[0][0]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_cnt[0][0]_i_6_n_0\,
      I1 => \corse_cnt[0][0]_i_7_n_0\,
      O => final_coarse_tap(0),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\corse_cnt_reg[0][0]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_cnt[0][0]_i_8_n_0\,
      I1 => \corse_cnt[0][0]_i_9_n_0\,
      O => \corse_cnt_reg[0][0]_i_5_n_0\,
      S => dqs_count_r(2)
    );
\corse_cnt_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[0][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[0][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[0][1]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_cnt[0][1]_i_6_n_0\,
      I1 => \corse_cnt[0][1]_i_7_n_0\,
      O => final_coarse_tap(1),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\corse_cnt_reg[0][1]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_cnt[0][1]_i_8_n_0\,
      I1 => \corse_cnt[0][1]_i_9_n_0\,
      O => \corse_cnt_reg[0][1]_i_5_n_0\,
      S => dqs_count_r(2)
    );
\corse_cnt_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[0][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[0][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_cnt_reg[0][2]_i_10\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_cnt[0][2]_i_12_n_0\,
      I1 => \corse_cnt[0][2]_i_13_n_0\,
      O => \corse_cnt_reg[0][2]_i_10_n_0\,
      S => dqs_count_r(2)
    );
\corse_cnt_reg[0][2]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_cnt[0][2]_i_8_n_0\,
      I1 => \corse_cnt[0][2]_i_9_n_0\,
      O => \corse_cnt_reg[0][2]_i_4_n_0\,
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\corse_cnt_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[1][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[1][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[1][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[1][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[1][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[1][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_cnt_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[2][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[2][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[2][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[2][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[2][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[2][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_cnt_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[3][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[3][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[3][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[3][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[3][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[3][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_cnt_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[4][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[4][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[4][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[4][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[4][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[4][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_cnt_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[5][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[5][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[5][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[5][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[5][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[5][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_cnt_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[6][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[6][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[6][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[6][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[6][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[6][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_cnt_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[7][0]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[7][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[7][1]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[7][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\corse_cnt_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_cnt[7][2]_i_1_n_0\,
      Q => \corse_cnt_reg_n_0_[7][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\corse_dec[0][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[0][5]_i_6_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[0]_30\(0),
      O => \corse_dec[0][0]_i_2_n_0\
    );
\corse_dec[0][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[0][5]_i_6_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[0]_30\(1),
      O => \corse_dec[0][1]_i_1_n_0\
    );
\corse_dec[0][1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \corse_dec[0][1]_i_4_n_0\,
      I1 => \corse_dec_reg[0][2]_i_4_n_0\,
      O => \corse_dec[0][1]_i_2_n_0\
    );
\corse_dec[0][1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \corse_dec_reg[0][1]_i_3_n_0\,
      I1 => \corse_dec_reg[0][2]_i_5_n_0\,
      O => \corse_dec[0][1]_i_4_n_0\
    );
\corse_dec[0][1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[3]_33\(1),
      I1 => \corse_dec_reg[2]_32\(1),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_dec_reg[1]_31\(1),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_dec_reg[0]_30\(1),
      O => \corse_dec[0][1]_i_5_n_0\
    );
\corse_dec[0][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[7]_37\(1),
      I1 => \corse_dec_reg[6]_36\(1),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_dec_reg[5]_35\(1),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_dec_reg[4]_34\(1),
      O => \corse_dec[0][1]_i_6_n_0\
    );
\corse_dec[0][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[0][5]_i_6_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[0]_30\(2),
      O => \corse_dec[0][2]_i_1_n_0\
    );
\corse_dec[0][2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => \corse_dec_reg[0][2]_i_4_n_0\,
      I1 => \corse_dec_reg[0][2]_i_5_n_0\,
      I2 => \corse_dec_reg[0][1]_i_3_n_0\,
      I3 => wl_state_r(3),
      O => corse_dec(2)
    );
\corse_dec[0][2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(1),
      I2 => wl_state_r(3),
      I3 => wl_state_r(4),
      I4 => wl_state_r(2),
      O => \corse_dec[0][2]_i_3_n_0\
    );
\corse_dec[0][2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[3]_33\(0),
      I1 => \corse_dec_reg[2]_32\(0),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_dec_reg[1]_31\(0),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_dec_reg[0]_30\(0),
      O => \corse_dec[0][2]_i_6_n_0\
    );
\corse_dec[0][2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[7]_37\(0),
      I1 => \corse_dec_reg[6]_36\(0),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_dec_reg[5]_35\(0),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_dec_reg[4]_34\(0),
      O => \corse_dec[0][2]_i_7_n_0\
    );
\corse_dec[0][2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[3]_33\(2),
      I1 => \corse_dec_reg[2]_32\(2),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_dec_reg[1]_31\(2),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_dec_reg[0]_30\(2),
      O => \corse_dec[0][2]_i_8_n_0\
    );
\corse_dec[0][2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_dec_reg[7]_37\(2),
      I1 => \corse_dec_reg[6]_36\(2),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_dec_reg[5]_35\(2),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_dec_reg[4]_34\(2),
      O => \corse_dec[0][2]_i_9_n_0\
    );
\corse_dec[1][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[1][5]_i_3_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[1]_31\(0),
      O => \corse_dec[1][0]_i_1_n_0\
    );
\corse_dec[1][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[1][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[1]_31\(1),
      O => \corse_dec[1][1]_i_1_n_0\
    );
\corse_dec[1][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[1][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[1]_31\(2),
      O => \corse_dec[1][2]_i_1_n_0\
    );
\corse_dec[2][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[2][5]_i_3_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[2]_32\(0),
      O => \corse_dec[2][0]_i_1_n_0\
    );
\corse_dec[2][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[2][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[2]_32\(1),
      O => \corse_dec[2][1]_i_1_n_0\
    );
\corse_dec[2][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[2][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[2]_32\(2),
      O => \corse_dec[2][2]_i_1_n_0\
    );
\corse_dec[3][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[3][5]_i_3_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[3]_33\(0),
      O => \corse_dec[3][0]_i_1_n_0\
    );
\corse_dec[3][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[3][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[3]_33\(1),
      O => \corse_dec[3][1]_i_1_n_0\
    );
\corse_dec[3][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[3][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[3]_33\(2),
      O => \corse_dec[3][2]_i_1_n_0\
    );
\corse_dec[4][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[4][5]_i_3_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[4]_34\(0),
      O => \corse_dec[4][0]_i_1_n_0\
    );
\corse_dec[4][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[4][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[4]_34\(1),
      O => \corse_dec[4][1]_i_1_n_0\
    );
\corse_dec[4][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[4][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[4]_34\(2),
      O => \corse_dec[4][2]_i_1_n_0\
    );
\corse_dec[5][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[5][5]_i_3_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[5]_35\(0),
      O => \corse_dec[5][0]_i_1_n_0\
    );
\corse_dec[5][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[5][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[5]_35\(1),
      O => \corse_dec[5][1]_i_1_n_0\
    );
\corse_dec[5][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[5][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[5]_35\(2),
      O => \corse_dec[5][2]_i_1_n_0\
    );
\corse_dec[6][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[6][5]_i_3_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[6]_36\(0),
      O => \corse_dec[6][0]_i_1_n_0\
    );
\corse_dec[6][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[6][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[6]_36\(1),
      O => \corse_dec[6][1]_i_1_n_0\
    );
\corse_dec[6][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[6][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[6]_36\(2),
      O => \corse_dec[6][2]_i_1_n_0\
    );
\corse_dec[7][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2F0020"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => wl_state_r(3),
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \corse_dec[0][2]_i_3_n_0\,
      I4 => \corse_dec_reg[7]_37\(0),
      O => \corse_dec[7][0]_i_1_n_0\
    );
\corse_dec[7][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF06FF00000600"
    )
        port map (
      I0 => \corse_dec[0][1]_i_2_n_0\,
      I1 => \corse_dec_reg[0][1]_i_3_n_0\,
      I2 => wl_state_r(3),
      I3 => \fine_inc[7][5]_i_3_n_0\,
      I4 => \corse_dec[0][2]_i_3_n_0\,
      I5 => \corse_dec_reg[7]_37\(1),
      O => \corse_dec[7][1]_i_1_n_0\
    );
\corse_dec[7][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => corse_dec(2),
      I1 => \fine_inc[7][5]_i_3_n_0\,
      I2 => \corse_dec[0][2]_i_3_n_0\,
      I3 => \corse_dec_reg[7]_37\(2),
      O => \corse_dec[7][2]_i_1_n_0\
    );
\corse_dec_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[0][0]_i_2_n_0\,
      Q => \corse_dec_reg[0]_30\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[0][1]_i_1_n_0\,
      Q => \corse_dec_reg[0]_30\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[0][1]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_dec[0][1]_i_5_n_0\,
      I1 => \corse_dec[0][1]_i_6_n_0\,
      O => \corse_dec_reg[0][1]_i_3_n_0\,
      S => dqs_count_r(2)
    );
\corse_dec_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[0][2]_i_1_n_0\,
      Q => \corse_dec_reg[0]_30\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[0][2]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_dec[0][2]_i_6_n_0\,
      I1 => \corse_dec[0][2]_i_7_n_0\,
      O => \corse_dec_reg[0][2]_i_4_n_0\,
      S => dqs_count_r(2)
    );
\corse_dec_reg[0][2]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_dec[0][2]_i_8_n_0\,
      I1 => \corse_dec[0][2]_i_9_n_0\,
      O => \corse_dec_reg[0][2]_i_5_n_0\,
      S => dqs_count_r(2)
    );
\corse_dec_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[1][0]_i_1_n_0\,
      Q => \corse_dec_reg[1]_31\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[1][1]_i_1_n_0\,
      Q => \corse_dec_reg[1]_31\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[1][2]_i_1_n_0\,
      Q => \corse_dec_reg[1]_31\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[2][0]_i_1_n_0\,
      Q => \corse_dec_reg[2]_32\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[2][1]_i_1_n_0\,
      Q => \corse_dec_reg[2]_32\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[2][2]_i_1_n_0\,
      Q => \corse_dec_reg[2]_32\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[3][0]_i_1_n_0\,
      Q => \corse_dec_reg[3]_33\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[3][1]_i_1_n_0\,
      Q => \corse_dec_reg[3]_33\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[3][2]_i_1_n_0\,
      Q => \corse_dec_reg[3]_33\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[4][0]_i_1_n_0\,
      Q => \corse_dec_reg[4]_34\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[4][1]_i_1_n_0\,
      Q => \corse_dec_reg[4]_34\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[4][2]_i_1_n_0\,
      Q => \corse_dec_reg[4]_34\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[5][0]_i_1_n_0\,
      Q => \corse_dec_reg[5]_35\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[5][1]_i_1_n_0\,
      Q => \corse_dec_reg[5]_35\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[5][2]_i_1_n_0\,
      Q => \corse_dec_reg[5]_35\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[6][0]_i_1_n_0\,
      Q => \corse_dec_reg[6]_36\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[6][1]_i_1_n_0\,
      Q => \corse_dec_reg[6]_36\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[6][2]_i_1_n_0\,
      Q => \corse_dec_reg[6]_36\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[7][0]_i_1_n_0\,
      Q => \corse_dec_reg[7]_37\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_dec_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[7][1]_i_1_n_0\,
      Q => \corse_dec_reg[7]_37\(1),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_dec_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_dec[7][2]_i_1_n_0\,
      Q => \corse_dec_reg[7]_37\(2),
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\corse_inc[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[0][0]\,
      I4 => \corse_inc[0][2]_i_3_n_0\,
      I5 => \corse_inc_reg[0]_38\(0),
      O => \corse_inc[0][0]_i_1_n_0\
    );
\corse_inc[0][0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \corse_inc[0][0]_i_3_n_0\,
      I1 => \corse_inc[0][0]_i_4_n_0\,
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      O => \corse_inc[0][0]_i_2_n_0\
    );
\corse_inc[0][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[3]_41\(0),
      I1 => \corse_inc_reg[2]_40\(0),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_inc_reg[1]_39\(0),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_inc_reg[0]_38\(0),
      O => \corse_inc[0][0]_i_3_n_0\
    );
\corse_inc[0][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[7]_45\(0),
      I1 => \corse_inc_reg[6]_44\(0),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_inc_reg[5]_43\(0),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_inc_reg[4]_42\(0),
      O => \corse_inc[0][0]_i_4_n_0\
    );
\corse_inc[0][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[0][1]\,
      I4 => \corse_inc[0][2]_i_3_n_0\,
      I5 => \corse_inc_reg[0]_38\(1),
      O => \corse_inc[0][1]_i_1_n_0\
    );
\corse_inc[0][1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0009"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => \corse_inc_reg[0][2]_i_4_n_0\,
      I2 => wl_state_r(0),
      I3 => wl_state_r(4),
      O => \corse_inc[0][1]_i_2_n_0\
    );
\corse_inc[0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[0][2]\,
      I4 => \corse_inc[0][2]_i_3_n_0\,
      I5 => \corse_inc_reg[0]_38\(2),
      O => \corse_inc[0][2]_i_1_n_0\
    );
\corse_inc[0][2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[7]_45\(2),
      I1 => \corse_inc_reg[6]_44\(2),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_inc_reg[5]_43\(2),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_inc_reg[4]_42\(2),
      O => \corse_inc[0][2]_i_10_n_0\
    );
\corse_inc[0][2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E1"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_4_n_0\,
      I1 => \corse_inc[0][0]_i_2_n_0\,
      I2 => \corse_inc_reg[0][2]_i_5_n_0\,
      I3 => wl_state_r(0),
      I4 => wl_state_r(4),
      O => \corse_inc[0][2]_i_2_n_0\
    );
\corse_inc[0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[0][5]_i_6_n_0\,
      O => \corse_inc[0][2]_i_3_n_0\
    );
\corse_inc[0][2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(0),
      I2 => wl_state_r(3),
      I3 => wl_state_r(1),
      I4 => wl_state_r(2),
      O => \corse_inc[0][2]_i_6_n_0\
    );
\corse_inc[0][2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[3]_41\(1),
      I1 => \corse_inc_reg[2]_40\(1),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_inc_reg[1]_39\(1),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_inc_reg[0]_38\(1),
      O => \corse_inc[0][2]_i_7_n_0\
    );
\corse_inc[0][2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[7]_45\(1),
      I1 => \corse_inc_reg[6]_44\(1),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_inc_reg[5]_43\(1),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_inc_reg[4]_42\(1),
      O => \corse_inc[0][2]_i_8_n_0\
    );
\corse_inc[0][2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_inc_reg[3]_41\(2),
      I1 => \corse_inc_reg[2]_40\(2),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_inc_reg[1]_39\(2),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_inc_reg[0]_38\(2),
      O => \corse_inc[0][2]_i_9_n_0\
    );
\corse_inc[1][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[1][0]\,
      I4 => \corse_inc[1][2]_i_2_n_0\,
      I5 => \corse_inc_reg[1]_39\(0),
      O => \corse_inc[1][0]_i_1_n_0\
    );
\corse_inc[1][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[1][1]\,
      I4 => \corse_inc[1][2]_i_2_n_0\,
      I5 => \corse_inc_reg[1]_39\(1),
      O => \corse_inc[1][1]_i_1_n_0\
    );
\corse_inc[1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[1][2]\,
      I4 => \corse_inc[1][2]_i_2_n_0\,
      I5 => \corse_inc_reg[1]_39\(2),
      O => \corse_inc[1][2]_i_1_n_0\
    );
\corse_inc[1][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[1][5]_i_3_n_0\,
      O => \corse_inc[1][2]_i_2_n_0\
    );
\corse_inc[2][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[2][0]\,
      I4 => \corse_inc[2][2]_i_2_n_0\,
      I5 => \corse_inc_reg[2]_40\(0),
      O => \corse_inc[2][0]_i_1_n_0\
    );
\corse_inc[2][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[2][1]\,
      I4 => \corse_inc[2][2]_i_2_n_0\,
      I5 => \corse_inc_reg[2]_40\(1),
      O => \corse_inc[2][1]_i_1_n_0\
    );
\corse_inc[2][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[2][2]\,
      I4 => \corse_inc[2][2]_i_2_n_0\,
      I5 => \corse_inc_reg[2]_40\(2),
      O => \corse_inc[2][2]_i_1_n_0\
    );
\corse_inc[2][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[2][5]_i_3_n_0\,
      O => \corse_inc[2][2]_i_2_n_0\
    );
\corse_inc[3][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[3][0]\,
      I4 => \corse_inc[3][2]_i_2_n_0\,
      I5 => \corse_inc_reg[3]_41\(0),
      O => \corse_inc[3][0]_i_1_n_0\
    );
\corse_inc[3][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[3][1]\,
      I4 => \corse_inc[3][2]_i_2_n_0\,
      I5 => \corse_inc_reg[3]_41\(1),
      O => \corse_inc[3][1]_i_1_n_0\
    );
\corse_inc[3][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[3][2]\,
      I4 => \corse_inc[3][2]_i_2_n_0\,
      I5 => \corse_inc_reg[3]_41\(2),
      O => \corse_inc[3][2]_i_1_n_0\
    );
\corse_inc[3][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[3][5]_i_3_n_0\,
      O => \corse_inc[3][2]_i_2_n_0\
    );
\corse_inc[4][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[4][0]\,
      I4 => \corse_inc[4][2]_i_2_n_0\,
      I5 => \corse_inc_reg[4]_42\(0),
      O => \corse_inc[4][0]_i_1_n_0\
    );
\corse_inc[4][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[4][1]\,
      I4 => \corse_inc[4][2]_i_2_n_0\,
      I5 => \corse_inc_reg[4]_42\(1),
      O => \corse_inc[4][1]_i_1_n_0\
    );
\corse_inc[4][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[4][2]\,
      I4 => \corse_inc[4][2]_i_2_n_0\,
      I5 => \corse_inc_reg[4]_42\(2),
      O => \corse_inc[4][2]_i_1_n_0\
    );
\corse_inc[4][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[4][5]_i_3_n_0\,
      O => \corse_inc[4][2]_i_2_n_0\
    );
\corse_inc[5][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[5][0]\,
      I4 => \corse_inc[5][2]_i_2_n_0\,
      I5 => \corse_inc_reg[5]_43\(0),
      O => \corse_inc[5][0]_i_1_n_0\
    );
\corse_inc[5][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[5][1]\,
      I4 => \corse_inc[5][2]_i_2_n_0\,
      I5 => \corse_inc_reg[5]_43\(1),
      O => \corse_inc[5][1]_i_1_n_0\
    );
\corse_inc[5][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[5][2]\,
      I4 => \corse_inc[5][2]_i_2_n_0\,
      I5 => \corse_inc_reg[5]_43\(2),
      O => \corse_inc[5][2]_i_1_n_0\
    );
\corse_inc[5][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[5][5]_i_3_n_0\,
      O => \corse_inc[5][2]_i_2_n_0\
    );
\corse_inc[6][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[6][0]\,
      I4 => \corse_inc[6][2]_i_2_n_0\,
      I5 => \corse_inc_reg[6]_44\(0),
      O => \corse_inc[6][0]_i_1_n_0\
    );
\corse_inc[6][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[6][1]\,
      I4 => \corse_inc[6][2]_i_2_n_0\,
      I5 => \corse_inc_reg[6]_44\(1),
      O => \corse_inc[6][1]_i_1_n_0\
    );
\corse_inc[6][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[6][2]\,
      I4 => \corse_inc[6][2]_i_2_n_0\,
      I5 => \corse_inc_reg[6]_44\(2),
      O => \corse_inc[6][2]_i_1_n_0\
    );
\corse_inc[6][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[6][5]_i_3_n_0\,
      O => \corse_inc[6][2]_i_2_n_0\
    );
\corse_inc[7][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0D01FFFF0D010000"
    )
        port map (
      I0 => \corse_inc[0][0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => \final_coarse_tap_reg_n_0_[7][0]\,
      I4 => \corse_inc[7][2]_i_2_n_0\,
      I5 => \corse_inc_reg[7]_45\(0),
      O => \corse_inc[7][0]_i_1_n_0\
    );
\corse_inc[7][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[7][1]\,
      I4 => \corse_inc[7][2]_i_2_n_0\,
      I5 => \corse_inc_reg[7]_45\(1),
      O => \corse_inc[7][1]_i_1_n_0\
    );
\corse_inc[7][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAFFFFBAAA0000"
    )
        port map (
      I0 => \corse_inc[0][2]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => \final_coarse_tap_reg_n_0_[7][2]\,
      I4 => \corse_inc[7][2]_i_2_n_0\,
      I5 => \corse_inc_reg[7]_45\(2),
      O => \corse_inc[7][2]_i_1_n_0\
    );
\corse_inc[7][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => wrlvl_byte_redo,
      I5 => \fine_inc[7][5]_i_3_n_0\,
      O => \corse_inc[7][2]_i_2_n_0\
    );
\corse_inc_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[0][0]_i_1_n_0\,
      Q => \corse_inc_reg[0]_38\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[0][1]_i_1_n_0\,
      Q => \corse_inc_reg[0]_38\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[0][2]_i_1_n_0\,
      Q => \corse_inc_reg[0]_38\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[0][2]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_inc[0][2]_i_7_n_0\,
      I1 => \corse_inc[0][2]_i_8_n_0\,
      O => \corse_inc_reg[0][2]_i_4_n_0\,
      S => dqs_count_r(2)
    );
\corse_inc_reg[0][2]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \corse_inc[0][2]_i_9_n_0\,
      I1 => \corse_inc[0][2]_i_10_n_0\,
      O => \corse_inc_reg[0][2]_i_5_n_0\,
      S => dqs_count_r(2)
    );
\corse_inc_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[1][0]_i_1_n_0\,
      Q => \corse_inc_reg[1]_39\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[1][1]_i_1_n_0\,
      Q => \corse_inc_reg[1]_39\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[1][2]_i_1_n_0\,
      Q => \corse_inc_reg[1]_39\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[2][0]_i_1_n_0\,
      Q => \corse_inc_reg[2]_40\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[2][1]_i_1_n_0\,
      Q => \corse_inc_reg[2]_40\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[2][2]_i_1_n_0\,
      Q => \corse_inc_reg[2]_40\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[3][0]_i_1_n_0\,
      Q => \corse_inc_reg[3]_41\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[3][1]_i_1_n_0\,
      Q => \corse_inc_reg[3]_41\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[3][2]_i_1_n_0\,
      Q => \corse_inc_reg[3]_41\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[4][0]_i_1_n_0\,
      Q => \corse_inc_reg[4]_42\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[4][1]_i_1_n_0\,
      Q => \corse_inc_reg[4]_42\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[4][2]_i_1_n_0\,
      Q => \corse_inc_reg[4]_42\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[5][0]_i_1_n_0\,
      Q => \corse_inc_reg[5]_43\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[5][1]_i_1_n_0\,
      Q => \corse_inc_reg[5]_43\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[5][2]_i_1_n_0\,
      Q => \corse_inc_reg[5]_43\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[6][0]_i_1_n_0\,
      Q => \corse_inc_reg[6]_44\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[6][1]_i_1_n_0\,
      Q => \corse_inc_reg[6]_44\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[6][2]_i_1_n_0\,
      Q => \corse_inc_reg[6]_44\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[7][0]_i_1_n_0\,
      Q => \corse_inc_reg[7]_45\(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[7][1]_i_1_n_0\,
      Q => \corse_inc_reg[7]_45\(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\corse_inc_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \corse_inc[7][2]_i_1_n_0\,
      Q => \corse_inc_reg[7]_45\(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\ctl_lane_cnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23\,
      I1 => \^dqs_po_dec_done\,
      I2 => pi_fine_dly_dec_done,
      O => p_1_in
    );
dq_cnt_inc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF15FF00001500"
    )
        port map (
      I0 => \fine_inc[7][5]_i_3_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => wl_state_r(3),
      I3 => dq_cnt_inc_i_2_n_0,
      I4 => dq_cnt_inc_i_3_n_0,
      I5 => \^p_0_in\,
      O => dq_cnt_inc_i_1_n_0
    );
dq_cnt_inc_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(2),
      O => dq_cnt_inc_i_2_n_0
    );
dq_cnt_inc_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(0),
      O => dq_cnt_inc_i_3_n_0
    );
dq_cnt_inc_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => dq_cnt_inc_i_1_n_0,
      Q => \^p_0_in\,
      S => \rstdiv0_sync_r1_reg_rep__5\
    );
\dqs_count_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF04"
    )
        port map (
      I0 => \dqs_count_r[0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(2),
      I3 => \dqs_count_r[0]_i_3_n_0\,
      I4 => \dqs_count_r[0]_i_4_n_0\,
      O => \dqs_count_r[0]_i_1_n_0\
    );
\dqs_count_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"330C770C330C3C0C"
    )
        port map (
      I0 => \^p_0_in\,
      I1 => dqs_count_r(0),
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => wl_state_r(3),
      I4 => wrlvl_byte_redo,
      I5 => wl_state_r(1),
      O => \dqs_count_r[0]_i_2_n_0\
    );
\dqs_count_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F5F5F44001F001F"
    )
        port map (
      I0 => \dqs_count_r[3]_i_11_n_0\,
      I1 => \dqs_count_r[1]_i_6_n_0\,
      I2 => \dqs_count_r[1]_i_7_n_0\,
      I3 => \fine_inc[0][5]_i_3_n_0\,
      I4 => \fine_inc[7][5]_i_3_n_0\,
      I5 => dqs_count_r(0),
      O => \dqs_count_r[0]_i_3_n_0\
    );
\dqs_count_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F111F1F0F000000"
    )
        port map (
      I0 => \dqs_count_r[1]_i_10_n_0\,
      I1 => dqs_count_r140_out,
      I2 => \dqs_count_r[1]_i_9_n_0\,
      I3 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I4 => done_dqs_dec239_out,
      I5 => dqs_count_r(0),
      O => \dqs_count_r[0]_i_4_n_0\
    );
\dqs_count_r[0]_rep_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF04"
    )
        port map (
      I0 => \dqs_count_r[0]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(2),
      I3 => \dqs_count_r[0]_i_3_n_0\,
      I4 => \dqs_count_r[0]_i_4_n_0\,
      O => \dqs_count_r[0]_rep_i_1_n_0\
    );
\dqs_count_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF04"
    )
        port map (
      I0 => \dqs_count_r[1]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(2),
      I3 => \dqs_count_r[1]_i_3_n_0\,
      I4 => \dqs_count_r[1]_i_4_n_0\,
      O => \dqs_count_r[1]_i_1_n_0\
    );
\dqs_count_r[1]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(4),
      I2 => wl_state_r(3),
      O => \dqs_count_r[1]_i_10_n_0\
    );
\dqs_count_r[1]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wr_level_done_r4,
      I1 => \^wr_level_done_r5\,
      O => dqs_count_r140_out
    );
\dqs_count_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000057FFFFFF"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => \^p_0_in\,
      I2 => wrlvl_byte_redo,
      I3 => wl_state_r(3),
      I4 => wl_state_r(1),
      I5 => \dqs_count_r[1]_i_5_n_0\,
      O => \dqs_count_r[1]_i_2_n_0\
    );
\dqs_count_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F005F1F5F004400"
    )
        port map (
      I0 => \dqs_count_r[3]_i_11_n_0\,
      I1 => \dqs_count_r[1]_i_6_n_0\,
      I2 => \dqs_count_r[1]_i_7_n_0\,
      I3 => dqs_count_r(1),
      I4 => \fine_inc[0][5]_i_3_n_0\,
      I5 => \dqs_count_r[1]_i_8_n_0\,
      O => \dqs_count_r[1]_i_3_n_0\
    );
\dqs_count_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4545404045FF4040"
    )
        port map (
      I0 => \dqs_count_r[1]_i_9_n_0\,
      I1 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I2 => done_dqs_dec239_out,
      I3 => \dqs_count_r[1]_i_10_n_0\,
      I4 => dqs_count_r(1),
      I5 => dqs_count_r140_out,
      O => \dqs_count_r[1]_i_4_n_0\
    );
\dqs_count_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F400F1F5F5F0F00"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wrlvl_byte_redo,
      I2 => wl_state_r(3),
      I3 => \fine_inc[7][5]_i_3_n_0\,
      I4 => dqs_count_r(1),
      I5 => dqs_count_r(0),
      O => \dqs_count_r[1]_i_5_n_0\
    );
\dqs_count_r[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \corse_inc_reg[0][2]_i_4_n_0\,
      I1 => \corse_inc[0][0]_i_2_n_0\,
      I2 => \corse_inc_reg[0][2]_i_5_n_0\,
      I3 => wrlvl_byte_redo,
      I4 => \^wr_level_done_r5\,
      O => \dqs_count_r[1]_i_6_n_0\
    );
\dqs_count_r[1]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(3),
      I2 => wl_state_r(4),
      O => \dqs_count_r[1]_i_7_n_0\
    );
\dqs_count_r[1]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2FF0"
    )
        port map (
      I0 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I1 => dqs_count_r(3),
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(0),
      O => \dqs_count_r[1]_i_8_n_0\
    );
\dqs_count_r[1]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(4),
      O => \dqs_count_r[1]_i_9_n_0\
    );
\dqs_count_r[1]_rep_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF04"
    )
        port map (
      I0 => \dqs_count_r[1]_i_2_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(2),
      I3 => \dqs_count_r[1]_i_3_n_0\,
      I4 => \dqs_count_r[1]_i_4_n_0\,
      O => \dqs_count_r[1]_rep_i_1_n_0\
    );
\dqs_count_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0DFF0DFFFFFF0D"
    )
        port map (
      I0 => \dqs_count_r[2]_i_2_n_0\,
      I1 => \dqs_count_r[2]_i_3_n_0\,
      I2 => wl_state_r(4),
      I3 => \dqs_count_r[2]_i_4_n_0\,
      I4 => \dqs_count_r[2]_i_5_n_0\,
      I5 => \dqs_count_r[2]_i_6_n_0\,
      O => \dqs_count_r[2]_i_1_n_0\
    );
\dqs_count_r[2]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BF40FF40"
    )
        port map (
      I0 => wrlvl_byte_redo,
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(0),
      I3 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I4 => dqs_count_r(3),
      O => \dqs_count_r[2]_i_10_n_0\
    );
\dqs_count_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77F7FFFF"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(3),
      I2 => wr_level_done_r4,
      I3 => \^wr_level_done_r5\,
      I4 => \dqs_count_r_reg[2]_rep__0_n_0\,
      O => \dqs_count_r[2]_i_2_n_0\
    );
\dqs_count_r[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAA8A0022"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => dqs_count_r(3),
      I3 => \dqs_count_r[2]_i_7_n_0\,
      I4 => \dqs_count_r_reg[2]_rep_n_0\,
      I5 => \dqs_count_r[2]_i_8_n_0\,
      O => \dqs_count_r[2]_i_3_n_0\
    );
\dqs_count_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F0F0E2F0"
    )
        port map (
      I0 => \dqs_count_r[2]_i_9_n_0\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => \dqs_count_r[3]_i_10_n_0\,
      I4 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I5 => \dqs_count_r[3]_i_11_n_0\,
      O => \dqs_count_r[2]_i_4_n_0\
    );
\dqs_count_r[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(2),
      O => \dqs_count_r[2]_i_5_n_0\
    );
\dqs_count_r[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F303F3F353535353"
    )
        port map (
      I0 => \dqs_count_r[2]_i_10_n_0\,
      I1 => \dqs_count_r[2]_i_9_n_0\,
      I2 => wl_state_r(3),
      I3 => wrlvl_byte_redo_reg_0,
      I4 => \dqs_count_r_reg[2]_rep_n_0\,
      I5 => wl_state_r(1),
      O => \dqs_count_r[2]_i_6_n_0\
    );
\dqs_count_r[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      O => \dqs_count_r[2]_i_7_n_0\
    );
\dqs_count_r[2]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I1 => \^wrlvl_byte_redo_r\,
      I2 => wrlvl_byte_redo,
      I3 => \po_stg2_wrcal_cnt_reg[3]\(2),
      I4 => wl_state_r(3),
      O => \dqs_count_r[2]_i_8_n_0\
    );
\dqs_count_r[2]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FC0"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => dqs_count_r(0),
      I2 => dqs_count_r(1),
      I3 => \dqs_count_r_reg[2]_rep__0_n_0\,
      O => \dqs_count_r[2]_i_9_n_0\
    );
\dqs_count_r[2]_rep__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0DFF0DFFFFFF0D"
    )
        port map (
      I0 => \dqs_count_r[2]_i_2_n_0\,
      I1 => \dqs_count_r[2]_i_3_n_0\,
      I2 => wl_state_r(4),
      I3 => \dqs_count_r[2]_i_4_n_0\,
      I4 => \dqs_count_r[2]_i_5_n_0\,
      I5 => \dqs_count_r[2]_i_6_n_0\,
      O => \dqs_count_r[2]_rep__0_i_1_n_0\
    );
\dqs_count_r[2]_rep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0DFF0DFFFFFF0D"
    )
        port map (
      I0 => \dqs_count_r[2]_i_2_n_0\,
      I1 => \dqs_count_r[2]_i_3_n_0\,
      I2 => wl_state_r(4),
      I3 => \dqs_count_r[2]_i_4_n_0\,
      I4 => \dqs_count_r[2]_i_5_n_0\,
      I5 => \dqs_count_r[2]_i_6_n_0\,
      O => \dqs_count_r[2]_rep_i_1_n_0\
    );
\dqs_count_r[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => wrlvl_byte_redo,
      O => \dqs_count_r[3]_i_10_n_0\
    );
\dqs_count_r[3]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(0),
      I2 => wl_state_r(2),
      O => \dqs_count_r[3]_i_11_n_0\
    );
\dqs_count_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11C04041"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => wl_state_r(2),
      I4 => wl_state_r(3),
      O => \dqs_count_r[3]_i_2_n_0\
    );
\dqs_count_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF040404FF"
    )
        port map (
      I0 => \dqs_count_r[3]_i_4_n_0\,
      I1 => wl_state_r(0),
      I2 => wl_state_r(2),
      I3 => wl_state_r(4),
      I4 => \dqs_count_r[3]_i_5_n_0\,
      I5 => \dqs_count_r[3]_i_6_n_0\,
      O => \dqs_count_r[3]_i_3_n_0\
    );
\dqs_count_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F3F5F3F0F3F3F3F"
    )
        port map (
      I0 => \^p_0_in\,
      I1 => \dqs_count_r[3]_i_7_n_0\,
      I2 => dqs_count_r(3),
      I3 => wl_state_r(3),
      I4 => wrlvl_byte_redo,
      I5 => wl_state_r(1),
      O => \dqs_count_r[3]_i_4_n_0\
    );
\dqs_count_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002222222222222"
    )
        port map (
      I0 => \dqs_count_r[3]_i_8_n_0\,
      I1 => \dqs_count_r[3]_i_9_n_0\,
      I2 => \dqs_count_r[3]_i_7_n_0\,
      I3 => \fine_inc[0][5]_i_3_n_0\,
      I4 => dqs_count_r(3),
      I5 => \FSM_sequential_wl_state_r[4]_i_16_n_0\,
      O => \dqs_count_r[3]_i_5_n_0\
    );
\dqs_count_r[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFEF0000"
    )
        port map (
      I0 => \fine_inc[0][5]_i_3_n_0\,
      I1 => \dqs_count_r[3]_i_7_n_0\,
      I2 => \dqs_count_r[3]_i_10_n_0\,
      I3 => \FSM_sequential_wl_state_r[4]_i_13_n_0\,
      I4 => dqs_count_r(3),
      I5 => \dqs_count_r[3]_i_11_n_0\,
      O => \dqs_count_r[3]_i_6_n_0\
    );
\dqs_count_r[3]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      O => \dqs_count_r[3]_i_7_n_0\
    );
\dqs_count_r[3]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77F7FFFF"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(3),
      I2 => wr_level_done_r4,
      I3 => \^wr_level_done_r5\,
      I4 => dqs_count_r(3),
      O => \dqs_count_r[3]_i_8_n_0\
    );
\dqs_count_r[3]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => \^wrlvl_byte_redo_r\,
      I2 => wrlvl_byte_redo,
      I3 => \po_stg2_wrcal_cnt_reg[3]\(3),
      I4 => wl_state_r(3),
      O => \dqs_count_r[3]_i_9_n_0\
    );
\dqs_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[0]_i_1_n_0\,
      Q => dqs_count_r(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\dqs_count_r_reg[0]_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[0]_rep_i_1_n_0\,
      Q => \dqs_count_r_reg[0]_rep_n_0\,
      R => rstdiv0_sync_r1_reg_rep
    );
\dqs_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[1]_i_1_n_0\,
      Q => dqs_count_r(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\dqs_count_r_reg[1]_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[1]_rep_i_1_n_0\,
      Q => \dqs_count_r_reg[1]_rep_n_0\,
      R => rstdiv0_sync_r1_reg_rep
    );
\dqs_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[2]_i_1_n_0\,
      Q => dqs_count_r(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\dqs_count_r_reg[2]_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[2]_rep_i_1_n_0\,
      Q => \dqs_count_r_reg[2]_rep_n_0\,
      R => rstdiv0_sync_r1_reg_rep
    );
\dqs_count_r_reg[2]_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[2]_rep__0_i_1_n_0\,
      Q => \dqs_count_r_reg[2]_rep__0_n_0\,
      R => rstdiv0_sync_r1_reg_rep
    );
\dqs_count_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \dqs_count_r[3]_i_2_n_0\,
      D => \dqs_count_r[3]_i_3_n_0\,
      Q => dqs_count_r(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
dqs_po_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_dec_done,
      Q => \^dqs_po_dec_done\,
      R => '0'
    );
dqs_po_en_stg2_f_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABAABBBAA"
    )
        port map (
      I0 => \^dqs_po_en_stg2_f_reg_0\,
      I1 => wl_state_r(2),
      I2 => wl_state_r(0),
      I3 => wl_state_r(1),
      I4 => wl_state_r(3),
      I5 => wl_state_r(4),
      O => dqs_po_en_stg2_f_i_1_n_0
    );
dqs_po_en_stg2_f_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_po_en_stg2_f_i_1_n_0,
      Q => dqs_po_en_stg2_f,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
dqs_po_stg2_f_incdec_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002222222A"
    )
        port map (
      I0 => dqs_po_stg2_f_incdec_i_2_n_0,
      I1 => \fine_inc[0][5]_i_5_n_0\,
      I2 => \wl_tap_count_r[5]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(2),
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => dqs_po_stg2_f_incdec0
    );
dqs_po_stg2_f_incdec_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFEFFB"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(3),
      I2 => wl_state_r(1),
      I3 => wl_state_r(0),
      I4 => wl_state_r(2),
      I5 => \^dqs_po_en_stg2_f_reg_0\,
      O => dqs_po_stg2_f_incdec_i_2_n_0
    );
dqs_po_stg2_f_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => dqs_po_stg2_f_incdec0,
      Q => dqs_po_stg2_f_incdec,
      R => '0'
    );
dqs_wl_po_stg2_c_incdec_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(1),
      I2 => wl_state_r(3),
      I3 => wl_state_r(0),
      I4 => wl_state_r(4),
      O => p_3_in
    );
dqs_wl_po_stg2_c_incdec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => p_3_in,
      Q => po_stg2_cincdec(2),
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\final_coarse_tap_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][0]_22\(0),
      Q => \final_coarse_tap_reg_n_0_[0][0]\,
      R => '0'
    );
\final_coarse_tap_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][0]_22\(1),
      Q => \final_coarse_tap_reg_n_0_[0][1]\,
      R => '0'
    );
\final_coarse_tap_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][0]_22\(2),
      Q => \final_coarse_tap_reg_n_0_[0][2]\,
      R => '0'
    );
\final_coarse_tap_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][1]_23\(0),
      Q => \final_coarse_tap_reg_n_0_[1][0]\,
      R => '0'
    );
\final_coarse_tap_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][1]_23\(1),
      Q => \final_coarse_tap_reg_n_0_[1][1]\,
      R => '0'
    );
\final_coarse_tap_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][1]_23\(2),
      Q => \final_coarse_tap_reg_n_0_[1][2]\,
      R => '0'
    );
\final_coarse_tap_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][2]_24\(0),
      Q => \final_coarse_tap_reg_n_0_[2][0]\,
      R => '0'
    );
\final_coarse_tap_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][2]_24\(1),
      Q => \final_coarse_tap_reg_n_0_[2][1]\,
      R => '0'
    );
\final_coarse_tap_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][2]_24\(2),
      Q => \final_coarse_tap_reg_n_0_[2][2]\,
      R => '0'
    );
\final_coarse_tap_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][3]_25\(0),
      Q => \final_coarse_tap_reg_n_0_[3][0]\,
      R => '0'
    );
\final_coarse_tap_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][3]_25\(1),
      Q => \final_coarse_tap_reg_n_0_[3][1]\,
      R => '0'
    );
\final_coarse_tap_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][3]_25\(2),
      Q => \final_coarse_tap_reg_n_0_[3][2]\,
      R => '0'
    );
\final_coarse_tap_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][4]_26\(0),
      Q => \final_coarse_tap_reg_n_0_[4][0]\,
      R => '0'
    );
\final_coarse_tap_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][4]_26\(1),
      Q => \final_coarse_tap_reg_n_0_[4][1]\,
      R => '0'
    );
\final_coarse_tap_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][4]_26\(2),
      Q => \final_coarse_tap_reg_n_0_[4][2]\,
      R => '0'
    );
\final_coarse_tap_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][5]_27\(0),
      Q => \final_coarse_tap_reg_n_0_[5][0]\,
      R => '0'
    );
\final_coarse_tap_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][5]_27\(1),
      Q => \final_coarse_tap_reg_n_0_[5][1]\,
      R => '0'
    );
\final_coarse_tap_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][5]_27\(2),
      Q => \final_coarse_tap_reg_n_0_[5][2]\,
      R => '0'
    );
\final_coarse_tap_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][6]_28\(0),
      Q => \final_coarse_tap_reg_n_0_[6][0]\,
      R => '0'
    );
\final_coarse_tap_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][6]_28\(1),
      Q => \final_coarse_tap_reg_n_0_[6][1]\,
      R => '0'
    );
\final_coarse_tap_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][6]_28\(2),
      Q => \final_coarse_tap_reg_n_0_[6][2]\,
      R => '0'
    );
\final_coarse_tap_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][7]_29\(0),
      Q => \final_coarse_tap_reg_n_0_[7][0]\,
      R => '0'
    );
\final_coarse_tap_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][7]_29\(1),
      Q => \final_coarse_tap_reg_n_0_[7][1]\,
      R => '0'
    );
\final_coarse_tap_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_corse_cnt_reg[0][7]_29\(2),
      Q => \final_coarse_tap_reg_n_0_[7][2]\,
      R => '0'
    );
\fine_dec_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"001DFF1F00110010"
    )
        port map (
      I0 => \fine_dec_cnt__0\(0),
      I1 => wl_state_r(4),
      I2 => wl_state_r(1),
      I3 => wl_state_r(2),
      I4 => wl_state_r(3),
      I5 => \wl_tap_count_r_reg_n_0_[0]\,
      O => fine_dec_cnt(0)
    );
\fine_dec_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"41FF4141"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_5_n_0\,
      I1 => \fine_dec_cnt__0\(1),
      I2 => \fine_dec_cnt__0\(0),
      I3 => \fine_dec_cnt[5]_i_7_n_0\,
      I4 => \wl_tap_count_r_reg_n_0_[1]\,
      O => fine_dec_cnt(1)
    );
\fine_dec_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4441FFFF44414441"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_5_n_0\,
      I1 => \fine_dec_cnt__0\(2),
      I2 => \fine_dec_cnt__0\(0),
      I3 => \fine_dec_cnt__0\(1),
      I4 => \fine_dec_cnt[5]_i_7_n_0\,
      I5 => \wl_tap_count_r_reg_n_0_[2]\,
      O => fine_dec_cnt(2)
    );
\fine_dec_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14FF1414"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_5_n_0\,
      I1 => \fine_dec_cnt__0\(3),
      I2 => \fine_dec_cnt[3]_i_2_n_0\,
      I3 => \fine_dec_cnt[5]_i_7_n_0\,
      I4 => \wl_tap_count_r_reg_n_0_[3]\,
      O => fine_dec_cnt(3)
    );
\fine_dec_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \fine_dec_cnt__0\(0),
      I1 => \fine_dec_cnt__0\(1),
      I2 => \fine_dec_cnt__0\(2),
      O => \fine_dec_cnt[3]_i_2_n_0\
    );
\fine_dec_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14FF1414"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_5_n_0\,
      I1 => \fine_dec_cnt__0\(4),
      I2 => \fine_dec_cnt[4]_i_2_n_0\,
      I3 => \fine_dec_cnt[5]_i_7_n_0\,
      I4 => \wl_tap_count_r_reg_n_0_[4]\,
      O => fine_dec_cnt(4)
    );
\fine_dec_cnt[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \fine_dec_cnt__0\(2),
      I1 => \fine_dec_cnt__0\(1),
      I2 => \fine_dec_cnt__0\(0),
      I3 => \fine_dec_cnt__0\(3),
      O => \fine_dec_cnt[4]_i_2_n_0\
    );
\fine_dec_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAEABAAAAAAAAAA"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_3_n_0\,
      I1 => wl_state_r(2),
      I2 => wl_state_r(0),
      I3 => wl_state_r(3),
      I4 => wl_state_r(1),
      I5 => \fine_dec_cnt[5]_i_4_n_0\,
      O => \fine_dec_cnt[5]_i_1_n_0\
    );
\fine_dec_cnt[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_11_n_0\,
      I1 => \wl_tap_count_r_reg_n_0_[5]\,
      I2 => \wl_tap_count_r_reg_n_0_[3]\,
      I3 => \wl_tap_count_r_reg_n_0_[4]\,
      I4 => wl_edge_detect_valid_r_reg_n_0,
      I5 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \fine_dec_cnt[5]_i_10_n_0\
    );
\fine_dec_cnt[5]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \corse_cnt__0\(2),
      I1 => \corse_cnt__0\(0),
      I2 => \corse_cnt__0\(1),
      O => \fine_dec_cnt[5]_i_11_n_0\
    );
\fine_dec_cnt[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14FF1414"
    )
        port map (
      I0 => \fine_dec_cnt[5]_i_5_n_0\,
      I1 => \fine_dec_cnt__0\(5),
      I2 => \fine_dec_cnt[5]_i_6_n_0\,
      I3 => \fine_dec_cnt[5]_i_7_n_0\,
      I4 => \wl_tap_count_r_reg_n_0_[5]\,
      O => fine_dec_cnt(5)
    );
\fine_dec_cnt[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4040000"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => wl_state_r(1),
      I3 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I4 => \fine_dec_cnt[5]_i_8_n_0\,
      I5 => \FSM_sequential_wl_state_r[2]_i_10_n_0\,
      O => \fine_dec_cnt[5]_i_3_n_0\
    );
\fine_dec_cnt[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00F0880000F088"
    )
        port map (
      I0 => stable_cnt227_in,
      I1 => \fine_dec_cnt[5]_i_9_n_0\,
      I2 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I3 => wl_state_r(3),
      I4 => wl_state_r(4),
      I5 => \fine_dec_cnt[5]_i_10_n_0\,
      O => \fine_dec_cnt[5]_i_4_n_0\
    );
\fine_dec_cnt[5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF1"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(3),
      I2 => wl_state_r(2),
      I3 => wl_state_r(4),
      O => \fine_dec_cnt[5]_i_5_n_0\
    );
\fine_dec_cnt[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \fine_dec_cnt__0\(3),
      I1 => \fine_dec_cnt__0\(0),
      I2 => \fine_dec_cnt__0\(1),
      I3 => \fine_dec_cnt__0\(2),
      I4 => \fine_dec_cnt__0\(4),
      O => \fine_dec_cnt[5]_i_6_n_0\
    );
\fine_dec_cnt[5]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FD0C"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => wl_state_r(2),
      I3 => wl_state_r(3),
      O => \fine_dec_cnt[5]_i_7_n_0\
    );
\fine_dec_cnt[5]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(2),
      O => \fine_dec_cnt[5]_i_8_n_0\
    );
\fine_dec_cnt[5]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => wl_sm_start,
      I1 => \stable_cnt_reg_n_0_[1]\,
      I2 => \stable_cnt_reg_n_0_[2]\,
      I3 => \stable_cnt_reg_n_0_[3]\,
      O => \fine_dec_cnt[5]_i_9_n_0\
    );
\fine_dec_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(0),
      Q => \fine_dec_cnt__0\(0),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\fine_dec_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(1),
      Q => \fine_dec_cnt__0\(1),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\fine_dec_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(2),
      Q => \fine_dec_cnt__0\(2),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\fine_dec_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(3),
      Q => \fine_dec_cnt__0\(3),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\fine_dec_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(4),
      Q => \fine_dec_cnt__0\(4),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\fine_dec_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_dec_cnt[5]_i_1_n_0\,
      D => fine_dec_cnt(5),
      Q => \fine_dec_cnt__0\(5),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\fine_inc[0][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[0].final_val_reg_n_0_[0][0]\,
      O => fine_inc(0)
    );
\fine_inc[0][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[0].final_val_reg_n_0_[0][1]\,
      O => fine_inc(1)
    );
\fine_inc[0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[0].final_val_reg_n_0_[0][2]\,
      O => fine_inc(2)
    );
\fine_inc[0][2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_13\(2),
      I1 => \fine_inc_reg[6]_12\(2),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[5]_11\(2),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[4]_10\(2),
      O => \fine_inc[0][2]_i_10_n_0\
    );
\fine_inc[0][2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_9\(1),
      I1 => \fine_inc_reg[2]_8\(1),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[1]_7\(1),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[0]_6\(1),
      O => \fine_inc[0][2]_i_5_n_0\
    );
\fine_inc[0][2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_13\(1),
      I1 => \fine_inc_reg[6]_12\(1),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[5]_11\(1),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[4]_10\(1),
      O => \fine_inc[0][2]_i_6_n_0\
    );
\fine_inc[0][2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_9\(0),
      I1 => \fine_inc_reg[2]_8\(0),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[1]_7\(0),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[0]_6\(0),
      O => \fine_inc[0][2]_i_7_n_0\
    );
\fine_inc[0][2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_13\(0),
      I1 => \fine_inc_reg[6]_12\(0),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[5]_11\(0),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[4]_10\(0),
      O => \fine_inc[0][2]_i_8_n_0\
    );
\fine_inc[0][2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_9\(2),
      I1 => \fine_inc_reg[2]_8\(2),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[1]_7\(2),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[0]_6\(2),
      O => \fine_inc[0][2]_i_9_n_0\
    );
\fine_inc[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[0].final_val_reg_n_0_[0][3]\,
      O => fine_inc(3)
    );
\fine_inc[0][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FE0100000000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => \fine_inc_reg[0][5]_i_10_n_0\,
      I4 => wl_state_r(4),
      I5 => wl_state_r(1),
      O => \fine_inc[0][3]_i_2_n_0\
    );
\fine_inc[0][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[0].final_val_reg_n_0_[0][4]\,
      O => fine_inc(4)
    );
\fine_inc[0][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F8F0F0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_5_n_0\,
      I4 => \fine_inc[0][5]_i_6_n_0\,
      O => \fine_inc[0][5]_i_1_n_0\
    );
\fine_inc[0][5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_9\(5),
      I1 => \fine_inc_reg[2]_8\(5),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[1]_7\(5),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[0]_6\(5),
      O => \fine_inc[0][5]_i_11_n_0\
    );
\fine_inc[0][5]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_13\(5),
      I1 => \fine_inc_reg[6]_12\(5),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \fine_inc_reg[5]_11\(5),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \fine_inc_reg[4]_10\(5),
      O => \fine_inc[0][5]_i_12_n_0\
    );
\fine_inc[0][5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_9\(4),
      I1 => \fine_inc_reg[2]_8\(4),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \fine_inc_reg[1]_7\(4),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \fine_inc_reg[0]_6\(4),
      O => \fine_inc[0][5]_i_13_n_0\
    );
\fine_inc[0][5]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_13\(4),
      I1 => \fine_inc_reg[6]_12\(4),
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \fine_inc_reg[5]_11\(4),
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \fine_inc_reg[4]_10\(4),
      O => \fine_inc[0][5]_i_14_n_0\
    );
\fine_inc[0][5]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[3]_9\(3),
      I1 => \fine_inc_reg[2]_8\(3),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[1]_7\(3),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[0]_6\(3),
      O => \fine_inc[0][5]_i_15_n_0\
    );
\fine_inc[0][5]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fine_inc_reg[7]_13\(3),
      I1 => \fine_inc_reg[6]_12\(3),
      I2 => dqs_count_r(1),
      I3 => \fine_inc_reg[5]_11\(3),
      I4 => dqs_count_r(0),
      I5 => \fine_inc_reg[4]_10\(3),
      O => \fine_inc[0][5]_i_16_n_0\
    );
\fine_inc[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[0].final_val_reg_n_0_[0][5]\,
      O => fine_inc(5)
    );
\fine_inc[0][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][5]_i_7_n_0\,
      I3 => \fine_inc_reg[0][5]_i_10_n_0\,
      I4 => \fine_inc_reg[0][5]_i_8_n_0\,
      I5 => \fine_inc_reg[0][2]_i_4_n_0\,
      O => \fine_inc[0][5]_i_3_n_0\
    );
\fine_inc[0][5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(2),
      I2 => wr_level_done_r4,
      I3 => \^wr_level_done_r5\,
      I4 => wl_state_r(3),
      I5 => \FSM_sequential_wl_state_r[2]_i_10_n_0\,
      O => \fine_inc[0][5]_i_4_n_0\
    );
\fine_inc[0][5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(4),
      I2 => wl_state_r(1),
      I3 => wl_state_r(0),
      I4 => wl_state_r(2),
      O => \fine_inc[0][5]_i_5_n_0\
    );
\fine_inc[0][5]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I3 => dqs_count_r(3),
      O => \fine_inc[0][5]_i_6_n_0\
    );
\fine_inc[0][5]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => \fine_inc_reg[0][5]_i_10_n_0\,
      O => \fine_inc[0][5]_i_9_n_0\
    );
\fine_inc[1][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[1].final_val_reg_n_0_[1][0]\,
      O => \fine_inc[1][0]_i_1_n_0\
    );
\fine_inc[1][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[1].final_val_reg_n_0_[1][1]\,
      O => \fine_inc[1][1]_i_1_n_0\
    );
\fine_inc[1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[1].final_val_reg_n_0_[1][2]\,
      O => \fine_inc[1][2]_i_1_n_0\
    );
\fine_inc[1][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[1].final_val_reg_n_0_[1][3]\,
      O => \fine_inc[1][3]_i_1_n_0\
    );
\fine_inc[1][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[1].final_val_reg_n_0_[1][4]\,
      O => \fine_inc[1][4]_i_1_n_0\
    );
\fine_inc[1][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F8F0F0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_5_n_0\,
      I4 => \fine_inc[1][5]_i_3_n_0\,
      O => \fine_inc[1][5]_i_1_n_0\
    );
\fine_inc[1][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[1].final_val_reg_n_0_[1][5]\,
      O => \fine_inc[1][5]_i_2_n_0\
    );
\fine_inc[1][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I1 => dqs_count_r(3),
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      O => \fine_inc[1][5]_i_3_n_0\
    );
\fine_inc[2][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[2].final_val_reg_n_0_[2][0]\,
      O => \fine_inc[2][0]_i_1_n_0\
    );
\fine_inc[2][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[2].final_val_reg_n_0_[2][1]\,
      O => \fine_inc[2][1]_i_1_n_0\
    );
\fine_inc[2][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[2].final_val_reg_n_0_[2][2]\,
      O => \fine_inc[2][2]_i_1_n_0\
    );
\fine_inc[2][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[2].final_val_reg_n_0_[2][3]\,
      O => \fine_inc[2][3]_i_1_n_0\
    );
\fine_inc[2][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[2].final_val_reg_n_0_[2][4]\,
      O => \fine_inc[2][4]_i_1_n_0\
    );
\fine_inc[2][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F8F0F0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_5_n_0\,
      I4 => \fine_inc[2][5]_i_3_n_0\,
      O => \fine_inc[2][5]_i_1_n_0\
    );
\fine_inc[2][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[2].final_val_reg_n_0_[2][5]\,
      O => \fine_inc[2][5]_i_2_n_0\
    );
\fine_inc[2][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I1 => dqs_count_r(3),
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(0),
      O => \fine_inc[2][5]_i_3_n_0\
    );
\fine_inc[3][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[3].final_val_reg_n_0_[3][0]\,
      O => \fine_inc[3][0]_i_1_n_0\
    );
\fine_inc[3][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[3].final_val_reg_n_0_[3][1]\,
      O => \fine_inc[3][1]_i_1_n_0\
    );
\fine_inc[3][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[3].final_val_reg_n_0_[3][2]\,
      O => \fine_inc[3][2]_i_1_n_0\
    );
\fine_inc[3][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[3].final_val_reg_n_0_[3][3]\,
      O => \fine_inc[3][3]_i_1_n_0\
    );
\fine_inc[3][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[3].final_val_reg_n_0_[3][4]\,
      O => \fine_inc[3][4]_i_1_n_0\
    );
\fine_inc[3][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F8F0F0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_5_n_0\,
      I4 => \fine_inc[3][5]_i_3_n_0\,
      O => \fine_inc[3][5]_i_1_n_0\
    );
\fine_inc[3][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[3].final_val_reg_n_0_[3][5]\,
      O => \fine_inc[3][5]_i_2_n_0\
    );
\fine_inc[3][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I1 => dqs_count_r(3),
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(0),
      O => \fine_inc[3][5]_i_3_n_0\
    );
\fine_inc[4][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[4].final_val_reg_n_0_[4][0]\,
      O => \fine_inc[4][0]_i_1_n_0\
    );
\fine_inc[4][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[4].final_val_reg_n_0_[4][1]\,
      O => \fine_inc[4][1]_i_1_n_0\
    );
\fine_inc[4][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[4].final_val_reg_n_0_[4][2]\,
      O => \fine_inc[4][2]_i_1_n_0\
    );
\fine_inc[4][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[4].final_val_reg_n_0_[4][3]\,
      O => \fine_inc[4][3]_i_1_n_0\
    );
\fine_inc[4][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[4].final_val_reg_n_0_[4][4]\,
      O => \fine_inc[4][4]_i_1_n_0\
    );
\fine_inc[4][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F8F0F0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_5_n_0\,
      I4 => \fine_inc[4][5]_i_3_n_0\,
      O => \fine_inc[4][5]_i_1_n_0\
    );
\fine_inc[4][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[4].final_val_reg_n_0_[4][5]\,
      O => \fine_inc[4][5]_i_2_n_0\
    );
\fine_inc[4][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I3 => dqs_count_r(3),
      O => \fine_inc[4][5]_i_3_n_0\
    );
\fine_inc[5][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[5].final_val_reg_n_0_[5][0]\,
      O => \fine_inc[5][0]_i_1_n_0\
    );
\fine_inc[5][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[5].final_val_reg_n_0_[5][1]\,
      O => \fine_inc[5][1]_i_1_n_0\
    );
\fine_inc[5][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[5].final_val_reg_n_0_[5][2]\,
      O => \fine_inc[5][2]_i_1_n_0\
    );
\fine_inc[5][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[5].final_val_reg_n_0_[5][3]\,
      O => \fine_inc[5][3]_i_1_n_0\
    );
\fine_inc[5][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[5].final_val_reg_n_0_[5][4]\,
      O => \fine_inc[5][4]_i_1_n_0\
    );
\fine_inc[5][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F8F0F0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_5_n_0\,
      I4 => \fine_inc[5][5]_i_3_n_0\,
      O => \fine_inc[5][5]_i_1_n_0\
    );
\fine_inc[5][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[5].final_val_reg_n_0_[5][5]\,
      O => \fine_inc[5][5]_i_2_n_0\
    );
\fine_inc[5][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I3 => dqs_count_r(3),
      O => \fine_inc[5][5]_i_3_n_0\
    );
\fine_inc[6][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[6].final_val_reg_n_0_[6][0]\,
      O => \fine_inc[6][0]_i_1_n_0\
    );
\fine_inc[6][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[6].final_val_reg_n_0_[6][1]\,
      O => \fine_inc[6][1]_i_1_n_0\
    );
\fine_inc[6][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[6].final_val_reg_n_0_[6][2]\,
      O => \fine_inc[6][2]_i_1_n_0\
    );
\fine_inc[6][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[6].final_val_reg_n_0_[6][3]\,
      O => \fine_inc[6][3]_i_1_n_0\
    );
\fine_inc[6][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[6].final_val_reg_n_0_[6][4]\,
      O => \fine_inc[6][4]_i_1_n_0\
    );
\fine_inc[6][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F8F0F0"
    )
        port map (
      I0 => \^wr_level_done_r5\,
      I1 => \fine_inc[0][5]_i_3_n_0\,
      I2 => \fine_inc[0][5]_i_4_n_0\,
      I3 => \fine_inc[0][5]_i_5_n_0\,
      I4 => \fine_inc[6][5]_i_3_n_0\,
      O => \fine_inc[6][5]_i_1_n_0\
    );
\fine_inc[6][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[6].final_val_reg_n_0_[6][5]\,
      O => \fine_inc[6][5]_i_2_n_0\
    );
\fine_inc[6][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I3 => dqs_count_r(3),
      O => \fine_inc[6][5]_i_3_n_0\
    );
\fine_inc[7][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1504"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => \fine_inc_reg[0][2]_i_3_n_0\,
      I3 => \gen_final_tap[7].final_val_reg_n_0_[7][0]\,
      O => \fine_inc[7][0]_i_1_n_0\
    );
\fine_inc[7][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"090F0900"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_3_n_0\,
      I1 => \fine_inc_reg[0][2]_i_2_n_0\,
      I2 => wl_state_r(4),
      I3 => wl_state_r(1),
      I4 => \gen_final_tap[7].final_val_reg_n_0_[7][1]\,
      O => \fine_inc[7][1]_i_1_n_0\
    );
\fine_inc[7][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E100FF00E10000"
    )
        port map (
      I0 => \fine_inc_reg[0][2]_i_2_n_0\,
      I1 => \fine_inc_reg[0][2]_i_3_n_0\,
      I2 => \fine_inc_reg[0][2]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => \gen_final_tap[7].final_val_reg_n_0_[7][2]\,
      O => \fine_inc[7][2]_i_1_n_0\
    );
\fine_inc[7][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \fine_inc[0][3]_i_2_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => \gen_final_tap[7].final_val_reg_n_0_[7][3]\,
      O => \fine_inc[7][3]_i_1_n_0\
    );
\fine_inc[7][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"006F0060"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_8_n_0\,
      I1 => \fine_inc[0][5]_i_9_n_0\,
      I2 => wl_state_r(1),
      I3 => wl_state_r(4),
      I4 => \gen_final_tap[7].final_val_reg_n_0_[7][4]\,
      O => \fine_inc[7][4]_i_1_n_0\
    );
\fine_inc[7][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BAAAAAAA"
    )
        port map (
      I0 => \fine_inc[0][5]_i_4_n_0\,
      I1 => \fine_inc[0][5]_i_5_n_0\,
      I2 => \fine_inc[7][5]_i_3_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => \fine_inc[0][5]_i_3_n_0\,
      O => \fine_inc[7][5]_i_1_n_0\
    );
\fine_inc[7][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00009AFF00009A00"
    )
        port map (
      I0 => \fine_inc_reg[0][5]_i_7_n_0\,
      I1 => \fine_inc_reg[0][5]_i_8_n_0\,
      I2 => \fine_inc[0][5]_i_9_n_0\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \gen_final_tap[7].final_val_reg_n_0_[7][5]\,
      O => \fine_inc[7][5]_i_2_n_0\
    );
\fine_inc[7][5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      O => \fine_inc[7][5]_i_3_n_0\
    );
\fine_inc_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(0),
      Q => \fine_inc_reg[0]_6\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(1),
      Q => \fine_inc_reg[0]_6\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(2),
      Q => \fine_inc_reg[0]_6\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[0][2]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][2]_i_5_n_0\,
      I1 => \fine_inc[0][2]_i_6_n_0\,
      O => \fine_inc_reg[0][2]_i_2_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][2]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][2]_i_7_n_0\,
      I1 => \fine_inc[0][2]_i_8_n_0\,
      O => \fine_inc_reg[0][2]_i_3_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][2]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][2]_i_9_n_0\,
      I1 => \fine_inc[0][2]_i_10_n_0\,
      O => \fine_inc_reg[0][2]_i_4_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(3),
      Q => \fine_inc_reg[0]_6\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(4),
      Q => \fine_inc_reg[0]_6\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[0][5]_i_1_n_0\,
      D => fine_inc(5),
      Q => \fine_inc_reg[0]_6\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\fine_inc_reg[0][5]_i_10\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][5]_i_15_n_0\,
      I1 => \fine_inc[0][5]_i_16_n_0\,
      O => \fine_inc_reg[0][5]_i_10_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][5]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][5]_i_11_n_0\,
      I1 => \fine_inc[0][5]_i_12_n_0\,
      O => \fine_inc_reg[0][5]_i_7_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[0][5]_i_8\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fine_inc[0][5]_i_13_n_0\,
      I1 => \fine_inc[0][5]_i_14_n_0\,
      O => \fine_inc_reg[0][5]_i_8_n_0\,
      S => dqs_count_r(2)
    );
\fine_inc_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][0]_i_1_n_0\,
      Q => \fine_inc_reg[1]_7\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][1]_i_1_n_0\,
      Q => \fine_inc_reg[1]_7\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][2]_i_1_n_0\,
      Q => \fine_inc_reg[1]_7\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][3]_i_1_n_0\,
      Q => \fine_inc_reg[1]_7\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][4]_i_1_n_0\,
      Q => \fine_inc_reg[1]_7\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[1][5]_i_1_n_0\,
      D => \fine_inc[1][5]_i_2_n_0\,
      Q => \fine_inc_reg[1]_7\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\fine_inc_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][0]_i_1_n_0\,
      Q => \fine_inc_reg[2]_8\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][1]_i_1_n_0\,
      Q => \fine_inc_reg[2]_8\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][2]_i_1_n_0\,
      Q => \fine_inc_reg[2]_8\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][3]_i_1_n_0\,
      Q => \fine_inc_reg[2]_8\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][4]_i_1_n_0\,
      Q => \fine_inc_reg[2]_8\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[2][5]_i_1_n_0\,
      D => \fine_inc[2][5]_i_2_n_0\,
      Q => \fine_inc_reg[2]_8\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\fine_inc_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][0]_i_1_n_0\,
      Q => \fine_inc_reg[3]_9\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][1]_i_1_n_0\,
      Q => \fine_inc_reg[3]_9\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][2]_i_1_n_0\,
      Q => \fine_inc_reg[3]_9\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][3]_i_1_n_0\,
      Q => \fine_inc_reg[3]_9\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][4]_i_1_n_0\,
      Q => \fine_inc_reg[3]_9\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[3][5]_i_1_n_0\,
      D => \fine_inc[3][5]_i_2_n_0\,
      Q => \fine_inc_reg[3]_9\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\fine_inc_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][0]_i_1_n_0\,
      Q => \fine_inc_reg[4]_10\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][1]_i_1_n_0\,
      Q => \fine_inc_reg[4]_10\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][2]_i_1_n_0\,
      Q => \fine_inc_reg[4]_10\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][3]_i_1_n_0\,
      Q => \fine_inc_reg[4]_10\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][4]_i_1_n_0\,
      Q => \fine_inc_reg[4]_10\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[4][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[4][5]_i_1_n_0\,
      D => \fine_inc[4][5]_i_2_n_0\,
      Q => \fine_inc_reg[4]_10\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\fine_inc_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][0]_i_1_n_0\,
      Q => \fine_inc_reg[5]_11\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][1]_i_1_n_0\,
      Q => \fine_inc_reg[5]_11\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][2]_i_1_n_0\,
      Q => \fine_inc_reg[5]_11\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][3]_i_1_n_0\,
      Q => \fine_inc_reg[5]_11\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][4]_i_1_n_0\,
      Q => \fine_inc_reg[5]_11\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[5][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[5][5]_i_1_n_0\,
      D => \fine_inc[5][5]_i_2_n_0\,
      Q => \fine_inc_reg[5]_11\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\fine_inc_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][0]_i_1_n_0\,
      Q => \fine_inc_reg[6]_12\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][1]_i_1_n_0\,
      Q => \fine_inc_reg[6]_12\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][2]_i_1_n_0\,
      Q => \fine_inc_reg[6]_12\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][3]_i_1_n_0\,
      Q => \fine_inc_reg[6]_12\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][4]_i_1_n_0\,
      Q => \fine_inc_reg[6]_12\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[6][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[6][5]_i_1_n_0\,
      D => \fine_inc[6][5]_i_2_n_0\,
      Q => \fine_inc_reg[6]_12\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\fine_inc_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][0]_i_1_n_0\,
      Q => \fine_inc_reg[7]_13\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][1]_i_1_n_0\,
      Q => \fine_inc_reg[7]_13\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][2]_i_1_n_0\,
      Q => \fine_inc_reg[7]_13\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][3]_i_1_n_0\,
      Q => \fine_inc_reg[7]_13\(3),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][4]_i_1_n_0\,
      Q => \fine_inc_reg[7]_13\(4),
      R => \rstdiv0_sync_r1_reg_rep__10\(0)
    );
\fine_inc_reg[7][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \fine_inc[7][5]_i_1_n_0\,
      D => \fine_inc[7][5]_i_2_n_0\,
      Q => \fine_inc_reg[7]_13\(5),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
flag_ck_negedge_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001010001"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23\,
      I1 => flag_ck_negedge_i_2_n_0,
      I2 => flag_ck_negedge_i_3_n_0,
      I3 => flag_ck_negedge_i_4_n_0,
      I4 => flag_ck_negedge_i_5_n_0,
      I5 => \stable_cnt[3]_i_6_n_0\,
      O => flag_ck_negedge_i_1_n_0
    );
flag_ck_negedge_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(0),
      I2 => wl_state_r(1),
      I3 => wl_state_r(2),
      I4 => wl_state_r(3),
      O => flag_ck_negedge_i_2_n_0
    );
flag_ck_negedge_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBBBFBB"
    )
        port map (
      I0 => wr_level_done_r_reg_n_0,
      I1 => flag_ck_negedge_reg_n_0,
      I2 => \stable_cnt_reg_n_0_[0]\,
      I3 => flag_ck_negedge_i_6_n_0,
      I4 => stable_cnt227_in,
      I5 => flag_ck_negedge09_out,
      O => flag_ck_negedge_i_3_n_0
    );
flag_ck_negedge_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(4),
      O => flag_ck_negedge_i_4_n_0
    );
flag_ck_negedge_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(0),
      I2 => wl_state_r(1),
      O => flag_ck_negedge_i_5_n_0
    );
flag_ck_negedge_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[3]\,
      I1 => \stable_cnt_reg_n_0_[2]\,
      I2 => \stable_cnt_reg_n_0_[1]\,
      O => flag_ck_negedge_i_6_n_0
    );
flag_ck_negedge_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBB3BBBBBBBB"
    )
        port map (
      I0 => stable_cnt227_in,
      I1 => \corse_inc[0][2]_i_6_n_0\,
      I2 => \stable_cnt[3]_i_5_n_0\,
      I3 => \stable_cnt_reg_n_0_[1]\,
      I4 => \stable_cnt_reg_n_0_[0]\,
      I5 => flag_ck_negedge_i_8_n_0,
      O => flag_ck_negedge09_out
    );
flag_ck_negedge_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000F0F070F"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(2),
      I2 => \stable_cnt_reg_n_0_[3]\,
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => \stable_cnt_reg_n_0_[2]\,
      O => flag_ck_negedge_i_8_n_0
    );
flag_ck_negedge_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => flag_ck_negedge_i_1_n_0,
      Q => flag_ck_negedge_reg_n_0,
      R => '0'
    );
flag_init_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA8AAAAA"
    )
        port map (
      I0 => flag_init,
      I1 => \wl_state_r1_reg_n_0_[0]\,
      I2 => p_1_in28_in,
      I3 => \wl_state_r1_reg_n_0_[4]\,
      I4 => \wl_state_r1_reg_n_0_[2]\,
      I5 => \wl_state_r1_reg_n_0_[3]\,
      O => flag_init_i_1_n_0
    );
flag_init_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(1),
      I2 => wl_state_r(4),
      I3 => wl_state_r(0),
      I4 => wl_state_r(3),
      O => p_1_in28_in
    );
flag_init_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => flag_init_i_1_n_0,
      Q => flag_init,
      S => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[0]\,
      I1 => \^wrlvl_done_r_reg\,
      I2 => \dqs_count_r_reg[0]_rep_n_0\,
      O => D(0)
    );
\gen_byte_sel_div2.byte_sel_cnt[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[1]\,
      I1 => \^wrlvl_done_r_reg\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      O => D(1)
    );
\gen_byte_sel_div2.byte_sel_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[2]\,
      I1 => \^wrlvl_done_r_reg\,
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      O => D(2)
    );
\gen_byte_sel_div2.byte_sel_cnt[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \po_stg2_wrcal_cnt_reg[3]_0\,
      I1 => \^wrlvl_done_r_reg\,
      I2 => dqs_count_r(3),
      O => D(3)
    );
\gen_final_tap[0].final_val[0][5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wr_level_done_r2,
      I1 => wr_level_done_r3,
      O => p_21_out
    );
\gen_final_tap[0].final_val_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[0]_14\(0),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][0]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[0].final_val_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[0]_14\(1),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][1]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[0].final_val_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[0]_14\(2),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][2]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[0].final_val_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[0]_14\(3),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][3]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[0].final_val_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[0]_14\(4),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][4]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[0].final_val_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[0]_14\(5),
      Q => \gen_final_tap[0].final_val_reg_n_0_[0][5]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[1].final_val_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[1]_15\(0),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][0]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[1].final_val_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[1]_15\(1),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][1]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[1].final_val_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[1]_15\(2),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][2]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[1].final_val_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[1]_15\(3),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][3]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[1].final_val_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[1]_15\(4),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][4]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[1].final_val_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[1]_15\(5),
      Q => \gen_final_tap[1].final_val_reg_n_0_[1][5]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[2].final_val_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[2]_16\(0),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][0]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[2].final_val_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[2]_16\(1),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][1]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[2].final_val_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[2]_16\(2),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][2]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[2].final_val_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[2]_16\(3),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][3]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[2].final_val_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[2]_16\(4),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][4]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[2].final_val_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[2]_16\(5),
      Q => \gen_final_tap[2].final_val_reg_n_0_[2][5]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[3].final_val_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[3]_17\(0),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][0]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[3].final_val_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[3]_17\(1),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][1]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[3].final_val_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[3]_17\(2),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][2]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[3].final_val_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[3]_17\(3),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][3]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[3].final_val_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[3]_17\(4),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][4]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[3].final_val_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[3]_17\(5),
      Q => \gen_final_tap[3].final_val_reg_n_0_[3][5]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[4].final_val_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[4]_18\(0),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][0]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[4].final_val_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[4]_18\(1),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][1]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[4].final_val_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[4]_18\(2),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][2]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[4].final_val_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[4]_18\(3),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][3]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[4].final_val_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[4]_18\(4),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][4]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[4].final_val_reg[4][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[4]_18\(5),
      Q => \gen_final_tap[4].final_val_reg_n_0_[4][5]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[5].final_val_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[5]_19\(0),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][0]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[5].final_val_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[5]_19\(1),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][1]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[5].final_val_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[5]_19\(2),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][2]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[5].final_val_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[5]_19\(3),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][3]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[5].final_val_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[5]_19\(4),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][4]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[5].final_val_reg[5][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[5]_19\(5),
      Q => \gen_final_tap[5].final_val_reg_n_0_[5][5]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[6].final_val_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[6]_20\(0),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][0]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[6].final_val_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[6]_20\(1),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][1]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[6].final_val_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[6]_20\(2),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][2]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[6].final_val_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[6]_20\(3),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][3]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[6].final_val_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[6]_20\(4),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][4]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[6].final_val_reg[6][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[6]_20\(5),
      Q => \gen_final_tap[6].final_val_reg_n_0_[6][5]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\gen_final_tap[7].final_val_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[7]_21\(0),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][0]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[7].final_val_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[7]_21\(1),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][1]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[7].final_val_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[7]_21\(2),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][2]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[7].final_val_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[7]_21\(3),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][3]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[7].final_val_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[7]_21\(4),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][4]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_final_tap[7].final_val_reg[7][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => p_21_out,
      D => \smallest_reg[7]_21\(5),
      Q => \gen_final_tap[7].final_val_reg_n_0_[7][5]\,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\gen_rd[0].rd_data_rise_wl_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\,
      Q => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      R => '0'
    );
\gen_rd[1].rd_data_rise_wl_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\,
      Q => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      R => '0'
    );
\gen_rd[2].rd_data_rise_wl_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0\,
      Q => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      R => '0'
    );
\gen_rd[3].rd_data_rise_wl_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0\,
      Q => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      R => '0'
    );
\gen_rd[4].rd_data_rise_wl_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0\,
      Q => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      R => '0'
    );
\gen_rd[5].rd_data_rise_wl_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0\,
      Q => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      R => '0'
    );
\gen_rd[6].rd_data_rise_wl_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0\,
      Q => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      R => '0'
    );
\gen_rd[7].rd_data_rise_wl_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0\,
      Q => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      R => '0'
    );
\incdec_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \incdec_wait_cnt_reg__0\(0),
      O => \p_0_in__2\(0)
    );
\incdec_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \incdec_wait_cnt_reg__0\(0),
      I1 => \incdec_wait_cnt_reg__0\(1),
      O => \p_0_in__2\(1)
    );
\incdec_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \incdec_wait_cnt_reg__0\(2),
      I1 => \incdec_wait_cnt_reg__0\(1),
      I2 => \incdec_wait_cnt_reg__0\(0),
      O => \p_0_in__2\(2)
    );
\incdec_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFEFFBFF"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(3),
      I3 => wl_state_r(2),
      I4 => wl_state_r(0),
      I5 => wl_state_r(1),
      O => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \incdec_wait_cnt_reg__0\(3),
      I1 => \incdec_wait_cnt_reg__0\(0),
      I2 => \incdec_wait_cnt_reg__0\(1),
      I3 => \incdec_wait_cnt_reg__0\(2),
      O => \p_0_in__2\(3)
    );
\incdec_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(0),
      Q => \incdec_wait_cnt_reg__0\(0),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(1),
      Q => \incdec_wait_cnt_reg__0\(1),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(2),
      Q => \incdec_wait_cnt_reg__0\(2),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
\incdec_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__2\(3),
      Q => \incdec_wait_cnt_reg__0\(3),
      R => \incdec_wait_cnt[3]_i_1_n_0\
    );
inhibit_edge_detect_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEFAA20"
    )
        port map (
      I0 => inhibit_edge_detect_r,
      I1 => inhibit_edge_detect_r_i_3_n_0,
      I2 => inhibit_edge_detect_r_i_4_n_0,
      I3 => inhibit_edge_detect_r_i_5_n_0,
      I4 => inhibit_edge_detect_r_reg_n_0,
      O => inhibit_edge_detect_r_i_1_n_0
    );
inhibit_edge_detect_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FCF00C00AFF0AFF"
    )
        port map (
      I0 => \FSM_sequential_wl_state_r[3]_i_11_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => wl_state_r(4),
      I3 => wl_state_r(3),
      I4 => stable_cnt227_in,
      I5 => wl_state_r(2),
      O => inhibit_edge_detect_r
    );
inhibit_edge_detect_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDD5DDDDDDDD"
    )
        port map (
      I0 => inhibit_edge_detect_r_i_6_n_0,
      I1 => wl_state_r(4),
      I2 => wrlvl_redo_corse_inc(2),
      I3 => wrlvl_redo_corse_inc(0),
      I4 => wrlvl_redo_corse_inc(1),
      I5 => wrlvl_byte_redo,
      O => inhibit_edge_detect_r_i_3_n_0
    );
inhibit_edge_detect_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080818080808"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(4),
      I2 => wl_state_r(1),
      I3 => flag_ck_negedge_i_6_n_0,
      I4 => wl_sm_start,
      I5 => stable_cnt227_in,
      O => inhibit_edge_detect_r_i_4_n_0
    );
inhibit_edge_detect_r_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00011001"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(4),
      I2 => wl_state_r(1),
      I3 => wl_state_r(3),
      I4 => wl_state_r(0),
      O => inhibit_edge_detect_r_i_5_n_0
    );
inhibit_edge_detect_r_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(3),
      O => inhibit_edge_detect_r_i_6_n_0
    );
inhibit_edge_detect_r_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => inhibit_edge_detect_r_i_1_n_0,
      Q => inhibit_edge_detect_r_reg_n_0,
      S => \rstdiv0_sync_r1_reg_rep__5\
    );
\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      I4 => \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\,
      O => \p_0_in__0\
    );
\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      O => \p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\
    );
\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      I4 => \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\,
      O => \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\
    );
\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      O => \p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\
    );
\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      I4 => \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0\,
      O => \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0\
    );
\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      O => \p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0\
    );
\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      I4 => \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0\,
      O => \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0\
    );
\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      O => \p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0\
    );
\p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      I4 => \p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0\,
      O => \p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0\
    );
\p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      O => \p_0_out_inferred__4/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0\
    );
\p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      I4 => \p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0\,
      O => \p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0\
    );
\p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_4\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      O => \p_0_out_inferred__5/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0\
    );
\p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      I4 => \p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0\,
      O => \p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0\
    );
\p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_5\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      O => \p_0_out_inferred__6/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0\
    );
\p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      I4 => \p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0\,
      O => \p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0\
    );
\p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_6\,
      I1 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\,
      I2 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      I3 => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      O => \p_0_out_inferred__7/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0\
    );
phaser_out_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => calib_in_common,
      I1 => Q(0),
      I2 => po_stg2_cincdec(2),
      I3 => Q(1),
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]\
    );
\phaser_out_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => calib_in_common,
      I1 => Q(1),
      I2 => Q(0),
      I3 => po_stg2_cincdec(2),
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => D_po_coarse_enable105_out
    );
\phaser_out_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => po_stg2_cincdec(2),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]_0\
    );
\phaser_out_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => calib_in_common,
      I1 => Q(0),
      I2 => po_stg2_cincdec(2),
      I3 => Q(1),
      I4 => \calib_zero_inputs_reg[2]\(1),
      O => \po_counter_read_val_reg[8]_1\
    );
\phaser_out_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => po_stg2_cincdec(2),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_2\
    );
\phaser_out_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => Q(1),
      I1 => po_stg2_cincdec(2),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_3\
    );
\phaser_out_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => po_stg2_cincdec(2),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_4\
    );
\phaser_out_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => po_stg2_cincdec(2),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(0),
      O => \po_counter_read_val_reg[8]_5\
    );
\phaser_out_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => po_stg2_cincdec(2),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_6\
    );
\phaser_out_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => Q(1),
      I1 => po_stg2_cincdec(2),
      I2 => Q(0),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_7\
    );
\phaser_out_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => po_stg2_cincdec(2),
      I1 => Q(0),
      I2 => Q(1),
      I3 => calib_in_common,
      I4 => \calib_zero_inputs_reg[2]\(2),
      O => \po_counter_read_val_reg[8]_8\
    );
phy_ctl_ready_r4_reg_srl4: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => phy_mc_go,
      Q => phy_ctl_ready_r4_reg_srl4_n_0
    );
phy_ctl_ready_r5_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_ready_r4_reg_srl4_n_0,
      Q => phy_ctl_ready_r5,
      R => '0'
    );
phy_ctl_ready_r6_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_ready_r5,
      Q => phy_ctl_ready_r6_reg_n_0,
      R => '0'
    );
po_cnt_dec_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \po_rdval_cnt[8]_i_3_n_0\,
      I1 => po_cnt_dec_i_2_n_0,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \rstdiv0_sync_r1_reg_rep__23\,
      I4 => \wait_cnt_reg__0\(1),
      I5 => \wait_cnt_reg__0\(0),
      O => po_cnt_dec_i_1_n_0
    );
po_cnt_dec_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_cnt_reg__0\(2),
      I1 => \wait_cnt_reg__0\(3),
      O => po_cnt_dec_i_2_n_0
    );
po_cnt_dec_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_cnt_dec_i_1_n_0,
      Q => \^dqs_po_en_stg2_f_reg_0\,
      R => '0'
    );
po_dec_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => po_dec_done_i_2_n_0,
      I1 => po_dec_done_i_3_n_0,
      I2 => po_dec_done,
      O => po_dec_done_i_1_n_0
    );
po_dec_done_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEFFFEF"
    )
        port map (
      I0 => po_rdval_cnt(2),
      I1 => po_rdval_cnt(1),
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => po_rdval_cnt(0),
      I4 => \^dqs_po_en_stg2_f_reg_0\,
      O => po_dec_done_i_2_n_0
    );
po_dec_done_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => po_rdval_cnt(7),
      I1 => po_rdval_cnt(3),
      I2 => po_rdval_cnt(4),
      I3 => po_rdval_cnt(5),
      I4 => po_rdval_cnt(6),
      I5 => po_rdval_cnt(8),
      O => po_dec_done_i_3_n_0
    );
po_dec_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => po_dec_done_i_1_n_0,
      Q => po_dec_done,
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\po_rdval_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \po_counter_read_val_reg[0]\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \po_rdval_cnt[8]_i_3_n_0\,
      I4 => po_rdval_cnt(0),
      O => \po_rdval_cnt[0]_i_1_n_0\
    );
\po_rdval_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB0808080808FB08"
    )
        port map (
      I0 => \po_counter_read_val_reg[1]\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \po_rdval_cnt[8]_i_3_n_0\,
      I4 => po_rdval_cnt(0),
      I5 => po_rdval_cnt(1),
      O => \po_rdval_cnt[1]_i_1_n_0\
    );
\po_rdval_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B888888888B8"
    )
        port map (
      I0 => \po_counter_read_val_reg[2]\,
      I1 => \po_rdval_cnt[6]_i_3_n_0\,
      I2 => \po_rdval_cnt[8]_i_3_n_0\,
      I3 => po_rdval_cnt(1),
      I4 => po_rdval_cnt(0),
      I5 => po_rdval_cnt(2),
      O => \po_rdval_cnt[2]_i_1_n_0\
    );
\po_rdval_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FBFB08"
    )
        port map (
      I0 => \po_counter_read_val_reg[3]\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => po_rdval_cnt(3),
      I4 => \po_rdval_cnt[4]_i_3_n_0\,
      O => \po_rdval_cnt[3]_i_1_n_0\
    );
\po_rdval_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB0808FBFB08FB08"
    )
        port map (
      I0 => \po_counter_read_val_reg[4]\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => po_rdval_cnt(4),
      I4 => po_rdval_cnt(3),
      I5 => \po_rdval_cnt[4]_i_3_n_0\,
      O => \po_rdval_cnt[4]_i_1_n_0\
    );
\po_rdval_cnt[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => po_rdval_cnt(1),
      I1 => po_rdval_cnt(0),
      I2 => po_rdval_cnt(2),
      I3 => po_dec_done_i_3_n_0,
      O => \po_rdval_cnt[4]_i_3_n_0\
    );
\po_rdval_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB0808080808FB08"
    )
        port map (
      I0 => \po_counter_read_val_reg[5]\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \po_rdval_cnt[8]_i_3_n_0\,
      I4 => \po_rdval_cnt[6]_i_4_n_0\,
      I5 => po_rdval_cnt(5),
      O => \po_rdval_cnt[5]_i_1_n_0\
    );
\po_rdval_cnt[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B888888888B8"
    )
        port map (
      I0 => \po_counter_read_val_reg[6]\,
      I1 => \po_rdval_cnt[6]_i_3_n_0\,
      I2 => \po_rdval_cnt[8]_i_3_n_0\,
      I3 => po_rdval_cnt(5),
      I4 => \po_rdval_cnt[6]_i_4_n_0\,
      I5 => po_rdval_cnt(6),
      O => \po_rdval_cnt[6]_i_1_n_0\
    );
\po_rdval_cnt[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => phy_ctl_ready_r5,
      I1 => phy_ctl_ready_r6_reg_n_0,
      O => \po_rdval_cnt[6]_i_3_n_0\
    );
\po_rdval_cnt[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => po_rdval_cnt(1),
      I1 => po_rdval_cnt(0),
      I2 => po_rdval_cnt(2),
      I3 => po_rdval_cnt(3),
      I4 => po_rdval_cnt(4),
      O => \po_rdval_cnt[6]_i_4_n_0\
    );
\po_rdval_cnt[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFB08080808FB08"
    )
        port map (
      I0 => \po_counter_read_val_reg[7]\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => po_rdval_cnt(8),
      I4 => \po_rdval_cnt[7]_i_3_n_0\,
      I5 => po_rdval_cnt(7),
      O => \po_rdval_cnt[7]_i_1_n_0\
    );
\po_rdval_cnt[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \po_rdval_cnt[8]_i_7_n_0\,
      I1 => po_rdval_cnt(6),
      I2 => po_rdval_cnt(5),
      I3 => po_rdval_cnt(4),
      I4 => po_rdval_cnt(3),
      O => \po_rdval_cnt[7]_i_3_n_0\
    );
\po_rdval_cnt[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AEFF"
    )
        port map (
      I0 => \^dqs_po_en_stg2_f_reg_0\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => \po_rdval_cnt[8]_i_3_n_0\,
      O => \po_rdval_cnt[8]_i_1_n_0\
    );
\po_rdval_cnt[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808FB08"
    )
        port map (
      I0 => \po_counter_read_val_reg[8]_9\,
      I1 => phy_ctl_ready_r5,
      I2 => phy_ctl_ready_r6_reg_n_0,
      I3 => po_rdval_cnt(8),
      I4 => \po_rdval_cnt[8]_i_5_n_0\,
      O => \po_rdval_cnt[8]_i_2_n_0\
    );
\po_rdval_cnt[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => po_rdval_cnt(8),
      I1 => po_rdval_cnt(1),
      I2 => po_rdval_cnt(0),
      I3 => po_rdval_cnt(2),
      I4 => \po_rdval_cnt[8]_i_6_n_0\,
      I5 => po_rdval_cnt(7),
      O => \po_rdval_cnt[8]_i_3_n_0\
    );
\po_rdval_cnt[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => po_rdval_cnt(7),
      I1 => po_rdval_cnt(3),
      I2 => po_rdval_cnt(4),
      I3 => po_rdval_cnt(5),
      I4 => po_rdval_cnt(6),
      I5 => \po_rdval_cnt[8]_i_7_n_0\,
      O => \po_rdval_cnt[8]_i_5_n_0\
    );
\po_rdval_cnt[8]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => po_rdval_cnt(3),
      I1 => po_rdval_cnt(4),
      I2 => po_rdval_cnt(5),
      I3 => po_rdval_cnt(6),
      O => \po_rdval_cnt[8]_i_6_n_0\
    );
\po_rdval_cnt[8]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => po_rdval_cnt(2),
      I1 => po_rdval_cnt(0),
      I2 => po_rdval_cnt(1),
      O => \po_rdval_cnt[8]_i_7_n_0\
    );
\po_rdval_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[0]_i_1_n_0\,
      Q => po_rdval_cnt(0),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[1]_i_1_n_0\,
      Q => po_rdval_cnt(1),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[2]_i_1_n_0\,
      Q => po_rdval_cnt(2),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[3]_i_1_n_0\,
      Q => po_rdval_cnt(3),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[4]_i_1_n_0\,
      Q => po_rdval_cnt(4),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[5]_i_1_n_0\,
      Q => po_rdval_cnt(5),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[6]_i_1_n_0\,
      Q => po_rdval_cnt(6),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[7]_i_1_n_0\,
      Q => po_rdval_cnt(7),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\po_rdval_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \po_rdval_cnt[8]_i_1_n_0\,
      D => \po_rdval_cnt[8]_i_2_n_0\,
      Q => po_rdval_cnt(8),
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\rank_cnt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"38"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[1]\,
      I1 => rank_cnt_r,
      I2 => \rank_cnt_r_reg_n_0_[0]\,
      O => \rank_cnt_r[0]_i_1_n_0\
    );
\rank_cnt_r[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[0]\,
      I1 => rank_cnt_r,
      I2 => \rank_cnt_r_reg_n_0_[1]\,
      O => \rank_cnt_r[1]_i_2_n_0\
    );
\rank_cnt_r[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000000"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => \^p_0_in\,
      I2 => wl_state_r(2),
      I3 => wl_state_r(3),
      I4 => wl_state_r(1),
      I5 => wl_state_r(0),
      O => rank_cnt_r
    );
\rank_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_cnt_r[0]_i_1_n_0\,
      Q => \rank_cnt_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\rank_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_cnt_r[1]_i_2_n_0\,
      Q => \rank_cnt_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\rd_data_edge_detect_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[0]\,
      I2 => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[0]_i_1_n_0\
    );
\rd_data_edge_detect_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[1]\,
      I2 => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[1]_i_1_n_0\
    );
\rd_data_edge_detect_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[2]\,
      I2 => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[2]_i_1_n_0\
    );
\rd_data_edge_detect_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[3]\,
      I2 => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[3]_i_1_n_0\
    );
\rd_data_edge_detect_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[4]\,
      I2 => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[4]_i_1_n_0\
    );
\rd_data_edge_detect_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[5]\,
      I2 => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[5]_i_1_n_0\
    );
\rd_data_edge_detect_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[6]\,
      I2 => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[6]_i_1_n_0\
    );
\rd_data_edge_detect_r[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I1 => inhibit_edge_detect_r_reg_n_0,
      I2 => flag_init,
      I3 => \rstdiv0_sync_r1_reg_rep__23\,
      I4 => flag_ck_negedge_reg_n_0,
      O => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_previous_r_reg_n_0_[3]\,
      I1 => \rd_data_previous_r_reg_n_0_[2]\,
      I2 => dqs_count_r(1),
      I3 => \rd_data_previous_r_reg_n_0_[1]\,
      I4 => dqs_count_r(0),
      I5 => \rd_data_previous_r_reg_n_0_[0]\,
      O => \rd_data_edge_detect_r[7]_i_10_n_0\
    );
\rd_data_edge_detect_r[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_previous_r_reg_n_0_[7]\,
      I1 => \rd_data_previous_r_reg_n_0_[6]\,
      I2 => dqs_count_r(1),
      I3 => \rd_data_previous_r_reg_n_0_[5]\,
      I4 => dqs_count_r(0),
      I5 => \rd_data_previous_r_reg_n_0_[4]\,
      O => \rd_data_edge_detect_r[7]_i_11_n_0\
    );
\rd_data_edge_detect_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555FF55DD5557D5"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      I1 => wl_state_r(1),
      I2 => wl_state_r(0),
      I3 => wl_state_r(2),
      I4 => wl_state_r(3),
      I5 => wl_state_r(4),
      O => \rd_data_edge_detect_r[7]_i_2_n_0\
    );
\rd_data_edge_detect_r[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rd_data_edge_detect_r[7]_i_6_n_0\,
      I1 => \rd_data_previous_r_reg_n_0_[7]\,
      I2 => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      I3 => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      O => \rd_data_edge_detect_r[7]_i_3_n_0\
    );
\rd_data_edge_detect_r[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[0]\,
      I1 => \wl_tap_count_r_reg_n_0_[1]\,
      I2 => \wl_tap_count_r_reg_n_0_[2]\,
      I3 => \wl_tap_count_r_reg_n_0_[3]\,
      I4 => \wl_tap_count_r_reg_n_0_[5]\,
      I5 => \wl_tap_count_r_reg_n_0_[4]\,
      O => \rd_data_edge_detect_r[7]_i_4_n_0\
    );
\rd_data_edge_detect_r[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80FF"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[1]\,
      I1 => \stable_cnt_reg_n_0_[2]\,
      I2 => \stable_cnt_reg_n_0_[3]\,
      I3 => stable_cnt227_in,
      O => \rd_data_edge_detect_r[7]_i_6_n_0\
    );
\rd_data_edge_detect_r[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg_n_0_[3]\,
      I1 => \rd_data_edge_detect_r_reg_n_0_[2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \rd_data_edge_detect_r_reg_n_0_[1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \rd_data_edge_detect_r_reg_n_0_[0]\,
      O => \rd_data_edge_detect_r[7]_i_7_n_0\
    );
\rd_data_edge_detect_r[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rd_data_edge_detect_r_reg_n_0_[7]\,
      I1 => \rd_data_edge_detect_r_reg_n_0_[6]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \rd_data_edge_detect_r_reg_n_0_[5]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \rd_data_edge_detect_r_reg_n_0_[4]\,
      O => \rd_data_edge_detect_r[7]_i_8_n_0\
    );
\rd_data_edge_detect_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[0]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[0]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[1]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[1]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[2]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[2]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[3]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[3]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[4]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[4]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[5]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[5]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[6]_i_1_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[6]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \rd_data_edge_detect_r[7]_i_2_n_0\,
      D => \rd_data_edge_detect_r[7]_i_3_n_0\,
      Q => \rd_data_edge_detect_r_reg_n_0_[7]\,
      R => rd_data_edge_detect_r0
    );
\rd_data_edge_detect_r_reg[7]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rd_data_edge_detect_r[7]_i_7_n_0\,
      I1 => \rd_data_edge_detect_r[7]_i_8_n_0\,
      O => \rd_data_edge_detect_r_reg[7]_i_5_n_0\,
      S => dqs_count_r(2)
    );
\rd_data_edge_detect_r_reg[7]_i_9\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rd_data_edge_detect_r[7]_i_10_n_0\,
      I1 => \rd_data_edge_detect_r[7]_i_11_n_0\,
      O => stable_cnt227_in,
      S => dqs_count_r(2)
    );
\rd_data_previous_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BEABBEAAAEABAFAA"
    )
        port map (
      I0 => \rd_data_previous_r[7]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(3),
      I3 => wl_state_r(2),
      I4 => wl_state_r(0),
      I5 => wl_state_r(1),
      O => rd_data_previous_r0
    );
\rd_data_previous_r[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAB"
    )
        port map (
      I0 => \rd_data_previous_r[7]_i_3_n_0\,
      I1 => \rd_data_previous_r[7]_i_4_n_0\,
      I2 => \wl_tap_count_r[5]_i_4_n_0\,
      I3 => wl_state_r(4),
      I4 => wl_state_r(2),
      I5 => \wl_state_r1_reg_n_0_[0]\,
      O => \rd_data_previous_r[7]_i_2_n_0\
    );
\rd_data_previous_r[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => wl_state_r(0),
      I3 => wl_state_r(3),
      I4 => wl_state_r(2),
      I5 => wl_edge_detect_valid_r_reg_n_0,
      O => \rd_data_previous_r[7]_i_3_n_0\
    );
\rd_data_previous_r[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \wl_state_r1_reg_n_0_[1]\,
      I1 => \wl_state_r1_reg_n_0_[3]\,
      I2 => \wl_state_r1_reg_n_0_[2]\,
      I3 => \wl_state_r1_reg_n_0_[4]\,
      O => \rd_data_previous_r[7]_i_4_n_0\
    );
\rd_data_previous_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      Q => \rd_data_previous_r_reg_n_0_[0]\,
      R => '0'
    );
\rd_data_previous_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      Q => \rd_data_previous_r_reg_n_0_[1]\,
      R => '0'
    );
\rd_data_previous_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      Q => \rd_data_previous_r_reg_n_0_[2]\,
      R => '0'
    );
\rd_data_previous_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      Q => \rd_data_previous_r_reg_n_0_[3]\,
      R => '0'
    );
\rd_data_previous_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      Q => \rd_data_previous_r_reg_n_0_[4]\,
      R => '0'
    );
\rd_data_previous_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      Q => \rd_data_previous_r_reg_n_0_[5]\,
      R => '0'
    );
\rd_data_previous_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      Q => \rd_data_previous_r_reg_n_0_[6]\,
      R => '0'
    );
\rd_data_previous_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_data_previous_r0,
      D => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      Q => \rd_data_previous_r_reg_n_0_[7]\,
      R => '0'
    );
\single_rank.done_dqs_dec_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000BA"
    )
        port map (
      I0 => \^done_dqs_tap_inc\,
      I1 => wr_level_done_r4,
      I2 => wr_level_done_r3,
      I3 => done_dqs_dec239_out,
      I4 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \single_rank.done_dqs_dec_i_1_n_0\
    );
\single_rank.done_dqs_dec_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \single_rank.done_dqs_dec_i_1_n_0\,
      Q => \^done_dqs_tap_inc\,
      R => '0'
    );
\smallest[0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][0]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][0]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][0]\,
      O => \smallest[0][0]_i_2_n_0\
    );
\smallest[0][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][0]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][0]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][0]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][0]\,
      O => \smallest[0][0]_i_3_n_0\
    );
\smallest[0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][1]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][1]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][1]\,
      O => \smallest[0][1]_i_2_n_0\
    );
\smallest[0][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][1]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][1]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][1]\,
      O => \smallest[0][1]_i_3_n_0\
    );
\smallest[0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][2]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][2]\,
      O => \smallest[0][2]_i_3_n_0\
    );
\smallest[0][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][2]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][2]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][2]\,
      O => \smallest[0][2]_i_4_n_0\
    );
\smallest[0][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][3]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][3]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][3]\,
      O => \smallest[0][3]_i_2_n_0\
    );
\smallest[0][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][3]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][3]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][3]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][3]\,
      O => \smallest[0][3]_i_3_n_0\
    );
\smallest[0][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][4]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][4]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][4]\,
      O => \smallest[0][4]_i_2_n_0\
    );
\smallest[0][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][4]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][4]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][4]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][4]\,
      O => \smallest[0][4]_i_3_n_0\
    );
\smallest[0][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => \dqs_count_r_reg[2]_rep_n_0\,
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[0][5]_i_1_n_0\
    );
\smallest[0][5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFB7FF"
    )
        port map (
      I0 => wl_state_r(1),
      I1 => wl_state_r(4),
      I2 => wl_state_r(0),
      I3 => wl_state_r(3),
      I4 => wl_state_r(2),
      O => \smallest[0][5]_i_3_n_0\
    );
\smallest[0][5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][3][5]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][2][5]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][0][5]\,
      O => \smallest[0][5]_i_4_n_0\
    );
\smallest[0][5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \wl_dqs_tap_count_r_reg_n_0_[0][7][5]\,
      I1 => \wl_dqs_tap_count_r_reg_n_0_[0][6][5]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \wl_dqs_tap_count_r_reg_n_0_[0][5][5]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \wl_dqs_tap_count_r_reg_n_0_[0][4][5]\,
      O => \smallest[0][5]_i_5_n_0\
    );
\smallest[1][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => dqs_count_r(3),
      I3 => \dqs_count_r_reg[2]_rep_n_0\,
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[1][5]_i_1_n_0\
    );
\smallest[2][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(3),
      I3 => \dqs_count_r_reg[2]_rep_n_0\,
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[2][5]_i_1_n_0\
    );
\smallest[3][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => dqs_count_r(0),
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(3),
      I3 => \dqs_count_r_reg[2]_rep_n_0\,
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[3][5]_i_1_n_0\
    );
\smallest[4][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => \dqs_count_r_reg[2]_rep_n_0\,
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[4][5]_i_1_n_0\
    );
\smallest[5][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000400"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => \dqs_count_r_reg[2]_rep_n_0\,
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(0),
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[5][5]_i_1_n_0\
    );
\smallest[6][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000400"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => \dqs_count_r_reg[2]_rep_n_0\,
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[6][5]_i_1_n_0\
    );
\smallest[7][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => dqs_count_r(1),
      I1 => dqs_count_r(0),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(3),
      I4 => \smallest[0][5]_i_3_n_0\,
      O => \smallest[7][5]_i_1_n_0\
    );
\smallest_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[0]_14\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[0][0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][0]_i_2_n_0\,
      I1 => \smallest[0][0]_i_3_n_0\,
      O => largest(0),
      S => dqs_count_r(2)
    );
\smallest_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[0]_14\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[0][1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][1]_i_2_n_0\,
      I1 => \smallest[0][1]_i_3_n_0\,
      O => largest(1),
      S => dqs_count_r(2)
    );
\smallest_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[0]_14\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[0][2]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][2]_i_3_n_0\,
      I1 => \smallest[0][2]_i_4_n_0\,
      O => largest(2),
      S => dqs_count_r(2)
    );
\smallest_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[0]_14\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[0][3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][3]_i_2_n_0\,
      I1 => \smallest[0][3]_i_3_n_0\,
      O => largest(3),
      S => dqs_count_r(2)
    );
\smallest_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[0]_14\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[0][4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][4]_i_2_n_0\,
      I1 => \smallest[0][4]_i_3_n_0\,
      O => largest(4),
      S => dqs_count_r(2)
    );
\smallest_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[0][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[0]_14\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[0][5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \smallest[0][5]_i_4_n_0\,
      I1 => \smallest[0][5]_i_5_n_0\,
      O => largest(5),
      S => dqs_count_r(2)
    );
\smallest_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[1][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[1]_15\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[1][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[1]_15\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[1][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[1]_15\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[1][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[1]_15\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[1][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[1]_15\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[1][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[1]_15\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[2][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[2]_16\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[2][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[2]_16\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[2][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[2]_16\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[2][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[2]_16\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[2][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[2]_16\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[2][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[2]_16\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[3][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[3]_17\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[3][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[3]_17\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[3][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[3]_17\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[3][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[3]_17\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[3][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[3]_17\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[3][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[3]_17\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[4][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[4]_18\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[4][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[4]_18\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[4][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[4]_18\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[4][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[4]_18\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[4][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[4]_18\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[4][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[4][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[4]_18\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[5][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[5]_19\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[5][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[5]_19\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[5][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[5]_19\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[5][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[5]_19\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[5][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[5]_19\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[5][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[5][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[5]_19\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[6][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[6]_20\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[6][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[6]_20\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[6][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[6]_20\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[6][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[6]_20\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[6][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[6]_20\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[6][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[6][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[6]_20\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[7][5]_i_1_n_0\,
      D => largest(0),
      Q => \smallest_reg[7]_21\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[7][5]_i_1_n_0\,
      D => largest(1),
      Q => \smallest_reg[7]_21\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[7][5]_i_1_n_0\,
      D => largest(2),
      Q => \smallest_reg[7]_21\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\smallest_reg[7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[7][5]_i_1_n_0\,
      D => largest(3),
      Q => \smallest_reg[7]_21\(3),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[7][5]_i_1_n_0\,
      D => largest(4),
      Q => \smallest_reg[7]_21\(4),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\smallest_reg[7][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \smallest[7][5]_i_1_n_0\,
      D => largest(5),
      Q => \smallest_reg[7]_21\(5),
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\stable_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[0]\,
      O => \p_0_in__1\(0)
    );
\stable_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[0]\,
      I1 => \stable_cnt_reg_n_0_[1]\,
      O => \p_0_in__1\(1)
    );
\stable_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[2]\,
      I1 => \stable_cnt_reg_n_0_[1]\,
      I2 => \stable_cnt_reg_n_0_[0]\,
      O => \p_0_in__1\(2)
    );
\stable_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => \stable_cnt[3]_i_4_n_0\,
      I1 => \smallest[0][5]_i_3_n_0\,
      I2 => \stable_cnt[3]_i_5_n_0\,
      I3 => \rstdiv0_sync_r1_reg_rep__23\,
      I4 => \stable_cnt[3]_i_6_n_0\,
      O => stable_cnt0
    );
\stable_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007F0000"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[1]\,
      I1 => \stable_cnt_reg_n_0_[2]\,
      I2 => \stable_cnt_reg_n_0_[3]\,
      I3 => \rd_data_edge_detect_r[7]_i_4_n_0\,
      I4 => \rd_data_previous_r[7]_i_2_n_0\,
      O => stable_cnt
    );
\stable_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \stable_cnt_reg_n_0_[3]\,
      I1 => \stable_cnt_reg_n_0_[1]\,
      I2 => \stable_cnt_reg_n_0_[2]\,
      I3 => \stable_cnt_reg_n_0_[0]\,
      O => \p_0_in__1\(3)
    );
\stable_cnt[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => stable_cnt227_in,
      I1 => \stable_cnt[3]_i_7_n_0\,
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      I3 => \stable_cnt[3]_i_8_n_0\,
      O => \stable_cnt[3]_i_4_n_0\
    );
\stable_cnt[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(3),
      I2 => wl_state_r(1),
      I3 => wl_state_r(0),
      I4 => wl_state_r(2),
      O => \stable_cnt[3]_i_5_n_0\
    );
\stable_cnt[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \wl_state_r1_reg_n_0_[0]\,
      I1 => \wl_state_r1_reg_n_0_[4]\,
      I2 => \wl_state_r1_reg_n_0_[2]\,
      I3 => \wl_state_r1_reg_n_0_[3]\,
      I4 => \wl_state_r1_reg_n_0_[1]\,
      O => \stable_cnt[3]_i_6_n_0\
    );
\stable_cnt[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3]\,
      I1 => \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\,
      O => \stable_cnt[3]_i_7_n_0\
    );
\stable_cnt[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7]\,
      I1 => \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4]\,
      O => \stable_cnt[3]_i_8_n_0\
    );
\stable_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_cnt,
      D => \p_0_in__1\(0),
      Q => \stable_cnt_reg_n_0_[0]\,
      R => stable_cnt0
    );
\stable_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_cnt,
      D => \p_0_in__1\(1),
      Q => \stable_cnt_reg_n_0_[1]\,
      R => stable_cnt0
    );
\stable_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_cnt,
      D => \p_0_in__1\(2),
      Q => \stable_cnt_reg_n_0_[2]\,
      R => stable_cnt0
    );
\stable_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => stable_cnt,
      D => \p_0_in__1\(3),
      Q => \stable_cnt_reg_n_0_[3]\,
      R => stable_cnt0
    );
\wait_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wait_cnt_reg__0\(0),
      O => \wait_cnt0__0\(0)
    );
\wait_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \wait_cnt_reg__0\(0),
      I1 => \wait_cnt_reg__0\(1),
      O => \wait_cnt[1]_i_1_n_0\
    );
\wait_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \wait_cnt_reg__0\(2),
      I1 => \wait_cnt_reg__0\(1),
      I2 => \wait_cnt_reg__0\(0),
      O => \wait_cnt0__0\(2)
    );
\wait_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => phy_ctl_ready_r6_reg_n_0,
      I1 => \wait_cnt_reg__0\(2),
      I2 => \wait_cnt_reg__0\(3),
      I3 => \wait_cnt_reg__0\(0),
      I4 => \wait_cnt_reg__0\(1),
      O => wait_cnt0
    );
\wait_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \wait_cnt_reg__0\(3),
      I1 => \wait_cnt_reg__0\(2),
      I2 => \wait_cnt_reg__0\(0),
      I3 => \wait_cnt_reg__0\(1),
      O => \wait_cnt0__0\(3)
    );
\wait_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt0,
      D => \wait_cnt0__0\(0),
      Q => \wait_cnt_reg__0\(0),
      R => SS(0)
    );
\wait_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt0,
      D => \wait_cnt[1]_i_1_n_0\,
      Q => \wait_cnt_reg__0\(1),
      R => SS(0)
    );
\wait_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wait_cnt0,
      D => \wait_cnt0__0\(2),
      Q => \wait_cnt_reg__0\(2),
      R => SS(0)
    );
\wait_cnt_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => wait_cnt0,
      D => \wait_cnt0__0\(3),
      Q => \wait_cnt_reg__0\(3),
      S => SS(0)
    );
\wl_corse_cnt[0][0][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][0]_i_2_n_0\,
      I1 => \wl_corse_cnt[0][0][0]_i_3_n_0\,
      I2 => \dqs_count_r_reg[2]_rep__0_n_0\,
      O => \corse_cnt__0\(0)
    );
\wl_corse_cnt[0][0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[3][0]\,
      I1 => \corse_cnt_reg_n_0_[2][0]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_cnt_reg_n_0_[1][0]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_cnt_reg_n_0_[0][0]\,
      O => \wl_corse_cnt[0][0][0]_i_2_n_0\
    );
\wl_corse_cnt[0][0][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[7][0]\,
      I1 => \corse_cnt_reg_n_0_[6][0]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_cnt_reg_n_0_[5][0]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_cnt_reg_n_0_[4][0]\,
      O => \wl_corse_cnt[0][0][0]_i_3_n_0\
    );
\wl_corse_cnt[0][0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[3][1]\,
      I1 => \corse_cnt_reg_n_0_[2][1]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_cnt_reg_n_0_[1][1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_cnt_reg_n_0_[0][1]\,
      O => \wl_corse_cnt[0][0][1]_i_2_n_0\
    );
\wl_corse_cnt[0][0][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[7][1]\,
      I1 => \corse_cnt_reg_n_0_[6][1]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_cnt_reg_n_0_[5][1]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_cnt_reg_n_0_[4][1]\,
      O => \wl_corse_cnt[0][0][1]_i_3_n_0\
    );
\wl_corse_cnt[0][0][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => dqs_count_r(3),
      I1 => \dqs_count_r_reg[2]_rep_n_0\,
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(1),
      I4 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      O => wl_corse_cnt
    );
\wl_corse_cnt[0][0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000008008000"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_6_n_0\,
      I1 => wl_state_r(3),
      I2 => wl_state_r(0),
      I3 => wl_state_r(4),
      I4 => wl_state_r(1),
      I5 => wl_state_r(2),
      O => \wl_corse_cnt[0][0][2]_i_3_n_0\
    );
\wl_corse_cnt[0][0][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[3][2]\,
      I1 => \corse_cnt_reg_n_0_[2][2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_cnt_reg_n_0_[1][2]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_cnt_reg_n_0_[0][2]\,
      O => \wl_corse_cnt[0][0][2]_i_4_n_0\
    );
\wl_corse_cnt[0][0][2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \corse_cnt_reg_n_0_[7][2]\,
      I1 => \corse_cnt_reg_n_0_[6][2]\,
      I2 => \dqs_count_r_reg[1]_rep_n_0\,
      I3 => \corse_cnt_reg_n_0_[5][2]\,
      I4 => \dqs_count_r_reg[0]_rep_n_0\,
      I5 => \corse_cnt_reg_n_0_[4][2]\,
      O => \wl_corse_cnt[0][0][2]_i_5_n_0\
    );
\wl_corse_cnt[0][0][2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[1]\,
      I1 => \rank_cnt_r_reg_n_0_[0]\,
      O => \wl_corse_cnt[0][0][2]_i_6_n_0\
    );
\wl_corse_cnt[0][1][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(0),
      I3 => dqs_count_r(3),
      I4 => \dqs_count_r_reg[2]_rep_n_0\,
      O => \wl_corse_cnt[0][1][2]_i_1_n_0\
    );
\wl_corse_cnt[0][2][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      I1 => dqs_count_r(0),
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(3),
      I4 => \dqs_count_r_reg[2]_rep_n_0\,
      O => \wl_corse_cnt[0][2][2]_i_1_n_0\
    );
\wl_corse_cnt[0][3][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      I1 => dqs_count_r(0),
      I2 => dqs_count_r(1),
      I3 => dqs_count_r(3),
      I4 => \dqs_count_r_reg[2]_rep_n_0\,
      O => \wl_corse_cnt[0][3][2]_i_1_n_0\
    );
\wl_corse_cnt[0][4][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      I1 => dqs_count_r(3),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(0),
      I4 => dqs_count_r(1),
      O => \wl_corse_cnt[0][4][2]_i_1_n_0\
    );
\wl_corse_cnt[0][5][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      I1 => dqs_count_r(3),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(1),
      I4 => dqs_count_r(0),
      O => \wl_corse_cnt[0][5][2]_i_1_n_0\
    );
\wl_corse_cnt[0][6][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      I1 => dqs_count_r(3),
      I2 => \dqs_count_r_reg[2]_rep_n_0\,
      I3 => dqs_count_r(0),
      I4 => dqs_count_r(1),
      O => \wl_corse_cnt[0][6][2]_i_1_n_0\
    );
\wl_corse_cnt[0][7][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \wl_corse_cnt[0][0][2]_i_3_n_0\,
      I1 => dqs_count_r(1),
      I2 => dqs_count_r(0),
      I3 => \dqs_count_r_reg[2]_rep_n_0\,
      I4 => dqs_count_r(3),
      O => \wl_corse_cnt[0][7][2]_i_1_n_0\
    );
\wl_corse_cnt_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][0]_22\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][0]_22\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][0][1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_corse_cnt[0][0][1]_i_2_n_0\,
      I1 => \wl_corse_cnt[0][0][1]_i_3_n_0\,
      O => \corse_cnt__0\(1),
      S => dqs_count_r(2)
    );
\wl_corse_cnt_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][0]_22\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][0][2]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_corse_cnt[0][0][2]_i_4_n_0\,
      I1 => \wl_corse_cnt[0][0][2]_i_5_n_0\,
      O => \corse_cnt__0\(2),
      S => dqs_count_r(2)
    );
\wl_corse_cnt_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][1]_23\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][1]_23\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][1]_23\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][2]_24\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][2]_24\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][2]_24\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][3]_25\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][3]_25\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][3]_25\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][4]_26\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][4]_26\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][4]_26\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][5]_27\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][5]_27\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][5]_27\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][6]_28\(0),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][6]_28\(1),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][6]_28\(2),
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_corse_cnt_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \corse_cnt__0\(0),
      Q => \wl_corse_cnt_reg[0][7]_29\(0),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \corse_cnt__0\(1),
      Q => \wl_corse_cnt_reg[0][7]_29\(1),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_corse_cnt_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \corse_cnt__0\(2),
      Q => \wl_corse_cnt_reg[0][7]_29\(2),
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][0][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][0]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][0][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][1]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][0][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][0][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][3]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][0][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][4]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][0][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wl_corse_cnt,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][0][5]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][1][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][1][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][1][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][1][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][1][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][1][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][1][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][2][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][0]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][2][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][1]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][2][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][2][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][3]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][2][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][4]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][2][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][2][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][2][5]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][3][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][0]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][3][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][3][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][2]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][3][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][3]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][3][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][4]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][3][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][3][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][3][5]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_dqs_tap_count_r_reg[0][4][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][0]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][4][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][1]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][4][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][4][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][3]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][4][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][4]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][4][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][4][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][4][5]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][5][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][0]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][5][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][1]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][5][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][2]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][5][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][3]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][5][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][4]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][5][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][5][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][5][5]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][6][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][0]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][6][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][1]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][6][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][2]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][6][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][3]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][6][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][4]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][6][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][6][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][6][5]\,
      R => \rstdiv0_sync_r1_reg_rep__10\(1)
    );
\wl_dqs_tap_count_r_reg[0][7][0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[0]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][0]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][7][1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[1]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][1]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][7][2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[2]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][2]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][7][3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[3]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][3]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][7][4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[4]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][4]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
\wl_dqs_tap_count_r_reg[0][7][5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_corse_cnt[0][7][2]_i_1_n_0\,
      D => \wl_tap_count_r_reg_n_0_[5]\,
      Q => \wl_dqs_tap_count_r_reg_n_0_[0][7][5]\,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
wl_edge_detect_valid_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA22AAAA32A2"
    )
        port map (
      I0 => wl_edge_detect_valid_r_reg_n_0,
      I1 => wl_state_r(0),
      I2 => wl_state_r(3),
      I3 => wl_state_r(4),
      I4 => wl_state_r(2),
      I5 => wl_state_r(1),
      O => wl_edge_detect_valid_r_i_1_n_0
    );
wl_edge_detect_valid_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wl_edge_detect_valid_r_i_1_n_0,
      Q => wl_edge_detect_valid_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__8\(0)
    );
\wl_state_r1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4B8E4F2C"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(0),
      I2 => wl_state_r(1),
      I3 => wl_state_r(3),
      I4 => wl_state_r(2),
      O => \wl_state_r1[0]_i_1_n_0\
    );
\wl_state_r1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEDC9CA4"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(1),
      I2 => wl_state_r(2),
      I3 => wl_state_r(0),
      I4 => wl_state_r(3),
      O => \wl_state_r1[1]_i_1_n_0\
    );
\wl_state_r1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"53160252"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wl_state_r(2),
      I2 => wl_state_r(3),
      I3 => wl_state_r(0),
      I4 => wl_state_r(1),
      O => \wl_state_r1[2]_i_1_n_0\
    );
\wl_state_r1[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCDEE288"
    )
        port map (
      I0 => wl_state_r(0),
      I1 => wl_state_r(3),
      I2 => wl_state_r(2),
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      O => \wl_state_r1[3]_i_1_n_0\
    );
\wl_state_r1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0E0F30A2"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(1),
      I2 => wl_state_r(3),
      I3 => wl_state_r(0),
      I4 => wl_state_r(4),
      O => \wl_state_r1[4]_i_1_n_0\
    );
\wl_state_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_state_r1[0]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\wl_state_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_state_r1[1]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\wl_state_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_state_r1[2]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\wl_state_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_state_r1[3]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\wl_state_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wl_state_r1[4]_i_1_n_0\,
      Q => \wl_state_r1_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__5\
    );
\wl_tap_count_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F011F100F0FFFF"
    )
        port map (
      I0 => \wl_tap_count_r[5]_i_8_n_0\,
      I1 => \^wr_level_done_r5\,
      I2 => smallest(0),
      I3 => \wl_tap_count_r[5]_i_6_n_0\,
      I4 => \wl_tap_count_r_reg_n_0_[0]\,
      I5 => \wl_tap_count_r[5]_i_4_n_0\,
      O => wl_tap_count_r(0)
    );
\wl_tap_count_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_17\(0),
      I1 => \smallest_reg[2]_16\(0),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[1]_15\(0),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[0]_14\(0),
      O => \wl_tap_count_r[0]_i_3_n_0\
    );
\wl_tap_count_r[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_21\(0),
      I1 => \smallest_reg[6]_20\(0),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[5]_19\(0),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[4]_18\(0),
      O => \wl_tap_count_r[0]_i_4_n_0\
    );
\wl_tap_count_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D0C0C5DFF0C0C"
    )
        port map (
      I0 => \wl_tap_count_r[5]_i_4_n_0\,
      I1 => smallest(1),
      I2 => \wl_tap_count_r[5]_i_6_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => \wl_tap_count_r[1]_i_3_n_0\,
      I5 => \wl_tap_count_r[5]_i_8_n_0\,
      O => wl_tap_count_r(1)
    );
\wl_tap_count_r[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[1]\,
      I1 => \wl_tap_count_r_reg_n_0_[0]\,
      O => \wl_tap_count_r[1]_i_3_n_0\
    );
\wl_tap_count_r[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_17\(1),
      I1 => \smallest_reg[2]_16\(1),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[1]_15\(1),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[0]_14\(1),
      O => \wl_tap_count_r[1]_i_4_n_0\
    );
\wl_tap_count_r[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_21\(1),
      I1 => \smallest_reg[6]_20\(1),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[5]_19\(1),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[4]_18\(1),
      O => \wl_tap_count_r[1]_i_5_n_0\
    );
\wl_tap_count_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D0C0C5DFF0C0C"
    )
        port map (
      I0 => \wl_tap_count_r[5]_i_4_n_0\,
      I1 => smallest(2),
      I2 => \wl_tap_count_r[5]_i_6_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => \wl_tap_count_r[2]_i_3_n_0\,
      I5 => \wl_tap_count_r[5]_i_8_n_0\,
      O => wl_tap_count_r(2)
    );
\wl_tap_count_r[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[2]\,
      I1 => \wl_tap_count_r_reg_n_0_[0]\,
      I2 => \wl_tap_count_r_reg_n_0_[1]\,
      O => \wl_tap_count_r[2]_i_3_n_0\
    );
\wl_tap_count_r[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_17\(2),
      I1 => \smallest_reg[2]_16\(2),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[1]_15\(2),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[0]_14\(2),
      O => \wl_tap_count_r[2]_i_4_n_0\
    );
\wl_tap_count_r[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_21\(2),
      I1 => \smallest_reg[6]_20\(2),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[5]_19\(2),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[4]_18\(2),
      O => \wl_tap_count_r[2]_i_5_n_0\
    );
\wl_tap_count_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D0C0C5DFF0C0C"
    )
        port map (
      I0 => \wl_tap_count_r[5]_i_4_n_0\,
      I1 => smallest(3),
      I2 => \wl_tap_count_r[5]_i_6_n_0\,
      I3 => \^wr_level_done_r5\,
      I4 => \wl_tap_count_r[3]_i_3_n_0\,
      I5 => \wl_tap_count_r[5]_i_8_n_0\,
      O => wl_tap_count_r(3)
    );
\wl_tap_count_r[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[3]\,
      I1 => \wl_tap_count_r_reg_n_0_[1]\,
      I2 => \wl_tap_count_r_reg_n_0_[0]\,
      I3 => \wl_tap_count_r_reg_n_0_[2]\,
      O => \wl_tap_count_r[3]_i_3_n_0\
    );
\wl_tap_count_r[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_17\(3),
      I1 => \smallest_reg[2]_16\(3),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[1]_15\(3),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[0]_14\(3),
      O => \wl_tap_count_r[3]_i_4_n_0\
    );
\wl_tap_count_r[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_21\(3),
      I1 => \smallest_reg[6]_20\(3),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[5]_19\(3),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[4]_18\(3),
      O => \wl_tap_count_r[3]_i_5_n_0\
    );
\wl_tap_count_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"11F100F0FFFF00F0"
    )
        port map (
      I0 => \wl_tap_count_r[5]_i_8_n_0\,
      I1 => \^wr_level_done_r5\,
      I2 => smallest(4),
      I3 => \wl_tap_count_r[5]_i_6_n_0\,
      I4 => \wl_tap_count_r[4]_i_3_n_0\,
      I5 => \wl_tap_count_r[5]_i_4_n_0\,
      O => wl_tap_count_r(4)
    );
\wl_tap_count_r[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[4]\,
      I1 => \wl_tap_count_r_reg_n_0_[2]\,
      I2 => \wl_tap_count_r_reg_n_0_[0]\,
      I3 => \wl_tap_count_r_reg_n_0_[1]\,
      I4 => \wl_tap_count_r_reg_n_0_[3]\,
      O => \wl_tap_count_r[4]_i_3_n_0\
    );
\wl_tap_count_r[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_17\(4),
      I1 => \smallest_reg[2]_16\(4),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[1]_15\(4),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[0]_14\(4),
      O => \wl_tap_count_r[4]_i_4_n_0\
    );
\wl_tap_count_r[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_21\(4),
      I1 => \smallest_reg[6]_20\(4),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[5]_19\(4),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[4]_18\(4),
      O => \wl_tap_count_r[4]_i_5_n_0\
    );
\wl_tap_count_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000C000CF32"
    )
        port map (
      I0 => done_dqs_dec239_out,
      I1 => wl_state_r(0),
      I2 => wl_state_r(3),
      I3 => wl_state_r(1),
      I4 => wl_state_r(4),
      I5 => wl_state_r(2),
      O => \wl_tap_count_r[5]_i_1_n_0\
    );
\wl_tap_count_r[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[7]_21\(5),
      I1 => \smallest_reg[6]_20\(5),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[5]_19\(5),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[4]_18\(5),
      O => \wl_tap_count_r[5]_i_10_n_0\
    );
\wl_tap_count_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C5D0C5D0C5D0CFF"
    )
        port map (
      I0 => \wl_tap_count_r[5]_i_4_n_0\,
      I1 => smallest(5),
      I2 => \wl_tap_count_r[5]_i_6_n_0\,
      I3 => \wl_tap_count_r[5]_i_7_n_0\,
      I4 => \^wr_level_done_r5\,
      I5 => \wl_tap_count_r[5]_i_8_n_0\,
      O => wl_tap_count_r(5)
    );
\wl_tap_count_r[5]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(1),
      I2 => wl_state_r(0),
      O => \wl_tap_count_r[5]_i_4_n_0\
    );
\wl_tap_count_r[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(1),
      O => \wl_tap_count_r[5]_i_6_n_0\
    );
\wl_tap_count_r[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \wl_tap_count_r_reg_n_0_[5]\,
      I1 => \wl_tap_count_r_reg_n_0_[3]\,
      I2 => \wl_tap_count_r_reg_n_0_[1]\,
      I3 => \wl_tap_count_r_reg_n_0_[0]\,
      I4 => \wl_tap_count_r_reg_n_0_[2]\,
      I5 => \wl_tap_count_r_reg_n_0_[4]\,
      O => \wl_tap_count_r[5]_i_7_n_0\
    );
\wl_tap_count_r[5]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => wl_state_r(3),
      I1 => wl_state_r(4),
      I2 => wl_state_r(1),
      O => \wl_tap_count_r[5]_i_8_n_0\
    );
\wl_tap_count_r[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \smallest_reg[3]_17\(5),
      I1 => \smallest_reg[2]_16\(5),
      I2 => \po_stg2_wrcal_cnt_reg[3]\(1),
      I3 => \smallest_reg[1]_15\(5),
      I4 => \po_stg2_wrcal_cnt_reg[3]\(0),
      I5 => \smallest_reg[0]_14\(5),
      O => \wl_tap_count_r[5]_i_9_n_0\
    );
\wl_tap_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(0),
      Q => \wl_tap_count_r_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\wl_tap_count_r_reg[0]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[0]_i_3_n_0\,
      I1 => \wl_tap_count_r[0]_i_4_n_0\,
      O => smallest(0),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\wl_tap_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(1),
      Q => \wl_tap_count_r_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\wl_tap_count_r_reg[1]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[1]_i_4_n_0\,
      I1 => \wl_tap_count_r[1]_i_5_n_0\,
      O => smallest(1),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\wl_tap_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(2),
      Q => \wl_tap_count_r_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\wl_tap_count_r_reg[2]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[2]_i_4_n_0\,
      I1 => \wl_tap_count_r[2]_i_5_n_0\,
      O => smallest(2),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\wl_tap_count_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(3),
      Q => \wl_tap_count_r_reg_n_0_[3]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\wl_tap_count_r_reg[3]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[3]_i_4_n_0\,
      I1 => \wl_tap_count_r[3]_i_5_n_0\,
      O => smallest(3),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\wl_tap_count_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(4),
      Q => \wl_tap_count_r_reg_n_0_[4]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\wl_tap_count_r_reg[4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[4]_i_4_n_0\,
      I1 => \wl_tap_count_r[4]_i_5_n_0\,
      O => smallest(4),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
\wl_tap_count_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \wl_tap_count_r[5]_i_1_n_0\,
      D => wl_tap_count_r(5),
      Q => \wl_tap_count_r_reg_n_0_[5]\,
      R => \rstdiv0_sync_r1_reg_rep__8\(1)
    );
\wl_tap_count_r_reg[5]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \wl_tap_count_r[5]_i_9_n_0\,
      I1 => \wl_tap_count_r[5]_i_10_n_0\,
      O => smallest(5),
      S => \po_stg2_wrcal_cnt_reg[3]\(2)
    );
wr_level_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^done_dqs_tap_inc\,
      I1 => \^wrlvl_byte_redo_r\,
      I2 => wrlvl_byte_redo,
      O => wr_level_done_i_1_n_0
    );
wr_level_done_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_r_reg_n_0,
      Q => wr_level_done_r1,
      R => '0'
    );
wr_level_done_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_r1,
      Q => wr_level_done_r2,
      R => '0'
    );
wr_level_done_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_r2,
      Q => wr_level_done_r3,
      R => '0'
    );
wr_level_done_r4_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_r3,
      Q => wr_level_done_r4,
      R => '0'
    );
wr_level_done_r5_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_r4,
      Q => \^wr_level_done_r5\,
      R => '0'
    );
wr_level_done_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100FFFF01000000"
    )
        port map (
      I0 => \rank_cnt_r_reg_n_0_[0]\,
      I1 => \rank_cnt_r_reg_n_0_[1]\,
      I2 => wl_state_r(2),
      I3 => wl_state_r(0),
      I4 => wr_level_done_r_i_2_n_0,
      I5 => wr_level_done_r_reg_n_0,
      O => wr_level_done_r_i_1_n_0
    );
wr_level_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800080000020000"
    )
        port map (
      I0 => wr_level_done_r_i_3_n_0,
      I1 => wl_state_r(3),
      I2 => wl_state_r(2),
      I3 => wl_state_r(0),
      I4 => done_dqs_dec239_out,
      I5 => wl_state_r(1),
      O => wr_level_done_r_i_2_n_0
    );
wr_level_done_r_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"43"
    )
        port map (
      I0 => \^p_0_in\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(3),
      O => wr_level_done_r_i_3_n_0
    );
wr_level_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_r_i_1_n_0,
      Q => wr_level_done_r_reg_n_0,
      R => \rstdiv0_sync_r1_reg_rep__6\(0)
    );
wr_level_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_level_done_i_1_n_0,
      Q => \^wrlvl_done_r_reg\,
      R => '0'
    );
wr_level_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_lvl_start_reg,
      Q => wr_level_start_r,
      R => '0'
    );
wrlvl_byte_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA00AA"
    )
        port map (
      I0 => \^wrlvl_byte_done\,
      I1 => wr_level_done_r4,
      I2 => wr_level_done_r3,
      I3 => wrlvl_byte_redo,
      I4 => \^wrlvl_byte_redo_r\,
      I5 => \rstdiv0_sync_r1_reg_rep__23\,
      O => wrlvl_byte_done_i_1_n_0
    );
wrlvl_byte_done_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_byte_done_i_1_n_0,
      Q => \^wrlvl_byte_done\,
      R => '0'
    );
wrlvl_byte_redo_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_byte_redo,
      Q => \^wrlvl_byte_redo_r\,
      R => '0'
    );
wrlvl_rank_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40FF4000"
    )
        port map (
      I0 => wl_state_r(2),
      I1 => wl_state_r(0),
      I2 => wl_state_r(4),
      I3 => wrlvl_rank_done_r_i_2_n_0,
      I4 => \^wrlvl_rank_done\,
      O => wrlvl_rank_done_r_i_1_n_0
    );
wrlvl_rank_done_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000505"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => \^p_0_in\,
      I2 => wl_state_r(2),
      I3 => wl_state_r(0),
      I4 => wl_state_r(3),
      I5 => wl_state_r(1),
      O => wrlvl_rank_done_r_i_2_n_0
    );
wrlvl_rank_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wrlvl_rank_done_r_i_1_n_0,
      Q => \^wrlvl_rank_done\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\wrlvl_redo_corse_inc[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01FF3100"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc[1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(2),
      I3 => \wrlvl_redo_corse_inc[2]_i_2_n_0\,
      I4 => wrlvl_redo_corse_inc(0),
      O => \wrlvl_redo_corse_inc[0]_i_1_n_0\
    );
\wrlvl_redo_corse_inc[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3202FFFF02320000"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc[1]_i_2_n_0\,
      I1 => wl_state_r(4),
      I2 => wl_state_r(2),
      I3 => wrlvl_redo_corse_inc(0),
      I4 => \wrlvl_redo_corse_inc[2]_i_2_n_0\,
      I5 => wrlvl_redo_corse_inc(1),
      O => \wrlvl_redo_corse_inc[1]_i_1_n_0\
    );
\wrlvl_redo_corse_inc[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F777"
    )
        port map (
      I0 => \corse_cnt_reg[0][2]_i_4_n_0\,
      I1 => early1_data_reg,
      I2 => final_coarse_tap(0),
      I3 => final_coarse_tap(1),
      O => \wrlvl_redo_corse_inc[1]_i_2_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5455FFFF01550000"
    )
        port map (
      I0 => wl_state_r(4),
      I1 => wrlvl_redo_corse_inc(1),
      I2 => wrlvl_redo_corse_inc(0),
      I3 => wl_state_r(2),
      I4 => \wrlvl_redo_corse_inc[2]_i_2_n_0\,
      I5 => wrlvl_redo_corse_inc(2),
      O => \wrlvl_redo_corse_inc[2]_i_1_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000004CC04"
    )
        port map (
      I0 => \wrlvl_redo_corse_inc[2]_i_3_n_0\,
      I1 => wrlvl_byte_redo,
      I2 => \^wrlvl_byte_redo_r\,
      I3 => wl_state_r(2),
      I4 => \wrlvl_redo_corse_inc[2]_i_4_n_0\,
      I5 => \corse_cnt[0][2]_i_6_n_0\,
      O => \wrlvl_redo_corse_inc[2]_i_2_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0B3FFFF"
    )
        port map (
      I0 => final_coarse_tap(0),
      I1 => early1_data_reg,
      I2 => final_coarse_tap(1),
      I3 => early2_data_reg,
      I4 => \corse_cnt_reg[0][2]_i_4_n_0\,
      O => \wrlvl_redo_corse_inc[2]_i_3_n_0\
    );
\wrlvl_redo_corse_inc[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wrlvl_redo_corse_inc(1),
      I1 => wrlvl_redo_corse_inc(0),
      I2 => wrlvl_redo_corse_inc(2),
      O => \wrlvl_redo_corse_inc[2]_i_4_n_0\
    );
\wrlvl_redo_corse_inc_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrlvl_redo_corse_inc[0]_i_1_n_0\,
      Q => wrlvl_redo_corse_inc(0),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\wrlvl_redo_corse_inc_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrlvl_redo_corse_inc[1]_i_1_n_0\,
      Q => wrlvl_redo_corse_inc(1),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
\wrlvl_redo_corse_inc_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wrlvl_redo_corse_inc[2]_i_1_n_0\,
      Q => wrlvl_redo_corse_inc(2),
      R => \rstdiv0_sync_r1_reg_rep__11\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_infrastructure is
  port (
    rst_sync_r1_reg_0 : out STD_LOGIC;
    CLK : out STD_LOGIC;
    freq_refclk : out STD_LOGIC;
    mem_refclk : out STD_LOGIC;
    sync_pulse : out STD_LOGIC;
    in0 : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_rdval_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    complex_oclkdelay_calib_start_int_reg : out STD_LOGIC;
    \po_rdval_cnt_reg[0]\ : out STD_LOGIC;
    \wl_dqs_tap_count_r_reg[0][3][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \smallest_reg[7][3]\ : out STD_LOGIC;
    \fine_inc_reg[6][5]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    wrcal_pat_resume_r_reg : out STD_LOGIC_VECTOR ( 1 downto 0 );
    wrlvl_byte_redo_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \two_inc_max_limit_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_fine_adj_state_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \last_master_r_reg[2]\ : out STD_LOGIC;
    pre_wait_r_reg : out STD_LOGIC;
    \cnt_shift_r_reg[0]\ : out STD_LOGIC;
    \wait_cnt_r_reg[0]\ : out STD_LOGIC;
    reset_reg : out STD_LOGIC;
    RST0 : out STD_LOGIC;
    pll_locked : out STD_LOGIC;
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    \complex_num_writes_dec_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ : out STD_LOGIC;
    \tap_cnt_cpt_r_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    clear : out STD_LOGIC;
    \wait_cnt_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cnt_shift_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_clk : in STD_LOGIC;
    AS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rst_ref_sync_r_reg[0][14]\ : in STD_LOGIC;
    bm_end_r1 : in STD_LOGIC;
    bm_end_r1_0 : in STD_LOGIC;
    bm_end_r1_1 : in STD_LOGIC;
    bm_end_r1_2 : in STD_LOGIC;
    po_cnt_dec : in STD_LOGIC;
    prbs_rdlvl_done_pulse : in STD_LOGIC;
    \init_state_r_reg[5]\ : in STD_LOGIC;
    new_cnt_cpt_r_reg : in STD_LOGIC;
    samp_edge_cnt0_en_r : in STD_LOGIC;
    pi_cnt_dec : in STD_LOGIC;
    rdlvl_stg1_start_reg : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_infrastructure : entity is "mig_7series_v2_3_infrastructure";
end mig_7series_0_mig_7series_v2_3_infrastructure;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_infrastructure is
  signal \^clk\ : STD_LOGIC;
  signal RST0_0 : STD_LOGIC;
  signal auxout_clk_i : STD_LOGIC;
  signal clk_pll_i : STD_LOGIC;
  signal \^cnt_shift_r_reg[0]\ : STD_LOGIC;
  signal \gen_mmcm.mmcm_i_n_17\ : STD_LOGIC;
  signal \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\ : STD_LOGIC;
  signal mmcm_ps_clk_bufg_in : STD_LOGIC;
  signal pll_clk3 : STD_LOGIC;
  signal pll_clk3_out : STD_LOGIC;
  signal pll_clkfbout : STD_LOGIC;
  signal pll_locked_i : STD_LOGIC;
  signal \^pre_wait_r_reg\ : STD_LOGIC;
  signal \^reset_reg\ : STD_LOGIC;
  signal rst_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal rst_sync_r1 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of rst_sync_r1 : signal is "10";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of rst_sync_r1 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of rst_sync_r1 : signal is "10";
  signal \^rst_sync_r1_reg_0\ : STD_LOGIC;
  signal rstdiv0_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \rstdiv0_sync_r1_reg_rep__0_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__10_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__11_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__12_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__13_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__14_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__15_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__16_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__17_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__18_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__19_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__1_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__20_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__21_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__22_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__23_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__2_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__3_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__4_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__5_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__6_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__7_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__8_n_0\ : STD_LOGIC;
  signal \rstdiv0_sync_r1_reg_rep__9_n_0\ : STD_LOGIC;
  signal rstdiv0_sync_r1_reg_rep_n_0 : STD_LOGIC;
  signal u_bufh_auxout_clk_n_0 : STD_LOGIC;
  signal \^wait_cnt_r_reg[0]\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_plle2_i_CLKOUT5_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_DRDY_UNCONNECTED : STD_LOGIC;
  signal NLW_plle2_i_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of \FSM_onehot_cal1_state_r[20]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \FSM_onehot_cal1_state_r[25]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \FSM_sequential_fine_adj_state_r[3]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \FSM_sequential_wl_state_r[4]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \cal1_cnt_cpt_r[2]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of cke_r_i_1 : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \cnt_pwron_ce_r[9]_i_1\ : label is 1;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \complex_num_writes_dec[4]_i_1\ : label is "soft_lutpair6";
  attribute IS_FANOUT_CONSTRAINED of \corse_dec[0][0]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \dqs_count_r[3]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of dqs_wl_po_stg2_c_incdec_i_1 : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \fine_inc[0][4]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \gen_final_tap[0].final_val[0][5]_i_1\ : label is 1;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \gen_mmcm.mmcm_i\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_mmcm.u_bufg_mmcm_ps_clk\ : label is "PRIMITIVE";
  attribute IS_FANOUT_CONSTRAINED of \i___22_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \i___43_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \i___70_i_1\ : label is 1;
  attribute SOFT_HLUTNM of phaser_ref_i_i_1 : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of phy_control_i_i_1 : label is "soft_lutpair9";
  attribute IS_FANOUT_CONSTRAINED of \pi_dqs_found_all_bank[2]_i_1\ : label is 1;
  attribute BOX_TYPE of plle2_i : label is "PRIMITIVE";
  attribute IS_FANOUT_CONSTRAINED of pwron_ce_r_i_1 : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \rank_cnt_r[1]_i_1\ : label is 1;
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_4\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_4__0\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_4__1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \ras_timer_r[0]_i_4__2\ : label is "soft_lutpair8";
  attribute IS_FANOUT_CONSTRAINED of reset_i_1 : label is 1;
  attribute RTL_MAX_FANOUT of rst_sync_r1_reg : label is "found";
  attribute syn_maxfan of rst_sync_r1_reg : label is "10";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of rstdiv0_sync_r1_reg_rep : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__0\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__1\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__10\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__11\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__12\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__13\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__14\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__15\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__16\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__17\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__18\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__19\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__2\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__20\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__21\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__22\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__23\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__3\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__4\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__5\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__6\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__7\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__8\ : label is "rstdiv0_sync_r1_reg";
  attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__9\ : label is "rstdiv0_sync_r1_reg";
  attribute SOFT_HLUTNM of \samp_edge_cnt0_r[0]_i_1\ : label is "soft_lutpair10";
  attribute IS_FANOUT_CONSTRAINED of \smallest[0][2]_i_1\ : label is 1;
  attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_1\ : label is "soft_lutpair6";
  attribute IS_FANOUT_CONSTRAINED of \tempmon_state[10]_i_1\ : label is 1;
  attribute BOX_TYPE of u_bufg_clkdiv0 : label is "PRIMITIVE";
  attribute BOX_TYPE of u_bufh_auxout_clk : label is "PRIMITIVE";
  attribute BOX_TYPE of u_bufh_pll_clk3 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_1__0\ : label is "soft_lutpair10";
  attribute IS_FANOUT_CONSTRAINED of \wl_dqs_tap_count_r[0][3][0]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \wrcal_dqs_cnt_r[3]_i_1\ : label is 1;
  attribute IS_FANOUT_CONSTRAINED of \wrcal_reads[7]_i_4\ : label is 1;
begin
  CLK <= \^clk\;
  \cnt_shift_r_reg[0]\ <= \^cnt_shift_r_reg[0]\;
  pre_wait_r_reg <= \^pre_wait_r_reg\;
  reset_reg <= \^reset_reg\;
  rst_sync_r1_reg_0 <= \^rst_sync_r1_reg_0\;
  \wait_cnt_r_reg[0]\ <= \^wait_cnt_r_reg[0]\;
\FSM_onehot_cal1_state_r[20]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__16_n_0\,
      O => wrlvl_byte_redo_reg(1)
    );
\FSM_onehot_cal1_state_r[25]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__14_n_0\,
      O => wrlvl_byte_redo_reg(2)
    );
\FSM_sequential_fine_adj_state_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__17_n_0\,
      O => \FSM_sequential_fine_adj_state_r_reg[3]\(0)
    );
\FSM_sequential_wl_state_r[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__1_n_0\,
      O => SR(1)
    );
\cal1_cnt_cpt_r[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__2_n_0\,
      O => \pi_rdval_cnt_reg[0]\(1)
    );
cke_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__0_n_0\,
      O => SR(0)
    );
\cnt_pwron_ce_r[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__18_n_0\,
      O => wrlvl_byte_redo_reg(0)
    );
\cnt_shift_r[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^cnt_shift_r_reg[0]\,
      I1 => rdlvl_stg1_start_reg,
      O => \cnt_shift_r_reg[0]_0\(0)
    );
\complex_num_writes_dec[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^wait_cnt_r_reg[0]\,
      I1 => prbs_rdlvl_done_pulse,
      O => \complex_num_writes_dec_reg[0]\(0)
    );
\corse_dec[0][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__5_n_0\,
      O => \po_rdval_cnt_reg[0]\
    );
\dqs_count_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__10_n_0\,
      O => \fine_inc_reg[6][5]\(1)
    );
dqs_wl_po_stg2_c_incdec_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__4_n_0\,
      O => complex_oclkdelay_calib_start_int_reg
    );
\en_cnt_div4.enable_wrlvl_cnt[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^wait_cnt_r_reg[0]\,
      I1 => \init_state_r_reg[5]\,
      O => \en_cnt_div4.enable_wrlvl_cnt_reg[4]\
    );
\fine_inc[0][4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__9_n_0\,
      O => \fine_inc_reg[6][5]\(0)
    );
\gen_final_tap[0].final_val[0][5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__11_n_0\,
      O => wrcal_pat_resume_r_reg(0)
    );
\gen_mmcm.mmcm_i\: unisim.vcomponents.MMCME2_ADV
    generic map(
      BANDWIDTH => "HIGH",
      CLKFBOUT_MULT_F => 8.000000,
      CLKFBOUT_PHASE => 0.000000,
      CLKFBOUT_USE_FINE_PS => false,
      CLKIN1_PERIOD => 12.000000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE_F => 16.000000,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT0_USE_FINE_PS => true,
      CLKOUT1_DIVIDE => 1,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT1_USE_FINE_PS => false,
      CLKOUT2_DIVIDE => 1,
      CLKOUT2_DUTY_CYCLE => 0.500000,
      CLKOUT2_PHASE => 0.000000,
      CLKOUT2_USE_FINE_PS => false,
      CLKOUT3_DIVIDE => 1,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT3_USE_FINE_PS => false,
      CLKOUT4_CASCADE => false,
      CLKOUT4_DIVIDE => 1,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 0.000000,
      CLKOUT4_USE_FINE_PS => false,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      CLKOUT5_USE_FINE_PS => false,
      CLKOUT6_DIVIDE => 1,
      CLKOUT6_DUTY_CYCLE => 0.500000,
      CLKOUT6_PHASE => 0.000000,
      CLKOUT6_USE_FINE_PS => false,
      COMPENSATION => "BUF_IN",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PSEN_INVERTED => '0',
      IS_PSINCDEC_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.000000,
      REF_JITTER2 => 0.010000,
      SS_EN => "FALSE",
      SS_MODE => "CENTER_HIGH",
      SS_MOD_PERIOD => 10000,
      STARTUP_WAIT => false
    )
        port map (
      CLKFBIN => \^clk\,
      CLKFBOUT => clk_pll_i,
      CLKFBOUTB => \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\,
      CLKFBSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\,
      CLKIN1 => pll_clk3,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKINSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\,
      CLKOUT0 => mmcm_ps_clk_bufg_in,
      CLKOUT0B => \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\,
      CLKOUT1 => \NLW_gen_mmcm.mmcm_i_CLKOUT1_UNCONNECTED\,
      CLKOUT1B => \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\,
      CLKOUT2 => \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\,
      CLKOUT2B => \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\,
      CLKOUT3 => \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\,
      CLKOUT3B => \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\,
      CLKOUT4 => \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\,
      CLKOUT5 => \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\,
      CLKOUT6 => \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\(15 downto 0),
      DRDY => \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\,
      DWE => '0',
      LOCKED => \^rst_sync_r1_reg_0\,
      PSCLK => \^clk\,
      PSDONE => \gen_mmcm.mmcm_i_n_17\,
      PSEN => '0',
      PSINCDEC => '0',
      PWRDWN => '0',
      RST => RST0_0
    );
\gen_mmcm.mmcm_i_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pll_locked_i,
      O => RST0_0
    );
\gen_mmcm.u_bufg_mmcm_ps_clk\: unisim.vcomponents.BUFG
     port map (
      I => mmcm_ps_clk_bufg_in,
      O => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\
    );
\i___22_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21_n_0\,
      O => \^cnt_shift_r_reg[0]\
    );
\i___43_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20_n_0\,
      O => \^pre_wait_r_reg\
    );
\i___70_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19_n_0\,
      O => \last_master_r_reg[2]\
    );
phaser_ref_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => pll_locked_i,
      I1 => \^rst_sync_r1_reg_0\,
      O => RST0
    );
phy_control_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => pll_locked_i,
      I1 => \^rst_sync_r1_reg_0\,
      O => pll_locked
    );
\pi_dqs_found_all_bank[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__12_n_0\,
      O => wrcal_pat_resume_r_reg(1)
    );
plle2_i: unisim.vcomponents.PLLE2_ADV
    generic map(
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_MULT => 4,
      CLKFBOUT_PHASE => 0.000000,
      CLKIN1_PERIOD => 3.000000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE => 2,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT1_DIVIDE => 4,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT2_DIVIDE => 64,
      CLKOUT2_DUTY_CYCLE => 0.062500,
      CLKOUT2_PHASE => 9.843750,
      CLKOUT3_DIVIDE => 16,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT4_DIVIDE => 8,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 168.750000,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      COMPENSATION => "INTERNAL",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.010000,
      REF_JITTER2 => 0.010000,
      STARTUP_WAIT => "FALSE"
    )
        port map (
      CLKFBIN => pll_clkfbout,
      CLKFBOUT => pll_clkfbout,
      CLKIN1 => mmcm_clk,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKOUT0 => freq_refclk,
      CLKOUT1 => mem_refclk,
      CLKOUT2 => sync_pulse,
      CLKOUT3 => pll_clk3_out,
      CLKOUT4 => auxout_clk_i,
      CLKOUT5 => NLW_plle2_i_CLKOUT5_UNCONNECTED,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => NLW_plle2_i_DO_UNCONNECTED(15 downto 0),
      DRDY => NLW_plle2_i_DRDY_UNCONNECTED,
      DWE => '0',
      LOCKED => pll_locked_i,
      PWRDWN => '0',
      RST => AS(0)
    );
pwron_ce_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__3_n_0\,
      O => \pi_rdval_cnt_reg[0]\(0)
    );
\rank_cnt_r[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__8_n_0\,
      O => \smallest_reg[7][3]\
    );
\ras_timer_r[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^pre_wait_r_reg\,
      I1 => bm_end_r1,
      O => \ras_timer_r_reg[0]\
    );
\ras_timer_r[0]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^pre_wait_r_reg\,
      I1 => bm_end_r1_0,
      O => ras_timer_zero_r_reg
    );
\ras_timer_r[0]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^pre_wait_r_reg\,
      I1 => bm_end_r1_1,
      O => ras_timer_zero_r_reg_0
    );
\ras_timer_r[0]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^pre_wait_r_reg\,
      I1 => bm_end_r1_2,
      O => \ras_timer_r_reg[0]_0\
    );
reset_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__23_n_0\,
      O => \^reset_reg\
    );
rst_sync_r1_reg: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r1
    );
\rst_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => '0',
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(0)
    );
\rst_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(9),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(10)
    );
\rst_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(10),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(11)
    );
\rst_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(0),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(1)
    );
\rst_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(1),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(2)
    );
\rst_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(2),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(3)
    );
\rst_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(3),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(4)
    );
\rst_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(4),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(5)
    );
\rst_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(5),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(6)
    );
\rst_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(6),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(7)
    );
\rst_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(7),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(8)
    );
\rst_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\,
      CE => '1',
      D => rst_sync_r(8),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rst_sync_r(9)
    );
rstdiv0_sync_r1_reg_rep: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r1_reg_rep_n_0
    );
\rstdiv0_sync_r1_reg_rep__0\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__0_n_0\
    );
\rstdiv0_sync_r1_reg_rep__1\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__1_n_0\
    );
\rstdiv0_sync_r1_reg_rep__10\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__10_n_0\
    );
\rstdiv0_sync_r1_reg_rep__11\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__11_n_0\
    );
\rstdiv0_sync_r1_reg_rep__12\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__12_n_0\
    );
\rstdiv0_sync_r1_reg_rep__13\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__13_n_0\
    );
\rstdiv0_sync_r1_reg_rep__14\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__14_n_0\
    );
\rstdiv0_sync_r1_reg_rep__15\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__15_n_0\
    );
\rstdiv0_sync_r1_reg_rep__16\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__16_n_0\
    );
\rstdiv0_sync_r1_reg_rep__17\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__17_n_0\
    );
\rstdiv0_sync_r1_reg_rep__18\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__18_n_0\
    );
\rstdiv0_sync_r1_reg_rep__19\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__19_n_0\
    );
\rstdiv0_sync_r1_reg_rep__2\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__2_n_0\
    );
\rstdiv0_sync_r1_reg_rep__20\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__20_n_0\
    );
\rstdiv0_sync_r1_reg_rep__21\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__21_n_0\
    );
\rstdiv0_sync_r1_reg_rep__22\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__22_n_0\
    );
\rstdiv0_sync_r1_reg_rep__23\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__23_n_0\
    );
\rstdiv0_sync_r1_reg_rep__3\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__3_n_0\
    );
\rstdiv0_sync_r1_reg_rep__4\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__4_n_0\
    );
\rstdiv0_sync_r1_reg_rep__5\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__5_n_0\
    );
\rstdiv0_sync_r1_reg_rep__6\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__6_n_0\
    );
\rstdiv0_sync_r1_reg_rep__7\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__7_n_0\
    );
\rstdiv0_sync_r1_reg_rep__8\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__8_n_0\
    );
\rstdiv0_sync_r1_reg_rep__9\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(11),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => \rstdiv0_sync_r1_reg_rep__9_n_0\
    );
\rstdiv0_sync_r_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => '0',
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(0)
    );
\rstdiv0_sync_r_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(9),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(10)
    );
\rstdiv0_sync_r_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(10),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(11)
    );
\rstdiv0_sync_r_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(0),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(1)
    );
\rstdiv0_sync_r_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(1),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(2)
    );
\rstdiv0_sync_r_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(2),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(3)
    );
\rstdiv0_sync_r_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(3),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(4)
    );
\rstdiv0_sync_r_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(4),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(5)
    );
\rstdiv0_sync_r_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(5),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(6)
    );
\rstdiv0_sync_r_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(6),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(7)
    );
\rstdiv0_sync_r_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(7),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(8)
    );
\rstdiv0_sync_r_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => \^clk\,
      CE => '1',
      D => rstdiv0_sync_r(8),
      PRE => \rst_ref_sync_r_reg[0][14]\,
      Q => rstdiv0_sync_r(9)
    );
\samp_edge_cnt0_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^wait_cnt_r_reg[0]\,
      I1 => samp_edge_cnt0_en_r,
      O => clear
    );
\smallest[0][2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__7_n_0\,
      O => \wl_dqs_tap_count_r_reg[0][3][1]\(1)
    );
\tap_cnt_cpt_r[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^wait_cnt_r_reg[0]\,
      I1 => new_cnt_cpt_r_reg,
      O => \tap_cnt_cpt_r_reg[5]\(0)
    );
\tempmon_state[10]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__15_n_0\,
      O => \two_inc_max_limit_reg[1]\(0)
    );
u_bufg_clkdiv0: unisim.vcomponents.BUFG
     port map (
      I => clk_pll_i,
      O => \^clk\
    );
u_bufh_auxout_clk: unisim.vcomponents.BUFH
     port map (
      I => auxout_clk_i,
      O => u_bufh_auxout_clk_n_0
    );
u_bufh_pll_clk3: unisim.vcomponents.BUFH
     port map (
      I => pll_clk3_out,
      O => pll_clk3
    );
ui_clk_sync_rst_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rstdiv0_sync_r1_reg_rep_n_0,
      O => in0
    );
\wait_cnt[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset_reg\,
      I1 => po_cnt_dec,
      O => SS(0)
    );
\wait_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^wait_cnt_r_reg[0]\,
      I1 => pi_cnt_dec,
      O => \wait_cnt_r_reg[0]_0\(0)
    );
\wl_dqs_tap_count_r[0][3][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__6_n_0\,
      O => \wl_dqs_tap_count_r_reg[0][3][1]\(0)
    );
\wrcal_dqs_cnt_r[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__13_n_0\,
      O => wrlvl_byte_redo_reg(3)
    );
\wrcal_reads[7]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__22_n_0\,
      O => \^wait_cnt_r_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_iodelay_ctrl is
  port (
    iodelay_ctrl_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    AS : out STD_LOGIC_VECTOR ( 0 to 0 );
    clk_ref_i : in STD_LOGIC;
    sys_rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_iodelay_ctrl : entity is "mig_7series_v2_3_iodelay_ctrl";
end mig_7series_0_mig_7series_v2_3_iodelay_ctrl;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_iodelay_ctrl is
  signal \^as\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rst_ref : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rst_ref_sync_r_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][10]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][11]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][12]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][13]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][8]\ : STD_LOGIC;
  signal \rst_ref_sync_r_reg_n_0_[0][9]\ : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][0]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][10]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][11]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][12]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][13]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][14]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][1]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][2]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][3]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][4]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][5]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][6]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][7]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][8]\ : label is "10";
  attribute syn_maxfan of \rst_ref_sync_r_reg[0][9]\ : label is "10";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_idelayctrl_200 : label is "PRIMITIVE";
  attribute IODELAY_GROUP : string;
  attribute IODELAY_GROUP of u_idelayctrl_200 : label is "MIG_7SERIES_0_IODELAY_MIG0";
begin
  AS(0) <= \^as\(0);
plle2_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sys_rst,
      O => \^as\(0)
    );
\rst_ref_sync_r_reg[0][0]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => '0',
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][0]\
    );
\rst_ref_sync_r_reg[0][10]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][9]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][10]\
    );
\rst_ref_sync_r_reg[0][11]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][10]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][11]\
    );
\rst_ref_sync_r_reg[0][12]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][11]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][12]\
    );
\rst_ref_sync_r_reg[0][13]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][12]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][13]\
    );
\rst_ref_sync_r_reg[0][14]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][13]\,
      PRE => \^as\(0),
      Q => rst_ref(0)
    );
\rst_ref_sync_r_reg[0][1]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][0]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][1]\
    );
\rst_ref_sync_r_reg[0][2]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][1]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][2]\
    );
\rst_ref_sync_r_reg[0][3]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][2]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][3]\
    );
\rst_ref_sync_r_reg[0][4]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][3]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][4]\
    );
\rst_ref_sync_r_reg[0][5]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][4]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][5]\
    );
\rst_ref_sync_r_reg[0][6]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][5]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][6]\
    );
\rst_ref_sync_r_reg[0][7]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][6]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][7]\
    );
\rst_ref_sync_r_reg[0][8]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][7]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][8]\
    );
\rst_ref_sync_r_reg[0][9]\: unisim.vcomponents.FDPE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \rst_ref_sync_r_reg_n_0_[0][8]\,
      PRE => \^as\(0),
      Q => \rst_ref_sync_r_reg_n_0_[0][9]\
    );
u_idelayctrl_200: unisim.vcomponents.IDELAYCTRL
    generic map(
      SIM_DEVICE => "7SERIES"
    )
        port map (
      RDY => iodelay_ctrl_rdy(0),
      REFCLK => clk_ref_i,
      RST => rst_ref(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_rank_cntrl is
  port (
    \inhbt_act_faw.act_delayed\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : out STD_LOGIC;
    inhbt_act_faw_r : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \periodic_rd_generation.periodic_rd_cntr1_r\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \maintenance_request.upd_last_master_r_reg\ : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg_0\ : out STD_LOGIC;
    \inhbt_act_faw.inhbt_act_faw_r_reg_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    act_this_rank : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : in STD_LOGIC;
    in0 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \maint_prescaler.maint_prescaler_r1\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[1]_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[1]_1\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_read_request.periodic_rd_grant_r_reg[0]\ : in STD_LOGIC;
    insert_maint_r1_lcl_reg : in STD_LOGIC;
    \maint_prescaler.maint_prescaler_tick_r_lcl_reg\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    \periodic_rd_generation.int_read_this_rank\ : in STD_LOGIC;
    \sr_cntrl.sre_request_logic.sre_request_r_reg\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \wtr_timer.wtr_cnt_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_rank_cntrl : entity is "mig_7series_v2_3_rank_cntrl";
end mig_7series_0_mig_7series_v2_3_rank_cntrl;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_rank_cntrl is
  signal \^grant_r_reg[0]\ : STD_LOGIC;
  signal \^inhbt_act_faw.act_delayed\ : STD_LOGIC;
  signal \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\ : STD_LOGIC;
  signal \^inhbt_act_faw.inhbt_act_faw_r_reg_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC;
  signal \^periodic_rd_generation.periodic_rd_timer_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \inhbt_act_faw.SRLC32E0\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl ";
  attribute srl_name : string;
  attribute srl_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 ";
begin
  \grant_r_reg[0]\ <= \^grant_r_reg[0]\;
  \inhbt_act_faw.act_delayed\ <= \^inhbt_act_faw.act_delayed\;
  \inhbt_act_faw.inhbt_act_faw_r_reg_0\(2 downto 0) <= \^inhbt_act_faw.inhbt_act_faw_r_reg_0\(2 downto 0);
  \periodic_rd_generation.periodic_rd_request_r\ <= \^periodic_rd_generation.periodic_rd_request_r\;
  \periodic_rd_generation.periodic_rd_timer_r\(2 downto 0) <= \^periodic_rd_generation.periodic_rd_timer_r\(2 downto 0);
\i___17_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FDFF"
    )
        port map (
      I0 => \^periodic_rd_generation.periodic_rd_timer_r\(0),
      I1 => \^periodic_rd_generation.periodic_rd_timer_r\(1),
      I2 => \^periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => \maint_prescaler.maint_prescaler_tick_r_lcl_reg\,
      I4 => \^periodic_rd_generation.periodic_rd_request_r\,
      O => \periodic_rd_generation.periodic_rd_request_r_reg_0\
    );
\inhbt_act_faw.SRLC32E0\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"00000",
      CE => '1',
      CLK => CLK,
      D => act_this_rank,
      Q => \^inhbt_act_faw.act_delayed\,
      Q31 => \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\
    );
\inhbt_act_faw.faw_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => \^inhbt_act_faw.inhbt_act_faw_r_reg_0\(0),
      R => '0'
    );
\inhbt_act_faw.faw_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => \^inhbt_act_faw.inhbt_act_faw_r_reg_0\(1),
      R => '0'
    );
\inhbt_act_faw.faw_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => \^inhbt_act_faw.inhbt_act_faw_r_reg_0\(2),
      R => '0'
    );
\inhbt_act_faw.inhbt_act_faw_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000202002"
    )
        port map (
      I0 => \^inhbt_act_faw.inhbt_act_faw_r_reg_0\(2),
      I1 => \rstdiv0_sync_r1_reg_rep__19\,
      I2 => \^inhbt_act_faw.act_delayed\,
      I3 => act_this_rank,
      I4 => \^inhbt_act_faw.inhbt_act_faw_r_reg_0\(0),
      I5 => \^inhbt_act_faw.inhbt_act_faw_r_reg_0\(1),
      O => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\
    );
\inhbt_act_faw.inhbt_act_faw_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\,
      Q => inhbt_act_faw_r,
      R => '0'
    );
\maintenance_request.upd_last_master_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2F"
    )
        port map (
      I0 => \^grant_r_reg[0]\,
      I1 => \sr_cntrl.sre_request_logic.sre_request_r_reg\,
      I2 => \init_calib_complete_reg_rep__12\,
      O => \maintenance_request.upd_last_master_r_reg\
    );
\periodic_rd_generation.periodic_rd_cntr1_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.periodic_rd_grant_r_reg[0]\,
      Q => \periodic_rd_generation.periodic_rd_cntr1_r\,
      R => SR(0)
    );
\periodic_rd_generation.periodic_rd_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => periodic_rd_ack_r_lcl_reg,
      Q => \^periodic_rd_generation.periodic_rd_request_r\,
      R => in0
    );
\periodic_rd_generation.periodic_rd_timer_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F5080000"
    )
        port map (
      I0 => \maint_prescaler.maint_prescaler_tick_r_lcl_reg\,
      I1 => \^periodic_rd_generation.periodic_rd_timer_r\(2),
      I2 => \^periodic_rd_generation.periodic_rd_timer_r\(0),
      I3 => \^periodic_rd_generation.periodic_rd_timer_r\(1),
      I4 => \init_calib_complete_reg_rep__12\,
      I5 => \periodic_rd_generation.int_read_this_rank\,
      O => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r_reg[1]_1\,
      Q => \^periodic_rd_generation.periodic_rd_timer_r\(0),
      R => \maint_prescaler.maint_prescaler_r1\
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\,
      Q => \^periodic_rd_generation.periodic_rd_timer_r\(1),
      R => '0'
    );
\periodic_rd_generation.periodic_rd_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_timer_r_reg[1]_0\,
      Q => \^periodic_rd_generation.periodic_rd_timer_r\(2),
      R => \maint_prescaler.maint_prescaler_r1\
    );
\periodic_rd_generation.read_this_rank_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.read_this_rank\,
      Q => \periodic_rd_generation.read_this_rank_r\,
      R => '0'
    );
\refresh_generation.refresh_bank_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => insert_maint_r1_lcl_reg,
      Q => \^grant_r_reg[0]\,
      R => \maint_prescaler.maint_prescaler_r1\
    );
\wtr_timer.wtr_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wtr_timer.wtr_cnt_r_reg[0]_1\(0),
      Q => \wtr_timer.wtr_cnt_r_reg[0]_0\(0),
      R => '0'
    );
\wtr_timer.wtr_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wtr_timer.wtr_cnt_r_reg[0]_1\(1),
      Q => \wtr_timer.wtr_cnt_r_reg[0]_0\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_round_robin_arb is
  port (
    \maintenance_request.maint_sre_ns\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_srx_r_lcl_reg\ : out STD_LOGIC;
    \maintenance_request.maint_zq_r_lcl_reg\ : out STD_LOGIC;
    \last_master_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \maintenance_request.maint_sre_r_lcl_reg\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \sr_cntrl.ckesr_timer.ckesr_timer_r\ : in STD_LOGIC;
    \maintenance_request.upd_last_master_r_reg\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC;
    \sr_cntrl.sre_request_logic.sre_request_r_reg\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]\ : in STD_LOGIC;
    \last_master_r_reg[2]_1\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_round_robin_arb : entity is "mig_7series_v2_3_round_robin_arb";
end mig_7series_0_mig_7series_v2_3_round_robin_arb;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_round_robin_arb is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \grant_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \last_master_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \^last_master_r_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \maintenance_request.maint_grant_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \last_master_r[1]_i_1__2\ : label is "soft_lutpair1012";
  attribute SOFT_HLUTNM of \maintenance_request.maint_zq_r_lcl_i_1\ : label is "soft_lutpair1012";
begin
  Q(0) <= \^q\(0);
  \last_master_r_reg[2]_0\(0) <= \^last_master_r_reg[2]_0\(0);
\grant_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000007370000"
    )
        port map (
      I0 => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      I1 => \last_master_r[0]_i_1__2_n_0\,
      I2 => \sr_cntrl.sre_request_logic.sre_request_r_reg\,
      I3 => \last_master_r[1]_i_1__2_n_0\,
      I4 => \init_calib_complete_reg_rep__12\,
      I5 => \refresh_generation.refresh_bank_r_reg[0]\,
      O => \grant_r[0]_i_1_n_0\
    );
\grant_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7000500070000000"
    )
        port map (
      I0 => \last_master_r[1]_i_1__2_n_0\,
      I1 => \sr_cntrl.sre_request_logic.sre_request_r_reg\,
      I2 => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      I3 => \init_calib_complete_reg_rep__12\,
      I4 => \refresh_generation.refresh_bank_r_reg[0]\,
      I5 => \last_master_r_reg[2]_1\,
      O => \grant_r[1]_i_1_n_0\
    );
\grant_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000E000A000E000"
    )
        port map (
      I0 => \last_master_r_reg[2]_1\,
      I1 => \refresh_generation.refresh_bank_r_reg[0]\,
      I2 => \init_calib_complete_reg_rep__12\,
      I3 => \sr_cntrl.sre_request_logic.sre_request_r_reg\,
      I4 => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      I5 => \last_master_r[0]_i_1__2_n_0\,
      O => \grant_r[2]_i_1_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1_n_0\,
      Q => \maintenance_request.maint_grant_r\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[1]_i_1_n_0\,
      Q => \maintenance_request.maint_grant_r\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\last_master_r[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(0),
      I1 => \maintenance_request.upd_last_master_r_reg\,
      I2 => \maintenance_request.maint_grant_r\(0),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \last_master_r[0]_i_1__2_n_0\
    );
\last_master_r[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(1),
      I1 => \maintenance_request.upd_last_master_r_reg\,
      I2 => \maintenance_request.maint_grant_r\(1),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \last_master_r[1]_i_1__2_n_0\
    );
\last_master_r[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFB8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \maintenance_request.upd_last_master_r_reg\,
      I2 => \^last_master_r_reg[2]_0\(0),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \last_master_r[2]_i_1__2_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[0]_i_1__2_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1__2_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1__2_n_0\,
      Q => \^last_master_r_reg[2]_0\(0),
      R => '0'
    );
\maintenance_request.maint_sre_r_lcl_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFA800A8"
    )
        port map (
      I0 => \maintenance_request.maint_sre_r_lcl_reg\,
      I1 => app_sr_req,
      I2 => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      I3 => \maintenance_request.upd_last_master_r_reg\,
      I4 => \^q\(0),
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \maintenance_request.maint_sre_ns\
    );
\maintenance_request.maint_srx_r_lcl_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5702575702020202"
    )
        port map (
      I0 => \maintenance_request.maint_sre_r_lcl_reg\,
      I1 => app_sr_req,
      I2 => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      I3 => \^q\(0),
      I4 => \maintenance_request.upd_last_master_r_reg\,
      I5 => maint_srx_r,
      O => \maintenance_request.maint_srx_r_lcl_reg\
    );
\maintenance_request.maint_zq_r_lcl_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \maintenance_request.maint_grant_r\(1),
      I1 => \maintenance_request.upd_last_master_r_reg\,
      I2 => maint_zq_r,
      O => \maintenance_request.maint_zq_r_lcl_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1\ is
  port (
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.int_read_this_rank\ : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : out STD_LOGIC;
    \last_master_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_address_reg[24]\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    demand_priority_r_reg : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    demand_priority_r_reg_2 : out STD_LOGIC;
    \grant_r_reg[3]_2\ : out STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rd_wr_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_aux_out0_reg[1]\ : in STD_LOGIC;
    col_rd_wr_r : in STD_LOGIC;
    \col_mux.col_periodic_rd_r\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_5 : in STD_LOGIC;
    rd_wr_r_lcl_reg_6 : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    ofs_rdy_r : in STD_LOGIC;
    \genblk3[1].rnk_config_strobe_r_reg\ : in STD_LOGIC;
    \genblk3[2].rnk_config_strobe_r_reg\ : in STD_LOGIC;
    rnk_config_strobe : in STD_LOGIC;
    ofs_rdy_r_3 : in STD_LOGIC;
    ofs_rdy_r_4 : in STD_LOGIC;
    ofs_rdy_r_5 : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \col_mux.col_data_buf_addr_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    auto_pre_r : in STD_LOGIC;
    auto_pre_r_6 : in STD_LOGIC;
    auto_pre_r_7 : in STD_LOGIC;
    auto_pre_r_8 : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_bank_rdy_r : in STD_LOGIC;
    req_bank_rdy_r_9 : in STD_LOGIC;
    req_bank_rdy_r_10 : in STD_LOGIC;
    req_bank_rdy_r_11 : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1\ : entity is "mig_7series_v2_3_round_robin_arb";
end \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1\ is
  signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[14]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[15]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[16]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[17]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[18]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[19]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[20]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[21]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[22]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[23]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[24]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[3]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[4]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[5]_i_2_n_0\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_odt_reg[0]\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_we_n_reg[1]\ : STD_LOGIC;
  signal \col_mux.col_data_buf_addr_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \col_mux.col_periodic_rd_r_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_4_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_3_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_5_n_0\ : STD_LOGIC;
  signal \i___19_i_2_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \^last_master_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \periodic_rd_generation.read_this_rank_r_i_2_n_0\ : STD_LOGIC;
  signal \read_fifo.fifo_ram[0].RAM32M0_i_10_n_0\ : STD_LOGIC;
  signal \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\ : STD_LOGIC;
  signal \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\ : STD_LOGIC;
  signal \read_fifo.fifo_ram[0].RAM32M0_i_9_n_0\ : STD_LOGIC;
  signal \^wtr_timer.wtr_cnt_r_reg[0]\ : STD_LOGIC;
  signal \^wtr_timer.wtr_cnt_r_reg[0]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[14]_i_1\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[15]_i_1\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cmd[1]_i_1\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[5]_i_1\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_odt[0]_i_1\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of \col_mux.col_rd_wr_r_i_1\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of demand_priority_r_i_4 : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \demand_priority_r_i_4__0\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \demand_priority_r_i_4__1\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \demand_priority_r_i_4__2\ : label is "soft_lutpair956";
  attribute SOFT_HLUTNM of \last_master_r[0]_i_1\ : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \last_master_r[1]_i_1\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \last_master_r[2]_i_1\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \last_master_r[3]_i_1\ : label is "soft_lutpair956";
begin
  D(1 downto 0) <= \^d\(1 downto 0);
  Q(3 downto 0) <= \^q\(3 downto 0);
  \cmd_pipe_plus.mc_odt_reg[0]\ <= \^cmd_pipe_plus.mc_odt_reg[0]\;
  \cmd_pipe_plus.mc_we_n_reg[1]\ <= \^cmd_pipe_plus.mc_we_n_reg[1]\;
  \last_master_r_reg[1]_0\(0) <= \^last_master_r_reg[1]_0\(0);
  \wtr_timer.wtr_cnt_r_reg[0]\ <= \^wtr_timer.wtr_cnt_r_reg[0]\;
  \wtr_timer.wtr_cnt_r_reg[0]_0\ <= \^wtr_timer.wtr_cnt_r_reg[0]_0\;
\cmd_pipe_plus.mc_address[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[14]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(0),
      O => \cmd_pipe_plus.mc_address_reg[24]\(0)
    );
\cmd_pipe_plus.mc_address[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(0),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(0),
      O => \cmd_pipe_plus.mc_address[14]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[15]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(1),
      O => \cmd_pipe_plus.mc_address_reg[24]\(1)
    );
\cmd_pipe_plus.mc_address[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(1),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(1),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(1),
      O => \cmd_pipe_plus.mc_address[15]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[16]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(2),
      O => \cmd_pipe_plus.mc_address_reg[24]\(2)
    );
\cmd_pipe_plus.mc_address[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(2),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(2),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(2),
      O => \cmd_pipe_plus.mc_address[16]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[17]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(3),
      O => \cmd_pipe_plus.mc_address_reg[24]\(3)
    );
\cmd_pipe_plus.mc_address[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(3),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(3),
      O => \cmd_pipe_plus.mc_address[17]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[18]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(4),
      O => \cmd_pipe_plus.mc_address_reg[24]\(4)
    );
\cmd_pipe_plus.mc_address[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(4),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(4),
      O => \cmd_pipe_plus.mc_address[18]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[19]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(5),
      O => \cmd_pipe_plus.mc_address_reg[24]\(5)
    );
\cmd_pipe_plus.mc_address[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(5),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(5),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(5),
      O => \cmd_pipe_plus.mc_address[19]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[20]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(6),
      O => \cmd_pipe_plus.mc_address_reg[24]\(6)
    );
\cmd_pipe_plus.mc_address[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(6),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(6),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(6),
      O => \cmd_pipe_plus.mc_address[20]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[21]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(7),
      O => \cmd_pipe_plus.mc_address_reg[24]\(7)
    );
\cmd_pipe_plus.mc_address[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(7),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(7),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(7),
      O => \cmd_pipe_plus.mc_address[21]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[22]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(8),
      O => \cmd_pipe_plus.mc_address_reg[24]\(8)
    );
\cmd_pipe_plus.mc_address[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(8),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(8),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(8),
      O => \cmd_pipe_plus.mc_address[22]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[23]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_col_r_reg[9]\(9),
      O => \cmd_pipe_plus.mc_address_reg[24]\(9)
    );
\cmd_pipe_plus.mc_address[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_col_r_reg[9]_0\(9),
      I1 => \^q\(0),
      I2 => \req_col_r_reg[9]_1\(9),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_col_r_reg[9]_2\(9),
      O => \cmd_pipe_plus.mc_address[23]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_address[24]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => auto_pre_r,
      O => \cmd_pipe_plus.mc_address_reg[24]\(10)
    );
\cmd_pipe_plus.mc_address[24]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => auto_pre_r_6,
      I1 => \^q\(0),
      I2 => auto_pre_r_7,
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => auto_pre_r_8,
      O => \cmd_pipe_plus.mc_address[24]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_bank_r_lcl_reg[2]\(0),
      O => \cmd_pipe_plus.mc_bank_reg[5]\(0)
    );
\cmd_pipe_plus.mc_bank[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]_0\(0),
      I1 => \^q\(0),
      I2 => \req_bank_r_lcl_reg[2]_1\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_bank_r_lcl_reg[2]_2\(0),
      O => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_bank_r_lcl_reg[2]\(1),
      O => \cmd_pipe_plus.mc_bank_reg[5]\(1)
    );
\cmd_pipe_plus.mc_bank[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]_0\(1),
      I1 => \^q\(0),
      I2 => \req_bank_r_lcl_reg[2]_1\(1),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_bank_r_lcl_reg[2]_2\(1),
      O => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F737"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\,
      I1 => granted_col_r_reg,
      I2 => \^q\(3),
      I3 => \req_bank_r_lcl_reg[2]\(2),
      O => \cmd_pipe_plus.mc_bank_reg[5]\(2)
    );
\cmd_pipe_plus.mc_bank[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F77FFFF0F77"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]_0\(2),
      I1 => \^q\(0),
      I2 => \req_bank_r_lcl_reg[2]_1\(2),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \req_bank_r_lcl_reg[2]_2\(2),
      O => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cmd[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => granted_col_r_reg,
      I1 => \^cmd_pipe_plus.mc_odt_reg[0]\,
      O => E(0)
    );
\cmd_pipe_plus.mc_data_offset[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => granted_col_r_reg,
      I1 => \^cmd_pipe_plus.mc_odt_reg[0]\,
      O => \cmd_pipe_plus.mc_data_offset_2_reg[0]\
    );
\cmd_pipe_plus.mc_odt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_aux_out0_reg[1]\,
      I1 => granted_col_r_reg,
      I2 => \^cmd_pipe_plus.mc_odt_reg[0]\,
      O => mc_odt_ns(0)
    );
\col_mux.col_data_buf_addr_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(19),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(14),
      I3 => \^q\(2),
      I4 => \col_mux.col_data_buf_addr_r[4]_i_2_n_0\,
      O => col_data_buf_addr(4)
    );
\col_mux.col_data_buf_addr_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF00B8B8"
    )
        port map (
      I0 => req_data_buf_addr_r(4),
      I1 => \^q\(0),
      I2 => \col_mux.col_data_buf_addr_r\(0),
      I3 => req_data_buf_addr_r(9),
      I4 => \^q\(1),
      O => \col_mux.col_data_buf_addr_r[4]_i_2_n_0\
    );
\col_mux.col_periodic_rd_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFC500C5"
    )
        port map (
      I0 => \col_mux.col_periodic_rd_r_i_2_n_0\,
      I1 => req_periodic_rd_r(2),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => req_periodic_rd_r(3),
      O => DIC(0)
    );
\col_mux.col_periodic_rd_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1D3F1D3F1D0C1D3F"
    )
        port map (
      I0 => req_periodic_rd_r(0),
      I1 => \^q\(1),
      I2 => req_periodic_rd_r(1),
      I3 => \^q\(0),
      I4 => \col_mux.col_periodic_rd_r\,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \col_mux.col_periodic_rd_r_i_2_n_0\
    );
\col_mux.col_rd_wr_r_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_odt_reg[0]\,
      O => col_rd_wr
    );
demand_priority_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => req_bank_rdy_r,
      I1 => \^q\(0),
      I2 => granted_col_r_reg,
      O => demand_priority_r_reg
    );
\demand_priority_r_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => req_bank_rdy_r_9,
      I1 => \^q\(1),
      I2 => granted_col_r_reg,
      O => demand_priority_r_reg_0
    );
\demand_priority_r_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => req_bank_rdy_r_10,
      I1 => \^q\(2),
      I2 => granted_col_r_reg,
      O => demand_priority_r_reg_1
    );
\demand_priority_r_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => req_bank_rdy_r_11,
      I1 => \^q\(3),
      I2 => granted_col_r_reg,
      O => demand_priority_r_reg_2
    );
\grant_r[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44004404"
    )
        port map (
      I0 => \grant_r[2]_i_3_n_0\,
      I1 => rd_wr_r_lcl_reg,
      I2 => \^d\(0),
      I3 => rd_wr_r_lcl_reg_0,
      I4 => \last_master_r[1]_i_1_n_0\,
      O => \grant_r[0]_i_1__0_n_0\
    );
\grant_r[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => rnk_config_valid_r_lcl_reg,
      I1 => \^q\(1),
      I2 => ofs_rdy_r_4,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => \grant_r_reg[1]_0\
    );
\grant_r[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => rnk_config_valid_r_lcl_reg,
      I1 => \^q\(0),
      I2 => ofs_rdy_r_5,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => \grant_r_reg[0]_0\
    );
\grant_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0005000000450045"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_1,
      I1 => \grant_r[2]_i_2__0_n_0\,
      I2 => rd_wr_r_lcl_reg,
      I3 => \grant_r[1]_i_4_n_0\,
      I4 => rd_wr_r_lcl_reg_0,
      I5 => \last_master_r[1]_i_1_n_0\,
      O => \grant_r[1]_i_1__0_n_0\
    );
\grant_r[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004540"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^q\(2),
      I2 => granted_col_r_reg,
      I3 => last_master_r(2),
      I4 => rd_wr_r_lcl_reg_4,
      O => \grant_r[1]_i_4_n_0\
    );
\grant_r[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_2,
      I1 => \grant_r[2]_i_2__0_n_0\,
      I2 => rd_wr_r_lcl_reg_3,
      I3 => \grant_r[2]_i_3_n_0\,
      O => \grant_r[2]_i_1__0_n_0\
    );
\grant_r[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000005000533"
    )
        port map (
      I0 => \^q\(2),
      I1 => last_master_r(2),
      I2 => \^q\(3),
      I3 => granted_col_r_reg,
      I4 => last_master_r(3),
      I5 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \grant_r[2]_i_2__0_n_0\
    );
\grant_r[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_1,
      I1 => \^d\(0),
      I2 => rd_wr_r_lcl_reg_4,
      I3 => \last_master_r[2]_i_1_n_0\,
      O => \grant_r[2]_i_3_n_0\
    );
\grant_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000007000707"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_2,
      I1 => \^d\(1),
      I2 => rd_wr_r_lcl_reg_4,
      I3 => \grant_r_reg[1]_1\,
      I4 => rd_wr_r_lcl_reg_3,
      I5 => \grant_r[3]_i_5_n_0\,
      O => \grant_r[3]_i_1_n_0\
    );
\grant_r[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => rnk_config_valid_r_lcl_reg,
      I1 => \^q\(3),
      I2 => ofs_rdy_r_3,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => \grant_r_reg[3]_1\
    );
\grant_r[3]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
        port map (
      I0 => rnk_config_valid_r_lcl_reg,
      I1 => \^q\(2),
      I2 => ofs_rdy_r,
      I3 => \genblk3[1].rnk_config_strobe_r_reg\,
      I4 => \genblk3[2].rnk_config_strobe_r_reg\,
      I5 => rnk_config_strobe,
      O => \grant_r_reg[2]_0\
    );
\grant_r[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004540"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \^q\(0),
      I2 => granted_col_r_reg,
      I3 => last_master_r(0),
      I4 => rd_wr_r_lcl_reg_1,
      O => \grant_r[3]_i_5_n_0\
    );
\grant_r[3]_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FB"
    )
        port map (
      I0 => \^wtr_timer.wtr_cnt_r_reg[0]\,
      I1 => \^wtr_timer.wtr_cnt_r_reg[0]_0\,
      I2 => \wtr_timer.wtr_cnt_r_reg[1]\(0),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \grant_r_reg[3]_2\
    );
\grant_r[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CACFCAC0"
    )
        port map (
      I0 => rd_wr_r(0),
      I1 => rd_wr_r(1),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => \i___19_i_2_n_0\,
      I5 => \rstdiv0_sync_r1_reg_rep__21\,
      O => \grant_r_reg[3]_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1__0_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[1]_i_1__0_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[3]_i_1_n_0\,
      Q => \^q\(3),
      R => '0'
    );
\i___19_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE0EF202"
    )
        port map (
      I0 => \i___19_i_2_n_0\,
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => rd_wr_r(1),
      I4 => rd_wr_r(0),
      O => \^cmd_pipe_plus.mc_we_n_reg[1]\
    );
\i___19_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CAC0"
    )
        port map (
      I0 => rd_wr_r_lcl_reg_5,
      I1 => rd_wr_r_lcl_reg_6,
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \i___19_i_2_n_0\
    );
\i___20_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFEFFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => col_rd_wr_r,
      I5 => \^cmd_pipe_plus.mc_we_n_reg[1]\,
      O => \^cmd_pipe_plus.mc_odt_reg[0]\
    );
\i___67_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => wr_this_rank_r(1),
      I1 => \^q\(1),
      I2 => wr_this_rank_r(2),
      I3 => \^q\(2),
      O => \^wtr_timer.wtr_cnt_r_reg[0]_0\
    );
\i___67_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => wr_this_rank_r(0),
      I1 => \^q\(0),
      I2 => wr_this_rank_r(3),
      I3 => \^q\(3),
      O => \^wtr_timer.wtr_cnt_r_reg[0]\
    );
\i___8_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA888A888A888"
    )
        port map (
      I0 => \periodic_rd_generation.read_this_rank_r\,
      I1 => \periodic_rd_generation.read_this_rank_r_i_2_n_0\,
      I2 => rd_this_rank_r(1),
      I3 => \^q\(1),
      I4 => rd_this_rank_r(2),
      I5 => \^q\(2),
      O => \periodic_rd_generation.int_read_this_rank\
    );
\last_master_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(0),
      I1 => granted_col_r_reg,
      I2 => \^q\(0),
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \^d\(0)
    );
\last_master_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \^last_master_r_reg[1]_0\(0),
      I1 => granted_col_r_reg,
      I2 => \^q\(1),
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \last_master_r[1]_i_1_n_0\
    );
\last_master_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(2),
      I1 => granted_col_r_reg,
      I2 => \^q\(2),
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \last_master_r[2]_i_1_n_0\
    );
\last_master_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => last_master_r(3),
      I2 => granted_col_r_reg,
      I3 => \^q\(3),
      O => \^d\(1)
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^d\(0),
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1_n_0\,
      Q => \^last_master_r_reg[1]_0\(0),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^d\(1),
      Q => last_master_r(3),
      R => '0'
    );
\periodic_rd_generation.read_this_rank_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \periodic_rd_generation.read_this_rank_r_i_2_n_0\,
      I1 => rd_this_rank_r(1),
      I2 => \^q\(1),
      I3 => rd_this_rank_r(2),
      I4 => \^q\(2),
      O => \periodic_rd_generation.read_this_rank\
    );
\periodic_rd_generation.read_this_rank_r_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => rd_this_rank_r(3),
      I1 => \^q\(3),
      I2 => rd_this_rank_r(0),
      I3 => \^q\(0),
      O => \periodic_rd_generation.read_this_rank_r_i_2_n_0\
    );
\read_fifo.fifo_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(18),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(13),
      I3 => \^q\(2),
      I4 => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\,
      O => col_data_buf_addr(3)
    );
\read_fifo.fifo_ram[0].RAM32M0_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(5),
      I1 => \^q\(1),
      I2 => req_data_buf_addr_r(0),
      I3 => \^q\(0),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(0),
      O => \read_fifo.fifo_ram[0].RAM32M0_i_10_n_0\
    );
\read_fifo.fifo_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(17),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(12),
      I3 => \^q\(2),
      I4 => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\,
      O => col_data_buf_addr(2)
    );
\read_fifo.fifo_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(16),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(11),
      I3 => \^q\(2),
      I4 => \read_fifo.fifo_ram[0].RAM32M0_i_9_n_0\,
      O => col_data_buf_addr(1)
    );
\read_fifo.fifo_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(15),
      I1 => \^q\(3),
      I2 => req_data_buf_addr_r(10),
      I3 => \^q\(2),
      I4 => \read_fifo.fifo_ram[0].RAM32M0_i_10_n_0\,
      O => col_data_buf_addr(0)
    );
\read_fifo.fifo_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => req_data_buf_addr_r(8),
      I1 => \^q\(1),
      I2 => req_data_buf_addr_r(3),
      I3 => \^q\(0),
      I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3),
      O => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\
    );
\read_fifo.fifo_ram[0].RAM32M0_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF00B8B8"
    )
        port map (
      I0 => req_data_buf_addr_r(2),
      I1 => \^q\(0),
      I2 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(2),
      I3 => req_data_buf_addr_r(7),
      I4 => \^q\(1),
      O => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\
    );
\read_fifo.fifo_ram[0].RAM32M0_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF00B8B8"
    )
        port map (
      I0 => req_data_buf_addr_r(1),
      I1 => \^q\(0),
      I2 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(1),
      I3 => req_data_buf_addr_r(6),
      I4 => \^q\(1),
      O => \read_fifo.fifo_ram[0].RAM32M0_i_9_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_3\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \last_master_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[7]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[6]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[40]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[39]\ : out STD_LOGIC;
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address_reg[36]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[35]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[34]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[32]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[30]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[29]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[28]\ : out STD_LOGIC;
    \last_master_r_reg[3]_1\ : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    req_row_r : in STD_LOGIC_VECTOR ( 29 downto 0 );
    \req_row_r_lcl_reg[13]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_3\ : entity is "mig_7series_v2_3_round_robin_arb";
end \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_3\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_3\ is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[28]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[29]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[30]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[31]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[32]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[33]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[34]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[35]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[36]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[37]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[39]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[40]_i_3_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[41]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[6]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[7]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[8]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_3__0_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \last_master_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \^last_master_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[28]_i_1\ : label is "soft_lutpair968";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[29]_i_1\ : label is "soft_lutpair968";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[30]_i_1\ : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[32]_i_1\ : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[34]_i_1\ : label is "soft_lutpair966";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[35]_i_1\ : label is "soft_lutpair963";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[36]_i_1\ : label is "soft_lutpair964";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[39]_i_1\ : label is "soft_lutpair966";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[40]_i_2\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_bank[6]_i_1\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_bank[7]_i_1\ : label is "soft_lutpair964";
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_bank[8]_i_1\ : label is "soft_lutpair963";
begin
  D(0) <= \^d\(0);
  Q(3 downto 0) <= \^q\(3 downto 0);
  \last_master_r_reg[3]_0\(0) <= \^last_master_r_reg[3]_0\(0);
\cmd_pipe_plus.mc_address[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(19),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[28]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[28]\
    );
\cmd_pipe_plus.mc_address[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(8),
      I1 => \^q\(2),
      I2 => req_row_r(0),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(0),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[28]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(20),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[29]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[29]\
    );
\cmd_pipe_plus.mc_address[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(9),
      I1 => \^q\(2),
      I2 => req_row_r(1),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(1),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[29]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(21),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[30]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[30]\
    );
\cmd_pipe_plus.mc_address[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(10),
      I1 => \^q\(2),
      I2 => req_row_r(2),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(2),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[30]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFB3B3B3BFBFBFBF"
    )
        port map (
      I0 => req_row_r(22),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => req_row_r(11),
      I5 => \cmd_pipe_plus.mc_address[31]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[41]\(0)
    );
\cmd_pipe_plus.mc_address[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABFFFBF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \req_row_r_lcl_reg[13]\(3),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]_0\(0),
      O => \cmd_pipe_plus.mc_address[31]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(23),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[32]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[32]\
    );
\cmd_pipe_plus.mc_address[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(12),
      I1 => \^q\(2),
      I2 => \req_row_r_lcl_reg[13]_0\(1),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(4),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[32]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFB3B3B3BFBFBFBF"
    )
        port map (
      I0 => req_row_r(24),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => req_row_r(13),
      I5 => \cmd_pipe_plus.mc_address[33]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[41]\(1)
    );
\cmd_pipe_plus.mc_address[33]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABFFFBF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \req_row_r_lcl_reg[13]\(5),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]_0\(2),
      O => \cmd_pipe_plus.mc_address[33]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(25),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[34]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[34]\
    );
\cmd_pipe_plus.mc_address[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(14),
      I1 => \^q\(2),
      I2 => req_row_r(3),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(6),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[34]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(26),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[35]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[35]\
    );
\cmd_pipe_plus.mc_address[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(15),
      I1 => \^q\(2),
      I2 => req_row_r(4),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(7),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[35]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(27),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[36]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[36]\
    );
\cmd_pipe_plus.mc_address[36]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(16),
      I1 => \^q\(2),
      I2 => req_row_r(5),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(8),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[36]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFB3B3B3BFBFBFBF"
    )
        port map (
      I0 => req_row_r(28),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => req_row_r(17),
      I5 => \cmd_pipe_plus.mc_address[37]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[41]\(2)
    );
\cmd_pipe_plus.mc_address[37]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABFFFBF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \req_row_r_lcl_reg[13]\(9),
      I3 => \^q\(1),
      I4 => req_row_r(6),
      O => \cmd_pipe_plus.mc_address[37]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => req_row_r(29),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[39]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[39]\
    );
\cmd_pipe_plus.mc_address[39]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => req_row_r(18),
      I1 => \^q\(2),
      I2 => req_row_r(7),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(10),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[39]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[40]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \req_row_r_lcl_reg[13]_0\(7),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_address[40]_i_3_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[40]\
    );
\cmd_pipe_plus.mc_address[40]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \req_row_r_lcl_reg[13]_0\(5),
      I1 => \^q\(2),
      I2 => \req_row_r_lcl_reg[13]_0\(3),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]\(11),
      I5 => \^q\(0),
      O => \cmd_pipe_plus.mc_address[40]_i_3_n_0\
    );
\cmd_pipe_plus.mc_address[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFB3B3B3BFBFBFBF"
    )
        port map (
      I0 => \req_row_r_lcl_reg[13]_0\(8),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => \req_row_r_lcl_reg[13]_0\(6),
      I5 => \cmd_pipe_plus.mc_address[41]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_address_reg[41]\(3)
    );
\cmd_pipe_plus.mc_address[41]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABFFFBF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \req_row_r_lcl_reg[13]\(12),
      I3 => \^q\(1),
      I4 => \req_row_r_lcl_reg[13]_0\(4),
      O => \cmd_pipe_plus.mc_address[41]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]\(0),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_bank_reg[6]\
    );
\cmd_pipe_plus.mc_bank[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]_0\(0),
      I1 => \^q\(2),
      I2 => \req_bank_r_lcl_reg[2]_1\(0),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \req_bank_r_lcl_reg[2]_2\(0),
      O => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]\(1),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_bank_reg[7]\
    );
\cmd_pipe_plus.mc_bank[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]_0\(1),
      I1 => \^q\(2),
      I2 => \req_bank_r_lcl_reg[2]_1\(1),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \req_bank_r_lcl_reg[2]_2\(1),
      O => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]\(2),
      I1 => \^q\(3),
      I2 => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\,
      O => \cmd_pipe_plus.mc_bank_reg[8]\
    );
\cmd_pipe_plus.mc_bank[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBB888B888B888"
    )
        port map (
      I0 => \req_bank_r_lcl_reg[2]_0\(2),
      I1 => \^q\(2),
      I2 => \req_bank_r_lcl_reg[2]_1\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \req_bank_r_lcl_reg[2]_2\(2),
      O => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cas_n[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => mc_cas_n_ns(0)
    );
\cmd_pipe_plus.mc_we_n[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEBAAAFFFFFFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => act_wait_r_lcl_reg,
      I4 => act_wait_r_lcl_reg_0,
      I5 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      O => \cmd_pipe_plus.mc_we_n_reg[2]\(0)
    );
\cmd_pipe_plus.mc_we_n[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111100000001000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => act_wait_r_lcl_reg_1,
      I4 => \^q\(1),
      I5 => act_wait_r_lcl_reg_2,
      O => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\
    );
\grant_r[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AA000002AA0000"
    )
        port map (
      I0 => \grant_r[1]_i_2__1_n_0\,
      I1 => auto_pre_r_lcl_reg_1,
      I2 => auto_pre_r_lcl_reg_2,
      I3 => \^d\(0),
      I4 => auto_pre_r_lcl_reg,
      I5 => auto_pre_r_lcl_reg_0,
      O => \grant_r[0]_i_1__2_n_0\
    );
\grant_r[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA0000"
    )
        port map (
      I0 => \grant_r[1]_i_2__1_n_0\,
      I1 => \last_master_r_reg[3]_1\,
      I2 => \grant_r[1]_i_3__1_n_0\,
      I3 => auto_pre_r_lcl_reg,
      I4 => auto_pre_r_lcl_reg_0,
      O => \grant_r[1]_i_1__2_n_0\
    );
\grant_r[1]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0737"
    )
        port map (
      I0 => \last_master_r[2]_i_1__1_n_0\,
      I1 => auto_pre_r_lcl_reg_2,
      I2 => \last_master_r[1]_i_1__1_n_0\,
      I3 => auto_pre_r_lcl_reg_1,
      O => \grant_r[1]_i_2__1_n_0\
    );
\grant_r[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F5F0F0F0F5F3F3"
    )
        port map (
      I0 => \^q\(2),
      I1 => last_master_r(2),
      I2 => \rstdiv0_sync_r1_reg_rep__19\,
      I3 => \^q\(1),
      I4 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I5 => last_master_r(1),
      O => \grant_r[1]_i_3__1_n_0\
    );
\grant_r[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0030303000200020"
    )
        port map (
      I0 => \last_master_r_reg[3]_1\,
      I1 => ras_timer_zero_r_reg,
      I2 => auto_pre_r_lcl_reg_1,
      I3 => \last_master_r[2]_i_1__1_n_0\,
      I4 => auto_pre_r_lcl_reg_2,
      I5 => ras_timer_zero_r_reg_0,
      O => \grant_r[2]_i_1__2_n_0\
    );
\grant_r[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575000000000000"
    )
        port map (
      I0 => auto_pre_r_lcl_reg_1,
      I1 => \last_master_r[1]_i_1__1_n_0\,
      I2 => \last_master_r_reg[3]_1\,
      I3 => \^d\(0),
      I4 => \grant_r[3]_i_3__0_n_0\,
      I5 => auto_pre_r_lcl_reg_2,
      O => \grant_r[3]_i_1__1_n_0\
    );
\grant_r[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444545454445"
    )
        port map (
      I0 => ras_timer_zero_r_reg,
      I1 => ras_timer_zero_r_reg_0,
      I2 => \rstdiv0_sync_r1_reg_rep__20\,
      I3 => \^last_master_r_reg[3]_0\(0),
      I4 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I5 => \^q\(3),
      O => \grant_r[3]_i_3__0_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1__2_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => '0'
    );
\last_master_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(0),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^q\(0),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \^d\(0)
    );
\last_master_r[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(1),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^q\(1),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \last_master_r[1]_i_1__1_n_0\
    );
\last_master_r[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(2),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^q\(2),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \last_master_r[2]_i_1__1_n_0\
    );
\last_master_r[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFB8"
    )
        port map (
      I0 => \^q\(3),
      I1 => \pre_4_1_1T_arb.granted_pre_r_reg\,
      I2 => \^last_master_r_reg[3]_0\(0),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \last_master_r[3]_i_1__1_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^d\(0),
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1__1_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1__1_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[3]_i_1__1_n_0\,
      Q => \^last_master_r_reg[3]_0\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_4\ is
  port (
    \cmd_pipe_plus.mc_we_n_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \cmd_pipe_plus.mc_address_reg[11]\ : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    act_this_rank : out STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    insert_maint_r1_lcl_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    granted_row_r_reg : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    granted_row_r_reg_0 : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    granted_row_r_reg_1 : in STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 30 downto 0 );
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_2 : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : in STD_LOGIC;
    head_r_lcl_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_4\ : entity is "mig_7series_v2_3_round_robin_arb";
end \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_4\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_4\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \cmd_pipe_plus.mc_address[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[10]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[11]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[12]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[13]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[3]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[4]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[5]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[6]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[7]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[8]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_address[9]_i_2_n_0\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_address_reg[11]\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[1]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_bank[2]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\ : STD_LOGIC;
  signal \cmd_pipe_plus.mc_we_n[0]_i_3_n_0\ : STD_LOGIC;
  signal \grant_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \grant_r[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \grant_r[3]_i_9__0_n_0\ : STD_LOGIC;
  signal \^grant_r_reg[3]_0\ : STD_LOGIC;
  signal \^grant_r_reg[3]_1\ : STD_LOGIC;
  signal \inhbt_act_faw.SRLC32E0_i_2_n_0\ : STD_LOGIC;
  signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \last_master_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \last_master_r[3]_i_1__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \grant_r[1]_i_3__0\ : label is "soft_lutpair970";
  attribute SOFT_HLUTNM of \grant_r[3]_i_3__1\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \last_master_r[0]_i_1__0\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \last_master_r[2]_i_1__0\ : label is "soft_lutpair970";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \cmd_pipe_plus.mc_address_reg[11]\ <= \^cmd_pipe_plus.mc_address_reg[11]\;
  \grant_r_reg[3]_0\ <= \^grant_r_reg[3]_0\;
  \grant_r_reg[3]_1\ <= \^grant_r_reg[3]_1\;
\cmd_pipe_plus.mc_address[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(0),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[0]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(0)
    );
\cmd_pipe_plus.mc_address[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(0),
      I2 => req_row_r(8),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(20),
      O => \cmd_pipe_plus.mc_address[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF800000FF80FF80"
    )
        port map (
      I0 => \req_row_r_lcl_reg[13]\(10),
      I1 => \^q\(0),
      I2 => act_wait_r_lcl_reg_0,
      I3 => granted_row_r_reg,
      I4 => \cmd_pipe_plus.mc_address[10]_i_2_n_0\,
      I5 => act_wait_r_lcl_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(10)
    );
\cmd_pipe_plus.mc_address[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0800FFFF"
    )
        port map (
      I0 => act_wait_r_lcl_reg_2,
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => req_row_r(18),
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address[10]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(11),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[11]_i_2_n_0\,
      I4 => \^cmd_pipe_plus.mc_address_reg[11]\,
      I5 => req_row_r(7),
      O => \cmd_pipe_plus.mc_address_reg[13]\(11)
    );
\cmd_pipe_plus.mc_address[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F808FFFF"
    )
        port map (
      I0 => req_row_r(19),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => req_row_r(30),
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address[11]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[11]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \^cmd_pipe_plus.mc_address_reg[11]\
    );
\cmd_pipe_plus.mc_address[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(12),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[12]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(12)
    );
\cmd_pipe_plus.mc_address[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_row_r_lcl_reg[13]_0\(3),
      I2 => \req_row_r_lcl_reg[13]_0\(5),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \req_row_r_lcl_reg[13]_0\(7),
      O => \cmd_pipe_plus.mc_address[12]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(13),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[13]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(13)
    );
\cmd_pipe_plus.mc_address[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_row_r_lcl_reg[13]_0\(4),
      I2 => \req_row_r_lcl_reg[13]_0\(6),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \req_row_r_lcl_reg[13]_0\(8),
      O => \cmd_pipe_plus.mc_address[13]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(1),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[1]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(1)
    );
\cmd_pipe_plus.mc_address[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(1),
      I2 => req_row_r(9),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(21),
      O => \cmd_pipe_plus.mc_address[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(2),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[2]_i_2_n_0\,
      I4 => \^cmd_pipe_plus.mc_address_reg[11]\,
      I5 => req_row_r(2),
      O => \cmd_pipe_plus.mc_address_reg[13]\(2)
    );
\cmd_pipe_plus.mc_address[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F808FFFF"
    )
        port map (
      I0 => req_row_r(10),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => req_row_r(22),
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address[2]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(3),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[3]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(3)
    );
\cmd_pipe_plus.mc_address[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_row_r_lcl_reg[13]_0\(0),
      I2 => req_row_r(11),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(23),
      O => \cmd_pipe_plus.mc_address[3]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(4),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[4]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(4)
    );
\cmd_pipe_plus.mc_address[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_row_r_lcl_reg[13]_0\(1),
      I2 => req_row_r(12),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(24),
      O => \cmd_pipe_plus.mc_address[4]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(5),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[5]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(5)
    );
\cmd_pipe_plus.mc_address[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_row_r_lcl_reg[13]_0\(2),
      I2 => req_row_r(13),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(25),
      O => \cmd_pipe_plus.mc_address[5]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(6),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[6]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(6)
    );
\cmd_pipe_plus.mc_address[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(3),
      I2 => req_row_r(14),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(26),
      O => \cmd_pipe_plus.mc_address[6]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(7),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[7]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(7)
    );
\cmd_pipe_plus.mc_address[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(4),
      I2 => req_row_r(15),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(27),
      O => \cmd_pipe_plus.mc_address[7]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(8),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[8]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address_reg[13]\(8)
    );
\cmd_pipe_plus.mc_address[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => req_row_r(5),
      I2 => req_row_r(16),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => req_row_r(28),
      O => \cmd_pipe_plus.mc_address[8]_i_2_n_0\
    );
\cmd_pipe_plus.mc_address[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F8F8F800F800"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_row_r_lcl_reg[13]\(9),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_address[9]_i_2_n_0\,
      I4 => \^cmd_pipe_plus.mc_address_reg[11]\,
      I5 => req_row_r(6),
      O => \cmd_pipe_plus.mc_address_reg[13]\(9)
    );
\cmd_pipe_plus.mc_address[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F808FFFF"
    )
        port map (
      I0 => req_row_r(17),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => req_row_r(29),
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_address[9]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_bank_r_lcl_reg[2]\(0),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_bank_reg[2]\(0)
    );
\cmd_pipe_plus.mc_bank[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_bank_r_lcl_reg[2]_0\(0),
      I2 => \req_bank_r_lcl_reg[2]_1\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \req_bank_r_lcl_reg[2]_2\(0),
      O => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F800F8F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \req_bank_r_lcl_reg[2]\(1),
      I2 => granted_row_r_reg,
      I3 => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_bank_reg[2]\(1)
    );
\cmd_pipe_plus.mc_bank[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_bank_r_lcl_reg[2]_0\(1),
      I2 => \req_bank_r_lcl_reg[2]_1\(1),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \req_bank_r_lcl_reg[2]_2\(1),
      O => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\
    );
\cmd_pipe_plus.mc_bank[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EA00EAEA"
    )
        port map (
      I0 => granted_row_r_reg,
      I1 => \^q\(0),
      I2 => \req_bank_r_lcl_reg[2]\(2),
      I3 => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\,
      I4 => granted_row_r_reg_1,
      O => \cmd_pipe_plus.mc_bank_reg[2]\(2)
    );
\cmd_pipe_plus.mc_bank[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0880000F088"
    )
        port map (
      I0 => \^q\(1),
      I1 => \req_bank_r_lcl_reg[2]_0\(2),
      I2 => \req_bank_r_lcl_reg[2]_1\(2),
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \req_bank_r_lcl_reg[2]_2\(2),
      O => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\
    );
\cmd_pipe_plus.mc_cas_n[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFAFBFAFBFAFAFA"
    )
        port map (
      I0 => granted_row_r_reg,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => \^q\(0),
      I3 => insert_maint_r1_lcl_reg,
      I4 => maint_zq_r,
      I5 => maint_srx_r,
      O => mc_cas_n_ns(0)
    );
\cmd_pipe_plus.mc_ras_n[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000200020002FFFF"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => insert_maint_r1_lcl_reg,
      I5 => granted_row_r_reg_0,
      O => mc_ras_n_ns(0)
    );
\cmd_pipe_plus.mc_ras_n[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10101000"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^q\(0),
      I2 => insert_maint_r1_lcl_reg,
      I3 => maint_zq_r,
      I4 => maint_srx_r,
      O => \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_we_n[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCCCFCCCEE"
    )
        port map (
      I0 => \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\,
      I1 => \cmd_pipe_plus.mc_we_n[0]_i_3_n_0\,
      I2 => act_wait_r_lcl_reg,
      I3 => \^q\(2),
      I4 => \^q\(1),
      I5 => \^q\(3),
      O => \cmd_pipe_plus.mc_we_n_reg[0]\(0)
    );
\cmd_pipe_plus.mc_we_n[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA00AA30"
    )
        port map (
      I0 => act_wait_r_lcl_reg_0,
      I1 => maint_zq_r,
      I2 => insert_maint_r1_lcl_reg,
      I3 => \^q\(0),
      I4 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\
    );
\cmd_pipe_plus.mc_we_n[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F088F088F088FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => act_wait_r_lcl_reg_2,
      I2 => act_wait_r_lcl_reg_3,
      I3 => \^q\(3),
      I4 => insert_maint_r1_lcl_reg,
      I5 => granted_row_r_reg_0,
      O => \cmd_pipe_plus.mc_we_n[0]_i_3_n_0\
    );
\grant_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => \grant_r[3]_i_5__0_n_0\,
      I1 => wait_for_maint_r_lcl_reg_2,
      I2 => act_wait_r_lcl_reg_4,
      I3 => \grant_r[2]_i_3__1_n_0\,
      O => \grant_r[0]_i_1__1_n_0\
    );
\grant_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0005000000450045"
    )
        port map (
      I0 => wait_for_maint_r_lcl_reg_1,
      I1 => \grant_r[2]_i_2__1_n_0\,
      I2 => act_wait_r_lcl_reg_4,
      I3 => \grant_r[1]_i_3__0_n_0\,
      I4 => wait_for_maint_r_lcl_reg_2,
      I5 => \last_master_r[1]_i_1__0_n_0\,
      O => \grant_r[1]_i_1__1_n_0\
    );
\grant_r[1]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004540"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^q\(2),
      I2 => granted_row_r_reg_0,
      I3 => last_master_r(2),
      I4 => \^grant_r_reg[3]_0\,
      O => \grant_r[1]_i_3__0_n_0\
    );
\grant_r[1]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFEFE"
    )
        port map (
      I0 => \^q\(1),
      I1 => inhbt_act_faw_r,
      I2 => \generate_maint_cmds.insert_maint_r_lcl_reg\,
      I3 => act_wait_r_lcl_reg_2,
      I4 => \^q\(2),
      I5 => \grant_r[3]_i_9__0_n_0\,
      O => \grant_r_reg[1]_0\
    );
\grant_r[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \grant_r[2]_i_2__1_n_0\,
      I1 => wait_for_maint_r_lcl_reg,
      I2 => \grant_r[2]_i_3__1_n_0\,
      I3 => wait_for_maint_r_lcl_reg_0,
      O => \grant_r[2]_i_1__1_n_0\
    );
\grant_r[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000005000533"
    )
        port map (
      I0 => \^q\(2),
      I1 => last_master_r(2),
      I2 => \^q\(3),
      I3 => granted_row_r_reg_0,
      I4 => last_master_r(3),
      I5 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \grant_r[2]_i_2__1_n_0\
    );
\grant_r[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00005404"
    )
        port map (
      I0 => wait_for_maint_r_lcl_reg_1,
      I1 => last_master_r(0),
      I2 => granted_row_r_reg_0,
      I3 => \^q\(0),
      I4 => \rstdiv0_sync_r1_reg_rep__20\,
      I5 => \grant_r[1]_i_3__0_n_0\,
      O => \grant_r[2]_i_3__1_n_0\
    );
\grant_r[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0202030300000003"
    )
        port map (
      I0 => wait_for_maint_r_lcl_reg,
      I1 => \grant_r[3]_i_3__1_n_0\,
      I2 => \^grant_r_reg[3]_0\,
      I3 => \grant_r[3]_i_5__0_n_0\,
      I4 => \last_master_r[3]_i_1__0_n_0\,
      I5 => wait_for_maint_r_lcl_reg_0,
      O => \grant_r[3]_i_1__0_n_0\
    );
\grant_r[3]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004540"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \^q\(0),
      I2 => granted_row_r_reg_0,
      I3 => last_master_r(0),
      I4 => wait_for_maint_r_lcl_reg_1,
      O => \grant_r[3]_i_3__1_n_0\
    );
\grant_r[3]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
        port map (
      I0 => head_r_lcl_reg,
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => act_wait_r_lcl_reg_0,
      I4 => \^grant_r_reg[3]_1\,
      O => \^grant_r_reg[3]_0\
    );
\grant_r[3]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0A0F0F0F0A0C0C"
    )
        port map (
      I0 => \^q\(0),
      I1 => last_master_r(0),
      I2 => \rstdiv0_sync_r1_reg_rep__20\,
      I3 => \^q\(1),
      I4 => granted_row_r_reg_0,
      I5 => last_master_r(1),
      O => \grant_r[3]_i_5__0_n_0\
    );
\grant_r[3]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFFFE"
    )
        port map (
      I0 => \grant_r[3]_i_9__0_n_0\,
      I1 => \^q\(2),
      I2 => inhbt_act_faw_r,
      I3 => \generate_maint_cmds.insert_maint_r_lcl_reg\,
      I4 => act_wait_r_lcl_reg,
      I5 => \^q\(1),
      O => \grant_r_reg[2]_0\
    );
\grant_r[3]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \^q\(0),
      I1 => act_wait_r_lcl_reg_0,
      I2 => \^q\(3),
      I3 => act_wait_r_lcl_reg_3,
      O => \grant_r[3]_i_9__0_n_0\
    );
\grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\grant_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\grant_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\grant_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \grant_r[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => '0'
    );
\i___59_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF8FFF8FFF8"
    )
        port map (
      I0 => \^q\(1),
      I1 => act_wait_r_lcl_reg,
      I2 => \generate_maint_cmds.insert_maint_r_lcl_reg\,
      I3 => inhbt_act_faw_r,
      I4 => act_wait_r_lcl_reg_2,
      I5 => \^q\(2),
      O => \^grant_r_reg[3]_1\
    );
\inhbt_act_faw.SRLC32E0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \^q\(2),
      I1 => act_this_rank_r(2),
      I2 => \^q\(1),
      I3 => act_this_rank_r(1),
      I4 => \inhbt_act_faw.SRLC32E0_i_2_n_0\,
      O => act_this_rank
    );
\inhbt_act_faw.SRLC32E0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => act_this_rank_r(0),
      I1 => \^q\(0),
      I2 => act_this_rank_r(3),
      I3 => \^q\(3),
      O => \inhbt_act_faw.SRLC32E0_i_2_n_0\
    );
\last_master_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(0),
      I1 => granted_row_r_reg_0,
      I2 => \^q\(0),
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \last_master_r[0]_i_1__0_n_0\
    );
\last_master_r[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(1),
      I1 => granted_row_r_reg_0,
      I2 => \^q\(1),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      O => \last_master_r[1]_i_1__0_n_0\
    );
\last_master_r[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => last_master_r(2),
      I1 => granted_row_r_reg_0,
      I2 => \^q\(2),
      I3 => \rstdiv0_sync_r1_reg_rep__20\,
      O => \last_master_r[2]_i_1__0_n_0\
    );
\last_master_r[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => last_master_r(3),
      I2 => granted_row_r_reg_0,
      I3 => \^q\(3),
      O => \last_master_r[3]_i_1__0_n_0\
    );
\last_master_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[0]_i_1__0_n_0\,
      Q => last_master_r(0),
      R => '0'
    );
\last_master_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[1]_i_1__0_n_0\,
      Q => last_master_r(1),
      R => '0'
    );
\last_master_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[2]_i_1__0_n_0\,
      Q => last_master_r(2),
      R => '0'
    );
\last_master_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \last_master_r[3]_i_1__0_n_0\,
      Q => last_master_r(3),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_tempmon is
  port (
    D : out STD_LOGIC_VECTOR ( 11 downto 0 );
    clk_ref_i : in STD_LOGIC;
    in0 : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_tempmon : entity is "mig_7series_v2_3_tempmon";
end mig_7series_0_mig_7series_v2_3_tempmon;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_tempmon is
  signal \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\ : signal is "yes";
  signal \device_temp_101[11]_i_4_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_5_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_6_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_7_n_0\ : STD_LOGIC;
  signal \device_temp_101[11]_i_8_n_0\ : STD_LOGIC;
  signal device_temp_lcl : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal device_temp_r : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg : string;
  attribute async_reg of device_temp_r : signal is "true";
  signal \device_temp_r[11]_i_1_n_0\ : STD_LOGIC;
  signal device_temp_sync_r1 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r1 : signal is "true";
  signal device_temp_sync_r2 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r2 : signal is "true";
  signal device_temp_sync_r3 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r3 : signal is "true";
  attribute syn_srlstyle : string;
  attribute syn_srlstyle of device_temp_sync_r3 : signal is "registers";
  signal device_temp_sync_r4 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r4 : signal is "true";
  signal device_temp_sync_r4_neq_r3 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_2_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_3_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_4_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_i_5_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_0 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_1 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_2 : STD_LOGIC;
  signal device_temp_sync_r4_neq_r3_reg_i_1_n_3 : STD_LOGIC;
  signal device_temp_sync_r5 : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute async_reg of device_temp_sync_r5 : signal is "true";
  signal p_0_in : STD_LOGIC_VECTOR ( 10 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sync_cntr0 : STD_LOGIC;
  signal \sync_cntr[2]_i_1_n_0\ : STD_LOGIC;
  signal \sync_cntr[3]_i_2_n_0\ : STD_LOGIC;
  signal \sync_cntr_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\ : STD_LOGIC;
  signal \xadc_supplied_temperature.rst_r1\ : STD_LOGIC;
  attribute async_reg of \xadc_supplied_temperature.rst_r1\ : signal is "true";
  signal \xadc_supplied_temperature.rst_r2\ : STD_LOGIC;
  attribute async_reg of \xadc_supplied_temperature.rst_r2\ : signal is "true";
  signal \xadc_supplied_temperature.sample_en\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_en_i_1_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_en_i_2_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer[0]_i_1_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_clr_i_1_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_en\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_en_i_1_n_0\ : STD_LOGIC;
  signal \xadc_supplied_temperature.sample_timer_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \xadc_supplied_temperature.temperature\ : STD_LOGIC;
  attribute RTL_KEEP of \xadc_supplied_temperature.temperature\ : signal is "yes";
  signal \xadc_supplied_temperature.xadc_den\ : STD_LOGIC;
  signal \xadc_supplied_temperature.xadc_do\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \xadc_supplied_temperature.xadc_do_r\ : STD_LOGIC_VECTOR ( 15 downto 4 );
  signal \xadc_supplied_temperature.xadc_drdy\ : STD_LOGIC;
  signal \xadc_supplied_temperature.xadc_drdy_r\ : STD_LOGIC;
  signal NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:0010,WAIT_FOR_READ:0100,READ:1000";
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:0010,WAIT_FOR_READ:0100,READ:1000";
  attribute KEEP of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:0010,WAIT_FOR_READ:0100,READ:1000";
  attribute KEEP of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3]\ : label is "INIT_IDLE:0001,REQUEST_READ_TEMP:0010,WAIT_FOR_READ:0100,READ:1000";
  attribute KEEP of \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \device_temp_r_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_r_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_r_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r1_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r2_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[0]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[0]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[10]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[10]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[11]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[11]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[1]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[1]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[2]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[2]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[3]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[3]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[4]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[4]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[5]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[5]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[6]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[6]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[7]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[7]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[8]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[8]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r3_reg[9]\ : label is "yes";
  attribute syn_srlstyle of \device_temp_sync_r3_reg[9]\ : label is "registers";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r4_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[10]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[11]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[1]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[2]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[3]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[4]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[5]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[6]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[7]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[8]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[9]\ : label is std.standard.true;
  attribute KEEP of \device_temp_sync_r5_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \sync_cntr[0]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \sync_cntr[1]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \sync_cntr[2]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \sync_cntr[3]_i_3\ : label is "soft_lutpair2";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \xadc_supplied_temperature.XADC_inst\ : label is "PRIMITIVE";
  attribute ASYNC_REG_boolean of \xadc_supplied_temperature.rst_r1_reg\ : label is std.standard.true;
  attribute KEEP of \xadc_supplied_temperature.rst_r1_reg\ : label is "yes";
  attribute ASYNC_REG_boolean of \xadc_supplied_temperature.rst_r2_reg\ : label is std.standard.true;
  attribute KEEP of \xadc_supplied_temperature.rst_r2_reg\ : label is "yes";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[1]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[2]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[4]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[6]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[7]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[8]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \xadc_supplied_temperature.sample_timer[9]_i_1\ : label is "soft_lutpair1";
begin
\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEEEFEEEFEEE"
    )
        port map (
      I0 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1]\,
      I1 => \xadc_supplied_temperature.temperature\,
      I2 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      I3 => \xadc_supplied_temperature.sample_en\,
      I4 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      I5 => \xadc_supplied_temperature.xadc_drdy_r\,
      O => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \xadc_supplied_temperature.temperature\,
      Q => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      S => \xadc_supplied_temperature.rst_r2\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      Q => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1]\,
      R => \xadc_supplied_temperature.rst_r2\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1]\,
      Q => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      R => \xadc_supplied_temperature.rst_r2\
    );
\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0\,
      D => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      Q => \xadc_supplied_temperature.temperature\,
      R => \xadc_supplied_temperature.rst_r2\
    );
\device_temp_101[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(0),
      O => D(0)
    );
\device_temp_101[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(10),
      O => D(10)
    );
\device_temp_101[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I2 => device_temp_r(11),
      O => D(11)
    );
\device_temp_101[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011111115"
    )
        port map (
      I0 => \device_temp_101[11]_i_4_n_0\,
      I1 => device_temp_r(11),
      I2 => device_temp_r(8),
      I3 => device_temp_r(10),
      I4 => device_temp_r(9),
      I5 => \device_temp_101[11]_i_5_n_0\,
      O => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\
    );
\device_temp_101[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FD55"
    )
        port map (
      I0 => \device_temp_101[11]_i_6_n_0\,
      I1 => device_temp_r(1),
      I2 => device_temp_r(0),
      I3 => device_temp_r(2),
      I4 => \device_temp_101[11]_i_7_n_0\,
      O => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\
    );
\device_temp_101[11]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => device_temp_r(4),
      I1 => device_temp_r(11),
      I2 => device_temp_r(7),
      I3 => device_temp_r(5),
      O => \device_temp_101[11]_i_4_n_0\
    );
\device_temp_101[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E000A000A000A000"
    )
        port map (
      I0 => device_temp_r(6),
      I1 => device_temp_r(5),
      I2 => device_temp_r(7),
      I3 => device_temp_r(11),
      I4 => device_temp_r(2),
      I5 => device_temp_r(3),
      O => \device_temp_101[11]_i_5_n_0\
    );
\device_temp_101[11]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => device_temp_r(6),
      I1 => device_temp_r(9),
      I2 => device_temp_r(8),
      I3 => device_temp_r(4),
      I4 => device_temp_r(3),
      O => \device_temp_101[11]_i_6_n_0\
    );
\device_temp_101[11]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F777F777F77FF77"
    )
        port map (
      I0 => device_temp_r(11),
      I1 => device_temp_r(10),
      I2 => device_temp_r(7),
      I3 => \device_temp_101[11]_i_8_n_0\,
      I4 => device_temp_r(6),
      I5 => device_temp_r(5),
      O => \device_temp_101[11]_i_7_n_0\
    );
\device_temp_101[11]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => device_temp_r(9),
      I1 => device_temp_r(8),
      O => \device_temp_101[11]_i_8_n_0\
    );
\device_temp_101[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(1),
      O => D(1)
    );
\device_temp_101[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I2 => device_temp_r(2),
      O => D(2)
    );
\device_temp_101[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DC"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(3),
      O => D(3)
    );
\device_temp_101[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(4),
      O => D(4)
    );
\device_temp_101[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I2 => device_temp_r(5),
      O => D(5)
    );
\device_temp_101[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(6),
      O => D(6)
    );
\device_temp_101[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I2 => device_temp_r(7),
      O => D(7)
    );
\device_temp_101[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(8),
      O => D(8)
    );
\device_temp_101[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high\,
      I1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\,
      I2 => device_temp_r(9),
      O => D(9)
    );
\device_temp_r[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \sync_cntr_reg__0\(1),
      I1 => \sync_cntr_reg__0\(0),
      I2 => \sync_cntr_reg__0\(2),
      I3 => \sync_cntr_reg__0\(3),
      O => \device_temp_r[11]_i_1_n_0\
    );
\device_temp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(0),
      Q => device_temp_r(0),
      R => '0'
    );
\device_temp_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(10),
      Q => device_temp_r(10),
      R => '0'
    );
\device_temp_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(11),
      Q => device_temp_r(11),
      R => '0'
    );
\device_temp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(1),
      Q => device_temp_r(1),
      R => '0'
    );
\device_temp_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(2),
      Q => device_temp_r(2),
      R => '0'
    );
\device_temp_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(3),
      Q => device_temp_r(3),
      R => '0'
    );
\device_temp_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(4),
      Q => device_temp_r(4),
      R => '0'
    );
\device_temp_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(5),
      Q => device_temp_r(5),
      R => '0'
    );
\device_temp_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(6),
      Q => device_temp_r(6),
      R => '0'
    );
\device_temp_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(7),
      Q => device_temp_r(7),
      R => '0'
    );
\device_temp_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(8),
      Q => device_temp_r(8),
      R => '0'
    );
\device_temp_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \device_temp_r[11]_i_1_n_0\,
      D => device_temp_sync_r5(9),
      Q => device_temp_r(9),
      R => '0'
    );
\device_temp_sync_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(0),
      Q => device_temp_sync_r1(0),
      R => '0'
    );
\device_temp_sync_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(10),
      Q => device_temp_sync_r1(10),
      R => '0'
    );
\device_temp_sync_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(11),
      Q => device_temp_sync_r1(11),
      R => '0'
    );
\device_temp_sync_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(1),
      Q => device_temp_sync_r1(1),
      R => '0'
    );
\device_temp_sync_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(2),
      Q => device_temp_sync_r1(2),
      R => '0'
    );
\device_temp_sync_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(3),
      Q => device_temp_sync_r1(3),
      R => '0'
    );
\device_temp_sync_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(4),
      Q => device_temp_sync_r1(4),
      R => '0'
    );
\device_temp_sync_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(5),
      Q => device_temp_sync_r1(5),
      R => '0'
    );
\device_temp_sync_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(6),
      Q => device_temp_sync_r1(6),
      R => '0'
    );
\device_temp_sync_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(7),
      Q => device_temp_sync_r1(7),
      R => '0'
    );
\device_temp_sync_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(8),
      Q => device_temp_sync_r1(8),
      R => '0'
    );
\device_temp_sync_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_lcl(9),
      Q => device_temp_sync_r1(9),
      R => '0'
    );
\device_temp_sync_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(0),
      Q => device_temp_sync_r2(0),
      R => '0'
    );
\device_temp_sync_r2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(10),
      Q => device_temp_sync_r2(10),
      R => '0'
    );
\device_temp_sync_r2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(11),
      Q => device_temp_sync_r2(11),
      R => '0'
    );
\device_temp_sync_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(1),
      Q => device_temp_sync_r2(1),
      R => '0'
    );
\device_temp_sync_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(2),
      Q => device_temp_sync_r2(2),
      R => '0'
    );
\device_temp_sync_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(3),
      Q => device_temp_sync_r2(3),
      R => '0'
    );
\device_temp_sync_r2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(4),
      Q => device_temp_sync_r2(4),
      R => '0'
    );
\device_temp_sync_r2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(5),
      Q => device_temp_sync_r2(5),
      R => '0'
    );
\device_temp_sync_r2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(6),
      Q => device_temp_sync_r2(6),
      R => '0'
    );
\device_temp_sync_r2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(7),
      Q => device_temp_sync_r2(7),
      R => '0'
    );
\device_temp_sync_r2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(8),
      Q => device_temp_sync_r2(8),
      R => '0'
    );
\device_temp_sync_r2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r1(9),
      Q => device_temp_sync_r2(9),
      R => '0'
    );
\device_temp_sync_r3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(0),
      Q => device_temp_sync_r3(0),
      R => '0'
    );
\device_temp_sync_r3_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(10),
      Q => device_temp_sync_r3(10),
      R => '0'
    );
\device_temp_sync_r3_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(11),
      Q => device_temp_sync_r3(11),
      R => '0'
    );
\device_temp_sync_r3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(1),
      Q => device_temp_sync_r3(1),
      R => '0'
    );
\device_temp_sync_r3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(2),
      Q => device_temp_sync_r3(2),
      R => '0'
    );
\device_temp_sync_r3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(3),
      Q => device_temp_sync_r3(3),
      R => '0'
    );
\device_temp_sync_r3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(4),
      Q => device_temp_sync_r3(4),
      R => '0'
    );
\device_temp_sync_r3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(5),
      Q => device_temp_sync_r3(5),
      R => '0'
    );
\device_temp_sync_r3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(6),
      Q => device_temp_sync_r3(6),
      R => '0'
    );
\device_temp_sync_r3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(7),
      Q => device_temp_sync_r3(7),
      R => '0'
    );
\device_temp_sync_r3_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(8),
      Q => device_temp_sync_r3(8),
      R => '0'
    );
\device_temp_sync_r3_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r2(9),
      Q => device_temp_sync_r3(9),
      R => '0'
    );
device_temp_sync_r4_neq_r3_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(9),
      I1 => device_temp_sync_r3(9),
      I2 => device_temp_sync_r3(11),
      I3 => device_temp_sync_r4(11),
      I4 => device_temp_sync_r3(10),
      I5 => device_temp_sync_r4(10),
      O => device_temp_sync_r4_neq_r3_i_2_n_0
    );
device_temp_sync_r4_neq_r3_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(6),
      I1 => device_temp_sync_r3(6),
      I2 => device_temp_sync_r3(8),
      I3 => device_temp_sync_r4(8),
      I4 => device_temp_sync_r3(7),
      I5 => device_temp_sync_r4(7),
      O => device_temp_sync_r4_neq_r3_i_3_n_0
    );
device_temp_sync_r4_neq_r3_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(3),
      I1 => device_temp_sync_r3(3),
      I2 => device_temp_sync_r3(5),
      I3 => device_temp_sync_r4(5),
      I4 => device_temp_sync_r3(4),
      I5 => device_temp_sync_r4(4),
      O => device_temp_sync_r4_neq_r3_i_4_n_0
    );
device_temp_sync_r4_neq_r3_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => device_temp_sync_r4(0),
      I1 => device_temp_sync_r3(0),
      I2 => device_temp_sync_r3(2),
      I3 => device_temp_sync_r4(2),
      I4 => device_temp_sync_r3(1),
      I5 => device_temp_sync_r4(1),
      O => device_temp_sync_r4_neq_r3_i_5_n_0
    );
device_temp_sync_r4_neq_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4_neq_r3_reg_i_1_n_0,
      Q => device_temp_sync_r4_neq_r3,
      R => '0'
    );
device_temp_sync_r4_neq_r3_reg_i_1: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => device_temp_sync_r4_neq_r3_reg_i_1_n_0,
      CO(2) => device_temp_sync_r4_neq_r3_reg_i_1_n_1,
      CO(1) => device_temp_sync_r4_neq_r3_reg_i_1_n_2,
      CO(0) => device_temp_sync_r4_neq_r3_reg_i_1_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3 downto 0) => NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED(3 downto 0),
      S(3) => device_temp_sync_r4_neq_r3_i_2_n_0,
      S(2) => device_temp_sync_r4_neq_r3_i_3_n_0,
      S(1) => device_temp_sync_r4_neq_r3_i_4_n_0,
      S(0) => device_temp_sync_r4_neq_r3_i_5_n_0
    );
\device_temp_sync_r4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(0),
      Q => device_temp_sync_r4(0),
      R => '0'
    );
\device_temp_sync_r4_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(10),
      Q => device_temp_sync_r4(10),
      R => '0'
    );
\device_temp_sync_r4_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(11),
      Q => device_temp_sync_r4(11),
      R => '0'
    );
\device_temp_sync_r4_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(1),
      Q => device_temp_sync_r4(1),
      R => '0'
    );
\device_temp_sync_r4_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(2),
      Q => device_temp_sync_r4(2),
      R => '0'
    );
\device_temp_sync_r4_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(3),
      Q => device_temp_sync_r4(3),
      R => '0'
    );
\device_temp_sync_r4_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(4),
      Q => device_temp_sync_r4(4),
      R => '0'
    );
\device_temp_sync_r4_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(5),
      Q => device_temp_sync_r4(5),
      R => '0'
    );
\device_temp_sync_r4_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(6),
      Q => device_temp_sync_r4(6),
      R => '0'
    );
\device_temp_sync_r4_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(7),
      Q => device_temp_sync_r4(7),
      R => '0'
    );
\device_temp_sync_r4_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(8),
      Q => device_temp_sync_r4(8),
      R => '0'
    );
\device_temp_sync_r4_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r3(9),
      Q => device_temp_sync_r4(9),
      R => '0'
    );
\device_temp_sync_r5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(0),
      Q => device_temp_sync_r5(0),
      R => '0'
    );
\device_temp_sync_r5_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(10),
      Q => device_temp_sync_r5(10),
      R => '0'
    );
\device_temp_sync_r5_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(11),
      Q => device_temp_sync_r5(11),
      R => '0'
    );
\device_temp_sync_r5_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(1),
      Q => device_temp_sync_r5(1),
      R => '0'
    );
\device_temp_sync_r5_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(2),
      Q => device_temp_sync_r5(2),
      R => '0'
    );
\device_temp_sync_r5_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(3),
      Q => device_temp_sync_r5(3),
      R => '0'
    );
\device_temp_sync_r5_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(4),
      Q => device_temp_sync_r5(4),
      R => '0'
    );
\device_temp_sync_r5_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(5),
      Q => device_temp_sync_r5(5),
      R => '0'
    );
\device_temp_sync_r5_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(6),
      Q => device_temp_sync_r5(6),
      R => '0'
    );
\device_temp_sync_r5_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(7),
      Q => device_temp_sync_r5(7),
      R => '0'
    );
\device_temp_sync_r5_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(8),
      Q => device_temp_sync_r5(8),
      R => '0'
    );
\device_temp_sync_r5_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => device_temp_sync_r4(9),
      Q => device_temp_sync_r5(9),
      R => '0'
    );
\sync_cntr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \sync_cntr_reg__0\(0),
      O => \p_0_in__0\(0)
    );
\sync_cntr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \sync_cntr_reg__0\(0),
      I1 => \sync_cntr_reg__0\(1),
      O => \p_0_in__0\(1)
    );
\sync_cntr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \sync_cntr_reg__0\(1),
      I1 => \sync_cntr_reg__0\(0),
      I2 => \sync_cntr_reg__0\(2),
      O => \sync_cntr[2]_i_1_n_0\
    );
\sync_cntr[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in0,
      I1 => device_temp_sync_r4_neq_r3,
      O => sync_cntr0
    );
\sync_cntr[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \sync_cntr_reg__0\(3),
      I1 => \sync_cntr_reg__0\(2),
      I2 => \sync_cntr_reg__0\(0),
      I3 => \sync_cntr_reg__0\(1),
      O => \sync_cntr[3]_i_2_n_0\
    );
\sync_cntr[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \sync_cntr_reg__0\(0),
      I1 => \sync_cntr_reg__0\(1),
      I2 => \sync_cntr_reg__0\(2),
      I3 => \sync_cntr_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\sync_cntr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(0),
      Q => \sync_cntr_reg__0\(0),
      R => sync_cntr0
    );
\sync_cntr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(1),
      Q => \sync_cntr_reg__0\(1),
      R => sync_cntr0
    );
\sync_cntr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \sync_cntr[2]_i_1_n_0\,
      Q => \sync_cntr_reg__0\(2),
      R => sync_cntr0
    );
\sync_cntr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \sync_cntr[3]_i_2_n_0\,
      D => \p_0_in__0\(3),
      Q => \sync_cntr_reg__0\(3),
      R => sync_cntr0
    );
\xadc_supplied_temperature.XADC_inst\: unisim.vcomponents.XADC
    generic map(
      INIT_40 => X"1000",
      INIT_41 => X"2FFF",
      INIT_42 => X"0800",
      INIT_43 => X"0000",
      INIT_44 => X"0000",
      INIT_45 => X"0000",
      INIT_46 => X"0000",
      INIT_47 => X"0000",
      INIT_48 => X"0101",
      INIT_49 => X"0000",
      INIT_4A => X"0100",
      INIT_4B => X"0000",
      INIT_4C => X"0000",
      INIT_4D => X"0000",
      INIT_4E => X"0000",
      INIT_4F => X"0000",
      INIT_50 => X"B5ED",
      INIT_51 => X"57E4",
      INIT_52 => X"A147",
      INIT_53 => X"CA33",
      INIT_54 => X"A93A",
      INIT_55 => X"52C6",
      INIT_56 => X"9555",
      INIT_57 => X"AE4E",
      INIT_58 => X"5999",
      INIT_59 => X"0000",
      INIT_5A => X"0000",
      INIT_5B => X"0000",
      INIT_5C => X"5111",
      INIT_5D => X"0000",
      INIT_5E => X"0000",
      INIT_5F => X"0000",
      IS_CONVSTCLK_INVERTED => '0',
      IS_DCLK_INVERTED => '0',
      SIM_DEVICE => "7SERIES",
      SIM_MONITOR_FILE => "design.txt"
    )
        port map (
      ALM(7 downto 0) => \NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED\(7 downto 0),
      BUSY => \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED\,
      CHANNEL(4 downto 0) => \NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED\(4 downto 0),
      CONVST => '0',
      CONVSTCLK => '0',
      DADDR(6 downto 0) => B"0000000",
      DCLK => clk_ref_i,
      DEN => \xadc_supplied_temperature.xadc_den\,
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => \xadc_supplied_temperature.xadc_do\(15 downto 0),
      DRDY => \xadc_supplied_temperature.xadc_drdy\,
      DWE => '0',
      EOC => \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED\,
      EOS => \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED\,
      JTAGBUSY => \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED\,
      JTAGLOCKED => \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED\,
      JTAGMODIFIED => \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED\,
      MUXADDR(4 downto 0) => \NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED\(4 downto 0),
      OT => \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED\,
      RESET => '0',
      VAUXN(15 downto 0) => B"0000000000000000",
      VAUXP(15 downto 0) => B"0000000000000000",
      VN => '0',
      VP => '0'
    );
\xadc_supplied_temperature.rst_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => in0,
      Q => \xadc_supplied_temperature.rst_r1\,
      R => '0'
    );
\xadc_supplied_temperature.rst_r2_reg\: unisim.vcomponents.FDRE
     port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.rst_r1\,
      Q => \xadc_supplied_temperature.rst_r2\,
      R => '0'
    );
\xadc_supplied_temperature.sample_en_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(3),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(4),
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(2),
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      I4 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      I5 => \xadc_supplied_temperature.sample_en_i_2_n_0\,
      O => \xadc_supplied_temperature.sample_en_i_1_n_0\
    );
\xadc_supplied_temperature.sample_en_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(7),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(8),
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(6),
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(5),
      I4 => \xadc_supplied_temperature.sample_timer_reg__0\(10),
      I5 => \xadc_supplied_temperature.sample_timer_reg__0\(9),
      O => \xadc_supplied_temperature.sample_en_i_2_n_0\
    );
\xadc_supplied_temperature.sample_en_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.sample_en_i_1_n_0\,
      Q => \xadc_supplied_temperature.sample_en\,
      R => '0'
    );
\xadc_supplied_temperature.sample_timer[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      O => \xadc_supplied_temperature.sample_timer[0]_i_1_n_0\
    );
\xadc_supplied_temperature.sample_timer[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \xadc_supplied_temperature.rst_r2\,
      I1 => \xadc_supplied_temperature.xadc_den\,
      O => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFF08000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(9),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(7),
      I2 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(6),
      I4 => \xadc_supplied_temperature.sample_timer_reg__0\(8),
      I5 => \xadc_supplied_temperature.sample_timer_reg__0\(10),
      O => p_0_in(10)
    );
\xadc_supplied_temperature.sample_timer[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(4),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(2),
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      I4 => \xadc_supplied_temperature.sample_timer_reg__0\(3),
      I5 => \xadc_supplied_temperature.sample_timer_reg__0\(5),
      O => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\
    );
\xadc_supplied_temperature.sample_timer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      O => p_0_in(1)
    );
\xadc_supplied_temperature.sample_timer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(2),
      O => p_0_in(2)
    );
\xadc_supplied_temperature.sample_timer[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(2),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(3),
      O => p_0_in(3)
    );
\xadc_supplied_temperature.sample_timer[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(3),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(2),
      I4 => \xadc_supplied_temperature.sample_timer_reg__0\(4),
      O => p_0_in(4)
    );
\xadc_supplied_temperature.sample_timer[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(4),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(2),
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      I4 => \xadc_supplied_temperature.sample_timer_reg__0\(3),
      I5 => \xadc_supplied_temperature.sample_timer_reg__0\(5),
      O => p_0_in(5)
    );
\xadc_supplied_temperature.sample_timer[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(6),
      O => p_0_in(6)
    );
\xadc_supplied_temperature.sample_timer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(6),
      I1 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(7),
      O => p_0_in(7)
    );
\xadc_supplied_temperature.sample_timer[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(7),
      I1 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I2 => \xadc_supplied_temperature.sample_timer_reg__0\(6),
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(8),
      O => p_0_in(8)
    );
\xadc_supplied_temperature.sample_timer[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FF0800"
    )
        port map (
      I0 => \xadc_supplied_temperature.sample_timer_reg__0\(8),
      I1 => \xadc_supplied_temperature.sample_timer_reg__0\(6),
      I2 => \xadc_supplied_temperature.sample_timer[10]_i_3_n_0\,
      I3 => \xadc_supplied_temperature.sample_timer_reg__0\(7),
      I4 => \xadc_supplied_temperature.sample_timer_reg__0\(9),
      O => p_0_in(9)
    );
\xadc_supplied_temperature.sample_timer_clr_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1110"
    )
        port map (
      I0 => \xadc_supplied_temperature.rst_r2\,
      I1 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2]\,
      I2 => \xadc_supplied_temperature.xadc_den\,
      I3 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1]\,
      O => \xadc_supplied_temperature.sample_timer_clr_i_1_n_0\
    );
\xadc_supplied_temperature.sample_timer_clr_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.sample_timer_clr_i_1_n_0\,
      Q => \xadc_supplied_temperature.xadc_den\,
      R => '0'
    );
\xadc_supplied_temperature.sample_timer_en_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11111110"
    )
        port map (
      I0 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1]\,
      I1 => \xadc_supplied_temperature.rst_r2\,
      I2 => \xadc_supplied_temperature.sample_timer_en\,
      I3 => \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0]\,
      I4 => \xadc_supplied_temperature.temperature\,
      O => \xadc_supplied_temperature.sample_timer_en_i_1_n_0\
    );
\xadc_supplied_temperature.sample_timer_en_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.sample_timer_en_i_1_n_0\,
      Q => \xadc_supplied_temperature.sample_timer_en\,
      R => '0'
    );
\xadc_supplied_temperature.sample_timer_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => \xadc_supplied_temperature.sample_timer[0]_i_1_n_0\,
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(0),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(10),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(10),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(1),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(1),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(2),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(2),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(3),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(3),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(4),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(4),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(5),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(5),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(6),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(6),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(7),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(7),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(8),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(8),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.sample_timer_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.sample_timer_en\,
      D => p_0_in(9),
      Q => \xadc_supplied_temperature.sample_timer_reg__0\(9),
      R => \xadc_supplied_temperature.sample_timer0\
    );
\xadc_supplied_temperature.temperature_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(4),
      Q => device_temp_lcl(0),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(14),
      Q => device_temp_lcl(10),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(15),
      Q => device_temp_lcl(11),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(5),
      Q => device_temp_lcl(1),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(6),
      Q => device_temp_lcl(2),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(7),
      Q => device_temp_lcl(3),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(8),
      Q => device_temp_lcl(4),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(9),
      Q => device_temp_lcl(5),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(10),
      Q => device_temp_lcl(6),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(11),
      Q => device_temp_lcl(7),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(12),
      Q => device_temp_lcl(8),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.temperature_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => \xadc_supplied_temperature.temperature\,
      D => \xadc_supplied_temperature.xadc_do_r\(13),
      Q => device_temp_lcl(9),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(10),
      Q => \xadc_supplied_temperature.xadc_do_r\(10),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(11),
      Q => \xadc_supplied_temperature.xadc_do_r\(11),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(12),
      Q => \xadc_supplied_temperature.xadc_do_r\(12),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(13),
      Q => \xadc_supplied_temperature.xadc_do_r\(13),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(14),
      Q => \xadc_supplied_temperature.xadc_do_r\(14),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(15),
      Q => \xadc_supplied_temperature.xadc_do_r\(15),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(4),
      Q => \xadc_supplied_temperature.xadc_do_r\(4),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(5),
      Q => \xadc_supplied_temperature.xadc_do_r\(5),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(6),
      Q => \xadc_supplied_temperature.xadc_do_r\(6),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(7),
      Q => \xadc_supplied_temperature.xadc_do_r\(7),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(8),
      Q => \xadc_supplied_temperature.xadc_do_r\(8),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_do_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_do\(9),
      Q => \xadc_supplied_temperature.xadc_do_r\(9),
      R => \xadc_supplied_temperature.rst_r2\
    );
\xadc_supplied_temperature.xadc_drdy_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk_ref_i,
      CE => '1',
      D => \xadc_supplied_temperature.xadc_drdy\,
      Q => \xadc_supplied_temperature.xadc_drdy_r\,
      R => \xadc_supplied_temperature.rst_r2\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ui_cmd is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : out STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[12]\ : out STD_LOGIC;
    row_hit_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 12 downto 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    \req_bank_r_lcl_reg[0]\ : out STD_LOGIC;
    \req_bank_r_lcl_reg[1]\ : out STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    rb_hit_busy_r_reg_1 : out STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[3]\ : out STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wr_req_counter.wr_req_cnt_r_reg[0]_0\ : out STD_LOGIC;
    wr_accepted : out STD_LOGIC;
    \not_strict_mode.occ_cnt_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.occ_cnt_r_reg[3]\ : out STD_LOGIC;
    rd_accepted : out STD_LOGIC;
    use_addr : out STD_LOGIC;
    \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cmd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    app_rdy_ns : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    app_en : in STD_LOGIC;
    reset_reg : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \not_strict_mode.occ_cnt_r\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_valid_copy\ : in STD_LOGIC;
    \not_strict_mode.app_rd_data_end_reg\ : in STD_LOGIC;
    wr_data_buf_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ui_cmd : entity is "mig_7series_v2_3_ui_cmd";
end mig_7series_0_mig_7series_v2_3_ui_cmd;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ui_cmd is
  signal \^d\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal app_addr_r10 : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[0]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[10]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[11]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[12]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[13]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[14]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[15]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[16]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[17]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[18]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[19]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[1]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[20]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[21]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[22]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[23]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[2]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[3]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[4]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[5]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[6]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[7]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[8]\ : STD_LOGIC;
  signal \app_addr_r1_reg_n_0_[9]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[0]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[10]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[11]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[12]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[13]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[14]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[15]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[16]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[17]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[18]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[19]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[1]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[20]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[21]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[22]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[23]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[2]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[3]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[4]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[5]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[6]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[7]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[8]\ : STD_LOGIC;
  signal \app_addr_r2_reg_n_0_[9]\ : STD_LOGIC;
  signal app_cmd_r1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal app_cmd_r2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal app_en_ns1 : STD_LOGIC;
  signal app_en_ns2 : STD_LOGIC;
  signal app_en_r1 : STD_LOGIC;
  signal app_en_r2 : STD_LOGIC;
  signal p_0_in_0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^req_bank_r_lcl_reg[0]\ : STD_LOGIC;
  signal \^req_bank_r_lcl_reg[1]\ : STD_LOGIC;
  signal \^req_bank_r_lcl_reg[2]\ : STD_LOGIC;
  signal \^req_row_r_lcl_reg[12]\ : STD_LOGIC;
  signal \^wr_req_counter.wr_req_cnt_r_reg[0]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of app_en_r1_i_1 : label is "soft_lutpair1030";
  attribute SOFT_HLUTNM of app_en_r2_i_1 : label is "soft_lutpair1030";
  attribute syn_maxfan : string;
  attribute syn_maxfan of app_rdy_r_reg : label is "10";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \i___34_i_1\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \i___55_i_1\ : label is "soft_lutpair1040";
  attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_1\ : label is "soft_lutpair1028";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[0]_i_1\ : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[1]_i_1\ : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \req_bank_r_lcl[2]_i_1\ : label is "soft_lutpair1036";
  attribute SOFT_HLUTNM of \req_col_r[0]_i_1\ : label is "soft_lutpair1041";
  attribute SOFT_HLUTNM of \req_col_r[2]_i_1\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \req_col_r[3]_i_1\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \req_col_r[4]_i_1\ : label is "soft_lutpair1044";
  attribute SOFT_HLUTNM of \req_col_r[5]_i_1\ : label is "soft_lutpair1044";
  attribute SOFT_HLUTNM of \req_col_r[6]_i_1\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \req_col_r[7]_i_1\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \req_col_r[8]_i_1\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \req_col_r[9]_i_1\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \req_data_buf_addr_r[2]_i_1\ : label is "soft_lutpair1029";
  attribute SOFT_HLUTNM of \req_data_buf_addr_r[4]_i_1\ : label is "soft_lutpair1029";
  attribute SOFT_HLUTNM of \req_row_r_lcl[0]_i_1\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \req_row_r_lcl[10]_i_1\ : label is "soft_lutpair1036";
  attribute SOFT_HLUTNM of \req_row_r_lcl[11]_i_1\ : label is "soft_lutpair1033";
  attribute SOFT_HLUTNM of \req_row_r_lcl[12]_i_1\ : label is "soft_lutpair1032";
  attribute SOFT_HLUTNM of \req_row_r_lcl[13]_i_1\ : label is "soft_lutpair1041";
  attribute SOFT_HLUTNM of \req_row_r_lcl[1]_i_1\ : label is "soft_lutpair1034";
  attribute SOFT_HLUTNM of \req_row_r_lcl[2]_i_1\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \req_row_r_lcl[3]_i_1\ : label is "soft_lutpair1034";
  attribute SOFT_HLUTNM of \req_row_r_lcl[4]_i_1\ : label is "soft_lutpair1033";
  attribute SOFT_HLUTNM of \req_row_r_lcl[5]_i_1\ : label is "soft_lutpair1032";
  attribute SOFT_HLUTNM of \req_row_r_lcl[6]_i_1\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of \req_row_r_lcl[7]_i_1\ : label is "soft_lutpair1038";
  attribute SOFT_HLUTNM of \req_row_r_lcl[8]_i_1\ : label is "soft_lutpair1038";
  attribute SOFT_HLUTNM of \req_row_r_lcl[9]_i_1\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of req_wr_r_lcl_i_2 : label is "soft_lutpair1040";
  attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[3]_i_2\ : label is "soft_lutpair1028";
begin
  D(12 downto 0) <= \^d\(12 downto 0);
  E(0) <= \^e\(0);
  \req_bank_r_lcl_reg[0]\ <= \^req_bank_r_lcl_reg[0]\;
  \req_bank_r_lcl_reg[1]\ <= \^req_bank_r_lcl_reg[1]\;
  \req_bank_r_lcl_reg[2]\ <= \^req_bank_r_lcl_reg[2]\;
  \req_row_r_lcl_reg[12]\ <= \^req_row_r_lcl_reg[12]\;
  \wr_req_counter.wr_req_cnt_r_reg[0]_0\ <= \^wr_req_counter.wr_req_cnt_r_reg[0]_0\;
\app_addr_r1[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^e\(0),
      I1 => app_en,
      O => app_addr_r10
    );
\app_addr_r1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(0),
      Q => \app_addr_r1_reg_n_0_[0]\,
      R => reset_reg
    );
\app_addr_r1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(10),
      Q => \app_addr_r1_reg_n_0_[10]\,
      R => reset_reg
    );
\app_addr_r1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(11),
      Q => \app_addr_r1_reg_n_0_[11]\,
      R => reset_reg
    );
\app_addr_r1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(12),
      Q => \app_addr_r1_reg_n_0_[12]\,
      R => reset_reg
    );
\app_addr_r1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(13),
      Q => \app_addr_r1_reg_n_0_[13]\,
      R => reset_reg
    );
\app_addr_r1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(14),
      Q => \app_addr_r1_reg_n_0_[14]\,
      R => reset_reg
    );
\app_addr_r1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(15),
      Q => \app_addr_r1_reg_n_0_[15]\,
      R => reset_reg
    );
\app_addr_r1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(16),
      Q => \app_addr_r1_reg_n_0_[16]\,
      R => reset_reg
    );
\app_addr_r1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(17),
      Q => \app_addr_r1_reg_n_0_[17]\,
      R => reset_reg
    );
\app_addr_r1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(18),
      Q => \app_addr_r1_reg_n_0_[18]\,
      R => reset_reg
    );
\app_addr_r1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(19),
      Q => \app_addr_r1_reg_n_0_[19]\,
      R => reset_reg
    );
\app_addr_r1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(1),
      Q => \app_addr_r1_reg_n_0_[1]\,
      R => reset_reg
    );
\app_addr_r1_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(20),
      Q => \app_addr_r1_reg_n_0_[20]\,
      R => reset_reg
    );
\app_addr_r1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(21),
      Q => \app_addr_r1_reg_n_0_[21]\,
      R => reset_reg
    );
\app_addr_r1_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(22),
      Q => \app_addr_r1_reg_n_0_[22]\,
      R => reset_reg
    );
\app_addr_r1_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(23),
      Q => \app_addr_r1_reg_n_0_[23]\,
      R => reset_reg
    );
\app_addr_r1_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(24),
      Q => p_1_in(0),
      R => reset_reg
    );
\app_addr_r1_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(25),
      Q => p_1_in(1),
      R => reset_reg
    );
\app_addr_r1_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(26),
      Q => p_1_in(2),
      R => reset_reg
    );
\app_addr_r1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(2),
      Q => \app_addr_r1_reg_n_0_[2]\,
      R => reset_reg
    );
\app_addr_r1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(3),
      Q => \app_addr_r1_reg_n_0_[3]\,
      R => reset_reg
    );
\app_addr_r1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(4),
      Q => \app_addr_r1_reg_n_0_[4]\,
      R => reset_reg
    );
\app_addr_r1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(5),
      Q => \app_addr_r1_reg_n_0_[5]\,
      R => reset_reg
    );
\app_addr_r1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(6),
      Q => \app_addr_r1_reg_n_0_[6]\,
      R => reset_reg
    );
\app_addr_r1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(7),
      Q => \app_addr_r1_reg_n_0_[7]\,
      R => reset_reg
    );
\app_addr_r1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(8),
      Q => \app_addr_r1_reg_n_0_[8]\,
      R => reset_reg
    );
\app_addr_r1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => app_addr_r10,
      D => app_addr(9),
      Q => \app_addr_r1_reg_n_0_[9]\,
      R => reset_reg
    );
\app_addr_r2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[0]\,
      Q => \app_addr_r2_reg_n_0_[0]\,
      R => reset_reg
    );
\app_addr_r2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[10]\,
      Q => \app_addr_r2_reg_n_0_[10]\,
      R => reset_reg
    );
\app_addr_r2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[11]\,
      Q => \app_addr_r2_reg_n_0_[11]\,
      R => reset_reg
    );
\app_addr_r2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[12]\,
      Q => \app_addr_r2_reg_n_0_[12]\,
      R => reset_reg
    );
\app_addr_r2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[13]\,
      Q => \app_addr_r2_reg_n_0_[13]\,
      R => reset_reg
    );
\app_addr_r2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[14]\,
      Q => \app_addr_r2_reg_n_0_[14]\,
      R => reset_reg
    );
\app_addr_r2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[15]\,
      Q => \app_addr_r2_reg_n_0_[15]\,
      R => reset_reg
    );
\app_addr_r2_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[16]\,
      Q => \app_addr_r2_reg_n_0_[16]\,
      R => reset_reg
    );
\app_addr_r2_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[17]\,
      Q => \app_addr_r2_reg_n_0_[17]\,
      R => reset_reg
    );
\app_addr_r2_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[18]\,
      Q => \app_addr_r2_reg_n_0_[18]\,
      R => reset_reg
    );
\app_addr_r2_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[19]\,
      Q => \app_addr_r2_reg_n_0_[19]\,
      R => reset_reg
    );
\app_addr_r2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[1]\,
      Q => \app_addr_r2_reg_n_0_[1]\,
      R => reset_reg
    );
\app_addr_r2_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[20]\,
      Q => \app_addr_r2_reg_n_0_[20]\,
      R => reset_reg
    );
\app_addr_r2_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[21]\,
      Q => \app_addr_r2_reg_n_0_[21]\,
      R => reset_reg
    );
\app_addr_r2_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[22]\,
      Q => \app_addr_r2_reg_n_0_[22]\,
      R => reset_reg
    );
\app_addr_r2_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[23]\,
      Q => \app_addr_r2_reg_n_0_[23]\,
      R => reset_reg
    );
\app_addr_r2_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => p_1_in(0),
      Q => p_0_in_0(0),
      R => reset_reg
    );
\app_addr_r2_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => p_1_in(1),
      Q => p_0_in_0(1),
      R => reset_reg
    );
\app_addr_r2_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => p_1_in(2),
      Q => p_0_in_0(2),
      R => reset_reg
    );
\app_addr_r2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[2]\,
      Q => \app_addr_r2_reg_n_0_[2]\,
      R => reset_reg
    );
\app_addr_r2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[3]\,
      Q => \app_addr_r2_reg_n_0_[3]\,
      R => reset_reg
    );
\app_addr_r2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[4]\,
      Q => \app_addr_r2_reg_n_0_[4]\,
      R => reset_reg
    );
\app_addr_r2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[5]\,
      Q => \app_addr_r2_reg_n_0_[5]\,
      R => reset_reg
    );
\app_addr_r2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[6]\,
      Q => \app_addr_r2_reg_n_0_[6]\,
      R => reset_reg
    );
\app_addr_r2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[7]\,
      Q => \app_addr_r2_reg_n_0_[7]\,
      R => reset_reg
    );
\app_addr_r2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[8]\,
      Q => \app_addr_r2_reg_n_0_[8]\,
      R => reset_reg
    );
\app_addr_r2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => \app_addr_r1_reg_n_0_[9]\,
      Q => \app_addr_r2_reg_n_0_[9]\,
      R => reset_reg
    );
\app_cmd_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd(0),
      Q => app_cmd_r1(0),
      R => '0'
    );
\app_cmd_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd(1),
      Q => app_cmd_r1(1),
      R => '0'
    );
\app_cmd_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd_r1(0),
      Q => app_cmd_r2(0),
      R => '0'
    );
\app_cmd_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => app_cmd_r1(1),
      Q => app_cmd_r2(1),
      R => '0'
    );
app_en_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_en,
      I1 => reset_reg,
      I2 => app_en_r1,
      I3 => \^e\(0),
      O => app_en_ns1
    );
app_en_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_en_ns1,
      Q => app_en_r1,
      R => '0'
    );
app_en_r2_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_en_r1,
      I1 => reset_reg,
      I2 => app_en_r2,
      I3 => \^e\(0),
      O => app_en_ns2
    );
app_en_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_en_ns2,
      Q => app_en_r2,
      R => '0'
    );
app_rdy_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_rdy_ns,
      Q => \^e\(0),
      R => '0'
    );
\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8008"
    )
        port map (
      I0 => \^e\(0),
      I1 => app_en_r2,
      I2 => app_cmd_r2(0),
      I3 => app_cmd_r2(1),
      O => wr_accepted
    );
\i___34_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => app_en_r2,
      I1 => \^e\(0),
      O => use_addr
    );
\i___55_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_cmd_r1(0),
      I1 => \^e\(0),
      I2 => app_cmd_r2(0),
      O => cmd(0)
    );
\not_strict_mode.occ_cnt_r[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008000AAAAEAAA"
    )
        port map (
      I0 => \not_strict_mode.occ_cnt_r\(0),
      I1 => app_en_r2,
      I2 => \^e\(0),
      I3 => app_cmd_r2(0),
      I4 => app_cmd_r2(1),
      I5 => \not_strict_mode.occ_cnt_r\(1),
      O => \not_strict_mode.occ_cnt_r_reg[4]\
    );
\not_strict_mode.occ_cnt_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8788888888888888"
    )
        port map (
      I0 => \not_strict_mode.app_rd_data_valid_copy\,
      I1 => \not_strict_mode.app_rd_data_end_reg\,
      I2 => app_cmd_r2(1),
      I3 => app_cmd_r2(0),
      I4 => \^e\(0),
      I5 => app_en_r2,
      O => \not_strict_mode.occ_cnt_r_reg[3]\
    );
\not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => app_cmd_r2(1),
      I1 => app_cmd_r2(0),
      I2 => \^e\(0),
      I3 => app_en_r2,
      O => rd_accepted
    );
\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^req_bank_r_lcl_reg[0]\,
      I1 => \req_bank_r_lcl_reg[2]_0\(0),
      I2 => \req_bank_r_lcl_reg[2]_0\(1),
      I3 => \^req_bank_r_lcl_reg[1]\,
      I4 => \req_bank_r_lcl_reg[2]_0\(2),
      I5 => \^req_bank_r_lcl_reg[2]\,
      O => rb_hit_busy_r_reg
    );
\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^req_bank_r_lcl_reg[2]\,
      I1 => \req_bank_r_lcl_reg[2]_0\(5),
      I2 => \req_bank_r_lcl_reg[2]_0\(4),
      I3 => \^req_bank_r_lcl_reg[1]\,
      I4 => \req_bank_r_lcl_reg[2]_0\(3),
      I5 => \^req_bank_r_lcl_reg[0]\,
      O => rb_hit_busy_r_reg_0
    );
\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^req_bank_r_lcl_reg[0]\,
      I1 => \req_bank_r_lcl_reg[2]_0\(6),
      I2 => \req_bank_r_lcl_reg[2]_0\(7),
      I3 => \^req_bank_r_lcl_reg[1]\,
      I4 => \req_bank_r_lcl_reg[2]_0\(8),
      I5 => \^req_bank_r_lcl_reg[2]\,
      O => rb_hit_busy_r_reg_1
    );
\req_bank_r_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(0),
      I1 => \^e\(0),
      I2 => p_0_in_0(0),
      O => \^req_bank_r_lcl_reg[0]\
    );
\req_bank_r_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(1),
      I1 => \^e\(0),
      I2 => p_0_in_0(1),
      O => \^req_bank_r_lcl_reg[1]\
    );
\req_bank_r_lcl[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(2),
      I1 => \^e\(0),
      I2 => p_0_in_0(2),
      O => \^req_bank_r_lcl_reg[2]\
    );
\req_col_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[0]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[0]\,
      O => \req_col_r_reg[9]\(0)
    );
\req_col_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[1]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[1]\,
      O => \req_col_r_reg[9]\(1)
    );
\req_col_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[2]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[2]\,
      O => \req_col_r_reg[9]\(2)
    );
\req_col_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[3]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[3]\,
      O => \req_col_r_reg[9]\(3)
    );
\req_col_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[4]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[4]\,
      O => \req_col_r_reg[9]\(4)
    );
\req_col_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[5]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[5]\,
      O => \req_col_r_reg[9]\(5)
    );
\req_col_r[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[6]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[6]\,
      O => \req_col_r_reg[9]\(6)
    );
\req_col_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[7]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[7]\,
      O => \req_col_r_reg[9]\(7)
    );
\req_col_r[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[8]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[8]\,
      O => \req_col_r_reg[9]\(8)
    );
\req_col_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[9]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[9]\,
      O => \req_col_r_reg[9]\(9)
    );
\req_data_buf_addr_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BE82"
    )
        port map (
      I0 => wr_data_buf_addr(0),
      I1 => app_cmd_r2(1),
      I2 => app_cmd_r2(0),
      I3 => Q(0),
      O => \req_data_buf_addr_r_reg[4]\(0)
    );
\req_data_buf_addr_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BE82"
    )
        port map (
      I0 => wr_data_buf_addr(1),
      I1 => app_cmd_r2(1),
      I2 => app_cmd_r2(0),
      I3 => Q(1),
      O => \req_data_buf_addr_r_reg[4]\(1)
    );
\req_data_buf_addr_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BE82"
    )
        port map (
      I0 => wr_data_buf_addr(2),
      I1 => app_cmd_r2(1),
      I2 => app_cmd_r2(0),
      I3 => Q(2),
      O => \req_data_buf_addr_r_reg[4]\(2)
    );
\req_data_buf_addr_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BE82"
    )
        port map (
      I0 => wr_data_buf_addr(3),
      I1 => app_cmd_r2(1),
      I2 => app_cmd_r2(0),
      I3 => Q(3),
      O => \req_data_buf_addr_r_reg[4]\(3)
    );
\req_data_buf_addr_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => Q(4),
      I1 => app_cmd_r2(0),
      I2 => app_cmd_r2(1),
      O => \req_data_buf_addr_r_reg[4]\(4)
    );
\req_row_r_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[10]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[10]\,
      O => \^d\(0)
    );
\req_row_r_lcl[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[20]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[20]\,
      O => \^d\(10)
    );
\req_row_r_lcl[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[21]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[21]\,
      O => \^d\(11)
    );
\req_row_r_lcl[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[22]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[22]\,
      O => \^req_row_r_lcl_reg[12]\
    );
\req_row_r_lcl[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      O => \^d\(12)
    );
\req_row_r_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[11]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[11]\,
      O => \^d\(1)
    );
\req_row_r_lcl[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[12]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[12]\,
      O => \^d\(2)
    );
\req_row_r_lcl[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[13]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[13]\,
      O => \^d\(3)
    );
\req_row_r_lcl[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[14]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[14]\,
      O => \^d\(4)
    );
\req_row_r_lcl[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[15]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[15]\,
      O => \^d\(5)
    );
\req_row_r_lcl[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[16]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[16]\,
      O => \^d\(6)
    );
\req_row_r_lcl[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[17]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[17]\,
      O => \^d\(7)
    );
\req_row_r_lcl[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[18]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[18]\,
      O => \^d\(8)
    );
\req_row_r_lcl[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[19]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[19]\,
      O => \^d\(9)
    );
req_wr_r_lcl_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_cmd_r1(1),
      I1 => \^e\(0),
      I2 => app_cmd_r2(1),
      O => cmd(1)
    );
\row_hit_ns_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^req_row_r_lcl_reg[12]\,
      I4 => \req_row_r_lcl_reg[13]\(0),
      I5 => \req_row_r_lcl_reg[13]\(1),
      O => S(0)
    );
\row_hit_ns_carry__0_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^req_row_r_lcl_reg[12]\,
      I4 => \req_row_r_lcl_reg[13]\(5),
      I5 => \req_row_r_lcl_reg[13]\(6),
      O => row_hit_r_reg(0)
    );
\row_hit_ns_carry__0_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^req_row_r_lcl_reg[12]\,
      I4 => \req_row_r_lcl_reg[13]\(7),
      I5 => \req_row_r_lcl_reg[13]\(8),
      O => row_hit_r_reg_0(0)
    );
\row_hit_ns_carry__0_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B80000B847000047"
    )
        port map (
      I0 => \app_addr_r1_reg_n_0_[23]\,
      I1 => \^e\(0),
      I2 => \app_addr_r2_reg_n_0_[23]\,
      I3 => \^req_row_r_lcl_reg[12]\,
      I4 => \req_row_r_lcl_reg[13]\(9),
      I5 => \req_row_r_lcl_reg[13]\(10),
      O => row_hit_r_reg_1(0)
    );
\row_hit_ns_carry_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^d\(3),
      I1 => \req_row_r_lcl_reg[13]\(2),
      I2 => \req_row_r_lcl_reg[13]\(4),
      I3 => \^d\(5),
      I4 => \req_row_r_lcl_reg[13]\(3),
      I5 => \^d\(4),
      O => row_hit_r_reg_2(0)
    );
\wr_req_counter.wr_req_cnt_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      I1 => \wr_req_counter.wr_req_cnt_r\(0),
      I2 => reset_reg,
      O => \wr_req_counter.wr_req_cnt_r_reg[0]\(0)
    );
\wr_req_counter.wr_req_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAA6A"
    )
        port map (
      I0 => p_0_in(0),
      I1 => \^e\(0),
      I2 => app_en_r2,
      I3 => app_cmd_r2(0),
      I4 => app_cmd_r2(1),
      O => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\
    );
\wr_req_counter.wr_req_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"82000000EBAAAAAA"
    )
        port map (
      I0 => \wr_req_counter.wr_req_cnt_r\(0),
      I1 => app_cmd_r2(1),
      I2 => app_cmd_r2(0),
      I3 => app_en_r2,
      I4 => \^e\(0),
      I5 => \wr_req_counter.wr_req_cnt_r\(1),
      O => \wr_req_counter.wr_req_cnt_r_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ui_rd_data is
  port (
    \not_strict_mode.app_rd_data_end_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ADDRA : out STD_LOGIC_VECTOR ( 4 downto 0 );
    DOA : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DOC : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[11]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[9]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[7]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[17]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[15]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[13]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[23]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[21]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[19]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[29]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[27]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[25]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[35]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[33]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[31]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[41]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[39]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[37]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[47]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[45]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[43]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[53]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[51]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[49]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[59]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[57]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[55]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[63]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[61]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[83]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[81]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[79]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[89]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[87]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[85]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[95]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[93]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[91]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[101]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[99]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[97]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[107]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[105]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[103]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[113]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[111]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[109]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[119]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[117]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[115]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[125]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[123]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[121]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[131]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[129]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[127]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[137]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[135]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[133]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[143]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[141]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[139]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[149]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[147]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[145]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[155]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[153]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[151]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[161]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[159]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[157]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[167]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[165]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[163]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[173]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[171]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[169]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[179]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[177]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[175]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[185]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[183]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[181]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[191]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[189]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[187]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[197]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[195]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[193]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[203]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[201]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[199]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[209]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[207]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[205]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[215]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[213]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[211]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[221]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[219]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[217]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[227]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[225]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[223]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[233]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[231]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[229]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[239]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[237]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[235]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[245]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[243]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[241]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[251]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[249]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[247]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[257]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[255]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[253]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[263]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[261]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[259]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[269]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[267]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[265]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[275]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[273]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[271]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[281]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[279]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[277]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[287]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[285]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[283]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[293]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[291]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[289]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[299]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[297]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[295]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[305]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[303]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[301]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[311]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[309]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[307]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[317]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[315]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[313]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[323]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[321]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[319]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[329]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[327]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[325]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[335]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[333]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[331]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[341]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[339]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[337]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[347]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[345]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[343]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[353]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[351]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[349]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[359]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[357]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[355]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[365]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[363]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[361]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[371]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[369]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[367]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[377]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[375]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[373]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[383]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[381]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[379]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[389]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[387]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[385]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[395]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[393]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[391]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[401]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[399]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[397]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[407]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[405]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[403]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[413]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[411]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[409]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[419]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[417]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[415]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[425]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[423]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[421]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[431]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[429]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[427]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[437]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[435]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[433]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[443]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[441]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[439]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[449]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[447]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[445]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[455]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[453]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[451]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[461]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[459]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[457]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[467]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[465]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[463]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[473]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[471]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[469]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[479]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[477]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[475]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[485]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[483]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[481]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[491]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[489]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[487]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[497]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[495]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[493]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[503]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[501]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[499]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[509]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[507]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[505]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\ : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    \not_strict_mode.app_rd_data_valid_copy\ : out STD_LOGIC;
    \not_strict_mode.occ_cnt_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    ADDRD : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \pointer_ram.pointer_wr_data\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 511 downto 0 );
    CLK : in STD_LOGIC;
    \not_strict_mode.rd_buf_we\ : in STD_LOGIC;
    DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_end_ns\ : in STD_LOGIC;
    rd_accepted : in STD_LOGIC;
    \not_strict_mode.app_rd_data_valid_copy_reg_0\ : in STD_LOGIC;
    \not_strict_mode.occ_cnt_r_reg[0]_0\ : in STD_LOGIC;
    reset_reg : in STD_LOGIC;
    \not_strict_mode.bypass__0\ : in STD_LOGIC;
    \read_data_indx.rd_data_indx_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.wr_data_addr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\ : in STD_LOGIC_VECTOR ( 511 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ui_rd_data : entity is "mig_7series_v2_3_ui_rd_data";
end mig_7series_0_mig_7series_v2_3_ui_rd_data;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ui_rd_data is
  signal \^addra\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^app_rd_data_end\ : STD_LOGIC;
  signal app_rd_data_valid_ns : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_valid_copy\ : STD_LOGIC;
  signal \not_strict_mode.occ_cnt_r\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \not_strict_mode.occ_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \not_strict_mode.occ_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \not_strict_mode.occ_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \not_strict_mode.occ_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \not_strict_mode.occ_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \not_strict_mode.occ_cnt_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \^not_strict_mode.occ_cnt_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \not_strict_mode.rd_buf.rd_buf_indx_copy_r\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r\ : signal is "true";
  attribute syn_keep : string;
  attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r\ : signal is "true";
  signal \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \not_strict_mode.rd_status\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \not_strict_mode.status_ram.rd_buf_we_r1\ : STD_LOGIC;
  signal \not_strict_mode.status_ram.status_ram_wr_addr_ns\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \not_strict_mode.status_ram.status_ram_wr_addr_r\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \not_strict_mode.status_ram.status_ram_wr_data_ns\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \not_strict_mode.status_ram.status_ram_wr_data_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\ : STD_LOGIC;
  signal \not_strict_mode.status_ram.wr_status\ : STD_LOGIC;
  signal \not_strict_mode.status_ram.wr_status_r1\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \rd_buf_indx.ram_init_done_ns\ : STD_LOGIC;
  signal \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \rd_buf_indx.upd_rd_buf_indx__0\ : STD_LOGIC;
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \not_strict_mode.app_rd_data_valid_copy_reg\ : label is "no";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data_valid_i_1\ : label is "soft_lutpair1048";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \not_strict_mode.app_rd_data_valid_reg\ : label is "10";
  attribute KEEP : string;
  attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]\ : label is "yes";
  attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]\ : label is "true";
  attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1]\ : label is "yes";
  attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1]\ : label is "true";
  attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2]\ : label is "yes";
  attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2]\ : label is "true";
  attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3]\ : label is "yes";
  attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3]\ : label is "true";
  attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : label is "yes";
  attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : label is "true";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[1]_i_1\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[2]_i_1\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[3]_i_1\ : label is "soft_lutpair1047";
  attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_2\ : label is "soft_lutpair1047";
  attribute BOX_TYPE of \not_strict_mode.status_ram.RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1\ : label is "soft_lutpair1049";
  attribute SOFT_HLUTNM of \not_strict_mode.status_ram.status_ram_wr_data_r[1]_i_1\ : label is "soft_lutpair1049";
  attribute syn_maxfan of \rd_buf_indx.ram_init_done_r_lcl_reg\ : label is "10";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[2]_i_1\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[3]_i_1\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[4]_i_2\ : label is "soft_lutpair1048";
begin
  ADDRA(4 downto 0) <= \^addra\(4 downto 0);
  D(0) <= \^d\(0);
  app_rd_data_end <= \^app_rd_data_end\;
  \not_strict_mode.app_rd_data_valid_copy\ <= \^not_strict_mode.app_rd_data_valid_copy\;
  \not_strict_mode.occ_cnt_r_reg[1]_0\(1 downto 0) <= \^not_strict_mode.occ_cnt_r_reg[1]_0\(1 downto 0);
  \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(4 downto 0) <= \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(4 downto 0);
  \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\ <= \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\;
\not_strict_mode.app_rd_data_end_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.app_rd_data_end_ns\,
      Q => \^app_rd_data_end\,
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(0),
      Q => app_rd_data(0),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(100),
      Q => app_rd_data(100),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(101),
      Q => app_rd_data(101),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(102),
      Q => app_rd_data(102),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(103),
      Q => app_rd_data(103),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(104),
      Q => app_rd_data(104),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(105),
      Q => app_rd_data(105),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(106),
      Q => app_rd_data(106),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(107),
      Q => app_rd_data(107),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(108),
      Q => app_rd_data(108),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(109),
      Q => app_rd_data(109),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(10),
      Q => app_rd_data(10),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(110),
      Q => app_rd_data(110),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(111),
      Q => app_rd_data(111),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(112),
      Q => app_rd_data(112),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(113),
      Q => app_rd_data(113),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(114),
      Q => app_rd_data(114),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(115),
      Q => app_rd_data(115),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(116),
      Q => app_rd_data(116),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(117),
      Q => app_rd_data(117),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(118),
      Q => app_rd_data(118),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(119),
      Q => app_rd_data(119),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(11),
      Q => app_rd_data(11),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(120),
      Q => app_rd_data(120),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(121),
      Q => app_rd_data(121),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(122),
      Q => app_rd_data(122),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(123),
      Q => app_rd_data(123),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(124),
      Q => app_rd_data(124),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(125),
      Q => app_rd_data(125),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(126),
      Q => app_rd_data(126),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(127),
      Q => app_rd_data(127),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(128),
      Q => app_rd_data(128),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(129),
      Q => app_rd_data(129),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(12),
      Q => app_rd_data(12),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(130),
      Q => app_rd_data(130),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(131),
      Q => app_rd_data(131),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(132),
      Q => app_rd_data(132),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(133),
      Q => app_rd_data(133),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(134),
      Q => app_rd_data(134),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(135),
      Q => app_rd_data(135),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(136),
      Q => app_rd_data(136),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(137),
      Q => app_rd_data(137),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(138),
      Q => app_rd_data(138),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(139),
      Q => app_rd_data(139),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(13),
      Q => app_rd_data(13),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(140),
      Q => app_rd_data(140),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(141),
      Q => app_rd_data(141),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(142),
      Q => app_rd_data(142),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(143),
      Q => app_rd_data(143),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(144),
      Q => app_rd_data(144),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(145),
      Q => app_rd_data(145),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(146),
      Q => app_rd_data(146),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(147),
      Q => app_rd_data(147),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(148),
      Q => app_rd_data(148),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(149),
      Q => app_rd_data(149),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(14),
      Q => app_rd_data(14),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(150),
      Q => app_rd_data(150),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(151),
      Q => app_rd_data(151),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(152),
      Q => app_rd_data(152),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(153),
      Q => app_rd_data(153),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(154),
      Q => app_rd_data(154),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(155),
      Q => app_rd_data(155),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(156),
      Q => app_rd_data(156),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(157),
      Q => app_rd_data(157),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(158),
      Q => app_rd_data(158),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[159]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(159),
      Q => app_rd_data(159),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(15),
      Q => app_rd_data(15),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[160]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(160),
      Q => app_rd_data(160),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[161]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(161),
      Q => app_rd_data(161),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[162]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(162),
      Q => app_rd_data(162),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[163]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(163),
      Q => app_rd_data(163),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[164]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(164),
      Q => app_rd_data(164),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[165]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(165),
      Q => app_rd_data(165),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[166]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(166),
      Q => app_rd_data(166),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[167]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(167),
      Q => app_rd_data(167),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[168]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(168),
      Q => app_rd_data(168),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[169]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(169),
      Q => app_rd_data(169),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(16),
      Q => app_rd_data(16),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[170]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(170),
      Q => app_rd_data(170),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[171]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(171),
      Q => app_rd_data(171),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[172]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(172),
      Q => app_rd_data(172),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[173]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(173),
      Q => app_rd_data(173),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[174]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(174),
      Q => app_rd_data(174),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[175]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(175),
      Q => app_rd_data(175),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[176]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(176),
      Q => app_rd_data(176),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[177]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(177),
      Q => app_rd_data(177),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[178]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(178),
      Q => app_rd_data(178),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[179]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(179),
      Q => app_rd_data(179),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(17),
      Q => app_rd_data(17),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[180]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(180),
      Q => app_rd_data(180),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[181]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(181),
      Q => app_rd_data(181),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[182]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(182),
      Q => app_rd_data(182),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[183]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(183),
      Q => app_rd_data(183),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[184]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(184),
      Q => app_rd_data(184),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[185]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(185),
      Q => app_rd_data(185),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[186]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(186),
      Q => app_rd_data(186),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[187]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(187),
      Q => app_rd_data(187),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[188]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(188),
      Q => app_rd_data(188),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[189]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(189),
      Q => app_rd_data(189),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(18),
      Q => app_rd_data(18),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[190]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(190),
      Q => app_rd_data(190),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[191]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(191),
      Q => app_rd_data(191),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[192]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(192),
      Q => app_rd_data(192),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[193]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(193),
      Q => app_rd_data(193),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[194]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(194),
      Q => app_rd_data(194),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[195]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(195),
      Q => app_rd_data(195),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[196]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(196),
      Q => app_rd_data(196),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[197]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(197),
      Q => app_rd_data(197),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[198]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(198),
      Q => app_rd_data(198),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[199]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(199),
      Q => app_rd_data(199),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(19),
      Q => app_rd_data(19),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(1),
      Q => app_rd_data(1),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[200]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(200),
      Q => app_rd_data(200),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[201]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(201),
      Q => app_rd_data(201),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[202]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(202),
      Q => app_rd_data(202),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[203]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(203),
      Q => app_rd_data(203),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[204]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(204),
      Q => app_rd_data(204),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[205]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(205),
      Q => app_rd_data(205),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[206]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(206),
      Q => app_rd_data(206),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[207]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(207),
      Q => app_rd_data(207),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[208]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(208),
      Q => app_rd_data(208),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[209]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(209),
      Q => app_rd_data(209),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(20),
      Q => app_rd_data(20),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[210]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(210),
      Q => app_rd_data(210),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[211]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(211),
      Q => app_rd_data(211),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[212]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(212),
      Q => app_rd_data(212),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[213]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(213),
      Q => app_rd_data(213),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[214]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(214),
      Q => app_rd_data(214),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[215]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(215),
      Q => app_rd_data(215),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[216]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(216),
      Q => app_rd_data(216),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[217]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(217),
      Q => app_rd_data(217),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[218]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(218),
      Q => app_rd_data(218),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[219]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(219),
      Q => app_rd_data(219),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(21),
      Q => app_rd_data(21),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[220]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(220),
      Q => app_rd_data(220),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[221]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(221),
      Q => app_rd_data(221),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[222]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(222),
      Q => app_rd_data(222),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[223]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(223),
      Q => app_rd_data(223),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[224]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(224),
      Q => app_rd_data(224),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[225]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(225),
      Q => app_rd_data(225),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[226]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(226),
      Q => app_rd_data(226),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[227]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(227),
      Q => app_rd_data(227),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[228]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(228),
      Q => app_rd_data(228),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[229]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(229),
      Q => app_rd_data(229),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(22),
      Q => app_rd_data(22),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[230]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(230),
      Q => app_rd_data(230),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[231]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(231),
      Q => app_rd_data(231),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[232]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(232),
      Q => app_rd_data(232),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[233]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(233),
      Q => app_rd_data(233),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[234]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(234),
      Q => app_rd_data(234),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[235]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(235),
      Q => app_rd_data(235),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[236]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(236),
      Q => app_rd_data(236),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[237]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(237),
      Q => app_rd_data(237),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[238]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(238),
      Q => app_rd_data(238),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[239]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(239),
      Q => app_rd_data(239),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(23),
      Q => app_rd_data(23),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[240]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(240),
      Q => app_rd_data(240),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[241]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(241),
      Q => app_rd_data(241),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[242]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(242),
      Q => app_rd_data(242),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[243]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(243),
      Q => app_rd_data(243),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[244]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(244),
      Q => app_rd_data(244),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[245]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(245),
      Q => app_rd_data(245),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[246]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(246),
      Q => app_rd_data(246),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[247]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(247),
      Q => app_rd_data(247),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[248]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(248),
      Q => app_rd_data(248),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[249]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(249),
      Q => app_rd_data(249),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(24),
      Q => app_rd_data(24),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[250]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(250),
      Q => app_rd_data(250),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[251]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(251),
      Q => app_rd_data(251),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[252]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(252),
      Q => app_rd_data(252),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[253]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(253),
      Q => app_rd_data(253),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[254]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(254),
      Q => app_rd_data(254),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[255]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(255),
      Q => app_rd_data(255),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[256]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(256),
      Q => app_rd_data(256),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[257]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(257),
      Q => app_rd_data(257),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[258]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(258),
      Q => app_rd_data(258),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[259]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(259),
      Q => app_rd_data(259),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(25),
      Q => app_rd_data(25),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[260]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(260),
      Q => app_rd_data(260),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[261]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(261),
      Q => app_rd_data(261),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[262]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(262),
      Q => app_rd_data(262),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[263]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(263),
      Q => app_rd_data(263),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[264]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(264),
      Q => app_rd_data(264),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[265]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(265),
      Q => app_rd_data(265),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[266]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(266),
      Q => app_rd_data(266),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[267]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(267),
      Q => app_rd_data(267),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[268]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(268),
      Q => app_rd_data(268),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[269]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(269),
      Q => app_rd_data(269),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(26),
      Q => app_rd_data(26),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[270]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(270),
      Q => app_rd_data(270),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[271]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(271),
      Q => app_rd_data(271),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[272]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(272),
      Q => app_rd_data(272),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[273]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(273),
      Q => app_rd_data(273),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[274]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(274),
      Q => app_rd_data(274),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[275]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(275),
      Q => app_rd_data(275),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[276]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(276),
      Q => app_rd_data(276),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[277]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(277),
      Q => app_rd_data(277),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[278]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(278),
      Q => app_rd_data(278),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[279]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(279),
      Q => app_rd_data(279),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(27),
      Q => app_rd_data(27),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[280]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(280),
      Q => app_rd_data(280),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[281]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(281),
      Q => app_rd_data(281),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[282]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(282),
      Q => app_rd_data(282),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[283]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(283),
      Q => app_rd_data(283),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[284]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(284),
      Q => app_rd_data(284),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[285]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(285),
      Q => app_rd_data(285),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[286]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(286),
      Q => app_rd_data(286),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[287]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(287),
      Q => app_rd_data(287),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[288]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(288),
      Q => app_rd_data(288),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[289]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(289),
      Q => app_rd_data(289),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(28),
      Q => app_rd_data(28),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[290]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(290),
      Q => app_rd_data(290),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[291]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(291),
      Q => app_rd_data(291),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[292]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(292),
      Q => app_rd_data(292),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[293]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(293),
      Q => app_rd_data(293),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[294]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(294),
      Q => app_rd_data(294),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[295]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(295),
      Q => app_rd_data(295),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[296]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(296),
      Q => app_rd_data(296),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[297]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(297),
      Q => app_rd_data(297),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[298]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(298),
      Q => app_rd_data(298),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[299]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(299),
      Q => app_rd_data(299),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(29),
      Q => app_rd_data(29),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(2),
      Q => app_rd_data(2),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[300]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(300),
      Q => app_rd_data(300),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[301]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(301),
      Q => app_rd_data(301),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[302]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(302),
      Q => app_rd_data(302),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[303]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(303),
      Q => app_rd_data(303),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[304]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(304),
      Q => app_rd_data(304),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[305]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(305),
      Q => app_rd_data(305),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[306]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(306),
      Q => app_rd_data(306),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[307]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(307),
      Q => app_rd_data(307),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[308]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(308),
      Q => app_rd_data(308),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[309]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(309),
      Q => app_rd_data(309),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(30),
      Q => app_rd_data(30),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[310]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(310),
      Q => app_rd_data(310),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[311]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(311),
      Q => app_rd_data(311),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[312]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(312),
      Q => app_rd_data(312),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[313]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(313),
      Q => app_rd_data(313),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[314]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(314),
      Q => app_rd_data(314),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[315]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(315),
      Q => app_rd_data(315),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[316]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(316),
      Q => app_rd_data(316),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[317]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(317),
      Q => app_rd_data(317),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[318]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(318),
      Q => app_rd_data(318),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[319]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(319),
      Q => app_rd_data(319),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(31),
      Q => app_rd_data(31),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[320]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(320),
      Q => app_rd_data(320),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[321]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(321),
      Q => app_rd_data(321),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[322]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(322),
      Q => app_rd_data(322),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[323]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(323),
      Q => app_rd_data(323),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[324]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(324),
      Q => app_rd_data(324),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[325]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(325),
      Q => app_rd_data(325),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[326]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(326),
      Q => app_rd_data(326),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[327]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(327),
      Q => app_rd_data(327),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[328]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(328),
      Q => app_rd_data(328),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[329]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(329),
      Q => app_rd_data(329),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(32),
      Q => app_rd_data(32),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[330]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(330),
      Q => app_rd_data(330),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[331]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(331),
      Q => app_rd_data(331),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[332]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(332),
      Q => app_rd_data(332),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[333]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(333),
      Q => app_rd_data(333),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[334]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(334),
      Q => app_rd_data(334),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[335]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(335),
      Q => app_rd_data(335),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[336]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(336),
      Q => app_rd_data(336),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[337]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(337),
      Q => app_rd_data(337),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[338]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(338),
      Q => app_rd_data(338),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[339]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(339),
      Q => app_rd_data(339),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(33),
      Q => app_rd_data(33),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[340]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(340),
      Q => app_rd_data(340),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[341]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(341),
      Q => app_rd_data(341),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[342]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(342),
      Q => app_rd_data(342),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[343]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(343),
      Q => app_rd_data(343),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[344]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(344),
      Q => app_rd_data(344),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[345]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(345),
      Q => app_rd_data(345),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[346]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(346),
      Q => app_rd_data(346),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[347]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(347),
      Q => app_rd_data(347),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[348]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(348),
      Q => app_rd_data(348),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[349]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(349),
      Q => app_rd_data(349),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(34),
      Q => app_rd_data(34),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[350]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(350),
      Q => app_rd_data(350),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[351]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(351),
      Q => app_rd_data(351),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[352]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(352),
      Q => app_rd_data(352),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[353]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(353),
      Q => app_rd_data(353),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[354]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(354),
      Q => app_rd_data(354),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[355]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(355),
      Q => app_rd_data(355),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[356]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(356),
      Q => app_rd_data(356),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[357]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(357),
      Q => app_rd_data(357),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[358]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(358),
      Q => app_rd_data(358),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[359]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(359),
      Q => app_rd_data(359),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(35),
      Q => app_rd_data(35),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[360]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(360),
      Q => app_rd_data(360),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[361]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(361),
      Q => app_rd_data(361),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[362]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(362),
      Q => app_rd_data(362),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[363]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(363),
      Q => app_rd_data(363),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[364]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(364),
      Q => app_rd_data(364),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[365]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(365),
      Q => app_rd_data(365),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[366]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(366),
      Q => app_rd_data(366),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[367]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(367),
      Q => app_rd_data(367),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[368]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(368),
      Q => app_rd_data(368),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[369]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(369),
      Q => app_rd_data(369),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(36),
      Q => app_rd_data(36),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[370]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(370),
      Q => app_rd_data(370),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[371]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(371),
      Q => app_rd_data(371),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[372]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(372),
      Q => app_rd_data(372),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[373]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(373),
      Q => app_rd_data(373),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[374]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(374),
      Q => app_rd_data(374),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[375]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(375),
      Q => app_rd_data(375),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[376]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(376),
      Q => app_rd_data(376),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[377]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(377),
      Q => app_rd_data(377),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[378]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(378),
      Q => app_rd_data(378),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[379]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(379),
      Q => app_rd_data(379),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(37),
      Q => app_rd_data(37),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[380]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(380),
      Q => app_rd_data(380),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[381]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(381),
      Q => app_rd_data(381),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[382]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(382),
      Q => app_rd_data(382),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[383]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(383),
      Q => app_rd_data(383),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[384]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(384),
      Q => app_rd_data(384),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[385]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(385),
      Q => app_rd_data(385),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[386]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(386),
      Q => app_rd_data(386),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[387]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(387),
      Q => app_rd_data(387),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[388]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(388),
      Q => app_rd_data(388),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[389]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(389),
      Q => app_rd_data(389),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(38),
      Q => app_rd_data(38),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[390]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(390),
      Q => app_rd_data(390),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[391]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(391),
      Q => app_rd_data(391),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[392]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(392),
      Q => app_rd_data(392),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[393]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(393),
      Q => app_rd_data(393),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[394]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(394),
      Q => app_rd_data(394),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[395]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(395),
      Q => app_rd_data(395),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[396]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(396),
      Q => app_rd_data(396),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[397]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(397),
      Q => app_rd_data(397),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[398]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(398),
      Q => app_rd_data(398),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[399]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(399),
      Q => app_rd_data(399),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(39),
      Q => app_rd_data(39),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(3),
      Q => app_rd_data(3),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[400]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(400),
      Q => app_rd_data(400),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[401]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(401),
      Q => app_rd_data(401),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[402]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(402),
      Q => app_rd_data(402),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[403]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(403),
      Q => app_rd_data(403),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[404]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(404),
      Q => app_rd_data(404),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[405]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(405),
      Q => app_rd_data(405),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[406]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(406),
      Q => app_rd_data(406),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[407]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(407),
      Q => app_rd_data(407),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[408]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(408),
      Q => app_rd_data(408),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[409]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(409),
      Q => app_rd_data(409),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(40),
      Q => app_rd_data(40),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[410]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(410),
      Q => app_rd_data(410),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[411]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(411),
      Q => app_rd_data(411),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[412]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(412),
      Q => app_rd_data(412),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[413]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(413),
      Q => app_rd_data(413),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[414]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(414),
      Q => app_rd_data(414),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[415]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(415),
      Q => app_rd_data(415),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[416]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(416),
      Q => app_rd_data(416),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[417]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(417),
      Q => app_rd_data(417),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[418]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(418),
      Q => app_rd_data(418),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[419]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(419),
      Q => app_rd_data(419),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(41),
      Q => app_rd_data(41),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[420]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(420),
      Q => app_rd_data(420),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[421]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(421),
      Q => app_rd_data(421),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[422]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(422),
      Q => app_rd_data(422),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[423]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(423),
      Q => app_rd_data(423),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[424]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(424),
      Q => app_rd_data(424),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[425]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(425),
      Q => app_rd_data(425),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[426]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(426),
      Q => app_rd_data(426),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[427]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(427),
      Q => app_rd_data(427),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[428]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(428),
      Q => app_rd_data(428),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[429]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(429),
      Q => app_rd_data(429),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(42),
      Q => app_rd_data(42),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[430]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(430),
      Q => app_rd_data(430),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[431]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(431),
      Q => app_rd_data(431),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[432]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(432),
      Q => app_rd_data(432),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[433]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(433),
      Q => app_rd_data(433),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[434]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(434),
      Q => app_rd_data(434),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[435]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(435),
      Q => app_rd_data(435),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[436]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(436),
      Q => app_rd_data(436),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[437]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(437),
      Q => app_rd_data(437),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[438]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(438),
      Q => app_rd_data(438),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[439]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(439),
      Q => app_rd_data(439),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(43),
      Q => app_rd_data(43),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[440]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(440),
      Q => app_rd_data(440),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[441]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(441),
      Q => app_rd_data(441),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[442]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(442),
      Q => app_rd_data(442),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[443]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(443),
      Q => app_rd_data(443),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[444]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(444),
      Q => app_rd_data(444),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[445]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(445),
      Q => app_rd_data(445),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[446]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(446),
      Q => app_rd_data(446),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[447]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(447),
      Q => app_rd_data(447),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[448]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(448),
      Q => app_rd_data(448),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[449]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(449),
      Q => app_rd_data(449),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(44),
      Q => app_rd_data(44),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[450]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(450),
      Q => app_rd_data(450),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[451]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(451),
      Q => app_rd_data(451),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[452]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(452),
      Q => app_rd_data(452),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[453]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(453),
      Q => app_rd_data(453),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[454]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(454),
      Q => app_rd_data(454),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[455]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(455),
      Q => app_rd_data(455),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[456]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(456),
      Q => app_rd_data(456),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[457]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(457),
      Q => app_rd_data(457),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[458]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(458),
      Q => app_rd_data(458),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[459]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(459),
      Q => app_rd_data(459),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(45),
      Q => app_rd_data(45),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[460]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(460),
      Q => app_rd_data(460),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[461]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(461),
      Q => app_rd_data(461),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[462]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(462),
      Q => app_rd_data(462),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[463]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(463),
      Q => app_rd_data(463),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[464]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(464),
      Q => app_rd_data(464),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[465]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(465),
      Q => app_rd_data(465),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[466]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(466),
      Q => app_rd_data(466),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[467]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(467),
      Q => app_rd_data(467),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[468]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(468),
      Q => app_rd_data(468),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[469]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(469),
      Q => app_rd_data(469),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(46),
      Q => app_rd_data(46),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[470]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(470),
      Q => app_rd_data(470),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[471]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(471),
      Q => app_rd_data(471),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[472]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(472),
      Q => app_rd_data(472),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[473]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(473),
      Q => app_rd_data(473),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[474]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(474),
      Q => app_rd_data(474),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[475]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(475),
      Q => app_rd_data(475),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[476]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(476),
      Q => app_rd_data(476),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[477]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(477),
      Q => app_rd_data(477),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[478]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(478),
      Q => app_rd_data(478),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[479]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(479),
      Q => app_rd_data(479),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(47),
      Q => app_rd_data(47),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[480]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(480),
      Q => app_rd_data(480),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[481]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(481),
      Q => app_rd_data(481),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[482]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(482),
      Q => app_rd_data(482),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[483]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(483),
      Q => app_rd_data(483),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[484]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(484),
      Q => app_rd_data(484),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[485]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(485),
      Q => app_rd_data(485),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[486]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(486),
      Q => app_rd_data(486),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[487]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(487),
      Q => app_rd_data(487),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[488]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(488),
      Q => app_rd_data(488),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[489]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(489),
      Q => app_rd_data(489),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(48),
      Q => app_rd_data(48),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[490]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(490),
      Q => app_rd_data(490),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[491]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(491),
      Q => app_rd_data(491),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[492]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(492),
      Q => app_rd_data(492),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[493]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(493),
      Q => app_rd_data(493),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[494]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(494),
      Q => app_rd_data(494),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[495]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(495),
      Q => app_rd_data(495),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[496]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(496),
      Q => app_rd_data(496),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[497]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(497),
      Q => app_rd_data(497),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[498]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(498),
      Q => app_rd_data(498),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[499]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(499),
      Q => app_rd_data(499),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(49),
      Q => app_rd_data(49),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(4),
      Q => app_rd_data(4),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[500]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(500),
      Q => app_rd_data(500),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[501]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(501),
      Q => app_rd_data(501),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[502]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(502),
      Q => app_rd_data(502),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[503]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(503),
      Q => app_rd_data(503),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[504]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(504),
      Q => app_rd_data(504),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[505]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(505),
      Q => app_rd_data(505),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[506]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(506),
      Q => app_rd_data(506),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[507]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(507),
      Q => app_rd_data(507),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[508]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(508),
      Q => app_rd_data(508),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[509]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(509),
      Q => app_rd_data(509),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(50),
      Q => app_rd_data(50),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[510]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(510),
      Q => app_rd_data(510),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[511]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(511),
      Q => app_rd_data(511),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(51),
      Q => app_rd_data(51),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(52),
      Q => app_rd_data(52),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(53),
      Q => app_rd_data(53),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(54),
      Q => app_rd_data(54),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(55),
      Q => app_rd_data(55),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(56),
      Q => app_rd_data(56),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(57),
      Q => app_rd_data(57),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(58),
      Q => app_rd_data(58),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(59),
      Q => app_rd_data(59),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(5),
      Q => app_rd_data(5),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(60),
      Q => app_rd_data(60),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(61),
      Q => app_rd_data(61),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(62),
      Q => app_rd_data(62),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(63),
      Q => app_rd_data(63),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(64),
      Q => app_rd_data(64),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(65),
      Q => app_rd_data(65),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(66),
      Q => app_rd_data(66),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(67),
      Q => app_rd_data(67),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(68),
      Q => app_rd_data(68),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(69),
      Q => app_rd_data(69),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(6),
      Q => app_rd_data(6),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(70),
      Q => app_rd_data(70),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(71),
      Q => app_rd_data(71),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(72),
      Q => app_rd_data(72),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(73),
      Q => app_rd_data(73),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(74),
      Q => app_rd_data(74),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(75),
      Q => app_rd_data(75),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(76),
      Q => app_rd_data(76),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(77),
      Q => app_rd_data(77),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(78),
      Q => app_rd_data(78),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(79),
      Q => app_rd_data(79),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(7),
      Q => app_rd_data(7),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(80),
      Q => app_rd_data(80),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(81),
      Q => app_rd_data(81),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(82),
      Q => app_rd_data(82),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(83),
      Q => app_rd_data(83),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(84),
      Q => app_rd_data(84),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(85),
      Q => app_rd_data(85),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(86),
      Q => app_rd_data(86),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(87),
      Q => app_rd_data(87),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(88),
      Q => app_rd_data(88),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(89),
      Q => app_rd_data(89),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(8),
      Q => app_rd_data(8),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(90),
      Q => app_rd_data(90),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(91),
      Q => app_rd_data(91),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(92),
      Q => app_rd_data(92),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(93),
      Q => app_rd_data(93),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(94),
      Q => app_rd_data(94),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(95),
      Q => app_rd_data(95),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(96),
      Q => app_rd_data(96),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(97),
      Q => app_rd_data(97),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(98),
      Q => app_rd_data(98),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(99),
      Q => app_rd_data(99),
      R => '0'
    );
\not_strict_mode.app_rd_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(9),
      Q => app_rd_data(9),
      R => '0'
    );
\not_strict_mode.app_rd_data_valid_copy_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_rd_data_valid_ns,
      Q => \^not_strict_mode.app_rd_data_valid_copy\,
      R => '0'
    );
\not_strict_mode.app_rd_data_valid_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A88A"
    )
        port map (
      I0 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I1 => \not_strict_mode.bypass__0\,
      I2 => p_0_in,
      I3 => \not_strict_mode.rd_status\(0),
      O => app_rd_data_valid_ns
    );
\not_strict_mode.app_rd_data_valid_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_rd_data_valid_ns,
      Q => app_rd_data_valid,
      R => '0'
    );
\not_strict_mode.occ_cnt_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0),
      I1 => \not_strict_mode.app_rd_data_valid_copy_reg_0\,
      O => \not_strict_mode.occ_cnt_r[0]_i_1_n_0\
    );
\not_strict_mode.occ_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E1787878"
    )
        port map (
      I0 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0),
      I1 => rd_accepted,
      I2 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1),
      I3 => \^not_strict_mode.app_rd_data_valid_copy\,
      I4 => \^app_rd_data_end\,
      O => \not_strict_mode.occ_cnt_r[1]_i_1_n_0\
    );
\not_strict_mode.occ_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0E178F078F078F0"
    )
        port map (
      I0 => rd_accepted,
      I1 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0),
      I2 => \not_strict_mode.occ_cnt_r\(2),
      I3 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1),
      I4 => \^not_strict_mode.app_rd_data_valid_copy\,
      I5 => \^app_rd_data_end\,
      O => \not_strict_mode.occ_cnt_r[2]_i_1_n_0\
    );
\not_strict_mode.occ_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F80FE01FF00FF00"
    )
        port map (
      I0 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1),
      I1 => rd_accepted,
      I2 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0),
      I3 => \not_strict_mode.occ_cnt_r\(3),
      I4 => \not_strict_mode.occ_cnt_r\(2),
      I5 => \not_strict_mode.app_rd_data_valid_copy_reg_0\,
      O => \not_strict_mode.occ_cnt_r[3]_i_1_n_0\
    );
\not_strict_mode.occ_cnt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F80FE01FF00FF00"
    )
        port map (
      I0 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1),
      I1 => \not_strict_mode.occ_cnt_r_reg[0]_0\,
      I2 => \not_strict_mode.occ_cnt_r\(2),
      I3 => \not_strict_mode.occ_cnt_r\(4),
      I4 => \not_strict_mode.occ_cnt_r\(3),
      I5 => \not_strict_mode.app_rd_data_valid_copy_reg_0\,
      O => \not_strict_mode.occ_cnt_r[4]_i_1_n_0\
    );
\not_strict_mode.occ_cnt_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000078F0F0D2"
    )
        port map (
      I0 => \not_strict_mode.app_rd_data_valid_copy_reg_0\,
      I1 => \not_strict_mode.occ_cnt_r\(4),
      I2 => \not_strict_mode.occ_cnt_r\(5),
      I3 => \not_strict_mode.occ_cnt_r[5]_i_3_n_0\,
      I4 => \not_strict_mode.occ_cnt_r\(3),
      I5 => reset_reg,
      O => \^d\(0)
    );
\not_strict_mode.occ_cnt_r[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D5555554"
    )
        port map (
      I0 => \not_strict_mode.occ_cnt_r\(3),
      I1 => \not_strict_mode.occ_cnt_r\(2),
      I2 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0),
      I3 => rd_accepted,
      I4 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1),
      O => \not_strict_mode.occ_cnt_r[5]_i_3_n_0\
    );
\not_strict_mode.occ_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.occ_cnt_r[0]_i_1_n_0\,
      Q => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0),
      R => reset_reg
    );
\not_strict_mode.occ_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.occ_cnt_r[1]_i_1_n_0\,
      Q => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1),
      R => reset_reg
    );
\not_strict_mode.occ_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.occ_cnt_r[2]_i_1_n_0\,
      Q => \not_strict_mode.occ_cnt_r\(2),
      R => reset_reg
    );
\not_strict_mode.occ_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.occ_cnt_r[3]_i_1_n_0\,
      Q => \not_strict_mode.occ_cnt_r\(3),
      R => reset_reg
    );
\not_strict_mode.occ_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.occ_cnt_r[4]_i_1_n_0\,
      Q => \not_strict_mode.occ_cnt_r\(4),
      R => reset_reg
    );
\not_strict_mode.occ_cnt_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^d\(0),
      Q => \not_strict_mode.occ_cnt_r\(5),
      R => '0'
    );
\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0\,
      Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(0),
      R => '0'
    );
\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0\,
      Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(1),
      R => reset_reg
    );
\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0\,
      Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(2),
      R => reset_reg
    );
\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0\,
      Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(3),
      R => reset_reg
    );
\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4),
      R => reset_reg
    );
\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => DIA(1 downto 0),
      DIB(1 downto 0) => DIB(1 downto 0),
      DIC(1 downto 0) => DIC(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[131]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[129]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[137]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[135]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[133]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[143]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[141]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[139]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[149]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[147]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[145]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[155]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[153]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[151]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[161]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[159]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[157]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[167]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[165]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[163]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[173]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[171]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[169]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[179]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[177]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[175]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[185]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[183]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[181]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[191]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[189]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[187]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[197]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[195]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[193]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[203]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[201]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[199]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[209]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[207]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[205]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[215]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[213]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[211]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[221]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[219]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[217]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[227]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[225]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[223]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[233]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[231]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[229]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[239]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[237]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[235]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[245]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[243]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[241]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[251]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[249]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[247]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[257]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[255]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[253]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[263]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[261]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[259]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[269]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[267]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[265]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[275]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[273]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[271]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[281]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[279]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[277]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[287]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[285]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[283]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[293]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[291]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[289]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[299]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[297]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[295]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[305]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[303]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[301]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[311]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[309]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[307]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[317]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[315]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[313]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[323]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[321]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[319]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[329]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[327]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[325]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[335]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[333]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[331]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[341]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[339]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[337]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[347]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[345]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[343]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[353]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[351]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[349]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[359]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[357]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[355]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[365]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[363]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[361]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[371]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[369]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[367]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[377]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[375]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[373]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[383]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[381]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[379]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[389]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[387]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[385]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[395]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[393]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[391]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[401]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[399]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[397]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[407]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[405]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[403]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[413]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[411]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[409]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[419]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[417]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[415]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[425]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[423]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[421]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[431]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[429]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[427]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[437]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[435]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[433]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[443]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[441]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[439]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[449]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[447]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[445]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[455]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[453]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[451]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[461]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[459]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[457]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[467]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[465]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[463]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[473]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[471]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[469]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[479]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[477]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[475]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[485]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[483]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[481]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[491]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[489]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[487]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[497]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[495]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[493]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[503]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[501]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[499]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[509]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[507]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[505]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOB_UNCONNECTED\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[511]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0),
      ADDRD(4 downto 0) => Q(5 downto 1),
      DIA(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\(1 downto 0),
      DIB(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\(1 downto 0),
      DIC(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]_0\(1 downto 0),
      DOB(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]_0\(1 downto 0),
      DOC(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]_0\(1 downto 0),
      DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.rd_buf_we\
    );
\not_strict_mode.rd_data_buf_addr_r_lcl[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(0),
      O => \p_0_in__2\(0)
    );
\not_strict_mode.rd_data_buf_addr_r_lcl[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(0),
      I1 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(1),
      O => \p_0_in__2\(1)
    );
\not_strict_mode.rd_data_buf_addr_r_lcl[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(0),
      I1 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(1),
      I2 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(2),
      O => \p_0_in__2\(2)
    );
\not_strict_mode.rd_data_buf_addr_r_lcl[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(1),
      I1 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(0),
      I2 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(2),
      I3 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(3),
      O => \p_0_in__2\(3)
    );
\not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(2),
      I1 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(0),
      I2 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(1),
      I3 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(3),
      I4 => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(4),
      O => \p_0_in__2\(4)
    );
\not_strict_mode.rd_data_buf_addr_r_lcl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_accepted,
      D => \p_0_in__2\(0),
      Q => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(0),
      R => reset_reg
    );
\not_strict_mode.rd_data_buf_addr_r_lcl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_accepted,
      D => \p_0_in__2\(1),
      Q => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(1),
      R => reset_reg
    );
\not_strict_mode.rd_data_buf_addr_r_lcl_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_accepted,
      D => \p_0_in__2\(2),
      Q => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(2),
      R => reset_reg
    );
\not_strict_mode.rd_data_buf_addr_r_lcl_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_accepted,
      D => \p_0_in__2\(3),
      Q => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(3),
      R => reset_reg
    );
\not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => rd_accepted,
      D => \p_0_in__2\(4),
      Q => \^not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(4),
      R => reset_reg
    );
\not_strict_mode.status_ram.RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => \^addra\(4 downto 0),
      ADDRB(4 downto 0) => B"00000",
      ADDRC(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(4 downto 0),
      ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_addr_r\(4 downto 0),
      DIA(1 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r\(1 downto 0),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r\(1 downto 0),
      DID(1 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r\(1 downto 0),
      DOA(1) => \not_strict_mode.app_rd_data_end_reg_0\(0),
      DOA(0) => \not_strict_mode.rd_status\(0),
      DOB(1 downto 0) => \NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED\(1 downto 0),
      DOC(1) => \NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED\(1),
      DOC(0) => \not_strict_mode.status_ram.wr_status\,
      DOD(1 downto 0) => \NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \not_strict_mode.status_ram.rd_buf_we_r1\
    );
\not_strict_mode.status_ram.RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(4),
      O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(4)
    );
\not_strict_mode.status_ram.RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(3),
      O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(3)
    );
\not_strict_mode.status_ram.RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(3),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(2),
      O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(2)
    );
\not_strict_mode.status_ram.RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(2),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(1),
      O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(1)
    );
\not_strict_mode.status_ram.RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(0),
      O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(0)
    );
\not_strict_mode.status_ram.rd_buf_we_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.rd_buf_we\,
      Q => \not_strict_mode.status_ram.rd_buf_we_r1\,
      R => '0'
    );
\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(0),
      Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(0),
      R => '0'
    );
\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(1),
      Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(1),
      R => '0'
    );
\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(2),
      Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(2),
      R => '0'
    );
\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(3),
      Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(3),
      R => '0'
    );
\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(4),
      Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(4),
      R => '0'
    );
\not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4070"
    )
        port map (
      I0 => \not_strict_mode.status_ram.wr_status_r1\,
      I1 => Q(0),
      I2 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I3 => \not_strict_mode.status_ram.wr_status\,
      O => \not_strict_mode.status_ram.status_ram_wr_data_ns\(0)
    );
\not_strict_mode.status_ram.status_ram_wr_data_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I1 => Q(6),
      O => \not_strict_mode.status_ram.status_ram_wr_data_ns\(1)
    );
\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.status_ram_wr_data_ns\(0),
      Q => \not_strict_mode.status_ram.status_ram_wr_data_r\(0),
      R => '0'
    );
\not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.status_ram_wr_data_ns\(1),
      Q => \not_strict_mode.status_ram.status_ram_wr_data_r\(1),
      R => '0'
    );
\not_strict_mode.status_ram.wr_status_r1_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \not_strict_mode.status_ram.wr_status\,
      Q => \not_strict_mode.status_ram.wr_status_r1\,
      R => '0'
    );
\pointer_ram.rams[0].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.wr_data_addr_reg[3]\(1),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(1),
      O => \pointer_ram.pointer_wr_data\(1)
    );
\pointer_ram.rams[0].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.wr_data_addr_reg[3]\(0),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(0),
      O => \pointer_ram.pointer_wr_data\(0)
    );
\pointer_ram.rams[0].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \read_data_indx.rd_data_indx_r_reg[3]\(3),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(3),
      O => ADDRD(3)
    );
\pointer_ram.rams[0].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \read_data_indx.rd_data_indx_r_reg[3]\(2),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(2),
      O => ADDRD(2)
    );
\pointer_ram.rams[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \read_data_indx.rd_data_indx_r_reg[3]\(1),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(1),
      O => ADDRD(1)
    );
\pointer_ram.rams[0].RAM32M0_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \read_data_indx.rd_data_indx_r_reg[3]\(0),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(0),
      O => ADDRD(0)
    );
\pointer_ram.rams[1].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.wr_data_addr_reg[3]\(3),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(3),
      O => \pointer_ram.pointer_wr_data\(3)
    );
\pointer_ram.rams[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \cmd_pipe_plus.wr_data_addr_reg[3]\(2),
      I1 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I2 => \^addra\(2),
      O => \pointer_ram.pointer_wr_data\(2)
    );
\rd_buf_indx.ram_init_done_r_lcl_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\,
      I1 => reset_reg,
      I2 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      O => \rd_buf_indx.ram_init_done_ns\
    );
\rd_buf_indx.ram_init_done_r_lcl_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => \^addra\(1),
      I1 => \^addra\(2),
      I2 => \^addra\(0),
      I3 => reset_reg,
      I4 => \^addra\(4),
      I5 => \^addra\(3),
      O => \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0\
    );
\rd_buf_indx.ram_init_done_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.ram_init_done_ns\,
      Q => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      R => '0'
    );
\rd_buf_indx.rd_buf_indx_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000014000000EBFF"
    )
        port map (
      I0 => \not_strict_mode.bypass__0\,
      I1 => p_0_in,
      I2 => \not_strict_mode.rd_status\(0),
      I3 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I4 => reset_reg,
      I5 => \^addra\(0),
      O => \rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"57755555A88AAAAA"
    )
        port map (
      I0 => \^addra\(0),
      I1 => \not_strict_mode.bypass__0\,
      I2 => p_0_in,
      I3 => \not_strict_mode.rd_status\(0),
      I4 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I5 => \^addra\(1),
      O => \rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^addra\(1),
      I1 => \^addra\(0),
      I2 => \rd_buf_indx.upd_rd_buf_indx__0\,
      I3 => \^addra\(2),
      O => \rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^addra\(2),
      I1 => \^addra\(0),
      I2 => \^addra\(1),
      I3 => \rd_buf_indx.upd_rd_buf_indx__0\,
      I4 => \^addra\(3),
      O => \rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^addra\(3),
      I1 => \^addra\(1),
      I2 => \^addra\(0),
      I3 => \^addra\(2),
      I4 => \rd_buf_indx.upd_rd_buf_indx__0\,
      I5 => \^addra\(4),
      O => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EBFF"
    )
        port map (
      I0 => \not_strict_mode.bypass__0\,
      I1 => p_0_in,
      I2 => \not_strict_mode.rd_status\(0),
      I3 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      O => \rd_buf_indx.upd_rd_buf_indx__0\
    );
\rd_buf_indx.rd_buf_indx_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777F777780888888"
    )
        port map (
      I0 => \^addra\(4),
      I1 => \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0\,
      I2 => \not_strict_mode.bypass__0\,
      I3 => \not_strict_mode.rd_status\(0),
      I4 => \^not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\,
      I5 => p_0_in,
      O => \rd_buf_indx.rd_buf_indx_r[5]_i_1_n_0\
    );
\rd_buf_indx.rd_buf_indx_r[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^addra\(3),
      I1 => \^addra\(1),
      I2 => \^addra\(0),
      I3 => \^addra\(2),
      O => \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0\
    );
\rd_buf_indx.rd_buf_indx_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[0]_i_1_n_0\,
      Q => \^addra\(0),
      R => '0'
    );
\rd_buf_indx.rd_buf_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[1]_i_1_n_0\,
      Q => \^addra\(1),
      R => reset_reg
    );
\rd_buf_indx.rd_buf_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[2]_i_1_n_0\,
      Q => \^addra\(2),
      R => reset_reg
    );
\rd_buf_indx.rd_buf_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[3]_i_1_n_0\,
      Q => \^addra\(3),
      R => reset_reg
    );
\rd_buf_indx.rd_buf_indx_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0\,
      Q => \^addra\(4),
      R => reset_reg
    );
\rd_buf_indx.rd_buf_indx_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rd_buf_indx.rd_buf_indx_r[5]_i_1_n_0\,
      Q => p_0_in,
      R => reset_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ui_wr_data is
  port (
    wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_wdf_rdy : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 95 downto 0 );
    \my_empty_reg[7]_0\ : out STD_LOGIC_VECTOR ( 575 downto 0 );
    app_rdy_ns : out STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    CLK : in STD_LOGIC;
    \pointer_ram.pointer_we\ : in STD_LOGIC;
    \pointer_ram.pointer_wr_data\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ADDRD : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \cmd_pipe_plus.wr_data_addr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__22\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__21\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__20\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__19\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__18\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__17\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__16\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__15\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__14\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_ns : in STD_LOGIC;
    reset_reg : in STD_LOGIC;
    wr_accepted : in STD_LOGIC;
    \read_data_indx.rd_data_upd_indx_r_reg_0\ : in STD_LOGIC;
    \wr_req_counter.wr_req_cnt_r_reg[0]_0\ : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    \wr_req_counter.wr_req_cnt_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ui_wr_data : entity is "mig_7series_v2_3_ui_wr_data";
end mig_7series_0_mig_7series_v2_3_ui_wr_data;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ui_wr_data is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal app_rdy_r_i_2_n_0 : STD_LOGIC;
  signal app_wdf_data_r1 : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal app_wdf_end_ns1 : STD_LOGIC;
  signal app_wdf_end_r1 : STD_LOGIC;
  signal app_wdf_mask_r1 : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal app_wdf_rdy_r_copy1 : STD_LOGIC;
  signal app_wdf_rdy_r_copy2 : STD_LOGIC;
  signal app_wdf_rdy_r_copy3 : STD_LOGIC;
  signal app_wdf_wren_ns1 : STD_LOGIC;
  signal app_wdf_wren_r1 : STD_LOGIC;
  signal \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^my_empty_reg[7]_0\ : STD_LOGIC_VECTOR ( 575 downto 0 );
  signal \occupied_counter.occ_cnt[15]_i_1_n_0\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \occupied_counter.occ_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0_0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_4_in : STD_LOGIC;
  signal wb_wr_data_addr_w : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal wdf_rdy_ns : STD_LOGIC;
  signal wr_buf_out_data_w : STD_LOGIC_VECTOR ( 575 downto 0 );
  signal wr_data_pntr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \^wr_req_counter.wr_req_cnt_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \write_buffer.wr_buf_in_data\ : STD_LOGIC_VECTOR ( 575 downto 0 );
  signal \write_data_control.wb_wr_data_addr0_ns\ : STD_LOGIC;
  signal \write_data_control.wb_wr_data_addr0_r\ : STD_LOGIC;
  signal \write_data_control.wb_wr_data_addr_r\ : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal \write_data_control.wr_data_addr_le\ : STD_LOGIC;
  signal \write_data_control.wr_data_indx_r_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of app_wdf_rdy_r_copy1_reg : label is "no";
  attribute equivalent_register_removal of app_wdf_rdy_r_copy2_reg : label is "no";
  attribute equivalent_register_removal of app_wdf_rdy_r_copy3_reg : label is "no";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \occupied_counter.app_wdf_rdy_r_i_2\ : label is "soft_lutpair1051";
  attribute equivalent_register_removal of \occupied_counter.app_wdf_rdy_r_reg\ : label is "no";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[0]_i_1\ : label is "soft_lutpair1052";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[13]_i_1\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[15]_i_2\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[2]_i_1\ : label is "soft_lutpair1052";
  attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[9]_i_1\ : label is "soft_lutpair1051";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \pointer_ram.rams[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \pointer_ram.rams[1].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[0]_i_1\ : label is "soft_lutpair1058";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[1]_i_1\ : label is "soft_lutpair1058";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[2]_i_1\ : label is "soft_lutpair1054";
  attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[3]_i_1\ : label is "soft_lutpair1054";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[0].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[10].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[11].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[12].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[13].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[14].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[15].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[16].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[17].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[18].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[19].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[1].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[20].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[21].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[22].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[23].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[24].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[25].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[26].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[27].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[28].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[29].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[2].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[30].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[31].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[32].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[33].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[34].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[35].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[36].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[37].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[38].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[39].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[3].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[40].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[41].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[42].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[43].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[44].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[45].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[46].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[47].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[48].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[49].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[4].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[50].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[51].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[52].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[53].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[54].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[55].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[56].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[57].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[58].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[59].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[5].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[60].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[61].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[62].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[63].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[64].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[65].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[66].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[67].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[68].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[69].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[6].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[70].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[71].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[72].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[73].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[74].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[75].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[76].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[77].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[78].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[79].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[7].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[80].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[81].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[82].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[83].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[84].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[85].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[86].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[87].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[88].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[89].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[8].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[90].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[91].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[92].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[93].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[94].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[95].RAM32M0\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \write_buffer.wr_buffer_ram[9].RAM32M0\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[2]_i_1\ : label is "soft_lutpair1056";
  attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[3]_i_2\ : label is "soft_lutpair1056";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  \my_empty_reg[7]_0\(575 downto 0) <= \^my_empty_reg[7]_0\(575 downto 0);
  p_0_in(0) <= \^p_0_in\(0);
  \wr_req_counter.wr_req_cnt_r_reg[1]_0\(1 downto 0) <= \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1 downto 0);
app_rdy_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44440444"
    )
        port map (
      I0 => D(0),
      I1 => accept_ns,
      I2 => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\,
      I3 => app_rdy_r_i_2_n_0,
      I4 => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\,
      O => app_rdy_ns
    );
app_rdy_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000400040001"
    )
        port map (
      I0 => reset_reg,
      I1 => \^p_0_in\(0),
      I2 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I3 => \wr_req_counter.wr_req_cnt_r\(2),
      I4 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I5 => wr_accepted,
      O => app_rdy_r_i_2_n_0
    );
\app_wdf_data_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(0),
      Q => app_wdf_data_r1(0),
      R => '0'
    );
\app_wdf_data_r1_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(100),
      Q => app_wdf_data_r1(100),
      R => '0'
    );
\app_wdf_data_r1_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(101),
      Q => app_wdf_data_r1(101),
      R => '0'
    );
\app_wdf_data_r1_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(102),
      Q => app_wdf_data_r1(102),
      R => '0'
    );
\app_wdf_data_r1_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(103),
      Q => app_wdf_data_r1(103),
      R => '0'
    );
\app_wdf_data_r1_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(104),
      Q => app_wdf_data_r1(104),
      R => '0'
    );
\app_wdf_data_r1_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(105),
      Q => app_wdf_data_r1(105),
      R => '0'
    );
\app_wdf_data_r1_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(106),
      Q => app_wdf_data_r1(106),
      R => '0'
    );
\app_wdf_data_r1_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(107),
      Q => app_wdf_data_r1(107),
      R => '0'
    );
\app_wdf_data_r1_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(108),
      Q => app_wdf_data_r1(108),
      R => '0'
    );
\app_wdf_data_r1_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(109),
      Q => app_wdf_data_r1(109),
      R => '0'
    );
\app_wdf_data_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(10),
      Q => app_wdf_data_r1(10),
      R => '0'
    );
\app_wdf_data_r1_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(110),
      Q => app_wdf_data_r1(110),
      R => '0'
    );
\app_wdf_data_r1_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(111),
      Q => app_wdf_data_r1(111),
      R => '0'
    );
\app_wdf_data_r1_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(112),
      Q => app_wdf_data_r1(112),
      R => '0'
    );
\app_wdf_data_r1_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(113),
      Q => app_wdf_data_r1(113),
      R => '0'
    );
\app_wdf_data_r1_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(114),
      Q => app_wdf_data_r1(114),
      R => '0'
    );
\app_wdf_data_r1_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(115),
      Q => app_wdf_data_r1(115),
      R => '0'
    );
\app_wdf_data_r1_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(116),
      Q => app_wdf_data_r1(116),
      R => '0'
    );
\app_wdf_data_r1_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(117),
      Q => app_wdf_data_r1(117),
      R => '0'
    );
\app_wdf_data_r1_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(118),
      Q => app_wdf_data_r1(118),
      R => '0'
    );
\app_wdf_data_r1_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(119),
      Q => app_wdf_data_r1(119),
      R => '0'
    );
\app_wdf_data_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(11),
      Q => app_wdf_data_r1(11),
      R => '0'
    );
\app_wdf_data_r1_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(120),
      Q => app_wdf_data_r1(120),
      R => '0'
    );
\app_wdf_data_r1_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(121),
      Q => app_wdf_data_r1(121),
      R => '0'
    );
\app_wdf_data_r1_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(122),
      Q => app_wdf_data_r1(122),
      R => '0'
    );
\app_wdf_data_r1_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(123),
      Q => app_wdf_data_r1(123),
      R => '0'
    );
\app_wdf_data_r1_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(124),
      Q => app_wdf_data_r1(124),
      R => '0'
    );
\app_wdf_data_r1_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(125),
      Q => app_wdf_data_r1(125),
      R => '0'
    );
\app_wdf_data_r1_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(126),
      Q => app_wdf_data_r1(126),
      R => '0'
    );
\app_wdf_data_r1_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(127),
      Q => app_wdf_data_r1(127),
      R => '0'
    );
\app_wdf_data_r1_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(128),
      Q => app_wdf_data_r1(128),
      R => '0'
    );
\app_wdf_data_r1_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(129),
      Q => app_wdf_data_r1(129),
      R => '0'
    );
\app_wdf_data_r1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(12),
      Q => app_wdf_data_r1(12),
      R => '0'
    );
\app_wdf_data_r1_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(130),
      Q => app_wdf_data_r1(130),
      R => '0'
    );
\app_wdf_data_r1_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(131),
      Q => app_wdf_data_r1(131),
      R => '0'
    );
\app_wdf_data_r1_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(132),
      Q => app_wdf_data_r1(132),
      R => '0'
    );
\app_wdf_data_r1_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(133),
      Q => app_wdf_data_r1(133),
      R => '0'
    );
\app_wdf_data_r1_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(134),
      Q => app_wdf_data_r1(134),
      R => '0'
    );
\app_wdf_data_r1_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(135),
      Q => app_wdf_data_r1(135),
      R => '0'
    );
\app_wdf_data_r1_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(136),
      Q => app_wdf_data_r1(136),
      R => '0'
    );
\app_wdf_data_r1_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(137),
      Q => app_wdf_data_r1(137),
      R => '0'
    );
\app_wdf_data_r1_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(138),
      Q => app_wdf_data_r1(138),
      R => '0'
    );
\app_wdf_data_r1_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(139),
      Q => app_wdf_data_r1(139),
      R => '0'
    );
\app_wdf_data_r1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(13),
      Q => app_wdf_data_r1(13),
      R => '0'
    );
\app_wdf_data_r1_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(140),
      Q => app_wdf_data_r1(140),
      R => '0'
    );
\app_wdf_data_r1_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(141),
      Q => app_wdf_data_r1(141),
      R => '0'
    );
\app_wdf_data_r1_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(142),
      Q => app_wdf_data_r1(142),
      R => '0'
    );
\app_wdf_data_r1_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(143),
      Q => app_wdf_data_r1(143),
      R => '0'
    );
\app_wdf_data_r1_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(144),
      Q => app_wdf_data_r1(144),
      R => '0'
    );
\app_wdf_data_r1_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(145),
      Q => app_wdf_data_r1(145),
      R => '0'
    );
\app_wdf_data_r1_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(146),
      Q => app_wdf_data_r1(146),
      R => '0'
    );
\app_wdf_data_r1_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(147),
      Q => app_wdf_data_r1(147),
      R => '0'
    );
\app_wdf_data_r1_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(148),
      Q => app_wdf_data_r1(148),
      R => '0'
    );
\app_wdf_data_r1_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(149),
      Q => app_wdf_data_r1(149),
      R => '0'
    );
\app_wdf_data_r1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(14),
      Q => app_wdf_data_r1(14),
      R => '0'
    );
\app_wdf_data_r1_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(150),
      Q => app_wdf_data_r1(150),
      R => '0'
    );
\app_wdf_data_r1_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(151),
      Q => app_wdf_data_r1(151),
      R => '0'
    );
\app_wdf_data_r1_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(152),
      Q => app_wdf_data_r1(152),
      R => '0'
    );
\app_wdf_data_r1_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(153),
      Q => app_wdf_data_r1(153),
      R => '0'
    );
\app_wdf_data_r1_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(154),
      Q => app_wdf_data_r1(154),
      R => '0'
    );
\app_wdf_data_r1_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(155),
      Q => app_wdf_data_r1(155),
      R => '0'
    );
\app_wdf_data_r1_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(156),
      Q => app_wdf_data_r1(156),
      R => '0'
    );
\app_wdf_data_r1_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(157),
      Q => app_wdf_data_r1(157),
      R => '0'
    );
\app_wdf_data_r1_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(158),
      Q => app_wdf_data_r1(158),
      R => '0'
    );
\app_wdf_data_r1_reg[159]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(159),
      Q => app_wdf_data_r1(159),
      R => '0'
    );
\app_wdf_data_r1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(15),
      Q => app_wdf_data_r1(15),
      R => '0'
    );
\app_wdf_data_r1_reg[160]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(160),
      Q => app_wdf_data_r1(160),
      R => '0'
    );
\app_wdf_data_r1_reg[161]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(161),
      Q => app_wdf_data_r1(161),
      R => '0'
    );
\app_wdf_data_r1_reg[162]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(162),
      Q => app_wdf_data_r1(162),
      R => '0'
    );
\app_wdf_data_r1_reg[163]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(163),
      Q => app_wdf_data_r1(163),
      R => '0'
    );
\app_wdf_data_r1_reg[164]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(164),
      Q => app_wdf_data_r1(164),
      R => '0'
    );
\app_wdf_data_r1_reg[165]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(165),
      Q => app_wdf_data_r1(165),
      R => '0'
    );
\app_wdf_data_r1_reg[166]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(166),
      Q => app_wdf_data_r1(166),
      R => '0'
    );
\app_wdf_data_r1_reg[167]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(167),
      Q => app_wdf_data_r1(167),
      R => '0'
    );
\app_wdf_data_r1_reg[168]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(168),
      Q => app_wdf_data_r1(168),
      R => '0'
    );
\app_wdf_data_r1_reg[169]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(169),
      Q => app_wdf_data_r1(169),
      R => '0'
    );
\app_wdf_data_r1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(16),
      Q => app_wdf_data_r1(16),
      R => '0'
    );
\app_wdf_data_r1_reg[170]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(170),
      Q => app_wdf_data_r1(170),
      R => '0'
    );
\app_wdf_data_r1_reg[171]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(171),
      Q => app_wdf_data_r1(171),
      R => '0'
    );
\app_wdf_data_r1_reg[172]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(172),
      Q => app_wdf_data_r1(172),
      R => '0'
    );
\app_wdf_data_r1_reg[173]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(173),
      Q => app_wdf_data_r1(173),
      R => '0'
    );
\app_wdf_data_r1_reg[174]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(174),
      Q => app_wdf_data_r1(174),
      R => '0'
    );
\app_wdf_data_r1_reg[175]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(175),
      Q => app_wdf_data_r1(175),
      R => '0'
    );
\app_wdf_data_r1_reg[176]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(176),
      Q => app_wdf_data_r1(176),
      R => '0'
    );
\app_wdf_data_r1_reg[177]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(177),
      Q => app_wdf_data_r1(177),
      R => '0'
    );
\app_wdf_data_r1_reg[178]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(178),
      Q => app_wdf_data_r1(178),
      R => '0'
    );
\app_wdf_data_r1_reg[179]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(179),
      Q => app_wdf_data_r1(179),
      R => '0'
    );
\app_wdf_data_r1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(17),
      Q => app_wdf_data_r1(17),
      R => '0'
    );
\app_wdf_data_r1_reg[180]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(180),
      Q => app_wdf_data_r1(180),
      R => '0'
    );
\app_wdf_data_r1_reg[181]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(181),
      Q => app_wdf_data_r1(181),
      R => '0'
    );
\app_wdf_data_r1_reg[182]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(182),
      Q => app_wdf_data_r1(182),
      R => '0'
    );
\app_wdf_data_r1_reg[183]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(183),
      Q => app_wdf_data_r1(183),
      R => '0'
    );
\app_wdf_data_r1_reg[184]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(184),
      Q => app_wdf_data_r1(184),
      R => '0'
    );
\app_wdf_data_r1_reg[185]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(185),
      Q => app_wdf_data_r1(185),
      R => '0'
    );
\app_wdf_data_r1_reg[186]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(186),
      Q => app_wdf_data_r1(186),
      R => '0'
    );
\app_wdf_data_r1_reg[187]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(187),
      Q => app_wdf_data_r1(187),
      R => '0'
    );
\app_wdf_data_r1_reg[188]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(188),
      Q => app_wdf_data_r1(188),
      R => '0'
    );
\app_wdf_data_r1_reg[189]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(189),
      Q => app_wdf_data_r1(189),
      R => '0'
    );
\app_wdf_data_r1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(18),
      Q => app_wdf_data_r1(18),
      R => '0'
    );
\app_wdf_data_r1_reg[190]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(190),
      Q => app_wdf_data_r1(190),
      R => '0'
    );
\app_wdf_data_r1_reg[191]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(191),
      Q => app_wdf_data_r1(191),
      R => '0'
    );
\app_wdf_data_r1_reg[192]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(192),
      Q => app_wdf_data_r1(192),
      R => '0'
    );
\app_wdf_data_r1_reg[193]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(193),
      Q => app_wdf_data_r1(193),
      R => '0'
    );
\app_wdf_data_r1_reg[194]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(194),
      Q => app_wdf_data_r1(194),
      R => '0'
    );
\app_wdf_data_r1_reg[195]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(195),
      Q => app_wdf_data_r1(195),
      R => '0'
    );
\app_wdf_data_r1_reg[196]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(196),
      Q => app_wdf_data_r1(196),
      R => '0'
    );
\app_wdf_data_r1_reg[197]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(197),
      Q => app_wdf_data_r1(197),
      R => '0'
    );
\app_wdf_data_r1_reg[198]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(198),
      Q => app_wdf_data_r1(198),
      R => '0'
    );
\app_wdf_data_r1_reg[199]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(199),
      Q => app_wdf_data_r1(199),
      R => '0'
    );
\app_wdf_data_r1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(19),
      Q => app_wdf_data_r1(19),
      R => '0'
    );
\app_wdf_data_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(1),
      Q => app_wdf_data_r1(1),
      R => '0'
    );
\app_wdf_data_r1_reg[200]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(200),
      Q => app_wdf_data_r1(200),
      R => '0'
    );
\app_wdf_data_r1_reg[201]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(201),
      Q => app_wdf_data_r1(201),
      R => '0'
    );
\app_wdf_data_r1_reg[202]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(202),
      Q => app_wdf_data_r1(202),
      R => '0'
    );
\app_wdf_data_r1_reg[203]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(203),
      Q => app_wdf_data_r1(203),
      R => '0'
    );
\app_wdf_data_r1_reg[204]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(204),
      Q => app_wdf_data_r1(204),
      R => '0'
    );
\app_wdf_data_r1_reg[205]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(205),
      Q => app_wdf_data_r1(205),
      R => '0'
    );
\app_wdf_data_r1_reg[206]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(206),
      Q => app_wdf_data_r1(206),
      R => '0'
    );
\app_wdf_data_r1_reg[207]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(207),
      Q => app_wdf_data_r1(207),
      R => '0'
    );
\app_wdf_data_r1_reg[208]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(208),
      Q => app_wdf_data_r1(208),
      R => '0'
    );
\app_wdf_data_r1_reg[209]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(209),
      Q => app_wdf_data_r1(209),
      R => '0'
    );
\app_wdf_data_r1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(20),
      Q => app_wdf_data_r1(20),
      R => '0'
    );
\app_wdf_data_r1_reg[210]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(210),
      Q => app_wdf_data_r1(210),
      R => '0'
    );
\app_wdf_data_r1_reg[211]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(211),
      Q => app_wdf_data_r1(211),
      R => '0'
    );
\app_wdf_data_r1_reg[212]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(212),
      Q => app_wdf_data_r1(212),
      R => '0'
    );
\app_wdf_data_r1_reg[213]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(213),
      Q => app_wdf_data_r1(213),
      R => '0'
    );
\app_wdf_data_r1_reg[214]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(214),
      Q => app_wdf_data_r1(214),
      R => '0'
    );
\app_wdf_data_r1_reg[215]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(215),
      Q => app_wdf_data_r1(215),
      R => '0'
    );
\app_wdf_data_r1_reg[216]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(216),
      Q => app_wdf_data_r1(216),
      R => '0'
    );
\app_wdf_data_r1_reg[217]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(217),
      Q => app_wdf_data_r1(217),
      R => '0'
    );
\app_wdf_data_r1_reg[218]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(218),
      Q => app_wdf_data_r1(218),
      R => '0'
    );
\app_wdf_data_r1_reg[219]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(219),
      Q => app_wdf_data_r1(219),
      R => '0'
    );
\app_wdf_data_r1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(21),
      Q => app_wdf_data_r1(21),
      R => '0'
    );
\app_wdf_data_r1_reg[220]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(220),
      Q => app_wdf_data_r1(220),
      R => '0'
    );
\app_wdf_data_r1_reg[221]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(221),
      Q => app_wdf_data_r1(221),
      R => '0'
    );
\app_wdf_data_r1_reg[222]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(222),
      Q => app_wdf_data_r1(222),
      R => '0'
    );
\app_wdf_data_r1_reg[223]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(223),
      Q => app_wdf_data_r1(223),
      R => '0'
    );
\app_wdf_data_r1_reg[224]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(224),
      Q => app_wdf_data_r1(224),
      R => '0'
    );
\app_wdf_data_r1_reg[225]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(225),
      Q => app_wdf_data_r1(225),
      R => '0'
    );
\app_wdf_data_r1_reg[226]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(226),
      Q => app_wdf_data_r1(226),
      R => '0'
    );
\app_wdf_data_r1_reg[227]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(227),
      Q => app_wdf_data_r1(227),
      R => '0'
    );
\app_wdf_data_r1_reg[228]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(228),
      Q => app_wdf_data_r1(228),
      R => '0'
    );
\app_wdf_data_r1_reg[229]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(229),
      Q => app_wdf_data_r1(229),
      R => '0'
    );
\app_wdf_data_r1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(22),
      Q => app_wdf_data_r1(22),
      R => '0'
    );
\app_wdf_data_r1_reg[230]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(230),
      Q => app_wdf_data_r1(230),
      R => '0'
    );
\app_wdf_data_r1_reg[231]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(231),
      Q => app_wdf_data_r1(231),
      R => '0'
    );
\app_wdf_data_r1_reg[232]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(232),
      Q => app_wdf_data_r1(232),
      R => '0'
    );
\app_wdf_data_r1_reg[233]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(233),
      Q => app_wdf_data_r1(233),
      R => '0'
    );
\app_wdf_data_r1_reg[234]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(234),
      Q => app_wdf_data_r1(234),
      R => '0'
    );
\app_wdf_data_r1_reg[235]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(235),
      Q => app_wdf_data_r1(235),
      R => '0'
    );
\app_wdf_data_r1_reg[236]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(236),
      Q => app_wdf_data_r1(236),
      R => '0'
    );
\app_wdf_data_r1_reg[237]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(237),
      Q => app_wdf_data_r1(237),
      R => '0'
    );
\app_wdf_data_r1_reg[238]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(238),
      Q => app_wdf_data_r1(238),
      R => '0'
    );
\app_wdf_data_r1_reg[239]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(239),
      Q => app_wdf_data_r1(239),
      R => '0'
    );
\app_wdf_data_r1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(23),
      Q => app_wdf_data_r1(23),
      R => '0'
    );
\app_wdf_data_r1_reg[240]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(240),
      Q => app_wdf_data_r1(240),
      R => '0'
    );
\app_wdf_data_r1_reg[241]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(241),
      Q => app_wdf_data_r1(241),
      R => '0'
    );
\app_wdf_data_r1_reg[242]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(242),
      Q => app_wdf_data_r1(242),
      R => '0'
    );
\app_wdf_data_r1_reg[243]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(243),
      Q => app_wdf_data_r1(243),
      R => '0'
    );
\app_wdf_data_r1_reg[244]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(244),
      Q => app_wdf_data_r1(244),
      R => '0'
    );
\app_wdf_data_r1_reg[245]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(245),
      Q => app_wdf_data_r1(245),
      R => '0'
    );
\app_wdf_data_r1_reg[246]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(246),
      Q => app_wdf_data_r1(246),
      R => '0'
    );
\app_wdf_data_r1_reg[247]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(247),
      Q => app_wdf_data_r1(247),
      R => '0'
    );
\app_wdf_data_r1_reg[248]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(248),
      Q => app_wdf_data_r1(248),
      R => '0'
    );
\app_wdf_data_r1_reg[249]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(249),
      Q => app_wdf_data_r1(249),
      R => '0'
    );
\app_wdf_data_r1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(24),
      Q => app_wdf_data_r1(24),
      R => '0'
    );
\app_wdf_data_r1_reg[250]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(250),
      Q => app_wdf_data_r1(250),
      R => '0'
    );
\app_wdf_data_r1_reg[251]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(251),
      Q => app_wdf_data_r1(251),
      R => '0'
    );
\app_wdf_data_r1_reg[252]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(252),
      Q => app_wdf_data_r1(252),
      R => '0'
    );
\app_wdf_data_r1_reg[253]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(253),
      Q => app_wdf_data_r1(253),
      R => '0'
    );
\app_wdf_data_r1_reg[254]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(254),
      Q => app_wdf_data_r1(254),
      R => '0'
    );
\app_wdf_data_r1_reg[255]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(255),
      Q => app_wdf_data_r1(255),
      R => '0'
    );
\app_wdf_data_r1_reg[256]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(256),
      Q => app_wdf_data_r1(256),
      R => '0'
    );
\app_wdf_data_r1_reg[257]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(257),
      Q => app_wdf_data_r1(257),
      R => '0'
    );
\app_wdf_data_r1_reg[258]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(258),
      Q => app_wdf_data_r1(258),
      R => '0'
    );
\app_wdf_data_r1_reg[259]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(259),
      Q => app_wdf_data_r1(259),
      R => '0'
    );
\app_wdf_data_r1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(25),
      Q => app_wdf_data_r1(25),
      R => '0'
    );
\app_wdf_data_r1_reg[260]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(260),
      Q => app_wdf_data_r1(260),
      R => '0'
    );
\app_wdf_data_r1_reg[261]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(261),
      Q => app_wdf_data_r1(261),
      R => '0'
    );
\app_wdf_data_r1_reg[262]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(262),
      Q => app_wdf_data_r1(262),
      R => '0'
    );
\app_wdf_data_r1_reg[263]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(263),
      Q => app_wdf_data_r1(263),
      R => '0'
    );
\app_wdf_data_r1_reg[264]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(264),
      Q => app_wdf_data_r1(264),
      R => '0'
    );
\app_wdf_data_r1_reg[265]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(265),
      Q => app_wdf_data_r1(265),
      R => '0'
    );
\app_wdf_data_r1_reg[266]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(266),
      Q => app_wdf_data_r1(266),
      R => '0'
    );
\app_wdf_data_r1_reg[267]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(267),
      Q => app_wdf_data_r1(267),
      R => '0'
    );
\app_wdf_data_r1_reg[268]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(268),
      Q => app_wdf_data_r1(268),
      R => '0'
    );
\app_wdf_data_r1_reg[269]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(269),
      Q => app_wdf_data_r1(269),
      R => '0'
    );
\app_wdf_data_r1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(26),
      Q => app_wdf_data_r1(26),
      R => '0'
    );
\app_wdf_data_r1_reg[270]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(270),
      Q => app_wdf_data_r1(270),
      R => '0'
    );
\app_wdf_data_r1_reg[271]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(271),
      Q => app_wdf_data_r1(271),
      R => '0'
    );
\app_wdf_data_r1_reg[272]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(272),
      Q => app_wdf_data_r1(272),
      R => '0'
    );
\app_wdf_data_r1_reg[273]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(273),
      Q => app_wdf_data_r1(273),
      R => '0'
    );
\app_wdf_data_r1_reg[274]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(274),
      Q => app_wdf_data_r1(274),
      R => '0'
    );
\app_wdf_data_r1_reg[275]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(275),
      Q => app_wdf_data_r1(275),
      R => '0'
    );
\app_wdf_data_r1_reg[276]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(276),
      Q => app_wdf_data_r1(276),
      R => '0'
    );
\app_wdf_data_r1_reg[277]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(277),
      Q => app_wdf_data_r1(277),
      R => '0'
    );
\app_wdf_data_r1_reg[278]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(278),
      Q => app_wdf_data_r1(278),
      R => '0'
    );
\app_wdf_data_r1_reg[279]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(279),
      Q => app_wdf_data_r1(279),
      R => '0'
    );
\app_wdf_data_r1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(27),
      Q => app_wdf_data_r1(27),
      R => '0'
    );
\app_wdf_data_r1_reg[280]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(280),
      Q => app_wdf_data_r1(280),
      R => '0'
    );
\app_wdf_data_r1_reg[281]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(281),
      Q => app_wdf_data_r1(281),
      R => '0'
    );
\app_wdf_data_r1_reg[282]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(282),
      Q => app_wdf_data_r1(282),
      R => '0'
    );
\app_wdf_data_r1_reg[283]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(283),
      Q => app_wdf_data_r1(283),
      R => '0'
    );
\app_wdf_data_r1_reg[284]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(284),
      Q => app_wdf_data_r1(284),
      R => '0'
    );
\app_wdf_data_r1_reg[285]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(285),
      Q => app_wdf_data_r1(285),
      R => '0'
    );
\app_wdf_data_r1_reg[286]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(286),
      Q => app_wdf_data_r1(286),
      R => '0'
    );
\app_wdf_data_r1_reg[287]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(287),
      Q => app_wdf_data_r1(287),
      R => '0'
    );
\app_wdf_data_r1_reg[288]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(288),
      Q => app_wdf_data_r1(288),
      R => '0'
    );
\app_wdf_data_r1_reg[289]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(289),
      Q => app_wdf_data_r1(289),
      R => '0'
    );
\app_wdf_data_r1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(28),
      Q => app_wdf_data_r1(28),
      R => '0'
    );
\app_wdf_data_r1_reg[290]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(290),
      Q => app_wdf_data_r1(290),
      R => '0'
    );
\app_wdf_data_r1_reg[291]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(291),
      Q => app_wdf_data_r1(291),
      R => '0'
    );
\app_wdf_data_r1_reg[292]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(292),
      Q => app_wdf_data_r1(292),
      R => '0'
    );
\app_wdf_data_r1_reg[293]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(293),
      Q => app_wdf_data_r1(293),
      R => '0'
    );
\app_wdf_data_r1_reg[294]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(294),
      Q => app_wdf_data_r1(294),
      R => '0'
    );
\app_wdf_data_r1_reg[295]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(295),
      Q => app_wdf_data_r1(295),
      R => '0'
    );
\app_wdf_data_r1_reg[296]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(296),
      Q => app_wdf_data_r1(296),
      R => '0'
    );
\app_wdf_data_r1_reg[297]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(297),
      Q => app_wdf_data_r1(297),
      R => '0'
    );
\app_wdf_data_r1_reg[298]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(298),
      Q => app_wdf_data_r1(298),
      R => '0'
    );
\app_wdf_data_r1_reg[299]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(299),
      Q => app_wdf_data_r1(299),
      R => '0'
    );
\app_wdf_data_r1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(29),
      Q => app_wdf_data_r1(29),
      R => '0'
    );
\app_wdf_data_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(2),
      Q => app_wdf_data_r1(2),
      R => '0'
    );
\app_wdf_data_r1_reg[300]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(300),
      Q => app_wdf_data_r1(300),
      R => '0'
    );
\app_wdf_data_r1_reg[301]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(301),
      Q => app_wdf_data_r1(301),
      R => '0'
    );
\app_wdf_data_r1_reg[302]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(302),
      Q => app_wdf_data_r1(302),
      R => '0'
    );
\app_wdf_data_r1_reg[303]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(303),
      Q => app_wdf_data_r1(303),
      R => '0'
    );
\app_wdf_data_r1_reg[304]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(304),
      Q => app_wdf_data_r1(304),
      R => '0'
    );
\app_wdf_data_r1_reg[305]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(305),
      Q => app_wdf_data_r1(305),
      R => '0'
    );
\app_wdf_data_r1_reg[306]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(306),
      Q => app_wdf_data_r1(306),
      R => '0'
    );
\app_wdf_data_r1_reg[307]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(307),
      Q => app_wdf_data_r1(307),
      R => '0'
    );
\app_wdf_data_r1_reg[308]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(308),
      Q => app_wdf_data_r1(308),
      R => '0'
    );
\app_wdf_data_r1_reg[309]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(309),
      Q => app_wdf_data_r1(309),
      R => '0'
    );
\app_wdf_data_r1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(30),
      Q => app_wdf_data_r1(30),
      R => '0'
    );
\app_wdf_data_r1_reg[310]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(310),
      Q => app_wdf_data_r1(310),
      R => '0'
    );
\app_wdf_data_r1_reg[311]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(311),
      Q => app_wdf_data_r1(311),
      R => '0'
    );
\app_wdf_data_r1_reg[312]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(312),
      Q => app_wdf_data_r1(312),
      R => '0'
    );
\app_wdf_data_r1_reg[313]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(313),
      Q => app_wdf_data_r1(313),
      R => '0'
    );
\app_wdf_data_r1_reg[314]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(314),
      Q => app_wdf_data_r1(314),
      R => '0'
    );
\app_wdf_data_r1_reg[315]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(315),
      Q => app_wdf_data_r1(315),
      R => '0'
    );
\app_wdf_data_r1_reg[316]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(316),
      Q => app_wdf_data_r1(316),
      R => '0'
    );
\app_wdf_data_r1_reg[317]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(317),
      Q => app_wdf_data_r1(317),
      R => '0'
    );
\app_wdf_data_r1_reg[318]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(318),
      Q => app_wdf_data_r1(318),
      R => '0'
    );
\app_wdf_data_r1_reg[319]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(319),
      Q => app_wdf_data_r1(319),
      R => '0'
    );
\app_wdf_data_r1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(31),
      Q => app_wdf_data_r1(31),
      R => '0'
    );
\app_wdf_data_r1_reg[320]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(320),
      Q => app_wdf_data_r1(320),
      R => '0'
    );
\app_wdf_data_r1_reg[321]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(321),
      Q => app_wdf_data_r1(321),
      R => '0'
    );
\app_wdf_data_r1_reg[322]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(322),
      Q => app_wdf_data_r1(322),
      R => '0'
    );
\app_wdf_data_r1_reg[323]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(323),
      Q => app_wdf_data_r1(323),
      R => '0'
    );
\app_wdf_data_r1_reg[324]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(324),
      Q => app_wdf_data_r1(324),
      R => '0'
    );
\app_wdf_data_r1_reg[325]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(325),
      Q => app_wdf_data_r1(325),
      R => '0'
    );
\app_wdf_data_r1_reg[326]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(326),
      Q => app_wdf_data_r1(326),
      R => '0'
    );
\app_wdf_data_r1_reg[327]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(327),
      Q => app_wdf_data_r1(327),
      R => '0'
    );
\app_wdf_data_r1_reg[328]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(328),
      Q => app_wdf_data_r1(328),
      R => '0'
    );
\app_wdf_data_r1_reg[329]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(329),
      Q => app_wdf_data_r1(329),
      R => '0'
    );
\app_wdf_data_r1_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(32),
      Q => app_wdf_data_r1(32),
      R => '0'
    );
\app_wdf_data_r1_reg[330]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(330),
      Q => app_wdf_data_r1(330),
      R => '0'
    );
\app_wdf_data_r1_reg[331]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(331),
      Q => app_wdf_data_r1(331),
      R => '0'
    );
\app_wdf_data_r1_reg[332]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(332),
      Q => app_wdf_data_r1(332),
      R => '0'
    );
\app_wdf_data_r1_reg[333]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(333),
      Q => app_wdf_data_r1(333),
      R => '0'
    );
\app_wdf_data_r1_reg[334]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(334),
      Q => app_wdf_data_r1(334),
      R => '0'
    );
\app_wdf_data_r1_reg[335]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(335),
      Q => app_wdf_data_r1(335),
      R => '0'
    );
\app_wdf_data_r1_reg[336]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(336),
      Q => app_wdf_data_r1(336),
      R => '0'
    );
\app_wdf_data_r1_reg[337]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(337),
      Q => app_wdf_data_r1(337),
      R => '0'
    );
\app_wdf_data_r1_reg[338]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(338),
      Q => app_wdf_data_r1(338),
      R => '0'
    );
\app_wdf_data_r1_reg[339]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(339),
      Q => app_wdf_data_r1(339),
      R => '0'
    );
\app_wdf_data_r1_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(33),
      Q => app_wdf_data_r1(33),
      R => '0'
    );
\app_wdf_data_r1_reg[340]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(340),
      Q => app_wdf_data_r1(340),
      R => '0'
    );
\app_wdf_data_r1_reg[341]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(341),
      Q => app_wdf_data_r1(341),
      R => '0'
    );
\app_wdf_data_r1_reg[342]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(342),
      Q => app_wdf_data_r1(342),
      R => '0'
    );
\app_wdf_data_r1_reg[343]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(343),
      Q => app_wdf_data_r1(343),
      R => '0'
    );
\app_wdf_data_r1_reg[344]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(344),
      Q => app_wdf_data_r1(344),
      R => '0'
    );
\app_wdf_data_r1_reg[345]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(345),
      Q => app_wdf_data_r1(345),
      R => '0'
    );
\app_wdf_data_r1_reg[346]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(346),
      Q => app_wdf_data_r1(346),
      R => '0'
    );
\app_wdf_data_r1_reg[347]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(347),
      Q => app_wdf_data_r1(347),
      R => '0'
    );
\app_wdf_data_r1_reg[348]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(348),
      Q => app_wdf_data_r1(348),
      R => '0'
    );
\app_wdf_data_r1_reg[349]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(349),
      Q => app_wdf_data_r1(349),
      R => '0'
    );
\app_wdf_data_r1_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(34),
      Q => app_wdf_data_r1(34),
      R => '0'
    );
\app_wdf_data_r1_reg[350]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(350),
      Q => app_wdf_data_r1(350),
      R => '0'
    );
\app_wdf_data_r1_reg[351]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(351),
      Q => app_wdf_data_r1(351),
      R => '0'
    );
\app_wdf_data_r1_reg[352]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(352),
      Q => app_wdf_data_r1(352),
      R => '0'
    );
\app_wdf_data_r1_reg[353]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(353),
      Q => app_wdf_data_r1(353),
      R => '0'
    );
\app_wdf_data_r1_reg[354]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(354),
      Q => app_wdf_data_r1(354),
      R => '0'
    );
\app_wdf_data_r1_reg[355]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(355),
      Q => app_wdf_data_r1(355),
      R => '0'
    );
\app_wdf_data_r1_reg[356]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(356),
      Q => app_wdf_data_r1(356),
      R => '0'
    );
\app_wdf_data_r1_reg[357]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(357),
      Q => app_wdf_data_r1(357),
      R => '0'
    );
\app_wdf_data_r1_reg[358]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(358),
      Q => app_wdf_data_r1(358),
      R => '0'
    );
\app_wdf_data_r1_reg[359]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(359),
      Q => app_wdf_data_r1(359),
      R => '0'
    );
\app_wdf_data_r1_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(35),
      Q => app_wdf_data_r1(35),
      R => '0'
    );
\app_wdf_data_r1_reg[360]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(360),
      Q => app_wdf_data_r1(360),
      R => '0'
    );
\app_wdf_data_r1_reg[361]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(361),
      Q => app_wdf_data_r1(361),
      R => '0'
    );
\app_wdf_data_r1_reg[362]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(362),
      Q => app_wdf_data_r1(362),
      R => '0'
    );
\app_wdf_data_r1_reg[363]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(363),
      Q => app_wdf_data_r1(363),
      R => '0'
    );
\app_wdf_data_r1_reg[364]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(364),
      Q => app_wdf_data_r1(364),
      R => '0'
    );
\app_wdf_data_r1_reg[365]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(365),
      Q => app_wdf_data_r1(365),
      R => '0'
    );
\app_wdf_data_r1_reg[366]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(366),
      Q => app_wdf_data_r1(366),
      R => '0'
    );
\app_wdf_data_r1_reg[367]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(367),
      Q => app_wdf_data_r1(367),
      R => '0'
    );
\app_wdf_data_r1_reg[368]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(368),
      Q => app_wdf_data_r1(368),
      R => '0'
    );
\app_wdf_data_r1_reg[369]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(369),
      Q => app_wdf_data_r1(369),
      R => '0'
    );
\app_wdf_data_r1_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(36),
      Q => app_wdf_data_r1(36),
      R => '0'
    );
\app_wdf_data_r1_reg[370]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(370),
      Q => app_wdf_data_r1(370),
      R => '0'
    );
\app_wdf_data_r1_reg[371]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(371),
      Q => app_wdf_data_r1(371),
      R => '0'
    );
\app_wdf_data_r1_reg[372]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(372),
      Q => app_wdf_data_r1(372),
      R => '0'
    );
\app_wdf_data_r1_reg[373]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(373),
      Q => app_wdf_data_r1(373),
      R => '0'
    );
\app_wdf_data_r1_reg[374]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(374),
      Q => app_wdf_data_r1(374),
      R => '0'
    );
\app_wdf_data_r1_reg[375]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(375),
      Q => app_wdf_data_r1(375),
      R => '0'
    );
\app_wdf_data_r1_reg[376]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(376),
      Q => app_wdf_data_r1(376),
      R => '0'
    );
\app_wdf_data_r1_reg[377]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(377),
      Q => app_wdf_data_r1(377),
      R => '0'
    );
\app_wdf_data_r1_reg[378]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(378),
      Q => app_wdf_data_r1(378),
      R => '0'
    );
\app_wdf_data_r1_reg[379]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(379),
      Q => app_wdf_data_r1(379),
      R => '0'
    );
\app_wdf_data_r1_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(37),
      Q => app_wdf_data_r1(37),
      R => '0'
    );
\app_wdf_data_r1_reg[380]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(380),
      Q => app_wdf_data_r1(380),
      R => '0'
    );
\app_wdf_data_r1_reg[381]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(381),
      Q => app_wdf_data_r1(381),
      R => '0'
    );
\app_wdf_data_r1_reg[382]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(382),
      Q => app_wdf_data_r1(382),
      R => '0'
    );
\app_wdf_data_r1_reg[383]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(383),
      Q => app_wdf_data_r1(383),
      R => '0'
    );
\app_wdf_data_r1_reg[384]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(384),
      Q => app_wdf_data_r1(384),
      R => '0'
    );
\app_wdf_data_r1_reg[385]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(385),
      Q => app_wdf_data_r1(385),
      R => '0'
    );
\app_wdf_data_r1_reg[386]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(386),
      Q => app_wdf_data_r1(386),
      R => '0'
    );
\app_wdf_data_r1_reg[387]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(387),
      Q => app_wdf_data_r1(387),
      R => '0'
    );
\app_wdf_data_r1_reg[388]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(388),
      Q => app_wdf_data_r1(388),
      R => '0'
    );
\app_wdf_data_r1_reg[389]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(389),
      Q => app_wdf_data_r1(389),
      R => '0'
    );
\app_wdf_data_r1_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(38),
      Q => app_wdf_data_r1(38),
      R => '0'
    );
\app_wdf_data_r1_reg[390]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(390),
      Q => app_wdf_data_r1(390),
      R => '0'
    );
\app_wdf_data_r1_reg[391]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(391),
      Q => app_wdf_data_r1(391),
      R => '0'
    );
\app_wdf_data_r1_reg[392]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(392),
      Q => app_wdf_data_r1(392),
      R => '0'
    );
\app_wdf_data_r1_reg[393]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(393),
      Q => app_wdf_data_r1(393),
      R => '0'
    );
\app_wdf_data_r1_reg[394]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(394),
      Q => app_wdf_data_r1(394),
      R => '0'
    );
\app_wdf_data_r1_reg[395]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(395),
      Q => app_wdf_data_r1(395),
      R => '0'
    );
\app_wdf_data_r1_reg[396]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(396),
      Q => app_wdf_data_r1(396),
      R => '0'
    );
\app_wdf_data_r1_reg[397]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(397),
      Q => app_wdf_data_r1(397),
      R => '0'
    );
\app_wdf_data_r1_reg[398]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(398),
      Q => app_wdf_data_r1(398),
      R => '0'
    );
\app_wdf_data_r1_reg[399]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(399),
      Q => app_wdf_data_r1(399),
      R => '0'
    );
\app_wdf_data_r1_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(39),
      Q => app_wdf_data_r1(39),
      R => '0'
    );
\app_wdf_data_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(3),
      Q => app_wdf_data_r1(3),
      R => '0'
    );
\app_wdf_data_r1_reg[400]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(400),
      Q => app_wdf_data_r1(400),
      R => '0'
    );
\app_wdf_data_r1_reg[401]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(401),
      Q => app_wdf_data_r1(401),
      R => '0'
    );
\app_wdf_data_r1_reg[402]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(402),
      Q => app_wdf_data_r1(402),
      R => '0'
    );
\app_wdf_data_r1_reg[403]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(403),
      Q => app_wdf_data_r1(403),
      R => '0'
    );
\app_wdf_data_r1_reg[404]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(404),
      Q => app_wdf_data_r1(404),
      R => '0'
    );
\app_wdf_data_r1_reg[405]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(405),
      Q => app_wdf_data_r1(405),
      R => '0'
    );
\app_wdf_data_r1_reg[406]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(406),
      Q => app_wdf_data_r1(406),
      R => '0'
    );
\app_wdf_data_r1_reg[407]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(407),
      Q => app_wdf_data_r1(407),
      R => '0'
    );
\app_wdf_data_r1_reg[408]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(408),
      Q => app_wdf_data_r1(408),
      R => '0'
    );
\app_wdf_data_r1_reg[409]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(409),
      Q => app_wdf_data_r1(409),
      R => '0'
    );
\app_wdf_data_r1_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(40),
      Q => app_wdf_data_r1(40),
      R => '0'
    );
\app_wdf_data_r1_reg[410]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(410),
      Q => app_wdf_data_r1(410),
      R => '0'
    );
\app_wdf_data_r1_reg[411]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(411),
      Q => app_wdf_data_r1(411),
      R => '0'
    );
\app_wdf_data_r1_reg[412]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(412),
      Q => app_wdf_data_r1(412),
      R => '0'
    );
\app_wdf_data_r1_reg[413]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(413),
      Q => app_wdf_data_r1(413),
      R => '0'
    );
\app_wdf_data_r1_reg[414]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(414),
      Q => app_wdf_data_r1(414),
      R => '0'
    );
\app_wdf_data_r1_reg[415]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(415),
      Q => app_wdf_data_r1(415),
      R => '0'
    );
\app_wdf_data_r1_reg[416]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(416),
      Q => app_wdf_data_r1(416),
      R => '0'
    );
\app_wdf_data_r1_reg[417]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(417),
      Q => app_wdf_data_r1(417),
      R => '0'
    );
\app_wdf_data_r1_reg[418]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(418),
      Q => app_wdf_data_r1(418),
      R => '0'
    );
\app_wdf_data_r1_reg[419]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(419),
      Q => app_wdf_data_r1(419),
      R => '0'
    );
\app_wdf_data_r1_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(41),
      Q => app_wdf_data_r1(41),
      R => '0'
    );
\app_wdf_data_r1_reg[420]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(420),
      Q => app_wdf_data_r1(420),
      R => '0'
    );
\app_wdf_data_r1_reg[421]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(421),
      Q => app_wdf_data_r1(421),
      R => '0'
    );
\app_wdf_data_r1_reg[422]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(422),
      Q => app_wdf_data_r1(422),
      R => '0'
    );
\app_wdf_data_r1_reg[423]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(423),
      Q => app_wdf_data_r1(423),
      R => '0'
    );
\app_wdf_data_r1_reg[424]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(424),
      Q => app_wdf_data_r1(424),
      R => '0'
    );
\app_wdf_data_r1_reg[425]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(425),
      Q => app_wdf_data_r1(425),
      R => '0'
    );
\app_wdf_data_r1_reg[426]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(426),
      Q => app_wdf_data_r1(426),
      R => '0'
    );
\app_wdf_data_r1_reg[427]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(427),
      Q => app_wdf_data_r1(427),
      R => '0'
    );
\app_wdf_data_r1_reg[428]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(428),
      Q => app_wdf_data_r1(428),
      R => '0'
    );
\app_wdf_data_r1_reg[429]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(429),
      Q => app_wdf_data_r1(429),
      R => '0'
    );
\app_wdf_data_r1_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(42),
      Q => app_wdf_data_r1(42),
      R => '0'
    );
\app_wdf_data_r1_reg[430]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(430),
      Q => app_wdf_data_r1(430),
      R => '0'
    );
\app_wdf_data_r1_reg[431]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(431),
      Q => app_wdf_data_r1(431),
      R => '0'
    );
\app_wdf_data_r1_reg[432]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(432),
      Q => app_wdf_data_r1(432),
      R => '0'
    );
\app_wdf_data_r1_reg[433]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(433),
      Q => app_wdf_data_r1(433),
      R => '0'
    );
\app_wdf_data_r1_reg[434]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(434),
      Q => app_wdf_data_r1(434),
      R => '0'
    );
\app_wdf_data_r1_reg[435]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(435),
      Q => app_wdf_data_r1(435),
      R => '0'
    );
\app_wdf_data_r1_reg[436]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(436),
      Q => app_wdf_data_r1(436),
      R => '0'
    );
\app_wdf_data_r1_reg[437]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(437),
      Q => app_wdf_data_r1(437),
      R => '0'
    );
\app_wdf_data_r1_reg[438]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(438),
      Q => app_wdf_data_r1(438),
      R => '0'
    );
\app_wdf_data_r1_reg[439]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(439),
      Q => app_wdf_data_r1(439),
      R => '0'
    );
\app_wdf_data_r1_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(43),
      Q => app_wdf_data_r1(43),
      R => '0'
    );
\app_wdf_data_r1_reg[440]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(440),
      Q => app_wdf_data_r1(440),
      R => '0'
    );
\app_wdf_data_r1_reg[441]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(441),
      Q => app_wdf_data_r1(441),
      R => '0'
    );
\app_wdf_data_r1_reg[442]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(442),
      Q => app_wdf_data_r1(442),
      R => '0'
    );
\app_wdf_data_r1_reg[443]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(443),
      Q => app_wdf_data_r1(443),
      R => '0'
    );
\app_wdf_data_r1_reg[444]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(444),
      Q => app_wdf_data_r1(444),
      R => '0'
    );
\app_wdf_data_r1_reg[445]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(445),
      Q => app_wdf_data_r1(445),
      R => '0'
    );
\app_wdf_data_r1_reg[446]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(446),
      Q => app_wdf_data_r1(446),
      R => '0'
    );
\app_wdf_data_r1_reg[447]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(447),
      Q => app_wdf_data_r1(447),
      R => '0'
    );
\app_wdf_data_r1_reg[448]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(448),
      Q => app_wdf_data_r1(448),
      R => '0'
    );
\app_wdf_data_r1_reg[449]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(449),
      Q => app_wdf_data_r1(449),
      R => '0'
    );
\app_wdf_data_r1_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(44),
      Q => app_wdf_data_r1(44),
      R => '0'
    );
\app_wdf_data_r1_reg[450]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(450),
      Q => app_wdf_data_r1(450),
      R => '0'
    );
\app_wdf_data_r1_reg[451]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(451),
      Q => app_wdf_data_r1(451),
      R => '0'
    );
\app_wdf_data_r1_reg[452]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(452),
      Q => app_wdf_data_r1(452),
      R => '0'
    );
\app_wdf_data_r1_reg[453]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(453),
      Q => app_wdf_data_r1(453),
      R => '0'
    );
\app_wdf_data_r1_reg[454]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(454),
      Q => app_wdf_data_r1(454),
      R => '0'
    );
\app_wdf_data_r1_reg[455]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(455),
      Q => app_wdf_data_r1(455),
      R => '0'
    );
\app_wdf_data_r1_reg[456]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(456),
      Q => app_wdf_data_r1(456),
      R => '0'
    );
\app_wdf_data_r1_reg[457]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(457),
      Q => app_wdf_data_r1(457),
      R => '0'
    );
\app_wdf_data_r1_reg[458]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(458),
      Q => app_wdf_data_r1(458),
      R => '0'
    );
\app_wdf_data_r1_reg[459]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(459),
      Q => app_wdf_data_r1(459),
      R => '0'
    );
\app_wdf_data_r1_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(45),
      Q => app_wdf_data_r1(45),
      R => '0'
    );
\app_wdf_data_r1_reg[460]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(460),
      Q => app_wdf_data_r1(460),
      R => '0'
    );
\app_wdf_data_r1_reg[461]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(461),
      Q => app_wdf_data_r1(461),
      R => '0'
    );
\app_wdf_data_r1_reg[462]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(462),
      Q => app_wdf_data_r1(462),
      R => '0'
    );
\app_wdf_data_r1_reg[463]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(463),
      Q => app_wdf_data_r1(463),
      R => '0'
    );
\app_wdf_data_r1_reg[464]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(464),
      Q => app_wdf_data_r1(464),
      R => '0'
    );
\app_wdf_data_r1_reg[465]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(465),
      Q => app_wdf_data_r1(465),
      R => '0'
    );
\app_wdf_data_r1_reg[466]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(466),
      Q => app_wdf_data_r1(466),
      R => '0'
    );
\app_wdf_data_r1_reg[467]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(467),
      Q => app_wdf_data_r1(467),
      R => '0'
    );
\app_wdf_data_r1_reg[468]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(468),
      Q => app_wdf_data_r1(468),
      R => '0'
    );
\app_wdf_data_r1_reg[469]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(469),
      Q => app_wdf_data_r1(469),
      R => '0'
    );
\app_wdf_data_r1_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(46),
      Q => app_wdf_data_r1(46),
      R => '0'
    );
\app_wdf_data_r1_reg[470]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(470),
      Q => app_wdf_data_r1(470),
      R => '0'
    );
\app_wdf_data_r1_reg[471]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(471),
      Q => app_wdf_data_r1(471),
      R => '0'
    );
\app_wdf_data_r1_reg[472]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(472),
      Q => app_wdf_data_r1(472),
      R => '0'
    );
\app_wdf_data_r1_reg[473]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(473),
      Q => app_wdf_data_r1(473),
      R => '0'
    );
\app_wdf_data_r1_reg[474]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(474),
      Q => app_wdf_data_r1(474),
      R => '0'
    );
\app_wdf_data_r1_reg[475]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(475),
      Q => app_wdf_data_r1(475),
      R => '0'
    );
\app_wdf_data_r1_reg[476]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(476),
      Q => app_wdf_data_r1(476),
      R => '0'
    );
\app_wdf_data_r1_reg[477]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(477),
      Q => app_wdf_data_r1(477),
      R => '0'
    );
\app_wdf_data_r1_reg[478]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(478),
      Q => app_wdf_data_r1(478),
      R => '0'
    );
\app_wdf_data_r1_reg[479]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(479),
      Q => app_wdf_data_r1(479),
      R => '0'
    );
\app_wdf_data_r1_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(47),
      Q => app_wdf_data_r1(47),
      R => '0'
    );
\app_wdf_data_r1_reg[480]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(480),
      Q => app_wdf_data_r1(480),
      R => '0'
    );
\app_wdf_data_r1_reg[481]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(481),
      Q => app_wdf_data_r1(481),
      R => '0'
    );
\app_wdf_data_r1_reg[482]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(482),
      Q => app_wdf_data_r1(482),
      R => '0'
    );
\app_wdf_data_r1_reg[483]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(483),
      Q => app_wdf_data_r1(483),
      R => '0'
    );
\app_wdf_data_r1_reg[484]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(484),
      Q => app_wdf_data_r1(484),
      R => '0'
    );
\app_wdf_data_r1_reg[485]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(485),
      Q => app_wdf_data_r1(485),
      R => '0'
    );
\app_wdf_data_r1_reg[486]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(486),
      Q => app_wdf_data_r1(486),
      R => '0'
    );
\app_wdf_data_r1_reg[487]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(487),
      Q => app_wdf_data_r1(487),
      R => '0'
    );
\app_wdf_data_r1_reg[488]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(488),
      Q => app_wdf_data_r1(488),
      R => '0'
    );
\app_wdf_data_r1_reg[489]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(489),
      Q => app_wdf_data_r1(489),
      R => '0'
    );
\app_wdf_data_r1_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(48),
      Q => app_wdf_data_r1(48),
      R => '0'
    );
\app_wdf_data_r1_reg[490]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(490),
      Q => app_wdf_data_r1(490),
      R => '0'
    );
\app_wdf_data_r1_reg[491]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(491),
      Q => app_wdf_data_r1(491),
      R => '0'
    );
\app_wdf_data_r1_reg[492]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(492),
      Q => app_wdf_data_r1(492),
      R => '0'
    );
\app_wdf_data_r1_reg[493]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(493),
      Q => app_wdf_data_r1(493),
      R => '0'
    );
\app_wdf_data_r1_reg[494]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(494),
      Q => app_wdf_data_r1(494),
      R => '0'
    );
\app_wdf_data_r1_reg[495]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(495),
      Q => app_wdf_data_r1(495),
      R => '0'
    );
\app_wdf_data_r1_reg[496]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(496),
      Q => app_wdf_data_r1(496),
      R => '0'
    );
\app_wdf_data_r1_reg[497]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(497),
      Q => app_wdf_data_r1(497),
      R => '0'
    );
\app_wdf_data_r1_reg[498]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(498),
      Q => app_wdf_data_r1(498),
      R => '0'
    );
\app_wdf_data_r1_reg[499]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(499),
      Q => app_wdf_data_r1(499),
      R => '0'
    );
\app_wdf_data_r1_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(49),
      Q => app_wdf_data_r1(49),
      R => '0'
    );
\app_wdf_data_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(4),
      Q => app_wdf_data_r1(4),
      R => '0'
    );
\app_wdf_data_r1_reg[500]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(500),
      Q => app_wdf_data_r1(500),
      R => '0'
    );
\app_wdf_data_r1_reg[501]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(501),
      Q => app_wdf_data_r1(501),
      R => '0'
    );
\app_wdf_data_r1_reg[502]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(502),
      Q => app_wdf_data_r1(502),
      R => '0'
    );
\app_wdf_data_r1_reg[503]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(503),
      Q => app_wdf_data_r1(503),
      R => '0'
    );
\app_wdf_data_r1_reg[504]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(504),
      Q => app_wdf_data_r1(504),
      R => '0'
    );
\app_wdf_data_r1_reg[505]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(505),
      Q => app_wdf_data_r1(505),
      R => '0'
    );
\app_wdf_data_r1_reg[506]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(506),
      Q => app_wdf_data_r1(506),
      R => '0'
    );
\app_wdf_data_r1_reg[507]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(507),
      Q => app_wdf_data_r1(507),
      R => '0'
    );
\app_wdf_data_r1_reg[508]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(508),
      Q => app_wdf_data_r1(508),
      R => '0'
    );
\app_wdf_data_r1_reg[509]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(509),
      Q => app_wdf_data_r1(509),
      R => '0'
    );
\app_wdf_data_r1_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(50),
      Q => app_wdf_data_r1(50),
      R => '0'
    );
\app_wdf_data_r1_reg[510]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(510),
      Q => app_wdf_data_r1(510),
      R => '0'
    );
\app_wdf_data_r1_reg[511]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(511),
      Q => app_wdf_data_r1(511),
      R => '0'
    );
\app_wdf_data_r1_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(51),
      Q => app_wdf_data_r1(51),
      R => '0'
    );
\app_wdf_data_r1_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(52),
      Q => app_wdf_data_r1(52),
      R => '0'
    );
\app_wdf_data_r1_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(53),
      Q => app_wdf_data_r1(53),
      R => '0'
    );
\app_wdf_data_r1_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(54),
      Q => app_wdf_data_r1(54),
      R => '0'
    );
\app_wdf_data_r1_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(55),
      Q => app_wdf_data_r1(55),
      R => '0'
    );
\app_wdf_data_r1_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(56),
      Q => app_wdf_data_r1(56),
      R => '0'
    );
\app_wdf_data_r1_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(57),
      Q => app_wdf_data_r1(57),
      R => '0'
    );
\app_wdf_data_r1_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(58),
      Q => app_wdf_data_r1(58),
      R => '0'
    );
\app_wdf_data_r1_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(59),
      Q => app_wdf_data_r1(59),
      R => '0'
    );
\app_wdf_data_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(5),
      Q => app_wdf_data_r1(5),
      R => '0'
    );
\app_wdf_data_r1_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(60),
      Q => app_wdf_data_r1(60),
      R => '0'
    );
\app_wdf_data_r1_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(61),
      Q => app_wdf_data_r1(61),
      R => '0'
    );
\app_wdf_data_r1_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(62),
      Q => app_wdf_data_r1(62),
      R => '0'
    );
\app_wdf_data_r1_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(63),
      Q => app_wdf_data_r1(63),
      R => '0'
    );
\app_wdf_data_r1_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(64),
      Q => app_wdf_data_r1(64),
      R => '0'
    );
\app_wdf_data_r1_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(65),
      Q => app_wdf_data_r1(65),
      R => '0'
    );
\app_wdf_data_r1_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(66),
      Q => app_wdf_data_r1(66),
      R => '0'
    );
\app_wdf_data_r1_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(67),
      Q => app_wdf_data_r1(67),
      R => '0'
    );
\app_wdf_data_r1_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(68),
      Q => app_wdf_data_r1(68),
      R => '0'
    );
\app_wdf_data_r1_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(69),
      Q => app_wdf_data_r1(69),
      R => '0'
    );
\app_wdf_data_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(6),
      Q => app_wdf_data_r1(6),
      R => '0'
    );
\app_wdf_data_r1_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(70),
      Q => app_wdf_data_r1(70),
      R => '0'
    );
\app_wdf_data_r1_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(71),
      Q => app_wdf_data_r1(71),
      R => '0'
    );
\app_wdf_data_r1_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(72),
      Q => app_wdf_data_r1(72),
      R => '0'
    );
\app_wdf_data_r1_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(73),
      Q => app_wdf_data_r1(73),
      R => '0'
    );
\app_wdf_data_r1_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(74),
      Q => app_wdf_data_r1(74),
      R => '0'
    );
\app_wdf_data_r1_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(75),
      Q => app_wdf_data_r1(75),
      R => '0'
    );
\app_wdf_data_r1_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(76),
      Q => app_wdf_data_r1(76),
      R => '0'
    );
\app_wdf_data_r1_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(77),
      Q => app_wdf_data_r1(77),
      R => '0'
    );
\app_wdf_data_r1_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(78),
      Q => app_wdf_data_r1(78),
      R => '0'
    );
\app_wdf_data_r1_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(79),
      Q => app_wdf_data_r1(79),
      R => '0'
    );
\app_wdf_data_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(7),
      Q => app_wdf_data_r1(7),
      R => '0'
    );
\app_wdf_data_r1_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(80),
      Q => app_wdf_data_r1(80),
      R => '0'
    );
\app_wdf_data_r1_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(81),
      Q => app_wdf_data_r1(81),
      R => '0'
    );
\app_wdf_data_r1_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(82),
      Q => app_wdf_data_r1(82),
      R => '0'
    );
\app_wdf_data_r1_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(83),
      Q => app_wdf_data_r1(83),
      R => '0'
    );
\app_wdf_data_r1_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(84),
      Q => app_wdf_data_r1(84),
      R => '0'
    );
\app_wdf_data_r1_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(85),
      Q => app_wdf_data_r1(85),
      R => '0'
    );
\app_wdf_data_r1_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(86),
      Q => app_wdf_data_r1(86),
      R => '0'
    );
\app_wdf_data_r1_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(87),
      Q => app_wdf_data_r1(87),
      R => '0'
    );
\app_wdf_data_r1_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(88),
      Q => app_wdf_data_r1(88),
      R => '0'
    );
\app_wdf_data_r1_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(89),
      Q => app_wdf_data_r1(89),
      R => '0'
    );
\app_wdf_data_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(8),
      Q => app_wdf_data_r1(8),
      R => '0'
    );
\app_wdf_data_r1_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(90),
      Q => app_wdf_data_r1(90),
      R => '0'
    );
\app_wdf_data_r1_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(91),
      Q => app_wdf_data_r1(91),
      R => '0'
    );
\app_wdf_data_r1_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(92),
      Q => app_wdf_data_r1(92),
      R => '0'
    );
\app_wdf_data_r1_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(93),
      Q => app_wdf_data_r1(93),
      R => '0'
    );
\app_wdf_data_r1_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(94),
      Q => app_wdf_data_r1(94),
      R => '0'
    );
\app_wdf_data_r1_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(95),
      Q => app_wdf_data_r1(95),
      R => '0'
    );
\app_wdf_data_r1_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(96),
      Q => app_wdf_data_r1(96),
      R => '0'
    );
\app_wdf_data_r1_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(97),
      Q => app_wdf_data_r1(97),
      R => '0'
    );
\app_wdf_data_r1_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(98),
      Q => app_wdf_data_r1(98),
      R => '0'
    );
\app_wdf_data_r1_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(99),
      Q => app_wdf_data_r1(99),
      R => '0'
    );
\app_wdf_data_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_data(9),
      Q => app_wdf_data_r1(9),
      R => '0'
    );
app_wdf_end_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_wdf_end,
      I1 => reset_reg,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy2,
      O => app_wdf_end_ns1
    );
app_wdf_end_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_wdf_end_ns1,
      Q => app_wdf_end_r1,
      R => '0'
    );
\app_wdf_mask_r1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(0),
      Q => app_wdf_mask_r1(0),
      R => '0'
    );
\app_wdf_mask_r1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(10),
      Q => app_wdf_mask_r1(10),
      R => '0'
    );
\app_wdf_mask_r1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(11),
      Q => app_wdf_mask_r1(11),
      R => '0'
    );
\app_wdf_mask_r1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(12),
      Q => app_wdf_mask_r1(12),
      R => '0'
    );
\app_wdf_mask_r1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(13),
      Q => app_wdf_mask_r1(13),
      R => '0'
    );
\app_wdf_mask_r1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(14),
      Q => app_wdf_mask_r1(14),
      R => '0'
    );
\app_wdf_mask_r1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(15),
      Q => app_wdf_mask_r1(15),
      R => '0'
    );
\app_wdf_mask_r1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(16),
      Q => app_wdf_mask_r1(16),
      R => '0'
    );
\app_wdf_mask_r1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(17),
      Q => app_wdf_mask_r1(17),
      R => '0'
    );
\app_wdf_mask_r1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(18),
      Q => app_wdf_mask_r1(18),
      R => '0'
    );
\app_wdf_mask_r1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(19),
      Q => app_wdf_mask_r1(19),
      R => '0'
    );
\app_wdf_mask_r1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(1),
      Q => app_wdf_mask_r1(1),
      R => '0'
    );
\app_wdf_mask_r1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(20),
      Q => app_wdf_mask_r1(20),
      R => '0'
    );
\app_wdf_mask_r1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(21),
      Q => app_wdf_mask_r1(21),
      R => '0'
    );
\app_wdf_mask_r1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(22),
      Q => app_wdf_mask_r1(22),
      R => '0'
    );
\app_wdf_mask_r1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(23),
      Q => app_wdf_mask_r1(23),
      R => '0'
    );
\app_wdf_mask_r1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(24),
      Q => app_wdf_mask_r1(24),
      R => '0'
    );
\app_wdf_mask_r1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(25),
      Q => app_wdf_mask_r1(25),
      R => '0'
    );
\app_wdf_mask_r1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(26),
      Q => app_wdf_mask_r1(26),
      R => '0'
    );
\app_wdf_mask_r1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(27),
      Q => app_wdf_mask_r1(27),
      R => '0'
    );
\app_wdf_mask_r1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(28),
      Q => app_wdf_mask_r1(28),
      R => '0'
    );
\app_wdf_mask_r1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(29),
      Q => app_wdf_mask_r1(29),
      R => '0'
    );
\app_wdf_mask_r1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(2),
      Q => app_wdf_mask_r1(2),
      R => '0'
    );
\app_wdf_mask_r1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(30),
      Q => app_wdf_mask_r1(30),
      R => '0'
    );
\app_wdf_mask_r1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(31),
      Q => app_wdf_mask_r1(31),
      R => '0'
    );
\app_wdf_mask_r1_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(32),
      Q => app_wdf_mask_r1(32),
      R => '0'
    );
\app_wdf_mask_r1_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(33),
      Q => app_wdf_mask_r1(33),
      R => '0'
    );
\app_wdf_mask_r1_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(34),
      Q => app_wdf_mask_r1(34),
      R => '0'
    );
\app_wdf_mask_r1_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(35),
      Q => app_wdf_mask_r1(35),
      R => '0'
    );
\app_wdf_mask_r1_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(36),
      Q => app_wdf_mask_r1(36),
      R => '0'
    );
\app_wdf_mask_r1_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(37),
      Q => app_wdf_mask_r1(37),
      R => '0'
    );
\app_wdf_mask_r1_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(38),
      Q => app_wdf_mask_r1(38),
      R => '0'
    );
\app_wdf_mask_r1_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(39),
      Q => app_wdf_mask_r1(39),
      R => '0'
    );
\app_wdf_mask_r1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(3),
      Q => app_wdf_mask_r1(3),
      R => '0'
    );
\app_wdf_mask_r1_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(40),
      Q => app_wdf_mask_r1(40),
      R => '0'
    );
\app_wdf_mask_r1_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(41),
      Q => app_wdf_mask_r1(41),
      R => '0'
    );
\app_wdf_mask_r1_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(42),
      Q => app_wdf_mask_r1(42),
      R => '0'
    );
\app_wdf_mask_r1_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(43),
      Q => app_wdf_mask_r1(43),
      R => '0'
    );
\app_wdf_mask_r1_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(44),
      Q => app_wdf_mask_r1(44),
      R => '0'
    );
\app_wdf_mask_r1_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(45),
      Q => app_wdf_mask_r1(45),
      R => '0'
    );
\app_wdf_mask_r1_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(46),
      Q => app_wdf_mask_r1(46),
      R => '0'
    );
\app_wdf_mask_r1_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(47),
      Q => app_wdf_mask_r1(47),
      R => '0'
    );
\app_wdf_mask_r1_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(48),
      Q => app_wdf_mask_r1(48),
      R => '0'
    );
\app_wdf_mask_r1_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(49),
      Q => app_wdf_mask_r1(49),
      R => '0'
    );
\app_wdf_mask_r1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(4),
      Q => app_wdf_mask_r1(4),
      R => '0'
    );
\app_wdf_mask_r1_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(50),
      Q => app_wdf_mask_r1(50),
      R => '0'
    );
\app_wdf_mask_r1_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(51),
      Q => app_wdf_mask_r1(51),
      R => '0'
    );
\app_wdf_mask_r1_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(52),
      Q => app_wdf_mask_r1(52),
      R => '0'
    );
\app_wdf_mask_r1_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(53),
      Q => app_wdf_mask_r1(53),
      R => '0'
    );
\app_wdf_mask_r1_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(54),
      Q => app_wdf_mask_r1(54),
      R => '0'
    );
\app_wdf_mask_r1_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(55),
      Q => app_wdf_mask_r1(55),
      R => '0'
    );
\app_wdf_mask_r1_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(56),
      Q => app_wdf_mask_r1(56),
      R => '0'
    );
\app_wdf_mask_r1_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(57),
      Q => app_wdf_mask_r1(57),
      R => '0'
    );
\app_wdf_mask_r1_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(58),
      Q => app_wdf_mask_r1(58),
      R => '0'
    );
\app_wdf_mask_r1_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(59),
      Q => app_wdf_mask_r1(59),
      R => '0'
    );
\app_wdf_mask_r1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(5),
      Q => app_wdf_mask_r1(5),
      R => '0'
    );
\app_wdf_mask_r1_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(60),
      Q => app_wdf_mask_r1(60),
      R => '0'
    );
\app_wdf_mask_r1_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(61),
      Q => app_wdf_mask_r1(61),
      R => '0'
    );
\app_wdf_mask_r1_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(62),
      Q => app_wdf_mask_r1(62),
      R => '0'
    );
\app_wdf_mask_r1_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(63),
      Q => app_wdf_mask_r1(63),
      R => '0'
    );
\app_wdf_mask_r1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(6),
      Q => app_wdf_mask_r1(6),
      R => '0'
    );
\app_wdf_mask_r1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(7),
      Q => app_wdf_mask_r1(7),
      R => '0'
    );
\app_wdf_mask_r1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(8),
      Q => app_wdf_mask_r1(8),
      R => '0'
    );
\app_wdf_mask_r1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => app_wdf_rdy_r_copy2,
      D => app_wdf_mask(9),
      Q => app_wdf_mask_r1(9),
      R => '0'
    );
app_wdf_rdy_r_copy1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy1,
      R => '0'
    );
app_wdf_rdy_r_copy2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy2,
      R => '0'
    );
app_wdf_rdy_r_copy3_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy_r_copy3,
      R => '0'
    );
app_wdf_wren_r1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2230"
    )
        port map (
      I0 => app_wdf_wren,
      I1 => reset_reg,
      I2 => app_wdf_wren_r1,
      I3 => app_wdf_rdy_r_copy2,
      O => app_wdf_wren_ns1
    );
app_wdf_wren_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => app_wdf_wren_ns1,
      Q => app_wdf_wren_r1,
      R => '0'
    );
\data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(0),
      O => \p_0_in__0\(0)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(0),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(1),
      O => \p_0_in__0\(1)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(0),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(1),
      I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(1),
      I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(0),
      I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(2),
      I3 => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(0),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(0),
      R => reset_reg
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(1),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(1),
      R => reset_reg
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(2),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(2),
      R => reset_reg
    );
\data_buf_address_counter.data_buf_addr_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => wr_accepted,
      D => \p_0_in__0\(3),
      Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(3),
      R => reset_reg
    );
mem_reg_0_15_0_5_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(63),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(31)
    );
\mem_reg_0_15_0_5_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(39),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(19)
    );
\mem_reg_0_15_0_5_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(31),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(15)
    );
mem_reg_0_15_0_5_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(383),
      I1 => \init_calib_complete_reg_rep__22\,
      O => \my_empty_reg[7]\(95)
    );
\mem_reg_0_15_0_5_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(359),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(89)
    );
\mem_reg_0_15_0_5_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(351),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(87)
    );
\mem_reg_0_15_12_17_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(375),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(93)
    );
\mem_reg_0_15_12_17_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(367),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(91)
    );
\mem_reg_0_15_12_17_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(343),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(85)
    );
\mem_reg_0_15_12_17_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(335),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(83)
    );
\mem_reg_0_15_12_17_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(327),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(81)
    );
\mem_reg_0_15_12_17_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(318),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(79)
    );
\mem_reg_0_15_12_17_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(294),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(73)
    );
\mem_reg_0_15_12_17_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(286),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(71)
    );
\mem_reg_0_15_18_23_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(246),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(61)
    );
\mem_reg_0_15_18_23_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(238),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(59)
    );
\mem_reg_0_15_18_23_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(214),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(53)
    );
\mem_reg_0_15_18_23_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(206),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(51)
    );
\mem_reg_0_15_18_23_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(198),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(49)
    );
\mem_reg_0_15_18_23_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(189),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(47)
    );
\mem_reg_0_15_18_23_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(165),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(41)
    );
\mem_reg_0_15_18_23_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(157),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(39)
    );
\mem_reg_0_15_18_23_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(310),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(77)
    );
\mem_reg_0_15_18_23_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(302),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(75)
    );
\mem_reg_0_15_18_23_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(278),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(69)
    );
\mem_reg_0_15_18_23_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(270),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(67)
    );
\mem_reg_0_15_18_23_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(262),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(65)
    );
\mem_reg_0_15_24_29_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(60),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(30)
    );
\mem_reg_0_15_24_29_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(36),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(18)
    );
\mem_reg_0_15_24_29_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(28),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(14)
    );
\mem_reg_0_15_24_29_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(181),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(45)
    );
\mem_reg_0_15_24_29_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(173),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(43)
    );
\mem_reg_0_15_24_29_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(149),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(37)
    );
\mem_reg_0_15_24_29_i_4__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(141),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(35)
    );
\mem_reg_0_15_24_29_i_4__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(133),
      I1 => \init_calib_complete_reg_rep__16\,
      O => \my_empty_reg[7]\(33)
    );
\mem_reg_0_15_30_35_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(59),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(29)
    );
\mem_reg_0_15_30_35_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(52),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(26)
    );
\mem_reg_0_15_30_35_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(44),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(22)
    );
\mem_reg_0_15_30_35_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(35),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(17)
    );
\mem_reg_0_15_30_35_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(27),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(13)
    );
\mem_reg_0_15_30_35_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(20),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(10)
    );
\mem_reg_0_15_30_35_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(12),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(6)
    );
\mem_reg_0_15_30_35_i_4__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(4),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(2)
    );
\mem_reg_0_15_36_41_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(379),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(94)
    );
\mem_reg_0_15_36_41_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(355),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(88)
    );
\mem_reg_0_15_36_41_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(347),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(86)
    );
\mem_reg_0_15_36_41_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(43),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(21)
    );
\mem_reg_0_15_36_41_i_6__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(11),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(5)
    );
\mem_reg_0_15_36_41_i_6__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(3),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(1)
    );
\mem_reg_0_15_42_47_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(250),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(62)
    );
\mem_reg_0_15_42_47_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(226),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(56)
    );
\mem_reg_0_15_42_47_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(218),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(54)
    );
\mem_reg_0_15_42_47_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(363),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(90)
    );
\mem_reg_0_15_42_47_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(331),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(82)
    );
\mem_reg_0_15_42_47_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(323),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(80)
    );
\mem_reg_0_15_42_47_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(314),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(78)
    );
\mem_reg_0_15_42_47_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(290),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(72)
    );
\mem_reg_0_15_42_47_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(282),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(70)
    );
\mem_reg_0_15_48_53_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(51),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(25)
    );
\mem_reg_0_15_48_53_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(19),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(9)
    );
\mem_reg_0_15_48_53_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(234),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(58)
    );
\mem_reg_0_15_48_53_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(202),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(50)
    );
\mem_reg_0_15_48_53_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(194),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(48)
    );
\mem_reg_0_15_48_53_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(185),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(46)
    );
\mem_reg_0_15_48_53_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(161),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(40)
    );
\mem_reg_0_15_48_53_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(153),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(38)
    );
\mem_reg_0_15_48_53_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(371),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(92)
    );
\mem_reg_0_15_48_53_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(339),
      I1 => \init_calib_complete_reg_rep__21\,
      O => \my_empty_reg[7]\(84)
    );
\mem_reg_0_15_48_53_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(298),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(74)
    );
\mem_reg_0_15_48_53_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(266),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(66)
    );
\mem_reg_0_15_48_53_i_6__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(258),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(64)
    );
\mem_reg_0_15_54_59_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(56),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(28)
    );
\mem_reg_0_15_54_59_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(32),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(16)
    );
\mem_reg_0_15_54_59_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(24),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(12)
    );
\mem_reg_0_15_54_59_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(242),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(60)
    );
\mem_reg_0_15_54_59_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(210),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(52)
    );
\mem_reg_0_15_54_59_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(169),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(42)
    );
\mem_reg_0_15_54_59_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(137),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(34)
    );
\mem_reg_0_15_54_59_i_6__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(129),
      I1 => \init_calib_complete_reg_rep__16\,
      O => \my_empty_reg[7]\(32)
    );
\mem_reg_0_15_60_65_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(306),
      I1 => \init_calib_complete_reg_rep__20\,
      O => \my_empty_reg[7]\(76)
    );
\mem_reg_0_15_60_65_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(274),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(68)
    );
\mem_reg_0_15_60_65_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(40),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(20)
    );
\mem_reg_0_15_60_65_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(8),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(4)
    );
\mem_reg_0_15_60_65_i_6__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(0),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(0)
    );
\mem_reg_0_15_66_71_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(177),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(44)
    );
\mem_reg_0_15_66_71_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(145),
      I1 => \init_calib_complete_reg_rep__17\,
      O => \my_empty_reg[7]\(36)
    );
\mem_reg_0_15_6_11_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(55),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(27)
    );
\mem_reg_0_15_6_11_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(47),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(23)
    );
\mem_reg_0_15_6_11_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(23),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(11)
    );
\mem_reg_0_15_6_11_i_2__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(15),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(7)
    );
\mem_reg_0_15_6_11_i_2__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(7),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(3)
    );
mem_reg_0_15_6_11_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(254),
      I1 => \init_calib_complete_reg_rep__19\,
      O => \my_empty_reg[7]\(63)
    );
\mem_reg_0_15_6_11_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(230),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(57)
    );
\mem_reg_0_15_6_11_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(222),
      I1 => \init_calib_complete_reg_rep__18\,
      O => \my_empty_reg[7]\(55)
    );
\mem_reg_0_15_72_77_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(48),
      I1 => \init_calib_complete_reg_rep__15\,
      O => \my_empty_reg[7]\(24)
    );
\mem_reg_0_15_72_77_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^my_empty_reg[7]_0\(16),
      I1 => \init_calib_complete_reg_rep__14\,
      O => \my_empty_reg[7]\(8)
    );
\occupied_counter.app_wdf_rdy_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404040444444"
    )
        port map (
      I0 => reset_reg,
      I1 => ram_init_done_r,
      I2 => \^p_0_in\(0),
      I3 => \p_0_in__0_0\(1),
      I4 => p_4_in,
      I5 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      O => wdf_rdy_ns
    );
\occupied_counter.app_wdf_rdy_r_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => app_wdf_wren_r1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_rdy_r_copy1,
      O => \p_0_in__0_0\(1)
    );
\occupied_counter.app_wdf_rdy_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wdf_rdy_ns,
      Q => app_wdf_rdy,
      R => '0'
    );
\occupied_counter.occ_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => app_wdf_rdy_r_copy1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_wren_r1,
      I3 => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      O => p_1_in(0)
    );
\occupied_counter.occ_cnt[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      O => p_1_in(10)
    );
\occupied_counter.occ_cnt[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      O => p_1_in(11)
    );
\occupied_counter.occ_cnt[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      O => p_1_in(12)
    );
\occupied_counter.occ_cnt[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => p_4_in,
      O => p_1_in(13)
    );
\occupied_counter.occ_cnt[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      O => p_1_in(14)
    );
\occupied_counter.occ_cnt[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \^p_0_in\(0),
      I1 => app_wdf_rdy_r_copy1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_wren_r1,
      O => \occupied_counter.occ_cnt[15]_i_1_n_0\
    );
\occupied_counter.occ_cnt[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => app_wdf_wren_r1,
      I1 => app_wdf_end_r1,
      I2 => app_wdf_rdy_r_copy1,
      I3 => p_4_in,
      O => p_1_in(15)
    );
\occupied_counter.occ_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[0]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      O => p_1_in(1)
    );
\occupied_counter.occ_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      O => p_1_in(2)
    );
\occupied_counter.occ_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      O => p_1_in(3)
    );
\occupied_counter.occ_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      O => p_1_in(4)
    );
\occupied_counter.occ_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      O => p_1_in(5)
    );
\occupied_counter.occ_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      O => p_1_in(6)
    );
\occupied_counter.occ_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      O => p_1_in(7)
    );
\occupied_counter.occ_cnt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      O => p_1_in(8)
    );
\occupied_counter.occ_cnt[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      I1 => app_wdf_wren_r1,
      I2 => app_wdf_end_r1,
      I3 => app_wdf_rdy_r_copy1,
      I4 => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      O => p_1_in(9)
    );
\occupied_counter.occ_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(0),
      Q => \occupied_counter.occ_cnt_reg_n_0_[0]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(10),
      Q => \occupied_counter.occ_cnt_reg_n_0_[10]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(11),
      Q => \occupied_counter.occ_cnt_reg_n_0_[11]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(12),
      Q => \occupied_counter.occ_cnt_reg_n_0_[12]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(13),
      Q => \occupied_counter.occ_cnt_reg_n_0_[13]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(14),
      Q => p_4_in,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(15),
      Q => \occupied_counter.occ_cnt_reg_n_0_[15]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(1),
      Q => \occupied_counter.occ_cnt_reg_n_0_[1]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(2),
      Q => \occupied_counter.occ_cnt_reg_n_0_[2]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(3),
      Q => \occupied_counter.occ_cnt_reg_n_0_[3]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(4),
      Q => \occupied_counter.occ_cnt_reg_n_0_[4]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(5),
      Q => \occupied_counter.occ_cnt_reg_n_0_[5]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(6),
      Q => \occupied_counter.occ_cnt_reg_n_0_[6]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(7),
      Q => \occupied_counter.occ_cnt_reg_n_0_[7]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(8),
      Q => \occupied_counter.occ_cnt_reg_n_0_[8]\,
      R => reset_reg
    );
\occupied_counter.occ_cnt_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \occupied_counter.occ_cnt[15]_i_1_n_0\,
      D => p_1_in(9),
      Q => \occupied_counter.occ_cnt_reg_n_0_[9]\,
      R => reset_reg
    );
\pointer_ram.rams[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => B"00000",
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg__0\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => ADDRD(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0),
      DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => wr_data_buf_addr(1 downto 0),
      DOC(1 downto 0) => wr_data_pntr(1 downto 0),
      DOD(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \pointer_ram.pointer_we\
    );
\pointer_ram.rams[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 0) => B"00000",
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg__0\(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg__0\(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => ADDRD(3 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2),
      DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0),
      DOB(1 downto 0) => wr_data_buf_addr(3 downto 2),
      DOC(1 downto 0) => wr_data_pntr(3 downto 2),
      DOD(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => \pointer_ram.pointer_we\
    );
\read_data_indx.rd_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \p_0_in__1\(0)
    );
\read_data_indx.rd_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \p_0_in__1\(1)
    );
\read_data_indx.rd_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \p_0_in__1\(2)
    );
\read_data_indx.rd_data_indx_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \p_0_in__1\(3)
    );
\read_data_indx.rd_data_indx_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(0),
      Q => \^q\(0),
      R => reset_reg
    );
\read_data_indx.rd_data_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(1),
      Q => \^q\(1),
      R => reset_reg
    );
\read_data_indx.rd_data_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(2),
      Q => \^q\(2),
      R => reset_reg
    );
\read_data_indx.rd_data_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => E(0),
      D => \p_0_in__1\(3),
      Q => \^q\(3),
      R => reset_reg
    );
\read_data_indx.rd_data_upd_indx_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => E(0),
      Q => \^p_0_in\(0),
      R => '0'
    );
\wr_req_counter.wr_req_cnt_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E178"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I1 => wr_accepted,
      I2 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I3 => \^p_0_in\(0),
      O => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B4F0F0D2"
    )
        port map (
      I0 => \^p_0_in\(0),
      I1 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I2 => \wr_req_counter.wr_req_cnt_r\(2),
      I3 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      I4 => wr_accepted,
      I5 => reset_reg,
      O => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000078F0F0D2"
    )
        port map (
      I0 => \read_data_indx.rd_data_upd_indx_r_reg_0\,
      I1 => \wr_req_counter.wr_req_cnt_r\(2),
      I2 => \wr_req_counter.wr_req_cnt_r\(3),
      I3 => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      I4 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I5 => reset_reg,
      O => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F80FE01FF00FF00"
    )
        port map (
      I0 => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      I1 => \wr_req_counter.wr_req_cnt_r_reg[0]_0\,
      I2 => \wr_req_counter.wr_req_cnt_r\(2),
      I3 => \wr_req_counter.wr_req_cnt_r\(4),
      I4 => \wr_req_counter.wr_req_cnt_r\(3),
      I5 => \read_data_indx.rd_data_upd_indx_r_reg_0\,
      O => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\
    );
\wr_req_counter.wr_req_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r_reg[0]_1\(0),
      Q => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(0),
      R => '0'
    );
\wr_req_counter.wr_req_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\,
      Q => \^wr_req_counter.wr_req_cnt_r_reg[1]_0\(1),
      R => reset_reg
    );
\wr_req_counter.wr_req_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(2),
      R => '0'
    );
\wr_req_counter.wr_req_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(3),
      R => '0'
    );
\wr_req_counter.wr_req_cnt_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\,
      Q => \wr_req_counter.wr_req_cnt_r\(4),
      R => reset_reg
    );
\write_buffer.wr_buf_out_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(0),
      Q => \^my_empty_reg[7]_0\(0),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(100),
      Q => \^my_empty_reg[7]_0\(100),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(101),
      Q => \^my_empty_reg[7]_0\(101),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(102),
      Q => \^my_empty_reg[7]_0\(102),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(103),
      Q => \^my_empty_reg[7]_0\(103),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(104),
      Q => \^my_empty_reg[7]_0\(104),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(105),
      Q => \^my_empty_reg[7]_0\(105),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(106),
      Q => \^my_empty_reg[7]_0\(106),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(107),
      Q => \^my_empty_reg[7]_0\(107),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(108),
      Q => \^my_empty_reg[7]_0\(108),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(109),
      Q => \^my_empty_reg[7]_0\(109),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(10),
      Q => \^my_empty_reg[7]_0\(10),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(110),
      Q => \^my_empty_reg[7]_0\(110),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(111),
      Q => \^my_empty_reg[7]_0\(111),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(112),
      Q => \^my_empty_reg[7]_0\(112),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(113),
      Q => \^my_empty_reg[7]_0\(113),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(114),
      Q => \^my_empty_reg[7]_0\(114),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(115),
      Q => \^my_empty_reg[7]_0\(115),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(116),
      Q => \^my_empty_reg[7]_0\(116),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(117),
      Q => \^my_empty_reg[7]_0\(117),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(118),
      Q => \^my_empty_reg[7]_0\(118),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(119),
      Q => \^my_empty_reg[7]_0\(119),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(11),
      Q => \^my_empty_reg[7]_0\(11),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(120),
      Q => \^my_empty_reg[7]_0\(120),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(121),
      Q => \^my_empty_reg[7]_0\(121),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(122),
      Q => \^my_empty_reg[7]_0\(122),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(123),
      Q => \^my_empty_reg[7]_0\(123),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(124),
      Q => \^my_empty_reg[7]_0\(124),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(125),
      Q => \^my_empty_reg[7]_0\(125),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(126),
      Q => \^my_empty_reg[7]_0\(126),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(127),
      Q => \^my_empty_reg[7]_0\(127),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(128),
      Q => \^my_empty_reg[7]_0\(128),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(129),
      Q => \^my_empty_reg[7]_0\(129),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(12),
      Q => \^my_empty_reg[7]_0\(12),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(130),
      Q => \^my_empty_reg[7]_0\(130),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(131),
      Q => \^my_empty_reg[7]_0\(131),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(132),
      Q => \^my_empty_reg[7]_0\(132),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(133),
      Q => \^my_empty_reg[7]_0\(133),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(134),
      Q => \^my_empty_reg[7]_0\(134),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(135),
      Q => \^my_empty_reg[7]_0\(135),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(136),
      Q => \^my_empty_reg[7]_0\(136),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(137),
      Q => \^my_empty_reg[7]_0\(137),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(138),
      Q => \^my_empty_reg[7]_0\(138),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(139),
      Q => \^my_empty_reg[7]_0\(139),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(13),
      Q => \^my_empty_reg[7]_0\(13),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(140),
      Q => \^my_empty_reg[7]_0\(140),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(141),
      Q => \^my_empty_reg[7]_0\(141),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(142),
      Q => \^my_empty_reg[7]_0\(142),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(143),
      Q => \^my_empty_reg[7]_0\(143),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(144),
      Q => \^my_empty_reg[7]_0\(144),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(145),
      Q => \^my_empty_reg[7]_0\(145),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(146),
      Q => \^my_empty_reg[7]_0\(146),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(147),
      Q => \^my_empty_reg[7]_0\(147),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(148),
      Q => \^my_empty_reg[7]_0\(148),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(149),
      Q => \^my_empty_reg[7]_0\(149),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(14),
      Q => \^my_empty_reg[7]_0\(14),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(150),
      Q => \^my_empty_reg[7]_0\(150),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(151),
      Q => \^my_empty_reg[7]_0\(151),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(152),
      Q => \^my_empty_reg[7]_0\(152),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(153),
      Q => \^my_empty_reg[7]_0\(153),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(154),
      Q => \^my_empty_reg[7]_0\(154),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(155),
      Q => \^my_empty_reg[7]_0\(155),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(156),
      Q => \^my_empty_reg[7]_0\(156),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(157),
      Q => \^my_empty_reg[7]_0\(157),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(158),
      Q => \^my_empty_reg[7]_0\(158),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[159]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(159),
      Q => \^my_empty_reg[7]_0\(159),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(15),
      Q => \^my_empty_reg[7]_0\(15),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[160]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(160),
      Q => \^my_empty_reg[7]_0\(160),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[161]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(161),
      Q => \^my_empty_reg[7]_0\(161),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[162]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(162),
      Q => \^my_empty_reg[7]_0\(162),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[163]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(163),
      Q => \^my_empty_reg[7]_0\(163),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[164]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(164),
      Q => \^my_empty_reg[7]_0\(164),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[165]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(165),
      Q => \^my_empty_reg[7]_0\(165),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[166]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(166),
      Q => \^my_empty_reg[7]_0\(166),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[167]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(167),
      Q => \^my_empty_reg[7]_0\(167),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[168]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(168),
      Q => \^my_empty_reg[7]_0\(168),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[169]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(169),
      Q => \^my_empty_reg[7]_0\(169),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(16),
      Q => \^my_empty_reg[7]_0\(16),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[170]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(170),
      Q => \^my_empty_reg[7]_0\(170),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[171]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(171),
      Q => \^my_empty_reg[7]_0\(171),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[172]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(172),
      Q => \^my_empty_reg[7]_0\(172),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[173]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(173),
      Q => \^my_empty_reg[7]_0\(173),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[174]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(174),
      Q => \^my_empty_reg[7]_0\(174),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[175]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(175),
      Q => \^my_empty_reg[7]_0\(175),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[176]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(176),
      Q => \^my_empty_reg[7]_0\(176),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[177]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(177),
      Q => \^my_empty_reg[7]_0\(177),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[178]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(178),
      Q => \^my_empty_reg[7]_0\(178),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[179]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(179),
      Q => \^my_empty_reg[7]_0\(179),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(17),
      Q => \^my_empty_reg[7]_0\(17),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[180]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(180),
      Q => \^my_empty_reg[7]_0\(180),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[181]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(181),
      Q => \^my_empty_reg[7]_0\(181),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[182]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(182),
      Q => \^my_empty_reg[7]_0\(182),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[183]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(183),
      Q => \^my_empty_reg[7]_0\(183),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[184]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(184),
      Q => \^my_empty_reg[7]_0\(184),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[185]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(185),
      Q => \^my_empty_reg[7]_0\(185),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[186]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(186),
      Q => \^my_empty_reg[7]_0\(186),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[187]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(187),
      Q => \^my_empty_reg[7]_0\(187),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[188]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(188),
      Q => \^my_empty_reg[7]_0\(188),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[189]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(189),
      Q => \^my_empty_reg[7]_0\(189),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(18),
      Q => \^my_empty_reg[7]_0\(18),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[190]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(190),
      Q => \^my_empty_reg[7]_0\(190),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[191]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(191),
      Q => \^my_empty_reg[7]_0\(191),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[192]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(192),
      Q => \^my_empty_reg[7]_0\(192),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[193]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(193),
      Q => \^my_empty_reg[7]_0\(193),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[194]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(194),
      Q => \^my_empty_reg[7]_0\(194),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[195]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(195),
      Q => \^my_empty_reg[7]_0\(195),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[196]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(196),
      Q => \^my_empty_reg[7]_0\(196),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[197]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(197),
      Q => \^my_empty_reg[7]_0\(197),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[198]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(198),
      Q => \^my_empty_reg[7]_0\(198),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[199]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(199),
      Q => \^my_empty_reg[7]_0\(199),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(19),
      Q => \^my_empty_reg[7]_0\(19),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(1),
      Q => \^my_empty_reg[7]_0\(1),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[200]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(200),
      Q => \^my_empty_reg[7]_0\(200),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[201]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(201),
      Q => \^my_empty_reg[7]_0\(201),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[202]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(202),
      Q => \^my_empty_reg[7]_0\(202),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[203]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(203),
      Q => \^my_empty_reg[7]_0\(203),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[204]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(204),
      Q => \^my_empty_reg[7]_0\(204),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[205]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(205),
      Q => \^my_empty_reg[7]_0\(205),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[206]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(206),
      Q => \^my_empty_reg[7]_0\(206),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[207]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(207),
      Q => \^my_empty_reg[7]_0\(207),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[208]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(208),
      Q => \^my_empty_reg[7]_0\(208),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[209]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(209),
      Q => \^my_empty_reg[7]_0\(209),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(20),
      Q => \^my_empty_reg[7]_0\(20),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[210]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(210),
      Q => \^my_empty_reg[7]_0\(210),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[211]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(211),
      Q => \^my_empty_reg[7]_0\(211),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[212]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(212),
      Q => \^my_empty_reg[7]_0\(212),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[213]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(213),
      Q => \^my_empty_reg[7]_0\(213),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[214]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(214),
      Q => \^my_empty_reg[7]_0\(214),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[215]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(215),
      Q => \^my_empty_reg[7]_0\(215),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[216]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(216),
      Q => \^my_empty_reg[7]_0\(216),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[217]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(217),
      Q => \^my_empty_reg[7]_0\(217),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[218]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(218),
      Q => \^my_empty_reg[7]_0\(218),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[219]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(219),
      Q => \^my_empty_reg[7]_0\(219),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(21),
      Q => \^my_empty_reg[7]_0\(21),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[220]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(220),
      Q => \^my_empty_reg[7]_0\(220),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[221]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(221),
      Q => \^my_empty_reg[7]_0\(221),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[222]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(222),
      Q => \^my_empty_reg[7]_0\(222),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[223]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(223),
      Q => \^my_empty_reg[7]_0\(223),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[224]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(224),
      Q => \^my_empty_reg[7]_0\(224),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[225]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(225),
      Q => \^my_empty_reg[7]_0\(225),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[226]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(226),
      Q => \^my_empty_reg[7]_0\(226),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[227]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(227),
      Q => \^my_empty_reg[7]_0\(227),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[228]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(228),
      Q => \^my_empty_reg[7]_0\(228),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[229]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(229),
      Q => \^my_empty_reg[7]_0\(229),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(22),
      Q => \^my_empty_reg[7]_0\(22),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[230]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(230),
      Q => \^my_empty_reg[7]_0\(230),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[231]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(231),
      Q => \^my_empty_reg[7]_0\(231),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[232]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(232),
      Q => \^my_empty_reg[7]_0\(232),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[233]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(233),
      Q => \^my_empty_reg[7]_0\(233),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[234]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(234),
      Q => \^my_empty_reg[7]_0\(234),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[235]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(235),
      Q => \^my_empty_reg[7]_0\(235),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[236]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(236),
      Q => \^my_empty_reg[7]_0\(236),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[237]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(237),
      Q => \^my_empty_reg[7]_0\(237),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[238]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(238),
      Q => \^my_empty_reg[7]_0\(238),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[239]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(239),
      Q => \^my_empty_reg[7]_0\(239),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(23),
      Q => \^my_empty_reg[7]_0\(23),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[240]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(240),
      Q => \^my_empty_reg[7]_0\(240),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[241]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(241),
      Q => \^my_empty_reg[7]_0\(241),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[242]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(242),
      Q => \^my_empty_reg[7]_0\(242),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[243]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(243),
      Q => \^my_empty_reg[7]_0\(243),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[244]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(244),
      Q => \^my_empty_reg[7]_0\(244),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[245]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(245),
      Q => \^my_empty_reg[7]_0\(245),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[246]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(246),
      Q => \^my_empty_reg[7]_0\(246),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[247]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(247),
      Q => \^my_empty_reg[7]_0\(247),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[248]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(248),
      Q => \^my_empty_reg[7]_0\(248),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[249]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(249),
      Q => \^my_empty_reg[7]_0\(249),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(24),
      Q => \^my_empty_reg[7]_0\(24),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[250]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(250),
      Q => \^my_empty_reg[7]_0\(250),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[251]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(251),
      Q => \^my_empty_reg[7]_0\(251),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[252]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(252),
      Q => \^my_empty_reg[7]_0\(252),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[253]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(253),
      Q => \^my_empty_reg[7]_0\(253),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[254]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(254),
      Q => \^my_empty_reg[7]_0\(254),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[255]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(255),
      Q => \^my_empty_reg[7]_0\(255),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[256]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(256),
      Q => \^my_empty_reg[7]_0\(256),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[257]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(257),
      Q => \^my_empty_reg[7]_0\(257),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[258]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(258),
      Q => \^my_empty_reg[7]_0\(258),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[259]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(259),
      Q => \^my_empty_reg[7]_0\(259),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(25),
      Q => \^my_empty_reg[7]_0\(25),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[260]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(260),
      Q => \^my_empty_reg[7]_0\(260),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[261]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(261),
      Q => \^my_empty_reg[7]_0\(261),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[262]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(262),
      Q => \^my_empty_reg[7]_0\(262),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[263]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(263),
      Q => \^my_empty_reg[7]_0\(263),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[264]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(264),
      Q => \^my_empty_reg[7]_0\(264),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[265]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(265),
      Q => \^my_empty_reg[7]_0\(265),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[266]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(266),
      Q => \^my_empty_reg[7]_0\(266),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[267]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(267),
      Q => \^my_empty_reg[7]_0\(267),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[268]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(268),
      Q => \^my_empty_reg[7]_0\(268),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[269]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(269),
      Q => \^my_empty_reg[7]_0\(269),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(26),
      Q => \^my_empty_reg[7]_0\(26),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[270]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(270),
      Q => \^my_empty_reg[7]_0\(270),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[271]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(271),
      Q => \^my_empty_reg[7]_0\(271),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[272]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(272),
      Q => \^my_empty_reg[7]_0\(272),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[273]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(273),
      Q => \^my_empty_reg[7]_0\(273),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[274]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(274),
      Q => \^my_empty_reg[7]_0\(274),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[275]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(275),
      Q => \^my_empty_reg[7]_0\(275),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[276]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(276),
      Q => \^my_empty_reg[7]_0\(276),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[277]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(277),
      Q => \^my_empty_reg[7]_0\(277),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[278]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(278),
      Q => \^my_empty_reg[7]_0\(278),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[279]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(279),
      Q => \^my_empty_reg[7]_0\(279),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(27),
      Q => \^my_empty_reg[7]_0\(27),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[280]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(280),
      Q => \^my_empty_reg[7]_0\(280),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[281]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(281),
      Q => \^my_empty_reg[7]_0\(281),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[282]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(282),
      Q => \^my_empty_reg[7]_0\(282),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[283]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(283),
      Q => \^my_empty_reg[7]_0\(283),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[284]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(284),
      Q => \^my_empty_reg[7]_0\(284),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[285]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(285),
      Q => \^my_empty_reg[7]_0\(285),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[286]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(286),
      Q => \^my_empty_reg[7]_0\(286),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[287]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(287),
      Q => \^my_empty_reg[7]_0\(287),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[288]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(288),
      Q => \^my_empty_reg[7]_0\(288),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[289]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(289),
      Q => \^my_empty_reg[7]_0\(289),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(28),
      Q => \^my_empty_reg[7]_0\(28),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[290]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(290),
      Q => \^my_empty_reg[7]_0\(290),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[291]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(291),
      Q => \^my_empty_reg[7]_0\(291),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[292]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(292),
      Q => \^my_empty_reg[7]_0\(292),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[293]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(293),
      Q => \^my_empty_reg[7]_0\(293),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[294]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(294),
      Q => \^my_empty_reg[7]_0\(294),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[295]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(295),
      Q => \^my_empty_reg[7]_0\(295),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[296]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(296),
      Q => \^my_empty_reg[7]_0\(296),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[297]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(297),
      Q => \^my_empty_reg[7]_0\(297),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[298]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(298),
      Q => \^my_empty_reg[7]_0\(298),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[299]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(299),
      Q => \^my_empty_reg[7]_0\(299),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(29),
      Q => \^my_empty_reg[7]_0\(29),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(2),
      Q => \^my_empty_reg[7]_0\(2),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[300]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(300),
      Q => \^my_empty_reg[7]_0\(300),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[301]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(301),
      Q => \^my_empty_reg[7]_0\(301),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[302]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(302),
      Q => \^my_empty_reg[7]_0\(302),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[303]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(303),
      Q => \^my_empty_reg[7]_0\(303),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[304]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(304),
      Q => \^my_empty_reg[7]_0\(304),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[305]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(305),
      Q => \^my_empty_reg[7]_0\(305),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[306]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(306),
      Q => \^my_empty_reg[7]_0\(306),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[307]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(307),
      Q => \^my_empty_reg[7]_0\(307),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[308]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(308),
      Q => \^my_empty_reg[7]_0\(308),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[309]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(309),
      Q => \^my_empty_reg[7]_0\(309),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(30),
      Q => \^my_empty_reg[7]_0\(30),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[310]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(310),
      Q => \^my_empty_reg[7]_0\(310),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[311]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(311),
      Q => \^my_empty_reg[7]_0\(311),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[312]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(312),
      Q => \^my_empty_reg[7]_0\(312),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[313]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(313),
      Q => \^my_empty_reg[7]_0\(313),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[314]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(314),
      Q => \^my_empty_reg[7]_0\(314),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[315]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(315),
      Q => \^my_empty_reg[7]_0\(315),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[316]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(316),
      Q => \^my_empty_reg[7]_0\(316),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[317]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(317),
      Q => \^my_empty_reg[7]_0\(317),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[318]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(318),
      Q => \^my_empty_reg[7]_0\(318),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[319]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(319),
      Q => \^my_empty_reg[7]_0\(319),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(31),
      Q => \^my_empty_reg[7]_0\(31),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[320]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(320),
      Q => \^my_empty_reg[7]_0\(320),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[321]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(321),
      Q => \^my_empty_reg[7]_0\(321),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[322]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(322),
      Q => \^my_empty_reg[7]_0\(322),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[323]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(323),
      Q => \^my_empty_reg[7]_0\(323),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[324]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(324),
      Q => \^my_empty_reg[7]_0\(324),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[325]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(325),
      Q => \^my_empty_reg[7]_0\(325),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[326]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(326),
      Q => \^my_empty_reg[7]_0\(326),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[327]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(327),
      Q => \^my_empty_reg[7]_0\(327),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[328]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(328),
      Q => \^my_empty_reg[7]_0\(328),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[329]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(329),
      Q => \^my_empty_reg[7]_0\(329),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(32),
      Q => \^my_empty_reg[7]_0\(32),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[330]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(330),
      Q => \^my_empty_reg[7]_0\(330),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[331]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(331),
      Q => \^my_empty_reg[7]_0\(331),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[332]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(332),
      Q => \^my_empty_reg[7]_0\(332),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[333]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(333),
      Q => \^my_empty_reg[7]_0\(333),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[334]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(334),
      Q => \^my_empty_reg[7]_0\(334),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[335]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(335),
      Q => \^my_empty_reg[7]_0\(335),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[336]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(336),
      Q => \^my_empty_reg[7]_0\(336),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[337]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(337),
      Q => \^my_empty_reg[7]_0\(337),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[338]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(338),
      Q => \^my_empty_reg[7]_0\(338),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[339]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(339),
      Q => \^my_empty_reg[7]_0\(339),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(33),
      Q => \^my_empty_reg[7]_0\(33),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[340]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(340),
      Q => \^my_empty_reg[7]_0\(340),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[341]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(341),
      Q => \^my_empty_reg[7]_0\(341),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[342]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(342),
      Q => \^my_empty_reg[7]_0\(342),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[343]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(343),
      Q => \^my_empty_reg[7]_0\(343),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[344]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(344),
      Q => \^my_empty_reg[7]_0\(344),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[345]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(345),
      Q => \^my_empty_reg[7]_0\(345),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[346]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(346),
      Q => \^my_empty_reg[7]_0\(346),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[347]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(347),
      Q => \^my_empty_reg[7]_0\(347),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[348]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(348),
      Q => \^my_empty_reg[7]_0\(348),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[349]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(349),
      Q => \^my_empty_reg[7]_0\(349),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(34),
      Q => \^my_empty_reg[7]_0\(34),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[350]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(350),
      Q => \^my_empty_reg[7]_0\(350),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[351]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(351),
      Q => \^my_empty_reg[7]_0\(351),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[352]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(352),
      Q => \^my_empty_reg[7]_0\(352),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[353]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(353),
      Q => \^my_empty_reg[7]_0\(353),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[354]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(354),
      Q => \^my_empty_reg[7]_0\(354),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[355]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(355),
      Q => \^my_empty_reg[7]_0\(355),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[356]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(356),
      Q => \^my_empty_reg[7]_0\(356),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[357]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(357),
      Q => \^my_empty_reg[7]_0\(357),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[358]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(358),
      Q => \^my_empty_reg[7]_0\(358),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[359]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(359),
      Q => \^my_empty_reg[7]_0\(359),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(35),
      Q => \^my_empty_reg[7]_0\(35),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[360]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(360),
      Q => \^my_empty_reg[7]_0\(360),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[361]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(361),
      Q => \^my_empty_reg[7]_0\(361),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[362]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(362),
      Q => \^my_empty_reg[7]_0\(362),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[363]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(363),
      Q => \^my_empty_reg[7]_0\(363),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[364]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(364),
      Q => \^my_empty_reg[7]_0\(364),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[365]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(365),
      Q => \^my_empty_reg[7]_0\(365),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[366]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(366),
      Q => \^my_empty_reg[7]_0\(366),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[367]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(367),
      Q => \^my_empty_reg[7]_0\(367),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[368]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(368),
      Q => \^my_empty_reg[7]_0\(368),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[369]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(369),
      Q => \^my_empty_reg[7]_0\(369),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(36),
      Q => \^my_empty_reg[7]_0\(36),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[370]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(370),
      Q => \^my_empty_reg[7]_0\(370),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[371]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(371),
      Q => \^my_empty_reg[7]_0\(371),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[372]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(372),
      Q => \^my_empty_reg[7]_0\(372),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[373]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(373),
      Q => \^my_empty_reg[7]_0\(373),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[374]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(374),
      Q => \^my_empty_reg[7]_0\(374),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[375]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(375),
      Q => \^my_empty_reg[7]_0\(375),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[376]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(376),
      Q => \^my_empty_reg[7]_0\(376),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[377]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(377),
      Q => \^my_empty_reg[7]_0\(377),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[378]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(378),
      Q => \^my_empty_reg[7]_0\(378),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[379]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(379),
      Q => \^my_empty_reg[7]_0\(379),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(37),
      Q => \^my_empty_reg[7]_0\(37),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[380]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(380),
      Q => \^my_empty_reg[7]_0\(380),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[381]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(381),
      Q => \^my_empty_reg[7]_0\(381),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[382]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(382),
      Q => \^my_empty_reg[7]_0\(382),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[383]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(383),
      Q => \^my_empty_reg[7]_0\(383),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[384]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(384),
      Q => \^my_empty_reg[7]_0\(384),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[385]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(385),
      Q => \^my_empty_reg[7]_0\(385),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[386]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(386),
      Q => \^my_empty_reg[7]_0\(386),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[387]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(387),
      Q => \^my_empty_reg[7]_0\(387),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[388]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(388),
      Q => \^my_empty_reg[7]_0\(388),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[389]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(389),
      Q => \^my_empty_reg[7]_0\(389),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(38),
      Q => \^my_empty_reg[7]_0\(38),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[390]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(390),
      Q => \^my_empty_reg[7]_0\(390),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[391]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(391),
      Q => \^my_empty_reg[7]_0\(391),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[392]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(392),
      Q => \^my_empty_reg[7]_0\(392),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[393]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(393),
      Q => \^my_empty_reg[7]_0\(393),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[394]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(394),
      Q => \^my_empty_reg[7]_0\(394),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[395]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(395),
      Q => \^my_empty_reg[7]_0\(395),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[396]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(396),
      Q => \^my_empty_reg[7]_0\(396),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[397]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(397),
      Q => \^my_empty_reg[7]_0\(397),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[398]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(398),
      Q => \^my_empty_reg[7]_0\(398),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[399]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(399),
      Q => \^my_empty_reg[7]_0\(399),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(39),
      Q => \^my_empty_reg[7]_0\(39),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(3),
      Q => \^my_empty_reg[7]_0\(3),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[400]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(400),
      Q => \^my_empty_reg[7]_0\(400),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[401]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(401),
      Q => \^my_empty_reg[7]_0\(401),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[402]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(402),
      Q => \^my_empty_reg[7]_0\(402),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[403]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(403),
      Q => \^my_empty_reg[7]_0\(403),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[404]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(404),
      Q => \^my_empty_reg[7]_0\(404),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[405]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(405),
      Q => \^my_empty_reg[7]_0\(405),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[406]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(406),
      Q => \^my_empty_reg[7]_0\(406),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[407]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(407),
      Q => \^my_empty_reg[7]_0\(407),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[408]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(408),
      Q => \^my_empty_reg[7]_0\(408),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[409]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(409),
      Q => \^my_empty_reg[7]_0\(409),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(40),
      Q => \^my_empty_reg[7]_0\(40),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[410]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(410),
      Q => \^my_empty_reg[7]_0\(410),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[411]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(411),
      Q => \^my_empty_reg[7]_0\(411),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[412]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(412),
      Q => \^my_empty_reg[7]_0\(412),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[413]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(413),
      Q => \^my_empty_reg[7]_0\(413),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[414]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(414),
      Q => \^my_empty_reg[7]_0\(414),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[415]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(415),
      Q => \^my_empty_reg[7]_0\(415),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[416]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(416),
      Q => \^my_empty_reg[7]_0\(416),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[417]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(417),
      Q => \^my_empty_reg[7]_0\(417),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[418]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(418),
      Q => \^my_empty_reg[7]_0\(418),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[419]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(419),
      Q => \^my_empty_reg[7]_0\(419),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(41),
      Q => \^my_empty_reg[7]_0\(41),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[420]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(420),
      Q => \^my_empty_reg[7]_0\(420),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[421]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(421),
      Q => \^my_empty_reg[7]_0\(421),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[422]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(422),
      Q => \^my_empty_reg[7]_0\(422),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[423]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(423),
      Q => \^my_empty_reg[7]_0\(423),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[424]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(424),
      Q => \^my_empty_reg[7]_0\(424),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[425]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(425),
      Q => \^my_empty_reg[7]_0\(425),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[426]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(426),
      Q => \^my_empty_reg[7]_0\(426),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[427]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(427),
      Q => \^my_empty_reg[7]_0\(427),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[428]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(428),
      Q => \^my_empty_reg[7]_0\(428),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[429]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(429),
      Q => \^my_empty_reg[7]_0\(429),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(42),
      Q => \^my_empty_reg[7]_0\(42),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[430]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(430),
      Q => \^my_empty_reg[7]_0\(430),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[431]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(431),
      Q => \^my_empty_reg[7]_0\(431),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[432]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(432),
      Q => \^my_empty_reg[7]_0\(432),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[433]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(433),
      Q => \^my_empty_reg[7]_0\(433),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[434]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(434),
      Q => \^my_empty_reg[7]_0\(434),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[435]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(435),
      Q => \^my_empty_reg[7]_0\(435),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[436]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(436),
      Q => \^my_empty_reg[7]_0\(436),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[437]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(437),
      Q => \^my_empty_reg[7]_0\(437),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[438]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(438),
      Q => \^my_empty_reg[7]_0\(438),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[439]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(439),
      Q => \^my_empty_reg[7]_0\(439),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(43),
      Q => \^my_empty_reg[7]_0\(43),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[440]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(440),
      Q => \^my_empty_reg[7]_0\(440),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[441]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(441),
      Q => \^my_empty_reg[7]_0\(441),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[442]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(442),
      Q => \^my_empty_reg[7]_0\(442),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[443]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(443),
      Q => \^my_empty_reg[7]_0\(443),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[444]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(444),
      Q => \^my_empty_reg[7]_0\(444),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[445]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(445),
      Q => \^my_empty_reg[7]_0\(445),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[446]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(446),
      Q => \^my_empty_reg[7]_0\(446),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[447]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(447),
      Q => \^my_empty_reg[7]_0\(447),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[448]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(448),
      Q => \^my_empty_reg[7]_0\(448),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[449]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(449),
      Q => \^my_empty_reg[7]_0\(449),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(44),
      Q => \^my_empty_reg[7]_0\(44),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[450]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(450),
      Q => \^my_empty_reg[7]_0\(450),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[451]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(451),
      Q => \^my_empty_reg[7]_0\(451),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[452]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(452),
      Q => \^my_empty_reg[7]_0\(452),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[453]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(453),
      Q => \^my_empty_reg[7]_0\(453),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[454]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(454),
      Q => \^my_empty_reg[7]_0\(454),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[455]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(455),
      Q => \^my_empty_reg[7]_0\(455),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[456]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(456),
      Q => \^my_empty_reg[7]_0\(456),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[457]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(457),
      Q => \^my_empty_reg[7]_0\(457),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[458]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(458),
      Q => \^my_empty_reg[7]_0\(458),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[459]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(459),
      Q => \^my_empty_reg[7]_0\(459),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(45),
      Q => \^my_empty_reg[7]_0\(45),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[460]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(460),
      Q => \^my_empty_reg[7]_0\(460),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[461]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(461),
      Q => \^my_empty_reg[7]_0\(461),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[462]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(462),
      Q => \^my_empty_reg[7]_0\(462),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[463]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(463),
      Q => \^my_empty_reg[7]_0\(463),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[464]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(464),
      Q => \^my_empty_reg[7]_0\(464),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[465]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(465),
      Q => \^my_empty_reg[7]_0\(465),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[466]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(466),
      Q => \^my_empty_reg[7]_0\(466),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[467]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(467),
      Q => \^my_empty_reg[7]_0\(467),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[468]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(468),
      Q => \^my_empty_reg[7]_0\(468),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[469]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(469),
      Q => \^my_empty_reg[7]_0\(469),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(46),
      Q => \^my_empty_reg[7]_0\(46),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[470]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(470),
      Q => \^my_empty_reg[7]_0\(470),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[471]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(471),
      Q => \^my_empty_reg[7]_0\(471),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[472]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(472),
      Q => \^my_empty_reg[7]_0\(472),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[473]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(473),
      Q => \^my_empty_reg[7]_0\(473),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[474]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(474),
      Q => \^my_empty_reg[7]_0\(474),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[475]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(475),
      Q => \^my_empty_reg[7]_0\(475),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[476]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(476),
      Q => \^my_empty_reg[7]_0\(476),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[477]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(477),
      Q => \^my_empty_reg[7]_0\(477),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[478]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(478),
      Q => \^my_empty_reg[7]_0\(478),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[479]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(479),
      Q => \^my_empty_reg[7]_0\(479),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(47),
      Q => \^my_empty_reg[7]_0\(47),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[480]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(480),
      Q => \^my_empty_reg[7]_0\(480),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[481]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(481),
      Q => \^my_empty_reg[7]_0\(481),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[482]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(482),
      Q => \^my_empty_reg[7]_0\(482),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[483]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(483),
      Q => \^my_empty_reg[7]_0\(483),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[484]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(484),
      Q => \^my_empty_reg[7]_0\(484),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[485]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(485),
      Q => \^my_empty_reg[7]_0\(485),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[486]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(486),
      Q => \^my_empty_reg[7]_0\(486),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[487]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(487),
      Q => \^my_empty_reg[7]_0\(487),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[488]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(488),
      Q => \^my_empty_reg[7]_0\(488),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[489]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(489),
      Q => \^my_empty_reg[7]_0\(489),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(48),
      Q => \^my_empty_reg[7]_0\(48),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[490]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(490),
      Q => \^my_empty_reg[7]_0\(490),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[491]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(491),
      Q => \^my_empty_reg[7]_0\(491),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[492]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(492),
      Q => \^my_empty_reg[7]_0\(492),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[493]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(493),
      Q => \^my_empty_reg[7]_0\(493),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[494]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(494),
      Q => \^my_empty_reg[7]_0\(494),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[495]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(495),
      Q => \^my_empty_reg[7]_0\(495),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[496]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(496),
      Q => \^my_empty_reg[7]_0\(496),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[497]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(497),
      Q => \^my_empty_reg[7]_0\(497),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[498]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(498),
      Q => \^my_empty_reg[7]_0\(498),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[499]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(499),
      Q => \^my_empty_reg[7]_0\(499),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(49),
      Q => \^my_empty_reg[7]_0\(49),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(4),
      Q => \^my_empty_reg[7]_0\(4),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[500]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(500),
      Q => \^my_empty_reg[7]_0\(500),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[501]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(501),
      Q => \^my_empty_reg[7]_0\(501),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[502]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(502),
      Q => \^my_empty_reg[7]_0\(502),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[503]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(503),
      Q => \^my_empty_reg[7]_0\(503),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[504]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(504),
      Q => \^my_empty_reg[7]_0\(504),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[505]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(505),
      Q => \^my_empty_reg[7]_0\(505),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[506]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(506),
      Q => \^my_empty_reg[7]_0\(506),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[507]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(507),
      Q => \^my_empty_reg[7]_0\(507),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[508]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(508),
      Q => \^my_empty_reg[7]_0\(508),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[509]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(509),
      Q => \^my_empty_reg[7]_0\(509),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(50),
      Q => \^my_empty_reg[7]_0\(50),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[510]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(510),
      Q => \^my_empty_reg[7]_0\(510),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[511]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(511),
      Q => \^my_empty_reg[7]_0\(511),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[512]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(512),
      Q => \^my_empty_reg[7]_0\(512),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[513]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(513),
      Q => \^my_empty_reg[7]_0\(513),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[514]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(514),
      Q => \^my_empty_reg[7]_0\(514),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[515]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(515),
      Q => \^my_empty_reg[7]_0\(515),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[516]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(516),
      Q => \^my_empty_reg[7]_0\(516),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[517]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(517),
      Q => \^my_empty_reg[7]_0\(517),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[518]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(518),
      Q => \^my_empty_reg[7]_0\(518),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[519]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(519),
      Q => \^my_empty_reg[7]_0\(519),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(51),
      Q => \^my_empty_reg[7]_0\(51),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[520]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(520),
      Q => \^my_empty_reg[7]_0\(520),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[521]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(521),
      Q => \^my_empty_reg[7]_0\(521),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[522]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(522),
      Q => \^my_empty_reg[7]_0\(522),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[523]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(523),
      Q => \^my_empty_reg[7]_0\(523),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[524]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(524),
      Q => \^my_empty_reg[7]_0\(524),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[525]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(525),
      Q => \^my_empty_reg[7]_0\(525),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[526]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(526),
      Q => \^my_empty_reg[7]_0\(526),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[527]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(527),
      Q => \^my_empty_reg[7]_0\(527),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[528]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(528),
      Q => \^my_empty_reg[7]_0\(528),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[529]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(529),
      Q => \^my_empty_reg[7]_0\(529),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(52),
      Q => \^my_empty_reg[7]_0\(52),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[530]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(530),
      Q => \^my_empty_reg[7]_0\(530),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[531]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(531),
      Q => \^my_empty_reg[7]_0\(531),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[532]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(532),
      Q => \^my_empty_reg[7]_0\(532),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[533]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(533),
      Q => \^my_empty_reg[7]_0\(533),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[534]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(534),
      Q => \^my_empty_reg[7]_0\(534),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[535]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(535),
      Q => \^my_empty_reg[7]_0\(535),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[536]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(536),
      Q => \^my_empty_reg[7]_0\(536),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[537]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(537),
      Q => \^my_empty_reg[7]_0\(537),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[538]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(538),
      Q => \^my_empty_reg[7]_0\(538),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[539]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(539),
      Q => \^my_empty_reg[7]_0\(539),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(53),
      Q => \^my_empty_reg[7]_0\(53),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[540]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(540),
      Q => \^my_empty_reg[7]_0\(540),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[541]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(541),
      Q => \^my_empty_reg[7]_0\(541),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[542]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(542),
      Q => \^my_empty_reg[7]_0\(542),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[543]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(543),
      Q => \^my_empty_reg[7]_0\(543),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[544]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(544),
      Q => \^my_empty_reg[7]_0\(544),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[545]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(545),
      Q => \^my_empty_reg[7]_0\(545),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[546]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(546),
      Q => \^my_empty_reg[7]_0\(546),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[547]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(547),
      Q => \^my_empty_reg[7]_0\(547),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[548]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(548),
      Q => \^my_empty_reg[7]_0\(548),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[549]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(549),
      Q => \^my_empty_reg[7]_0\(549),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(54),
      Q => \^my_empty_reg[7]_0\(54),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[550]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(550),
      Q => \^my_empty_reg[7]_0\(550),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[551]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(551),
      Q => \^my_empty_reg[7]_0\(551),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[552]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(552),
      Q => \^my_empty_reg[7]_0\(552),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[553]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(553),
      Q => \^my_empty_reg[7]_0\(553),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[554]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(554),
      Q => \^my_empty_reg[7]_0\(554),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[555]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(555),
      Q => \^my_empty_reg[7]_0\(555),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[556]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(556),
      Q => \^my_empty_reg[7]_0\(556),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[557]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(557),
      Q => \^my_empty_reg[7]_0\(557),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[558]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(558),
      Q => \^my_empty_reg[7]_0\(558),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[559]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(559),
      Q => \^my_empty_reg[7]_0\(559),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(55),
      Q => \^my_empty_reg[7]_0\(55),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[560]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(560),
      Q => \^my_empty_reg[7]_0\(560),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[561]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(561),
      Q => \^my_empty_reg[7]_0\(561),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[562]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(562),
      Q => \^my_empty_reg[7]_0\(562),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[563]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(563),
      Q => \^my_empty_reg[7]_0\(563),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[564]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(564),
      Q => \^my_empty_reg[7]_0\(564),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[565]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(565),
      Q => \^my_empty_reg[7]_0\(565),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[566]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(566),
      Q => \^my_empty_reg[7]_0\(566),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[567]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(567),
      Q => \^my_empty_reg[7]_0\(567),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[568]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(568),
      Q => \^my_empty_reg[7]_0\(568),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[569]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(569),
      Q => \^my_empty_reg[7]_0\(569),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(56),
      Q => \^my_empty_reg[7]_0\(56),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[570]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(570),
      Q => \^my_empty_reg[7]_0\(570),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[571]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(571),
      Q => \^my_empty_reg[7]_0\(571),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[572]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(572),
      Q => \^my_empty_reg[7]_0\(572),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[573]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(573),
      Q => \^my_empty_reg[7]_0\(573),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[574]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(574),
      Q => \^my_empty_reg[7]_0\(574),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[575]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(575),
      Q => \^my_empty_reg[7]_0\(575),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(57),
      Q => \^my_empty_reg[7]_0\(57),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(58),
      Q => \^my_empty_reg[7]_0\(58),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(59),
      Q => \^my_empty_reg[7]_0\(59),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(5),
      Q => \^my_empty_reg[7]_0\(5),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(60),
      Q => \^my_empty_reg[7]_0\(60),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(61),
      Q => \^my_empty_reg[7]_0\(61),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(62),
      Q => \^my_empty_reg[7]_0\(62),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(63),
      Q => \^my_empty_reg[7]_0\(63),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(64),
      Q => \^my_empty_reg[7]_0\(64),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(65),
      Q => \^my_empty_reg[7]_0\(65),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(66),
      Q => \^my_empty_reg[7]_0\(66),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(67),
      Q => \^my_empty_reg[7]_0\(67),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(68),
      Q => \^my_empty_reg[7]_0\(68),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(69),
      Q => \^my_empty_reg[7]_0\(69),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(6),
      Q => \^my_empty_reg[7]_0\(6),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(70),
      Q => \^my_empty_reg[7]_0\(70),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(71),
      Q => \^my_empty_reg[7]_0\(71),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(72),
      Q => \^my_empty_reg[7]_0\(72),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(73),
      Q => \^my_empty_reg[7]_0\(73),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(74),
      Q => \^my_empty_reg[7]_0\(74),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(75),
      Q => \^my_empty_reg[7]_0\(75),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(76),
      Q => \^my_empty_reg[7]_0\(76),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(77),
      Q => \^my_empty_reg[7]_0\(77),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(78),
      Q => \^my_empty_reg[7]_0\(78),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(79),
      Q => \^my_empty_reg[7]_0\(79),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(7),
      Q => \^my_empty_reg[7]_0\(7),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(80),
      Q => \^my_empty_reg[7]_0\(80),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(81),
      Q => \^my_empty_reg[7]_0\(81),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(82),
      Q => \^my_empty_reg[7]_0\(82),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(83),
      Q => \^my_empty_reg[7]_0\(83),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(84),
      Q => \^my_empty_reg[7]_0\(84),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(85),
      Q => \^my_empty_reg[7]_0\(85),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(86),
      Q => \^my_empty_reg[7]_0\(86),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(87),
      Q => \^my_empty_reg[7]_0\(87),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(88),
      Q => \^my_empty_reg[7]_0\(88),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(89),
      Q => \^my_empty_reg[7]_0\(89),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(8),
      Q => \^my_empty_reg[7]_0\(8),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(90),
      Q => \^my_empty_reg[7]_0\(90),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(91),
      Q => \^my_empty_reg[7]_0\(91),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(92),
      Q => \^my_empty_reg[7]_0\(92),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(93),
      Q => \^my_empty_reg[7]_0\(93),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(94),
      Q => \^my_empty_reg[7]_0\(94),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(95),
      Q => \^my_empty_reg[7]_0\(95),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(96),
      Q => \^my_empty_reg[7]_0\(96),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(97),
      Q => \^my_empty_reg[7]_0\(97),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(98),
      Q => \^my_empty_reg[7]_0\(98),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(99),
      Q => \^my_empty_reg[7]_0\(99),
      R => '0'
    );
\write_buffer.wr_buf_out_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wr_buf_out_data_w(9),
      Q => \^my_empty_reg[7]_0\(9),
      R => '0'
    );
\write_buffer.wr_buffer_ram[0].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(5 downto 4),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(3 downto 2),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(1 downto 0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(5 downto 4),
      DOB(1 downto 0) => wr_buf_out_data_w(3 downto 2),
      DOC(1 downto 0) => wr_buf_out_data_w(1 downto 0),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(5),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(5),
      O => \write_buffer.wr_buf_in_data\(5)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(0),
      I1 => \write_data_control.wb_wr_data_addr_r\(1),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => reset_reg,
      O => wb_wr_data_addr_w(1)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02020F00"
    )
        port map (
      I0 => app_wdf_rdy_r_copy3,
      I1 => app_wdf_end_r1,
      I2 => reset_reg,
      I3 => \write_data_control.wb_wr_data_addr0_r\,
      I4 => app_wdf_wren_r1,
      O => \write_data_control.wb_wr_data_addr0_ns\
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(4),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(4),
      O => \write_buffer.wr_buf_in_data\(4)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(3),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(3),
      O => \write_buffer.wr_buf_in_data\(3)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(2),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(2),
      O => \write_buffer.wr_buf_in_data\(2)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(1),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(1),
      O => \write_buffer.wr_buf_in_data\(1)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(0),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(0),
      O => \write_buffer.wr_buf_in_data\(0)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(3),
      I1 => \write_data_control.wb_wr_data_addr_r\(4),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => reset_reg,
      O => wb_wr_data_addr_w(4)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(2),
      I1 => \write_data_control.wb_wr_data_addr_r\(3),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => reset_reg,
      O => wb_wr_data_addr_w(3)
    );
\write_buffer.wr_buffer_ram[0].RAM32M0_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => wr_data_pntr(1),
      I1 => \write_data_control.wb_wr_data_addr_r\(2),
      I2 => \write_data_control.wr_data_addr_le\,
      I3 => reset_reg,
      O => wb_wr_data_addr_w(2)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(65 downto 64),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(63 downto 62),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(61 downto 60),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(65 downto 64),
      DOB(1 downto 0) => wr_buf_out_data_w(63 downto 62),
      DOC(1 downto 0) => wr_buf_out_data_w(61 downto 60),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(65),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(65),
      O => \write_buffer.wr_buf_in_data\(65)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(64),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(64),
      O => \write_buffer.wr_buf_in_data\(64)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(63),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(63),
      O => \write_buffer.wr_buf_in_data\(63)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(62),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(62),
      O => \write_buffer.wr_buf_in_data\(62)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(61),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(61),
      O => \write_buffer.wr_buf_in_data\(61)
    );
\write_buffer.wr_buffer_ram[10].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(60),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(60),
      O => \write_buffer.wr_buf_in_data\(60)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(71 downto 70),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(69 downto 68),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(67 downto 66),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(71 downto 70),
      DOB(1 downto 0) => wr_buf_out_data_w(69 downto 68),
      DOC(1 downto 0) => wr_buf_out_data_w(67 downto 66),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(71),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(71),
      O => \write_buffer.wr_buf_in_data\(71)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(70),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(70),
      O => \write_buffer.wr_buf_in_data\(70)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(69),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(69),
      O => \write_buffer.wr_buf_in_data\(69)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(68),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(68),
      O => \write_buffer.wr_buf_in_data\(68)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(67),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(67),
      O => \write_buffer.wr_buf_in_data\(67)
    );
\write_buffer.wr_buffer_ram[11].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(66),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(66),
      O => \write_buffer.wr_buf_in_data\(66)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(77 downto 76),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(75 downto 74),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(73 downto 72),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(77 downto 76),
      DOB(1 downto 0) => wr_buf_out_data_w(75 downto 74),
      DOC(1 downto 0) => wr_buf_out_data_w(73 downto 72),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(77),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(77),
      O => \write_buffer.wr_buf_in_data\(77)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(76),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(76),
      O => \write_buffer.wr_buf_in_data\(76)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(75),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(75),
      O => \write_buffer.wr_buf_in_data\(75)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(74),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(74),
      O => \write_buffer.wr_buf_in_data\(74)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(73),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(73),
      O => \write_buffer.wr_buf_in_data\(73)
    );
\write_buffer.wr_buffer_ram[12].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(72),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(72),
      O => \write_buffer.wr_buf_in_data\(72)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(83 downto 82),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(81 downto 80),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(79 downto 78),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(83 downto 82),
      DOB(1 downto 0) => wr_buf_out_data_w(81 downto 80),
      DOC(1 downto 0) => wr_buf_out_data_w(79 downto 78),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(83),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(83),
      O => \write_buffer.wr_buf_in_data\(83)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(82),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(82),
      O => \write_buffer.wr_buf_in_data\(82)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(81),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(81),
      O => \write_buffer.wr_buf_in_data\(81)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(80),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(80),
      O => \write_buffer.wr_buf_in_data\(80)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(79),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(79),
      O => \write_buffer.wr_buf_in_data\(79)
    );
\write_buffer.wr_buffer_ram[13].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(78),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(78),
      O => \write_buffer.wr_buf_in_data\(78)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(89 downto 88),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(87 downto 86),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(85 downto 84),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(89 downto 88),
      DOB(1 downto 0) => wr_buf_out_data_w(87 downto 86),
      DOC(1 downto 0) => wr_buf_out_data_w(85 downto 84),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(89),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(89),
      O => \write_buffer.wr_buf_in_data\(89)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(88),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(88),
      O => \write_buffer.wr_buf_in_data\(88)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(87),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(87),
      O => \write_buffer.wr_buf_in_data\(87)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(86),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(86),
      O => \write_buffer.wr_buf_in_data\(86)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(85),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(85),
      O => \write_buffer.wr_buf_in_data\(85)
    );
\write_buffer.wr_buffer_ram[14].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(84),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(84),
      O => \write_buffer.wr_buf_in_data\(84)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(95 downto 94),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(93 downto 92),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(91 downto 90),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(95 downto 94),
      DOB(1 downto 0) => wr_buf_out_data_w(93 downto 92),
      DOC(1 downto 0) => wr_buf_out_data_w(91 downto 90),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(95),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(95),
      O => \write_buffer.wr_buf_in_data\(95)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(94),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(94),
      O => \write_buffer.wr_buf_in_data\(94)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(93),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(93),
      O => \write_buffer.wr_buf_in_data\(93)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(92),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(92),
      O => \write_buffer.wr_buf_in_data\(92)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(91),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(91),
      O => \write_buffer.wr_buf_in_data\(91)
    );
\write_buffer.wr_buffer_ram[15].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(90),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(90),
      O => \write_buffer.wr_buf_in_data\(90)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(101 downto 100),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(99 downto 98),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(97 downto 96),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(101 downto 100),
      DOB(1 downto 0) => wr_buf_out_data_w(99 downto 98),
      DOC(1 downto 0) => wr_buf_out_data_w(97 downto 96),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(101),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(101),
      O => \write_buffer.wr_buf_in_data\(101)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(100),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(100),
      O => \write_buffer.wr_buf_in_data\(100)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(99),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(99),
      O => \write_buffer.wr_buf_in_data\(99)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(98),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(98),
      O => \write_buffer.wr_buf_in_data\(98)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(97),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(97),
      O => \write_buffer.wr_buf_in_data\(97)
    );
\write_buffer.wr_buffer_ram[16].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(96),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(96),
      O => \write_buffer.wr_buf_in_data\(96)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(107 downto 106),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(105 downto 104),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(103 downto 102),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(107 downto 106),
      DOB(1 downto 0) => wr_buf_out_data_w(105 downto 104),
      DOC(1 downto 0) => wr_buf_out_data_w(103 downto 102),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(107),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(107),
      O => \write_buffer.wr_buf_in_data\(107)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(106),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(106),
      O => \write_buffer.wr_buf_in_data\(106)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(105),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(105),
      O => \write_buffer.wr_buf_in_data\(105)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(104),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(104),
      O => \write_buffer.wr_buf_in_data\(104)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(103),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(103),
      O => \write_buffer.wr_buf_in_data\(103)
    );
\write_buffer.wr_buffer_ram[17].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(102),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(102),
      O => \write_buffer.wr_buf_in_data\(102)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(113 downto 112),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(111 downto 110),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(109 downto 108),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(113 downto 112),
      DOB(1 downto 0) => wr_buf_out_data_w(111 downto 110),
      DOC(1 downto 0) => wr_buf_out_data_w(109 downto 108),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(113),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(113),
      O => \write_buffer.wr_buf_in_data\(113)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(112),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(112),
      O => \write_buffer.wr_buf_in_data\(112)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(111),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(111),
      O => \write_buffer.wr_buf_in_data\(111)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(110),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(110),
      O => \write_buffer.wr_buf_in_data\(110)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(109),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(109),
      O => \write_buffer.wr_buf_in_data\(109)
    );
\write_buffer.wr_buffer_ram[18].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(108),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(108),
      O => \write_buffer.wr_buf_in_data\(108)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(119 downto 118),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(117 downto 116),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(115 downto 114),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(119 downto 118),
      DOB(1 downto 0) => wr_buf_out_data_w(117 downto 116),
      DOC(1 downto 0) => wr_buf_out_data_w(115 downto 114),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(119),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(119),
      O => \write_buffer.wr_buf_in_data\(119)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(118),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(118),
      O => \write_buffer.wr_buf_in_data\(118)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(117),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(117),
      O => \write_buffer.wr_buf_in_data\(117)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(116),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(116),
      O => \write_buffer.wr_buf_in_data\(116)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(115),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(115),
      O => \write_buffer.wr_buf_in_data\(115)
    );
\write_buffer.wr_buffer_ram[19].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(114),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(114),
      O => \write_buffer.wr_buf_in_data\(114)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(11 downto 10),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(9 downto 8),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(7 downto 6),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(11 downto 10),
      DOB(1 downto 0) => wr_buf_out_data_w(9 downto 8),
      DOC(1 downto 0) => wr_buf_out_data_w(7 downto 6),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(11),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(11),
      O => \write_buffer.wr_buf_in_data\(11)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(10),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(10),
      O => \write_buffer.wr_buf_in_data\(10)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(9),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(9),
      O => \write_buffer.wr_buf_in_data\(9)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(8),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(8),
      O => \write_buffer.wr_buf_in_data\(8)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(7),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(7),
      O => \write_buffer.wr_buf_in_data\(7)
    );
\write_buffer.wr_buffer_ram[1].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(6),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(6),
      O => \write_buffer.wr_buf_in_data\(6)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(125 downto 124),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(123 downto 122),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(121 downto 120),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(125 downto 124),
      DOB(1 downto 0) => wr_buf_out_data_w(123 downto 122),
      DOC(1 downto 0) => wr_buf_out_data_w(121 downto 120),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(125),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(125),
      O => \write_buffer.wr_buf_in_data\(125)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(124),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(124),
      O => \write_buffer.wr_buf_in_data\(124)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(123),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(123),
      O => \write_buffer.wr_buf_in_data\(123)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(122),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(122),
      O => \write_buffer.wr_buf_in_data\(122)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(121),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(121),
      O => \write_buffer.wr_buf_in_data\(121)
    );
\write_buffer.wr_buffer_ram[20].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(120),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(120),
      O => \write_buffer.wr_buf_in_data\(120)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(131 downto 130),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(129 downto 128),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(127 downto 126),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(131 downto 130),
      DOB(1 downto 0) => wr_buf_out_data_w(129 downto 128),
      DOC(1 downto 0) => wr_buf_out_data_w(127 downto 126),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(131),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(131),
      O => \write_buffer.wr_buf_in_data\(131)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(130),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(130),
      O => \write_buffer.wr_buf_in_data\(130)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(129),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(129),
      O => \write_buffer.wr_buf_in_data\(129)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(128),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(128),
      O => \write_buffer.wr_buf_in_data\(128)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(127),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(127),
      O => \write_buffer.wr_buf_in_data\(127)
    );
\write_buffer.wr_buffer_ram[21].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(126),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(126),
      O => \write_buffer.wr_buf_in_data\(126)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(137 downto 136),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(135 downto 134),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(133 downto 132),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(137 downto 136),
      DOB(1 downto 0) => wr_buf_out_data_w(135 downto 134),
      DOC(1 downto 0) => wr_buf_out_data_w(133 downto 132),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(137),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(137),
      O => \write_buffer.wr_buf_in_data\(137)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(136),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(136),
      O => \write_buffer.wr_buf_in_data\(136)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(135),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(135),
      O => \write_buffer.wr_buf_in_data\(135)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(134),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(134),
      O => \write_buffer.wr_buf_in_data\(134)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(133),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(133),
      O => \write_buffer.wr_buf_in_data\(133)
    );
\write_buffer.wr_buffer_ram[22].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(132),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(132),
      O => \write_buffer.wr_buf_in_data\(132)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(143 downto 142),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(141 downto 140),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(139 downto 138),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(143 downto 142),
      DOB(1 downto 0) => wr_buf_out_data_w(141 downto 140),
      DOC(1 downto 0) => wr_buf_out_data_w(139 downto 138),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(143),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(143),
      O => \write_buffer.wr_buf_in_data\(143)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(142),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(142),
      O => \write_buffer.wr_buf_in_data\(142)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(141),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(141),
      O => \write_buffer.wr_buf_in_data\(141)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(140),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(140),
      O => \write_buffer.wr_buf_in_data\(140)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(139),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(139),
      O => \write_buffer.wr_buf_in_data\(139)
    );
\write_buffer.wr_buffer_ram[23].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(138),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(138),
      O => \write_buffer.wr_buf_in_data\(138)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(149 downto 148),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(147 downto 146),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(145 downto 144),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(149 downto 148),
      DOB(1 downto 0) => wr_buf_out_data_w(147 downto 146),
      DOC(1 downto 0) => wr_buf_out_data_w(145 downto 144),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(149),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(149),
      O => \write_buffer.wr_buf_in_data\(149)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(148),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(148),
      O => \write_buffer.wr_buf_in_data\(148)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(147),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(147),
      O => \write_buffer.wr_buf_in_data\(147)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(146),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(146),
      O => \write_buffer.wr_buf_in_data\(146)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(145),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(145),
      O => \write_buffer.wr_buf_in_data\(145)
    );
\write_buffer.wr_buffer_ram[24].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(144),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(144),
      O => \write_buffer.wr_buf_in_data\(144)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(155 downto 154),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(153 downto 152),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(151 downto 150),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(155 downto 154),
      DOB(1 downto 0) => wr_buf_out_data_w(153 downto 152),
      DOC(1 downto 0) => wr_buf_out_data_w(151 downto 150),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(155),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(155),
      O => \write_buffer.wr_buf_in_data\(155)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(154),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(154),
      O => \write_buffer.wr_buf_in_data\(154)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(153),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(153),
      O => \write_buffer.wr_buf_in_data\(153)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(152),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(152),
      O => \write_buffer.wr_buf_in_data\(152)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(151),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(151),
      O => \write_buffer.wr_buf_in_data\(151)
    );
\write_buffer.wr_buffer_ram[25].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(150),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(150),
      O => \write_buffer.wr_buf_in_data\(150)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(161 downto 160),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(159 downto 158),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(157 downto 156),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(161 downto 160),
      DOB(1 downto 0) => wr_buf_out_data_w(159 downto 158),
      DOC(1 downto 0) => wr_buf_out_data_w(157 downto 156),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(161),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(161),
      O => \write_buffer.wr_buf_in_data\(161)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(160),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(160),
      O => \write_buffer.wr_buf_in_data\(160)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(159),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(159),
      O => \write_buffer.wr_buf_in_data\(159)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(158),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(158),
      O => \write_buffer.wr_buf_in_data\(158)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(157),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(157),
      O => \write_buffer.wr_buf_in_data\(157)
    );
\write_buffer.wr_buffer_ram[26].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(156),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(156),
      O => \write_buffer.wr_buf_in_data\(156)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(167 downto 166),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(165 downto 164),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(163 downto 162),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(167 downto 166),
      DOB(1 downto 0) => wr_buf_out_data_w(165 downto 164),
      DOC(1 downto 0) => wr_buf_out_data_w(163 downto 162),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(167),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(167),
      O => \write_buffer.wr_buf_in_data\(167)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(166),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(166),
      O => \write_buffer.wr_buf_in_data\(166)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(165),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(165),
      O => \write_buffer.wr_buf_in_data\(165)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(164),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(164),
      O => \write_buffer.wr_buf_in_data\(164)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(163),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(163),
      O => \write_buffer.wr_buf_in_data\(163)
    );
\write_buffer.wr_buffer_ram[27].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(162),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(162),
      O => \write_buffer.wr_buf_in_data\(162)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(173 downto 172),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(171 downto 170),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(169 downto 168),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(173 downto 172),
      DOB(1 downto 0) => wr_buf_out_data_w(171 downto 170),
      DOC(1 downto 0) => wr_buf_out_data_w(169 downto 168),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(173),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(173),
      O => \write_buffer.wr_buf_in_data\(173)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(172),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(172),
      O => \write_buffer.wr_buf_in_data\(172)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(171),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(171),
      O => \write_buffer.wr_buf_in_data\(171)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(170),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(170),
      O => \write_buffer.wr_buf_in_data\(170)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(169),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(169),
      O => \write_buffer.wr_buf_in_data\(169)
    );
\write_buffer.wr_buffer_ram[28].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(168),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(168),
      O => \write_buffer.wr_buf_in_data\(168)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(179 downto 178),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(177 downto 176),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(175 downto 174),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(179 downto 178),
      DOB(1 downto 0) => wr_buf_out_data_w(177 downto 176),
      DOC(1 downto 0) => wr_buf_out_data_w(175 downto 174),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(179),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(179),
      O => \write_buffer.wr_buf_in_data\(179)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(178),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(178),
      O => \write_buffer.wr_buf_in_data\(178)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(177),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(177),
      O => \write_buffer.wr_buf_in_data\(177)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(176),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(176),
      O => \write_buffer.wr_buf_in_data\(176)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(175),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(175),
      O => \write_buffer.wr_buf_in_data\(175)
    );
\write_buffer.wr_buffer_ram[29].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(174),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(174),
      O => \write_buffer.wr_buf_in_data\(174)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(17 downto 16),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(15 downto 14),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(13 downto 12),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(17 downto 16),
      DOB(1 downto 0) => wr_buf_out_data_w(15 downto 14),
      DOC(1 downto 0) => wr_buf_out_data_w(13 downto 12),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(17),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(17),
      O => \write_buffer.wr_buf_in_data\(17)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(16),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(16),
      O => \write_buffer.wr_buf_in_data\(16)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(15),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(15),
      O => \write_buffer.wr_buf_in_data\(15)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(14),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(14),
      O => \write_buffer.wr_buf_in_data\(14)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(13),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(13),
      O => \write_buffer.wr_buf_in_data\(13)
    );
\write_buffer.wr_buffer_ram[2].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(12),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(12),
      O => \write_buffer.wr_buf_in_data\(12)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(185 downto 184),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(183 downto 182),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(181 downto 180),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(185 downto 184),
      DOB(1 downto 0) => wr_buf_out_data_w(183 downto 182),
      DOC(1 downto 0) => wr_buf_out_data_w(181 downto 180),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(185),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(185),
      O => \write_buffer.wr_buf_in_data\(185)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(184),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(184),
      O => \write_buffer.wr_buf_in_data\(184)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(183),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(183),
      O => \write_buffer.wr_buf_in_data\(183)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(182),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(182),
      O => \write_buffer.wr_buf_in_data\(182)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(181),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(181),
      O => \write_buffer.wr_buf_in_data\(181)
    );
\write_buffer.wr_buffer_ram[30].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(180),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(180),
      O => \write_buffer.wr_buf_in_data\(180)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(191 downto 190),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(189 downto 188),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(187 downto 186),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(191 downto 190),
      DOB(1 downto 0) => wr_buf_out_data_w(189 downto 188),
      DOC(1 downto 0) => wr_buf_out_data_w(187 downto 186),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(191),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(191),
      O => \write_buffer.wr_buf_in_data\(191)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(190),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(190),
      O => \write_buffer.wr_buf_in_data\(190)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(189),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(189),
      O => \write_buffer.wr_buf_in_data\(189)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(188),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(188),
      O => \write_buffer.wr_buf_in_data\(188)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(187),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(187),
      O => \write_buffer.wr_buf_in_data\(187)
    );
\write_buffer.wr_buffer_ram[31].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(186),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(186),
      O => \write_buffer.wr_buf_in_data\(186)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(197 downto 196),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(195 downto 194),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(193 downto 192),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(197 downto 196),
      DOB(1 downto 0) => wr_buf_out_data_w(195 downto 194),
      DOC(1 downto 0) => wr_buf_out_data_w(193 downto 192),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(197),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(197),
      O => \write_buffer.wr_buf_in_data\(197)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(196),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(196),
      O => \write_buffer.wr_buf_in_data\(196)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(195),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(195),
      O => \write_buffer.wr_buf_in_data\(195)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(194),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(194),
      O => \write_buffer.wr_buf_in_data\(194)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(193),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(193),
      O => \write_buffer.wr_buf_in_data\(193)
    );
\write_buffer.wr_buffer_ram[32].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(192),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(192),
      O => \write_buffer.wr_buf_in_data\(192)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(203 downto 202),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(201 downto 200),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(199 downto 198),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(203 downto 202),
      DOB(1 downto 0) => wr_buf_out_data_w(201 downto 200),
      DOC(1 downto 0) => wr_buf_out_data_w(199 downto 198),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(203),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(203),
      O => \write_buffer.wr_buf_in_data\(203)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(202),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(202),
      O => \write_buffer.wr_buf_in_data\(202)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(201),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(201),
      O => \write_buffer.wr_buf_in_data\(201)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(200),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(200),
      O => \write_buffer.wr_buf_in_data\(200)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(199),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(199),
      O => \write_buffer.wr_buf_in_data\(199)
    );
\write_buffer.wr_buffer_ram[33].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(198),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(198),
      O => \write_buffer.wr_buf_in_data\(198)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(209 downto 208),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(207 downto 206),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(205 downto 204),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(209 downto 208),
      DOB(1 downto 0) => wr_buf_out_data_w(207 downto 206),
      DOC(1 downto 0) => wr_buf_out_data_w(205 downto 204),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(209),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(209),
      O => \write_buffer.wr_buf_in_data\(209)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(208),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(208),
      O => \write_buffer.wr_buf_in_data\(208)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(207),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(207),
      O => \write_buffer.wr_buf_in_data\(207)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(206),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(206),
      O => \write_buffer.wr_buf_in_data\(206)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(205),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(205),
      O => \write_buffer.wr_buf_in_data\(205)
    );
\write_buffer.wr_buffer_ram[34].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(204),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(204),
      O => \write_buffer.wr_buf_in_data\(204)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(215 downto 214),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(213 downto 212),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(211 downto 210),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(215 downto 214),
      DOB(1 downto 0) => wr_buf_out_data_w(213 downto 212),
      DOC(1 downto 0) => wr_buf_out_data_w(211 downto 210),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(215),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(215),
      O => \write_buffer.wr_buf_in_data\(215)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(214),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(214),
      O => \write_buffer.wr_buf_in_data\(214)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(213),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(213),
      O => \write_buffer.wr_buf_in_data\(213)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(212),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(212),
      O => \write_buffer.wr_buf_in_data\(212)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(211),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(211),
      O => \write_buffer.wr_buf_in_data\(211)
    );
\write_buffer.wr_buffer_ram[35].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(210),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(210),
      O => \write_buffer.wr_buf_in_data\(210)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(221 downto 220),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(219 downto 218),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(217 downto 216),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(221 downto 220),
      DOB(1 downto 0) => wr_buf_out_data_w(219 downto 218),
      DOC(1 downto 0) => wr_buf_out_data_w(217 downto 216),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(221),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(221),
      O => \write_buffer.wr_buf_in_data\(221)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(220),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(220),
      O => \write_buffer.wr_buf_in_data\(220)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(219),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(219),
      O => \write_buffer.wr_buf_in_data\(219)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(218),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(218),
      O => \write_buffer.wr_buf_in_data\(218)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(217),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(217),
      O => \write_buffer.wr_buf_in_data\(217)
    );
\write_buffer.wr_buffer_ram[36].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(216),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(216),
      O => \write_buffer.wr_buf_in_data\(216)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(227 downto 226),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(225 downto 224),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(223 downto 222),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(227 downto 226),
      DOB(1 downto 0) => wr_buf_out_data_w(225 downto 224),
      DOC(1 downto 0) => wr_buf_out_data_w(223 downto 222),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(227),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(227),
      O => \write_buffer.wr_buf_in_data\(227)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(226),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(226),
      O => \write_buffer.wr_buf_in_data\(226)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(225),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(225),
      O => \write_buffer.wr_buf_in_data\(225)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(224),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(224),
      O => \write_buffer.wr_buf_in_data\(224)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(223),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(223),
      O => \write_buffer.wr_buf_in_data\(223)
    );
\write_buffer.wr_buffer_ram[37].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(222),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(222),
      O => \write_buffer.wr_buf_in_data\(222)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(233 downto 232),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(231 downto 230),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(229 downto 228),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(233 downto 232),
      DOB(1 downto 0) => wr_buf_out_data_w(231 downto 230),
      DOC(1 downto 0) => wr_buf_out_data_w(229 downto 228),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(233),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(233),
      O => \write_buffer.wr_buf_in_data\(233)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(232),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(232),
      O => \write_buffer.wr_buf_in_data\(232)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(231),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(231),
      O => \write_buffer.wr_buf_in_data\(231)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(230),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(230),
      O => \write_buffer.wr_buf_in_data\(230)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(229),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(229),
      O => \write_buffer.wr_buf_in_data\(229)
    );
\write_buffer.wr_buffer_ram[38].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(228),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(228),
      O => \write_buffer.wr_buf_in_data\(228)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(239 downto 238),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(237 downto 236),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(235 downto 234),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(239 downto 238),
      DOB(1 downto 0) => wr_buf_out_data_w(237 downto 236),
      DOC(1 downto 0) => wr_buf_out_data_w(235 downto 234),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(239),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(239),
      O => \write_buffer.wr_buf_in_data\(239)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(238),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(238),
      O => \write_buffer.wr_buf_in_data\(238)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(237),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(237),
      O => \write_buffer.wr_buf_in_data\(237)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(236),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(236),
      O => \write_buffer.wr_buf_in_data\(236)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(235),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(235),
      O => \write_buffer.wr_buf_in_data\(235)
    );
\write_buffer.wr_buffer_ram[39].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(234),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(234),
      O => \write_buffer.wr_buf_in_data\(234)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(23 downto 22),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(21 downto 20),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(19 downto 18),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(23 downto 22),
      DOB(1 downto 0) => wr_buf_out_data_w(21 downto 20),
      DOC(1 downto 0) => wr_buf_out_data_w(19 downto 18),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(23),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(23),
      O => \write_buffer.wr_buf_in_data\(23)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(22),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(22),
      O => \write_buffer.wr_buf_in_data\(22)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(21),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(21),
      O => \write_buffer.wr_buf_in_data\(21)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(20),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(20),
      O => \write_buffer.wr_buf_in_data\(20)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(19),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(19),
      O => \write_buffer.wr_buf_in_data\(19)
    );
\write_buffer.wr_buffer_ram[3].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(18),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(18),
      O => \write_buffer.wr_buf_in_data\(18)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(245 downto 244),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(243 downto 242),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(241 downto 240),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(245 downto 244),
      DOB(1 downto 0) => wr_buf_out_data_w(243 downto 242),
      DOC(1 downto 0) => wr_buf_out_data_w(241 downto 240),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(245),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(245),
      O => \write_buffer.wr_buf_in_data\(245)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(244),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(244),
      O => \write_buffer.wr_buf_in_data\(244)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(243),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(243),
      O => \write_buffer.wr_buf_in_data\(243)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(242),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(242),
      O => \write_buffer.wr_buf_in_data\(242)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(241),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(241),
      O => \write_buffer.wr_buf_in_data\(241)
    );
\write_buffer.wr_buffer_ram[40].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(240),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(240),
      O => \write_buffer.wr_buf_in_data\(240)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(251 downto 250),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(249 downto 248),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(247 downto 246),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(251 downto 250),
      DOB(1 downto 0) => wr_buf_out_data_w(249 downto 248),
      DOC(1 downto 0) => wr_buf_out_data_w(247 downto 246),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(251),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(251),
      O => \write_buffer.wr_buf_in_data\(251)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(250),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(250),
      O => \write_buffer.wr_buf_in_data\(250)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(249),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(249),
      O => \write_buffer.wr_buf_in_data\(249)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(248),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(248),
      O => \write_buffer.wr_buf_in_data\(248)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(247),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(247),
      O => \write_buffer.wr_buf_in_data\(247)
    );
\write_buffer.wr_buffer_ram[41].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(246),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(246),
      O => \write_buffer.wr_buf_in_data\(246)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(257 downto 256),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(255 downto 254),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(253 downto 252),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(257 downto 256),
      DOB(1 downto 0) => wr_buf_out_data_w(255 downto 254),
      DOC(1 downto 0) => wr_buf_out_data_w(253 downto 252),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(257),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(257),
      O => \write_buffer.wr_buf_in_data\(257)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(256),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(256),
      O => \write_buffer.wr_buf_in_data\(256)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(255),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(255),
      O => \write_buffer.wr_buf_in_data\(255)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(254),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(254),
      O => \write_buffer.wr_buf_in_data\(254)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(253),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(253),
      O => \write_buffer.wr_buf_in_data\(253)
    );
\write_buffer.wr_buffer_ram[42].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(252),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(252),
      O => \write_buffer.wr_buf_in_data\(252)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(263 downto 262),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(261 downto 260),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(259 downto 258),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(263 downto 262),
      DOB(1 downto 0) => wr_buf_out_data_w(261 downto 260),
      DOC(1 downto 0) => wr_buf_out_data_w(259 downto 258),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(263),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(263),
      O => \write_buffer.wr_buf_in_data\(263)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(262),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(262),
      O => \write_buffer.wr_buf_in_data\(262)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(261),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(261),
      O => \write_buffer.wr_buf_in_data\(261)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(260),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(260),
      O => \write_buffer.wr_buf_in_data\(260)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(259),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(259),
      O => \write_buffer.wr_buf_in_data\(259)
    );
\write_buffer.wr_buffer_ram[43].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(258),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(258),
      O => \write_buffer.wr_buf_in_data\(258)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(269 downto 268),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(267 downto 266),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(265 downto 264),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(269 downto 268),
      DOB(1 downto 0) => wr_buf_out_data_w(267 downto 266),
      DOC(1 downto 0) => wr_buf_out_data_w(265 downto 264),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(269),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(269),
      O => \write_buffer.wr_buf_in_data\(269)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(268),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(268),
      O => \write_buffer.wr_buf_in_data\(268)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(267),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(267),
      O => \write_buffer.wr_buf_in_data\(267)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(266),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(266),
      O => \write_buffer.wr_buf_in_data\(266)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(265),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(265),
      O => \write_buffer.wr_buf_in_data\(265)
    );
\write_buffer.wr_buffer_ram[44].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(264),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(264),
      O => \write_buffer.wr_buf_in_data\(264)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(275 downto 274),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(273 downto 272),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(271 downto 270),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(275 downto 274),
      DOB(1 downto 0) => wr_buf_out_data_w(273 downto 272),
      DOC(1 downto 0) => wr_buf_out_data_w(271 downto 270),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(275),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(275),
      O => \write_buffer.wr_buf_in_data\(275)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(274),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(274),
      O => \write_buffer.wr_buf_in_data\(274)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(273),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(273),
      O => \write_buffer.wr_buf_in_data\(273)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(272),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(272),
      O => \write_buffer.wr_buf_in_data\(272)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(271),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(271),
      O => \write_buffer.wr_buf_in_data\(271)
    );
\write_buffer.wr_buffer_ram[45].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(270),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(270),
      O => \write_buffer.wr_buf_in_data\(270)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(281 downto 280),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(279 downto 278),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(277 downto 276),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(281 downto 280),
      DOB(1 downto 0) => wr_buf_out_data_w(279 downto 278),
      DOC(1 downto 0) => wr_buf_out_data_w(277 downto 276),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(281),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(281),
      O => \write_buffer.wr_buf_in_data\(281)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(280),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(280),
      O => \write_buffer.wr_buf_in_data\(280)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(279),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(279),
      O => \write_buffer.wr_buf_in_data\(279)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(278),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(278),
      O => \write_buffer.wr_buf_in_data\(278)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(277),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(277),
      O => \write_buffer.wr_buf_in_data\(277)
    );
\write_buffer.wr_buffer_ram[46].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(276),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(276),
      O => \write_buffer.wr_buf_in_data\(276)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(287 downto 286),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(285 downto 284),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(283 downto 282),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(287 downto 286),
      DOB(1 downto 0) => wr_buf_out_data_w(285 downto 284),
      DOC(1 downto 0) => wr_buf_out_data_w(283 downto 282),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(287),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(287),
      O => \write_buffer.wr_buf_in_data\(287)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(286),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(286),
      O => \write_buffer.wr_buf_in_data\(286)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(285),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(285),
      O => \write_buffer.wr_buf_in_data\(285)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(284),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(284),
      O => \write_buffer.wr_buf_in_data\(284)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(283),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(283),
      O => \write_buffer.wr_buf_in_data\(283)
    );
\write_buffer.wr_buffer_ram[47].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(282),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(282),
      O => \write_buffer.wr_buf_in_data\(282)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(293 downto 292),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(291 downto 290),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(289 downto 288),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(293 downto 292),
      DOB(1 downto 0) => wr_buf_out_data_w(291 downto 290),
      DOC(1 downto 0) => wr_buf_out_data_w(289 downto 288),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(293),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(293),
      O => \write_buffer.wr_buf_in_data\(293)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(292),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(292),
      O => \write_buffer.wr_buf_in_data\(292)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(291),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(291),
      O => \write_buffer.wr_buf_in_data\(291)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(290),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(290),
      O => \write_buffer.wr_buf_in_data\(290)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(289),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(289),
      O => \write_buffer.wr_buf_in_data\(289)
    );
\write_buffer.wr_buffer_ram[48].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(288),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(288),
      O => \write_buffer.wr_buf_in_data\(288)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(299 downto 298),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(297 downto 296),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(295 downto 294),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(299 downto 298),
      DOB(1 downto 0) => wr_buf_out_data_w(297 downto 296),
      DOC(1 downto 0) => wr_buf_out_data_w(295 downto 294),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(299),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(299),
      O => \write_buffer.wr_buf_in_data\(299)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(298),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(298),
      O => \write_buffer.wr_buf_in_data\(298)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(297),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(297),
      O => \write_buffer.wr_buf_in_data\(297)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(296),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(296),
      O => \write_buffer.wr_buf_in_data\(296)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(295),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(295),
      O => \write_buffer.wr_buf_in_data\(295)
    );
\write_buffer.wr_buffer_ram[49].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(294),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(294),
      O => \write_buffer.wr_buf_in_data\(294)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(29 downto 28),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(27 downto 26),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(25 downto 24),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(29 downto 28),
      DOB(1 downto 0) => wr_buf_out_data_w(27 downto 26),
      DOC(1 downto 0) => wr_buf_out_data_w(25 downto 24),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(29),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(29),
      O => \write_buffer.wr_buf_in_data\(29)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(28),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(28),
      O => \write_buffer.wr_buf_in_data\(28)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(27),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(27),
      O => \write_buffer.wr_buf_in_data\(27)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(26),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(26),
      O => \write_buffer.wr_buf_in_data\(26)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(25),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(25),
      O => \write_buffer.wr_buf_in_data\(25)
    );
\write_buffer.wr_buffer_ram[4].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(24),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(24),
      O => \write_buffer.wr_buf_in_data\(24)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(305 downto 304),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(303 downto 302),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(301 downto 300),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(305 downto 304),
      DOB(1 downto 0) => wr_buf_out_data_w(303 downto 302),
      DOC(1 downto 0) => wr_buf_out_data_w(301 downto 300),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(305),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(305),
      O => \write_buffer.wr_buf_in_data\(305)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(304),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(304),
      O => \write_buffer.wr_buf_in_data\(304)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(303),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(303),
      O => \write_buffer.wr_buf_in_data\(303)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(302),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(302),
      O => \write_buffer.wr_buf_in_data\(302)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(301),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(301),
      O => \write_buffer.wr_buf_in_data\(301)
    );
\write_buffer.wr_buffer_ram[50].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(300),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(300),
      O => \write_buffer.wr_buf_in_data\(300)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(311 downto 310),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(309 downto 308),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(307 downto 306),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(311 downto 310),
      DOB(1 downto 0) => wr_buf_out_data_w(309 downto 308),
      DOC(1 downto 0) => wr_buf_out_data_w(307 downto 306),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(311),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(311),
      O => \write_buffer.wr_buf_in_data\(311)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(310),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(310),
      O => \write_buffer.wr_buf_in_data\(310)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(309),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(309),
      O => \write_buffer.wr_buf_in_data\(309)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(308),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(308),
      O => \write_buffer.wr_buf_in_data\(308)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(307),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(307),
      O => \write_buffer.wr_buf_in_data\(307)
    );
\write_buffer.wr_buffer_ram[51].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(306),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(306),
      O => \write_buffer.wr_buf_in_data\(306)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(317 downto 316),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(315 downto 314),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(313 downto 312),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(317 downto 316),
      DOB(1 downto 0) => wr_buf_out_data_w(315 downto 314),
      DOC(1 downto 0) => wr_buf_out_data_w(313 downto 312),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(317),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(317),
      O => \write_buffer.wr_buf_in_data\(317)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(316),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(316),
      O => \write_buffer.wr_buf_in_data\(316)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(315),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(315),
      O => \write_buffer.wr_buf_in_data\(315)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(314),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(314),
      O => \write_buffer.wr_buf_in_data\(314)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(313),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(313),
      O => \write_buffer.wr_buf_in_data\(313)
    );
\write_buffer.wr_buffer_ram[52].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(312),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(312),
      O => \write_buffer.wr_buf_in_data\(312)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(323 downto 322),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(321 downto 320),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(319 downto 318),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(323 downto 322),
      DOB(1 downto 0) => wr_buf_out_data_w(321 downto 320),
      DOC(1 downto 0) => wr_buf_out_data_w(319 downto 318),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(323),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(323),
      O => \write_buffer.wr_buf_in_data\(323)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(322),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(322),
      O => \write_buffer.wr_buf_in_data\(322)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(321),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(321),
      O => \write_buffer.wr_buf_in_data\(321)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(320),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(320),
      O => \write_buffer.wr_buf_in_data\(320)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(319),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(319),
      O => \write_buffer.wr_buf_in_data\(319)
    );
\write_buffer.wr_buffer_ram[53].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(318),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(318),
      O => \write_buffer.wr_buf_in_data\(318)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(329 downto 328),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(327 downto 326),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(325 downto 324),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(329 downto 328),
      DOB(1 downto 0) => wr_buf_out_data_w(327 downto 326),
      DOC(1 downto 0) => wr_buf_out_data_w(325 downto 324),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(329),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(329),
      O => \write_buffer.wr_buf_in_data\(329)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(328),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(328),
      O => \write_buffer.wr_buf_in_data\(328)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(327),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(327),
      O => \write_buffer.wr_buf_in_data\(327)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(326),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(326),
      O => \write_buffer.wr_buf_in_data\(326)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(325),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(325),
      O => \write_buffer.wr_buf_in_data\(325)
    );
\write_buffer.wr_buffer_ram[54].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(324),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(324),
      O => \write_buffer.wr_buf_in_data\(324)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(335 downto 334),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(333 downto 332),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(331 downto 330),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(335 downto 334),
      DOB(1 downto 0) => wr_buf_out_data_w(333 downto 332),
      DOC(1 downto 0) => wr_buf_out_data_w(331 downto 330),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(335),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(335),
      O => \write_buffer.wr_buf_in_data\(335)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(334),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(334),
      O => \write_buffer.wr_buf_in_data\(334)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(333),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(333),
      O => \write_buffer.wr_buf_in_data\(333)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(332),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(332),
      O => \write_buffer.wr_buf_in_data\(332)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(331),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(331),
      O => \write_buffer.wr_buf_in_data\(331)
    );
\write_buffer.wr_buffer_ram[55].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(330),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(330),
      O => \write_buffer.wr_buf_in_data\(330)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(341 downto 340),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(339 downto 338),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(337 downto 336),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(341 downto 340),
      DOB(1 downto 0) => wr_buf_out_data_w(339 downto 338),
      DOC(1 downto 0) => wr_buf_out_data_w(337 downto 336),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(341),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(341),
      O => \write_buffer.wr_buf_in_data\(341)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(340),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(340),
      O => \write_buffer.wr_buf_in_data\(340)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(339),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(339),
      O => \write_buffer.wr_buf_in_data\(339)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(338),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(338),
      O => \write_buffer.wr_buf_in_data\(338)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(337),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(337),
      O => \write_buffer.wr_buf_in_data\(337)
    );
\write_buffer.wr_buffer_ram[56].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(336),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(336),
      O => \write_buffer.wr_buf_in_data\(336)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(347 downto 346),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(345 downto 344),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(343 downto 342),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(347 downto 346),
      DOB(1 downto 0) => wr_buf_out_data_w(345 downto 344),
      DOC(1 downto 0) => wr_buf_out_data_w(343 downto 342),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(347),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(347),
      O => \write_buffer.wr_buf_in_data\(347)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(346),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(346),
      O => \write_buffer.wr_buf_in_data\(346)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(345),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(345),
      O => \write_buffer.wr_buf_in_data\(345)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(344),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(344),
      O => \write_buffer.wr_buf_in_data\(344)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(343),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(343),
      O => \write_buffer.wr_buf_in_data\(343)
    );
\write_buffer.wr_buffer_ram[57].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(342),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(342),
      O => \write_buffer.wr_buf_in_data\(342)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(353 downto 352),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(351 downto 350),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(349 downto 348),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(353 downto 352),
      DOB(1 downto 0) => wr_buf_out_data_w(351 downto 350),
      DOC(1 downto 0) => wr_buf_out_data_w(349 downto 348),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(353),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(353),
      O => \write_buffer.wr_buf_in_data\(353)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(352),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(352),
      O => \write_buffer.wr_buf_in_data\(352)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(351),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(351),
      O => \write_buffer.wr_buf_in_data\(351)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(350),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(350),
      O => \write_buffer.wr_buf_in_data\(350)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(349),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(349),
      O => \write_buffer.wr_buf_in_data\(349)
    );
\write_buffer.wr_buffer_ram[58].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(348),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(348),
      O => \write_buffer.wr_buf_in_data\(348)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(359 downto 358),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(357 downto 356),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(355 downto 354),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(359 downto 358),
      DOB(1 downto 0) => wr_buf_out_data_w(357 downto 356),
      DOC(1 downto 0) => wr_buf_out_data_w(355 downto 354),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(359),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(359),
      O => \write_buffer.wr_buf_in_data\(359)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(358),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(358),
      O => \write_buffer.wr_buf_in_data\(358)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(357),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(357),
      O => \write_buffer.wr_buf_in_data\(357)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(356),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(356),
      O => \write_buffer.wr_buf_in_data\(356)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(355),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(355),
      O => \write_buffer.wr_buf_in_data\(355)
    );
\write_buffer.wr_buffer_ram[59].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(354),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(354),
      O => \write_buffer.wr_buf_in_data\(354)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(35 downto 34),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(33 downto 32),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(31 downto 30),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(35 downto 34),
      DOB(1 downto 0) => wr_buf_out_data_w(33 downto 32),
      DOC(1 downto 0) => wr_buf_out_data_w(31 downto 30),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(35),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(35),
      O => \write_buffer.wr_buf_in_data\(35)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(34),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(34),
      O => \write_buffer.wr_buf_in_data\(34)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(33),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(33),
      O => \write_buffer.wr_buf_in_data\(33)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(32),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(32),
      O => \write_buffer.wr_buf_in_data\(32)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(31),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(31),
      O => \write_buffer.wr_buf_in_data\(31)
    );
\write_buffer.wr_buffer_ram[5].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(30),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(30),
      O => \write_buffer.wr_buf_in_data\(30)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(365 downto 364),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(363 downto 362),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(361 downto 360),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(365 downto 364),
      DOB(1 downto 0) => wr_buf_out_data_w(363 downto 362),
      DOC(1 downto 0) => wr_buf_out_data_w(361 downto 360),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(365),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(365),
      O => \write_buffer.wr_buf_in_data\(365)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(364),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(364),
      O => \write_buffer.wr_buf_in_data\(364)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(363),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(363),
      O => \write_buffer.wr_buf_in_data\(363)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(362),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(362),
      O => \write_buffer.wr_buf_in_data\(362)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(361),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(361),
      O => \write_buffer.wr_buf_in_data\(361)
    );
\write_buffer.wr_buffer_ram[60].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(360),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(360),
      O => \write_buffer.wr_buf_in_data\(360)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(371 downto 370),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(369 downto 368),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(367 downto 366),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(371 downto 370),
      DOB(1 downto 0) => wr_buf_out_data_w(369 downto 368),
      DOC(1 downto 0) => wr_buf_out_data_w(367 downto 366),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(371),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(371),
      O => \write_buffer.wr_buf_in_data\(371)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(370),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(370),
      O => \write_buffer.wr_buf_in_data\(370)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(369),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(369),
      O => \write_buffer.wr_buf_in_data\(369)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(368),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(368),
      O => \write_buffer.wr_buf_in_data\(368)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(367),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(367),
      O => \write_buffer.wr_buf_in_data\(367)
    );
\write_buffer.wr_buffer_ram[61].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(366),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(366),
      O => \write_buffer.wr_buf_in_data\(366)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(377 downto 376),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(375 downto 374),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(373 downto 372),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(377 downto 376),
      DOB(1 downto 0) => wr_buf_out_data_w(375 downto 374),
      DOC(1 downto 0) => wr_buf_out_data_w(373 downto 372),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(377),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(377),
      O => \write_buffer.wr_buf_in_data\(377)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(376),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(376),
      O => \write_buffer.wr_buf_in_data\(376)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(375),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(375),
      O => \write_buffer.wr_buf_in_data\(375)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(374),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(374),
      O => \write_buffer.wr_buf_in_data\(374)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(373),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(373),
      O => \write_buffer.wr_buf_in_data\(373)
    );
\write_buffer.wr_buffer_ram[62].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(372),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(372),
      O => \write_buffer.wr_buf_in_data\(372)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(383 downto 382),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(381 downto 380),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(379 downto 378),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(383 downto 382),
      DOB(1 downto 0) => wr_buf_out_data_w(381 downto 380),
      DOC(1 downto 0) => wr_buf_out_data_w(379 downto 378),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(383),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(383),
      O => \write_buffer.wr_buf_in_data\(383)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(382),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(382),
      O => \write_buffer.wr_buf_in_data\(382)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(381),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(381),
      O => \write_buffer.wr_buf_in_data\(381)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(380),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(380),
      O => \write_buffer.wr_buf_in_data\(380)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(379),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(379),
      O => \write_buffer.wr_buf_in_data\(379)
    );
\write_buffer.wr_buffer_ram[63].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(378),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(378),
      O => \write_buffer.wr_buf_in_data\(378)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(389 downto 388),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(387 downto 386),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(385 downto 384),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(389 downto 388),
      DOB(1 downto 0) => wr_buf_out_data_w(387 downto 386),
      DOC(1 downto 0) => wr_buf_out_data_w(385 downto 384),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(389),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(389),
      O => \write_buffer.wr_buf_in_data\(389)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(388),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(388),
      O => \write_buffer.wr_buf_in_data\(388)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(387),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(387),
      O => \write_buffer.wr_buf_in_data\(387)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(386),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(386),
      O => \write_buffer.wr_buf_in_data\(386)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(385),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(385),
      O => \write_buffer.wr_buf_in_data\(385)
    );
\write_buffer.wr_buffer_ram[64].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(384),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(384),
      O => \write_buffer.wr_buf_in_data\(384)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(395 downto 394),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(393 downto 392),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(391 downto 390),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(395 downto 394),
      DOB(1 downto 0) => wr_buf_out_data_w(393 downto 392),
      DOC(1 downto 0) => wr_buf_out_data_w(391 downto 390),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(395),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(395),
      O => \write_buffer.wr_buf_in_data\(395)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(394),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(394),
      O => \write_buffer.wr_buf_in_data\(394)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(393),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(393),
      O => \write_buffer.wr_buf_in_data\(393)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(392),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(392),
      O => \write_buffer.wr_buf_in_data\(392)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(391),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(391),
      O => \write_buffer.wr_buf_in_data\(391)
    );
\write_buffer.wr_buffer_ram[65].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(390),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(390),
      O => \write_buffer.wr_buf_in_data\(390)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(401 downto 400),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(399 downto 398),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(397 downto 396),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(401 downto 400),
      DOB(1 downto 0) => wr_buf_out_data_w(399 downto 398),
      DOC(1 downto 0) => wr_buf_out_data_w(397 downto 396),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(401),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(401),
      O => \write_buffer.wr_buf_in_data\(401)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(400),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(400),
      O => \write_buffer.wr_buf_in_data\(400)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(399),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(399),
      O => \write_buffer.wr_buf_in_data\(399)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(398),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(398),
      O => \write_buffer.wr_buf_in_data\(398)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(397),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(397),
      O => \write_buffer.wr_buf_in_data\(397)
    );
\write_buffer.wr_buffer_ram[66].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(396),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(396),
      O => \write_buffer.wr_buf_in_data\(396)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(407 downto 406),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(405 downto 404),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(403 downto 402),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(407 downto 406),
      DOB(1 downto 0) => wr_buf_out_data_w(405 downto 404),
      DOC(1 downto 0) => wr_buf_out_data_w(403 downto 402),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(407),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(407),
      O => \write_buffer.wr_buf_in_data\(407)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(406),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(406),
      O => \write_buffer.wr_buf_in_data\(406)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(405),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(405),
      O => \write_buffer.wr_buf_in_data\(405)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(404),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(404),
      O => \write_buffer.wr_buf_in_data\(404)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(403),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(403),
      O => \write_buffer.wr_buf_in_data\(403)
    );
\write_buffer.wr_buffer_ram[67].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(402),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(402),
      O => \write_buffer.wr_buf_in_data\(402)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(413 downto 412),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(411 downto 410),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(409 downto 408),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(413 downto 412),
      DOB(1 downto 0) => wr_buf_out_data_w(411 downto 410),
      DOC(1 downto 0) => wr_buf_out_data_w(409 downto 408),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(413),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(413),
      O => \write_buffer.wr_buf_in_data\(413)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(412),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(412),
      O => \write_buffer.wr_buf_in_data\(412)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(411),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(411),
      O => \write_buffer.wr_buf_in_data\(411)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(410),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(410),
      O => \write_buffer.wr_buf_in_data\(410)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(409),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(409),
      O => \write_buffer.wr_buf_in_data\(409)
    );
\write_buffer.wr_buffer_ram[68].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(408),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(408),
      O => \write_buffer.wr_buf_in_data\(408)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(419 downto 418),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(417 downto 416),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(415 downto 414),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(419 downto 418),
      DOB(1 downto 0) => wr_buf_out_data_w(417 downto 416),
      DOC(1 downto 0) => wr_buf_out_data_w(415 downto 414),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(419),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(419),
      O => \write_buffer.wr_buf_in_data\(419)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(418),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(418),
      O => \write_buffer.wr_buf_in_data\(418)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(417),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(417),
      O => \write_buffer.wr_buf_in_data\(417)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(416),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(416),
      O => \write_buffer.wr_buf_in_data\(416)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(415),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(415),
      O => \write_buffer.wr_buf_in_data\(415)
    );
\write_buffer.wr_buffer_ram[69].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(414),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(414),
      O => \write_buffer.wr_buf_in_data\(414)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(41 downto 40),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(39 downto 38),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(37 downto 36),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(41 downto 40),
      DOB(1 downto 0) => wr_buf_out_data_w(39 downto 38),
      DOC(1 downto 0) => wr_buf_out_data_w(37 downto 36),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(41),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(41),
      O => \write_buffer.wr_buf_in_data\(41)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(40),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(40),
      O => \write_buffer.wr_buf_in_data\(40)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(39),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(39),
      O => \write_buffer.wr_buf_in_data\(39)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(38),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(38),
      O => \write_buffer.wr_buf_in_data\(38)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(37),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(37),
      O => \write_buffer.wr_buf_in_data\(37)
    );
\write_buffer.wr_buffer_ram[6].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(36),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(36),
      O => \write_buffer.wr_buf_in_data\(36)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(425 downto 424),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(423 downto 422),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(421 downto 420),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(425 downto 424),
      DOB(1 downto 0) => wr_buf_out_data_w(423 downto 422),
      DOC(1 downto 0) => wr_buf_out_data_w(421 downto 420),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(425),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(425),
      O => \write_buffer.wr_buf_in_data\(425)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(424),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(424),
      O => \write_buffer.wr_buf_in_data\(424)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(423),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(423),
      O => \write_buffer.wr_buf_in_data\(423)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(422),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(422),
      O => \write_buffer.wr_buf_in_data\(422)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(421),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(421),
      O => \write_buffer.wr_buf_in_data\(421)
    );
\write_buffer.wr_buffer_ram[70].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(420),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(420),
      O => \write_buffer.wr_buf_in_data\(420)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(431 downto 430),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(429 downto 428),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(427 downto 426),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(431 downto 430),
      DOB(1 downto 0) => wr_buf_out_data_w(429 downto 428),
      DOC(1 downto 0) => wr_buf_out_data_w(427 downto 426),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(431),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(431),
      O => \write_buffer.wr_buf_in_data\(431)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(430),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(430),
      O => \write_buffer.wr_buf_in_data\(430)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(429),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(429),
      O => \write_buffer.wr_buf_in_data\(429)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(428),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(428),
      O => \write_buffer.wr_buf_in_data\(428)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(427),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(427),
      O => \write_buffer.wr_buf_in_data\(427)
    );
\write_buffer.wr_buffer_ram[71].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(426),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(426),
      O => \write_buffer.wr_buf_in_data\(426)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(437 downto 436),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(435 downto 434),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(433 downto 432),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(437 downto 436),
      DOB(1 downto 0) => wr_buf_out_data_w(435 downto 434),
      DOC(1 downto 0) => wr_buf_out_data_w(433 downto 432),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(437),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(437),
      O => \write_buffer.wr_buf_in_data\(437)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(436),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(436),
      O => \write_buffer.wr_buf_in_data\(436)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(435),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(435),
      O => \write_buffer.wr_buf_in_data\(435)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(434),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(434),
      O => \write_buffer.wr_buf_in_data\(434)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(433),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(433),
      O => \write_buffer.wr_buf_in_data\(433)
    );
\write_buffer.wr_buffer_ram[72].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(432),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(432),
      O => \write_buffer.wr_buf_in_data\(432)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(443 downto 442),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(441 downto 440),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(439 downto 438),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(443 downto 442),
      DOB(1 downto 0) => wr_buf_out_data_w(441 downto 440),
      DOC(1 downto 0) => wr_buf_out_data_w(439 downto 438),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(443),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(443),
      O => \write_buffer.wr_buf_in_data\(443)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(442),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(442),
      O => \write_buffer.wr_buf_in_data\(442)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(441),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(441),
      O => \write_buffer.wr_buf_in_data\(441)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(440),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(440),
      O => \write_buffer.wr_buf_in_data\(440)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(439),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(439),
      O => \write_buffer.wr_buf_in_data\(439)
    );
\write_buffer.wr_buffer_ram[73].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(438),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(438),
      O => \write_buffer.wr_buf_in_data\(438)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(449 downto 448),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(447 downto 446),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(445 downto 444),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(449 downto 448),
      DOB(1 downto 0) => wr_buf_out_data_w(447 downto 446),
      DOC(1 downto 0) => wr_buf_out_data_w(445 downto 444),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(449),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(449),
      O => \write_buffer.wr_buf_in_data\(449)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(448),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(448),
      O => \write_buffer.wr_buf_in_data\(448)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(447),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(447),
      O => \write_buffer.wr_buf_in_data\(447)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(446),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(446),
      O => \write_buffer.wr_buf_in_data\(446)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(445),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(445),
      O => \write_buffer.wr_buf_in_data\(445)
    );
\write_buffer.wr_buffer_ram[74].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(444),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(444),
      O => \write_buffer.wr_buf_in_data\(444)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(455 downto 454),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(453 downto 452),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(451 downto 450),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(455 downto 454),
      DOB(1 downto 0) => wr_buf_out_data_w(453 downto 452),
      DOC(1 downto 0) => wr_buf_out_data_w(451 downto 450),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(455),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(455),
      O => \write_buffer.wr_buf_in_data\(455)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(454),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(454),
      O => \write_buffer.wr_buf_in_data\(454)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(453),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(453),
      O => \write_buffer.wr_buf_in_data\(453)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(452),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(452),
      O => \write_buffer.wr_buf_in_data\(452)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(451),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(451),
      O => \write_buffer.wr_buf_in_data\(451)
    );
\write_buffer.wr_buffer_ram[75].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(450),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(450),
      O => \write_buffer.wr_buf_in_data\(450)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(461 downto 460),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(459 downto 458),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(457 downto 456),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(461 downto 460),
      DOB(1 downto 0) => wr_buf_out_data_w(459 downto 458),
      DOC(1 downto 0) => wr_buf_out_data_w(457 downto 456),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(461),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(461),
      O => \write_buffer.wr_buf_in_data\(461)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(460),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(460),
      O => \write_buffer.wr_buf_in_data\(460)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(459),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(459),
      O => \write_buffer.wr_buf_in_data\(459)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(458),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(458),
      O => \write_buffer.wr_buf_in_data\(458)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(457),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(457),
      O => \write_buffer.wr_buf_in_data\(457)
    );
\write_buffer.wr_buffer_ram[76].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(456),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(456),
      O => \write_buffer.wr_buf_in_data\(456)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(467 downto 466),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(465 downto 464),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(463 downto 462),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(467 downto 466),
      DOB(1 downto 0) => wr_buf_out_data_w(465 downto 464),
      DOC(1 downto 0) => wr_buf_out_data_w(463 downto 462),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(467),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(467),
      O => \write_buffer.wr_buf_in_data\(467)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(466),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(466),
      O => \write_buffer.wr_buf_in_data\(466)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(465),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(465),
      O => \write_buffer.wr_buf_in_data\(465)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(464),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(464),
      O => \write_buffer.wr_buf_in_data\(464)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(463),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(463),
      O => \write_buffer.wr_buf_in_data\(463)
    );
\write_buffer.wr_buffer_ram[77].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(462),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(462),
      O => \write_buffer.wr_buf_in_data\(462)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(473 downto 472),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(471 downto 470),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(469 downto 468),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(473 downto 472),
      DOB(1 downto 0) => wr_buf_out_data_w(471 downto 470),
      DOC(1 downto 0) => wr_buf_out_data_w(469 downto 468),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(473),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(473),
      O => \write_buffer.wr_buf_in_data\(473)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(472),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(472),
      O => \write_buffer.wr_buf_in_data\(472)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(471),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(471),
      O => \write_buffer.wr_buf_in_data\(471)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(470),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(470),
      O => \write_buffer.wr_buf_in_data\(470)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(469),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(469),
      O => \write_buffer.wr_buf_in_data\(469)
    );
\write_buffer.wr_buffer_ram[78].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(468),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(468),
      O => \write_buffer.wr_buf_in_data\(468)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(479 downto 478),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(477 downto 476),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(475 downto 474),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(479 downto 478),
      DOB(1 downto 0) => wr_buf_out_data_w(477 downto 476),
      DOC(1 downto 0) => wr_buf_out_data_w(475 downto 474),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(479),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(479),
      O => \write_buffer.wr_buf_in_data\(479)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(478),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(478),
      O => \write_buffer.wr_buf_in_data\(478)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(477),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(477),
      O => \write_buffer.wr_buf_in_data\(477)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(476),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(476),
      O => \write_buffer.wr_buf_in_data\(476)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(475),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(475),
      O => \write_buffer.wr_buf_in_data\(475)
    );
\write_buffer.wr_buffer_ram[79].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(474),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(474),
      O => \write_buffer.wr_buf_in_data\(474)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(47 downto 46),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(45 downto 44),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(43 downto 42),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(47 downto 46),
      DOB(1 downto 0) => wr_buf_out_data_w(45 downto 44),
      DOC(1 downto 0) => wr_buf_out_data_w(43 downto 42),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(47),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(47),
      O => \write_buffer.wr_buf_in_data\(47)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(46),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(46),
      O => \write_buffer.wr_buf_in_data\(46)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(45),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(45),
      O => \write_buffer.wr_buf_in_data\(45)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(44),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(44),
      O => \write_buffer.wr_buf_in_data\(44)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(43),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(43),
      O => \write_buffer.wr_buf_in_data\(43)
    );
\write_buffer.wr_buffer_ram[7].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(42),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(42),
      O => \write_buffer.wr_buf_in_data\(42)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(485 downto 484),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(483 downto 482),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(481 downto 480),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(485 downto 484),
      DOB(1 downto 0) => wr_buf_out_data_w(483 downto 482),
      DOC(1 downto 0) => wr_buf_out_data_w(481 downto 480),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(485),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(485),
      O => \write_buffer.wr_buf_in_data\(485)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(484),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(484),
      O => \write_buffer.wr_buf_in_data\(484)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(483),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(483),
      O => \write_buffer.wr_buf_in_data\(483)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(482),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(482),
      O => \write_buffer.wr_buf_in_data\(482)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(481),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(481),
      O => \write_buffer.wr_buf_in_data\(481)
    );
\write_buffer.wr_buffer_ram[80].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(480),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(480),
      O => \write_buffer.wr_buf_in_data\(480)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(491 downto 490),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(489 downto 488),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(487 downto 486),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(491 downto 490),
      DOB(1 downto 0) => wr_buf_out_data_w(489 downto 488),
      DOC(1 downto 0) => wr_buf_out_data_w(487 downto 486),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(491),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(491),
      O => \write_buffer.wr_buf_in_data\(491)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(490),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(490),
      O => \write_buffer.wr_buf_in_data\(490)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(489),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(489),
      O => \write_buffer.wr_buf_in_data\(489)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(488),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(488),
      O => \write_buffer.wr_buf_in_data\(488)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(487),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(487),
      O => \write_buffer.wr_buf_in_data\(487)
    );
\write_buffer.wr_buffer_ram[81].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(486),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(486),
      O => \write_buffer.wr_buf_in_data\(486)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(497 downto 496),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(495 downto 494),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(493 downto 492),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(497 downto 496),
      DOB(1 downto 0) => wr_buf_out_data_w(495 downto 494),
      DOC(1 downto 0) => wr_buf_out_data_w(493 downto 492),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(497),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(497),
      O => \write_buffer.wr_buf_in_data\(497)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(496),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(496),
      O => \write_buffer.wr_buf_in_data\(496)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(495),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(495),
      O => \write_buffer.wr_buf_in_data\(495)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(494),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(494),
      O => \write_buffer.wr_buf_in_data\(494)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(493),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(493),
      O => \write_buffer.wr_buf_in_data\(493)
    );
\write_buffer.wr_buffer_ram[82].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(492),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(492),
      O => \write_buffer.wr_buf_in_data\(492)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(503 downto 502),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(501 downto 500),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(499 downto 498),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(503 downto 502),
      DOB(1 downto 0) => wr_buf_out_data_w(501 downto 500),
      DOC(1 downto 0) => wr_buf_out_data_w(499 downto 498),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(503),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(503),
      O => \write_buffer.wr_buf_in_data\(503)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(502),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(502),
      O => \write_buffer.wr_buf_in_data\(502)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(501),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(501),
      O => \write_buffer.wr_buf_in_data\(501)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(500),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(500),
      O => \write_buffer.wr_buf_in_data\(500)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(499),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(499),
      O => \write_buffer.wr_buf_in_data\(499)
    );
\write_buffer.wr_buffer_ram[83].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(498),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(498),
      O => \write_buffer.wr_buf_in_data\(498)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(509 downto 508),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(507 downto 506),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(505 downto 504),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(509 downto 508),
      DOB(1 downto 0) => wr_buf_out_data_w(507 downto 506),
      DOC(1 downto 0) => wr_buf_out_data_w(505 downto 504),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(509),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(509),
      O => \write_buffer.wr_buf_in_data\(509)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(508),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(508),
      O => \write_buffer.wr_buf_in_data\(508)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(507),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(507),
      O => \write_buffer.wr_buf_in_data\(507)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(506),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(506),
      O => \write_buffer.wr_buf_in_data\(506)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(505),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(505),
      O => \write_buffer.wr_buf_in_data\(505)
    );
\write_buffer.wr_buffer_ram[84].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(504),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(504),
      O => \write_buffer.wr_buf_in_data\(504)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(515 downto 514),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(513 downto 512),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(511 downto 510),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(515 downto 514),
      DOB(1 downto 0) => wr_buf_out_data_w(513 downto 512),
      DOC(1 downto 0) => wr_buf_out_data_w(511 downto 510),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(3),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(3),
      O => \write_buffer.wr_buf_in_data\(515)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(2),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(2),
      O => \write_buffer.wr_buf_in_data\(514)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(1),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(1),
      O => \write_buffer.wr_buf_in_data\(513)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(0),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(0),
      O => \write_buffer.wr_buf_in_data\(512)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(511),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(511),
      O => \write_buffer.wr_buf_in_data\(511)
    );
\write_buffer.wr_buffer_ram[85].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(510),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(510),
      O => \write_buffer.wr_buf_in_data\(510)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(521 downto 520),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(519 downto 518),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(517 downto 516),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(521 downto 520),
      DOB(1 downto 0) => wr_buf_out_data_w(519 downto 518),
      DOC(1 downto 0) => wr_buf_out_data_w(517 downto 516),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(9),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(9),
      O => \write_buffer.wr_buf_in_data\(521)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(8),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(8),
      O => \write_buffer.wr_buf_in_data\(520)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(7),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(7),
      O => \write_buffer.wr_buf_in_data\(519)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(6),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(6),
      O => \write_buffer.wr_buf_in_data\(518)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(5),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(5),
      O => \write_buffer.wr_buf_in_data\(517)
    );
\write_buffer.wr_buffer_ram[86].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(4),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(4),
      O => \write_buffer.wr_buf_in_data\(516)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(527 downto 526),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(525 downto 524),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(523 downto 522),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(527 downto 526),
      DOB(1 downto 0) => wr_buf_out_data_w(525 downto 524),
      DOC(1 downto 0) => wr_buf_out_data_w(523 downto 522),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(15),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(15),
      O => \write_buffer.wr_buf_in_data\(527)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(14),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(14),
      O => \write_buffer.wr_buf_in_data\(526)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(13),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(13),
      O => \write_buffer.wr_buf_in_data\(525)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(12),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(12),
      O => \write_buffer.wr_buf_in_data\(524)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(11),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(11),
      O => \write_buffer.wr_buf_in_data\(523)
    );
\write_buffer.wr_buffer_ram[87].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(10),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(10),
      O => \write_buffer.wr_buf_in_data\(522)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(533 downto 532),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(531 downto 530),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(529 downto 528),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(533 downto 532),
      DOB(1 downto 0) => wr_buf_out_data_w(531 downto 530),
      DOC(1 downto 0) => wr_buf_out_data_w(529 downto 528),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(21),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(21),
      O => \write_buffer.wr_buf_in_data\(533)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(20),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(20),
      O => \write_buffer.wr_buf_in_data\(532)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(19),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(19),
      O => \write_buffer.wr_buf_in_data\(531)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(18),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(18),
      O => \write_buffer.wr_buf_in_data\(530)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(17),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(17),
      O => \write_buffer.wr_buf_in_data\(529)
    );
\write_buffer.wr_buffer_ram[88].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(16),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(16),
      O => \write_buffer.wr_buf_in_data\(528)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(539 downto 538),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(537 downto 536),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(535 downto 534),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(539 downto 538),
      DOB(1 downto 0) => wr_buf_out_data_w(537 downto 536),
      DOC(1 downto 0) => wr_buf_out_data_w(535 downto 534),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(27),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(27),
      O => \write_buffer.wr_buf_in_data\(539)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(26),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(26),
      O => \write_buffer.wr_buf_in_data\(538)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(25),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(25),
      O => \write_buffer.wr_buf_in_data\(537)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(24),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(24),
      O => \write_buffer.wr_buf_in_data\(536)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(23),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(23),
      O => \write_buffer.wr_buf_in_data\(535)
    );
\write_buffer.wr_buffer_ram[89].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(22),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(22),
      O => \write_buffer.wr_buf_in_data\(534)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(53 downto 52),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(51 downto 50),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(49 downto 48),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(53 downto 52),
      DOB(1 downto 0) => wr_buf_out_data_w(51 downto 50),
      DOC(1 downto 0) => wr_buf_out_data_w(49 downto 48),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(53),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(53),
      O => \write_buffer.wr_buf_in_data\(53)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(52),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(52),
      O => \write_buffer.wr_buf_in_data\(52)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(51),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(51),
      O => \write_buffer.wr_buf_in_data\(51)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(50),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(50),
      O => \write_buffer.wr_buf_in_data\(50)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(49),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(49),
      O => \write_buffer.wr_buf_in_data\(49)
    );
\write_buffer.wr_buffer_ram[8].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(48),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(48),
      O => \write_buffer.wr_buf_in_data\(48)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(545 downto 544),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(543 downto 542),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(541 downto 540),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(545 downto 544),
      DOB(1 downto 0) => wr_buf_out_data_w(543 downto 542),
      DOC(1 downto 0) => wr_buf_out_data_w(541 downto 540),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(33),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(33),
      O => \write_buffer.wr_buf_in_data\(545)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(32),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(32),
      O => \write_buffer.wr_buf_in_data\(544)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(31),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(31),
      O => \write_buffer.wr_buf_in_data\(543)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(30),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(30),
      O => \write_buffer.wr_buf_in_data\(542)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(29),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(29),
      O => \write_buffer.wr_buf_in_data\(541)
    );
\write_buffer.wr_buffer_ram[90].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(28),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(28),
      O => \write_buffer.wr_buf_in_data\(540)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(551 downto 550),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(549 downto 548),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(547 downto 546),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(551 downto 550),
      DOB(1 downto 0) => wr_buf_out_data_w(549 downto 548),
      DOC(1 downto 0) => wr_buf_out_data_w(547 downto 546),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(39),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(39),
      O => \write_buffer.wr_buf_in_data\(551)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(38),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(38),
      O => \write_buffer.wr_buf_in_data\(550)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(37),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(37),
      O => \write_buffer.wr_buf_in_data\(549)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(36),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(36),
      O => \write_buffer.wr_buf_in_data\(548)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(35),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(35),
      O => \write_buffer.wr_buf_in_data\(547)
    );
\write_buffer.wr_buffer_ram[91].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(34),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(34),
      O => \write_buffer.wr_buf_in_data\(546)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(557 downto 556),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(555 downto 554),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(553 downto 552),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(557 downto 556),
      DOB(1 downto 0) => wr_buf_out_data_w(555 downto 554),
      DOC(1 downto 0) => wr_buf_out_data_w(553 downto 552),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(45),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(45),
      O => \write_buffer.wr_buf_in_data\(557)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(44),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(44),
      O => \write_buffer.wr_buf_in_data\(556)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(43),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(43),
      O => \write_buffer.wr_buf_in_data\(555)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(42),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(42),
      O => \write_buffer.wr_buf_in_data\(554)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(41),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(41),
      O => \write_buffer.wr_buf_in_data\(553)
    );
\write_buffer.wr_buffer_ram[92].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(40),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(40),
      O => \write_buffer.wr_buf_in_data\(552)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(563 downto 562),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(561 downto 560),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(559 downto 558),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(563 downto 562),
      DOB(1 downto 0) => wr_buf_out_data_w(561 downto 560),
      DOC(1 downto 0) => wr_buf_out_data_w(559 downto 558),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(51),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(51),
      O => \write_buffer.wr_buf_in_data\(563)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(50),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(50),
      O => \write_buffer.wr_buf_in_data\(562)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(49),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(49),
      O => \write_buffer.wr_buf_in_data\(561)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(48),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(48),
      O => \write_buffer.wr_buf_in_data\(560)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(47),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(47),
      O => \write_buffer.wr_buf_in_data\(559)
    );
\write_buffer.wr_buffer_ram[93].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(46),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(46),
      O => \write_buffer.wr_buf_in_data\(558)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(569 downto 568),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(567 downto 566),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(565 downto 564),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(569 downto 568),
      DOB(1 downto 0) => wr_buf_out_data_w(567 downto 566),
      DOC(1 downto 0) => wr_buf_out_data_w(565 downto 564),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(57),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(57),
      O => \write_buffer.wr_buf_in_data\(569)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(56),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(56),
      O => \write_buffer.wr_buf_in_data\(568)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(55),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(55),
      O => \write_buffer.wr_buf_in_data\(567)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(54),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(54),
      O => \write_buffer.wr_buf_in_data\(566)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(53),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(53),
      O => \write_buffer.wr_buf_in_data\(565)
    );
\write_buffer.wr_buffer_ram[94].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(52),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(52),
      O => \write_buffer.wr_buf_in_data\(564)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(575 downto 574),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(573 downto 572),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(571 downto 570),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(575 downto 574),
      DOB(1 downto 0) => wr_buf_out_data_w(573 downto 572),
      DOC(1 downto 0) => wr_buf_out_data_w(571 downto 570),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(63),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(63),
      O => \write_buffer.wr_buf_in_data\(575)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(62),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(62),
      O => \write_buffer.wr_buf_in_data\(574)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(61),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(61),
      O => \write_buffer.wr_buf_in_data\(573)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(60),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(60),
      O => \write_buffer.wr_buf_in_data\(572)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(59),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(59),
      O => \write_buffer.wr_buf_in_data\(571)
    );
\write_buffer.wr_buffer_ram[95].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_mask(58),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_mask_r1(58),
      O => \write_buffer.wr_buf_in_data\(570)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRA(0) => '0',
      ADDRB(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRB(0) => '0',
      ADDRC(4 downto 1) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      ADDRC(0) => '0',
      ADDRD(4 downto 1) => wb_wr_data_addr_w(4 downto 1),
      ADDRD(0) => \write_data_control.wb_wr_data_addr0_ns\,
      DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(59 downto 58),
      DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(57 downto 56),
      DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(55 downto 54),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wr_buf_out_data_w(59 downto 58),
      DOB(1 downto 0) => wr_buf_out_data_w(57 downto 56),
      DOC(1 downto 0) => wr_buf_out_data_w(55 downto 54),
      DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\(1 downto 0),
      WCLK => CLK,
      WE => wdf_rdy_ns
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(59),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(59),
      O => \write_buffer.wr_buf_in_data\(59)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(58),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(58),
      O => \write_buffer.wr_buf_in_data\(58)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(57),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(57),
      O => \write_buffer.wr_buf_in_data\(57)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(56),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(56),
      O => \write_buffer.wr_buf_in_data\(56)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(55),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(55),
      O => \write_buffer.wr_buf_in_data\(55)
    );
\write_buffer.wr_buffer_ram[9].RAM32M0_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => app_wdf_data(54),
      I1 => app_wdf_rdy_r_copy2,
      I2 => app_wdf_data_r1(54),
      O => \write_buffer.wr_buf_in_data\(54)
    );
\write_data_control.wb_wr_data_addr0_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \write_data_control.wb_wr_data_addr0_ns\,
      Q => \write_data_control.wb_wr_data_addr0_r\,
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(1),
      Q => \write_data_control.wb_wr_data_addr_r\(1),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(2),
      Q => \write_data_control.wb_wr_data_addr_r\(2),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(3),
      Q => \write_data_control.wb_wr_data_addr_r\(3),
      R => '0'
    );
\write_data_control.wb_wr_data_addr_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => wb_wr_data_addr_w(4),
      Q => \write_data_control.wb_wr_data_addr_r\(4),
      R => '0'
    );
\write_data_control.wr_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\write_data_control.wr_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg__0\(0),
      I1 => \write_data_control.wr_data_indx_r_reg__0\(1),
      O => \p_0_in__0__0\(1)
    );
\write_data_control.wr_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg__0\(0),
      I1 => \write_data_control.wr_data_indx_r_reg__0\(1),
      I2 => \write_data_control.wr_data_indx_r_reg__0\(2),
      O => \p_0_in__0__0\(2)
    );
\write_data_control.wr_data_indx_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C000AAAA"
    )
        port map (
      I0 => \^p_0_in\(0),
      I1 => wdf_rdy_ns,
      I2 => app_wdf_wren_r1,
      I3 => app_wdf_end_r1,
      I4 => app_wdf_rdy_r_copy1,
      O => \write_data_control.wr_data_addr_le\
    );
\write_data_control.wr_data_indx_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \write_data_control.wr_data_indx_r_reg__0\(1),
      I1 => \write_data_control.wr_data_indx_r_reg__0\(0),
      I2 => \write_data_control.wr_data_indx_r_reg__0\(2),
      I3 => \write_data_control.wr_data_indx_r_reg__0\(3),
      O => \p_0_in__0__0\(3)
    );
\write_data_control.wr_data_indx_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(0),
      Q => \write_data_control.wr_data_indx_r_reg__0\(0),
      S => reset_reg
    );
\write_data_control.wr_data_indx_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(1),
      Q => \write_data_control.wr_data_indx_r_reg__0\(1),
      R => reset_reg
    );
\write_data_control.wr_data_indx_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(2),
      Q => \write_data_control.wr_data_indx_r_reg__0\(2),
      R => reset_reg
    );
\write_data_control.wr_data_indx_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \write_data_control.wr_data_addr_le\,
      D => \p_0_in__0__0\(3),
      Q => \write_data_control.wr_data_indx_r_reg__0\(3),
      R => reset_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_arb_row_col is
  port (
    \last_master_r_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_cmd_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_ras_n_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[2]\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.int_read_this_rank\ : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]\ : out STD_LOGIC;
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \last_master_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 28 downto 0 );
    \cmd_pipe_plus.mc_address_reg[11]\ : out STD_LOGIC;
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\ : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]_0\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_1 : out STD_LOGIC;
    override_demand_ns : out STD_LOGIC;
    \last_master_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \last_master_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address_reg[28]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[2]\ : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_2\ : out STD_LOGIC;
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : out STD_LOGIC;
    \last_master_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 );
    act_this_rank : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    demand_priority_r_reg_2 : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[8]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[7]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[6]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[40]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[39]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[36]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[35]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[34]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[32]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[30]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[29]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[28]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_3\ : out STD_LOGIC;
    granted_row_ns : in STD_LOGIC;
    CLK : in STD_LOGIC;
    granted_col_ns : in STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    rnk_config_valid_r_lcl_reg_2 : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rd_wr_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_aux_out0_reg[1]\ : in STD_LOGIC;
    col_rd_wr_r : in STD_LOGIC;
    \col_mux.col_periodic_rd_r\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_5 : in STD_LOGIC;
    rd_wr_r_lcl_reg_6 : in STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    granted_row_r_reg_0 : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    granted_row_r_reg_1 : in STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 30 downto 0 );
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    maint_sre_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    req_bank_rdy_ns_0 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    req_bank_rdy_ns_1 : in STD_LOGIC;
    demand_priority_r_reg_5 : in STD_LOGIC;
    demand_priority_r_reg_6 : in STD_LOGIC;
    req_bank_rdy_ns_2 : in STD_LOGIC;
    \last_master_r_reg[3]_1\ : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    head_r_lcl_reg : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ofs_rdy_r : in STD_LOGIC;
    ofs_rdy_r_3 : in STD_LOGIC;
    ofs_rdy_r_4 : in STD_LOGIC;
    ofs_rdy_r_5 : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \col_mux.col_data_buf_addr_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    auto_pre_r : in STD_LOGIC;
    auto_pre_r_6 : in STD_LOGIC;
    auto_pre_r_7 : in STD_LOGIC;
    auto_pre_r_8 : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_bank_rdy_r : in STD_LOGIC;
    req_bank_rdy_r_9 : in STD_LOGIC;
    req_bank_rdy_r_10 : in STD_LOGIC;
    req_bank_rdy_r_11 : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_arb_row_col : entity is "mig_7series_v2_3_arb_row_col";
end mig_7series_0_mig_7series_v2_3_arb_row_col;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_arb_row_col is
  signal \^cmd_pipe_plus.mc_cas_n_reg[2]\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_cmd_reg[0]\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_ras_n_reg[0]\ : STD_LOGIC;
  signal \genblk3[1].rnk_config_strobe_r_reg\ : STD_LOGIC;
  signal \genblk3[2].rnk_config_strobe_r_reg\ : STD_LOGIC;
  signal \^last_master_r_reg[1]\ : STD_LOGIC;
  signal \^override_demand_ns\ : STD_LOGIC;
  signal rnk_config_strobe : STD_LOGIC;
  signal rnk_config_strobe_ns : STD_LOGIC;
  signal \rnk_config_strobe_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \^rnk_config_strobe_r_reg[0]_0\ : STD_LOGIC;
  signal \^rnk_config_valid_r_lcl_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cs_n[0]_i_1\ : label is "soft_lutpair972";
  attribute SOFT_HLUTNM of override_demand_r_i_1 : label is "soft_lutpair971";
  attribute SOFT_HLUTNM of \rnk_config_strobe_r[0]_i_3\ : label is "soft_lutpair971";
  attribute SOFT_HLUTNM of \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1\ : label is "soft_lutpair972";
begin
  \cmd_pipe_plus.mc_cas_n_reg[2]\ <= \^cmd_pipe_plus.mc_cas_n_reg[2]\;
  \cmd_pipe_plus.mc_cmd_reg[0]\ <= \^cmd_pipe_plus.mc_cmd_reg[0]\;
  \cmd_pipe_plus.mc_ras_n_reg[0]\ <= \^cmd_pipe_plus.mc_ras_n_reg[0]\;
  \last_master_r_reg[1]\ <= \^last_master_r_reg[1]\;
  override_demand_ns <= \^override_demand_ns\;
  \rnk_config_strobe_r_reg[0]_0\ <= \^rnk_config_strobe_r_reg[0]_0\;
  rnk_config_valid_r_lcl_reg_0 <= \^rnk_config_valid_r_lcl_reg_0\;
\cmd_pipe_plus.mc_address[40]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_cas_n_reg[2]\,
      O => mc_ras_n_ns(1)
    );
\cmd_pipe_plus.mc_cas_n[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      O => mc_cas_n_ns(1)
    );
\cmd_pipe_plus.mc_cs_n[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_ras_n_reg[0]\,
      I1 => \^last_master_r_reg[1]\,
      O => mc_cs_n_ns(0)
    );
col_arb0: entity work.\mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1\
     port map (
      CLK => CLK,
      D(1 downto 0) => D(1 downto 0),
      DIC(0) => DIC(0),
      E(0) => E(0),
      Q(3 downto 0) => Q(3 downto 0),
      auto_pre_r => auto_pre_r,
      auto_pre_r_6 => auto_pre_r_6,
      auto_pre_r_7 => auto_pre_r_7,
      auto_pre_r_8 => auto_pre_r_8,
      \cmd_pipe_plus.mc_address_reg[24]\(10 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(24 downto 14),
      \cmd_pipe_plus.mc_aux_out0_reg[1]\ => \cmd_pipe_plus.mc_aux_out0_reg[1]\,
      \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(5 downto 3),
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[1]\ => \cmd_pipe_plus.mc_we_n_reg[1]\,
      col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0),
      \col_mux.col_data_buf_addr_r\(0) => \col_mux.col_data_buf_addr_r\(0),
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      col_rd_wr => col_rd_wr,
      col_rd_wr_r => col_rd_wr_r,
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      demand_priority_r_reg => demand_priority_r_reg,
      demand_priority_r_reg_0 => demand_priority_r_reg_0,
      demand_priority_r_reg_1 => demand_priority_r_reg_1,
      demand_priority_r_reg_2 => demand_priority_r_reg_2,
      \genblk3[1].rnk_config_strobe_r_reg\ => \genblk3[1].rnk_config_strobe_r_reg\,
      \genblk3[2].rnk_config_strobe_r_reg\ => \genblk3[2].rnk_config_strobe_r_reg\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]_0\,
      \grant_r_reg[1]_1\ => \grant_r_reg[1]_1\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_2\,
      \grant_r_reg[3]_2\ => \grant_r_reg[3]_3\,
      granted_col_r_reg => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      \last_master_r_reg[1]_0\(0) => \last_master_r_reg[1]_0\(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r_3 => ofs_rdy_r_3,
      ofs_rdy_r_4 => ofs_rdy_r_4,
      ofs_rdy_r_5 => ofs_rdy_r_5,
      \periodic_rd_generation.int_read_this_rank\ => \periodic_rd_generation.int_read_this_rank\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(1 downto 0) => rd_wr_r(1 downto 0),
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_2,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_3,
      rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg_4,
      rd_wr_r_lcl_reg_5 => rd_wr_r_lcl_reg_5,
      rd_wr_r_lcl_reg_6 => rd_wr_r_lcl_reg_6,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \req_bank_r_lcl_reg[2]_2\(2 downto 0),
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_10 => req_bank_rdy_r_10,
      req_bank_rdy_r_11 => req_bank_rdy_r_11,
      req_bank_rdy_r_9 => req_bank_rdy_r_9,
      \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_1\(9 downto 0),
      \req_col_r_reg[9]_2\(9 downto 0) => \req_col_r_reg[9]_2\(9 downto 0),
      req_data_buf_addr_r(19 downto 0) => req_data_buf_addr_r(19 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      rnk_config_strobe => rnk_config_strobe,
      rnk_config_valid_r_lcl_reg => \^rnk_config_valid_r_lcl_reg_0\,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]\ => \wtr_timer.wtr_cnt_r_reg[0]\,
      \wtr_timer.wtr_cnt_r_reg[0]_0\ => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      \wtr_timer.wtr_cnt_r_reg[1]\(0) => \wtr_timer.wtr_cnt_r_reg[1]\(0)
    );
\genblk3[1].rnk_config_strobe_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rnk_config_strobe,
      Q => \genblk3[1].rnk_config_strobe_r_reg\,
      R => '0'
    );
\genblk3[2].rnk_config_strobe_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \genblk3[1].rnk_config_strobe_r_reg\,
      Q => \genblk3[2].rnk_config_strobe_r_reg\,
      R => '0'
    );
granted_col_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => granted_col_ns,
      Q => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      R => '0'
    );
granted_row_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => granted_row_ns,
      Q => \^last_master_r_reg[1]\,
      R => '0'
    );
\i___60_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0FFF7FFF7FFF7"
    )
        port map (
      I0 => req_bank_rdy_ns_1,
      I1 => demand_priority_r_reg_5,
      I2 => \^rnk_config_valid_r_lcl_reg_0\,
      I3 => \^override_demand_ns\,
      I4 => demand_priority_r_reg_6,
      I5 => req_bank_rdy_ns_2,
      O => \^rnk_config_strobe_r_reg[0]_0\
    );
\i___60_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000F800000088"
    )
        port map (
      I0 => demand_priority_r_reg_4,
      I1 => req_bank_rdy_ns_0,
      I2 => req_bank_rdy_ns,
      I3 => \^rnk_config_valid_r_lcl_reg_0\,
      I4 => \^override_demand_ns\,
      I5 => demand_priority_r_reg_3,
      O => rnk_config_valid_r_lcl_reg_1
    );
insert_maint_r1_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \generate_maint_cmds.insert_maint_r_lcl_reg\,
      Q => \^cmd_pipe_plus.mc_ras_n_reg[0]\,
      R => '0'
    );
override_demand_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \genblk3[1].rnk_config_strobe_r_reg\,
      I1 => \genblk3[2].rnk_config_strobe_r_reg\,
      I2 => rnk_config_strobe,
      O => \^override_demand_ns\
    );
\pre_4_1_1T_arb.granted_pre_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \pre_4_1_1T_arb.granted_pre_ns\,
      Q => \^cmd_pipe_plus.mc_cas_n_reg[2]\,
      R => '0'
    );
\pre_4_1_1T_arb.pre_arb0\: entity work.\mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_3\
     port map (
      CLK => CLK,
      D(0) => \last_master_r_reg[0]\(0),
      Q(3 downto 0) => \cmd_pipe_plus.mc_address_reg[28]\(3 downto 0),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_2,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_3,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg,
      auto_pre_r_lcl_reg_0 => auto_pre_r_lcl_reg_0,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_1,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_2,
      \cmd_pipe_plus.mc_address_reg[28]\ => \cmd_pipe_plus.mc_address_reg[28]_0\,
      \cmd_pipe_plus.mc_address_reg[29]\ => \cmd_pipe_plus.mc_address_reg[29]\,
      \cmd_pipe_plus.mc_address_reg[30]\ => \cmd_pipe_plus.mc_address_reg[30]\,
      \cmd_pipe_plus.mc_address_reg[32]\ => \cmd_pipe_plus.mc_address_reg[32]\,
      \cmd_pipe_plus.mc_address_reg[34]\ => \cmd_pipe_plus.mc_address_reg[34]\,
      \cmd_pipe_plus.mc_address_reg[35]\ => \cmd_pipe_plus.mc_address_reg[35]\,
      \cmd_pipe_plus.mc_address_reg[36]\ => \cmd_pipe_plus.mc_address_reg[36]\,
      \cmd_pipe_plus.mc_address_reg[39]\ => \cmd_pipe_plus.mc_address_reg[39]\,
      \cmd_pipe_plus.mc_address_reg[40]\ => \cmd_pipe_plus.mc_address_reg[40]\,
      \cmd_pipe_plus.mc_address_reg[41]\(3 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(28 downto 25),
      \cmd_pipe_plus.mc_bank_reg[6]\ => \cmd_pipe_plus.mc_bank_reg[6]\,
      \cmd_pipe_plus.mc_bank_reg[7]\ => \cmd_pipe_plus.mc_bank_reg[7]\,
      \cmd_pipe_plus.mc_bank_reg[8]\ => \cmd_pipe_plus.mc_bank_reg[8]\,
      \cmd_pipe_plus.mc_we_n_reg[2]\(0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1),
      \last_master_r_reg[3]_0\(0) => \last_master_r_reg[3]_0\(0),
      \last_master_r_reg[3]_1\ => \last_master_r_reg[3]_1\,
      mc_cas_n_ns(0) => mc_cas_n_ns(2),
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \^cmd_pipe_plus.mc_cas_n_reg[2]\,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      req_row_r(29 downto 18) => req_row_r(30 downto 19),
      req_row_r(17 downto 0) => req_row_r(17 downto 0),
      \req_row_r_lcl_reg[13]\(12 downto 10) => \req_row_r_lcl_reg[13]\(13 downto 11),
      \req_row_r_lcl_reg[13]\(9 downto 0) => \req_row_r_lcl_reg[13]\(9 downto 0),
      \req_row_r_lcl_reg[13]_0\(8 downto 0) => \req_row_r_lcl_reg[13]_0\(8 downto 0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\
    );
\rnk_config_strobe_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33202020FFFFFFFF"
    )
        port map (
      I0 => demand_priority_r_reg_3,
      I1 => \rnk_config_strobe_r[0]_i_3_n_0\,
      I2 => req_bank_rdy_ns,
      I3 => req_bank_rdy_ns_0,
      I4 => demand_priority_r_reg_4,
      I5 => \^rnk_config_strobe_r_reg[0]_0\,
      O => rnk_config_strobe_ns
    );
\rnk_config_strobe_r[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rnk_config_strobe,
      I1 => \genblk3[2].rnk_config_strobe_r_reg\,
      I2 => \genblk3[1].rnk_config_strobe_r_reg\,
      I3 => \^rnk_config_valid_r_lcl_reg_0\,
      O => \rnk_config_strobe_r[0]_i_3_n_0\
    );
\rnk_config_strobe_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rnk_config_strobe_ns,
      Q => rnk_config_strobe,
      R => '0'
    );
rnk_config_valid_r_lcl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rnk_config_valid_r_lcl_reg_2,
      Q => \^rnk_config_valid_r_lcl_reg_0\,
      R => SR(0)
    );
row_arb0: entity work.\mig_7series_0_mig_7series_v2_3_round_robin_arb__parameterized1_4\
     port map (
      CLK => CLK,
      Q(3 downto 0) => \last_master_r_reg[3]\(3 downto 0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_2,
      act_wait_r_lcl_reg_3 => act_wait_r_lcl_reg_3,
      act_wait_r_lcl_reg_4 => act_wait_r_lcl_reg_4,
      \cmd_pipe_plus.mc_address_reg[11]\ => \cmd_pipe_plus.mc_address_reg[11]\,
      \cmd_pipe_plus.mc_address_reg[13]\(13 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(13 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[0]\(0) => \cmd_pipe_plus.mc_we_n_reg[2]\(0),
      \generate_maint_cmds.insert_maint_r_lcl_reg\ => \generate_maint_cmds.insert_maint_r_lcl_reg\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_0\,
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_1\,
      granted_row_r_reg => granted_row_r_reg_0,
      granted_row_r_reg_0 => \^last_master_r_reg[1]\,
      granted_row_r_reg_1 => granted_row_r_reg_1,
      head_r_lcl_reg => head_r_lcl_reg,
      inhbt_act_faw_r => inhbt_act_faw_r,
      insert_maint_r1_lcl_reg => \^cmd_pipe_plus.mc_ras_n_reg[0]\,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(0) => mc_cas_n_ns(0),
      mc_ras_n_ns(0) => mc_ras_n_ns(0),
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_2\(2 downto 0),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      req_row_r(30 downto 0) => req_row_r(30 downto 0),
      \req_row_r_lcl_reg[13]\(13 downto 0) => \req_row_r_lcl_reg[13]\(13 downto 0),
      \req_row_r_lcl_reg[13]_0\(8 downto 0) => \req_row_r_lcl_reg[13]_0\(8 downto 0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      wait_for_maint_r_lcl_reg => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_0,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_1,
      wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_2
    );
\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_ras_n_reg[0]\,
      I1 => maint_sre_r,
      O => \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_cntrl is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC;
    ordered_r_lcl_reg : out STD_LOGIC;
    q_has_priority_r_reg : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    \act_this_rank_r_reg[0]\ : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    wait_for_maint_r_lcl_reg : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    accept_internal_r_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_ns : out STD_LOGIC;
    granted_col_r_reg : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    \q_entry_r_reg[1]_2\ : out STD_LOGIC;
    q_entry_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_7_in : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    head_r_lcl_reg_1 : out STD_LOGIC;
    head_r_lcl_reg_2 : out STD_LOGIC;
    head_r_lcl_reg_3 : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    act_wait_r_lcl_reg_2 : out STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    head_r_lcl_reg_4 : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ofs_rdy_r0 : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    head_r_lcl_reg_5 : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \q_entry_r_reg[0]_1\ : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    override_demand_r_reg : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    \q_entry_r_reg[1]_3\ : in STD_LOGIC;
    \q_entry_r_reg[1]_4\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    idle_r_lcl_reg_3 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_2 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg_0 : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    accept_r_reg : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    req_wr_r_lcl_reg_1 : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    rd_wr_r_lcl_reg_5 : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    idle_r_lcl_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_5 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : in STD_LOGIC;
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \grant_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    demanded_prior_r_reg_0 : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_bank_rdy_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg_7 : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ordered_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_cntrl : entity is "mig_7series_v2_3_bank_cntrl";
end mig_7series_0_mig_7series_v2_3_bank_cntrl;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_cntrl is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^accept_internal_r_reg\ : STD_LOGIC;
  signal \^act_this_rank_r_reg[0]\ : STD_LOGIC;
  signal act_wait_ns : STD_LOGIC;
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^auto_pre_r\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_13 : STD_LOGIC;
  signal bank_compare0_n_28 : STD_LOGIC;
  signal bank_compare0_n_6 : STD_LOGIC;
  signal bank_queue0_n_22 : STD_LOGIC;
  signal bank_queue0_n_39 : STD_LOGIC;
  signal bank_queue0_n_40 : STD_LOGIC;
  signal bank_state0_n_15 : STD_LOGIC;
  signal bank_state0_n_20 : STD_LOGIC;
  signal \^head_r_lcl_reg_1\ : STD_LOGIC;
  signal \^head_r_lcl_reg_3\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^ordered_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal p_130_out : STD_LOGIC;
  signal p_145_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal \^pre_bm_end_r\ : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_priority_r_reg\ : STD_LOGIC;
  signal \^q_has_rd\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[0]_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^ras_timer_zero_r_reg\ : STD_LOGIC;
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC;
  signal \^req_bank_rdy_ns\ : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]\ : STD_LOGIC;
  signal \^tail_r\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  accept_internal_r_reg <= \^accept_internal_r_reg\;
  \act_this_rank_r_reg[0]\ <= \^act_this_rank_r_reg[0]\;
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r <= \^auto_pre_r\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  head_r_lcl_reg_1 <= \^head_r_lcl_reg_1\;
  head_r_lcl_reg_3 <= \^head_r_lcl_reg_3\;
  ordered_r(0) <= \^ordered_r\(0);
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  pre_bm_end_r <= \^pre_bm_end_r\;
  q_has_priority_r_reg <= \^q_has_priority_r_reg\;
  q_has_rd <= \^q_has_rd\;
  \ras_timer_r_reg[0]_0\ <= \^ras_timer_r_reg[0]_0\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  ras_timer_zero_r_reg <= \^ras_timer_zero_r_reg\;
  \rd_this_rank_r_reg[0]\ <= \^rd_this_rank_r_reg[0]\;
  req_bank_rdy_ns <= \^req_bank_rdy_ns\;
  \starve_limit_cntr_r_reg[2]\ <= \^starve_limit_cntr_r_reg[2]\;
  tail_r <= \^tail_r\;
bank_compare0: entity work.mig_7series_0_mig_7series_v2_3_bank_compare_2
     port map (
      CLK => CLK,
      E(0) => idle_ns(0),
      Q(0) => Q(0),
      S(0) => S(0),
      accept_r_reg => accept_r_reg,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_2,
      \app_addr_r1_reg[23]\(13 downto 0) => \app_addr_r1_reg[23]\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[13]\(13 downto 0) => \cmd_pipe_plus.mc_address_reg[13]\(13 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0),
      \grant_r_reg[0]\(0) => \grant_r_reg[2]_0\(0),
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      head_r_lcl_reg => \^head_r_lcl_reg_3\,
      head_r_lcl_reg_0 => \^head_r_lcl_reg_1\,
      hi_priority => hi_priority,
      idle_r_lcl_reg => \^accept_internal_r_reg\,
      idle_r_lcl_reg_0 => \^e\(0),
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg_0\,
      maint_req_r => maint_req_r,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      ordered_r(0) => \^ordered_r\(0),
      ordered_r_lcl_reg => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_0 => bank_compare0_n_6,
      p_130_out => p_130_out,
      p_145_out => p_145_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg => \^act_wait_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg_1,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_0,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r => \^pre_bm_end_r\,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_wait_r => pre_wait_r,
      q_has_priority_r_reg => \^q_has_priority_r_reg\,
      ras_timer_zero_r_reg => bank_compare0_n_13,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\(0),
      rb_hit_busy_r_reg_0 => bank_compare0_n_28,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg,
      rb_hit_busy_r_reg_2 => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_3 => rb_hit_busy_r_reg_1,
      \rd_this_rank_r_reg[0]\ => \^rd_this_rank_r_reg[0]\,
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => req_wr_r_lcl_reg,
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      start_wtp_timer0 => start_wtp_timer0,
      tail_r => \^tail_r\,
      wait_for_maint_r_lcl_reg => \^auto_pre_r_lcl_reg\
    );
bank_queue0: entity work.mig_7series_0_mig_7series_v2_3_bank_queue
     port map (
      CLK => CLK,
      D(0) => D(0),
      E(0) => idle_ns(0),
      Q(0) => Q(0),
      SR(0) => SR(0),
      accept_internal_r_reg => \^accept_internal_r_reg\,
      accept_internal_r_reg_0 => accept_internal_r_reg_0,
      act_wait_ns => act_wait_ns,
      act_wait_r_lcl_reg => \^act_wait_r_lcl_reg\,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_1 => bank_queue0_n_22,
      act_wait_r_lcl_reg_2 => \^act_this_rank_r_reg[0]\,
      act_wait_r_lcl_reg_3 => bank_state0_n_15,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => \^auto_pre_r\,
      bm_end_r1_reg => \^ras_timer_r_reg[1]\,
      bm_end_r1_reg_0 => \^ras_timer_zero_r_reg\,
      bm_end_r1_reg_1 => bm_end_r1_reg_0,
      bm_end_r1_reg_2 => bm_end_r1_reg_1,
      bm_end_r1_reg_3 => bm_end_r1_reg_2,
      col_wait_r_reg => \^starve_limit_cntr_r_reg[2]\,
      \compute_tail.tail_r_lcl_reg_0\ => bank_state0_n_20,
      demand_priority_r_reg => bank_queue0_n_39,
      \grant_r_reg[0]\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_0\ => bank_queue0_n_40,
      \grant_r_reg[0]_1\(0) => \grant_r_reg[2]_0\(0),
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => head_r_lcl_reg_0,
      head_r_lcl_reg_2 => head_r_lcl_reg_2,
      head_r_lcl_reg_3 => head_r_lcl_reg_4,
      head_r_lcl_reg_4 => head_r_lcl_reg_5,
      idle_r_lcl_reg_0 => idle_r_lcl_reg,
      idle_r_lcl_reg_1 => idle_r_lcl_reg_7,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_3 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_4 => idle_r_lcl_reg_2,
      idle_r_lcl_reg_5 => idle_r_lcl_reg_3,
      idle_r_lcl_reg_6(0) => idle_r_lcl_reg_4(0),
      idle_r_lcl_reg_7(0) => idle_r_lcl_reg_5(0),
      idle_r_lcl_reg_8(0) => idle_r_lcl_reg_6(0),
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg\,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      ordered_r(0) => \^ordered_r\(0),
      ordered_r_lcl_reg_0 => bank_compare0_n_6,
      ordered_r_lcl_reg_1 => ordered_r_lcl_reg_0,
      ordered_r_lcl_reg_2 => ordered_r_lcl_reg_1,
      p_145_out => p_145_out,
      p_7_in => p_7_in,
      pass_open_bank_ns => pass_open_bank_ns,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_0,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg_2,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r => \^pre_bm_end_r\,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg_1,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_passing_open_bank_r_reg_1 => pre_passing_open_bank_r_reg_0,
      q_entry_ns(0) => q_entry_ns(0),
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\(0),
      \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_1\,
      \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_2\,
      \q_entry_r_reg[1]_4\ => \q_entry_r_reg[1]_3\,
      \q_entry_r_reg[1]_5\ => \q_entry_r_reg[1]_4\,
      q_has_priority => q_has_priority,
      q_has_priority_r_reg_0 => q_has_priority_r_reg_0,
      q_has_rd => \^q_has_rd\,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[1]\(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(2 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(2 downto 0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(2 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(2 downto 0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(0),
      rb_hit_busy_r_reg => \^head_r_lcl_reg_1\,
      rb_hit_busy_r_reg_0 => \^head_r_lcl_reg_3\,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg,
      rb_hit_busy_r_reg_2 => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_3 => rb_hit_busy_r_reg_1,
      rb_hit_busy_r_reg_4 => \^q_has_priority_r_reg\,
      rd_wr_r_lcl_reg => \^ras_timer_r_reg[0]_0\,
      rd_wr_r_lcl_reg_0 => \^rd_this_rank_r_reg[0]\,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_2,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_3,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_4,
      rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg_5,
      \req_bank_r_lcl_reg[2]\ => bank_compare0_n_28,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      \req_data_buf_addr_r_reg[4]\ => \^e\(0),
      req_priority_r => req_priority_r,
      req_wr_r_lcl_reg => req_wr_r_lcl_reg,
      req_wr_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      req_wr_r_lcl_reg_1 => req_wr_r_lcl_reg_0,
      req_wr_r_lcl_reg_2 => req_wr_r_lcl_reg_1,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      tail_r => \^tail_r\,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0
    );
bank_state0: entity work.mig_7series_0_mig_7series_v2_3_bank_state
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      SR(0) => SR(0),
      act_this_rank_r(0) => act_this_rank_r(0),
      \act_this_rank_r_reg[0]_0\ => \^act_this_rank_r_reg[0]\,
      act_wait_ns => act_wait_ns,
      auto_pre_r_lcl_reg => bank_state0_n_20,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      bm_end_r1_reg_0 => bm_end_r1_reg,
      col_wait_r_reg_0 => col_wait_r_reg,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demand_priority_r_reg_1 => demand_priority_r_reg_0,
      demanded_prior_r_reg_0 => demanded_prior_r,
      demanded_prior_r_reg_1 => demanded_prior_r_reg,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_3 => demanded_prior_r_reg_1,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_0\(0) => \grant_r_reg[0]_1\(0),
      \grant_r_reg[0]_1\(0) => \grant_r_reg[0]_2\(0),
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[2]\ => \grant_r_reg[2]\,
      \grant_r_reg[2]_0\(1 downto 0) => \grant_r_reg[2]_0\(1 downto 0),
      granted_col_ns => granted_col_ns,
      granted_col_r_reg => granted_col_r_reg,
      granted_col_r_reg_0 => granted_col_r_reg_0,
      idle_r_lcl_reg => \^accept_internal_r_reg\,
      idle_r_lcl_reg_0 => bank_queue0_n_22,
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      override_demand_r_reg => override_demand_r_reg,
      p_130_out => p_130_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg => \^act_wait_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      q_has_rd => \^q_has_rd\,
      \ras_timer_r_reg[0]_0\ => \^ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => \^ras_timer_zero_r_reg\,
      ras_timer_zero_r_reg_1 => bank_state0_n_15,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\,
      rb_hit_busy_r_reg => \^q_has_priority_r_reg\,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      rd_wr_r_lcl_reg => \^rd_this_rank_r_reg[0]\,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_2 => bank_queue0_n_40,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_4 => bank_queue0_n_39,
      rd_wr_r_lcl_reg_5 => bank_compare0_n_13,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg,
      req_wr_r_lcl_reg => \^ordered_r_lcl_reg\,
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      start_wtp_timer0 => start_wtp_timer0,
      \starve_limit_cntr_r_reg[2]_0\ => \^starve_limit_cntr_r_reg[2]\,
      tail_r => \^tail_r\,
      wr_this_rank_r(0) => wr_this_rank_r(0),
      \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized0\ is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    q_has_priority_r_reg : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    \act_this_rank_r_reg[0]\ : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_wait_r_lcl_reg : out STD_LOGIC;
    bm_end_r1_reg_0 : out STD_LOGIC;
    q_has_rd_4 : out STD_LOGIC;
    q_has_priority_5 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    tail_r_19 : out STD_LOGIC;
    wait_for_maint_r_lcl_reg : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    ordered_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[1]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : out STD_LOGIC;
    \maint_controller.maint_rdy\ : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    granted_row_ns : out STD_LOGIC;
    granted_row_r_reg : out STD_LOGIC;
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    req_bank_rdy_r_reg : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    \grant_r_reg[1]_1\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[13]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : out STD_LOGIC;
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ofs_rdy_r0 : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    head_r_lcl_reg_1 : in STD_LOGIC;
    \req_row_r_lcl_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[0]\ : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    \grant_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    accept_r_reg : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : in STD_LOGIC;
    idle_r_lcl_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_5 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pre_bm_end_r_reg : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    idle_r_lcl_reg_6 : in STD_LOGIC;
    pre_passing_open_bank_r_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    bm_end_r1_reg_3 : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    req_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    req_wr_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg_4 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_2 : in STD_LOGIC;
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[1]_3\ : in STD_LOGIC;
    \last_master_r_reg[0]\ : in STD_LOGIC;
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \grant_r_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_0\ : in STD_LOGIC;
    demanded_prior_r_reg_0 : in STD_LOGIC;
    override_demand_r : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    q_entry_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_7 : in STD_LOGIC;
    idle_r_lcl_reg_8 : in STD_LOGIC;
    ordered_r_lcl_reg : in STD_LOGIC;
    ordered_r_lcl_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized0\ : entity is "mig_7series_v2_3_bank_cntrl";
end \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized0\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^act_this_rank_r_reg[0]\ : STD_LOGIC;
  signal act_wait_ns : STD_LOGIC;
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^auto_pre_r\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_12 : STD_LOGIC;
  signal bank_compare0_n_13 : STD_LOGIC;
  signal bank_queue0_n_37 : STD_LOGIC;
  signal bank_state0_n_18 : STD_LOGIC;
  signal \^bm_end_r1_0\ : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal \^bm_end_r1_reg_0\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ordered_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_106_out : STD_LOGIC;
  signal p_91_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_priority_r_reg\ : STD_LOGIC;
  signal \^q_has_rd_4\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^ras_timer_zero_r_reg\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_0\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_1\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC;
  signal \^req_bank_rdy_ns\ : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]\ : STD_LOGIC;
  signal \^tail_r_19\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  \act_this_rank_r_reg[0]\ <= \^act_this_rank_r_reg[0]\;
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  auto_pre_r <= \^auto_pre_r\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  bm_end_r1_0 <= \^bm_end_r1_0\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\;
  ordered_r(0) <= \^ordered_r\(0);
  q_has_priority_r_reg <= \^q_has_priority_r_reg\;
  q_has_rd_4 <= \^q_has_rd_4\;
  ras_timer_zero_r_reg <= \^ras_timer_zero_r_reg\;
  ras_timer_zero_r_reg_0 <= \^ras_timer_zero_r_reg_0\;
  ras_timer_zero_r_reg_1 <= \^ras_timer_zero_r_reg_1\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  \rd_this_rank_r_reg[0]\ <= \^rd_this_rank_r_reg[0]\;
  req_bank_rdy_ns <= \^req_bank_rdy_ns\;
  \starve_limit_cntr_r_reg[2]\ <= \^starve_limit_cntr_r_reg[2]\;
  tail_r_19 <= \^tail_r_19\;
bank_compare0: entity work.mig_7series_0_mig_7series_v2_3_bank_compare_1
     port map (
      CLK => CLK,
      E(0) => idle_ns(1),
      Q(0) => Q(0),
      accept_r_reg => accept_r_reg,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_0 => \^act_this_rank_r_reg[0]\,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]\(0),
      \app_addr_r1_reg[23]_0\(13 downto 0) => \app_addr_r1_reg[23]_0\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      bm_end_r1_reg => \^bm_end_r1_reg\,
      \cmd_pipe_plus.mc_address_reg[13]\(13 downto 0) => \cmd_pipe_plus.mc_address_reg[13]\(13 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[38]\ => \cmd_pipe_plus.mc_address_reg[38]\,
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0),
      \grant_r_reg[1]\ => bank_compare0_n_13,
      \grant_r_reg[1]_0\(1 downto 0) => \grant_r_reg[3]\(1 downto 0),
      \grant_r_reg[1]_1\(1 downto 0) => \grant_r_reg[1]_2\(1 downto 0),
      head_r_lcl_reg => head_r_lcl_reg,
      hi_priority => hi_priority,
      idle_r_lcl_reg => \^rb_hit_busy_r_reg\,
      idle_r_lcl_reg_0 => \^e\(0),
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg\,
      maint_req_r => maint_req_r,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      order_q_r(1 downto 0) => order_q_r(1 downto 0),
      ordered_r(0) => \^ordered_r\(0),
      ordered_r_lcl_reg => bank_compare0_n_12,
      p_106_out => p_106_out,
      p_91_out => p_91_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg => \^act_wait_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_1,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r_reg => pre_bm_end_r_reg,
      pre_bm_end_r_reg_0 => \^bm_end_r1_reg_0\,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_wait_r => pre_wait_r,
      q_has_priority_r_reg => \^q_has_priority_r_reg\,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      \rd_this_rank_r_reg[0]\ => \^rd_this_rank_r_reg[0]\,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg_3,
      req_bank_rdy_r_reg => req_bank_rdy_r_reg,
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      \req_row_r_lcl_reg[10]_0\(0) => \req_row_r_lcl_reg[10]\(0),
      \req_row_r_lcl_reg[3]_0\(0) => \req_row_r_lcl_reg[3]\(0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => req_wr_r_lcl_reg,
      req_wr_r_lcl_reg_1 => req_wr_r_lcl_reg_1,
      req_wr_r_lcl_reg_2(0) => req_wr_r_lcl_reg_2(0),
      row_cmd_wr(0) => row_cmd_wr(0),
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      start_wtp_timer0 => start_wtp_timer0,
      tail_r_19 => \^tail_r_19\,
      wait_for_maint_r_lcl_reg => \^auto_pre_r_lcl_reg\
    );
bank_queue0: entity work.\mig_7series_0_mig_7series_v2_3_bank_queue__parameterized0\
     port map (
      CLK => CLK,
      D(0) => D(0),
      E(0) => idle_ns(1),
      Q(0) => Q(0),
      SR(0) => SR(0),
      accept_internal_r_reg => accept_internal_r_reg,
      act_wait_ns => act_wait_ns,
      act_wait_r_lcl_reg => \^act_wait_r_lcl_reg\,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_1 => \^act_this_rank_r_reg[0]\,
      act_wait_r_lcl_reg_2 => \^ras_timer_zero_r_reg_1\,
      act_wait_r_lcl_reg_3 => act_wait_r_lcl_reg_2,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => \^auto_pre_r\,
      bm_end_r1_0 => \^bm_end_r1_0\,
      bm_end_r1_reg => \^bm_end_r1_reg_0\,
      bm_end_r1_reg_0 => \^ras_timer_zero_r_reg_0\,
      bm_end_r1_reg_1 => bm_end_r1_reg_1,
      bm_end_r1_reg_2 => bm_end_r1_reg_2,
      bm_end_r1_reg_3 => bm_end_r1_reg_3,
      col_wait_r_reg => \^starve_limit_cntr_r_reg[2]\,
      \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\,
      \compute_tail.tail_r_lcl_reg_1\ => bank_state0_n_18,
      demand_priority_r_reg => bank_queue0_n_37,
      \grant_r_reg[1]\ => \grant_r_reg[1]_0\,
      \grant_r_reg[1]_0\(0) => \grant_r_reg[3]\(1),
      \grant_r_reg[1]_1\ => \grant_r_reg[1]_3\,
      granted_row_ns => granted_row_ns,
      granted_row_r_reg => granted_row_r_reg,
      head_r_lcl_reg_0 => head_r_lcl_reg_0,
      head_r_lcl_reg_1 => head_r_lcl_reg_1,
      idle_r_lcl_reg_0 => idle_r_lcl_reg,
      idle_r_lcl_reg_1 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_3 => idle_r_lcl_reg_2,
      idle_r_lcl_reg_4(0) => idle_r_lcl_reg_3(0),
      idle_r_lcl_reg_5(0) => idle_r_lcl_reg_4(0),
      idle_r_lcl_reg_6(0) => idle_r_lcl_reg_5(0),
      idle_r_lcl_reg_7 => idle_r_lcl_reg_6,
      idle_r_lcl_reg_8 => idle_r_lcl_reg_7,
      idle_r_lcl_reg_9 => idle_r_lcl_reg_8,
      \maint_controller.maint_hit_busies_r_reg[3]\(3 downto 0) => \maint_controller.maint_hit_busies_r_reg[3]\(3 downto 0),
      \maint_controller.maint_rdy\ => \maint_controller.maint_rdy\,
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg\,
      \maint_controller.maint_wip_r_lcl_reg_0\ => \maint_controller.maint_wip_r_lcl_reg_0\,
      maint_req_r => maint_req_r,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      order_q_r(1 downto 0) => order_q_r(1 downto 0),
      ordered_r(0) => \^ordered_r\(0),
      ordered_r_lcl_reg_0 => bank_compare0_n_12,
      ordered_r_lcl_reg_1 => ordered_r_lcl_reg,
      ordered_r_lcl_reg_2 => ordered_r_lcl_reg_0,
      p_106_out => p_106_out,
      pass_open_bank_ns => pass_open_bank_ns,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg_0,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_1,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg_2,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg_1,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_passing_open_bank_r_reg_1 => pre_passing_open_bank_r_reg_0,
      q_entry_ns(0) => q_entry_ns(0),
      \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_1\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      q_has_priority_5 => q_has_priority_5,
      q_has_priority_r_reg_0 => q_has_priority_r_reg_0,
      q_has_rd_4 => \^q_has_rd_4\,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]_2\,
      \ras_timer_r_reg[1]\(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(2 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(2 downto 0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(2 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\(2 downto 0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0),
      rb_hit_busy_r_reg => \^rb_hit_busy_r_reg\,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1,
      rd_wr_r_lcl_reg => \^rd_this_rank_r_reg[0]\,
      rd_wr_r_lcl_reg_0 => \^ras_timer_zero_r_reg\,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_2,
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]\,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      \req_data_buf_addr_r_reg[4]\ => \^e\(0),
      req_priority_r => req_priority_r,
      req_wr_r_lcl_reg => \^bm_end_r1_reg\,
      req_wr_r_lcl_reg_0 => req_wr_r_lcl_reg,
      req_wr_r_lcl_reg_1 => req_wr_r_lcl_reg_0,
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      tail_r_19 => \^tail_r_19\,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0,
      wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_1
    );
bank_state0: entity work.\mig_7series_0_mig_7series_v2_3_bank_state__parameterized0\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      SR(0) => SR(0),
      act_this_rank_r(0) => act_this_rank_r(0),
      \act_this_rank_r_reg[0]_0\ => \^act_this_rank_r_reg[0]\,
      act_wait_ns => act_wait_ns,
      auto_pre_r_lcl_reg => bank_state0_n_18,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_0,
      bm_end_r1_0 => \^bm_end_r1_0\,
      bm_end_r1_reg_0 => bm_end_r1_reg_4,
      col_wait_r_reg_0 => col_wait_r_reg,
      col_wait_r_reg_1 => col_wait_r_reg_0,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demand_priority_r_reg_1 => demand_priority_r_reg_0,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_1,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]_1\,
      \grant_r_reg[1]_1\(0) => \grant_r_reg[1]_2\(1),
      \grant_r_reg[1]_2\(0) => \grant_r_reg[1]_4\(0),
      \grant_r_reg[2]\ => \grant_r_reg[2]\,
      \grant_r_reg[3]\(1 downto 0) => \grant_r_reg[3]\(2 downto 1),
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_0\,
      granted_col_r_reg => granted_col_r_reg,
      idle_r_lcl_reg => \^rb_hit_busy_r_reg\,
      \last_master_r_reg[0]\ => \last_master_r_reg[0]\,
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      \order_q_r_reg[0]\ => bank_compare0_n_13,
      override_demand_r => override_demand_r,
      p_91_out => p_91_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r_lcl_reg => \^act_wait_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg_2,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      q_has_rd_4 => \^q_has_rd_4\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => \^ras_timer_zero_r_reg\,
      ras_timer_zero_r_reg_1 => \^ras_timer_zero_r_reg_0\,
      ras_timer_zero_r_reg_2 => \^ras_timer_zero_r_reg_1\,
      rb_hit_busy_r_reg => \^q_has_priority_r_reg\,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      rd_wr_r_lcl_reg => \^rd_this_rank_r_reg[0]\,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_1 => bank_queue0_n_37,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg_0,
      req_wr_r_lcl_reg => \^bm_end_r1_reg\,
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      start_wtp_timer0 => start_wtp_timer0,
      \starve_limit_cntr_r_reg[2]_0\ => \^starve_limit_cntr_r_reg[2]\,
      tail_r_19 => \^tail_r_19\,
      wr_this_rank_r(0) => wr_this_rank_r(0),
      \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized1\ is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_priority_r_reg : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    \act_this_rank_r_reg[0]\ : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd_9 : out STD_LOGIC;
    q_has_priority_10 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    tail_r_20 : out STD_LOGIC;
    wait_for_maint_r_lcl_reg : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[2]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    head_r_lcl_reg : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \order_q_r_reg[0]\ : out STD_LOGIC;
    req_bank_rdy_r_reg : out STD_LOGIC;
    \order_q_r_reg[1]\ : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : out STD_LOGIC;
    granted_row_r_reg : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ofs_rdy_r0 : out STD_LOGIC;
    ofs_rdy_r0_0 : out STD_LOGIC;
    ofs_rdy_r0_1 : out STD_LOGIC;
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    override_demand_ns : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd_r_reg : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_mc_ctl_full : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    ordered_r_lcl_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    idle_r_lcl_reg_3 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_2 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    \grant_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    accept_r_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_3 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : in STD_LOGIC;
    ras_timer_zero_r_reg_1 : in STD_LOGIC;
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    \grant_r_reg[3]_1\ : in STD_LOGIC;
    \grant_r_reg[2]_1\ : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    demanded_prior_r_reg_0 : in STD_LOGIC;
    \grant_r_reg[0]_1\ : in STD_LOGIC;
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \grant_r_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    demand_priority_r : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    \req_row_r_lcl_reg[10]\ : in STD_LOGIC;
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_5 : in STD_LOGIC;
    phy_mc_data_full : in STD_LOGIC;
    rd_wr_r_lcl_reg_6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r_reg_0 : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    idle_r_lcl_reg_4 : in STD_LOGIC;
    \q_entry_r_reg[1]_2\ : in STD_LOGIC;
    idle_r_lcl_reg_5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized1\ : entity is "mig_7series_v2_3_bank_cntrl";
end \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized1\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^act_this_rank_r_reg[0]\ : STD_LOGIC;
  signal act_wait_ns : STD_LOGIC;
  signal \^auto_pre_r\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_14 : STD_LOGIC;
  signal bank_compare0_n_5 : STD_LOGIC;
  signal bank_queue0_n_21 : STD_LOGIC;
  signal bank_queue0_n_31 : STD_LOGIC;
  signal bank_state0_n_14 : STD_LOGIC;
  signal bank_state0_n_19 : STD_LOGIC;
  signal \^bm_end_r1_1\ : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 2 to 2 );
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^order_q_r_reg[0]\ : STD_LOGIC;
  signal \^order_q_r_reg[1]\ : STD_LOGIC;
  signal ordered_r : STD_LOGIC_VECTOR ( 2 to 2 );
  signal p_67_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal pass_open_bank_r : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_priority_10\ : STD_LOGIC;
  signal \^q_has_priority_r_reg\ : STD_LOGIC;
  signal \^q_has_rd_9\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^ras_timer_zero_r_reg\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_0\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rd_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^req_bank_rdy_ns\ : STD_LOGIC;
  signal \^req_bank_rdy_r_reg\ : STD_LOGIC;
  signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]\ : STD_LOGIC;
  signal \^tail_r_20\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  \act_this_rank_r_reg[0]\ <= \^act_this_rank_r_reg[0]\;
  auto_pre_r <= \^auto_pre_r\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  bm_end_r1_1 <= \^bm_end_r1_1\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  \order_q_r_reg[0]\ <= \^order_q_r_reg[0]\;
  \order_q_r_reg[1]\ <= \^order_q_r_reg[1]\;
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  q_has_priority_10 <= \^q_has_priority_10\;
  q_has_priority_r_reg <= \^q_has_priority_r_reg\;
  q_has_rd_9 <= \^q_has_rd_9\;
  ras_timer_zero_r_reg <= \^ras_timer_zero_r_reg\;
  ras_timer_zero_r_reg_0 <= \^ras_timer_zero_r_reg_0\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rd_wr_r(0) <= \^rd_wr_r\(0);
  req_bank_rdy_ns <= \^req_bank_rdy_ns\;
  req_bank_rdy_r_reg <= \^req_bank_rdy_r_reg\;
  req_wr_r(0) <= \^req_wr_r\(0);
  \starve_limit_cntr_r_reg[2]\ <= \^starve_limit_cntr_r_reg[2]\;
  tail_r_20 <= \^tail_r_20\;
bank_compare0: entity work.mig_7series_0_mig_7series_v2_3_bank_compare_0
     port map (
      CLK => CLK,
      E(0) => idle_ns(2),
      Q(0) => Q(0),
      accept_r_reg => accept_r_reg,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_1 => \^act_this_rank_r_reg[0]\,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_1,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]\(0),
      \app_addr_r1_reg[23]_0\(13 downto 0) => \app_addr_r1_reg[23]_0\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[38]\(0) => \cmd_pipe_plus.mc_address_reg[38]\(0),
      \cmd_pipe_plus.mc_address_reg[41]\(13 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(13 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0),
      col_wait_r_reg => \^starve_limit_cntr_r_reg[2]\,
      demand_priority_r_reg => bank_compare0_n_14,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[3]\(1 downto 0) => \grant_r_reg[3]\(2 downto 1),
      \grant_r_reg[3]_0\(1 downto 0) => \grant_r_reg[3]_0\(1 downto 0),
      hi_priority => hi_priority,
      idle_r_lcl_reg => \^rb_hit_busy_r_reg\,
      idle_r_lcl_reg_0 => \^e\(0),
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg_0\,
      maint_req_r => maint_req_r,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      order_q_r(1 downto 0) => order_q_r(1 downto 0),
      \order_q_r_reg[0]\ => \^order_q_r_reg[0]\,
      \order_q_r_reg[1]\ => \^order_q_r_reg[1]\,
      ordered_r(0) => ordered_r(2),
      ordered_r_lcl_reg => \^req_wr_r\(0),
      ordered_r_lcl_reg_0 => bank_compare0_n_5,
      ordered_r_lcl_reg_1(2 downto 0) => ordered_r_lcl_reg(2 downto 0),
      p_67_out => p_67_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      pass_open_bank_r_lcl_reg => \^pass_open_bank_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg_1,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r => pre_bm_end_r,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_wait_r => pre_wait_r,
      q_has_priority_10 => \^q_has_priority_10\,
      q_has_priority_r_reg => \^q_has_priority_r_reg\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\(0),
      \rd_this_rank_r_reg[0]\ => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg_0(0) => rd_wr_r_lcl_reg_4(0),
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_3,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r_reg => \^req_bank_rdy_r_reg\,
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      \req_row_r_lcl_reg[10]_0\ => \req_row_r_lcl_reg[10]\,
      req_wr_r_lcl0 => req_wr_r_lcl0,
      req_wr_r_lcl_reg_0 => req_wr_r_lcl_reg_0,
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      start_wtp_timer0 => start_wtp_timer0,
      tail_r_20 => \^tail_r_20\,
      wait_for_maint_r_lcl_reg => \^auto_pre_r_lcl_reg\
    );
bank_queue0: entity work.\mig_7series_0_mig_7series_v2_3_bank_queue__parameterized1\
     port map (
      CLK => CLK,
      D(0) => D(0),
      E(0) => idle_ns(2),
      Q(0) => Q(0),
      SR(0) => SR(0),
      accept_internal_r_reg => accept_internal_r_reg,
      act_wait_ns => act_wait_ns,
      act_wait_r_lcl_reg => bank_queue0_n_21,
      act_wait_r_lcl_reg_0 => \^act_this_rank_r_reg[0]\,
      act_wait_r_lcl_reg_1 => bank_state0_n_14,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => \^auto_pre_r\,
      bm_end_r1_1 => \^bm_end_r1_1\,
      bm_end_r1_reg => \^bm_end_r1_reg\,
      bm_end_r1_reg_0 => \^ras_timer_zero_r_reg_0\,
      bm_end_r1_reg_1 => bm_end_r1_reg_0,
      bm_end_r1_reg_2 => bm_end_r1_reg_1,
      bm_end_r1_reg_3 => bm_end_r1_reg_2,
      \compute_tail.tail_r_lcl_reg_0\ => bank_state0_n_19,
      \grant_r_reg[2]\ => bank_queue0_n_31,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      \grant_r_reg[2]_1\(0) => \grant_r_reg[3]\(1),
      \grant_r_reg[2]_2\ => \grant_r_reg[2]_1\,
      \grant_r_reg[3]\ => \grant_r_reg[3]_1\,
      granted_row_r_reg => granted_row_r_reg,
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => head_r_lcl_reg_0,
      idle_r_lcl_reg_0 => idle_r_lcl_reg,
      idle_r_lcl_reg_1 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_3 => idle_r_lcl_reg_2,
      idle_r_lcl_reg_4 => idle_r_lcl_reg_3,
      idle_r_lcl_reg_5 => idle_r_lcl_reg_4,
      idle_r_lcl_reg_6 => idle_r_lcl_reg_5,
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg\,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      order_q_r(1 downto 0) => order_q_r(1 downto 0),
      ordered_r(0) => ordered_r(2),
      ordered_r_lcl_reg_0 => bank_compare0_n_5,
      ordered_r_lcl_reg_1 => \^order_q_r_reg[1]\,
      ordered_r_lcl_reg_2 => \^order_q_r_reg[0]\,
      p_67_out => p_67_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_0,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg_2,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r => pre_bm_end_r,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg_1,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_passing_open_bank_r_reg_1 => pre_passing_open_bank_r_reg_0,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_1\,
      \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_2\,
      q_has_priority_10 => \^q_has_priority_10\,
      q_has_priority_r_reg_0 => q_has_priority_r_reg_0,
      q_has_rd_9 => \^q_has_rd_9\,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[1]\(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(2 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(2 downto 0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2\(2 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\(2 downto 0),
      rb_hit_busy_r_reg => \^rb_hit_busy_r_reg\,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1,
      rd_wr_r_lcl_reg => \^ras_timer_zero_r_reg\,
      rd_wr_r_lcl_reg_0 => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_2,
      rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg_3,
      \req_bank_r_lcl_reg[2]\ => \req_bank_r_lcl_reg[2]\,
      \req_data_buf_addr_r_reg[4]\ => \^e\(0),
      req_wr_r_lcl_reg => \^pass_open_bank_r_lcl_reg\,
      req_wr_r_lcl_reg_0 => \^req_wr_r\(0),
      req_wr_r_lcl_reg_1 => req_wr_r_lcl_reg,
      req_wr_r_lcl_reg_2 => \^req_bank_rdy_r_reg\,
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      tail_r_20 => \^tail_r_20\,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0
    );
bank_state0: entity work.\mig_7series_0_mig_7series_v2_3_bank_state__parameterized1\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      SR(0) => SR(0),
      act_this_rank_r(0) => act_this_rank_r(0),
      \act_this_rank_r_reg[0]_0\ => \^act_this_rank_r_reg[0]\,
      act_wait_ns => act_wait_ns,
      auto_pre_r_lcl_reg => bank_state0_n_19,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_0,
      bm_end_r1_1 => \^bm_end_r1_1\,
      bm_end_r1_reg_0 => bm_end_r1_reg_3,
      col_wait_r_reg_0 => col_wait_r_reg,
      demand_priority_r => demand_priority_r,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      \grant_r_reg[0]\ => \grant_r_reg[0]_0\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]_1\,
      \grant_r_reg[2]\ => \grant_r_reg[2]\,
      \grant_r_reg[2]_0\(1 downto 0) => \grant_r_reg[3]\(1 downto 0),
      \grant_r_reg[2]_1\(0) => \grant_r_reg[3]_0\(0),
      \grant_r_reg[2]_2\(0) => \grant_r_reg[2]_2\(0),
      granted_col_r_reg => granted_col_r_reg,
      idle_r_lcl_reg => \^rb_hit_busy_r_reg\,
      idle_r_lcl_reg_0 => bank_queue0_n_21,
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      ofs_rdy_r0_0 => ofs_rdy_r0_0,
      ofs_rdy_r0_1 => ofs_rdy_r0_1,
      \order_q_r_reg[0]\ => bank_queue0_n_31,
      override_demand_ns => override_demand_ns,
      override_demand_r => override_demand_r,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg_0,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg => \^bm_end_r1_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      q_has_rd_9 => \^q_has_rd_9\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => bank_state0_n_14,
      ras_timer_zero_r_reg_1 => \^ras_timer_zero_r_reg\,
      ras_timer_zero_r_reg_2 => \^ras_timer_zero_r_reg_0\,
      ras_timer_zero_r_reg_3 => ras_timer_zero_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\,
      rb_hit_busy_r_reg => \^q_has_priority_r_reg\,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      rd_wr_r_lcl_reg => \^rd_wr_r\(0),
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_1 => bank_compare0_n_14,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_5,
      rd_wr_r_lcl_reg_3(0) => rd_wr_r_lcl_reg_4(0),
      rd_wr_r_lcl_reg_4(0) => rd_wr_r_lcl_reg_6(0),
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg_0,
      req_wr_r(0) => \^req_wr_r\(0),
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      start_wtp_timer0 => start_wtp_timer0,
      \starve_limit_cntr_r_reg[2]_0\ => \^starve_limit_cntr_r_reg[2]\,
      tail_r_20 => \^tail_r_20\,
      wr_this_rank_r(0) => wr_this_rank_r(0),
      \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized2\ is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ordered_r_lcl_reg : out STD_LOGIC;
    q_has_priority_r_reg : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    bm_end_r1_reg : out STD_LOGIC;
    \act_this_rank_r_reg[0]\ : out STD_LOGIC;
    \starve_limit_cntr_r_reg[2]\ : out STD_LOGIC;
    act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    req_bank_rdy_r : out STD_LOGIC;
    req_bank_rdy_ns : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    ofs_rdy_r : out STD_LOGIC;
    wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    q_has_rd_14 : out STD_LOGIC;
    q_has_priority_15 : out STD_LOGIC;
    auto_pre_r_lcl_reg : out STD_LOGIC;
    tail_r_21 : out STD_LOGIC;
    wait_for_maint_r_lcl_reg : out STD_LOGIC;
    auto_pre_r : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    granted_col_r_reg : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    \ras_timer_r_reg[1]\ : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[2]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \cmd_pipe_plus.mc_address_reg[10]\ : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[38]\ : out STD_LOGIC;
    \col_mux.col_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_address_reg[23]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CLK : in STD_LOGIC;
    periodic_rd_insert : in STD_LOGIC;
    req_wr_r_lcl0 : in STD_LOGIC;
    hi_priority : in STD_LOGIC;
    col_wait_r_reg : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ofs_rdy_r0 : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    head_r_lcl_reg_0 : in STD_LOGIC;
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[0]\ : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    idle_r_lcl_reg_2 : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    rd_wr_r_lcl_reg : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    override_demand_r_reg : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    pre_passing_open_bank_r_reg : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : in STD_LOGIC;
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC;
    pre_passing_open_bank_r_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg_3 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    rb_hit_busy_r_reg_0 : in STD_LOGIC;
    idle_r_lcl_reg_4 : in STD_LOGIC;
    rb_hit_busy_r_reg_1 : in STD_LOGIC;
    rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 );
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    pre_bm_end_r_reg_0 : in STD_LOGIC;
    pre_bm_end_r_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_1 : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_2 : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    accept_internal_r_reg : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    \grant_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    accept_r_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    bm_end_r1_reg_3 : in STD_LOGIC;
    maint_req_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg_0\ : in STD_LOGIC;
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \req_row_r_lcl_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    row_cmd_wr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_4\ : in STD_LOGIC;
    demanded_prior_r : in STD_LOGIC;
    demand_priority_r_reg_0 : in STD_LOGIC;
    demanded_prior_r_reg_1 : in STD_LOGIC;
    req_bank_rdy_r_reg : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC;
    cs_en2 : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    idle_r_lcl_reg_5 : in STD_LOGIC;
    pre_bm_end_r_reg_2 : in STD_LOGIC;
    ordered_r_lcl_reg_1 : in STD_LOGIC;
    idle_r_lcl_reg_6 : in STD_LOGIC;
    ordered_r_lcl_reg_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized2\ : entity is "mig_7series_v2_3_bank_cntrl";
end \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized2\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^act_this_rank_r_reg[0]\ : STD_LOGIC;
  signal act_wait_ns : STD_LOGIC;
  signal \^auto_pre_r\ : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal bank_compare0_n_15 : STD_LOGIC;
  signal bank_compare0_n_8 : STD_LOGIC;
  signal bank_queue0_n_30 : STD_LOGIC;
  signal bank_state0_n_17 : STD_LOGIC;
  signal \^bm_end_r1_reg\ : STD_LOGIC;
  signal idle_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ordered_r_lcl_reg\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_28_out : STD_LOGIC;
  signal pass_open_bank_ns : STD_LOGIC;
  signal pass_open_bank_r : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg\ : STD_LOGIC;
  signal pre_bm_end_ns : STD_LOGIC;
  signal pre_bm_end_r : STD_LOGIC;
  signal pre_passing_open_bank_ns : STD_LOGIC;
  signal pre_passing_open_bank_r : STD_LOGIC;
  signal pre_wait_r : STD_LOGIC;
  signal \^q_has_priority_r_reg\ : STD_LOGIC;
  signal \^q_has_rd_14\ : STD_LOGIC;
  signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ras_timer_r_reg[0]_0\ : STD_LOGIC;
  signal \^ras_timer_r_reg[1]\ : STD_LOGIC;
  signal ras_timer_zero_r : STD_LOGIC;
  signal \^ras_timer_zero_r_reg\ : STD_LOGIC;
  signal \^ras_timer_zero_r_reg_0\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^req_bank_rdy_ns\ : STD_LOGIC;
  signal req_priority_r : STD_LOGIC;
  signal req_row_r : STD_LOGIC_VECTOR ( 52 to 52 );
  signal row_hit_r : STD_LOGIC;
  signal start_wtp_timer0 : STD_LOGIC;
  signal \^starve_limit_cntr_r_reg[2]\ : STD_LOGIC;
  signal \^tail_r_21\ : STD_LOGIC;
begin
  E(0) <= \^e\(0);
  \act_this_rank_r_reg[0]\ <= \^act_this_rank_r_reg[0]\;
  auto_pre_r <= \^auto_pre_r\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  bm_end_r1_reg <= \^bm_end_r1_reg\;
  ordered_r_lcl_reg <= \^ordered_r_lcl_reg\;
  ordered_r_lcl_reg_0(0) <= \^ordered_r_lcl_reg_0\(0);
  pass_open_bank_r_lcl_reg <= \^pass_open_bank_r_lcl_reg\;
  q_has_priority_r_reg <= \^q_has_priority_r_reg\;
  q_has_rd_14 <= \^q_has_rd_14\;
  \ras_timer_r_reg[0]_0\ <= \^ras_timer_r_reg[0]_0\;
  \ras_timer_r_reg[1]\ <= \^ras_timer_r_reg[1]\;
  ras_timer_zero_r_reg <= \^ras_timer_zero_r_reg\;
  ras_timer_zero_r_reg_0 <= \^ras_timer_zero_r_reg_0\;
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  \rd_this_rank_r_reg[0]\(0) <= \^rd_this_rank_r_reg[0]\(0);
  req_bank_rdy_ns <= \^req_bank_rdy_ns\;
  \starve_limit_cntr_r_reg[2]\ <= \^starve_limit_cntr_r_reg[2]\;
  tail_r_21 <= \^tail_r_21\;
bank_compare0: entity work.mig_7series_0_mig_7series_v2_3_bank_compare
     port map (
      CLK => CLK,
      E(0) => idle_ns(3),
      Q(1 downto 0) => Q(2 downto 1),
      accept_r_reg => accept_r_reg,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_0,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]\(0),
      \app_addr_r1_reg[23]_0\(13 downto 0) => \app_addr_r1_reg[23]_0\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[41]\(13 downto 11) => \cmd_pipe_plus.mc_address_reg[41]\(12 downto 10),
      \cmd_pipe_plus.mc_address_reg[41]\(10) => req_row_r(52),
      \cmd_pipe_plus.mc_address_reg[41]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(9 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0),
      col_wait_r_reg => col_wait_r_reg_0,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[2]\ => \grant_r_reg[2]\,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_0\,
      granted_col_r_reg => granted_col_r_reg,
      hi_priority => hi_priority,
      idle_r_lcl_reg => \^rb_hit_busy_r_reg\,
      idle_r_lcl_reg_0 => \^e\(0),
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg_0\,
      maint_req_r => maint_req_r,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      order_q_r(1 downto 0) => order_q_r(1 downto 0),
      ordered_r_lcl_reg => \^ordered_r_lcl_reg\,
      ordered_r_lcl_reg_0 => bank_compare0_n_8,
      ordered_r_lcl_reg_1(0) => \^ordered_r_lcl_reg_0\(0),
      override_demand_r_reg => override_demand_r_reg,
      p_28_out => p_28_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      pass_open_bank_r_lcl_reg => \^pass_open_bank_r_lcl_reg\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_1,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r => pre_bm_end_r,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_wait_r => pre_wait_r,
      q_has_priority_r_reg => \^q_has_priority_r_reg\,
      ras_timer_zero_r_reg => bank_compare0_n_15,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\(0),
      \rd_this_rank_r_reg[0]\ => \^rd_this_rank_r_reg[0]\(0),
      rd_wr_r(0) => rd_wr_r(0),
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_4,
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_priority_r => req_priority_r,
      req_wr_r(0) => req_wr_r(0),
      req_wr_r_lcl0 => req_wr_r_lcl0,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg,
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      start_wtp_timer0 => start_wtp_timer0,
      tail_r_21 => \^tail_r_21\,
      wait_for_maint_r_lcl_reg => \^auto_pre_r_lcl_reg\,
      \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\
    );
bank_queue0: entity work.\mig_7series_0_mig_7series_v2_3_bank_queue__parameterized2\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      E(0) => idle_ns(3),
      Q(2 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\(2 downto 0),
      SR(0) => SR(0),
      accept_internal_r_reg => accept_internal_r_reg,
      act_wait_ns => act_wait_ns,
      act_wait_r_lcl_reg => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_0 => \^act_this_rank_r_reg[0]\,
      act_wait_r_lcl_reg_1 => \^ras_timer_zero_r_reg_0\,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r_lcl_reg\,
      auto_pre_r_lcl_reg_1 => \^auto_pre_r\,
      bm_end_r1_reg => \^bm_end_r1_reg\,
      bm_end_r1_reg_0 => \^ras_timer_r_reg[1]\,
      bm_end_r1_reg_1 => \^ras_timer_zero_r_reg\,
      bm_end_r1_reg_2 => bm_end_r1_reg_0,
      bm_end_r1_reg_3 => bm_end_r1_reg_1,
      bm_end_r1_reg_4 => bm_end_r1_reg_2,
      col_wait_r_reg => \^starve_limit_cntr_r_reg[2]\,
      \compute_tail.tail_r_lcl_reg_0\ => bank_state0_n_17,
      demand_priority_r_reg => bank_queue0_n_30,
      \grant_r_reg[3]\ => \grant_r_reg[3]_1\,
      \grant_r_reg[3]_0\(0) => Q(2),
      head_r_lcl_reg_0 => head_r_lcl_reg,
      head_r_lcl_reg_1 => head_r_lcl_reg_0,
      idle_r_lcl_reg_0 => idle_r_lcl_reg,
      idle_r_lcl_reg_1 => idle_r_lcl_reg_0,
      idle_r_lcl_reg_2 => idle_r_lcl_reg_1,
      idle_r_lcl_reg_3 => idle_r_lcl_reg_2,
      idle_r_lcl_reg_4 => idle_r_lcl_reg_3,
      idle_r_lcl_reg_5 => idle_r_lcl_reg_4,
      idle_r_lcl_reg_6 => idle_r_lcl_reg_5,
      idle_r_lcl_reg_7 => idle_r_lcl_reg_6,
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg\,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      order_q_r(1 downto 0) => order_q_r(1 downto 0),
      ordered_r_lcl_reg_0(0) => \^ordered_r_lcl_reg_0\(0),
      ordered_r_lcl_reg_1 => ordered_r_lcl_reg_1,
      ordered_r_lcl_reg_2 => ordered_r_lcl_reg_2,
      p_28_out => p_28_out,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg_0,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg_2,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r => pre_bm_end_r,
      pre_bm_end_r_reg_0 => pre_bm_end_r_reg,
      pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg_1,
      pre_bm_end_r_reg_3 => pre_bm_end_r_reg_2,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_passing_open_bank_r => pre_passing_open_bank_r,
      pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg,
      pre_passing_open_bank_r_reg_1 => pre_passing_open_bank_r_reg_0,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_0\,
      q_has_priority_15 => q_has_priority_15,
      q_has_priority_r_reg_0 => q_has_priority_r_reg_0,
      q_has_rd_14 => \^q_has_rd_14\,
      q_has_rd_r_reg_0 => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]_1\,
      ras_timer_zero_r => ras_timer_zero_r,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\(0),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\(2 downto 0) => D(2 downto 0),
      rb_hit_busy_r(2 downto 0) => rb_hit_busy_r(2 downto 0),
      rb_hit_busy_r_reg => \^rb_hit_busy_r_reg\,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1,
      rb_hit_busy_r_reg_2 => \^q_has_priority_r_reg\,
      rd_wr_r_lcl_reg => bank_compare0_n_8,
      rd_wr_r_lcl_reg_0 => \^ras_timer_r_reg[0]_0\,
      rd_wr_r_lcl_reg_1 => \^rd_this_rank_r_reg[0]\(0),
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_2,
      rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg_3,
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]\,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      \req_data_buf_addr_r_reg[4]\ => \^e\(0),
      req_priority_r => req_priority_r,
      req_wr_r_lcl_reg => \^pass_open_bank_r_lcl_reg\,
      req_wr_r_lcl_reg_0 => \^ordered_r_lcl_reg\,
      req_wr_r_lcl_reg_1 => req_wr_r_lcl_reg,
      row_hit_r => row_hit_r,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      tail_r_21 => \^tail_r_21\,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0
    );
bank_state0: entity work.\mig_7series_0_mig_7series_v2_3_bank_state__parameterized2\
     port map (
      CLK => CLK,
      D(1 downto 0) => ras_timer_passed_ns(1 downto 0),
      Q(1) => Q(2),
      Q(0) => Q(0),
      SR(0) => SR(0),
      act_this_rank_r(0) => act_this_rank_r(0),
      \act_this_rank_r_reg[0]_0\ => \^act_this_rank_r_reg[0]\,
      act_wait_ns => act_wait_ns,
      auto_pre_r_lcl_reg => bank_state0_n_17,
      auto_pre_r_lcl_reg_0 => \^auto_pre_r\,
      bm_end_r1_reg_0 => bm_end_r1_reg_3,
      \cmd_pipe_plus.mc_address_reg[10]\ => \cmd_pipe_plus.mc_address_reg[10]\,
      \cmd_pipe_plus.mc_address_reg[38]\ => \cmd_pipe_plus.mc_address_reg[38]\,
      col_wait_r_reg_0 => col_wait_r_reg,
      cs_en2 => cs_en2,
      demand_priority_r_reg_0 => demand_priority_r_reg,
      demand_priority_r_reg_1 => demand_priority_r_reg_0,
      demanded_prior_r => demanded_prior_r,
      demanded_prior_r_reg_0 => demanded_prior_r_reg,
      demanded_prior_r_reg_1 => demanded_prior_r_reg_0,
      demanded_prior_r_reg_2 => demanded_prior_r_reg_1,
      \grant_r_reg[3]\(0) => \grant_r_reg[3]_2\(0),
      \grant_r_reg[3]_0\(0) => \grant_r_reg[3]_3\(0),
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_4\,
      granted_col_r_reg => granted_col_r_reg_0,
      idle_r_lcl_reg => \^rb_hit_busy_r_reg\,
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r0 => ofs_rdy_r0,
      pass_open_bank_ns => pass_open_bank_ns,
      pass_open_bank_r => pass_open_bank_r,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg_0,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \pre_4_1_1T_arb.granted_pre_r_reg\,
      pre_bm_end_ns => pre_bm_end_ns,
      pre_bm_end_r_reg => \^bm_end_r1_reg\,
      pre_passing_open_bank_ns => pre_passing_open_bank_ns,
      pre_wait_r => pre_wait_r,
      q_has_rd_14 => \^q_has_rd_14\,
      \ras_timer_r_reg[0]_0\ => \^ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[1]_0\ => \^ras_timer_r_reg[1]\,
      ras_timer_zero_r => ras_timer_zero_r,
      ras_timer_zero_r_reg_0 => \^ras_timer_zero_r_reg\,
      ras_timer_zero_r_reg_1 => \^ras_timer_zero_r_reg_0\,
      rb_hit_busy_r_reg => \^q_has_priority_r_reg\,
      rd_this_rank_r(0) => rd_this_rank_r(0),
      rd_wr_r_lcl_reg => \^rd_this_rank_r_reg[0]\(0),
      rd_wr_r_lcl_reg_0 => bank_queue0_n_30,
      rd_wr_r_lcl_reg_1 => bank_compare0_n_15,
      req_bank_rdy_ns => \^req_bank_rdy_ns\,
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg,
      \req_row_r_lcl_reg[10]\(0) => req_row_r(52),
      \req_row_r_lcl_reg[10]_0\(0) => \req_row_r_lcl_reg[10]\(0),
      req_wr_r_lcl_reg => \^ordered_r_lcl_reg\,
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      row_cmd_wr(0) => row_cmd_wr(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      start_wtp_timer0 => start_wtp_timer0,
      \starve_limit_cntr_r_reg[2]_0\ => \^starve_limit_cntr_r_reg[2]\,
      tail_r_21 => \^tail_r_21\,
      wr_this_rank_r(0) => wr_this_rank_r(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_byte_lane is
  port (
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_5 : out STD_LOGIC;
    \my_empty_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[56]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[58]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[60]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[62]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[120]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[122]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[124]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[126]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[184]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[186]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[188]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[190]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[248]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[250]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[252]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[254]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[312]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[314]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[316]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[318]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[376]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[378]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[380]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[382]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[440]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[442]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[444]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[446]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[504]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[506]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[508]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[510]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC;
    A_byte_rd_en : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[511]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[510]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[509]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[444]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[507]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[506]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[505]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[440]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_11 : in STD_LOGIC;
    phy_if_reset : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__8\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_byte_lane : entity is "mig_7series_v2_3_ddr_byte_lane";
end mig_7series_0_mig_7series_v2_3_ddr_byte_lane;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_byte_lane is
  signal A_if_a_empty : STD_LOGIC;
  signal A_of_a_full : STD_LOGIC;
  signal A_of_full : STD_LOGIC;
  signal A_pi_dqs_out_of_range : STD_LOGIC;
  signal A_pi_fine_overflow : STD_LOGIC;
  signal A_po_coarse_overflow : STD_LOGIC;
  signal A_po_fine_overflow : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d1 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d3 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d4 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d6 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d7 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 65 downto 0 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.mig_7series_0_mig_7series_v2_3_ddr_byte_group_io
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0_11 => CLKB0_11,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_10 => LD0_10,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 32) => of_dqbus(39 downto 36),
      of_dqbus(31 downto 0) => of_dqbus(31 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_7 => out_dqs_7,
      po_oserdes_rst => po_oserdes_rst,
      ts_dqs_7 => ts_dqs_7
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(0),
      Q => rd_data_r(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(1),
      Q => rd_data_r(1),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(2),
      Q => rd_data_r(2),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(3),
      Q => rd_data_r(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(4),
      Q => rd_data_r(4),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(5),
      Q => rd_data_r(5),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_8
     port map (
      A_byte_rd_en => A_byte_rd_en,
      CLK => CLK,
      Q(65 downto 0) => rd_data_r(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^if_empty_r\(0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      ififo_rst => ififo_rst,
      \my_empty_reg[3]_0\(1 downto 0) => \my_empty_reg[3]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[120]\ => \not_strict_mode.app_rd_data_reg[120]\,
      \not_strict_mode.app_rd_data_reg[121]\ => \not_strict_mode.app_rd_data_reg[121]\,
      \not_strict_mode.app_rd_data_reg[122]\ => \not_strict_mode.app_rd_data_reg[122]\,
      \not_strict_mode.app_rd_data_reg[123]\ => \not_strict_mode.app_rd_data_reg[123]\,
      \not_strict_mode.app_rd_data_reg[124]\ => \not_strict_mode.app_rd_data_reg[124]\,
      \not_strict_mode.app_rd_data_reg[125]\ => \not_strict_mode.app_rd_data_reg[125]\,
      \not_strict_mode.app_rd_data_reg[126]\ => \not_strict_mode.app_rd_data_reg[126]\,
      \not_strict_mode.app_rd_data_reg[127]\ => \not_strict_mode.app_rd_data_reg[127]\,
      \not_strict_mode.app_rd_data_reg[184]\ => \not_strict_mode.app_rd_data_reg[184]\,
      \not_strict_mode.app_rd_data_reg[185]\ => \not_strict_mode.app_rd_data_reg[185]\,
      \not_strict_mode.app_rd_data_reg[186]\ => \not_strict_mode.app_rd_data_reg[186]\,
      \not_strict_mode.app_rd_data_reg[187]\ => \not_strict_mode.app_rd_data_reg[187]\,
      \not_strict_mode.app_rd_data_reg[188]\ => \not_strict_mode.app_rd_data_reg[188]\,
      \not_strict_mode.app_rd_data_reg[189]\ => \not_strict_mode.app_rd_data_reg[189]\,
      \not_strict_mode.app_rd_data_reg[190]\ => \not_strict_mode.app_rd_data_reg[190]\,
      \not_strict_mode.app_rd_data_reg[191]\ => \not_strict_mode.app_rd_data_reg[191]\,
      \not_strict_mode.app_rd_data_reg[248]\ => \not_strict_mode.app_rd_data_reg[248]\,
      \not_strict_mode.app_rd_data_reg[249]\ => \not_strict_mode.app_rd_data_reg[249]\,
      \not_strict_mode.app_rd_data_reg[250]\ => \not_strict_mode.app_rd_data_reg[250]\,
      \not_strict_mode.app_rd_data_reg[251]\ => \not_strict_mode.app_rd_data_reg[251]\,
      \not_strict_mode.app_rd_data_reg[252]\ => \not_strict_mode.app_rd_data_reg[252]\,
      \not_strict_mode.app_rd_data_reg[253]\ => \not_strict_mode.app_rd_data_reg[253]\,
      \not_strict_mode.app_rd_data_reg[254]\ => \not_strict_mode.app_rd_data_reg[254]\,
      \not_strict_mode.app_rd_data_reg[255]\ => \not_strict_mode.app_rd_data_reg[255]\,
      \not_strict_mode.app_rd_data_reg[312]\ => \not_strict_mode.app_rd_data_reg[312]\,
      \not_strict_mode.app_rd_data_reg[313]\ => \not_strict_mode.app_rd_data_reg[313]\,
      \not_strict_mode.app_rd_data_reg[314]\ => \not_strict_mode.app_rd_data_reg[314]\,
      \not_strict_mode.app_rd_data_reg[315]\ => \not_strict_mode.app_rd_data_reg[315]\,
      \not_strict_mode.app_rd_data_reg[316]\ => \not_strict_mode.app_rd_data_reg[316]\,
      \not_strict_mode.app_rd_data_reg[317]\ => \not_strict_mode.app_rd_data_reg[317]\,
      \not_strict_mode.app_rd_data_reg[318]\ => \not_strict_mode.app_rd_data_reg[318]\,
      \not_strict_mode.app_rd_data_reg[319]\ => \not_strict_mode.app_rd_data_reg[319]\,
      \not_strict_mode.app_rd_data_reg[376]\ => \not_strict_mode.app_rd_data_reg[376]\,
      \not_strict_mode.app_rd_data_reg[377]\ => \not_strict_mode.app_rd_data_reg[377]\,
      \not_strict_mode.app_rd_data_reg[378]\ => \not_strict_mode.app_rd_data_reg[378]\,
      \not_strict_mode.app_rd_data_reg[379]\ => \not_strict_mode.app_rd_data_reg[379]\,
      \not_strict_mode.app_rd_data_reg[380]\ => \not_strict_mode.app_rd_data_reg[380]\,
      \not_strict_mode.app_rd_data_reg[381]\ => \not_strict_mode.app_rd_data_reg[381]\,
      \not_strict_mode.app_rd_data_reg[382]\ => \not_strict_mode.app_rd_data_reg[382]\,
      \not_strict_mode.app_rd_data_reg[383]\ => \not_strict_mode.app_rd_data_reg[383]\,
      \not_strict_mode.app_rd_data_reg[440]\ => \not_strict_mode.app_rd_data_reg[440]\,
      \not_strict_mode.app_rd_data_reg[441]\ => \not_strict_mode.app_rd_data_reg[441]\,
      \not_strict_mode.app_rd_data_reg[442]\ => \not_strict_mode.app_rd_data_reg[442]\,
      \not_strict_mode.app_rd_data_reg[443]\ => \not_strict_mode.app_rd_data_reg[443]\,
      \not_strict_mode.app_rd_data_reg[444]\ => \not_strict_mode.app_rd_data_reg[444]\,
      \not_strict_mode.app_rd_data_reg[445]\ => \not_strict_mode.app_rd_data_reg[445]\,
      \not_strict_mode.app_rd_data_reg[446]\ => \not_strict_mode.app_rd_data_reg[446]\,
      \not_strict_mode.app_rd_data_reg[447]\ => \not_strict_mode.app_rd_data_reg[447]\,
      \not_strict_mode.app_rd_data_reg[504]\ => \not_strict_mode.app_rd_data_reg[504]\,
      \not_strict_mode.app_rd_data_reg[505]\ => \not_strict_mode.app_rd_data_reg[505]\,
      \not_strict_mode.app_rd_data_reg[506]\ => \not_strict_mode.app_rd_data_reg[506]\,
      \not_strict_mode.app_rd_data_reg[507]\ => \not_strict_mode.app_rd_data_reg[507]\,
      \not_strict_mode.app_rd_data_reg[508]\ => \not_strict_mode.app_rd_data_reg[508]\,
      \not_strict_mode.app_rd_data_reg[509]\ => \not_strict_mode.app_rd_data_reg[509]\,
      \not_strict_mode.app_rd_data_reg[510]\ => \not_strict_mode.app_rd_data_reg[510]\,
      \not_strict_mode.app_rd_data_reg[511]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[511]\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[511]_0\ => \not_strict_mode.app_rd_data_reg[511]_0\,
      \not_strict_mode.app_rd_data_reg[56]\ => \not_strict_mode.app_rd_data_reg[56]\,
      \not_strict_mode.app_rd_data_reg[57]\ => \not_strict_mode.app_rd_data_reg[57]\,
      \not_strict_mode.app_rd_data_reg[58]\ => \not_strict_mode.app_rd_data_reg[58]\,
      \not_strict_mode.app_rd_data_reg[59]\ => \not_strict_mode.app_rd_data_reg[59]\,
      \not_strict_mode.app_rd_data_reg[60]\ => \not_strict_mode.app_rd_data_reg[60]\,
      \not_strict_mode.app_rd_data_reg[61]\ => \not_strict_mode.app_rd_data_reg[61]\,
      \not_strict_mode.app_rd_data_reg[62]\ => \not_strict_mode.app_rd_data_reg[62]\,
      \not_strict_mode.app_rd_data_reg[63]\ => \not_strict_mode.app_rd_data_reg[63]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \po_stg2_wrcal_cnt_reg[1]\(1 downto 0) => \po_stg2_wrcal_cnt_reg[1]\(1 downto 0),
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_2\,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => A_if_a_empty,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => B"0000",
      D9(3 downto 0) => B"0000",
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_9\
     port map (
      A_of_full => A_of_full,
      CLK => CLK,
      D0(2) => of_d0(5),
      D0(1 downto 0) => of_d0(1 downto 0),
      D1(2 downto 1) => of_d1(4 downto 3),
      D1(0) => of_d1(1),
      D2(1) => of_d2(4),
      D2(0) => of_d2(2),
      D3(1) => of_d3(7),
      D3(0) => of_d3(0),
      D4(2) => of_d4(5),
      D4(1 downto 0) => of_d4(1 downto 0),
      D5(2 downto 1) => of_d5(4 downto 3),
      D5(0) => of_d5(1),
      D6(1) => of_d6(4),
      D6(0) => of_d6(2),
      D7(1) => of_d7(7),
      D7(0) => of_d7(0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => of_d9(7 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__8\ => \init_calib_complete_reg_rep__8\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      \write_buffer.wr_buf_out_data_reg[575]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofifo_rst_reg0_11,
      Q => ofifo_rst,
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => A_of_a_full,
      D0(7 downto 6) => \write_buffer.wr_buf_out_data_reg[511]\(4 downto 3),
      D0(5) => of_d0(5),
      D0(4 downto 2) => \write_buffer.wr_buf_out_data_reg[511]\(2 downto 0),
      D0(1 downto 0) => of_d0(1 downto 0),
      D1(7 downto 5) => \write_buffer.wr_buf_out_data_reg[510]\(4 downto 2),
      D1(4 downto 3) => of_d1(4 downto 3),
      D1(2) => \write_buffer.wr_buf_out_data_reg[510]\(1),
      D1(1) => of_d1(1),
      D1(0) => \write_buffer.wr_buf_out_data_reg[510]\(0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[509]\(5 downto 3),
      D2(4) => of_d2(4),
      D2(3) => \write_buffer.wr_buf_out_data_reg[509]\(2),
      D2(2) => of_d2(2),
      D2(1 downto 0) => \write_buffer.wr_buf_out_data_reg[509]\(1 downto 0),
      D3(7) => of_d3(7),
      D3(6 downto 1) => \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0),
      D3(0) => of_d3(0),
      D4(7 downto 6) => \write_buffer.wr_buf_out_data_reg[507]\(4 downto 3),
      D4(5) => of_d4(5),
      D4(4 downto 2) => \write_buffer.wr_buf_out_data_reg[507]\(2 downto 0),
      D4(1 downto 0) => of_d4(1 downto 0),
      D5(7 downto 5) => \write_buffer.wr_buf_out_data_reg[506]\(4 downto 2),
      D5(4 downto 3) => of_d5(4 downto 3),
      D5(2) => \write_buffer.wr_buf_out_data_reg[506]\(1),
      D5(1) => of_d5(1),
      D5(0) => \write_buffer.wr_buf_out_data_reg[506]\(0),
      D6(7 downto 5) => \write_buffer.wr_buf_out_data_reg[505]\(5 downto 3),
      D6(4) => of_d6(4),
      D6(3) => \write_buffer.wr_buf_out_data_reg[505]\(2),
      D6(2) => of_d6(2),
      D6(1 downto 0) => \write_buffer.wr_buf_out_data_reg[505]\(1 downto 0),
      D7(7) => of_d7(7),
      D7(6 downto 1) => \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0),
      D7(0) => of_d7(0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => of_d9(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => A_of_full,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \calib_sel_reg[1]_0\,
      COUNTERLOADVAL(5 downto 0) => \calib_sel_reg[1]_3\(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => A_pi_dqs_out_of_range,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => A_pi_fine_overflow,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => pi_phase_locked_all_r1_reg,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives_reg,
      RSTDQSFIND => \calib_sel_reg[1]_2\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \calib_sel_reg[1]_4\,
      COARSEINC => \calib_sel_reg[1]_4\,
      COARSEOVERFLOW => A_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[1]_5\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => A_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_byte_lane_16 is
  port (
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_0 : out STD_LOGIC;
    rst_r4 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[24]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[26]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[28]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[30]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[88]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[90]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[92]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[94]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[152]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[154]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[156]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[158]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[216]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[218]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[220]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[222]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[280]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[282]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[284]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[286]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[344]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[346]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[348]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[350]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[408]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[410]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[412]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[414]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[472]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[474]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[476]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[478]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]_0\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \rd_ptr_reg[0]\ : out STD_LOGIC;
    \rd_ptr_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[0]_2\ : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_6 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[479]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[478]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[477]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[412]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[475]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[474]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[473]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[408]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_if_reset : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[571]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \po_stg2_wrcal_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_7\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_8\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_9\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_10\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_11\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_12\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_13\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_14\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_15\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_16\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_17\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_18\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_19\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_20\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_21\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_22\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_23\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_24\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_25\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_26\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_27\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_28\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_29\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_30\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_31\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_32\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_33\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_34\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_35\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_36\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_37\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_38\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_39\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_40\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_41\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_42\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_43\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_44\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_45\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_46\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_47\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_48\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_49\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_50\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_51\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_52\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_53\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_54\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_55\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_56\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_57\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_58\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_59\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_60\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_61\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_62\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ : in STD_LOGIC;
    byte_rd_en_v_1 : in STD_LOGIC;
    byte_rd_en_v_2 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_byte_lane_16 : entity is "mig_7series_v2_3_ddr_byte_lane";
end mig_7series_0_mig_7series_v2_3_ddr_byte_lane_16;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_byte_lane_16 is
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d1 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d3 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d4 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d6 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d7 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 65 downto 0 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_28
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0_7 => CLKB0_7,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_6 => LD0_6,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 32) => of_dqbus(39 downto 36),
      of_dqbus(31 downto 0) => of_dqbus(31 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_3 => out_dqs_3,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_3 => ts_dqs_3
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(0),
      Q => rd_data_r(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(1),
      Q => rd_data_r(1),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(2),
      Q => rd_data_r(2),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(3),
      Q => rd_data_r(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(4),
      Q => rd_data_r(4),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(5),
      Q => rd_data_r(5),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_29
     port map (
      CLK => CLK,
      Q(1 downto 0) => Q(1 downto 0),
      SR(0) => ififo_rst,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \^if_empty_r\(0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\(65 downto 0) => rd_data_r(65 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \not_strict_mode.app_rd_data_reg[152]\ => \not_strict_mode.app_rd_data_reg[152]\,
      \not_strict_mode.app_rd_data_reg[153]\ => \not_strict_mode.app_rd_data_reg[153]\,
      \not_strict_mode.app_rd_data_reg[154]\ => \not_strict_mode.app_rd_data_reg[154]\,
      \not_strict_mode.app_rd_data_reg[155]\ => \not_strict_mode.app_rd_data_reg[155]\,
      \not_strict_mode.app_rd_data_reg[156]\ => \not_strict_mode.app_rd_data_reg[156]\,
      \not_strict_mode.app_rd_data_reg[157]\ => \not_strict_mode.app_rd_data_reg[157]\,
      \not_strict_mode.app_rd_data_reg[158]\ => \not_strict_mode.app_rd_data_reg[158]\,
      \not_strict_mode.app_rd_data_reg[159]\ => \not_strict_mode.app_rd_data_reg[159]\,
      \not_strict_mode.app_rd_data_reg[216]\ => \not_strict_mode.app_rd_data_reg[216]\,
      \not_strict_mode.app_rd_data_reg[217]\ => \not_strict_mode.app_rd_data_reg[217]\,
      \not_strict_mode.app_rd_data_reg[218]\ => \not_strict_mode.app_rd_data_reg[218]\,
      \not_strict_mode.app_rd_data_reg[219]\ => \not_strict_mode.app_rd_data_reg[219]\,
      \not_strict_mode.app_rd_data_reg[220]\ => \not_strict_mode.app_rd_data_reg[220]\,
      \not_strict_mode.app_rd_data_reg[221]\ => \not_strict_mode.app_rd_data_reg[221]\,
      \not_strict_mode.app_rd_data_reg[222]\ => \not_strict_mode.app_rd_data_reg[222]\,
      \not_strict_mode.app_rd_data_reg[223]\ => \not_strict_mode.app_rd_data_reg[223]\,
      \not_strict_mode.app_rd_data_reg[24]\ => \not_strict_mode.app_rd_data_reg[24]\,
      \not_strict_mode.app_rd_data_reg[25]\ => \not_strict_mode.app_rd_data_reg[25]\,
      \not_strict_mode.app_rd_data_reg[26]\ => \not_strict_mode.app_rd_data_reg[26]\,
      \not_strict_mode.app_rd_data_reg[27]\ => \not_strict_mode.app_rd_data_reg[27]\,
      \not_strict_mode.app_rd_data_reg[280]\ => \not_strict_mode.app_rd_data_reg[280]\,
      \not_strict_mode.app_rd_data_reg[281]\ => \not_strict_mode.app_rd_data_reg[281]\,
      \not_strict_mode.app_rd_data_reg[282]\ => \not_strict_mode.app_rd_data_reg[282]\,
      \not_strict_mode.app_rd_data_reg[283]\ => \not_strict_mode.app_rd_data_reg[283]\,
      \not_strict_mode.app_rd_data_reg[284]\ => \not_strict_mode.app_rd_data_reg[284]\,
      \not_strict_mode.app_rd_data_reg[285]\ => \not_strict_mode.app_rd_data_reg[285]\,
      \not_strict_mode.app_rd_data_reg[286]\ => \not_strict_mode.app_rd_data_reg[286]\,
      \not_strict_mode.app_rd_data_reg[287]\ => \not_strict_mode.app_rd_data_reg[287]\,
      \not_strict_mode.app_rd_data_reg[28]\ => \not_strict_mode.app_rd_data_reg[28]\,
      \not_strict_mode.app_rd_data_reg[29]\ => \not_strict_mode.app_rd_data_reg[29]\,
      \not_strict_mode.app_rd_data_reg[30]\ => \not_strict_mode.app_rd_data_reg[30]\,
      \not_strict_mode.app_rd_data_reg[31]\ => \not_strict_mode.app_rd_data_reg[31]\,
      \not_strict_mode.app_rd_data_reg[344]\ => \not_strict_mode.app_rd_data_reg[344]\,
      \not_strict_mode.app_rd_data_reg[345]\ => \not_strict_mode.app_rd_data_reg[345]\,
      \not_strict_mode.app_rd_data_reg[346]\ => \not_strict_mode.app_rd_data_reg[346]\,
      \not_strict_mode.app_rd_data_reg[347]\ => \not_strict_mode.app_rd_data_reg[347]\,
      \not_strict_mode.app_rd_data_reg[348]\ => \not_strict_mode.app_rd_data_reg[348]\,
      \not_strict_mode.app_rd_data_reg[349]\ => \not_strict_mode.app_rd_data_reg[349]\,
      \not_strict_mode.app_rd_data_reg[350]\ => \not_strict_mode.app_rd_data_reg[350]\,
      \not_strict_mode.app_rd_data_reg[351]\ => \not_strict_mode.app_rd_data_reg[351]\,
      \not_strict_mode.app_rd_data_reg[408]\ => \not_strict_mode.app_rd_data_reg[408]\,
      \not_strict_mode.app_rd_data_reg[409]\ => \not_strict_mode.app_rd_data_reg[409]\,
      \not_strict_mode.app_rd_data_reg[410]\ => \not_strict_mode.app_rd_data_reg[410]\,
      \not_strict_mode.app_rd_data_reg[411]\ => \not_strict_mode.app_rd_data_reg[411]\,
      \not_strict_mode.app_rd_data_reg[412]\ => \not_strict_mode.app_rd_data_reg[412]\,
      \not_strict_mode.app_rd_data_reg[413]\ => \not_strict_mode.app_rd_data_reg[413]\,
      \not_strict_mode.app_rd_data_reg[414]\ => \not_strict_mode.app_rd_data_reg[414]\,
      \not_strict_mode.app_rd_data_reg[415]\ => \not_strict_mode.app_rd_data_reg[415]\,
      \not_strict_mode.app_rd_data_reg[472]\ => \not_strict_mode.app_rd_data_reg[472]\,
      \not_strict_mode.app_rd_data_reg[473]\ => \not_strict_mode.app_rd_data_reg[473]\,
      \not_strict_mode.app_rd_data_reg[474]\ => \not_strict_mode.app_rd_data_reg[474]\,
      \not_strict_mode.app_rd_data_reg[475]\ => \not_strict_mode.app_rd_data_reg[475]\,
      \not_strict_mode.app_rd_data_reg[476]\ => \not_strict_mode.app_rd_data_reg[476]\,
      \not_strict_mode.app_rd_data_reg[477]\ => \not_strict_mode.app_rd_data_reg[477]\,
      \not_strict_mode.app_rd_data_reg[478]\ => \not_strict_mode.app_rd_data_reg[478]\,
      \not_strict_mode.app_rd_data_reg[479]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[479]\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[479]_0\ => \not_strict_mode.app_rd_data_reg[479]_0\,
      \not_strict_mode.app_rd_data_reg[88]\ => \not_strict_mode.app_rd_data_reg[88]\,
      \not_strict_mode.app_rd_data_reg[89]\ => \not_strict_mode.app_rd_data_reg[89]\,
      \not_strict_mode.app_rd_data_reg[90]\ => \not_strict_mode.app_rd_data_reg[90]\,
      \not_strict_mode.app_rd_data_reg[91]\ => \not_strict_mode.app_rd_data_reg[91]\,
      \not_strict_mode.app_rd_data_reg[92]\ => \not_strict_mode.app_rd_data_reg[92]\,
      \not_strict_mode.app_rd_data_reg[93]\ => \not_strict_mode.app_rd_data_reg[93]\,
      \not_strict_mode.app_rd_data_reg[94]\ => \not_strict_mode.app_rd_data_reg[94]\,
      \not_strict_mode.app_rd_data_reg[95]\ => \not_strict_mode.app_rd_data_reg[95]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      p_0_out => p_0_out,
      \po_stg2_wrcal_cnt_reg[1]\ => \po_stg2_wrcal_cnt_reg[1]\,
      \po_stg2_wrcal_cnt_reg[1]_0\ => \po_stg2_wrcal_cnt_reg[1]_0\,
      \po_stg2_wrcal_cnt_reg[1]_1\ => \po_stg2_wrcal_cnt_reg[1]_1\,
      \po_stg2_wrcal_cnt_reg[1]_10\ => \po_stg2_wrcal_cnt_reg[1]_10\,
      \po_stg2_wrcal_cnt_reg[1]_11\ => \po_stg2_wrcal_cnt_reg[1]_11\,
      \po_stg2_wrcal_cnt_reg[1]_12\ => \po_stg2_wrcal_cnt_reg[1]_12\,
      \po_stg2_wrcal_cnt_reg[1]_13\ => \po_stg2_wrcal_cnt_reg[1]_13\,
      \po_stg2_wrcal_cnt_reg[1]_14\ => \po_stg2_wrcal_cnt_reg[1]_14\,
      \po_stg2_wrcal_cnt_reg[1]_15\ => \po_stg2_wrcal_cnt_reg[1]_15\,
      \po_stg2_wrcal_cnt_reg[1]_16\ => \po_stg2_wrcal_cnt_reg[1]_16\,
      \po_stg2_wrcal_cnt_reg[1]_17\ => \po_stg2_wrcal_cnt_reg[1]_17\,
      \po_stg2_wrcal_cnt_reg[1]_18\ => \po_stg2_wrcal_cnt_reg[1]_18\,
      \po_stg2_wrcal_cnt_reg[1]_19\ => \po_stg2_wrcal_cnt_reg[1]_19\,
      \po_stg2_wrcal_cnt_reg[1]_2\ => \po_stg2_wrcal_cnt_reg[1]_2\,
      \po_stg2_wrcal_cnt_reg[1]_20\ => \po_stg2_wrcal_cnt_reg[1]_20\,
      \po_stg2_wrcal_cnt_reg[1]_21\ => \po_stg2_wrcal_cnt_reg[1]_21\,
      \po_stg2_wrcal_cnt_reg[1]_22\ => \po_stg2_wrcal_cnt_reg[1]_22\,
      \po_stg2_wrcal_cnt_reg[1]_23\ => \po_stg2_wrcal_cnt_reg[1]_23\,
      \po_stg2_wrcal_cnt_reg[1]_24\ => \po_stg2_wrcal_cnt_reg[1]_24\,
      \po_stg2_wrcal_cnt_reg[1]_25\ => \po_stg2_wrcal_cnt_reg[1]_25\,
      \po_stg2_wrcal_cnt_reg[1]_26\ => \po_stg2_wrcal_cnt_reg[1]_26\,
      \po_stg2_wrcal_cnt_reg[1]_27\ => \po_stg2_wrcal_cnt_reg[1]_27\,
      \po_stg2_wrcal_cnt_reg[1]_28\ => \po_stg2_wrcal_cnt_reg[1]_28\,
      \po_stg2_wrcal_cnt_reg[1]_29\ => \po_stg2_wrcal_cnt_reg[1]_29\,
      \po_stg2_wrcal_cnt_reg[1]_3\ => \po_stg2_wrcal_cnt_reg[1]_3\,
      \po_stg2_wrcal_cnt_reg[1]_30\ => \po_stg2_wrcal_cnt_reg[1]_30\,
      \po_stg2_wrcal_cnt_reg[1]_31\ => \po_stg2_wrcal_cnt_reg[1]_31\,
      \po_stg2_wrcal_cnt_reg[1]_32\ => \po_stg2_wrcal_cnt_reg[1]_32\,
      \po_stg2_wrcal_cnt_reg[1]_33\ => \po_stg2_wrcal_cnt_reg[1]_33\,
      \po_stg2_wrcal_cnt_reg[1]_34\ => \po_stg2_wrcal_cnt_reg[1]_34\,
      \po_stg2_wrcal_cnt_reg[1]_35\ => \po_stg2_wrcal_cnt_reg[1]_35\,
      \po_stg2_wrcal_cnt_reg[1]_36\ => \po_stg2_wrcal_cnt_reg[1]_36\,
      \po_stg2_wrcal_cnt_reg[1]_37\ => \po_stg2_wrcal_cnt_reg[1]_37\,
      \po_stg2_wrcal_cnt_reg[1]_38\ => \po_stg2_wrcal_cnt_reg[1]_38\,
      \po_stg2_wrcal_cnt_reg[1]_39\ => \po_stg2_wrcal_cnt_reg[1]_39\,
      \po_stg2_wrcal_cnt_reg[1]_4\ => \po_stg2_wrcal_cnt_reg[1]_4\,
      \po_stg2_wrcal_cnt_reg[1]_40\ => \po_stg2_wrcal_cnt_reg[1]_40\,
      \po_stg2_wrcal_cnt_reg[1]_41\ => \po_stg2_wrcal_cnt_reg[1]_41\,
      \po_stg2_wrcal_cnt_reg[1]_42\ => \po_stg2_wrcal_cnt_reg[1]_42\,
      \po_stg2_wrcal_cnt_reg[1]_43\ => \po_stg2_wrcal_cnt_reg[1]_43\,
      \po_stg2_wrcal_cnt_reg[1]_44\ => \po_stg2_wrcal_cnt_reg[1]_44\,
      \po_stg2_wrcal_cnt_reg[1]_45\ => \po_stg2_wrcal_cnt_reg[1]_45\,
      \po_stg2_wrcal_cnt_reg[1]_46\ => \po_stg2_wrcal_cnt_reg[1]_46\,
      \po_stg2_wrcal_cnt_reg[1]_47\ => \po_stg2_wrcal_cnt_reg[1]_47\,
      \po_stg2_wrcal_cnt_reg[1]_48\ => \po_stg2_wrcal_cnt_reg[1]_48\,
      \po_stg2_wrcal_cnt_reg[1]_49\ => \po_stg2_wrcal_cnt_reg[1]_49\,
      \po_stg2_wrcal_cnt_reg[1]_5\ => \po_stg2_wrcal_cnt_reg[1]_5\,
      \po_stg2_wrcal_cnt_reg[1]_50\ => \po_stg2_wrcal_cnt_reg[1]_50\,
      \po_stg2_wrcal_cnt_reg[1]_51\ => \po_stg2_wrcal_cnt_reg[1]_51\,
      \po_stg2_wrcal_cnt_reg[1]_52\ => \po_stg2_wrcal_cnt_reg[1]_52\,
      \po_stg2_wrcal_cnt_reg[1]_53\ => \po_stg2_wrcal_cnt_reg[1]_53\,
      \po_stg2_wrcal_cnt_reg[1]_54\ => \po_stg2_wrcal_cnt_reg[1]_54\,
      \po_stg2_wrcal_cnt_reg[1]_55\ => \po_stg2_wrcal_cnt_reg[1]_55\,
      \po_stg2_wrcal_cnt_reg[1]_56\ => \po_stg2_wrcal_cnt_reg[1]_56\,
      \po_stg2_wrcal_cnt_reg[1]_57\ => \po_stg2_wrcal_cnt_reg[1]_57\,
      \po_stg2_wrcal_cnt_reg[1]_58\ => \po_stg2_wrcal_cnt_reg[1]_58\,
      \po_stg2_wrcal_cnt_reg[1]_59\ => \po_stg2_wrcal_cnt_reg[1]_59\,
      \po_stg2_wrcal_cnt_reg[1]_6\ => \po_stg2_wrcal_cnt_reg[1]_6\,
      \po_stg2_wrcal_cnt_reg[1]_60\ => \po_stg2_wrcal_cnt_reg[1]_60\,
      \po_stg2_wrcal_cnt_reg[1]_61\ => \po_stg2_wrcal_cnt_reg[1]_61\,
      \po_stg2_wrcal_cnt_reg[1]_62\ => \po_stg2_wrcal_cnt_reg[1]_62\,
      \po_stg2_wrcal_cnt_reg[1]_7\ => \po_stg2_wrcal_cnt_reg[1]_7\,
      \po_stg2_wrcal_cnt_reg[1]_8\ => \po_stg2_wrcal_cnt_reg[1]_8\,
      \po_stg2_wrcal_cnt_reg[1]_9\ => \po_stg2_wrcal_cnt_reg[1]_9\,
      \po_stg2_wrcal_cnt_reg[2]\(2 downto 0) => \po_stg2_wrcal_cnt_reg[2]\(2 downto 0),
      \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\,
      \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_0\,
      \rd_ptr_reg[0]_2\ => \rd_ptr_reg[0]_1\,
      \rd_ptr_reg[0]_3\ => \rd_ptr_reg[0]_2\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_2\,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => B"0000",
      D9(3 downto 0) => B"0000",
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_30\
     port map (
      CLK => CLK,
      D0(2) => of_d0(5),
      D0(1 downto 0) => of_d0(1 downto 0),
      D1(2 downto 1) => of_d1(4 downto 3),
      D1(0) => of_d1(1),
      D2(1) => of_d2(4),
      D2(0) => of_d2(2),
      D3(1) => of_d3(7),
      D3(0) => of_d3(0),
      D4(2) => of_d4(5),
      D4(1 downto 0) => of_d4(1 downto 0),
      D5(2 downto 1) => of_d5(4 downto 3),
      D5(0) => of_d5(1),
      D6(1) => of_d6(4),
      D6(0) => of_d6(2),
      D7(1) => of_d7(7),
      D7(0) => of_d7(0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => of_d9(7 downto 0),
      \entry_cnt_reg[4]_0\(2 downto 0) => \entry_cnt_reg[4]\(2 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      ofifo_rst_reg => out_fifo_n_3,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      \write_buffer.wr_buf_out_data_reg[571]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[571]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_2\,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7 downto 6) => \write_buffer.wr_buf_out_data_reg[479]\(4 downto 3),
      D0(5) => of_d0(5),
      D0(4 downto 2) => \write_buffer.wr_buf_out_data_reg[479]\(2 downto 0),
      D0(1 downto 0) => of_d0(1 downto 0),
      D1(7 downto 5) => \write_buffer.wr_buf_out_data_reg[478]\(4 downto 2),
      D1(4 downto 3) => of_d1(4 downto 3),
      D1(2) => \write_buffer.wr_buf_out_data_reg[478]\(1),
      D1(1) => of_d1(1),
      D1(0) => \write_buffer.wr_buf_out_data_reg[478]\(0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[477]\(5 downto 3),
      D2(4) => of_d2(4),
      D2(3) => \write_buffer.wr_buf_out_data_reg[477]\(2),
      D2(2) => of_d2(2),
      D2(1 downto 0) => \write_buffer.wr_buf_out_data_reg[477]\(1 downto 0),
      D3(7) => of_d3(7),
      D3(6 downto 1) => \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0),
      D3(0) => of_d3(0),
      D4(7 downto 6) => \write_buffer.wr_buf_out_data_reg[475]\(4 downto 3),
      D4(5) => of_d4(5),
      D4(4 downto 2) => \write_buffer.wr_buf_out_data_reg[475]\(2 downto 0),
      D4(1 downto 0) => of_d4(1 downto 0),
      D5(7 downto 5) => \write_buffer.wr_buf_out_data_reg[474]\(4 downto 2),
      D5(4 downto 3) => of_d5(4 downto 3),
      D5(2) => \write_buffer.wr_buf_out_data_reg[474]\(1),
      D5(1) => of_d5(1),
      D5(0) => \write_buffer.wr_buf_out_data_reg[474]\(0),
      D6(7 downto 5) => \write_buffer.wr_buf_out_data_reg[473]\(5 downto 3),
      D6(4) => of_d6(4),
      D6(3) => \write_buffer.wr_buf_out_data_reg[473]\(2),
      D6(2) => of_d6(2),
      D6(1 downto 0) => \write_buffer.wr_buf_out_data_reg[473]\(1 downto 0),
      D7(7) => of_d7(7),
      D7(6 downto 1) => \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0),
      D7(0) => of_d7(0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => of_d9(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \calib_sel_reg[1]_0\,
      COUNTERLOADVAL(5 downto 0) => \calib_sel_reg[1]_3\(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => pi_phase_locked_all_r1_reg,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => \calib_sel_reg[1]_2\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \calib_sel_reg[1]_4\,
      COARSEINC => \calib_sel_reg[1]_4\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[1]_5\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0\ is
  port (
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    B_rclk : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[48]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[50]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[52]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[54]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[112]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[114]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[116]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[118]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[176]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[178]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[180]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[182]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[240]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[242]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[244]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[246]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[304]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[306]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[308]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[310]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[368]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[370]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[372]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[374]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[432]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[434]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[436]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[438]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[496]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[498]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[500]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[502]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]_0\ : out STD_LOGIC;
    B_byte_rd_en : out STD_LOGIC;
    ofs_rdy_r_reg : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    CLK : in STD_LOGIC;
    idelay_ce_r2_reg : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pi_stg2_load_reg : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pi_rst_stg1_cal_reg[2]\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_stg2_reg_l_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg : in STD_LOGIC;
    \calib_sel_reg[0]_0\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[503]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[502]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[501]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[436]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[499]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[498]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[497]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[432]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_13 : in STD_LOGIC;
    phy_if_reset : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \my_empty_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[574]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0\ is
  signal B_if_a_empty : STD_LOGIC;
  signal B_of_a_full : STD_LOGIC;
  signal B_of_full : STD_LOGIC;
  signal B_pi_dqs_out_of_range : STD_LOGIC;
  signal B_pi_fine_overflow : STD_LOGIC;
  signal B_po_coarse_overflow : STD_LOGIC;
  signal B_po_fine_overflow : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d3 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d7 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d8 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 6 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0\
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0_12 => CLKB0_12,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_12 => LD0_12,
      idelay_ce_r2_reg => idelay_ce_r2_reg,
      idelay_inc => idelay_inc,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_6 => out_dqs_6,
      po_oserdes_rst => po_oserdes_rst,
      ts_dqs_6 => ts_dqs_6
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_6
     port map (
      B_byte_rd_en => B_byte_rd_en,
      CLK => CLK,
      Q(67 downto 36) => rd_data_r(79 downto 48),
      Q(35 downto 0) => rd_data_r(41 downto 6),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^if_empty_r\(0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      if_empty_r_0(0) => if_empty_r_0(0),
      ififo_rst => ififo_rst,
      \my_empty_reg[0]_0\(0) => \my_empty_reg[3]\(0),
      \my_empty_reg[3]_0\ => \my_empty_reg[3]\(1),
      \my_empty_reg[3]_1\(0) => \my_empty_reg[3]_0\(0),
      \not_strict_mode.app_rd_data_reg[112]\ => \not_strict_mode.app_rd_data_reg[112]\,
      \not_strict_mode.app_rd_data_reg[113]\ => \not_strict_mode.app_rd_data_reg[113]\,
      \not_strict_mode.app_rd_data_reg[114]\ => \not_strict_mode.app_rd_data_reg[114]\,
      \not_strict_mode.app_rd_data_reg[115]\ => \not_strict_mode.app_rd_data_reg[115]\,
      \not_strict_mode.app_rd_data_reg[116]\ => \not_strict_mode.app_rd_data_reg[116]\,
      \not_strict_mode.app_rd_data_reg[117]\ => \not_strict_mode.app_rd_data_reg[117]\,
      \not_strict_mode.app_rd_data_reg[118]\ => \not_strict_mode.app_rd_data_reg[118]\,
      \not_strict_mode.app_rd_data_reg[119]\ => \not_strict_mode.app_rd_data_reg[119]\,
      \not_strict_mode.app_rd_data_reg[176]\ => \not_strict_mode.app_rd_data_reg[176]\,
      \not_strict_mode.app_rd_data_reg[177]\ => \not_strict_mode.app_rd_data_reg[177]\,
      \not_strict_mode.app_rd_data_reg[178]\ => \not_strict_mode.app_rd_data_reg[178]\,
      \not_strict_mode.app_rd_data_reg[179]\ => \not_strict_mode.app_rd_data_reg[179]\,
      \not_strict_mode.app_rd_data_reg[180]\ => \not_strict_mode.app_rd_data_reg[180]\,
      \not_strict_mode.app_rd_data_reg[181]\ => \not_strict_mode.app_rd_data_reg[181]\,
      \not_strict_mode.app_rd_data_reg[182]\ => \not_strict_mode.app_rd_data_reg[182]\,
      \not_strict_mode.app_rd_data_reg[183]\ => \not_strict_mode.app_rd_data_reg[183]\,
      \not_strict_mode.app_rd_data_reg[240]\ => \not_strict_mode.app_rd_data_reg[240]\,
      \not_strict_mode.app_rd_data_reg[241]\ => \not_strict_mode.app_rd_data_reg[241]\,
      \not_strict_mode.app_rd_data_reg[242]\ => \not_strict_mode.app_rd_data_reg[242]\,
      \not_strict_mode.app_rd_data_reg[243]\ => \not_strict_mode.app_rd_data_reg[243]\,
      \not_strict_mode.app_rd_data_reg[244]\ => \not_strict_mode.app_rd_data_reg[244]\,
      \not_strict_mode.app_rd_data_reg[245]\ => \not_strict_mode.app_rd_data_reg[245]\,
      \not_strict_mode.app_rd_data_reg[246]\ => \not_strict_mode.app_rd_data_reg[246]\,
      \not_strict_mode.app_rd_data_reg[247]\ => \not_strict_mode.app_rd_data_reg[247]\,
      \not_strict_mode.app_rd_data_reg[304]\ => \not_strict_mode.app_rd_data_reg[304]\,
      \not_strict_mode.app_rd_data_reg[305]\ => \not_strict_mode.app_rd_data_reg[305]\,
      \not_strict_mode.app_rd_data_reg[306]\ => \not_strict_mode.app_rd_data_reg[306]\,
      \not_strict_mode.app_rd_data_reg[307]\ => \not_strict_mode.app_rd_data_reg[307]\,
      \not_strict_mode.app_rd_data_reg[308]\ => \not_strict_mode.app_rd_data_reg[308]\,
      \not_strict_mode.app_rd_data_reg[309]\ => \not_strict_mode.app_rd_data_reg[309]\,
      \not_strict_mode.app_rd_data_reg[310]\ => \not_strict_mode.app_rd_data_reg[310]\,
      \not_strict_mode.app_rd_data_reg[311]\ => \not_strict_mode.app_rd_data_reg[311]\,
      \not_strict_mode.app_rd_data_reg[368]\ => \not_strict_mode.app_rd_data_reg[368]\,
      \not_strict_mode.app_rd_data_reg[369]\ => \not_strict_mode.app_rd_data_reg[369]\,
      \not_strict_mode.app_rd_data_reg[370]\ => \not_strict_mode.app_rd_data_reg[370]\,
      \not_strict_mode.app_rd_data_reg[371]\ => \not_strict_mode.app_rd_data_reg[371]\,
      \not_strict_mode.app_rd_data_reg[372]\ => \not_strict_mode.app_rd_data_reg[372]\,
      \not_strict_mode.app_rd_data_reg[373]\ => \not_strict_mode.app_rd_data_reg[373]\,
      \not_strict_mode.app_rd_data_reg[374]\ => \not_strict_mode.app_rd_data_reg[374]\,
      \not_strict_mode.app_rd_data_reg[375]\ => \not_strict_mode.app_rd_data_reg[375]\,
      \not_strict_mode.app_rd_data_reg[432]\ => \not_strict_mode.app_rd_data_reg[432]\,
      \not_strict_mode.app_rd_data_reg[433]\ => \not_strict_mode.app_rd_data_reg[433]\,
      \not_strict_mode.app_rd_data_reg[434]\ => \not_strict_mode.app_rd_data_reg[434]\,
      \not_strict_mode.app_rd_data_reg[435]\ => \not_strict_mode.app_rd_data_reg[435]\,
      \not_strict_mode.app_rd_data_reg[436]\ => \not_strict_mode.app_rd_data_reg[436]\,
      \not_strict_mode.app_rd_data_reg[437]\ => \not_strict_mode.app_rd_data_reg[437]\,
      \not_strict_mode.app_rd_data_reg[438]\ => \not_strict_mode.app_rd_data_reg[438]\,
      \not_strict_mode.app_rd_data_reg[439]\ => \not_strict_mode.app_rd_data_reg[439]\,
      \not_strict_mode.app_rd_data_reg[48]\ => \not_strict_mode.app_rd_data_reg[48]\,
      \not_strict_mode.app_rd_data_reg[496]\ => \not_strict_mode.app_rd_data_reg[496]\,
      \not_strict_mode.app_rd_data_reg[497]\ => \not_strict_mode.app_rd_data_reg[497]\,
      \not_strict_mode.app_rd_data_reg[498]\ => \not_strict_mode.app_rd_data_reg[498]\,
      \not_strict_mode.app_rd_data_reg[499]\ => \not_strict_mode.app_rd_data_reg[499]\,
      \not_strict_mode.app_rd_data_reg[49]\ => \not_strict_mode.app_rd_data_reg[49]\,
      \not_strict_mode.app_rd_data_reg[500]\ => \not_strict_mode.app_rd_data_reg[500]\,
      \not_strict_mode.app_rd_data_reg[501]\ => \not_strict_mode.app_rd_data_reg[501]\,
      \not_strict_mode.app_rd_data_reg[502]\ => \not_strict_mode.app_rd_data_reg[502]\,
      \not_strict_mode.app_rd_data_reg[503]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[503]\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[503]_0\ => \not_strict_mode.app_rd_data_reg[503]_0\,
      \not_strict_mode.app_rd_data_reg[50]\ => \not_strict_mode.app_rd_data_reg[50]\,
      \not_strict_mode.app_rd_data_reg[51]\ => \not_strict_mode.app_rd_data_reg[51]\,
      \not_strict_mode.app_rd_data_reg[52]\ => \not_strict_mode.app_rd_data_reg[52]\,
      \not_strict_mode.app_rd_data_reg[53]\ => \not_strict_mode.app_rd_data_reg[53]\,
      \not_strict_mode.app_rd_data_reg[54]\ => \not_strict_mode.app_rd_data_reg[54]\,
      \not_strict_mode.app_rd_data_reg[55]\ => \not_strict_mode.app_rd_data_reg[55]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \rd_ptr_timing_reg[0]_0\ => \rd_ptr_timing_reg[0]\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_reg[2]\,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => B_if_a_empty,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => B"0000",
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_7\
     port map (
      B_of_full => B_of_full,
      CLK => CLK,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(2) => of_d1(5),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(2 downto 1) => of_d2(4 downto 3),
      D2(0) => of_d2(1),
      D3(1) => of_d3(4),
      D3(0) => of_d3(2),
      D4(1) => of_d4(7),
      D4(0) => of_d4(0),
      D5(7 downto 0) => of_d5(7 downto 0),
      D6(2) => of_d6(5),
      D6(1 downto 0) => of_d6(1 downto 0),
      D7(2 downto 1) => of_d7(4 downto 3),
      D7(0) => of_d7(1),
      D8(1) => of_d8(4),
      D8(0) => of_d8(2),
      D9(1) => of_d9(7),
      D9(0) => of_d9(0),
      Q(2 downto 0) => Q(2 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      ofs_rdy_r_reg => ofs_rdy_r_reg,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      \write_buffer.wr_buf_out_data_reg[574]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[574]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofifo_rst_reg0_13,
      Q => ofifo_rst,
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => B_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 6) => \write_buffer.wr_buf_out_data_reg[503]\(4 downto 3),
      D1(5) => of_d1(5),
      D1(4 downto 2) => \write_buffer.wr_buf_out_data_reg[503]\(2 downto 0),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[502]\(4 downto 2),
      D2(4 downto 3) => of_d2(4 downto 3),
      D2(2) => \write_buffer.wr_buf_out_data_reg[502]\(1),
      D2(1) => of_d2(1),
      D2(0) => \write_buffer.wr_buf_out_data_reg[502]\(0),
      D3(7 downto 5) => \write_buffer.wr_buf_out_data_reg[501]\(5 downto 3),
      D3(4) => of_d3(4),
      D3(3) => \write_buffer.wr_buf_out_data_reg[501]\(2),
      D3(2) => of_d3(2),
      D3(1 downto 0) => \write_buffer.wr_buf_out_data_reg[501]\(1 downto 0),
      D4(7) => of_d4(7),
      D4(6 downto 1) => \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0),
      D4(0) => of_d4(0),
      D5(7 downto 0) => of_d5(7 downto 0),
      D6(7 downto 6) => \write_buffer.wr_buf_out_data_reg[499]\(4 downto 3),
      D6(5) => of_d6(5),
      D6(4 downto 2) => \write_buffer.wr_buf_out_data_reg[499]\(2 downto 0),
      D6(1 downto 0) => of_d6(1 downto 0),
      D7(7 downto 5) => \write_buffer.wr_buf_out_data_reg[498]\(4 downto 2),
      D7(4 downto 3) => of_d7(4 downto 3),
      D7(2) => \write_buffer.wr_buf_out_data_reg[498]\(1),
      D7(1) => of_d7(1),
      D7(0) => \write_buffer.wr_buf_out_data_reg[498]\(0),
      D8(7 downto 5) => \write_buffer.wr_buf_out_data_reg[497]\(5 downto 3),
      D8(4) => of_d8(4),
      D8(3) => \write_buffer.wr_buf_out_data_reg[497]\(2),
      D8(2) => of_d8(2),
      D8(1 downto 0) => \write_buffer.wr_buf_out_data_reg[497]\(1 downto 0),
      D9(7) => of_d9(7),
      D9(6 downto 1) => \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0),
      D9(0) => of_d9(0),
      EMPTY => out_fifo_n_2,
      FULL => B_of_full,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => pi_stg2_load_reg,
      COUNTERLOADVAL(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[0]\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => B_pi_dqs_out_of_range,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => B_pi_fine_overflow,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => pi_phase_locked_all_r1_reg,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => B_rclk,
      RST => A_rst_primitives_reg,
      RSTDQSFIND => \pi_rst_stg1_cal_reg[2]\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => dqs_wl_po_stg2_c_incdec_reg,
      COARSEINC => dqs_wl_po_stg2_c_incdec_reg,
      COARSEOVERFLOW => B_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[0]\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[0]_0\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => B_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0_17\ is
  port (
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    B_rclk : out STD_LOGIC;
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_1 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[16]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[18]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[20]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[22]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[80]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[82]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[84]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[86]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[144]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[146]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[148]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[150]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[208]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[210]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[212]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[214]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[272]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[274]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[276]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[278]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[336]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[338]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[340]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[342]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[400]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[402]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[404]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[406]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[464]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[466]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[468]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[470]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[471]_0\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    \rd_ptr_reg[1]_0\ : out STD_LOGIC;
    byte_rd_en_v_0 : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC;
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[471]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[470]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[469]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[404]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[467]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[466]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[465]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[400]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_if_reset : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[570]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    byte_rd_en_v_1 : in STD_LOGIC;
    byte_rd_en_v_2 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : in STD_LOGIC;
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 );
    COUNTERREADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    A_rst_primitives_reg_1 : in STD_LOGIC;
    A_rst_primitives_reg_2 : in STD_LOGIC;
    A_rst_primitives_reg_3 : in STD_LOGIC;
    A_rst_primitives_reg_4 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    A_rst_primitives_reg_5 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    A_rst_primitives_reg_6 : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0_17\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0_17\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0_17\ is
  signal B_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d3 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d7 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d8 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_6\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 79 downto 6 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized0_25\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0_8 => CLKB0_8,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_7 => LD0_7,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_2 => out_dqs_2,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_2 => ts_dqs_2
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(72),
      Q => rd_data_r(72),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(73),
      Q => rd_data_r(73),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(74),
      Q => rd_data_r(74),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(75),
      Q => rd_data_r(75),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(76),
      Q => rd_data_r(76),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(77),
      Q => rd_data_r(77),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(78),
      Q => rd_data_r(78),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(79),
      Q => rd_data_r(79),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_26
     port map (
      CLK => CLK,
      Q(0) => Q(0),
      SR(0) => ififo_rst,
      byte_rd_en_v_0 => byte_rd_en_v_0,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \^if_empty_r\(0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(67 downto 36) => rd_data_r(79 downto 48),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(35 downto 0) => rd_data_r(41 downto 6),
      if_empty_r_0(0) => if_empty_r_0(0),
      \my_empty_reg[3]_0\(0) => \my_empty_reg[3]\(0),
      \not_strict_mode.app_rd_data_reg[144]\ => \not_strict_mode.app_rd_data_reg[144]\,
      \not_strict_mode.app_rd_data_reg[145]\ => \not_strict_mode.app_rd_data_reg[145]\,
      \not_strict_mode.app_rd_data_reg[146]\ => \not_strict_mode.app_rd_data_reg[146]\,
      \not_strict_mode.app_rd_data_reg[147]\ => \not_strict_mode.app_rd_data_reg[147]\,
      \not_strict_mode.app_rd_data_reg[148]\ => \not_strict_mode.app_rd_data_reg[148]\,
      \not_strict_mode.app_rd_data_reg[149]\ => \not_strict_mode.app_rd_data_reg[149]\,
      \not_strict_mode.app_rd_data_reg[150]\ => \not_strict_mode.app_rd_data_reg[150]\,
      \not_strict_mode.app_rd_data_reg[151]\ => \not_strict_mode.app_rd_data_reg[151]\,
      \not_strict_mode.app_rd_data_reg[16]\ => \not_strict_mode.app_rd_data_reg[16]\,
      \not_strict_mode.app_rd_data_reg[17]\ => \not_strict_mode.app_rd_data_reg[17]\,
      \not_strict_mode.app_rd_data_reg[18]\ => \not_strict_mode.app_rd_data_reg[18]\,
      \not_strict_mode.app_rd_data_reg[19]\ => \not_strict_mode.app_rd_data_reg[19]\,
      \not_strict_mode.app_rd_data_reg[208]\ => \not_strict_mode.app_rd_data_reg[208]\,
      \not_strict_mode.app_rd_data_reg[209]\ => \not_strict_mode.app_rd_data_reg[209]\,
      \not_strict_mode.app_rd_data_reg[20]\ => \not_strict_mode.app_rd_data_reg[20]\,
      \not_strict_mode.app_rd_data_reg[210]\ => \not_strict_mode.app_rd_data_reg[210]\,
      \not_strict_mode.app_rd_data_reg[211]\ => \not_strict_mode.app_rd_data_reg[211]\,
      \not_strict_mode.app_rd_data_reg[212]\ => \not_strict_mode.app_rd_data_reg[212]\,
      \not_strict_mode.app_rd_data_reg[213]\ => \not_strict_mode.app_rd_data_reg[213]\,
      \not_strict_mode.app_rd_data_reg[214]\ => \not_strict_mode.app_rd_data_reg[214]\,
      \not_strict_mode.app_rd_data_reg[215]\ => \not_strict_mode.app_rd_data_reg[215]\,
      \not_strict_mode.app_rd_data_reg[21]\ => \not_strict_mode.app_rd_data_reg[21]\,
      \not_strict_mode.app_rd_data_reg[22]\ => \not_strict_mode.app_rd_data_reg[22]\,
      \not_strict_mode.app_rd_data_reg[23]\ => \not_strict_mode.app_rd_data_reg[23]\,
      \not_strict_mode.app_rd_data_reg[272]\ => \not_strict_mode.app_rd_data_reg[272]\,
      \not_strict_mode.app_rd_data_reg[273]\ => \not_strict_mode.app_rd_data_reg[273]\,
      \not_strict_mode.app_rd_data_reg[274]\ => \not_strict_mode.app_rd_data_reg[274]\,
      \not_strict_mode.app_rd_data_reg[275]\ => \not_strict_mode.app_rd_data_reg[275]\,
      \not_strict_mode.app_rd_data_reg[276]\ => \not_strict_mode.app_rd_data_reg[276]\,
      \not_strict_mode.app_rd_data_reg[277]\ => \not_strict_mode.app_rd_data_reg[277]\,
      \not_strict_mode.app_rd_data_reg[278]\ => \not_strict_mode.app_rd_data_reg[278]\,
      \not_strict_mode.app_rd_data_reg[279]\ => \not_strict_mode.app_rd_data_reg[279]\,
      \not_strict_mode.app_rd_data_reg[336]\ => \not_strict_mode.app_rd_data_reg[336]\,
      \not_strict_mode.app_rd_data_reg[337]\ => \not_strict_mode.app_rd_data_reg[337]\,
      \not_strict_mode.app_rd_data_reg[338]\ => \not_strict_mode.app_rd_data_reg[338]\,
      \not_strict_mode.app_rd_data_reg[339]\ => \not_strict_mode.app_rd_data_reg[339]\,
      \not_strict_mode.app_rd_data_reg[340]\ => \not_strict_mode.app_rd_data_reg[340]\,
      \not_strict_mode.app_rd_data_reg[341]\ => \not_strict_mode.app_rd_data_reg[341]\,
      \not_strict_mode.app_rd_data_reg[342]\ => \not_strict_mode.app_rd_data_reg[342]\,
      \not_strict_mode.app_rd_data_reg[343]\ => \not_strict_mode.app_rd_data_reg[343]\,
      \not_strict_mode.app_rd_data_reg[400]\ => \not_strict_mode.app_rd_data_reg[400]\,
      \not_strict_mode.app_rd_data_reg[401]\ => \not_strict_mode.app_rd_data_reg[401]\,
      \not_strict_mode.app_rd_data_reg[402]\ => \not_strict_mode.app_rd_data_reg[402]\,
      \not_strict_mode.app_rd_data_reg[403]\ => \not_strict_mode.app_rd_data_reg[403]\,
      \not_strict_mode.app_rd_data_reg[404]\ => \not_strict_mode.app_rd_data_reg[404]\,
      \not_strict_mode.app_rd_data_reg[405]\ => \not_strict_mode.app_rd_data_reg[405]\,
      \not_strict_mode.app_rd_data_reg[406]\ => \not_strict_mode.app_rd_data_reg[406]\,
      \not_strict_mode.app_rd_data_reg[407]\ => \not_strict_mode.app_rd_data_reg[407]\,
      \not_strict_mode.app_rd_data_reg[464]\ => \not_strict_mode.app_rd_data_reg[464]\,
      \not_strict_mode.app_rd_data_reg[465]\ => \not_strict_mode.app_rd_data_reg[465]\,
      \not_strict_mode.app_rd_data_reg[466]\ => \not_strict_mode.app_rd_data_reg[466]\,
      \not_strict_mode.app_rd_data_reg[467]\ => \not_strict_mode.app_rd_data_reg[467]\,
      \not_strict_mode.app_rd_data_reg[468]\ => \not_strict_mode.app_rd_data_reg[468]\,
      \not_strict_mode.app_rd_data_reg[469]\ => \not_strict_mode.app_rd_data_reg[469]\,
      \not_strict_mode.app_rd_data_reg[470]\ => \not_strict_mode.app_rd_data_reg[470]\,
      \not_strict_mode.app_rd_data_reg[471]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[471]\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[471]_0\ => \not_strict_mode.app_rd_data_reg[471]_0\,
      \not_strict_mode.app_rd_data_reg[80]\ => \not_strict_mode.app_rd_data_reg[80]\,
      \not_strict_mode.app_rd_data_reg[81]\ => \not_strict_mode.app_rd_data_reg[81]\,
      \not_strict_mode.app_rd_data_reg[82]\ => \not_strict_mode.app_rd_data_reg[82]\,
      \not_strict_mode.app_rd_data_reg[83]\ => \not_strict_mode.app_rd_data_reg[83]\,
      \not_strict_mode.app_rd_data_reg[84]\ => \not_strict_mode.app_rd_data_reg[84]\,
      \not_strict_mode.app_rd_data_reg[85]\ => \not_strict_mode.app_rd_data_reg[85]\,
      \not_strict_mode.app_rd_data_reg[86]\ => \not_strict_mode.app_rd_data_reg[86]\,
      \not_strict_mode.app_rd_data_reg[87]\ => \not_strict_mode.app_rd_data_reg[87]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\,
      \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_0\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_1\,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => B"0000",
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => if_d9(3 downto 0),
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_27\
     port map (
      CLK => CLK,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(2) => of_d1(5),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(2 downto 1) => of_d2(4 downto 3),
      D2(0) => of_d2(1),
      D3(1) => of_d3(4),
      D3(0) => of_d3(2),
      D4(1) => of_d4(7),
      D4(0) => of_d4(0),
      D5(7 downto 0) => of_d5(7 downto 0),
      D6(2) => of_d6(5),
      D6(1 downto 0) => of_d6(1 downto 0),
      D7(2 downto 1) => of_d7(4 downto 3),
      D7(0) => of_d7(1),
      D8(1) => of_d8(4),
      D8(0) => of_d8(2),
      D9(1) => of_d9(7),
      D9(0) => of_d9(0),
      \entry_cnt_reg[4]_0\(2 downto 0) => \entry_cnt_reg[4]\(2 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      ofifo_rst_reg => out_fifo_n_3,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      \write_buffer.wr_buf_out_data_reg[570]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[570]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_1\,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 6) => \write_buffer.wr_buf_out_data_reg[471]\(4 downto 3),
      D1(5) => of_d1(5),
      D1(4 downto 2) => \write_buffer.wr_buf_out_data_reg[471]\(2 downto 0),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[470]\(4 downto 2),
      D2(4 downto 3) => of_d2(4 downto 3),
      D2(2) => \write_buffer.wr_buf_out_data_reg[470]\(1),
      D2(1) => of_d2(1),
      D2(0) => \write_buffer.wr_buf_out_data_reg[470]\(0),
      D3(7 downto 5) => \write_buffer.wr_buf_out_data_reg[469]\(5 downto 3),
      D3(4) => of_d3(4),
      D3(3) => \write_buffer.wr_buf_out_data_reg[469]\(2),
      D3(2) => of_d3(2),
      D3(1 downto 0) => \write_buffer.wr_buf_out_data_reg[469]\(1 downto 0),
      D4(7) => of_d4(7),
      D4(6 downto 1) => \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0),
      D4(0) => of_d4(0),
      D5(7 downto 0) => of_d5(7 downto 0),
      D6(7 downto 6) => \write_buffer.wr_buf_out_data_reg[467]\(4 downto 3),
      D6(5) => of_d6(5),
      D6(4 downto 2) => \write_buffer.wr_buf_out_data_reg[467]\(2 downto 0),
      D6(1 downto 0) => of_d6(1 downto 0),
      D7(7 downto 5) => \write_buffer.wr_buf_out_data_reg[466]\(4 downto 2),
      D7(4 downto 3) => of_d7(4 downto 3),
      D7(2) => \write_buffer.wr_buf_out_data_reg[466]\(1),
      D7(1) => of_d7(1),
      D7(0) => \write_buffer.wr_buf_out_data_reg[466]\(0),
      D8(7 downto 5) => \write_buffer.wr_buf_out_data_reg[465]\(5 downto 3),
      D8(4) => of_d8(4),
      D8(3) => \write_buffer.wr_buf_out_data_reg[465]\(2),
      D8(2) => of_d8(2),
      D8(1 downto 0) => \write_buffer.wr_buf_out_data_reg[465]\(1 downto 0),
      D9(7) => of_d9(7),
      D9(6 downto 1) => \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0),
      D9(0) => of_d9(0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \calib_sel_reg[1]_0\,
      COUNTERLOADVAL(5 downto 0) => \calib_sel_reg[1]_2\(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[0]\,
      COUNTERREADVAL(5 downto 0) => B_pi_counter_read_val(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => \phaser_in_gen.phaser_in_n_6\,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => B_rclk,
      RST => A_rst_primitives,
      RSTDQSFIND => \calib_sel_reg[1]_1\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \calib_sel_reg[1]_3\,
      COARSEINC => \calib_sel_reg[1]_3\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[0]\,
      COUNTERREADVAL(8 downto 0) => B_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[1]_4\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
\pi_counter_read_val[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(0),
      I1 => COUNTERREADVAL(0),
      I2 => A_rst_primitives_reg(0),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_0(0),
      O => D(0)
    );
\pi_counter_read_val[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(1),
      I1 => COUNTERREADVAL(1),
      I2 => A_rst_primitives_reg(1),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_0(1),
      O => D(1)
    );
\pi_counter_read_val[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(2),
      I1 => COUNTERREADVAL(2),
      I2 => A_rst_primitives_reg(2),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_0(2),
      O => D(2)
    );
\pi_counter_read_val[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(3),
      I1 => COUNTERREADVAL(3),
      I2 => A_rst_primitives_reg(3),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_0(3),
      O => D(3)
    );
\pi_counter_read_val[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(4),
      I1 => COUNTERREADVAL(4),
      I2 => A_rst_primitives_reg(4),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_0(4),
      O => D(4)
    );
\pi_counter_read_val[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_pi_counter_read_val(5),
      I1 => COUNTERREADVAL(5),
      I2 => A_rst_primitives_reg(5),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_0(5),
      O => D(5)
    );
pi_phase_locked_all_inferred_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \phaser_in_gen.phaser_in_n_6\,
      I1 => A_rst_primitives_reg_1,
      I2 => A_rst_primitives_reg_2,
      I3 => A_rst_primitives_reg_3,
      O => pi_phase_locked_all_r1_reg
    );
\po_counter_read_val[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(0),
      I1 => A_rst_primitives_reg_4(0),
      I2 => A_rst_primitives_reg_5(0),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(0),
      O => \po_counter_read_val_reg[8]\(0)
    );
\po_counter_read_val[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(1),
      I1 => A_rst_primitives_reg_4(1),
      I2 => A_rst_primitives_reg_5(1),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(1),
      O => \po_counter_read_val_reg[8]\(1)
    );
\po_counter_read_val[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(2),
      I1 => A_rst_primitives_reg_4(2),
      I2 => A_rst_primitives_reg_5(2),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(2),
      O => \po_counter_read_val_reg[8]\(2)
    );
\po_counter_read_val[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(3),
      I1 => A_rst_primitives_reg_4(3),
      I2 => A_rst_primitives_reg_5(3),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(3),
      O => \po_counter_read_val_reg[8]\(3)
    );
\po_counter_read_val[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(4),
      I1 => A_rst_primitives_reg_4(4),
      I2 => A_rst_primitives_reg_5(4),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(4),
      O => \po_counter_read_val_reg[8]\(4)
    );
\po_counter_read_val[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(5),
      I1 => A_rst_primitives_reg_4(5),
      I2 => A_rst_primitives_reg_5(5),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(5),
      O => \po_counter_read_val_reg[8]\(5)
    );
\po_counter_read_val[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(6),
      I1 => A_rst_primitives_reg_4(6),
      I2 => A_rst_primitives_reg_5(6),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(6),
      O => \po_counter_read_val_reg[8]\(6)
    );
\po_counter_read_val[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(7),
      I1 => A_rst_primitives_reg_4(7),
      I2 => A_rst_primitives_reg_5(7),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(7),
      O => \po_counter_read_val_reg[8]\(7)
    );
\po_counter_read_val[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(8),
      I1 => A_rst_primitives_reg_4(8),
      I2 => A_rst_primitives_reg_5(8),
      I3 => \calib_sel_reg[1]_5\(1),
      I4 => \calib_sel_reg[1]_5\(0),
      I5 => A_rst_primitives_reg_6(8),
      O => \po_counter_read_val_reg[8]\(8)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1\ is
  port (
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[42]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[44]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[46]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[104]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[106]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[108]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[110]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[168]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[170]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[172]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[174]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[232]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[234]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[236]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[238]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[296]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[298]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[300]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[302]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[360]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[362]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[364]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[366]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[424]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[426]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[428]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[430]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[488]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[490]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[492]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[494]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    if_empty_or_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    byte_rd_en_v_2 : out STD_LOGIC;
    C_byte_rd_en : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_14 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[495]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[494]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[493]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[428]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[491]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[490]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[489]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[424]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_15 : in STD_LOGIC;
    phy_if_reset : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \my_empty_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[573]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_0\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_1\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_2\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_3\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_4\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_5\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_6\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_7\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_8\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_9\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_10\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_11\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_12\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_13\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_14\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_15\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_16\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_17\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_18\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_19\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_20\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_21\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_22\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_23\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_24\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_25\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_26\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_27\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_28\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_29\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_30\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_31\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_32\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_33\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_34\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_35\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_36\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_37\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_38\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_39\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_40\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_41\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_42\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_43\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_44\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_45\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_46\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_47\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_48\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_49\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_50\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_51\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_52\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_53\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_54\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_55\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_56\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_57\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_58\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_59\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_60\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_61\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_62\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_63\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : in STD_LOGIC;
    A_rst_primitives_reg_1 : in STD_LOGIC;
    A_rst_primitives_reg_2 : in STD_LOGIC;
    A_rst_primitives_reg_3 : in STD_LOGIC;
    pre_data_a_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    \entry_cnt_reg[2]\ : in STD_LOGIC;
    \entry_cnt_reg[2]_0\ : in STD_LOGIC;
    \entry_cnt_reg[2]_1\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1\ is
  signal C_if_a_empty : STD_LOGIC;
  signal C_of_a_full : STD_LOGIC;
  signal C_of_full : STD_LOGIC;
  signal C_pi_dqs_out_of_range : STD_LOGIC;
  signal C_pi_fine_overflow : STD_LOGIC;
  signal C_po_coarse_overflow : STD_LOGIC;
  signal C_po_fine_overflow : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal if_empty_r_1 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d3 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d7 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d8 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_6\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 71 downto 6 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1\
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0_13 => CLKB0_13,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_14 => LD0_14,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      idelay_inc => idelay_inc,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_5 => out_dqs_5,
      po_oserdes_rst => po_oserdes_rst,
      ts_dqs_5 => ts_dqs_5
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => if_empty_r_1(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo
     port map (
      CLK => CLK,
      C_byte_rd_en => C_byte_rd_en,
      Q(65 downto 0) => rd_data_r(71 downto 6),
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      if_empty_or_v(0) => if_empty_or_v(0),
      if_empty_r(0) => if_empty_r(0),
      if_empty_r_0(0) => if_empty_r_0(0),
      if_empty_r_1(0) => if_empty_r_1(3),
      ififo_rst => ififo_rst,
      \my_empty_reg[3]_0\(1 downto 0) => \my_empty_reg[3]\(1 downto 0),
      \my_empty_reg[3]_1\(1 downto 0) => \my_empty_reg[3]_0\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[104]\ => \not_strict_mode.app_rd_data_reg[104]\,
      \not_strict_mode.app_rd_data_reg[105]\ => \not_strict_mode.app_rd_data_reg[105]\,
      \not_strict_mode.app_rd_data_reg[106]\ => \not_strict_mode.app_rd_data_reg[106]\,
      \not_strict_mode.app_rd_data_reg[107]\ => \not_strict_mode.app_rd_data_reg[107]\,
      \not_strict_mode.app_rd_data_reg[108]\ => \not_strict_mode.app_rd_data_reg[108]\,
      \not_strict_mode.app_rd_data_reg[109]\ => \not_strict_mode.app_rd_data_reg[109]\,
      \not_strict_mode.app_rd_data_reg[110]\ => \not_strict_mode.app_rd_data_reg[110]\,
      \not_strict_mode.app_rd_data_reg[111]\ => \not_strict_mode.app_rd_data_reg[111]\,
      \not_strict_mode.app_rd_data_reg[168]\ => \not_strict_mode.app_rd_data_reg[168]\,
      \not_strict_mode.app_rd_data_reg[169]\ => \not_strict_mode.app_rd_data_reg[169]\,
      \not_strict_mode.app_rd_data_reg[170]\ => \not_strict_mode.app_rd_data_reg[170]\,
      \not_strict_mode.app_rd_data_reg[171]\ => \not_strict_mode.app_rd_data_reg[171]\,
      \not_strict_mode.app_rd_data_reg[172]\ => \not_strict_mode.app_rd_data_reg[172]\,
      \not_strict_mode.app_rd_data_reg[173]\ => \not_strict_mode.app_rd_data_reg[173]\,
      \not_strict_mode.app_rd_data_reg[174]\ => \not_strict_mode.app_rd_data_reg[174]\,
      \not_strict_mode.app_rd_data_reg[175]\ => \not_strict_mode.app_rd_data_reg[175]\,
      \not_strict_mode.app_rd_data_reg[232]\ => \not_strict_mode.app_rd_data_reg[232]\,
      \not_strict_mode.app_rd_data_reg[233]\ => \not_strict_mode.app_rd_data_reg[233]\,
      \not_strict_mode.app_rd_data_reg[234]\ => \not_strict_mode.app_rd_data_reg[234]\,
      \not_strict_mode.app_rd_data_reg[235]\ => \not_strict_mode.app_rd_data_reg[235]\,
      \not_strict_mode.app_rd_data_reg[236]\ => \not_strict_mode.app_rd_data_reg[236]\,
      \not_strict_mode.app_rd_data_reg[237]\ => \not_strict_mode.app_rd_data_reg[237]\,
      \not_strict_mode.app_rd_data_reg[238]\ => \not_strict_mode.app_rd_data_reg[238]\,
      \not_strict_mode.app_rd_data_reg[239]\ => \not_strict_mode.app_rd_data_reg[239]\,
      \not_strict_mode.app_rd_data_reg[296]\ => \not_strict_mode.app_rd_data_reg[296]\,
      \not_strict_mode.app_rd_data_reg[297]\ => \not_strict_mode.app_rd_data_reg[297]\,
      \not_strict_mode.app_rd_data_reg[298]\ => \not_strict_mode.app_rd_data_reg[298]\,
      \not_strict_mode.app_rd_data_reg[299]\ => \not_strict_mode.app_rd_data_reg[299]\,
      \not_strict_mode.app_rd_data_reg[300]\ => \not_strict_mode.app_rd_data_reg[300]\,
      \not_strict_mode.app_rd_data_reg[301]\ => \not_strict_mode.app_rd_data_reg[301]\,
      \not_strict_mode.app_rd_data_reg[302]\ => \not_strict_mode.app_rd_data_reg[302]\,
      \not_strict_mode.app_rd_data_reg[303]\ => \not_strict_mode.app_rd_data_reg[303]\,
      \not_strict_mode.app_rd_data_reg[360]\ => \not_strict_mode.app_rd_data_reg[360]\,
      \not_strict_mode.app_rd_data_reg[361]\ => \not_strict_mode.app_rd_data_reg[361]\,
      \not_strict_mode.app_rd_data_reg[362]\ => \not_strict_mode.app_rd_data_reg[362]\,
      \not_strict_mode.app_rd_data_reg[363]\ => \not_strict_mode.app_rd_data_reg[363]\,
      \not_strict_mode.app_rd_data_reg[364]\ => \not_strict_mode.app_rd_data_reg[364]\,
      \not_strict_mode.app_rd_data_reg[365]\ => \not_strict_mode.app_rd_data_reg[365]\,
      \not_strict_mode.app_rd_data_reg[366]\ => \not_strict_mode.app_rd_data_reg[366]\,
      \not_strict_mode.app_rd_data_reg[367]\ => \not_strict_mode.app_rd_data_reg[367]\,
      \not_strict_mode.app_rd_data_reg[40]\ => \not_strict_mode.app_rd_data_reg[40]\,
      \not_strict_mode.app_rd_data_reg[41]\ => \not_strict_mode.app_rd_data_reg[41]\,
      \not_strict_mode.app_rd_data_reg[424]\ => \not_strict_mode.app_rd_data_reg[424]\,
      \not_strict_mode.app_rd_data_reg[425]\ => \not_strict_mode.app_rd_data_reg[425]\,
      \not_strict_mode.app_rd_data_reg[426]\ => \not_strict_mode.app_rd_data_reg[426]\,
      \not_strict_mode.app_rd_data_reg[427]\ => \not_strict_mode.app_rd_data_reg[427]\,
      \not_strict_mode.app_rd_data_reg[428]\ => \not_strict_mode.app_rd_data_reg[428]\,
      \not_strict_mode.app_rd_data_reg[429]\ => \not_strict_mode.app_rd_data_reg[429]\,
      \not_strict_mode.app_rd_data_reg[42]\ => \not_strict_mode.app_rd_data_reg[42]\,
      \not_strict_mode.app_rd_data_reg[430]\ => \not_strict_mode.app_rd_data_reg[430]\,
      \not_strict_mode.app_rd_data_reg[431]\ => \not_strict_mode.app_rd_data_reg[431]\,
      \not_strict_mode.app_rd_data_reg[43]\ => \not_strict_mode.app_rd_data_reg[43]\,
      \not_strict_mode.app_rd_data_reg[44]\ => \not_strict_mode.app_rd_data_reg[44]\,
      \not_strict_mode.app_rd_data_reg[45]\ => \not_strict_mode.app_rd_data_reg[45]\,
      \not_strict_mode.app_rd_data_reg[46]\ => \not_strict_mode.app_rd_data_reg[46]\,
      \not_strict_mode.app_rd_data_reg[47]\ => \not_strict_mode.app_rd_data_reg[47]\,
      \not_strict_mode.app_rd_data_reg[488]\ => \not_strict_mode.app_rd_data_reg[488]\,
      \not_strict_mode.app_rd_data_reg[489]\ => \not_strict_mode.app_rd_data_reg[489]\,
      \not_strict_mode.app_rd_data_reg[490]\ => \not_strict_mode.app_rd_data_reg[490]\,
      \not_strict_mode.app_rd_data_reg[491]\ => \not_strict_mode.app_rd_data_reg[491]\,
      \not_strict_mode.app_rd_data_reg[492]\ => \not_strict_mode.app_rd_data_reg[492]\,
      \not_strict_mode.app_rd_data_reg[493]\ => \not_strict_mode.app_rd_data_reg[493]\,
      \not_strict_mode.app_rd_data_reg[494]\ => \not_strict_mode.app_rd_data_reg[494]\,
      \not_strict_mode.app_rd_data_reg[495]\ => \not_strict_mode.app_rd_data_reg[495]\,
      \not_strict_mode.app_rd_data_reg[495]_0\(63 downto 0) => \not_strict_mode.app_rd_data_reg[495]_0\(63 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \rd_mux_sel_r_reg[1]\(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      \rd_mux_sel_r_reg[1]_0\ => \rd_mux_sel_r_reg[1]_0\,
      \rd_mux_sel_r_reg[1]_1\ => \rd_mux_sel_r_reg[1]_1\,
      \rd_mux_sel_r_reg[1]_10\ => \rd_mux_sel_r_reg[1]_10\,
      \rd_mux_sel_r_reg[1]_11\ => \rd_mux_sel_r_reg[1]_11\,
      \rd_mux_sel_r_reg[1]_12\ => \rd_mux_sel_r_reg[1]_12\,
      \rd_mux_sel_r_reg[1]_13\ => \rd_mux_sel_r_reg[1]_13\,
      \rd_mux_sel_r_reg[1]_14\ => \rd_mux_sel_r_reg[1]_14\,
      \rd_mux_sel_r_reg[1]_15\ => \rd_mux_sel_r_reg[1]_15\,
      \rd_mux_sel_r_reg[1]_16\ => \rd_mux_sel_r_reg[1]_16\,
      \rd_mux_sel_r_reg[1]_17\ => \rd_mux_sel_r_reg[1]_17\,
      \rd_mux_sel_r_reg[1]_18\ => \rd_mux_sel_r_reg[1]_18\,
      \rd_mux_sel_r_reg[1]_19\ => \rd_mux_sel_r_reg[1]_19\,
      \rd_mux_sel_r_reg[1]_2\ => \rd_mux_sel_r_reg[1]_2\,
      \rd_mux_sel_r_reg[1]_20\ => \rd_mux_sel_r_reg[1]_20\,
      \rd_mux_sel_r_reg[1]_21\ => \rd_mux_sel_r_reg[1]_21\,
      \rd_mux_sel_r_reg[1]_22\ => \rd_mux_sel_r_reg[1]_22\,
      \rd_mux_sel_r_reg[1]_23\ => \rd_mux_sel_r_reg[1]_23\,
      \rd_mux_sel_r_reg[1]_24\ => \rd_mux_sel_r_reg[1]_24\,
      \rd_mux_sel_r_reg[1]_25\ => \rd_mux_sel_r_reg[1]_25\,
      \rd_mux_sel_r_reg[1]_26\ => \rd_mux_sel_r_reg[1]_26\,
      \rd_mux_sel_r_reg[1]_27\ => \rd_mux_sel_r_reg[1]_27\,
      \rd_mux_sel_r_reg[1]_28\ => \rd_mux_sel_r_reg[1]_28\,
      \rd_mux_sel_r_reg[1]_29\ => \rd_mux_sel_r_reg[1]_29\,
      \rd_mux_sel_r_reg[1]_3\ => \rd_mux_sel_r_reg[1]_3\,
      \rd_mux_sel_r_reg[1]_30\ => \rd_mux_sel_r_reg[1]_30\,
      \rd_mux_sel_r_reg[1]_31\ => \rd_mux_sel_r_reg[1]_31\,
      \rd_mux_sel_r_reg[1]_32\ => \rd_mux_sel_r_reg[1]_32\,
      \rd_mux_sel_r_reg[1]_33\ => \rd_mux_sel_r_reg[1]_33\,
      \rd_mux_sel_r_reg[1]_34\ => \rd_mux_sel_r_reg[1]_34\,
      \rd_mux_sel_r_reg[1]_35\ => \rd_mux_sel_r_reg[1]_35\,
      \rd_mux_sel_r_reg[1]_36\ => \rd_mux_sel_r_reg[1]_36\,
      \rd_mux_sel_r_reg[1]_37\ => \rd_mux_sel_r_reg[1]_37\,
      \rd_mux_sel_r_reg[1]_38\ => \rd_mux_sel_r_reg[1]_38\,
      \rd_mux_sel_r_reg[1]_39\ => \rd_mux_sel_r_reg[1]_39\,
      \rd_mux_sel_r_reg[1]_4\ => \rd_mux_sel_r_reg[1]_4\,
      \rd_mux_sel_r_reg[1]_40\ => \rd_mux_sel_r_reg[1]_40\,
      \rd_mux_sel_r_reg[1]_41\ => \rd_mux_sel_r_reg[1]_41\,
      \rd_mux_sel_r_reg[1]_42\ => \rd_mux_sel_r_reg[1]_42\,
      \rd_mux_sel_r_reg[1]_43\ => \rd_mux_sel_r_reg[1]_43\,
      \rd_mux_sel_r_reg[1]_44\ => \rd_mux_sel_r_reg[1]_44\,
      \rd_mux_sel_r_reg[1]_45\ => \rd_mux_sel_r_reg[1]_45\,
      \rd_mux_sel_r_reg[1]_46\ => \rd_mux_sel_r_reg[1]_46\,
      \rd_mux_sel_r_reg[1]_47\ => \rd_mux_sel_r_reg[1]_47\,
      \rd_mux_sel_r_reg[1]_48\ => \rd_mux_sel_r_reg[1]_48\,
      \rd_mux_sel_r_reg[1]_49\ => \rd_mux_sel_r_reg[1]_49\,
      \rd_mux_sel_r_reg[1]_5\ => \rd_mux_sel_r_reg[1]_5\,
      \rd_mux_sel_r_reg[1]_50\ => \rd_mux_sel_r_reg[1]_50\,
      \rd_mux_sel_r_reg[1]_51\ => \rd_mux_sel_r_reg[1]_51\,
      \rd_mux_sel_r_reg[1]_52\ => \rd_mux_sel_r_reg[1]_52\,
      \rd_mux_sel_r_reg[1]_53\ => \rd_mux_sel_r_reg[1]_53\,
      \rd_mux_sel_r_reg[1]_54\ => \rd_mux_sel_r_reg[1]_54\,
      \rd_mux_sel_r_reg[1]_55\ => \rd_mux_sel_r_reg[1]_55\,
      \rd_mux_sel_r_reg[1]_56\ => \rd_mux_sel_r_reg[1]_56\,
      \rd_mux_sel_r_reg[1]_57\ => \rd_mux_sel_r_reg[1]_57\,
      \rd_mux_sel_r_reg[1]_58\ => \rd_mux_sel_r_reg[1]_58\,
      \rd_mux_sel_r_reg[1]_59\ => \rd_mux_sel_r_reg[1]_59\,
      \rd_mux_sel_r_reg[1]_6\ => \rd_mux_sel_r_reg[1]_6\,
      \rd_mux_sel_r_reg[1]_60\ => \rd_mux_sel_r_reg[1]_60\,
      \rd_mux_sel_r_reg[1]_61\ => \rd_mux_sel_r_reg[1]_61\,
      \rd_mux_sel_r_reg[1]_62\ => \rd_mux_sel_r_reg[1]_62\,
      \rd_mux_sel_r_reg[1]_63\ => \rd_mux_sel_r_reg[1]_63\,
      \rd_mux_sel_r_reg[1]_7\ => \rd_mux_sel_r_reg[1]_7\,
      \rd_mux_sel_r_reg[1]_8\ => \rd_mux_sel_r_reg[1]_8\,
      \rd_mux_sel_r_reg[1]_9\ => \rd_mux_sel_r_reg[1]_9\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_ptr_timing_reg[0]_0\ => \rd_ptr_timing_reg[0]\,
      \rd_ptr_timing_reg[0]_1\ => \rd_ptr_timing_reg[0]_0\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_2\,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => C_if_a_empty,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => B"0000",
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1\
     port map (
      CLK => CLK,
      C_of_full => C_of_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(2) => of_d1(5),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(2 downto 1) => of_d2(4 downto 3),
      D2(0) => of_d2(1),
      D3(1) => of_d3(4),
      D3(0) => of_d3(2),
      D4(1) => of_d4(7),
      D4(0) => of_d4(0),
      D5(2) => of_d5(5),
      D5(1 downto 0) => of_d5(1 downto 0),
      D6(2 downto 1) => of_d6(4 downto 3),
      D6(0) => of_d6(1),
      D7(1) => of_d7(4),
      D7(0) => of_d7(2),
      D8(1) => of_d8(7),
      D8(0) => of_d8(0),
      D9(7 downto 0) => of_d9(7 downto 0),
      \entry_cnt_reg[2]_0\ => \entry_cnt_reg[2]\,
      \entry_cnt_reg[2]_1\ => \entry_cnt_reg[2]_0\,
      \entry_cnt_reg[2]_2\ => \entry_cnt_reg[2]_1\,
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      phy_mc_data_full => phy_mc_data_full,
      pre_data_a_full_v(0) => pre_data_a_full_v(0),
      \write_buffer.wr_buf_out_data_reg[573]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[573]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofifo_rst_reg0_15,
      Q => ofifo_rst,
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => C_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 6) => \write_buffer.wr_buf_out_data_reg[495]\(4 downto 3),
      D1(5) => of_d1(5),
      D1(4 downto 2) => \write_buffer.wr_buf_out_data_reg[495]\(2 downto 0),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[494]\(4 downto 2),
      D2(4 downto 3) => of_d2(4 downto 3),
      D2(2) => \write_buffer.wr_buf_out_data_reg[494]\(1),
      D2(1) => of_d2(1),
      D2(0) => \write_buffer.wr_buf_out_data_reg[494]\(0),
      D3(7 downto 5) => \write_buffer.wr_buf_out_data_reg[493]\(5 downto 3),
      D3(4) => of_d3(4),
      D3(3) => \write_buffer.wr_buf_out_data_reg[493]\(2),
      D3(2) => of_d3(2),
      D3(1 downto 0) => \write_buffer.wr_buf_out_data_reg[493]\(1 downto 0),
      D4(7) => of_d4(7),
      D4(6 downto 1) => \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0),
      D4(0) => of_d4(0),
      D5(7 downto 6) => \write_buffer.wr_buf_out_data_reg[491]\(4 downto 3),
      D5(5) => of_d5(5),
      D5(4 downto 2) => \write_buffer.wr_buf_out_data_reg[491]\(2 downto 0),
      D5(1 downto 0) => of_d5(1 downto 0),
      D6(7 downto 5) => \write_buffer.wr_buf_out_data_reg[490]\(4 downto 2),
      D6(4 downto 3) => of_d6(4 downto 3),
      D6(2) => \write_buffer.wr_buf_out_data_reg[490]\(1),
      D6(1) => of_d6(1),
      D6(0) => \write_buffer.wr_buf_out_data_reg[490]\(0),
      D7(7 downto 5) => \write_buffer.wr_buf_out_data_reg[489]\(5 downto 3),
      D7(4) => of_d7(4),
      D7(3) => \write_buffer.wr_buf_out_data_reg[489]\(2),
      D7(2) => of_d7(2),
      D7(1 downto 0) => \write_buffer.wr_buf_out_data_reg[489]\(1 downto 0),
      D8(7) => of_d8(7),
      D8(6 downto 1) => \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0),
      D8(0) => of_d8(0),
      D9(7 downto 0) => of_d9(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => C_of_full,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \calib_sel_reg[1]_0\,
      COUNTERLOADVAL(5 downto 0) => \calib_sel_reg[1]_3\(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => C_pi_dqs_out_of_range,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => C_pi_fine_overflow,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => \phaser_in_gen.phaser_in_n_6\,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives_reg,
      RSTDQSFIND => \calib_sel_reg[1]_2\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \calib_sel_reg[1]_4\,
      COARSEINC => \calib_sel_reg[1]_4\,
      COARSEOVERFLOW => C_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[1]_5\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => C_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
pi_phase_locked_all_inferred_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => A_rst_primitives_reg_0,
      I1 => \phaser_in_gen.phaser_in_n_6\,
      I2 => A_rst_primitives_reg_1,
      I3 => A_rst_primitives_reg_2,
      I4 => A_rst_primitives_reg_3,
      O => pi_phase_locked_all_r1_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1_18\ is
  port (
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    \pi_counter_read_val_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_2 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[8]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[10]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[12]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[14]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[72]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[74]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[76]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[78]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[136]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[138]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[140]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[142]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[200]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[202]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[204]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[206]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[264]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[266]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[268]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[270]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[328]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[330]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[332]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[334]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[392]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[394]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[396]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[398]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[456]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[458]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[460]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[462]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC;
    rd_active_r_reg : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[463]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[462]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[461]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[396]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[459]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[458]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[457]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[392]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_if_reset : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[569]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1_18\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1_18\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1_18\ is
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d3 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d7 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d8 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 71 downto 6 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
  if_empty_r(0) <= \^if_empty_r\(0);
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_22\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0_9 => CLKB0_9,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_8 => LD0_8,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_1 => out_dqs_1,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_1 => ts_dqs_1
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => \^if_empty_r\(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_23
     port map (
      CLK => CLK,
      Q(0) => Q(0),
      SR(0) => ififo_rst,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \^if_empty_r\(0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\(65 downto 0) => rd_data_r(71 downto 6),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      if_empty_r_0(0) => if_empty_r_0(0),
      \my_empty_reg[0]_0\(0) => \my_empty_reg[0]\(0),
      \not_strict_mode.app_rd_data_reg[10]\ => \not_strict_mode.app_rd_data_reg[10]\,
      \not_strict_mode.app_rd_data_reg[11]\ => \not_strict_mode.app_rd_data_reg[11]\,
      \not_strict_mode.app_rd_data_reg[12]\ => \not_strict_mode.app_rd_data_reg[12]\,
      \not_strict_mode.app_rd_data_reg[136]\ => \not_strict_mode.app_rd_data_reg[136]\,
      \not_strict_mode.app_rd_data_reg[137]\ => \not_strict_mode.app_rd_data_reg[137]\,
      \not_strict_mode.app_rd_data_reg[138]\ => \not_strict_mode.app_rd_data_reg[138]\,
      \not_strict_mode.app_rd_data_reg[139]\ => \not_strict_mode.app_rd_data_reg[139]\,
      \not_strict_mode.app_rd_data_reg[13]\ => \not_strict_mode.app_rd_data_reg[13]\,
      \not_strict_mode.app_rd_data_reg[140]\ => \not_strict_mode.app_rd_data_reg[140]\,
      \not_strict_mode.app_rd_data_reg[141]\ => \not_strict_mode.app_rd_data_reg[141]\,
      \not_strict_mode.app_rd_data_reg[142]\ => \not_strict_mode.app_rd_data_reg[142]\,
      \not_strict_mode.app_rd_data_reg[143]\ => \not_strict_mode.app_rd_data_reg[143]\,
      \not_strict_mode.app_rd_data_reg[14]\ => \not_strict_mode.app_rd_data_reg[14]\,
      \not_strict_mode.app_rd_data_reg[15]\ => \not_strict_mode.app_rd_data_reg[15]\,
      \not_strict_mode.app_rd_data_reg[200]\ => \not_strict_mode.app_rd_data_reg[200]\,
      \not_strict_mode.app_rd_data_reg[201]\ => \not_strict_mode.app_rd_data_reg[201]\,
      \not_strict_mode.app_rd_data_reg[202]\ => \not_strict_mode.app_rd_data_reg[202]\,
      \not_strict_mode.app_rd_data_reg[203]\ => \not_strict_mode.app_rd_data_reg[203]\,
      \not_strict_mode.app_rd_data_reg[204]\ => \not_strict_mode.app_rd_data_reg[204]\,
      \not_strict_mode.app_rd_data_reg[205]\ => \not_strict_mode.app_rd_data_reg[205]\,
      \not_strict_mode.app_rd_data_reg[206]\ => \not_strict_mode.app_rd_data_reg[206]\,
      \not_strict_mode.app_rd_data_reg[207]\ => \not_strict_mode.app_rd_data_reg[207]\,
      \not_strict_mode.app_rd_data_reg[264]\ => \not_strict_mode.app_rd_data_reg[264]\,
      \not_strict_mode.app_rd_data_reg[265]\ => \not_strict_mode.app_rd_data_reg[265]\,
      \not_strict_mode.app_rd_data_reg[266]\ => \not_strict_mode.app_rd_data_reg[266]\,
      \not_strict_mode.app_rd_data_reg[267]\ => \not_strict_mode.app_rd_data_reg[267]\,
      \not_strict_mode.app_rd_data_reg[268]\ => \not_strict_mode.app_rd_data_reg[268]\,
      \not_strict_mode.app_rd_data_reg[269]\ => \not_strict_mode.app_rd_data_reg[269]\,
      \not_strict_mode.app_rd_data_reg[270]\ => \not_strict_mode.app_rd_data_reg[270]\,
      \not_strict_mode.app_rd_data_reg[271]\ => \not_strict_mode.app_rd_data_reg[271]\,
      \not_strict_mode.app_rd_data_reg[328]\ => \not_strict_mode.app_rd_data_reg[328]\,
      \not_strict_mode.app_rd_data_reg[329]\ => \not_strict_mode.app_rd_data_reg[329]\,
      \not_strict_mode.app_rd_data_reg[330]\ => \not_strict_mode.app_rd_data_reg[330]\,
      \not_strict_mode.app_rd_data_reg[331]\ => \not_strict_mode.app_rd_data_reg[331]\,
      \not_strict_mode.app_rd_data_reg[332]\ => \not_strict_mode.app_rd_data_reg[332]\,
      \not_strict_mode.app_rd_data_reg[333]\ => \not_strict_mode.app_rd_data_reg[333]\,
      \not_strict_mode.app_rd_data_reg[334]\ => \not_strict_mode.app_rd_data_reg[334]\,
      \not_strict_mode.app_rd_data_reg[335]\ => \not_strict_mode.app_rd_data_reg[335]\,
      \not_strict_mode.app_rd_data_reg[392]\ => \not_strict_mode.app_rd_data_reg[392]\,
      \not_strict_mode.app_rd_data_reg[393]\ => \not_strict_mode.app_rd_data_reg[393]\,
      \not_strict_mode.app_rd_data_reg[394]\ => \not_strict_mode.app_rd_data_reg[394]\,
      \not_strict_mode.app_rd_data_reg[395]\ => \not_strict_mode.app_rd_data_reg[395]\,
      \not_strict_mode.app_rd_data_reg[396]\ => \not_strict_mode.app_rd_data_reg[396]\,
      \not_strict_mode.app_rd_data_reg[397]\ => \not_strict_mode.app_rd_data_reg[397]\,
      \not_strict_mode.app_rd_data_reg[398]\ => \not_strict_mode.app_rd_data_reg[398]\,
      \not_strict_mode.app_rd_data_reg[399]\ => \not_strict_mode.app_rd_data_reg[399]\,
      \not_strict_mode.app_rd_data_reg[456]\ => \not_strict_mode.app_rd_data_reg[456]\,
      \not_strict_mode.app_rd_data_reg[457]\ => \not_strict_mode.app_rd_data_reg[457]\,
      \not_strict_mode.app_rd_data_reg[458]\ => \not_strict_mode.app_rd_data_reg[458]\,
      \not_strict_mode.app_rd_data_reg[459]\ => \not_strict_mode.app_rd_data_reg[459]\,
      \not_strict_mode.app_rd_data_reg[460]\ => \not_strict_mode.app_rd_data_reg[460]\,
      \not_strict_mode.app_rd_data_reg[461]\ => \not_strict_mode.app_rd_data_reg[461]\,
      \not_strict_mode.app_rd_data_reg[462]\ => \not_strict_mode.app_rd_data_reg[462]\,
      \not_strict_mode.app_rd_data_reg[463]\ => \not_strict_mode.app_rd_data_reg[463]\,
      \not_strict_mode.app_rd_data_reg[463]_0\(63 downto 0) => \not_strict_mode.app_rd_data_reg[463]_0\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[72]\ => \not_strict_mode.app_rd_data_reg[72]\,
      \not_strict_mode.app_rd_data_reg[73]\ => \not_strict_mode.app_rd_data_reg[73]\,
      \not_strict_mode.app_rd_data_reg[74]\ => \not_strict_mode.app_rd_data_reg[74]\,
      \not_strict_mode.app_rd_data_reg[75]\ => \not_strict_mode.app_rd_data_reg[75]\,
      \not_strict_mode.app_rd_data_reg[76]\ => \not_strict_mode.app_rd_data_reg[76]\,
      \not_strict_mode.app_rd_data_reg[77]\ => \not_strict_mode.app_rd_data_reg[77]\,
      \not_strict_mode.app_rd_data_reg[78]\ => \not_strict_mode.app_rd_data_reg[78]\,
      \not_strict_mode.app_rd_data_reg[79]\ => \not_strict_mode.app_rd_data_reg[79]\,
      \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\,
      \not_strict_mode.app_rd_data_reg[9]\ => \not_strict_mode.app_rd_data_reg[9]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      rd_active_r_reg => rd_active_r_reg,
      \rd_mux_sel_r_reg[1]\(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      \rd_ptr_timing_reg[0]_0\ => \rd_ptr_timing_reg[0]\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_2\,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => B"0000",
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_24\
     port map (
      CLK => CLK,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(2) => of_d1(5),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(2 downto 1) => of_d2(4 downto 3),
      D2(0) => of_d2(1),
      D3(1) => of_d3(4),
      D3(0) => of_d3(2),
      D4(1) => of_d4(7),
      D4(0) => of_d4(0),
      D5(2) => of_d5(5),
      D5(1 downto 0) => of_d5(1 downto 0),
      D6(2 downto 1) => of_d6(4 downto 3),
      D6(0) => of_d6(1),
      D7(1) => of_d7(4),
      D7(0) => of_d7(2),
      D8(1) => of_d8(7),
      D8(0) => of_d8(0),
      D9(7 downto 0) => of_d9(7 downto 0),
      \entry_cnt_reg[4]_0\(2 downto 0) => \entry_cnt_reg[4]\(2 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      ofifo_rst_reg => out_fifo_n_3,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      \write_buffer.wr_buf_out_data_reg[569]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[569]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \calib_sel_reg[1]_2\,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 6) => \write_buffer.wr_buf_out_data_reg[463]\(4 downto 3),
      D1(5) => of_d1(5),
      D1(4 downto 2) => \write_buffer.wr_buf_out_data_reg[463]\(2 downto 0),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[462]\(4 downto 2),
      D2(4 downto 3) => of_d2(4 downto 3),
      D2(2) => \write_buffer.wr_buf_out_data_reg[462]\(1),
      D2(1) => of_d2(1),
      D2(0) => \write_buffer.wr_buf_out_data_reg[462]\(0),
      D3(7 downto 5) => \write_buffer.wr_buf_out_data_reg[461]\(5 downto 3),
      D3(4) => of_d3(4),
      D3(3) => \write_buffer.wr_buf_out_data_reg[461]\(2),
      D3(2) => of_d3(2),
      D3(1 downto 0) => \write_buffer.wr_buf_out_data_reg[461]\(1 downto 0),
      D4(7) => of_d4(7),
      D4(6 downto 1) => \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0),
      D4(0) => of_d4(0),
      D5(7 downto 6) => \write_buffer.wr_buf_out_data_reg[459]\(4 downto 3),
      D5(5) => of_d5(5),
      D5(4 downto 2) => \write_buffer.wr_buf_out_data_reg[459]\(2 downto 0),
      D5(1 downto 0) => of_d5(1 downto 0),
      D6(7 downto 5) => \write_buffer.wr_buf_out_data_reg[458]\(4 downto 2),
      D6(4 downto 3) => of_d6(4 downto 3),
      D6(2) => \write_buffer.wr_buf_out_data_reg[458]\(1),
      D6(1) => of_d6(1),
      D6(0) => \write_buffer.wr_buf_out_data_reg[458]\(0),
      D7(7 downto 5) => \write_buffer.wr_buf_out_data_reg[457]\(5 downto 3),
      D7(4) => of_d7(4),
      D7(3) => \write_buffer.wr_buf_out_data_reg[457]\(2),
      D7(2) => of_d7(2),
      D7(1 downto 0) => \write_buffer.wr_buf_out_data_reg[457]\(1 downto 0),
      D8(7) => of_d8(7),
      D8(6 downto 1) => \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0),
      D8(0) => of_d8(0),
      D9(7 downto 0) => of_d9(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => \calib_sel_reg[1]_0\,
      COUNTERLOADVAL(5 downto 0) => \calib_sel_reg[1]_3\(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(5 downto 0) => \pi_counter_read_val_reg[5]\(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => pi_phase_locked_all_r1_reg,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => \calib_sel_reg[1]_2\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => \calib_sel_reg[1]_4\,
      COARSEINC => \calib_sel_reg[1]_4\,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[1]_5\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized2\ is
  port (
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    \pi_counter_read_val_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst_3 : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[64]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[66]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[68]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[70]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[128]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[130]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[132]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[134]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[192]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[194]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[196]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[198]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[256]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[258]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[260]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[262]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[320]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[322]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[324]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[326]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[384]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[386]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[388]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[390]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[448]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[450]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[452]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[454]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC;
    \rd_ptr_reg[1]\ : out STD_LOGIC;
    rd_active_r_reg : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \entry_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC;
    idelay_ce_r2_reg : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    phaser_ctl_bus : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pi_stg2_load_reg : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pi_rst_stg1_cal_reg[0]\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_stg2_reg_l_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[455]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[454]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[453]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[388]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[451]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[450]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[449]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[384]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_if_reset : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    if_empty_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : in STD_LOGIC;
    rst_r4 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[568]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    DOC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    C_byte_rd_en : in STD_LOGIC;
    byte_rd_en_v_1 : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : in STD_LOGIC;
    \my_empty_reg[3]\ : in STD_LOGIC;
    A_byte_rd_en : in STD_LOGIC;
    \my_empty_reg[3]_0\ : in STD_LOGIC;
    B_byte_rd_en : in STD_LOGIC;
    \my_empty_reg[3]_1\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized2\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized2\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized2\ is
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal if_empty_r_0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d3 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d7 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d8 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_1\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_2\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 71 downto 6 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized1_19\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0_10 => CLKB0_10,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0_9 => LD0_9,
      idelay_ce_r2_reg => idelay_ce_r2_reg,
      idelay_inc => idelay_inc,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 0) => of_dqbus(39 downto 4),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_0 => out_dqs_0,
      po_oserdes_rst => po_oserdes_rst,
      rst_r4 => rst_r4,
      ts_dqs_0 => ts_dqs_0
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => if_empty_r_0(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(66),
      Q => rd_data_r(66),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(67),
      Q => rd_data_r(67),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(68),
      Q => rd_data_r(68),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(69),
      Q => rd_data_r(69),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(70),
      Q => rd_data_r(70),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(71),
      Q => rd_data_r(71),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_20
     port map (
      A_byte_rd_en => A_byte_rd_en,
      B_byte_rd_en => B_byte_rd_en,
      CLK => CLK,
      C_byte_rd_en => C_byte_rd_en,
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      SR(0) => ififo_rst,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(65 downto 0) => rd_data_r(71 downto 6),
      if_empty_r(0) => if_empty_r(0),
      if_empty_r_0(0) => if_empty_r_0(3),
      \my_empty_reg[3]_0\ => \my_empty_reg[3]\,
      \my_empty_reg[3]_1\ => \my_empty_reg[3]_0\,
      \my_empty_reg[3]_2\ => \my_empty_reg[3]_1\,
      \not_strict_mode.app_rd_data_reg[0]\ => \not_strict_mode.app_rd_data_reg[0]\,
      \not_strict_mode.app_rd_data_reg[128]\ => \not_strict_mode.app_rd_data_reg[128]\,
      \not_strict_mode.app_rd_data_reg[129]\ => \not_strict_mode.app_rd_data_reg[129]\,
      \not_strict_mode.app_rd_data_reg[130]\ => \not_strict_mode.app_rd_data_reg[130]\,
      \not_strict_mode.app_rd_data_reg[131]\ => \not_strict_mode.app_rd_data_reg[131]\,
      \not_strict_mode.app_rd_data_reg[132]\ => \not_strict_mode.app_rd_data_reg[132]\,
      \not_strict_mode.app_rd_data_reg[133]\ => \not_strict_mode.app_rd_data_reg[133]\,
      \not_strict_mode.app_rd_data_reg[134]\ => \not_strict_mode.app_rd_data_reg[134]\,
      \not_strict_mode.app_rd_data_reg[135]\ => \not_strict_mode.app_rd_data_reg[135]\,
      \not_strict_mode.app_rd_data_reg[192]\ => \not_strict_mode.app_rd_data_reg[192]\,
      \not_strict_mode.app_rd_data_reg[193]\ => \not_strict_mode.app_rd_data_reg[193]\,
      \not_strict_mode.app_rd_data_reg[194]\ => \not_strict_mode.app_rd_data_reg[194]\,
      \not_strict_mode.app_rd_data_reg[195]\ => \not_strict_mode.app_rd_data_reg[195]\,
      \not_strict_mode.app_rd_data_reg[196]\ => \not_strict_mode.app_rd_data_reg[196]\,
      \not_strict_mode.app_rd_data_reg[197]\ => \not_strict_mode.app_rd_data_reg[197]\,
      \not_strict_mode.app_rd_data_reg[198]\ => \not_strict_mode.app_rd_data_reg[198]\,
      \not_strict_mode.app_rd_data_reg[199]\ => \not_strict_mode.app_rd_data_reg[199]\,
      \not_strict_mode.app_rd_data_reg[1]\ => \not_strict_mode.app_rd_data_reg[1]\,
      \not_strict_mode.app_rd_data_reg[256]\ => \not_strict_mode.app_rd_data_reg[256]\,
      \not_strict_mode.app_rd_data_reg[257]\ => \not_strict_mode.app_rd_data_reg[257]\,
      \not_strict_mode.app_rd_data_reg[258]\ => \not_strict_mode.app_rd_data_reg[258]\,
      \not_strict_mode.app_rd_data_reg[259]\ => \not_strict_mode.app_rd_data_reg[259]\,
      \not_strict_mode.app_rd_data_reg[260]\ => \not_strict_mode.app_rd_data_reg[260]\,
      \not_strict_mode.app_rd_data_reg[261]\ => \not_strict_mode.app_rd_data_reg[261]\,
      \not_strict_mode.app_rd_data_reg[262]\ => \not_strict_mode.app_rd_data_reg[262]\,
      \not_strict_mode.app_rd_data_reg[263]\ => \not_strict_mode.app_rd_data_reg[263]\,
      \not_strict_mode.app_rd_data_reg[2]\ => \not_strict_mode.app_rd_data_reg[2]\,
      \not_strict_mode.app_rd_data_reg[320]\ => \not_strict_mode.app_rd_data_reg[320]\,
      \not_strict_mode.app_rd_data_reg[321]\ => \not_strict_mode.app_rd_data_reg[321]\,
      \not_strict_mode.app_rd_data_reg[322]\ => \not_strict_mode.app_rd_data_reg[322]\,
      \not_strict_mode.app_rd_data_reg[323]\ => \not_strict_mode.app_rd_data_reg[323]\,
      \not_strict_mode.app_rd_data_reg[324]\ => \not_strict_mode.app_rd_data_reg[324]\,
      \not_strict_mode.app_rd_data_reg[325]\ => \not_strict_mode.app_rd_data_reg[325]\,
      \not_strict_mode.app_rd_data_reg[326]\ => \not_strict_mode.app_rd_data_reg[326]\,
      \not_strict_mode.app_rd_data_reg[327]\ => \not_strict_mode.app_rd_data_reg[327]\,
      \not_strict_mode.app_rd_data_reg[384]\ => \not_strict_mode.app_rd_data_reg[384]\,
      \not_strict_mode.app_rd_data_reg[385]\ => \not_strict_mode.app_rd_data_reg[385]\,
      \not_strict_mode.app_rd_data_reg[386]\ => \not_strict_mode.app_rd_data_reg[386]\,
      \not_strict_mode.app_rd_data_reg[387]\ => \not_strict_mode.app_rd_data_reg[387]\,
      \not_strict_mode.app_rd_data_reg[388]\ => \not_strict_mode.app_rd_data_reg[388]\,
      \not_strict_mode.app_rd_data_reg[389]\ => \not_strict_mode.app_rd_data_reg[389]\,
      \not_strict_mode.app_rd_data_reg[390]\ => \not_strict_mode.app_rd_data_reg[390]\,
      \not_strict_mode.app_rd_data_reg[391]\ => \not_strict_mode.app_rd_data_reg[391]\,
      \not_strict_mode.app_rd_data_reg[3]\ => \not_strict_mode.app_rd_data_reg[3]\,
      \not_strict_mode.app_rd_data_reg[448]\ => \not_strict_mode.app_rd_data_reg[448]\,
      \not_strict_mode.app_rd_data_reg[449]\ => \not_strict_mode.app_rd_data_reg[449]\,
      \not_strict_mode.app_rd_data_reg[450]\ => \not_strict_mode.app_rd_data_reg[450]\,
      \not_strict_mode.app_rd_data_reg[451]\ => \not_strict_mode.app_rd_data_reg[451]\,
      \not_strict_mode.app_rd_data_reg[452]\ => \not_strict_mode.app_rd_data_reg[452]\,
      \not_strict_mode.app_rd_data_reg[453]\ => \not_strict_mode.app_rd_data_reg[453]\,
      \not_strict_mode.app_rd_data_reg[454]\ => \not_strict_mode.app_rd_data_reg[454]\,
      \not_strict_mode.app_rd_data_reg[455]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[455]\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[455]_0\ => \not_strict_mode.app_rd_data_reg[455]_0\,
      \not_strict_mode.app_rd_data_reg[4]\ => \not_strict_mode.app_rd_data_reg[4]\,
      \not_strict_mode.app_rd_data_reg[5]\ => \not_strict_mode.app_rd_data_reg[5]\,
      \not_strict_mode.app_rd_data_reg[64]\ => \not_strict_mode.app_rd_data_reg[64]\,
      \not_strict_mode.app_rd_data_reg[65]\ => \not_strict_mode.app_rd_data_reg[65]\,
      \not_strict_mode.app_rd_data_reg[66]\ => \not_strict_mode.app_rd_data_reg[66]\,
      \not_strict_mode.app_rd_data_reg[67]\ => \not_strict_mode.app_rd_data_reg[67]\,
      \not_strict_mode.app_rd_data_reg[68]\ => \not_strict_mode.app_rd_data_reg[68]\,
      \not_strict_mode.app_rd_data_reg[69]\ => \not_strict_mode.app_rd_data_reg[69]\,
      \not_strict_mode.app_rd_data_reg[6]\ => \not_strict_mode.app_rd_data_reg[6]\,
      \not_strict_mode.app_rd_data_reg[70]\ => \not_strict_mode.app_rd_data_reg[70]\,
      \not_strict_mode.app_rd_data_reg[71]\ => \not_strict_mode.app_rd_data_reg[71]\,
      \not_strict_mode.app_rd_data_reg[7]\ => \not_strict_mode.app_rd_data_reg[7]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      rd_active_r_reg => rd_active_r_reg,
      \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\,
      \rd_ptr_timing_reg[0]_0\ => \rd_ptr_timing_reg[0]\,
      \rd_ptr_timing_reg[0]_1\ => \rd_ptr_timing_reg[0]_0\,
      \rd_ptr_timing_reg[0]_2\ => \rd_ptr_timing_reg[0]_1\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\
    );
ififo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_reg[0]\,
      Q => ififo_rst,
      S => phy_if_reset
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => B"0000",
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => if_d8(3 downto 0),
      D9(3 downto 0) => B"0000",
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_21\
     port map (
      CLK => CLK,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(2) => of_d1(5),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(2 downto 1) => of_d2(4 downto 3),
      D2(0) => of_d2(1),
      D3(1) => of_d3(4),
      D3(0) => of_d3(2),
      D4(1) => of_d4(7),
      D4(0) => of_d4(0),
      D5(2) => of_d5(5),
      D5(1 downto 0) => of_d5(1 downto 0),
      D6(2 downto 1) => of_d6(4 downto 3),
      D6(0) => of_d6(1),
      D7(1) => of_d7(4),
      D7(0) => of_d7(2),
      D8(1) => of_d8(7),
      D8(0) => of_d8(0),
      D9(7 downto 0) => of_d9(7 downto 0),
      \entry_cnt_reg[4]_0\(2 downto 0) => \entry_cnt_reg[4]\(2 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      ofifo_rst_reg => out_fifo_n_3,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      \write_buffer.wr_buf_out_data_reg[568]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[568]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \pi_rst_stg1_cal_reg[0]\,
      Q => ofifo_rst,
      S => A_rst_primitives
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(7 downto 6) => \write_buffer.wr_buf_out_data_reg[455]\(4 downto 3),
      D1(5) => of_d1(5),
      D1(4 downto 2) => \write_buffer.wr_buf_out_data_reg[455]\(2 downto 0),
      D1(1 downto 0) => of_d1(1 downto 0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[454]\(4 downto 2),
      D2(4 downto 3) => of_d2(4 downto 3),
      D2(2) => \write_buffer.wr_buf_out_data_reg[454]\(1),
      D2(1) => of_d2(1),
      D2(0) => \write_buffer.wr_buf_out_data_reg[454]\(0),
      D3(7 downto 5) => \write_buffer.wr_buf_out_data_reg[453]\(5 downto 3),
      D3(4) => of_d3(4),
      D3(3) => \write_buffer.wr_buf_out_data_reg[453]\(2),
      D3(2) => of_d3(2),
      D3(1 downto 0) => \write_buffer.wr_buf_out_data_reg[453]\(1 downto 0),
      D4(7) => of_d4(7),
      D4(6 downto 1) => \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0),
      D4(0) => of_d4(0),
      D5(7 downto 6) => \write_buffer.wr_buf_out_data_reg[451]\(4 downto 3),
      D5(5) => of_d5(5),
      D5(4 downto 2) => \write_buffer.wr_buf_out_data_reg[451]\(2 downto 0),
      D5(1 downto 0) => of_d5(1 downto 0),
      D6(7 downto 5) => \write_buffer.wr_buf_out_data_reg[450]\(4 downto 2),
      D6(4 downto 3) => of_d6(4 downto 3),
      D6(2) => \write_buffer.wr_buf_out_data_reg[450]\(1),
      D6(1) => of_d6(1),
      D6(0) => \write_buffer.wr_buf_out_data_reg[450]\(0),
      D7(7 downto 5) => \write_buffer.wr_buf_out_data_reg[449]\(5 downto 3),
      D7(4) => of_d7(4),
      D7(3) => \write_buffer.wr_buf_out_data_reg[449]\(2),
      D7(2) => of_d7(2),
      D7(1 downto 0) => \write_buffer.wr_buf_out_data_reg[449]\(1 downto 0),
      D8(7) => of_d8(7),
      D8(6 downto 1) => \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0),
      D8(0) => of_d8(0),
      D9(7 downto 0) => of_d9(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(1),
      COUNTERLOADEN => pi_stg2_load_reg,
      COUNTERLOADVAL(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[1]\,
      COUNTERREADVAL(5 downto 0) => \pi_counter_read_val_reg[5]\(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => \phaser_in_gen.phaser_in_n_1\,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => \phaser_in_gen.phaser_in_n_2\,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => pi_phase_locked_all_r1_reg,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => phaser_ctl_bus(3 downto 2),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives,
      RSTDQSFIND => \pi_rst_stg1_cal_reg[0]\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => phaser_ctl_bus(0),
      COARSEENABLE => dqs_wl_po_stg2_c_incdec_reg,
      COARSEINC => dqs_wl_po_stg2_c_incdec_reg,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[1]\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[0]\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized3\ is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.rd_buf_we\ : out STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[32]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[34]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[36]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[38]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[96]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[98]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[100]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[102]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[160]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[162]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[164]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[166]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[224]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[226]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[228]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[230]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[288]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[290]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[292]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[294]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[352]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[354]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[356]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[358]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[416]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[418]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[420]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[422]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[480]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[482]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[484]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[486]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]_0\ : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    byte_rd_en_v_1 : out STD_LOGIC;
    pre_data_a_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    INBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    INRANKA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC;
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[487]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[486]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[485]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[420]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[483]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[482]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[481]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[416]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    byte_rd_en_v_2 : in STD_LOGIC;
    byte_rd_en_v_0 : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_init_done_r : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[572]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    if_empty_or_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.fifo_out_data_r_reg[6]_0\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized3\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized3\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized3\ is
  signal A_pi_dqs_out_of_range : STD_LOGIC;
  signal A_pi_fine_overflow : STD_LOGIC;
  signal A_po_coarse_overflow : STD_LOGIC;
  signal A_po_fine_overflow : STD_LOGIC;
  signal \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : STD_LOGIC;
  signal if_d0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \if_empty_\ : STD_LOGIC;
  signal if_empty_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal ififo_rst : STD_LOGIC;
  signal ififo_wr_enable : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_0\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC;
  signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC;
  signal iserdes_clkdiv : STD_LOGIC;
  signal of_d0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d1 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d2 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d3 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d4 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 4 downto 1 );
  signal of_d6 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal of_d7 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_d9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal ofifo_rst : STD_LOGIC;
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal out_fifo_n_3 : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC;
  signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal rd_data_r : STD_LOGIC_VECTOR ( 65 downto 0 );
  signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute syn_maxfan : string;
  attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ <= \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\;
ddr_byte_group_io: entity work.mig_7series_0_mig_7series_v2_3_ddr_byte_group_io_13
     port map (
      A_rst_primitives_reg => A_rst_primitives_reg,
      A_rst_primitives_reg_0 => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      CLK => CLK,
      CLKB0 => CLKB0,
      CTSBUS(0) => oserdes_dqs_ts(0),
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      LD0 => LD0,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      iserdes_clkdiv => iserdes_clkdiv,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      of_dqbus(35 downto 32) => of_dqbus(39 downto 36),
      of_dqbus(31 downto 0) => of_dqbus(31 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clk_delayed => oserdes_clk_delayed,
      oserdes_clkdiv => oserdes_clkdiv,
      out_dqs_4 => out_dqs_4,
      po_oserdes_rst => po_oserdes_rst,
      ts_dqs_4 => ts_dqs_4
    );
\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \if_empty_\,
      Q => if_empty_r(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(0),
      Q => rd_data_r(0),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(10),
      Q => rd_data_r(10),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(11),
      Q => rd_data_r(11),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(12),
      Q => rd_data_r(12),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(13),
      Q => rd_data_r(13),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(14),
      Q => rd_data_r(14),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(15),
      Q => rd_data_r(15),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(16),
      Q => rd_data_r(16),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(17),
      Q => rd_data_r(17),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(18),
      Q => rd_data_r(18),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(19),
      Q => rd_data_r(19),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(1),
      Q => rd_data_r(1),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(20),
      Q => rd_data_r(20),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(21),
      Q => rd_data_r(21),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(22),
      Q => rd_data_r(22),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(23),
      Q => rd_data_r(23),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(24),
      Q => rd_data_r(24),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(25),
      Q => rd_data_r(25),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(26),
      Q => rd_data_r(26),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(27),
      Q => rd_data_r(27),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(28),
      Q => rd_data_r(28),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(29),
      Q => rd_data_r(29),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(2),
      Q => rd_data_r(2),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(30),
      Q => rd_data_r(30),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(31),
      Q => rd_data_r(31),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(32),
      Q => rd_data_r(32),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(33),
      Q => rd_data_r(33),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(34),
      Q => rd_data_r(34),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(35),
      Q => rd_data_r(35),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(36),
      Q => rd_data_r(36),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(37),
      Q => rd_data_r(37),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(38),
      Q => rd_data_r(38),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(39),
      Q => rd_data_r(39),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(3),
      Q => rd_data_r(3),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(40),
      Q => rd_data_r(40),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(41),
      Q => rd_data_r(41),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(42),
      Q => rd_data_r(42),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(43),
      Q => rd_data_r(43),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(44),
      Q => rd_data_r(44),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(45),
      Q => rd_data_r(45),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(46),
      Q => rd_data_r(46),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(47),
      Q => rd_data_r(47),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(48),
      Q => rd_data_r(48),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(49),
      Q => rd_data_r(49),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(4),
      Q => rd_data_r(4),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(50),
      Q => rd_data_r(50),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(51),
      Q => rd_data_r(51),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(52),
      Q => rd_data_r(52),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(53),
      Q => rd_data_r(53),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(54),
      Q => rd_data_r(54),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(55),
      Q => rd_data_r(55),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(56),
      Q => rd_data_r(56),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(57),
      Q => rd_data_r(57),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(58),
      Q => rd_data_r(58),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(59),
      Q => rd_data_r(59),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(5),
      Q => rd_data_r(5),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(60),
      Q => rd_data_r(60),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(61),
      Q => rd_data_r(61),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(62),
      Q => rd_data_r(62),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(63),
      Q => rd_data_r(63),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(64),
      Q => rd_data_r(64),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(65),
      Q => rd_data_r(65),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(6),
      Q => rd_data_r(6),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(7),
      Q => rd_data_r(7),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(8),
      Q => rd_data_r(8),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rd_data(9),
      Q => rd_data_r(9),
      R => '0'
    );
\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.mig_7series_0_mig_7series_v2_3_ddr_if_post_fifo_14
     port map (
      CLK => CLK,
      Q(65 downto 0) => rd_data_r(65 downto 0),
      byte_rd_en_v_0 => byte_rd_en_v_0,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      if_empty_or_v(0) => if_empty_or_v(0),
      if_empty_r(0) => if_empty_r(3),
      ififo_rst => ififo_rst,
      \not_strict_mode.app_rd_data_reg[100]\ => \not_strict_mode.app_rd_data_reg[100]\,
      \not_strict_mode.app_rd_data_reg[101]\ => \not_strict_mode.app_rd_data_reg[101]\,
      \not_strict_mode.app_rd_data_reg[102]\ => \not_strict_mode.app_rd_data_reg[102]\,
      \not_strict_mode.app_rd_data_reg[103]\ => \not_strict_mode.app_rd_data_reg[103]\,
      \not_strict_mode.app_rd_data_reg[160]\ => \not_strict_mode.app_rd_data_reg[160]\,
      \not_strict_mode.app_rd_data_reg[161]\ => \not_strict_mode.app_rd_data_reg[161]\,
      \not_strict_mode.app_rd_data_reg[162]\ => \not_strict_mode.app_rd_data_reg[162]\,
      \not_strict_mode.app_rd_data_reg[163]\ => \not_strict_mode.app_rd_data_reg[163]\,
      \not_strict_mode.app_rd_data_reg[164]\ => \not_strict_mode.app_rd_data_reg[164]\,
      \not_strict_mode.app_rd_data_reg[165]\ => \not_strict_mode.app_rd_data_reg[165]\,
      \not_strict_mode.app_rd_data_reg[166]\ => \not_strict_mode.app_rd_data_reg[166]\,
      \not_strict_mode.app_rd_data_reg[167]\ => \not_strict_mode.app_rd_data_reg[167]\,
      \not_strict_mode.app_rd_data_reg[224]\ => \not_strict_mode.app_rd_data_reg[224]\,
      \not_strict_mode.app_rd_data_reg[225]\ => \not_strict_mode.app_rd_data_reg[225]\,
      \not_strict_mode.app_rd_data_reg[226]\ => \not_strict_mode.app_rd_data_reg[226]\,
      \not_strict_mode.app_rd_data_reg[227]\ => \not_strict_mode.app_rd_data_reg[227]\,
      \not_strict_mode.app_rd_data_reg[228]\ => \not_strict_mode.app_rd_data_reg[228]\,
      \not_strict_mode.app_rd_data_reg[229]\ => \not_strict_mode.app_rd_data_reg[229]\,
      \not_strict_mode.app_rd_data_reg[230]\ => \not_strict_mode.app_rd_data_reg[230]\,
      \not_strict_mode.app_rd_data_reg[231]\ => \not_strict_mode.app_rd_data_reg[231]\,
      \not_strict_mode.app_rd_data_reg[288]\ => \not_strict_mode.app_rd_data_reg[288]\,
      \not_strict_mode.app_rd_data_reg[289]\ => \not_strict_mode.app_rd_data_reg[289]\,
      \not_strict_mode.app_rd_data_reg[290]\ => \not_strict_mode.app_rd_data_reg[290]\,
      \not_strict_mode.app_rd_data_reg[291]\ => \not_strict_mode.app_rd_data_reg[291]\,
      \not_strict_mode.app_rd_data_reg[292]\ => \not_strict_mode.app_rd_data_reg[292]\,
      \not_strict_mode.app_rd_data_reg[293]\ => \not_strict_mode.app_rd_data_reg[293]\,
      \not_strict_mode.app_rd_data_reg[294]\ => \not_strict_mode.app_rd_data_reg[294]\,
      \not_strict_mode.app_rd_data_reg[295]\ => \not_strict_mode.app_rd_data_reg[295]\,
      \not_strict_mode.app_rd_data_reg[32]\ => \not_strict_mode.app_rd_data_reg[32]\,
      \not_strict_mode.app_rd_data_reg[33]\ => \not_strict_mode.app_rd_data_reg[33]\,
      \not_strict_mode.app_rd_data_reg[34]\ => \not_strict_mode.app_rd_data_reg[34]\,
      \not_strict_mode.app_rd_data_reg[352]\ => \not_strict_mode.app_rd_data_reg[352]\,
      \not_strict_mode.app_rd_data_reg[353]\ => \not_strict_mode.app_rd_data_reg[353]\,
      \not_strict_mode.app_rd_data_reg[354]\ => \not_strict_mode.app_rd_data_reg[354]\,
      \not_strict_mode.app_rd_data_reg[355]\ => \not_strict_mode.app_rd_data_reg[355]\,
      \not_strict_mode.app_rd_data_reg[356]\ => \not_strict_mode.app_rd_data_reg[356]\,
      \not_strict_mode.app_rd_data_reg[357]\ => \not_strict_mode.app_rd_data_reg[357]\,
      \not_strict_mode.app_rd_data_reg[358]\ => \not_strict_mode.app_rd_data_reg[358]\,
      \not_strict_mode.app_rd_data_reg[359]\ => \not_strict_mode.app_rd_data_reg[359]\,
      \not_strict_mode.app_rd_data_reg[35]\ => \not_strict_mode.app_rd_data_reg[35]\,
      \not_strict_mode.app_rd_data_reg[36]\ => \not_strict_mode.app_rd_data_reg[36]\,
      \not_strict_mode.app_rd_data_reg[37]\ => \not_strict_mode.app_rd_data_reg[37]\,
      \not_strict_mode.app_rd_data_reg[38]\ => \not_strict_mode.app_rd_data_reg[38]\,
      \not_strict_mode.app_rd_data_reg[39]\ => \not_strict_mode.app_rd_data_reg[39]\,
      \not_strict_mode.app_rd_data_reg[416]\ => \not_strict_mode.app_rd_data_reg[416]\,
      \not_strict_mode.app_rd_data_reg[417]\ => \not_strict_mode.app_rd_data_reg[417]\,
      \not_strict_mode.app_rd_data_reg[418]\ => \not_strict_mode.app_rd_data_reg[418]\,
      \not_strict_mode.app_rd_data_reg[419]\ => \not_strict_mode.app_rd_data_reg[419]\,
      \not_strict_mode.app_rd_data_reg[420]\ => \not_strict_mode.app_rd_data_reg[420]\,
      \not_strict_mode.app_rd_data_reg[421]\ => \not_strict_mode.app_rd_data_reg[421]\,
      \not_strict_mode.app_rd_data_reg[422]\ => \not_strict_mode.app_rd_data_reg[422]\,
      \not_strict_mode.app_rd_data_reg[423]\ => \not_strict_mode.app_rd_data_reg[423]\,
      \not_strict_mode.app_rd_data_reg[480]\ => \not_strict_mode.app_rd_data_reg[480]\,
      \not_strict_mode.app_rd_data_reg[481]\ => \not_strict_mode.app_rd_data_reg[481]\,
      \not_strict_mode.app_rd_data_reg[482]\ => \not_strict_mode.app_rd_data_reg[482]\,
      \not_strict_mode.app_rd_data_reg[483]\ => \not_strict_mode.app_rd_data_reg[483]\,
      \not_strict_mode.app_rd_data_reg[484]\ => \not_strict_mode.app_rd_data_reg[484]\,
      \not_strict_mode.app_rd_data_reg[485]\ => \not_strict_mode.app_rd_data_reg[485]\,
      \not_strict_mode.app_rd_data_reg[486]\ => \not_strict_mode.app_rd_data_reg[486]\,
      \not_strict_mode.app_rd_data_reg[487]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[487]\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[487]_0\ => \not_strict_mode.app_rd_data_reg[487]_0\,
      \not_strict_mode.app_rd_data_reg[96]\ => \not_strict_mode.app_rd_data_reg[96]\,
      \not_strict_mode.app_rd_data_reg[97]\ => \not_strict_mode.app_rd_data_reg[97]\,
      \not_strict_mode.app_rd_data_reg[98]\ => \not_strict_mode.app_rd_data_reg[98]\,
      \not_strict_mode.app_rd_data_reg[99]\ => \not_strict_mode.app_rd_data_reg[99]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \not_strict_mode.rd_buf_we\,
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\ => \not_strict_mode.status_ram.rd_buf_we_r1_reg\,
      \out\ => \out\,
      phy_rddata_en => phy_rddata_en,
      ram_init_done_r => ram_init_done_r,
      \read_fifo.fifo_out_data_r_reg[6]\(0) => \read_fifo.fifo_out_data_r_reg[6]\(0),
      \read_fifo.fifo_out_data_r_reg[6]_0\ => \read_fifo.fifo_out_data_r_reg[6]_0\,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\
    );
ififo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ififo_rst_reg0,
      Q => ififo_rst,
      R => '0'
    );
\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_8",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => \in_fifo_gen.in_fifo_n_0\,
      ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\,
      D0(3 downto 0) => if_d0(3 downto 0),
      D1(3 downto 0) => if_d1(3 downto 0),
      D2(3 downto 0) => if_d2(3 downto 0),
      D3(3 downto 0) => if_d3(3 downto 0),
      D4(3 downto 0) => if_d4(3 downto 0),
      D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4),
      D5(3 downto 0) => if_d5(3 downto 0),
      D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4),
      D6(3 downto 0) => if_d6(3 downto 0),
      D7(3 downto 0) => if_d7(3 downto 0),
      D8(3 downto 0) => B"0000",
      D9(3 downto 0) => B"0000",
      EMPTY => \if_empty_\,
      FULL => \in_fifo_gen.in_fifo_n_3\,
      Q0(7 downto 0) => rd_data(7 downto 0),
      Q1(7 downto 0) => rd_data(15 downto 8),
      Q2(7 downto 0) => rd_data(23 downto 16),
      Q3(7 downto 0) => rd_data(31 downto 24),
      Q4(7 downto 0) => rd_data(39 downto 32),
      Q5(7 downto 0) => rd_data(47 downto 40),
      Q6(7 downto 0) => rd_data(55 downto 48),
      Q7(7 downto 0) => rd_data(63 downto 56),
      Q8(7 downto 0) => rd_data(71 downto 64),
      Q9(7 downto 0) => rd_data(79 downto 72),
      RDCLK => CLK,
      RDEN => '1',
      RESET => ififo_rst,
      WRCLK => iserdes_clkdiv,
      WREN => ififo_wr_enable
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_15\
     port map (
      CLK => CLK,
      D0(2) => of_d0(5),
      D0(1 downto 0) => of_d0(1 downto 0),
      D1(2 downto 1) => of_d1(4 downto 3),
      D1(0) => of_d1(1),
      D2(1) => of_d2(4),
      D2(0) => of_d2(2),
      D3(1) => of_d3(7),
      D3(0) => of_d3(0),
      D4(2) => of_d4(5),
      D4(1 downto 0) => of_d4(1 downto 0),
      D5(2 downto 1) => of_d5(4 downto 3),
      D5(0) => of_d5(1),
      D6(1) => of_d6(4),
      D6(0) => of_d6(2),
      D7(1) => of_d7(7),
      D7(0) => of_d7(0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => of_d9(7 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      \my_empty_reg[7]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\,
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      ofifo_rst => ofifo_rst,
      ofifo_rst_reg => out_fifo_n_3,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      pre_data_a_full_v(0) => pre_data_a_full_v(0),
      \write_buffer.wr_buf_out_data_reg[572]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[572]\(27 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ofifo_rst_reg0,
      Q => ofifo_rst,
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_8_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7 downto 6) => \write_buffer.wr_buf_out_data_reg[487]\(4 downto 3),
      D0(5) => of_d0(5),
      D0(4 downto 2) => \write_buffer.wr_buf_out_data_reg[487]\(2 downto 0),
      D0(1 downto 0) => of_d0(1 downto 0),
      D1(7 downto 5) => \write_buffer.wr_buf_out_data_reg[486]\(4 downto 2),
      D1(4 downto 3) => of_d1(4 downto 3),
      D1(2) => \write_buffer.wr_buf_out_data_reg[486]\(1),
      D1(1) => of_d1(1),
      D1(0) => \write_buffer.wr_buf_out_data_reg[486]\(0),
      D2(7 downto 5) => \write_buffer.wr_buf_out_data_reg[485]\(5 downto 3),
      D2(4) => of_d2(4),
      D2(3) => \write_buffer.wr_buf_out_data_reg[485]\(2),
      D2(2) => of_d2(2),
      D2(1 downto 0) => \write_buffer.wr_buf_out_data_reg[485]\(1 downto 0),
      D3(7) => of_d3(7),
      D3(6 downto 1) => \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0),
      D3(0) => of_d3(0),
      D4(7 downto 6) => \write_buffer.wr_buf_out_data_reg[483]\(4 downto 3),
      D4(5) => of_d4(5),
      D4(4 downto 2) => \write_buffer.wr_buf_out_data_reg[483]\(2 downto 0),
      D4(1 downto 0) => of_d4(1 downto 0),
      D5(7 downto 5) => \write_buffer.wr_buf_out_data_reg[482]\(4 downto 2),
      D5(4 downto 3) => of_d5(4 downto 3),
      D5(2) => \write_buffer.wr_buf_out_data_reg[482]\(1),
      D5(1) => of_d5(1),
      D5(0) => \write_buffer.wr_buf_out_data_reg[482]\(0),
      D6(7 downto 5) => \write_buffer.wr_buf_out_data_reg[481]\(5 downto 3),
      D6(4) => of_d6(4),
      D6(3) => \write_buffer.wr_buf_out_data_reg[481]\(2),
      D6(2) => of_d6(2),
      D6(1 downto 0) => \write_buffer.wr_buf_out_data_reg[481]\(1 downto 0),
      D7(7) => of_d7(7),
      D7(6 downto 1) => \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0),
      D7(0) => of_d7(0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D9(7 downto 0) => of_d9(7 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => out_fifo_n_3,
      Q0(3 downto 0) => of_dqbus(3 downto 0),
      Q1(3 downto 0) => of_dqbus(7 downto 4),
      Q2(3 downto 0) => of_dqbus(11 downto 8),
      Q3(3 downto 0) => of_dqbus(15 downto 12),
      Q4(3 downto 0) => of_dqbus(19 downto 16),
      Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4),
      Q5(3 downto 0) => of_dqbus(23 downto 20),
      Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4),
      Q6(3 downto 0) => of_dqbus(27 downto 24),
      Q7(3 downto 0) => of_dqbus(31 downto 28),
      Q8(3 downto 0) => of_dqbus(35 downto 32),
      Q9(3 downto 0) => of_dqbus(39 downto 36),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => ofifo_rst,
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0\
    );
\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY
    generic map(
      BURST_MODE => "TRUE",
      CLKOUT_DIV => 2,
      DQS_AUTO_RECAL => '1',
      DQS_BIAS_MODE => "FALSE",
      DQS_FIND_PATTERN => B"000",
      FINE_DELAY => 33,
      FREQ_REF_DIV => "DIV2",
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 3.000000,
      REFCLK_PERIOD => 1.500000,
      SEL_CLK_OFFSET => 6,
      SYNC_IN_DIV_RST => "TRUE",
      WR_CYCLES => "FALSE"
    )
        port map (
      BURSTPENDINGPHY => INBURSTPENDING(0),
      COUNTERLOADEN => \calib_sel_reg[1]_0\,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      DQSFOUND => pi_dqs_found_lanes(0),
      DQSOUTOFRANGE => A_pi_dqs_out_of_range,
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => tempmon_pi_f_en_r_reg,
      FINEINC => tempmon_pi_f_inc_r_reg,
      FINEOVERFLOW => A_pi_fine_overflow,
      FREQREFCLK => freq_refclk,
      ICLK => \^dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      ICLKDIV => iserdes_clkdiv,
      ISERDESRST => \phaser_in_gen.phaser_in_n_5\,
      MEMREFCLK => mem_refclk,
      PHASELOCKED => pi_phase_locked_all_r1_reg,
      PHASEREFCLK => mem_dqs_in(0),
      RANKSELPHY(1 downto 0) => INRANKA(1 downto 0),
      RCLK => \phaser_in_gen.phaser_in_n_7\,
      RST => A_rst_primitives_reg,
      RSTDQSFIND => \calib_sel_reg[1]_2\,
      SYNCIN => sync_pulse,
      SYSCLK => CLK,
      WRENABLE => ififo_wr_enable
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 2,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "TRUE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => \calib_sel_reg[1]_3\,
      COARSEINC => \calib_sel_reg[1]_3\,
      COARSEOVERFLOW => A_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \calib_sel_reg[1]_1\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \calib_sel_reg[1]_4\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => A_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized4\ is
  port (
    B_of_full : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 10 downto 0 );
    D : out STD_LOGIC_VECTOR ( 8 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.calib_in_common_reg\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_1\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    CLK : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_cmd_wr_en : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[2]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    A_rst_primitives_reg_0 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    COUNTERREADVAL : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \calib_sel_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_1 : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized4\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized4\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized4\ is
  signal B_of_a_full : STD_LOGIC;
  signal \^b_of_full\ : STD_LOGIC;
  signal B_po_coarse_overflow : STD_LOGIC;
  signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal B_po_fine_overflow : STD_LOGIC;
  signal of_d5 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal of_d6 : STD_LOGIC_VECTOR ( 6 downto 4 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  B_of_full <= \^b_of_full\;
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized2\
     port map (
      mem_dq_out(4 downto 0) => mem_dq_out(4 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(19 downto 16) => of_q6(7 downto 4),
      oserdes_dq(15 downto 8) => of_q5(7 downto 0),
      oserdes_dq(7 downto 4) => of_q3(3 downto 0),
      oserdes_dq(3 downto 0) => of_q1(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_12\
     port map (
      CLK => CLK,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D4(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D4(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D5(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      D5(4) => of_d5(6),
      D5(3) => of_d5(4),
      D5(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D5(1) => of_d5(2),
      D5(0) => of_d5(0),
      D6(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D6(5) => of_d6(6),
      D6(4) => of_d6(4),
      D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D6(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      SR(0) => SR(0),
      \cmd_pipe_plus.mc_cas_n_reg[2]\(10 downto 0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(10 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0),
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      mc_cas_n(1 downto 0) => mc_cas_n(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(0) => mc_ras_n(0),
      mem_out(10 downto 0) => mem_out(10 downto 0),
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      ofifo_rst_reg => \^b_of_full\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      \rd_ptr_timing_reg[0]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => B_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D1(3 downto 0) => D1(3 downto 0),
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D2(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D2(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D3(3 downto 0) => D3(3 downto 0),
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D4(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D4(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D5(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      D5(6) => of_d5(6),
      D5(5) => D5(1),
      D5(4) => of_d5(4),
      D5(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D5(2) => of_d5(2),
      D5(1) => D5(0),
      D5(0) => of_d5(0),
      D6(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D6(6) => of_d6(6),
      D6(5) => D6(0),
      D6(4) => of_d6(4),
      D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D6(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D9(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D9(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      EMPTY => out_fifo_n_2,
      FULL => \^b_of_full\,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => SR(0),
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => \gen_byte_sel_div2.calib_in_common_reg\,
      COARSEINC => \gen_byte_sel_div2.calib_in_common_reg\,
      COARSEOVERFLOW => B_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \gen_byte_sel_div2.calib_in_common_reg_0\,
      COUNTERREADVAL(8 downto 0) => B_po_counter_read_val(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \gen_byte_sel_div2.calib_in_common_reg_1\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => B_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
\po_counter_read_val[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(0),
      I1 => A_rst_primitives_reg_0(0),
      I2 => COUNTERREADVAL(0),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(0),
      O => D(0)
    );
\po_counter_read_val[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(1),
      I1 => A_rst_primitives_reg_0(1),
      I2 => COUNTERREADVAL(1),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(1),
      O => D(1)
    );
\po_counter_read_val[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(2),
      I1 => A_rst_primitives_reg_0(2),
      I2 => COUNTERREADVAL(2),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(2),
      O => D(2)
    );
\po_counter_read_val[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(3),
      I1 => A_rst_primitives_reg_0(3),
      I2 => COUNTERREADVAL(3),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(3),
      O => D(3)
    );
\po_counter_read_val[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(4),
      I1 => A_rst_primitives_reg_0(4),
      I2 => COUNTERREADVAL(4),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(4),
      O => D(4)
    );
\po_counter_read_val[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(5),
      I1 => A_rst_primitives_reg_0(5),
      I2 => COUNTERREADVAL(5),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(5),
      O => D(5)
    );
\po_counter_read_val[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(6),
      I1 => A_rst_primitives_reg_0(6),
      I2 => COUNTERREADVAL(6),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(6),
      O => D(6)
    );
\po_counter_read_val[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(7),
      I1 => A_rst_primitives_reg_0(7),
      I2 => COUNTERREADVAL(7),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(7),
      O => D(7)
    );
\po_counter_read_val[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => B_po_counter_read_val(8),
      I1 => A_rst_primitives_reg_0(8),
      I2 => COUNTERREADVAL(8),
      I3 => \calib_sel_reg[1]\(1),
      I4 => \calib_sel_reg[1]\(0),
      I5 => A_rst_primitives_reg_1(8),
      O => D(8)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized5\ is
  port (
    \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    C_of_full : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.calib_in_common_reg\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_1\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    A_rst_primitives_reg : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    CLK : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \init_calib_complete_reg_rep__11_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_cmd_wr_en : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 46 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized5\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized5\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized5\ is
  signal C_of_a_full : STD_LOGIC;
  signal \^c_of_full\ : STD_LOGIC;
  signal C_po_coarse_overflow : STD_LOGIC;
  signal C_po_fine_overflow : STD_LOGIC;
  signal of_d0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  C_of_full <= \^c_of_full\;
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized3\
     port map (
      mem_dq_out(11 downto 0) => mem_dq_out(11 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(47 downto 44) => of_q6(7 downto 4),
      oserdes_dq(43 downto 40) => of_q5(7 downto 4),
      oserdes_dq(39 downto 36) => of_q9(3 downto 0),
      oserdes_dq(35 downto 32) => of_q8(3 downto 0),
      oserdes_dq(31 downto 28) => of_q7(3 downto 0),
      oserdes_dq(27 downto 24) => of_q6(3 downto 0),
      oserdes_dq(23 downto 20) => of_q5(3 downto 0),
      oserdes_dq(19 downto 16) => of_q4(3 downto 0),
      oserdes_dq(15 downto 12) => of_q3(3 downto 0),
      oserdes_dq(11 downto 8) => of_q2(3 downto 0),
      oserdes_dq(7 downto 4) => of_q1(3 downto 0),
      oserdes_dq(3 downto 0) => of_q0(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_11\
     port map (
      CLK => CLK,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(1) => of_d0(2),
      D0(0) => of_d0(0),
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D2(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D2(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D4(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D4(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D4(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D4(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D9(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D9(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      SR(0) => SR(0),
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      ofifo_rst_reg => \^c_of_full\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_dout(46 downto 0) => phy_dout(46 downto 0),
      \rd_ptr_timing_reg[0]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      \rd_ptr_timing_reg[0]_1\(44 downto 0) => \rd_ptr_timing_reg[0]\(44 downto 0)
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => C_of_a_full,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D0(2) => of_d0(2),
      D0(1) => D0(0),
      D0(0) => of_d0(0),
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12\,
      D1(3 downto 0) => \init_calib_complete_reg_rep__10\(3 downto 0),
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D2(3 downto 0) => \init_calib_complete_reg_rep__10_0\(3 downto 0),
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D3(3 downto 0) => \init_calib_complete_reg_rep__10_1\(3 downto 0),
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D4(3 downto 0) => D4(3 downto 0),
      D5(7 downto 0) => \init_calib_complete_reg_rep__11\(7 downto 0),
      D6(7 downto 0) => \init_calib_complete_reg_rep__11_0\(7 downto 0),
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D7(3 downto 0) => D7(3 downto 0),
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D8(3 downto 0) => D8(3 downto 0),
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36\,
      D9(3 downto 0) => D9(3 downto 0),
      EMPTY => out_fifo_n_2,
      FULL => \^c_of_full\,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => SR(0),
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => \gen_byte_sel_div2.calib_in_common_reg\,
      COARSEINC => \gen_byte_sel_div2.calib_in_common_reg\,
      COARSEOVERFLOW => C_po_coarse_overflow,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => \gen_byte_sel_div2.calib_in_common_reg_0\,
      COUNTERREADVAL(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => \gen_byte_sel_div2.calib_in_common_reg_1\,
      FINEINC => ck_po_stg2_f_indec_reg,
      FINEOVERFLOW => C_po_fine_overflow,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized6\ is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_dq_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    A_rst_primitives_reg : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \init_calib_complete_reg_rep__11\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    B_of_full : in STD_LOGIC;
    C_of_full : in STD_LOGIC;
    OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 );
    D_po_coarse_enable105_out : in STD_LOGIC;
    D_po_counter_read_en117_out : in STD_LOGIC;
    D_po_fine_enable102_out : in STD_LOGIC;
    D_po_fine_inc108_out : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_cmd_wr_en : in STD_LOGIC;
    init_calib_complete_reg : in STD_LOGIC_VECTOR ( 21 downto 0 );
    \init_calib_complete_reg_rep__12_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized6\ : entity is "mig_7series_v2_3_ddr_byte_lane";
end \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized6\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized6\ is
  signal D_of_full : STD_LOGIC;
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ddr_ck_out_q : STD_LOGIC_VECTOR ( 0 to 0 );
  signal of_d4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_d5 : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC;
  signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal oserdes_clk : STD_LOGIC;
  signal oserdes_clk_delayed : STD_LOGIC;
  signal oserdes_clkdiv : STD_LOGIC;
  signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal out_fifo_n_0 : STD_LOGIC;
  signal out_fifo_n_1 : STD_LOGIC;
  signal out_fifo_n_2 : STD_LOGIC;
  signal phaser_out_n_0 : STD_LOGIC;
  signal phaser_out_n_1 : STD_LOGIC;
  signal po_oserdes_rst : STD_LOGIC;
  signal po_rd_enable : STD_LOGIC;
  signal \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\ : STD_LOGIC;
  signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "PRIMITIVE";
  attribute \__SRVAL\ : string;
  attribute \__SRVAL\ of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "FALSE";
  attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "DONT_CARE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "OBUFDS";
  attribute BOX_TYPE of out_fifo : label is "PRIMITIVE";
  attribute BOX_TYPE of phaser_out : label is "PRIMITIVE";
begin
  SR(0) <= \^sr\(0);
ddr_byte_group_io: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_group_io__parameterized4\
     port map (
      mem_dq_out(5 downto 0) => mem_dq_out(5 downto 0),
      oserdes_clk => oserdes_clk,
      oserdes_clkdiv => oserdes_clkdiv,
      oserdes_dq(23 downto 16) => of_q5(7 downto 0),
      oserdes_dq(15 downto 12) => of_q4(3 downto 0),
      oserdes_dq(11 downto 8) => of_q3(3 downto 0),
      oserdes_dq(7 downto 4) => of_q2(3 downto 0),
      oserdes_dq(3 downto 0) => of_q1(3 downto 0),
      po_oserdes_rst => po_oserdes_rst
    );
\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\: unisim.vcomponents.ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D1_INVERTED => '0',
      IS_D2_INVERTED => '0',
      SRTYPE => "SYNC"
    )
        port map (
      C => oserdes_clk,
      CE => '1',
      D1 => '0',
      D2 => '1',
      Q => ddr_ck_out_q(0),
      R => '0',
      S => \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\
    );
\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\: unisim.vcomponents.OBUFDS
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => ddr_ck_out_q(0),
      O => ddr_ck_out(0),
      OB => ddr_ck_out(1)
    );
\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized1_10\
     port map (
      CLK => CLK,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D1(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D1(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D1(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D1(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D2(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D2(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D3(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D3(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D3(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D3(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D4(3 downto 0) => of_d4(3 downto 0),
      D5(3 downto 0) => of_d5(7 downto 4),
      D_of_full => D_of_full,
      SR(0) => \^sr\(0),
      init_calib_complete_reg(21 downto 0) => init_calib_complete_reg(21 downto 0),
      \init_calib_complete_reg_rep__11\ => \init_calib_complete_reg_rep__11\,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12_2\,
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(0) => mc_cas_n(0),
      \my_empty_reg[1]_0\ => \my_empty_reg[1]\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      \rd_ptr_timing_reg[0]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\,
      \rd_ptr_timing_reg[0]_1\(15 downto 0) => \rd_ptr_timing_reg[0]\(15 downto 0)
    );
ofifo_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => A_rst_primitives_reg,
      Q => \^sr\(0),
      R => '0'
    );
out_fifo: unisim.vcomponents.OUT_FIFO
    generic map(
      ALMOST_EMPTY_VALUE => 1,
      ALMOST_FULL_VALUE => 1,
      ARRAY_MODE => "ARRAY_MODE_4_X_4",
      OUTPUT_DISABLE => "FALSE",
      SYNCHRONOUS_MODE => "FALSE"
    )
        port map (
      ALMOSTEMPTY => out_fifo_n_0,
      ALMOSTFULL => out_fifo_n_1,
      D0(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14\,
      D0(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15\,
      D0(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D0(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D0(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D0(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D0(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D0(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D1(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22\,
      D1(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23\,
      D1(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24\,
      D1(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25\,
      D1(3 downto 0) => \init_calib_complete_reg_rep__12\(3 downto 0),
      D2(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26\,
      D2(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27\,
      D2(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28\,
      D2(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29\,
      D2(3 downto 0) => D2(3 downto 0),
      D3(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30\,
      D3(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31\,
      D3(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32\,
      D3(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33\,
      D3(3 downto 0) => \init_calib_complete_reg_rep__12_0\(3 downto 0),
      D4(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5\,
      D4(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\,
      D4(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\,
      D4(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\,
      D4(3 downto 0) => of_d4(3 downto 0),
      D5(7 downto 4) => of_d5(7 downto 4),
      D5(3 downto 0) => \init_calib_complete_reg_rep__12_1\(3 downto 0),
      D6(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D6(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D6(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D6(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D6(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D6(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D7(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D7(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D7(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D7(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D7(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D7(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D7(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D7(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D8(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D8(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D8(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D8(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D8(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D8(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D8(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D8(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D9(7) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D9(6) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      D9(5) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16\,
      D9(4) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17\,
      D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18\,
      D9(2) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19\,
      D9(1) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20\,
      D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21\,
      EMPTY => out_fifo_n_2,
      FULL => D_of_full,
      Q0(3 downto 0) => of_q0(3 downto 0),
      Q1(3 downto 0) => of_q1(3 downto 0),
      Q2(3 downto 0) => of_q2(3 downto 0),
      Q3(3 downto 0) => of_q3(3 downto 0),
      Q4(3 downto 0) => of_q4(3 downto 0),
      Q5(7 downto 0) => of_q5(7 downto 0),
      Q6(7 downto 0) => of_q6(7 downto 0),
      Q7(3 downto 0) => of_q7(3 downto 0),
      Q8(3 downto 0) => of_q8(3 downto 0),
      Q9(3 downto 0) => of_q9(3 downto 0),
      RDCLK => oserdes_clkdiv,
      RDEN => po_rd_enable,
      RESET => \^sr\(0),
      WRCLK => CLK,
      WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\
    );
phaser_out: unisim.vcomponents.PHASER_OUT_PHY
    generic map(
      CLKOUT_DIV => 4,
      COARSE_BYPASS => "FALSE",
      COARSE_DELAY => 0,
      DATA_CTL_N => "FALSE",
      DATA_RD_CYCLES => "FALSE",
      FINE_DELAY => 60,
      IS_RST_INVERTED => '0',
      MEMREFCLK_PERIOD => 3.000000,
      OCLKDELAY_INV => "FALSE",
      OCLK_DELAY => 8,
      OUTPUT_CLK_SRC => "DELAYED_REF",
      PHASEREFCLK_PERIOD => 1.000000,
      PO => B"111",
      REFCLK_PERIOD => 1.500000,
      SYNC_IN_DIV_RST => "TRUE"
    )
        port map (
      BURSTPENDINGPHY => OUTBURSTPENDING(0),
      COARSEENABLE => D_po_coarse_enable105_out,
      COARSEINC => D_po_coarse_enable105_out,
      COARSEOVERFLOW => phaser_out_n_0,
      COUNTERLOADEN => '0',
      COUNTERLOADVAL(8 downto 0) => B"000000000",
      COUNTERREADEN => D_po_counter_read_en117_out,
      COUNTERREADVAL(8 downto 0) => COUNTERREADVAL(8 downto 0),
      CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0),
      DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0),
      DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0),
      ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0),
      FINEENABLE => D_po_fine_enable102_out,
      FINEINC => D_po_fine_inc108_out,
      FINEOVERFLOW => phaser_out_n_1,
      FREQREFCLK => freq_refclk,
      MEMREFCLK => mem_refclk,
      OCLK => oserdes_clk,
      OCLKDELAYED => oserdes_clk_delayed,
      OCLKDIV => oserdes_clkdiv,
      OSERDESRST => po_oserdes_rst,
      PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED,
      RDENABLE => po_rd_enable,
      RST => A_rst_primitives_reg,
      SELFINEOCLKDELAY => '0',
      SYNCIN => sync_pulse,
      SYSCLK => CLK
    );
phy_mc_cmd_full_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => D_of_full,
      I1 => B_of_full,
      I2 => C_of_full,
      O => of_ctl_full_v(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_calib_top is
  port (
    dqs_po_en_stg2_f_reg : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    \complex_row1_rd_cnt_reg[1]\ : out STD_LOGIC;
    cnt_pwron_cke_done_r : out STD_LOGIC;
    rdlvl_stg1_start_r_reg : out STD_LOGIC;
    phy_write_calib : out STD_LOGIC;
    phy_read_calib : out STD_LOGIC;
    idelay_tap_limit_r_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    fine_dly_dec_done_r1_reg : out STD_LOGIC;
    phy_if_reset : out STD_LOGIC;
    idelay_inc : out STD_LOGIC;
    phy_dout : out STD_LOGIC_VECTOR ( 21 downto 0 );
    \my_empty_reg[7]\ : out STD_LOGIC;
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[7]_1\ : out STD_LOGIC;
    \my_empty_reg[7]_2\ : out STD_LOGIC;
    \my_empty_reg[7]_3\ : out STD_LOGIC;
    \my_empty_reg[7]_4\ : out STD_LOGIC;
    \my_empty_reg[7]_5\ : out STD_LOGIC;
    \my_empty_reg[7]_6\ : out STD_LOGIC;
    \my_empty_reg[7]_7\ : out STD_LOGIC;
    \my_empty_reg[7]_8\ : out STD_LOGIC;
    \my_empty_reg[7]_9\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    app_zq_r_reg : out STD_LOGIC;
    \my_empty_reg[7]_10\ : out STD_LOGIC;
    \my_empty_reg[7]_11\ : out STD_LOGIC;
    \my_empty_reg[7]_12\ : out STD_LOGIC;
    \my_empty_reg[7]_13\ : out STD_LOGIC;
    \my_empty_reg[7]_14\ : out STD_LOGIC;
    \my_empty_reg[7]_15\ : out STD_LOGIC;
    \my_empty_reg[7]_16\ : out STD_LOGIC;
    \my_empty_reg[7]_17\ : out STD_LOGIC;
    \my_empty_reg[7]_18\ : out STD_LOGIC;
    \phy_ctl_wd_i1_reg[0]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D_po_coarse_enable105_out : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]\ : out STD_LOGIC;
    COUNTERLOADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_1\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]_0\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]_1\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_2\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_3\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_4\ : out STD_LOGIC;
    D_po_fine_enable102_out : out STD_LOGIC;
    D_po_counter_read_en117_out : out STD_LOGIC;
    \po_counter_read_val_reg[8]_5\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_6\ : out STD_LOGIC;
    LD0 : out STD_LOGIC;
    LD0_0 : out STD_LOGIC;
    LD0_1 : out STD_LOGIC;
    LD0_2 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_7\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_8\ : out STD_LOGIC;
    ififo_rst_reg : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_1\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_9\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_10\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_11\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_12\ : out STD_LOGIC;
    ififo_rst_reg_0 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_13\ : out STD_LOGIC;
    ififo_rst_reg_1 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_14\ : out STD_LOGIC;
    ififo_rst_reg_2 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_0\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[2]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[3]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[8]\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_15\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_16\ : out STD_LOGIC;
    ififo_rst_reg_3 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_1\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_17\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_18\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_19\ : out STD_LOGIC;
    ififo_rst_reg_4 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_20\ : out STD_LOGIC;
    ififo_rst_reg_5 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_0\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_dqs_found_lanes_r1_reg[10]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \rdlvl_dqs_tap_cnt_r_reg[0][4][0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pi_dqs_found_lanes_r1_reg[0]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]_2\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[0]_3\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[1]_3\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[2]_3\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[3]_3\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[8]_3\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[9]_3\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]_3\ : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[4]_3\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_21\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_22\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_23\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_24\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_25\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_26\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_27\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_28\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_29\ : out STD_LOGIC;
    \po_counter_read_val_reg[8]_30\ : out STD_LOGIC;
    D_po_fine_inc108_out : out STD_LOGIC;
    D5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : out STD_LOGIC_VECTOR ( 0 to 0 );
    D0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    D1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_3\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_4\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rd_ptr_timing_reg[0]_5\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_6\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_7\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_ptr_timing_reg[0]_8\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \my_empty_reg[7]_19\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_20\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_21\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_22\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_23\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_24\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_25\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_26\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_27\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_28\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_29\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_30\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_31\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_32\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_33\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_34\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_35\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_36\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_37\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_38\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_39\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_40\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_41\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_42\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_43\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_44\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_45\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_46\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_47\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_48\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_49\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_50\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_51\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_52\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_53\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_54\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_55\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_56\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_57\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_58\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_59\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_60\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_61\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_62\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_63\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_64\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_65\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \my_empty_reg[7]_66\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_67\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_68\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_69\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_70\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_71\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_72\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_73\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_74\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_75\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_76\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_77\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_78\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_79\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_80\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_81\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \my_empty_reg[7]_82\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \maint_prescaler.maint_prescaler_r1\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : out STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ : out STD_LOGIC;
    phy_data_wr_en : out STD_LOGIC;
    phy_cmd_wr_en : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_9\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    mux_reset_n : out STD_LOGIC;
    \data_offset_1_i1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \data_offset_2_i1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_ptr_timing_reg[0]_10\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    \phy_ctl_wd_i1_reg[24]\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    mux_wrdata : out STD_LOGIC_VECTOR ( 415 downto 0 );
    mux_wrdata_mask : out STD_LOGIC_VECTOR ( 63 downto 0 );
    LD0_3 : out STD_LOGIC;
    ififo_rst_reg0 : out STD_LOGIC;
    ofifo_rst_reg0 : out STD_LOGIC;
    \pi_counter_read_val_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    LD0_4 : out STD_LOGIC;
    ofifo_rst_reg0_5 : out STD_LOGIC;
    LD0_6 : out STD_LOGIC;
    ofifo_rst_reg0_7 : out STD_LOGIC;
    LD0_8 : out STD_LOGIC;
    ofifo_rst_reg0_9 : out STD_LOGIC;
    phy_mc_go : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__4\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__5\ : in STD_LOGIC;
    in0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_110_in : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_0\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_1\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_2\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_3\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_4\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_5\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_6\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_7\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_8\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_9\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_10\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_11\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_12\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_13\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_14\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_15\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_16\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_17\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_18\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_19\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_20\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_21\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_22\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_23\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_24\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_25\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_26\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_27\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_28\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_29\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_30\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_31\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_32\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_33\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_34\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_35\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_36\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_37\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_38\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_39\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_40\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_41\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_42\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_43\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_44\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_45\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_46\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_47\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_48\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_49\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_50\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_51\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_52\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_53\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_54\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_55\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_56\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_57\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_58\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_59\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_60\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_61\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]_62\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tempmon_sample_en : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__15\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__17\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_rddata_en : in STD_LOGIC;
    p_0_out : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_3\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_4\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_5\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_6\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_7\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_8\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_9\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_10\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_11\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_12\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_13\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_14\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_15\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_16\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_17\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_18\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_19\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_20\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_21\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_22\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_23\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_24\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_25\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_26\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_27\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_28\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_29\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_30\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_31\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_32\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_33\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_34\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_35\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_36\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_37\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_38\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_39\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_40\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_41\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_42\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_43\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_44\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_45\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_46\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_47\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_48\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_49\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_50\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_51\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_52\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_53\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_54\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_55\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_56\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_57\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_58\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_59\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_60\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]_61\ : in STD_LOGIC;
    idelay_ld_rst : in STD_LOGIC;
    idelay_ld_rst_10 : in STD_LOGIC;
    idelay_ld_rst_11 : in STD_LOGIC;
    idelay_ld_rst_12 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__22\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mem_out : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \my_empty_reg[1]\ : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_reg[3]\ : in STD_LOGIC_VECTOR ( 44 downto 0 );
    \my_empty_reg[1]_0\ : in STD_LOGIC;
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_calib_complete_reg_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \my_empty_reg[1]_1\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 38 downto 0 );
    mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \write_buffer.wr_buf_out_data_reg[575]\ : in STD_LOGIC_VECTOR ( 479 downto 0 );
    \rd_ptr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_2\ : in STD_LOGIC;
    \rd_ptr_reg[3]_1\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_3\ : in STD_LOGIC;
    \rd_ptr_reg[3]_2\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_4\ : in STD_LOGIC;
    \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_5\ : in STD_LOGIC;
    \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_6\ : in STD_LOGIC;
    \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_7\ : in STD_LOGIC;
    \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_8\ : in STD_LOGIC;
    \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[1]_9\ : in STD_LOGIC;
    sent_col : in STD_LOGIC;
    \grant_r_reg[3]\ : in STD_LOGIC;
    \po_counter_read_val_reg[0]\ : in STD_LOGIC;
    \po_counter_read_val_reg[1]\ : in STD_LOGIC;
    \po_counter_read_val_reg[2]\ : in STD_LOGIC;
    \po_counter_read_val_reg[3]\ : in STD_LOGIC;
    \po_counter_read_val_reg[4]\ : in STD_LOGIC;
    \po_counter_read_val_reg[5]\ : in STD_LOGIC;
    \po_counter_read_val_reg[6]\ : in STD_LOGIC;
    \po_counter_read_val_reg[7]\ : in STD_LOGIC;
    \po_counter_read_val_reg[8]_31\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    \pi_counter_read_val_reg[2]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[3]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[4]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[5]_0\ : in STD_LOGIC;
    \pi_counter_read_val_reg[0]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[1]\ : in STD_LOGIC;
    \pi_counter_read_val_reg[2]_0\ : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[5]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[4]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[1]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]_0\ : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    idelay_ld_rst_13 : in STD_LOGIC;
    A_rst_primitives : in STD_LOGIC;
    COUNTERREADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    idelay_ld_rst_14 : in STD_LOGIC;
    A_rst_primitives_15 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rstdiv0_sync_r1_reg_rep : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_rdlvl_done_pulse_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__22_0\ : in STD_LOGIC;
    new_cnt_cpt_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_start_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    clear : in STD_LOGIC;
    pi_cnt_dec_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \device_temp_r_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ : in STD_LOGIC;
    pi_dqs_found_lanes : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_calib_top : entity is "mig_7series_v2_3_ddr_calib_top";
end mig_7series_0_mig_7series_v2_3_ddr_calib_top;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_calib_top is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^app_zq_r_reg\ : STD_LOGIC;
  signal cal1_state_r1536_out : STD_LOGIC;
  signal calib_complete : STD_LOGIC;
  signal calib_in_common : STD_LOGIC;
  signal \calib_sel[0]_i_2_n_0\ : STD_LOGIC;
  signal \calib_sel[1]_i_2_n_0\ : STD_LOGIC;
  signal calib_zero_inputs : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \calib_zero_inputs[1]_i_2_n_0\ : STD_LOGIC;
  signal \calib_zero_inputs[2]_i_4_n_0\ : STD_LOGIC;
  signal ck_addr_cmd_delay_done : STD_LOGIC;
  signal ck_po_stg2_f_en : STD_LOGIC;
  signal cmd_delay_start0 : STD_LOGIC;
  signal cmd_po_en_stg2_f : STD_LOGIC;
  signal \^cnt_pwron_cke_done_r\ : STD_LOGIC;
  signal ctl_lane_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ctl_lane_sel : STD_LOGIC;
  signal ddr3_lm_done_r : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_10 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_2 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_4 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_5 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_6 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_7 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_8 : STD_LOGIC;
  signal ddr_phy_tempmon_0_n_9 : STD_LOGIC;
  signal detect_pi_found_dqs : STD_LOGIC;
  signal done_dqs_dec239_out : STD_LOGIC;
  signal done_dqs_tap_inc : STD_LOGIC;
  signal dqs_found_prech_req : STD_LOGIC;
  signal dqs_po_dec_done : STD_LOGIC;
  signal dqs_po_en_stg2_f : STD_LOGIC;
  signal dqs_po_stg2_f_incdec : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_10\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_11\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_55\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_63\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_64\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_65\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_66\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_68\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_69\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_70\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_71\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_73\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_74\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_76\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_82\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_84\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_85\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_86\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_87\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_88\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_89\ : STD_LOGIC;
  signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_9\ : STD_LOGIC;
  signal first_rdlvl_pat_r : STD_LOGIC;
  signal first_wrcal_pat_r : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2]\ : STD_LOGIC;
  signal \^gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal idelay_ce : STD_LOGIC;
  signal idelay_ce_int : STD_LOGIC;
  signal idelay_ce_r1 : STD_LOGIC;
  signal idelay_inc_int : STD_LOGIC;
  signal idelay_inc_r1 : STD_LOGIC;
  signal \init_calib_complete_reg_rep__13_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__13_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__13_n_0\ : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of \init_calib_complete_reg_rep__13_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__23_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__23_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__23_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__23_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__24_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__24_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__24_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__24_n_0\ : signal is "10";
  signal \init_calib_complete_reg_rep__25_n_0\ : STD_LOGIC;
  attribute MAX_FANOUT of \init_calib_complete_reg_rep__25_n_0\ : signal is "50";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__25_n_0\ : signal is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__25_n_0\ : signal is "10";
  signal init_dqsfound_done_r2 : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_23\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24\ : STD_LOGIC;
  signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7\ : STD_LOGIC;
  signal mem_init_done_r : STD_LOGIC;
  signal mpr_rdlvl_start_r : STD_LOGIC;
  signal \^my_empty_reg[7]_0\ : STD_LOGIC;
  signal \^my_empty_reg[7]_1\ : STD_LOGIC;
  signal \^my_empty_reg[7]_10\ : STD_LOGIC;
  signal \^my_empty_reg[7]_11\ : STD_LOGIC;
  signal \^my_empty_reg[7]_12\ : STD_LOGIC;
  signal \^my_empty_reg[7]_13\ : STD_LOGIC;
  signal \^my_empty_reg[7]_14\ : STD_LOGIC;
  signal \^my_empty_reg[7]_15\ : STD_LOGIC;
  signal \^my_empty_reg[7]_16\ : STD_LOGIC;
  signal \^my_empty_reg[7]_17\ : STD_LOGIC;
  signal \^my_empty_reg[7]_18\ : STD_LOGIC;
  signal \^my_empty_reg[7]_2\ : STD_LOGIC;
  signal \^my_empty_reg[7]_3\ : STD_LOGIC;
  signal \^my_empty_reg[7]_4\ : STD_LOGIC;
  signal \^my_empty_reg[7]_5\ : STD_LOGIC;
  signal \^my_empty_reg[7]_6\ : STD_LOGIC;
  signal \^my_empty_reg[7]_7\ : STD_LOGIC;
  signal \^my_empty_reg[7]_8\ : STD_LOGIC;
  signal \^my_empty_reg[7]_9\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 to 3 );
  signal p_0_in_0 : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal \^phy_ctl_wd_i1_reg[0]\ : STD_LOGIC;
  signal \^phy_if_reset\ : STD_LOGIC;
  signal \phy_if_reset0__0\ : STD_LOGIC;
  signal phy_if_reset_w : STD_LOGIC;
  signal pi_calib_done : STD_LOGIC;
  signal pi_dqs_found_done_r1 : STD_LOGIC;
  signal pi_dqs_found_rank_done : STD_LOGIC;
  signal pi_fine_dly_dec_done : STD_LOGIC;
  signal po_enstg2_f : STD_LOGIC_VECTOR ( 2 to 2 );
  signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 3 to 3 );
  signal prbs_rdlvl_done_pulse0 : STD_LOGIC;
  signal prech_done : STD_LOGIC;
  signal rd_active_r : STD_LOGIC;
  signal rd_data_offset_ranks_0 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal rd_data_offset_ranks_1 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal rd_data_offset_ranks_2 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^rd_ptr_timing_reg[0]\ : STD_LOGIC;
  signal \^rd_ptr_timing_reg[0]_0\ : STD_LOGIC;
  signal rdlvl_last_byte_done : STD_LOGIC;
  signal rdlvl_prech_req : STD_LOGIC;
  signal rdlvl_stg1_done_r1 : STD_LOGIC;
  signal rdlvl_stg1_rank_done : STD_LOGIC;
  signal \^rdlvl_stg1_start_r_reg\ : STD_LOGIC;
  signal reset_if : STD_LOGIC;
  signal reset_if_r8_reg_srl8_n_0 : STD_LOGIC;
  signal reset_if_r9 : STD_LOGIC;
  signal stg1_wr_done : STD_LOGIC;
  signal tempmon_pi_f_dec : STD_LOGIC;
  signal tempmon_pi_f_en_r : STD_LOGIC;
  signal tempmon_pi_f_en_r0 : STD_LOGIC;
  signal tempmon_pi_f_inc : STD_LOGIC;
  signal tempmon_pi_f_inc_r : STD_LOGIC;
  signal u_ddr_phy_init_n_13 : STD_LOGIC;
  signal u_ddr_phy_init_n_15 : STD_LOGIC;
  signal u_ddr_phy_init_n_4 : STD_LOGIC;
  signal u_ddr_phy_init_n_451 : STD_LOGIC;
  signal u_ddr_phy_init_n_896 : STD_LOGIC;
  signal u_ddr_phy_init_n_897 : STD_LOGIC;
  signal u_ddr_phy_init_n_898 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_100 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_101 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_102 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_103 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_104 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_105 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_106 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_107 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_67 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_68 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_69 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_70 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_71 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_72 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_8 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_92 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_94 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_95 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_96 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_97 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_98 : STD_LOGIC;
  signal u_ddr_phy_rdlvl_n_99 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_13 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_18 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_19 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_20 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_21 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_22 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_23 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_24 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_25 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_27 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_28 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_29 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_3 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_30 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_31 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_32 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_33 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_34 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_35 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_36 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_37 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_38 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_4 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_43 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_6 : STD_LOGIC;
  signal u_ddr_phy_wrcal_n_7 : STD_LOGIC;
  signal wl_sm_start : STD_LOGIC;
  signal wr_level_done_r5 : STD_LOGIC;
  signal wrcal_prech_req : STD_LOGIC;
  signal wrcal_rd_wait : STD_LOGIC;
  signal wrcal_resume_w : STD_LOGIC;
  signal wrcal_sanity_chk : STD_LOGIC;
  signal wrlvl_byte_done : STD_LOGIC;
  signal wrlvl_byte_redo : STD_LOGIC;
  signal wrlvl_byte_redo_r : STD_LOGIC;
  signal wrlvl_done_r1 : STD_LOGIC;
  signal wrlvl_final_if_rst : STD_LOGIC;
  signal wrlvl_rank_done : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \calib_sel[0]_i_2\ : label is "soft_lutpair456";
  attribute SOFT_HLUTNM of \calib_sel[1]_i_2\ : label is "soft_lutpair459";
  attribute syn_maxfan of \calib_sel_reg[0]\ : label is "10";
  attribute syn_maxfan of \calib_sel_reg[1]\ : label is "10";
  attribute syn_maxfan of \calib_sel_reg[3]\ : label is "10";
  attribute syn_maxfan of \calib_sel_reg[4]\ : label is "10";
  attribute SOFT_HLUTNM of \calib_zero_inputs[1]_i_2\ : label is "soft_lutpair459";
  attribute SOFT_HLUTNM of \calib_zero_inputs[2]_i_4\ : label is "soft_lutpair456";
  attribute syn_maxfan of \calib_zero_inputs_reg[0]\ : label is "10";
  attribute syn_maxfan of \calib_zero_inputs_reg[1]\ : label is "10";
  attribute syn_maxfan of \calib_zero_inputs_reg[2]\ : label is "10";
  attribute syn_maxfan of \gen_byte_sel_div2.calib_in_common_reg\ : label is "10";
  attribute syn_maxfan of idelay_inc_r2_reg : label is "30";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of init_calib_complete_reg : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED : integer;
  attribute IS_FANOUT_CONSTRAINED of init_calib_complete_reg_rep : label is 1;
  attribute ORIG_CELL_NAME of init_calib_complete_reg_rep : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__0\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__0\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__1\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__1\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__10\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__10\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__11\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__11\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__12\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__12\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__13\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__13\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__13\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__13\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__14\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__14\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__15\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__15\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__16\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__16\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__17\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__17\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__18\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__18\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__19\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__19\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__2\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__2\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__20\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__20\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__21\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__21\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__22\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__22\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__23\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__23\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__23\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__23\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__24\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__24\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__24\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__24\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__25\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__25\ : label is "init_calib_complete_reg";
  attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__25\ : label is "found";
  attribute syn_maxfan of \init_calib_complete_reg_rep__25\ : label is "10";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__26\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__26\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__3\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__3\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__4\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__4\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__5\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__5\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__6\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__6\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__7\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__7\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__8\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__8\ : label is "init_calib_complete_reg";
  attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__9\ : label is 1;
  attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__9\ : label is "init_calib_complete_reg";
  attribute SOFT_HLUTNM of \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair449";
  attribute SOFT_HLUTNM of \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1__0\ : label is "soft_lutpair448";
  attribute SOFT_HLUTNM of \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1__1\ : label is "soft_lutpair451";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair450";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__0\ : label is "soft_lutpair450";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__1\ : label is "soft_lutpair448";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__2\ : label is "soft_lutpair452";
  attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__3\ : label is "soft_lutpair451";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2\ : label is "soft_lutpair449";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__0\ : label is "soft_lutpair454";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__1\ : label is "soft_lutpair454";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__2\ : label is "soft_lutpair455";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__3\ : label is "soft_lutpair455";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__4\ : label is "soft_lutpair452";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__5\ : label is "soft_lutpair453";
  attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__6\ : label is "soft_lutpair453";
  attribute SOFT_HLUTNM of \phaser_out_i_2__0\ : label is "soft_lutpair457";
  attribute SOFT_HLUTNM of \phaser_out_i_2__1\ : label is "soft_lutpair457";
  attribute SOFT_HLUTNM of \phaser_out_i_2__2\ : label is "soft_lutpair458";
  attribute SOFT_HLUTNM of \pi_counter_read_val[0]_i_1\ : label is "soft_lutpair458";
  attribute SOFT_HLUTNM of \pi_counter_read_val[1]_i_1\ : label is "soft_lutpair460";
  attribute SOFT_HLUTNM of \pi_counter_read_val[2]_i_1\ : label is "soft_lutpair460";
  attribute SOFT_HLUTNM of \pi_counter_read_val[3]_i_1\ : label is "soft_lutpair461";
  attribute SOFT_HLUTNM of \pi_counter_read_val[4]_i_1\ : label is "soft_lutpair461";
  attribute srl_name : string;
  attribute srl_name of reset_if_r8_reg_srl8 : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 ";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  app_zq_r_reg <= \^app_zq_r_reg\;
  cnt_pwron_cke_done_r <= \^cnt_pwron_cke_done_r\;
  \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0) <= \^gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0);
  \my_empty_reg[7]_0\ <= \^my_empty_reg[7]_0\;
  \my_empty_reg[7]_1\ <= \^my_empty_reg[7]_1\;
  \my_empty_reg[7]_10\ <= \^my_empty_reg[7]_10\;
  \my_empty_reg[7]_11\ <= \^my_empty_reg[7]_11\;
  \my_empty_reg[7]_12\ <= \^my_empty_reg[7]_12\;
  \my_empty_reg[7]_13\ <= \^my_empty_reg[7]_13\;
  \my_empty_reg[7]_14\ <= \^my_empty_reg[7]_14\;
  \my_empty_reg[7]_15\ <= \^my_empty_reg[7]_15\;
  \my_empty_reg[7]_16\ <= \^my_empty_reg[7]_16\;
  \my_empty_reg[7]_17\ <= \^my_empty_reg[7]_17\;
  \my_empty_reg[7]_18\ <= \^my_empty_reg[7]_18\;
  \my_empty_reg[7]_2\ <= \^my_empty_reg[7]_2\;
  \my_empty_reg[7]_3\ <= \^my_empty_reg[7]_3\;
  \my_empty_reg[7]_4\ <= \^my_empty_reg[7]_4\;
  \my_empty_reg[7]_5\ <= \^my_empty_reg[7]_5\;
  \my_empty_reg[7]_6\ <= \^my_empty_reg[7]_6\;
  \my_empty_reg[7]_7\ <= \^my_empty_reg[7]_7\;
  \my_empty_reg[7]_8\ <= \^my_empty_reg[7]_8\;
  \my_empty_reg[7]_9\ <= \^my_empty_reg[7]_9\;
  \phy_ctl_wd_i1_reg[0]\ <= \^phy_ctl_wd_i1_reg[0]\;
  phy_if_reset <= \^phy_if_reset\;
  \rd_ptr_timing_reg[0]\ <= \^rd_ptr_timing_reg[0]\;
  \rd_ptr_timing_reg[0]_0\ <= \^rd_ptr_timing_reg[0]_0\;
  rdlvl_stg1_start_r_reg <= \^rdlvl_stg1_start_r_reg\;
\calib_sel[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF4"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      O => \calib_sel[0]_i_2_n_0\
    );
\calib_sel[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF4"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      O => \calib_sel[1]_i_2_n_0\
    );
\calib_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr_phy_tempmon_0_n_9,
      Q => \^q\(0),
      R => '0'
    );
\calib_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr_phy_tempmon_0_n_8,
      Q => \^q\(1),
      R => '0'
    );
\calib_sel_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr_phy_tempmon_0_n_7,
      Q => \^q\(2),
      R => '0'
    );
\calib_sel_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ddr_phy_tempmon_0_n_6,
      Q => \^q\(3),
      R => '0'
    );
\calib_zero_inputs[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      O => \calib_zero_inputs[1]_i_2_n_0\
    );
\calib_zero_inputs[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1F"
    )
        port map (
      I0 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      I1 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      I2 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      I3 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      O => \calib_zero_inputs[2]_i_4_n_0\
    );
\calib_zero_inputs_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_11\,
      Q => calib_zero_inputs(0),
      R => '0'
    );
\calib_zero_inputs_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_10\,
      Q => calib_zero_inputs(1),
      R => '0'
    );
\calib_zero_inputs_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_9\,
      Q => calib_zero_inputs(2),
      R => '0'
    );
ddr_phy_tempmon_0: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_tempmon
     port map (
      CLK => CLK,
      D(3) => ddr_phy_tempmon_0_n_6,
      D(2) => ddr_phy_tempmon_0_n_7,
      D(1) => ddr_phy_tempmon_0_n_8,
      D(0) => ddr_phy_tempmon_0_n_9,
      E(0) => ddr_phy_tempmon_0_n_2,
      Q(3) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      Q(2) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      Q(1) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      Q(0) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      calib_complete => calib_complete,
      \calib_sel_reg[0]\ => ddr_phy_tempmon_0_n_10,
      ck_addr_cmd_delay_done => ck_addr_cmd_delay_done,
      ctl_lane_sel => ctl_lane_sel,
      \device_temp_r_reg[11]\(11 downto 0) => \device_temp_r_reg[11]\(11 downto 0),
      fine_adjust_done_r_reg => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_87\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \calib_sel[1]_i_2_n_0\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \calib_sel[0]_i_2_n_0\,
      \gen_byte_sel_div2.calib_in_common_reg\ => ddr_phy_tempmon_0_n_4,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => ddr_phy_tempmon_0_n_5,
      \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[2]\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2]\,
      rdlvl_stg1_done_reg => u_ddr_phy_rdlvl_n_8,
      \rstdiv0_sync_r1_reg_rep__13\(3 downto 0) => \rstdiv0_sync_r1_reg_rep__13\(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__15\(0) => \rstdiv0_sync_r1_reg_rep__15\(0),
      \rstdiv0_sync_r1_reg_rep__17\(0) => \rstdiv0_sync_r1_reg_rep__17\(0),
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      tempmon_pi_f_dec => tempmon_pi_f_dec,
      tempmon_pi_f_en_r0 => tempmon_pi_f_en_r0,
      tempmon_pi_f_inc => tempmon_pi_f_inc,
      tempmon_sample_en => tempmon_sample_en,
      wr_level_done_reg => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7\,
      wrcal_done_reg => u_ddr_phy_wrcal_n_3
    );
\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr\: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_dqs_found_cal_hr
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_15 => A_rst_primitives_15,
      CLK => CLK,
      D(2) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_9\,
      D(1) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_10\,
      D(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_11\,
      D_po_fine_inc108_out => D_po_fine_inc108_out,
      Q(1 downto 0) => \^q\(1 downto 0),
      SR(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_86\,
      \calib_data_offset_0_reg[0]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\,
      \calib_data_offset_0_reg[1]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57\,
      \calib_data_offset_0_reg[2]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56\,
      \calib_data_offset_0_reg[3]\(0) => rd_data_offset_ranks_0(3),
      \calib_data_offset_0_reg[4]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_55\,
      \calib_data_offset_0_reg[5]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53\,
      \calib_data_offset_1_reg[0]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_65\,
      \calib_data_offset_1_reg[1]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_64\,
      \calib_data_offset_1_reg[2]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_63\,
      \calib_data_offset_1_reg[3]\(0) => rd_data_offset_ranks_1(3),
      \calib_data_offset_1_reg[4]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62\,
      \calib_data_offset_1_reg[5]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59\,
      \calib_data_offset_2_reg[0]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_71\,
      \calib_data_offset_2_reg[1]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_70\,
      \calib_data_offset_2_reg[2]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_69\,
      \calib_data_offset_2_reg[3]\(0) => rd_data_offset_ranks_2(3),
      \calib_data_offset_2_reg[4]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_68\,
      \calib_data_offset_2_reg[5]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_66\,
      calib_in_common => calib_in_common,
      \calib_zero_inputs_reg[2]\(2 downto 0) => calib_zero_inputs(2 downto 0),
      ck_addr_cmd_delay_done => ck_addr_cmd_delay_done,
      ck_po_stg2_f_en => ck_po_stg2_f_en,
      cmd_delay_start0 => cmd_delay_start0,
      \cmd_pipe_plus.mc_data_offset_1_reg[0]\ => \cmd_pipe_plus.mc_data_offset_1_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[1]\ => \cmd_pipe_plus.mc_data_offset_1_reg[1]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0),
      \cmd_pipe_plus.mc_data_offset_1_reg[4]\ => \cmd_pipe_plus.mc_data_offset_1_reg[4]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[1]\ => \cmd_pipe_plus.mc_data_offset_2_reg[1]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0) => D(0),
      \cmd_pipe_plus.mc_data_offset_2_reg[4]\ => \cmd_pipe_plus.mc_data_offset_2_reg[4]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_reg[0]\ => \cmd_pipe_plus.mc_data_offset_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_reg[1]\ => \cmd_pipe_plus.mc_data_offset_reg[1]\,
      \cmd_pipe_plus.mc_data_offset_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_reg[3]\(0),
      \cmd_pipe_plus.mc_data_offset_reg[4]\ => \cmd_pipe_plus.mc_data_offset_reg[4]\,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0),
      ctl_lane_cnt(2 downto 0) => ctl_lane_cnt(2 downto 0),
      ctl_lane_sel => ctl_lane_sel,
      detect_pi_found_dqs => detect_pi_found_dqs,
      dqs_found_prech_req => dqs_found_prech_req,
      dqs_po_dec_done => dqs_po_dec_done,
      dqs_po_stg2_f_incdec => dqs_po_stg2_f_incdec,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \calib_zero_inputs[2]_i_4_n_0\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]\ => \calib_zero_inputs[1]_i_2_n_0\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(3) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(2) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(1) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0\(0) => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      \gen_byte_sel_div2.calib_in_common_reg\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_76\,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_87\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_85\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_84\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[2]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_82\,
      \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2]\,
      \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72\,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      ififo_rst_reg => ififo_rst_reg,
      ififo_rst_reg0 => ififo_rst_reg0,
      ififo_rst_reg_0 => ififo_rst_reg_0,
      ififo_rst_reg_1 => ififo_rst_reg_1,
      ififo_rst_reg_2 => ififo_rst_reg_2,
      ififo_rst_reg_3 => ififo_rst_reg_3,
      ififo_rst_reg_4 => ififo_rst_reg_4,
      ififo_rst_reg_5 => ififo_rst_reg_5,
      init_dqsfound_done_r2 => init_dqsfound_done_r2,
      \init_state_r_reg[1]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_74\,
      ofifo_rst_reg0 => ofifo_rst_reg0,
      ofifo_rst_reg0_5 => ofifo_rst_reg0_5,
      ofifo_rst_reg0_7 => ofifo_rst_reg0_7,
      ofifo_rst_reg0_9 => ofifo_rst_reg0_9,
      phy_if_reset => \^phy_if_reset\,
      pi_calib_done => pi_calib_done,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_73\,
      pi_dqs_found_done_r1 => pi_dqs_found_done_r1,
      pi_dqs_found_lanes(7 downto 0) => pi_dqs_found_lanes(7 downto 0),
      \pi_dqs_found_lanes_r1_reg[4]_0\ => \pi_dqs_found_lanes_r1_reg[4]_0\,
      pi_dqs_found_rank_done => pi_dqs_found_rank_done,
      pi_dqs_found_start_reg => u_ddr_phy_init_n_898,
      pi_f_dec_reg => ddr_phy_tempmon_0_n_4,
      pi_f_inc_reg => ddr_phy_tempmon_0_n_10,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_21\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_22\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_23\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_24\,
      \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_25\,
      \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_26\,
      \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_27\,
      \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_28\,
      \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_29\,
      \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_30\,
      prech_done => prech_done,
      prech_req_posedge_r_reg => u_ddr_phy_init_n_4,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_88\,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0\(0) => p_0_in(3),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_89\,
      rdlvl_stg1_done_reg => u_ddr_phy_rdlvl_n_8,
      rdlvl_stg1_done_reg_0 => ddr_phy_tempmon_0_n_5,
      \rstdiv0_sync_r1_reg_rep__1\(1 downto 0) => SR(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__12\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__12\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__17\(0) => \rstdiv0_sync_r1_reg_rep__17\(0),
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \rstdiv0_sync_r1_reg_rep__23\ => \rstdiv0_sync_r1_reg_rep__23\,
      sent_col => sent_col,
      tempmon_pi_f_dec => tempmon_pi_f_dec,
      tempmon_pi_f_inc => tempmon_pi_f_inc
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => ddr_phy_tempmon_0_n_2,
      D => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24\,
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_86\
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => ddr_phy_tempmon_0_n_2,
      D => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_23\,
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_86\
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => ddr_phy_tempmon_0_n_2,
      D => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22\,
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_86\
    );
\gen_byte_sel_div2.byte_sel_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => ddr_phy_tempmon_0_n_2,
      D => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21\,
      Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3]\,
      R => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_86\
    );
\gen_byte_sel_div2.calib_in_common_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_76\,
      Q => calib_in_common,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\gen_byte_sel_div2.ctl_lane_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_85\,
      Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\gen_byte_sel_div2.ctl_lane_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_84\,
      Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
\gen_byte_sel_div2.ctl_lane_sel_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_82\,
      Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2]\,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
idelay_ce_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ce_int,
      Q => idelay_ce_r1,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
idelay_ce_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_ce_r1,
      Q => idelay_ce,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
idelay_inc_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_inc_int,
      Q => idelay_inc_r1,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
idelay_inc_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => idelay_inc_r1,
      Q => idelay_inc,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
init_calib_complete_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => phy_dout(21),
      R => '0'
    );
init_calib_complete_reg_rep: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \my_empty_reg[7]\,
      R => '0'
    );
\init_calib_complete_reg_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__1\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_1\,
      R => '0'
    );
\init_calib_complete_reg_rep__10\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^rd_ptr_timing_reg[0]\,
      R => '0'
    );
\init_calib_complete_reg_rep__11\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^rd_ptr_timing_reg[0]_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__12\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^app_zq_r_reg\,
      R => '0'
    );
\init_calib_complete_reg_rep__13\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__13_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__14\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_10\,
      R => '0'
    );
\init_calib_complete_reg_rep__15\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_11\,
      R => '0'
    );
\init_calib_complete_reg_rep__16\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_12\,
      R => '0'
    );
\init_calib_complete_reg_rep__17\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_13\,
      R => '0'
    );
\init_calib_complete_reg_rep__18\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_14\,
      R => '0'
    );
\init_calib_complete_reg_rep__19\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_15\,
      R => '0'
    );
\init_calib_complete_reg_rep__2\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_2\,
      R => '0'
    );
\init_calib_complete_reg_rep__20\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_16\,
      R => '0'
    );
\init_calib_complete_reg_rep__21\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_17\,
      R => '0'
    );
\init_calib_complete_reg_rep__22\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_18\,
      R => '0'
    );
\init_calib_complete_reg_rep__23\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__23_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__24\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__24_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__25\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \init_calib_complete_reg_rep__25_n_0\,
      R => '0'
    );
\init_calib_complete_reg_rep__26\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^phy_ctl_wd_i1_reg[0]\,
      R => '0'
    );
\init_calib_complete_reg_rep__3\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_3\,
      R => '0'
    );
\init_calib_complete_reg_rep__4\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_4\,
      R => '0'
    );
\init_calib_complete_reg_rep__5\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_5\,
      R => '0'
    );
\init_calib_complete_reg_rep__6\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_6\,
      R => '0'
    );
\init_calib_complete_reg_rep__7\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_7\,
      R => '0'
    );
\init_calib_complete_reg_rep__8\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_8\,
      R => '0'
    );
\init_calib_complete_reg_rep__9\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => calib_complete,
      Q => \^my_empty_reg[7]_9\,
      R => '0'
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => idelay_ce,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(1),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => idelay_ce,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\
    );
\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F010"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => idelay_ce,
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC40"
    )
        port map (
      I0 => \^q\(1),
      I1 => idelay_ce,
      I2 => \^q\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^q\(1),
      I1 => idelay_ce,
      I2 => \^q\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA80"
    )
        port map (
      I0 => idelay_ce,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(0),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA08"
    )
        port map (
      I0 => idelay_ce,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\
    );
\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC08"
    )
        port map (
      I0 => \^q\(1),
      I1 => idelay_ce,
      I2 => \^q\(0),
      I3 => calib_in_common,
      I4 => calib_zero_inputs(2),
      O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\
    );
\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay\: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay
     port map (
      CLK => CLK,
      D_po_fine_enable102_out => D_po_fine_enable102_out,
      Q(1 downto 0) => \^q\(1 downto 0),
      SR(0) => SR(0),
      calib_in_common => calib_in_common,
      \calib_zero_inputs_reg[2]\(2 downto 0) => calib_zero_inputs(2 downto 0),
      ck_addr_cmd_delay_done => ck_addr_cmd_delay_done,
      cmd_delay_start0 => cmd_delay_start0,
      cmd_po_en_stg2_f => cmd_po_en_stg2_f,
      cnt_pwron_cke_done_r_reg => \^cnt_pwron_cke_done_r\,
      ctl_lane_cnt(2 downto 0) => ctl_lane_cnt(2 downto 0),
      dqs_po_dec_done => dqs_po_dec_done,
      \init_state_r_reg[0]\ => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13\,
      p_1_in => p_1_in,
      phy_mc_go => phy_mc_go,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_0\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_3\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_4\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_7\,
      \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_12\,
      \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_13\,
      \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_14\,
      \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_15\,
      \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_19\,
      \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_20\,
      po_enstg2_f(0) => po_enstg2_f(2),
      \rstdiv0_sync_r1_reg_rep__23\ => \rstdiv0_sync_r1_reg_rep__23\
    );
\mb_wrlvl_inst.u_ddr_phy_wrlvl\: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_wrlvl
     port map (
      CLK => CLK,
      D(3) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21\,
      D(2) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22\,
      D(1) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_23\,
      D(0) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24\,
      D_po_coarse_enable105_out => D_po_coarse_enable105_out,
      Q(1 downto 0) => \^q\(1 downto 0),
      SR(0) => SR(1),
      SS(0) => SS(0),
      calib_in_common => calib_in_common,
      \calib_zero_inputs_reg[2]\(2 downto 0) => calib_zero_inputs(2 downto 0),
      done_dqs_dec239_out => done_dqs_dec239_out,
      done_dqs_tap_inc => done_dqs_tap_inc,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_4\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_4\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_5\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_5\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_6\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_6\,
      dqs_po_dec_done => dqs_po_dec_done,
      dqs_po_en_stg2_f => dqs_po_en_stg2_f,
      dqs_po_en_stg2_f_reg_0 => dqs_po_en_stg2_f_reg,
      dqs_po_stg2_f_incdec => dqs_po_stg2_f_incdec,
      early1_data_reg => u_ddr_phy_wrcal_n_6,
      early2_data_reg => u_ddr_phy_wrcal_n_7,
      p_0_in => p_0_in_0,
      p_1_in => p_1_in,
      phy_mc_go => phy_mc_go,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      \po_counter_read_val_reg[0]\ => \po_counter_read_val_reg[0]\,
      \po_counter_read_val_reg[1]\ => \po_counter_read_val_reg[1]\,
      \po_counter_read_val_reg[2]\ => \po_counter_read_val_reg[2]\,
      \po_counter_read_val_reg[3]\ => \po_counter_read_val_reg[3]\,
      \po_counter_read_val_reg[4]\ => \po_counter_read_val_reg[4]\,
      \po_counter_read_val_reg[5]\ => \po_counter_read_val_reg[5]\,
      \po_counter_read_val_reg[6]\ => \po_counter_read_val_reg[6]\,
      \po_counter_read_val_reg[7]\ => \po_counter_read_val_reg[7]\,
      \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]\,
      \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_1\,
      \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_2\,
      \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_8\,
      \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_9\,
      \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_10\,
      \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_11\,
      \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_16\,
      \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_17\,
      \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_18\,
      \po_counter_read_val_reg[8]_9\ => \po_counter_read_val_reg[8]_31\,
      \po_stg2_wrcal_cnt_reg[0]\ => u_ddr_phy_rdlvl_n_107,
      \po_stg2_wrcal_cnt_reg[0]_0\ => u_ddr_phy_wrcal_n_13,
      \po_stg2_wrcal_cnt_reg[0]_1\ => u_ddr_phy_wrcal_n_19,
      \po_stg2_wrcal_cnt_reg[0]_2\ => u_ddr_phy_wrcal_n_25,
      \po_stg2_wrcal_cnt_reg[0]_3\ => u_ddr_phy_wrcal_n_22,
      \po_stg2_wrcal_cnt_reg[1]\ => u_ddr_phy_rdlvl_n_106,
      \po_stg2_wrcal_cnt_reg[1]_0\ => u_ddr_phy_wrcal_n_18,
      \po_stg2_wrcal_cnt_reg[1]_1\ => u_ddr_phy_wrcal_n_21,
      \po_stg2_wrcal_cnt_reg[1]_2\ => u_ddr_phy_wrcal_n_24,
      \po_stg2_wrcal_cnt_reg[1]_3\ => u_ddr_phy_wrcal_n_23,
      \po_stg2_wrcal_cnt_reg[2]\ => u_ddr_phy_rdlvl_n_105,
      \po_stg2_wrcal_cnt_reg[3]\(3) => po_stg2_wrcal_cnt(3),
      \po_stg2_wrcal_cnt_reg[3]\(2 downto 0) => \^gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0),
      \po_stg2_wrcal_cnt_reg[3]_0\ => u_ddr_phy_rdlvl_n_104,
      rstdiv0_sync_r1_reg_rep => rstdiv0_sync_r1_reg_rep,
      \rstdiv0_sync_r1_reg_rep__10\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__10\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__11\(0) => \rstdiv0_sync_r1_reg_rep__12\(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__23\ => \rstdiv0_sync_r1_reg_rep__23\,
      \rstdiv0_sync_r1_reg_rep__4\ => \rstdiv0_sync_r1_reg_rep__4\,
      \rstdiv0_sync_r1_reg_rep__5\ => \rstdiv0_sync_r1_reg_rep__5\,
      \rstdiv0_sync_r1_reg_rep__6\(0) => \rstdiv0_sync_r1_reg_rep__6\(0),
      \rstdiv0_sync_r1_reg_rep__8\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__8\(1 downto 0),
      wl_sm_start => wl_sm_start,
      wr_level_done_r5 => wr_level_done_r5,
      wr_lvl_start_reg => u_ddr_phy_init_n_15,
      wrlvl_byte_done => wrlvl_byte_done,
      wrlvl_byte_redo => wrlvl_byte_redo,
      wrlvl_byte_redo_r => wrlvl_byte_redo_r,
      wrlvl_byte_redo_reg => u_ddr_phy_wrcal_n_43,
      wrlvl_byte_redo_reg_0 => u_ddr_phy_wrcal_n_27,
      wrlvl_done_r_reg => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7\,
      wrlvl_rank_done => wrlvl_rank_done
    );
\mem_reg_0_15_0_5_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(95),
      O => mux_wrdata(95)
    );
\mem_reg_0_15_0_5_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(71),
      O => mux_wrdata(71)
    );
\mem_reg_0_15_0_5_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(63),
      O => mux_wrdata(63)
    );
\mem_reg_0_15_12_17_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(86),
      O => mux_wrdata(86)
    );
\mem_reg_0_15_12_17_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(78),
      O => mux_wrdata(78)
    );
\mem_reg_0_15_12_17_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(54),
      O => mux_wrdata(54)
    );
\mem_reg_0_15_12_17_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(46),
      O => mux_wrdata(46)
    );
\mem_reg_0_15_12_17_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(38),
      O => mux_wrdata(38)
    );
mem_reg_0_15_18_23_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(238),
      O => mux_wrdata(238)
    );
\mem_reg_0_15_18_23_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(220),
      O => mux_wrdata(220)
    );
\mem_reg_0_15_18_23_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(214),
      O => mux_wrdata(214)
    );
\mem_reg_0_15_24_29_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(232),
      O => mux_wrdata(232)
    );
\mem_reg_0_15_24_29_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(226),
      O => mux_wrdata(226)
    );
\mem_reg_0_15_24_29_i_6__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_15\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(208),
      O => mux_wrdata(208)
    );
\mem_reg_0_15_24_29_i_6__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_15\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(202),
      O => mux_wrdata(202)
    );
\mem_reg_0_15_24_29_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_15\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(196),
      O => mux_wrdata(196)
    );
mem_reg_0_15_30_35_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25_n_0\,
      I1 => mc_cas_n(0),
      O => phy_dout(19)
    );
\mem_reg_0_15_30_35_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(412),
      O => mux_wrdata(412)
    );
\mem_reg_0_15_30_35_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(388),
      O => mux_wrdata(388)
    );
\mem_reg_0_15_30_35_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(380),
      O => mux_wrdata(380)
    );
mem_reg_0_15_30_35_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25_n_0\,
      I1 => mc_address(11),
      O => phy_dout(12)
    );
\mem_reg_0_15_30_35_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25_n_0\,
      I1 => mc_address(36),
      O => phy_dout(13)
    );
\mem_reg_0_15_30_35_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(91),
      O => mux_wrdata(91)
    );
\mem_reg_0_15_30_35_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(67),
      O => mux_wrdata(67)
    );
\mem_reg_0_15_30_35_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(59),
      O => mux_wrdata(59)
    );
\mem_reg_0_15_36_41_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(404),
      O => mux_wrdata(404)
    );
\mem_reg_0_15_36_41_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(396),
      O => mux_wrdata(396)
    );
\mem_reg_0_15_36_41_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(372),
      O => mux_wrdata(372)
    );
\mem_reg_0_15_36_41_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(364),
      O => mux_wrdata(364)
    );
\mem_reg_0_15_36_41_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(356),
      O => mux_wrdata(356)
    );
mem_reg_0_15_36_41_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(90),
      O => mux_wrdata(90)
    );
\mem_reg_0_15_36_41_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(75),
      O => mux_wrdata(75)
    );
\mem_reg_0_15_36_41_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(66),
      O => mux_wrdata(66)
    );
\mem_reg_0_15_36_41_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(58),
      O => mux_wrdata(58)
    );
\mem_reg_0_15_36_41_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(43),
      O => mux_wrdata(43)
    );
\mem_reg_0_15_36_41_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(35),
      O => mux_wrdata(35)
    );
\mem_reg_0_15_36_41_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(430),
      O => mux_wrdata_mask(14)
    );
\mem_reg_0_15_36_41_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(426),
      O => mux_wrdata_mask(10)
    );
\mem_reg_0_15_36_41_i_6__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(422),
      O => mux_wrdata_mask(6)
    );
\mem_reg_0_15_36_41_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^app_zq_r_reg\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(418),
      O => mux_wrdata_mask(2)
    );
\mem_reg_0_15_42_47_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(446),
      O => mux_wrdata_mask(30)
    );
\mem_reg_0_15_42_47_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(442),
      O => mux_wrdata_mask(26)
    );
\mem_reg_0_15_42_47_i_2__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(438),
      O => mux_wrdata_mask(22)
    );
\mem_reg_0_15_42_47_i_2__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(434),
      O => mux_wrdata_mask(18)
    );
\mem_reg_0_15_42_47_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25_n_0\,
      I1 => mc_address(13),
      O => phy_dout(18)
    );
\mem_reg_0_15_42_47_i_3__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(462),
      O => mux_wrdata_mask(46)
    );
\mem_reg_0_15_42_47_i_3__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(458),
      O => mux_wrdata_mask(42)
    );
\mem_reg_0_15_42_47_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__25_n_0\,
      I1 => mc_address(38),
      O => phy_dout(20)
    );
\mem_reg_0_15_42_47_i_4__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(454),
      O => mux_wrdata_mask(38)
    );
\mem_reg_0_15_42_47_i_4__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(450),
      O => mux_wrdata_mask(34)
    );
\mem_reg_0_15_42_47_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(478),
      O => mux_wrdata_mask(62)
    );
\mem_reg_0_15_42_47_i_5__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(474),
      O => mux_wrdata_mask(58)
    );
\mem_reg_0_15_42_47_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(470),
      O => mux_wrdata_mask(54)
    );
\mem_reg_0_15_42_47_i_6__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(466),
      O => mux_wrdata_mask(50)
    );
\mem_reg_0_15_48_53_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(83),
      O => mux_wrdata(83)
    );
\mem_reg_0_15_48_53_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(74),
      O => mux_wrdata(74)
    );
\mem_reg_0_15_48_53_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(51),
      O => mux_wrdata(51)
    );
\mem_reg_0_15_48_53_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(42),
      O => mux_wrdata(42)
    );
\mem_reg_0_15_48_53_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(34),
      O => mux_wrdata(34)
    );
\mem_reg_0_15_48_53_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(235),
      O => mux_wrdata(235)
    );
\mem_reg_0_15_48_53_i_6__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(217),
      O => mux_wrdata(217)
    );
\mem_reg_0_15_48_53_i_6__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_15\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(211),
      O => mux_wrdata(211)
    );
\mem_reg_0_15_54_59_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(82),
      O => mux_wrdata(82)
    );
\mem_reg_0_15_54_59_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(50),
      O => mux_wrdata(50)
    );
\mem_reg_0_15_60_65_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(223),
      O => mux_wrdata(223)
    );
\mem_reg_0_15_60_65_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_15\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(199),
      O => mux_wrdata(199)
    );
\mem_reg_0_15_60_65_i_2__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_15\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(193),
      O => mux_wrdata(193)
    );
mem_reg_0_15_60_65_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(408),
      O => mux_wrdata(408)
    );
\mem_reg_0_15_60_65_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(384),
      O => mux_wrdata(384)
    );
\mem_reg_0_15_60_65_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(376),
      O => mux_wrdata(376)
    );
mem_reg_0_15_66_71_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_16\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(229),
      O => mux_wrdata(229)
    );
\mem_reg_0_15_66_71_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_15\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(205),
      O => mux_wrdata(205)
    );
\mem_reg_0_15_66_71_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(392),
      O => mux_wrdata(392)
    );
\mem_reg_0_15_66_71_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(360),
      O => mux_wrdata(360)
    );
\mem_reg_0_15_66_71_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(352),
      O => mux_wrdata(352)
    );
\mem_reg_0_15_6_11_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(87),
      O => mux_wrdata(87)
    );
\mem_reg_0_15_6_11_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(79),
      O => mux_wrdata(79)
    );
\mem_reg_0_15_6_11_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(55),
      O => mux_wrdata(55)
    );
\mem_reg_0_15_6_11_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(47),
      O => mux_wrdata(47)
    );
\mem_reg_0_15_6_11_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_11\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(39),
      O => mux_wrdata(39)
    );
\mem_reg_0_15_6_11_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(94),
      O => mux_wrdata(94)
    );
\mem_reg_0_15_6_11_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(70),
      O => mux_wrdata(70)
    );
\mem_reg_0_15_6_11_i_3__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_12\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(62),
      O => mux_wrdata(62)
    );
\mem_reg_0_15_72_77_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(431),
      O => mux_wrdata_mask(15)
    );
\mem_reg_0_15_72_77_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(429),
      O => mux_wrdata_mask(13)
    );
\mem_reg_0_15_72_77_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(428),
      O => mux_wrdata_mask(12)
    );
\mem_reg_0_15_72_77_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(427),
      O => mux_wrdata_mask(11)
    );
\mem_reg_0_15_72_77_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(425),
      O => mux_wrdata_mask(9)
    );
\mem_reg_0_15_72_77_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(424),
      O => mux_wrdata_mask(8)
    );
\mem_reg_0_15_72_77_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(423),
      O => mux_wrdata_mask(7)
    );
\mem_reg_0_15_72_77_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(421),
      O => mux_wrdata_mask(5)
    );
\mem_reg_0_15_72_77_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(420),
      O => mux_wrdata_mask(4)
    );
\mem_reg_0_15_72_77_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^app_zq_r_reg\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(419),
      O => mux_wrdata_mask(3)
    );
\mem_reg_0_15_72_77_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^app_zq_r_reg\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(417),
      O => mux_wrdata_mask(1)
    );
\mem_reg_0_15_72_77_i_2__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^app_zq_r_reg\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(416),
      O => mux_wrdata_mask(0)
    );
\mem_reg_0_15_72_77_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(447),
      O => mux_wrdata_mask(31)
    );
\mem_reg_0_15_72_77_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(445),
      O => mux_wrdata_mask(29)
    );
\mem_reg_0_15_72_77_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(444),
      O => mux_wrdata_mask(28)
    );
\mem_reg_0_15_72_77_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(443),
      O => mux_wrdata_mask(27)
    );
\mem_reg_0_15_72_77_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(441),
      O => mux_wrdata_mask(25)
    );
\mem_reg_0_15_72_77_i_3__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(440),
      O => mux_wrdata_mask(24)
    );
\mem_reg_0_15_72_77_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(439),
      O => mux_wrdata_mask(23)
    );
\mem_reg_0_15_72_77_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(437),
      O => mux_wrdata_mask(21)
    );
\mem_reg_0_15_72_77_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(436),
      O => mux_wrdata_mask(20)
    );
\mem_reg_0_15_72_77_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(435),
      O => mux_wrdata_mask(19)
    );
\mem_reg_0_15_72_77_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(433),
      O => mux_wrdata_mask(17)
    );
\mem_reg_0_15_72_77_i_4__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(432),
      O => mux_wrdata_mask(16)
    );
\mem_reg_0_15_72_77_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(463),
      O => mux_wrdata_mask(47)
    );
\mem_reg_0_15_72_77_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(461),
      O => mux_wrdata_mask(45)
    );
\mem_reg_0_15_72_77_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(460),
      O => mux_wrdata_mask(44)
    );
\mem_reg_0_15_72_77_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(459),
      O => mux_wrdata_mask(43)
    );
\mem_reg_0_15_72_77_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(457),
      O => mux_wrdata_mask(41)
    );
\mem_reg_0_15_72_77_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(456),
      O => mux_wrdata_mask(40)
    );
\mem_reg_0_15_72_77_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(455),
      O => mux_wrdata_mask(39)
    );
\mem_reg_0_15_72_77_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(453),
      O => mux_wrdata_mask(37)
    );
\mem_reg_0_15_72_77_i_6__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(452),
      O => mux_wrdata_mask(36)
    );
\mem_reg_0_15_72_77_i_6__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(451),
      O => mux_wrdata_mask(35)
    );
\mem_reg_0_15_72_77_i_6__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(449),
      O => mux_wrdata_mask(33)
    );
\mem_reg_0_15_72_77_i_6__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(448),
      O => mux_wrdata_mask(32)
    );
mem_reg_0_15_78_79_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__24_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(400),
      O => mux_wrdata(400)
    );
\mem_reg_0_15_78_79_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__23_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(368),
      O => mux_wrdata(368)
    );
\mem_reg_0_15_78_79_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(479),
      O => mux_wrdata_mask(63)
    );
\mem_reg_0_15_78_79_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(477),
      O => mux_wrdata_mask(61)
    );
\mem_reg_0_15_78_79_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(476),
      O => mux_wrdata_mask(60)
    );
\mem_reg_0_15_78_79_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(475),
      O => mux_wrdata_mask(59)
    );
\mem_reg_0_15_78_79_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(473),
      O => mux_wrdata_mask(57)
    );
\mem_reg_0_15_78_79_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(472),
      O => mux_wrdata_mask(56)
    );
\mem_reg_0_15_78_79_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(471),
      O => mux_wrdata_mask(55)
    );
\mem_reg_0_15_78_79_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^my_empty_reg[7]_10\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(469),
      O => mux_wrdata_mask(53)
    );
\mem_reg_0_15_78_79_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(468),
      O => mux_wrdata_mask(52)
    );
\mem_reg_0_15_78_79_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(467),
      O => mux_wrdata_mask(51)
    );
\mem_reg_0_15_78_79_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(465),
      O => mux_wrdata_mask(49)
    );
\mem_reg_0_15_78_79_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__13_n_0\,
      I1 => \write_buffer.wr_buf_out_data_reg[575]\(464),
      O => mux_wrdata_mask(48)
    );
\periodic_read_request.periodic_rd_r_lcl_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^app_zq_r_reg\,
      O => \maint_prescaler.maint_prescaler_r1\
    );
\phaser_in_gen.phaser_in_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F1"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(1),
      O => \pi_dqs_found_lanes_r1_reg[4]\
    );
\phaser_in_gen.phaser_in_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F1"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \pi_dqs_found_lanes_r1_reg[0]\
    );
\phaser_in_gen.phaser_in_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F8"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \pi_dqs_found_lanes_r1_reg[3]\
    );
\phaser_in_gen.phaser_in_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \pi_dqs_found_lanes_r1_reg[2]\
    );
\phaser_in_gen.phaser_in_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(0),
      O => \pi_dqs_found_lanes_r1_reg[1]\
    );
\phaser_in_gen.phaser_in_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F1"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(2),
      O => \pi_dqs_found_lanes_r1_reg[8]\
    );
\phaser_in_gen.phaser_in_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(2),
      O => \pi_dqs_found_lanes_r1_reg[10]\
    );
\phaser_in_gen.phaser_in_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F2"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => calib_in_common,
      I3 => calib_zero_inputs(2),
      O => \pi_dqs_found_lanes_r1_reg[9]\
    );
\phaser_out_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => calib_in_common,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => calib_zero_inputs(1),
      O => D_po_counter_read_en117_out
    );
\phaser_out_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => calib_in_common,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => calib_zero_inputs(1),
      O => \po_counter_read_val_reg[8]_5\
    );
\phaser_out_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => calib_in_common,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => calib_zero_inputs(1),
      O => \po_counter_read_val_reg[8]_6\
    );
phy_if_reset0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => reset_if,
      I1 => phy_if_reset_w,
      I2 => wrlvl_final_if_rst,
      O => \phy_if_reset0__0\
    );
phy_if_reset_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \phy_if_reset0__0\,
      Q => \^phy_if_reset\,
      R => '0'
    );
\pi_counter_read_val[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => COUNTERREADVAL(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \pi_counter_read_val_reg[5]\(0)
    );
\pi_counter_read_val[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => COUNTERREADVAL(1),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \pi_counter_read_val_reg[5]\(1)
    );
\pi_counter_read_val[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => COUNTERREADVAL(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \pi_counter_read_val_reg[5]\(2)
    );
\pi_counter_read_val[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => COUNTERREADVAL(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \pi_counter_read_val_reg[5]\(3)
    );
\pi_counter_read_val[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => COUNTERREADVAL(4),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \pi_counter_read_val_reg[5]\(4)
    );
\pi_counter_read_val[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => COUNTERREADVAL(5),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \pi_counter_read_val_reg[5]\(5)
    );
po_en_stg2_f0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cmd_po_en_stg2_f,
      I1 => ck_po_stg2_f_en,
      I2 => dqs_po_en_stg2_f,
      O => po_enstg2_f(2)
    );
reset_if_r8_reg_srl8: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => CLK,
      D => reset_if,
      Q => reset_if_r8_reg_srl8_n_0
    );
reset_if_r9_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reset_if_r8_reg_srl8_n_0,
      Q => reset_if_r9,
      R => '0'
    );
reset_if_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => u_ddr_phy_init_n_896,
      Q => reset_if,
      R => '0'
    );
tempmon_pi_f_en_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tempmon_pi_f_en_r0,
      Q => tempmon_pi_f_en_r,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
tempmon_pi_f_inc_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tempmon_pi_f_inc,
      Q => tempmon_pi_f_inc_r,
      R => \rstdiv0_sync_r1_reg_rep__4\
    );
u_ddr_phy_init: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_init
     port map (
      CLK => CLK,
      D(3) => u_ddr_phy_rdlvl_n_94,
      D(2) => u_ddr_phy_rdlvl_n_95,
      D(1) => u_ddr_phy_rdlvl_n_96,
      D(0) => u_ddr_phy_rdlvl_n_97,
      D0(0) => D0(0),
      D1(3 downto 0) => D1(3 downto 0),
      D2(3 downto 0) => D2(3 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D4(3 downto 0) => D4(3 downto 0),
      D5(1 downto 0) => D5(1 downto 0),
      D6(0) => D6(0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D9(3 downto 0) => D9(3 downto 0),
      E(0) => u_ddr_phy_rdlvl_n_100,
      cal1_state_r1536_out => cal1_state_r1536_out,
      \calib_cke_reg[0]_0\ => \^cnt_pwron_cke_done_r\,
      calib_complete => calib_complete,
      ck_addr_cmd_delay_done => ck_addr_cmd_delay_done,
      \cmd_pipe_plus.mc_data_offset_1_reg[0]\ => \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_1_reg[1]\ => \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\,
      \cmd_pipe_plus.mc_data_offset_1_reg[2]\ => \cmd_pipe_plus.mc_data_offset_1_reg[2]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\(0),
      \cmd_pipe_plus.mc_data_offset_1_reg[4]\ => \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\ => \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[1]\ => \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[2]\ => \cmd_pipe_plus.mc_data_offset_2_reg[2]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0),
      \cmd_pipe_plus.mc_data_offset_2_reg[4]\ => \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\ => \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[0]\ => \cmd_pipe_plus.mc_data_offset_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[1]\ => \cmd_pipe_plus.mc_data_offset_reg[1]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[2]\ => \cmd_pipe_plus.mc_data_offset_reg[2]\,
      \cmd_pipe_plus.mc_data_offset_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0),
      \cmd_pipe_plus.mc_data_offset_reg[4]\ => \cmd_pipe_plus.mc_data_offset_reg[4]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[5]\ => \cmd_pipe_plus.mc_data_offset_reg[5]_0\,
      \cmd_pipe_plus.mc_we_n_reg[1]\(0) => \cmd_pipe_plus.mc_we_n_reg[1]\(0),
      \complex_row1_rd_cnt_reg[1]_0\ => \complex_row1_rd_cnt_reg[1]\,
      \data_offset_1_i1_reg[5]\(5 downto 0) => \data_offset_1_i1_reg[5]\(5 downto 0),
      \data_offset_2_i1_reg[5]\(5 downto 0) => \data_offset_2_i1_reg[5]\(5 downto 0),
      ddr3_lm_done_r => ddr3_lm_done_r,
      delay_done_r4_reg => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13\,
      detect_pi_found_dqs => detect_pi_found_dqs,
      done_dqs_tap_inc => done_dqs_tap_inc,
      dqs_found_done_r_reg => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_72\,
      dqs_found_prech_req => dqs_found_prech_req,
      dqs_found_start_r_reg => u_ddr_phy_init_n_898,
      \en_cnt_div4.enable_wrlvl_cnt_reg[3]_0\ => \en_cnt_div4.enable_wrlvl_cnt_reg[3]\,
      first_rdlvl_pat_r => first_rdlvl_pat_r,
      first_wrcal_pat_r => first_wrcal_pat_r,
      in0 => in0,
      init_calib_complete_reg_0(15 downto 0) => init_calib_complete_reg_0(15 downto 0),
      \init_calib_complete_reg_rep__0\ => \^my_empty_reg[7]_0\,
      \init_calib_complete_reg_rep__1\ => \^my_empty_reg[7]_1\,
      \init_calib_complete_reg_rep__10\ => \^rd_ptr_timing_reg[0]\,
      \init_calib_complete_reg_rep__11\ => \^rd_ptr_timing_reg[0]_0\,
      \init_calib_complete_reg_rep__12\ => \^app_zq_r_reg\,
      \init_calib_complete_reg_rep__14\ => \^my_empty_reg[7]_10\,
      \init_calib_complete_reg_rep__15\ => \^my_empty_reg[7]_11\,
      \init_calib_complete_reg_rep__16\ => \^my_empty_reg[7]_12\,
      \init_calib_complete_reg_rep__17\ => \^my_empty_reg[7]_13\,
      \init_calib_complete_reg_rep__18\ => \^my_empty_reg[7]_14\,
      \init_calib_complete_reg_rep__19\ => \^my_empty_reg[7]_15\,
      \init_calib_complete_reg_rep__2\ => \^my_empty_reg[7]_2\,
      \init_calib_complete_reg_rep__20\ => \^my_empty_reg[7]_16\,
      \init_calib_complete_reg_rep__21\ => \^my_empty_reg[7]_17\,
      \init_calib_complete_reg_rep__22\ => \^my_empty_reg[7]_18\,
      \init_calib_complete_reg_rep__23\ => \init_calib_complete_reg_rep__23_n_0\,
      \init_calib_complete_reg_rep__24\ => \init_calib_complete_reg_rep__24_n_0\,
      \init_calib_complete_reg_rep__25\ => \init_calib_complete_reg_rep__25_n_0\,
      \init_calib_complete_reg_rep__26\ => \^phy_ctl_wd_i1_reg[0]\,
      \init_calib_complete_reg_rep__3\ => \^my_empty_reg[7]_3\,
      \init_calib_complete_reg_rep__4\ => \^my_empty_reg[7]_4\,
      \init_calib_complete_reg_rep__5\ => \^my_empty_reg[7]_5\,
      \init_calib_complete_reg_rep__6\ => \^my_empty_reg[7]_6\,
      \init_calib_complete_reg_rep__7\ => \^my_empty_reg[7]_7\,
      \init_calib_complete_reg_rep__8\ => \^my_empty_reg[7]_8\,
      \init_calib_complete_reg_rep__9\ => \^my_empty_reg[7]_9\,
      init_dqsfound_done_r2 => init_dqsfound_done_r2,
      mc_address(34) => mc_address(37),
      mc_address(33 downto 12) => mc_address(35 downto 14),
      mc_address(11) => mc_address(12),
      mc_address(10 downto 0) => mc_address(10 downto 0),
      mc_bank(8 downto 0) => mc_bank(8 downto 0),
      mc_cas_n(0) => mc_cas_n(0),
      mc_cke(0) => mc_cke(0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(0) => mc_ras_n(0),
      mc_wrdata_en => mc_wrdata_en,
      mem_init_done_r => mem_init_done_r,
      mem_out(10 downto 0) => mem_out(10 downto 0),
      mpr_rdlvl_start_r => mpr_rdlvl_start_r,
      mpr_rdlvl_start_r_reg => u_ddr_phy_init_n_451,
      mux_reset_n => mux_reset_n,
      mux_wrdata(351 downto 349) => mux_wrdata(415 downto 413),
      mux_wrdata(348 downto 346) => mux_wrdata(411 downto 409),
      mux_wrdata(345 downto 343) => mux_wrdata(407 downto 405),
      mux_wrdata(342 downto 340) => mux_wrdata(403 downto 401),
      mux_wrdata(339 downto 337) => mux_wrdata(399 downto 397),
      mux_wrdata(336 downto 334) => mux_wrdata(395 downto 393),
      mux_wrdata(333 downto 331) => mux_wrdata(391 downto 389),
      mux_wrdata(330 downto 328) => mux_wrdata(387 downto 385),
      mux_wrdata(327 downto 325) => mux_wrdata(383 downto 381),
      mux_wrdata(324 downto 322) => mux_wrdata(379 downto 377),
      mux_wrdata(321 downto 319) => mux_wrdata(375 downto 373),
      mux_wrdata(318 downto 316) => mux_wrdata(371 downto 369),
      mux_wrdata(315 downto 313) => mux_wrdata(367 downto 365),
      mux_wrdata(312 downto 310) => mux_wrdata(363 downto 361),
      mux_wrdata(309 downto 307) => mux_wrdata(359 downto 357),
      mux_wrdata(306 downto 304) => mux_wrdata(355 downto 353),
      mux_wrdata(303 downto 191) => mux_wrdata(351 downto 239),
      mux_wrdata(190 downto 189) => mux_wrdata(237 downto 236),
      mux_wrdata(188 downto 187) => mux_wrdata(234 downto 233),
      mux_wrdata(186 downto 185) => mux_wrdata(231 downto 230),
      mux_wrdata(184 downto 183) => mux_wrdata(228 downto 227),
      mux_wrdata(182 downto 181) => mux_wrdata(225 downto 224),
      mux_wrdata(180 downto 179) => mux_wrdata(222 downto 221),
      mux_wrdata(178 downto 177) => mux_wrdata(219 downto 218),
      mux_wrdata(176 downto 175) => mux_wrdata(216 downto 215),
      mux_wrdata(174 downto 173) => mux_wrdata(213 downto 212),
      mux_wrdata(172 downto 171) => mux_wrdata(210 downto 209),
      mux_wrdata(170 downto 169) => mux_wrdata(207 downto 206),
      mux_wrdata(168 downto 167) => mux_wrdata(204 downto 203),
      mux_wrdata(166 downto 165) => mux_wrdata(201 downto 200),
      mux_wrdata(164 downto 163) => mux_wrdata(198 downto 197),
      mux_wrdata(162 downto 161) => mux_wrdata(195 downto 194),
      mux_wrdata(160 downto 64) => mux_wrdata(192 downto 96),
      mux_wrdata(63 downto 62) => mux_wrdata(93 downto 92),
      mux_wrdata(61 downto 60) => mux_wrdata(89 downto 88),
      mux_wrdata(59 downto 58) => mux_wrdata(85 downto 84),
      mux_wrdata(57 downto 56) => mux_wrdata(81 downto 80),
      mux_wrdata(55 downto 54) => mux_wrdata(77 downto 76),
      mux_wrdata(53 downto 52) => mux_wrdata(73 downto 72),
      mux_wrdata(51 downto 50) => mux_wrdata(69 downto 68),
      mux_wrdata(49 downto 48) => mux_wrdata(65 downto 64),
      mux_wrdata(47 downto 46) => mux_wrdata(61 downto 60),
      mux_wrdata(45 downto 44) => mux_wrdata(57 downto 56),
      mux_wrdata(43 downto 42) => mux_wrdata(53 downto 52),
      mux_wrdata(41 downto 40) => mux_wrdata(49 downto 48),
      mux_wrdata(39 downto 38) => mux_wrdata(45 downto 44),
      mux_wrdata(37 downto 36) => mux_wrdata(41 downto 40),
      mux_wrdata(35 downto 34) => mux_wrdata(37 downto 36),
      mux_wrdata(33 downto 0) => mux_wrdata(33 downto 0),
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\,
      \my_empty_reg[1]_3\ => \my_empty_reg[1]_3\,
      \my_empty_reg[1]_4\ => \my_empty_reg[1]_4\,
      \my_empty_reg[1]_5\ => \my_empty_reg[1]_5\,
      \my_empty_reg[1]_6\ => \my_empty_reg[1]_6\,
      \my_empty_reg[1]_7\ => \my_empty_reg[1]_7\,
      \my_empty_reg[1]_8\ => \my_empty_reg[1]_8\,
      \my_empty_reg[1]_9\ => \my_empty_reg[1]_9\,
      \my_empty_reg[7]\(4 downto 0) => \my_empty_reg[7]_19\(4 downto 0),
      \my_empty_reg[7]_0\(4 downto 0) => \my_empty_reg[7]_20\(4 downto 0),
      \my_empty_reg[7]_1\(5 downto 0) => \my_empty_reg[7]_21\(5 downto 0),
      \my_empty_reg[7]_10\(5 downto 0) => \my_empty_reg[7]_30\(5 downto 0),
      \my_empty_reg[7]_11\(4 downto 0) => \my_empty_reg[7]_31\(4 downto 0),
      \my_empty_reg[7]_12\(4 downto 0) => \my_empty_reg[7]_32\(4 downto 0),
      \my_empty_reg[7]_13\(5 downto 0) => \my_empty_reg[7]_33\(5 downto 0),
      \my_empty_reg[7]_14\(4 downto 0) => \my_empty_reg[7]_34\(4 downto 0),
      \my_empty_reg[7]_15\(4 downto 0) => \my_empty_reg[7]_35\(4 downto 0),
      \my_empty_reg[7]_16\(5 downto 0) => \my_empty_reg[7]_36\(5 downto 0),
      \my_empty_reg[7]_17\(4 downto 0) => \my_empty_reg[7]_37\(4 downto 0),
      \my_empty_reg[7]_18\(4 downto 0) => \my_empty_reg[7]_38\(4 downto 0),
      \my_empty_reg[7]_19\(5 downto 0) => \my_empty_reg[7]_39\(5 downto 0),
      \my_empty_reg[7]_2\(4 downto 0) => \my_empty_reg[7]_22\(4 downto 0),
      \my_empty_reg[7]_20\(4 downto 0) => \my_empty_reg[7]_40\(4 downto 0),
      \my_empty_reg[7]_21\(4 downto 0) => \my_empty_reg[7]_41\(4 downto 0),
      \my_empty_reg[7]_22\(5 downto 0) => \my_empty_reg[7]_42\(5 downto 0),
      \my_empty_reg[7]_23\(4 downto 0) => \my_empty_reg[7]_43\(4 downto 0),
      \my_empty_reg[7]_24\(4 downto 0) => \my_empty_reg[7]_44\(4 downto 0),
      \my_empty_reg[7]_25\(5 downto 0) => \my_empty_reg[7]_45\(5 downto 0),
      \my_empty_reg[7]_26\(4 downto 0) => \my_empty_reg[7]_46\(4 downto 0),
      \my_empty_reg[7]_27\(4 downto 0) => \my_empty_reg[7]_47\(4 downto 0),
      \my_empty_reg[7]_28\(5 downto 0) => \my_empty_reg[7]_48\(5 downto 0),
      \my_empty_reg[7]_29\(4 downto 0) => \my_empty_reg[7]_49\(4 downto 0),
      \my_empty_reg[7]_3\(4 downto 0) => \my_empty_reg[7]_23\(4 downto 0),
      \my_empty_reg[7]_30\(4 downto 0) => \my_empty_reg[7]_50\(4 downto 0),
      \my_empty_reg[7]_31\(5 downto 0) => \my_empty_reg[7]_51\(5 downto 0),
      \my_empty_reg[7]_32\(4 downto 0) => \my_empty_reg[7]_52\(4 downto 0),
      \my_empty_reg[7]_33\(4 downto 0) => \my_empty_reg[7]_53\(4 downto 0),
      \my_empty_reg[7]_34\(5 downto 0) => \my_empty_reg[7]_54\(5 downto 0),
      \my_empty_reg[7]_35\(4 downto 0) => \my_empty_reg[7]_55\(4 downto 0),
      \my_empty_reg[7]_36\(4 downto 0) => \my_empty_reg[7]_56\(4 downto 0),
      \my_empty_reg[7]_37\(5 downto 0) => \my_empty_reg[7]_57\(5 downto 0),
      \my_empty_reg[7]_38\(4 downto 0) => \my_empty_reg[7]_58\(4 downto 0),
      \my_empty_reg[7]_39\(4 downto 0) => \my_empty_reg[7]_59\(4 downto 0),
      \my_empty_reg[7]_4\(5 downto 0) => \my_empty_reg[7]_24\(5 downto 0),
      \my_empty_reg[7]_40\(5 downto 0) => \my_empty_reg[7]_60\(5 downto 0),
      \my_empty_reg[7]_41\(4 downto 0) => \my_empty_reg[7]_61\(4 downto 0),
      \my_empty_reg[7]_42\(4 downto 0) => \my_empty_reg[7]_62\(4 downto 0),
      \my_empty_reg[7]_43\(5 downto 0) => \my_empty_reg[7]_63\(5 downto 0),
      \my_empty_reg[7]_44\(4 downto 0) => \my_empty_reg[7]_64\(4 downto 0),
      \my_empty_reg[7]_45\(4 downto 0) => \my_empty_reg[7]_65\(4 downto 0),
      \my_empty_reg[7]_46\(5 downto 0) => \my_empty_reg[7]_66\(5 downto 0),
      \my_empty_reg[7]_47\(5 downto 0) => \my_empty_reg[7]_67\(5 downto 0),
      \my_empty_reg[7]_48\(5 downto 0) => \my_empty_reg[7]_68\(5 downto 0),
      \my_empty_reg[7]_49\(5 downto 0) => \my_empty_reg[7]_69\(5 downto 0),
      \my_empty_reg[7]_5\(4 downto 0) => \my_empty_reg[7]_25\(4 downto 0),
      \my_empty_reg[7]_50\(5 downto 0) => \my_empty_reg[7]_70\(5 downto 0),
      \my_empty_reg[7]_51\(5 downto 0) => \my_empty_reg[7]_71\(5 downto 0),
      \my_empty_reg[7]_52\(5 downto 0) => \my_empty_reg[7]_72\(5 downto 0),
      \my_empty_reg[7]_53\(5 downto 0) => \my_empty_reg[7]_73\(5 downto 0),
      \my_empty_reg[7]_54\(5 downto 0) => \my_empty_reg[7]_74\(5 downto 0),
      \my_empty_reg[7]_55\(5 downto 0) => \my_empty_reg[7]_75\(5 downto 0),
      \my_empty_reg[7]_56\(5 downto 0) => \my_empty_reg[7]_76\(5 downto 0),
      \my_empty_reg[7]_57\(5 downto 0) => \my_empty_reg[7]_77\(5 downto 0),
      \my_empty_reg[7]_58\(5 downto 0) => \my_empty_reg[7]_78\(5 downto 0),
      \my_empty_reg[7]_59\(5 downto 0) => \my_empty_reg[7]_79\(5 downto 0),
      \my_empty_reg[7]_6\(4 downto 0) => \my_empty_reg[7]_26\(4 downto 0),
      \my_empty_reg[7]_60\(5 downto 0) => \my_empty_reg[7]_80\(5 downto 0),
      \my_empty_reg[7]_61\(5 downto 0) => \my_empty_reg[7]_81\(5 downto 0),
      \my_empty_reg[7]_62\(5 downto 0) => \my_empty_reg[7]_82\(5 downto 0),
      \my_empty_reg[7]_7\(5 downto 0) => \my_empty_reg[7]_27\(5 downto 0),
      \my_empty_reg[7]_8\(4 downto 0) => \my_empty_reg[7]_28\(4 downto 0),
      \my_empty_reg[7]_9\(4 downto 0) => \my_empty_reg[7]_29\(4 downto 0),
      \one_rank.stg1_wr_done_reg_0\ => u_ddr_phy_init_n_13,
      \out\ => \out\,
      p_110_in => p_110_in,
      phy_cmd_wr_en => phy_cmd_wr_en,
      \phy_ctl_wd_i1_reg[24]\(10 downto 0) => \phy_ctl_wd_i1_reg[24]\(10 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(15 downto 12) => phy_dout(17 downto 14),
      phy_dout(11 downto 0) => phy_dout(11 downto 0),
      phy_mc_go => phy_mc_go,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_calib_done => pi_calib_done,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_73\,
      pi_dqs_found_done_r1 => pi_dqs_found_done_r1,
      pi_dqs_found_done_r1_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53\,
      pi_dqs_found_done_r1_reg_1 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_55\,
      pi_dqs_found_done_r1_reg_10 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_66\,
      pi_dqs_found_done_r1_reg_11 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_68\,
      pi_dqs_found_done_r1_reg_12 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_69\,
      pi_dqs_found_done_r1_reg_13 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_70\,
      pi_dqs_found_done_r1_reg_14 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_71\,
      pi_dqs_found_done_r1_reg_2 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56\,
      pi_dqs_found_done_r1_reg_3 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57\,
      pi_dqs_found_done_r1_reg_4 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58\,
      pi_dqs_found_done_r1_reg_5 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59\,
      pi_dqs_found_done_r1_reg_6 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62\,
      pi_dqs_found_done_r1_reg_7 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_63\,
      pi_dqs_found_done_r1_reg_8 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_64\,
      pi_dqs_found_done_r1_reg_9 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_65\,
      pi_dqs_found_rank_done => pi_dqs_found_rank_done,
      prbs_rdlvl_done_pulse0 => prbs_rdlvl_done_pulse0,
      prbs_rdlvl_done_pulse_reg_0(0) => prbs_rdlvl_done_pulse_reg(0),
      prech_done => prech_done,
      prech_pending_r_reg_0 => u_ddr_phy_init_n_4,
      prech_req_posedge_r_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_74\,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]\(0) => rd_data_offset_ranks_0(3),
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]\(0) => rd_data_offset_ranks_1(3),
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]\(0) => rd_data_offset_ranks_2(3),
      \rd_byte_data_offset_reg[0][15]\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_89\,
      \rd_byte_data_offset_reg[0][3]\(0) => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_88\,
      \rd_byte_data_offset_reg[0][9]\(0) => p_0_in(3),
      \rd_ptr_reg[3]\(44 downto 0) => \rd_ptr_reg[3]\(44 downto 0),
      \rd_ptr_reg[3]_0\(43 downto 0) => \rd_ptr_reg[3]_0\(43 downto 0),
      \rd_ptr_reg[3]_1\(43 downto 0) => \rd_ptr_reg[3]_1\(43 downto 0),
      \rd_ptr_reg[3]_2\(43 downto 0) => \rd_ptr_reg[3]_2\(43 downto 0),
      \rd_ptr_reg[3]_3\(43 downto 0) => \rd_ptr_reg[3]_3\(43 downto 0),
      \rd_ptr_reg[3]_4\(43 downto 0) => \rd_ptr_reg[3]_4\(43 downto 0),
      \rd_ptr_reg[3]_5\(43 downto 0) => \rd_ptr_reg[3]_5\(43 downto 0),
      \rd_ptr_reg[3]_6\(43 downto 0) => \rd_ptr_reg[3]_6\(43 downto 0),
      \rd_ptr_reg[3]_7\(43 downto 0) => \rd_ptr_reg[3]_7\(43 downto 0),
      \rd_ptr_timing_reg[0]\(3 downto 0) => \rd_ptr_timing_reg[0]_1\(3 downto 0),
      \rd_ptr_timing_reg[0]_0\(3 downto 0) => \rd_ptr_timing_reg[0]_2\(3 downto 0),
      \rd_ptr_timing_reg[0]_1\(3 downto 0) => \rd_ptr_timing_reg[0]_3\(3 downto 0),
      \rd_ptr_timing_reg[0]_2\(7 downto 0) => \rd_ptr_timing_reg[0]_4\(7 downto 0),
      \rd_ptr_timing_reg[0]_3\(7 downto 0) => \rd_ptr_timing_reg[0]_5\(7 downto 0),
      \rd_ptr_timing_reg[0]_4\(3 downto 0) => \rd_ptr_timing_reg[0]_6\(3 downto 0),
      \rd_ptr_timing_reg[0]_5\(3 downto 0) => \rd_ptr_timing_reg[0]_7\(3 downto 0),
      \rd_ptr_timing_reg[0]_6\(3 downto 0) => \rd_ptr_timing_reg[0]_8\(3 downto 0),
      \rd_ptr_timing_reg[0]_7\(4 downto 0) => \rd_ptr_timing_reg[0]_9\(4 downto 0),
      \rd_ptr_timing_reg[0]_8\(44 downto 0) => \rd_ptr_timing_reg[0]_10\(44 downto 0),
      rdlvl_last_byte_done => rdlvl_last_byte_done,
      rdlvl_last_byte_done_reg => u_ddr_phy_rdlvl_n_68,
      rdlvl_prech_req => rdlvl_prech_req,
      rdlvl_stg1_done_r1 => rdlvl_stg1_done_r1,
      rdlvl_stg1_done_reg => u_ddr_phy_rdlvl_n_8,
      rdlvl_stg1_done_reg_0 => u_ddr_phy_rdlvl_n_98,
      rdlvl_stg1_done_reg_1 => u_ddr_phy_rdlvl_n_67,
      rdlvl_stg1_done_reg_2 => u_ddr_phy_rdlvl_n_99,
      rdlvl_stg1_done_reg_3 => u_ddr_phy_rdlvl_n_92,
      rdlvl_stg1_done_reg_4 => u_ddr_phy_rdlvl_n_101,
      rdlvl_stg1_rank_done => rdlvl_stg1_rank_done,
      rdlvl_stg1_start_r_reg => \^rdlvl_stg1_start_r_reg\,
      reset_if => reset_if,
      reset_if_r9 => reset_if_r9,
      reset_if_reg => u_ddr_phy_init_n_896,
      \rstdiv0_sync_r1_reg_rep__18\(0) => \rstdiv0_sync_r1_reg_rep__13\(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \rstdiv0_sync_r1_reg_rep__22\ => \rstdiv0_sync_r1_reg_rep__22\,
      \rstdiv0_sync_r1_reg_rep__22_0\ => \rstdiv0_sync_r1_reg_rep__22_0\,
      \rstdiv0_sync_r1_reg_rep__23\ => \rstdiv0_sync_r1_reg_rep__23\,
      \rstdiv0_sync_r1_reg_rep__3\(0) => \rstdiv0_sync_r1_reg_rep__2\(0),
      \rstdiv0_sync_r1_reg_rep__4\ => \rstdiv0_sync_r1_reg_rep__4\,
      stg1_wr_done => stg1_wr_done,
      wl_sm_start => wl_sm_start,
      wr_level_done_reg => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7\,
      wr_level_start_r_reg => u_ddr_phy_init_n_15,
      wrcal_done_reg => u_ddr_phy_wrcal_n_3,
      wrcal_done_reg_0 => u_ddr_phy_wrcal_n_30,
      wrcal_done_reg_1 => u_ddr_phy_wrcal_n_29,
      wrcal_prech_req => wrcal_prech_req,
      wrcal_rd_wait => wrcal_rd_wait,
      wrcal_resume_w => wrcal_resume_w,
      wrcal_sanity_chk => wrcal_sanity_chk,
      wrcal_sanity_chk_done_reg => u_ddr_phy_wrcal_n_4,
      wrcal_sanity_chk_done_reg_0 => u_ddr_phy_wrcal_n_28,
      wrcal_start_reg_0 => u_ddr_phy_init_n_897,
      \write_buffer.wr_buf_out_data_reg[511]\(351 downto 349) => \write_buffer.wr_buf_out_data_reg[575]\(415 downto 413),
      \write_buffer.wr_buf_out_data_reg[511]\(348 downto 346) => \write_buffer.wr_buf_out_data_reg[575]\(411 downto 409),
      \write_buffer.wr_buf_out_data_reg[511]\(345 downto 343) => \write_buffer.wr_buf_out_data_reg[575]\(407 downto 405),
      \write_buffer.wr_buf_out_data_reg[511]\(342 downto 340) => \write_buffer.wr_buf_out_data_reg[575]\(403 downto 401),
      \write_buffer.wr_buf_out_data_reg[511]\(339 downto 337) => \write_buffer.wr_buf_out_data_reg[575]\(399 downto 397),
      \write_buffer.wr_buf_out_data_reg[511]\(336 downto 334) => \write_buffer.wr_buf_out_data_reg[575]\(395 downto 393),
      \write_buffer.wr_buf_out_data_reg[511]\(333 downto 331) => \write_buffer.wr_buf_out_data_reg[575]\(391 downto 389),
      \write_buffer.wr_buf_out_data_reg[511]\(330 downto 328) => \write_buffer.wr_buf_out_data_reg[575]\(387 downto 385),
      \write_buffer.wr_buf_out_data_reg[511]\(327 downto 325) => \write_buffer.wr_buf_out_data_reg[575]\(383 downto 381),
      \write_buffer.wr_buf_out_data_reg[511]\(324 downto 322) => \write_buffer.wr_buf_out_data_reg[575]\(379 downto 377),
      \write_buffer.wr_buf_out_data_reg[511]\(321 downto 319) => \write_buffer.wr_buf_out_data_reg[575]\(375 downto 373),
      \write_buffer.wr_buf_out_data_reg[511]\(318 downto 316) => \write_buffer.wr_buf_out_data_reg[575]\(371 downto 369),
      \write_buffer.wr_buf_out_data_reg[511]\(315 downto 313) => \write_buffer.wr_buf_out_data_reg[575]\(367 downto 365),
      \write_buffer.wr_buf_out_data_reg[511]\(312 downto 310) => \write_buffer.wr_buf_out_data_reg[575]\(363 downto 361),
      \write_buffer.wr_buf_out_data_reg[511]\(309 downto 307) => \write_buffer.wr_buf_out_data_reg[575]\(359 downto 357),
      \write_buffer.wr_buf_out_data_reg[511]\(306 downto 304) => \write_buffer.wr_buf_out_data_reg[575]\(355 downto 353),
      \write_buffer.wr_buf_out_data_reg[511]\(303 downto 191) => \write_buffer.wr_buf_out_data_reg[575]\(351 downto 239),
      \write_buffer.wr_buf_out_data_reg[511]\(190 downto 189) => \write_buffer.wr_buf_out_data_reg[575]\(237 downto 236),
      \write_buffer.wr_buf_out_data_reg[511]\(188 downto 187) => \write_buffer.wr_buf_out_data_reg[575]\(234 downto 233),
      \write_buffer.wr_buf_out_data_reg[511]\(186 downto 185) => \write_buffer.wr_buf_out_data_reg[575]\(231 downto 230),
      \write_buffer.wr_buf_out_data_reg[511]\(184 downto 183) => \write_buffer.wr_buf_out_data_reg[575]\(228 downto 227),
      \write_buffer.wr_buf_out_data_reg[511]\(182 downto 181) => \write_buffer.wr_buf_out_data_reg[575]\(225 downto 224),
      \write_buffer.wr_buf_out_data_reg[511]\(180 downto 179) => \write_buffer.wr_buf_out_data_reg[575]\(222 downto 221),
      \write_buffer.wr_buf_out_data_reg[511]\(178 downto 177) => \write_buffer.wr_buf_out_data_reg[575]\(219 downto 218),
      \write_buffer.wr_buf_out_data_reg[511]\(176 downto 175) => \write_buffer.wr_buf_out_data_reg[575]\(216 downto 215),
      \write_buffer.wr_buf_out_data_reg[511]\(174 downto 173) => \write_buffer.wr_buf_out_data_reg[575]\(213 downto 212),
      \write_buffer.wr_buf_out_data_reg[511]\(172 downto 171) => \write_buffer.wr_buf_out_data_reg[575]\(210 downto 209),
      \write_buffer.wr_buf_out_data_reg[511]\(170 downto 169) => \write_buffer.wr_buf_out_data_reg[575]\(207 downto 206),
      \write_buffer.wr_buf_out_data_reg[511]\(168 downto 167) => \write_buffer.wr_buf_out_data_reg[575]\(204 downto 203),
      \write_buffer.wr_buf_out_data_reg[511]\(166 downto 165) => \write_buffer.wr_buf_out_data_reg[575]\(201 downto 200),
      \write_buffer.wr_buf_out_data_reg[511]\(164 downto 163) => \write_buffer.wr_buf_out_data_reg[575]\(198 downto 197),
      \write_buffer.wr_buf_out_data_reg[511]\(162 downto 161) => \write_buffer.wr_buf_out_data_reg[575]\(195 downto 194),
      \write_buffer.wr_buf_out_data_reg[511]\(160 downto 64) => \write_buffer.wr_buf_out_data_reg[575]\(192 downto 96),
      \write_buffer.wr_buf_out_data_reg[511]\(63 downto 62) => \write_buffer.wr_buf_out_data_reg[575]\(93 downto 92),
      \write_buffer.wr_buf_out_data_reg[511]\(61 downto 60) => \write_buffer.wr_buf_out_data_reg[575]\(89 downto 88),
      \write_buffer.wr_buf_out_data_reg[511]\(59 downto 58) => \write_buffer.wr_buf_out_data_reg[575]\(85 downto 84),
      \write_buffer.wr_buf_out_data_reg[511]\(57 downto 56) => \write_buffer.wr_buf_out_data_reg[575]\(81 downto 80),
      \write_buffer.wr_buf_out_data_reg[511]\(55 downto 54) => \write_buffer.wr_buf_out_data_reg[575]\(77 downto 76),
      \write_buffer.wr_buf_out_data_reg[511]\(53 downto 52) => \write_buffer.wr_buf_out_data_reg[575]\(73 downto 72),
      \write_buffer.wr_buf_out_data_reg[511]\(51 downto 50) => \write_buffer.wr_buf_out_data_reg[575]\(69 downto 68),
      \write_buffer.wr_buf_out_data_reg[511]\(49 downto 48) => \write_buffer.wr_buf_out_data_reg[575]\(65 downto 64),
      \write_buffer.wr_buf_out_data_reg[511]\(47 downto 46) => \write_buffer.wr_buf_out_data_reg[575]\(61 downto 60),
      \write_buffer.wr_buf_out_data_reg[511]\(45 downto 44) => \write_buffer.wr_buf_out_data_reg[575]\(57 downto 56),
      \write_buffer.wr_buf_out_data_reg[511]\(43 downto 42) => \write_buffer.wr_buf_out_data_reg[575]\(53 downto 52),
      \write_buffer.wr_buf_out_data_reg[511]\(41 downto 40) => \write_buffer.wr_buf_out_data_reg[575]\(49 downto 48),
      \write_buffer.wr_buf_out_data_reg[511]\(39 downto 38) => \write_buffer.wr_buf_out_data_reg[575]\(45 downto 44),
      \write_buffer.wr_buf_out_data_reg[511]\(37 downto 36) => \write_buffer.wr_buf_out_data_reg[575]\(41 downto 40),
      \write_buffer.wr_buf_out_data_reg[511]\(35 downto 34) => \write_buffer.wr_buf_out_data_reg[575]\(37 downto 36),
      \write_buffer.wr_buf_out_data_reg[511]\(33 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(33 downto 0),
      wrlvl_byte_redo => wrlvl_byte_redo,
      wrlvl_byte_redo_reg => u_ddr_phy_wrcal_n_20,
      wrlvl_done_r1 => wrlvl_done_r1,
      wrlvl_final_if_rst => wrlvl_final_if_rst,
      wrlvl_rank_done => wrlvl_rank_done
    );
u_ddr_phy_rdlvl: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_rdlvl
     port map (
      CLK => CLK,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      D(3) => u_ddr_phy_rdlvl_n_94,
      D(2) => u_ddr_phy_rdlvl_n_95,
      D(1) => u_ddr_phy_rdlvl_n_96,
      D(0) => u_ddr_phy_rdlvl_n_97,
      E(0) => rd_active_r,
      Q(1 downto 0) => \^q\(1 downto 0),
      SR(1 downto 0) => SR(1 downto 0),
      \cal1_cnt_cpt_r_reg[1]_0\ => u_ddr_phy_rdlvl_n_103,
      cal1_state_r1536_out => cal1_state_r1536_out,
      calib_in_common => calib_in_common,
      \calib_zero_inputs_reg[2]\(2 downto 0) => calib_zero_inputs(2 downto 0),
      clear => clear,
      cmd_delay_start0 => cmd_delay_start0,
      dqs_po_dec_done => dqs_po_dec_done,
      fine_dly_dec_done_r1_reg_0 => fine_dly_dec_done_r1_reg,
      first_rdlvl_pat_r => first_rdlvl_pat_r,
      first_wrcal_pat_r => first_wrcal_pat_r,
      \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => u_ddr_phy_rdlvl_n_107,
      \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => u_ddr_phy_rdlvl_n_106,
      \gen_byte_sel_div2.byte_sel_cnt_reg[2]\ => u_ddr_phy_rdlvl_n_105,
      \gen_byte_sel_div2.byte_sel_cnt_reg[3]\ => u_ddr_phy_rdlvl_n_104,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      idelay_ce_int => idelay_ce_int,
      idelay_inc_int => idelay_inc_int,
      \idelay_tap_cnt_r_reg[0][0][4]_0\ => u_ddr_phy_rdlvl_n_70,
      \idelay_tap_cnt_r_reg[0][1][4]_0\ => u_ddr_phy_rdlvl_n_72,
      \idelay_tap_cnt_r_reg[0][2][4]_0\ => u_ddr_phy_rdlvl_n_71,
      \idelay_tap_cnt_r_reg[0][3][4]_0\ => u_ddr_phy_rdlvl_n_69,
      \idelay_tap_cnt_r_reg[0][7][4]_0\ => u_ddr_phy_rdlvl_n_102,
      idelay_tap_limit_r_reg_0 => idelay_tap_limit_r_reg,
      \init_state_r_reg[2]\ => u_ddr_phy_rdlvl_n_98,
      \init_state_r_reg[4]\ => u_ddr_phy_rdlvl_n_68,
      \init_state_r_reg[4]_0\ => u_ddr_phy_rdlvl_n_92,
      \init_state_r_reg[4]_1\ => u_ddr_phy_rdlvl_n_99,
      mem_init_done_r => mem_init_done_r,
      mpr_rdlvl_start_r => mpr_rdlvl_start_r,
      mpr_rdlvl_start_reg => u_ddr_phy_init_n_451,
      new_cnt_cpt_r_reg_0(0) => new_cnt_cpt_r_reg(0),
      \one_rank.stg1_wr_done_reg\ => u_ddr_phy_init_n_13,
      pi_cnt_dec_reg_0(0) => pi_cnt_dec_reg(0),
      \pi_counter_read_val_reg[0]\ => \pi_counter_read_val_reg[0]\,
      \pi_counter_read_val_reg[1]\ => \pi_counter_read_val_reg[1]\,
      \pi_counter_read_val_reg[2]\ => \pi_counter_read_val_reg[2]\,
      \pi_counter_read_val_reg[2]_0\ => \pi_counter_read_val_reg[2]_0\,
      \pi_counter_read_val_reg[3]\ => \pi_counter_read_val_reg[3]\,
      \pi_counter_read_val_reg[4]\ => \pi_counter_read_val_reg[4]\,
      \pi_counter_read_val_reg[5]\ => \pi_counter_read_val_reg[5]_0\,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_73\,
      \pi_dqs_found_lanes_r1_reg[0]\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[0]_0\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[0]_0\ => \pi_dqs_found_lanes_r1_reg[0]_1\,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => \pi_dqs_found_lanes_r1_reg[0]_2\,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => \pi_dqs_found_lanes_r1_reg[0]_3\,
      \pi_dqs_found_lanes_r1_reg[10]\ => \pi_dqs_found_lanes_r1_reg[10]_0\,
      \pi_dqs_found_lanes_r1_reg[10]_0\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[10]_1\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[10]_1\ => \pi_dqs_found_lanes_r1_reg[10]_2\,
      \pi_dqs_found_lanes_r1_reg[10]_2\ => \pi_dqs_found_lanes_r1_reg[10]_3\,
      \pi_dqs_found_lanes_r1_reg[1]\ => \pi_dqs_found_lanes_r1_reg[1]_0\,
      \pi_dqs_found_lanes_r1_reg[1]_0\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[1]_1\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[1]_1\ => \pi_dqs_found_lanes_r1_reg[1]_2\,
      \pi_dqs_found_lanes_r1_reg[1]_2\ => \pi_dqs_found_lanes_r1_reg[1]_3\,
      \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]_0\,
      \pi_dqs_found_lanes_r1_reg[2]_0\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[2]_1\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_2\,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_3\,
      \pi_dqs_found_lanes_r1_reg[3]\ => \pi_dqs_found_lanes_r1_reg[3]_0\,
      \pi_dqs_found_lanes_r1_reg[3]_0\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_1\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[3]_1\ => \pi_dqs_found_lanes_r1_reg[3]_2\,
      \pi_dqs_found_lanes_r1_reg[3]_2\ => \pi_dqs_found_lanes_r1_reg[3]_3\,
      \pi_dqs_found_lanes_r1_reg[4]\ => \pi_dqs_found_lanes_r1_reg[4]_1\,
      \pi_dqs_found_lanes_r1_reg[4]_0\ => \pi_dqs_found_lanes_r1_reg[4]_2\,
      \pi_dqs_found_lanes_r1_reg[4]_1\ => \pi_dqs_found_lanes_r1_reg[4]_3\,
      \pi_dqs_found_lanes_r1_reg[8]\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[8]_0\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[8]_0\ => \pi_dqs_found_lanes_r1_reg[8]_1\,
      \pi_dqs_found_lanes_r1_reg[8]_1\ => \pi_dqs_found_lanes_r1_reg[8]_2\,
      \pi_dqs_found_lanes_r1_reg[8]_2\ => \pi_dqs_found_lanes_r1_reg[8]_3\,
      \pi_dqs_found_lanes_r1_reg[9]\ => \pi_dqs_found_lanes_r1_reg[9]_0\,
      \pi_dqs_found_lanes_r1_reg[9]_0\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[9]_1\(5 downto 0),
      \pi_dqs_found_lanes_r1_reg[9]_1\ => \pi_dqs_found_lanes_r1_reg[9]_2\,
      \pi_dqs_found_lanes_r1_reg[9]_2\ => \pi_dqs_found_lanes_r1_reg[9]_3\,
      pi_fine_dly_dec_done => pi_fine_dly_dec_done,
      \po_stg2_wrcal_cnt_reg[0]\(0) => u_ddr_phy_wrcal_n_34,
      \po_stg2_wrcal_cnt_reg[0]_0\(0) => u_ddr_phy_wrcal_n_37,
      \po_stg2_wrcal_cnt_reg[1]\(0) => u_ddr_phy_wrcal_n_33,
      \po_stg2_wrcal_cnt_reg[1]_0\(0) => u_ddr_phy_wrcal_n_35,
      \po_stg2_wrcal_cnt_reg[1]_1\(0) => u_ddr_phy_wrcal_n_32,
      \po_stg2_wrcal_cnt_reg[1]_2\(0) => u_ddr_phy_wrcal_n_38,
      \po_stg2_wrcal_cnt_reg[1]_3\(0) => u_ddr_phy_wrcal_n_36,
      \po_stg2_wrcal_cnt_reg[1]_4\(0) => u_ddr_phy_wrcal_n_31,
      \po_stg2_wrcal_cnt_reg[3]\(3) => po_stg2_wrcal_cnt(3),
      \po_stg2_wrcal_cnt_reg[3]\(2 downto 0) => \^gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0),
      prbs_rdlvl_done_pulse0 => prbs_rdlvl_done_pulse0,
      prech_done => prech_done,
      \rd_mux_sel_r_reg[2]_0\ => \rd_mux_sel_r_reg[2]\,
      \rd_mux_sel_r_reg[2]_1\ => \rd_mux_sel_r_reg[2]_0\,
      \rd_mux_sel_r_reg[2]_10\ => \rd_mux_sel_r_reg[2]_9\,
      \rd_mux_sel_r_reg[2]_11\ => \rd_mux_sel_r_reg[2]_10\,
      \rd_mux_sel_r_reg[2]_12\ => \rd_mux_sel_r_reg[2]_11\,
      \rd_mux_sel_r_reg[2]_13\ => \rd_mux_sel_r_reg[2]_12\,
      \rd_mux_sel_r_reg[2]_14\ => \rd_mux_sel_r_reg[2]_13\,
      \rd_mux_sel_r_reg[2]_15\ => \rd_mux_sel_r_reg[2]_14\,
      \rd_mux_sel_r_reg[2]_16\ => \rd_mux_sel_r_reg[2]_15\,
      \rd_mux_sel_r_reg[2]_17\ => \rd_mux_sel_r_reg[2]_16\,
      \rd_mux_sel_r_reg[2]_18\ => \rd_mux_sel_r_reg[2]_17\,
      \rd_mux_sel_r_reg[2]_19\ => \rd_mux_sel_r_reg[2]_18\,
      \rd_mux_sel_r_reg[2]_2\ => \rd_mux_sel_r_reg[2]_1\,
      \rd_mux_sel_r_reg[2]_20\ => \rd_mux_sel_r_reg[2]_19\,
      \rd_mux_sel_r_reg[2]_21\ => \rd_mux_sel_r_reg[2]_20\,
      \rd_mux_sel_r_reg[2]_22\ => \rd_mux_sel_r_reg[2]_21\,
      \rd_mux_sel_r_reg[2]_23\ => \rd_mux_sel_r_reg[2]_22\,
      \rd_mux_sel_r_reg[2]_24\ => \rd_mux_sel_r_reg[2]_23\,
      \rd_mux_sel_r_reg[2]_25\ => \rd_mux_sel_r_reg[2]_24\,
      \rd_mux_sel_r_reg[2]_26\ => \rd_mux_sel_r_reg[2]_25\,
      \rd_mux_sel_r_reg[2]_27\ => \rd_mux_sel_r_reg[2]_26\,
      \rd_mux_sel_r_reg[2]_28\ => \rd_mux_sel_r_reg[2]_27\,
      \rd_mux_sel_r_reg[2]_29\ => \rd_mux_sel_r_reg[2]_28\,
      \rd_mux_sel_r_reg[2]_3\ => \rd_mux_sel_r_reg[2]_2\,
      \rd_mux_sel_r_reg[2]_30\ => \rd_mux_sel_r_reg[2]_29\,
      \rd_mux_sel_r_reg[2]_31\ => \rd_mux_sel_r_reg[2]_30\,
      \rd_mux_sel_r_reg[2]_32\ => \rd_mux_sel_r_reg[2]_31\,
      \rd_mux_sel_r_reg[2]_33\ => \rd_mux_sel_r_reg[2]_32\,
      \rd_mux_sel_r_reg[2]_34\ => \rd_mux_sel_r_reg[2]_33\,
      \rd_mux_sel_r_reg[2]_35\ => \rd_mux_sel_r_reg[2]_34\,
      \rd_mux_sel_r_reg[2]_36\ => \rd_mux_sel_r_reg[2]_35\,
      \rd_mux_sel_r_reg[2]_37\ => \rd_mux_sel_r_reg[2]_36\,
      \rd_mux_sel_r_reg[2]_38\ => \rd_mux_sel_r_reg[2]_37\,
      \rd_mux_sel_r_reg[2]_39\ => \rd_mux_sel_r_reg[2]_38\,
      \rd_mux_sel_r_reg[2]_4\ => \rd_mux_sel_r_reg[2]_3\,
      \rd_mux_sel_r_reg[2]_40\ => \rd_mux_sel_r_reg[2]_39\,
      \rd_mux_sel_r_reg[2]_41\ => \rd_mux_sel_r_reg[2]_40\,
      \rd_mux_sel_r_reg[2]_42\ => \rd_mux_sel_r_reg[2]_41\,
      \rd_mux_sel_r_reg[2]_43\ => \rd_mux_sel_r_reg[2]_42\,
      \rd_mux_sel_r_reg[2]_44\ => \rd_mux_sel_r_reg[2]_43\,
      \rd_mux_sel_r_reg[2]_45\ => \rd_mux_sel_r_reg[2]_44\,
      \rd_mux_sel_r_reg[2]_46\ => \rd_mux_sel_r_reg[2]_45\,
      \rd_mux_sel_r_reg[2]_47\ => \rd_mux_sel_r_reg[2]_46\,
      \rd_mux_sel_r_reg[2]_48\ => \rd_mux_sel_r_reg[2]_47\,
      \rd_mux_sel_r_reg[2]_49\ => \rd_mux_sel_r_reg[2]_48\,
      \rd_mux_sel_r_reg[2]_5\ => \rd_mux_sel_r_reg[2]_4\,
      \rd_mux_sel_r_reg[2]_50\ => \rd_mux_sel_r_reg[2]_49\,
      \rd_mux_sel_r_reg[2]_51\ => \rd_mux_sel_r_reg[2]_50\,
      \rd_mux_sel_r_reg[2]_52\ => \rd_mux_sel_r_reg[2]_51\,
      \rd_mux_sel_r_reg[2]_53\ => \rd_mux_sel_r_reg[2]_52\,
      \rd_mux_sel_r_reg[2]_54\ => \rd_mux_sel_r_reg[2]_53\,
      \rd_mux_sel_r_reg[2]_55\ => \rd_mux_sel_r_reg[2]_54\,
      \rd_mux_sel_r_reg[2]_56\ => \rd_mux_sel_r_reg[2]_55\,
      \rd_mux_sel_r_reg[2]_57\ => \rd_mux_sel_r_reg[2]_56\,
      \rd_mux_sel_r_reg[2]_58\ => \rd_mux_sel_r_reg[2]_57\,
      \rd_mux_sel_r_reg[2]_59\ => \rd_mux_sel_r_reg[2]_58\,
      \rd_mux_sel_r_reg[2]_6\ => \rd_mux_sel_r_reg[2]_5\,
      \rd_mux_sel_r_reg[2]_60\ => \rd_mux_sel_r_reg[2]_59\,
      \rd_mux_sel_r_reg[2]_61\ => \rd_mux_sel_r_reg[2]_60\,
      \rd_mux_sel_r_reg[2]_62\ => \rd_mux_sel_r_reg[2]_61\,
      \rd_mux_sel_r_reg[2]_63\ => \rd_mux_sel_r_reg[2]_62\,
      \rd_mux_sel_r_reg[2]_7\ => \rd_mux_sel_r_reg[2]_6\,
      \rd_mux_sel_r_reg[2]_8\ => \rd_mux_sel_r_reg[2]_7\,
      \rd_mux_sel_r_reg[2]_9\ => \rd_mux_sel_r_reg[2]_8\,
      \rdlvl_dqs_tap_cnt_r_reg[0][4][0]_0\(1 downto 0) => \rdlvl_dqs_tap_cnt_r_reg[0][4][0]\(1 downto 0),
      rdlvl_last_byte_done => rdlvl_last_byte_done,
      rdlvl_prech_req => rdlvl_prech_req,
      rdlvl_stg1_done_r1 => rdlvl_stg1_done_r1,
      rdlvl_stg1_rank_done => rdlvl_stg1_rank_done,
      rdlvl_stg1_start_reg => \^rdlvl_stg1_start_r_reg\,
      rdlvl_stg1_start_reg_0(0) => rdlvl_stg1_start_reg(0),
      \rstdiv0_sync_r1_reg_rep__13\(3 downto 0) => \rstdiv0_sync_r1_reg_rep__13\(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__2\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__2\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \rstdiv0_sync_r1_reg_rep__22\ => \rstdiv0_sync_r1_reg_rep__22\,
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      stg1_wr_done => stg1_wr_done,
      \stg1_wr_rd_cnt_reg[3]\ => u_ddr_phy_rdlvl_n_67,
      tempmon_pi_f_en_r => tempmon_pi_f_en_r,
      tempmon_pi_f_inc_r => tempmon_pi_f_inc_r,
      wrcal_done_reg => u_ddr_phy_wrcal_n_3,
      \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[445]_rep\ => u_ddr_phy_rdlvl_n_101,
      \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[447]\ => u_ddr_phy_rdlvl_n_8,
      \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[511]\(0) => u_ddr_phy_rdlvl_n_100,
      wrlvl_done_r1 => wrlvl_done_r1
    );
u_ddr_phy_wrcal: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_wrcal
     port map (
      CLK => CLK,
      E(0) => rd_active_r,
      \FSM_sequential_wl_state_r_reg[2]\ => u_ddr_phy_wrcal_n_43,
      LD0 => LD0,
      LD0_0 => LD0_0,
      LD0_1 => LD0_1,
      LD0_2 => LD0_2,
      LD0_3 => LD0_3,
      LD0_4 => LD0_4,
      LD0_6 => LD0_6,
      LD0_8 => LD0_8,
      Q(2 downto 0) => calib_zero_inputs(2 downto 0),
      \cal1_cnt_cpt_r_reg[0]\ => u_ddr_phy_rdlvl_n_72,
      \cal1_cnt_cpt_r_reg[1]\ => u_ddr_phy_rdlvl_n_70,
      \cal1_cnt_cpt_r_reg[2]\ => u_ddr_phy_rdlvl_n_103,
      \cal1_cnt_cpt_r_reg[2]_0\ => u_ddr_phy_rdlvl_n_69,
      cal1_dq_idel_ce_reg => u_ddr_phy_rdlvl_n_102,
      cal1_dq_idel_ce_reg_0 => u_ddr_phy_rdlvl_n_71,
      calib_in_common => calib_in_common,
      \calib_sel_reg[1]\(1 downto 0) => \^q\(1 downto 0),
      \corse_cnt_reg[0][2]\ => u_ddr_phy_wrcal_n_13,
      \corse_cnt_reg[1][2]\ => u_ddr_phy_wrcal_n_18,
      \corse_cnt_reg[2][2]\ => u_ddr_phy_wrcal_n_19,
      \corse_cnt_reg[3][2]\ => u_ddr_phy_wrcal_n_21,
      \corse_cnt_reg[4][2]\ => u_ddr_phy_wrcal_n_25,
      \corse_cnt_reg[5][2]\ => u_ddr_phy_wrcal_n_24,
      \corse_cnt_reg[6][2]\ => u_ddr_phy_wrcal_n_22,
      \corse_cnt_reg[7][2]\ => u_ddr_phy_wrcal_n_23,
      ddr3_lm_done_r => ddr3_lm_done_r,
      done_dqs_dec239_out => done_dqs_dec239_out,
      \dqs_count_r_reg[2]_rep__0\ => u_ddr_phy_wrcal_n_27,
      early1_data_reg_0 => u_ddr_phy_wrcal_n_6,
      early2_data_reg_0 => u_ddr_phy_wrcal_n_7,
      idelay_ce_int => idelay_ce_int,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_10 => idelay_ld_rst_10,
      idelay_ld_rst_11 => idelay_ld_rst_11,
      idelay_ld_rst_12 => idelay_ld_rst_12,
      idelay_ld_rst_13 => idelay_ld_rst_13,
      idelay_ld_rst_14 => idelay_ld_rst_14,
      \idelay_tap_cnt_r_reg[0][0][4]\(0) => u_ddr_phy_wrcal_n_33,
      \idelay_tap_cnt_r_reg[0][1][4]\(0) => u_ddr_phy_wrcal_n_34,
      \idelay_tap_cnt_r_reg[0][2][4]\(3) => po_stg2_wrcal_cnt(3),
      \idelay_tap_cnt_r_reg[0][2][4]\(2 downto 0) => \^gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0),
      \idelay_tap_cnt_r_reg[0][2][4]_0\(0) => u_ddr_phy_wrcal_n_35,
      \idelay_tap_cnt_r_reg[0][3][4]\(0) => u_ddr_phy_wrcal_n_32,
      \idelay_tap_cnt_r_reg[0][4][4]\(0) => u_ddr_phy_wrcal_n_38,
      \idelay_tap_cnt_r_reg[0][5][4]\(0) => u_ddr_phy_wrcal_n_37,
      \idelay_tap_cnt_r_reg[0][6][4]\(0) => u_ddr_phy_wrcal_n_36,
      \idelay_tap_cnt_r_reg[0][7][4]\(0) => u_ddr_phy_wrcal_n_31,
      \init_state_r_reg[0]\ => u_ddr_phy_wrcal_n_28,
      \init_state_r_reg[2]\ => u_ddr_phy_wrcal_n_20,
      \init_state_r_reg[3]\ => u_ddr_phy_wrcal_n_29,
      \init_state_r_reg[4]\ => u_ddr_phy_wrcal_n_30,
      p_0_in => p_0_in_0,
      p_0_out => p_0_out,
      phy_if_reset_w => phy_if_reset_w,
      phy_rddata_en => phy_rddata_en,
      pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_73\,
      \po_stg2_wrcal_cnt_reg[2]_0\ => \po_stg2_wrcal_cnt_reg[2]\,
      \po_stg2_wrcal_cnt_reg[2]_1\ => \po_stg2_wrcal_cnt_reg[2]_0\,
      \po_stg2_wrcal_cnt_reg[2]_10\ => \po_stg2_wrcal_cnt_reg[2]_9\,
      \po_stg2_wrcal_cnt_reg[2]_11\ => \po_stg2_wrcal_cnt_reg[2]_10\,
      \po_stg2_wrcal_cnt_reg[2]_12\ => \po_stg2_wrcal_cnt_reg[2]_11\,
      \po_stg2_wrcal_cnt_reg[2]_13\ => \po_stg2_wrcal_cnt_reg[2]_12\,
      \po_stg2_wrcal_cnt_reg[2]_14\ => \po_stg2_wrcal_cnt_reg[2]_13\,
      \po_stg2_wrcal_cnt_reg[2]_15\ => \po_stg2_wrcal_cnt_reg[2]_14\,
      \po_stg2_wrcal_cnt_reg[2]_16\ => \po_stg2_wrcal_cnt_reg[2]_15\,
      \po_stg2_wrcal_cnt_reg[2]_17\ => \po_stg2_wrcal_cnt_reg[2]_16\,
      \po_stg2_wrcal_cnt_reg[2]_18\ => \po_stg2_wrcal_cnt_reg[2]_17\,
      \po_stg2_wrcal_cnt_reg[2]_19\ => \po_stg2_wrcal_cnt_reg[2]_18\,
      \po_stg2_wrcal_cnt_reg[2]_2\ => \po_stg2_wrcal_cnt_reg[2]_1\,
      \po_stg2_wrcal_cnt_reg[2]_20\ => \po_stg2_wrcal_cnt_reg[2]_19\,
      \po_stg2_wrcal_cnt_reg[2]_21\ => \po_stg2_wrcal_cnt_reg[2]_20\,
      \po_stg2_wrcal_cnt_reg[2]_22\ => \po_stg2_wrcal_cnt_reg[2]_21\,
      \po_stg2_wrcal_cnt_reg[2]_23\ => \po_stg2_wrcal_cnt_reg[2]_22\,
      \po_stg2_wrcal_cnt_reg[2]_24\ => \po_stg2_wrcal_cnt_reg[2]_23\,
      \po_stg2_wrcal_cnt_reg[2]_25\ => \po_stg2_wrcal_cnt_reg[2]_24\,
      \po_stg2_wrcal_cnt_reg[2]_26\ => \po_stg2_wrcal_cnt_reg[2]_25\,
      \po_stg2_wrcal_cnt_reg[2]_27\ => \po_stg2_wrcal_cnt_reg[2]_26\,
      \po_stg2_wrcal_cnt_reg[2]_28\ => \po_stg2_wrcal_cnt_reg[2]_27\,
      \po_stg2_wrcal_cnt_reg[2]_29\ => \po_stg2_wrcal_cnt_reg[2]_28\,
      \po_stg2_wrcal_cnt_reg[2]_3\ => \po_stg2_wrcal_cnt_reg[2]_2\,
      \po_stg2_wrcal_cnt_reg[2]_30\ => \po_stg2_wrcal_cnt_reg[2]_29\,
      \po_stg2_wrcal_cnt_reg[2]_31\ => \po_stg2_wrcal_cnt_reg[2]_30\,
      \po_stg2_wrcal_cnt_reg[2]_32\ => \po_stg2_wrcal_cnt_reg[2]_31\,
      \po_stg2_wrcal_cnt_reg[2]_33\ => \po_stg2_wrcal_cnt_reg[2]_32\,
      \po_stg2_wrcal_cnt_reg[2]_34\ => \po_stg2_wrcal_cnt_reg[2]_33\,
      \po_stg2_wrcal_cnt_reg[2]_35\ => \po_stg2_wrcal_cnt_reg[2]_34\,
      \po_stg2_wrcal_cnt_reg[2]_36\ => \po_stg2_wrcal_cnt_reg[2]_35\,
      \po_stg2_wrcal_cnt_reg[2]_37\ => \po_stg2_wrcal_cnt_reg[2]_36\,
      \po_stg2_wrcal_cnt_reg[2]_38\ => \po_stg2_wrcal_cnt_reg[2]_37\,
      \po_stg2_wrcal_cnt_reg[2]_39\ => \po_stg2_wrcal_cnt_reg[2]_38\,
      \po_stg2_wrcal_cnt_reg[2]_4\ => \po_stg2_wrcal_cnt_reg[2]_3\,
      \po_stg2_wrcal_cnt_reg[2]_40\ => \po_stg2_wrcal_cnt_reg[2]_39\,
      \po_stg2_wrcal_cnt_reg[2]_41\ => \po_stg2_wrcal_cnt_reg[2]_40\,
      \po_stg2_wrcal_cnt_reg[2]_42\ => \po_stg2_wrcal_cnt_reg[2]_41\,
      \po_stg2_wrcal_cnt_reg[2]_43\ => \po_stg2_wrcal_cnt_reg[2]_42\,
      \po_stg2_wrcal_cnt_reg[2]_44\ => \po_stg2_wrcal_cnt_reg[2]_43\,
      \po_stg2_wrcal_cnt_reg[2]_45\ => \po_stg2_wrcal_cnt_reg[2]_44\,
      \po_stg2_wrcal_cnt_reg[2]_46\ => \po_stg2_wrcal_cnt_reg[2]_45\,
      \po_stg2_wrcal_cnt_reg[2]_47\ => \po_stg2_wrcal_cnt_reg[2]_46\,
      \po_stg2_wrcal_cnt_reg[2]_48\ => \po_stg2_wrcal_cnt_reg[2]_47\,
      \po_stg2_wrcal_cnt_reg[2]_49\ => \po_stg2_wrcal_cnt_reg[2]_48\,
      \po_stg2_wrcal_cnt_reg[2]_5\ => \po_stg2_wrcal_cnt_reg[2]_4\,
      \po_stg2_wrcal_cnt_reg[2]_50\ => \po_stg2_wrcal_cnt_reg[2]_49\,
      \po_stg2_wrcal_cnt_reg[2]_51\ => \po_stg2_wrcal_cnt_reg[2]_50\,
      \po_stg2_wrcal_cnt_reg[2]_52\ => \po_stg2_wrcal_cnt_reg[2]_51\,
      \po_stg2_wrcal_cnt_reg[2]_53\ => \po_stg2_wrcal_cnt_reg[2]_52\,
      \po_stg2_wrcal_cnt_reg[2]_54\ => \po_stg2_wrcal_cnt_reg[2]_53\,
      \po_stg2_wrcal_cnt_reg[2]_55\ => \po_stg2_wrcal_cnt_reg[2]_54\,
      \po_stg2_wrcal_cnt_reg[2]_56\ => \po_stg2_wrcal_cnt_reg[2]_55\,
      \po_stg2_wrcal_cnt_reg[2]_57\ => \po_stg2_wrcal_cnt_reg[2]_56\,
      \po_stg2_wrcal_cnt_reg[2]_58\ => \po_stg2_wrcal_cnt_reg[2]_57\,
      \po_stg2_wrcal_cnt_reg[2]_59\ => \po_stg2_wrcal_cnt_reg[2]_58\,
      \po_stg2_wrcal_cnt_reg[2]_6\ => \po_stg2_wrcal_cnt_reg[2]_5\,
      \po_stg2_wrcal_cnt_reg[2]_60\ => \po_stg2_wrcal_cnt_reg[2]_59\,
      \po_stg2_wrcal_cnt_reg[2]_61\ => \po_stg2_wrcal_cnt_reg[2]_60\,
      \po_stg2_wrcal_cnt_reg[2]_62\ => \po_stg2_wrcal_cnt_reg[2]_61\,
      \po_stg2_wrcal_cnt_reg[2]_7\ => \po_stg2_wrcal_cnt_reg[2]_6\,
      \po_stg2_wrcal_cnt_reg[2]_8\ => \po_stg2_wrcal_cnt_reg[2]_7\,
      \po_stg2_wrcal_cnt_reg[2]_9\ => \po_stg2_wrcal_cnt_reg[2]_8\,
      prech_done => prech_done,
      rdlvl_stg1_done_reg => u_ddr_phy_rdlvl_n_8,
      \rstdiv0_sync_r1_reg_rep__12\(0) => \rstdiv0_sync_r1_reg_rep__12\(1),
      \rstdiv0_sync_r1_reg_rep__13\(0) => \rstdiv0_sync_r1_reg_rep__13\(3),
      \rstdiv0_sync_r1_reg_rep__22\ => \rstdiv0_sync_r1_reg_rep__22\,
      wl_sm_start => wl_sm_start,
      wr_level_done_r5 => wr_level_done_r5,
      wrcal_done_reg_0 => u_ddr_phy_wrcal_n_3,
      wrcal_prech_req => wrcal_prech_req,
      wrcal_rd_wait => wrcal_rd_wait,
      wrcal_resume_w => wrcal_resume_w,
      wrcal_sanity_chk => wrcal_sanity_chk,
      wrcal_sanity_chk_done_reg_0 => u_ddr_phy_wrcal_n_4,
      wrcal_start_reg => u_ddr_phy_init_n_897,
      wrlvl_byte_done => wrlvl_byte_done,
      wrlvl_byte_redo => wrlvl_byte_redo,
      wrlvl_byte_redo_r => wrlvl_byte_redo_r,
      wrlvl_done_r1 => wrlvl_done_r1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_rank_common is
  port (
    \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\ : out STD_LOGIC;
    \maintenance_request.new_maint_rank_r_reg_0\ : out STD_LOGIC;
    maint_req_r : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_0\ : out STD_LOGIC;
    \periodic_read_request.upd_last_master_r\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    maint_zq_r : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    maint_srx_r : out STD_LOGIC;
    \grant_r_reg[0]_0\ : out STD_LOGIC;
    periodic_rd_r : out STD_LOGIC;
    app_ref_r : out STD_LOGIC;
    app_zq_r : out STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt\ : out STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r\ : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    maint_ref_zq_wip : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \refresh_timer.refresh_timer_r_reg[5]_0\ : out STD_LOGIC;
    \refresh_timer.refresh_timer_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[0]_1\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    \maint_prescaler.maint_prescaler_r1\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]\ : in STD_LOGIC;
    app_zq_r_reg_0 : in STD_LOGIC;
    insert_maint_r1_lcl_reg : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg\ : in STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_2\ : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]_0\ : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_0\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    insert_maint_r1 : in STD_LOGIC;
    cke_r : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]_1\ : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]_2\ : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \maint_prescaler.maint_prescaler_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__12_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \refresh_timer.refresh_timer_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_rank_common : entity is "mig_7series_v2_3_rank_common";
end mig_7series_0_mig_7series_v2_3_rank_common;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_rank_common is
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal app_ref_ack_ns : STD_LOGIC;
  signal \^app_ref_r\ : STD_LOGIC;
  signal app_zq_ack_ns : STD_LOGIC;
  signal \^app_zq_r\ : STD_LOGIC;
  signal \^grant_r_reg[0]\ : STD_LOGIC;
  signal \^grant_r_reg[0]_0\ : STD_LOGIC;
  signal \i___14_i_2_n_0\ : STD_LOGIC;
  signal \maint_prescaler.maint_prescaler_r0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \maint_prescaler.maint_prescaler_tick_ns\ : STD_LOGIC;
  signal \^maint_srx_r\ : STD_LOGIC;
  signal \^maint_zq_r\ : STD_LOGIC;
  signal \maintenance_request.maint_arb0_n_2\ : STD_LOGIC;
  signal \maintenance_request.maint_arb0_n_3\ : STD_LOGIC;
  signal \maintenance_request.maint_sre_ns\ : STD_LOGIC;
  signal \^maintenance_request.maint_sre_r_lcl_reg_0\ : STD_LOGIC;
  signal \maintenance_request.new_maint_rank_r\ : STD_LOGIC;
  signal \^maintenance_request.new_maint_rank_r_reg_0\ : STD_LOGIC;
  signal \maintenance_request.upd_last_master_ns\ : STD_LOGIC;
  signal \^periodic_rd_r\ : STD_LOGIC;
  signal \periodic_read_request.upd_last_master_ns\ : STD_LOGIC;
  signal \^periodic_read_request.upd_last_master_r\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \refresh_timer.refresh_timer_r0_0\ : STD_LOGIC;
  signal \refresh_timer.refresh_timer_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \^refresh_timer.refresh_timer_r_reg[4]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \refresh_timer.refresh_timer_r_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal sel : STD_LOGIC;
  signal \sr_cntrl.ckesr_timer.ckesr_timer_r\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg\ : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\ : STD_LOGIC;
  signal \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_1\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of app_ref_ack_r_i_1 : label is "soft_lutpair1016";
  attribute SOFT_HLUTNM of app_zq_ack_r_i_1 : label is "soft_lutpair1016";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[2]_i_1\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[3]_i_1\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[2]_i_1\ : label is "soft_lutpair1015";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[3]_i_1\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[4]_i_1\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[5]_i_3\ : label is "soft_lutpair1015";
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
  app_ref_r <= \^app_ref_r\;
  app_zq_r <= \^app_zq_r\;
  \grant_r_reg[0]\ <= \^grant_r_reg[0]\;
  \grant_r_reg[0]_0\ <= \^grant_r_reg[0]_0\;
  maint_srx_r <= \^maint_srx_r\;
  maint_zq_r <= \^maint_zq_r\;
  \maintenance_request.maint_sre_r_lcl_reg_0\ <= \^maintenance_request.maint_sre_r_lcl_reg_0\;
  \maintenance_request.new_maint_rank_r_reg_0\ <= \^maintenance_request.new_maint_rank_r_reg_0\;
  periodic_rd_r <= \^periodic_rd_r\;
  \periodic_read_request.upd_last_master_r\ <= \^periodic_read_request.upd_last_master_r\;
  \refresh_timer.refresh_timer_r_reg[4]_0\(1 downto 0) <= \^refresh_timer.refresh_timer_r_reg[4]_0\(1 downto 0);
  \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\ <= \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\;
  \zq_cntrl.zq_timer.zq_timer_r_reg[0]_1\ <= \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_1\;
app_ref_ack_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^app_ref_r\,
      I1 => \refresh_generation.refresh_bank_r_reg[0]_1\,
      I2 => \init_calib_complete_reg_rep__12_0\,
      O => app_ref_ack_ns
    );
app_ref_ack_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_ref_ack_ns,
      Q => app_ref_ack,
      R => '0'
    );
app_ref_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \refresh_generation.refresh_bank_r_reg[0]\,
      Q => \^app_ref_r\,
      R => \maint_prescaler.maint_prescaler_r1\
    );
app_sr_active_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_sre_r_lcl_reg_2\,
      Q => app_sr_active,
      R => '0'
    );
app_zq_ack_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \^app_zq_r\,
      I1 => \init_calib_complete_reg_rep__12_0\,
      I2 => \^grant_r_reg[0]\,
      O => app_zq_ack_ns
    );
app_zq_ack_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_zq_ack_ns,
      Q => app_zq_ack,
      R => '0'
    );
app_zq_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => app_zq_r_reg_0,
      Q => \^app_zq_r\,
      R => \maint_prescaler.maint_prescaler_r1\
    );
cke_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3F08"
    )
        port map (
      I0 => \^maint_srx_r\,
      I1 => insert_maint_r1,
      I2 => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      I3 => cke_r,
      O => mc_cke_ns(0)
    );
\i___14_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg__0\(2),
      I1 => \refresh_timer.refresh_timer_r_reg__0\(5),
      I2 => \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\,
      I3 => \^refresh_timer.refresh_timer_r_reg[4]_0\(1),
      I4 => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      I5 => \i___14_i_2_n_0\,
      O => \refresh_timer.refresh_timer_r_reg[5]_0\
    );
\i___14_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg__0\(3),
      I1 => \refresh_timer.refresh_timer_r_reg__0\(4),
      O => \i___14_i_2_n_0\
    );
\i___16_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AAAAAAA"
    )
        port map (
      I0 => \init_calib_complete_reg_rep__12_0\,
      I1 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\,
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      I3 => \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\,
      I4 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\,
      O => \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_1\
    );
\maint_prescaler.maint_prescaler_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \maint_prescaler.maint_prescaler_r0\(0)
    );
\maint_prescaler.maint_prescaler_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \maint_prescaler.maint_prescaler_r0\(2)
    );
\maint_prescaler.maint_prescaler_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      O => \maint_prescaler.maint_prescaler_r0\(3)
    );
\maint_prescaler.maint_prescaler_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => sel
    );
\maint_prescaler.maint_prescaler_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \maint_prescaler.maint_prescaler_r0\(4)
    );
\maint_prescaler.maint_prescaler_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(0),
      Q => \^q\(0),
      R => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r_reg[0]_0\(0),
      Q => \^q\(1),
      R => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(2),
      Q => \^q\(2),
      R => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(3),
      Q => \^q\(3),
      R => SS(0)
    );
\maint_prescaler.maint_prescaler_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => sel,
      D => \maint_prescaler.maint_prescaler_r0\(4),
      Q => \^q\(4),
      S => SS(0)
    );
\maint_prescaler.maint_prescaler_tick_r_lcl_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(4),
      I4 => \^q\(3),
      O => \maint_prescaler.maint_prescaler_tick_ns\
    );
\maint_prescaler.maint_prescaler_tick_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maint_prescaler.maint_prescaler_tick_ns\,
      Q => \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\,
      R => '0'
    );
maint_ref_zq_wip_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \refresh_generation.refresh_bank_r_reg[0]_0\,
      Q => maint_ref_zq_wip,
      R => SR(0)
    );
\maintenance_request.maint_arb0\: entity work.mig_7series_0_mig_7series_v2_3_round_robin_arb
     port map (
      CLK => CLK,
      Q(0) => \maintenance_request.maint_sre_r_lcl_reg_1\(0),
      app_sr_req => app_sr_req,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12_0\,
      \last_master_r_reg[2]_0\(0) => \last_master_r_reg[2]\(0),
      \last_master_r_reg[2]_1\ => \last_master_r_reg[2]_0\,
      maint_srx_r => \^maint_srx_r\,
      maint_zq_r => \^maint_zq_r\,
      \maintenance_request.maint_sre_ns\ => \maintenance_request.maint_sre_ns\,
      \maintenance_request.maint_sre_r_lcl_reg\ => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      \maintenance_request.maint_srx_r_lcl_reg\ => \maintenance_request.maint_arb0_n_2\,
      \maintenance_request.maint_zq_r_lcl_reg\ => \maintenance_request.maint_arb0_n_3\,
      \maintenance_request.upd_last_master_r_reg\ => \^maintenance_request.new_maint_rank_r_reg_0\,
      \refresh_generation.refresh_bank_r_reg[0]\ => \refresh_generation.refresh_bank_r_reg[0]_1\,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \sr_cntrl.ckesr_timer.ckesr_timer_r\ => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      \sr_cntrl.sre_request_logic.sre_request_r_reg\ => \^grant_r_reg[0]_0\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \^grant_r_reg[0]\
    );
\maintenance_request.maint_req_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.new_maint_rank_r\,
      Q => maint_req_r,
      R => '0'
    );
\maintenance_request.maint_sre_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_sre_ns\,
      Q => \^maintenance_request.maint_sre_r_lcl_reg_0\,
      R => '0'
    );
\maintenance_request.maint_srx_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_arb0_n_2\,
      Q => \^maint_srx_r\,
      R => in0
    );
\maintenance_request.maint_zq_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.maint_arb0_n_3\,
      Q => \^maint_zq_r\,
      R => SR(0)
    );
\maintenance_request.new_maint_rank_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^maintenance_request.new_maint_rank_r_reg_0\,
      Q => \maintenance_request.new_maint_rank_r\,
      R => '0'
    );
\maintenance_request.upd_last_master_r_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000D5"
    )
        port map (
      I0 => \refresh_generation.refresh_bank_r_reg[0]_2\,
      I1 => \^grant_r_reg[0]\,
      I2 => \init_calib_complete_reg_rep__12_0\,
      I3 => \^maintenance_request.new_maint_rank_r_reg_0\,
      I4 => \maintenance_request.new_maint_rank_r\,
      I5 => \maint_controller.maint_wip_r_lcl_reg\,
      O => \maintenance_request.upd_last_master_ns\
    );
\maintenance_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \maintenance_request.upd_last_master_ns\,
      Q => \^maintenance_request.new_maint_rank_r_reg_0\,
      R => '0'
    );
\periodic_read_request.periodic_rd_grant_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_rd_generation.periodic_rd_request_r_reg\,
      Q => \periodic_read_request.periodic_rd_grant_r\,
      R => '0'
    );
\periodic_read_request.periodic_rd_r_cnt_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.periodic_rd_r_lcl_reg_0\,
      Q => \periodic_read_request.periodic_rd_r_cnt\,
      R => SR(0)
    );
\periodic_read_request.periodic_rd_r_lcl_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => periodic_rd_ack_r_lcl_reg,
      Q => \^periodic_rd_r\,
      R => \maint_prescaler.maint_prescaler_r1\
    );
\periodic_read_request.upd_last_master_r_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \periodic_rd_generation.periodic_rd_request_r\,
      I1 => \init_calib_complete_reg_rep__12_0\,
      I2 => \^periodic_read_request.upd_last_master_r\,
      I3 => \^periodic_rd_r\,
      O => \periodic_read_request.upd_last_master_ns\
    );
\periodic_read_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \periodic_read_request.upd_last_master_ns\,
      Q => \^periodic_read_request.upd_last_master_r\,
      R => '0'
    );
\refresh_timer.refresh_timer_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      O => \refresh_timer.refresh_timer_r0\(0)
    );
\refresh_timer.refresh_timer_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg__0\(2),
      I1 => \^refresh_timer.refresh_timer_r_reg[4]_0\(1),
      I2 => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      O => \refresh_timer.refresh_timer_r0\(2)
    );
\refresh_timer.refresh_timer_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg__0\(3),
      I1 => \refresh_timer.refresh_timer_r_reg__0\(2),
      I2 => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      I3 => \^refresh_timer.refresh_timer_r_reg[4]_0\(1),
      O => \refresh_timer.refresh_timer_r0\(3)
    );
\refresh_timer.refresh_timer_r[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg__0\(4),
      I1 => \refresh_timer.refresh_timer_r_reg__0\(3),
      I2 => \^refresh_timer.refresh_timer_r_reg[4]_0\(1),
      I3 => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      I4 => \refresh_timer.refresh_timer_r_reg__0\(2),
      O => \refresh_timer.refresh_timer_r0\(4)
    );
\refresh_timer.refresh_timer_r[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA8A"
    )
        port map (
      I0 => \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\,
      I1 => \refresh_timer.refresh_timer_r_reg__0\(5),
      I2 => \refresh_timer.refresh_timer_r[5]_i_3_n_0\,
      I3 => \refresh_timer.refresh_timer_r_reg__0\(4),
      I4 => \refresh_timer.refresh_timer_r_reg__0\(3),
      O => \refresh_timer.refresh_timer_r0_0\
    );
\refresh_timer.refresh_timer_r[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \refresh_timer.refresh_timer_r_reg__0\(5),
      I1 => \refresh_timer.refresh_timer_r_reg__0\(3),
      I2 => \refresh_timer.refresh_timer_r_reg__0\(4),
      I3 => \^refresh_timer.refresh_timer_r_reg[4]_0\(1),
      I4 => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      I5 => \refresh_timer.refresh_timer_r_reg__0\(2),
      O => \refresh_timer.refresh_timer_r0\(5)
    );
\refresh_timer.refresh_timer_r[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^refresh_timer.refresh_timer_r_reg[4]_0\(1),
      I1 => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      I2 => \refresh_timer.refresh_timer_r_reg__0\(2),
      O => \refresh_timer.refresh_timer_r[5]_i_3_n_0\
    );
\refresh_timer.refresh_timer_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(0),
      Q => \^refresh_timer.refresh_timer_r_reg[4]_0\(0),
      S => \init_calib_complete_reg_rep__12_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r_reg[0]_0\(0),
      Q => \^refresh_timer.refresh_timer_r_reg[4]_0\(1),
      R => \init_calib_complete_reg_rep__12_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(2),
      Q => \refresh_timer.refresh_timer_r_reg__0\(2),
      S => \init_calib_complete_reg_rep__12_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(3),
      Q => \refresh_timer.refresh_timer_r_reg__0\(3),
      R => \init_calib_complete_reg_rep__12_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(4),
      Q => \refresh_timer.refresh_timer_r_reg__0\(4),
      R => \init_calib_complete_reg_rep__12_1\(0)
    );
\refresh_timer.refresh_timer_r_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \refresh_timer.refresh_timer_r0_0\,
      D => \refresh_timer.refresh_timer_r0\(5),
      Q => \refresh_timer.refresh_timer_r_reg__0\(5),
      S => \init_calib_complete_reg_rep__12_1\(0)
    );
\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => insert_maint_r1_lcl_reg,
      Q => \sr_cntrl.ckesr_timer.ckesr_timer_r\,
      R => '0'
    );
\sr_cntrl.sre_request_logic.sre_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \init_calib_complete_reg_rep__12\,
      Q => \^grant_r_reg[0]_0\,
      R => in0
    );
\zq_cntrl.zq_request_logic.zq_request_r_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \zq_cntrl.zq_request_logic.zq_request_r_reg_0\,
      Q => \^grant_r_reg[0]\,
      R => in0
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_1\,
      O => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(14),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(13),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(18),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(17),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(12),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(4),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(10),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(3),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(6),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(5),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(11),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(7),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => \^zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\,
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      I2 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\,
      I3 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\,
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(19),
      I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1),
      I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(16),
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(15),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\,
      I1 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\,
      I2 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\,
      I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(2),
      I4 => \zq_cntrl.zq_timer.zq_timer_r_reg\(9),
      I5 => \zq_cntrl.zq_timer.zq_timer_r_reg\(8),
      O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(3),
      O => S(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(2),
      O => S(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1),
      O => S(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[0]_i_9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      O => S(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(15),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(14),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(13),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[12]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(12),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(19),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(18),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(17),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[16]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(16),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(7),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(6),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(5),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[4]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(4),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(11),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(10),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(2)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(9),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(1)
    );
\zq_cntrl.zq_timer.zq_timer_r[8]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(8),
      O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(0)
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(0),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(10),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(11),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(12),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(13),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[14]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(14),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[15]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(15),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[16]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(16),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(17),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(18),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[19]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(19),
      S => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(1),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(2),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => O(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(3),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(4),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(5),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(2),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(6),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(3),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(7),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(0),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(8),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\,
      D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(1),
      Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(9),
      R => \zq_cntrl.zq_timer.zq_timer_r0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ui_top is
  port (
    app_rdy : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    \not_strict_mode.app_rd_data_end_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4]\ : out STD_LOGIC;
    ram_init_addr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    DOA : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DOC : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ram_init_done_r : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 13 downto 0 );
    row_hit_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    row_hit_r_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rb_hit_busy_r_reg : out STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    rb_hit_busy_r_reg_1 : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 95 downto 0 );
    \my_empty_reg[7]_0\ : out STD_LOGIC_VECTOR ( 575 downto 0 );
    use_addr : out STD_LOGIC;
    \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cmd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    app_rd_data : out STD_LOGIC_VECTOR ( 511 downto 0 );
    CLK : in STD_LOGIC;
    \pointer_ram.pointer_we\ : in STD_LOGIC;
    \cmd_pipe_plus.wr_data_addr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \not_strict_mode.rd_buf_we\ : in STD_LOGIC;
    DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.app_rd_data_end_ns\ : in STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \init_calib_complete_reg_rep__22\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__21\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__20\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__19\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__18\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__17\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__16\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__15\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__14\ : in STD_LOGIC;
    app_en : in STD_LOGIC;
    reset_reg : in STD_LOGIC;
    accept_ns : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC;
    \not_strict_mode.bypass__0\ : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\ : in STD_LOGIC_VECTOR ( 511 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ui_top : entity is "mig_7series_v2_3_ui_top";
end mig_7series_0_mig_7series_v2_3_ui_top;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ui_top is
  signal \^app_rd_data_end\ : STD_LOGIC;
  signal app_rdy_ns : STD_LOGIC;
  signal \not_strict_mode.app_rd_data_valid_copy\ : STD_LOGIC;
  signal \not_strict_mode.occ_cnt_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \pointer_ram.pointer_wr_addr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pointer_ram.pointer_wr_data\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^ram_init_done_r\ : STD_LOGIC;
  signal rd_accepted : STD_LOGIC;
  signal rd_data_buf_addr_r : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \read_data_indx.rd_data_indx_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ui_cmd0_n_26 : STD_LOGIC;
  signal ui_cmd0_n_27 : STD_LOGIC;
  signal ui_cmd0_n_28 : STD_LOGIC;
  signal ui_cmd0_n_30 : STD_LOGIC;
  signal ui_cmd0_n_31 : STD_LOGIC;
  signal ui_rd_data0_n_524 : STD_LOGIC;
  signal wr_accepted : STD_LOGIC;
  signal wr_data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
  app_rd_data_end <= \^app_rd_data_end\;
  ram_init_done_r <= \^ram_init_done_r\;
ui_cmd0: entity work.mig_7series_0_mig_7series_v2_3_ui_cmd
     port map (
      CLK => CLK,
      D(12) => D(13),
      D(11 downto 0) => D(11 downto 0),
      E(0) => app_rdy,
      Q(4 downto 0) => rd_data_buf_addr_r(4 downto 0),
      S(0) => S(0),
      app_addr(26 downto 0) => app_addr(26 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rdy_ns => app_rdy_ns,
      cmd(1 downto 0) => cmd(1 downto 0),
      \not_strict_mode.app_rd_data_end_reg\ => \^app_rd_data_end\,
      \not_strict_mode.app_rd_data_valid_copy\ => \not_strict_mode.app_rd_data_valid_copy\,
      \not_strict_mode.occ_cnt_r\(1 downto 0) => \not_strict_mode.occ_cnt_r\(1 downto 0),
      \not_strict_mode.occ_cnt_r_reg[3]\ => ui_cmd0_n_31,
      \not_strict_mode.occ_cnt_r_reg[4]\ => ui_cmd0_n_30,
      p_0_in(0) => p_0_in(0),
      rb_hit_busy_r_reg => rb_hit_busy_r_reg,
      rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0,
      rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1,
      rd_accepted => rd_accepted,
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[2]\(0),
      \req_bank_r_lcl_reg[1]\ => \req_bank_r_lcl_reg[2]\(1),
      \req_bank_r_lcl_reg[2]\ => \req_bank_r_lcl_reg[2]\(2),
      \req_bank_r_lcl_reg[2]_0\(8 downto 0) => \req_bank_r_lcl_reg[2]_0\(8 downto 0),
      \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_data_buf_addr_r_reg[4]\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0),
      \req_row_r_lcl_reg[12]\ => D(12),
      \req_row_r_lcl_reg[13]\(10 downto 0) => \req_row_r_lcl_reg[13]\(10 downto 0),
      reset_reg => reset_reg,
      row_hit_r_reg(0) => row_hit_r_reg(0),
      row_hit_r_reg_0(0) => row_hit_r_reg_0(0),
      row_hit_r_reg_1(0) => row_hit_r_reg_1(0),
      row_hit_r_reg_2(0) => row_hit_r_reg_2(0),
      use_addr => use_addr,
      wr_accepted => wr_accepted,
      wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0),
      \wr_req_counter.wr_req_cnt_r\(1 downto 0) => \wr_req_counter.wr_req_cnt_r\(1 downto 0),
      \wr_req_counter.wr_req_cnt_r_reg[0]\(0) => ui_cmd0_n_27,
      \wr_req_counter.wr_req_cnt_r_reg[0]_0\ => ui_cmd0_n_28,
      \wr_req_counter.wr_req_cnt_r_reg[3]\ => ui_cmd0_n_26
    );
ui_rd_data0: entity work.mig_7series_0_mig_7series_v2_3_ui_rd_data
     port map (
      ADDRA(4) => \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4]\,
      ADDRA(3 downto 0) => ram_init_addr(3 downto 0),
      ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0),
      CLK => CLK,
      D(0) => ui_rd_data0_n_524,
      DIA(1 downto 0) => DIA(1 downto 0),
      DIB(1 downto 0) => DIB(1 downto 0),
      DIC(1 downto 0) => DIC(1 downto 0),
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      Q(6 downto 0) => Q(6 downto 0),
      app_rd_data(511 downto 0) => app_rd_data(511 downto 0),
      app_rd_data_end => \^app_rd_data_end\,
      app_rd_data_valid => app_rd_data_valid,
      \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(511 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(511 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3\(1 downto 0),
      \not_strict_mode.app_rd_data_end_ns\ => \not_strict_mode.app_rd_data_end_ns\,
      \not_strict_mode.app_rd_data_end_reg_0\(0) => \not_strict_mode.app_rd_data_end_reg\(0),
      \not_strict_mode.app_rd_data_reg[101]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[103]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[105]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[107]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[109]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[111]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[113]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[115]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[119]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[11]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[121]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[123]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[125]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[129]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[129]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[131]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[131]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[133]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[133]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[135]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[135]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[137]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[137]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[139]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[139]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[13]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[141]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[141]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[143]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[143]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[145]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[145]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[147]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[147]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[149]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[149]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[151]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[151]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[153]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[153]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[155]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[155]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[157]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[157]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[159]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[159]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[15]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[161]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[161]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[163]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[163]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[165]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[165]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[167]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[167]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[169]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[169]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[171]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[171]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[173]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[173]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[175]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[175]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[177]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[177]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[179]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[179]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[17]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[181]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[181]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[183]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[183]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[185]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[185]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[187]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[187]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[189]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[189]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[191]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[191]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[193]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[193]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[195]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[195]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[197]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[197]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[199]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[199]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[19]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[201]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[201]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[203]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[203]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[205]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[205]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[207]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[207]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[209]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[209]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[211]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[211]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[213]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[213]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[215]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[215]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[217]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[217]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[219]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[219]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[21]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[221]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[221]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[223]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[223]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[225]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[225]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[227]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[227]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[229]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[229]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[231]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[231]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[233]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[233]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[235]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[235]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[237]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[237]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[239]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[239]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[23]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[241]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[241]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[243]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[243]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[245]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[245]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[247]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[247]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[249]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[249]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[251]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[251]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[253]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[253]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[255]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[255]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[257]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[257]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[259]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[259]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[25]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[261]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[261]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[263]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[263]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[265]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[265]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[267]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[267]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[269]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[269]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[271]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[271]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[273]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[273]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[275]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[275]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[277]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[277]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[279]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[279]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[27]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[281]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[281]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[283]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[283]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[285]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[285]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[287]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[287]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[289]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[289]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[291]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[291]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[293]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[293]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[295]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[295]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[297]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[297]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[299]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[299]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[29]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[301]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[301]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[303]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[303]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[305]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[305]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[307]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[307]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[309]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[309]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[311]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[311]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[313]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[313]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[315]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[315]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[317]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[317]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[319]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[319]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[31]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[321]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[321]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[323]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[323]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[325]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[325]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[327]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[327]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[329]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[329]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[331]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[331]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[333]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[333]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[335]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[335]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[337]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[337]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[339]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[339]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[33]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[341]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[341]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[343]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[343]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[345]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[345]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[347]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[347]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[349]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[349]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[351]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[351]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[353]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[353]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[355]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[355]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[357]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[357]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[359]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[359]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[35]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[361]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[361]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[363]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[363]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[365]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[365]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[367]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[367]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[369]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[369]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[371]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[371]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[373]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[373]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[375]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[375]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[377]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[377]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[379]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[379]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[37]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[381]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[381]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[383]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[383]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[385]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[385]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[387]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[387]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[389]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[389]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[391]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[391]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[393]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[393]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[395]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[395]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[397]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[397]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[399]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[399]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[39]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[401]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[401]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[403]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[403]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[405]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[405]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[407]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[407]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[409]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[409]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[411]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[411]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[413]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[413]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[415]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[415]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[417]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[417]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[419]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[419]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[41]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[421]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[421]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[423]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[423]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[425]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[425]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[427]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[427]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[429]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[429]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[431]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[431]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[433]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[433]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[435]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[435]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[437]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[437]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[439]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[439]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[43]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[441]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[441]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[443]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[443]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[445]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[445]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[447]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[447]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[449]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[449]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[451]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[451]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[453]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[453]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[455]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[455]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[457]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[457]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[459]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[459]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[45]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[461]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[461]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[463]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[463]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[465]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[465]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[467]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[467]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[469]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[469]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[471]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[471]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[473]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[473]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[475]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[475]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[477]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[477]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[479]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[479]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[47]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[481]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[481]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[483]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[483]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[485]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[485]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[487]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[487]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[489]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[489]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[491]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[491]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[493]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[493]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[495]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[495]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[497]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[497]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[499]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[499]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[49]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[501]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[501]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[503]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[503]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[505]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[505]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[507]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[507]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[509]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[509]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[511]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[511]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[51]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[53]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[55]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[57]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[59]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[61]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[63]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[65]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[67]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[69]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[71]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[73]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[75]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[77]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[79]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[7]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[81]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[83]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[85]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[87]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[89]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[91]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[93]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[95]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[97]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[99]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[9]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]\(1 downto 0),
      \not_strict_mode.app_rd_data_valid_copy\ => \not_strict_mode.app_rd_data_valid_copy\,
      \not_strict_mode.app_rd_data_valid_copy_reg_0\ => ui_cmd0_n_31,
      \not_strict_mode.bypass__0\ => \not_strict_mode.bypass__0\,
      \not_strict_mode.occ_cnt_r_reg[0]_0\ => ui_cmd0_n_30,
      \not_strict_mode.occ_cnt_r_reg[1]_0\(1 downto 0) => \not_strict_mode.occ_cnt_r\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \not_strict_mode.rd_buf_we\,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]_0\(4 downto 0) => rd_data_buf_addr_r(4 downto 0),
      \not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0\ => \^ram_init_done_r\,
      \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0),
      rd_accepted => rd_accepted,
      \read_data_indx.rd_data_indx_r_reg[3]\(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0),
      reset_reg => reset_reg
    );
ui_wr_data0: entity work.mig_7series_0_mig_7series_v2_3_ui_wr_data
     port map (
      ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0),
      CLK => CLK,
      D(0) => ui_rd_data0_n_524,
      E(0) => E(0),
      Q(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0),
      accept_ns => accept_ns,
      app_rdy_ns => app_rdy_ns,
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0) => \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0),
      \init_calib_complete_reg_rep__14\ => \init_calib_complete_reg_rep__14\,
      \init_calib_complete_reg_rep__15\ => \init_calib_complete_reg_rep__15\,
      \init_calib_complete_reg_rep__16\ => \init_calib_complete_reg_rep__16\,
      \init_calib_complete_reg_rep__17\ => \init_calib_complete_reg_rep__17\,
      \init_calib_complete_reg_rep__18\ => \init_calib_complete_reg_rep__18\,
      \init_calib_complete_reg_rep__19\ => \init_calib_complete_reg_rep__19\,
      \init_calib_complete_reg_rep__20\ => \init_calib_complete_reg_rep__20\,
      \init_calib_complete_reg_rep__21\ => \init_calib_complete_reg_rep__21\,
      \init_calib_complete_reg_rep__22\ => \init_calib_complete_reg_rep__22\,
      \my_empty_reg[7]\(95 downto 0) => \my_empty_reg[7]\(95 downto 0),
      \my_empty_reg[7]_0\(575 downto 0) => \my_empty_reg[7]_0\(575 downto 0),
      p_0_in(0) => p_0_in(0),
      \pointer_ram.pointer_we\ => \pointer_ram.pointer_we\,
      \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0),
      ram_init_done_r => \^ram_init_done_r\,
      \read_data_indx.rd_data_upd_indx_r_reg_0\ => ui_cmd0_n_28,
      reset_reg => reset_reg,
      wr_accepted => wr_accepted,
      wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0),
      \wr_req_counter.wr_req_cnt_r_reg[0]_0\ => ui_cmd0_n_26,
      \wr_req_counter.wr_req_cnt_r_reg[0]_1\(0) => ui_cmd0_n_27,
      \wr_req_counter.wr_req_cnt_r_reg[1]_0\(1 downto 0) => \wr_req_counter.wr_req_cnt_r\(1 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_arb_mux is
  port (
    \last_master_r_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_cmd_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_ras_n_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_cas_n_reg[2]\ : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cke_r : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.int_read_this_rank\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \grant_r_reg[3]\ : out STD_LOGIC;
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \last_master_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 28 downto 0 );
    \cmd_pipe_plus.mc_address_reg[11]\ : out STD_LOGIC;
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\ : out STD_LOGIC;
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : out STD_LOGIC;
    override_demand_ns : out STD_LOGIC;
    \last_master_r_reg[0]\ : out STD_LOGIC;
    \last_master_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_address_reg[28]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \grant_r_reg[2]\ : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    \grant_r_reg[3]_1\ : out STD_LOGIC;
    \grant_r_reg[2]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_2\ : out STD_LOGIC;
    \grant_r_reg[1]_0\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : out STD_LOGIC;
    \last_master_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    act_this_rank : out STD_LOGIC;
    demand_priority_r_reg : out STD_LOGIC;
    demand_priority_r_reg_0 : out STD_LOGIC;
    demand_priority_r_reg_1 : out STD_LOGIC;
    demand_priority_r_reg_2 : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[8]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[7]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[6]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[40]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[39]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[36]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[35]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[34]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[32]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[30]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[29]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[28]_0\ : out STD_LOGIC;
    \grant_r_reg[3]_3\ : out STD_LOGIC;
    granted_row_ns : in STD_LOGIC;
    CLK : in STD_LOGIC;
    granted_col_ns : in STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : in STD_LOGIC;
    \pre_4_1_1T_arb.granted_pre_ns\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    rnk_config_valid_r_lcl_reg_1 : in STD_LOGIC;
    rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rd_wr_r_lcl_reg : in STD_LOGIC;
    rd_wr_r_lcl_reg_0 : in STD_LOGIC;
    rd_wr_r_lcl_reg_1 : in STD_LOGIC;
    rd_wr_r_lcl_reg_2 : in STD_LOGIC;
    rd_wr_r_lcl_reg_3 : in STD_LOGIC;
    rd_wr_r_lcl_reg_4 : in STD_LOGIC;
    \grant_r_reg[1]_1\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    rd_wr_r : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_aux_out0_reg[1]\ : in STD_LOGIC;
    rd_wr_r_lcl_reg_5 : in STD_LOGIC;
    rd_wr_r_lcl_reg_6 : in STD_LOGIC;
    act_wait_r_lcl_reg : in STD_LOGIC;
    act_wait_r_lcl_reg_0 : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    granted_row_r_reg : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    granted_row_r_reg_0 : in STD_LOGIC;
    \req_row_r_lcl_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    req_row_r : in STD_LOGIC_VECTOR ( 30 downto 0 );
    act_wait_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_2 : in STD_LOGIC;
    act_wait_r_lcl_reg_3 : in STD_LOGIC;
    maint_sre_r : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    act_wait_r_lcl_reg_4 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_2 : in STD_LOGIC;
    demand_priority_r_reg_3 : in STD_LOGIC;
    req_bank_rdy_ns : in STD_LOGIC;
    req_bank_rdy_ns_0 : in STD_LOGIC;
    demand_priority_r_reg_4 : in STD_LOGIC;
    req_bank_rdy_ns_1 : in STD_LOGIC;
    demand_priority_r_reg_5 : in STD_LOGIC;
    demand_priority_r_reg_6 : in STD_LOGIC;
    req_bank_rdy_ns_2 : in STD_LOGIC;
    \last_master_r_reg[3]_1\ : in STD_LOGIC;
    auto_pre_r_lcl_reg : in STD_LOGIC;
    auto_pre_r_lcl_reg_0 : in STD_LOGIC;
    auto_pre_r_lcl_reg_1 : in STD_LOGIC;
    auto_pre_r_lcl_reg_2 : in STD_LOGIC;
    ras_timer_zero_r_reg : in STD_LOGIC;
    ras_timer_zero_r_reg_0 : in STD_LOGIC;
    inhbt_act_faw_r : in STD_LOGIC;
    head_r_lcl_reg : in STD_LOGIC;
    \req_row_r_lcl_reg[13]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ofs_rdy_r : in STD_LOGIC;
    ofs_rdy_r_3 : in STD_LOGIC;
    ofs_rdy_r_4 : in STD_LOGIC;
    ofs_rdy_r_5 : in STD_LOGIC;
    wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \req_col_r_reg[9]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    auto_pre_r : in STD_LOGIC;
    auto_pre_r_6 : in STD_LOGIC;
    auto_pre_r_7 : in STD_LOGIC;
    auto_pre_r_8 : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \req_bank_r_lcl_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    req_bank_rdy_r : in STD_LOGIC;
    req_bank_rdy_r_9 : in STD_LOGIC;
    req_bank_rdy_r_10 : in STD_LOGIC;
    req_bank_rdy_r_11 : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_arb_mux : entity is "mig_7series_v2_3_arb_mux";
end mig_7series_0_mig_7series_v2_3_arb_mux;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_arb_mux is
  signal \^dic\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^col_data_buf_addr\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \col_mux.col_data_buf_addr_r\ : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \col_mux.col_periodic_rd_r\ : STD_LOGIC;
  signal \^col_rd_wr\ : STD_LOGIC;
  signal col_rd_wr_r : STD_LOGIC;
begin
  DIC(0) <= \^dic\(0);
  col_data_buf_addr(4 downto 0) <= \^col_data_buf_addr\(4 downto 0);
  col_rd_wr <= \^col_rd_wr\;
arb_row_col0: entity work.mig_7series_0_mig_7series_v2_3_arb_row_col
     port map (
      CLK => CLK,
      D(1 downto 0) => D(1 downto 0),
      DIC(0) => \^dic\(0),
      E(0) => E(0),
      Q(3 downto 0) => Q(3 downto 0),
      SR(0) => SR(0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg,
      act_wait_r_lcl_reg_0 => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_1,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_2,
      act_wait_r_lcl_reg_3 => act_wait_r_lcl_reg_3,
      act_wait_r_lcl_reg_4 => act_wait_r_lcl_reg_4,
      auto_pre_r => auto_pre_r,
      auto_pre_r_6 => auto_pre_r_6,
      auto_pre_r_7 => auto_pre_r_7,
      auto_pre_r_8 => auto_pre_r_8,
      auto_pre_r_lcl_reg => auto_pre_r_lcl_reg,
      auto_pre_r_lcl_reg_0 => auto_pre_r_lcl_reg_0,
      auto_pre_r_lcl_reg_1 => auto_pre_r_lcl_reg_1,
      auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_2,
      \cmd_pipe_plus.mc_address_reg[11]\ => \cmd_pipe_plus.mc_address_reg[11]\,
      \cmd_pipe_plus.mc_address_reg[28]\(3 downto 0) => \cmd_pipe_plus.mc_address_reg[28]\(3 downto 0),
      \cmd_pipe_plus.mc_address_reg[28]_0\ => \cmd_pipe_plus.mc_address_reg[28]_0\,
      \cmd_pipe_plus.mc_address_reg[29]\ => \cmd_pipe_plus.mc_address_reg[29]\,
      \cmd_pipe_plus.mc_address_reg[30]\ => \cmd_pipe_plus.mc_address_reg[30]\,
      \cmd_pipe_plus.mc_address_reg[32]\ => \cmd_pipe_plus.mc_address_reg[32]\,
      \cmd_pipe_plus.mc_address_reg[34]\ => \cmd_pipe_plus.mc_address_reg[34]\,
      \cmd_pipe_plus.mc_address_reg[35]\ => \cmd_pipe_plus.mc_address_reg[35]\,
      \cmd_pipe_plus.mc_address_reg[36]\ => \cmd_pipe_plus.mc_address_reg[36]\,
      \cmd_pipe_plus.mc_address_reg[39]\ => \cmd_pipe_plus.mc_address_reg[39]\,
      \cmd_pipe_plus.mc_address_reg[40]\ => \cmd_pipe_plus.mc_address_reg[40]\,
      \cmd_pipe_plus.mc_address_reg[41]\(28 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(28 downto 0),
      \cmd_pipe_plus.mc_aux_out0_reg[1]\ => \cmd_pipe_plus.mc_aux_out0_reg[1]\,
      \cmd_pipe_plus.mc_bank_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_bank_reg[6]\ => \cmd_pipe_plus.mc_bank_reg[6]\,
      \cmd_pipe_plus.mc_bank_reg[7]\ => \cmd_pipe_plus.mc_bank_reg[7]\,
      \cmd_pipe_plus.mc_bank_reg[8]\ => \cmd_pipe_plus.mc_bank_reg[8]\,
      \cmd_pipe_plus.mc_cas_n_reg[2]\ => \cmd_pipe_plus.mc_cas_n_reg[2]\,
      \cmd_pipe_plus.mc_cmd_reg[0]\ => \cmd_pipe_plus.mc_cmd_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \cmd_pipe_plus.mc_ras_n_reg[0]\ => \cmd_pipe_plus.mc_ras_n_reg[0]\,
      \cmd_pipe_plus.mc_we_n_reg[1]\ => \cmd_pipe_plus.mc_we_n_reg[1]\,
      \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0),
      col_data_buf_addr(4 downto 0) => \^col_data_buf_addr\(4 downto 0),
      \col_mux.col_data_buf_addr_r\(0) => \col_mux.col_data_buf_addr_r\(4),
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      col_rd_wr => \^col_rd_wr\,
      col_rd_wr_r => col_rd_wr_r,
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      demand_priority_r_reg => demand_priority_r_reg,
      demand_priority_r_reg_0 => demand_priority_r_reg_0,
      demand_priority_r_reg_1 => demand_priority_r_reg_1,
      demand_priority_r_reg_2 => demand_priority_r_reg_2,
      demand_priority_r_reg_3 => demand_priority_r_reg_3,
      demand_priority_r_reg_4 => demand_priority_r_reg_4,
      demand_priority_r_reg_5 => demand_priority_r_reg_5,
      demand_priority_r_reg_6 => demand_priority_r_reg_6,
      \generate_maint_cmds.insert_maint_r_lcl_reg\ => \generate_maint_cmds.insert_maint_r_lcl_reg\,
      \grant_r_reg[0]\ => \grant_r_reg[0]\,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[1]_0\ => \grant_r_reg[1]_0\,
      \grant_r_reg[1]_1\ => \grant_r_reg[1]_1\,
      \grant_r_reg[2]\ => \grant_r_reg[2]\,
      \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\,
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_0\,
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_1\,
      \grant_r_reg[3]_2\ => \grant_r_reg[3]_2\,
      \grant_r_reg[3]_3\ => \grant_r_reg[3]_3\,
      granted_col_ns => granted_col_ns,
      granted_row_ns => granted_row_ns,
      granted_row_r_reg_0 => granted_row_r_reg,
      granted_row_r_reg_1 => granted_row_r_reg_0,
      head_r_lcl_reg => head_r_lcl_reg,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \last_master_r_reg[0]\(0) => \last_master_r_reg[0]\,
      \last_master_r_reg[1]\ => \last_master_r_reg[1]\,
      \last_master_r_reg[1]_0\(0) => \last_master_r_reg[1]_0\(0),
      \last_master_r_reg[3]\(3 downto 0) => \last_master_r_reg[3]\(3 downto 0),
      \last_master_r_reg[3]_0\(0) => \last_master_r_reg[3]_0\(0),
      \last_master_r_reg[3]_1\ => \last_master_r_reg[3]_1\,
      maint_sre_r => maint_sre_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(1 downto 0) => mc_ras_n_ns(1 downto 0),
      ofs_rdy_r => ofs_rdy_r,
      ofs_rdy_r_3 => ofs_rdy_r_3,
      ofs_rdy_r_4 => ofs_rdy_r_4,
      ofs_rdy_r_5 => ofs_rdy_r_5,
      override_demand_ns => override_demand_ns,
      \periodic_rd_generation.int_read_this_rank\ => \periodic_rd_generation.int_read_this_rank\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(1 downto 0) => rd_wr_r(1 downto 0),
      rd_wr_r_lcl_reg => rd_wr_r_lcl_reg,
      rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg_0,
      rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_1,
      rd_wr_r_lcl_reg_2 => rd_wr_r_lcl_reg_2,
      rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_3,
      rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg_4,
      rd_wr_r_lcl_reg_5 => rd_wr_r_lcl_reg_5,
      rd_wr_r_lcl_reg_6 => rd_wr_r_lcl_reg_6,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_1\(2 downto 0),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \req_bank_r_lcl_reg[2]_2\(2 downto 0),
      req_bank_rdy_ns => req_bank_rdy_ns,
      req_bank_rdy_ns_0 => req_bank_rdy_ns_0,
      req_bank_rdy_ns_1 => req_bank_rdy_ns_1,
      req_bank_rdy_ns_2 => req_bank_rdy_ns_2,
      req_bank_rdy_r => req_bank_rdy_r,
      req_bank_rdy_r_10 => req_bank_rdy_r_10,
      req_bank_rdy_r_11 => req_bank_rdy_r_11,
      req_bank_rdy_r_9 => req_bank_rdy_r_9,
      \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_1\(9 downto 0),
      \req_col_r_reg[9]_2\(9 downto 0) => \req_col_r_reg[9]_2\(9 downto 0),
      req_data_buf_addr_r(19 downto 0) => req_data_buf_addr_r(19 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      req_row_r(30 downto 0) => req_row_r(30 downto 0),
      \req_row_r_lcl_reg[13]\(13 downto 0) => \req_row_r_lcl_reg[13]\(13 downto 0),
      \req_row_r_lcl_reg[13]_0\(8 downto 0) => \req_row_r_lcl_reg[13]_0\(8 downto 0),
      \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]\,
      rnk_config_valid_r_lcl_reg_0 => rnk_config_valid_r_lcl_reg,
      rnk_config_valid_r_lcl_reg_1 => rnk_config_valid_r_lcl_reg_0,
      rnk_config_valid_r_lcl_reg_2 => rnk_config_valid_r_lcl_reg_1,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\ => \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\,
      wait_for_maint_r_lcl_reg => wait_for_maint_r_lcl_reg,
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_0,
      wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_1,
      wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_2,
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]\ => \wtr_timer.wtr_cnt_r_reg[0]\,
      \wtr_timer.wtr_cnt_r_reg[0]_0\ => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      \wtr_timer.wtr_cnt_r_reg[1]\(0) => \wtr_timer.wtr_cnt_r_reg[1]\(0)
    );
arb_select0: entity work.mig_7series_0_mig_7series_v2_3_arb_select
     port map (
      CLK => CLK,
      DIC(0) => \^dic\(0),
      SR(0) => SR(0),
      cke_r => cke_r,
      col_data_buf_addr(0) => \^col_data_buf_addr\(4),
      \col_mux.col_data_buf_addr_r\(0) => \col_mux.col_data_buf_addr_r\(4),
      \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\,
      col_rd_wr => \^col_rd_wr\,
      col_rd_wr_r => col_rd_wr_r,
      mc_cke_ns(0) => mc_cke_ns(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes is
  port (
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 35 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 35 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 3 downto 0 );
    idelay_ld_rst_0 : out STD_LOGIC;
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    idelay_ld_rst_1 : out STD_LOGIC;
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    idelay_ld_rst_2 : out STD_LOGIC;
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    idelay_ld_rst_3 : out STD_LOGIC;
    \_phy_ctl_full_p__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ref_dll_lock_w__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \mcGo_w__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[8]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[16]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[10]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[18]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[12]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[20]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[14]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[22]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[72]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[80]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[64]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[74]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[82]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[66]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[76]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[84]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[68]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[78]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[86]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[70]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[136]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[144]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[128]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[138]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[146]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[130]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[140]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[148]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[132]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[142]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[150]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[134]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[200]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[208]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[192]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[202]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[210]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[194]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[204]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[212]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[196]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[206]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[214]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[198]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[264]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[272]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[256]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[266]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[274]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[258]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[268]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[276]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[260]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[270]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[278]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[262]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[328]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[336]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[320]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[330]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[338]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[322]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[332]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[340]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[324]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[334]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[342]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[326]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[392]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[400]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[384]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[394]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[402]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[386]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[396]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[404]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[388]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[398]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[406]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[390]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[456]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[464]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[448]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[458]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[466]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[450]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[460]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[468]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[452]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[462]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[470]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[454]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC_VECTOR ( 255 downto 0 );
    \not_strict_mode.app_rd_data_reg[24]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[26]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[28]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[30]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[88]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[90]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[92]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[94]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[152]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[154]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[156]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[158]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[216]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[218]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[220]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[222]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[280]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[282]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[284]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[286]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[344]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[346]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[348]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[350]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[408]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[410]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[412]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[414]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[472]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[474]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[476]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[478]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_0\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_2\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \po_rdval_cnt_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \pi_rdval_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    ofs_rdy_r_reg : out STD_LOGIC;
    ofs_rdy_r_reg_0 : out STD_LOGIC;
    rd_active_r_reg : out STD_LOGIC;
    rd_active_r_reg_0 : out STD_LOGIC;
    byte_rd_en_v_0 : out STD_LOGIC;
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_6 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \calib_sel_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[479]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[478]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[477]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[412]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[475]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[474]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[473]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[408]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \calib_sel_reg[1]_6\ : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    \calib_sel_reg[1]_7\ : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_0 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_0 : in STD_LOGIC;
    \calib_sel_reg[1]_8\ : in STD_LOGIC;
    \calib_sel_reg[1]_9\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_10\ : in STD_LOGIC;
    \calib_sel_reg[1]_11\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_0 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[471]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[470]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[469]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[404]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[467]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[466]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[465]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[400]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_12\ : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    \calib_sel_reg[1]_13\ : in STD_LOGIC;
    \calib_sel_reg[1]_14\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_1 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_1 : in STD_LOGIC;
    \calib_sel_reg[1]_15\ : in STD_LOGIC;
    \calib_sel_reg[1]_16\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_17\ : in STD_LOGIC;
    \calib_sel_reg[1]_18\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_1 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[463]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[462]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[461]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[396]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[459]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[458]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[457]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[392]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    idelay_ce_r2_reg : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    pi_stg2_load_reg : in STD_LOGIC;
    \calib_sel_reg[1]_19\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_2 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_2 : in STD_LOGIC;
    \pi_rst_stg1_cal_reg[0]\ : in STD_LOGIC;
    \pi_stg2_reg_l_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg : in STD_LOGIC;
    \calib_sel_reg[0]_0\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_2 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[455]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[454]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[453]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[388]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[451]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[450]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[449]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[384]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_ctl_mstr_empty : in STD_LOGIC;
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    in0 : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_data_wr_en : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[571]\ : in STD_LOGIC_VECTOR ( 111 downto 0 );
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    DOC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    C_byte_rd_en : in STD_LOGIC;
    byte_rd_en_v_1 : in STD_LOGIC;
    \my_empty_reg[3]\ : in STD_LOGIC;
    A_byte_rd_en : in STD_LOGIC;
    \my_empty_reg[3]_0\ : in STD_LOGIC;
    B_byte_rd_en : in STD_LOGIC;
    \my_empty_reg[3]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_0\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_1\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_2\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_3\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_4\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_5\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_6\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_7\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_8\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_9\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_10\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_11\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_12\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_13\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_14\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_15\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_16\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_17\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_18\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_19\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_20\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_21\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_22\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_23\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_24\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_25\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_26\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_27\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_28\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_29\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_30\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_31\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_32\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_33\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_34\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_35\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_36\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_37\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_38\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_39\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_40\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_41\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_42\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_43\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_44\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_45\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_46\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_47\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_48\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_49\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_50\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_51\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_52\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_53\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_54\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_55\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_56\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_57\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_58\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_59\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_60\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_61\ : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]_62\ : in STD_LOGIC;
    mux_wrdata : in STD_LOGIC_VECTOR ( 207 downto 0 );
    \write_buffer.wr_buf_out_data_reg[351]\ : in STD_LOGIC_VECTOR ( 47 downto 0 );
    mux_wrdata_mask : in STD_LOGIC_VECTOR ( 31 downto 0 );
    byte_rd_en_v_2 : in STD_LOGIC;
    \calib_sel_reg[1]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes : entity is "mig_7series_v2_3_ddr_phy_4lanes";
end mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes is
  signal A_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal A_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal A_rst_primitives : STD_LOGIC;
  signal B_rclk : STD_LOGIC;
  signal C_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal D_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal D_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_236\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_237\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_238\ : STD_LOGIC;
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_239\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_155\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_156\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_205\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_206\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_207\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_208\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_209\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_210\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_212\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_213\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_214\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_215\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_216\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_217\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_218\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_219\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_220\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_C.ddr_byte_lane_C_n_234\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_171\ : STD_LOGIC;
  signal \ddr_byte_lane_D.ddr_byte_lane_D_n_22\ : STD_LOGIC;
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal if_empty_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal if_empty_r_2 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal if_empty_r_5 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^not_strict_mode.app_rd_data_reg[0]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[10]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[11]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[128]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[129]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[12]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[130]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[131]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[132]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[133]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[134]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[135]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[136]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[137]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[138]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[139]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[13]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[140]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[141]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[142]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[143]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[144]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[145]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[146]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[147]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[148]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[149]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[14]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[150]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[151]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[15]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[16]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[17]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[18]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[192]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[193]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[194]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[195]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[196]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[197]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[198]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[199]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[19]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[1]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[200]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[201]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[202]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[203]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[204]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[205]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[206]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[207]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[208]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[209]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[20]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[210]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[211]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[212]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[213]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[214]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[215]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[21]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[22]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[23]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[256]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[257]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[258]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[259]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[260]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[261]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[262]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[263]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[264]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[265]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[266]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[267]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[268]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[269]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[270]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[271]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[272]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[273]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[274]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[275]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[276]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[277]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[278]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[279]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[2]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[320]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[321]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[322]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[323]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[324]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[325]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[326]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[327]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[328]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[329]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[330]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[331]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[332]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[333]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[334]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[335]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[336]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[337]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[338]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[339]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[340]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[341]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[342]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[343]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[384]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[385]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[386]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[387]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[388]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[389]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[390]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[391]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[392]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[393]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[394]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[395]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[396]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[397]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[398]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[399]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[3]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[400]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[401]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[402]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[403]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[404]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[405]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[406]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[407]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[448]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[449]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[450]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[451]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[452]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[453]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[454]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[455]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[456]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[457]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[458]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[459]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[460]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[461]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[462]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[463]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[464]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[465]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[466]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[467]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[468]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[469]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[470]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[471]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[4]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[5]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[64]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[65]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[66]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[67]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[68]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[69]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[6]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[70]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[71]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[72]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[73]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[74]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[75]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[76]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[77]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[78]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[79]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[7]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[80]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[81]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[82]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[83]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[84]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[85]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[86]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[87]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[8]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[9]\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_6\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal phy_control_i_n_0 : STD_LOGIC;
  signal phy_control_i_n_1 : STD_LOGIC;
  signal phy_control_i_n_14 : STD_LOGIC;
  signal phy_control_i_n_15 : STD_LOGIC;
  signal phy_control_i_n_16 : STD_LOGIC;
  signal phy_control_i_n_17 : STD_LOGIC;
  signal phy_control_i_n_3 : STD_LOGIC;
  signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rclk_delay_11 : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_i_1__0_n_0\ : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC;
  signal \^ref_dll_lock_w__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rst_out_i_1__0_n_0\ : STD_LOGIC;
  signal rst_out_reg_n_0 : STD_LOGIC;
  signal rst_primitives : STD_LOGIC;
  signal \rst_primitives_i_1__0_n_0\ : STD_LOGIC;
  signal rst_r4 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE";
  attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg ";
  attribute srl_name : string;
  attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 ";
begin
  \not_strict_mode.app_rd_data_reg[0]\ <= \^not_strict_mode.app_rd_data_reg[0]\;
  \not_strict_mode.app_rd_data_reg[10]\ <= \^not_strict_mode.app_rd_data_reg[10]\;
  \not_strict_mode.app_rd_data_reg[11]\ <= \^not_strict_mode.app_rd_data_reg[11]\;
  \not_strict_mode.app_rd_data_reg[128]\ <= \^not_strict_mode.app_rd_data_reg[128]\;
  \not_strict_mode.app_rd_data_reg[129]\ <= \^not_strict_mode.app_rd_data_reg[129]\;
  \not_strict_mode.app_rd_data_reg[12]\ <= \^not_strict_mode.app_rd_data_reg[12]\;
  \not_strict_mode.app_rd_data_reg[130]\ <= \^not_strict_mode.app_rd_data_reg[130]\;
  \not_strict_mode.app_rd_data_reg[131]\ <= \^not_strict_mode.app_rd_data_reg[131]\;
  \not_strict_mode.app_rd_data_reg[132]\ <= \^not_strict_mode.app_rd_data_reg[132]\;
  \not_strict_mode.app_rd_data_reg[133]\ <= \^not_strict_mode.app_rd_data_reg[133]\;
  \not_strict_mode.app_rd_data_reg[134]\ <= \^not_strict_mode.app_rd_data_reg[134]\;
  \not_strict_mode.app_rd_data_reg[135]\ <= \^not_strict_mode.app_rd_data_reg[135]\;
  \not_strict_mode.app_rd_data_reg[136]\ <= \^not_strict_mode.app_rd_data_reg[136]\;
  \not_strict_mode.app_rd_data_reg[137]\ <= \^not_strict_mode.app_rd_data_reg[137]\;
  \not_strict_mode.app_rd_data_reg[138]\ <= \^not_strict_mode.app_rd_data_reg[138]\;
  \not_strict_mode.app_rd_data_reg[139]\ <= \^not_strict_mode.app_rd_data_reg[139]\;
  \not_strict_mode.app_rd_data_reg[13]\ <= \^not_strict_mode.app_rd_data_reg[13]\;
  \not_strict_mode.app_rd_data_reg[140]\ <= \^not_strict_mode.app_rd_data_reg[140]\;
  \not_strict_mode.app_rd_data_reg[141]\ <= \^not_strict_mode.app_rd_data_reg[141]\;
  \not_strict_mode.app_rd_data_reg[142]\ <= \^not_strict_mode.app_rd_data_reg[142]\;
  \not_strict_mode.app_rd_data_reg[143]\ <= \^not_strict_mode.app_rd_data_reg[143]\;
  \not_strict_mode.app_rd_data_reg[144]\ <= \^not_strict_mode.app_rd_data_reg[144]\;
  \not_strict_mode.app_rd_data_reg[145]\ <= \^not_strict_mode.app_rd_data_reg[145]\;
  \not_strict_mode.app_rd_data_reg[146]\ <= \^not_strict_mode.app_rd_data_reg[146]\;
  \not_strict_mode.app_rd_data_reg[147]\ <= \^not_strict_mode.app_rd_data_reg[147]\;
  \not_strict_mode.app_rd_data_reg[148]\ <= \^not_strict_mode.app_rd_data_reg[148]\;
  \not_strict_mode.app_rd_data_reg[149]\ <= \^not_strict_mode.app_rd_data_reg[149]\;
  \not_strict_mode.app_rd_data_reg[14]\ <= \^not_strict_mode.app_rd_data_reg[14]\;
  \not_strict_mode.app_rd_data_reg[150]\ <= \^not_strict_mode.app_rd_data_reg[150]\;
  \not_strict_mode.app_rd_data_reg[151]\ <= \^not_strict_mode.app_rd_data_reg[151]\;
  \not_strict_mode.app_rd_data_reg[15]\ <= \^not_strict_mode.app_rd_data_reg[15]\;
  \not_strict_mode.app_rd_data_reg[16]\ <= \^not_strict_mode.app_rd_data_reg[16]\;
  \not_strict_mode.app_rd_data_reg[17]\ <= \^not_strict_mode.app_rd_data_reg[17]\;
  \not_strict_mode.app_rd_data_reg[18]\ <= \^not_strict_mode.app_rd_data_reg[18]\;
  \not_strict_mode.app_rd_data_reg[192]\ <= \^not_strict_mode.app_rd_data_reg[192]\;
  \not_strict_mode.app_rd_data_reg[193]\ <= \^not_strict_mode.app_rd_data_reg[193]\;
  \not_strict_mode.app_rd_data_reg[194]\ <= \^not_strict_mode.app_rd_data_reg[194]\;
  \not_strict_mode.app_rd_data_reg[195]\ <= \^not_strict_mode.app_rd_data_reg[195]\;
  \not_strict_mode.app_rd_data_reg[196]\ <= \^not_strict_mode.app_rd_data_reg[196]\;
  \not_strict_mode.app_rd_data_reg[197]\ <= \^not_strict_mode.app_rd_data_reg[197]\;
  \not_strict_mode.app_rd_data_reg[198]\ <= \^not_strict_mode.app_rd_data_reg[198]\;
  \not_strict_mode.app_rd_data_reg[199]\ <= \^not_strict_mode.app_rd_data_reg[199]\;
  \not_strict_mode.app_rd_data_reg[19]\ <= \^not_strict_mode.app_rd_data_reg[19]\;
  \not_strict_mode.app_rd_data_reg[1]\ <= \^not_strict_mode.app_rd_data_reg[1]\;
  \not_strict_mode.app_rd_data_reg[200]\ <= \^not_strict_mode.app_rd_data_reg[200]\;
  \not_strict_mode.app_rd_data_reg[201]\ <= \^not_strict_mode.app_rd_data_reg[201]\;
  \not_strict_mode.app_rd_data_reg[202]\ <= \^not_strict_mode.app_rd_data_reg[202]\;
  \not_strict_mode.app_rd_data_reg[203]\ <= \^not_strict_mode.app_rd_data_reg[203]\;
  \not_strict_mode.app_rd_data_reg[204]\ <= \^not_strict_mode.app_rd_data_reg[204]\;
  \not_strict_mode.app_rd_data_reg[205]\ <= \^not_strict_mode.app_rd_data_reg[205]\;
  \not_strict_mode.app_rd_data_reg[206]\ <= \^not_strict_mode.app_rd_data_reg[206]\;
  \not_strict_mode.app_rd_data_reg[207]\ <= \^not_strict_mode.app_rd_data_reg[207]\;
  \not_strict_mode.app_rd_data_reg[208]\ <= \^not_strict_mode.app_rd_data_reg[208]\;
  \not_strict_mode.app_rd_data_reg[209]\ <= \^not_strict_mode.app_rd_data_reg[209]\;
  \not_strict_mode.app_rd_data_reg[20]\ <= \^not_strict_mode.app_rd_data_reg[20]\;
  \not_strict_mode.app_rd_data_reg[210]\ <= \^not_strict_mode.app_rd_data_reg[210]\;
  \not_strict_mode.app_rd_data_reg[211]\ <= \^not_strict_mode.app_rd_data_reg[211]\;
  \not_strict_mode.app_rd_data_reg[212]\ <= \^not_strict_mode.app_rd_data_reg[212]\;
  \not_strict_mode.app_rd_data_reg[213]\ <= \^not_strict_mode.app_rd_data_reg[213]\;
  \not_strict_mode.app_rd_data_reg[214]\ <= \^not_strict_mode.app_rd_data_reg[214]\;
  \not_strict_mode.app_rd_data_reg[215]\ <= \^not_strict_mode.app_rd_data_reg[215]\;
  \not_strict_mode.app_rd_data_reg[21]\ <= \^not_strict_mode.app_rd_data_reg[21]\;
  \not_strict_mode.app_rd_data_reg[22]\ <= \^not_strict_mode.app_rd_data_reg[22]\;
  \not_strict_mode.app_rd_data_reg[23]\ <= \^not_strict_mode.app_rd_data_reg[23]\;
  \not_strict_mode.app_rd_data_reg[256]\ <= \^not_strict_mode.app_rd_data_reg[256]\;
  \not_strict_mode.app_rd_data_reg[257]\ <= \^not_strict_mode.app_rd_data_reg[257]\;
  \not_strict_mode.app_rd_data_reg[258]\ <= \^not_strict_mode.app_rd_data_reg[258]\;
  \not_strict_mode.app_rd_data_reg[259]\ <= \^not_strict_mode.app_rd_data_reg[259]\;
  \not_strict_mode.app_rd_data_reg[260]\ <= \^not_strict_mode.app_rd_data_reg[260]\;
  \not_strict_mode.app_rd_data_reg[261]\ <= \^not_strict_mode.app_rd_data_reg[261]\;
  \not_strict_mode.app_rd_data_reg[262]\ <= \^not_strict_mode.app_rd_data_reg[262]\;
  \not_strict_mode.app_rd_data_reg[263]\ <= \^not_strict_mode.app_rd_data_reg[263]\;
  \not_strict_mode.app_rd_data_reg[264]\ <= \^not_strict_mode.app_rd_data_reg[264]\;
  \not_strict_mode.app_rd_data_reg[265]\ <= \^not_strict_mode.app_rd_data_reg[265]\;
  \not_strict_mode.app_rd_data_reg[266]\ <= \^not_strict_mode.app_rd_data_reg[266]\;
  \not_strict_mode.app_rd_data_reg[267]\ <= \^not_strict_mode.app_rd_data_reg[267]\;
  \not_strict_mode.app_rd_data_reg[268]\ <= \^not_strict_mode.app_rd_data_reg[268]\;
  \not_strict_mode.app_rd_data_reg[269]\ <= \^not_strict_mode.app_rd_data_reg[269]\;
  \not_strict_mode.app_rd_data_reg[270]\ <= \^not_strict_mode.app_rd_data_reg[270]\;
  \not_strict_mode.app_rd_data_reg[271]\ <= \^not_strict_mode.app_rd_data_reg[271]\;
  \not_strict_mode.app_rd_data_reg[272]\ <= \^not_strict_mode.app_rd_data_reg[272]\;
  \not_strict_mode.app_rd_data_reg[273]\ <= \^not_strict_mode.app_rd_data_reg[273]\;
  \not_strict_mode.app_rd_data_reg[274]\ <= \^not_strict_mode.app_rd_data_reg[274]\;
  \not_strict_mode.app_rd_data_reg[275]\ <= \^not_strict_mode.app_rd_data_reg[275]\;
  \not_strict_mode.app_rd_data_reg[276]\ <= \^not_strict_mode.app_rd_data_reg[276]\;
  \not_strict_mode.app_rd_data_reg[277]\ <= \^not_strict_mode.app_rd_data_reg[277]\;
  \not_strict_mode.app_rd_data_reg[278]\ <= \^not_strict_mode.app_rd_data_reg[278]\;
  \not_strict_mode.app_rd_data_reg[279]\ <= \^not_strict_mode.app_rd_data_reg[279]\;
  \not_strict_mode.app_rd_data_reg[2]\ <= \^not_strict_mode.app_rd_data_reg[2]\;
  \not_strict_mode.app_rd_data_reg[320]\ <= \^not_strict_mode.app_rd_data_reg[320]\;
  \not_strict_mode.app_rd_data_reg[321]\ <= \^not_strict_mode.app_rd_data_reg[321]\;
  \not_strict_mode.app_rd_data_reg[322]\ <= \^not_strict_mode.app_rd_data_reg[322]\;
  \not_strict_mode.app_rd_data_reg[323]\ <= \^not_strict_mode.app_rd_data_reg[323]\;
  \not_strict_mode.app_rd_data_reg[324]\ <= \^not_strict_mode.app_rd_data_reg[324]\;
  \not_strict_mode.app_rd_data_reg[325]\ <= \^not_strict_mode.app_rd_data_reg[325]\;
  \not_strict_mode.app_rd_data_reg[326]\ <= \^not_strict_mode.app_rd_data_reg[326]\;
  \not_strict_mode.app_rd_data_reg[327]\ <= \^not_strict_mode.app_rd_data_reg[327]\;
  \not_strict_mode.app_rd_data_reg[328]\ <= \^not_strict_mode.app_rd_data_reg[328]\;
  \not_strict_mode.app_rd_data_reg[329]\ <= \^not_strict_mode.app_rd_data_reg[329]\;
  \not_strict_mode.app_rd_data_reg[330]\ <= \^not_strict_mode.app_rd_data_reg[330]\;
  \not_strict_mode.app_rd_data_reg[331]\ <= \^not_strict_mode.app_rd_data_reg[331]\;
  \not_strict_mode.app_rd_data_reg[332]\ <= \^not_strict_mode.app_rd_data_reg[332]\;
  \not_strict_mode.app_rd_data_reg[333]\ <= \^not_strict_mode.app_rd_data_reg[333]\;
  \not_strict_mode.app_rd_data_reg[334]\ <= \^not_strict_mode.app_rd_data_reg[334]\;
  \not_strict_mode.app_rd_data_reg[335]\ <= \^not_strict_mode.app_rd_data_reg[335]\;
  \not_strict_mode.app_rd_data_reg[336]\ <= \^not_strict_mode.app_rd_data_reg[336]\;
  \not_strict_mode.app_rd_data_reg[337]\ <= \^not_strict_mode.app_rd_data_reg[337]\;
  \not_strict_mode.app_rd_data_reg[338]\ <= \^not_strict_mode.app_rd_data_reg[338]\;
  \not_strict_mode.app_rd_data_reg[339]\ <= \^not_strict_mode.app_rd_data_reg[339]\;
  \not_strict_mode.app_rd_data_reg[340]\ <= \^not_strict_mode.app_rd_data_reg[340]\;
  \not_strict_mode.app_rd_data_reg[341]\ <= \^not_strict_mode.app_rd_data_reg[341]\;
  \not_strict_mode.app_rd_data_reg[342]\ <= \^not_strict_mode.app_rd_data_reg[342]\;
  \not_strict_mode.app_rd_data_reg[343]\ <= \^not_strict_mode.app_rd_data_reg[343]\;
  \not_strict_mode.app_rd_data_reg[384]\ <= \^not_strict_mode.app_rd_data_reg[384]\;
  \not_strict_mode.app_rd_data_reg[385]\ <= \^not_strict_mode.app_rd_data_reg[385]\;
  \not_strict_mode.app_rd_data_reg[386]\ <= \^not_strict_mode.app_rd_data_reg[386]\;
  \not_strict_mode.app_rd_data_reg[387]\ <= \^not_strict_mode.app_rd_data_reg[387]\;
  \not_strict_mode.app_rd_data_reg[388]\ <= \^not_strict_mode.app_rd_data_reg[388]\;
  \not_strict_mode.app_rd_data_reg[389]\ <= \^not_strict_mode.app_rd_data_reg[389]\;
  \not_strict_mode.app_rd_data_reg[390]\ <= \^not_strict_mode.app_rd_data_reg[390]\;
  \not_strict_mode.app_rd_data_reg[391]\ <= \^not_strict_mode.app_rd_data_reg[391]\;
  \not_strict_mode.app_rd_data_reg[392]\ <= \^not_strict_mode.app_rd_data_reg[392]\;
  \not_strict_mode.app_rd_data_reg[393]\ <= \^not_strict_mode.app_rd_data_reg[393]\;
  \not_strict_mode.app_rd_data_reg[394]\ <= \^not_strict_mode.app_rd_data_reg[394]\;
  \not_strict_mode.app_rd_data_reg[395]\ <= \^not_strict_mode.app_rd_data_reg[395]\;
  \not_strict_mode.app_rd_data_reg[396]\ <= \^not_strict_mode.app_rd_data_reg[396]\;
  \not_strict_mode.app_rd_data_reg[397]\ <= \^not_strict_mode.app_rd_data_reg[397]\;
  \not_strict_mode.app_rd_data_reg[398]\ <= \^not_strict_mode.app_rd_data_reg[398]\;
  \not_strict_mode.app_rd_data_reg[399]\ <= \^not_strict_mode.app_rd_data_reg[399]\;
  \not_strict_mode.app_rd_data_reg[3]\ <= \^not_strict_mode.app_rd_data_reg[3]\;
  \not_strict_mode.app_rd_data_reg[400]\ <= \^not_strict_mode.app_rd_data_reg[400]\;
  \not_strict_mode.app_rd_data_reg[401]\ <= \^not_strict_mode.app_rd_data_reg[401]\;
  \not_strict_mode.app_rd_data_reg[402]\ <= \^not_strict_mode.app_rd_data_reg[402]\;
  \not_strict_mode.app_rd_data_reg[403]\ <= \^not_strict_mode.app_rd_data_reg[403]\;
  \not_strict_mode.app_rd_data_reg[404]\ <= \^not_strict_mode.app_rd_data_reg[404]\;
  \not_strict_mode.app_rd_data_reg[405]\ <= \^not_strict_mode.app_rd_data_reg[405]\;
  \not_strict_mode.app_rd_data_reg[406]\ <= \^not_strict_mode.app_rd_data_reg[406]\;
  \not_strict_mode.app_rd_data_reg[407]\ <= \^not_strict_mode.app_rd_data_reg[407]\;
  \not_strict_mode.app_rd_data_reg[448]\ <= \^not_strict_mode.app_rd_data_reg[448]\;
  \not_strict_mode.app_rd_data_reg[449]\ <= \^not_strict_mode.app_rd_data_reg[449]\;
  \not_strict_mode.app_rd_data_reg[450]\ <= \^not_strict_mode.app_rd_data_reg[450]\;
  \not_strict_mode.app_rd_data_reg[451]\ <= \^not_strict_mode.app_rd_data_reg[451]\;
  \not_strict_mode.app_rd_data_reg[452]\ <= \^not_strict_mode.app_rd_data_reg[452]\;
  \not_strict_mode.app_rd_data_reg[453]\ <= \^not_strict_mode.app_rd_data_reg[453]\;
  \not_strict_mode.app_rd_data_reg[454]\ <= \^not_strict_mode.app_rd_data_reg[454]\;
  \not_strict_mode.app_rd_data_reg[455]\ <= \^not_strict_mode.app_rd_data_reg[455]\;
  \not_strict_mode.app_rd_data_reg[456]\ <= \^not_strict_mode.app_rd_data_reg[456]\;
  \not_strict_mode.app_rd_data_reg[457]\ <= \^not_strict_mode.app_rd_data_reg[457]\;
  \not_strict_mode.app_rd_data_reg[458]\ <= \^not_strict_mode.app_rd_data_reg[458]\;
  \not_strict_mode.app_rd_data_reg[459]\ <= \^not_strict_mode.app_rd_data_reg[459]\;
  \not_strict_mode.app_rd_data_reg[460]\ <= \^not_strict_mode.app_rd_data_reg[460]\;
  \not_strict_mode.app_rd_data_reg[461]\ <= \^not_strict_mode.app_rd_data_reg[461]\;
  \not_strict_mode.app_rd_data_reg[462]\ <= \^not_strict_mode.app_rd_data_reg[462]\;
  \not_strict_mode.app_rd_data_reg[463]\ <= \^not_strict_mode.app_rd_data_reg[463]\;
  \not_strict_mode.app_rd_data_reg[464]\ <= \^not_strict_mode.app_rd_data_reg[464]\;
  \not_strict_mode.app_rd_data_reg[465]\ <= \^not_strict_mode.app_rd_data_reg[465]\;
  \not_strict_mode.app_rd_data_reg[466]\ <= \^not_strict_mode.app_rd_data_reg[466]\;
  \not_strict_mode.app_rd_data_reg[467]\ <= \^not_strict_mode.app_rd_data_reg[467]\;
  \not_strict_mode.app_rd_data_reg[468]\ <= \^not_strict_mode.app_rd_data_reg[468]\;
  \not_strict_mode.app_rd_data_reg[469]\ <= \^not_strict_mode.app_rd_data_reg[469]\;
  \not_strict_mode.app_rd_data_reg[470]\ <= \^not_strict_mode.app_rd_data_reg[470]\;
  \not_strict_mode.app_rd_data_reg[471]\ <= \^not_strict_mode.app_rd_data_reg[471]\;
  \not_strict_mode.app_rd_data_reg[4]\ <= \^not_strict_mode.app_rd_data_reg[4]\;
  \not_strict_mode.app_rd_data_reg[5]\ <= \^not_strict_mode.app_rd_data_reg[5]\;
  \not_strict_mode.app_rd_data_reg[64]\ <= \^not_strict_mode.app_rd_data_reg[64]\;
  \not_strict_mode.app_rd_data_reg[65]\ <= \^not_strict_mode.app_rd_data_reg[65]\;
  \not_strict_mode.app_rd_data_reg[66]\ <= \^not_strict_mode.app_rd_data_reg[66]\;
  \not_strict_mode.app_rd_data_reg[67]\ <= \^not_strict_mode.app_rd_data_reg[67]\;
  \not_strict_mode.app_rd_data_reg[68]\ <= \^not_strict_mode.app_rd_data_reg[68]\;
  \not_strict_mode.app_rd_data_reg[69]\ <= \^not_strict_mode.app_rd_data_reg[69]\;
  \not_strict_mode.app_rd_data_reg[6]\ <= \^not_strict_mode.app_rd_data_reg[6]\;
  \not_strict_mode.app_rd_data_reg[70]\ <= \^not_strict_mode.app_rd_data_reg[70]\;
  \not_strict_mode.app_rd_data_reg[71]\ <= \^not_strict_mode.app_rd_data_reg[71]\;
  \not_strict_mode.app_rd_data_reg[72]\ <= \^not_strict_mode.app_rd_data_reg[72]\;
  \not_strict_mode.app_rd_data_reg[73]\ <= \^not_strict_mode.app_rd_data_reg[73]\;
  \not_strict_mode.app_rd_data_reg[74]\ <= \^not_strict_mode.app_rd_data_reg[74]\;
  \not_strict_mode.app_rd_data_reg[75]\ <= \^not_strict_mode.app_rd_data_reg[75]\;
  \not_strict_mode.app_rd_data_reg[76]\ <= \^not_strict_mode.app_rd_data_reg[76]\;
  \not_strict_mode.app_rd_data_reg[77]\ <= \^not_strict_mode.app_rd_data_reg[77]\;
  \not_strict_mode.app_rd_data_reg[78]\ <= \^not_strict_mode.app_rd_data_reg[78]\;
  \not_strict_mode.app_rd_data_reg[79]\ <= \^not_strict_mode.app_rd_data_reg[79]\;
  \not_strict_mode.app_rd_data_reg[7]\ <= \^not_strict_mode.app_rd_data_reg[7]\;
  \not_strict_mode.app_rd_data_reg[80]\ <= \^not_strict_mode.app_rd_data_reg[80]\;
  \not_strict_mode.app_rd_data_reg[81]\ <= \^not_strict_mode.app_rd_data_reg[81]\;
  \not_strict_mode.app_rd_data_reg[82]\ <= \^not_strict_mode.app_rd_data_reg[82]\;
  \not_strict_mode.app_rd_data_reg[83]\ <= \^not_strict_mode.app_rd_data_reg[83]\;
  \not_strict_mode.app_rd_data_reg[84]\ <= \^not_strict_mode.app_rd_data_reg[84]\;
  \not_strict_mode.app_rd_data_reg[85]\ <= \^not_strict_mode.app_rd_data_reg[85]\;
  \not_strict_mode.app_rd_data_reg[86]\ <= \^not_strict_mode.app_rd_data_reg[86]\;
  \not_strict_mode.app_rd_data_reg[87]\ <= \^not_strict_mode.app_rd_data_reg[87]\;
  \not_strict_mode.app_rd_data_reg[8]\ <= \^not_strict_mode.app_rd_data_reg[8]\;
  \not_strict_mode.app_rd_data_reg[9]\ <= \^not_strict_mode.app_rd_data_reg[9]\;
  \ref_dll_lock_w__0\(0) <= \^ref_dll_lock_w__0\(0);
A_rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_primitives,
      Q => A_rst_primitives,
      R => '0'
    );
\ddr_byte_lane_A.ddr_byte_lane_A\: entity work.mig_7series_0_mig_7series_v2_3_ddr_byte_lane_16
     port map (
      A_rst_primitives => A_rst_primitives,
      CLK => CLK,
      CLKB0_7 => CLKB0_7,
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      LD0_6 => LD0_6,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      Q(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_0\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_1\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_2\,
      \calib_sel_reg[1]_3\(5 downto 0) => \calib_sel_reg[1]_3\(5 downto 0),
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_4\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_5\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_155\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_171\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_234\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_156\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \^not_strict_mode.app_rd_data_reg[151]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \^not_strict_mode.app_rd_data_reg[143]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ => \^not_strict_mode.app_rd_data_reg[135]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \^not_strict_mode.app_rd_data_reg[215]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \^not_strict_mode.app_rd_data_reg[207]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ => \^not_strict_mode.app_rd_data_reg[199]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \^not_strict_mode.app_rd_data_reg[279]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \^not_strict_mode.app_rd_data_reg[271]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ => \^not_strict_mode.app_rd_data_reg[263]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \^not_strict_mode.app_rd_data_reg[343]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \^not_strict_mode.app_rd_data_reg[335]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ => \^not_strict_mode.app_rd_data_reg[327]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \^not_strict_mode.app_rd_data_reg[407]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \^not_strict_mode.app_rd_data_reg[399]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ => \^not_strict_mode.app_rd_data_reg[391]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \^not_strict_mode.app_rd_data_reg[471]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \^not_strict_mode.app_rd_data_reg[463]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ => \^not_strict_mode.app_rd_data_reg[455]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^not_strict_mode.app_rd_data_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \^not_strict_mode.app_rd_data_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^not_strict_mode.app_rd_data_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^not_strict_mode.app_rd_data_reg[86]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \^not_strict_mode.app_rd_data_reg[78]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \^not_strict_mode.app_rd_data_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^not_strict_mode.app_rd_data_reg[150]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \^not_strict_mode.app_rd_data_reg[142]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \^not_strict_mode.app_rd_data_reg[134]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^not_strict_mode.app_rd_data_reg[214]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \^not_strict_mode.app_rd_data_reg[206]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \^not_strict_mode.app_rd_data_reg[198]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^not_strict_mode.app_rd_data_reg[278]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \^not_strict_mode.app_rd_data_reg[270]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \^not_strict_mode.app_rd_data_reg[262]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^not_strict_mode.app_rd_data_reg[342]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \^not_strict_mode.app_rd_data_reg[334]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \^not_strict_mode.app_rd_data_reg[326]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^not_strict_mode.app_rd_data_reg[406]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \^not_strict_mode.app_rd_data_reg[398]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \^not_strict_mode.app_rd_data_reg[390]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^not_strict_mode.app_rd_data_reg[470]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \^not_strict_mode.app_rd_data_reg[462]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \^not_strict_mode.app_rd_data_reg[454]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^not_strict_mode.app_rd_data_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \^not_strict_mode.app_rd_data_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^not_strict_mode.app_rd_data_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^not_strict_mode.app_rd_data_reg[85]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \^not_strict_mode.app_rd_data_reg[77]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \^not_strict_mode.app_rd_data_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^not_strict_mode.app_rd_data_reg[149]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \^not_strict_mode.app_rd_data_reg[141]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \^not_strict_mode.app_rd_data_reg[133]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^not_strict_mode.app_rd_data_reg[213]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \^not_strict_mode.app_rd_data_reg[205]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \^not_strict_mode.app_rd_data_reg[197]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^not_strict_mode.app_rd_data_reg[277]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \^not_strict_mode.app_rd_data_reg[269]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \^not_strict_mode.app_rd_data_reg[261]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^not_strict_mode.app_rd_data_reg[341]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \^not_strict_mode.app_rd_data_reg[333]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \^not_strict_mode.app_rd_data_reg[325]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^not_strict_mode.app_rd_data_reg[405]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \^not_strict_mode.app_rd_data_reg[397]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \^not_strict_mode.app_rd_data_reg[389]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^not_strict_mode.app_rd_data_reg[469]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \^not_strict_mode.app_rd_data_reg[461]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \^not_strict_mode.app_rd_data_reg[453]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^not_strict_mode.app_rd_data_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \^not_strict_mode.app_rd_data_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^not_strict_mode.app_rd_data_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^not_strict_mode.app_rd_data_reg[84]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \^not_strict_mode.app_rd_data_reg[76]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \^not_strict_mode.app_rd_data_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^not_strict_mode.app_rd_data_reg[148]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \^not_strict_mode.app_rd_data_reg[140]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \^not_strict_mode.app_rd_data_reg[132]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^not_strict_mode.app_rd_data_reg[212]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \^not_strict_mode.app_rd_data_reg[204]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \^not_strict_mode.app_rd_data_reg[196]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^not_strict_mode.app_rd_data_reg[276]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \^not_strict_mode.app_rd_data_reg[268]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \^not_strict_mode.app_rd_data_reg[260]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^not_strict_mode.app_rd_data_reg[340]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \^not_strict_mode.app_rd_data_reg[332]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \^not_strict_mode.app_rd_data_reg[324]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^not_strict_mode.app_rd_data_reg[404]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \^not_strict_mode.app_rd_data_reg[396]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \^not_strict_mode.app_rd_data_reg[388]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^not_strict_mode.app_rd_data_reg[468]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \^not_strict_mode.app_rd_data_reg[460]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \^not_strict_mode.app_rd_data_reg[452]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^not_strict_mode.app_rd_data_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \^not_strict_mode.app_rd_data_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^not_strict_mode.app_rd_data_reg[75]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \^not_strict_mode.app_rd_data_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^not_strict_mode.app_rd_data_reg[139]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \^not_strict_mode.app_rd_data_reg[131]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^not_strict_mode.app_rd_data_reg[203]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \^not_strict_mode.app_rd_data_reg[195]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^not_strict_mode.app_rd_data_reg[267]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \^not_strict_mode.app_rd_data_reg[259]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^not_strict_mode.app_rd_data_reg[331]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \^not_strict_mode.app_rd_data_reg[323]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^not_strict_mode.app_rd_data_reg[395]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \^not_strict_mode.app_rd_data_reg[387]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^not_strict_mode.app_rd_data_reg[459]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \^not_strict_mode.app_rd_data_reg[451]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^not_strict_mode.app_rd_data_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \^not_strict_mode.app_rd_data_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^not_strict_mode.app_rd_data_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^not_strict_mode.app_rd_data_reg[74]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \^not_strict_mode.app_rd_data_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \^not_strict_mode.app_rd_data_reg[83]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^not_strict_mode.app_rd_data_reg[138]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \^not_strict_mode.app_rd_data_reg[130]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \^not_strict_mode.app_rd_data_reg[147]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^not_strict_mode.app_rd_data_reg[202]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \^not_strict_mode.app_rd_data_reg[194]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \^not_strict_mode.app_rd_data_reg[211]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^not_strict_mode.app_rd_data_reg[266]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \^not_strict_mode.app_rd_data_reg[258]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \^not_strict_mode.app_rd_data_reg[275]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^not_strict_mode.app_rd_data_reg[330]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \^not_strict_mode.app_rd_data_reg[322]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \^not_strict_mode.app_rd_data_reg[339]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^not_strict_mode.app_rd_data_reg[394]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \^not_strict_mode.app_rd_data_reg[386]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \^not_strict_mode.app_rd_data_reg[403]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^not_strict_mode.app_rd_data_reg[458]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \^not_strict_mode.app_rd_data_reg[450]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \^not_strict_mode.app_rd_data_reg[467]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^not_strict_mode.app_rd_data_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \^not_strict_mode.app_rd_data_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^not_strict_mode.app_rd_data_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^not_strict_mode.app_rd_data_reg[73]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \^not_strict_mode.app_rd_data_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \^not_strict_mode.app_rd_data_reg[82]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^not_strict_mode.app_rd_data_reg[137]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \^not_strict_mode.app_rd_data_reg[129]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \^not_strict_mode.app_rd_data_reg[146]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^not_strict_mode.app_rd_data_reg[201]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \^not_strict_mode.app_rd_data_reg[193]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \^not_strict_mode.app_rd_data_reg[210]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^not_strict_mode.app_rd_data_reg[265]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \^not_strict_mode.app_rd_data_reg[257]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \^not_strict_mode.app_rd_data_reg[274]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^not_strict_mode.app_rd_data_reg[329]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \^not_strict_mode.app_rd_data_reg[321]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \^not_strict_mode.app_rd_data_reg[338]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^not_strict_mode.app_rd_data_reg[393]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \^not_strict_mode.app_rd_data_reg[385]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \^not_strict_mode.app_rd_data_reg[402]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^not_strict_mode.app_rd_data_reg[457]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \^not_strict_mode.app_rd_data_reg[449]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \^not_strict_mode.app_rd_data_reg[466]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^not_strict_mode.app_rd_data_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \^not_strict_mode.app_rd_data_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \^not_strict_mode.app_rd_data_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^not_strict_mode.app_rd_data_reg[72]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \^not_strict_mode.app_rd_data_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2\ => \^not_strict_mode.app_rd_data_reg[81]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \^not_strict_mode.app_rd_data_reg[136]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^not_strict_mode.app_rd_data_reg[128]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \^not_strict_mode.app_rd_data_reg[145]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \^not_strict_mode.app_rd_data_reg[200]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^not_strict_mode.app_rd_data_reg[192]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \^not_strict_mode.app_rd_data_reg[209]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \^not_strict_mode.app_rd_data_reg[264]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^not_strict_mode.app_rd_data_reg[256]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \^not_strict_mode.app_rd_data_reg[273]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \^not_strict_mode.app_rd_data_reg[328]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^not_strict_mode.app_rd_data_reg[320]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \^not_strict_mode.app_rd_data_reg[337]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \^not_strict_mode.app_rd_data_reg[392]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^not_strict_mode.app_rd_data_reg[384]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \^not_strict_mode.app_rd_data_reg[401]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \^not_strict_mode.app_rd_data_reg[456]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^not_strict_mode.app_rd_data_reg[448]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \^not_strict_mode.app_rd_data_reg[465]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \^not_strict_mode.app_rd_data_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \^not_strict_mode.app_rd_data_reg[80]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \^not_strict_mode.app_rd_data_reg[144]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \^not_strict_mode.app_rd_data_reg[208]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \^not_strict_mode.app_rd_data_reg[272]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \^not_strict_mode.app_rd_data_reg[336]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \^not_strict_mode.app_rd_data_reg[400]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \^not_strict_mode.app_rd_data_reg[464]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \^not_strict_mode.app_rd_data_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \^not_strict_mode.app_rd_data_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ => \^not_strict_mode.app_rd_data_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \^not_strict_mode.app_rd_data_reg[87]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \^not_strict_mode.app_rd_data_reg[79]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ => \^not_strict_mode.app_rd_data_reg[71]\,
      \entry_cnt_reg[4]\(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2),
      freq_refclk => freq_refclk,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      if_empty_r(0) => if_empty_r(3),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_in(0) => mem_dqs_in(0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[152]\ => \not_strict_mode.app_rd_data_reg[152]\,
      \not_strict_mode.app_rd_data_reg[153]\ => \not_strict_mode.app_rd_data_reg[153]\,
      \not_strict_mode.app_rd_data_reg[154]\ => \not_strict_mode.app_rd_data_reg[154]\,
      \not_strict_mode.app_rd_data_reg[155]\ => \not_strict_mode.app_rd_data_reg[155]\,
      \not_strict_mode.app_rd_data_reg[156]\ => \not_strict_mode.app_rd_data_reg[156]\,
      \not_strict_mode.app_rd_data_reg[157]\ => \not_strict_mode.app_rd_data_reg[157]\,
      \not_strict_mode.app_rd_data_reg[158]\ => \not_strict_mode.app_rd_data_reg[158]\,
      \not_strict_mode.app_rd_data_reg[159]\ => \not_strict_mode.app_rd_data_reg[159]\,
      \not_strict_mode.app_rd_data_reg[216]\ => \not_strict_mode.app_rd_data_reg[216]\,
      \not_strict_mode.app_rd_data_reg[217]\ => \not_strict_mode.app_rd_data_reg[217]\,
      \not_strict_mode.app_rd_data_reg[218]\ => \not_strict_mode.app_rd_data_reg[218]\,
      \not_strict_mode.app_rd_data_reg[219]\ => \not_strict_mode.app_rd_data_reg[219]\,
      \not_strict_mode.app_rd_data_reg[220]\ => \not_strict_mode.app_rd_data_reg[220]\,
      \not_strict_mode.app_rd_data_reg[221]\ => \not_strict_mode.app_rd_data_reg[221]\,
      \not_strict_mode.app_rd_data_reg[222]\ => \not_strict_mode.app_rd_data_reg[222]\,
      \not_strict_mode.app_rd_data_reg[223]\ => \not_strict_mode.app_rd_data_reg[223]\,
      \not_strict_mode.app_rd_data_reg[24]\ => \not_strict_mode.app_rd_data_reg[24]\,
      \not_strict_mode.app_rd_data_reg[25]\ => \not_strict_mode.app_rd_data_reg[25]\,
      \not_strict_mode.app_rd_data_reg[26]\ => \not_strict_mode.app_rd_data_reg[26]\,
      \not_strict_mode.app_rd_data_reg[27]\ => \not_strict_mode.app_rd_data_reg[27]\,
      \not_strict_mode.app_rd_data_reg[280]\ => \not_strict_mode.app_rd_data_reg[280]\,
      \not_strict_mode.app_rd_data_reg[281]\ => \not_strict_mode.app_rd_data_reg[281]\,
      \not_strict_mode.app_rd_data_reg[282]\ => \not_strict_mode.app_rd_data_reg[282]\,
      \not_strict_mode.app_rd_data_reg[283]\ => \not_strict_mode.app_rd_data_reg[283]\,
      \not_strict_mode.app_rd_data_reg[284]\ => \not_strict_mode.app_rd_data_reg[284]\,
      \not_strict_mode.app_rd_data_reg[285]\ => \not_strict_mode.app_rd_data_reg[285]\,
      \not_strict_mode.app_rd_data_reg[286]\ => \not_strict_mode.app_rd_data_reg[286]\,
      \not_strict_mode.app_rd_data_reg[287]\ => \not_strict_mode.app_rd_data_reg[287]\,
      \not_strict_mode.app_rd_data_reg[28]\ => \not_strict_mode.app_rd_data_reg[28]\,
      \not_strict_mode.app_rd_data_reg[29]\ => \not_strict_mode.app_rd_data_reg[29]\,
      \not_strict_mode.app_rd_data_reg[30]\ => \not_strict_mode.app_rd_data_reg[30]\,
      \not_strict_mode.app_rd_data_reg[31]\ => \not_strict_mode.app_rd_data_reg[31]\,
      \not_strict_mode.app_rd_data_reg[344]\ => \not_strict_mode.app_rd_data_reg[344]\,
      \not_strict_mode.app_rd_data_reg[345]\ => \not_strict_mode.app_rd_data_reg[345]\,
      \not_strict_mode.app_rd_data_reg[346]\ => \not_strict_mode.app_rd_data_reg[346]\,
      \not_strict_mode.app_rd_data_reg[347]\ => \not_strict_mode.app_rd_data_reg[347]\,
      \not_strict_mode.app_rd_data_reg[348]\ => \not_strict_mode.app_rd_data_reg[348]\,
      \not_strict_mode.app_rd_data_reg[349]\ => \not_strict_mode.app_rd_data_reg[349]\,
      \not_strict_mode.app_rd_data_reg[350]\ => \not_strict_mode.app_rd_data_reg[350]\,
      \not_strict_mode.app_rd_data_reg[351]\ => \not_strict_mode.app_rd_data_reg[351]\,
      \not_strict_mode.app_rd_data_reg[408]\ => \not_strict_mode.app_rd_data_reg[408]\,
      \not_strict_mode.app_rd_data_reg[409]\ => \not_strict_mode.app_rd_data_reg[409]\,
      \not_strict_mode.app_rd_data_reg[410]\ => \not_strict_mode.app_rd_data_reg[410]\,
      \not_strict_mode.app_rd_data_reg[411]\ => \not_strict_mode.app_rd_data_reg[411]\,
      \not_strict_mode.app_rd_data_reg[412]\ => \not_strict_mode.app_rd_data_reg[412]\,
      \not_strict_mode.app_rd_data_reg[413]\ => \not_strict_mode.app_rd_data_reg[413]\,
      \not_strict_mode.app_rd_data_reg[414]\ => \not_strict_mode.app_rd_data_reg[414]\,
      \not_strict_mode.app_rd_data_reg[415]\ => \not_strict_mode.app_rd_data_reg[415]\,
      \not_strict_mode.app_rd_data_reg[472]\ => \not_strict_mode.app_rd_data_reg[472]\,
      \not_strict_mode.app_rd_data_reg[473]\ => \not_strict_mode.app_rd_data_reg[473]\,
      \not_strict_mode.app_rd_data_reg[474]\ => \not_strict_mode.app_rd_data_reg[474]\,
      \not_strict_mode.app_rd_data_reg[475]\ => \not_strict_mode.app_rd_data_reg[475]\,
      \not_strict_mode.app_rd_data_reg[476]\ => \not_strict_mode.app_rd_data_reg[476]\,
      \not_strict_mode.app_rd_data_reg[477]\ => \not_strict_mode.app_rd_data_reg[477]\,
      \not_strict_mode.app_rd_data_reg[478]\ => \not_strict_mode.app_rd_data_reg[478]\,
      \not_strict_mode.app_rd_data_reg[479]\(63 downto 56) => \not_strict_mode.app_rd_data_reg[479]\(255 downto 248),
      \not_strict_mode.app_rd_data_reg[479]\(55 downto 48) => \not_strict_mode.app_rd_data_reg[479]\(223 downto 216),
      \not_strict_mode.app_rd_data_reg[479]\(47 downto 40) => \not_strict_mode.app_rd_data_reg[479]\(191 downto 184),
      \not_strict_mode.app_rd_data_reg[479]\(39 downto 32) => \not_strict_mode.app_rd_data_reg[479]\(159 downto 152),
      \not_strict_mode.app_rd_data_reg[479]\(31 downto 24) => \not_strict_mode.app_rd_data_reg[479]\(127 downto 120),
      \not_strict_mode.app_rd_data_reg[479]\(23 downto 16) => \not_strict_mode.app_rd_data_reg[479]\(95 downto 88),
      \not_strict_mode.app_rd_data_reg[479]\(15 downto 8) => \not_strict_mode.app_rd_data_reg[479]\(63 downto 56),
      \not_strict_mode.app_rd_data_reg[479]\(7 downto 0) => \not_strict_mode.app_rd_data_reg[479]\(31 downto 24),
      \not_strict_mode.app_rd_data_reg[479]_0\ => \not_strict_mode.app_rd_data_reg[479]_0\,
      \not_strict_mode.app_rd_data_reg[88]\ => \not_strict_mode.app_rd_data_reg[88]\,
      \not_strict_mode.app_rd_data_reg[89]\ => \not_strict_mode.app_rd_data_reg[89]\,
      \not_strict_mode.app_rd_data_reg[90]\ => \not_strict_mode.app_rd_data_reg[90]\,
      \not_strict_mode.app_rd_data_reg[91]\ => \not_strict_mode.app_rd_data_reg[91]\,
      \not_strict_mode.app_rd_data_reg[92]\ => \not_strict_mode.app_rd_data_reg[92]\,
      \not_strict_mode.app_rd_data_reg[93]\ => \not_strict_mode.app_rd_data_reg[93]\,
      \not_strict_mode.app_rd_data_reg[94]\ => \not_strict_mode.app_rd_data_reg[94]\,
      \not_strict_mode.app_rd_data_reg[95]\ => \not_strict_mode.app_rd_data_reg[95]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0),
      out_dqs_3 => out_dqs_3,
      p_0_out => p_0_out,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(9 downto 8),
      phaser_ctl_bus(1) => phaser_ctl_bus(4),
      phaser_ctl_bus(0) => phaser_ctl_bus(0),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata_mask(31),
      phy_dout(70) => mux_wrdata_mask(27),
      phy_dout(69) => mux_wrdata_mask(23),
      phy_dout(68) => mux_wrdata_mask(19),
      phy_dout(67) => mux_wrdata_mask(15),
      phy_dout(66) => mux_wrdata_mask(11),
      phy_dout(65) => mux_wrdata_mask(7),
      phy_dout(64) => mux_wrdata_mask(3),
      phy_dout(63) => mux_wrdata(200),
      phy_dout(62) => mux_wrdata(168),
      phy_dout(61) => mux_wrdata(138),
      phy_dout(60) => mux_wrdata(114),
      phy_dout(59) => mux_wrdata(90),
      phy_dout(58) => mux_wrdata(66),
      phy_dout(57) => mux_wrdata(40),
      phy_dout(56) => \write_buffer.wr_buf_out_data_reg[351]\(12),
      phy_dout(55) => mux_wrdata(201),
      phy_dout(54) => mux_wrdata(169),
      phy_dout(53) => mux_wrdata(139),
      phy_dout(52) => mux_wrdata(115),
      phy_dout(51) => mux_wrdata(91),
      phy_dout(50) => \write_buffer.wr_buf_out_data_reg[351]\(22),
      phy_dout(49) => mux_wrdata(41),
      phy_dout(48) => mux_wrdata(12),
      phy_dout(47) => mux_wrdata(202),
      phy_dout(46) => mux_wrdata(170),
      phy_dout(45) => mux_wrdata(140),
      phy_dout(44) => \write_buffer.wr_buf_out_data_reg[351]\(38),
      phy_dout(43) => \write_buffer.wr_buf_out_data_reg[351]\(30),
      phy_dout(42) => mux_wrdata(67),
      phy_dout(41) => mux_wrdata(42),
      phy_dout(40) => mux_wrdata(13),
      phy_dout(39) => mux_wrdata(203),
      phy_dout(38) => mux_wrdata(171),
      phy_dout(37) => \write_buffer.wr_buf_out_data_reg[351]\(46),
      phy_dout(36) => mux_wrdata(116),
      phy_dout(35) => mux_wrdata(92),
      phy_dout(34) => mux_wrdata(68),
      phy_dout(33) => mux_wrdata(43),
      phy_dout(32) => \write_buffer.wr_buf_out_data_reg[351]\(13),
      phy_dout(31) => mux_wrdata(204),
      phy_dout(30) => mux_wrdata(172),
      phy_dout(29) => mux_wrdata(141),
      phy_dout(28) => mux_wrdata(117),
      phy_dout(27) => mux_wrdata(93),
      phy_dout(26) => mux_wrdata(69),
      phy_dout(25) => mux_wrdata(44),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[351]\(14),
      phy_dout(23) => mux_wrdata(205),
      phy_dout(22) => mux_wrdata(173),
      phy_dout(21) => mux_wrdata(142),
      phy_dout(20) => mux_wrdata(118),
      phy_dout(19) => mux_wrdata(94),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[351]\(23),
      phy_dout(17) => mux_wrdata(45),
      phy_dout(16) => mux_wrdata(14),
      phy_dout(15) => mux_wrdata(206),
      phy_dout(14) => mux_wrdata(174),
      phy_dout(13) => mux_wrdata(143),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[351]\(39),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[351]\(31),
      phy_dout(10) => mux_wrdata(70),
      phy_dout(9) => mux_wrdata(46),
      phy_dout(8) => mux_wrdata(15),
      phy_dout(7) => mux_wrdata(207),
      phy_dout(6) => mux_wrdata(175),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[351]\(47),
      phy_dout(4) => mux_wrdata(119),
      phy_dout(3) => mux_wrdata(95),
      phy_dout(2) => mux_wrdata(71),
      phy_dout(1) => mux_wrdata(47),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[351]\(15),
      phy_if_reset => phy_if_reset,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(0),
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      \po_counter_read_val_reg[8]\(8 downto 0) => A_po_counter_read_val(8 downto 0),
      \po_stg2_wrcal_cnt_reg[1]\ => \po_stg2_wrcal_cnt_reg[1]\,
      \po_stg2_wrcal_cnt_reg[1]_0\ => \po_stg2_wrcal_cnt_reg[1]_0\,
      \po_stg2_wrcal_cnt_reg[1]_1\ => \po_stg2_wrcal_cnt_reg[1]_1\,
      \po_stg2_wrcal_cnt_reg[1]_10\ => \po_stg2_wrcal_cnt_reg[1]_10\,
      \po_stg2_wrcal_cnt_reg[1]_11\ => \po_stg2_wrcal_cnt_reg[1]_11\,
      \po_stg2_wrcal_cnt_reg[1]_12\ => \po_stg2_wrcal_cnt_reg[1]_12\,
      \po_stg2_wrcal_cnt_reg[1]_13\ => \po_stg2_wrcal_cnt_reg[1]_13\,
      \po_stg2_wrcal_cnt_reg[1]_14\ => \po_stg2_wrcal_cnt_reg[1]_14\,
      \po_stg2_wrcal_cnt_reg[1]_15\ => \po_stg2_wrcal_cnt_reg[1]_15\,
      \po_stg2_wrcal_cnt_reg[1]_16\ => \po_stg2_wrcal_cnt_reg[1]_16\,
      \po_stg2_wrcal_cnt_reg[1]_17\ => \po_stg2_wrcal_cnt_reg[1]_17\,
      \po_stg2_wrcal_cnt_reg[1]_18\ => \po_stg2_wrcal_cnt_reg[1]_18\,
      \po_stg2_wrcal_cnt_reg[1]_19\ => \po_stg2_wrcal_cnt_reg[1]_19\,
      \po_stg2_wrcal_cnt_reg[1]_2\ => \po_stg2_wrcal_cnt_reg[1]_2\,
      \po_stg2_wrcal_cnt_reg[1]_20\ => \po_stg2_wrcal_cnt_reg[1]_20\,
      \po_stg2_wrcal_cnt_reg[1]_21\ => \po_stg2_wrcal_cnt_reg[1]_21\,
      \po_stg2_wrcal_cnt_reg[1]_22\ => \po_stg2_wrcal_cnt_reg[1]_22\,
      \po_stg2_wrcal_cnt_reg[1]_23\ => \po_stg2_wrcal_cnt_reg[1]_23\,
      \po_stg2_wrcal_cnt_reg[1]_24\ => \po_stg2_wrcal_cnt_reg[1]_24\,
      \po_stg2_wrcal_cnt_reg[1]_25\ => \po_stg2_wrcal_cnt_reg[1]_25\,
      \po_stg2_wrcal_cnt_reg[1]_26\ => \po_stg2_wrcal_cnt_reg[1]_26\,
      \po_stg2_wrcal_cnt_reg[1]_27\ => \po_stg2_wrcal_cnt_reg[1]_27\,
      \po_stg2_wrcal_cnt_reg[1]_28\ => \po_stg2_wrcal_cnt_reg[1]_28\,
      \po_stg2_wrcal_cnt_reg[1]_29\ => \po_stg2_wrcal_cnt_reg[1]_29\,
      \po_stg2_wrcal_cnt_reg[1]_3\ => \po_stg2_wrcal_cnt_reg[1]_3\,
      \po_stg2_wrcal_cnt_reg[1]_30\ => \po_stg2_wrcal_cnt_reg[1]_30\,
      \po_stg2_wrcal_cnt_reg[1]_31\ => \po_stg2_wrcal_cnt_reg[1]_31\,
      \po_stg2_wrcal_cnt_reg[1]_32\ => \po_stg2_wrcal_cnt_reg[1]_32\,
      \po_stg2_wrcal_cnt_reg[1]_33\ => \po_stg2_wrcal_cnt_reg[1]_33\,
      \po_stg2_wrcal_cnt_reg[1]_34\ => \po_stg2_wrcal_cnt_reg[1]_34\,
      \po_stg2_wrcal_cnt_reg[1]_35\ => \po_stg2_wrcal_cnt_reg[1]_35\,
      \po_stg2_wrcal_cnt_reg[1]_36\ => \po_stg2_wrcal_cnt_reg[1]_36\,
      \po_stg2_wrcal_cnt_reg[1]_37\ => \po_stg2_wrcal_cnt_reg[1]_37\,
      \po_stg2_wrcal_cnt_reg[1]_38\ => \po_stg2_wrcal_cnt_reg[1]_38\,
      \po_stg2_wrcal_cnt_reg[1]_39\ => \po_stg2_wrcal_cnt_reg[1]_39\,
      \po_stg2_wrcal_cnt_reg[1]_4\ => \po_stg2_wrcal_cnt_reg[1]_4\,
      \po_stg2_wrcal_cnt_reg[1]_40\ => \po_stg2_wrcal_cnt_reg[1]_40\,
      \po_stg2_wrcal_cnt_reg[1]_41\ => \po_stg2_wrcal_cnt_reg[1]_41\,
      \po_stg2_wrcal_cnt_reg[1]_42\ => \po_stg2_wrcal_cnt_reg[1]_42\,
      \po_stg2_wrcal_cnt_reg[1]_43\ => \po_stg2_wrcal_cnt_reg[1]_43\,
      \po_stg2_wrcal_cnt_reg[1]_44\ => \po_stg2_wrcal_cnt_reg[1]_44\,
      \po_stg2_wrcal_cnt_reg[1]_45\ => \po_stg2_wrcal_cnt_reg[1]_45\,
      \po_stg2_wrcal_cnt_reg[1]_46\ => \po_stg2_wrcal_cnt_reg[1]_46\,
      \po_stg2_wrcal_cnt_reg[1]_47\ => \po_stg2_wrcal_cnt_reg[1]_47\,
      \po_stg2_wrcal_cnt_reg[1]_48\ => \po_stg2_wrcal_cnt_reg[1]_48\,
      \po_stg2_wrcal_cnt_reg[1]_49\ => \po_stg2_wrcal_cnt_reg[1]_49\,
      \po_stg2_wrcal_cnt_reg[1]_5\ => \po_stg2_wrcal_cnt_reg[1]_5\,
      \po_stg2_wrcal_cnt_reg[1]_50\ => \po_stg2_wrcal_cnt_reg[1]_50\,
      \po_stg2_wrcal_cnt_reg[1]_51\ => \po_stg2_wrcal_cnt_reg[1]_51\,
      \po_stg2_wrcal_cnt_reg[1]_52\ => \po_stg2_wrcal_cnt_reg[1]_52\,
      \po_stg2_wrcal_cnt_reg[1]_53\ => \po_stg2_wrcal_cnt_reg[1]_53\,
      \po_stg2_wrcal_cnt_reg[1]_54\ => \po_stg2_wrcal_cnt_reg[1]_54\,
      \po_stg2_wrcal_cnt_reg[1]_55\ => \po_stg2_wrcal_cnt_reg[1]_55\,
      \po_stg2_wrcal_cnt_reg[1]_56\ => \po_stg2_wrcal_cnt_reg[1]_56\,
      \po_stg2_wrcal_cnt_reg[1]_57\ => \po_stg2_wrcal_cnt_reg[1]_57\,
      \po_stg2_wrcal_cnt_reg[1]_58\ => \po_stg2_wrcal_cnt_reg[1]_58\,
      \po_stg2_wrcal_cnt_reg[1]_59\ => \po_stg2_wrcal_cnt_reg[1]_59\,
      \po_stg2_wrcal_cnt_reg[1]_6\ => \po_stg2_wrcal_cnt_reg[1]_6\,
      \po_stg2_wrcal_cnt_reg[1]_60\ => \po_stg2_wrcal_cnt_reg[1]_60\,
      \po_stg2_wrcal_cnt_reg[1]_61\ => \po_stg2_wrcal_cnt_reg[1]_61\,
      \po_stg2_wrcal_cnt_reg[1]_62\ => \po_stg2_wrcal_cnt_reg[1]_62\,
      \po_stg2_wrcal_cnt_reg[1]_7\ => \po_stg2_wrcal_cnt_reg[1]_7\,
      \po_stg2_wrcal_cnt_reg[1]_8\ => \po_stg2_wrcal_cnt_reg[1]_8\,
      \po_stg2_wrcal_cnt_reg[1]_9\ => \po_stg2_wrcal_cnt_reg[1]_9\,
      \po_stg2_wrcal_cnt_reg[2]\(2 downto 0) => \po_stg2_wrcal_cnt_reg[2]\(2 downto 0),
      \rd_ptr_reg[0]\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_236\,
      \rd_ptr_reg[0]_0\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_237\,
      \rd_ptr_reg[0]_1\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_238\,
      \rd_ptr_reg[0]_2\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_239\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg,
      ts_dqs_3 => ts_dqs_3,
      \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[473]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[473]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[474]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[474]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[475]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[475]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[477]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[477]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[478]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[478]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[479]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[479]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[571]\(27) => \write_buffer.wr_buf_out_data_reg[571]\(111),
      \write_buffer.wr_buf_out_data_reg[571]\(26) => \write_buffer.wr_buf_out_data_reg[571]\(107),
      \write_buffer.wr_buf_out_data_reg[571]\(25) => \write_buffer.wr_buf_out_data_reg[571]\(103),
      \write_buffer.wr_buf_out_data_reg[571]\(24) => \write_buffer.wr_buf_out_data_reg[571]\(99),
      \write_buffer.wr_buf_out_data_reg[571]\(23) => \write_buffer.wr_buf_out_data_reg[571]\(95),
      \write_buffer.wr_buf_out_data_reg[571]\(22) => \write_buffer.wr_buf_out_data_reg[571]\(91),
      \write_buffer.wr_buf_out_data_reg[571]\(21) => \write_buffer.wr_buf_out_data_reg[571]\(87),
      \write_buffer.wr_buf_out_data_reg[571]\(20) => \write_buffer.wr_buf_out_data_reg[571]\(83),
      \write_buffer.wr_buf_out_data_reg[571]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[571]\(79 downto 78),
      \write_buffer.wr_buf_out_data_reg[571]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[571]\(71 downto 70),
      \write_buffer.wr_buf_out_data_reg[571]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[571]\(63 downto 60),
      \write_buffer.wr_buf_out_data_reg[571]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[571]\(47 downto 46),
      \write_buffer.wr_buf_out_data_reg[571]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[571]\(39 downto 38),
      \write_buffer.wr_buf_out_data_reg[571]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[571]\(31 downto 28),
      \write_buffer.wr_buf_out_data_reg[571]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[571]\(15 downto 12)
    );
\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0_17\
     port map (
      A_rst_primitives => A_rst_primitives,
      A_rst_primitives_reg(5 downto 0) => D_pi_counter_read_val(5 downto 0),
      A_rst_primitives_reg_0(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      A_rst_primitives_reg_1 => \ddr_byte_lane_C.ddr_byte_lane_C_n_22\,
      A_rst_primitives_reg_2 => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      A_rst_primitives_reg_3 => \ddr_byte_lane_D.ddr_byte_lane_D_n_22\,
      A_rst_primitives_reg_4(8 downto 0) => A_po_counter_read_val(8 downto 0),
      A_rst_primitives_reg_5(8 downto 0) => D_po_counter_read_val(8 downto 0),
      A_rst_primitives_reg_6(8 downto 0) => C_po_counter_read_val(8 downto 0),
      B_rclk => B_rclk,
      CLK => CLK,
      CLKB0_8 => CLKB0_8,
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      D(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_205\,
      D(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_206\,
      D(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_207\,
      D(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_208\,
      D(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_209\,
      D(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_210\,
      LD0_7 => LD0_7,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\(0),
      byte_rd_en_v_0 => byte_rd_en_v_0,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \calib_sel_reg[0]\ => \calib_sel_reg[0]\,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_6\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_7\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_8\,
      \calib_sel_reg[1]_2\(5 downto 0) => \calib_sel_reg[1]_9\(5 downto 0),
      \calib_sel_reg[1]_3\ => \calib_sel_reg[1]_10\,
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_11\,
      \calib_sel_reg[1]_5\(1 downto 0) => \calib_sel_reg[1]_20\(1 downto 0),
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_0,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_237\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_171\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_234\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_236\,
      \entry_cnt_reg[4]\(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(4 downto 2),
      freq_refclk => freq_refclk,
      idelay_inc => idelay_inc,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      if_empty_r(0) => if_empty_r_2(3),
      if_empty_r_0(0) => if_empty_r_5(3),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      mem_dq_in(7 downto 0) => mem_dq_in(15 downto 8),
      mem_dq_out(8 downto 0) => mem_dq_out(17 downto 9),
      mem_dq_ts(8 downto 0) => mem_dq_ts(17 downto 9),
      mem_dqs_in(0) => mem_dqs_in(1),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_0\,
      \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\(3),
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]_0\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[144]\ => \^not_strict_mode.app_rd_data_reg[144]\,
      \not_strict_mode.app_rd_data_reg[145]\ => \^not_strict_mode.app_rd_data_reg[145]\,
      \not_strict_mode.app_rd_data_reg[146]\ => \^not_strict_mode.app_rd_data_reg[146]\,
      \not_strict_mode.app_rd_data_reg[147]\ => \^not_strict_mode.app_rd_data_reg[147]\,
      \not_strict_mode.app_rd_data_reg[148]\ => \^not_strict_mode.app_rd_data_reg[148]\,
      \not_strict_mode.app_rd_data_reg[149]\ => \^not_strict_mode.app_rd_data_reg[149]\,
      \not_strict_mode.app_rd_data_reg[150]\ => \^not_strict_mode.app_rd_data_reg[150]\,
      \not_strict_mode.app_rd_data_reg[151]\ => \^not_strict_mode.app_rd_data_reg[151]\,
      \not_strict_mode.app_rd_data_reg[16]\ => \^not_strict_mode.app_rd_data_reg[16]\,
      \not_strict_mode.app_rd_data_reg[17]\ => \^not_strict_mode.app_rd_data_reg[17]\,
      \not_strict_mode.app_rd_data_reg[18]\ => \^not_strict_mode.app_rd_data_reg[18]\,
      \not_strict_mode.app_rd_data_reg[19]\ => \^not_strict_mode.app_rd_data_reg[19]\,
      \not_strict_mode.app_rd_data_reg[208]\ => \^not_strict_mode.app_rd_data_reg[208]\,
      \not_strict_mode.app_rd_data_reg[209]\ => \^not_strict_mode.app_rd_data_reg[209]\,
      \not_strict_mode.app_rd_data_reg[20]\ => \^not_strict_mode.app_rd_data_reg[20]\,
      \not_strict_mode.app_rd_data_reg[210]\ => \^not_strict_mode.app_rd_data_reg[210]\,
      \not_strict_mode.app_rd_data_reg[211]\ => \^not_strict_mode.app_rd_data_reg[211]\,
      \not_strict_mode.app_rd_data_reg[212]\ => \^not_strict_mode.app_rd_data_reg[212]\,
      \not_strict_mode.app_rd_data_reg[213]\ => \^not_strict_mode.app_rd_data_reg[213]\,
      \not_strict_mode.app_rd_data_reg[214]\ => \^not_strict_mode.app_rd_data_reg[214]\,
      \not_strict_mode.app_rd_data_reg[215]\ => \^not_strict_mode.app_rd_data_reg[215]\,
      \not_strict_mode.app_rd_data_reg[21]\ => \^not_strict_mode.app_rd_data_reg[21]\,
      \not_strict_mode.app_rd_data_reg[22]\ => \^not_strict_mode.app_rd_data_reg[22]\,
      \not_strict_mode.app_rd_data_reg[23]\ => \^not_strict_mode.app_rd_data_reg[23]\,
      \not_strict_mode.app_rd_data_reg[272]\ => \^not_strict_mode.app_rd_data_reg[272]\,
      \not_strict_mode.app_rd_data_reg[273]\ => \^not_strict_mode.app_rd_data_reg[273]\,
      \not_strict_mode.app_rd_data_reg[274]\ => \^not_strict_mode.app_rd_data_reg[274]\,
      \not_strict_mode.app_rd_data_reg[275]\ => \^not_strict_mode.app_rd_data_reg[275]\,
      \not_strict_mode.app_rd_data_reg[276]\ => \^not_strict_mode.app_rd_data_reg[276]\,
      \not_strict_mode.app_rd_data_reg[277]\ => \^not_strict_mode.app_rd_data_reg[277]\,
      \not_strict_mode.app_rd_data_reg[278]\ => \^not_strict_mode.app_rd_data_reg[278]\,
      \not_strict_mode.app_rd_data_reg[279]\ => \^not_strict_mode.app_rd_data_reg[279]\,
      \not_strict_mode.app_rd_data_reg[336]\ => \^not_strict_mode.app_rd_data_reg[336]\,
      \not_strict_mode.app_rd_data_reg[337]\ => \^not_strict_mode.app_rd_data_reg[337]\,
      \not_strict_mode.app_rd_data_reg[338]\ => \^not_strict_mode.app_rd_data_reg[338]\,
      \not_strict_mode.app_rd_data_reg[339]\ => \^not_strict_mode.app_rd_data_reg[339]\,
      \not_strict_mode.app_rd_data_reg[340]\ => \^not_strict_mode.app_rd_data_reg[340]\,
      \not_strict_mode.app_rd_data_reg[341]\ => \^not_strict_mode.app_rd_data_reg[341]\,
      \not_strict_mode.app_rd_data_reg[342]\ => \^not_strict_mode.app_rd_data_reg[342]\,
      \not_strict_mode.app_rd_data_reg[343]\ => \^not_strict_mode.app_rd_data_reg[343]\,
      \not_strict_mode.app_rd_data_reg[400]\ => \^not_strict_mode.app_rd_data_reg[400]\,
      \not_strict_mode.app_rd_data_reg[401]\ => \^not_strict_mode.app_rd_data_reg[401]\,
      \not_strict_mode.app_rd_data_reg[402]\ => \^not_strict_mode.app_rd_data_reg[402]\,
      \not_strict_mode.app_rd_data_reg[403]\ => \^not_strict_mode.app_rd_data_reg[403]\,
      \not_strict_mode.app_rd_data_reg[404]\ => \^not_strict_mode.app_rd_data_reg[404]\,
      \not_strict_mode.app_rd_data_reg[405]\ => \^not_strict_mode.app_rd_data_reg[405]\,
      \not_strict_mode.app_rd_data_reg[406]\ => \^not_strict_mode.app_rd_data_reg[406]\,
      \not_strict_mode.app_rd_data_reg[407]\ => \^not_strict_mode.app_rd_data_reg[407]\,
      \not_strict_mode.app_rd_data_reg[464]\ => \^not_strict_mode.app_rd_data_reg[464]\,
      \not_strict_mode.app_rd_data_reg[465]\ => \^not_strict_mode.app_rd_data_reg[465]\,
      \not_strict_mode.app_rd_data_reg[466]\ => \^not_strict_mode.app_rd_data_reg[466]\,
      \not_strict_mode.app_rd_data_reg[467]\ => \^not_strict_mode.app_rd_data_reg[467]\,
      \not_strict_mode.app_rd_data_reg[468]\ => \^not_strict_mode.app_rd_data_reg[468]\,
      \not_strict_mode.app_rd_data_reg[469]\ => \^not_strict_mode.app_rd_data_reg[469]\,
      \not_strict_mode.app_rd_data_reg[470]\ => \^not_strict_mode.app_rd_data_reg[470]\,
      \not_strict_mode.app_rd_data_reg[471]\(63 downto 56) => \not_strict_mode.app_rd_data_reg[479]\(247 downto 240),
      \not_strict_mode.app_rd_data_reg[471]\(55 downto 48) => \not_strict_mode.app_rd_data_reg[479]\(215 downto 208),
      \not_strict_mode.app_rd_data_reg[471]\(47 downto 40) => \not_strict_mode.app_rd_data_reg[479]\(183 downto 176),
      \not_strict_mode.app_rd_data_reg[471]\(39 downto 32) => \not_strict_mode.app_rd_data_reg[479]\(151 downto 144),
      \not_strict_mode.app_rd_data_reg[471]\(31 downto 24) => \not_strict_mode.app_rd_data_reg[479]\(119 downto 112),
      \not_strict_mode.app_rd_data_reg[471]\(23 downto 16) => \not_strict_mode.app_rd_data_reg[479]\(87 downto 80),
      \not_strict_mode.app_rd_data_reg[471]\(15 downto 8) => \not_strict_mode.app_rd_data_reg[479]\(55 downto 48),
      \not_strict_mode.app_rd_data_reg[471]\(7 downto 0) => \not_strict_mode.app_rd_data_reg[479]\(23 downto 16),
      \not_strict_mode.app_rd_data_reg[471]_0\ => \^not_strict_mode.app_rd_data_reg[471]\,
      \not_strict_mode.app_rd_data_reg[80]\ => \^not_strict_mode.app_rd_data_reg[80]\,
      \not_strict_mode.app_rd_data_reg[81]\ => \^not_strict_mode.app_rd_data_reg[81]\,
      \not_strict_mode.app_rd_data_reg[82]\ => \^not_strict_mode.app_rd_data_reg[82]\,
      \not_strict_mode.app_rd_data_reg[83]\ => \^not_strict_mode.app_rd_data_reg[83]\,
      \not_strict_mode.app_rd_data_reg[84]\ => \^not_strict_mode.app_rd_data_reg[84]\,
      \not_strict_mode.app_rd_data_reg[85]\ => \^not_strict_mode.app_rd_data_reg[85]\,
      \not_strict_mode.app_rd_data_reg[86]\ => \^not_strict_mode.app_rd_data_reg[86]\,
      \not_strict_mode.app_rd_data_reg[87]\ => \^not_strict_mode.app_rd_data_reg[87]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0),
      out_dqs_2 => out_dqs_2,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(11 downto 10),
      phaser_ctl_bus(1) => phaser_ctl_bus(5),
      phaser_ctl_bus(0) => phaser_ctl_bus(1),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata(192),
      phy_dout(70) => mux_wrdata(160),
      phy_dout(69) => mux_wrdata(132),
      phy_dout(68) => mux_wrdata(108),
      phy_dout(67) => mux_wrdata(84),
      phy_dout(66) => mux_wrdata(60),
      phy_dout(65) => mux_wrdata(32),
      phy_dout(64) => \write_buffer.wr_buf_out_data_reg[351]\(8),
      phy_dout(63) => mux_wrdata(193),
      phy_dout(62) => mux_wrdata(161),
      phy_dout(61) => mux_wrdata(133),
      phy_dout(60) => mux_wrdata(109),
      phy_dout(59) => mux_wrdata(85),
      phy_dout(58) => \write_buffer.wr_buf_out_data_reg[351]\(20),
      phy_dout(57) => mux_wrdata(33),
      phy_dout(56) => mux_wrdata(8),
      phy_dout(55) => mux_wrdata(194),
      phy_dout(54) => mux_wrdata(162),
      phy_dout(53) => mux_wrdata(134),
      phy_dout(52) => \write_buffer.wr_buf_out_data_reg[351]\(36),
      phy_dout(51) => \write_buffer.wr_buf_out_data_reg[351]\(28),
      phy_dout(50) => mux_wrdata(61),
      phy_dout(49) => mux_wrdata(34),
      phy_dout(48) => mux_wrdata(9),
      phy_dout(47) => mux_wrdata(195),
      phy_dout(46) => mux_wrdata(163),
      phy_dout(45) => \write_buffer.wr_buf_out_data_reg[351]\(44),
      phy_dout(44) => mux_wrdata(110),
      phy_dout(43) => mux_wrdata(86),
      phy_dout(42) => mux_wrdata(62),
      phy_dout(41) => mux_wrdata(35),
      phy_dout(40) => \write_buffer.wr_buf_out_data_reg[351]\(9),
      phy_dout(39) => mux_wrdata_mask(30),
      phy_dout(38) => mux_wrdata_mask(26),
      phy_dout(37) => mux_wrdata_mask(22),
      phy_dout(36) => mux_wrdata_mask(18),
      phy_dout(35) => mux_wrdata_mask(14),
      phy_dout(34) => mux_wrdata_mask(10),
      phy_dout(33) => mux_wrdata_mask(6),
      phy_dout(32) => mux_wrdata_mask(2),
      phy_dout(31) => mux_wrdata(196),
      phy_dout(30) => mux_wrdata(164),
      phy_dout(29) => mux_wrdata(135),
      phy_dout(28) => mux_wrdata(111),
      phy_dout(27) => mux_wrdata(87),
      phy_dout(26) => mux_wrdata(63),
      phy_dout(25) => mux_wrdata(36),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[351]\(10),
      phy_dout(23) => mux_wrdata(197),
      phy_dout(22) => mux_wrdata(165),
      phy_dout(21) => mux_wrdata(136),
      phy_dout(20) => mux_wrdata(112),
      phy_dout(19) => mux_wrdata(88),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[351]\(21),
      phy_dout(17) => mux_wrdata(37),
      phy_dout(16) => mux_wrdata(10),
      phy_dout(15) => mux_wrdata(198),
      phy_dout(14) => mux_wrdata(166),
      phy_dout(13) => mux_wrdata(137),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[351]\(37),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[351]\(29),
      phy_dout(10) => mux_wrdata(64),
      phy_dout(9) => mux_wrdata(38),
      phy_dout(8) => mux_wrdata(11),
      phy_dout(7) => mux_wrdata(199),
      phy_dout(6) => mux_wrdata(167),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[351]\(45),
      phy_dout(4) => mux_wrdata(113),
      phy_dout(3) => mux_wrdata(89),
      phy_dout(2) => mux_wrdata(65),
      phy_dout(1) => mux_wrdata(39),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[351]\(11),
      phy_if_reset => phy_if_reset,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(1),
      pi_phase_locked_all_r1_reg => pi_phase_locked_all_r1_reg,
      \po_counter_read_val_reg[8]\(8) => \ddr_byte_lane_B.ddr_byte_lane_B_n_212\,
      \po_counter_read_val_reg[8]\(7) => \ddr_byte_lane_B.ddr_byte_lane_B_n_213\,
      \po_counter_read_val_reg[8]\(6) => \ddr_byte_lane_B.ddr_byte_lane_B_n_214\,
      \po_counter_read_val_reg[8]\(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_215\,
      \po_counter_read_val_reg[8]\(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_216\,
      \po_counter_read_val_reg[8]\(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_217\,
      \po_counter_read_val_reg[8]\(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_218\,
      \po_counter_read_val_reg[8]\(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_219\,
      \po_counter_read_val_reg[8]\(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_220\,
      \rd_ptr_reg[1]\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_155\,
      \rd_ptr_reg[1]_0\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_156\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_0,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_0,
      ts_dqs_2 => ts_dqs_2,
      \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[465]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[465]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[466]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[466]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[467]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[467]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[469]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[469]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[470]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[470]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[471]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[471]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[570]\(27) => \write_buffer.wr_buf_out_data_reg[571]\(110),
      \write_buffer.wr_buf_out_data_reg[570]\(26) => \write_buffer.wr_buf_out_data_reg[571]\(106),
      \write_buffer.wr_buf_out_data_reg[570]\(25) => \write_buffer.wr_buf_out_data_reg[571]\(102),
      \write_buffer.wr_buf_out_data_reg[570]\(24) => \write_buffer.wr_buf_out_data_reg[571]\(98),
      \write_buffer.wr_buf_out_data_reg[570]\(23) => \write_buffer.wr_buf_out_data_reg[571]\(94),
      \write_buffer.wr_buf_out_data_reg[570]\(22) => \write_buffer.wr_buf_out_data_reg[571]\(90),
      \write_buffer.wr_buf_out_data_reg[570]\(21) => \write_buffer.wr_buf_out_data_reg[571]\(86),
      \write_buffer.wr_buf_out_data_reg[570]\(20) => \write_buffer.wr_buf_out_data_reg[571]\(82),
      \write_buffer.wr_buf_out_data_reg[570]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[571]\(77 downto 76),
      \write_buffer.wr_buf_out_data_reg[570]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[571]\(69 downto 68),
      \write_buffer.wr_buf_out_data_reg[570]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[571]\(59 downto 56),
      \write_buffer.wr_buf_out_data_reg[570]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[571]\(45 downto 44),
      \write_buffer.wr_buf_out_data_reg[570]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[571]\(37 downto 36),
      \write_buffer.wr_buf_out_data_reg[570]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[571]\(27 downto 24),
      \write_buffer.wr_buf_out_data_reg[570]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[571]\(11 downto 8)
    );
\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1_18\
     port map (
      A_rst_primitives => A_rst_primitives,
      CLK => CLK,
      CLKB0_9 => CLKB0_9,
      LD0_8 => LD0_8,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4\(3),
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_12\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_13\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_14\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_15\,
      \calib_sel_reg[1]_3\(5 downto 0) => \calib_sel_reg[1]_16\(5 downto 0),
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_17\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_18\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_1,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_238\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \^not_strict_mode.app_rd_data_reg[151]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ => \^not_strict_mode.app_rd_data_reg[135]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \^not_strict_mode.app_rd_data_reg[215]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ => \^not_strict_mode.app_rd_data_reg[199]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \^not_strict_mode.app_rd_data_reg[279]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ => \^not_strict_mode.app_rd_data_reg[263]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \^not_strict_mode.app_rd_data_reg[343]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ => \^not_strict_mode.app_rd_data_reg[327]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \^not_strict_mode.app_rd_data_reg[407]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ => \^not_strict_mode.app_rd_data_reg[391]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \^not_strict_mode.app_rd_data_reg[471]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ => \^not_strict_mode.app_rd_data_reg[455]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \^not_strict_mode.app_rd_data_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^not_strict_mode.app_rd_data_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \^not_strict_mode.app_rd_data_reg[86]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \^not_strict_mode.app_rd_data_reg[70]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \^not_strict_mode.app_rd_data_reg[150]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \^not_strict_mode.app_rd_data_reg[134]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \^not_strict_mode.app_rd_data_reg[214]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \^not_strict_mode.app_rd_data_reg[198]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \^not_strict_mode.app_rd_data_reg[278]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \^not_strict_mode.app_rd_data_reg[262]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \^not_strict_mode.app_rd_data_reg[342]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \^not_strict_mode.app_rd_data_reg[326]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \^not_strict_mode.app_rd_data_reg[406]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \^not_strict_mode.app_rd_data_reg[390]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \^not_strict_mode.app_rd_data_reg[470]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \^not_strict_mode.app_rd_data_reg[454]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \^not_strict_mode.app_rd_data_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^not_strict_mode.app_rd_data_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \^not_strict_mode.app_rd_data_reg[85]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \^not_strict_mode.app_rd_data_reg[69]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \^not_strict_mode.app_rd_data_reg[149]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \^not_strict_mode.app_rd_data_reg[133]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \^not_strict_mode.app_rd_data_reg[213]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \^not_strict_mode.app_rd_data_reg[197]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \^not_strict_mode.app_rd_data_reg[277]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \^not_strict_mode.app_rd_data_reg[261]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \^not_strict_mode.app_rd_data_reg[341]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \^not_strict_mode.app_rd_data_reg[325]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \^not_strict_mode.app_rd_data_reg[405]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \^not_strict_mode.app_rd_data_reg[389]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \^not_strict_mode.app_rd_data_reg[469]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \^not_strict_mode.app_rd_data_reg[453]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \^not_strict_mode.app_rd_data_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^not_strict_mode.app_rd_data_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \^not_strict_mode.app_rd_data_reg[84]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \^not_strict_mode.app_rd_data_reg[68]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \^not_strict_mode.app_rd_data_reg[148]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \^not_strict_mode.app_rd_data_reg[132]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \^not_strict_mode.app_rd_data_reg[212]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \^not_strict_mode.app_rd_data_reg[196]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \^not_strict_mode.app_rd_data_reg[276]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \^not_strict_mode.app_rd_data_reg[260]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \^not_strict_mode.app_rd_data_reg[340]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \^not_strict_mode.app_rd_data_reg[324]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \^not_strict_mode.app_rd_data_reg[404]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \^not_strict_mode.app_rd_data_reg[388]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \^not_strict_mode.app_rd_data_reg[468]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \^not_strict_mode.app_rd_data_reg[452]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \^not_strict_mode.app_rd_data_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \^not_strict_mode.app_rd_data_reg[67]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \^not_strict_mode.app_rd_data_reg[131]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \^not_strict_mode.app_rd_data_reg[195]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \^not_strict_mode.app_rd_data_reg[259]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \^not_strict_mode.app_rd_data_reg[323]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \^not_strict_mode.app_rd_data_reg[387]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \^not_strict_mode.app_rd_data_reg[451]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \^not_strict_mode.app_rd_data_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^not_strict_mode.app_rd_data_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \^not_strict_mode.app_rd_data_reg[66]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \^not_strict_mode.app_rd_data_reg[83]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \^not_strict_mode.app_rd_data_reg[130]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \^not_strict_mode.app_rd_data_reg[147]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \^not_strict_mode.app_rd_data_reg[194]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \^not_strict_mode.app_rd_data_reg[211]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \^not_strict_mode.app_rd_data_reg[258]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \^not_strict_mode.app_rd_data_reg[275]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \^not_strict_mode.app_rd_data_reg[322]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \^not_strict_mode.app_rd_data_reg[339]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \^not_strict_mode.app_rd_data_reg[386]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \^not_strict_mode.app_rd_data_reg[403]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \^not_strict_mode.app_rd_data_reg[450]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \^not_strict_mode.app_rd_data_reg[467]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \^not_strict_mode.app_rd_data_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^not_strict_mode.app_rd_data_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \^not_strict_mode.app_rd_data_reg[65]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \^not_strict_mode.app_rd_data_reg[82]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \^not_strict_mode.app_rd_data_reg[129]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \^not_strict_mode.app_rd_data_reg[146]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \^not_strict_mode.app_rd_data_reg[193]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \^not_strict_mode.app_rd_data_reg[210]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \^not_strict_mode.app_rd_data_reg[257]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \^not_strict_mode.app_rd_data_reg[274]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \^not_strict_mode.app_rd_data_reg[321]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \^not_strict_mode.app_rd_data_reg[338]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \^not_strict_mode.app_rd_data_reg[385]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \^not_strict_mode.app_rd_data_reg[402]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \^not_strict_mode.app_rd_data_reg[449]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \^not_strict_mode.app_rd_data_reg[466]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^not_strict_mode.app_rd_data_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \^not_strict_mode.app_rd_data_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^not_strict_mode.app_rd_data_reg[64]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \^not_strict_mode.app_rd_data_reg[81]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^not_strict_mode.app_rd_data_reg[128]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1\ => \^not_strict_mode.app_rd_data_reg[145]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^not_strict_mode.app_rd_data_reg[192]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1\ => \^not_strict_mode.app_rd_data_reg[209]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^not_strict_mode.app_rd_data_reg[256]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1\ => \^not_strict_mode.app_rd_data_reg[273]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^not_strict_mode.app_rd_data_reg[320]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1\ => \^not_strict_mode.app_rd_data_reg[337]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^not_strict_mode.app_rd_data_reg[384]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1\ => \^not_strict_mode.app_rd_data_reg[401]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^not_strict_mode.app_rd_data_reg[448]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1\ => \^not_strict_mode.app_rd_data_reg[465]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \^not_strict_mode.app_rd_data_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \^not_strict_mode.app_rd_data_reg[80]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \^not_strict_mode.app_rd_data_reg[144]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \^not_strict_mode.app_rd_data_reg[208]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \^not_strict_mode.app_rd_data_reg[272]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \^not_strict_mode.app_rd_data_reg[336]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \^not_strict_mode.app_rd_data_reg[400]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \^not_strict_mode.app_rd_data_reg[464]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \^not_strict_mode.app_rd_data_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ => \^not_strict_mode.app_rd_data_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \^not_strict_mode.app_rd_data_reg[87]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ => \^not_strict_mode.app_rd_data_reg[71]\,
      \entry_cnt_reg[4]\(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(4 downto 2),
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      if_empty_r(0) => if_empty_r_5(3),
      if_empty_r_0(0) => if_empty_r_2(3),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      mem_dq_in(7 downto 0) => mem_dq_in(23 downto 16),
      mem_dq_out(8 downto 0) => mem_dq_out(26 downto 18),
      mem_dq_ts(8 downto 0) => mem_dq_ts(26 downto 18),
      mem_dqs_in(0) => mem_dqs_in(2),
      mem_refclk => mem_refclk,
      \my_empty_reg[0]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1\(0),
      \my_empty_reg[1]\ => \my_empty_reg[1]_1\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]_1\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[10]\ => \^not_strict_mode.app_rd_data_reg[10]\,
      \not_strict_mode.app_rd_data_reg[11]\ => \^not_strict_mode.app_rd_data_reg[11]\,
      \not_strict_mode.app_rd_data_reg[12]\ => \^not_strict_mode.app_rd_data_reg[12]\,
      \not_strict_mode.app_rd_data_reg[136]\ => \^not_strict_mode.app_rd_data_reg[136]\,
      \not_strict_mode.app_rd_data_reg[137]\ => \^not_strict_mode.app_rd_data_reg[137]\,
      \not_strict_mode.app_rd_data_reg[138]\ => \^not_strict_mode.app_rd_data_reg[138]\,
      \not_strict_mode.app_rd_data_reg[139]\ => \^not_strict_mode.app_rd_data_reg[139]\,
      \not_strict_mode.app_rd_data_reg[13]\ => \^not_strict_mode.app_rd_data_reg[13]\,
      \not_strict_mode.app_rd_data_reg[140]\ => \^not_strict_mode.app_rd_data_reg[140]\,
      \not_strict_mode.app_rd_data_reg[141]\ => \^not_strict_mode.app_rd_data_reg[141]\,
      \not_strict_mode.app_rd_data_reg[142]\ => \^not_strict_mode.app_rd_data_reg[142]\,
      \not_strict_mode.app_rd_data_reg[143]\ => \^not_strict_mode.app_rd_data_reg[143]\,
      \not_strict_mode.app_rd_data_reg[14]\ => \^not_strict_mode.app_rd_data_reg[14]\,
      \not_strict_mode.app_rd_data_reg[15]\ => \^not_strict_mode.app_rd_data_reg[15]\,
      \not_strict_mode.app_rd_data_reg[200]\ => \^not_strict_mode.app_rd_data_reg[200]\,
      \not_strict_mode.app_rd_data_reg[201]\ => \^not_strict_mode.app_rd_data_reg[201]\,
      \not_strict_mode.app_rd_data_reg[202]\ => \^not_strict_mode.app_rd_data_reg[202]\,
      \not_strict_mode.app_rd_data_reg[203]\ => \^not_strict_mode.app_rd_data_reg[203]\,
      \not_strict_mode.app_rd_data_reg[204]\ => \^not_strict_mode.app_rd_data_reg[204]\,
      \not_strict_mode.app_rd_data_reg[205]\ => \^not_strict_mode.app_rd_data_reg[205]\,
      \not_strict_mode.app_rd_data_reg[206]\ => \^not_strict_mode.app_rd_data_reg[206]\,
      \not_strict_mode.app_rd_data_reg[207]\ => \^not_strict_mode.app_rd_data_reg[207]\,
      \not_strict_mode.app_rd_data_reg[264]\ => \^not_strict_mode.app_rd_data_reg[264]\,
      \not_strict_mode.app_rd_data_reg[265]\ => \^not_strict_mode.app_rd_data_reg[265]\,
      \not_strict_mode.app_rd_data_reg[266]\ => \^not_strict_mode.app_rd_data_reg[266]\,
      \not_strict_mode.app_rd_data_reg[267]\ => \^not_strict_mode.app_rd_data_reg[267]\,
      \not_strict_mode.app_rd_data_reg[268]\ => \^not_strict_mode.app_rd_data_reg[268]\,
      \not_strict_mode.app_rd_data_reg[269]\ => \^not_strict_mode.app_rd_data_reg[269]\,
      \not_strict_mode.app_rd_data_reg[270]\ => \^not_strict_mode.app_rd_data_reg[270]\,
      \not_strict_mode.app_rd_data_reg[271]\ => \^not_strict_mode.app_rd_data_reg[271]\,
      \not_strict_mode.app_rd_data_reg[328]\ => \^not_strict_mode.app_rd_data_reg[328]\,
      \not_strict_mode.app_rd_data_reg[329]\ => \^not_strict_mode.app_rd_data_reg[329]\,
      \not_strict_mode.app_rd_data_reg[330]\ => \^not_strict_mode.app_rd_data_reg[330]\,
      \not_strict_mode.app_rd_data_reg[331]\ => \^not_strict_mode.app_rd_data_reg[331]\,
      \not_strict_mode.app_rd_data_reg[332]\ => \^not_strict_mode.app_rd_data_reg[332]\,
      \not_strict_mode.app_rd_data_reg[333]\ => \^not_strict_mode.app_rd_data_reg[333]\,
      \not_strict_mode.app_rd_data_reg[334]\ => \^not_strict_mode.app_rd_data_reg[334]\,
      \not_strict_mode.app_rd_data_reg[335]\ => \^not_strict_mode.app_rd_data_reg[335]\,
      \not_strict_mode.app_rd_data_reg[392]\ => \^not_strict_mode.app_rd_data_reg[392]\,
      \not_strict_mode.app_rd_data_reg[393]\ => \^not_strict_mode.app_rd_data_reg[393]\,
      \not_strict_mode.app_rd_data_reg[394]\ => \^not_strict_mode.app_rd_data_reg[394]\,
      \not_strict_mode.app_rd_data_reg[395]\ => \^not_strict_mode.app_rd_data_reg[395]\,
      \not_strict_mode.app_rd_data_reg[396]\ => \^not_strict_mode.app_rd_data_reg[396]\,
      \not_strict_mode.app_rd_data_reg[397]\ => \^not_strict_mode.app_rd_data_reg[397]\,
      \not_strict_mode.app_rd_data_reg[398]\ => \^not_strict_mode.app_rd_data_reg[398]\,
      \not_strict_mode.app_rd_data_reg[399]\ => \^not_strict_mode.app_rd_data_reg[399]\,
      \not_strict_mode.app_rd_data_reg[456]\ => \^not_strict_mode.app_rd_data_reg[456]\,
      \not_strict_mode.app_rd_data_reg[457]\ => \^not_strict_mode.app_rd_data_reg[457]\,
      \not_strict_mode.app_rd_data_reg[458]\ => \^not_strict_mode.app_rd_data_reg[458]\,
      \not_strict_mode.app_rd_data_reg[459]\ => \^not_strict_mode.app_rd_data_reg[459]\,
      \not_strict_mode.app_rd_data_reg[460]\ => \^not_strict_mode.app_rd_data_reg[460]\,
      \not_strict_mode.app_rd_data_reg[461]\ => \^not_strict_mode.app_rd_data_reg[461]\,
      \not_strict_mode.app_rd_data_reg[462]\ => \^not_strict_mode.app_rd_data_reg[462]\,
      \not_strict_mode.app_rd_data_reg[463]\ => \^not_strict_mode.app_rd_data_reg[463]\,
      \not_strict_mode.app_rd_data_reg[463]_0\(63 downto 56) => \not_strict_mode.app_rd_data_reg[479]\(239 downto 232),
      \not_strict_mode.app_rd_data_reg[463]_0\(55 downto 48) => \not_strict_mode.app_rd_data_reg[479]\(207 downto 200),
      \not_strict_mode.app_rd_data_reg[463]_0\(47 downto 40) => \not_strict_mode.app_rd_data_reg[479]\(175 downto 168),
      \not_strict_mode.app_rd_data_reg[463]_0\(39 downto 32) => \not_strict_mode.app_rd_data_reg[479]\(143 downto 136),
      \not_strict_mode.app_rd_data_reg[463]_0\(31 downto 24) => \not_strict_mode.app_rd_data_reg[479]\(111 downto 104),
      \not_strict_mode.app_rd_data_reg[463]_0\(23 downto 16) => \not_strict_mode.app_rd_data_reg[479]\(79 downto 72),
      \not_strict_mode.app_rd_data_reg[463]_0\(15 downto 8) => \not_strict_mode.app_rd_data_reg[479]\(47 downto 40),
      \not_strict_mode.app_rd_data_reg[463]_0\(7 downto 0) => \not_strict_mode.app_rd_data_reg[479]\(15 downto 8),
      \not_strict_mode.app_rd_data_reg[72]\ => \^not_strict_mode.app_rd_data_reg[72]\,
      \not_strict_mode.app_rd_data_reg[73]\ => \^not_strict_mode.app_rd_data_reg[73]\,
      \not_strict_mode.app_rd_data_reg[74]\ => \^not_strict_mode.app_rd_data_reg[74]\,
      \not_strict_mode.app_rd_data_reg[75]\ => \^not_strict_mode.app_rd_data_reg[75]\,
      \not_strict_mode.app_rd_data_reg[76]\ => \^not_strict_mode.app_rd_data_reg[76]\,
      \not_strict_mode.app_rd_data_reg[77]\ => \^not_strict_mode.app_rd_data_reg[77]\,
      \not_strict_mode.app_rd_data_reg[78]\ => \^not_strict_mode.app_rd_data_reg[78]\,
      \not_strict_mode.app_rd_data_reg[79]\ => \^not_strict_mode.app_rd_data_reg[79]\,
      \not_strict_mode.app_rd_data_reg[8]\ => \^not_strict_mode.app_rd_data_reg[8]\,
      \not_strict_mode.app_rd_data_reg[9]\ => \^not_strict_mode.app_rd_data_reg[9]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0),
      out_dqs_1 => out_dqs_1,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(13 downto 12),
      phaser_ctl_bus(1) => phaser_ctl_bus(6),
      phaser_ctl_bus(0) => phaser_ctl_bus(2),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata_mask(29),
      phy_dout(70) => mux_wrdata_mask(25),
      phy_dout(69) => mux_wrdata_mask(21),
      phy_dout(68) => mux_wrdata_mask(17),
      phy_dout(67) => mux_wrdata_mask(13),
      phy_dout(66) => mux_wrdata_mask(9),
      phy_dout(65) => mux_wrdata_mask(5),
      phy_dout(64) => mux_wrdata_mask(1),
      phy_dout(63) => mux_wrdata(184),
      phy_dout(62) => mux_wrdata(152),
      phy_dout(61) => mux_wrdata(126),
      phy_dout(60) => mux_wrdata(102),
      phy_dout(59) => mux_wrdata(78),
      phy_dout(58) => mux_wrdata(54),
      phy_dout(57) => mux_wrdata(24),
      phy_dout(56) => \write_buffer.wr_buf_out_data_reg[351]\(4),
      phy_dout(55) => mux_wrdata(185),
      phy_dout(54) => mux_wrdata(153),
      phy_dout(53) => mux_wrdata(127),
      phy_dout(52) => mux_wrdata(103),
      phy_dout(51) => mux_wrdata(79),
      phy_dout(50) => \write_buffer.wr_buf_out_data_reg[351]\(18),
      phy_dout(49) => mux_wrdata(25),
      phy_dout(48) => mux_wrdata(4),
      phy_dout(47) => mux_wrdata(186),
      phy_dout(46) => mux_wrdata(154),
      phy_dout(45) => mux_wrdata(128),
      phy_dout(44) => \write_buffer.wr_buf_out_data_reg[351]\(34),
      phy_dout(43) => \write_buffer.wr_buf_out_data_reg[351]\(26),
      phy_dout(42) => mux_wrdata(55),
      phy_dout(41) => mux_wrdata(26),
      phy_dout(40) => mux_wrdata(5),
      phy_dout(39) => mux_wrdata(187),
      phy_dout(38) => mux_wrdata(155),
      phy_dout(37) => \write_buffer.wr_buf_out_data_reg[351]\(42),
      phy_dout(36) => mux_wrdata(104),
      phy_dout(35) => mux_wrdata(80),
      phy_dout(34) => mux_wrdata(56),
      phy_dout(33) => mux_wrdata(27),
      phy_dout(32) => \write_buffer.wr_buf_out_data_reg[351]\(5),
      phy_dout(31) => mux_wrdata(188),
      phy_dout(30) => mux_wrdata(156),
      phy_dout(29) => mux_wrdata(129),
      phy_dout(28) => mux_wrdata(105),
      phy_dout(27) => mux_wrdata(81),
      phy_dout(26) => mux_wrdata(57),
      phy_dout(25) => mux_wrdata(28),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[351]\(6),
      phy_dout(23) => mux_wrdata(189),
      phy_dout(22) => mux_wrdata(157),
      phy_dout(21) => mux_wrdata(130),
      phy_dout(20) => mux_wrdata(106),
      phy_dout(19) => mux_wrdata(82),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[351]\(19),
      phy_dout(17) => mux_wrdata(29),
      phy_dout(16) => mux_wrdata(6),
      phy_dout(15) => mux_wrdata(190),
      phy_dout(14) => mux_wrdata(158),
      phy_dout(13) => mux_wrdata(131),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[351]\(35),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[351]\(27),
      phy_dout(10) => mux_wrdata(58),
      phy_dout(9) => mux_wrdata(30),
      phy_dout(8) => mux_wrdata(7),
      phy_dout(7) => mux_wrdata(191),
      phy_dout(6) => mux_wrdata(159),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[351]\(43),
      phy_dout(4) => mux_wrdata(107),
      phy_dout(3) => mux_wrdata(83),
      phy_dout(2) => mux_wrdata(59),
      phy_dout(1) => mux_wrdata(31),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[351]\(7),
      phy_if_reset => phy_if_reset,
      \pi_counter_read_val_reg[5]\(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(2),
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_C.ddr_byte_lane_C_n_22\,
      \po_counter_read_val_reg[8]\(8 downto 0) => C_po_counter_read_val(8 downto 0),
      rd_active_r_reg => rd_active_r_reg_0,
      \rd_mux_sel_r_reg[1]\(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      \rd_ptr_timing_reg[0]\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_234\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_1,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_1,
      ts_dqs_1 => ts_dqs_1,
      \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[457]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[457]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[458]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[458]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[459]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[459]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[461]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[461]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[462]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[462]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[463]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[463]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[569]\(27) => \write_buffer.wr_buf_out_data_reg[571]\(109),
      \write_buffer.wr_buf_out_data_reg[569]\(26) => \write_buffer.wr_buf_out_data_reg[571]\(105),
      \write_buffer.wr_buf_out_data_reg[569]\(25) => \write_buffer.wr_buf_out_data_reg[571]\(101),
      \write_buffer.wr_buf_out_data_reg[569]\(24) => \write_buffer.wr_buf_out_data_reg[571]\(97),
      \write_buffer.wr_buf_out_data_reg[569]\(23) => \write_buffer.wr_buf_out_data_reg[571]\(93),
      \write_buffer.wr_buf_out_data_reg[569]\(22) => \write_buffer.wr_buf_out_data_reg[571]\(89),
      \write_buffer.wr_buf_out_data_reg[569]\(21) => \write_buffer.wr_buf_out_data_reg[571]\(85),
      \write_buffer.wr_buf_out_data_reg[569]\(20) => \write_buffer.wr_buf_out_data_reg[571]\(81),
      \write_buffer.wr_buf_out_data_reg[569]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[571]\(75 downto 74),
      \write_buffer.wr_buf_out_data_reg[569]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[571]\(67 downto 66),
      \write_buffer.wr_buf_out_data_reg[569]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[571]\(55 downto 52),
      \write_buffer.wr_buf_out_data_reg[569]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[571]\(43 downto 42),
      \write_buffer.wr_buf_out_data_reg[569]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[571]\(35 downto 34),
      \write_buffer.wr_buf_out_data_reg[569]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[571]\(23 downto 20),
      \write_buffer.wr_buf_out_data_reg[569]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[571]\(7 downto 4)
    );
\ddr_byte_lane_D.ddr_byte_lane_D\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized2\
     port map (
      A_byte_rd_en => A_byte_rd_en,
      A_rst_primitives => A_rst_primitives,
      B_byte_rd_en => B_byte_rd_en,
      CLK => CLK,
      CLKB0_10 => CLKB0_10,
      C_byte_rd_en => C_byte_rd_en,
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      LD0_9 => LD0_9,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      Q(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      byte_rd_en_v_1 => byte_rd_en_v_1,
      \calib_sel_reg[0]\ => \calib_sel_reg[0]_0\,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_19\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_2,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_byte_lane_A.ddr_byte_lane_A_n_239\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_byte_lane_C.ddr_byte_lane_C_n_234\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_156\,
      dqs_wl_po_stg2_c_incdec_reg => dqs_wl_po_stg2_c_incdec_reg,
      \entry_cnt_reg[4]\(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_6\(4 downto 2),
      freq_refclk => freq_refclk,
      idelay_ce_r2_reg => idelay_ce_r2_reg,
      idelay_inc => idelay_inc,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      if_empty_r(0) => if_empty_r(3),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      mem_dq_in(7 downto 0) => mem_dq_in(31 downto 24),
      mem_dq_out(8 downto 0) => mem_dq_out(35 downto 27),
      mem_dq_ts(8 downto 0) => mem_dq_ts(35 downto 27),
      mem_dqs_in(0) => mem_dqs_in(3),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_2\,
      \my_empty_reg[3]\ => \my_empty_reg[3]\,
      \my_empty_reg[3]_0\ => \my_empty_reg[3]_0\,
      \my_empty_reg[3]_1\ => \my_empty_reg[3]_1\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]_2\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[0]\ => \^not_strict_mode.app_rd_data_reg[0]\,
      \not_strict_mode.app_rd_data_reg[128]\ => \^not_strict_mode.app_rd_data_reg[128]\,
      \not_strict_mode.app_rd_data_reg[129]\ => \^not_strict_mode.app_rd_data_reg[129]\,
      \not_strict_mode.app_rd_data_reg[130]\ => \^not_strict_mode.app_rd_data_reg[130]\,
      \not_strict_mode.app_rd_data_reg[131]\ => \^not_strict_mode.app_rd_data_reg[131]\,
      \not_strict_mode.app_rd_data_reg[132]\ => \^not_strict_mode.app_rd_data_reg[132]\,
      \not_strict_mode.app_rd_data_reg[133]\ => \^not_strict_mode.app_rd_data_reg[133]\,
      \not_strict_mode.app_rd_data_reg[134]\ => \^not_strict_mode.app_rd_data_reg[134]\,
      \not_strict_mode.app_rd_data_reg[135]\ => \^not_strict_mode.app_rd_data_reg[135]\,
      \not_strict_mode.app_rd_data_reg[192]\ => \^not_strict_mode.app_rd_data_reg[192]\,
      \not_strict_mode.app_rd_data_reg[193]\ => \^not_strict_mode.app_rd_data_reg[193]\,
      \not_strict_mode.app_rd_data_reg[194]\ => \^not_strict_mode.app_rd_data_reg[194]\,
      \not_strict_mode.app_rd_data_reg[195]\ => \^not_strict_mode.app_rd_data_reg[195]\,
      \not_strict_mode.app_rd_data_reg[196]\ => \^not_strict_mode.app_rd_data_reg[196]\,
      \not_strict_mode.app_rd_data_reg[197]\ => \^not_strict_mode.app_rd_data_reg[197]\,
      \not_strict_mode.app_rd_data_reg[198]\ => \^not_strict_mode.app_rd_data_reg[198]\,
      \not_strict_mode.app_rd_data_reg[199]\ => \^not_strict_mode.app_rd_data_reg[199]\,
      \not_strict_mode.app_rd_data_reg[1]\ => \^not_strict_mode.app_rd_data_reg[1]\,
      \not_strict_mode.app_rd_data_reg[256]\ => \^not_strict_mode.app_rd_data_reg[256]\,
      \not_strict_mode.app_rd_data_reg[257]\ => \^not_strict_mode.app_rd_data_reg[257]\,
      \not_strict_mode.app_rd_data_reg[258]\ => \^not_strict_mode.app_rd_data_reg[258]\,
      \not_strict_mode.app_rd_data_reg[259]\ => \^not_strict_mode.app_rd_data_reg[259]\,
      \not_strict_mode.app_rd_data_reg[260]\ => \^not_strict_mode.app_rd_data_reg[260]\,
      \not_strict_mode.app_rd_data_reg[261]\ => \^not_strict_mode.app_rd_data_reg[261]\,
      \not_strict_mode.app_rd_data_reg[262]\ => \^not_strict_mode.app_rd_data_reg[262]\,
      \not_strict_mode.app_rd_data_reg[263]\ => \^not_strict_mode.app_rd_data_reg[263]\,
      \not_strict_mode.app_rd_data_reg[2]\ => \^not_strict_mode.app_rd_data_reg[2]\,
      \not_strict_mode.app_rd_data_reg[320]\ => \^not_strict_mode.app_rd_data_reg[320]\,
      \not_strict_mode.app_rd_data_reg[321]\ => \^not_strict_mode.app_rd_data_reg[321]\,
      \not_strict_mode.app_rd_data_reg[322]\ => \^not_strict_mode.app_rd_data_reg[322]\,
      \not_strict_mode.app_rd_data_reg[323]\ => \^not_strict_mode.app_rd_data_reg[323]\,
      \not_strict_mode.app_rd_data_reg[324]\ => \^not_strict_mode.app_rd_data_reg[324]\,
      \not_strict_mode.app_rd_data_reg[325]\ => \^not_strict_mode.app_rd_data_reg[325]\,
      \not_strict_mode.app_rd_data_reg[326]\ => \^not_strict_mode.app_rd_data_reg[326]\,
      \not_strict_mode.app_rd_data_reg[327]\ => \^not_strict_mode.app_rd_data_reg[327]\,
      \not_strict_mode.app_rd_data_reg[384]\ => \^not_strict_mode.app_rd_data_reg[384]\,
      \not_strict_mode.app_rd_data_reg[385]\ => \^not_strict_mode.app_rd_data_reg[385]\,
      \not_strict_mode.app_rd_data_reg[386]\ => \^not_strict_mode.app_rd_data_reg[386]\,
      \not_strict_mode.app_rd_data_reg[387]\ => \^not_strict_mode.app_rd_data_reg[387]\,
      \not_strict_mode.app_rd_data_reg[388]\ => \^not_strict_mode.app_rd_data_reg[388]\,
      \not_strict_mode.app_rd_data_reg[389]\ => \^not_strict_mode.app_rd_data_reg[389]\,
      \not_strict_mode.app_rd_data_reg[390]\ => \^not_strict_mode.app_rd_data_reg[390]\,
      \not_strict_mode.app_rd_data_reg[391]\ => \^not_strict_mode.app_rd_data_reg[391]\,
      \not_strict_mode.app_rd_data_reg[3]\ => \^not_strict_mode.app_rd_data_reg[3]\,
      \not_strict_mode.app_rd_data_reg[448]\ => \^not_strict_mode.app_rd_data_reg[448]\,
      \not_strict_mode.app_rd_data_reg[449]\ => \^not_strict_mode.app_rd_data_reg[449]\,
      \not_strict_mode.app_rd_data_reg[450]\ => \^not_strict_mode.app_rd_data_reg[450]\,
      \not_strict_mode.app_rd_data_reg[451]\ => \^not_strict_mode.app_rd_data_reg[451]\,
      \not_strict_mode.app_rd_data_reg[452]\ => \^not_strict_mode.app_rd_data_reg[452]\,
      \not_strict_mode.app_rd_data_reg[453]\ => \^not_strict_mode.app_rd_data_reg[453]\,
      \not_strict_mode.app_rd_data_reg[454]\ => \^not_strict_mode.app_rd_data_reg[454]\,
      \not_strict_mode.app_rd_data_reg[455]\(63 downto 56) => \not_strict_mode.app_rd_data_reg[479]\(231 downto 224),
      \not_strict_mode.app_rd_data_reg[455]\(55 downto 48) => \not_strict_mode.app_rd_data_reg[479]\(199 downto 192),
      \not_strict_mode.app_rd_data_reg[455]\(47 downto 40) => \not_strict_mode.app_rd_data_reg[479]\(167 downto 160),
      \not_strict_mode.app_rd_data_reg[455]\(39 downto 32) => \not_strict_mode.app_rd_data_reg[479]\(135 downto 128),
      \not_strict_mode.app_rd_data_reg[455]\(31 downto 24) => \not_strict_mode.app_rd_data_reg[479]\(103 downto 96),
      \not_strict_mode.app_rd_data_reg[455]\(23 downto 16) => \not_strict_mode.app_rd_data_reg[479]\(71 downto 64),
      \not_strict_mode.app_rd_data_reg[455]\(15 downto 8) => \not_strict_mode.app_rd_data_reg[479]\(39 downto 32),
      \not_strict_mode.app_rd_data_reg[455]\(7 downto 0) => \not_strict_mode.app_rd_data_reg[479]\(7 downto 0),
      \not_strict_mode.app_rd_data_reg[455]_0\ => \^not_strict_mode.app_rd_data_reg[455]\,
      \not_strict_mode.app_rd_data_reg[4]\ => \^not_strict_mode.app_rd_data_reg[4]\,
      \not_strict_mode.app_rd_data_reg[5]\ => \^not_strict_mode.app_rd_data_reg[5]\,
      \not_strict_mode.app_rd_data_reg[64]\ => \^not_strict_mode.app_rd_data_reg[64]\,
      \not_strict_mode.app_rd_data_reg[65]\ => \^not_strict_mode.app_rd_data_reg[65]\,
      \not_strict_mode.app_rd_data_reg[66]\ => \^not_strict_mode.app_rd_data_reg[66]\,
      \not_strict_mode.app_rd_data_reg[67]\ => \^not_strict_mode.app_rd_data_reg[67]\,
      \not_strict_mode.app_rd_data_reg[68]\ => \^not_strict_mode.app_rd_data_reg[68]\,
      \not_strict_mode.app_rd_data_reg[69]\ => \^not_strict_mode.app_rd_data_reg[69]\,
      \not_strict_mode.app_rd_data_reg[6]\ => \^not_strict_mode.app_rd_data_reg[6]\,
      \not_strict_mode.app_rd_data_reg[70]\ => \^not_strict_mode.app_rd_data_reg[70]\,
      \not_strict_mode.app_rd_data_reg[71]\ => \^not_strict_mode.app_rd_data_reg[71]\,
      \not_strict_mode.app_rd_data_reg[7]\ => \^not_strict_mode.app_rd_data_reg[7]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0),
      out_dqs_0 => out_dqs_0,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(15 downto 14),
      phaser_ctl_bus(1) => phaser_ctl_bus(7),
      phaser_ctl_bus(0) => phaser_ctl_bus(3),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata_mask(28),
      phy_dout(70) => mux_wrdata_mask(24),
      phy_dout(69) => mux_wrdata_mask(20),
      phy_dout(68) => mux_wrdata_mask(16),
      phy_dout(67) => mux_wrdata_mask(12),
      phy_dout(66) => mux_wrdata_mask(8),
      phy_dout(65) => mux_wrdata_mask(4),
      phy_dout(64) => mux_wrdata_mask(0),
      phy_dout(63) => mux_wrdata(176),
      phy_dout(62) => mux_wrdata(144),
      phy_dout(61) => mux_wrdata(120),
      phy_dout(60) => mux_wrdata(96),
      phy_dout(59) => mux_wrdata(72),
      phy_dout(58) => mux_wrdata(48),
      phy_dout(57) => mux_wrdata(16),
      phy_dout(56) => \write_buffer.wr_buf_out_data_reg[351]\(0),
      phy_dout(55) => mux_wrdata(177),
      phy_dout(54) => mux_wrdata(145),
      phy_dout(53) => mux_wrdata(121),
      phy_dout(52) => mux_wrdata(97),
      phy_dout(51) => mux_wrdata(73),
      phy_dout(50) => \write_buffer.wr_buf_out_data_reg[351]\(16),
      phy_dout(49) => mux_wrdata(17),
      phy_dout(48) => mux_wrdata(0),
      phy_dout(47) => mux_wrdata(178),
      phy_dout(46) => mux_wrdata(146),
      phy_dout(45) => mux_wrdata(122),
      phy_dout(44) => \write_buffer.wr_buf_out_data_reg[351]\(32),
      phy_dout(43) => \write_buffer.wr_buf_out_data_reg[351]\(24),
      phy_dout(42) => mux_wrdata(49),
      phy_dout(41) => mux_wrdata(18),
      phy_dout(40) => mux_wrdata(1),
      phy_dout(39) => mux_wrdata(179),
      phy_dout(38) => mux_wrdata(147),
      phy_dout(37) => \write_buffer.wr_buf_out_data_reg[351]\(40),
      phy_dout(36) => mux_wrdata(98),
      phy_dout(35) => mux_wrdata(74),
      phy_dout(34) => mux_wrdata(50),
      phy_dout(33) => mux_wrdata(19),
      phy_dout(32) => \write_buffer.wr_buf_out_data_reg[351]\(1),
      phy_dout(31) => mux_wrdata(180),
      phy_dout(30) => mux_wrdata(148),
      phy_dout(29) => mux_wrdata(123),
      phy_dout(28) => mux_wrdata(99),
      phy_dout(27) => mux_wrdata(75),
      phy_dout(26) => mux_wrdata(51),
      phy_dout(25) => mux_wrdata(20),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[351]\(2),
      phy_dout(23) => mux_wrdata(181),
      phy_dout(22) => mux_wrdata(149),
      phy_dout(21) => mux_wrdata(124),
      phy_dout(20) => mux_wrdata(100),
      phy_dout(19) => mux_wrdata(76),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[351]\(17),
      phy_dout(17) => mux_wrdata(21),
      phy_dout(16) => mux_wrdata(2),
      phy_dout(15) => mux_wrdata(182),
      phy_dout(14) => mux_wrdata(150),
      phy_dout(13) => mux_wrdata(125),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[351]\(33),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[351]\(25),
      phy_dout(10) => mux_wrdata(52),
      phy_dout(9) => mux_wrdata(22),
      phy_dout(8) => mux_wrdata(3),
      phy_dout(7) => mux_wrdata(183),
      phy_dout(6) => mux_wrdata(151),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[351]\(41),
      phy_dout(4) => mux_wrdata(101),
      phy_dout(3) => mux_wrdata(77),
      phy_dout(2) => mux_wrdata(53),
      phy_dout(1) => mux_wrdata(23),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[351]\(3),
      phy_if_reset => phy_if_reset,
      \pi_counter_read_val_reg[5]\(5 downto 0) => D_pi_counter_read_val(5 downto 0),
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(3),
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_D.ddr_byte_lane_D_n_22\,
      \pi_rst_stg1_cal_reg[0]\ => \pi_rst_stg1_cal_reg[0]\,
      pi_stg2_load_reg => pi_stg2_load_reg,
      \pi_stg2_reg_l_reg[5]\(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0),
      \po_counter_read_val_reg[8]\(8 downto 0) => D_po_counter_read_val(8 downto 0),
      rd_active_r_reg => rd_active_r_reg,
      \rd_ptr_reg[1]\ => \ddr_byte_lane_D.ddr_byte_lane_D_n_171\,
      \rd_ptr_timing_reg[0]\ => \rd_ptr_timing_reg[0]\,
      \rd_ptr_timing_reg[0]_0\ => \rd_ptr_timing_reg[0]_0\,
      \rd_ptr_timing_reg[0]_1\ => \rd_ptr_timing_reg[0]_1\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      rst_r4 => rst_r4,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_2,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_2,
      ts_dqs_0 => ts_dqs_0,
      \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[449]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[449]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[450]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[450]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[451]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[451]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[453]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[453]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[454]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[454]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[455]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[455]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[568]\(27) => \write_buffer.wr_buf_out_data_reg[571]\(108),
      \write_buffer.wr_buf_out_data_reg[568]\(26) => \write_buffer.wr_buf_out_data_reg[571]\(104),
      \write_buffer.wr_buf_out_data_reg[568]\(25) => \write_buffer.wr_buf_out_data_reg[571]\(100),
      \write_buffer.wr_buf_out_data_reg[568]\(24) => \write_buffer.wr_buf_out_data_reg[571]\(96),
      \write_buffer.wr_buf_out_data_reg[568]\(23) => \write_buffer.wr_buf_out_data_reg[571]\(92),
      \write_buffer.wr_buf_out_data_reg[568]\(22) => \write_buffer.wr_buf_out_data_reg[571]\(88),
      \write_buffer.wr_buf_out_data_reg[568]\(21) => \write_buffer.wr_buf_out_data_reg[571]\(84),
      \write_buffer.wr_buf_out_data_reg[568]\(20) => \write_buffer.wr_buf_out_data_reg[571]\(80),
      \write_buffer.wr_buf_out_data_reg[568]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[571]\(73 downto 72),
      \write_buffer.wr_buf_out_data_reg[568]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[571]\(65 downto 64),
      \write_buffer.wr_buf_out_data_reg[568]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[571]\(51 downto 48),
      \write_buffer.wr_buf_out_data_reg[568]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[571]\(41 downto 40),
      \write_buffer.wr_buf_out_data_reg[568]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[571]\(33 downto 32),
      \write_buffer.wr_buf_out_data_reg[568]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[571]\(19 downto 16),
      \write_buffer.wr_buf_out_data_reg[568]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[571]\(3 downto 0)
    );
mcGo_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_out_reg_n_0,
      Q => \mcGo_w__0\(0),
      R => '0'
    );
ofs_rdy_r_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(2),
      I1 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(4),
      I2 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3\(3),
      I3 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(2),
      I4 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(4),
      I5 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0\(3),
      O => ofs_rdy_r_reg_0
    );
ofs_rdy_r_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_6\(2),
      I1 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_6\(4),
      I2 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_6\(3),
      I3 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(2),
      I4 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4),
      I5 => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(3),
      O => ofs_rdy_r_reg
    );
phaser_ref_i: unisim.vcomponents.PHASER_REF
    generic map(
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0'
    )
        port map (
      CLKIN => freq_refclk,
      LOCKED => \^ref_dll_lock_w__0\(0),
      PWRDWN => '0',
      RST => RST0
    );
phy_control_i: unisim.vcomponents.PHY_CONTROL
    generic map(
      AO_TOGGLE => 1,
      AO_WRLVL_EN => B"0000",
      BURST_MODE => "TRUE",
      CLK_RATIO => 4,
      CMD_OFFSET => 8,
      CO_DURATION => 1,
      DATA_CTL_A_N => "TRUE",
      DATA_CTL_B_N => "TRUE",
      DATA_CTL_C_N => "TRUE",
      DATA_CTL_D_N => "TRUE",
      DISABLE_SEQ_MATCH => "TRUE",
      DI_DURATION => 1,
      DO_DURATION => 1,
      EVENTS_DELAY => 18,
      FOUR_WINDOW_CLOCKS => 63,
      MULTI_REGION => "TRUE",
      PHY_COUNT_ENABLE => "FALSE",
      RD_CMD_OFFSET_0 => 10,
      RD_CMD_OFFSET_1 => 10,
      RD_CMD_OFFSET_2 => 10,
      RD_CMD_OFFSET_3 => 10,
      RD_DURATION_0 => 6,
      RD_DURATION_1 => 6,
      RD_DURATION_2 => 6,
      RD_DURATION_3 => 6,
      SYNC_MODE => "FALSE",
      WR_CMD_OFFSET_0 => 8,
      WR_CMD_OFFSET_1 => 8,
      WR_CMD_OFFSET_2 => 8,
      WR_CMD_OFFSET_3 => 8,
      WR_DURATION_0 => 7,
      WR_DURATION_1 => 7,
      WR_DURATION_2 => 7,
      WR_DURATION_3 => 7
    )
        port map (
      AUXOUTPUT(3) => phy_control_i_n_14,
      AUXOUTPUT(2) => phy_control_i_n_15,
      AUXOUTPUT(1) => phy_control_i_n_16,
      AUXOUTPUT(0) => phy_control_i_n_17,
      INBURSTPENDING(3 downto 0) => phaser_ctl_bus(7 downto 4),
      INRANKA(1 downto 0) => phaser_ctl_bus(9 downto 8),
      INRANKB(1 downto 0) => phaser_ctl_bus(11 downto 10),
      INRANKC(1 downto 0) => phaser_ctl_bus(13 downto 12),
      INRANKD(1 downto 0) => phaser_ctl_bus(15 downto 14),
      MEMREFCLK => mem_refclk,
      OUTBURSTPENDING(3 downto 0) => phaser_ctl_bus(3 downto 0),
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      PHYCLK => CLK,
      PHYCTLALMOSTFULL => phy_control_i_n_0,
      PHYCTLEMPTY => phy_control_i_n_1,
      PHYCTLFULL => \_phy_ctl_full_p__0\(0),
      PHYCTLMSTREMPTY => phy_ctl_mstr_empty,
      PHYCTLREADY => phy_control_i_n_3,
      PHYCTLWD(31 downto 25) => B"0000001",
      PHYCTLWD(24 downto 17) => Q(10 downto 3),
      PHYCTLWD(16 downto 3) => B"00000000000000",
      PHYCTLWD(2 downto 0) => Q(2 downto 0),
      PHYCTLWRENABLE => phy_ctl_wr_i2,
      PLLLOCK => pll_locked,
      READCALIBENABLE => phy_read_calib,
      REFDLLLOCK => \^ref_dll_lock_w__0\(0),
      RESET => in0,
      SYNCIN => sync_pulse,
      WRITECALIBENABLE => phy_write_calib
    );
\pi_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_210\,
      Q => \pi_rdval_cnt_reg[5]\(0),
      R => '0'
    );
\pi_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_209\,
      Q => \pi_rdval_cnt_reg[5]\(1),
      R => '0'
    );
\pi_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_208\,
      Q => \pi_rdval_cnt_reg[5]\(2),
      R => '0'
    );
\pi_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_207\,
      Q => \pi_rdval_cnt_reg[5]\(3),
      R => '0'
    );
\pi_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_206\,
      Q => \pi_rdval_cnt_reg[5]\(4),
      R => '0'
    );
\pi_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_205\,
      Q => \pi_rdval_cnt_reg[5]\(5),
      R => '0'
    );
\po_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_220\,
      Q => \po_rdval_cnt_reg[8]\(0),
      R => '0'
    );
\po_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_219\,
      Q => \po_rdval_cnt_reg[8]\(1),
      R => '0'
    );
\po_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_218\,
      Q => \po_rdval_cnt_reg[8]\(2),
      R => '0'
    );
\po_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_217\,
      Q => \po_rdval_cnt_reg[8]\(3),
      R => '0'
    );
\po_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_216\,
      Q => \po_rdval_cnt_reg[8]\(4),
      R => '0'
    );
\po_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_215\,
      Q => \po_rdval_cnt_reg[8]\(5),
      R => '0'
    );
\po_counter_read_val_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_214\,
      Q => \po_rdval_cnt_reg[8]\(6),
      R => '0'
    );
\po_counter_read_val_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_213\,
      Q => \po_rdval_cnt_reg[8]\(7),
      R => '0'
    );
\po_counter_read_val_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_212\,
      Q => \po_rdval_cnt_reg[8]\(8),
      R => '0'
    );
\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => \rclk_delay_reg[10]_srl11_i_1__0_n_0\,
      Q => \rclk_delay_reg[10]_srl11_n_0\
    );
\rclk_delay_reg[10]_srl11_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_primitives,
      O => \rclk_delay_reg[10]_srl11_i_1__0_n_0\
    );
\rclk_delay_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rclk_delay_reg[10]_srl11_n_0\,
      Q => rclk_delay_11,
      R => '0'
    );
\rst_out_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rclk_delay_11,
      I1 => rst_out_reg_n_0,
      O => \rst_out_i_1__0_n_0\
    );
rst_out_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => SR(0),
      D => \rst_out_i_1__0_n_0\,
      Q => rst_out_reg_n_0
    );
\rst_primitives_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => phy_control_i_n_3,
      O => \rst_primitives_i_1__0_n_0\
    );
rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rst_primitives_i_1__0_n_0\,
      Q => rst_primitives,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized0\ is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    ofifo_rst_reg : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_ctl_mstr_empty : out STD_LOGIC;
    idelay_ld_rst : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    mcGo_r1 : out STD_LOGIC;
    \not_strict_mode.rd_buf_we\ : out STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : out STD_LOGIC;
    rst_sync_r1_reg : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    store_sr_req_r_reg : out STD_LOGIC;
    \pi_rdval_cnt_reg[2]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[3]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[1]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[0]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[5]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \not_strict_mode.app_rd_data_reg[32]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[34]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[36]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[38]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[96]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[98]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[100]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[102]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[160]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[162]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[164]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[166]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[224]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[226]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[228]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[230]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[288]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[290]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[292]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[294]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[352]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[354]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[356]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[358]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[416]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[418]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[420]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[422]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[480]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[482]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[484]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[486]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]_0\ : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    byte_rd_en_v_1 : out STD_LOGIC;
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_rdval_cnt_reg[0]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[1]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[2]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[3]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[4]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[5]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[6]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[7]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[8]\ : out STD_LOGIC;
    pre_data_a_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC;
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[487]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[486]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[485]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[420]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[483]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[482]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[481]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[416]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_1\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_0 : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.calib_in_common_reg_2\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_3\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_1 : in STD_LOGIC;
    D0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \init_calib_complete_reg_rep__11_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    in0 : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    PHYCTLWD : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    byte_rd_en_v_2 : in STD_LOGIC;
    byte_rd_en_v_0 : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    \_phy_ctl_full_p__0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \mcGo_w__0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_init_done_r : in STD_LOGIC;
    \ref_dll_lock_w__0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    sys_rst : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_rst_0 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__11_1\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_2\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[572]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    if_empty_or_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \read_fifo.fifo_out_data_r_reg[6]_0\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \cmd_pipe_plus.mc_cas_n_reg[2]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \init_calib_complete_reg_rep__25\ : in STD_LOGIC_VECTOR ( 45 downto 0 );
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \pi_counter_read_val_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \po_counter_read_val_reg[8]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \po_counter_read_val_reg[8]_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    D_po_coarse_enable105_out : in STD_LOGIC;
    D_po_counter_read_en117_out : in STD_LOGIC;
    D_po_fine_enable102_out : in STD_LOGIC;
    D_po_fine_inc108_out : in STD_LOGIC;
    \init_calib_complete_reg_rep__12_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    init_calib_complete_reg : in STD_LOGIC_VECTOR ( 21 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized0\ : entity is "mig_7series_v2_3_ddr_phy_4lanes";
end \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized0\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized0\ is
  signal A_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal B_of_full : STD_LOGIC;
  signal C_of_full : STD_LOGIC;
  signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal D_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \_phy_ctl_full_p\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_18\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_19\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_20\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_21\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_23\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_24\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_25\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_26\ : STD_LOGIC;
  signal mcGo_w : STD_LOGIC_VECTOR ( 1 to 1 );
  signal ofifo_rst : STD_LOGIC;
  signal \^ofifo_rst_reg\ : STD_LOGIC;
  signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 3 to 3 );
  signal phy_control_i_n_0 : STD_LOGIC;
  signal phy_control_i_n_10 : STD_LOGIC;
  signal phy_control_i_n_11 : STD_LOGIC;
  signal phy_control_i_n_14 : STD_LOGIC;
  signal phy_control_i_n_15 : STD_LOGIC;
  signal phy_control_i_n_16 : STD_LOGIC;
  signal phy_control_i_n_17 : STD_LOGIC;
  signal phy_control_i_n_18 : STD_LOGIC;
  signal phy_control_i_n_19 : STD_LOGIC;
  signal phy_control_i_n_20 : STD_LOGIC;
  signal phy_control_i_n_21 : STD_LOGIC;
  signal phy_control_i_n_23 : STD_LOGIC;
  signal phy_control_i_n_24 : STD_LOGIC;
  signal phy_control_i_n_25 : STD_LOGIC;
  signal phy_control_i_n_3 : STD_LOGIC;
  signal phy_control_i_n_4 : STD_LOGIC;
  signal phy_control_i_n_5 : STD_LOGIC;
  signal phy_control_i_n_6 : STD_LOGIC;
  signal phy_control_i_n_7 : STD_LOGIC;
  signal phy_control_i_n_8 : STD_LOGIC;
  signal phy_control_i_n_9 : STD_LOGIC;
  signal \^phy_ctl_mstr_empty\ : STD_LOGIC;
  signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \pi_counter_read_val_w[1]_1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^pi_rdval_cnt_reg[0]\ : STD_LOGIC;
  signal \^pi_rdval_cnt_reg[1]\ : STD_LOGIC;
  signal \^pi_rdval_cnt_reg[2]\ : STD_LOGIC;
  signal \^pi_rdval_cnt_reg[3]\ : STD_LOGIC;
  signal \^pi_rdval_cnt_reg[4]\ : STD_LOGIC;
  signal \^pi_rdval_cnt_reg[5]\ : STD_LOGIC;
  signal \po_counter_read_val_w[1]_0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal rclk_delay_11 : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_i_1_n_0\ : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC;
  signal ref_dll_lock_w : STD_LOGIC_VECTOR ( 1 to 1 );
  signal rst_out_i_1_n_0 : STD_LOGIC;
  signal rst_out_reg_n_0 : STD_LOGIC;
  signal rst_primitives : STD_LOGIC;
  signal rst_primitives_i_1_n_0 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE";
  attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg ";
  attribute srl_name : string;
  attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 ";
begin
  ofifo_rst_reg <= \^ofifo_rst_reg\;
  phy_ctl_mstr_empty <= \^phy_ctl_mstr_empty\;
  \pi_rdval_cnt_reg[0]\ <= \^pi_rdval_cnt_reg[0]\;
  \pi_rdval_cnt_reg[1]\ <= \^pi_rdval_cnt_reg[1]\;
  \pi_rdval_cnt_reg[2]\ <= \^pi_rdval_cnt_reg[2]\;
  \pi_rdval_cnt_reg[3]\ <= \^pi_rdval_cnt_reg[3]\;
  \pi_rdval_cnt_reg[4]\ <= \^pi_rdval_cnt_reg[4]\;
  \pi_rdval_cnt_reg[5]\ <= \^pi_rdval_cnt_reg[5]\;
A_rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_primitives,
      Q => \^ofifo_rst_reg\,
      R => '0'
    );
\cnt_idel_dec_cpt_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \pi_counter_read_val_w[1]_1\(0),
      I1 => \calib_sel_reg[4]\(2),
      I2 => Q(0),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \pi_counter_read_val_reg[5]_0\(0),
      O => \^pi_rdval_cnt_reg[0]\
    );
\cnt_idel_dec_cpt_r[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \pi_counter_read_val_w[1]_1\(1),
      I1 => \calib_sel_reg[4]\(2),
      I2 => Q(1),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \pi_counter_read_val_reg[5]_0\(1),
      O => \^pi_rdval_cnt_reg[1]\
    );
\cnt_idel_dec_cpt_r[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \pi_counter_read_val_w[1]_1\(2),
      I1 => \calib_sel_reg[4]\(2),
      I2 => Q(2),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \pi_counter_read_val_reg[5]_0\(2),
      O => \^pi_rdval_cnt_reg[2]\
    );
\cnt_idel_dec_cpt_r[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \pi_counter_read_val_w[1]_1\(3),
      I1 => \calib_sel_reg[4]\(2),
      I2 => Q(3),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \pi_counter_read_val_reg[5]_0\(3),
      O => \^pi_rdval_cnt_reg[3]\
    );
\cnt_idel_dec_cpt_r[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \pi_counter_read_val_w[1]_1\(4),
      I1 => \calib_sel_reg[4]\(2),
      I2 => Q(4),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \pi_counter_read_val_reg[5]_0\(4),
      O => \^pi_rdval_cnt_reg[4]\
    );
\cnt_idel_dec_cpt_r[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^pi_rdval_cnt_reg[2]\,
      I1 => \^pi_rdval_cnt_reg[3]\,
      I2 => \^pi_rdval_cnt_reg[1]\,
      I3 => \^pi_rdval_cnt_reg[0]\,
      I4 => \^pi_rdval_cnt_reg[5]\,
      I5 => \^pi_rdval_cnt_reg[4]\,
      O => store_sr_req_r_reg
    );
\cnt_idel_dec_cpt_r[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \pi_counter_read_val_w[1]_1\(5),
      I1 => \calib_sel_reg[4]\(2),
      I2 => Q(5),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \pi_counter_read_val_reg[5]_0\(5),
      O => \^pi_rdval_cnt_reg[5]\
    );
\ddr_byte_lane_A.ddr_byte_lane_A\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized3\
     port map (
      A_rst_primitives_reg => \^ofifo_rst_reg\,
      CLK => CLK,
      CLKB0 => CLKB0,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      INBURSTPENDING(0) => phy_control_i_n_21,
      INRANKA(1) => phy_control_i_n_4,
      INRANKA(0) => phy_control_i_n_5,
      LD0 => LD0,
      OUTBURSTPENDING(0) => phy_control_i_n_25,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      byte_rd_en_v_0 => byte_rd_en_v_0,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_0\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_1\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_2\,
      \calib_sel_reg[1]_3\ => \calib_sel_reg[1]_3\,
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_4\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      freq_refclk => freq_refclk,
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      if_empty_or_v(0) => if_empty_or_v(0),
      ififo_rst_reg0 => ififo_rst_reg0,
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10_2\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_in(0) => mem_dqs_in(0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_1\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[100]\ => \not_strict_mode.app_rd_data_reg[100]\,
      \not_strict_mode.app_rd_data_reg[101]\ => \not_strict_mode.app_rd_data_reg[101]\,
      \not_strict_mode.app_rd_data_reg[102]\ => \not_strict_mode.app_rd_data_reg[102]\,
      \not_strict_mode.app_rd_data_reg[103]\ => \not_strict_mode.app_rd_data_reg[103]\,
      \not_strict_mode.app_rd_data_reg[160]\ => \not_strict_mode.app_rd_data_reg[160]\,
      \not_strict_mode.app_rd_data_reg[161]\ => \not_strict_mode.app_rd_data_reg[161]\,
      \not_strict_mode.app_rd_data_reg[162]\ => \not_strict_mode.app_rd_data_reg[162]\,
      \not_strict_mode.app_rd_data_reg[163]\ => \not_strict_mode.app_rd_data_reg[163]\,
      \not_strict_mode.app_rd_data_reg[164]\ => \not_strict_mode.app_rd_data_reg[164]\,
      \not_strict_mode.app_rd_data_reg[165]\ => \not_strict_mode.app_rd_data_reg[165]\,
      \not_strict_mode.app_rd_data_reg[166]\ => \not_strict_mode.app_rd_data_reg[166]\,
      \not_strict_mode.app_rd_data_reg[167]\ => \not_strict_mode.app_rd_data_reg[167]\,
      \not_strict_mode.app_rd_data_reg[224]\ => \not_strict_mode.app_rd_data_reg[224]\,
      \not_strict_mode.app_rd_data_reg[225]\ => \not_strict_mode.app_rd_data_reg[225]\,
      \not_strict_mode.app_rd_data_reg[226]\ => \not_strict_mode.app_rd_data_reg[226]\,
      \not_strict_mode.app_rd_data_reg[227]\ => \not_strict_mode.app_rd_data_reg[227]\,
      \not_strict_mode.app_rd_data_reg[228]\ => \not_strict_mode.app_rd_data_reg[228]\,
      \not_strict_mode.app_rd_data_reg[229]\ => \not_strict_mode.app_rd_data_reg[229]\,
      \not_strict_mode.app_rd_data_reg[230]\ => \not_strict_mode.app_rd_data_reg[230]\,
      \not_strict_mode.app_rd_data_reg[231]\ => \not_strict_mode.app_rd_data_reg[231]\,
      \not_strict_mode.app_rd_data_reg[288]\ => \not_strict_mode.app_rd_data_reg[288]\,
      \not_strict_mode.app_rd_data_reg[289]\ => \not_strict_mode.app_rd_data_reg[289]\,
      \not_strict_mode.app_rd_data_reg[290]\ => \not_strict_mode.app_rd_data_reg[290]\,
      \not_strict_mode.app_rd_data_reg[291]\ => \not_strict_mode.app_rd_data_reg[291]\,
      \not_strict_mode.app_rd_data_reg[292]\ => \not_strict_mode.app_rd_data_reg[292]\,
      \not_strict_mode.app_rd_data_reg[293]\ => \not_strict_mode.app_rd_data_reg[293]\,
      \not_strict_mode.app_rd_data_reg[294]\ => \not_strict_mode.app_rd_data_reg[294]\,
      \not_strict_mode.app_rd_data_reg[295]\ => \not_strict_mode.app_rd_data_reg[295]\,
      \not_strict_mode.app_rd_data_reg[32]\ => \not_strict_mode.app_rd_data_reg[32]\,
      \not_strict_mode.app_rd_data_reg[33]\ => \not_strict_mode.app_rd_data_reg[33]\,
      \not_strict_mode.app_rd_data_reg[34]\ => \not_strict_mode.app_rd_data_reg[34]\,
      \not_strict_mode.app_rd_data_reg[352]\ => \not_strict_mode.app_rd_data_reg[352]\,
      \not_strict_mode.app_rd_data_reg[353]\ => \not_strict_mode.app_rd_data_reg[353]\,
      \not_strict_mode.app_rd_data_reg[354]\ => \not_strict_mode.app_rd_data_reg[354]\,
      \not_strict_mode.app_rd_data_reg[355]\ => \not_strict_mode.app_rd_data_reg[355]\,
      \not_strict_mode.app_rd_data_reg[356]\ => \not_strict_mode.app_rd_data_reg[356]\,
      \not_strict_mode.app_rd_data_reg[357]\ => \not_strict_mode.app_rd_data_reg[357]\,
      \not_strict_mode.app_rd_data_reg[358]\ => \not_strict_mode.app_rd_data_reg[358]\,
      \not_strict_mode.app_rd_data_reg[359]\ => \not_strict_mode.app_rd_data_reg[359]\,
      \not_strict_mode.app_rd_data_reg[35]\ => \not_strict_mode.app_rd_data_reg[35]\,
      \not_strict_mode.app_rd_data_reg[36]\ => \not_strict_mode.app_rd_data_reg[36]\,
      \not_strict_mode.app_rd_data_reg[37]\ => \not_strict_mode.app_rd_data_reg[37]\,
      \not_strict_mode.app_rd_data_reg[38]\ => \not_strict_mode.app_rd_data_reg[38]\,
      \not_strict_mode.app_rd_data_reg[39]\ => \not_strict_mode.app_rd_data_reg[39]\,
      \not_strict_mode.app_rd_data_reg[416]\ => \not_strict_mode.app_rd_data_reg[416]\,
      \not_strict_mode.app_rd_data_reg[417]\ => \not_strict_mode.app_rd_data_reg[417]\,
      \not_strict_mode.app_rd_data_reg[418]\ => \not_strict_mode.app_rd_data_reg[418]\,
      \not_strict_mode.app_rd_data_reg[419]\ => \not_strict_mode.app_rd_data_reg[419]\,
      \not_strict_mode.app_rd_data_reg[420]\ => \not_strict_mode.app_rd_data_reg[420]\,
      \not_strict_mode.app_rd_data_reg[421]\ => \not_strict_mode.app_rd_data_reg[421]\,
      \not_strict_mode.app_rd_data_reg[422]\ => \not_strict_mode.app_rd_data_reg[422]\,
      \not_strict_mode.app_rd_data_reg[423]\ => \not_strict_mode.app_rd_data_reg[423]\,
      \not_strict_mode.app_rd_data_reg[480]\ => \not_strict_mode.app_rd_data_reg[480]\,
      \not_strict_mode.app_rd_data_reg[481]\ => \not_strict_mode.app_rd_data_reg[481]\,
      \not_strict_mode.app_rd_data_reg[482]\ => \not_strict_mode.app_rd_data_reg[482]\,
      \not_strict_mode.app_rd_data_reg[483]\ => \not_strict_mode.app_rd_data_reg[483]\,
      \not_strict_mode.app_rd_data_reg[484]\ => \not_strict_mode.app_rd_data_reg[484]\,
      \not_strict_mode.app_rd_data_reg[485]\ => \not_strict_mode.app_rd_data_reg[485]\,
      \not_strict_mode.app_rd_data_reg[486]\ => \not_strict_mode.app_rd_data_reg[486]\,
      \not_strict_mode.app_rd_data_reg[487]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[487]\(63 downto 0),
      \not_strict_mode.app_rd_data_reg[487]_0\ => \not_strict_mode.app_rd_data_reg[487]_0\,
      \not_strict_mode.app_rd_data_reg[96]\ => \not_strict_mode.app_rd_data_reg[96]\,
      \not_strict_mode.app_rd_data_reg[97]\ => \not_strict_mode.app_rd_data_reg[97]\,
      \not_strict_mode.app_rd_data_reg[98]\ => \not_strict_mode.app_rd_data_reg[98]\,
      \not_strict_mode.app_rd_data_reg[99]\ => \not_strict_mode.app_rd_data_reg[99]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \not_strict_mode.rd_buf_we\,
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\ => \not_strict_mode.status_ram.rd_buf_we_r1_reg\,
      ofifo_rst_reg0 => ofifo_rst_reg0,
      \out\ => \out\,
      out_dqs_4 => out_dqs_4,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71 downto 0) => phy_dout(71 downto 0),
      phy_rddata_en => phy_rddata_en,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(0),
      pi_phase_locked_all_r1_reg => pi_phase_locked_all_r1_reg,
      \po_counter_read_val_reg[8]\(8 downto 0) => A_po_counter_read_val(8 downto 0),
      pre_data_a_full_v(0) => pre_data_a_full_v(0),
      ram_init_done_r => ram_init_done_r,
      \read_fifo.fifo_out_data_r_reg[6]\(0) => \read_fifo.fifo_out_data_r_reg[6]\(0),
      \read_fifo.fifo_out_data_r_reg[6]_0\ => \read_fifo.fifo_out_data_r_reg[6]_0\,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg,
      ts_dqs_4 => ts_dqs_4,
      \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[481]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[481]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[482]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[482]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[483]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[483]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[485]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[485]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[486]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[486]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[487]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[487]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[572]\(27 downto 0) => \write_buffer.wr_buf_out_data_reg[572]\(27 downto 0)
    );
\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized4\
     port map (
      A_rst_primitives_reg => \^ofifo_rst_reg\,
      A_rst_primitives_reg_0(8 downto 0) => A_po_counter_read_val(8 downto 0),
      A_rst_primitives_reg_1(8 downto 0) => C_po_counter_read_val(8 downto 0),
      B_of_full => B_of_full,
      CLK => CLK,
      COUNTERREADVAL(8 downto 0) => D_po_counter_read_val(8 downto 0),
      D(8) => \ddr_byte_lane_B.ddr_byte_lane_B_n_18\,
      D(7) => \ddr_byte_lane_B.ddr_byte_lane_B_n_19\,
      D(6) => \ddr_byte_lane_B.ddr_byte_lane_B_n_20\,
      D(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_21\,
      D(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      D(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_23\,
      D(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_24\,
      D(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_25\,
      D(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_26\,
      D1(3 downto 0) => D1(3 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D5(1 downto 0) => D5(1 downto 0),
      D6(0) => D6(0),
      OUTBURSTPENDING(0) => phy_control_i_n_24,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      SR(0) => ofifo_rst,
      \calib_sel_reg[1]\(1 downto 0) => \calib_sel_reg[4]\(1 downto 0),
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_0,
      \cmd_pipe_plus.mc_cas_n_reg[2]\(10 downto 0) => \cmd_pipe_plus.mc_cas_n_reg[2]\(10 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0),
      freq_refclk => freq_refclk,
      \gen_byte_sel_div2.calib_in_common_reg\ => \gen_byte_sel_div2.calib_in_common_reg\,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => \gen_byte_sel_div2.calib_in_common_reg_0\,
      \gen_byte_sel_div2.calib_in_common_reg_1\ => \gen_byte_sel_div2.calib_in_common_reg_1\,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      mc_cas_n(1) => mc_cas_n(2),
      mc_cas_n(0) => mc_cas_n(0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(0) => mc_ras_n(1),
      mem_dq_out(4 downto 0) => mem_dq_out(13 downto 9),
      mem_out(10 downto 0) => mem_out(10 downto 0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      sync_pulse => sync_pulse
    );
\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized5\
     port map (
      A_rst_primitives_reg => \^ofifo_rst_reg\,
      CLK => CLK,
      C_of_full => C_of_full,
      D0(0) => D0(0),
      D4(3 downto 0) => D4(3 downto 0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D9(3 downto 0) => D9(3 downto 0),
      OUTBURSTPENDING(0) => phy_control_i_n_23,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      SR(0) => ofifo_rst,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_1,
      freq_refclk => freq_refclk,
      \gen_byte_sel_div2.calib_in_common_reg\ => \gen_byte_sel_div2.calib_in_common_reg_2\,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => \gen_byte_sel_div2.calib_in_common_reg_3\,
      \gen_byte_sel_div2.calib_in_common_reg_1\ => \gen_byte_sel_div2.calib_in_common_reg_4\,
      \init_calib_complete_reg_rep__10\(3 downto 0) => \init_calib_complete_reg_rep__10\(3 downto 0),
      \init_calib_complete_reg_rep__10_0\(3 downto 0) => \init_calib_complete_reg_rep__10_0\(3 downto 0),
      \init_calib_complete_reg_rep__10_1\(3 downto 0) => \init_calib_complete_reg_rep__10_1\(3 downto 0),
      \init_calib_complete_reg_rep__11\(7 downto 0) => \init_calib_complete_reg_rep__11\(7 downto 0),
      \init_calib_complete_reg_rep__11_0\(7 downto 0) => \init_calib_complete_reg_rep__11_0\(7 downto 0),
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      mem_dq_out(11 downto 0) => mem_dq_out(25 downto 14),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_0\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_dout(46 downto 3) => \init_calib_complete_reg_rep__25\(45 downto 2),
      phy_dout(2) => \cmd_pipe_plus.mc_cas_n_reg[2]\(4),
      phy_dout(1 downto 0) => \init_calib_complete_reg_rep__25\(1 downto 0),
      \po_counter_read_val_reg[8]\(8 downto 0) => C_po_counter_read_val(8 downto 0),
      \rd_ptr_timing_reg[0]\(44 downto 0) => \rd_ptr_timing_reg[0]\(44 downto 0),
      sync_pulse => sync_pulse
    );
\ddr_byte_lane_D.ddr_byte_lane_D\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized6\
     port map (
      A_rst_primitives_reg => \^ofifo_rst_reg\,
      B_of_full => B_of_full,
      CLK => CLK,
      COUNTERREADVAL(8 downto 0) => D_po_counter_read_val(8 downto 0),
      C_of_full => C_of_full,
      D2(3 downto 0) => D2(3 downto 0),
      D_po_coarse_enable105_out => D_po_coarse_enable105_out,
      D_po_counter_read_en117_out => D_po_counter_read_en117_out,
      D_po_fine_enable102_out => D_po_fine_enable102_out,
      D_po_fine_inc108_out => D_po_fine_inc108_out,
      OUTBURSTPENDING(0) => phaser_ctl_bus(3),
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      SR(0) => ofifo_rst,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      freq_refclk => freq_refclk,
      init_calib_complete_reg(21 downto 0) => init_calib_complete_reg(21 downto 0),
      \init_calib_complete_reg_rep__11\ => \init_calib_complete_reg_rep__11_1\,
      \init_calib_complete_reg_rep__12\(3 downto 0) => \init_calib_complete_reg_rep__12_0\(3 downto 0),
      \init_calib_complete_reg_rep__12_0\(3 downto 0) => \init_calib_complete_reg_rep__12_1\(3 downto 0),
      \init_calib_complete_reg_rep__12_1\(3 downto 0) => \init_calib_complete_reg_rep__12_2\(3 downto 0),
      \init_calib_complete_reg_rep__12_2\ => \init_calib_complete_reg_rep__12\,
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(0) => mc_cas_n(1),
      mem_dq_out(5 downto 0) => mem_dq_out(31 downto 26),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_2\,
      of_ctl_full_v(0) => of_ctl_full_v(0),
      phy_cmd_wr_en => phy_cmd_wr_en,
      \rd_ptr_timing_reg[0]\(15 downto 0) => \rd_ptr_timing_reg[0]_0\(15 downto 0),
      sync_pulse => sync_pulse
    );
\mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => mcGo_w(1),
      I1 => \mcGo_w__0\(1),
      I2 => \mcGo_w__0\(0),
      O => mcGo_r1
    );
mcGo_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_out_reg_n_0,
      Q => mcGo_w(1),
      R => '0'
    );
phaser_ref_i: unisim.vcomponents.PHASER_REF
    generic map(
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0'
    )
        port map (
      CLKIN => freq_refclk,
      LOCKED => ref_dll_lock_w(1),
      PWRDWN => '0',
      RST => RST0
    );
phy_control_i: unisim.vcomponents.PHY_CONTROL
    generic map(
      AO_TOGGLE => 1,
      AO_WRLVL_EN => B"0000",
      BURST_MODE => "TRUE",
      CLK_RATIO => 4,
      CMD_OFFSET => 8,
      CO_DURATION => 1,
      DATA_CTL_A_N => "TRUE",
      DATA_CTL_B_N => "FALSE",
      DATA_CTL_C_N => "FALSE",
      DATA_CTL_D_N => "FALSE",
      DISABLE_SEQ_MATCH => "TRUE",
      DI_DURATION => 1,
      DO_DURATION => 1,
      EVENTS_DELAY => 18,
      FOUR_WINDOW_CLOCKS => 63,
      MULTI_REGION => "TRUE",
      PHY_COUNT_ENABLE => "FALSE",
      RD_CMD_OFFSET_0 => 10,
      RD_CMD_OFFSET_1 => 10,
      RD_CMD_OFFSET_2 => 10,
      RD_CMD_OFFSET_3 => 10,
      RD_DURATION_0 => 6,
      RD_DURATION_1 => 6,
      RD_DURATION_2 => 6,
      RD_DURATION_3 => 6,
      SYNC_MODE => "FALSE",
      WR_CMD_OFFSET_0 => 8,
      WR_CMD_OFFSET_1 => 8,
      WR_CMD_OFFSET_2 => 8,
      WR_CMD_OFFSET_3 => 8,
      WR_DURATION_0 => 7,
      WR_DURATION_1 => 7,
      WR_DURATION_2 => 7,
      WR_DURATION_3 => 7
    )
        port map (
      AUXOUTPUT(3) => phy_control_i_n_14,
      AUXOUTPUT(2) => phy_control_i_n_15,
      AUXOUTPUT(1) => phy_control_i_n_16,
      AUXOUTPUT(0) => phy_control_i_n_17,
      INBURSTPENDING(3) => phy_control_i_n_18,
      INBURSTPENDING(2) => phy_control_i_n_19,
      INBURSTPENDING(1) => phy_control_i_n_20,
      INBURSTPENDING(0) => phy_control_i_n_21,
      INRANKA(1) => phy_control_i_n_4,
      INRANKA(0) => phy_control_i_n_5,
      INRANKB(1) => phy_control_i_n_6,
      INRANKB(0) => phy_control_i_n_7,
      INRANKC(1) => phy_control_i_n_8,
      INRANKC(0) => phy_control_i_n_9,
      INRANKD(1) => phy_control_i_n_10,
      INRANKD(0) => phy_control_i_n_11,
      MEMREFCLK => mem_refclk,
      OUTBURSTPENDING(3) => phaser_ctl_bus(3),
      OUTBURSTPENDING(2) => phy_control_i_n_23,
      OUTBURSTPENDING(1) => phy_control_i_n_24,
      OUTBURSTPENDING(0) => phy_control_i_n_25,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      PHYCLK => CLK,
      PHYCTLALMOSTFULL => phy_control_i_n_0,
      PHYCTLEMPTY => \^phy_ctl_mstr_empty\,
      PHYCTLFULL => \_phy_ctl_full_p\(1),
      PHYCTLMSTREMPTY => \^phy_ctl_mstr_empty\,
      PHYCTLREADY => phy_control_i_n_3,
      PHYCTLWD(31 downto 25) => B"0000001",
      PHYCTLWD(24 downto 17) => PHYCTLWD(10 downto 3),
      PHYCTLWD(16 downto 3) => B"00000000000000",
      PHYCTLWD(2 downto 0) => PHYCTLWD(2 downto 0),
      PHYCTLWRENABLE => phy_ctl_wr_i2,
      PLLLOCK => pll_locked,
      READCALIBENABLE => phy_read_calib,
      REFDLLLOCK => ref_dll_lock_w(1),
      RESET => in0,
      SYNCIN => sync_pulse,
      WRITECALIBENABLE => phy_write_calib
    );
phy_mc_ctl_full_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \_phy_ctl_full_p\(1),
      I1 => \_phy_ctl_full_p__0\(1),
      I2 => \_phy_ctl_full_p__0\(0),
      O => phy_mc_ctl_full
    );
\pi_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => \pi_counter_read_val_w[1]_1\(0),
      R => '0'
    );
\pi_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => \pi_counter_read_val_w[1]_1\(1),
      R => '0'
    );
\pi_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => \pi_counter_read_val_w[1]_1\(2),
      R => '0'
    );
\pi_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(3),
      Q => \pi_counter_read_val_w[1]_1\(3),
      R => '0'
    );
\pi_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(4),
      Q => \pi_counter_read_val_w[1]_1\(4),
      R => '0'
    );
\pi_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(5),
      Q => \pi_counter_read_val_w[1]_1\(5),
      R => '0'
    );
\po_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_26\,
      Q => \po_counter_read_val_w[1]_0\(0),
      R => '0'
    );
\po_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_25\,
      Q => \po_counter_read_val_w[1]_0\(1),
      R => '0'
    );
\po_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_24\,
      Q => \po_counter_read_val_w[1]_0\(2),
      R => '0'
    );
\po_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_23\,
      Q => \po_counter_read_val_w[1]_0\(3),
      R => '0'
    );
\po_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      Q => \po_counter_read_val_w[1]_0\(4),
      R => '0'
    );
\po_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_21\,
      Q => \po_counter_read_val_w[1]_0\(5),
      R => '0'
    );
\po_counter_read_val_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_20\,
      Q => \po_counter_read_val_w[1]_0\(6),
      R => '0'
    );
\po_counter_read_val_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_19\,
      Q => \po_counter_read_val_w[1]_0\(7),
      R => '0'
    );
\po_counter_read_val_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \ddr_byte_lane_B.ddr_byte_lane_B_n_18\,
      Q => \po_counter_read_val_w[1]_0\(8),
      R => '0'
    );
\po_rdval_cnt[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(0),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(0),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(0),
      O => \po_rdval_cnt_reg[0]\
    );
\po_rdval_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(1),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(1),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(1),
      O => \po_rdval_cnt_reg[1]\
    );
\po_rdval_cnt[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(2),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(2),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(2),
      O => \po_rdval_cnt_reg[2]\
    );
\po_rdval_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(3),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(3),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(3),
      O => \po_rdval_cnt_reg[3]\
    );
\po_rdval_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(4),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(4),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(4),
      O => \po_rdval_cnt_reg[4]\
    );
\po_rdval_cnt[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(5),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(5),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(5),
      O => \po_rdval_cnt_reg[5]\
    );
\po_rdval_cnt[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(6),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(6),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(6),
      O => \po_rdval_cnt_reg[6]\
    );
\po_rdval_cnt[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(7),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(7),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(7),
      O => \po_rdval_cnt_reg[7]\
    );
\po_rdval_cnt[8]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \po_counter_read_val_w[1]_0\(8),
      I1 => \calib_sel_reg[4]\(2),
      I2 => \po_counter_read_val_reg[8]_0\(8),
      I3 => \calib_sel_reg[4]\(3),
      I4 => \po_counter_read_val_reg[8]_1\(8),
      O => \po_rdval_cnt_reg[8]\
    );
\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => \rclk_delay_reg[10]_srl11_i_1_n_0\,
      Q => \rclk_delay_reg[10]_srl11_n_0\
    );
\rclk_delay_reg[10]_srl11_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_primitives,
      O => \rclk_delay_reg[10]_srl11_i_1_n_0\
    );
\rclk_delay_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rclk_delay_reg[10]_srl11_n_0\,
      Q => rclk_delay_11,
      R => '0'
    );
rst_out_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rclk_delay_11,
      I1 => rst_out_reg_n_0,
      O => rst_out_i_1_n_0
    );
rst_out_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => in0,
      D => rst_out_i_1_n_0,
      Q => rst_out_reg_n_0
    );
rst_primitives_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => phy_control_i_n_3,
      O => rst_primitives_i_1_n_0
    );
rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_primitives_i_1_n_0,
      Q => rst_primitives,
      R => '0'
    );
\rstdiv0_sync_r[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => ref_dll_lock_w(1),
      I1 => \ref_dll_lock_w__0\(1),
      I2 => \ref_dll_lock_w__0\(0),
      I3 => sys_rst,
      I4 => iodelay_ctrl_rdy(0),
      I5 => sys_rst_0,
      O => rst_sync_r1_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized1\ is
  port (
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 26 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 26 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 2 downto 0 );
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \_phy_ctl_full_p__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ref_dll_lock_w__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \mcGo_w__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    idelay_ld_rst_5 : out STD_LOGIC;
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_1\ : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[48]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[42]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[50]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[44]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[52]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[46]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[54]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[104]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[112]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[106]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[114]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[108]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[116]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[110]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[118]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[168]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[176]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[170]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[178]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[172]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[180]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[174]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[182]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[232]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[240]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[234]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[242]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[236]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[244]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[238]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[246]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[296]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[304]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[298]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[306]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[300]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[308]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[302]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[310]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[360]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[368]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[362]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[370]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[364]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[372]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[366]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[374]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[424]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[432]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[426]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[434]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[428]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[436]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[430]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[438]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[488]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[496]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[490]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[498]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[492]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[500]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[494]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[502]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC_VECTOR ( 191 downto 0 );
    \not_strict_mode.app_rd_data_reg[56]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[58]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[60]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[62]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[120]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[122]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[124]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[126]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[184]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[186]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[188]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[190]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[248]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[250]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[252]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[254]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[312]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[314]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[316]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[318]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[376]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[378]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[380]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[382]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[440]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[442]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[444]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[446]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[504]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[506]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[508]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[510]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC;
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    if_empty_or_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    byte_rd_en_v_2 : out STD_LOGIC;
    A_byte_rd_en : out STD_LOGIC;
    B_byte_rd_en : out STD_LOGIC;
    C_byte_rd_en : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_0\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \pi_rdval_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_mc_data_full : out STD_LOGIC;
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    \calib_sel_reg[1]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[511]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[510]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[509]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[444]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[507]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[506]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[505]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[440]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_11 : in STD_LOGIC;
    idelay_ce_r2_reg : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    pi_stg2_load_reg : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_0 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_0 : in STD_LOGIC;
    \pi_rst_stg1_cal_reg[2]\ : in STD_LOGIC;
    \pi_stg2_reg_l_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg : in STD_LOGIC;
    \calib_sel_reg[0]_0\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_0 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[503]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[502]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[501]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[436]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[499]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[498]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[497]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[432]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_13 : in STD_LOGIC;
    \calib_sel_reg[1]_6\ : in STD_LOGIC;
    LD0_14 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \calib_sel_reg[1]_7\ : in STD_LOGIC;
    \calib_sel_reg[1]_8\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_1 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_1 : in STD_LOGIC;
    \calib_sel_reg[1]_9\ : in STD_LOGIC;
    \calib_sel_reg[1]_10\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_11\ : in STD_LOGIC;
    \calib_sel_reg[1]_12\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_1 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[495]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[494]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[493]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[428]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[491]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[490]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[489]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[424]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_15 : in STD_LOGIC;
    phy_ctl_mstr_empty : in STD_LOGIC;
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    in0 : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    PHYCTLWD : in STD_LOGIC_VECTOR ( 10 downto 0 );
    RST0 : in STD_LOGIC;
    phy_if_reset : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]\ : in STD_LOGIC_VECTOR ( 83 downto 0 );
    \init_calib_complete_reg_rep__8\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_0\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_1\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_2\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_3\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_4\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_5\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_6\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_7\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_8\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_9\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_10\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_11\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_12\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_13\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_14\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_15\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_16\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_17\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_18\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_19\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_20\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_21\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_22\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_23\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_24\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_25\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_26\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_27\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_28\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_29\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_30\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_31\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_32\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_33\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_34\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_35\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_36\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_37\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_38\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_39\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_40\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_41\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_42\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_43\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_44\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_45\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_46\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_47\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_48\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_49\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_50\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_51\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_52\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_53\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_54\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_55\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_56\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_57\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_58\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_59\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_60\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_61\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_62\ : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]_63\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    A_rst_primitives_reg_0 : in STD_LOGIC;
    A_rst_primitives_reg_1 : in STD_LOGIC;
    \po_stg2_wrcal_cnt_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mux_wrdata : in STD_LOGIC_VECTOR ( 155 downto 0 );
    \write_buffer.wr_buf_out_data_reg[383]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
    mux_wrdata_mask : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \calib_sel_reg[1]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pre_data_a_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    \entry_cnt_reg[2]\ : in STD_LOGIC;
    \entry_cnt_reg[2]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized1\ : entity is "mig_7series_v2_3_ddr_phy_4lanes";
end \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized1\;

architecture STRUCTURE of \mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized1\ is
  signal A_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal A_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal B_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal B_rclk : STD_LOGIC;
  signal C_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \_phy_ctl_a_full_p\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \aux_out_\ : STD_LOGIC_VECTOR ( 11 downto 8 );
  signal \ddr_byte_lane_A.ddr_byte_lane_A_n_22\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_173\ : STD_LOGIC;
  signal \ddr_byte_lane_B.ddr_byte_lane_B_n_22\ : STD_LOGIC;
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal if_empty_r : STD_LOGIC_VECTOR ( 3 to 3 );
  signal if_empty_r_1 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \^not_strict_mode.app_rd_data_reg[104]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[105]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[106]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[107]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[108]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[109]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[110]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[111]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[112]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[113]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[114]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[115]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[116]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[117]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[118]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[119]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[168]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[169]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[170]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[171]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[172]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[173]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[174]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[175]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[176]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[177]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[178]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[179]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[180]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[181]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[182]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[183]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[232]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[233]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[234]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[235]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[236]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[237]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[238]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[239]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[240]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[241]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[242]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[243]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[244]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[245]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[246]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[247]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[296]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[297]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[298]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[299]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[300]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[301]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[302]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[303]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[304]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[305]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[306]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[307]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[308]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[309]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[310]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[311]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[360]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[361]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[362]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[363]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[364]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[365]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[366]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[367]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[368]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[369]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[370]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[371]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[372]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[373]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[374]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[375]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[40]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[41]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[424]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[425]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[426]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[427]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[428]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[429]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[42]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[430]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[431]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[432]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[433]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[434]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[435]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[436]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[437]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[438]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[439]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[43]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[44]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[45]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[46]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[47]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[488]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[489]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[48]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[490]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[491]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[492]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[493]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[494]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[495]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[496]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[497]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[498]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[499]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[49]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[500]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[501]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[502]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[503]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[50]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[51]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[52]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[53]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[54]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[55]\ : STD_LOGIC;
  signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal p_0_in : STD_LOGIC_VECTOR ( 2 to 2 );
  signal p_0_in_0 : STD_LOGIC;
  signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal phy_control_i_n_1 : STD_LOGIC;
  signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \pi_counter_read_val[0]_i_1_n_0\ : STD_LOGIC;
  signal \pi_counter_read_val[1]_i_1_n_0\ : STD_LOGIC;
  signal \pi_counter_read_val[2]_i_1_n_0\ : STD_LOGIC;
  signal \pi_counter_read_val[3]_i_1_n_0\ : STD_LOGIC;
  signal \pi_counter_read_val[4]_i_1_n_0\ : STD_LOGIC;
  signal \pi_counter_read_val[5]_i_1_n_0\ : STD_LOGIC;
  signal \^pi_dqs_found_lanes_r1_reg[10]\ : STD_LOGIC;
  signal \po_counter_read_val[0]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[1]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[2]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[3]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[4]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[5]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[6]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[7]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_read_val[8]_i_1_n_0\ : STD_LOGIC;
  signal rclk_delay_11 : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_i_1__1_n_0\ : STD_LOGIC;
  signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC;
  signal \^ref_dll_lock_w__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rst_out_i_1__1_n_0\ : STD_LOGIC;
  signal rst_out_reg_n_0 : STD_LOGIC;
  signal rst_primitives : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE";
  attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg ";
  attribute srl_name : string;
  attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 ";
begin
  \not_strict_mode.app_rd_data_reg[104]\ <= \^not_strict_mode.app_rd_data_reg[104]\;
  \not_strict_mode.app_rd_data_reg[105]\ <= \^not_strict_mode.app_rd_data_reg[105]\;
  \not_strict_mode.app_rd_data_reg[106]\ <= \^not_strict_mode.app_rd_data_reg[106]\;
  \not_strict_mode.app_rd_data_reg[107]\ <= \^not_strict_mode.app_rd_data_reg[107]\;
  \not_strict_mode.app_rd_data_reg[108]\ <= \^not_strict_mode.app_rd_data_reg[108]\;
  \not_strict_mode.app_rd_data_reg[109]\ <= \^not_strict_mode.app_rd_data_reg[109]\;
  \not_strict_mode.app_rd_data_reg[110]\ <= \^not_strict_mode.app_rd_data_reg[110]\;
  \not_strict_mode.app_rd_data_reg[111]\ <= \^not_strict_mode.app_rd_data_reg[111]\;
  \not_strict_mode.app_rd_data_reg[112]\ <= \^not_strict_mode.app_rd_data_reg[112]\;
  \not_strict_mode.app_rd_data_reg[113]\ <= \^not_strict_mode.app_rd_data_reg[113]\;
  \not_strict_mode.app_rd_data_reg[114]\ <= \^not_strict_mode.app_rd_data_reg[114]\;
  \not_strict_mode.app_rd_data_reg[115]\ <= \^not_strict_mode.app_rd_data_reg[115]\;
  \not_strict_mode.app_rd_data_reg[116]\ <= \^not_strict_mode.app_rd_data_reg[116]\;
  \not_strict_mode.app_rd_data_reg[117]\ <= \^not_strict_mode.app_rd_data_reg[117]\;
  \not_strict_mode.app_rd_data_reg[118]\ <= \^not_strict_mode.app_rd_data_reg[118]\;
  \not_strict_mode.app_rd_data_reg[119]\ <= \^not_strict_mode.app_rd_data_reg[119]\;
  \not_strict_mode.app_rd_data_reg[168]\ <= \^not_strict_mode.app_rd_data_reg[168]\;
  \not_strict_mode.app_rd_data_reg[169]\ <= \^not_strict_mode.app_rd_data_reg[169]\;
  \not_strict_mode.app_rd_data_reg[170]\ <= \^not_strict_mode.app_rd_data_reg[170]\;
  \not_strict_mode.app_rd_data_reg[171]\ <= \^not_strict_mode.app_rd_data_reg[171]\;
  \not_strict_mode.app_rd_data_reg[172]\ <= \^not_strict_mode.app_rd_data_reg[172]\;
  \not_strict_mode.app_rd_data_reg[173]\ <= \^not_strict_mode.app_rd_data_reg[173]\;
  \not_strict_mode.app_rd_data_reg[174]\ <= \^not_strict_mode.app_rd_data_reg[174]\;
  \not_strict_mode.app_rd_data_reg[175]\ <= \^not_strict_mode.app_rd_data_reg[175]\;
  \not_strict_mode.app_rd_data_reg[176]\ <= \^not_strict_mode.app_rd_data_reg[176]\;
  \not_strict_mode.app_rd_data_reg[177]\ <= \^not_strict_mode.app_rd_data_reg[177]\;
  \not_strict_mode.app_rd_data_reg[178]\ <= \^not_strict_mode.app_rd_data_reg[178]\;
  \not_strict_mode.app_rd_data_reg[179]\ <= \^not_strict_mode.app_rd_data_reg[179]\;
  \not_strict_mode.app_rd_data_reg[180]\ <= \^not_strict_mode.app_rd_data_reg[180]\;
  \not_strict_mode.app_rd_data_reg[181]\ <= \^not_strict_mode.app_rd_data_reg[181]\;
  \not_strict_mode.app_rd_data_reg[182]\ <= \^not_strict_mode.app_rd_data_reg[182]\;
  \not_strict_mode.app_rd_data_reg[183]\ <= \^not_strict_mode.app_rd_data_reg[183]\;
  \not_strict_mode.app_rd_data_reg[232]\ <= \^not_strict_mode.app_rd_data_reg[232]\;
  \not_strict_mode.app_rd_data_reg[233]\ <= \^not_strict_mode.app_rd_data_reg[233]\;
  \not_strict_mode.app_rd_data_reg[234]\ <= \^not_strict_mode.app_rd_data_reg[234]\;
  \not_strict_mode.app_rd_data_reg[235]\ <= \^not_strict_mode.app_rd_data_reg[235]\;
  \not_strict_mode.app_rd_data_reg[236]\ <= \^not_strict_mode.app_rd_data_reg[236]\;
  \not_strict_mode.app_rd_data_reg[237]\ <= \^not_strict_mode.app_rd_data_reg[237]\;
  \not_strict_mode.app_rd_data_reg[238]\ <= \^not_strict_mode.app_rd_data_reg[238]\;
  \not_strict_mode.app_rd_data_reg[239]\ <= \^not_strict_mode.app_rd_data_reg[239]\;
  \not_strict_mode.app_rd_data_reg[240]\ <= \^not_strict_mode.app_rd_data_reg[240]\;
  \not_strict_mode.app_rd_data_reg[241]\ <= \^not_strict_mode.app_rd_data_reg[241]\;
  \not_strict_mode.app_rd_data_reg[242]\ <= \^not_strict_mode.app_rd_data_reg[242]\;
  \not_strict_mode.app_rd_data_reg[243]\ <= \^not_strict_mode.app_rd_data_reg[243]\;
  \not_strict_mode.app_rd_data_reg[244]\ <= \^not_strict_mode.app_rd_data_reg[244]\;
  \not_strict_mode.app_rd_data_reg[245]\ <= \^not_strict_mode.app_rd_data_reg[245]\;
  \not_strict_mode.app_rd_data_reg[246]\ <= \^not_strict_mode.app_rd_data_reg[246]\;
  \not_strict_mode.app_rd_data_reg[247]\ <= \^not_strict_mode.app_rd_data_reg[247]\;
  \not_strict_mode.app_rd_data_reg[296]\ <= \^not_strict_mode.app_rd_data_reg[296]\;
  \not_strict_mode.app_rd_data_reg[297]\ <= \^not_strict_mode.app_rd_data_reg[297]\;
  \not_strict_mode.app_rd_data_reg[298]\ <= \^not_strict_mode.app_rd_data_reg[298]\;
  \not_strict_mode.app_rd_data_reg[299]\ <= \^not_strict_mode.app_rd_data_reg[299]\;
  \not_strict_mode.app_rd_data_reg[300]\ <= \^not_strict_mode.app_rd_data_reg[300]\;
  \not_strict_mode.app_rd_data_reg[301]\ <= \^not_strict_mode.app_rd_data_reg[301]\;
  \not_strict_mode.app_rd_data_reg[302]\ <= \^not_strict_mode.app_rd_data_reg[302]\;
  \not_strict_mode.app_rd_data_reg[303]\ <= \^not_strict_mode.app_rd_data_reg[303]\;
  \not_strict_mode.app_rd_data_reg[304]\ <= \^not_strict_mode.app_rd_data_reg[304]\;
  \not_strict_mode.app_rd_data_reg[305]\ <= \^not_strict_mode.app_rd_data_reg[305]\;
  \not_strict_mode.app_rd_data_reg[306]\ <= \^not_strict_mode.app_rd_data_reg[306]\;
  \not_strict_mode.app_rd_data_reg[307]\ <= \^not_strict_mode.app_rd_data_reg[307]\;
  \not_strict_mode.app_rd_data_reg[308]\ <= \^not_strict_mode.app_rd_data_reg[308]\;
  \not_strict_mode.app_rd_data_reg[309]\ <= \^not_strict_mode.app_rd_data_reg[309]\;
  \not_strict_mode.app_rd_data_reg[310]\ <= \^not_strict_mode.app_rd_data_reg[310]\;
  \not_strict_mode.app_rd_data_reg[311]\ <= \^not_strict_mode.app_rd_data_reg[311]\;
  \not_strict_mode.app_rd_data_reg[360]\ <= \^not_strict_mode.app_rd_data_reg[360]\;
  \not_strict_mode.app_rd_data_reg[361]\ <= \^not_strict_mode.app_rd_data_reg[361]\;
  \not_strict_mode.app_rd_data_reg[362]\ <= \^not_strict_mode.app_rd_data_reg[362]\;
  \not_strict_mode.app_rd_data_reg[363]\ <= \^not_strict_mode.app_rd_data_reg[363]\;
  \not_strict_mode.app_rd_data_reg[364]\ <= \^not_strict_mode.app_rd_data_reg[364]\;
  \not_strict_mode.app_rd_data_reg[365]\ <= \^not_strict_mode.app_rd_data_reg[365]\;
  \not_strict_mode.app_rd_data_reg[366]\ <= \^not_strict_mode.app_rd_data_reg[366]\;
  \not_strict_mode.app_rd_data_reg[367]\ <= \^not_strict_mode.app_rd_data_reg[367]\;
  \not_strict_mode.app_rd_data_reg[368]\ <= \^not_strict_mode.app_rd_data_reg[368]\;
  \not_strict_mode.app_rd_data_reg[369]\ <= \^not_strict_mode.app_rd_data_reg[369]\;
  \not_strict_mode.app_rd_data_reg[370]\ <= \^not_strict_mode.app_rd_data_reg[370]\;
  \not_strict_mode.app_rd_data_reg[371]\ <= \^not_strict_mode.app_rd_data_reg[371]\;
  \not_strict_mode.app_rd_data_reg[372]\ <= \^not_strict_mode.app_rd_data_reg[372]\;
  \not_strict_mode.app_rd_data_reg[373]\ <= \^not_strict_mode.app_rd_data_reg[373]\;
  \not_strict_mode.app_rd_data_reg[374]\ <= \^not_strict_mode.app_rd_data_reg[374]\;
  \not_strict_mode.app_rd_data_reg[375]\ <= \^not_strict_mode.app_rd_data_reg[375]\;
  \not_strict_mode.app_rd_data_reg[40]\ <= \^not_strict_mode.app_rd_data_reg[40]\;
  \not_strict_mode.app_rd_data_reg[41]\ <= \^not_strict_mode.app_rd_data_reg[41]\;
  \not_strict_mode.app_rd_data_reg[424]\ <= \^not_strict_mode.app_rd_data_reg[424]\;
  \not_strict_mode.app_rd_data_reg[425]\ <= \^not_strict_mode.app_rd_data_reg[425]\;
  \not_strict_mode.app_rd_data_reg[426]\ <= \^not_strict_mode.app_rd_data_reg[426]\;
  \not_strict_mode.app_rd_data_reg[427]\ <= \^not_strict_mode.app_rd_data_reg[427]\;
  \not_strict_mode.app_rd_data_reg[428]\ <= \^not_strict_mode.app_rd_data_reg[428]\;
  \not_strict_mode.app_rd_data_reg[429]\ <= \^not_strict_mode.app_rd_data_reg[429]\;
  \not_strict_mode.app_rd_data_reg[42]\ <= \^not_strict_mode.app_rd_data_reg[42]\;
  \not_strict_mode.app_rd_data_reg[430]\ <= \^not_strict_mode.app_rd_data_reg[430]\;
  \not_strict_mode.app_rd_data_reg[431]\ <= \^not_strict_mode.app_rd_data_reg[431]\;
  \not_strict_mode.app_rd_data_reg[432]\ <= \^not_strict_mode.app_rd_data_reg[432]\;
  \not_strict_mode.app_rd_data_reg[433]\ <= \^not_strict_mode.app_rd_data_reg[433]\;
  \not_strict_mode.app_rd_data_reg[434]\ <= \^not_strict_mode.app_rd_data_reg[434]\;
  \not_strict_mode.app_rd_data_reg[435]\ <= \^not_strict_mode.app_rd_data_reg[435]\;
  \not_strict_mode.app_rd_data_reg[436]\ <= \^not_strict_mode.app_rd_data_reg[436]\;
  \not_strict_mode.app_rd_data_reg[437]\ <= \^not_strict_mode.app_rd_data_reg[437]\;
  \not_strict_mode.app_rd_data_reg[438]\ <= \^not_strict_mode.app_rd_data_reg[438]\;
  \not_strict_mode.app_rd_data_reg[439]\ <= \^not_strict_mode.app_rd_data_reg[439]\;
  \not_strict_mode.app_rd_data_reg[43]\ <= \^not_strict_mode.app_rd_data_reg[43]\;
  \not_strict_mode.app_rd_data_reg[44]\ <= \^not_strict_mode.app_rd_data_reg[44]\;
  \not_strict_mode.app_rd_data_reg[45]\ <= \^not_strict_mode.app_rd_data_reg[45]\;
  \not_strict_mode.app_rd_data_reg[46]\ <= \^not_strict_mode.app_rd_data_reg[46]\;
  \not_strict_mode.app_rd_data_reg[47]\ <= \^not_strict_mode.app_rd_data_reg[47]\;
  \not_strict_mode.app_rd_data_reg[488]\ <= \^not_strict_mode.app_rd_data_reg[488]\;
  \not_strict_mode.app_rd_data_reg[489]\ <= \^not_strict_mode.app_rd_data_reg[489]\;
  \not_strict_mode.app_rd_data_reg[48]\ <= \^not_strict_mode.app_rd_data_reg[48]\;
  \not_strict_mode.app_rd_data_reg[490]\ <= \^not_strict_mode.app_rd_data_reg[490]\;
  \not_strict_mode.app_rd_data_reg[491]\ <= \^not_strict_mode.app_rd_data_reg[491]\;
  \not_strict_mode.app_rd_data_reg[492]\ <= \^not_strict_mode.app_rd_data_reg[492]\;
  \not_strict_mode.app_rd_data_reg[493]\ <= \^not_strict_mode.app_rd_data_reg[493]\;
  \not_strict_mode.app_rd_data_reg[494]\ <= \^not_strict_mode.app_rd_data_reg[494]\;
  \not_strict_mode.app_rd_data_reg[495]\ <= \^not_strict_mode.app_rd_data_reg[495]\;
  \not_strict_mode.app_rd_data_reg[496]\ <= \^not_strict_mode.app_rd_data_reg[496]\;
  \not_strict_mode.app_rd_data_reg[497]\ <= \^not_strict_mode.app_rd_data_reg[497]\;
  \not_strict_mode.app_rd_data_reg[498]\ <= \^not_strict_mode.app_rd_data_reg[498]\;
  \not_strict_mode.app_rd_data_reg[499]\ <= \^not_strict_mode.app_rd_data_reg[499]\;
  \not_strict_mode.app_rd_data_reg[49]\ <= \^not_strict_mode.app_rd_data_reg[49]\;
  \not_strict_mode.app_rd_data_reg[500]\ <= \^not_strict_mode.app_rd_data_reg[500]\;
  \not_strict_mode.app_rd_data_reg[501]\ <= \^not_strict_mode.app_rd_data_reg[501]\;
  \not_strict_mode.app_rd_data_reg[502]\ <= \^not_strict_mode.app_rd_data_reg[502]\;
  \not_strict_mode.app_rd_data_reg[503]\ <= \^not_strict_mode.app_rd_data_reg[503]\;
  \not_strict_mode.app_rd_data_reg[50]\ <= \^not_strict_mode.app_rd_data_reg[50]\;
  \not_strict_mode.app_rd_data_reg[51]\ <= \^not_strict_mode.app_rd_data_reg[51]\;
  \not_strict_mode.app_rd_data_reg[52]\ <= \^not_strict_mode.app_rd_data_reg[52]\;
  \not_strict_mode.app_rd_data_reg[53]\ <= \^not_strict_mode.app_rd_data_reg[53]\;
  \not_strict_mode.app_rd_data_reg[54]\ <= \^not_strict_mode.app_rd_data_reg[54]\;
  \not_strict_mode.app_rd_data_reg[55]\ <= \^not_strict_mode.app_rd_data_reg[55]\;
  \pi_dqs_found_lanes_r1_reg[10]\ <= \^pi_dqs_found_lanes_r1_reg[10]\;
  \ref_dll_lock_w__0\(0) <= \^ref_dll_lock_w__0\(0);
A_rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_primitives,
      Q => \^pi_dqs_found_lanes_r1_reg[10]\,
      R => '0'
    );
\ddr_byte_lane_A.ddr_byte_lane_A\: entity work.mig_7series_0_mig_7series_v2_3_ddr_byte_lane
     port map (
      A_byte_rd_en => A_byte_rd_en,
      A_rst_primitives_reg => \^pi_dqs_found_lanes_r1_reg[10]\,
      CLK => CLK,
      CLKB0_11 => CLKB0_11,
      COUNTERREADVAL(5 downto 0) => A_pi_counter_read_val(5 downto 0),
      LD0_10 => LD0_10,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2),
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_0\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_1\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_2\,
      \calib_sel_reg[1]_3\(5 downto 0) => \calib_sel_reg[1]_3\(5 downto 0),
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_4\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_5\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \^not_strict_mode.app_rd_data_reg[183]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ => \^not_strict_mode.app_rd_data_reg[175]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \^not_strict_mode.app_rd_data_reg[247]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ => \^not_strict_mode.app_rd_data_reg[239]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \^not_strict_mode.app_rd_data_reg[311]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ => \^not_strict_mode.app_rd_data_reg[303]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \^not_strict_mode.app_rd_data_reg[375]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ => \^not_strict_mode.app_rd_data_reg[367]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \^not_strict_mode.app_rd_data_reg[439]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ => \^not_strict_mode.app_rd_data_reg[431]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \^not_strict_mode.app_rd_data_reg[503]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ => \^not_strict_mode.app_rd_data_reg[495]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \^not_strict_mode.app_rd_data_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^not_strict_mode.app_rd_data_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \^not_strict_mode.app_rd_data_reg[118]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \^not_strict_mode.app_rd_data_reg[110]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \^not_strict_mode.app_rd_data_reg[182]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \^not_strict_mode.app_rd_data_reg[174]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \^not_strict_mode.app_rd_data_reg[246]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \^not_strict_mode.app_rd_data_reg[238]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \^not_strict_mode.app_rd_data_reg[310]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \^not_strict_mode.app_rd_data_reg[302]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \^not_strict_mode.app_rd_data_reg[374]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \^not_strict_mode.app_rd_data_reg[366]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \^not_strict_mode.app_rd_data_reg[438]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \^not_strict_mode.app_rd_data_reg[430]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \^not_strict_mode.app_rd_data_reg[502]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \^not_strict_mode.app_rd_data_reg[494]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \^not_strict_mode.app_rd_data_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^not_strict_mode.app_rd_data_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \^not_strict_mode.app_rd_data_reg[117]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \^not_strict_mode.app_rd_data_reg[109]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \^not_strict_mode.app_rd_data_reg[181]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \^not_strict_mode.app_rd_data_reg[173]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \^not_strict_mode.app_rd_data_reg[245]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \^not_strict_mode.app_rd_data_reg[237]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \^not_strict_mode.app_rd_data_reg[309]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \^not_strict_mode.app_rd_data_reg[301]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \^not_strict_mode.app_rd_data_reg[373]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \^not_strict_mode.app_rd_data_reg[365]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \^not_strict_mode.app_rd_data_reg[437]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \^not_strict_mode.app_rd_data_reg[429]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \^not_strict_mode.app_rd_data_reg[501]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \^not_strict_mode.app_rd_data_reg[493]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \^not_strict_mode.app_rd_data_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^not_strict_mode.app_rd_data_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \^not_strict_mode.app_rd_data_reg[116]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \^not_strict_mode.app_rd_data_reg[108]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \^not_strict_mode.app_rd_data_reg[180]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \^not_strict_mode.app_rd_data_reg[172]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \^not_strict_mode.app_rd_data_reg[244]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \^not_strict_mode.app_rd_data_reg[236]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \^not_strict_mode.app_rd_data_reg[308]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \^not_strict_mode.app_rd_data_reg[300]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \^not_strict_mode.app_rd_data_reg[372]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \^not_strict_mode.app_rd_data_reg[364]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \^not_strict_mode.app_rd_data_reg[436]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \^not_strict_mode.app_rd_data_reg[428]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \^not_strict_mode.app_rd_data_reg[500]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \^not_strict_mode.app_rd_data_reg[492]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \^not_strict_mode.app_rd_data_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \^not_strict_mode.app_rd_data_reg[107]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \^not_strict_mode.app_rd_data_reg[171]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \^not_strict_mode.app_rd_data_reg[235]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \^not_strict_mode.app_rd_data_reg[299]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \^not_strict_mode.app_rd_data_reg[363]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \^not_strict_mode.app_rd_data_reg[427]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \^not_strict_mode.app_rd_data_reg[491]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \^not_strict_mode.app_rd_data_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^not_strict_mode.app_rd_data_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \^not_strict_mode.app_rd_data_reg[106]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \^not_strict_mode.app_rd_data_reg[115]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \^not_strict_mode.app_rd_data_reg[170]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \^not_strict_mode.app_rd_data_reg[179]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \^not_strict_mode.app_rd_data_reg[234]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \^not_strict_mode.app_rd_data_reg[243]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \^not_strict_mode.app_rd_data_reg[298]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \^not_strict_mode.app_rd_data_reg[307]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \^not_strict_mode.app_rd_data_reg[362]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \^not_strict_mode.app_rd_data_reg[371]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \^not_strict_mode.app_rd_data_reg[426]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \^not_strict_mode.app_rd_data_reg[435]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \^not_strict_mode.app_rd_data_reg[490]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \^not_strict_mode.app_rd_data_reg[499]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \^not_strict_mode.app_rd_data_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^not_strict_mode.app_rd_data_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \^not_strict_mode.app_rd_data_reg[105]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \^not_strict_mode.app_rd_data_reg[114]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \^not_strict_mode.app_rd_data_reg[169]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \^not_strict_mode.app_rd_data_reg[178]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \^not_strict_mode.app_rd_data_reg[233]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \^not_strict_mode.app_rd_data_reg[242]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \^not_strict_mode.app_rd_data_reg[297]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \^not_strict_mode.app_rd_data_reg[306]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \^not_strict_mode.app_rd_data_reg[361]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \^not_strict_mode.app_rd_data_reg[370]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \^not_strict_mode.app_rd_data_reg[425]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \^not_strict_mode.app_rd_data_reg[434]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \^not_strict_mode.app_rd_data_reg[489]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \^not_strict_mode.app_rd_data_reg[498]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^not_strict_mode.app_rd_data_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \^not_strict_mode.app_rd_data_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^not_strict_mode.app_rd_data_reg[104]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1\ => \^not_strict_mode.app_rd_data_reg[113]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ => \^not_strict_mode.app_rd_data_reg[168]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^not_strict_mode.app_rd_data_reg[177]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ => \^not_strict_mode.app_rd_data_reg[232]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^not_strict_mode.app_rd_data_reg[241]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ => \^not_strict_mode.app_rd_data_reg[296]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^not_strict_mode.app_rd_data_reg[305]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ => \^not_strict_mode.app_rd_data_reg[360]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^not_strict_mode.app_rd_data_reg[369]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ => \^not_strict_mode.app_rd_data_reg[424]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^not_strict_mode.app_rd_data_reg[433]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ => \^not_strict_mode.app_rd_data_reg[488]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^not_strict_mode.app_rd_data_reg[497]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \^not_strict_mode.app_rd_data_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \^not_strict_mode.app_rd_data_reg[112]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \^not_strict_mode.app_rd_data_reg[176]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \^not_strict_mode.app_rd_data_reg[240]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \^not_strict_mode.app_rd_data_reg[304]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \^not_strict_mode.app_rd_data_reg[368]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \^not_strict_mode.app_rd_data_reg[432]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \^not_strict_mode.app_rd_data_reg[496]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \^not_strict_mode.app_rd_data_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ => \^not_strict_mode.app_rd_data_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \^not_strict_mode.app_rd_data_reg[119]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ => \^not_strict_mode.app_rd_data_reg[111]\,
      freq_refclk => freq_refclk,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      if_empty_r(0) => if_empty_r(3),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__8\ => \init_calib_complete_reg_rep__8\,
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0),
      mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0),
      mem_dqs_in(0) => mem_dqs_in(0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[3]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[120]\ => \not_strict_mode.app_rd_data_reg[120]\,
      \not_strict_mode.app_rd_data_reg[121]\ => \not_strict_mode.app_rd_data_reg[121]\,
      \not_strict_mode.app_rd_data_reg[122]\ => \not_strict_mode.app_rd_data_reg[122]\,
      \not_strict_mode.app_rd_data_reg[123]\ => \not_strict_mode.app_rd_data_reg[123]\,
      \not_strict_mode.app_rd_data_reg[124]\ => \not_strict_mode.app_rd_data_reg[124]\,
      \not_strict_mode.app_rd_data_reg[125]\ => \not_strict_mode.app_rd_data_reg[125]\,
      \not_strict_mode.app_rd_data_reg[126]\ => \not_strict_mode.app_rd_data_reg[126]\,
      \not_strict_mode.app_rd_data_reg[127]\ => \not_strict_mode.app_rd_data_reg[127]\,
      \not_strict_mode.app_rd_data_reg[184]\ => \not_strict_mode.app_rd_data_reg[184]\,
      \not_strict_mode.app_rd_data_reg[185]\ => \not_strict_mode.app_rd_data_reg[185]\,
      \not_strict_mode.app_rd_data_reg[186]\ => \not_strict_mode.app_rd_data_reg[186]\,
      \not_strict_mode.app_rd_data_reg[187]\ => \not_strict_mode.app_rd_data_reg[187]\,
      \not_strict_mode.app_rd_data_reg[188]\ => \not_strict_mode.app_rd_data_reg[188]\,
      \not_strict_mode.app_rd_data_reg[189]\ => \not_strict_mode.app_rd_data_reg[189]\,
      \not_strict_mode.app_rd_data_reg[190]\ => \not_strict_mode.app_rd_data_reg[190]\,
      \not_strict_mode.app_rd_data_reg[191]\ => \not_strict_mode.app_rd_data_reg[191]\,
      \not_strict_mode.app_rd_data_reg[248]\ => \not_strict_mode.app_rd_data_reg[248]\,
      \not_strict_mode.app_rd_data_reg[249]\ => \not_strict_mode.app_rd_data_reg[249]\,
      \not_strict_mode.app_rd_data_reg[250]\ => \not_strict_mode.app_rd_data_reg[250]\,
      \not_strict_mode.app_rd_data_reg[251]\ => \not_strict_mode.app_rd_data_reg[251]\,
      \not_strict_mode.app_rd_data_reg[252]\ => \not_strict_mode.app_rd_data_reg[252]\,
      \not_strict_mode.app_rd_data_reg[253]\ => \not_strict_mode.app_rd_data_reg[253]\,
      \not_strict_mode.app_rd_data_reg[254]\ => \not_strict_mode.app_rd_data_reg[254]\,
      \not_strict_mode.app_rd_data_reg[255]\ => \not_strict_mode.app_rd_data_reg[255]\,
      \not_strict_mode.app_rd_data_reg[312]\ => \not_strict_mode.app_rd_data_reg[312]\,
      \not_strict_mode.app_rd_data_reg[313]\ => \not_strict_mode.app_rd_data_reg[313]\,
      \not_strict_mode.app_rd_data_reg[314]\ => \not_strict_mode.app_rd_data_reg[314]\,
      \not_strict_mode.app_rd_data_reg[315]\ => \not_strict_mode.app_rd_data_reg[315]\,
      \not_strict_mode.app_rd_data_reg[316]\ => \not_strict_mode.app_rd_data_reg[316]\,
      \not_strict_mode.app_rd_data_reg[317]\ => \not_strict_mode.app_rd_data_reg[317]\,
      \not_strict_mode.app_rd_data_reg[318]\ => \not_strict_mode.app_rd_data_reg[318]\,
      \not_strict_mode.app_rd_data_reg[319]\ => \not_strict_mode.app_rd_data_reg[319]\,
      \not_strict_mode.app_rd_data_reg[376]\ => \not_strict_mode.app_rd_data_reg[376]\,
      \not_strict_mode.app_rd_data_reg[377]\ => \not_strict_mode.app_rd_data_reg[377]\,
      \not_strict_mode.app_rd_data_reg[378]\ => \not_strict_mode.app_rd_data_reg[378]\,
      \not_strict_mode.app_rd_data_reg[379]\ => \not_strict_mode.app_rd_data_reg[379]\,
      \not_strict_mode.app_rd_data_reg[380]\ => \not_strict_mode.app_rd_data_reg[380]\,
      \not_strict_mode.app_rd_data_reg[381]\ => \not_strict_mode.app_rd_data_reg[381]\,
      \not_strict_mode.app_rd_data_reg[382]\ => \not_strict_mode.app_rd_data_reg[382]\,
      \not_strict_mode.app_rd_data_reg[383]\ => \not_strict_mode.app_rd_data_reg[383]\,
      \not_strict_mode.app_rd_data_reg[440]\ => \not_strict_mode.app_rd_data_reg[440]\,
      \not_strict_mode.app_rd_data_reg[441]\ => \not_strict_mode.app_rd_data_reg[441]\,
      \not_strict_mode.app_rd_data_reg[442]\ => \not_strict_mode.app_rd_data_reg[442]\,
      \not_strict_mode.app_rd_data_reg[443]\ => \not_strict_mode.app_rd_data_reg[443]\,
      \not_strict_mode.app_rd_data_reg[444]\ => \not_strict_mode.app_rd_data_reg[444]\,
      \not_strict_mode.app_rd_data_reg[445]\ => \not_strict_mode.app_rd_data_reg[445]\,
      \not_strict_mode.app_rd_data_reg[446]\ => \not_strict_mode.app_rd_data_reg[446]\,
      \not_strict_mode.app_rd_data_reg[447]\ => \not_strict_mode.app_rd_data_reg[447]\,
      \not_strict_mode.app_rd_data_reg[504]\ => \not_strict_mode.app_rd_data_reg[504]\,
      \not_strict_mode.app_rd_data_reg[505]\ => \not_strict_mode.app_rd_data_reg[505]\,
      \not_strict_mode.app_rd_data_reg[506]\ => \not_strict_mode.app_rd_data_reg[506]\,
      \not_strict_mode.app_rd_data_reg[507]\ => \not_strict_mode.app_rd_data_reg[507]\,
      \not_strict_mode.app_rd_data_reg[508]\ => \not_strict_mode.app_rd_data_reg[508]\,
      \not_strict_mode.app_rd_data_reg[509]\ => \not_strict_mode.app_rd_data_reg[509]\,
      \not_strict_mode.app_rd_data_reg[510]\ => \not_strict_mode.app_rd_data_reg[510]\,
      \not_strict_mode.app_rd_data_reg[511]\(63 downto 56) => \not_strict_mode.app_rd_data_reg[511]\(191 downto 184),
      \not_strict_mode.app_rd_data_reg[511]\(55 downto 48) => \not_strict_mode.app_rd_data_reg[511]\(167 downto 160),
      \not_strict_mode.app_rd_data_reg[511]\(47 downto 40) => \not_strict_mode.app_rd_data_reg[511]\(143 downto 136),
      \not_strict_mode.app_rd_data_reg[511]\(39 downto 32) => \not_strict_mode.app_rd_data_reg[511]\(119 downto 112),
      \not_strict_mode.app_rd_data_reg[511]\(31 downto 24) => \not_strict_mode.app_rd_data_reg[511]\(95 downto 88),
      \not_strict_mode.app_rd_data_reg[511]\(23 downto 16) => \not_strict_mode.app_rd_data_reg[511]\(71 downto 64),
      \not_strict_mode.app_rd_data_reg[511]\(15 downto 8) => \not_strict_mode.app_rd_data_reg[511]\(47 downto 40),
      \not_strict_mode.app_rd_data_reg[511]\(7 downto 0) => \not_strict_mode.app_rd_data_reg[511]\(23 downto 16),
      \not_strict_mode.app_rd_data_reg[511]_0\ => \not_strict_mode.app_rd_data_reg[511]_0\,
      \not_strict_mode.app_rd_data_reg[56]\ => \not_strict_mode.app_rd_data_reg[56]\,
      \not_strict_mode.app_rd_data_reg[57]\ => \not_strict_mode.app_rd_data_reg[57]\,
      \not_strict_mode.app_rd_data_reg[58]\ => \not_strict_mode.app_rd_data_reg[58]\,
      \not_strict_mode.app_rd_data_reg[59]\ => \not_strict_mode.app_rd_data_reg[59]\,
      \not_strict_mode.app_rd_data_reg[60]\ => \not_strict_mode.app_rd_data_reg[60]\,
      \not_strict_mode.app_rd_data_reg[61]\ => \not_strict_mode.app_rd_data_reg[61]\,
      \not_strict_mode.app_rd_data_reg[62]\ => \not_strict_mode.app_rd_data_reg[62]\,
      \not_strict_mode.app_rd_data_reg[63]\ => \not_strict_mode.app_rd_data_reg[63]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0),
      ofifo_rst_reg0_11 => ofifo_rst_reg0_11,
      out_dqs_7 => out_dqs_7,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(9 downto 8),
      phaser_ctl_bus(1) => phaser_ctl_bus(4),
      phaser_ctl_bus(0) => phaser_ctl_bus(0),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata_mask(23),
      phy_dout(70) => mux_wrdata_mask(20),
      phy_dout(69) => mux_wrdata_mask(17),
      phy_dout(68) => mux_wrdata_mask(14),
      phy_dout(67) => mux_wrdata_mask(11),
      phy_dout(66) => mux_wrdata_mask(8),
      phy_dout(65) => mux_wrdata_mask(5),
      phy_dout(64) => mux_wrdata_mask(2),
      phy_dout(63) => mux_wrdata(148),
      phy_dout(62) => mux_wrdata(124),
      phy_dout(61) => mux_wrdata(102),
      phy_dout(60) => mux_wrdata(84),
      phy_dout(59) => mux_wrdata(66),
      phy_dout(58) => mux_wrdata(48),
      phy_dout(57) => mux_wrdata(28),
      phy_dout(56) => \write_buffer.wr_buf_out_data_reg[383]\(8),
      phy_dout(55) => mux_wrdata(149),
      phy_dout(54) => mux_wrdata(125),
      phy_dout(53) => mux_wrdata(103),
      phy_dout(52) => mux_wrdata(85),
      phy_dout(51) => mux_wrdata(67),
      phy_dout(50) => \write_buffer.wr_buf_out_data_reg[383]\(16),
      phy_dout(49) => mux_wrdata(29),
      phy_dout(48) => mux_wrdata(8),
      phy_dout(47) => mux_wrdata(150),
      phy_dout(46) => mux_wrdata(126),
      phy_dout(45) => mux_wrdata(104),
      phy_dout(44) => \write_buffer.wr_buf_out_data_reg[383]\(28),
      phy_dout(43) => \write_buffer.wr_buf_out_data_reg[383]\(22),
      phy_dout(42) => mux_wrdata(49),
      phy_dout(41) => mux_wrdata(30),
      phy_dout(40) => mux_wrdata(9),
      phy_dout(39) => mux_wrdata(151),
      phy_dout(38) => mux_wrdata(127),
      phy_dout(37) => \write_buffer.wr_buf_out_data_reg[383]\(34),
      phy_dout(36) => mux_wrdata(86),
      phy_dout(35) => mux_wrdata(68),
      phy_dout(34) => mux_wrdata(50),
      phy_dout(33) => mux_wrdata(31),
      phy_dout(32) => \write_buffer.wr_buf_out_data_reg[383]\(9),
      phy_dout(31) => mux_wrdata(152),
      phy_dout(30) => mux_wrdata(128),
      phy_dout(29) => mux_wrdata(105),
      phy_dout(28) => mux_wrdata(87),
      phy_dout(27) => mux_wrdata(69),
      phy_dout(26) => mux_wrdata(51),
      phy_dout(25) => mux_wrdata(32),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[383]\(10),
      phy_dout(23) => mux_wrdata(153),
      phy_dout(22) => mux_wrdata(129),
      phy_dout(21) => mux_wrdata(106),
      phy_dout(20) => mux_wrdata(88),
      phy_dout(19) => mux_wrdata(70),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[383]\(17),
      phy_dout(17) => mux_wrdata(33),
      phy_dout(16) => mux_wrdata(10),
      phy_dout(15) => mux_wrdata(154),
      phy_dout(14) => mux_wrdata(130),
      phy_dout(13) => mux_wrdata(107),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[383]\(29),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[383]\(23),
      phy_dout(10) => mux_wrdata(52),
      phy_dout(9) => mux_wrdata(34),
      phy_dout(8) => mux_wrdata(11),
      phy_dout(7) => mux_wrdata(155),
      phy_dout(6) => mux_wrdata(131),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[383]\(35),
      phy_dout(4) => mux_wrdata(89),
      phy_dout(3) => mux_wrdata(71),
      phy_dout(2) => mux_wrdata(53),
      phy_dout(1) => mux_wrdata(35),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[383]\(11),
      phy_if_reset => phy_if_reset,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(0),
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      \po_counter_read_val_reg[8]\(8 downto 0) => A_po_counter_read_val(8 downto 0),
      \po_stg2_wrcal_cnt_reg[1]\(1 downto 0) => \po_stg2_wrcal_cnt_reg[1]\(1 downto 0),
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg,
      ts_dqs_7 => ts_dqs_7,
      \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[505]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[505]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[506]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[506]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[507]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[507]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[509]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[509]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[510]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[510]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[511]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[511]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[575]\(27) => \write_buffer.wr_buf_out_data_reg[575]\(83),
      \write_buffer.wr_buf_out_data_reg[575]\(26) => \write_buffer.wr_buf_out_data_reg[575]\(80),
      \write_buffer.wr_buf_out_data_reg[575]\(25) => \write_buffer.wr_buf_out_data_reg[575]\(77),
      \write_buffer.wr_buf_out_data_reg[575]\(24) => \write_buffer.wr_buf_out_data_reg[575]\(74),
      \write_buffer.wr_buf_out_data_reg[575]\(23) => \write_buffer.wr_buf_out_data_reg[575]\(71),
      \write_buffer.wr_buf_out_data_reg[575]\(22) => \write_buffer.wr_buf_out_data_reg[575]\(68),
      \write_buffer.wr_buf_out_data_reg[575]\(21) => \write_buffer.wr_buf_out_data_reg[575]\(65),
      \write_buffer.wr_buf_out_data_reg[575]\(20) => \write_buffer.wr_buf_out_data_reg[575]\(62),
      \write_buffer.wr_buf_out_data_reg[575]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[575]\(59 downto 58),
      \write_buffer.wr_buf_out_data_reg[575]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[575]\(53 downto 52),
      \write_buffer.wr_buf_out_data_reg[575]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[575]\(47 downto 44),
      \write_buffer.wr_buf_out_data_reg[575]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[575]\(35 downto 34),
      \write_buffer.wr_buf_out_data_reg[575]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[575]\(29 downto 28),
      \write_buffer.wr_buf_out_data_reg[575]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[575]\(23 downto 20),
      \write_buffer.wr_buf_out_data_reg[575]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(11 downto 8)
    );
\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized0\
     port map (
      A_rst_primitives_reg => \^pi_dqs_found_lanes_r1_reg[10]\,
      B_byte_rd_en => B_byte_rd_en,
      B_rclk => B_rclk,
      CLK => CLK,
      CLKB0_12 => CLKB0_12,
      COUNTERREADVAL(5 downto 0) => B_pi_counter_read_val(5 downto 0),
      LD0_12 => LD0_12,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      Q(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2),
      \calib_sel_reg[0]\ => \calib_sel_reg[0]\,
      \calib_sel_reg[0]_0\ => \calib_sel_reg[0]_0\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_0,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      dqs_wl_po_stg2_c_incdec_reg => dqs_wl_po_stg2_c_incdec_reg,
      freq_refclk => freq_refclk,
      idelay_ce_r2_reg => idelay_ce_r2_reg,
      idelay_inc => idelay_inc,
      if_empty_r(0) => if_empty_r_1(3),
      if_empty_r_0(0) => if_empty_r(3),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      mem_dq_in(7 downto 0) => mem_dq_in(15 downto 8),
      mem_dq_out(8 downto 0) => mem_dq_out(17 downto 9),
      mem_dq_ts(8 downto 0) => mem_dq_ts(17 downto 9),
      mem_dqs_in(0) => mem_dqs_in(1),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_0\,
      \my_empty_reg[3]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(3),
      \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(0),
      \my_empty_reg[3]_0\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]_0\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[112]\ => \^not_strict_mode.app_rd_data_reg[112]\,
      \not_strict_mode.app_rd_data_reg[113]\ => \^not_strict_mode.app_rd_data_reg[113]\,
      \not_strict_mode.app_rd_data_reg[114]\ => \^not_strict_mode.app_rd_data_reg[114]\,
      \not_strict_mode.app_rd_data_reg[115]\ => \^not_strict_mode.app_rd_data_reg[115]\,
      \not_strict_mode.app_rd_data_reg[116]\ => \^not_strict_mode.app_rd_data_reg[116]\,
      \not_strict_mode.app_rd_data_reg[117]\ => \^not_strict_mode.app_rd_data_reg[117]\,
      \not_strict_mode.app_rd_data_reg[118]\ => \^not_strict_mode.app_rd_data_reg[118]\,
      \not_strict_mode.app_rd_data_reg[119]\ => \^not_strict_mode.app_rd_data_reg[119]\,
      \not_strict_mode.app_rd_data_reg[176]\ => \^not_strict_mode.app_rd_data_reg[176]\,
      \not_strict_mode.app_rd_data_reg[177]\ => \^not_strict_mode.app_rd_data_reg[177]\,
      \not_strict_mode.app_rd_data_reg[178]\ => \^not_strict_mode.app_rd_data_reg[178]\,
      \not_strict_mode.app_rd_data_reg[179]\ => \^not_strict_mode.app_rd_data_reg[179]\,
      \not_strict_mode.app_rd_data_reg[180]\ => \^not_strict_mode.app_rd_data_reg[180]\,
      \not_strict_mode.app_rd_data_reg[181]\ => \^not_strict_mode.app_rd_data_reg[181]\,
      \not_strict_mode.app_rd_data_reg[182]\ => \^not_strict_mode.app_rd_data_reg[182]\,
      \not_strict_mode.app_rd_data_reg[183]\ => \^not_strict_mode.app_rd_data_reg[183]\,
      \not_strict_mode.app_rd_data_reg[240]\ => \^not_strict_mode.app_rd_data_reg[240]\,
      \not_strict_mode.app_rd_data_reg[241]\ => \^not_strict_mode.app_rd_data_reg[241]\,
      \not_strict_mode.app_rd_data_reg[242]\ => \^not_strict_mode.app_rd_data_reg[242]\,
      \not_strict_mode.app_rd_data_reg[243]\ => \^not_strict_mode.app_rd_data_reg[243]\,
      \not_strict_mode.app_rd_data_reg[244]\ => \^not_strict_mode.app_rd_data_reg[244]\,
      \not_strict_mode.app_rd_data_reg[245]\ => \^not_strict_mode.app_rd_data_reg[245]\,
      \not_strict_mode.app_rd_data_reg[246]\ => \^not_strict_mode.app_rd_data_reg[246]\,
      \not_strict_mode.app_rd_data_reg[247]\ => \^not_strict_mode.app_rd_data_reg[247]\,
      \not_strict_mode.app_rd_data_reg[304]\ => \^not_strict_mode.app_rd_data_reg[304]\,
      \not_strict_mode.app_rd_data_reg[305]\ => \^not_strict_mode.app_rd_data_reg[305]\,
      \not_strict_mode.app_rd_data_reg[306]\ => \^not_strict_mode.app_rd_data_reg[306]\,
      \not_strict_mode.app_rd_data_reg[307]\ => \^not_strict_mode.app_rd_data_reg[307]\,
      \not_strict_mode.app_rd_data_reg[308]\ => \^not_strict_mode.app_rd_data_reg[308]\,
      \not_strict_mode.app_rd_data_reg[309]\ => \^not_strict_mode.app_rd_data_reg[309]\,
      \not_strict_mode.app_rd_data_reg[310]\ => \^not_strict_mode.app_rd_data_reg[310]\,
      \not_strict_mode.app_rd_data_reg[311]\ => \^not_strict_mode.app_rd_data_reg[311]\,
      \not_strict_mode.app_rd_data_reg[368]\ => \^not_strict_mode.app_rd_data_reg[368]\,
      \not_strict_mode.app_rd_data_reg[369]\ => \^not_strict_mode.app_rd_data_reg[369]\,
      \not_strict_mode.app_rd_data_reg[370]\ => \^not_strict_mode.app_rd_data_reg[370]\,
      \not_strict_mode.app_rd_data_reg[371]\ => \^not_strict_mode.app_rd_data_reg[371]\,
      \not_strict_mode.app_rd_data_reg[372]\ => \^not_strict_mode.app_rd_data_reg[372]\,
      \not_strict_mode.app_rd_data_reg[373]\ => \^not_strict_mode.app_rd_data_reg[373]\,
      \not_strict_mode.app_rd_data_reg[374]\ => \^not_strict_mode.app_rd_data_reg[374]\,
      \not_strict_mode.app_rd_data_reg[375]\ => \^not_strict_mode.app_rd_data_reg[375]\,
      \not_strict_mode.app_rd_data_reg[432]\ => \^not_strict_mode.app_rd_data_reg[432]\,
      \not_strict_mode.app_rd_data_reg[433]\ => \^not_strict_mode.app_rd_data_reg[433]\,
      \not_strict_mode.app_rd_data_reg[434]\ => \^not_strict_mode.app_rd_data_reg[434]\,
      \not_strict_mode.app_rd_data_reg[435]\ => \^not_strict_mode.app_rd_data_reg[435]\,
      \not_strict_mode.app_rd_data_reg[436]\ => \^not_strict_mode.app_rd_data_reg[436]\,
      \not_strict_mode.app_rd_data_reg[437]\ => \^not_strict_mode.app_rd_data_reg[437]\,
      \not_strict_mode.app_rd_data_reg[438]\ => \^not_strict_mode.app_rd_data_reg[438]\,
      \not_strict_mode.app_rd_data_reg[439]\ => \^not_strict_mode.app_rd_data_reg[439]\,
      \not_strict_mode.app_rd_data_reg[48]\ => \^not_strict_mode.app_rd_data_reg[48]\,
      \not_strict_mode.app_rd_data_reg[496]\ => \^not_strict_mode.app_rd_data_reg[496]\,
      \not_strict_mode.app_rd_data_reg[497]\ => \^not_strict_mode.app_rd_data_reg[497]\,
      \not_strict_mode.app_rd_data_reg[498]\ => \^not_strict_mode.app_rd_data_reg[498]\,
      \not_strict_mode.app_rd_data_reg[499]\ => \^not_strict_mode.app_rd_data_reg[499]\,
      \not_strict_mode.app_rd_data_reg[49]\ => \^not_strict_mode.app_rd_data_reg[49]\,
      \not_strict_mode.app_rd_data_reg[500]\ => \^not_strict_mode.app_rd_data_reg[500]\,
      \not_strict_mode.app_rd_data_reg[501]\ => \^not_strict_mode.app_rd_data_reg[501]\,
      \not_strict_mode.app_rd_data_reg[502]\ => \^not_strict_mode.app_rd_data_reg[502]\,
      \not_strict_mode.app_rd_data_reg[503]\(63 downto 56) => \not_strict_mode.app_rd_data_reg[511]\(183 downto 176),
      \not_strict_mode.app_rd_data_reg[503]\(55 downto 48) => \not_strict_mode.app_rd_data_reg[511]\(159 downto 152),
      \not_strict_mode.app_rd_data_reg[503]\(47 downto 40) => \not_strict_mode.app_rd_data_reg[511]\(135 downto 128),
      \not_strict_mode.app_rd_data_reg[503]\(39 downto 32) => \not_strict_mode.app_rd_data_reg[511]\(111 downto 104),
      \not_strict_mode.app_rd_data_reg[503]\(31 downto 24) => \not_strict_mode.app_rd_data_reg[511]\(87 downto 80),
      \not_strict_mode.app_rd_data_reg[503]\(23 downto 16) => \not_strict_mode.app_rd_data_reg[511]\(63 downto 56),
      \not_strict_mode.app_rd_data_reg[503]\(15 downto 8) => \not_strict_mode.app_rd_data_reg[511]\(39 downto 32),
      \not_strict_mode.app_rd_data_reg[503]\(7 downto 0) => \not_strict_mode.app_rd_data_reg[511]\(15 downto 8),
      \not_strict_mode.app_rd_data_reg[503]_0\ => \^not_strict_mode.app_rd_data_reg[503]\,
      \not_strict_mode.app_rd_data_reg[50]\ => \^not_strict_mode.app_rd_data_reg[50]\,
      \not_strict_mode.app_rd_data_reg[51]\ => \^not_strict_mode.app_rd_data_reg[51]\,
      \not_strict_mode.app_rd_data_reg[52]\ => \^not_strict_mode.app_rd_data_reg[52]\,
      \not_strict_mode.app_rd_data_reg[53]\ => \^not_strict_mode.app_rd_data_reg[53]\,
      \not_strict_mode.app_rd_data_reg[54]\ => \^not_strict_mode.app_rd_data_reg[54]\,
      \not_strict_mode.app_rd_data_reg[55]\ => \^not_strict_mode.app_rd_data_reg[55]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      ofifo_rst_reg0_13 => ofifo_rst_reg0_13,
      ofs_rdy_r_reg => \ddr_byte_lane_B.ddr_byte_lane_B_n_173\,
      out_dqs_6 => out_dqs_6,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(11 downto 10),
      phaser_ctl_bus(1) => phaser_ctl_bus(5),
      phaser_ctl_bus(0) => phaser_ctl_bus(1),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata(140),
      phy_dout(70) => mux_wrdata(116),
      phy_dout(69) => mux_wrdata(96),
      phy_dout(68) => mux_wrdata(78),
      phy_dout(67) => mux_wrdata(60),
      phy_dout(66) => mux_wrdata(42),
      phy_dout(65) => mux_wrdata(20),
      phy_dout(64) => \write_buffer.wr_buf_out_data_reg[383]\(4),
      phy_dout(63) => mux_wrdata(141),
      phy_dout(62) => mux_wrdata(117),
      phy_dout(61) => mux_wrdata(97),
      phy_dout(60) => mux_wrdata(79),
      phy_dout(59) => mux_wrdata(61),
      phy_dout(58) => \write_buffer.wr_buf_out_data_reg[383]\(14),
      phy_dout(57) => mux_wrdata(21),
      phy_dout(56) => mux_wrdata(4),
      phy_dout(55) => mux_wrdata(142),
      phy_dout(54) => mux_wrdata(118),
      phy_dout(53) => mux_wrdata(98),
      phy_dout(52) => \write_buffer.wr_buf_out_data_reg[383]\(26),
      phy_dout(51) => \write_buffer.wr_buf_out_data_reg[383]\(20),
      phy_dout(50) => mux_wrdata(43),
      phy_dout(49) => mux_wrdata(22),
      phy_dout(48) => mux_wrdata(5),
      phy_dout(47) => mux_wrdata(143),
      phy_dout(46) => mux_wrdata(119),
      phy_dout(45) => \write_buffer.wr_buf_out_data_reg[383]\(32),
      phy_dout(44) => mux_wrdata(80),
      phy_dout(43) => mux_wrdata(62),
      phy_dout(42) => mux_wrdata(44),
      phy_dout(41) => mux_wrdata(23),
      phy_dout(40) => \write_buffer.wr_buf_out_data_reg[383]\(5),
      phy_dout(39) => mux_wrdata_mask(22),
      phy_dout(38) => mux_wrdata_mask(19),
      phy_dout(37) => mux_wrdata_mask(16),
      phy_dout(36) => mux_wrdata_mask(13),
      phy_dout(35) => mux_wrdata_mask(10),
      phy_dout(34) => mux_wrdata_mask(7),
      phy_dout(33) => mux_wrdata_mask(4),
      phy_dout(32) => mux_wrdata_mask(1),
      phy_dout(31) => mux_wrdata(144),
      phy_dout(30) => mux_wrdata(120),
      phy_dout(29) => mux_wrdata(99),
      phy_dout(28) => mux_wrdata(81),
      phy_dout(27) => mux_wrdata(63),
      phy_dout(26) => mux_wrdata(45),
      phy_dout(25) => mux_wrdata(24),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[383]\(6),
      phy_dout(23) => mux_wrdata(145),
      phy_dout(22) => mux_wrdata(121),
      phy_dout(21) => mux_wrdata(100),
      phy_dout(20) => mux_wrdata(82),
      phy_dout(19) => mux_wrdata(64),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[383]\(15),
      phy_dout(17) => mux_wrdata(25),
      phy_dout(16) => mux_wrdata(6),
      phy_dout(15) => mux_wrdata(146),
      phy_dout(14) => mux_wrdata(122),
      phy_dout(13) => mux_wrdata(101),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[383]\(27),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[383]\(21),
      phy_dout(10) => mux_wrdata(46),
      phy_dout(9) => mux_wrdata(26),
      phy_dout(8) => mux_wrdata(7),
      phy_dout(7) => mux_wrdata(147),
      phy_dout(6) => mux_wrdata(123),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[383]\(33),
      phy_dout(4) => mux_wrdata(83),
      phy_dout(3) => mux_wrdata(65),
      phy_dout(2) => mux_wrdata(47),
      phy_dout(1) => mux_wrdata(27),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[383]\(7),
      phy_if_reset => phy_if_reset,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(1),
      pi_phase_locked_all_r1_reg => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      \pi_rst_stg1_cal_reg[2]\ => \pi_rst_stg1_cal_reg[2]\,
      pi_stg2_load_reg => pi_stg2_load_reg,
      \pi_stg2_reg_l_reg[5]\(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0),
      \po_counter_read_val_reg[8]\(8 downto 0) => B_po_counter_read_val(8 downto 0),
      \rd_ptr_timing_reg[0]\ => \rd_ptr_timing_reg[0]\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_0,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_0,
      ts_dqs_6 => ts_dqs_6,
      \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[497]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[497]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[498]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[498]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[499]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[499]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[501]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[501]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[502]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[502]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[503]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[503]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[574]\(27) => \write_buffer.wr_buf_out_data_reg[575]\(82),
      \write_buffer.wr_buf_out_data_reg[574]\(26) => \write_buffer.wr_buf_out_data_reg[575]\(79),
      \write_buffer.wr_buf_out_data_reg[574]\(25) => \write_buffer.wr_buf_out_data_reg[575]\(76),
      \write_buffer.wr_buf_out_data_reg[574]\(24) => \write_buffer.wr_buf_out_data_reg[575]\(73),
      \write_buffer.wr_buf_out_data_reg[574]\(23) => \write_buffer.wr_buf_out_data_reg[575]\(70),
      \write_buffer.wr_buf_out_data_reg[574]\(22) => \write_buffer.wr_buf_out_data_reg[575]\(67),
      \write_buffer.wr_buf_out_data_reg[574]\(21) => \write_buffer.wr_buf_out_data_reg[575]\(64),
      \write_buffer.wr_buf_out_data_reg[574]\(20) => \write_buffer.wr_buf_out_data_reg[575]\(61),
      \write_buffer.wr_buf_out_data_reg[574]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[575]\(57 downto 56),
      \write_buffer.wr_buf_out_data_reg[574]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[575]\(51 downto 50),
      \write_buffer.wr_buf_out_data_reg[574]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[575]\(43 downto 40),
      \write_buffer.wr_buf_out_data_reg[574]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[575]\(33 downto 32),
      \write_buffer.wr_buf_out_data_reg[574]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[575]\(27 downto 26),
      \write_buffer.wr_buf_out_data_reg[574]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[575]\(19 downto 16),
      \write_buffer.wr_buf_out_data_reg[574]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(7 downto 4)
    );
\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_byte_lane__parameterized1\
     port map (
      A_rst_primitives_reg => \^pi_dqs_found_lanes_r1_reg[10]\,
      A_rst_primitives_reg_0 => A_rst_primitives_reg_0,
      A_rst_primitives_reg_1 => \ddr_byte_lane_A.ddr_byte_lane_A_n_22\,
      A_rst_primitives_reg_2 => \ddr_byte_lane_B.ddr_byte_lane_B_n_22\,
      A_rst_primitives_reg_3 => A_rst_primitives_reg_1,
      CLK => CLK,
      CLKB0_13 => CLKB0_13,
      COUNTERREADVAL(5 downto 0) => C_pi_counter_read_val(5 downto 0),
      C_byte_rd_en => C_byte_rd_en,
      LD0_14 => LD0_14,
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_6\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_7\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_8\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_9\,
      \calib_sel_reg[1]_3\(5 downto 0) => \calib_sel_reg[1]_10\(5 downto 0),
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_11\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_12\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_1,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\ => \^not_strict_mode.app_rd_data_reg[183]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\ => \^not_strict_mode.app_rd_data_reg[247]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\ => \^not_strict_mode.app_rd_data_reg[311]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\ => \^not_strict_mode.app_rd_data_reg[375]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\ => \^not_strict_mode.app_rd_data_reg[439]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\ => \^not_strict_mode.app_rd_data_reg[503]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^not_strict_mode.app_rd_data_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2\ => \^not_strict_mode.app_rd_data_reg[118]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2\ => \^not_strict_mode.app_rd_data_reg[182]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2\ => \^not_strict_mode.app_rd_data_reg[246]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2\ => \^not_strict_mode.app_rd_data_reg[310]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2\ => \^not_strict_mode.app_rd_data_reg[374]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2\ => \^not_strict_mode.app_rd_data_reg[438]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2\ => \^not_strict_mode.app_rd_data_reg[502]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^not_strict_mode.app_rd_data_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\ => \^not_strict_mode.app_rd_data_reg[117]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\ => \^not_strict_mode.app_rd_data_reg[181]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\ => \^not_strict_mode.app_rd_data_reg[245]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\ => \^not_strict_mode.app_rd_data_reg[309]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\ => \^not_strict_mode.app_rd_data_reg[373]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\ => \^not_strict_mode.app_rd_data_reg[437]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\ => \^not_strict_mode.app_rd_data_reg[501]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^not_strict_mode.app_rd_data_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2\ => \^not_strict_mode.app_rd_data_reg[116]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2\ => \^not_strict_mode.app_rd_data_reg[180]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2\ => \^not_strict_mode.app_rd_data_reg[244]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2\ => \^not_strict_mode.app_rd_data_reg[308]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2\ => \^not_strict_mode.app_rd_data_reg[372]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2\ => \^not_strict_mode.app_rd_data_reg[436]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2\ => \^not_strict_mode.app_rd_data_reg[500]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^not_strict_mode.app_rd_data_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\ => \^not_strict_mode.app_rd_data_reg[115]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\ => \^not_strict_mode.app_rd_data_reg[179]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\ => \^not_strict_mode.app_rd_data_reg[243]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\ => \^not_strict_mode.app_rd_data_reg[307]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\ => \^not_strict_mode.app_rd_data_reg[371]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\ => \^not_strict_mode.app_rd_data_reg[435]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\ => \^not_strict_mode.app_rd_data_reg[499]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^not_strict_mode.app_rd_data_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2\ => \^not_strict_mode.app_rd_data_reg[114]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2\ => \^not_strict_mode.app_rd_data_reg[178]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2\ => \^not_strict_mode.app_rd_data_reg[242]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2\ => \^not_strict_mode.app_rd_data_reg[306]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2\ => \^not_strict_mode.app_rd_data_reg[370]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2\ => \^not_strict_mode.app_rd_data_reg[434]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2\ => \^not_strict_mode.app_rd_data_reg[498]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^not_strict_mode.app_rd_data_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ => \^not_strict_mode.app_rd_data_reg[113]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ => \^not_strict_mode.app_rd_data_reg[177]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ => \^not_strict_mode.app_rd_data_reg[241]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ => \^not_strict_mode.app_rd_data_reg[305]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ => \^not_strict_mode.app_rd_data_reg[369]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ => \^not_strict_mode.app_rd_data_reg[433]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ => \^not_strict_mode.app_rd_data_reg[497]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \^not_strict_mode.app_rd_data_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ => \^not_strict_mode.app_rd_data_reg[112]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ => \^not_strict_mode.app_rd_data_reg[176]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ => \^not_strict_mode.app_rd_data_reg[240]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ => \^not_strict_mode.app_rd_data_reg[304]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ => \^not_strict_mode.app_rd_data_reg[368]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ => \^not_strict_mode.app_rd_data_reg[432]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ => \^not_strict_mode.app_rd_data_reg[496]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ => \^not_strict_mode.app_rd_data_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\ => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\ => \^not_strict_mode.app_rd_data_reg[119]\,
      \entry_cnt_reg[2]\ => \ddr_byte_lane_B.ddr_byte_lane_B_n_173\,
      \entry_cnt_reg[2]_0\ => \entry_cnt_reg[2]\,
      \entry_cnt_reg[2]_1\ => \entry_cnt_reg[2]_0\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_inc => idelay_inc,
      if_empty_or_v(0) => if_empty_or_v(0),
      if_empty_r(0) => if_empty_r(3),
      if_empty_r_0(0) => if_empty_r_1(3),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      mem_dq_in(7 downto 0) => mem_dq_in(23 downto 16),
      mem_dq_out(8 downto 0) => mem_dq_out(26 downto 18),
      mem_dq_ts(8 downto 0) => mem_dq_ts(26 downto 18),
      mem_dqs_in(0) => mem_dqs_in(2),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]_1\,
      \my_empty_reg[3]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3),
      \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0),
      \my_empty_reg[3]_0\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(3),
      \my_empty_reg[3]_0\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(0),
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]_1\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[104]\ => \^not_strict_mode.app_rd_data_reg[104]\,
      \not_strict_mode.app_rd_data_reg[105]\ => \^not_strict_mode.app_rd_data_reg[105]\,
      \not_strict_mode.app_rd_data_reg[106]\ => \^not_strict_mode.app_rd_data_reg[106]\,
      \not_strict_mode.app_rd_data_reg[107]\ => \^not_strict_mode.app_rd_data_reg[107]\,
      \not_strict_mode.app_rd_data_reg[108]\ => \^not_strict_mode.app_rd_data_reg[108]\,
      \not_strict_mode.app_rd_data_reg[109]\ => \^not_strict_mode.app_rd_data_reg[109]\,
      \not_strict_mode.app_rd_data_reg[110]\ => \^not_strict_mode.app_rd_data_reg[110]\,
      \not_strict_mode.app_rd_data_reg[111]\ => \^not_strict_mode.app_rd_data_reg[111]\,
      \not_strict_mode.app_rd_data_reg[168]\ => \^not_strict_mode.app_rd_data_reg[168]\,
      \not_strict_mode.app_rd_data_reg[169]\ => \^not_strict_mode.app_rd_data_reg[169]\,
      \not_strict_mode.app_rd_data_reg[170]\ => \^not_strict_mode.app_rd_data_reg[170]\,
      \not_strict_mode.app_rd_data_reg[171]\ => \^not_strict_mode.app_rd_data_reg[171]\,
      \not_strict_mode.app_rd_data_reg[172]\ => \^not_strict_mode.app_rd_data_reg[172]\,
      \not_strict_mode.app_rd_data_reg[173]\ => \^not_strict_mode.app_rd_data_reg[173]\,
      \not_strict_mode.app_rd_data_reg[174]\ => \^not_strict_mode.app_rd_data_reg[174]\,
      \not_strict_mode.app_rd_data_reg[175]\ => \^not_strict_mode.app_rd_data_reg[175]\,
      \not_strict_mode.app_rd_data_reg[232]\ => \^not_strict_mode.app_rd_data_reg[232]\,
      \not_strict_mode.app_rd_data_reg[233]\ => \^not_strict_mode.app_rd_data_reg[233]\,
      \not_strict_mode.app_rd_data_reg[234]\ => \^not_strict_mode.app_rd_data_reg[234]\,
      \not_strict_mode.app_rd_data_reg[235]\ => \^not_strict_mode.app_rd_data_reg[235]\,
      \not_strict_mode.app_rd_data_reg[236]\ => \^not_strict_mode.app_rd_data_reg[236]\,
      \not_strict_mode.app_rd_data_reg[237]\ => \^not_strict_mode.app_rd_data_reg[237]\,
      \not_strict_mode.app_rd_data_reg[238]\ => \^not_strict_mode.app_rd_data_reg[238]\,
      \not_strict_mode.app_rd_data_reg[239]\ => \^not_strict_mode.app_rd_data_reg[239]\,
      \not_strict_mode.app_rd_data_reg[296]\ => \^not_strict_mode.app_rd_data_reg[296]\,
      \not_strict_mode.app_rd_data_reg[297]\ => \^not_strict_mode.app_rd_data_reg[297]\,
      \not_strict_mode.app_rd_data_reg[298]\ => \^not_strict_mode.app_rd_data_reg[298]\,
      \not_strict_mode.app_rd_data_reg[299]\ => \^not_strict_mode.app_rd_data_reg[299]\,
      \not_strict_mode.app_rd_data_reg[300]\ => \^not_strict_mode.app_rd_data_reg[300]\,
      \not_strict_mode.app_rd_data_reg[301]\ => \^not_strict_mode.app_rd_data_reg[301]\,
      \not_strict_mode.app_rd_data_reg[302]\ => \^not_strict_mode.app_rd_data_reg[302]\,
      \not_strict_mode.app_rd_data_reg[303]\ => \^not_strict_mode.app_rd_data_reg[303]\,
      \not_strict_mode.app_rd_data_reg[360]\ => \^not_strict_mode.app_rd_data_reg[360]\,
      \not_strict_mode.app_rd_data_reg[361]\ => \^not_strict_mode.app_rd_data_reg[361]\,
      \not_strict_mode.app_rd_data_reg[362]\ => \^not_strict_mode.app_rd_data_reg[362]\,
      \not_strict_mode.app_rd_data_reg[363]\ => \^not_strict_mode.app_rd_data_reg[363]\,
      \not_strict_mode.app_rd_data_reg[364]\ => \^not_strict_mode.app_rd_data_reg[364]\,
      \not_strict_mode.app_rd_data_reg[365]\ => \^not_strict_mode.app_rd_data_reg[365]\,
      \not_strict_mode.app_rd_data_reg[366]\ => \^not_strict_mode.app_rd_data_reg[366]\,
      \not_strict_mode.app_rd_data_reg[367]\ => \^not_strict_mode.app_rd_data_reg[367]\,
      \not_strict_mode.app_rd_data_reg[40]\ => \^not_strict_mode.app_rd_data_reg[40]\,
      \not_strict_mode.app_rd_data_reg[41]\ => \^not_strict_mode.app_rd_data_reg[41]\,
      \not_strict_mode.app_rd_data_reg[424]\ => \^not_strict_mode.app_rd_data_reg[424]\,
      \not_strict_mode.app_rd_data_reg[425]\ => \^not_strict_mode.app_rd_data_reg[425]\,
      \not_strict_mode.app_rd_data_reg[426]\ => \^not_strict_mode.app_rd_data_reg[426]\,
      \not_strict_mode.app_rd_data_reg[427]\ => \^not_strict_mode.app_rd_data_reg[427]\,
      \not_strict_mode.app_rd_data_reg[428]\ => \^not_strict_mode.app_rd_data_reg[428]\,
      \not_strict_mode.app_rd_data_reg[429]\ => \^not_strict_mode.app_rd_data_reg[429]\,
      \not_strict_mode.app_rd_data_reg[42]\ => \^not_strict_mode.app_rd_data_reg[42]\,
      \not_strict_mode.app_rd_data_reg[430]\ => \^not_strict_mode.app_rd_data_reg[430]\,
      \not_strict_mode.app_rd_data_reg[431]\ => \^not_strict_mode.app_rd_data_reg[431]\,
      \not_strict_mode.app_rd_data_reg[43]\ => \^not_strict_mode.app_rd_data_reg[43]\,
      \not_strict_mode.app_rd_data_reg[44]\ => \^not_strict_mode.app_rd_data_reg[44]\,
      \not_strict_mode.app_rd_data_reg[45]\ => \^not_strict_mode.app_rd_data_reg[45]\,
      \not_strict_mode.app_rd_data_reg[46]\ => \^not_strict_mode.app_rd_data_reg[46]\,
      \not_strict_mode.app_rd_data_reg[47]\ => \^not_strict_mode.app_rd_data_reg[47]\,
      \not_strict_mode.app_rd_data_reg[488]\ => \^not_strict_mode.app_rd_data_reg[488]\,
      \not_strict_mode.app_rd_data_reg[489]\ => \^not_strict_mode.app_rd_data_reg[489]\,
      \not_strict_mode.app_rd_data_reg[490]\ => \^not_strict_mode.app_rd_data_reg[490]\,
      \not_strict_mode.app_rd_data_reg[491]\ => \^not_strict_mode.app_rd_data_reg[491]\,
      \not_strict_mode.app_rd_data_reg[492]\ => \^not_strict_mode.app_rd_data_reg[492]\,
      \not_strict_mode.app_rd_data_reg[493]\ => \^not_strict_mode.app_rd_data_reg[493]\,
      \not_strict_mode.app_rd_data_reg[494]\ => \^not_strict_mode.app_rd_data_reg[494]\,
      \not_strict_mode.app_rd_data_reg[495]\ => \^not_strict_mode.app_rd_data_reg[495]\,
      \not_strict_mode.app_rd_data_reg[495]_0\(63 downto 56) => \not_strict_mode.app_rd_data_reg[511]\(175 downto 168),
      \not_strict_mode.app_rd_data_reg[495]_0\(55 downto 48) => \not_strict_mode.app_rd_data_reg[511]\(151 downto 144),
      \not_strict_mode.app_rd_data_reg[495]_0\(47 downto 40) => \not_strict_mode.app_rd_data_reg[511]\(127 downto 120),
      \not_strict_mode.app_rd_data_reg[495]_0\(39 downto 32) => \not_strict_mode.app_rd_data_reg[511]\(103 downto 96),
      \not_strict_mode.app_rd_data_reg[495]_0\(31 downto 24) => \not_strict_mode.app_rd_data_reg[511]\(79 downto 72),
      \not_strict_mode.app_rd_data_reg[495]_0\(23 downto 16) => \not_strict_mode.app_rd_data_reg[511]\(55 downto 48),
      \not_strict_mode.app_rd_data_reg[495]_0\(15 downto 8) => \not_strict_mode.app_rd_data_reg[511]\(31 downto 24),
      \not_strict_mode.app_rd_data_reg[495]_0\(7 downto 0) => \not_strict_mode.app_rd_data_reg[511]\(7 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      ofifo_rst_reg0_15 => ofifo_rst_reg0_15,
      out_dqs_5 => out_dqs_5,
      phaser_ctl_bus(3 downto 2) => phaser_ctl_bus(13 downto 12),
      phaser_ctl_bus(1) => phaser_ctl_bus(6),
      phaser_ctl_bus(0) => phaser_ctl_bus(2),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata_mask(21),
      phy_dout(70) => mux_wrdata_mask(18),
      phy_dout(69) => mux_wrdata_mask(15),
      phy_dout(68) => mux_wrdata_mask(12),
      phy_dout(67) => mux_wrdata_mask(9),
      phy_dout(66) => mux_wrdata_mask(6),
      phy_dout(65) => mux_wrdata_mask(3),
      phy_dout(64) => mux_wrdata_mask(0),
      phy_dout(63) => mux_wrdata(132),
      phy_dout(62) => mux_wrdata(108),
      phy_dout(61) => mux_wrdata(90),
      phy_dout(60) => mux_wrdata(72),
      phy_dout(59) => mux_wrdata(54),
      phy_dout(58) => mux_wrdata(36),
      phy_dout(57) => mux_wrdata(12),
      phy_dout(56) => \write_buffer.wr_buf_out_data_reg[383]\(0),
      phy_dout(55) => mux_wrdata(133),
      phy_dout(54) => mux_wrdata(109),
      phy_dout(53) => mux_wrdata(91),
      phy_dout(52) => mux_wrdata(73),
      phy_dout(51) => mux_wrdata(55),
      phy_dout(50) => \write_buffer.wr_buf_out_data_reg[383]\(12),
      phy_dout(49) => mux_wrdata(13),
      phy_dout(48) => mux_wrdata(0),
      phy_dout(47) => mux_wrdata(134),
      phy_dout(46) => mux_wrdata(110),
      phy_dout(45) => mux_wrdata(92),
      phy_dout(44) => \write_buffer.wr_buf_out_data_reg[383]\(24),
      phy_dout(43) => \write_buffer.wr_buf_out_data_reg[383]\(18),
      phy_dout(42) => mux_wrdata(37),
      phy_dout(41) => mux_wrdata(14),
      phy_dout(40) => mux_wrdata(1),
      phy_dout(39) => mux_wrdata(135),
      phy_dout(38) => mux_wrdata(111),
      phy_dout(37) => \write_buffer.wr_buf_out_data_reg[383]\(30),
      phy_dout(36) => mux_wrdata(74),
      phy_dout(35) => mux_wrdata(56),
      phy_dout(34) => mux_wrdata(38),
      phy_dout(33) => mux_wrdata(15),
      phy_dout(32) => \write_buffer.wr_buf_out_data_reg[383]\(1),
      phy_dout(31) => mux_wrdata(136),
      phy_dout(30) => mux_wrdata(112),
      phy_dout(29) => mux_wrdata(93),
      phy_dout(28) => mux_wrdata(75),
      phy_dout(27) => mux_wrdata(57),
      phy_dout(26) => mux_wrdata(39),
      phy_dout(25) => mux_wrdata(16),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[383]\(2),
      phy_dout(23) => mux_wrdata(137),
      phy_dout(22) => mux_wrdata(113),
      phy_dout(21) => mux_wrdata(94),
      phy_dout(20) => mux_wrdata(76),
      phy_dout(19) => mux_wrdata(58),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[383]\(13),
      phy_dout(17) => mux_wrdata(17),
      phy_dout(16) => mux_wrdata(2),
      phy_dout(15) => mux_wrdata(138),
      phy_dout(14) => mux_wrdata(114),
      phy_dout(13) => mux_wrdata(95),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[383]\(25),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[383]\(19),
      phy_dout(10) => mux_wrdata(40),
      phy_dout(9) => mux_wrdata(18),
      phy_dout(8) => mux_wrdata(3),
      phy_dout(7) => mux_wrdata(139),
      phy_dout(6) => mux_wrdata(115),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[383]\(31),
      phy_dout(4) => mux_wrdata(77),
      phy_dout(3) => mux_wrdata(59),
      phy_dout(2) => mux_wrdata(41),
      phy_dout(1) => mux_wrdata(19),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[383]\(3),
      phy_if_reset => phy_if_reset,
      phy_mc_data_full => phy_mc_data_full,
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(2),
      pi_phase_locked_all_r1_reg => pi_phase_locked_all_r1_reg,
      \po_counter_read_val_reg[8]\(8 downto 0) => C_po_counter_read_val(8 downto 0),
      pre_data_a_full_v(0) => pre_data_a_full_v(0),
      \rd_mux_sel_r_reg[1]\(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      \rd_mux_sel_r_reg[1]_0\ => \rd_mux_sel_r_reg[1]_0\,
      \rd_mux_sel_r_reg[1]_1\ => \rd_mux_sel_r_reg[1]_1\,
      \rd_mux_sel_r_reg[1]_10\ => \rd_mux_sel_r_reg[1]_10\,
      \rd_mux_sel_r_reg[1]_11\ => \rd_mux_sel_r_reg[1]_11\,
      \rd_mux_sel_r_reg[1]_12\ => \rd_mux_sel_r_reg[1]_12\,
      \rd_mux_sel_r_reg[1]_13\ => \rd_mux_sel_r_reg[1]_13\,
      \rd_mux_sel_r_reg[1]_14\ => \rd_mux_sel_r_reg[1]_14\,
      \rd_mux_sel_r_reg[1]_15\ => \rd_mux_sel_r_reg[1]_15\,
      \rd_mux_sel_r_reg[1]_16\ => \rd_mux_sel_r_reg[1]_16\,
      \rd_mux_sel_r_reg[1]_17\ => \rd_mux_sel_r_reg[1]_17\,
      \rd_mux_sel_r_reg[1]_18\ => \rd_mux_sel_r_reg[1]_18\,
      \rd_mux_sel_r_reg[1]_19\ => \rd_mux_sel_r_reg[1]_19\,
      \rd_mux_sel_r_reg[1]_2\ => \rd_mux_sel_r_reg[1]_2\,
      \rd_mux_sel_r_reg[1]_20\ => \rd_mux_sel_r_reg[1]_20\,
      \rd_mux_sel_r_reg[1]_21\ => \rd_mux_sel_r_reg[1]_21\,
      \rd_mux_sel_r_reg[1]_22\ => \rd_mux_sel_r_reg[1]_22\,
      \rd_mux_sel_r_reg[1]_23\ => \rd_mux_sel_r_reg[1]_23\,
      \rd_mux_sel_r_reg[1]_24\ => \rd_mux_sel_r_reg[1]_24\,
      \rd_mux_sel_r_reg[1]_25\ => \rd_mux_sel_r_reg[1]_25\,
      \rd_mux_sel_r_reg[1]_26\ => \rd_mux_sel_r_reg[1]_26\,
      \rd_mux_sel_r_reg[1]_27\ => \rd_mux_sel_r_reg[1]_27\,
      \rd_mux_sel_r_reg[1]_28\ => \rd_mux_sel_r_reg[1]_28\,
      \rd_mux_sel_r_reg[1]_29\ => \rd_mux_sel_r_reg[1]_29\,
      \rd_mux_sel_r_reg[1]_3\ => \rd_mux_sel_r_reg[1]_3\,
      \rd_mux_sel_r_reg[1]_30\ => \rd_mux_sel_r_reg[1]_30\,
      \rd_mux_sel_r_reg[1]_31\ => \rd_mux_sel_r_reg[1]_31\,
      \rd_mux_sel_r_reg[1]_32\ => \rd_mux_sel_r_reg[1]_32\,
      \rd_mux_sel_r_reg[1]_33\ => \rd_mux_sel_r_reg[1]_33\,
      \rd_mux_sel_r_reg[1]_34\ => \rd_mux_sel_r_reg[1]_34\,
      \rd_mux_sel_r_reg[1]_35\ => \rd_mux_sel_r_reg[1]_35\,
      \rd_mux_sel_r_reg[1]_36\ => \rd_mux_sel_r_reg[1]_36\,
      \rd_mux_sel_r_reg[1]_37\ => \rd_mux_sel_r_reg[1]_37\,
      \rd_mux_sel_r_reg[1]_38\ => \rd_mux_sel_r_reg[1]_38\,
      \rd_mux_sel_r_reg[1]_39\ => \rd_mux_sel_r_reg[1]_39\,
      \rd_mux_sel_r_reg[1]_4\ => \rd_mux_sel_r_reg[1]_4\,
      \rd_mux_sel_r_reg[1]_40\ => \rd_mux_sel_r_reg[1]_40\,
      \rd_mux_sel_r_reg[1]_41\ => \rd_mux_sel_r_reg[1]_41\,
      \rd_mux_sel_r_reg[1]_42\ => \rd_mux_sel_r_reg[1]_42\,
      \rd_mux_sel_r_reg[1]_43\ => \rd_mux_sel_r_reg[1]_43\,
      \rd_mux_sel_r_reg[1]_44\ => \rd_mux_sel_r_reg[1]_44\,
      \rd_mux_sel_r_reg[1]_45\ => \rd_mux_sel_r_reg[1]_45\,
      \rd_mux_sel_r_reg[1]_46\ => \rd_mux_sel_r_reg[1]_46\,
      \rd_mux_sel_r_reg[1]_47\ => \rd_mux_sel_r_reg[1]_47\,
      \rd_mux_sel_r_reg[1]_48\ => \rd_mux_sel_r_reg[1]_48\,
      \rd_mux_sel_r_reg[1]_49\ => \rd_mux_sel_r_reg[1]_49\,
      \rd_mux_sel_r_reg[1]_5\ => \rd_mux_sel_r_reg[1]_5\,
      \rd_mux_sel_r_reg[1]_50\ => \rd_mux_sel_r_reg[1]_50\,
      \rd_mux_sel_r_reg[1]_51\ => \rd_mux_sel_r_reg[1]_51\,
      \rd_mux_sel_r_reg[1]_52\ => \rd_mux_sel_r_reg[1]_52\,
      \rd_mux_sel_r_reg[1]_53\ => \rd_mux_sel_r_reg[1]_53\,
      \rd_mux_sel_r_reg[1]_54\ => \rd_mux_sel_r_reg[1]_54\,
      \rd_mux_sel_r_reg[1]_55\ => \rd_mux_sel_r_reg[1]_55\,
      \rd_mux_sel_r_reg[1]_56\ => \rd_mux_sel_r_reg[1]_56\,
      \rd_mux_sel_r_reg[1]_57\ => \rd_mux_sel_r_reg[1]_57\,
      \rd_mux_sel_r_reg[1]_58\ => \rd_mux_sel_r_reg[1]_58\,
      \rd_mux_sel_r_reg[1]_59\ => \rd_mux_sel_r_reg[1]_59\,
      \rd_mux_sel_r_reg[1]_6\ => \rd_mux_sel_r_reg[1]_6\,
      \rd_mux_sel_r_reg[1]_60\ => \rd_mux_sel_r_reg[1]_60\,
      \rd_mux_sel_r_reg[1]_61\ => \rd_mux_sel_r_reg[1]_61\,
      \rd_mux_sel_r_reg[1]_62\ => \rd_mux_sel_r_reg[1]_62\,
      \rd_mux_sel_r_reg[1]_63\ => \rd_mux_sel_r_reg[1]_63\,
      \rd_mux_sel_r_reg[1]_7\ => \rd_mux_sel_r_reg[1]_7\,
      \rd_mux_sel_r_reg[1]_8\ => \rd_mux_sel_r_reg[1]_8\,
      \rd_mux_sel_r_reg[1]_9\ => \rd_mux_sel_r_reg[1]_9\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_ptr_timing_reg[0]\ => \rd_ptr_timing_reg[0]_0\,
      \rd_ptr_timing_reg[0]_0\ => \rd_ptr_timing_reg[0]_1\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_1,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_1,
      ts_dqs_5 => ts_dqs_5,
      \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[489]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[489]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[490]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[490]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[491]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[491]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[493]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[493]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[494]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[494]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[495]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[495]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[573]\(27) => \write_buffer.wr_buf_out_data_reg[575]\(81),
      \write_buffer.wr_buf_out_data_reg[573]\(26) => \write_buffer.wr_buf_out_data_reg[575]\(78),
      \write_buffer.wr_buf_out_data_reg[573]\(25) => \write_buffer.wr_buf_out_data_reg[575]\(75),
      \write_buffer.wr_buf_out_data_reg[573]\(24) => \write_buffer.wr_buf_out_data_reg[575]\(72),
      \write_buffer.wr_buf_out_data_reg[573]\(23) => \write_buffer.wr_buf_out_data_reg[575]\(69),
      \write_buffer.wr_buf_out_data_reg[573]\(22) => \write_buffer.wr_buf_out_data_reg[575]\(66),
      \write_buffer.wr_buf_out_data_reg[573]\(21) => \write_buffer.wr_buf_out_data_reg[575]\(63),
      \write_buffer.wr_buf_out_data_reg[573]\(20) => \write_buffer.wr_buf_out_data_reg[575]\(60),
      \write_buffer.wr_buf_out_data_reg[573]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[575]\(55 downto 54),
      \write_buffer.wr_buf_out_data_reg[573]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[575]\(49 downto 48),
      \write_buffer.wr_buf_out_data_reg[573]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[575]\(39 downto 36),
      \write_buffer.wr_buf_out_data_reg[573]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[575]\(31 downto 30),
      \write_buffer.wr_buf_out_data_reg[573]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[575]\(25 downto 24),
      \write_buffer.wr_buf_out_data_reg[573]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[575]\(15 downto 12),
      \write_buffer.wr_buf_out_data_reg[573]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(3 downto 0)
    );
mcGo_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rst_out_reg_n_0,
      Q => \mcGo_w__0\(0),
      R => '0'
    );
phaser_ref_i: unisim.vcomponents.PHASER_REF
    generic map(
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0'
    )
        port map (
      CLKIN => freq_refclk,
      LOCKED => \^ref_dll_lock_w__0\(0),
      PWRDWN => '0',
      RST => RST0
    );
phy_control_i: unisim.vcomponents.PHY_CONTROL
    generic map(
      AO_TOGGLE => 1,
      AO_WRLVL_EN => B"0000",
      BURST_MODE => "TRUE",
      CLK_RATIO => 4,
      CMD_OFFSET => 8,
      CO_DURATION => 1,
      DATA_CTL_A_N => "TRUE",
      DATA_CTL_B_N => "TRUE",
      DATA_CTL_C_N => "TRUE",
      DATA_CTL_D_N => "FALSE",
      DISABLE_SEQ_MATCH => "TRUE",
      DI_DURATION => 1,
      DO_DURATION => 1,
      EVENTS_DELAY => 18,
      FOUR_WINDOW_CLOCKS => 63,
      MULTI_REGION => "TRUE",
      PHY_COUNT_ENABLE => "FALSE",
      RD_CMD_OFFSET_0 => 10,
      RD_CMD_OFFSET_1 => 10,
      RD_CMD_OFFSET_2 => 10,
      RD_CMD_OFFSET_3 => 10,
      RD_DURATION_0 => 6,
      RD_DURATION_1 => 6,
      RD_DURATION_2 => 6,
      RD_DURATION_3 => 6,
      SYNC_MODE => "FALSE",
      WR_CMD_OFFSET_0 => 8,
      WR_CMD_OFFSET_1 => 8,
      WR_CMD_OFFSET_2 => 8,
      WR_CMD_OFFSET_3 => 8,
      WR_DURATION_0 => 7,
      WR_DURATION_1 => 7,
      WR_DURATION_2 => 7,
      WR_DURATION_3 => 7
    )
        port map (
      AUXOUTPUT(3 downto 0) => \aux_out_\(11 downto 8),
      INBURSTPENDING(3 downto 0) => phaser_ctl_bus(7 downto 4),
      INRANKA(1 downto 0) => phaser_ctl_bus(9 downto 8),
      INRANKB(1 downto 0) => phaser_ctl_bus(11 downto 10),
      INRANKC(1 downto 0) => phaser_ctl_bus(13 downto 12),
      INRANKD(1 downto 0) => phaser_ctl_bus(15 downto 14),
      MEMREFCLK => mem_refclk,
      OUTBURSTPENDING(3 downto 0) => phaser_ctl_bus(3 downto 0),
      PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0),
      PHYCLK => CLK,
      PHYCTLALMOSTFULL => \_phy_ctl_a_full_p\(2),
      PHYCTLEMPTY => phy_control_i_n_1,
      PHYCTLFULL => \_phy_ctl_full_p__0\(0),
      PHYCTLMSTREMPTY => phy_ctl_mstr_empty,
      PHYCTLREADY => p_0_in(2),
      PHYCTLWD(31 downto 25) => B"0000001",
      PHYCTLWD(24 downto 17) => PHYCTLWD(10 downto 3),
      PHYCTLWD(16 downto 3) => B"00000000000000",
      PHYCTLWD(2 downto 0) => PHYCTLWD(2 downto 0),
      PHYCTLWRENABLE => phy_ctl_wr_i2,
      PLLLOCK => pll_locked,
      READCALIBENABLE => phy_read_calib,
      REFDLLLOCK => \^ref_dll_lock_w__0\(0),
      RESET => in0,
      SYNCIN => sync_pulse,
      WRITECALIBENABLE => phy_write_calib
    );
\pi_counter_read_val[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_pi_counter_read_val(0),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_pi_counter_read_val(0),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_pi_counter_read_val(0),
      O => \pi_counter_read_val[0]_i_1_n_0\
    );
\pi_counter_read_val[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_pi_counter_read_val(1),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_pi_counter_read_val(1),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_pi_counter_read_val(1),
      O => \pi_counter_read_val[1]_i_1_n_0\
    );
\pi_counter_read_val[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_pi_counter_read_val(2),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_pi_counter_read_val(2),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_pi_counter_read_val(2),
      O => \pi_counter_read_val[2]_i_1_n_0\
    );
\pi_counter_read_val[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_pi_counter_read_val(3),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_pi_counter_read_val(3),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_pi_counter_read_val(3),
      O => \pi_counter_read_val[3]_i_1_n_0\
    );
\pi_counter_read_val[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_pi_counter_read_val(4),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_pi_counter_read_val(4),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_pi_counter_read_val(4),
      O => \pi_counter_read_val[4]_i_1_n_0\
    );
\pi_counter_read_val[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_pi_counter_read_val(5),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_pi_counter_read_val(5),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_pi_counter_read_val(5),
      O => \pi_counter_read_val[5]_i_1_n_0\
    );
\pi_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_counter_read_val[0]_i_1_n_0\,
      Q => \pi_rdval_cnt_reg[5]\(0),
      R => '0'
    );
\pi_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_counter_read_val[1]_i_1_n_0\,
      Q => \pi_rdval_cnt_reg[5]\(1),
      R => '0'
    );
\pi_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_counter_read_val[2]_i_1_n_0\,
      Q => \pi_rdval_cnt_reg[5]\(2),
      R => '0'
    );
\pi_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_counter_read_val[3]_i_1_n_0\,
      Q => \pi_rdval_cnt_reg[5]\(3),
      R => '0'
    );
\pi_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_counter_read_val[4]_i_1_n_0\,
      Q => \pi_rdval_cnt_reg[5]\(4),
      R => '0'
    );
\pi_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pi_counter_read_val[5]_i_1_n_0\,
      Q => \pi_rdval_cnt_reg[5]\(5),
      R => '0'
    );
\po_counter_read_val[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(0),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(0),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(0),
      O => \po_counter_read_val[0]_i_1_n_0\
    );
\po_counter_read_val[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(1),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(1),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(1),
      O => \po_counter_read_val[1]_i_1_n_0\
    );
\po_counter_read_val[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(2),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(2),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(2),
      O => \po_counter_read_val[2]_i_1_n_0\
    );
\po_counter_read_val[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(3),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(3),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(3),
      O => \po_counter_read_val[3]_i_1_n_0\
    );
\po_counter_read_val[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(4),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(4),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(4),
      O => \po_counter_read_val[4]_i_1_n_0\
    );
\po_counter_read_val[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(5),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(5),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(5),
      O => \po_counter_read_val[5]_i_1_n_0\
    );
\po_counter_read_val[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(6),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(6),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(6),
      O => \po_counter_read_val[6]_i_1_n_0\
    );
\po_counter_read_val[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(7),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(7),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(7),
      O => \po_counter_read_val[7]_i_1_n_0\
    );
\po_counter_read_val[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => B_po_counter_read_val(8),
      I1 => \calib_sel_reg[1]_13\(0),
      I2 => C_po_counter_read_val(8),
      I3 => \calib_sel_reg[1]_13\(1),
      I4 => A_po_counter_read_val(8),
      O => \po_counter_read_val[8]_i_1_n_0\
    );
\po_counter_read_val_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[0]_i_1_n_0\,
      Q => Q(0),
      R => '0'
    );
\po_counter_read_val_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[1]_i_1_n_0\,
      Q => Q(1),
      R => '0'
    );
\po_counter_read_val_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[2]_i_1_n_0\,
      Q => Q(2),
      R => '0'
    );
\po_counter_read_val_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[3]_i_1_n_0\,
      Q => Q(3),
      R => '0'
    );
\po_counter_read_val_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[4]_i_1_n_0\,
      Q => Q(4),
      R => '0'
    );
\po_counter_read_val_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[5]_i_1_n_0\,
      Q => Q(5),
      R => '0'
    );
\po_counter_read_val_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[6]_i_1_n_0\,
      Q => Q(6),
      R => '0'
    );
\po_counter_read_val_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[7]_i_1_n_0\,
      Q => Q(7),
      R => '0'
    );
\po_counter_read_val_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \po_counter_read_val[8]_i_1_n_0\,
      Q => Q(8),
      R => '0'
    );
\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => \rclk_delay_reg[10]_srl11_i_1__1_n_0\,
      Q => \rclk_delay_reg[10]_srl11_n_0\
    );
\rclk_delay_reg[10]_srl11_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst_primitives,
      O => \rclk_delay_reg[10]_srl11_i_1__1_n_0\
    );
\rclk_delay_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rclk_delay_reg[10]_srl11_n_0\,
      Q => rclk_delay_11,
      R => '0'
    );
\rst_out_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rclk_delay_11,
      I1 => rst_out_reg_n_0,
      O => \rst_out_i_1__1_n_0\
    );
rst_out_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => SR(0),
      D => \rst_out_i_1__1_n_0\,
      Q => rst_out_reg_n_0
    );
\rst_primitives_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in(2),
      O => p_0_in_0
    );
rst_primitives_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in_0,
      Q => rst_primitives,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_rank_mach is
  port (
    \inhbt_act_faw.act_delayed\ : out STD_LOGIC;
    maint_prescaler_tick_r : out STD_LOGIC;
    \maintenance_request.upd_last_master_r\ : out STD_LOGIC;
    maint_req_r : out STD_LOGIC;
    maint_sre_r : out STD_LOGIC;
    \periodic_read_request.upd_last_master_r\ : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : out STD_LOGIC;
    inhbt_act_faw_r : out STD_LOGIC;
    maint_zq_r : out STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r\ : out STD_LOGIC;
    maint_srx_r : out STD_LOGIC;
    \sr_cntrl.sre_request_logic.sre_request_r\ : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r\ : out STD_LOGIC;
    periodic_rd_r : out STD_LOGIC;
    app_ref_r : out STD_LOGIC;
    app_zq_r : out STD_LOGIC;
    \periodic_read_request.periodic_rd_r_cnt\ : out STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r\ : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    maint_ref_zq_wip : out STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \periodic_rd_generation.periodic_rd_cntr1_r\ : out STD_LOGIC;
    \refresh_generation.refresh_bank_r\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \refresh_timer.refresh_timer_r_reg[5]\ : out STD_LOGIC;
    \refresh_timer.refresh_timer_r_reg[4]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[0]\ : out STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \last_master_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \periodic_rd_generation.periodic_rd_request_r_reg\ : out STD_LOGIC;
    \inhbt_act_faw.inhbt_act_faw_r_reg\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \wtr_timer.wtr_cnt_r_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    act_this_rank : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : in STD_LOGIC;
    \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \maint_prescaler.maint_prescaler_r1\ : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg_0 : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]\ : in STD_LOGIC;
    app_zq_r_reg : in STD_LOGIC;
    insert_maint_r1_lcl_reg : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_request_r_reg_0\ : in STD_LOGIC;
    \maintenance_request.maint_sre_r_lcl_reg_0\ : in STD_LOGIC;
    \refresh_generation.refresh_bank_r_reg[0]_0\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[1]\ : in STD_LOGIC;
    \periodic_rd_generation.periodic_rd_timer_r_reg[1]_0\ : in STD_LOGIC;
    \periodic_read_request.periodic_rd_grant_r_reg[0]\ : in STD_LOGIC;
    insert_maint_r1_lcl_reg_0 : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_0\ : in STD_LOGIC;
    \periodic_rd_generation.int_read_this_rank\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    insert_maint_r1 : in STD_LOGIC;
    cke_r : in STD_LOGIC;
    \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC;
    \last_master_r_reg[2]_0\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \maint_prescaler.maint_prescaler_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__12_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \refresh_timer.refresh_timer_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_rank_mach : entity is "mig_7series_v2_3_rank_mach";
end mig_7series_0_mig_7series_v2_3_rank_mach;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_rank_mach is
  signal \^maint_prescaler_tick_r\ : STD_LOGIC;
  signal \^periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0_n_9\ : STD_LOGIC;
  signal \^refresh_generation.refresh_bank_r\ : STD_LOGIC;
  signal \^sr_cntrl.sre_request_logic.sre_request_r\ : STD_LOGIC;
begin
  maint_prescaler_tick_r <= \^maint_prescaler_tick_r\;
  \periodic_rd_generation.periodic_rd_request_r\ <= \^periodic_rd_generation.periodic_rd_request_r\;
  \refresh_generation.refresh_bank_r\ <= \^refresh_generation.refresh_bank_r\;
  \sr_cntrl.sre_request_logic.sre_request_r\ <= \^sr_cntrl.sre_request_logic.sre_request_r\;
\rank_cntrl[0].rank_cntrl0\: entity work.mig_7series_0_mig_7series_v2_3_rank_cntrl
     port map (
      CLK => CLK,
      D(2 downto 0) => D(2 downto 0),
      SR(0) => SR(0),
      act_this_rank => act_this_rank,
      \grant_r_reg[0]\ => \^refresh_generation.refresh_bank_r\,
      in0 => in0,
      \inhbt_act_faw.act_delayed\ => \inhbt_act_faw.act_delayed\,
      \inhbt_act_faw.inhbt_act_faw_r_reg_0\(2 downto 0) => \inhbt_act_faw.inhbt_act_faw_r_reg\(2 downto 0),
      inhbt_act_faw_r => inhbt_act_faw_r,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12_0\,
      insert_maint_r1_lcl_reg => insert_maint_r1_lcl_reg_0,
      \maint_prescaler.maint_prescaler_r1\ => \maint_prescaler.maint_prescaler_r1\,
      \maint_prescaler.maint_prescaler_tick_r_lcl_reg\ => \^maint_prescaler_tick_r\,
      \maintenance_request.upd_last_master_r_reg\ => \rank_cntrl[0].rank_cntrl0_n_9\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      \periodic_rd_generation.int_read_this_rank\ => \periodic_rd_generation.int_read_this_rank\,
      \periodic_rd_generation.periodic_rd_cntr1_r\ => \periodic_rd_generation.periodic_rd_cntr1_r\,
      \periodic_rd_generation.periodic_rd_request_r\ => \^periodic_rd_generation.periodic_rd_request_r\,
      \periodic_rd_generation.periodic_rd_request_r_reg_0\ => \periodic_rd_generation.periodic_rd_request_r_reg\,
      \periodic_rd_generation.periodic_rd_timer_r\(2 downto 0) => \periodic_rd_generation.periodic_rd_timer_r\(2 downto 0),
      \periodic_rd_generation.periodic_rd_timer_r_reg[1]_0\ => \periodic_rd_generation.periodic_rd_timer_r_reg[1]\,
      \periodic_rd_generation.periodic_rd_timer_r_reg[1]_1\ => \periodic_rd_generation.periodic_rd_timer_r_reg[1]_0\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      \periodic_read_request.periodic_rd_grant_r_reg[0]\ => \periodic_read_request.periodic_rd_grant_r_reg[0]\,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \sr_cntrl.sre_request_logic.sre_request_r_reg\ => \^sr_cntrl.sre_request_logic.sre_request_r\,
      \wtr_timer.wtr_cnt_r_reg[0]_0\(1 downto 0) => \wtr_timer.wtr_cnt_r_reg[0]\(1 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]_1\(1 downto 0) => \wtr_timer.wtr_cnt_r_reg[0]_0\(1 downto 0)
    );
rank_common0: entity work.mig_7series_0_mig_7series_v2_3_rank_common
     port map (
      CLK => CLK,
      O(3 downto 0) => O(3 downto 0),
      Q(4 downto 0) => Q(4 downto 0),
      S(3 downto 0) => S(3 downto 0),
      SR(0) => SR(0),
      SS(0) => SS(0),
      app_ref_ack => app_ref_ack,
      app_ref_r => app_ref_r,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_r => app_zq_r,
      app_zq_r_reg_0 => app_zq_r_reg,
      cke_r => cke_r,
      \grant_r_reg[0]\ => \zq_cntrl.zq_request_logic.zq_request_r\,
      \grant_r_reg[0]_0\ => \^sr_cntrl.sre_request_logic.sre_request_r\,
      in0 => in0,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      \init_calib_complete_reg_rep__12_0\ => \init_calib_complete_reg_rep__12_0\,
      \init_calib_complete_reg_rep__12_1\(0) => \init_calib_complete_reg_rep__12_1\(0),
      insert_maint_r1 => insert_maint_r1,
      insert_maint_r1_lcl_reg => insert_maint_r1_lcl_reg,
      \last_master_r_reg[2]\(0) => \last_master_r_reg[2]\(0),
      \last_master_r_reg[2]_0\ => \last_master_r_reg[2]_0\,
      \maint_controller.maint_wip_r_lcl_reg\ => \maint_controller.maint_wip_r_lcl_reg\,
      \maint_prescaler.maint_prescaler_r1\ => \maint_prescaler.maint_prescaler_r1\,
      \maint_prescaler.maint_prescaler_r_reg[0]_0\(0) => \maint_prescaler.maint_prescaler_r_reg[0]\(0),
      maint_ref_zq_wip => maint_ref_zq_wip,
      maint_req_r => maint_req_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      \maintenance_request.maint_sre_r_lcl_reg_0\ => maint_sre_r,
      \maintenance_request.maint_sre_r_lcl_reg_1\(0) => \maintenance_request.maint_sre_r_lcl_reg\(0),
      \maintenance_request.maint_sre_r_lcl_reg_2\ => \maintenance_request.maint_sre_r_lcl_reg_0\,
      \maintenance_request.new_maint_rank_r_reg_0\ => \maintenance_request.upd_last_master_r\,
      mc_cke_ns(0) => mc_cke_ns(0),
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg_0,
      \periodic_rd_generation.periodic_rd_request_r\ => \^periodic_rd_generation.periodic_rd_request_r\,
      \periodic_rd_generation.periodic_rd_request_r_reg\ => \periodic_rd_generation.periodic_rd_request_r_reg_0\,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_grant_r\ => \periodic_read_request.periodic_rd_grant_r\,
      \periodic_read_request.periodic_rd_r_cnt\ => \periodic_read_request.periodic_rd_r_cnt\,
      \periodic_read_request.periodic_rd_r_lcl_reg_0\ => \periodic_read_request.periodic_rd_r_lcl_reg\,
      \periodic_read_request.upd_last_master_r\ => \periodic_read_request.upd_last_master_r\,
      \refresh_generation.refresh_bank_r_reg[0]\ => \refresh_generation.refresh_bank_r_reg[0]\,
      \refresh_generation.refresh_bank_r_reg[0]_0\ => \refresh_generation.refresh_bank_r_reg[0]_0\,
      \refresh_generation.refresh_bank_r_reg[0]_1\ => \^refresh_generation.refresh_bank_r\,
      \refresh_generation.refresh_bank_r_reg[0]_2\ => \rank_cntrl[0].rank_cntrl0_n_9\,
      \refresh_timer.refresh_timer_r_reg[0]_0\(0) => \refresh_timer.refresh_timer_r_reg[0]\(0),
      \refresh_timer.refresh_timer_r_reg[4]_0\(1 downto 0) => \refresh_timer.refresh_timer_r_reg[4]\(1 downto 0),
      \refresh_timer.refresh_timer_r_reg[5]_0\ => \refresh_timer.refresh_timer_r_reg[5]\,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[0]_0\ => \^maint_prescaler_tick_r\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[0]_1\ => \zq_cntrl.zq_timer.zq_timer_r_reg[0]\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(3 downto 0),
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_bank_mach is
  port (
    accept_internal_r : out STD_LOGIC;
    periodic_rd_ack_r : out STD_LOGIC;
    \q_entry_r_reg[1]\ : out STD_LOGIC;
    accept_ns : out STD_LOGIC;
    was_wr : out STD_LOGIC;
    insert_maint_r : out STD_LOGIC;
    sent_row : out STD_LOGIC;
    \cmd_pipe_plus.mc_cmd_reg[0]\ : out STD_LOGIC;
    insert_maint_r1 : out STD_LOGIC;
    cs_en2 : out STD_LOGIC;
    DIC : out STD_LOGIC_VECTOR ( 0 to 0 );
    col_rd_wr : out STD_LOGIC;
    col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cke_r : out STD_LOGIC;
    idle_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rd_this_rank_r_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ordered_r_lcl_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rb_hit_busy_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ras_timer_zero_r_reg : out STD_LOGIC;
    row_cmd_wr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    col_wait_r : out STD_LOGIC;
    demand_priority_r : out STD_LOGIC;
    pass_open_bank_r : out STD_LOGIC;
    pre_bm_end_r : out STD_LOGIC;
    q_has_rd : out STD_LOGIC;
    q_has_priority : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    col_wait_r_0 : out STD_LOGIC;
    demand_priority_r_1 : out STD_LOGIC;
    demanded_prior_r : out STD_LOGIC;
    pass_open_bank_r_2 : out STD_LOGIC;
    pre_bm_end_r_3 : out STD_LOGIC;
    q_has_rd_4 : out STD_LOGIC;
    q_has_priority_5 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    p_52_out : out STD_LOGIC;
    col_wait_r_6 : out STD_LOGIC;
    demand_priority_r_7 : out STD_LOGIC;
    demanded_prior_r_8 : out STD_LOGIC;
    override_demand_r : out STD_LOGIC;
    q_has_rd_9 : out STD_LOGIC;
    q_has_priority_10 : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    p_13_out : out STD_LOGIC;
    col_wait_r_11 : out STD_LOGIC;
    demand_priority_r_12 : out STD_LOGIC;
    demanded_prior_r_13 : out STD_LOGIC;
    q_has_rd_14 : out STD_LOGIC;
    q_has_priority_15 : out STD_LOGIC;
    maint_wip_r : out STD_LOGIC;
    wait_for_maint_r : out STD_LOGIC;
    wait_for_maint_r_16 : out STD_LOGIC;
    wait_for_maint_r_17 : out STD_LOGIC;
    wait_for_maint_r_18 : out STD_LOGIC;
    rnk_config_valid_r : out STD_LOGIC;
    periodic_rd_cntr_r : out STD_LOGIC;
    tail_r : out STD_LOGIC;
    head_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
    tail_r_19 : out STD_LOGIC;
    tail_r_20 : out STD_LOGIC;
    tail_r_21 : out STD_LOGIC;
    was_priority : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC;
    rb_hit_busy_r_reg : out STD_LOGIC;
    rb_hit_busy_r_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[0]\ : out STD_LOGIC;
    rb_hit_busy_r_reg_1 : out STD_LOGIC;
    accept_internal_r_reg : out STD_LOGIC;
    act_wait_r_lcl_reg : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \periodic_rd_generation.read_this_rank\ : out STD_LOGIC;
    \periodic_rd_generation.int_read_this_rank\ : out STD_LOGIC;
    \last_master_r_reg[0]\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \last_master_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_odt_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]\ : out STD_LOGIC;
    \ras_timer_r_reg[0]_0\ : out STD_LOGIC;
    ras_timer_zero_r_reg_1 : out STD_LOGIC;
    act_wait_r_lcl_reg_0 : out STD_LOGIC;
    act_wait_r_lcl_reg_1 : out STD_LOGIC;
    act_wait_r_lcl_reg_2 : out STD_LOGIC;
    \ras_timer_r_reg[0]_1\ : out STD_LOGIC;
    ordered_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]_0\ : out STD_LOGIC;
    head_r_lcl_reg : out STD_LOGIC;
    head_r_lcl_reg_0 : out STD_LOGIC;
    \q_entry_r_reg[1]_1\ : out STD_LOGIC;
    \q_entry_r_reg[1]_2\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    auto_pre_r_lcl_reg : out STD_LOGIC;
    head_r_lcl_reg_1 : out STD_LOGIC;
    ordered_r_lcl_reg_1 : out STD_LOGIC;
    \q_entry_r_reg[1]_3\ : out STD_LOGIC;
    head_r_lcl_reg_2 : out STD_LOGIC;
    head_r_lcl_reg_3 : out STD_LOGIC;
    \q_entry_r_reg[0]_0\ : out STD_LOGIC;
    \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC;
    head_r_lcl_reg_4 : out STD_LOGIC;
    \q_entry_r_reg[0]_1\ : out STD_LOGIC;
    ordered_r_lcl_reg_2 : out STD_LOGIC;
    head_r_lcl_reg_5 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_0 : out STD_LOGIC;
    \ras_timer_r_reg[0]_2\ : out STD_LOGIC;
    ras_timer_zero_r_reg_2 : out STD_LOGIC;
    act_wait_r_lcl_reg_3 : out STD_LOGIC;
    act_wait_r_lcl_reg_4 : out STD_LOGIC;
    act_wait_r_lcl_reg_5 : out STD_LOGIC;
    \grant_r_reg[3]\ : out STD_LOGIC;
    \grant_r_reg[1]\ : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_1 : out STD_LOGIC;
    pass_open_bank_r_lcl_reg_2 : out STD_LOGIC;
    \cmd_pipe_plus.mc_we_n_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \last_master_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 29 downto 0 );
    \cmd_pipe_plus.mc_address_reg[41]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    mc_cs_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 );
    \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\ : out STD_LOGIC;
    \grant_r_reg[0]\ : out STD_LOGIC;
    \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC;
    rnk_config_valid_r_lcl_reg : out STD_LOGIC;
    head_r_lcl_reg_6 : out STD_LOGIC;
    \last_master_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \grant_r_reg[3]_0\ : out STD_LOGIC;
    demanded_prior_r_reg : out STD_LOGIC;
    demanded_prior_r_reg_0 : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]\ : out STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[0]_0\ : out STD_LOGIC;
    act_this_rank : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : out STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[8]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[7]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[6]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[40]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[39]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[36]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[35]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[34]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[32]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[30]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[29]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[28]_0\ : out STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    CLK : in STD_LOGIC;
    maint_srx_r : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke_ns : in STD_LOGIC_VECTOR ( 0 to 0 );
    col_wait_r_reg : in STD_LOGIC;
    q_has_rd_r_reg : in STD_LOGIC;
    q_has_priority_r_reg : in STD_LOGIC;
    col_wait_r_reg_0 : in STD_LOGIC;
    q_has_rd_r_reg_0 : in STD_LOGIC;
    q_has_priority_r_reg_0 : in STD_LOGIC;
    col_wait_r_reg_1 : in STD_LOGIC;
    q_has_rd_r_reg_1 : in STD_LOGIC;
    q_has_priority_r_reg_1 : in STD_LOGIC;
    col_wait_r_reg_2 : in STD_LOGIC;
    q_has_rd_r_reg_2 : in STD_LOGIC;
    q_has_priority_r_reg_2 : in STD_LOGIC;
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_mc_ctl_full : in STD_LOGIC;
    \maintenance_request.maint_req_r_lcl_reg\ : in STD_LOGIC;
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : in STD_LOGIC;
    wait_for_maint_r_lcl_reg : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_0 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_1 : in STD_LOGIC;
    wait_for_maint_r_lcl_reg_2 : in STD_LOGIC;
    rnk_config_valid_r_lcl_reg_0 : in STD_LOGIC;
    \periodic_read_request.periodic_rd_r_lcl_reg\ : in STD_LOGIC;
    idle_r_lcl_reg : in STD_LOGIC;
    head_r_lcl_reg_7 : in STD_LOGIC;
    idle_r_lcl_reg_0 : in STD_LOGIC;
    head_r_lcl_reg_8 : in STD_LOGIC;
    idle_r_lcl_reg_1 : in STD_LOGIC;
    head_r_lcl_reg_9 : in STD_LOGIC;
    idle_r_lcl_reg_2 : in STD_LOGIC;
    head_r_lcl_reg_10 : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[0]\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[0]_0\ : in STD_LOGIC;
    periodic_rd_r : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC;
    \grant_r_reg[1]_0\ : in STD_LOGIC;
    override_demand_r_reg : in STD_LOGIC;
    col_wait_r_reg_3 : in STD_LOGIC;
    col_wait_r_reg_4 : in STD_LOGIC;
    override_demand_r_reg_0 : in STD_LOGIC;
    \cmd_pipe_plus.mc_aux_out0_reg[1]\ : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    \maint_controller.maint_hit_busies_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    maint_req_r : in STD_LOGIC;
    periodic_rd_ack_r_lcl_reg : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    req_wr_r_lcl_reg : in STD_LOGIC;
    accept_r_reg : in STD_LOGIC;
    req_wr_r_lcl_reg_0 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    accept_r_reg_0 : in STD_LOGIC;
    maint_zq_r : in STD_LOGIC;
    granted_row_r_reg : in STD_LOGIC;
    granted_row_r_reg_0 : in STD_LOGIC;
    maint_sre_r : in STD_LOGIC;
    act_wait_r_lcl_reg_6 : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    \last_master_r_reg[3]_1\ : in STD_LOGIC;
    \app_addr_r1_reg[23]_2\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    inhbt_act_faw_r : in STD_LOGIC;
    \grant_r_reg[3]_1\ : in STD_LOGIC;
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ : in STD_LOGIC;
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_mc_data_full : in STD_LOGIC;
    \wtr_timer.wtr_cnt_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    app_rdy_r_reg : in STD_LOGIC;
    \generate_maint_cmds.insert_maint_r_lcl_reg\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \maintenance_request.maint_srx_r_lcl_reg\ : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    idle_r_lcl_reg_3 : in STD_LOGIC;
    idle_r_lcl_reg_4 : in STD_LOGIC;
    idle_r_lcl_reg_5 : in STD_LOGIC;
    idle_r_lcl_reg_6 : in STD_LOGIC;
    pre_bm_end_r_reg : in STD_LOGIC;
    idle_r_lcl_reg_7 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_bank_mach : entity is "mig_7series_v2_3_bank_mach";
end mig_7series_0_mig_7series_v2_3_bank_mach;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_bank_mach is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^accept_internal_r\ : STD_LOGIC;
  signal \^accept_internal_r_reg\ : STD_LOGIC;
  signal act_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^act_wait_r_lcl_reg\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_2\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_4\ : STD_LOGIC;
  signal \^act_wait_r_lcl_reg_5\ : STD_LOGIC;
  signal arb_mux0_n_100 : STD_LOGIC;
  signal arb_mux0_n_113 : STD_LOGIC;
  signal arb_mux0_n_23 : STD_LOGIC;
  signal arb_mux0_n_73 : STD_LOGIC;
  signal arb_mux0_n_76 : STD_LOGIC;
  signal arb_mux0_n_80 : STD_LOGIC;
  signal arb_mux0_n_86 : STD_LOGIC;
  signal arb_mux0_n_87 : STD_LOGIC;
  signal arb_mux0_n_89 : STD_LOGIC;
  signal arb_mux0_n_90 : STD_LOGIC;
  signal arb_mux0_n_91 : STD_LOGIC;
  signal arb_mux0_n_92 : STD_LOGIC;
  signal arb_mux0_n_97 : STD_LOGIC;
  signal arb_mux0_n_98 : STD_LOGIC;
  signal arb_mux0_n_99 : STD_LOGIC;
  signal \arb_row_col0/granted_col_ns\ : STD_LOGIC;
  signal auto_pre_r : STD_LOGIC;
  signal auto_pre_r_13 : STD_LOGIC;
  signal auto_pre_r_19 : STD_LOGIC;
  signal auto_pre_r_5 : STD_LOGIC;
  signal \^auto_pre_r_lcl_reg\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_32\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_33\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_35\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_36\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_40\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_42\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_44\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_48\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_50\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_51\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_54\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_55\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_58\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_73\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0_n_75\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_30\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_31\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_33\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_34\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_36\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_37\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_41\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_44\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_45\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_52\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_53\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_54\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_55\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_56\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_57\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_72\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0_n_73\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_28\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_30\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_31\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_36\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_37\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_40\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_43\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_44\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_45\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_46\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_48\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_49\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_50\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0_n_65\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_28\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_29\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_31\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_32\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_38\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_42\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_44\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_45\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_46\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_47\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_48\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_62\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_64\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0_n_65\ : STD_LOGIC;
  signal bank_common0_n_11 : STD_LOGIC;
  signal bank_common0_n_13 : STD_LOGIC;
  signal bank_common0_n_15 : STD_LOGIC;
  signal bank_common0_n_17 : STD_LOGIC;
  signal bank_common0_n_30 : STD_LOGIC;
  signal \bank_compare0/req_col_r\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_17\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_2\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_col_r_9\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \bank_compare0/req_wr_r_lcl0\ : STD_LOGIC;
  signal \bank_queue0/q_entry_ns\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \bank_queue0/rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \bank_queue0/rb_hit_busies.rb_hit_busies_ns_0\ : STD_LOGIC_VECTOR ( 5 downto 3 );
  signal \bank_queue0/rb_hit_busies.rb_hit_busies_ns_1\ : STD_LOGIC_VECTOR ( 6 downto 4 );
  signal \bank_queue0/rb_hit_busies.rb_hit_busies_ns_4\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0_10\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r0_11\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_14\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_20\ : STD_LOGIC;
  signal \bank_state0/ofs_rdy_r_6\ : STD_LOGIC;
  signal \bank_state0/override_demand_ns\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_ns\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_ns_15\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_ns_21\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_ns_7\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_r\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_r_16\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_r_22\ : STD_LOGIC;
  signal \bank_state0/req_bank_rdy_r_8\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_address_reg[28]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^cmd_pipe_plus.mc_address_reg[41]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^cmd_pipe_plus.mc_bank_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^cmd_pipe_plus.mc_bank_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^cmd_pipe_plus.mc_bank_reg[8]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^cmd_pipe_plus.mc_cmd_reg[0]\ : STD_LOGIC;
  signal \^cs_en2\ : STD_LOGIC;
  signal \^demand_priority_r\ : STD_LOGIC;
  signal \^demand_priority_r_1\ : STD_LOGIC;
  signal \^demand_priority_r_12\ : STD_LOGIC;
  signal \^demand_priority_r_7\ : STD_LOGIC;
  signal \^demanded_prior_r\ : STD_LOGIC;
  signal \^demanded_prior_r_13\ : STD_LOGIC;
  signal \^demanded_prior_r_8\ : STD_LOGIC;
  signal \^demanded_prior_r_reg\ : STD_LOGIC;
  signal \^demanded_prior_r_reg_0\ : STD_LOGIC;
  signal granted_row_ns : STD_LOGIC;
  signal \^head_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^head_r_lcl_reg_3\ : STD_LOGIC;
  signal hi_priority : STD_LOGIC;
  signal \^idle_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^insert_maint_r\ : STD_LOGIC;
  signal \^last_master_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \maint_controller.maint_rdy\ : STD_LOGIC;
  signal \^maint_wip_r\ : STD_LOGIC;
  signal ordered_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^ordered_r_lcl_reg\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^ordered_r_lcl_reg_0\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg_1\ : STD_LOGIC;
  signal \^ordered_r_lcl_reg_2\ : STD_LOGIC;
  signal \^override_demand_r\ : STD_LOGIC;
  signal \^p_13_out\ : STD_LOGIC;
  signal \^p_52_out\ : STD_LOGIC;
  signal p_7_in : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_1\ : STD_LOGIC;
  signal \^pass_open_bank_r_lcl_reg_2\ : STD_LOGIC;
  signal \^periodic_rd_ack_r\ : STD_LOGIC;
  signal periodic_rd_insert : STD_LOGIC;
  signal \pre_4_1_1T_arb.granted_pre_ns\ : STD_LOGIC;
  signal q_entry_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q_entry_r_reg[0]\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_0\ : STD_LOGIC;
  signal \^q_entry_r_reg[0]_1\ : STD_LOGIC;
  signal \^q_entry_r_reg[1]_2\ : STD_LOGIC;
  signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal rb_hit_busies_r_12 : STD_LOGIC_VECTOR ( 5 downto 3 );
  signal rb_hit_busies_r_18 : STD_LOGIC_VECTOR ( 6 downto 4 );
  signal rb_hit_busies_r_3 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \^rb_hit_busy_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rb_hit_busy_r_reg\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC;
  signal \^rb_hit_busy_r_reg_1\ : STD_LOGIC;
  signal rd_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rd_this_rank_r_reg[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rd_wr_r : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal req_bank_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req_data_buf_addr_r : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal req_periodic_rd_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal req_row_r : STD_LOGIC_VECTOR ( 53 downto 0 );
  signal req_wr_r : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_pre : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  accept_internal_r <= \^accept_internal_r\;
  accept_internal_r_reg <= \^accept_internal_r_reg\;
  act_wait_r_lcl_reg <= \^act_wait_r_lcl_reg\;
  act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\;
  act_wait_r_lcl_reg_2 <= \^act_wait_r_lcl_reg_2\;
  act_wait_r_lcl_reg_4 <= \^act_wait_r_lcl_reg_4\;
  act_wait_r_lcl_reg_5 <= \^act_wait_r_lcl_reg_5\;
  auto_pre_r_lcl_reg <= \^auto_pre_r_lcl_reg\;
  \cmd_pipe_plus.mc_address_reg[28]\(0) <= \^cmd_pipe_plus.mc_address_reg[28]\(0);
  \cmd_pipe_plus.mc_address_reg[41]_0\(10 downto 0) <= \^cmd_pipe_plus.mc_address_reg[41]_0\(10 downto 0);
  \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) <= \^cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0);
  \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) <= \^cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0);
  \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) <= \^cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0);
  \cmd_pipe_plus.mc_cmd_reg[0]\ <= \^cmd_pipe_plus.mc_cmd_reg[0]\;
  cs_en2 <= \^cs_en2\;
  demand_priority_r <= \^demand_priority_r\;
  demand_priority_r_1 <= \^demand_priority_r_1\;
  demand_priority_r_12 <= \^demand_priority_r_12\;
  demand_priority_r_7 <= \^demand_priority_r_7\;
  demanded_prior_r <= \^demanded_prior_r\;
  demanded_prior_r_13 <= \^demanded_prior_r_13\;
  demanded_prior_r_8 <= \^demanded_prior_r_8\;
  demanded_prior_r_reg <= \^demanded_prior_r_reg\;
  demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\;
  head_r(3 downto 0) <= \^head_r\(3 downto 0);
  head_r_lcl_reg_3 <= \^head_r_lcl_reg_3\;
  idle_r(3 downto 0) <= \^idle_r\(3 downto 0);
  insert_maint_r <= \^insert_maint_r\;
  \last_master_r_reg[3]\(3 downto 0) <= \^last_master_r_reg[3]\(3 downto 0);
  maint_wip_r <= \^maint_wip_r\;
  ordered_r_lcl_reg(2 downto 0) <= \^ordered_r_lcl_reg\(2 downto 0);
  ordered_r_lcl_reg_0 <= \^ordered_r_lcl_reg_0\;
  ordered_r_lcl_reg_1 <= \^ordered_r_lcl_reg_1\;
  ordered_r_lcl_reg_2 <= \^ordered_r_lcl_reg_2\;
  override_demand_r <= \^override_demand_r\;
  p_13_out <= \^p_13_out\;
  p_52_out <= \^p_52_out\;
  pass_open_bank_r_lcl_reg_1 <= \^pass_open_bank_r_lcl_reg_1\;
  pass_open_bank_r_lcl_reg_2 <= \^pass_open_bank_r_lcl_reg_2\;
  periodic_rd_ack_r <= \^periodic_rd_ack_r\;
  \q_entry_r_reg[0]\ <= \^q_entry_r_reg[0]\;
  \q_entry_r_reg[0]_0\ <= \^q_entry_r_reg[0]_0\;
  \q_entry_r_reg[0]_1\ <= \^q_entry_r_reg[0]_1\;
  \q_entry_r_reg[1]_2\ <= \^q_entry_r_reg[1]_2\;
  rb_hit_busy_r(3 downto 0) <= \^rb_hit_busy_r\(3 downto 0);
  rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\;
  rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\;
  rb_hit_busy_r_reg_1 <= \^rb_hit_busy_r_reg_1\;
  \rd_this_rank_r_reg[0]\(1 downto 0) <= \^rd_this_rank_r_reg[0]\(1 downto 0);
  row_cmd_wr(3 downto 0) <= \^row_cmd_wr\(3 downto 0);
arb_mux0: entity work.mig_7series_0_mig_7series_v2_3_arb_mux
     port map (
      CLK => CLK,
      D(1) => D(0),
      D(0) => \last_master_r_reg[0]\,
      DIC(0) => DIC(0),
      E(0) => E(0),
      Q(3 downto 0) => \^q\(3 downto 0),
      SR(0) => SR(0),
      act_this_rank => act_this_rank,
      act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0),
      act_wait_r_lcl_reg => \^row_cmd_wr\(1),
      act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0),
      act_wait_r_lcl_reg_1 => \bank_cntrl[3].bank0_n_62\,
      act_wait_r_lcl_reg_2 => \^row_cmd_wr\(2),
      act_wait_r_lcl_reg_3 => \^row_cmd_wr\(3),
      act_wait_r_lcl_reg_4 => act_wait_r_lcl_reg_6,
      auto_pre_r => auto_pre_r_19,
      auto_pre_r_6 => auto_pre_r,
      auto_pre_r_7 => auto_pre_r_5,
      auto_pre_r_8 => auto_pre_r_13,
      auto_pre_r_lcl_reg => \bank_cntrl[0].bank0_n_58\,
      auto_pre_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_57\,
      auto_pre_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_50\,
      auto_pre_r_lcl_reg_2 => \bank_cntrl[3].bank0_n_48\,
      cke_r => cke_r,
      \cmd_pipe_plus.mc_address_reg[11]\ => arb_mux0_n_73,
      \cmd_pipe_plus.mc_address_reg[28]\(3) => \^cmd_pipe_plus.mc_address_reg[28]\(0),
      \cmd_pipe_plus.mc_address_reg[28]\(2 downto 0) => sending_pre(2 downto 0),
      \cmd_pipe_plus.mc_address_reg[28]_0\ => \cmd_pipe_plus.mc_address_reg[28]_0\,
      \cmd_pipe_plus.mc_address_reg[29]\ => \cmd_pipe_plus.mc_address_reg[29]\,
      \cmd_pipe_plus.mc_address_reg[30]\ => \cmd_pipe_plus.mc_address_reg[30]\,
      \cmd_pipe_plus.mc_address_reg[32]\ => \cmd_pipe_plus.mc_address_reg[32]\,
      \cmd_pipe_plus.mc_address_reg[34]\ => \cmd_pipe_plus.mc_address_reg[34]\,
      \cmd_pipe_plus.mc_address_reg[35]\ => \cmd_pipe_plus.mc_address_reg[35]\,
      \cmd_pipe_plus.mc_address_reg[36]\ => \cmd_pipe_plus.mc_address_reg[36]\,
      \cmd_pipe_plus.mc_address_reg[39]\ => \cmd_pipe_plus.mc_address_reg[39]\,
      \cmd_pipe_plus.mc_address_reg[40]\ => \cmd_pipe_plus.mc_address_reg[40]\,
      \cmd_pipe_plus.mc_address_reg[41]\(28) => \cmd_pipe_plus.mc_address_reg[41]\(29),
      \cmd_pipe_plus.mc_address_reg[41]\(27 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(27 downto 0),
      \cmd_pipe_plus.mc_aux_out0_reg[1]\ => \cmd_pipe_plus.mc_aux_out0_reg[1]\,
      \cmd_pipe_plus.mc_bank_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_bank_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_bank_reg[6]\ => \cmd_pipe_plus.mc_bank_reg[6]\,
      \cmd_pipe_plus.mc_bank_reg[7]\ => \cmd_pipe_plus.mc_bank_reg[7]\,
      \cmd_pipe_plus.mc_bank_reg[8]\ => \cmd_pipe_plus.mc_bank_reg[8]_0\,
      \cmd_pipe_plus.mc_cas_n_reg[2]\ => \^cs_en2\,
      \cmd_pipe_plus.mc_cmd_reg[0]\ => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\,
      \cmd_pipe_plus.mc_ras_n_reg[0]\ => insert_maint_r1,
      \cmd_pipe_plus.mc_we_n_reg[1]\ => \cmd_pipe_plus.mc_we_n_reg[1]\,
      \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0),
      col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0),
      col_rd_wr => col_rd_wr,
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0),
      demand_priority_r_reg => arb_mux0_n_97,
      demand_priority_r_reg_0 => arb_mux0_n_98,
      demand_priority_r_reg_1 => arb_mux0_n_99,
      demand_priority_r_reg_2 => arb_mux0_n_100,
      demand_priority_r_reg_3 => \bank_cntrl[3].bank0_n_64\,
      demand_priority_r_reg_4 => \bank_cntrl[2].bank0_n_65\,
      demand_priority_r_reg_5 => \bank_cntrl[1].bank0_n_72\,
      demand_priority_r_reg_6 => \bank_cntrl[0].bank0_n_73\,
      \generate_maint_cmds.insert_maint_r_lcl_reg\ => \^insert_maint_r\,
      \grant_r_reg[0]\ => arb_mux0_n_92,
      \grant_r_reg[1]\ => arb_mux0_n_87,
      \grant_r_reg[1]_0\ => arb_mux0_n_91,
      \grant_r_reg[1]_1\ => \grant_r_reg[1]_0\,
      \grant_r_reg[2]\ => arb_mux0_n_86,
      \grant_r_reg[2]_0\ => arb_mux0_n_89,
      \grant_r_reg[3]\ => arb_mux0_n_23,
      \grant_r_reg[3]_0\ => arb_mux0_n_76,
      \grant_r_reg[3]_1\ => \grant_r_reg[3]_0\,
      \grant_r_reg[3]_2\ => arb_mux0_n_90,
      \grant_r_reg[3]_3\ => arb_mux0_n_113,
      granted_col_ns => \arb_row_col0/granted_col_ns\,
      granted_row_ns => granted_row_ns,
      granted_row_r_reg => granted_row_r_reg,
      granted_row_r_reg_0 => granted_row_r_reg_0,
      head_r_lcl_reg => \bank_cntrl[3].bank0_n_47\,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \last_master_r_reg[0]\ => arb_mux0_n_80,
      \last_master_r_reg[1]\ => sent_row,
      \last_master_r_reg[1]_0\(0) => \last_master_r_reg[1]\(0),
      \last_master_r_reg[3]\(3 downto 0) => \^last_master_r_reg[3]\(3 downto 0),
      \last_master_r_reg[3]_0\(0) => \last_master_r_reg[3]_0\(0),
      \last_master_r_reg[3]_1\ => \last_master_r_reg[3]_1\,
      maint_sre_r => maint_sre_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cke_ns(0) => mc_cke_ns(0),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(1 downto 0) => mc_ras_n_ns(1 downto 0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r_14\,
      ofs_rdy_r_3 => \bank_state0/ofs_rdy_r_20\,
      ofs_rdy_r_4 => \bank_state0/ofs_rdy_r_6\,
      ofs_rdy_r_5 => \bank_state0/ofs_rdy_r\,
      override_demand_ns => \bank_state0/override_demand_ns\,
      \periodic_rd_generation.int_read_this_rank\ => \periodic_rd_generation.int_read_this_rank\,
      \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\,
      \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\,
      ras_timer_zero_r_reg => \bank_cntrl[1].bank0_n_56\,
      ras_timer_zero_r_reg_0 => \bank_cntrl[1].bank0_n_55\,
      rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0),
      rd_wr_r(1 downto 0) => rd_wr_r(3 downto 2),
      rd_wr_r_lcl_reg => \bank_cntrl[0].bank0_n_33\,
      rd_wr_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_28\,
      rd_wr_r_lcl_reg_1 => \bank_cntrl[1].bank0_n_30\,
      rd_wr_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_32\,
      rd_wr_r_lcl_reg_3 => \bank_cntrl[2].bank0_n_28\,
      rd_wr_r_lcl_reg_4 => \bank_cntrl[3].bank0_n_29\,
      rd_wr_r_lcl_reg_5 => \^rd_this_rank_r_reg[0]\(0),
      rd_wr_r_lcl_reg_6 => \^rd_this_rank_r_reg[0]\(1),
      \req_bank_r_lcl_reg[2]\(2 downto 0) => req_bank_r(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \^cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \^cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \^cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0),
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns_7\,
      req_bank_rdy_ns_0 => \bank_state0/req_bank_rdy_ns\,
      req_bank_rdy_ns_1 => \bank_state0/req_bank_rdy_ns_21\,
      req_bank_rdy_ns_2 => \bank_state0/req_bank_rdy_ns_15\,
      req_bank_rdy_r => \bank_state0/req_bank_rdy_r\,
      req_bank_rdy_r_10 => \bank_state0/req_bank_rdy_r_16\,
      req_bank_rdy_r_11 => \bank_state0/req_bank_rdy_r_22\,
      req_bank_rdy_r_9 => \bank_state0/req_bank_rdy_r_8\,
      \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_17\(9 downto 0),
      \req_col_r_reg[9]_0\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0),
      \req_col_r_reg[9]_1\(9 downto 0) => \bank_compare0/req_col_r_2\(9 downto 0),
      \req_col_r_reg[9]_2\(9 downto 0) => \bank_compare0/req_col_r_9\(9 downto 0),
      req_data_buf_addr_r(19 downto 0) => req_data_buf_addr_r(19 downto 0),
      req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0),
      req_row_r(30) => req_row_r(53),
      req_row_r(29 downto 20) => req_row_r(51 downto 42),
      req_row_r(19 downto 8) => req_row_r(39 downto 28),
      req_row_r(7) => req_row_r(25),
      req_row_r(6 downto 3) => req_row_r(23 downto 20),
      req_row_r(2 downto 0) => req_row_r(16 downto 14),
      \req_row_r_lcl_reg[13]\(13 downto 12) => \^cmd_pipe_plus.mc_address_reg[41]_0\(1 downto 0),
      \req_row_r_lcl_reg[13]\(11 downto 0) => req_row_r(11 downto 0),
      \req_row_r_lcl_reg[13]_0\(8 downto 0) => \^cmd_pipe_plus.mc_address_reg[41]_0\(10 downto 2),
      \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\,
      rnk_config_valid_r_lcl_reg => rnk_config_valid_r,
      rnk_config_valid_r_lcl_reg_0 => rnk_config_valid_r_lcl_reg,
      rnk_config_valid_r_lcl_reg_1 => rnk_config_valid_r_lcl_reg_0,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\ => \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\,
      wait_for_maint_r_lcl_reg => \bank_cntrl[1].bank0_n_52\,
      wait_for_maint_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_49\,
      wait_for_maint_r_lcl_reg_1 => \bank_cntrl[1].bank0_n_53\,
      wait_for_maint_r_lcl_reg_2 => \bank_cntrl[2].bank0_n_48\,
      wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]\ => \wtr_timer.wtr_cnt_r_reg[0]\,
      \wtr_timer.wtr_cnt_r_reg[0]_0\ => \wtr_timer.wtr_cnt_r_reg[0]_0\,
      \wtr_timer.wtr_cnt_r_reg[1]\(0) => \wtr_timer.wtr_cnt_r_reg[1]\(0)
    );
\bank_cntrl[0].bank0\: entity work.mig_7series_0_mig_7series_v2_3_bank_cntrl
     port map (
      CLK => CLK,
      D(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_1\(4),
      E(0) => \^idle_r\(0),
      Q(0) => rb_hit_busies_r_18(4),
      S(0) => S(0),
      SR(0) => SR(0),
      accept_internal_r_reg => \^accept_internal_r_reg\,
      accept_internal_r_reg_0 => \^accept_internal_r\,
      accept_r_reg => accept_r_reg_0,
      act_this_rank_r(0) => act_this_rank_r(0),
      \act_this_rank_r_reg[0]\ => \^row_cmd_wr\(0),
      act_wait_r_lcl_reg => pass_open_bank_r,
      act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg\,
      act_wait_r_lcl_reg_1 => \^act_wait_r_lcl_reg_5\,
      act_wait_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_54\,
      \app_addr_r1_reg[23]\(13 downto 0) => \app_addr_r1_reg[23]_2\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      auto_pre_r => auto_pre_r,
      auto_pre_r_lcl_reg => wait_for_maint_r,
      bm_end_r1_reg => bm_end_r1_reg,
      bm_end_r1_reg_0 => \bank_cntrl[3].bank0_n_32\,
      bm_end_r1_reg_1 => \bank_cntrl[2].bank0_n_31\,
      bm_end_r1_reg_2 => \bank_cntrl[1].bank0_n_45\,
      \cmd_pipe_plus.mc_address_reg[13]\(13 downto 12) => \^cmd_pipe_plus.mc_address_reg[41]_0\(1 downto 0),
      \cmd_pipe_plus.mc_address_reg[13]\(11 downto 0) => req_row_r(11 downto 0),
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => req_bank_r(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(4 downto 0),
      col_wait_r_reg => col_wait_r_reg,
      demand_priority_r_reg => \^demand_priority_r\,
      demand_priority_r_reg_0 => \^demand_priority_r_7\,
      demanded_prior_r => \bank_state0/demanded_prior_r\,
      demanded_prior_r_reg => \^demanded_prior_r_reg_0\,
      demanded_prior_r_reg_0 => \^demanded_prior_r_reg\,
      demanded_prior_r_reg_1 => \^demanded_prior_r_8\,
      \grant_r_reg[0]\ => \bank_cntrl[0].bank0_n_33\,
      \grant_r_reg[0]_0\ => \grant_r_reg[0]\,
      \grant_r_reg[0]_1\(0) => sending_pre(0),
      \grant_r_reg[0]_2\(0) => \^last_master_r_reg[3]\(0),
      \grant_r_reg[1]\ => \bank_cntrl[0].bank0_n_58\,
      \grant_r_reg[2]\ => \bank_cntrl[0].bank0_n_75\,
      \grant_r_reg[2]_0\(1) => \^q\(2),
      \grant_r_reg[2]_0\(0) => \^q\(0),
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      granted_col_ns => \arb_row_col0/granted_col_ns\,
      granted_col_r_reg => \bank_cntrl[0].bank0_n_32\,
      granted_col_r_reg_0 => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      head_r_lcl_reg => head_r_lcl_reg,
      head_r_lcl_reg_0 => head_r_lcl_reg_2,
      head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_48\,
      head_r_lcl_reg_2 => \^head_r_lcl_reg_3\,
      head_r_lcl_reg_3 => \bank_cntrl[0].bank0_n_50\,
      head_r_lcl_reg_4 => head_r_lcl_reg_6,
      head_r_lcl_reg_5 => head_r_lcl_reg_7,
      hi_priority => hi_priority,
      idle_r_lcl_reg => idle_r_lcl_reg,
      idle_r_lcl_reg_0 => \^rb_hit_busy_r_reg_0\,
      idle_r_lcl_reg_1 => \^rb_hit_busy_r_reg_1\,
      idle_r_lcl_reg_2 => \^rb_hit_busy_r_reg\,
      idle_r_lcl_reg_3 => bank_common0_n_15,
      idle_r_lcl_reg_4(0) => \^idle_r\(1),
      idle_r_lcl_reg_5(0) => \^idle_r\(2),
      idle_r_lcl_reg_6(0) => \^idle_r\(3),
      idle_r_lcl_reg_7 => idle_r_lcl_reg_3,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      \maint_controller.maint_wip_r_lcl_reg\ => \^auto_pre_r_lcl_reg\,
      \maint_controller.maint_wip_r_lcl_reg_0\ => \^maint_wip_r\,
      maint_req_r => maint_req_r,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_11\,
      ordered_r(0) => ordered_r(0),
      ordered_r_lcl_reg => \^ordered_r_lcl_reg\(0),
      ordered_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_46\,
      ordered_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_44\,
      override_demand_r_reg => override_demand_r_reg,
      p_7_in => p_7_in,
      periodic_rd_ack_r_lcl_reg => \^q_entry_r_reg[1]_2\,
      periodic_rd_ack_r_lcl_reg_0 => \^q_entry_r_reg[0]_0\,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_2 => \^periodic_rd_ack_r\,
      periodic_rd_insert => periodic_rd_insert,
      pre_bm_end_r => pre_bm_end_r,
      pre_bm_end_r_reg => \^q_entry_r_reg[0]\,
      pre_bm_end_r_reg_0 => \^p_52_out\,
      pre_bm_end_r_reg_1 => \^p_13_out\,
      pre_passing_open_bank_r_reg => \bank_cntrl[2].bank0_n_43\,
      pre_passing_open_bank_r_reg_0 => \bank_cntrl[3].bank0_n_45\,
      q_entry_ns(0) => \bank_queue0/q_entry_ns\(1),
      \q_entry_r_reg[0]\(0) => q_entry_r(0),
      \q_entry_r_reg[0]_0\ => \bank_cntrl[0].bank0_n_51\,
      \q_entry_r_reg[0]_1\ => bank_common0_n_30,
      \q_entry_r_reg[1]\ => \bank_cntrl[0].bank0_n_40\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]_0\,
      \q_entry_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_42\,
      \q_entry_r_reg[1]_2\ => \bank_cntrl[0].bank0_n_44\,
      \q_entry_r_reg[1]_3\ => \bank_cntrl[2].bank0_n_37\,
      \q_entry_r_reg[1]_4\ => \bank_cntrl[1].bank0_n_41\,
      q_has_priority => q_has_priority,
      q_has_priority_r_reg => \^rb_hit_busy_r\(0),
      q_has_priority_r_reg_0 => q_has_priority_r_reg,
      q_has_rd => q_has_rd,
      q_has_rd_r_reg => q_has_rd_r_reg,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[0].bank0_n_35\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_55\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[0].bank0_n_36\,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ => \bank_cntrl[1].bank0_n_31\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \bank_cntrl[2].bank0_n_40\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(2 downto 0) => rb_hit_busies_r(3 downto 1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => \bank_cntrl[3].bank0_n_42\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(2 downto 0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_4\(3 downto 1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_0\(4),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns\(4),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\(0) => rb_hit_busies_r_12(4),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2\(0) => rb_hit_busies_r_3(4),
      rb_hit_busy_r_reg => \^rb_hit_busy_r\(3),
      rb_hit_busy_r_reg_0 => \^rb_hit_busy_r\(2),
      rb_hit_busy_r_reg_1 => \^rb_hit_busy_r\(1),
      rd_this_rank_r(0) => rd_this_rank_r(0),
      \rd_this_rank_r_reg[0]\ => \^rd_this_rank_r_reg[0]\(0),
      rd_wr_r_lcl_reg => \bank_cntrl[3].bank0_n_28\,
      rd_wr_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_30\,
      rd_wr_r_lcl_reg_1 => arb_mux0_n_23,
      rd_wr_r_lcl_reg_2 => \bank_cntrl[1].bank0_n_54\,
      rd_wr_r_lcl_reg_3 => \bank_cntrl[3].bank0_n_31\,
      rd_wr_r_lcl_reg_4 => \bank_cntrl[1].bank0_n_44\,
      rd_wr_r_lcl_reg_5 => \bank_cntrl[2].bank0_n_30\,
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns\,
      req_bank_rdy_r => \bank_state0/req_bank_rdy_r\,
      req_bank_rdy_r_reg => arb_mux0_n_97,
      req_periodic_rd_r(0) => req_periodic_rd_r(0),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => req_wr_r_lcl_reg_0,
      req_wr_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_45\,
      req_wr_r_lcl_reg_1 => \bank_cntrl[3].bank0_n_46\,
      \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[0].bank0_n_73\,
      rnk_config_valid_r_lcl_reg => arb_mux0_n_92,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \starve_limit_cntr_r_reg[2]\ => col_wait_r,
      tail_r => tail_r,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg => \^head_r\(0),
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg,
      wr_this_rank_r(0) => wr_this_rank_r(0),
      \wtr_timer.wtr_cnt_r_reg[1]\ => arb_mux0_n_113
    );
\bank_cntrl[1].bank0\: entity work.\mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized0\
     port map (
      CLK => CLK,
      D(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_1\(5),
      E(0) => \^idle_r\(1),
      Q(0) => rb_hit_busies_r_18(5),
      SR(0) => SR(0),
      accept_internal_r_reg => \^accept_internal_r\,
      accept_r_reg => accept_r_reg,
      act_this_rank_r(0) => act_this_rank_r(1),
      \act_this_rank_r_reg[0]\ => \^row_cmd_wr\(1),
      act_wait_r_lcl_reg => pass_open_bank_r_2,
      act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg_2\,
      act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_3,
      act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_6,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]\(0),
      \app_addr_r1_reg[23]_0\(13 downto 0) => \app_addr_r1_reg[23]_2\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      auto_pre_r => auto_pre_r_5,
      auto_pre_r_lcl_reg => wait_for_maint_r_16,
      auto_pre_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_58\,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_reg => \^ordered_r_lcl_reg\(1),
      bm_end_r1_reg_0 => pre_bm_end_r_3,
      bm_end_r1_reg_1 => \bank_cntrl[0].bank0_n_36\,
      bm_end_r1_reg_2 => \bank_cntrl[3].bank0_n_32\,
      bm_end_r1_reg_3 => \bank_cntrl[2].bank0_n_31\,
      bm_end_r1_reg_4 => bm_end_r1_reg_0,
      \cmd_pipe_plus.mc_address_reg[13]\(13 downto 12) => \^cmd_pipe_plus.mc_address_reg[41]_0\(6 downto 5),
      \cmd_pipe_plus.mc_address_reg[13]\(11 downto 6) => req_row_r(25 downto 20),
      \cmd_pipe_plus.mc_address_reg[13]\(5 downto 3) => \^cmd_pipe_plus.mc_address_reg[41]_0\(4 downto 2),
      \cmd_pipe_plus.mc_address_reg[13]\(2 downto 0) => req_row_r(16 downto 14),
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \bank_compare0/req_col_r_2\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[38]\ => \bank_cntrl[1].bank0_n_73\,
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \^cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(9 downto 5),
      col_wait_r_reg => col_wait_r_reg_0,
      col_wait_r_reg_0 => col_wait_r_reg_3,
      \compute_tail.tail_r_lcl_reg\ => \compute_tail.tail_r_lcl_reg\,
      demand_priority_r_reg => \^demand_priority_r_1\,
      demand_priority_r_reg_0 => \^demand_priority_r_12\,
      demanded_prior_r_reg => \^demanded_prior_r\,
      demanded_prior_r_reg_0 => \^demanded_prior_r_reg_0\,
      demanded_prior_r_reg_1 => \^demanded_prior_r_13\,
      \grant_r_reg[1]\ => \bank_cntrl[1].bank0_n_30\,
      \grant_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_53\,
      \grant_r_reg[1]_1\ => \bank_cntrl[1].bank0_n_57\,
      \grant_r_reg[1]_2\(1 downto 0) => sending_pre(1 downto 0),
      \grant_r_reg[1]_3\ => arb_mux0_n_87,
      \grant_r_reg[1]_4\(0) => \^last_master_r_reg[3]\(1),
      \grant_r_reg[2]\ => \bank_cntrl[1].bank0_n_56\,
      \grant_r_reg[3]\(2) => \^q\(3),
      \grant_r_reg[3]\(1 downto 0) => \^q\(1 downto 0),
      \grant_r_reg[3]_0\ => \grant_r_reg[3]_1\,
      granted_col_r_reg => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      granted_row_ns => granted_row_ns,
      granted_row_r_reg => \bank_cntrl[1].bank0_n_52\,
      head_r_lcl_reg => head_r_lcl_reg_4,
      head_r_lcl_reg_0 => head_r_lcl_reg_5,
      head_r_lcl_reg_1 => head_r_lcl_reg_8,
      hi_priority => hi_priority,
      idle_r_lcl_reg => idle_r_lcl_reg_0,
      idle_r_lcl_reg_0 => \^rb_hit_busy_r_reg_0\,
      idle_r_lcl_reg_1 => \^rb_hit_busy_r_reg_1\,
      idle_r_lcl_reg_2 => \^accept_internal_r_reg\,
      idle_r_lcl_reg_3(0) => \^idle_r\(0),
      idle_r_lcl_reg_4(0) => \^idle_r\(2),
      idle_r_lcl_reg_5(0) => \^idle_r\(3),
      idle_r_lcl_reg_6 => bank_common0_n_17,
      idle_r_lcl_reg_7 => idle_r_lcl_reg_5,
      idle_r_lcl_reg_8 => idle_r_lcl_reg_6,
      \last_master_r_reg[0]\ => arb_mux0_n_80,
      \maint_controller.maint_hit_busies_r_reg[3]\(3 downto 0) => \maint_controller.maint_hit_busies_r_reg[3]_0\(3 downto 0),
      \maint_controller.maint_rdy\ => \maint_controller.maint_rdy\,
      \maint_controller.maint_wip_r_lcl_reg\ => \^maint_wip_r\,
      \maint_controller.maint_wip_r_lcl_reg_0\ => \^auto_pre_r_lcl_reg\,
      maint_req_r => maint_req_r,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r_6\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0\,
      ordered_r(0) => ordered_r(1),
      ordered_r_lcl_reg => \bank_cntrl[2].bank0_n_46\,
      ordered_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_44\,
      override_demand_r => \^override_demand_r\,
      periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_0 => \^periodic_rd_ack_r\,
      periodic_rd_ack_r_lcl_reg_1 => \^ordered_r_lcl_reg_2\,
      periodic_rd_ack_r_lcl_reg_2 => \^q_entry_r_reg[1]_2\,
      periodic_rd_insert => periodic_rd_insert,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[1].bank0_n_55\,
      pre_bm_end_r_reg => \^act_wait_r_lcl_reg\,
      pre_bm_end_r_reg_0 => \^p_13_out\,
      pre_bm_end_r_reg_1 => \^p_52_out\,
      pre_passing_open_bank_r_reg => \bank_cntrl[3].bank0_n_45\,
      pre_passing_open_bank_r_reg_0 => \bank_cntrl[0].bank0_n_55\,
      q_entry_ns(0) => \bank_queue0/q_entry_ns\(1),
      \q_entry_r_reg[0]\ => \^q_entry_r_reg[0]\,
      \q_entry_r_reg[0]_0\ => \bank_cntrl[1].bank0_n_36\,
      \q_entry_r_reg[0]_1\ => \^q_entry_r_reg[0]_1\,
      \q_entry_r_reg[1]\ => \bank_cntrl[1].bank0_n_37\,
      \q_entry_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_41\,
      q_has_priority_5 => q_has_priority_5,
      q_has_priority_r_reg => \^rb_hit_busy_r\(1),
      q_has_priority_r_reg_0 => q_has_priority_r_reg_0,
      q_has_rd_4 => q_has_rd_4,
      q_has_rd_r_reg => q_has_rd_r_reg_0,
      \ras_timer_r_reg[0]\ => \bank_cntrl[1].bank0_n_31\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[1].bank0_n_33\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[1].bank0_n_34\,
      \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_2\,
      ras_timer_zero_r_reg => \bank_cntrl[1].bank0_n_44\,
      ras_timer_zero_r_reg_0 => \bank_cntrl[1].bank0_n_45\,
      ras_timer_zero_r_reg_1 => ras_timer_zero_r_reg_2,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_4\(1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\(0) => rb_hit_busies_r(1),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \^act_wait_r_lcl_reg_4\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\(2 downto 0) => rb_hit_busies_r_3(4 downto 2),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => \^act_wait_r_lcl_reg_5\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\(2 downto 0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns\(4 downto 2),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_0\(5),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\(0) => rb_hit_busies_r_12(5),
      rb_hit_busy_r_reg => \^rb_hit_busy_r_reg\,
      rb_hit_busy_r_reg_0 => \bank_cntrl[0].bank0_n_48\,
      rb_hit_busy_r_reg_1 => \bank_cntrl[0].bank0_n_50\,
      rd_this_rank_r(0) => rd_this_rank_r(1),
      \rd_this_rank_r_reg[0]\ => \^rd_this_rank_r_reg[0]\(1),
      rd_wr_r_lcl_reg => arb_mux0_n_23,
      rd_wr_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_35\,
      rd_wr_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_30\,
      rd_wr_r_lcl_reg_2 => \bank_cntrl[3].bank0_n_31\,
      rd_wr_r_lcl_reg_3 => \^rd_this_rank_r_reg[0]\(0),
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]\,
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns_7\,
      req_bank_rdy_r => \bank_state0/req_bank_rdy_r_8\,
      req_bank_rdy_r_reg => \bank_cntrl[1].bank0_n_54\,
      req_bank_rdy_r_reg_0 => arb_mux0_n_98,
      req_periodic_rd_r(0) => req_periodic_rd_r(1),
      \req_row_r_lcl_reg[10]\(0) => req_row_r(10),
      \req_row_r_lcl_reg[3]\(0) => \req_row_r_lcl_reg[3]\(0),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => req_wr_r_lcl_reg,
      req_wr_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_45\,
      req_wr_r_lcl_reg_1 => \bank_cntrl[3].bank0_n_46\,
      req_wr_r_lcl_reg_2(0) => \^ordered_r_lcl_reg\(0),
      \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[1].bank0_n_72\,
      rnk_config_valid_r_lcl_reg => arb_mux0_n_91,
      row_cmd_wr(0) => \^row_cmd_wr\(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \starve_limit_cntr_r_reg[2]\ => col_wait_r_0,
      tail_r_19 => tail_r_19,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg => \^head_r\(1),
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_0,
      wait_for_maint_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_48\,
      wr_this_rank_r(0) => wr_this_rank_r(1),
      \wtr_timer.wtr_cnt_r_reg[1]\ => arb_mux0_n_113
    );
\bank_cntrl[2].bank0\: entity work.\mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized1\
     port map (
      CLK => CLK,
      D(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_1\(6),
      E(0) => \^idle_r\(2),
      Q(0) => rb_hit_busies_r_18(6),
      SR(0) => SR(0),
      accept_internal_r_reg => \^accept_internal_r\,
      accept_r_reg => \^pass_open_bank_r_lcl_reg_2\,
      act_this_rank_r(0) => act_this_rank_r(2),
      \act_this_rank_r_reg[0]\ => \^row_cmd_wr\(2),
      act_wait_r_lcl_reg => \^act_wait_r_lcl_reg_4\,
      act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg_1\,
      act_wait_r_lcl_reg_1 => \bank_cntrl[3].bank0_n_65\,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]_0\(0),
      \app_addr_r1_reg[23]_0\(13 downto 0) => \app_addr_r1_reg[23]_2\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      auto_pre_r => auto_pre_r_13,
      auto_pre_r_lcl_reg => wait_for_maint_r_17,
      auto_pre_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_48\,
      bm_end_r1_1 => bm_end_r1_1,
      bm_end_r1_reg => \^p_52_out\,
      bm_end_r1_reg_0 => \bank_cntrl[1].bank0_n_45\,
      bm_end_r1_reg_1 => \bank_cntrl[0].bank0_n_36\,
      bm_end_r1_reg_2 => \bank_cntrl[3].bank0_n_32\,
      bm_end_r1_reg_3 => bm_end_r1_reg_1,
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \bank_compare0/req_col_r_9\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[38]\(0) => \cmd_pipe_plus.mc_address_reg[41]\(28),
      \cmd_pipe_plus.mc_address_reg[41]\(13 downto 12) => \^cmd_pipe_plus.mc_address_reg[41]_0\(8 downto 7),
      \cmd_pipe_plus.mc_address_reg[41]\(11 downto 0) => req_row_r(39 downto 28),
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \^cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(14 downto 10),
      col_wait_r_reg => col_wait_r_reg_1,
      demand_priority_r => \^demand_priority_r\,
      demand_priority_r_reg => \^demand_priority_r_7\,
      demanded_prior_r => \bank_state0/demanded_prior_r\,
      demanded_prior_r_reg => \^demanded_prior_r_8\,
      demanded_prior_r_reg_0 => \^demanded_prior_r_reg\,
      \grant_r_reg[0]\ => \bank_cntrl[2].bank0_n_40\,
      \grant_r_reg[0]_0\ => \bank_cntrl[2].bank0_n_50\,
      \grant_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_75\,
      \grant_r_reg[2]\ => \bank_cntrl[2].bank0_n_28\,
      \grant_r_reg[2]_0\ => \bank_cntrl[2].bank0_n_49\,
      \grant_r_reg[2]_1\ => arb_mux0_n_86,
      \grant_r_reg[2]_2\(0) => \^last_master_r_reg[3]\(2),
      \grant_r_reg[3]\(2 downto 1) => \^q\(3 downto 2),
      \grant_r_reg[3]\(0) => \^q\(0),
      \grant_r_reg[3]_0\(1) => \^cmd_pipe_plus.mc_address_reg[28]\(0),
      \grant_r_reg[3]_0\(0) => sending_pre(2),
      \grant_r_reg[3]_1\ => arb_mux0_n_76,
      granted_col_r_reg => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      granted_row_r_reg => \bank_cntrl[2].bank0_n_48\,
      head_r_lcl_reg => head_r_lcl_reg_1,
      head_r_lcl_reg_0 => head_r_lcl_reg_9,
      hi_priority => hi_priority,
      idle_r_lcl_reg => idle_r_lcl_reg_1,
      idle_r_lcl_reg_0 => \^rb_hit_busy_r_reg_0\,
      idle_r_lcl_reg_1 => \^accept_internal_r_reg\,
      idle_r_lcl_reg_2 => \^rb_hit_busy_r_reg\,
      idle_r_lcl_reg_3 => bank_common0_n_13,
      idle_r_lcl_reg_4 => \bank_cntrl[1].bank0_n_37\,
      idle_r_lcl_reg_5 => \bank_cntrl[1].bank0_n_36\,
      \maint_controller.maint_wip_r_lcl_reg\ => \^auto_pre_r_lcl_reg\,
      \maint_controller.maint_wip_r_lcl_reg_0\ => \^maint_wip_r\,
      maint_req_r => maint_req_r,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r_14\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_11\,
      ofs_rdy_r0_0 => \bank_state0/ofs_rdy_r0_10\,
      ofs_rdy_r0_1 => \bank_state0/ofs_rdy_r0\,
      \order_q_r_reg[0]\ => \bank_cntrl[2].bank0_n_44\,
      \order_q_r_reg[1]\ => \bank_cntrl[2].bank0_n_46\,
      ordered_r_lcl_reg(2) => ordered_r(3),
      ordered_r_lcl_reg(1 downto 0) => ordered_r(1 downto 0),
      override_demand_ns => \bank_state0/override_demand_ns\,
      override_demand_r => \^override_demand_r\,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg => \^ordered_r_lcl_reg_1\,
      periodic_rd_ack_r_lcl_reg_0 => \^q_entry_r_reg[1]_2\,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_2 => \^periodic_rd_ack_r\,
      periodic_rd_insert => periodic_rd_insert,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\,
      pre_bm_end_r_reg => \^q_entry_r_reg[0]\,
      pre_bm_end_r_reg_0 => \^p_13_out\,
      pre_bm_end_r_reg_1 => \^act_wait_r_lcl_reg\,
      pre_passing_open_bank_r_reg => \bank_cntrl[3].bank0_n_45\,
      pre_passing_open_bank_r_reg_0 => \bank_cntrl[0].bank0_n_55\,
      \q_entry_r_reg[1]\ => \bank_cntrl[2].bank0_n_36\,
      \q_entry_r_reg[1]_0\ => \bank_cntrl[2].bank0_n_37\,
      \q_entry_r_reg[1]_1\ => \q_entry_r_reg[1]_3\,
      \q_entry_r_reg[1]_2\ => \bank_cntrl[0].bank0_n_44\,
      q_has_priority_10 => q_has_priority_10,
      q_has_priority_r_reg => \^rb_hit_busy_r\(2),
      q_has_priority_r_reg_0 => q_has_priority_r_reg_1,
      q_has_rd_9 => q_has_rd_9,
      q_has_rd_r_reg => q_has_rd_r_reg_1,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]_1\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[2].bank0_n_43\,
      ras_timer_zero_r_reg => \bank_cntrl[2].bank0_n_30\,
      ras_timer_zero_r_reg_0 => \bank_cntrl[2].bank0_n_31\,
      ras_timer_zero_r_reg_1 => \bank_cntrl[1].bank0_n_55\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_4\(2),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns\(2),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\(0) => rb_hit_busies_r(2),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2\(0) => rb_hit_busies_r_3(2),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \bank_cntrl[3].bank0_n_44\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => \bank_cntrl[0].bank0_n_54\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\(2 downto 0) => rb_hit_busies_r_12(5 downto 3),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \bank_cntrl[1].bank0_n_33\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\(2 downto 0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_0\(5 downto 3),
      rb_hit_busy_r_reg => \^rb_hit_busy_r_reg_1\,
      rb_hit_busy_r_reg_0 => \bank_cntrl[0].bank0_n_50\,
      rb_hit_busy_r_reg_1 => \bank_cntrl[0].bank0_n_48\,
      rd_this_rank_r(0) => rd_this_rank_r(2),
      rd_wr_r(0) => rd_wr_r(2),
      rd_wr_r_lcl_reg => arb_mux0_n_23,
      rd_wr_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_44\,
      rd_wr_r_lcl_reg_1 => \bank_cntrl[3].bank0_n_31\,
      rd_wr_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_35\,
      rd_wr_r_lcl_reg_3 => \bank_cntrl[1].bank0_n_54\,
      rd_wr_r_lcl_reg_4(0) => rd_wr_r(3),
      rd_wr_r_lcl_reg_5 => \^rd_this_rank_r_reg[0]\(0),
      rd_wr_r_lcl_reg_6(0) => \^rd_this_rank_r_reg[0]\(1),
      \req_bank_r_lcl_reg[2]\ => \req_bank_r_lcl_reg[2]\,
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns_15\,
      req_bank_rdy_r => \bank_state0/req_bank_rdy_r_16\,
      req_bank_rdy_r_reg => \bank_cntrl[2].bank0_n_45\,
      req_bank_rdy_r_reg_0 => arb_mux0_n_99,
      req_periodic_rd_r(0) => req_periodic_rd_r(2),
      \req_row_r_lcl_reg[10]\ => \bank_cntrl[1].bank0_n_73\,
      req_wr_r(0) => req_wr_r(2),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => \bank_cntrl[3].bank0_n_46\,
      req_wr_r_lcl_reg_0 => \^ordered_r_lcl_reg\(2),
      \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[2].bank0_n_65\,
      rnk_config_valid_r_lcl_reg => arb_mux0_n_89,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \starve_limit_cntr_r_reg[2]\ => col_wait_r_6,
      tail_r_20 => tail_r_20,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg => \^head_r\(2),
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_1,
      wr_this_rank_r(0) => wr_this_rank_r(2),
      \wtr_timer.wtr_cnt_r_reg[1]\ => arb_mux0_n_113
    );
\bank_cntrl[3].bank0\: entity work.\mig_7series_0_mig_7series_v2_3_bank_cntrl__parameterized2\
     port map (
      CLK => CLK,
      D(2 downto 0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_1\(6 downto 4),
      E(0) => \^idle_r\(3),
      Q(2 downto 0) => \^q\(3 downto 1),
      SR(0) => SR(0),
      accept_internal_r_reg => \^accept_internal_r\,
      accept_r_reg => \^pass_open_bank_r_lcl_reg_1\,
      act_this_rank_r(0) => act_this_rank_r(3),
      \act_this_rank_r_reg[0]\ => \^row_cmd_wr\(3),
      act_wait_r_lcl_reg => act_wait_r_lcl_reg_0,
      act_wait_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_42\,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]_1\(0),
      \app_addr_r1_reg[23]_0\(13 downto 0) => \app_addr_r1_reg[23]_2\(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      auto_pre_r => auto_pre_r_19,
      auto_pre_r_lcl_reg => wait_for_maint_r_18,
      bm_end_r1_reg => \^p_13_out\,
      bm_end_r1_reg_0 => \bank_cntrl[2].bank0_n_31\,
      bm_end_r1_reg_1 => \bank_cntrl[1].bank0_n_45\,
      bm_end_r1_reg_2 => \bank_cntrl[0].bank0_n_36\,
      bm_end_r1_reg_3 => bm_end_r1_reg_2,
      \cmd_pipe_plus.mc_address_reg[10]\ => \bank_cntrl[3].bank0_n_62\,
      \cmd_pipe_plus.mc_address_reg[23]\(9 downto 0) => \bank_compare0/req_col_r_17\(9 downto 0),
      \cmd_pipe_plus.mc_address_reg[38]\ => \bank_cntrl[3].bank0_n_65\,
      \cmd_pipe_plus.mc_address_reg[41]\(12 downto 11) => \^cmd_pipe_plus.mc_address_reg[41]_0\(10 downto 9),
      \cmd_pipe_plus.mc_address_reg[41]\(10) => req_row_r(53),
      \cmd_pipe_plus.mc_address_reg[41]\(9 downto 0) => req_row_r(51 downto 42),
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \^cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \col_mux.col_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(19 downto 15),
      col_wait_r_reg => col_wait_r_reg_2,
      col_wait_r_reg_0 => col_wait_r_reg_4,
      cs_en2 => \^cs_en2\,
      demand_priority_r_reg => \^demand_priority_r_12\,
      demand_priority_r_reg_0 => \^demand_priority_r_1\,
      demanded_prior_r => \^demanded_prior_r\,
      demanded_prior_r_reg => \^demanded_prior_r_13\,
      demanded_prior_r_reg_0 => \^demanded_prior_r_reg\,
      demanded_prior_r_reg_1 => \^demanded_prior_r_reg_0\,
      \grant_r_reg[1]\ => \grant_r_reg[1]\,
      \grant_r_reg[2]\ => \bank_cntrl[3].bank0_n_44\,
      \grant_r_reg[3]\ => \bank_cntrl[3].bank0_n_29\,
      \grant_r_reg[3]_0\ => \bank_cntrl[3].bank0_n_46\,
      \grant_r_reg[3]_1\ => \bank_cntrl[3].bank0_n_47\,
      \grant_r_reg[3]_2\(0) => \^cmd_pipe_plus.mc_address_reg[28]\(0),
      \grant_r_reg[3]_3\(0) => \^last_master_r_reg[3]\(3),
      \grant_r_reg[3]_4\ => arb_mux0_n_73,
      granted_col_r_reg => \bank_cntrl[3].bank0_n_28\,
      granted_col_r_reg_0 => \^cmd_pipe_plus.mc_cmd_reg[0]\,
      head_r_lcl_reg => head_r_lcl_reg_0,
      head_r_lcl_reg_0 => head_r_lcl_reg_10,
      hi_priority => hi_priority,
      idle_r_lcl_reg => idle_r_lcl_reg_2,
      idle_r_lcl_reg_0 => \^accept_internal_r_reg\,
      idle_r_lcl_reg_1 => \^rb_hit_busy_r_reg_1\,
      idle_r_lcl_reg_2 => \^rb_hit_busy_r_reg\,
      idle_r_lcl_reg_3 => \bank_cntrl[0].bank0_n_40\,
      idle_r_lcl_reg_4 => bank_common0_n_11,
      idle_r_lcl_reg_5 => \bank_cntrl[0].bank0_n_42\,
      idle_r_lcl_reg_6 => idle_r_lcl_reg_7,
      \maint_controller.maint_wip_r_lcl_reg\ => \^auto_pre_r_lcl_reg\,
      \maint_controller.maint_wip_r_lcl_reg_0\ => \^maint_wip_r\,
      maint_req_r => maint_req_r,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      ofs_rdy_r => \bank_state0/ofs_rdy_r_20\,
      ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_10\,
      ordered_r_lcl_reg => \^ordered_r_lcl_reg\(2),
      ordered_r_lcl_reg_0(0) => ordered_r(3),
      ordered_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_46\,
      ordered_r_lcl_reg_2 => \bank_cntrl[2].bank0_n_44\,
      override_demand_r_reg => override_demand_r_reg_0,
      pass_open_bank_r_lcl_reg => pass_open_bank_r_lcl_reg_0,
      periodic_rd_ack_r_lcl_reg => \^ordered_r_lcl_reg_0\,
      periodic_rd_ack_r_lcl_reg_0 => \^q_entry_r_reg[1]_2\,
      periodic_rd_ack_r_lcl_reg_1 => periodic_rd_ack_r_lcl_reg,
      periodic_rd_ack_r_lcl_reg_2 => \^periodic_rd_ack_r\,
      periodic_rd_insert => periodic_rd_insert,
      \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[3].bank0_n_48\,
      pre_bm_end_r_reg => \^q_entry_r_reg[0]\,
      pre_bm_end_r_reg_0 => \^p_52_out\,
      pre_bm_end_r_reg_1 => \^act_wait_r_lcl_reg\,
      pre_bm_end_r_reg_2 => pre_bm_end_r_reg,
      pre_passing_open_bank_r_reg => \bank_cntrl[0].bank0_n_55\,
      pre_passing_open_bank_r_reg_0 => \bank_cntrl[1].bank0_n_34\,
      \q_entry_r_reg[1]\ => \bank_cntrl[3].bank0_n_38\,
      \q_entry_r_reg[1]_0\ => \q_entry_r_reg[1]_1\,
      q_has_priority_15 => q_has_priority_15,
      q_has_priority_r_reg => \^rb_hit_busy_r\(3),
      q_has_priority_r_reg_0 => q_has_priority_r_reg_2,
      q_has_rd_14 => q_has_rd_14,
      q_has_rd_r_reg => q_has_rd_r_reg_2,
      \ras_timer_r_reg[0]\ => \ras_timer_r_reg[0]_0\,
      \ras_timer_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_31\,
      \ras_timer_r_reg[0]_1\ => \bank_cntrl[3].bank0_n_45\,
      \ras_timer_r_reg[1]\ => \bank_cntrl[3].bank0_n_32\,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_1,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_4\(3),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns_0\(3),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\(0) => \bank_queue0/rb_hit_busies.rb_hit_busies_ns\(3),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0) => rb_hit_busies_r(3),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3\(0) => rb_hit_busies_r_12(3),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4\(0) => rb_hit_busies_r_3(3),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \^act_wait_r_lcl_reg_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\(2 downto 0) => rb_hit_busies_r_18(6 downto 4),
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \^act_wait_r_lcl_reg_1\,
      rb_hit_busy_r(2 downto 0) => \^rb_hit_busy_r\(2 downto 0),
      rb_hit_busy_r_reg => \^rb_hit_busy_r_reg_0\,
      rb_hit_busy_r_reg_0 => \bank_cntrl[0].bank0_n_48\,
      rb_hit_busy_r_reg_1 => \bank_cntrl[0].bank0_n_50\,
      rd_this_rank_r(0) => rd_this_rank_r(3),
      \rd_this_rank_r_reg[0]\(0) => rd_wr_r(3),
      rd_wr_r(0) => rd_wr_r(2),
      rd_wr_r_lcl_reg => \bank_cntrl[2].bank0_n_28\,
      rd_wr_r_lcl_reg_0 => arb_mux0_n_23,
      rd_wr_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_30\,
      rd_wr_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_35\,
      rd_wr_r_lcl_reg_3 => \bank_cntrl[1].bank0_n_44\,
      rd_wr_r_lcl_reg_4 => \bank_cntrl[1].bank0_n_54\,
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]_0\,
      req_bank_rdy_ns => \bank_state0/req_bank_rdy_ns_21\,
      req_bank_rdy_r => \bank_state0/req_bank_rdy_r_22\,
      req_bank_rdy_r_reg => arb_mux0_n_100,
      req_periodic_rd_r(0) => req_periodic_rd_r(3),
      \req_row_r_lcl_reg[10]\(0) => req_row_r(24),
      req_wr_r(0) => req_wr_r(2),
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => \bank_cntrl[2].bank0_n_45\,
      \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[3].bank0_n_64\,
      rnk_config_valid_r_lcl_reg => arb_mux0_n_90,
      row_cmd_wr(0) => \^row_cmd_wr\(1),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \starve_limit_cntr_r_reg[2]\ => col_wait_r_11,
      tail_r_21 => tail_r_21,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg => \^head_r\(3),
      wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_2,
      wr_this_rank_r(0) => wr_this_rank_r(3),
      \wtr_timer.wtr_cnt_r_reg[1]\ => arb_mux0_n_113
    );
bank_common0: entity work.mig_7series_0_mig_7series_v2_3_bank_common
     port map (
      CLK => CLK,
      E(0) => \^idle_r\(3),
      Q(1) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\(2),
      Q(0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\(0),
      SR(0) => SR(0),
      accept_ns => accept_ns,
      app_rdy_r_reg => app_rdy_r_reg,
      auto_pre_r_lcl_reg => \^auto_pre_r_lcl_reg\,
      cmd(1 downto 0) => cmd(1 downto 0),
      \generate_maint_cmds.insert_maint_r_lcl_reg_0\(1 downto 0) => \generate_maint_cmds.insert_maint_r_lcl_reg\(1 downto 0),
      head_r(3 downto 0) => \^head_r\(3 downto 0),
      head_r_lcl_reg => bank_common0_n_11,
      head_r_lcl_reg_0 => bank_common0_n_13,
      head_r_lcl_reg_1 => bank_common0_n_17,
      hi_priority => hi_priority,
      idle_r_lcl_reg(0) => \^idle_r\(2),
      idle_r_lcl_reg_0(0) => \^idle_r\(0),
      idle_r_lcl_reg_1(0) => \^idle_r\(1),
      idle_r_lcl_reg_2 => idle_r_lcl_reg_4,
      insert_maint_r1_lcl_reg => \^insert_maint_r\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(3 downto 0) => \maint_controller.maint_hit_busies_r_reg[3]\(3 downto 0),
      \maint_controller.maint_hit_busies_r_reg[3]_1\(3 downto 0) => \maint_controller.maint_hit_busies_r_reg[3]_0\(3 downto 0),
      \maint_controller.maint_rdy\ => \maint_controller.maint_rdy\,
      \maint_controller.maint_rdy_r1_reg_0\ => \^maint_wip_r\,
      maint_req_r => maint_req_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      \maintenance_request.maint_req_r_lcl_reg\ => \maintenance_request.maint_req_r_lcl_reg\,
      \maintenance_request.maint_srx_r_lcl_reg\ => \maintenance_request.maint_srx_r_lcl_reg\,
      ordered_r_lcl_reg => \^ordered_r_lcl_reg_0\,
      ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg_1\,
      ordered_r_lcl_reg_1 => \^ordered_r_lcl_reg_2\,
      p_7_in => p_7_in,
      pass_open_bank_r_lcl_reg => \^pass_open_bank_r_lcl_reg_1\,
      pass_open_bank_r_lcl_reg_0 => \^pass_open_bank_r_lcl_reg_2\,
      periodic_rd_insert => periodic_rd_insert,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_r_lcl_reg\ => \periodic_read_request.periodic_rd_r_lcl_reg\,
      pre_bm_end_r_reg => \^act_wait_r_lcl_reg\,
      \q_entry_r_reg[0]\ => bank_common0_n_15,
      \q_entry_r_reg[0]_0\ => \^q_entry_r_reg[0]_0\,
      \q_entry_r_reg[0]_1\ => bank_common0_n_30,
      \q_entry_r_reg[0]_2\(0) => q_entry_r(0),
      \q_entry_r_reg[1]\ => \q_entry_r_reg[1]\,
      \q_entry_r_reg[1]_0\ => \^q_entry_r_reg[1]_2\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ => \^head_r_lcl_reg_3\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => \^q_entry_r_reg[0]_1\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[3].bank0_n_38\,
      \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \bank_cntrl[2].bank0_n_36\,
      rb_hit_busy_r(1 downto 0) => \^rb_hit_busy_r\(3 downto 2),
      rb_hit_busy_r_reg => \bank_cntrl[0].bank0_n_51\,
      req_wr_r_lcl0 => \bank_compare0/req_wr_r_lcl0\,
      req_wr_r_lcl_reg => \^periodic_rd_ack_r\,
      req_wr_r_lcl_reg_0 => periodic_rd_cntr_r,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_1\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\(1),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_2\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\(0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\(3),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      use_addr => use_addr,
      wait_for_maint_r_lcl_reg => \^accept_internal_r\,
      was_priority => was_priority,
      was_wr => was_wr
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_mc_phy is
  port (
    out_dqs_4 : out STD_LOGIC;
    ts_dqs_4 : out STD_LOGIC;
    ofifo_rst_reg : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    mem_dq_out : out STD_LOGIC_VECTOR ( 94 downto 0 );
    mem_dq_ts : out STD_LOGIC_VECTOR ( 71 downto 0 );
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 7 downto 0 );
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    out_dqs_3 : out STD_LOGIC;
    ts_dqs_3 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    idelay_ld_rst_0 : out STD_LOGIC;
    out_dqs_2 : out STD_LOGIC;
    ts_dqs_2 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    idelay_ld_rst_1 : out STD_LOGIC;
    out_dqs_1 : out STD_LOGIC;
    ts_dqs_1 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    idelay_ld_rst_2 : out STD_LOGIC;
    out_dqs_0 : out STD_LOGIC;
    ts_dqs_0 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    idelay_ld_rst_3 : out STD_LOGIC;
    out_dqs_7 : out STD_LOGIC;
    ts_dqs_7 : out STD_LOGIC;
    \pi_dqs_found_lanes_r1_reg[10]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : out STD_LOGIC;
    out_dqs_6 : out STD_LOGIC;
    ts_dqs_6 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ : out STD_LOGIC;
    out_dqs_5 : out STD_LOGIC;
    ts_dqs_5 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ : out STD_LOGIC;
    idelay_ld_rst_5 : out STD_LOGIC;
    phy_mc_go : out STD_LOGIC;
    \my_empty_reg[1]\ : out STD_LOGIC;
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    \my_empty_reg[1]_3\ : out STD_LOGIC;
    \my_empty_reg[1]_4\ : out STD_LOGIC;
    \my_empty_reg[1]_5\ : out STD_LOGIC;
    \my_empty_reg[1]_6\ : out STD_LOGIC;
    \my_empty_reg[1]_7\ : out STD_LOGIC;
    \my_empty_reg[1]_8\ : out STD_LOGIC;
    \not_strict_mode.rd_buf_we\ : out STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : out STD_LOGIC;
    rst_sync_r1_reg : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[8]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[16]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[56]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[48]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[24]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[32]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[42]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[50]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[26]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[34]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[10]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[18]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[58]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[44]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[52]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[28]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[36]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[12]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[20]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[60]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[46]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[54]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[30]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[38]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[14]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[22]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[62]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[104]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[112]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[88]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[96]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[72]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[80]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[120]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[64]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[106]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[114]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[90]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[98]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[74]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[82]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[122]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[66]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[108]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[116]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[92]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[100]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[76]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[84]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[124]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[68]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[110]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[118]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[94]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[102]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[78]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[86]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[126]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[70]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[168]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[176]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[152]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[160]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[136]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[144]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[184]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[128]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[170]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[178]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[154]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[162]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[138]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[146]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[186]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[130]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[172]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[180]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[156]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[164]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[140]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[148]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[188]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[132]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[142]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[150]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[190]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[134]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[174]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[182]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[158]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[166]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[232]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[240]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[216]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[224]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[200]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[208]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[248]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[192]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[234]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[242]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[218]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[226]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[202]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[210]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[250]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[194]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[236]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[244]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[220]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[228]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[204]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[212]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[252]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[196]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[238]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[246]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[222]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[230]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[206]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[214]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[254]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[198]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[296]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[304]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[280]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[288]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[264]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[272]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[312]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[256]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[298]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[306]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[282]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[290]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[266]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[274]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[314]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[258]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[300]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[308]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[284]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[292]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[268]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[276]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[316]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[260]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[270]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[278]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[318]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[262]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[302]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[310]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[286]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[294]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[360]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[368]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[344]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[352]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[328]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[336]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[376]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[320]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[362]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[370]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[346]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[354]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[330]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[338]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[378]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[322]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[364]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[372]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[348]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[356]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[332]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[340]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[380]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[324]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[366]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[374]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[350]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[358]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[334]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[342]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[382]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[326]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[392]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[400]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[440]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[384]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[424]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[432]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[408]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[416]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[426]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[434]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[410]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[418]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[394]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[402]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[442]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[386]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[428]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[436]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[412]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[420]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[396]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[404]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[444]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[388]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[430]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[438]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[414]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[422]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[398]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[406]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[446]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[390]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[488]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[496]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[472]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[480]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[456]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[464]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[504]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[448]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[458]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[466]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[506]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[450]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[490]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[498]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[474]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[482]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[492]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[500]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[476]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[484]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[460]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[468]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[508]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[452]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[494]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[502]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[478]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[486]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[462]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[470]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[510]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[454]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC;
    \my_empty_reg[1]_9\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    p_110_in : out STD_LOGIC;
    store_sr_req_r_reg : out STD_LOGIC;
    \pi_rdval_cnt_reg[2]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[3]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[1]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[0]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[5]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC_VECTOR ( 511 downto 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    mem_out : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    \my_empty_reg[7]_0\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_2\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_3\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_4\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_5\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_6\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_rdval_cnt_reg[0]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[1]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[2]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[3]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[4]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[5]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[6]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[7]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[8]\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    mem_dq_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    mem_dqs_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC;
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[487]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[486]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[485]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[420]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[483]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[482]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[481]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[416]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_1\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_0 : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.calib_in_common_reg_2\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_3\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_1 : in STD_LOGIC;
    D0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \init_calib_complete_reg_rep__11_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_ctl_wr_i2 : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    in0 : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \data_offset_1_i2_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    RST0 : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    LD0_6 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    \calib_sel_reg[1]_6\ : in STD_LOGIC;
    \calib_sel_reg[1]_7\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_0 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_0 : in STD_LOGIC;
    \calib_sel_reg[1]_8\ : in STD_LOGIC;
    \calib_sel_reg[1]_9\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_10\ : in STD_LOGIC;
    \calib_sel_reg[1]_11\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_2 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[479]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[478]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[477]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[412]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[475]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[474]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[473]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[408]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \calib_sel_reg[1]_12\ : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    \calib_sel_reg[1]_13\ : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_1 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_1 : in STD_LOGIC;
    \calib_sel_reg[1]_14\ : in STD_LOGIC;
    \calib_sel_reg[1]_15\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_16\ : in STD_LOGIC;
    \calib_sel_reg[1]_17\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_3 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[471]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[470]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[469]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[404]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[467]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[466]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[465]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[400]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_18\ : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    \calib_sel_reg[1]_19\ : in STD_LOGIC;
    \calib_sel_reg[1]_20\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_2 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_2 : in STD_LOGIC;
    \calib_sel_reg[1]_21\ : in STD_LOGIC;
    \calib_sel_reg[1]_22\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_23\ : in STD_LOGIC;
    \calib_sel_reg[1]_24\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_4 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[463]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[462]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[461]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[396]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[459]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[458]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[457]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[392]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    idelay_ce_r2_reg : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    pi_stg2_load_reg : in STD_LOGIC;
    \calib_sel_reg[1]_25\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_3 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_3 : in STD_LOGIC;
    \pi_rst_stg1_cal_reg[0]\ : in STD_LOGIC;
    \pi_stg2_reg_l_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg : in STD_LOGIC;
    \calib_sel_reg[0]_0\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_5 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[455]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[454]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[453]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[388]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[451]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[450]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[449]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[384]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_26\ : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    \calib_sel_reg[1]_27\ : in STD_LOGIC;
    \calib_sel_reg[1]_28\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_4 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_4 : in STD_LOGIC;
    \calib_sel_reg[1]_29\ : in STD_LOGIC;
    \calib_sel_reg[1]_30\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_31\ : in STD_LOGIC;
    \calib_sel_reg[1]_32\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_6 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[511]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[510]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[509]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[444]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[507]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[506]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[505]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[440]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_11 : in STD_LOGIC;
    idelay_ce_r2_reg_0 : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    pi_stg2_load_reg_0 : in STD_LOGIC;
    \calib_sel_reg[0]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_5 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_5 : in STD_LOGIC;
    \pi_rst_stg1_cal_reg[2]\ : in STD_LOGIC;
    \pi_stg2_reg_l_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg_0 : in STD_LOGIC;
    \calib_sel_reg[0]_2\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_7 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[503]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[502]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[501]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[436]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[499]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[498]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[497]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[432]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_13 : in STD_LOGIC;
    \calib_sel_reg[1]_33\ : in STD_LOGIC;
    LD0_14 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \calib_sel_reg[1]_34\ : in STD_LOGIC;
    \calib_sel_reg[1]_35\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_6 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_6 : in STD_LOGIC;
    \calib_sel_reg[1]_36\ : in STD_LOGIC;
    \calib_sel_reg[1]_37\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_38\ : in STD_LOGIC;
    \calib_sel_reg[1]_39\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_8 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[495]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[494]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[493]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[428]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[491]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[490]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[489]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[424]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_15 : in STD_LOGIC;
    \data_offset_2_i2_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_data_wr_en : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_init_done_r : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_rst_0 : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__11_1\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_2\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]\ : in STD_LOGIC_VECTOR ( 223 downto 0 );
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__8\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    cnt_pwron_cke_done_r : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]_0\ : in STD_LOGIC;
    DOC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mux_wrdata : in STD_LOGIC_VECTOR ( 415 downto 0 );
    \write_buffer.wr_buf_out_data_reg[383]\ : in STD_LOGIC_VECTOR ( 95 downto 0 );
    mux_wrdata_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \init_calib_complete_reg_rep__25\ : in STD_LOGIC_VECTOR ( 45 downto 0 );
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \po_stg2_wrcal_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    D_po_coarse_enable105_out : in STD_LOGIC;
    D_po_counter_read_en117_out : in STD_LOGIC;
    D_po_fine_enable102_out : in STD_LOGIC;
    D_po_fine_inc108_out : in STD_LOGIC;
    \init_calib_complete_reg_rep__12_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    init_calib_complete_reg : in STD_LOGIC_VECTOR ( 21 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_mc_phy : entity is "mig_7series_v2_3_ddr_mc_phy";
end mig_7series_0_mig_7series_v2_3_ddr_mc_phy;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_mc_phy is
  signal A_byte_rd_en : STD_LOGIC;
  signal B_byte_rd_en : STD_LOGIC;
  signal C_byte_rd_en : STD_LOGIC;
  signal \_phy_ctl_full_p__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal byte_rd_en_v_0 : STD_LOGIC;
  signal byte_rd_en_v_1 : STD_LOGIC;
  signal byte_rd_en_v_2 : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_107\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_115\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_119\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_123\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_127\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_131\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_135\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_139\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_143\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_147\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_151\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_155\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_159\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_163\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_167\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_171\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_175\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_179\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_183\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_187\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_191\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_195\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_199\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_203\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_207\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_211\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_215\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_219\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_223\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_227\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_231\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_235\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_239\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_243\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_247\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_251\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_255\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_259\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_263\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_267\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_271\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_275\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_279\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_283\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_287\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_291\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_295\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_299\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_303\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_307\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_311\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_315\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_319\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_323\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_327\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_331\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_335\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_339\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_343\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_347\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_351\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_675\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_676\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_677\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_933\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_934\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_935\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_936\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_938\ : STD_LOGIC;
  signal \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_99\ : STD_LOGIC;
  signal \ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_46\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_531\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_532\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_533\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_534\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_535\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_536\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_537\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_538\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_539\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_540\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_541\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_542\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_543\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_544\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_545\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_546\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_547\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_548\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_549\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_550\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_551\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_552\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_553\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_554\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_555\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_556\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_557\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_558\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_559\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_560\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_561\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_562\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_563\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_564\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_565\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_566\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_567\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_568\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_569\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_570\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_571\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_572\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_573\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_574\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_575\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_576\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_577\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_578\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_579\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_580\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_581\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_582\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_583\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_584\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_585\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_586\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_587\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_588\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_589\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_590\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_591\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_592\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_593\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_594\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_71\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_72\ : STD_LOGIC;
  signal \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_73\ : STD_LOGIC;
  signal if_empty_or_v : STD_LOGIC_VECTOR ( 2 to 2 );
  signal mcGo_r1 : STD_LOGIC;
  signal \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0\ : STD_LOGIC;
  signal \mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0\ : STD_LOGIC;
  signal mcGo_r_reg_gate_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_0_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_10_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_11_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_12_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_13_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_1_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_2_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_3_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_4_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_5_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_6_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_7_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_8_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_9_n_0 : STD_LOGIC;
  signal mcGo_r_reg_r_n_0 : STD_LOGIC;
  signal \mcGo_w__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^not_strict_mode.app_rd_data_reg[100]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[101]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[102]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[103]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[120]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[121]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[122]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[123]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[124]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[125]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[126]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[127]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[152]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[153]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[154]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[155]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[156]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[157]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[158]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[159]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[160]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[161]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[162]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[163]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[164]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[165]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[166]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[167]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[184]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[185]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[186]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[187]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[188]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[189]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[190]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[191]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[216]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[217]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[218]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[219]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[220]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[221]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[222]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[223]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[224]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[225]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[226]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[227]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[228]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[229]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[230]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[231]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[248]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[249]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[24]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[250]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[251]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[252]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[253]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[254]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[255]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[25]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[26]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[27]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[280]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[281]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[282]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[283]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[284]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[285]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[286]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[287]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[288]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[289]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[28]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[290]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[291]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[292]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[293]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[294]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[295]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[29]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[30]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[312]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[313]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[314]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[315]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[316]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[317]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[318]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[319]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[31]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[32]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[33]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[344]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[345]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[346]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[347]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[348]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[349]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[34]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[350]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[351]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[352]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[353]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[354]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[355]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[356]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[357]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[358]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[359]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[35]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[36]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[376]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[377]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[378]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[379]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[37]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[380]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[381]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[382]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[383]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[38]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[39]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[408]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[409]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[410]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[411]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[412]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[413]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[414]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[415]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[416]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[417]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[418]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[419]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[420]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[421]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[422]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[423]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[440]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[441]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[442]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[443]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[444]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[445]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[446]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[447]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[472]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[473]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[474]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[475]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[476]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[477]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[478]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[479]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[480]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[481]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[482]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[483]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[484]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[485]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[486]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[487]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[504]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[505]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[506]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[507]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[508]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[509]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[510]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[511]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[56]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[57]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[58]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[59]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[60]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[61]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[62]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[63]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[88]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[89]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[90]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[91]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[92]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[93]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[94]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[95]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[96]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[97]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[98]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[99]\ : STD_LOGIC;
  signal phy_ctl_mstr_empty : STD_LOGIC;
  signal \^phy_mc_go\ : STD_LOGIC;
  signal \pi_counter_read_val_w[0]_3\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pi_counter_read_val_w[2]_5\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \po_counter_read_val_w[0]_2\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \po_counter_read_val_w[2]_4\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal pre_data_a_full_v : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \ref_dll_lock_w__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute srl_bus_name : string;
  attribute srl_bus_name of \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12\ : label is "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 ";
begin
  \not_strict_mode.app_rd_data_reg[100]\ <= \^not_strict_mode.app_rd_data_reg[100]\;
  \not_strict_mode.app_rd_data_reg[101]\ <= \^not_strict_mode.app_rd_data_reg[101]\;
  \not_strict_mode.app_rd_data_reg[102]\ <= \^not_strict_mode.app_rd_data_reg[102]\;
  \not_strict_mode.app_rd_data_reg[103]\ <= \^not_strict_mode.app_rd_data_reg[103]\;
  \not_strict_mode.app_rd_data_reg[120]\ <= \^not_strict_mode.app_rd_data_reg[120]\;
  \not_strict_mode.app_rd_data_reg[121]\ <= \^not_strict_mode.app_rd_data_reg[121]\;
  \not_strict_mode.app_rd_data_reg[122]\ <= \^not_strict_mode.app_rd_data_reg[122]\;
  \not_strict_mode.app_rd_data_reg[123]\ <= \^not_strict_mode.app_rd_data_reg[123]\;
  \not_strict_mode.app_rd_data_reg[124]\ <= \^not_strict_mode.app_rd_data_reg[124]\;
  \not_strict_mode.app_rd_data_reg[125]\ <= \^not_strict_mode.app_rd_data_reg[125]\;
  \not_strict_mode.app_rd_data_reg[126]\ <= \^not_strict_mode.app_rd_data_reg[126]\;
  \not_strict_mode.app_rd_data_reg[127]\ <= \^not_strict_mode.app_rd_data_reg[127]\;
  \not_strict_mode.app_rd_data_reg[152]\ <= \^not_strict_mode.app_rd_data_reg[152]\;
  \not_strict_mode.app_rd_data_reg[153]\ <= \^not_strict_mode.app_rd_data_reg[153]\;
  \not_strict_mode.app_rd_data_reg[154]\ <= \^not_strict_mode.app_rd_data_reg[154]\;
  \not_strict_mode.app_rd_data_reg[155]\ <= \^not_strict_mode.app_rd_data_reg[155]\;
  \not_strict_mode.app_rd_data_reg[156]\ <= \^not_strict_mode.app_rd_data_reg[156]\;
  \not_strict_mode.app_rd_data_reg[157]\ <= \^not_strict_mode.app_rd_data_reg[157]\;
  \not_strict_mode.app_rd_data_reg[158]\ <= \^not_strict_mode.app_rd_data_reg[158]\;
  \not_strict_mode.app_rd_data_reg[159]\ <= \^not_strict_mode.app_rd_data_reg[159]\;
  \not_strict_mode.app_rd_data_reg[160]\ <= \^not_strict_mode.app_rd_data_reg[160]\;
  \not_strict_mode.app_rd_data_reg[161]\ <= \^not_strict_mode.app_rd_data_reg[161]\;
  \not_strict_mode.app_rd_data_reg[162]\ <= \^not_strict_mode.app_rd_data_reg[162]\;
  \not_strict_mode.app_rd_data_reg[163]\ <= \^not_strict_mode.app_rd_data_reg[163]\;
  \not_strict_mode.app_rd_data_reg[164]\ <= \^not_strict_mode.app_rd_data_reg[164]\;
  \not_strict_mode.app_rd_data_reg[165]\ <= \^not_strict_mode.app_rd_data_reg[165]\;
  \not_strict_mode.app_rd_data_reg[166]\ <= \^not_strict_mode.app_rd_data_reg[166]\;
  \not_strict_mode.app_rd_data_reg[167]\ <= \^not_strict_mode.app_rd_data_reg[167]\;
  \not_strict_mode.app_rd_data_reg[184]\ <= \^not_strict_mode.app_rd_data_reg[184]\;
  \not_strict_mode.app_rd_data_reg[185]\ <= \^not_strict_mode.app_rd_data_reg[185]\;
  \not_strict_mode.app_rd_data_reg[186]\ <= \^not_strict_mode.app_rd_data_reg[186]\;
  \not_strict_mode.app_rd_data_reg[187]\ <= \^not_strict_mode.app_rd_data_reg[187]\;
  \not_strict_mode.app_rd_data_reg[188]\ <= \^not_strict_mode.app_rd_data_reg[188]\;
  \not_strict_mode.app_rd_data_reg[189]\ <= \^not_strict_mode.app_rd_data_reg[189]\;
  \not_strict_mode.app_rd_data_reg[190]\ <= \^not_strict_mode.app_rd_data_reg[190]\;
  \not_strict_mode.app_rd_data_reg[191]\ <= \^not_strict_mode.app_rd_data_reg[191]\;
  \not_strict_mode.app_rd_data_reg[216]\ <= \^not_strict_mode.app_rd_data_reg[216]\;
  \not_strict_mode.app_rd_data_reg[217]\ <= \^not_strict_mode.app_rd_data_reg[217]\;
  \not_strict_mode.app_rd_data_reg[218]\ <= \^not_strict_mode.app_rd_data_reg[218]\;
  \not_strict_mode.app_rd_data_reg[219]\ <= \^not_strict_mode.app_rd_data_reg[219]\;
  \not_strict_mode.app_rd_data_reg[220]\ <= \^not_strict_mode.app_rd_data_reg[220]\;
  \not_strict_mode.app_rd_data_reg[221]\ <= \^not_strict_mode.app_rd_data_reg[221]\;
  \not_strict_mode.app_rd_data_reg[222]\ <= \^not_strict_mode.app_rd_data_reg[222]\;
  \not_strict_mode.app_rd_data_reg[223]\ <= \^not_strict_mode.app_rd_data_reg[223]\;
  \not_strict_mode.app_rd_data_reg[224]\ <= \^not_strict_mode.app_rd_data_reg[224]\;
  \not_strict_mode.app_rd_data_reg[225]\ <= \^not_strict_mode.app_rd_data_reg[225]\;
  \not_strict_mode.app_rd_data_reg[226]\ <= \^not_strict_mode.app_rd_data_reg[226]\;
  \not_strict_mode.app_rd_data_reg[227]\ <= \^not_strict_mode.app_rd_data_reg[227]\;
  \not_strict_mode.app_rd_data_reg[228]\ <= \^not_strict_mode.app_rd_data_reg[228]\;
  \not_strict_mode.app_rd_data_reg[229]\ <= \^not_strict_mode.app_rd_data_reg[229]\;
  \not_strict_mode.app_rd_data_reg[230]\ <= \^not_strict_mode.app_rd_data_reg[230]\;
  \not_strict_mode.app_rd_data_reg[231]\ <= \^not_strict_mode.app_rd_data_reg[231]\;
  \not_strict_mode.app_rd_data_reg[248]\ <= \^not_strict_mode.app_rd_data_reg[248]\;
  \not_strict_mode.app_rd_data_reg[249]\ <= \^not_strict_mode.app_rd_data_reg[249]\;
  \not_strict_mode.app_rd_data_reg[24]\ <= \^not_strict_mode.app_rd_data_reg[24]\;
  \not_strict_mode.app_rd_data_reg[250]\ <= \^not_strict_mode.app_rd_data_reg[250]\;
  \not_strict_mode.app_rd_data_reg[251]\ <= \^not_strict_mode.app_rd_data_reg[251]\;
  \not_strict_mode.app_rd_data_reg[252]\ <= \^not_strict_mode.app_rd_data_reg[252]\;
  \not_strict_mode.app_rd_data_reg[253]\ <= \^not_strict_mode.app_rd_data_reg[253]\;
  \not_strict_mode.app_rd_data_reg[254]\ <= \^not_strict_mode.app_rd_data_reg[254]\;
  \not_strict_mode.app_rd_data_reg[255]\ <= \^not_strict_mode.app_rd_data_reg[255]\;
  \not_strict_mode.app_rd_data_reg[25]\ <= \^not_strict_mode.app_rd_data_reg[25]\;
  \not_strict_mode.app_rd_data_reg[26]\ <= \^not_strict_mode.app_rd_data_reg[26]\;
  \not_strict_mode.app_rd_data_reg[27]\ <= \^not_strict_mode.app_rd_data_reg[27]\;
  \not_strict_mode.app_rd_data_reg[280]\ <= \^not_strict_mode.app_rd_data_reg[280]\;
  \not_strict_mode.app_rd_data_reg[281]\ <= \^not_strict_mode.app_rd_data_reg[281]\;
  \not_strict_mode.app_rd_data_reg[282]\ <= \^not_strict_mode.app_rd_data_reg[282]\;
  \not_strict_mode.app_rd_data_reg[283]\ <= \^not_strict_mode.app_rd_data_reg[283]\;
  \not_strict_mode.app_rd_data_reg[284]\ <= \^not_strict_mode.app_rd_data_reg[284]\;
  \not_strict_mode.app_rd_data_reg[285]\ <= \^not_strict_mode.app_rd_data_reg[285]\;
  \not_strict_mode.app_rd_data_reg[286]\ <= \^not_strict_mode.app_rd_data_reg[286]\;
  \not_strict_mode.app_rd_data_reg[287]\ <= \^not_strict_mode.app_rd_data_reg[287]\;
  \not_strict_mode.app_rd_data_reg[288]\ <= \^not_strict_mode.app_rd_data_reg[288]\;
  \not_strict_mode.app_rd_data_reg[289]\ <= \^not_strict_mode.app_rd_data_reg[289]\;
  \not_strict_mode.app_rd_data_reg[28]\ <= \^not_strict_mode.app_rd_data_reg[28]\;
  \not_strict_mode.app_rd_data_reg[290]\ <= \^not_strict_mode.app_rd_data_reg[290]\;
  \not_strict_mode.app_rd_data_reg[291]\ <= \^not_strict_mode.app_rd_data_reg[291]\;
  \not_strict_mode.app_rd_data_reg[292]\ <= \^not_strict_mode.app_rd_data_reg[292]\;
  \not_strict_mode.app_rd_data_reg[293]\ <= \^not_strict_mode.app_rd_data_reg[293]\;
  \not_strict_mode.app_rd_data_reg[294]\ <= \^not_strict_mode.app_rd_data_reg[294]\;
  \not_strict_mode.app_rd_data_reg[295]\ <= \^not_strict_mode.app_rd_data_reg[295]\;
  \not_strict_mode.app_rd_data_reg[29]\ <= \^not_strict_mode.app_rd_data_reg[29]\;
  \not_strict_mode.app_rd_data_reg[30]\ <= \^not_strict_mode.app_rd_data_reg[30]\;
  \not_strict_mode.app_rd_data_reg[312]\ <= \^not_strict_mode.app_rd_data_reg[312]\;
  \not_strict_mode.app_rd_data_reg[313]\ <= \^not_strict_mode.app_rd_data_reg[313]\;
  \not_strict_mode.app_rd_data_reg[314]\ <= \^not_strict_mode.app_rd_data_reg[314]\;
  \not_strict_mode.app_rd_data_reg[315]\ <= \^not_strict_mode.app_rd_data_reg[315]\;
  \not_strict_mode.app_rd_data_reg[316]\ <= \^not_strict_mode.app_rd_data_reg[316]\;
  \not_strict_mode.app_rd_data_reg[317]\ <= \^not_strict_mode.app_rd_data_reg[317]\;
  \not_strict_mode.app_rd_data_reg[318]\ <= \^not_strict_mode.app_rd_data_reg[318]\;
  \not_strict_mode.app_rd_data_reg[319]\ <= \^not_strict_mode.app_rd_data_reg[319]\;
  \not_strict_mode.app_rd_data_reg[31]\ <= \^not_strict_mode.app_rd_data_reg[31]\;
  \not_strict_mode.app_rd_data_reg[32]\ <= \^not_strict_mode.app_rd_data_reg[32]\;
  \not_strict_mode.app_rd_data_reg[33]\ <= \^not_strict_mode.app_rd_data_reg[33]\;
  \not_strict_mode.app_rd_data_reg[344]\ <= \^not_strict_mode.app_rd_data_reg[344]\;
  \not_strict_mode.app_rd_data_reg[345]\ <= \^not_strict_mode.app_rd_data_reg[345]\;
  \not_strict_mode.app_rd_data_reg[346]\ <= \^not_strict_mode.app_rd_data_reg[346]\;
  \not_strict_mode.app_rd_data_reg[347]\ <= \^not_strict_mode.app_rd_data_reg[347]\;
  \not_strict_mode.app_rd_data_reg[348]\ <= \^not_strict_mode.app_rd_data_reg[348]\;
  \not_strict_mode.app_rd_data_reg[349]\ <= \^not_strict_mode.app_rd_data_reg[349]\;
  \not_strict_mode.app_rd_data_reg[34]\ <= \^not_strict_mode.app_rd_data_reg[34]\;
  \not_strict_mode.app_rd_data_reg[350]\ <= \^not_strict_mode.app_rd_data_reg[350]\;
  \not_strict_mode.app_rd_data_reg[351]\ <= \^not_strict_mode.app_rd_data_reg[351]\;
  \not_strict_mode.app_rd_data_reg[352]\ <= \^not_strict_mode.app_rd_data_reg[352]\;
  \not_strict_mode.app_rd_data_reg[353]\ <= \^not_strict_mode.app_rd_data_reg[353]\;
  \not_strict_mode.app_rd_data_reg[354]\ <= \^not_strict_mode.app_rd_data_reg[354]\;
  \not_strict_mode.app_rd_data_reg[355]\ <= \^not_strict_mode.app_rd_data_reg[355]\;
  \not_strict_mode.app_rd_data_reg[356]\ <= \^not_strict_mode.app_rd_data_reg[356]\;
  \not_strict_mode.app_rd_data_reg[357]\ <= \^not_strict_mode.app_rd_data_reg[357]\;
  \not_strict_mode.app_rd_data_reg[358]\ <= \^not_strict_mode.app_rd_data_reg[358]\;
  \not_strict_mode.app_rd_data_reg[359]\ <= \^not_strict_mode.app_rd_data_reg[359]\;
  \not_strict_mode.app_rd_data_reg[35]\ <= \^not_strict_mode.app_rd_data_reg[35]\;
  \not_strict_mode.app_rd_data_reg[36]\ <= \^not_strict_mode.app_rd_data_reg[36]\;
  \not_strict_mode.app_rd_data_reg[376]\ <= \^not_strict_mode.app_rd_data_reg[376]\;
  \not_strict_mode.app_rd_data_reg[377]\ <= \^not_strict_mode.app_rd_data_reg[377]\;
  \not_strict_mode.app_rd_data_reg[378]\ <= \^not_strict_mode.app_rd_data_reg[378]\;
  \not_strict_mode.app_rd_data_reg[379]\ <= \^not_strict_mode.app_rd_data_reg[379]\;
  \not_strict_mode.app_rd_data_reg[37]\ <= \^not_strict_mode.app_rd_data_reg[37]\;
  \not_strict_mode.app_rd_data_reg[380]\ <= \^not_strict_mode.app_rd_data_reg[380]\;
  \not_strict_mode.app_rd_data_reg[381]\ <= \^not_strict_mode.app_rd_data_reg[381]\;
  \not_strict_mode.app_rd_data_reg[382]\ <= \^not_strict_mode.app_rd_data_reg[382]\;
  \not_strict_mode.app_rd_data_reg[383]\ <= \^not_strict_mode.app_rd_data_reg[383]\;
  \not_strict_mode.app_rd_data_reg[38]\ <= \^not_strict_mode.app_rd_data_reg[38]\;
  \not_strict_mode.app_rd_data_reg[39]\ <= \^not_strict_mode.app_rd_data_reg[39]\;
  \not_strict_mode.app_rd_data_reg[408]\ <= \^not_strict_mode.app_rd_data_reg[408]\;
  \not_strict_mode.app_rd_data_reg[409]\ <= \^not_strict_mode.app_rd_data_reg[409]\;
  \not_strict_mode.app_rd_data_reg[410]\ <= \^not_strict_mode.app_rd_data_reg[410]\;
  \not_strict_mode.app_rd_data_reg[411]\ <= \^not_strict_mode.app_rd_data_reg[411]\;
  \not_strict_mode.app_rd_data_reg[412]\ <= \^not_strict_mode.app_rd_data_reg[412]\;
  \not_strict_mode.app_rd_data_reg[413]\ <= \^not_strict_mode.app_rd_data_reg[413]\;
  \not_strict_mode.app_rd_data_reg[414]\ <= \^not_strict_mode.app_rd_data_reg[414]\;
  \not_strict_mode.app_rd_data_reg[415]\ <= \^not_strict_mode.app_rd_data_reg[415]\;
  \not_strict_mode.app_rd_data_reg[416]\ <= \^not_strict_mode.app_rd_data_reg[416]\;
  \not_strict_mode.app_rd_data_reg[417]\ <= \^not_strict_mode.app_rd_data_reg[417]\;
  \not_strict_mode.app_rd_data_reg[418]\ <= \^not_strict_mode.app_rd_data_reg[418]\;
  \not_strict_mode.app_rd_data_reg[419]\ <= \^not_strict_mode.app_rd_data_reg[419]\;
  \not_strict_mode.app_rd_data_reg[420]\ <= \^not_strict_mode.app_rd_data_reg[420]\;
  \not_strict_mode.app_rd_data_reg[421]\ <= \^not_strict_mode.app_rd_data_reg[421]\;
  \not_strict_mode.app_rd_data_reg[422]\ <= \^not_strict_mode.app_rd_data_reg[422]\;
  \not_strict_mode.app_rd_data_reg[423]\ <= \^not_strict_mode.app_rd_data_reg[423]\;
  \not_strict_mode.app_rd_data_reg[440]\ <= \^not_strict_mode.app_rd_data_reg[440]\;
  \not_strict_mode.app_rd_data_reg[441]\ <= \^not_strict_mode.app_rd_data_reg[441]\;
  \not_strict_mode.app_rd_data_reg[442]\ <= \^not_strict_mode.app_rd_data_reg[442]\;
  \not_strict_mode.app_rd_data_reg[443]\ <= \^not_strict_mode.app_rd_data_reg[443]\;
  \not_strict_mode.app_rd_data_reg[444]\ <= \^not_strict_mode.app_rd_data_reg[444]\;
  \not_strict_mode.app_rd_data_reg[445]\ <= \^not_strict_mode.app_rd_data_reg[445]\;
  \not_strict_mode.app_rd_data_reg[446]\ <= \^not_strict_mode.app_rd_data_reg[446]\;
  \not_strict_mode.app_rd_data_reg[447]\ <= \^not_strict_mode.app_rd_data_reg[447]\;
  \not_strict_mode.app_rd_data_reg[472]\ <= \^not_strict_mode.app_rd_data_reg[472]\;
  \not_strict_mode.app_rd_data_reg[473]\ <= \^not_strict_mode.app_rd_data_reg[473]\;
  \not_strict_mode.app_rd_data_reg[474]\ <= \^not_strict_mode.app_rd_data_reg[474]\;
  \not_strict_mode.app_rd_data_reg[475]\ <= \^not_strict_mode.app_rd_data_reg[475]\;
  \not_strict_mode.app_rd_data_reg[476]\ <= \^not_strict_mode.app_rd_data_reg[476]\;
  \not_strict_mode.app_rd_data_reg[477]\ <= \^not_strict_mode.app_rd_data_reg[477]\;
  \not_strict_mode.app_rd_data_reg[478]\ <= \^not_strict_mode.app_rd_data_reg[478]\;
  \not_strict_mode.app_rd_data_reg[479]\ <= \^not_strict_mode.app_rd_data_reg[479]\;
  \not_strict_mode.app_rd_data_reg[480]\ <= \^not_strict_mode.app_rd_data_reg[480]\;
  \not_strict_mode.app_rd_data_reg[481]\ <= \^not_strict_mode.app_rd_data_reg[481]\;
  \not_strict_mode.app_rd_data_reg[482]\ <= \^not_strict_mode.app_rd_data_reg[482]\;
  \not_strict_mode.app_rd_data_reg[483]\ <= \^not_strict_mode.app_rd_data_reg[483]\;
  \not_strict_mode.app_rd_data_reg[484]\ <= \^not_strict_mode.app_rd_data_reg[484]\;
  \not_strict_mode.app_rd_data_reg[485]\ <= \^not_strict_mode.app_rd_data_reg[485]\;
  \not_strict_mode.app_rd_data_reg[486]\ <= \^not_strict_mode.app_rd_data_reg[486]\;
  \not_strict_mode.app_rd_data_reg[487]\ <= \^not_strict_mode.app_rd_data_reg[487]\;
  \not_strict_mode.app_rd_data_reg[504]\ <= \^not_strict_mode.app_rd_data_reg[504]\;
  \not_strict_mode.app_rd_data_reg[505]\ <= \^not_strict_mode.app_rd_data_reg[505]\;
  \not_strict_mode.app_rd_data_reg[506]\ <= \^not_strict_mode.app_rd_data_reg[506]\;
  \not_strict_mode.app_rd_data_reg[507]\ <= \^not_strict_mode.app_rd_data_reg[507]\;
  \not_strict_mode.app_rd_data_reg[508]\ <= \^not_strict_mode.app_rd_data_reg[508]\;
  \not_strict_mode.app_rd_data_reg[509]\ <= \^not_strict_mode.app_rd_data_reg[509]\;
  \not_strict_mode.app_rd_data_reg[510]\ <= \^not_strict_mode.app_rd_data_reg[510]\;
  \not_strict_mode.app_rd_data_reg[511]\ <= \^not_strict_mode.app_rd_data_reg[511]\;
  \not_strict_mode.app_rd_data_reg[56]\ <= \^not_strict_mode.app_rd_data_reg[56]\;
  \not_strict_mode.app_rd_data_reg[57]\ <= \^not_strict_mode.app_rd_data_reg[57]\;
  \not_strict_mode.app_rd_data_reg[58]\ <= \^not_strict_mode.app_rd_data_reg[58]\;
  \not_strict_mode.app_rd_data_reg[59]\ <= \^not_strict_mode.app_rd_data_reg[59]\;
  \not_strict_mode.app_rd_data_reg[60]\ <= \^not_strict_mode.app_rd_data_reg[60]\;
  \not_strict_mode.app_rd_data_reg[61]\ <= \^not_strict_mode.app_rd_data_reg[61]\;
  \not_strict_mode.app_rd_data_reg[62]\ <= \^not_strict_mode.app_rd_data_reg[62]\;
  \not_strict_mode.app_rd_data_reg[63]\ <= \^not_strict_mode.app_rd_data_reg[63]\;
  \not_strict_mode.app_rd_data_reg[88]\ <= \^not_strict_mode.app_rd_data_reg[88]\;
  \not_strict_mode.app_rd_data_reg[89]\ <= \^not_strict_mode.app_rd_data_reg[89]\;
  \not_strict_mode.app_rd_data_reg[90]\ <= \^not_strict_mode.app_rd_data_reg[90]\;
  \not_strict_mode.app_rd_data_reg[91]\ <= \^not_strict_mode.app_rd_data_reg[91]\;
  \not_strict_mode.app_rd_data_reg[92]\ <= \^not_strict_mode.app_rd_data_reg[92]\;
  \not_strict_mode.app_rd_data_reg[93]\ <= \^not_strict_mode.app_rd_data_reg[93]\;
  \not_strict_mode.app_rd_data_reg[94]\ <= \^not_strict_mode.app_rd_data_reg[94]\;
  \not_strict_mode.app_rd_data_reg[95]\ <= \^not_strict_mode.app_rd_data_reg[95]\;
  \not_strict_mode.app_rd_data_reg[96]\ <= \^not_strict_mode.app_rd_data_reg[96]\;
  \not_strict_mode.app_rd_data_reg[97]\ <= \^not_strict_mode.app_rd_data_reg[97]\;
  \not_strict_mode.app_rd_data_reg[98]\ <= \^not_strict_mode.app_rd_data_reg[98]\;
  \not_strict_mode.app_rd_data_reg[99]\ <= \^not_strict_mode.app_rd_data_reg[99]\;
  phy_mc_go <= \^phy_mc_go\;
calib_ctl_wren_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^phy_mc_go\,
      I1 => cnt_pwron_cke_done_r,
      O => p_110_in
    );
\ddr_phy_4lanes_0.u_ddr_phy_4lanes\: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes
     port map (
      A_byte_rd_en => A_byte_rd_en,
      B_byte_rd_en => B_byte_rd_en,
      CLK => CLK,
      CLKB0_10 => CLKB0_10,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      C_byte_rd_en => C_byte_rd_en,
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      LD0_6 => LD0_6,
      LD0_7 => LD0_7,
      LD0_8 => LD0_8,
      LD0_9 => LD0_9,
      Q(10 downto 0) => Q(10 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      \_phy_ctl_full_p__0\(0) => \_phy_ctl_full_p__0\(0),
      byte_rd_en_v_0 => byte_rd_en_v_0,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \calib_sel_reg[0]\ => \calib_sel_reg[0]\,
      \calib_sel_reg[0]_0\ => \calib_sel_reg[0]_0\,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_5\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_6\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_7\,
      \calib_sel_reg[1]_10\ => \calib_sel_reg[1]_16\,
      \calib_sel_reg[1]_11\ => \calib_sel_reg[1]_17\,
      \calib_sel_reg[1]_12\ => \calib_sel_reg[1]_18\,
      \calib_sel_reg[1]_13\ => \calib_sel_reg[1]_19\,
      \calib_sel_reg[1]_14\ => \calib_sel_reg[1]_20\,
      \calib_sel_reg[1]_15\ => \calib_sel_reg[1]_21\,
      \calib_sel_reg[1]_16\(5 downto 0) => \calib_sel_reg[1]_22\(5 downto 0),
      \calib_sel_reg[1]_17\ => \calib_sel_reg[1]_23\,
      \calib_sel_reg[1]_18\ => \calib_sel_reg[1]_24\,
      \calib_sel_reg[1]_19\ => \calib_sel_reg[1]_25\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_8\,
      \calib_sel_reg[1]_20\(1 downto 0) => \calib_sel_reg[4]\(1 downto 0),
      \calib_sel_reg[1]_3\(5 downto 0) => \calib_sel_reg[1]_9\(5 downto 0),
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_10\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_11\,
      \calib_sel_reg[1]_6\ => \calib_sel_reg[1]_12\,
      \calib_sel_reg[1]_7\ => \calib_sel_reg[1]_13\,
      \calib_sel_reg[1]_8\ => \calib_sel_reg[1]_14\,
      \calib_sel_reg[1]_9\(5 downto 0) => \calib_sel_reg[1]_15\(5 downto 0),
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_2,
      ck_po_stg2_f_indec_reg_0 => ck_po_stg2_f_indec_reg_3,
      ck_po_stg2_f_indec_reg_1 => ck_po_stg2_f_indec_reg_4,
      ck_po_stg2_f_indec_reg_2 => ck_po_stg2_f_indec_reg_5,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \^not_strict_mode.app_rd_data_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \^not_strict_mode.app_rd_data_reg[190]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \^not_strict_mode.app_rd_data_reg[254]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \^not_strict_mode.app_rd_data_reg[318]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \^not_strict_mode.app_rd_data_reg[382]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \^not_strict_mode.app_rd_data_reg[446]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \^not_strict_mode.app_rd_data_reg[510]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \^not_strict_mode.app_rd_data_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \^not_strict_mode.app_rd_data_reg[125]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \^not_strict_mode.app_rd_data_reg[189]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \^not_strict_mode.app_rd_data_reg[253]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \^not_strict_mode.app_rd_data_reg[127]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \^not_strict_mode.app_rd_data_reg[317]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \^not_strict_mode.app_rd_data_reg[381]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \^not_strict_mode.app_rd_data_reg[445]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \^not_strict_mode.app_rd_data_reg[509]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \^not_strict_mode.app_rd_data_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \^not_strict_mode.app_rd_data_reg[124]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \^not_strict_mode.app_rd_data_reg[188]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \^not_strict_mode.app_rd_data_reg[252]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \^not_strict_mode.app_rd_data_reg[316]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \^not_strict_mode.app_rd_data_reg[380]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \^not_strict_mode.app_rd_data_reg[191]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \^not_strict_mode.app_rd_data_reg[444]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \^not_strict_mode.app_rd_data_reg[508]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \^not_strict_mode.app_rd_data_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \^not_strict_mode.app_rd_data_reg[123]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \^not_strict_mode.app_rd_data_reg[187]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \^not_strict_mode.app_rd_data_reg[251]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \^not_strict_mode.app_rd_data_reg[315]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \^not_strict_mode.app_rd_data_reg[379]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \^not_strict_mode.app_rd_data_reg[443]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \^not_strict_mode.app_rd_data_reg[507]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \^not_strict_mode.app_rd_data_reg[255]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \^not_strict_mode.app_rd_data_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \^not_strict_mode.app_rd_data_reg[122]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \^not_strict_mode.app_rd_data_reg[186]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \^not_strict_mode.app_rd_data_reg[250]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \^not_strict_mode.app_rd_data_reg[314]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \^not_strict_mode.app_rd_data_reg[378]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \^not_strict_mode.app_rd_data_reg[442]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \^not_strict_mode.app_rd_data_reg[506]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \^not_strict_mode.app_rd_data_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \^not_strict_mode.app_rd_data_reg[121]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \^not_strict_mode.app_rd_data_reg[319]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \^not_strict_mode.app_rd_data_reg[185]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \^not_strict_mode.app_rd_data_reg[249]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \^not_strict_mode.app_rd_data_reg[313]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \^not_strict_mode.app_rd_data_reg[377]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \^not_strict_mode.app_rd_data_reg[441]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \^not_strict_mode.app_rd_data_reg[505]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \^not_strict_mode.app_rd_data_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \^not_strict_mode.app_rd_data_reg[120]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \^not_strict_mode.app_rd_data_reg[184]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \^not_strict_mode.app_rd_data_reg[248]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \^not_strict_mode.app_rd_data_reg[383]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \^not_strict_mode.app_rd_data_reg[312]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \^not_strict_mode.app_rd_data_reg[376]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \^not_strict_mode.app_rd_data_reg[440]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \^not_strict_mode.app_rd_data_reg[504]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \^not_strict_mode.app_rd_data_reg[447]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \^not_strict_mode.app_rd_data_reg[511]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \^not_strict_mode.app_rd_data_reg[62]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \^not_strict_mode.app_rd_data_reg[126]\,
      dqs_wl_po_stg2_c_incdec_reg => dqs_wl_po_stg2_c_incdec_reg,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_131\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_195\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_259\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_323\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_99\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_163\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_227\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_291\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_135\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_199\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_263\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_327\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_167\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_231\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_295\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_139\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_203\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_267\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_331\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_107\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_171\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_235\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_299\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_143\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_207\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_271\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_335\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_175\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_239\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_303\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_147\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_211\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_275\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_339\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_115\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_179\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_243\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_307\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_151\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_215\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_279\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_343\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_119\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_183\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_247\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_311\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_155\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_219\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_283\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_347\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_123\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_187\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_251\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_315\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_159\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_223\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_287\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_351\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_127\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_191\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_255\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_319\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_ce_r2_reg => idelay_ce_r2_reg,
      idelay_inc => idelay_inc,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      in0 => in0,
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10_2\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      \mcGo_w__0\(0) => \mcGo_w__0\(0),
      mem_dq_in(31 downto 0) => mem_dq_in(31 downto 0),
      mem_dq_out(35 downto 0) => mem_dq_out(35 downto 0),
      mem_dq_ts(35 downto 0) => mem_dq_ts(35 downto 0),
      mem_dqs_in(3 downto 0) => mem_dqs_in(3 downto 0),
      mem_refclk => mem_refclk,
      mux_wrdata(207 downto 176) => mux_wrdata(383 downto 352),
      mux_wrdata(175 downto 144) => mux_wrdata(319 downto 288),
      mux_wrdata(143 downto 120) => mux_wrdata(263 downto 240),
      mux_wrdata(119 downto 96) => mux_wrdata(215 downto 192),
      mux_wrdata(95 downto 72) => mux_wrdata(167 downto 144),
      mux_wrdata(71 downto 48) => mux_wrdata(119 downto 96),
      mux_wrdata(47 downto 16) => mux_wrdata(63 downto 32),
      mux_wrdata(15 downto 0) => mux_wrdata(15 downto 0),
      mux_wrdata_mask(31 downto 28) => mux_wrdata_mask(59 downto 56),
      mux_wrdata_mask(27 downto 24) => mux_wrdata_mask(51 downto 48),
      mux_wrdata_mask(23 downto 20) => mux_wrdata_mask(43 downto 40),
      mux_wrdata_mask(19 downto 16) => mux_wrdata_mask(35 downto 32),
      mux_wrdata_mask(15 downto 12) => mux_wrdata_mask(27 downto 24),
      mux_wrdata_mask(11 downto 8) => mux_wrdata_mask(19 downto 16),
      mux_wrdata_mask(7 downto 4) => mux_wrdata_mask(11 downto 8),
      mux_wrdata_mask(3 downto 0) => mux_wrdata_mask(3 downto 0),
      \my_empty_reg[1]\ => \my_empty_reg[1]_2\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_3\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_4\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_5\,
      \my_empty_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_71\,
      \my_empty_reg[3]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_73\,
      \my_empty_reg[3]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_72\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]_0\(43 downto 0),
      \my_empty_reg[7]_0\(43 downto 0) => \my_empty_reg[7]_1\(43 downto 0),
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]_2\(43 downto 0),
      \my_empty_reg[7]_2\(43 downto 0) => \my_empty_reg[7]_3\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[0]\ => \not_strict_mode.app_rd_data_reg[0]\,
      \not_strict_mode.app_rd_data_reg[10]\ => \not_strict_mode.app_rd_data_reg[10]\,
      \not_strict_mode.app_rd_data_reg[11]\ => \not_strict_mode.app_rd_data_reg[11]\,
      \not_strict_mode.app_rd_data_reg[128]\ => \not_strict_mode.app_rd_data_reg[128]\,
      \not_strict_mode.app_rd_data_reg[129]\ => \not_strict_mode.app_rd_data_reg[129]\,
      \not_strict_mode.app_rd_data_reg[12]\ => \not_strict_mode.app_rd_data_reg[12]\,
      \not_strict_mode.app_rd_data_reg[130]\ => \not_strict_mode.app_rd_data_reg[130]\,
      \not_strict_mode.app_rd_data_reg[131]\ => \not_strict_mode.app_rd_data_reg[131]\,
      \not_strict_mode.app_rd_data_reg[132]\ => \not_strict_mode.app_rd_data_reg[132]\,
      \not_strict_mode.app_rd_data_reg[133]\ => \not_strict_mode.app_rd_data_reg[133]\,
      \not_strict_mode.app_rd_data_reg[134]\ => \not_strict_mode.app_rd_data_reg[134]\,
      \not_strict_mode.app_rd_data_reg[135]\ => \not_strict_mode.app_rd_data_reg[135]\,
      \not_strict_mode.app_rd_data_reg[136]\ => \not_strict_mode.app_rd_data_reg[136]\,
      \not_strict_mode.app_rd_data_reg[137]\ => \not_strict_mode.app_rd_data_reg[137]\,
      \not_strict_mode.app_rd_data_reg[138]\ => \not_strict_mode.app_rd_data_reg[138]\,
      \not_strict_mode.app_rd_data_reg[139]\ => \not_strict_mode.app_rd_data_reg[139]\,
      \not_strict_mode.app_rd_data_reg[13]\ => \not_strict_mode.app_rd_data_reg[13]\,
      \not_strict_mode.app_rd_data_reg[140]\ => \not_strict_mode.app_rd_data_reg[140]\,
      \not_strict_mode.app_rd_data_reg[141]\ => \not_strict_mode.app_rd_data_reg[141]\,
      \not_strict_mode.app_rd_data_reg[142]\ => \not_strict_mode.app_rd_data_reg[142]\,
      \not_strict_mode.app_rd_data_reg[143]\ => \not_strict_mode.app_rd_data_reg[143]\,
      \not_strict_mode.app_rd_data_reg[144]\ => \not_strict_mode.app_rd_data_reg[144]\,
      \not_strict_mode.app_rd_data_reg[145]\ => \not_strict_mode.app_rd_data_reg[145]\,
      \not_strict_mode.app_rd_data_reg[146]\ => \not_strict_mode.app_rd_data_reg[146]\,
      \not_strict_mode.app_rd_data_reg[147]\ => \not_strict_mode.app_rd_data_reg[147]\,
      \not_strict_mode.app_rd_data_reg[148]\ => \not_strict_mode.app_rd_data_reg[148]\,
      \not_strict_mode.app_rd_data_reg[149]\ => \not_strict_mode.app_rd_data_reg[149]\,
      \not_strict_mode.app_rd_data_reg[14]\ => \not_strict_mode.app_rd_data_reg[14]\,
      \not_strict_mode.app_rd_data_reg[150]\ => \not_strict_mode.app_rd_data_reg[150]\,
      \not_strict_mode.app_rd_data_reg[151]\ => \not_strict_mode.app_rd_data_reg[151]\,
      \not_strict_mode.app_rd_data_reg[152]\ => \^not_strict_mode.app_rd_data_reg[152]\,
      \not_strict_mode.app_rd_data_reg[153]\ => \^not_strict_mode.app_rd_data_reg[153]\,
      \not_strict_mode.app_rd_data_reg[154]\ => \^not_strict_mode.app_rd_data_reg[154]\,
      \not_strict_mode.app_rd_data_reg[155]\ => \^not_strict_mode.app_rd_data_reg[155]\,
      \not_strict_mode.app_rd_data_reg[156]\ => \^not_strict_mode.app_rd_data_reg[156]\,
      \not_strict_mode.app_rd_data_reg[157]\ => \^not_strict_mode.app_rd_data_reg[157]\,
      \not_strict_mode.app_rd_data_reg[158]\ => \^not_strict_mode.app_rd_data_reg[158]\,
      \not_strict_mode.app_rd_data_reg[159]\ => \^not_strict_mode.app_rd_data_reg[159]\,
      \not_strict_mode.app_rd_data_reg[15]\ => \not_strict_mode.app_rd_data_reg[15]\,
      \not_strict_mode.app_rd_data_reg[16]\ => \not_strict_mode.app_rd_data_reg[16]\,
      \not_strict_mode.app_rd_data_reg[17]\ => \not_strict_mode.app_rd_data_reg[17]\,
      \not_strict_mode.app_rd_data_reg[18]\ => \not_strict_mode.app_rd_data_reg[18]\,
      \not_strict_mode.app_rd_data_reg[192]\ => \not_strict_mode.app_rd_data_reg[192]\,
      \not_strict_mode.app_rd_data_reg[193]\ => \not_strict_mode.app_rd_data_reg[193]\,
      \not_strict_mode.app_rd_data_reg[194]\ => \not_strict_mode.app_rd_data_reg[194]\,
      \not_strict_mode.app_rd_data_reg[195]\ => \not_strict_mode.app_rd_data_reg[195]\,
      \not_strict_mode.app_rd_data_reg[196]\ => \not_strict_mode.app_rd_data_reg[196]\,
      \not_strict_mode.app_rd_data_reg[197]\ => \not_strict_mode.app_rd_data_reg[197]\,
      \not_strict_mode.app_rd_data_reg[198]\ => \not_strict_mode.app_rd_data_reg[198]\,
      \not_strict_mode.app_rd_data_reg[199]\ => \not_strict_mode.app_rd_data_reg[199]\,
      \not_strict_mode.app_rd_data_reg[19]\ => \not_strict_mode.app_rd_data_reg[19]\,
      \not_strict_mode.app_rd_data_reg[1]\ => \not_strict_mode.app_rd_data_reg[1]\,
      \not_strict_mode.app_rd_data_reg[200]\ => \not_strict_mode.app_rd_data_reg[200]\,
      \not_strict_mode.app_rd_data_reg[201]\ => \not_strict_mode.app_rd_data_reg[201]\,
      \not_strict_mode.app_rd_data_reg[202]\ => \not_strict_mode.app_rd_data_reg[202]\,
      \not_strict_mode.app_rd_data_reg[203]\ => \not_strict_mode.app_rd_data_reg[203]\,
      \not_strict_mode.app_rd_data_reg[204]\ => \not_strict_mode.app_rd_data_reg[204]\,
      \not_strict_mode.app_rd_data_reg[205]\ => \not_strict_mode.app_rd_data_reg[205]\,
      \not_strict_mode.app_rd_data_reg[206]\ => \not_strict_mode.app_rd_data_reg[206]\,
      \not_strict_mode.app_rd_data_reg[207]\ => \not_strict_mode.app_rd_data_reg[207]\,
      \not_strict_mode.app_rd_data_reg[208]\ => \not_strict_mode.app_rd_data_reg[208]\,
      \not_strict_mode.app_rd_data_reg[209]\ => \not_strict_mode.app_rd_data_reg[209]\,
      \not_strict_mode.app_rd_data_reg[20]\ => \not_strict_mode.app_rd_data_reg[20]\,
      \not_strict_mode.app_rd_data_reg[210]\ => \not_strict_mode.app_rd_data_reg[210]\,
      \not_strict_mode.app_rd_data_reg[211]\ => \not_strict_mode.app_rd_data_reg[211]\,
      \not_strict_mode.app_rd_data_reg[212]\ => \not_strict_mode.app_rd_data_reg[212]\,
      \not_strict_mode.app_rd_data_reg[213]\ => \not_strict_mode.app_rd_data_reg[213]\,
      \not_strict_mode.app_rd_data_reg[214]\ => \not_strict_mode.app_rd_data_reg[214]\,
      \not_strict_mode.app_rd_data_reg[215]\ => \not_strict_mode.app_rd_data_reg[215]\,
      \not_strict_mode.app_rd_data_reg[216]\ => \^not_strict_mode.app_rd_data_reg[216]\,
      \not_strict_mode.app_rd_data_reg[217]\ => \^not_strict_mode.app_rd_data_reg[217]\,
      \not_strict_mode.app_rd_data_reg[218]\ => \^not_strict_mode.app_rd_data_reg[218]\,
      \not_strict_mode.app_rd_data_reg[219]\ => \^not_strict_mode.app_rd_data_reg[219]\,
      \not_strict_mode.app_rd_data_reg[21]\ => \not_strict_mode.app_rd_data_reg[21]\,
      \not_strict_mode.app_rd_data_reg[220]\ => \^not_strict_mode.app_rd_data_reg[220]\,
      \not_strict_mode.app_rd_data_reg[221]\ => \^not_strict_mode.app_rd_data_reg[221]\,
      \not_strict_mode.app_rd_data_reg[222]\ => \^not_strict_mode.app_rd_data_reg[222]\,
      \not_strict_mode.app_rd_data_reg[223]\ => \^not_strict_mode.app_rd_data_reg[223]\,
      \not_strict_mode.app_rd_data_reg[22]\ => \not_strict_mode.app_rd_data_reg[22]\,
      \not_strict_mode.app_rd_data_reg[23]\ => \not_strict_mode.app_rd_data_reg[23]\,
      \not_strict_mode.app_rd_data_reg[24]\ => \^not_strict_mode.app_rd_data_reg[24]\,
      \not_strict_mode.app_rd_data_reg[256]\ => \not_strict_mode.app_rd_data_reg[256]\,
      \not_strict_mode.app_rd_data_reg[257]\ => \not_strict_mode.app_rd_data_reg[257]\,
      \not_strict_mode.app_rd_data_reg[258]\ => \not_strict_mode.app_rd_data_reg[258]\,
      \not_strict_mode.app_rd_data_reg[259]\ => \not_strict_mode.app_rd_data_reg[259]\,
      \not_strict_mode.app_rd_data_reg[25]\ => \^not_strict_mode.app_rd_data_reg[25]\,
      \not_strict_mode.app_rd_data_reg[260]\ => \not_strict_mode.app_rd_data_reg[260]\,
      \not_strict_mode.app_rd_data_reg[261]\ => \not_strict_mode.app_rd_data_reg[261]\,
      \not_strict_mode.app_rd_data_reg[262]\ => \not_strict_mode.app_rd_data_reg[262]\,
      \not_strict_mode.app_rd_data_reg[263]\ => \not_strict_mode.app_rd_data_reg[263]\,
      \not_strict_mode.app_rd_data_reg[264]\ => \not_strict_mode.app_rd_data_reg[264]\,
      \not_strict_mode.app_rd_data_reg[265]\ => \not_strict_mode.app_rd_data_reg[265]\,
      \not_strict_mode.app_rd_data_reg[266]\ => \not_strict_mode.app_rd_data_reg[266]\,
      \not_strict_mode.app_rd_data_reg[267]\ => \not_strict_mode.app_rd_data_reg[267]\,
      \not_strict_mode.app_rd_data_reg[268]\ => \not_strict_mode.app_rd_data_reg[268]\,
      \not_strict_mode.app_rd_data_reg[269]\ => \not_strict_mode.app_rd_data_reg[269]\,
      \not_strict_mode.app_rd_data_reg[26]\ => \^not_strict_mode.app_rd_data_reg[26]\,
      \not_strict_mode.app_rd_data_reg[270]\ => \not_strict_mode.app_rd_data_reg[270]\,
      \not_strict_mode.app_rd_data_reg[271]\ => \not_strict_mode.app_rd_data_reg[271]\,
      \not_strict_mode.app_rd_data_reg[272]\ => \not_strict_mode.app_rd_data_reg[272]\,
      \not_strict_mode.app_rd_data_reg[273]\ => \not_strict_mode.app_rd_data_reg[273]\,
      \not_strict_mode.app_rd_data_reg[274]\ => \not_strict_mode.app_rd_data_reg[274]\,
      \not_strict_mode.app_rd_data_reg[275]\ => \not_strict_mode.app_rd_data_reg[275]\,
      \not_strict_mode.app_rd_data_reg[276]\ => \not_strict_mode.app_rd_data_reg[276]\,
      \not_strict_mode.app_rd_data_reg[277]\ => \not_strict_mode.app_rd_data_reg[277]\,
      \not_strict_mode.app_rd_data_reg[278]\ => \not_strict_mode.app_rd_data_reg[278]\,
      \not_strict_mode.app_rd_data_reg[279]\ => \not_strict_mode.app_rd_data_reg[279]\,
      \not_strict_mode.app_rd_data_reg[27]\ => \^not_strict_mode.app_rd_data_reg[27]\,
      \not_strict_mode.app_rd_data_reg[280]\ => \^not_strict_mode.app_rd_data_reg[280]\,
      \not_strict_mode.app_rd_data_reg[281]\ => \^not_strict_mode.app_rd_data_reg[281]\,
      \not_strict_mode.app_rd_data_reg[282]\ => \^not_strict_mode.app_rd_data_reg[282]\,
      \not_strict_mode.app_rd_data_reg[283]\ => \^not_strict_mode.app_rd_data_reg[283]\,
      \not_strict_mode.app_rd_data_reg[284]\ => \^not_strict_mode.app_rd_data_reg[284]\,
      \not_strict_mode.app_rd_data_reg[285]\ => \^not_strict_mode.app_rd_data_reg[285]\,
      \not_strict_mode.app_rd_data_reg[286]\ => \^not_strict_mode.app_rd_data_reg[286]\,
      \not_strict_mode.app_rd_data_reg[287]\ => \^not_strict_mode.app_rd_data_reg[287]\,
      \not_strict_mode.app_rd_data_reg[28]\ => \^not_strict_mode.app_rd_data_reg[28]\,
      \not_strict_mode.app_rd_data_reg[29]\ => \^not_strict_mode.app_rd_data_reg[29]\,
      \not_strict_mode.app_rd_data_reg[2]\ => \not_strict_mode.app_rd_data_reg[2]\,
      \not_strict_mode.app_rd_data_reg[30]\ => \^not_strict_mode.app_rd_data_reg[30]\,
      \not_strict_mode.app_rd_data_reg[31]\ => \^not_strict_mode.app_rd_data_reg[31]\,
      \not_strict_mode.app_rd_data_reg[320]\ => \not_strict_mode.app_rd_data_reg[320]\,
      \not_strict_mode.app_rd_data_reg[321]\ => \not_strict_mode.app_rd_data_reg[321]\,
      \not_strict_mode.app_rd_data_reg[322]\ => \not_strict_mode.app_rd_data_reg[322]\,
      \not_strict_mode.app_rd_data_reg[323]\ => \not_strict_mode.app_rd_data_reg[323]\,
      \not_strict_mode.app_rd_data_reg[324]\ => \not_strict_mode.app_rd_data_reg[324]\,
      \not_strict_mode.app_rd_data_reg[325]\ => \not_strict_mode.app_rd_data_reg[325]\,
      \not_strict_mode.app_rd_data_reg[326]\ => \not_strict_mode.app_rd_data_reg[326]\,
      \not_strict_mode.app_rd_data_reg[327]\ => \not_strict_mode.app_rd_data_reg[327]\,
      \not_strict_mode.app_rd_data_reg[328]\ => \not_strict_mode.app_rd_data_reg[328]\,
      \not_strict_mode.app_rd_data_reg[329]\ => \not_strict_mode.app_rd_data_reg[329]\,
      \not_strict_mode.app_rd_data_reg[330]\ => \not_strict_mode.app_rd_data_reg[330]\,
      \not_strict_mode.app_rd_data_reg[331]\ => \not_strict_mode.app_rd_data_reg[331]\,
      \not_strict_mode.app_rd_data_reg[332]\ => \not_strict_mode.app_rd_data_reg[332]\,
      \not_strict_mode.app_rd_data_reg[333]\ => \not_strict_mode.app_rd_data_reg[333]\,
      \not_strict_mode.app_rd_data_reg[334]\ => \not_strict_mode.app_rd_data_reg[334]\,
      \not_strict_mode.app_rd_data_reg[335]\ => \not_strict_mode.app_rd_data_reg[335]\,
      \not_strict_mode.app_rd_data_reg[336]\ => \not_strict_mode.app_rd_data_reg[336]\,
      \not_strict_mode.app_rd_data_reg[337]\ => \not_strict_mode.app_rd_data_reg[337]\,
      \not_strict_mode.app_rd_data_reg[338]\ => \not_strict_mode.app_rd_data_reg[338]\,
      \not_strict_mode.app_rd_data_reg[339]\ => \not_strict_mode.app_rd_data_reg[339]\,
      \not_strict_mode.app_rd_data_reg[340]\ => \not_strict_mode.app_rd_data_reg[340]\,
      \not_strict_mode.app_rd_data_reg[341]\ => \not_strict_mode.app_rd_data_reg[341]\,
      \not_strict_mode.app_rd_data_reg[342]\ => \not_strict_mode.app_rd_data_reg[342]\,
      \not_strict_mode.app_rd_data_reg[343]\ => \not_strict_mode.app_rd_data_reg[343]\,
      \not_strict_mode.app_rd_data_reg[344]\ => \^not_strict_mode.app_rd_data_reg[344]\,
      \not_strict_mode.app_rd_data_reg[345]\ => \^not_strict_mode.app_rd_data_reg[345]\,
      \not_strict_mode.app_rd_data_reg[346]\ => \^not_strict_mode.app_rd_data_reg[346]\,
      \not_strict_mode.app_rd_data_reg[347]\ => \^not_strict_mode.app_rd_data_reg[347]\,
      \not_strict_mode.app_rd_data_reg[348]\ => \^not_strict_mode.app_rd_data_reg[348]\,
      \not_strict_mode.app_rd_data_reg[349]\ => \^not_strict_mode.app_rd_data_reg[349]\,
      \not_strict_mode.app_rd_data_reg[350]\ => \^not_strict_mode.app_rd_data_reg[350]\,
      \not_strict_mode.app_rd_data_reg[351]\ => \^not_strict_mode.app_rd_data_reg[351]\,
      \not_strict_mode.app_rd_data_reg[384]\ => \not_strict_mode.app_rd_data_reg[384]\,
      \not_strict_mode.app_rd_data_reg[385]\ => \not_strict_mode.app_rd_data_reg[385]\,
      \not_strict_mode.app_rd_data_reg[386]\ => \not_strict_mode.app_rd_data_reg[386]\,
      \not_strict_mode.app_rd_data_reg[387]\ => \not_strict_mode.app_rd_data_reg[387]\,
      \not_strict_mode.app_rd_data_reg[388]\ => \not_strict_mode.app_rd_data_reg[388]\,
      \not_strict_mode.app_rd_data_reg[389]\ => \not_strict_mode.app_rd_data_reg[389]\,
      \not_strict_mode.app_rd_data_reg[390]\ => \not_strict_mode.app_rd_data_reg[390]\,
      \not_strict_mode.app_rd_data_reg[391]\ => \not_strict_mode.app_rd_data_reg[391]\,
      \not_strict_mode.app_rd_data_reg[392]\ => \not_strict_mode.app_rd_data_reg[392]\,
      \not_strict_mode.app_rd_data_reg[393]\ => \not_strict_mode.app_rd_data_reg[393]\,
      \not_strict_mode.app_rd_data_reg[394]\ => \not_strict_mode.app_rd_data_reg[394]\,
      \not_strict_mode.app_rd_data_reg[395]\ => \not_strict_mode.app_rd_data_reg[395]\,
      \not_strict_mode.app_rd_data_reg[396]\ => \not_strict_mode.app_rd_data_reg[396]\,
      \not_strict_mode.app_rd_data_reg[397]\ => \not_strict_mode.app_rd_data_reg[397]\,
      \not_strict_mode.app_rd_data_reg[398]\ => \not_strict_mode.app_rd_data_reg[398]\,
      \not_strict_mode.app_rd_data_reg[399]\ => \not_strict_mode.app_rd_data_reg[399]\,
      \not_strict_mode.app_rd_data_reg[3]\ => \not_strict_mode.app_rd_data_reg[3]\,
      \not_strict_mode.app_rd_data_reg[400]\ => \not_strict_mode.app_rd_data_reg[400]\,
      \not_strict_mode.app_rd_data_reg[401]\ => \not_strict_mode.app_rd_data_reg[401]\,
      \not_strict_mode.app_rd_data_reg[402]\ => \not_strict_mode.app_rd_data_reg[402]\,
      \not_strict_mode.app_rd_data_reg[403]\ => \not_strict_mode.app_rd_data_reg[403]\,
      \not_strict_mode.app_rd_data_reg[404]\ => \not_strict_mode.app_rd_data_reg[404]\,
      \not_strict_mode.app_rd_data_reg[405]\ => \not_strict_mode.app_rd_data_reg[405]\,
      \not_strict_mode.app_rd_data_reg[406]\ => \not_strict_mode.app_rd_data_reg[406]\,
      \not_strict_mode.app_rd_data_reg[407]\ => \not_strict_mode.app_rd_data_reg[407]\,
      \not_strict_mode.app_rd_data_reg[408]\ => \^not_strict_mode.app_rd_data_reg[408]\,
      \not_strict_mode.app_rd_data_reg[409]\ => \^not_strict_mode.app_rd_data_reg[409]\,
      \not_strict_mode.app_rd_data_reg[410]\ => \^not_strict_mode.app_rd_data_reg[410]\,
      \not_strict_mode.app_rd_data_reg[411]\ => \^not_strict_mode.app_rd_data_reg[411]\,
      \not_strict_mode.app_rd_data_reg[412]\ => \^not_strict_mode.app_rd_data_reg[412]\,
      \not_strict_mode.app_rd_data_reg[413]\ => \^not_strict_mode.app_rd_data_reg[413]\,
      \not_strict_mode.app_rd_data_reg[414]\ => \^not_strict_mode.app_rd_data_reg[414]\,
      \not_strict_mode.app_rd_data_reg[415]\ => \^not_strict_mode.app_rd_data_reg[415]\,
      \not_strict_mode.app_rd_data_reg[448]\ => \not_strict_mode.app_rd_data_reg[448]\,
      \not_strict_mode.app_rd_data_reg[449]\ => \not_strict_mode.app_rd_data_reg[449]\,
      \not_strict_mode.app_rd_data_reg[450]\ => \not_strict_mode.app_rd_data_reg[450]\,
      \not_strict_mode.app_rd_data_reg[451]\ => \not_strict_mode.app_rd_data_reg[451]\,
      \not_strict_mode.app_rd_data_reg[452]\ => \not_strict_mode.app_rd_data_reg[452]\,
      \not_strict_mode.app_rd_data_reg[453]\ => \not_strict_mode.app_rd_data_reg[453]\,
      \not_strict_mode.app_rd_data_reg[454]\ => \not_strict_mode.app_rd_data_reg[454]\,
      \not_strict_mode.app_rd_data_reg[455]\ => \not_strict_mode.app_rd_data_reg[455]\,
      \not_strict_mode.app_rd_data_reg[456]\ => \not_strict_mode.app_rd_data_reg[456]\,
      \not_strict_mode.app_rd_data_reg[457]\ => \not_strict_mode.app_rd_data_reg[457]\,
      \not_strict_mode.app_rd_data_reg[458]\ => \not_strict_mode.app_rd_data_reg[458]\,
      \not_strict_mode.app_rd_data_reg[459]\ => \not_strict_mode.app_rd_data_reg[459]\,
      \not_strict_mode.app_rd_data_reg[460]\ => \not_strict_mode.app_rd_data_reg[460]\,
      \not_strict_mode.app_rd_data_reg[461]\ => \not_strict_mode.app_rd_data_reg[461]\,
      \not_strict_mode.app_rd_data_reg[462]\ => \not_strict_mode.app_rd_data_reg[462]\,
      \not_strict_mode.app_rd_data_reg[463]\ => \not_strict_mode.app_rd_data_reg[463]\,
      \not_strict_mode.app_rd_data_reg[464]\ => \not_strict_mode.app_rd_data_reg[464]\,
      \not_strict_mode.app_rd_data_reg[465]\ => \not_strict_mode.app_rd_data_reg[465]\,
      \not_strict_mode.app_rd_data_reg[466]\ => \not_strict_mode.app_rd_data_reg[466]\,
      \not_strict_mode.app_rd_data_reg[467]\ => \not_strict_mode.app_rd_data_reg[467]\,
      \not_strict_mode.app_rd_data_reg[468]\ => \not_strict_mode.app_rd_data_reg[468]\,
      \not_strict_mode.app_rd_data_reg[469]\ => \not_strict_mode.app_rd_data_reg[469]\,
      \not_strict_mode.app_rd_data_reg[470]\ => \not_strict_mode.app_rd_data_reg[470]\,
      \not_strict_mode.app_rd_data_reg[471]\ => \not_strict_mode.app_rd_data_reg[471]\,
      \not_strict_mode.app_rd_data_reg[472]\ => \^not_strict_mode.app_rd_data_reg[472]\,
      \not_strict_mode.app_rd_data_reg[473]\ => \^not_strict_mode.app_rd_data_reg[473]\,
      \not_strict_mode.app_rd_data_reg[474]\ => \^not_strict_mode.app_rd_data_reg[474]\,
      \not_strict_mode.app_rd_data_reg[475]\ => \^not_strict_mode.app_rd_data_reg[475]\,
      \not_strict_mode.app_rd_data_reg[476]\ => \^not_strict_mode.app_rd_data_reg[476]\,
      \not_strict_mode.app_rd_data_reg[477]\ => \^not_strict_mode.app_rd_data_reg[477]\,
      \not_strict_mode.app_rd_data_reg[478]\ => \^not_strict_mode.app_rd_data_reg[478]\,
      \not_strict_mode.app_rd_data_reg[479]\(255 downto 224) => \not_strict_mode.app_rd_data_reg[511]_0\(479 downto 448),
      \not_strict_mode.app_rd_data_reg[479]\(223 downto 192) => \not_strict_mode.app_rd_data_reg[511]_0\(415 downto 384),
      \not_strict_mode.app_rd_data_reg[479]\(191 downto 160) => \not_strict_mode.app_rd_data_reg[511]_0\(351 downto 320),
      \not_strict_mode.app_rd_data_reg[479]\(159 downto 128) => \not_strict_mode.app_rd_data_reg[511]_0\(287 downto 256),
      \not_strict_mode.app_rd_data_reg[479]\(127 downto 96) => \not_strict_mode.app_rd_data_reg[511]_0\(223 downto 192),
      \not_strict_mode.app_rd_data_reg[479]\(95 downto 64) => \not_strict_mode.app_rd_data_reg[511]_0\(159 downto 128),
      \not_strict_mode.app_rd_data_reg[479]\(63 downto 32) => \not_strict_mode.app_rd_data_reg[511]_0\(95 downto 64),
      \not_strict_mode.app_rd_data_reg[479]\(31 downto 0) => \not_strict_mode.app_rd_data_reg[511]_0\(31 downto 0),
      \not_strict_mode.app_rd_data_reg[479]_0\ => \^not_strict_mode.app_rd_data_reg[479]\,
      \not_strict_mode.app_rd_data_reg[4]\ => \not_strict_mode.app_rd_data_reg[4]\,
      \not_strict_mode.app_rd_data_reg[5]\ => \not_strict_mode.app_rd_data_reg[5]\,
      \not_strict_mode.app_rd_data_reg[64]\ => \not_strict_mode.app_rd_data_reg[64]\,
      \not_strict_mode.app_rd_data_reg[65]\ => \not_strict_mode.app_rd_data_reg[65]\,
      \not_strict_mode.app_rd_data_reg[66]\ => \not_strict_mode.app_rd_data_reg[66]\,
      \not_strict_mode.app_rd_data_reg[67]\ => \not_strict_mode.app_rd_data_reg[67]\,
      \not_strict_mode.app_rd_data_reg[68]\ => \not_strict_mode.app_rd_data_reg[68]\,
      \not_strict_mode.app_rd_data_reg[69]\ => \not_strict_mode.app_rd_data_reg[69]\,
      \not_strict_mode.app_rd_data_reg[6]\ => \not_strict_mode.app_rd_data_reg[6]\,
      \not_strict_mode.app_rd_data_reg[70]\ => \not_strict_mode.app_rd_data_reg[70]\,
      \not_strict_mode.app_rd_data_reg[71]\ => \not_strict_mode.app_rd_data_reg[71]\,
      \not_strict_mode.app_rd_data_reg[72]\ => \not_strict_mode.app_rd_data_reg[72]\,
      \not_strict_mode.app_rd_data_reg[73]\ => \not_strict_mode.app_rd_data_reg[73]\,
      \not_strict_mode.app_rd_data_reg[74]\ => \not_strict_mode.app_rd_data_reg[74]\,
      \not_strict_mode.app_rd_data_reg[75]\ => \not_strict_mode.app_rd_data_reg[75]\,
      \not_strict_mode.app_rd_data_reg[76]\ => \not_strict_mode.app_rd_data_reg[76]\,
      \not_strict_mode.app_rd_data_reg[77]\ => \not_strict_mode.app_rd_data_reg[77]\,
      \not_strict_mode.app_rd_data_reg[78]\ => \not_strict_mode.app_rd_data_reg[78]\,
      \not_strict_mode.app_rd_data_reg[79]\ => \not_strict_mode.app_rd_data_reg[79]\,
      \not_strict_mode.app_rd_data_reg[7]\ => \not_strict_mode.app_rd_data_reg[7]\,
      \not_strict_mode.app_rd_data_reg[80]\ => \not_strict_mode.app_rd_data_reg[80]\,
      \not_strict_mode.app_rd_data_reg[81]\ => \not_strict_mode.app_rd_data_reg[81]\,
      \not_strict_mode.app_rd_data_reg[82]\ => \not_strict_mode.app_rd_data_reg[82]\,
      \not_strict_mode.app_rd_data_reg[83]\ => \not_strict_mode.app_rd_data_reg[83]\,
      \not_strict_mode.app_rd_data_reg[84]\ => \not_strict_mode.app_rd_data_reg[84]\,
      \not_strict_mode.app_rd_data_reg[85]\ => \not_strict_mode.app_rd_data_reg[85]\,
      \not_strict_mode.app_rd_data_reg[86]\ => \not_strict_mode.app_rd_data_reg[86]\,
      \not_strict_mode.app_rd_data_reg[87]\ => \not_strict_mode.app_rd_data_reg[87]\,
      \not_strict_mode.app_rd_data_reg[88]\ => \^not_strict_mode.app_rd_data_reg[88]\,
      \not_strict_mode.app_rd_data_reg[89]\ => \^not_strict_mode.app_rd_data_reg[89]\,
      \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\,
      \not_strict_mode.app_rd_data_reg[90]\ => \^not_strict_mode.app_rd_data_reg[90]\,
      \not_strict_mode.app_rd_data_reg[91]\ => \^not_strict_mode.app_rd_data_reg[91]\,
      \not_strict_mode.app_rd_data_reg[92]\ => \^not_strict_mode.app_rd_data_reg[92]\,
      \not_strict_mode.app_rd_data_reg[93]\ => \^not_strict_mode.app_rd_data_reg[93]\,
      \not_strict_mode.app_rd_data_reg[94]\ => \^not_strict_mode.app_rd_data_reg[94]\,
      \not_strict_mode.app_rd_data_reg[95]\ => \^not_strict_mode.app_rd_data_reg[95]\,
      \not_strict_mode.app_rd_data_reg[9]\ => \not_strict_mode.app_rd_data_reg[9]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0),
      ofs_rdy_r_reg => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_933\,
      ofs_rdy_r_reg_0 => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_934\,
      out_dqs_0 => out_dqs_0,
      out_dqs_1 => out_dqs_1,
      out_dqs_2 => out_dqs_2,
      out_dqs_3 => out_dqs_3,
      p_0_out => p_0_out,
      phy_ctl_mstr_empty => phy_ctl_mstr_empty,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_dqs_found_lanes(3 downto 0) => pi_dqs_found_lanes(3 downto 0),
      pi_phase_locked_all_r1_reg => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_938\,
      \pi_rdval_cnt_reg[5]\(5 downto 0) => \pi_counter_read_val_w[0]_3\(5 downto 0),
      \pi_rst_stg1_cal_reg[0]\ => \pi_rst_stg1_cal_reg[0]\,
      pi_stg2_load_reg => pi_stg2_load_reg,
      \pi_stg2_reg_l_reg[5]\(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0),
      pll_locked => pll_locked,
      \po_rdval_cnt_reg[8]\(8 downto 0) => \po_counter_read_val_w[0]_2\(8 downto 0),
      \po_stg2_wrcal_cnt_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_531\,
      \po_stg2_wrcal_cnt_reg[1]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_532\,
      \po_stg2_wrcal_cnt_reg[1]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_533\,
      \po_stg2_wrcal_cnt_reg[1]_10\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_542\,
      \po_stg2_wrcal_cnt_reg[1]_11\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_543\,
      \po_stg2_wrcal_cnt_reg[1]_12\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_544\,
      \po_stg2_wrcal_cnt_reg[1]_13\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_545\,
      \po_stg2_wrcal_cnt_reg[1]_14\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_546\,
      \po_stg2_wrcal_cnt_reg[1]_15\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_547\,
      \po_stg2_wrcal_cnt_reg[1]_16\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_548\,
      \po_stg2_wrcal_cnt_reg[1]_17\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_549\,
      \po_stg2_wrcal_cnt_reg[1]_18\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_550\,
      \po_stg2_wrcal_cnt_reg[1]_19\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_551\,
      \po_stg2_wrcal_cnt_reg[1]_2\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_534\,
      \po_stg2_wrcal_cnt_reg[1]_20\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_552\,
      \po_stg2_wrcal_cnt_reg[1]_21\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_553\,
      \po_stg2_wrcal_cnt_reg[1]_22\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_554\,
      \po_stg2_wrcal_cnt_reg[1]_23\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_555\,
      \po_stg2_wrcal_cnt_reg[1]_24\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_556\,
      \po_stg2_wrcal_cnt_reg[1]_25\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_557\,
      \po_stg2_wrcal_cnt_reg[1]_26\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_558\,
      \po_stg2_wrcal_cnt_reg[1]_27\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_559\,
      \po_stg2_wrcal_cnt_reg[1]_28\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_560\,
      \po_stg2_wrcal_cnt_reg[1]_29\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_561\,
      \po_stg2_wrcal_cnt_reg[1]_3\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_535\,
      \po_stg2_wrcal_cnt_reg[1]_30\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_562\,
      \po_stg2_wrcal_cnt_reg[1]_31\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_563\,
      \po_stg2_wrcal_cnt_reg[1]_32\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_564\,
      \po_stg2_wrcal_cnt_reg[1]_33\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_565\,
      \po_stg2_wrcal_cnt_reg[1]_34\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_566\,
      \po_stg2_wrcal_cnt_reg[1]_35\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_567\,
      \po_stg2_wrcal_cnt_reg[1]_36\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_568\,
      \po_stg2_wrcal_cnt_reg[1]_37\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_569\,
      \po_stg2_wrcal_cnt_reg[1]_38\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_570\,
      \po_stg2_wrcal_cnt_reg[1]_39\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_571\,
      \po_stg2_wrcal_cnt_reg[1]_4\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_536\,
      \po_stg2_wrcal_cnt_reg[1]_40\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_572\,
      \po_stg2_wrcal_cnt_reg[1]_41\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_573\,
      \po_stg2_wrcal_cnt_reg[1]_42\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_574\,
      \po_stg2_wrcal_cnt_reg[1]_43\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_575\,
      \po_stg2_wrcal_cnt_reg[1]_44\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_576\,
      \po_stg2_wrcal_cnt_reg[1]_45\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_577\,
      \po_stg2_wrcal_cnt_reg[1]_46\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_578\,
      \po_stg2_wrcal_cnt_reg[1]_47\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_579\,
      \po_stg2_wrcal_cnt_reg[1]_48\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_580\,
      \po_stg2_wrcal_cnt_reg[1]_49\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_581\,
      \po_stg2_wrcal_cnt_reg[1]_5\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_537\,
      \po_stg2_wrcal_cnt_reg[1]_50\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_582\,
      \po_stg2_wrcal_cnt_reg[1]_51\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_583\,
      \po_stg2_wrcal_cnt_reg[1]_52\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_584\,
      \po_stg2_wrcal_cnt_reg[1]_53\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_585\,
      \po_stg2_wrcal_cnt_reg[1]_54\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_586\,
      \po_stg2_wrcal_cnt_reg[1]_55\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_587\,
      \po_stg2_wrcal_cnt_reg[1]_56\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_588\,
      \po_stg2_wrcal_cnt_reg[1]_57\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_589\,
      \po_stg2_wrcal_cnt_reg[1]_58\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_590\,
      \po_stg2_wrcal_cnt_reg[1]_59\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_591\,
      \po_stg2_wrcal_cnt_reg[1]_6\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_538\,
      \po_stg2_wrcal_cnt_reg[1]_60\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_592\,
      \po_stg2_wrcal_cnt_reg[1]_61\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_593\,
      \po_stg2_wrcal_cnt_reg[1]_62\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_594\,
      \po_stg2_wrcal_cnt_reg[1]_7\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_539\,
      \po_stg2_wrcal_cnt_reg[1]_8\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_540\,
      \po_stg2_wrcal_cnt_reg[1]_9\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_541\,
      \po_stg2_wrcal_cnt_reg[2]\(2 downto 0) => \po_stg2_wrcal_cnt_reg[2]\(2 downto 0),
      rd_active_r_reg => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_935\,
      rd_active_r_reg_0 => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_936\,
      \rd_mux_sel_r_reg[1]\(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      \rd_ptr_timing_reg[0]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_675\,
      \rd_ptr_timing_reg[0]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_676\,
      \rd_ptr_timing_reg[0]_1\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_677\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]_0\,
      \ref_dll_lock_w__0\(0) => \ref_dll_lock_w__0\(0),
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_0,
      tempmon_pi_f_en_r_reg_0 => tempmon_pi_f_en_r_reg_1,
      tempmon_pi_f_en_r_reg_1 => tempmon_pi_f_en_r_reg_2,
      tempmon_pi_f_en_r_reg_2 => tempmon_pi_f_en_r_reg_3,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_0,
      tempmon_pi_f_inc_r_reg_0 => tempmon_pi_f_inc_r_reg_1,
      tempmon_pi_f_inc_r_reg_1 => tempmon_pi_f_inc_r_reg_2,
      tempmon_pi_f_inc_r_reg_2 => tempmon_pi_f_inc_r_reg_3,
      ts_dqs_0 => ts_dqs_0,
      ts_dqs_1 => ts_dqs_1,
      ts_dqs_2 => ts_dqs_2,
      ts_dqs_3 => ts_dqs_3,
      \write_buffer.wr_buf_out_data_reg[351]\(47 downto 40) => \write_buffer.wr_buf_out_data_reg[383]\(87 downto 80),
      \write_buffer.wr_buf_out_data_reg[351]\(39 downto 32) => \write_buffer.wr_buf_out_data_reg[383]\(71 downto 64),
      \write_buffer.wr_buf_out_data_reg[351]\(31 downto 24) => \write_buffer.wr_buf_out_data_reg[383]\(55 downto 48),
      \write_buffer.wr_buf_out_data_reg[351]\(23 downto 16) => \write_buffer.wr_buf_out_data_reg[383]\(39 downto 32),
      \write_buffer.wr_buf_out_data_reg[351]\(15 downto 0) => \write_buffer.wr_buf_out_data_reg[383]\(15 downto 0),
      \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[449]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[449]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[450]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[450]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[451]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[451]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[453]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[453]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[454]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[454]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[455]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[455]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[457]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[457]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[458]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[458]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[459]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[459]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[461]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[461]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[462]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[462]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[463]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[463]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[465]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[465]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[466]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[466]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[467]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[467]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[469]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[469]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[470]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[470]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[471]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[471]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[473]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[473]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[474]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[474]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[475]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[475]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[477]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[477]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[478]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[478]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[479]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[479]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[571]\(111 downto 108) => \write_buffer.wr_buf_out_data_reg[575]\(219 downto 216),
      \write_buffer.wr_buf_out_data_reg[571]\(107 downto 104) => \write_buffer.wr_buf_out_data_reg[575]\(211 downto 208),
      \write_buffer.wr_buf_out_data_reg[571]\(103 downto 100) => \write_buffer.wr_buf_out_data_reg[575]\(203 downto 200),
      \write_buffer.wr_buf_out_data_reg[571]\(99 downto 96) => \write_buffer.wr_buf_out_data_reg[575]\(195 downto 192),
      \write_buffer.wr_buf_out_data_reg[571]\(95 downto 92) => \write_buffer.wr_buf_out_data_reg[575]\(187 downto 184),
      \write_buffer.wr_buf_out_data_reg[571]\(91 downto 88) => \write_buffer.wr_buf_out_data_reg[575]\(179 downto 176),
      \write_buffer.wr_buf_out_data_reg[571]\(87 downto 84) => \write_buffer.wr_buf_out_data_reg[575]\(171 downto 168),
      \write_buffer.wr_buf_out_data_reg[571]\(83 downto 80) => \write_buffer.wr_buf_out_data_reg[575]\(163 downto 160),
      \write_buffer.wr_buf_out_data_reg[571]\(79 downto 72) => \write_buffer.wr_buf_out_data_reg[575]\(151 downto 144),
      \write_buffer.wr_buf_out_data_reg[571]\(71 downto 64) => \write_buffer.wr_buf_out_data_reg[575]\(135 downto 128),
      \write_buffer.wr_buf_out_data_reg[571]\(63 downto 48) => \write_buffer.wr_buf_out_data_reg[575]\(111 downto 96),
      \write_buffer.wr_buf_out_data_reg[571]\(47 downto 40) => \write_buffer.wr_buf_out_data_reg[575]\(87 downto 80),
      \write_buffer.wr_buf_out_data_reg[571]\(39 downto 32) => \write_buffer.wr_buf_out_data_reg[575]\(71 downto 64),
      \write_buffer.wr_buf_out_data_reg[571]\(31 downto 16) => \write_buffer.wr_buf_out_data_reg[575]\(47 downto 32),
      \write_buffer.wr_buf_out_data_reg[571]\(15 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(15 downto 0)
    );
\ddr_phy_4lanes_1.u_ddr_phy_4lanes\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized0\
     port map (
      CLK => CLK,
      CLKB0 => CLKB0,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      D(5 downto 0) => D(5 downto 0),
      D0(0) => D0(0),
      D1(3 downto 0) => D1(3 downto 0),
      D2(3 downto 0) => D2(3 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D4(3 downto 0) => D4(3 downto 0),
      D5(1 downto 0) => D5(1 downto 0),
      D6(0) => D6(0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D9(3 downto 0) => D9(3 downto 0),
      D_po_coarse_enable105_out => D_po_coarse_enable105_out,
      D_po_counter_read_en117_out => D_po_counter_read_en117_out,
      D_po_fine_enable102_out => D_po_fine_enable102_out,
      D_po_fine_inc108_out => D_po_fine_inc108_out,
      LD0 => LD0,
      PHYCTLWD(10 downto 9) => Q(10 downto 9),
      PHYCTLWD(8 downto 3) => \data_offset_1_i2_reg[5]\(5 downto 0),
      PHYCTLWD(2 downto 0) => Q(2 downto 0),
      Q(5 downto 0) => \pi_counter_read_val_w[2]_5\(5 downto 0),
      RST0 => RST0,
      \_phy_ctl_full_p__0\(1) => \_phy_ctl_full_p__0\(2),
      \_phy_ctl_full_p__0\(0) => \_phy_ctl_full_p__0\(0),
      byte_rd_en_v_0 => byte_rd_en_v_0,
      byte_rd_en_v_1 => byte_rd_en_v_1,
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_0\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_1\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_2\,
      \calib_sel_reg[1]_3\ => \calib_sel_reg[1]_3\,
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_4\,
      \calib_sel_reg[4]\(3 downto 0) => \calib_sel_reg[4]\(3 downto 0),
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg,
      ck_po_stg2_f_indec_reg_0 => ck_po_stg2_f_indec_reg_0,
      ck_po_stg2_f_indec_reg_1 => ck_po_stg2_f_indec_reg_1,
      \cmd_pipe_plus.mc_cas_n_reg[2]\(10 downto 0) => phy_dout(10 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0),
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_936\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_935\,
      freq_refclk => freq_refclk,
      \gen_byte_sel_div2.calib_in_common_reg\ => \gen_byte_sel_div2.calib_in_common_reg\,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => \gen_byte_sel_div2.calib_in_common_reg_0\,
      \gen_byte_sel_div2.calib_in_common_reg_1\ => \gen_byte_sel_div2.calib_in_common_reg_1\,
      \gen_byte_sel_div2.calib_in_common_reg_2\ => \gen_byte_sel_div2.calib_in_common_reg_2\,
      \gen_byte_sel_div2.calib_in_common_reg_3\ => \gen_byte_sel_div2.calib_in_common_reg_3\,
      \gen_byte_sel_div2.calib_in_common_reg_4\ => \gen_byte_sel_div2.calib_in_common_reg_4\,
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      if_empty_or_v(0) => if_empty_or_v(2),
      ififo_rst_reg0 => ififo_rst_reg0,
      in0 => in0,
      init_calib_complete_reg(21 downto 0) => init_calib_complete_reg(21 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\(3 downto 0) => \init_calib_complete_reg_rep__10\(3 downto 0),
      \init_calib_complete_reg_rep__10_0\(3 downto 0) => \init_calib_complete_reg_rep__10_0\(3 downto 0),
      \init_calib_complete_reg_rep__10_1\(3 downto 0) => \init_calib_complete_reg_rep__10_1\(3 downto 0),
      \init_calib_complete_reg_rep__10_2\ => \init_calib_complete_reg_rep__10_2\,
      \init_calib_complete_reg_rep__11\(7 downto 0) => \init_calib_complete_reg_rep__11\(7 downto 0),
      \init_calib_complete_reg_rep__11_0\(7 downto 0) => \init_calib_complete_reg_rep__11_0\(7 downto 0),
      \init_calib_complete_reg_rep__11_1\ => \init_calib_complete_reg_rep__11_1\,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      \init_calib_complete_reg_rep__12_0\(3 downto 0) => \init_calib_complete_reg_rep__12_0\(3 downto 0),
      \init_calib_complete_reg_rep__12_1\(3 downto 0) => \init_calib_complete_reg_rep__12_1\(3 downto 0),
      \init_calib_complete_reg_rep__12_2\(3 downto 0) => \init_calib_complete_reg_rep__12_2\(3 downto 0),
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__25\(45 downto 0) => \init_calib_complete_reg_rep__25\(45 downto 0),
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      mcGo_r1 => mcGo_r1,
      \mcGo_w__0\(1) => \mcGo_w__0\(2),
      \mcGo_w__0\(0) => \mcGo_w__0\(0),
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      mem_dq_in(7 downto 0) => mem_dq_in(39 downto 32),
      mem_dq_out(31 downto 0) => mem_dq_out(67 downto 36),
      mem_dq_ts(8 downto 0) => mem_dq_ts(44 downto 36),
      mem_dqs_in(0) => mem_dqs_in(4),
      mem_out(10 downto 0) => mem_out(10 downto 0),
      mem_refclk => mem_refclk,
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_9\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[100]\ => \^not_strict_mode.app_rd_data_reg[100]\,
      \not_strict_mode.app_rd_data_reg[101]\ => \^not_strict_mode.app_rd_data_reg[101]\,
      \not_strict_mode.app_rd_data_reg[102]\ => \^not_strict_mode.app_rd_data_reg[102]\,
      \not_strict_mode.app_rd_data_reg[103]\ => \^not_strict_mode.app_rd_data_reg[103]\,
      \not_strict_mode.app_rd_data_reg[160]\ => \^not_strict_mode.app_rd_data_reg[160]\,
      \not_strict_mode.app_rd_data_reg[161]\ => \^not_strict_mode.app_rd_data_reg[161]\,
      \not_strict_mode.app_rd_data_reg[162]\ => \^not_strict_mode.app_rd_data_reg[162]\,
      \not_strict_mode.app_rd_data_reg[163]\ => \^not_strict_mode.app_rd_data_reg[163]\,
      \not_strict_mode.app_rd_data_reg[164]\ => \^not_strict_mode.app_rd_data_reg[164]\,
      \not_strict_mode.app_rd_data_reg[165]\ => \^not_strict_mode.app_rd_data_reg[165]\,
      \not_strict_mode.app_rd_data_reg[166]\ => \^not_strict_mode.app_rd_data_reg[166]\,
      \not_strict_mode.app_rd_data_reg[167]\ => \^not_strict_mode.app_rd_data_reg[167]\,
      \not_strict_mode.app_rd_data_reg[224]\ => \^not_strict_mode.app_rd_data_reg[224]\,
      \not_strict_mode.app_rd_data_reg[225]\ => \^not_strict_mode.app_rd_data_reg[225]\,
      \not_strict_mode.app_rd_data_reg[226]\ => \^not_strict_mode.app_rd_data_reg[226]\,
      \not_strict_mode.app_rd_data_reg[227]\ => \^not_strict_mode.app_rd_data_reg[227]\,
      \not_strict_mode.app_rd_data_reg[228]\ => \^not_strict_mode.app_rd_data_reg[228]\,
      \not_strict_mode.app_rd_data_reg[229]\ => \^not_strict_mode.app_rd_data_reg[229]\,
      \not_strict_mode.app_rd_data_reg[230]\ => \^not_strict_mode.app_rd_data_reg[230]\,
      \not_strict_mode.app_rd_data_reg[231]\ => \^not_strict_mode.app_rd_data_reg[231]\,
      \not_strict_mode.app_rd_data_reg[288]\ => \^not_strict_mode.app_rd_data_reg[288]\,
      \not_strict_mode.app_rd_data_reg[289]\ => \^not_strict_mode.app_rd_data_reg[289]\,
      \not_strict_mode.app_rd_data_reg[290]\ => \^not_strict_mode.app_rd_data_reg[290]\,
      \not_strict_mode.app_rd_data_reg[291]\ => \^not_strict_mode.app_rd_data_reg[291]\,
      \not_strict_mode.app_rd_data_reg[292]\ => \^not_strict_mode.app_rd_data_reg[292]\,
      \not_strict_mode.app_rd_data_reg[293]\ => \^not_strict_mode.app_rd_data_reg[293]\,
      \not_strict_mode.app_rd_data_reg[294]\ => \^not_strict_mode.app_rd_data_reg[294]\,
      \not_strict_mode.app_rd_data_reg[295]\ => \^not_strict_mode.app_rd_data_reg[295]\,
      \not_strict_mode.app_rd_data_reg[32]\ => \^not_strict_mode.app_rd_data_reg[32]\,
      \not_strict_mode.app_rd_data_reg[33]\ => \^not_strict_mode.app_rd_data_reg[33]\,
      \not_strict_mode.app_rd_data_reg[34]\ => \^not_strict_mode.app_rd_data_reg[34]\,
      \not_strict_mode.app_rd_data_reg[352]\ => \^not_strict_mode.app_rd_data_reg[352]\,
      \not_strict_mode.app_rd_data_reg[353]\ => \^not_strict_mode.app_rd_data_reg[353]\,
      \not_strict_mode.app_rd_data_reg[354]\ => \^not_strict_mode.app_rd_data_reg[354]\,
      \not_strict_mode.app_rd_data_reg[355]\ => \^not_strict_mode.app_rd_data_reg[355]\,
      \not_strict_mode.app_rd_data_reg[356]\ => \^not_strict_mode.app_rd_data_reg[356]\,
      \not_strict_mode.app_rd_data_reg[357]\ => \^not_strict_mode.app_rd_data_reg[357]\,
      \not_strict_mode.app_rd_data_reg[358]\ => \^not_strict_mode.app_rd_data_reg[358]\,
      \not_strict_mode.app_rd_data_reg[359]\ => \^not_strict_mode.app_rd_data_reg[359]\,
      \not_strict_mode.app_rd_data_reg[35]\ => \^not_strict_mode.app_rd_data_reg[35]\,
      \not_strict_mode.app_rd_data_reg[36]\ => \^not_strict_mode.app_rd_data_reg[36]\,
      \not_strict_mode.app_rd_data_reg[37]\ => \^not_strict_mode.app_rd_data_reg[37]\,
      \not_strict_mode.app_rd_data_reg[38]\ => \^not_strict_mode.app_rd_data_reg[38]\,
      \not_strict_mode.app_rd_data_reg[39]\ => \^not_strict_mode.app_rd_data_reg[39]\,
      \not_strict_mode.app_rd_data_reg[416]\ => \^not_strict_mode.app_rd_data_reg[416]\,
      \not_strict_mode.app_rd_data_reg[417]\ => \^not_strict_mode.app_rd_data_reg[417]\,
      \not_strict_mode.app_rd_data_reg[418]\ => \^not_strict_mode.app_rd_data_reg[418]\,
      \not_strict_mode.app_rd_data_reg[419]\ => \^not_strict_mode.app_rd_data_reg[419]\,
      \not_strict_mode.app_rd_data_reg[420]\ => \^not_strict_mode.app_rd_data_reg[420]\,
      \not_strict_mode.app_rd_data_reg[421]\ => \^not_strict_mode.app_rd_data_reg[421]\,
      \not_strict_mode.app_rd_data_reg[422]\ => \^not_strict_mode.app_rd_data_reg[422]\,
      \not_strict_mode.app_rd_data_reg[423]\ => \^not_strict_mode.app_rd_data_reg[423]\,
      \not_strict_mode.app_rd_data_reg[480]\ => \^not_strict_mode.app_rd_data_reg[480]\,
      \not_strict_mode.app_rd_data_reg[481]\ => \^not_strict_mode.app_rd_data_reg[481]\,
      \not_strict_mode.app_rd_data_reg[482]\ => \^not_strict_mode.app_rd_data_reg[482]\,
      \not_strict_mode.app_rd_data_reg[483]\ => \^not_strict_mode.app_rd_data_reg[483]\,
      \not_strict_mode.app_rd_data_reg[484]\ => \^not_strict_mode.app_rd_data_reg[484]\,
      \not_strict_mode.app_rd_data_reg[485]\ => \^not_strict_mode.app_rd_data_reg[485]\,
      \not_strict_mode.app_rd_data_reg[486]\ => \^not_strict_mode.app_rd_data_reg[486]\,
      \not_strict_mode.app_rd_data_reg[487]\(63 downto 56) => \not_strict_mode.app_rd_data_reg[511]_0\(487 downto 480),
      \not_strict_mode.app_rd_data_reg[487]\(55 downto 48) => \not_strict_mode.app_rd_data_reg[511]_0\(423 downto 416),
      \not_strict_mode.app_rd_data_reg[487]\(47 downto 40) => \not_strict_mode.app_rd_data_reg[511]_0\(359 downto 352),
      \not_strict_mode.app_rd_data_reg[487]\(39 downto 32) => \not_strict_mode.app_rd_data_reg[511]_0\(295 downto 288),
      \not_strict_mode.app_rd_data_reg[487]\(31 downto 24) => \not_strict_mode.app_rd_data_reg[511]_0\(231 downto 224),
      \not_strict_mode.app_rd_data_reg[487]\(23 downto 16) => \not_strict_mode.app_rd_data_reg[511]_0\(167 downto 160),
      \not_strict_mode.app_rd_data_reg[487]\(15 downto 8) => \not_strict_mode.app_rd_data_reg[511]_0\(103 downto 96),
      \not_strict_mode.app_rd_data_reg[487]\(7 downto 0) => \not_strict_mode.app_rd_data_reg[511]_0\(39 downto 32),
      \not_strict_mode.app_rd_data_reg[487]_0\ => \^not_strict_mode.app_rd_data_reg[487]\,
      \not_strict_mode.app_rd_data_reg[96]\ => \^not_strict_mode.app_rd_data_reg[96]\,
      \not_strict_mode.app_rd_data_reg[97]\ => \^not_strict_mode.app_rd_data_reg[97]\,
      \not_strict_mode.app_rd_data_reg[98]\ => \^not_strict_mode.app_rd_data_reg[98]\,
      \not_strict_mode.app_rd_data_reg[99]\ => \^not_strict_mode.app_rd_data_reg[99]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \not_strict_mode.rd_buf_we\,
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\ => \not_strict_mode.status_ram.rd_buf_we_r1_reg\,
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofifo_rst_reg => ofifo_rst_reg,
      ofifo_rst_reg0 => ofifo_rst_reg0,
      \out\ => \out\,
      out_dqs_4 => out_dqs_4,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_ctl_mstr_empty => phy_ctl_mstr_empty,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(71) => mux_wrdata_mask(60),
      phy_dout(70) => mux_wrdata_mask(52),
      phy_dout(69) => mux_wrdata_mask(44),
      phy_dout(68) => mux_wrdata_mask(36),
      phy_dout(67) => mux_wrdata_mask(28),
      phy_dout(66) => mux_wrdata_mask(20),
      phy_dout(65) => mux_wrdata_mask(12),
      phy_dout(64) => mux_wrdata_mask(4),
      phy_dout(63) => mux_wrdata(384),
      phy_dout(62) => mux_wrdata(320),
      phy_dout(61) => mux_wrdata(264),
      phy_dout(60) => mux_wrdata(216),
      phy_dout(59) => mux_wrdata(168),
      phy_dout(58) => mux_wrdata(120),
      phy_dout(57) => mux_wrdata(64),
      phy_dout(56) => \write_buffer.wr_buf_out_data_reg[383]\(16),
      phy_dout(55) => mux_wrdata(385),
      phy_dout(54) => mux_wrdata(321),
      phy_dout(53) => mux_wrdata(265),
      phy_dout(52) => mux_wrdata(217),
      phy_dout(51) => mux_wrdata(169),
      phy_dout(50) => \write_buffer.wr_buf_out_data_reg[383]\(40),
      phy_dout(49) => mux_wrdata(65),
      phy_dout(48) => mux_wrdata(16),
      phy_dout(47) => mux_wrdata(386),
      phy_dout(46) => mux_wrdata(322),
      phy_dout(45) => mux_wrdata(266),
      phy_dout(44) => \write_buffer.wr_buf_out_data_reg[383]\(72),
      phy_dout(43) => \write_buffer.wr_buf_out_data_reg[383]\(56),
      phy_dout(42) => mux_wrdata(121),
      phy_dout(41) => mux_wrdata(66),
      phy_dout(40) => mux_wrdata(17),
      phy_dout(39) => mux_wrdata(387),
      phy_dout(38) => mux_wrdata(323),
      phy_dout(37) => \write_buffer.wr_buf_out_data_reg[383]\(88),
      phy_dout(36) => mux_wrdata(218),
      phy_dout(35) => mux_wrdata(170),
      phy_dout(34) => mux_wrdata(122),
      phy_dout(33) => mux_wrdata(67),
      phy_dout(32) => \write_buffer.wr_buf_out_data_reg[383]\(17),
      phy_dout(31) => mux_wrdata(388),
      phy_dout(30) => mux_wrdata(324),
      phy_dout(29) => mux_wrdata(267),
      phy_dout(28) => mux_wrdata(219),
      phy_dout(27) => mux_wrdata(171),
      phy_dout(26) => mux_wrdata(123),
      phy_dout(25) => mux_wrdata(68),
      phy_dout(24) => \write_buffer.wr_buf_out_data_reg[383]\(18),
      phy_dout(23) => mux_wrdata(389),
      phy_dout(22) => mux_wrdata(325),
      phy_dout(21) => mux_wrdata(268),
      phy_dout(20) => mux_wrdata(220),
      phy_dout(19) => mux_wrdata(172),
      phy_dout(18) => \write_buffer.wr_buf_out_data_reg[383]\(41),
      phy_dout(17) => mux_wrdata(69),
      phy_dout(16) => mux_wrdata(18),
      phy_dout(15) => mux_wrdata(390),
      phy_dout(14) => mux_wrdata(326),
      phy_dout(13) => mux_wrdata(269),
      phy_dout(12) => \write_buffer.wr_buf_out_data_reg[383]\(73),
      phy_dout(11) => \write_buffer.wr_buf_out_data_reg[383]\(57),
      phy_dout(10) => mux_wrdata(124),
      phy_dout(9) => mux_wrdata(70),
      phy_dout(8) => mux_wrdata(19),
      phy_dout(7) => mux_wrdata(391),
      phy_dout(6) => mux_wrdata(327),
      phy_dout(5) => \write_buffer.wr_buf_out_data_reg[383]\(89),
      phy_dout(4) => mux_wrdata(221),
      phy_dout(3) => mux_wrdata(173),
      phy_dout(2) => mux_wrdata(125),
      phy_dout(1) => mux_wrdata(71),
      phy_dout(0) => \write_buffer.wr_buf_out_data_reg[383]\(19),
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      \pi_counter_read_val_reg[5]_0\(5 downto 0) => \pi_counter_read_val_w[0]_3\(5 downto 0),
      pi_dqs_found_lanes(0) => pi_dqs_found_lanes(4),
      pi_phase_locked_all_r1_reg => \ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_46\,
      \pi_rdval_cnt_reg[0]\ => \pi_rdval_cnt_reg[0]\,
      \pi_rdval_cnt_reg[1]\ => \pi_rdval_cnt_reg[1]\,
      \pi_rdval_cnt_reg[2]\ => \pi_rdval_cnt_reg[2]\,
      \pi_rdval_cnt_reg[3]\ => \pi_rdval_cnt_reg[3]\,
      \pi_rdval_cnt_reg[4]\ => \pi_rdval_cnt_reg[4]\,
      \pi_rdval_cnt_reg[5]\ => \pi_rdval_cnt_reg[5]\,
      pll_locked => pll_locked,
      \po_counter_read_val_reg[8]_0\(8 downto 0) => \po_counter_read_val_w[2]_4\(8 downto 0),
      \po_counter_read_val_reg[8]_1\(8 downto 0) => \po_counter_read_val_w[0]_2\(8 downto 0),
      \po_rdval_cnt_reg[0]\ => \po_rdval_cnt_reg[0]\,
      \po_rdval_cnt_reg[1]\ => \po_rdval_cnt_reg[1]\,
      \po_rdval_cnt_reg[2]\ => \po_rdval_cnt_reg[2]\,
      \po_rdval_cnt_reg[3]\ => \po_rdval_cnt_reg[3]\,
      \po_rdval_cnt_reg[4]\ => \po_rdval_cnt_reg[4]\,
      \po_rdval_cnt_reg[5]\ => \po_rdval_cnt_reg[5]\,
      \po_rdval_cnt_reg[6]\ => \po_rdval_cnt_reg[6]\,
      \po_rdval_cnt_reg[7]\ => \po_rdval_cnt_reg[7]\,
      \po_rdval_cnt_reg[8]\ => \po_rdval_cnt_reg[8]\,
      pre_data_a_full_v(0) => pre_data_a_full_v(1),
      ram_init_done_r => ram_init_done_r,
      \rd_ptr_timing_reg[0]\(44 downto 0) => \rd_ptr_timing_reg[0]\(44 downto 0),
      \rd_ptr_timing_reg[0]_0\(15 downto 0) => \rd_ptr_timing_reg[0]_0\(15 downto 0),
      \read_fifo.fifo_out_data_r_reg[6]\(0) => \read_fifo.fifo_out_data_r_reg[6]\(0),
      \read_fifo.fifo_out_data_r_reg[6]_0\ => \read_fifo.fifo_out_data_r_reg[6]_0\,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\,
      \ref_dll_lock_w__0\(1) => \ref_dll_lock_w__0\(2),
      \ref_dll_lock_w__0\(0) => \ref_dll_lock_w__0\(0),
      rst_sync_r1_reg => rst_sync_r1_reg,
      store_sr_req_r_reg => store_sr_req_r_reg,
      sync_pulse => sync_pulse,
      sys_rst => sys_rst,
      sys_rst_0 => sys_rst_0,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg,
      ts_dqs_4 => ts_dqs_4,
      \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[481]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[481]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[482]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[482]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[483]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[483]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[485]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[485]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[486]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[486]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[487]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[487]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[572]\(27) => \write_buffer.wr_buf_out_data_reg[575]\(220),
      \write_buffer.wr_buf_out_data_reg[572]\(26) => \write_buffer.wr_buf_out_data_reg[575]\(212),
      \write_buffer.wr_buf_out_data_reg[572]\(25) => \write_buffer.wr_buf_out_data_reg[575]\(204),
      \write_buffer.wr_buf_out_data_reg[572]\(24) => \write_buffer.wr_buf_out_data_reg[575]\(196),
      \write_buffer.wr_buf_out_data_reg[572]\(23) => \write_buffer.wr_buf_out_data_reg[575]\(188),
      \write_buffer.wr_buf_out_data_reg[572]\(22) => \write_buffer.wr_buf_out_data_reg[575]\(180),
      \write_buffer.wr_buf_out_data_reg[572]\(21) => \write_buffer.wr_buf_out_data_reg[575]\(172),
      \write_buffer.wr_buf_out_data_reg[572]\(20) => \write_buffer.wr_buf_out_data_reg[575]\(164),
      \write_buffer.wr_buf_out_data_reg[572]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[575]\(153 downto 152),
      \write_buffer.wr_buf_out_data_reg[572]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[575]\(137 downto 136),
      \write_buffer.wr_buf_out_data_reg[572]\(15 downto 12) => \write_buffer.wr_buf_out_data_reg[575]\(115 downto 112),
      \write_buffer.wr_buf_out_data_reg[572]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[575]\(89 downto 88),
      \write_buffer.wr_buf_out_data_reg[572]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[575]\(73 downto 72),
      \write_buffer.wr_buf_out_data_reg[572]\(7 downto 4) => \write_buffer.wr_buf_out_data_reg[575]\(51 downto 48),
      \write_buffer.wr_buf_out_data_reg[572]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(19 downto 16)
    );
\ddr_phy_4lanes_2.u_ddr_phy_4lanes\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_phy_4lanes__parameterized1\
     port map (
      A_byte_rd_en => A_byte_rd_en,
      A_rst_primitives_reg_0 => \ddr_phy_4lanes_1.u_ddr_phy_4lanes_n_46\,
      A_rst_primitives_reg_1 => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_938\,
      B_byte_rd_en => B_byte_rd_en,
      CLK => CLK,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      C_byte_rd_en => C_byte_rd_en,
      LD0_10 => LD0_10,
      LD0_12 => LD0_12,
      LD0_14 => LD0_14,
      PHYCTLWD(10 downto 9) => Q(10 downto 9),
      PHYCTLWD(8 downto 3) => \data_offset_2_i2_reg[5]\(5 downto 0),
      PHYCTLWD(2 downto 0) => Q(2 downto 0),
      Q(8 downto 0) => \po_counter_read_val_w[2]_4\(8 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      \_phy_ctl_full_p__0\(0) => \_phy_ctl_full_p__0\(2),
      byte_rd_en_v_2 => byte_rd_en_v_2,
      \calib_sel_reg[0]\ => \calib_sel_reg[0]_1\,
      \calib_sel_reg[0]_0\ => \calib_sel_reg[0]_2\,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]_26\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_27\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_28\,
      \calib_sel_reg[1]_10\(5 downto 0) => \calib_sel_reg[1]_37\(5 downto 0),
      \calib_sel_reg[1]_11\ => \calib_sel_reg[1]_38\,
      \calib_sel_reg[1]_12\ => \calib_sel_reg[1]_39\,
      \calib_sel_reg[1]_13\(1 downto 0) => \calib_sel_reg[4]\(1 downto 0),
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_29\,
      \calib_sel_reg[1]_3\(5 downto 0) => \calib_sel_reg[1]_30\(5 downto 0),
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_31\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_32\,
      \calib_sel_reg[1]_6\ => \calib_sel_reg[1]_33\,
      \calib_sel_reg[1]_7\ => \calib_sel_reg[1]_34\,
      \calib_sel_reg[1]_8\ => \calib_sel_reg[1]_35\,
      \calib_sel_reg[1]_9\ => \calib_sel_reg[1]_36\,
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg_6,
      ck_po_stg2_f_indec_reg_0 => ck_po_stg2_f_indec_reg_7,
      ck_po_stg2_f_indec_reg_1 => ck_po_stg2_f_indec_reg_8,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_675\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_676\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_677\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \^not_strict_mode.app_rd_data_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ => \^not_strict_mode.app_rd_data_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\ => \^not_strict_mode.app_rd_data_reg[158]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\ => \^not_strict_mode.app_rd_data_reg[166]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ => \^not_strict_mode.app_rd_data_reg[222]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ => \^not_strict_mode.app_rd_data_reg[230]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ => \^not_strict_mode.app_rd_data_reg[286]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ => \^not_strict_mode.app_rd_data_reg[294]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ => \^not_strict_mode.app_rd_data_reg[350]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ => \^not_strict_mode.app_rd_data_reg[358]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ => \^not_strict_mode.app_rd_data_reg[414]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ => \^not_strict_mode.app_rd_data_reg[422]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ => \^not_strict_mode.app_rd_data_reg[478]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ => \^not_strict_mode.app_rd_data_reg[486]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \^not_strict_mode.app_rd_data_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^not_strict_mode.app_rd_data_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\ => \^not_strict_mode.app_rd_data_reg[93]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\ => \^not_strict_mode.app_rd_data_reg[101]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\ => \^not_strict_mode.app_rd_data_reg[157]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\ => \^not_strict_mode.app_rd_data_reg[165]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\ => \^not_strict_mode.app_rd_data_reg[221]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\ => \^not_strict_mode.app_rd_data_reg[229]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\ => \^not_strict_mode.app_rd_data_reg[95]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\ => \^not_strict_mode.app_rd_data_reg[103]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\ => \^not_strict_mode.app_rd_data_reg[285]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\ => \^not_strict_mode.app_rd_data_reg[293]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\ => \^not_strict_mode.app_rd_data_reg[349]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\ => \^not_strict_mode.app_rd_data_reg[357]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\ => \^not_strict_mode.app_rd_data_reg[413]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\ => \^not_strict_mode.app_rd_data_reg[421]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\ => \^not_strict_mode.app_rd_data_reg[477]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\ => \^not_strict_mode.app_rd_data_reg[485]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \^not_strict_mode.app_rd_data_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^not_strict_mode.app_rd_data_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\ => \^not_strict_mode.app_rd_data_reg[92]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\ => \^not_strict_mode.app_rd_data_reg[100]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\ => \^not_strict_mode.app_rd_data_reg[156]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\ => \^not_strict_mode.app_rd_data_reg[164]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\ => \^not_strict_mode.app_rd_data_reg[220]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\ => \^not_strict_mode.app_rd_data_reg[228]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\ => \^not_strict_mode.app_rd_data_reg[284]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\ => \^not_strict_mode.app_rd_data_reg[292]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\ => \^not_strict_mode.app_rd_data_reg[348]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\ => \^not_strict_mode.app_rd_data_reg[356]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\ => \^not_strict_mode.app_rd_data_reg[159]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\ => \^not_strict_mode.app_rd_data_reg[167]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\ => \^not_strict_mode.app_rd_data_reg[412]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\ => \^not_strict_mode.app_rd_data_reg[420]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\ => \^not_strict_mode.app_rd_data_reg[476]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\ => \^not_strict_mode.app_rd_data_reg[484]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \^not_strict_mode.app_rd_data_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^not_strict_mode.app_rd_data_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ => \^not_strict_mode.app_rd_data_reg[91]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ => \^not_strict_mode.app_rd_data_reg[99]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ => \^not_strict_mode.app_rd_data_reg[155]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ => \^not_strict_mode.app_rd_data_reg[163]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ => \^not_strict_mode.app_rd_data_reg[219]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ => \^not_strict_mode.app_rd_data_reg[227]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ => \^not_strict_mode.app_rd_data_reg[283]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ => \^not_strict_mode.app_rd_data_reg[291]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ => \^not_strict_mode.app_rd_data_reg[347]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ => \^not_strict_mode.app_rd_data_reg[355]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ => \^not_strict_mode.app_rd_data_reg[411]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ => \^not_strict_mode.app_rd_data_reg[419]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ => \^not_strict_mode.app_rd_data_reg[475]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ => \^not_strict_mode.app_rd_data_reg[483]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\ => \^not_strict_mode.app_rd_data_reg[223]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\ => \^not_strict_mode.app_rd_data_reg[231]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \^not_strict_mode.app_rd_data_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^not_strict_mode.app_rd_data_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ => \^not_strict_mode.app_rd_data_reg[90]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ => \^not_strict_mode.app_rd_data_reg[98]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ => \^not_strict_mode.app_rd_data_reg[154]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ => \^not_strict_mode.app_rd_data_reg[162]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ => \^not_strict_mode.app_rd_data_reg[218]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ => \^not_strict_mode.app_rd_data_reg[226]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ => \^not_strict_mode.app_rd_data_reg[282]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ => \^not_strict_mode.app_rd_data_reg[290]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ => \^not_strict_mode.app_rd_data_reg[346]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ => \^not_strict_mode.app_rd_data_reg[354]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ => \^not_strict_mode.app_rd_data_reg[410]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ => \^not_strict_mode.app_rd_data_reg[418]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ => \^not_strict_mode.app_rd_data_reg[474]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ => \^not_strict_mode.app_rd_data_reg[482]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \^not_strict_mode.app_rd_data_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^not_strict_mode.app_rd_data_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\ => \^not_strict_mode.app_rd_data_reg[89]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\ => \^not_strict_mode.app_rd_data_reg[97]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\ => \^not_strict_mode.app_rd_data_reg[287]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\ => \^not_strict_mode.app_rd_data_reg[295]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\ => \^not_strict_mode.app_rd_data_reg[153]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\ => \^not_strict_mode.app_rd_data_reg[161]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\ => \^not_strict_mode.app_rd_data_reg[217]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\ => \^not_strict_mode.app_rd_data_reg[225]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\ => \^not_strict_mode.app_rd_data_reg[281]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\ => \^not_strict_mode.app_rd_data_reg[289]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\ => \^not_strict_mode.app_rd_data_reg[345]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\ => \^not_strict_mode.app_rd_data_reg[353]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\ => \^not_strict_mode.app_rd_data_reg[409]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\ => \^not_strict_mode.app_rd_data_reg[417]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\ => \^not_strict_mode.app_rd_data_reg[473]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\ => \^not_strict_mode.app_rd_data_reg[481]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \^not_strict_mode.app_rd_data_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^not_strict_mode.app_rd_data_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ => \^not_strict_mode.app_rd_data_reg[88]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ => \^not_strict_mode.app_rd_data_reg[96]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ => \^not_strict_mode.app_rd_data_reg[152]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ => \^not_strict_mode.app_rd_data_reg[160]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ => \^not_strict_mode.app_rd_data_reg[216]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ => \^not_strict_mode.app_rd_data_reg[224]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\ => \^not_strict_mode.app_rd_data_reg[351]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\ => \^not_strict_mode.app_rd_data_reg[359]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ => \^not_strict_mode.app_rd_data_reg[280]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ => \^not_strict_mode.app_rd_data_reg[288]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ => \^not_strict_mode.app_rd_data_reg[344]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ => \^not_strict_mode.app_rd_data_reg[352]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ => \^not_strict_mode.app_rd_data_reg[408]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ => \^not_strict_mode.app_rd_data_reg[416]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ => \^not_strict_mode.app_rd_data_reg[472]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ => \^not_strict_mode.app_rd_data_reg[480]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\ => \^not_strict_mode.app_rd_data_reg[415]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\ => \^not_strict_mode.app_rd_data_reg[423]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\ => \^not_strict_mode.app_rd_data_reg[479]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\ => \^not_strict_mode.app_rd_data_reg[487]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \^not_strict_mode.app_rd_data_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \^not_strict_mode.app_rd_data_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\ => \^not_strict_mode.app_rd_data_reg[94]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\ => \^not_strict_mode.app_rd_data_reg[102]\,
      dqs_wl_po_stg2_c_incdec_reg => dqs_wl_po_stg2_c_incdec_reg_0,
      \entry_cnt_reg[2]\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_934\,
      \entry_cnt_reg[2]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_933\,
      freq_refclk => freq_refclk,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_547\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_587\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_563\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_539\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_579\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_531\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_555\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_571\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_548\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_588\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_564\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_540\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_580\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_532\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_556\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_572\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_549\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_589\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_565\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_541\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_581\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_533\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_557\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_573\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_550\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_590\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_566\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_542\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_582\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_534\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_558\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_574\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_551\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_591\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_567\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_543\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_583\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_535\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_559\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_575\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_552\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_592\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_568\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_544\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_584\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_536\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_560\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_576\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_553\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_593\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_569\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_545\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_585\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_537\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_561\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_577\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_554\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_594\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_570\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_546\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_586\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_538\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_562\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_578\,
      idelay_ce_r2_reg => idelay_ce_r2_reg_0,
      idelay_inc => idelay_inc,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      if_empty_or_v(0) => if_empty_or_v(2),
      in0 => in0,
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\ => \init_calib_complete_reg_rep__10_2\,
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__8\ => \init_calib_complete_reg_rep__8\,
      \mcGo_w__0\(0) => \mcGo_w__0\(2),
      mem_dq_in(23 downto 0) => mem_dq_in(63 downto 40),
      mem_dq_out(26 downto 0) => mem_dq_out(94 downto 68),
      mem_dq_ts(26 downto 0) => mem_dq_ts(71 downto 45),
      mem_dqs_in(2 downto 0) => mem_dqs_in(7 downto 5),
      mem_refclk => mem_refclk,
      mux_wrdata(155 downto 132) => mux_wrdata(415 downto 392),
      mux_wrdata(131 downto 108) => mux_wrdata(351 downto 328),
      mux_wrdata(107 downto 90) => mux_wrdata(287 downto 270),
      mux_wrdata(89 downto 72) => mux_wrdata(239 downto 222),
      mux_wrdata(71 downto 54) => mux_wrdata(191 downto 174),
      mux_wrdata(53 downto 36) => mux_wrdata(143 downto 126),
      mux_wrdata(35 downto 12) => mux_wrdata(95 downto 72),
      mux_wrdata(11 downto 0) => mux_wrdata(31 downto 20),
      mux_wrdata_mask(23 downto 21) => mux_wrdata_mask(63 downto 61),
      mux_wrdata_mask(20 downto 18) => mux_wrdata_mask(55 downto 53),
      mux_wrdata_mask(17 downto 15) => mux_wrdata_mask(47 downto 45),
      mux_wrdata_mask(14 downto 12) => mux_wrdata_mask(39 downto 37),
      mux_wrdata_mask(11 downto 9) => mux_wrdata_mask(31 downto 29),
      mux_wrdata_mask(8 downto 6) => mux_wrdata_mask(23 downto 21),
      mux_wrdata_mask(5 downto 3) => mux_wrdata_mask(15 downto 13),
      mux_wrdata_mask(2 downto 0) => mux_wrdata_mask(7 downto 5),
      \my_empty_reg[1]\ => \my_empty_reg[1]_6\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_7\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_8\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]_4\(43 downto 0),
      \my_empty_reg[7]_0\(43 downto 0) => \my_empty_reg[7]_5\(43 downto 0),
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]_6\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[104]\ => \not_strict_mode.app_rd_data_reg[104]\,
      \not_strict_mode.app_rd_data_reg[105]\ => \not_strict_mode.app_rd_data_reg[105]\,
      \not_strict_mode.app_rd_data_reg[106]\ => \not_strict_mode.app_rd_data_reg[106]\,
      \not_strict_mode.app_rd_data_reg[107]\ => \not_strict_mode.app_rd_data_reg[107]\,
      \not_strict_mode.app_rd_data_reg[108]\ => \not_strict_mode.app_rd_data_reg[108]\,
      \not_strict_mode.app_rd_data_reg[109]\ => \not_strict_mode.app_rd_data_reg[109]\,
      \not_strict_mode.app_rd_data_reg[110]\ => \not_strict_mode.app_rd_data_reg[110]\,
      \not_strict_mode.app_rd_data_reg[111]\ => \not_strict_mode.app_rd_data_reg[111]\,
      \not_strict_mode.app_rd_data_reg[112]\ => \not_strict_mode.app_rd_data_reg[112]\,
      \not_strict_mode.app_rd_data_reg[113]\ => \not_strict_mode.app_rd_data_reg[113]\,
      \not_strict_mode.app_rd_data_reg[114]\ => \not_strict_mode.app_rd_data_reg[114]\,
      \not_strict_mode.app_rd_data_reg[115]\ => \not_strict_mode.app_rd_data_reg[115]\,
      \not_strict_mode.app_rd_data_reg[116]\ => \not_strict_mode.app_rd_data_reg[116]\,
      \not_strict_mode.app_rd_data_reg[117]\ => \not_strict_mode.app_rd_data_reg[117]\,
      \not_strict_mode.app_rd_data_reg[118]\ => \not_strict_mode.app_rd_data_reg[118]\,
      \not_strict_mode.app_rd_data_reg[119]\ => \not_strict_mode.app_rd_data_reg[119]\,
      \not_strict_mode.app_rd_data_reg[120]\ => \^not_strict_mode.app_rd_data_reg[120]\,
      \not_strict_mode.app_rd_data_reg[121]\ => \^not_strict_mode.app_rd_data_reg[121]\,
      \not_strict_mode.app_rd_data_reg[122]\ => \^not_strict_mode.app_rd_data_reg[122]\,
      \not_strict_mode.app_rd_data_reg[123]\ => \^not_strict_mode.app_rd_data_reg[123]\,
      \not_strict_mode.app_rd_data_reg[124]\ => \^not_strict_mode.app_rd_data_reg[124]\,
      \not_strict_mode.app_rd_data_reg[125]\ => \^not_strict_mode.app_rd_data_reg[125]\,
      \not_strict_mode.app_rd_data_reg[126]\ => \^not_strict_mode.app_rd_data_reg[126]\,
      \not_strict_mode.app_rd_data_reg[127]\ => \^not_strict_mode.app_rd_data_reg[127]\,
      \not_strict_mode.app_rd_data_reg[168]\ => \not_strict_mode.app_rd_data_reg[168]\,
      \not_strict_mode.app_rd_data_reg[169]\ => \not_strict_mode.app_rd_data_reg[169]\,
      \not_strict_mode.app_rd_data_reg[170]\ => \not_strict_mode.app_rd_data_reg[170]\,
      \not_strict_mode.app_rd_data_reg[171]\ => \not_strict_mode.app_rd_data_reg[171]\,
      \not_strict_mode.app_rd_data_reg[172]\ => \not_strict_mode.app_rd_data_reg[172]\,
      \not_strict_mode.app_rd_data_reg[173]\ => \not_strict_mode.app_rd_data_reg[173]\,
      \not_strict_mode.app_rd_data_reg[174]\ => \not_strict_mode.app_rd_data_reg[174]\,
      \not_strict_mode.app_rd_data_reg[175]\ => \not_strict_mode.app_rd_data_reg[175]\,
      \not_strict_mode.app_rd_data_reg[176]\ => \not_strict_mode.app_rd_data_reg[176]\,
      \not_strict_mode.app_rd_data_reg[177]\ => \not_strict_mode.app_rd_data_reg[177]\,
      \not_strict_mode.app_rd_data_reg[178]\ => \not_strict_mode.app_rd_data_reg[178]\,
      \not_strict_mode.app_rd_data_reg[179]\ => \not_strict_mode.app_rd_data_reg[179]\,
      \not_strict_mode.app_rd_data_reg[180]\ => \not_strict_mode.app_rd_data_reg[180]\,
      \not_strict_mode.app_rd_data_reg[181]\ => \not_strict_mode.app_rd_data_reg[181]\,
      \not_strict_mode.app_rd_data_reg[182]\ => \not_strict_mode.app_rd_data_reg[182]\,
      \not_strict_mode.app_rd_data_reg[183]\ => \not_strict_mode.app_rd_data_reg[183]\,
      \not_strict_mode.app_rd_data_reg[184]\ => \^not_strict_mode.app_rd_data_reg[184]\,
      \not_strict_mode.app_rd_data_reg[185]\ => \^not_strict_mode.app_rd_data_reg[185]\,
      \not_strict_mode.app_rd_data_reg[186]\ => \^not_strict_mode.app_rd_data_reg[186]\,
      \not_strict_mode.app_rd_data_reg[187]\ => \^not_strict_mode.app_rd_data_reg[187]\,
      \not_strict_mode.app_rd_data_reg[188]\ => \^not_strict_mode.app_rd_data_reg[188]\,
      \not_strict_mode.app_rd_data_reg[189]\ => \^not_strict_mode.app_rd_data_reg[189]\,
      \not_strict_mode.app_rd_data_reg[190]\ => \^not_strict_mode.app_rd_data_reg[190]\,
      \not_strict_mode.app_rd_data_reg[191]\ => \^not_strict_mode.app_rd_data_reg[191]\,
      \not_strict_mode.app_rd_data_reg[232]\ => \not_strict_mode.app_rd_data_reg[232]\,
      \not_strict_mode.app_rd_data_reg[233]\ => \not_strict_mode.app_rd_data_reg[233]\,
      \not_strict_mode.app_rd_data_reg[234]\ => \not_strict_mode.app_rd_data_reg[234]\,
      \not_strict_mode.app_rd_data_reg[235]\ => \not_strict_mode.app_rd_data_reg[235]\,
      \not_strict_mode.app_rd_data_reg[236]\ => \not_strict_mode.app_rd_data_reg[236]\,
      \not_strict_mode.app_rd_data_reg[237]\ => \not_strict_mode.app_rd_data_reg[237]\,
      \not_strict_mode.app_rd_data_reg[238]\ => \not_strict_mode.app_rd_data_reg[238]\,
      \not_strict_mode.app_rd_data_reg[239]\ => \not_strict_mode.app_rd_data_reg[239]\,
      \not_strict_mode.app_rd_data_reg[240]\ => \not_strict_mode.app_rd_data_reg[240]\,
      \not_strict_mode.app_rd_data_reg[241]\ => \not_strict_mode.app_rd_data_reg[241]\,
      \not_strict_mode.app_rd_data_reg[242]\ => \not_strict_mode.app_rd_data_reg[242]\,
      \not_strict_mode.app_rd_data_reg[243]\ => \not_strict_mode.app_rd_data_reg[243]\,
      \not_strict_mode.app_rd_data_reg[244]\ => \not_strict_mode.app_rd_data_reg[244]\,
      \not_strict_mode.app_rd_data_reg[245]\ => \not_strict_mode.app_rd_data_reg[245]\,
      \not_strict_mode.app_rd_data_reg[246]\ => \not_strict_mode.app_rd_data_reg[246]\,
      \not_strict_mode.app_rd_data_reg[247]\ => \not_strict_mode.app_rd_data_reg[247]\,
      \not_strict_mode.app_rd_data_reg[248]\ => \^not_strict_mode.app_rd_data_reg[248]\,
      \not_strict_mode.app_rd_data_reg[249]\ => \^not_strict_mode.app_rd_data_reg[249]\,
      \not_strict_mode.app_rd_data_reg[250]\ => \^not_strict_mode.app_rd_data_reg[250]\,
      \not_strict_mode.app_rd_data_reg[251]\ => \^not_strict_mode.app_rd_data_reg[251]\,
      \not_strict_mode.app_rd_data_reg[252]\ => \^not_strict_mode.app_rd_data_reg[252]\,
      \not_strict_mode.app_rd_data_reg[253]\ => \^not_strict_mode.app_rd_data_reg[253]\,
      \not_strict_mode.app_rd_data_reg[254]\ => \^not_strict_mode.app_rd_data_reg[254]\,
      \not_strict_mode.app_rd_data_reg[255]\ => \^not_strict_mode.app_rd_data_reg[255]\,
      \not_strict_mode.app_rd_data_reg[296]\ => \not_strict_mode.app_rd_data_reg[296]\,
      \not_strict_mode.app_rd_data_reg[297]\ => \not_strict_mode.app_rd_data_reg[297]\,
      \not_strict_mode.app_rd_data_reg[298]\ => \not_strict_mode.app_rd_data_reg[298]\,
      \not_strict_mode.app_rd_data_reg[299]\ => \not_strict_mode.app_rd_data_reg[299]\,
      \not_strict_mode.app_rd_data_reg[300]\ => \not_strict_mode.app_rd_data_reg[300]\,
      \not_strict_mode.app_rd_data_reg[301]\ => \not_strict_mode.app_rd_data_reg[301]\,
      \not_strict_mode.app_rd_data_reg[302]\ => \not_strict_mode.app_rd_data_reg[302]\,
      \not_strict_mode.app_rd_data_reg[303]\ => \not_strict_mode.app_rd_data_reg[303]\,
      \not_strict_mode.app_rd_data_reg[304]\ => \not_strict_mode.app_rd_data_reg[304]\,
      \not_strict_mode.app_rd_data_reg[305]\ => \not_strict_mode.app_rd_data_reg[305]\,
      \not_strict_mode.app_rd_data_reg[306]\ => \not_strict_mode.app_rd_data_reg[306]\,
      \not_strict_mode.app_rd_data_reg[307]\ => \not_strict_mode.app_rd_data_reg[307]\,
      \not_strict_mode.app_rd_data_reg[308]\ => \not_strict_mode.app_rd_data_reg[308]\,
      \not_strict_mode.app_rd_data_reg[309]\ => \not_strict_mode.app_rd_data_reg[309]\,
      \not_strict_mode.app_rd_data_reg[310]\ => \not_strict_mode.app_rd_data_reg[310]\,
      \not_strict_mode.app_rd_data_reg[311]\ => \not_strict_mode.app_rd_data_reg[311]\,
      \not_strict_mode.app_rd_data_reg[312]\ => \^not_strict_mode.app_rd_data_reg[312]\,
      \not_strict_mode.app_rd_data_reg[313]\ => \^not_strict_mode.app_rd_data_reg[313]\,
      \not_strict_mode.app_rd_data_reg[314]\ => \^not_strict_mode.app_rd_data_reg[314]\,
      \not_strict_mode.app_rd_data_reg[315]\ => \^not_strict_mode.app_rd_data_reg[315]\,
      \not_strict_mode.app_rd_data_reg[316]\ => \^not_strict_mode.app_rd_data_reg[316]\,
      \not_strict_mode.app_rd_data_reg[317]\ => \^not_strict_mode.app_rd_data_reg[317]\,
      \not_strict_mode.app_rd_data_reg[318]\ => \^not_strict_mode.app_rd_data_reg[318]\,
      \not_strict_mode.app_rd_data_reg[319]\ => \^not_strict_mode.app_rd_data_reg[319]\,
      \not_strict_mode.app_rd_data_reg[360]\ => \not_strict_mode.app_rd_data_reg[360]\,
      \not_strict_mode.app_rd_data_reg[361]\ => \not_strict_mode.app_rd_data_reg[361]\,
      \not_strict_mode.app_rd_data_reg[362]\ => \not_strict_mode.app_rd_data_reg[362]\,
      \not_strict_mode.app_rd_data_reg[363]\ => \not_strict_mode.app_rd_data_reg[363]\,
      \not_strict_mode.app_rd_data_reg[364]\ => \not_strict_mode.app_rd_data_reg[364]\,
      \not_strict_mode.app_rd_data_reg[365]\ => \not_strict_mode.app_rd_data_reg[365]\,
      \not_strict_mode.app_rd_data_reg[366]\ => \not_strict_mode.app_rd_data_reg[366]\,
      \not_strict_mode.app_rd_data_reg[367]\ => \not_strict_mode.app_rd_data_reg[367]\,
      \not_strict_mode.app_rd_data_reg[368]\ => \not_strict_mode.app_rd_data_reg[368]\,
      \not_strict_mode.app_rd_data_reg[369]\ => \not_strict_mode.app_rd_data_reg[369]\,
      \not_strict_mode.app_rd_data_reg[370]\ => \not_strict_mode.app_rd_data_reg[370]\,
      \not_strict_mode.app_rd_data_reg[371]\ => \not_strict_mode.app_rd_data_reg[371]\,
      \not_strict_mode.app_rd_data_reg[372]\ => \not_strict_mode.app_rd_data_reg[372]\,
      \not_strict_mode.app_rd_data_reg[373]\ => \not_strict_mode.app_rd_data_reg[373]\,
      \not_strict_mode.app_rd_data_reg[374]\ => \not_strict_mode.app_rd_data_reg[374]\,
      \not_strict_mode.app_rd_data_reg[375]\ => \not_strict_mode.app_rd_data_reg[375]\,
      \not_strict_mode.app_rd_data_reg[376]\ => \^not_strict_mode.app_rd_data_reg[376]\,
      \not_strict_mode.app_rd_data_reg[377]\ => \^not_strict_mode.app_rd_data_reg[377]\,
      \not_strict_mode.app_rd_data_reg[378]\ => \^not_strict_mode.app_rd_data_reg[378]\,
      \not_strict_mode.app_rd_data_reg[379]\ => \^not_strict_mode.app_rd_data_reg[379]\,
      \not_strict_mode.app_rd_data_reg[380]\ => \^not_strict_mode.app_rd_data_reg[380]\,
      \not_strict_mode.app_rd_data_reg[381]\ => \^not_strict_mode.app_rd_data_reg[381]\,
      \not_strict_mode.app_rd_data_reg[382]\ => \^not_strict_mode.app_rd_data_reg[382]\,
      \not_strict_mode.app_rd_data_reg[383]\ => \^not_strict_mode.app_rd_data_reg[383]\,
      \not_strict_mode.app_rd_data_reg[40]\ => \not_strict_mode.app_rd_data_reg[40]\,
      \not_strict_mode.app_rd_data_reg[41]\ => \not_strict_mode.app_rd_data_reg[41]\,
      \not_strict_mode.app_rd_data_reg[424]\ => \not_strict_mode.app_rd_data_reg[424]\,
      \not_strict_mode.app_rd_data_reg[425]\ => \not_strict_mode.app_rd_data_reg[425]\,
      \not_strict_mode.app_rd_data_reg[426]\ => \not_strict_mode.app_rd_data_reg[426]\,
      \not_strict_mode.app_rd_data_reg[427]\ => \not_strict_mode.app_rd_data_reg[427]\,
      \not_strict_mode.app_rd_data_reg[428]\ => \not_strict_mode.app_rd_data_reg[428]\,
      \not_strict_mode.app_rd_data_reg[429]\ => \not_strict_mode.app_rd_data_reg[429]\,
      \not_strict_mode.app_rd_data_reg[42]\ => \not_strict_mode.app_rd_data_reg[42]\,
      \not_strict_mode.app_rd_data_reg[430]\ => \not_strict_mode.app_rd_data_reg[430]\,
      \not_strict_mode.app_rd_data_reg[431]\ => \not_strict_mode.app_rd_data_reg[431]\,
      \not_strict_mode.app_rd_data_reg[432]\ => \not_strict_mode.app_rd_data_reg[432]\,
      \not_strict_mode.app_rd_data_reg[433]\ => \not_strict_mode.app_rd_data_reg[433]\,
      \not_strict_mode.app_rd_data_reg[434]\ => \not_strict_mode.app_rd_data_reg[434]\,
      \not_strict_mode.app_rd_data_reg[435]\ => \not_strict_mode.app_rd_data_reg[435]\,
      \not_strict_mode.app_rd_data_reg[436]\ => \not_strict_mode.app_rd_data_reg[436]\,
      \not_strict_mode.app_rd_data_reg[437]\ => \not_strict_mode.app_rd_data_reg[437]\,
      \not_strict_mode.app_rd_data_reg[438]\ => \not_strict_mode.app_rd_data_reg[438]\,
      \not_strict_mode.app_rd_data_reg[439]\ => \not_strict_mode.app_rd_data_reg[439]\,
      \not_strict_mode.app_rd_data_reg[43]\ => \not_strict_mode.app_rd_data_reg[43]\,
      \not_strict_mode.app_rd_data_reg[440]\ => \^not_strict_mode.app_rd_data_reg[440]\,
      \not_strict_mode.app_rd_data_reg[441]\ => \^not_strict_mode.app_rd_data_reg[441]\,
      \not_strict_mode.app_rd_data_reg[442]\ => \^not_strict_mode.app_rd_data_reg[442]\,
      \not_strict_mode.app_rd_data_reg[443]\ => \^not_strict_mode.app_rd_data_reg[443]\,
      \not_strict_mode.app_rd_data_reg[444]\ => \^not_strict_mode.app_rd_data_reg[444]\,
      \not_strict_mode.app_rd_data_reg[445]\ => \^not_strict_mode.app_rd_data_reg[445]\,
      \not_strict_mode.app_rd_data_reg[446]\ => \^not_strict_mode.app_rd_data_reg[446]\,
      \not_strict_mode.app_rd_data_reg[447]\ => \^not_strict_mode.app_rd_data_reg[447]\,
      \not_strict_mode.app_rd_data_reg[44]\ => \not_strict_mode.app_rd_data_reg[44]\,
      \not_strict_mode.app_rd_data_reg[45]\ => \not_strict_mode.app_rd_data_reg[45]\,
      \not_strict_mode.app_rd_data_reg[46]\ => \not_strict_mode.app_rd_data_reg[46]\,
      \not_strict_mode.app_rd_data_reg[47]\ => \not_strict_mode.app_rd_data_reg[47]\,
      \not_strict_mode.app_rd_data_reg[488]\ => \not_strict_mode.app_rd_data_reg[488]\,
      \not_strict_mode.app_rd_data_reg[489]\ => \not_strict_mode.app_rd_data_reg[489]\,
      \not_strict_mode.app_rd_data_reg[48]\ => \not_strict_mode.app_rd_data_reg[48]\,
      \not_strict_mode.app_rd_data_reg[490]\ => \not_strict_mode.app_rd_data_reg[490]\,
      \not_strict_mode.app_rd_data_reg[491]\ => \not_strict_mode.app_rd_data_reg[491]\,
      \not_strict_mode.app_rd_data_reg[492]\ => \not_strict_mode.app_rd_data_reg[492]\,
      \not_strict_mode.app_rd_data_reg[493]\ => \not_strict_mode.app_rd_data_reg[493]\,
      \not_strict_mode.app_rd_data_reg[494]\ => \not_strict_mode.app_rd_data_reg[494]\,
      \not_strict_mode.app_rd_data_reg[495]\ => \not_strict_mode.app_rd_data_reg[495]\,
      \not_strict_mode.app_rd_data_reg[496]\ => \not_strict_mode.app_rd_data_reg[496]\,
      \not_strict_mode.app_rd_data_reg[497]\ => \not_strict_mode.app_rd_data_reg[497]\,
      \not_strict_mode.app_rd_data_reg[498]\ => \not_strict_mode.app_rd_data_reg[498]\,
      \not_strict_mode.app_rd_data_reg[499]\ => \not_strict_mode.app_rd_data_reg[499]\,
      \not_strict_mode.app_rd_data_reg[49]\ => \not_strict_mode.app_rd_data_reg[49]\,
      \not_strict_mode.app_rd_data_reg[500]\ => \not_strict_mode.app_rd_data_reg[500]\,
      \not_strict_mode.app_rd_data_reg[501]\ => \not_strict_mode.app_rd_data_reg[501]\,
      \not_strict_mode.app_rd_data_reg[502]\ => \not_strict_mode.app_rd_data_reg[502]\,
      \not_strict_mode.app_rd_data_reg[503]\ => \not_strict_mode.app_rd_data_reg[503]\,
      \not_strict_mode.app_rd_data_reg[504]\ => \^not_strict_mode.app_rd_data_reg[504]\,
      \not_strict_mode.app_rd_data_reg[505]\ => \^not_strict_mode.app_rd_data_reg[505]\,
      \not_strict_mode.app_rd_data_reg[506]\ => \^not_strict_mode.app_rd_data_reg[506]\,
      \not_strict_mode.app_rd_data_reg[507]\ => \^not_strict_mode.app_rd_data_reg[507]\,
      \not_strict_mode.app_rd_data_reg[508]\ => \^not_strict_mode.app_rd_data_reg[508]\,
      \not_strict_mode.app_rd_data_reg[509]\ => \^not_strict_mode.app_rd_data_reg[509]\,
      \not_strict_mode.app_rd_data_reg[50]\ => \not_strict_mode.app_rd_data_reg[50]\,
      \not_strict_mode.app_rd_data_reg[510]\ => \^not_strict_mode.app_rd_data_reg[510]\,
      \not_strict_mode.app_rd_data_reg[511]\(191 downto 168) => \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 488),
      \not_strict_mode.app_rd_data_reg[511]\(167 downto 144) => \not_strict_mode.app_rd_data_reg[511]_0\(447 downto 424),
      \not_strict_mode.app_rd_data_reg[511]\(143 downto 120) => \not_strict_mode.app_rd_data_reg[511]_0\(383 downto 360),
      \not_strict_mode.app_rd_data_reg[511]\(119 downto 96) => \not_strict_mode.app_rd_data_reg[511]_0\(319 downto 296),
      \not_strict_mode.app_rd_data_reg[511]\(95 downto 72) => \not_strict_mode.app_rd_data_reg[511]_0\(255 downto 232),
      \not_strict_mode.app_rd_data_reg[511]\(71 downto 48) => \not_strict_mode.app_rd_data_reg[511]_0\(191 downto 168),
      \not_strict_mode.app_rd_data_reg[511]\(47 downto 24) => \not_strict_mode.app_rd_data_reg[511]_0\(127 downto 104),
      \not_strict_mode.app_rd_data_reg[511]\(23 downto 0) => \not_strict_mode.app_rd_data_reg[511]_0\(63 downto 40),
      \not_strict_mode.app_rd_data_reg[511]_0\ => \^not_strict_mode.app_rd_data_reg[511]\,
      \not_strict_mode.app_rd_data_reg[51]\ => \not_strict_mode.app_rd_data_reg[51]\,
      \not_strict_mode.app_rd_data_reg[52]\ => \not_strict_mode.app_rd_data_reg[52]\,
      \not_strict_mode.app_rd_data_reg[53]\ => \not_strict_mode.app_rd_data_reg[53]\,
      \not_strict_mode.app_rd_data_reg[54]\ => \not_strict_mode.app_rd_data_reg[54]\,
      \not_strict_mode.app_rd_data_reg[55]\ => \not_strict_mode.app_rd_data_reg[55]\,
      \not_strict_mode.app_rd_data_reg[56]\ => \^not_strict_mode.app_rd_data_reg[56]\,
      \not_strict_mode.app_rd_data_reg[57]\ => \^not_strict_mode.app_rd_data_reg[57]\,
      \not_strict_mode.app_rd_data_reg[58]\ => \^not_strict_mode.app_rd_data_reg[58]\,
      \not_strict_mode.app_rd_data_reg[59]\ => \^not_strict_mode.app_rd_data_reg[59]\,
      \not_strict_mode.app_rd_data_reg[60]\ => \^not_strict_mode.app_rd_data_reg[60]\,
      \not_strict_mode.app_rd_data_reg[61]\ => \^not_strict_mode.app_rd_data_reg[61]\,
      \not_strict_mode.app_rd_data_reg[62]\ => \^not_strict_mode.app_rd_data_reg[62]\,
      \not_strict_mode.app_rd_data_reg[63]\ => \^not_strict_mode.app_rd_data_reg[63]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1 downto 0),
      ofifo_rst_reg0_11 => ofifo_rst_reg0_11,
      ofifo_rst_reg0_13 => ofifo_rst_reg0_13,
      ofifo_rst_reg0_15 => ofifo_rst_reg0_15,
      out_dqs_5 => out_dqs_5,
      out_dqs_6 => out_dqs_6,
      out_dqs_7 => out_dqs_7,
      phy_ctl_mstr_empty => phy_ctl_mstr_empty,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_data_wr_en => phy_data_wr_en,
      phy_if_reset => phy_if_reset,
      phy_mc_data_full => phy_mc_data_full,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_dqs_found_lanes(2 downto 0) => pi_dqs_found_lanes(7 downto 5),
      \pi_dqs_found_lanes_r1_reg[10]\ => \pi_dqs_found_lanes_r1_reg[10]\,
      pi_phase_locked_all_r1_reg => pi_phase_locked_all_r1_reg,
      \pi_rdval_cnt_reg[5]\(5 downto 0) => \pi_counter_read_val_w[2]_5\(5 downto 0),
      \pi_rst_stg1_cal_reg[2]\ => \pi_rst_stg1_cal_reg[2]\,
      pi_stg2_load_reg => pi_stg2_load_reg_0,
      \pi_stg2_reg_l_reg[5]\(5 downto 0) => \pi_stg2_reg_l_reg[5]_0\(5 downto 0),
      pll_locked => pll_locked,
      \po_stg2_wrcal_cnt_reg[1]\(1 downto 0) => \po_stg2_wrcal_cnt_reg[2]\(1 downto 0),
      pre_data_a_full_v(0) => pre_data_a_full_v(1),
      \rd_mux_sel_r_reg[1]\(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      \rd_mux_sel_r_reg[1]_0\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_99\,
      \rd_mux_sel_r_reg[1]_1\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103\,
      \rd_mux_sel_r_reg[1]_10\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_271\,
      \rd_mux_sel_r_reg[1]_11\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_279\,
      \rd_mux_sel_r_reg[1]_12\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_287\,
      \rd_mux_sel_r_reg[1]_13\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_291\,
      \rd_mux_sel_r_reg[1]_14\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_295\,
      \rd_mux_sel_r_reg[1]_15\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_331\,
      \rd_mux_sel_r_reg[1]_16\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_351\,
      \rd_mux_sel_r_reg[1]_17\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_107\,
      \rd_mux_sel_r_reg[1]_18\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111\,
      \rd_mux_sel_r_reg[1]_19\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_115\,
      \rd_mux_sel_r_reg[1]_2\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_143\,
      \rd_mux_sel_r_reg[1]_20\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_119\,
      \rd_mux_sel_r_reg[1]_21\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_123\,
      \rd_mux_sel_r_reg[1]_22\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_127\,
      \rd_mux_sel_r_reg[1]_23\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_131\,
      \rd_mux_sel_r_reg[1]_24\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_135\,
      \rd_mux_sel_r_reg[1]_25\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_139\,
      \rd_mux_sel_r_reg[1]_26\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_147\,
      \rd_mux_sel_r_reg[1]_27\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_151\,
      \rd_mux_sel_r_reg[1]_28\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_155\,
      \rd_mux_sel_r_reg[1]_29\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_159\,
      \rd_mux_sel_r_reg[1]_3\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_183\,
      \rd_mux_sel_r_reg[1]_30\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_163\,
      \rd_mux_sel_r_reg[1]_31\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_167\,
      \rd_mux_sel_r_reg[1]_32\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_171\,
      \rd_mux_sel_r_reg[1]_33\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_175\,
      \rd_mux_sel_r_reg[1]_34\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_179\,
      \rd_mux_sel_r_reg[1]_35\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_195\,
      \rd_mux_sel_r_reg[1]_36\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_199\,
      \rd_mux_sel_r_reg[1]_37\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_203\,
      \rd_mux_sel_r_reg[1]_38\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_211\,
      \rd_mux_sel_r_reg[1]_39\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_215\,
      \rd_mux_sel_r_reg[1]_4\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_187\,
      \rd_mux_sel_r_reg[1]_40\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_219\,
      \rd_mux_sel_r_reg[1]_41\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_227\,
      \rd_mux_sel_r_reg[1]_42\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_235\,
      \rd_mux_sel_r_reg[1]_43\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_239\,
      \rd_mux_sel_r_reg[1]_44\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_243\,
      \rd_mux_sel_r_reg[1]_45\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_247\,
      \rd_mux_sel_r_reg[1]_46\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_255\,
      \rd_mux_sel_r_reg[1]_47\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_259\,
      \rd_mux_sel_r_reg[1]_48\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_263\,
      \rd_mux_sel_r_reg[1]_49\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_267\,
      \rd_mux_sel_r_reg[1]_5\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_191\,
      \rd_mux_sel_r_reg[1]_50\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_275\,
      \rd_mux_sel_r_reg[1]_51\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_283\,
      \rd_mux_sel_r_reg[1]_52\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_299\,
      \rd_mux_sel_r_reg[1]_53\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_303\,
      \rd_mux_sel_r_reg[1]_54\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_307\,
      \rd_mux_sel_r_reg[1]_55\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_311\,
      \rd_mux_sel_r_reg[1]_56\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_315\,
      \rd_mux_sel_r_reg[1]_57\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_319\,
      \rd_mux_sel_r_reg[1]_58\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_323\,
      \rd_mux_sel_r_reg[1]_59\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_327\,
      \rd_mux_sel_r_reg[1]_6\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_207\,
      \rd_mux_sel_r_reg[1]_60\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_335\,
      \rd_mux_sel_r_reg[1]_61\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_339\,
      \rd_mux_sel_r_reg[1]_62\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_343\,
      \rd_mux_sel_r_reg[1]_63\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_347\,
      \rd_mux_sel_r_reg[1]_7\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_223\,
      \rd_mux_sel_r_reg[1]_8\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_231\,
      \rd_mux_sel_r_reg[1]_9\ => \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_251\,
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_ptr_timing_reg[0]\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_71\,
      \rd_ptr_timing_reg[0]_0\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_72\,
      \rd_ptr_timing_reg[0]_1\ => \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_73\,
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]_0\,
      \ref_dll_lock_w__0\(0) => \ref_dll_lock_w__0\(2),
      sync_pulse => sync_pulse,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg_4,
      tempmon_pi_f_en_r_reg_0 => tempmon_pi_f_en_r_reg_5,
      tempmon_pi_f_en_r_reg_1 => tempmon_pi_f_en_r_reg_6,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg_4,
      tempmon_pi_f_inc_r_reg_0 => tempmon_pi_f_inc_r_reg_5,
      tempmon_pi_f_inc_r_reg_1 => tempmon_pi_f_inc_r_reg_6,
      ts_dqs_5 => ts_dqs_5,
      ts_dqs_6 => ts_dqs_6,
      ts_dqs_7 => ts_dqs_7,
      \write_buffer.wr_buf_out_data_reg[383]\(35 downto 30) => \write_buffer.wr_buf_out_data_reg[383]\(95 downto 90),
      \write_buffer.wr_buf_out_data_reg[383]\(29 downto 24) => \write_buffer.wr_buf_out_data_reg[383]\(79 downto 74),
      \write_buffer.wr_buf_out_data_reg[383]\(23 downto 18) => \write_buffer.wr_buf_out_data_reg[383]\(63 downto 58),
      \write_buffer.wr_buf_out_data_reg[383]\(17 downto 12) => \write_buffer.wr_buf_out_data_reg[383]\(47 downto 42),
      \write_buffer.wr_buf_out_data_reg[383]\(11 downto 0) => \write_buffer.wr_buf_out_data_reg[383]\(31 downto 20),
      \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[489]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[489]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[490]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[490]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[491]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[491]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[493]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[493]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[494]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[494]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[495]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[495]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[497]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[497]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[498]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[498]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[499]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[499]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[501]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[501]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[502]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[502]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[503]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[503]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[505]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[505]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[506]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[506]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[507]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[507]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[509]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[509]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[510]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[510]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[511]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[511]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[575]\(83 downto 81) => \write_buffer.wr_buf_out_data_reg[575]\(223 downto 221),
      \write_buffer.wr_buf_out_data_reg[575]\(80 downto 78) => \write_buffer.wr_buf_out_data_reg[575]\(215 downto 213),
      \write_buffer.wr_buf_out_data_reg[575]\(77 downto 75) => \write_buffer.wr_buf_out_data_reg[575]\(207 downto 205),
      \write_buffer.wr_buf_out_data_reg[575]\(74 downto 72) => \write_buffer.wr_buf_out_data_reg[575]\(199 downto 197),
      \write_buffer.wr_buf_out_data_reg[575]\(71 downto 69) => \write_buffer.wr_buf_out_data_reg[575]\(191 downto 189),
      \write_buffer.wr_buf_out_data_reg[575]\(68 downto 66) => \write_buffer.wr_buf_out_data_reg[575]\(183 downto 181),
      \write_buffer.wr_buf_out_data_reg[575]\(65 downto 63) => \write_buffer.wr_buf_out_data_reg[575]\(175 downto 173),
      \write_buffer.wr_buf_out_data_reg[575]\(62 downto 60) => \write_buffer.wr_buf_out_data_reg[575]\(167 downto 165),
      \write_buffer.wr_buf_out_data_reg[575]\(59 downto 54) => \write_buffer.wr_buf_out_data_reg[575]\(159 downto 154),
      \write_buffer.wr_buf_out_data_reg[575]\(53 downto 48) => \write_buffer.wr_buf_out_data_reg[575]\(143 downto 138),
      \write_buffer.wr_buf_out_data_reg[575]\(47 downto 36) => \write_buffer.wr_buf_out_data_reg[575]\(127 downto 116),
      \write_buffer.wr_buf_out_data_reg[575]\(35 downto 30) => \write_buffer.wr_buf_out_data_reg[575]\(95 downto 90),
      \write_buffer.wr_buf_out_data_reg[575]\(29 downto 24) => \write_buffer.wr_buf_out_data_reg[575]\(79 downto 74),
      \write_buffer.wr_buf_out_data_reg[575]\(23 downto 12) => \write_buffer.wr_buf_out_data_reg[575]\(63 downto 52),
      \write_buffer.wr_buf_out_data_reg[575]\(11 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(31 downto 20)
    );
\mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => CLK,
      D => mcGo_r1,
      Q => \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0\
    );
\mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \mcGo_r_reg[13]_srl14___u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0\,
      Q => \mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0\,
      R => '0'
    );
\mcGo_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_gate_n_0,
      Q => \^phy_mc_go\,
      R => in0
    );
mcGo_r_reg_gate: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \mcGo_r_reg[14]_u_mig_7series_0_mig_u_memc_ui_top_std_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0\,
      I1 => mcGo_r_reg_r_13_n_0,
      O => mcGo_r_reg_gate_n_0
    );
mcGo_r_reg_r: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '1',
      Q => mcGo_r_reg_r_n_0,
      R => in0
    );
mcGo_r_reg_r_0: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_n_0,
      Q => mcGo_r_reg_r_0_n_0,
      R => in0
    );
mcGo_r_reg_r_1: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_0_n_0,
      Q => mcGo_r_reg_r_1_n_0,
      R => in0
    );
mcGo_r_reg_r_10: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_9_n_0,
      Q => mcGo_r_reg_r_10_n_0,
      R => in0
    );
mcGo_r_reg_r_11: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_10_n_0,
      Q => mcGo_r_reg_r_11_n_0,
      R => in0
    );
mcGo_r_reg_r_12: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_11_n_0,
      Q => mcGo_r_reg_r_12_n_0,
      R => in0
    );
mcGo_r_reg_r_13: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_12_n_0,
      Q => mcGo_r_reg_r_13_n_0,
      R => in0
    );
mcGo_r_reg_r_2: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_1_n_0,
      Q => mcGo_r_reg_r_2_n_0,
      R => in0
    );
mcGo_r_reg_r_3: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_2_n_0,
      Q => mcGo_r_reg_r_3_n_0,
      R => in0
    );
mcGo_r_reg_r_4: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_3_n_0,
      Q => mcGo_r_reg_r_4_n_0,
      R => in0
    );
mcGo_r_reg_r_5: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_4_n_0,
      Q => mcGo_r_reg_r_5_n_0,
      R => in0
    );
mcGo_r_reg_r_6: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_5_n_0,
      Q => mcGo_r_reg_r_6_n_0,
      R => in0
    );
mcGo_r_reg_r_7: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_6_n_0,
      Q => mcGo_r_reg_r_7_n_0,
      R => in0
    );
mcGo_r_reg_r_8: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_7_n_0,
      Q => mcGo_r_reg_r_8_n_0,
      R => in0
    );
mcGo_r_reg_r_9: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mcGo_r_reg_r_8_n_0,
      Q => mcGo_r_reg_r_9_n_0,
      R => in0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_mc_phy_wrapper is
  port (
    A_rst_primitives : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 7 downto 0 );
    COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 );
    idelay_ld_rst : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    idelay_ld_rst_0 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    idelay_ld_rst_1 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    idelay_ld_rst_2 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    idelay_ld_rst_3 : out STD_LOGIC;
    A_rst_primitives_4 : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ : out STD_LOGIC;
    idelay_ld_rst_5 : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_mc_go : out STD_LOGIC;
    mem_out : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \my_empty_reg[1]\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    \my_empty_reg[1]_0\ : out STD_LOGIC;
    \my_empty_reg[1]_1\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    \my_empty_reg[1]_2\ : out STD_LOGIC;
    \my_empty_reg[1]_3\ : out STD_LOGIC;
    \my_empty_reg[1]_4\ : out STD_LOGIC;
    \my_empty_reg[1]_5\ : out STD_LOGIC;
    \my_empty_reg[1]_6\ : out STD_LOGIC;
    \my_empty_reg[1]_7\ : out STD_LOGIC;
    \my_empty_reg[1]_8\ : out STD_LOGIC;
    \not_strict_mode.rd_buf_we\ : out STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : out STD_LOGIC;
    rst_sync_r1_reg : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[8]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[16]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[56]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[48]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[24]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[32]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[42]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[50]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[26]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[34]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[10]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[18]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[58]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[44]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[52]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[28]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[36]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[12]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[20]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[60]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[46]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[54]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[30]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[38]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[14]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[22]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[62]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[104]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[112]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[88]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[96]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[72]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[80]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[120]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[64]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[106]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[114]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[90]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[98]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[74]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[82]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[122]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[66]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[108]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[116]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[92]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[100]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[76]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[84]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[124]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[68]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[110]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[118]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[94]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[102]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[78]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[86]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[126]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[70]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[168]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[176]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[152]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[160]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[136]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[144]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[184]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[128]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[170]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[178]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[154]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[162]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[138]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[146]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[186]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[130]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[172]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[180]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[156]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[164]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[140]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[148]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[188]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[132]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[142]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[150]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[190]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[134]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[174]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[182]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[158]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[166]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[232]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[240]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[216]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[224]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[200]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[208]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[248]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[192]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[234]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[242]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[218]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[226]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[202]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[210]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[250]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[194]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[236]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[244]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[220]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[228]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[204]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[212]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[252]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[196]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[238]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[246]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[222]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[230]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[206]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[214]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[254]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[198]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[296]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[304]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[280]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[288]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[264]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[272]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[312]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[256]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[298]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[306]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[282]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[290]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[266]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[274]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[314]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[258]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[300]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[308]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[284]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[292]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[268]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[276]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[316]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[260]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[270]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[278]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[318]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[262]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[302]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[310]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[286]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[294]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[360]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[368]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[344]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[352]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[328]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[336]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[376]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[320]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[362]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[370]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[346]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[354]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[330]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[338]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[378]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[322]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[364]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[372]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[348]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[356]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[332]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[340]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[380]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[324]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[366]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[374]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[350]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[358]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[334]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[342]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[382]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[326]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[392]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[400]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[440]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[384]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[424]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[432]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[408]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[416]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[426]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[434]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[410]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[418]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[394]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[402]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[442]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[386]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[428]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[436]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[412]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[420]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[396]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[404]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[444]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[388]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[430]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[438]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[414]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[422]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[398]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[406]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[446]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[390]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[488]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[496]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[472]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[480]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[456]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[464]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[504]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[448]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[458]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[466]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[506]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[450]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[490]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[498]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[474]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[482]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[492]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[500]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[476]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[484]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[460]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[468]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[508]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[452]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[494]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[502]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[478]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[486]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[462]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[470]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[510]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[454]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC;
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \my_empty_reg[1]_9\ : out STD_LOGIC;
    phy_rddata_en : out STD_LOGIC;
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    p_110_in : out STD_LOGIC;
    store_sr_req_r_reg : out STD_LOGIC;
    \pi_rdval_cnt_reg[2]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[3]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[1]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[0]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[5]\ : out STD_LOGIC;
    \pi_rdval_cnt_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC_VECTOR ( 511 downto 0 );
    pi_phase_locked_all_r1_reg : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_0\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_1\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_2\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_3\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_4\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_5\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    \my_empty_reg[7]_6\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    \po_rdval_cnt_reg[0]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[1]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[2]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[3]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[4]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[5]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[6]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[7]\ : out STD_LOGIC;
    \po_rdval_cnt_reg[8]\ : out STD_LOGIC;
    p_0_out : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ : out STD_LOGIC;
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : out STD_LOGIC;
    phy_mc_data_full : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    CLK : in STD_LOGIC;
    \calib_sel_reg[1]\ : in STD_LOGIC;
    idelay_inc : in STD_LOGIC;
    LD0 : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    \calib_sel_reg[1]_0\ : in STD_LOGIC;
    \calib_sel_reg[1]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    \calib_sel_reg[1]_2\ : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_3\ : in STD_LOGIC;
    \calib_sel_reg[1]_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[487]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[486]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[485]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[420]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[483]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[482]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[481]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[416]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ififo_rst_reg0 : in STD_LOGIC;
    ofifo_rst_reg0 : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_0\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_1\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_0 : in STD_LOGIC;
    D1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_byte_sel_div2.calib_in_common_reg_2\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_3\ : in STD_LOGIC;
    \gen_byte_sel_div2.calib_in_common_reg_4\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_1 : in STD_LOGIC;
    D0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_calib_complete_reg_rep__10\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \init_calib_complete_reg_rep__11_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    D7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D8 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D9 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pll_locked : in STD_LOGIC;
    phy_read_calib : in STD_LOGIC;
    in0 : in STD_LOGIC;
    phy_write_calib : in STD_LOGIC;
    RST0 : in STD_LOGIC;
    \calib_sel_reg[1]_5\ : in STD_LOGIC;
    LD0_6 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    \calib_sel_reg[1]_6\ : in STD_LOGIC;
    \calib_sel_reg[1]_7\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_0 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_0 : in STD_LOGIC;
    \calib_sel_reg[1]_8\ : in STD_LOGIC;
    \calib_sel_reg[1]_9\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_10\ : in STD_LOGIC;
    \calib_sel_reg[1]_11\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_2 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[479]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[478]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[477]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[412]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[475]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[474]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[473]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[408]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_if_reset : in STD_LOGIC;
    \calib_sel_reg[1]_12\ : in STD_LOGIC;
    LD0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    \calib_sel_reg[1]_13\ : in STD_LOGIC;
    \calib_sel_reg[0]\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_1 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_1 : in STD_LOGIC;
    \calib_sel_reg[1]_14\ : in STD_LOGIC;
    \calib_sel_reg[1]_15\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_16\ : in STD_LOGIC;
    \calib_sel_reg[1]_17\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_3 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[471]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[470]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[469]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[404]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[467]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[466]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[465]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[400]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_18\ : in STD_LOGIC;
    LD0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    \calib_sel_reg[1]_19\ : in STD_LOGIC;
    \calib_sel_reg[1]_20\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_2 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_2 : in STD_LOGIC;
    \calib_sel_reg[1]_21\ : in STD_LOGIC;
    \calib_sel_reg[1]_22\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_23\ : in STD_LOGIC;
    \calib_sel_reg[1]_24\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_4 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[463]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[462]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[461]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[396]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[459]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[458]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[457]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[392]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    idelay_ce_r2_reg : in STD_LOGIC;
    LD0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    pi_stg2_load_reg : in STD_LOGIC;
    \calib_sel_reg[1]_25\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_3 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_3 : in STD_LOGIC;
    \pi_rst_stg1_cal_reg[0]\ : in STD_LOGIC;
    \pi_stg2_reg_l_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg : in STD_LOGIC;
    \calib_sel_reg[0]_0\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_5 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[455]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[454]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[453]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[388]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[451]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[450]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[449]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[384]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \calib_sel_reg[1]_26\ : in STD_LOGIC;
    LD0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    \calib_sel_reg[1]_27\ : in STD_LOGIC;
    \calib_sel_reg[1]_28\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_4 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_4 : in STD_LOGIC;
    \calib_sel_reg[1]_29\ : in STD_LOGIC;
    \calib_sel_reg[1]_30\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_31\ : in STD_LOGIC;
    \calib_sel_reg[1]_32\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_6 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[511]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[510]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[509]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[444]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[507]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[506]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[505]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[440]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_11 : in STD_LOGIC;
    idelay_ce_r2_reg_0 : in STD_LOGIC;
    LD0_12 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    pi_stg2_load_reg_0 : in STD_LOGIC;
    \calib_sel_reg[0]_1\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_5 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_5 : in STD_LOGIC;
    \pi_rst_stg1_cal_reg[2]\ : in STD_LOGIC;
    \pi_stg2_reg_l_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dqs_wl_po_stg2_c_incdec_reg_0 : in STD_LOGIC;
    \calib_sel_reg[0]_2\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_7 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[503]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[502]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[501]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[436]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[499]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[498]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[497]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[432]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_13 : in STD_LOGIC;
    \calib_sel_reg[1]_33\ : in STD_LOGIC;
    LD0_14 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \calib_sel_reg[1]_34\ : in STD_LOGIC;
    \calib_sel_reg[1]_35\ : in STD_LOGIC;
    tempmon_pi_f_en_r_reg_6 : in STD_LOGIC;
    tempmon_pi_f_inc_r_reg_6 : in STD_LOGIC;
    \calib_sel_reg[1]_36\ : in STD_LOGIC;
    \calib_sel_reg[1]_37\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[1]_38\ : in STD_LOGIC;
    \calib_sel_reg[1]_39\ : in STD_LOGIC;
    ck_po_stg2_f_indec_reg_8 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[495]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[494]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[493]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[428]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[491]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[490]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \write_buffer.wr_buf_out_data_reg[489]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \write_buffer.wr_buf_out_data_reg[424]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ofifo_rst_reg0_15 : in STD_LOGIC;
    mux_reset_n : in STD_LOGIC;
    idle : in STD_LOGIC;
    phy_cmd_wr_en : in STD_LOGIC;
    phy_data_wr_en : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_init_done_r : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_rst_0 : in STD_LOGIC;
    \rd_mux_sel_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mc_ras_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \init_calib_complete_reg_rep__12_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__11_1\ : in STD_LOGIC;
    mc_address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__10_2\ : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]\ : in STD_LOGIC_VECTOR ( 223 downto 0 );
    \init_calib_complete_reg_rep__9\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__8\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__7\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__6\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__5\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__4\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__3\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__2\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__0\ : in STD_LOGIC;
    init_calib_complete_reg_rep : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    cnt_pwron_cke_done_r : in STD_LOGIC;
    \rd_mux_sel_r_reg[2]\ : in STD_LOGIC;
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    DOC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mux_wrdata : in STD_LOGIC_VECTOR ( 415 downto 0 );
    \write_buffer.wr_buf_out_data_reg[383]\ : in STD_LOGIC_VECTOR ( 95 downto 0 );
    mux_wrdata_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    phy_dout : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \init_calib_complete_reg_rep__25\ : in STD_LOGIC_VECTOR ( 45 downto 0 );
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_seq_reg[1]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \calib_sel_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \po_stg2_wrcal_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    D_po_coarse_enable105_out : in STD_LOGIC;
    D_po_counter_read_en117_out : in STD_LOGIC;
    D_po_fine_enable102_out : in STD_LOGIC;
    D_po_fine_inc108_out : in STD_LOGIC;
    \init_calib_complete_reg_rep__12_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \init_calib_complete_reg_rep__12_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    init_calib_complete_reg : in STD_LOGIC_VECTOR ( 21 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_mc_phy_wrapper : entity is "mig_7series_v2_3_ddr_mc_phy_wrapper";
end mig_7series_0_mig_7series_v2_3_ddr_mc_phy_wrapper;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_mc_phy_wrapper is
  signal data_offset_1_i1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_1_i2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_2_i1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_2_i2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal mem_dq_in : STD_LOGIC_VECTOR ( 108 downto 0 );
  signal mem_dq_out : STD_LOGIC_VECTOR ( 129 downto 0 );
  signal mem_dq_ts : STD_LOGIC_VECTOR ( 129 downto 0 );
  signal mem_dqs_in : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal out_dqs_0 : STD_LOGIC;
  signal out_dqs_1 : STD_LOGIC;
  signal out_dqs_2 : STD_LOGIC;
  signal out_dqs_3 : STD_LOGIC;
  signal out_dqs_4 : STD_LOGIC;
  signal out_dqs_5 : STD_LOGIC;
  signal out_dqs_6 : STD_LOGIC;
  signal out_dqs_7 : STD_LOGIC;
  signal phy_ctl_wd_i1 : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_ctl_wd_i2 : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_ctl_wr_i1 : STD_LOGIC;
  signal phy_ctl_wr_i2 : STD_LOGIC;
  signal ts_dqs_0 : STD_LOGIC;
  signal ts_dqs_1 : STD_LOGIC;
  signal ts_dqs_2 : STD_LOGIC;
  signal ts_dqs_3 : STD_LOGIC;
  signal ts_dqs_4 : STD_LOGIC;
  signal ts_dqs_5 : STD_LOGIC;
  signal ts_dqs_6 : STD_LOGIC;
  signal ts_dqs_7 : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE : string;
  attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[0].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[0].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[10].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[10].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[11].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[11].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[12].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[12].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[13].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[13].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[1].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[1].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[2].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[2].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[3].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[3].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[4].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[4].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[5].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[5].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[6].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[6].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[7].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[7].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[8].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[8].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_addr_obuf[9].u_addr_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_addr_obuf[9].u_addr_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[0].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[0].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[1].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[1].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_bank_obuf[2].u_bank_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_bank_obuf[2].u_bank_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[2].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[2].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[3].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[3].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[4].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[4].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[5].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[5].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[6].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[6].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dm_obuf.loop_dm[7].u_dm_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_dm_obuf.loop_dm[7].u_dm_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[16].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[17].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[18].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[19].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[20].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[21].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[22].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[23].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[24].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[25].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[26].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[27].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[28].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[29].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[30].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[31].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[32].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[33].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[34].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[35].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[36].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[37].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[38].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[39].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[40].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[41].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[42].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[43].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[44].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[45].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[46].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[47].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[48].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[49].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[50].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[51].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[52].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[53].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[54].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[55].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[56].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE";
  attribute BOX_TYPE of \gen_reset_obuf.u_reset_obuf\ : label is "PRIMITIVE";
  attribute CAPACITANCE of \gen_reset_obuf.u_reset_obuf\ : label is "DONT_CARE";
  attribute BOX_TYPE of u_cas_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_cas_n_obuf : label is "DONT_CARE";
  attribute BOX_TYPE of u_ras_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_ras_n_obuf : label is "DONT_CARE";
  attribute BOX_TYPE of u_we_n_obuf : label is "PRIMITIVE";
  attribute CAPACITANCE of u_we_n_obuf : label is "DONT_CARE";
begin
\cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(63),
      O => ddr3_cke(0)
    );
\cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(61),
      O => ddr3_odt(0)
    );
\data_offset_1_i1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(0),
      Q => data_offset_1_i1(0),
      R => '0'
    );
\data_offset_1_i1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(1),
      Q => data_offset_1_i1(1),
      R => '0'
    );
\data_offset_1_i1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(2),
      Q => data_offset_1_i1(2),
      R => '0'
    );
\data_offset_1_i1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(3),
      Q => data_offset_1_i1(3),
      R => '0'
    );
\data_offset_1_i1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(4),
      Q => data_offset_1_i1(4),
      R => '0'
    );
\data_offset_1_i1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5),
      Q => data_offset_1_i1(5),
      R => '0'
    );
\data_offset_1_i2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_1_i1(0),
      Q => data_offset_1_i2(0),
      R => '0'
    );
\data_offset_1_i2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_1_i1(1),
      Q => data_offset_1_i2(1),
      R => '0'
    );
\data_offset_1_i2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_1_i1(2),
      Q => data_offset_1_i2(2),
      R => '0'
    );
\data_offset_1_i2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_1_i1(3),
      Q => data_offset_1_i2(3),
      R => '0'
    );
\data_offset_1_i2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_1_i1(4),
      Q => data_offset_1_i2(4),
      R => '0'
    );
\data_offset_1_i2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_1_i1(5),
      Q => data_offset_1_i2(5),
      R => '0'
    );
\data_offset_2_i1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(0),
      Q => data_offset_2_i1(0),
      R => '0'
    );
\data_offset_2_i1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(1),
      Q => data_offset_2_i1(1),
      R => '0'
    );
\data_offset_2_i1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(2),
      Q => data_offset_2_i1(2),
      R => '0'
    );
\data_offset_2_i1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(3),
      Q => data_offset_2_i1(3),
      R => '0'
    );
\data_offset_2_i1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(4),
      Q => data_offset_2_i1(4),
      R => '0'
    );
\data_offset_2_i1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5),
      Q => data_offset_2_i1(5),
      R => '0'
    );
\data_offset_2_i2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_2_i1(0),
      Q => data_offset_2_i2(0),
      R => '0'
    );
\data_offset_2_i2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_2_i1(1),
      Q => data_offset_2_i2(1),
      R => '0'
    );
\data_offset_2_i2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_2_i1(2),
      Q => data_offset_2_i2(2),
      R => '0'
    );
\data_offset_2_i2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_2_i1(3),
      Q => data_offset_2_i2(3),
      R => '0'
    );
\data_offset_2_i2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_2_i1(4),
      Q => data_offset_2_i2(4),
      R => '0'
    );
\data_offset_2_i2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_offset_2_i1(5),
      Q => data_offset_2_i2(5),
      R => '0'
    );
\gen_addr_obuf[0].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(76),
      O => ddr3_addr(0)
    );
\gen_addr_obuf[10].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(87),
      O => ddr3_addr(10)
    );
\gen_addr_obuf[11].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(88),
      O => ddr3_addr(11)
    );
\gen_addr_obuf[12].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(89),
      O => ddr3_addr(12)
    );
\gen_addr_obuf[13].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(94),
      O => ddr3_addr(13)
    );
\gen_addr_obuf[1].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(77),
      O => ddr3_addr(1)
    );
\gen_addr_obuf[2].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(82),
      O => ddr3_addr(2)
    );
\gen_addr_obuf[3].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(83),
      O => ddr3_addr(3)
    );
\gen_addr_obuf[4].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(78),
      O => ddr3_addr(4)
    );
\gen_addr_obuf[5].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(79),
      O => ddr3_addr(5)
    );
\gen_addr_obuf[6].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(80),
      O => ddr3_addr(6)
    );
\gen_addr_obuf[7].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(81),
      O => ddr3_addr(7)
    );
\gen_addr_obuf[8].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(85),
      O => ddr3_addr(8)
    );
\gen_addr_obuf[9].u_addr_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(86),
      O => ddr3_addr(9)
    );
\gen_bank_obuf[0].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(73),
      O => ddr3_ba(0)
    );
\gen_bank_obuf[1].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(74),
      O => ddr3_ba(1)
    );
\gen_bank_obuf[2].u_bank_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(75),
      O => ddr3_ba(2)
    );
\gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(65),
      O => ddr3_cs_n(0)
    );
\gen_dm_obuf.loop_dm[0].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(45),
      O => ddr3_dm(0),
      T => mem_dq_ts(45)
    );
\gen_dm_obuf.loop_dm[1].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(33),
      O => ddr3_dm(1),
      T => mem_dq_ts(33)
    );
\gen_dm_obuf.loop_dm[2].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(17),
      O => ddr3_dm(2),
      T => mem_dq_ts(17)
    );
\gen_dm_obuf.loop_dm[3].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(9),
      O => ddr3_dm(3),
      T => mem_dq_ts(9)
    );
\gen_dm_obuf.loop_dm[4].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(57),
      O => ddr3_dm(4),
      T => mem_dq_ts(57)
    );
\gen_dm_obuf.loop_dm[5].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(129),
      O => ddr3_dm(5),
      T => mem_dq_ts(129)
    );
\gen_dm_obuf.loop_dm[6].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(113),
      O => ddr3_dm(6),
      T => mem_dq_ts(113)
    );
\gen_dm_obuf.loop_dm[7].u_dm_obuf\: unisim.vcomponents.OBUFT
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(105),
      O => ddr3_dm(7),
      T => mem_dq_ts(105)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(44),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(0),
      O => mem_dq_in(38),
      T => mem_dq_ts(44)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(30),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(10),
      O => mem_dq_in(26),
      T => mem_dq_ts(30)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(29),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(11),
      O => mem_dq_in(25),
      T => mem_dq_ts(29)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(28),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(12),
      O => mem_dq_in(24),
      T => mem_dq_ts(28)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(27),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(13),
      O => mem_dq_in(23),
      T => mem_dq_ts(27)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(26),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(14),
      O => mem_dq_in(22),
      T => mem_dq_ts(26)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(25),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(15),
      O => mem_dq_in(21),
      T => mem_dq_ts(25)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[16].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(21),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(16),
      O => mem_dq_in(19),
      T => mem_dq_ts(21)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[17].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(20),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(17),
      O => mem_dq_in(18),
      T => mem_dq_ts(20)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[18].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(19),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(18),
      O => mem_dq_in(17),
      T => mem_dq_ts(19)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[19].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(18),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(19),
      O => mem_dq_in(16),
      T => mem_dq_ts(18)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(43),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(1),
      O => mem_dq_in(37),
      T => mem_dq_ts(43)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[20].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(16),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(20),
      O => mem_dq_in(14),
      T => mem_dq_ts(16)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[21].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(15),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(21),
      O => mem_dq_in(13),
      T => mem_dq_ts(15)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[22].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(14),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(22),
      O => mem_dq_in(12),
      T => mem_dq_ts(14)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[23].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(13),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(23),
      O => mem_dq_in(11),
      T => mem_dq_ts(13)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[24].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(7),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(24),
      O => mem_dq_in(7),
      T => mem_dq_ts(7)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[25].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(6),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(25),
      O => mem_dq_in(6),
      T => mem_dq_ts(6)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[26].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(5),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(26),
      O => mem_dq_in(5),
      T => mem_dq_ts(5)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[27].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(4),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(27),
      O => mem_dq_in(4),
      T => mem_dq_ts(4)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[28].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(3),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(28),
      O => mem_dq_in(3),
      T => mem_dq_ts(3)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[29].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(2),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(29),
      O => mem_dq_in(2),
      T => mem_dq_ts(2)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(42),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(2),
      O => mem_dq_in(36),
      T => mem_dq_ts(42)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[30].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(1),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(30),
      O => mem_dq_in(1),
      T => mem_dq_ts(1)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[31].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(0),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(31),
      O => mem_dq_in(0),
      T => mem_dq_ts(0)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[32].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(55),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(32),
      O => mem_dq_in(47),
      T => mem_dq_ts(55)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[33].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(54),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(33),
      O => mem_dq_in(46),
      T => mem_dq_ts(54)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[34].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(53),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(34),
      O => mem_dq_in(45),
      T => mem_dq_ts(53)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[35].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(52),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(35),
      O => mem_dq_in(44),
      T => mem_dq_ts(52)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[36].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(51),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(36),
      O => mem_dq_in(43),
      T => mem_dq_ts(51)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[37].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(50),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(37),
      O => mem_dq_in(42),
      T => mem_dq_ts(50)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[38].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(49),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(38),
      O => mem_dq_in(41),
      T => mem_dq_ts(49)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[39].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(48),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(39),
      O => mem_dq_in(40),
      T => mem_dq_ts(48)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(41),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(3),
      O => mem_dq_in(35),
      T => mem_dq_ts(41)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[40].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(128),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(40),
      O => mem_dq_in(108),
      T => mem_dq_ts(128)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[41].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(127),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(41),
      O => mem_dq_in(107),
      T => mem_dq_ts(127)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[42].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(126),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(42),
      O => mem_dq_in(106),
      T => mem_dq_ts(126)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[43].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(125),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(43),
      O => mem_dq_in(105),
      T => mem_dq_ts(125)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[44].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(124),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(44),
      O => mem_dq_in(104),
      T => mem_dq_ts(124)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[45].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(123),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(45),
      O => mem_dq_in(103),
      T => mem_dq_ts(123)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[46].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(122),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(46),
      O => mem_dq_in(102),
      T => mem_dq_ts(122)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[47].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(121),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(47),
      O => mem_dq_in(101),
      T => mem_dq_ts(121)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[48].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(117),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(48),
      O => mem_dq_in(99),
      T => mem_dq_ts(117)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[49].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(116),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(49),
      O => mem_dq_in(98),
      T => mem_dq_ts(116)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(40),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(4),
      O => mem_dq_in(34),
      T => mem_dq_ts(40)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[50].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(115),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(50),
      O => mem_dq_in(97),
      T => mem_dq_ts(115)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[51].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(114),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(51),
      O => mem_dq_in(96),
      T => mem_dq_ts(114)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[52].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(112),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(52),
      O => mem_dq_in(94),
      T => mem_dq_ts(112)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[53].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(111),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(53),
      O => mem_dq_in(93),
      T => mem_dq_ts(111)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[54].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(110),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(54),
      O => mem_dq_in(92),
      T => mem_dq_ts(110)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[55].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(109),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(55),
      O => mem_dq_in(91),
      T => mem_dq_ts(109)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[56].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(103),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(56),
      O => mem_dq_in(87),
      T => mem_dq_ts(103)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(102),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(57),
      O => mem_dq_in(86),
      T => mem_dq_ts(102)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(101),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(58),
      O => mem_dq_in(85),
      T => mem_dq_ts(101)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(100),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(59),
      O => mem_dq_in(84),
      T => mem_dq_ts(100)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(39),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(5),
      O => mem_dq_in(33),
      T => mem_dq_ts(39)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(99),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(60),
      O => mem_dq_in(83),
      T => mem_dq_ts(99)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(98),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(61),
      O => mem_dq_in(82),
      T => mem_dq_ts(98)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(97),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(62),
      O => mem_dq_in(81),
      T => mem_dq_ts(97)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(96),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(63),
      O => mem_dq_in(80),
      T => mem_dq_ts(96)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(38),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(6),
      O => mem_dq_in(32),
      T => mem_dq_ts(38)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(37),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(7),
      O => mem_dq_in(31),
      T => mem_dq_ts(37)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(32),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(8),
      O => mem_dq_in(28),
      T => mem_dq_ts(32)
    );
\gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE
    generic map(
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => mem_dq_out(31),
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dq(9),
      O => mem_dq_in(27),
      T => mem_dq_ts(31)
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_0,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(0),
      IOB => ddr3_dqs_n(0),
      O => mem_dqs_in(3),
      T => ts_dqs_0
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_1,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(1),
      IOB => ddr3_dqs_n(1),
      O => mem_dqs_in(2),
      T => ts_dqs_1
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_2,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(2),
      IOB => ddr3_dqs_n(2),
      O => mem_dqs_in(1),
      T => ts_dqs_2
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_3,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(3),
      IOB => ddr3_dqs_n(3),
      O => mem_dqs_in(0),
      T => ts_dqs_3
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_4,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(4),
      IOB => ddr3_dqs_n(4),
      O => mem_dqs_in(4),
      T => ts_dqs_4
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_5,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(5),
      IOB => ddr3_dqs_n(5),
      O => mem_dqs_in(10),
      T => ts_dqs_5
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_6,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(6),
      IOB => ddr3_dqs_n(6),
      O => mem_dqs_in(9),
      T => ts_dqs_6
    );
\gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE
    generic map(
      DQS_BIAS => "TRUE",
      IOSTANDARD => "DEFAULT",
      SIM_DEVICE => "7SERIES",
      USE_IBUFDISABLE => "TRUE"
    )
        port map (
      I => out_dqs_7,
      IBUFDISABLE => idle,
      INTERMDISABLE => idle,
      IO => ddr3_dqs_p(7),
      IOB => ddr3_dqs_n(7),
      O => mem_dqs_in(8),
      T => ts_dqs_7
    );
\gen_reset_obuf.u_reset_obuf\: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mux_reset_n,
      O => ddr3_reset_n
    );
\genblk24.phy_ctl_pre_fifo_0\: entity work.mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo
     port map (
      CLK => CLK,
      in0 => in0
    );
\genblk24.phy_ctl_pre_fifo_1\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0\
     port map (
      CLK => CLK,
      in0 => in0
    );
\genblk24.phy_ctl_pre_fifo_2\: entity work.\mig_7series_0_mig_7series_v2_3_ddr_of_pre_fifo__parameterized0_5\
     port map (
      CLK => CLK,
      in0 => in0
    );
\phy_ctl_wd_i1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(0),
      Q => phy_ctl_wd_i1(0),
      R => '0'
    );
\phy_ctl_wd_i1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(3),
      Q => phy_ctl_wd_i1(17),
      R => '0'
    );
\phy_ctl_wd_i1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(4),
      Q => phy_ctl_wd_i1(18),
      R => '0'
    );
\phy_ctl_wd_i1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(5),
      Q => phy_ctl_wd_i1(19),
      R => '0'
    );
\phy_ctl_wd_i1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(1),
      Q => phy_ctl_wd_i1(1),
      R => '0'
    );
\phy_ctl_wd_i1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(6),
      Q => phy_ctl_wd_i1(20),
      R => '0'
    );
\phy_ctl_wd_i1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(7),
      Q => phy_ctl_wd_i1(21),
      R => '0'
    );
\phy_ctl_wd_i1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(8),
      Q => phy_ctl_wd_i1(22),
      R => '0'
    );
\phy_ctl_wd_i1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(9),
      Q => phy_ctl_wd_i1(23),
      R => '0'
    );
\phy_ctl_wd_i1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(10),
      Q => phy_ctl_wd_i1(24),
      R => '0'
    );
\phy_ctl_wd_i1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \calib_seq_reg[1]\(2),
      Q => phy_ctl_wd_i1(2),
      R => '0'
    );
\phy_ctl_wd_i2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(0),
      Q => phy_ctl_wd_i2(0),
      R => '0'
    );
\phy_ctl_wd_i2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(17),
      Q => phy_ctl_wd_i2(17),
      R => '0'
    );
\phy_ctl_wd_i2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(18),
      Q => phy_ctl_wd_i2(18),
      R => '0'
    );
\phy_ctl_wd_i2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(19),
      Q => phy_ctl_wd_i2(19),
      R => '0'
    );
\phy_ctl_wd_i2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(1),
      Q => phy_ctl_wd_i2(1),
      R => '0'
    );
\phy_ctl_wd_i2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(20),
      Q => phy_ctl_wd_i2(20),
      R => '0'
    );
\phy_ctl_wd_i2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(21),
      Q => phy_ctl_wd_i2(21),
      R => '0'
    );
\phy_ctl_wd_i2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(22),
      Q => phy_ctl_wd_i2(22),
      R => '0'
    );
\phy_ctl_wd_i2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(23),
      Q => phy_ctl_wd_i2(23),
      R => '0'
    );
\phy_ctl_wd_i2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(24),
      Q => phy_ctl_wd_i2(24),
      R => '0'
    );
\phy_ctl_wd_i2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wd_i1(2),
      Q => phy_ctl_wd_i2(2),
      R => '0'
    );
phy_ctl_wr_i1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_cmd_wr_en,
      Q => phy_ctl_wr_i1,
      R => '0'
    );
phy_ctl_wr_i2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phy_ctl_wr_i1,
      Q => phy_ctl_wr_i2,
      R => '0'
    );
u_cas_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(71),
      O => ddr3_cas_n
    );
u_ddr_mc_phy: entity work.mig_7series_0_mig_7series_v2_3_ddr_mc_phy
     port map (
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0),
      COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0),
      D(5 downto 0) => D(5 downto 0),
      D0(0) => D0(0),
      D1(3 downto 0) => D1(3 downto 0),
      D2(3 downto 0) => D2(3 downto 0),
      D3(3 downto 0) => D3(3 downto 0),
      D4(3 downto 0) => D4(3 downto 0),
      D5(1 downto 0) => D5(1 downto 0),
      D6(0) => D6(0),
      D7(3 downto 0) => D7(3 downto 0),
      D8(3 downto 0) => D8(3 downto 0),
      D9(3 downto 0) => D9(3 downto 0),
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      D_po_coarse_enable105_out => D_po_coarse_enable105_out,
      D_po_counter_read_en117_out => D_po_counter_read_en117_out,
      D_po_fine_enable102_out => D_po_fine_enable102_out,
      D_po_fine_inc108_out => D_po_fine_inc108_out,
      LD0 => LD0,
      LD0_10 => LD0_10,
      LD0_12 => LD0_12,
      LD0_14 => LD0_14,
      LD0_6 => LD0_6,
      LD0_7 => LD0_7,
      LD0_8 => LD0_8,
      LD0_9 => LD0_9,
      Q(10 downto 3) => phy_ctl_wd_i2(24 downto 17),
      Q(2 downto 0) => phy_ctl_wd_i2(2 downto 0),
      RST0 => RST0,
      SR(0) => SR(0),
      \calib_sel_reg[0]\ => \calib_sel_reg[0]\,
      \calib_sel_reg[0]_0\ => \calib_sel_reg[0]_0\,
      \calib_sel_reg[0]_1\ => \calib_sel_reg[0]_1\,
      \calib_sel_reg[0]_2\ => \calib_sel_reg[0]_2\,
      \calib_sel_reg[1]\ => \calib_sel_reg[1]\,
      \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_0\,
      \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_1\,
      \calib_sel_reg[1]_10\ => \calib_sel_reg[1]_10\,
      \calib_sel_reg[1]_11\ => \calib_sel_reg[1]_11\,
      \calib_sel_reg[1]_12\ => \calib_sel_reg[1]_12\,
      \calib_sel_reg[1]_13\ => \calib_sel_reg[1]_13\,
      \calib_sel_reg[1]_14\ => \calib_sel_reg[1]_14\,
      \calib_sel_reg[1]_15\(5 downto 0) => \calib_sel_reg[1]_15\(5 downto 0),
      \calib_sel_reg[1]_16\ => \calib_sel_reg[1]_16\,
      \calib_sel_reg[1]_17\ => \calib_sel_reg[1]_17\,
      \calib_sel_reg[1]_18\ => \calib_sel_reg[1]_18\,
      \calib_sel_reg[1]_19\ => \calib_sel_reg[1]_19\,
      \calib_sel_reg[1]_2\ => \calib_sel_reg[1]_2\,
      \calib_sel_reg[1]_20\ => \calib_sel_reg[1]_20\,
      \calib_sel_reg[1]_21\ => \calib_sel_reg[1]_21\,
      \calib_sel_reg[1]_22\(5 downto 0) => \calib_sel_reg[1]_22\(5 downto 0),
      \calib_sel_reg[1]_23\ => \calib_sel_reg[1]_23\,
      \calib_sel_reg[1]_24\ => \calib_sel_reg[1]_24\,
      \calib_sel_reg[1]_25\ => \calib_sel_reg[1]_25\,
      \calib_sel_reg[1]_26\ => \calib_sel_reg[1]_26\,
      \calib_sel_reg[1]_27\ => \calib_sel_reg[1]_27\,
      \calib_sel_reg[1]_28\ => \calib_sel_reg[1]_28\,
      \calib_sel_reg[1]_29\ => \calib_sel_reg[1]_29\,
      \calib_sel_reg[1]_3\ => \calib_sel_reg[1]_3\,
      \calib_sel_reg[1]_30\(5 downto 0) => \calib_sel_reg[1]_30\(5 downto 0),
      \calib_sel_reg[1]_31\ => \calib_sel_reg[1]_31\,
      \calib_sel_reg[1]_32\ => \calib_sel_reg[1]_32\,
      \calib_sel_reg[1]_33\ => \calib_sel_reg[1]_33\,
      \calib_sel_reg[1]_34\ => \calib_sel_reg[1]_34\,
      \calib_sel_reg[1]_35\ => \calib_sel_reg[1]_35\,
      \calib_sel_reg[1]_36\ => \calib_sel_reg[1]_36\,
      \calib_sel_reg[1]_37\(5 downto 0) => \calib_sel_reg[1]_37\(5 downto 0),
      \calib_sel_reg[1]_38\ => \calib_sel_reg[1]_38\,
      \calib_sel_reg[1]_39\ => \calib_sel_reg[1]_39\,
      \calib_sel_reg[1]_4\ => \calib_sel_reg[1]_4\,
      \calib_sel_reg[1]_5\ => \calib_sel_reg[1]_5\,
      \calib_sel_reg[1]_6\ => \calib_sel_reg[1]_6\,
      \calib_sel_reg[1]_7\ => \calib_sel_reg[1]_7\,
      \calib_sel_reg[1]_8\ => \calib_sel_reg[1]_8\,
      \calib_sel_reg[1]_9\(5 downto 0) => \calib_sel_reg[1]_9\(5 downto 0),
      \calib_sel_reg[4]\(3 downto 0) => \calib_sel_reg[4]\(3 downto 0),
      ck_po_stg2_f_indec_reg => ck_po_stg2_f_indec_reg,
      ck_po_stg2_f_indec_reg_0 => ck_po_stg2_f_indec_reg_0,
      ck_po_stg2_f_indec_reg_1 => ck_po_stg2_f_indec_reg_1,
      ck_po_stg2_f_indec_reg_2 => ck_po_stg2_f_indec_reg_2,
      ck_po_stg2_f_indec_reg_3 => ck_po_stg2_f_indec_reg_3,
      ck_po_stg2_f_indec_reg_4 => ck_po_stg2_f_indec_reg_4,
      ck_po_stg2_f_indec_reg_5 => ck_po_stg2_f_indec_reg_5,
      ck_po_stg2_f_indec_reg_6 => ck_po_stg2_f_indec_reg_6,
      ck_po_stg2_f_indec_reg_7 => ck_po_stg2_f_indec_reg_7,
      ck_po_stg2_f_indec_reg_8 => ck_po_stg2_f_indec_reg_8,
      \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1 downto 0),
      cnt_pwron_cke_done_r => cnt_pwron_cke_done_r,
      \data_offset_1_i2_reg[5]\(5 downto 0) => data_offset_1_i2(5 downto 0),
      \data_offset_2_i2_reg[5]\(5 downto 0) => data_offset_2_i2(5 downto 0),
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\,
      dqs_wl_po_stg2_c_incdec_reg => dqs_wl_po_stg2_c_incdec_reg,
      dqs_wl_po_stg2_c_incdec_reg_0 => dqs_wl_po_stg2_c_incdec_reg_0,
      freq_refclk => freq_refclk,
      \gen_byte_sel_div2.calib_in_common_reg\ => \gen_byte_sel_div2.calib_in_common_reg\,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => \gen_byte_sel_div2.calib_in_common_reg_0\,
      \gen_byte_sel_div2.calib_in_common_reg_1\ => \gen_byte_sel_div2.calib_in_common_reg_1\,
      \gen_byte_sel_div2.calib_in_common_reg_2\ => \gen_byte_sel_div2.calib_in_common_reg_2\,
      \gen_byte_sel_div2.calib_in_common_reg_3\ => \gen_byte_sel_div2.calib_in_common_reg_3\,
      \gen_byte_sel_div2.calib_in_common_reg_4\ => \gen_byte_sel_div2.calib_in_common_reg_4\,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\,
      idelay_ce_r2_reg => idelay_ce_r2_reg,
      idelay_ce_r2_reg_0 => idelay_ce_r2_reg_0,
      idelay_inc => idelay_inc,
      idelay_ld_rst => idelay_ld_rst,
      idelay_ld_rst_0 => idelay_ld_rst_0,
      idelay_ld_rst_1 => idelay_ld_rst_1,
      idelay_ld_rst_2 => idelay_ld_rst_2,
      idelay_ld_rst_3 => idelay_ld_rst_3,
      idelay_ld_rst_5 => idelay_ld_rst_5,
      ififo_rst_reg0 => ififo_rst_reg0,
      in0 => in0,
      init_calib_complete_reg(21 downto 0) => init_calib_complete_reg(21 downto 0),
      init_calib_complete_reg_rep => init_calib_complete_reg_rep,
      \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\,
      \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\,
      \init_calib_complete_reg_rep__10\(3 downto 0) => \init_calib_complete_reg_rep__10\(3 downto 0),
      \init_calib_complete_reg_rep__10_0\(3 downto 0) => \init_calib_complete_reg_rep__10_0\(3 downto 0),
      \init_calib_complete_reg_rep__10_1\(3 downto 0) => \init_calib_complete_reg_rep__10_1\(3 downto 0),
      \init_calib_complete_reg_rep__10_2\ => \init_calib_complete_reg_rep__10_2\,
      \init_calib_complete_reg_rep__11\(7 downto 0) => \init_calib_complete_reg_rep__11\(7 downto 0),
      \init_calib_complete_reg_rep__11_0\(7 downto 0) => \init_calib_complete_reg_rep__11_0\(7 downto 0),
      \init_calib_complete_reg_rep__11_1\ => \init_calib_complete_reg_rep__11_1\,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      \init_calib_complete_reg_rep__12_0\(3 downto 0) => \init_calib_complete_reg_rep__12_1\(3 downto 0),
      \init_calib_complete_reg_rep__12_1\(3 downto 0) => \init_calib_complete_reg_rep__12_2\(3 downto 0),
      \init_calib_complete_reg_rep__12_2\(3 downto 0) => \init_calib_complete_reg_rep__12_0\(3 downto 0),
      \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\,
      \init_calib_complete_reg_rep__25\(45 downto 0) => \init_calib_complete_reg_rep__25\(45 downto 0),
      \init_calib_complete_reg_rep__3\ => \init_calib_complete_reg_rep__3\,
      \init_calib_complete_reg_rep__4\ => \init_calib_complete_reg_rep__4\,
      \init_calib_complete_reg_rep__5\ => \init_calib_complete_reg_rep__5\,
      \init_calib_complete_reg_rep__6\ => \init_calib_complete_reg_rep__6\,
      \init_calib_complete_reg_rep__7\ => \init_calib_complete_reg_rep__7\,
      \init_calib_complete_reg_rep__8\ => \init_calib_complete_reg_rep__8\,
      \init_calib_complete_reg_rep__9\ => \init_calib_complete_reg_rep__9\,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      mc_address(3 downto 0) => mc_address(3 downto 0),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1 downto 0) => mc_ras_n(1 downto 0),
      mem_dq_in(63 downto 56) => mem_dq_in(108 downto 101),
      mem_dq_in(55 downto 52) => mem_dq_in(99 downto 96),
      mem_dq_in(51 downto 48) => mem_dq_in(94 downto 91),
      mem_dq_in(47 downto 40) => mem_dq_in(87 downto 80),
      mem_dq_in(39 downto 32) => mem_dq_in(47 downto 40),
      mem_dq_in(31 downto 24) => mem_dq_in(38 downto 31),
      mem_dq_in(23 downto 16) => mem_dq_in(28 downto 21),
      mem_dq_in(15 downto 12) => mem_dq_in(19 downto 16),
      mem_dq_in(11 downto 8) => mem_dq_in(14 downto 11),
      mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0),
      mem_dq_out(94 downto 86) => mem_dq_out(129 downto 121),
      mem_dq_out(85 downto 77) => mem_dq_out(117 downto 109),
      mem_dq_out(76) => mem_dq_out(105),
      mem_dq_out(75 downto 68) => mem_dq_out(103 downto 96),
      mem_dq_out(67) => mem_dq_out(94),
      mem_dq_out(66 downto 62) => mem_dq_out(89 downto 85),
      mem_dq_out(61 downto 48) => mem_dq_out(83 downto 70),
      mem_dq_out(47) => mem_dq_out(65),
      mem_dq_out(46) => mem_dq_out(63),
      mem_dq_out(45) => mem_dq_out(61),
      mem_dq_out(44) => mem_dq_out(57),
      mem_dq_out(43 downto 36) => mem_dq_out(55 downto 48),
      mem_dq_out(35 downto 27) => mem_dq_out(45 downto 37),
      mem_dq_out(26 downto 18) => mem_dq_out(33 downto 25),
      mem_dq_out(17 downto 9) => mem_dq_out(21 downto 13),
      mem_dq_out(8) => mem_dq_out(9),
      mem_dq_out(7 downto 0) => mem_dq_out(7 downto 0),
      mem_dq_ts(71 downto 63) => mem_dq_ts(129 downto 121),
      mem_dq_ts(62 downto 54) => mem_dq_ts(117 downto 109),
      mem_dq_ts(53) => mem_dq_ts(105),
      mem_dq_ts(52 downto 45) => mem_dq_ts(103 downto 96),
      mem_dq_ts(44) => mem_dq_ts(57),
      mem_dq_ts(43 downto 36) => mem_dq_ts(55 downto 48),
      mem_dq_ts(35 downto 27) => mem_dq_ts(45 downto 37),
      mem_dq_ts(26 downto 18) => mem_dq_ts(33 downto 25),
      mem_dq_ts(17 downto 9) => mem_dq_ts(21 downto 13),
      mem_dq_ts(8) => mem_dq_ts(9),
      mem_dq_ts(7 downto 0) => mem_dq_ts(7 downto 0),
      mem_dqs_in(7 downto 5) => mem_dqs_in(10 downto 8),
      mem_dqs_in(4 downto 0) => mem_dqs_in(4 downto 0),
      mem_out(10 downto 0) => mem_out(10 downto 0),
      mem_refclk => mem_refclk,
      mux_wrdata(415 downto 0) => mux_wrdata(415 downto 0),
      mux_wrdata_mask(63 downto 0) => mux_wrdata_mask(63 downto 0),
      \my_empty_reg[1]\ => \my_empty_reg[1]\,
      \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\,
      \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\,
      \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\,
      \my_empty_reg[1]_3\ => \my_empty_reg[1]_3\,
      \my_empty_reg[1]_4\ => \my_empty_reg[1]_4\,
      \my_empty_reg[1]_5\ => \my_empty_reg[1]_5\,
      \my_empty_reg[1]_6\ => \my_empty_reg[1]_6\,
      \my_empty_reg[1]_7\ => \my_empty_reg[1]_7\,
      \my_empty_reg[1]_8\ => \my_empty_reg[1]_8\,
      \my_empty_reg[1]_9\ => \my_empty_reg[1]_9\,
      \my_empty_reg[7]\(43 downto 0) => \my_empty_reg[7]\(43 downto 0),
      \my_empty_reg[7]_0\(43 downto 0) => \my_empty_reg[7]_0\(43 downto 0),
      \my_empty_reg[7]_1\(43 downto 0) => \my_empty_reg[7]_1\(43 downto 0),
      \my_empty_reg[7]_2\(43 downto 0) => \my_empty_reg[7]_2\(43 downto 0),
      \my_empty_reg[7]_3\(43 downto 0) => \my_empty_reg[7]_3\(43 downto 0),
      \my_empty_reg[7]_4\(43 downto 0) => \my_empty_reg[7]_4\(43 downto 0),
      \my_empty_reg[7]_5\(43 downto 0) => \my_empty_reg[7]_5\(43 downto 0),
      \my_empty_reg[7]_6\(43 downto 0) => \my_empty_reg[7]_6\(43 downto 0),
      \not_strict_mode.app_rd_data_reg[0]\ => \not_strict_mode.app_rd_data_reg[0]\,
      \not_strict_mode.app_rd_data_reg[100]\ => \not_strict_mode.app_rd_data_reg[100]\,
      \not_strict_mode.app_rd_data_reg[101]\ => \not_strict_mode.app_rd_data_reg[101]\,
      \not_strict_mode.app_rd_data_reg[102]\ => \not_strict_mode.app_rd_data_reg[102]\,
      \not_strict_mode.app_rd_data_reg[103]\ => \not_strict_mode.app_rd_data_reg[103]\,
      \not_strict_mode.app_rd_data_reg[104]\ => \not_strict_mode.app_rd_data_reg[104]\,
      \not_strict_mode.app_rd_data_reg[105]\ => \not_strict_mode.app_rd_data_reg[105]\,
      \not_strict_mode.app_rd_data_reg[106]\ => \not_strict_mode.app_rd_data_reg[106]\,
      \not_strict_mode.app_rd_data_reg[107]\ => \not_strict_mode.app_rd_data_reg[107]\,
      \not_strict_mode.app_rd_data_reg[108]\ => \not_strict_mode.app_rd_data_reg[108]\,
      \not_strict_mode.app_rd_data_reg[109]\ => \not_strict_mode.app_rd_data_reg[109]\,
      \not_strict_mode.app_rd_data_reg[10]\ => \not_strict_mode.app_rd_data_reg[10]\,
      \not_strict_mode.app_rd_data_reg[110]\ => \not_strict_mode.app_rd_data_reg[110]\,
      \not_strict_mode.app_rd_data_reg[111]\ => \not_strict_mode.app_rd_data_reg[111]\,
      \not_strict_mode.app_rd_data_reg[112]\ => \not_strict_mode.app_rd_data_reg[112]\,
      \not_strict_mode.app_rd_data_reg[113]\ => \not_strict_mode.app_rd_data_reg[113]\,
      \not_strict_mode.app_rd_data_reg[114]\ => \not_strict_mode.app_rd_data_reg[114]\,
      \not_strict_mode.app_rd_data_reg[115]\ => \not_strict_mode.app_rd_data_reg[115]\,
      \not_strict_mode.app_rd_data_reg[116]\ => \not_strict_mode.app_rd_data_reg[116]\,
      \not_strict_mode.app_rd_data_reg[117]\ => \not_strict_mode.app_rd_data_reg[117]\,
      \not_strict_mode.app_rd_data_reg[118]\ => \not_strict_mode.app_rd_data_reg[118]\,
      \not_strict_mode.app_rd_data_reg[119]\ => \not_strict_mode.app_rd_data_reg[119]\,
      \not_strict_mode.app_rd_data_reg[11]\ => \not_strict_mode.app_rd_data_reg[11]\,
      \not_strict_mode.app_rd_data_reg[120]\ => \not_strict_mode.app_rd_data_reg[120]\,
      \not_strict_mode.app_rd_data_reg[121]\ => \not_strict_mode.app_rd_data_reg[121]\,
      \not_strict_mode.app_rd_data_reg[122]\ => \not_strict_mode.app_rd_data_reg[122]\,
      \not_strict_mode.app_rd_data_reg[123]\ => \not_strict_mode.app_rd_data_reg[123]\,
      \not_strict_mode.app_rd_data_reg[124]\ => \not_strict_mode.app_rd_data_reg[124]\,
      \not_strict_mode.app_rd_data_reg[125]\ => \not_strict_mode.app_rd_data_reg[125]\,
      \not_strict_mode.app_rd_data_reg[126]\ => \not_strict_mode.app_rd_data_reg[126]\,
      \not_strict_mode.app_rd_data_reg[127]\ => \not_strict_mode.app_rd_data_reg[127]\,
      \not_strict_mode.app_rd_data_reg[128]\ => \not_strict_mode.app_rd_data_reg[128]\,
      \not_strict_mode.app_rd_data_reg[129]\ => \not_strict_mode.app_rd_data_reg[129]\,
      \not_strict_mode.app_rd_data_reg[12]\ => \not_strict_mode.app_rd_data_reg[12]\,
      \not_strict_mode.app_rd_data_reg[130]\ => \not_strict_mode.app_rd_data_reg[130]\,
      \not_strict_mode.app_rd_data_reg[131]\ => \not_strict_mode.app_rd_data_reg[131]\,
      \not_strict_mode.app_rd_data_reg[132]\ => \not_strict_mode.app_rd_data_reg[132]\,
      \not_strict_mode.app_rd_data_reg[133]\ => \not_strict_mode.app_rd_data_reg[133]\,
      \not_strict_mode.app_rd_data_reg[134]\ => \not_strict_mode.app_rd_data_reg[134]\,
      \not_strict_mode.app_rd_data_reg[135]\ => \not_strict_mode.app_rd_data_reg[135]\,
      \not_strict_mode.app_rd_data_reg[136]\ => \not_strict_mode.app_rd_data_reg[136]\,
      \not_strict_mode.app_rd_data_reg[137]\ => \not_strict_mode.app_rd_data_reg[137]\,
      \not_strict_mode.app_rd_data_reg[138]\ => \not_strict_mode.app_rd_data_reg[138]\,
      \not_strict_mode.app_rd_data_reg[139]\ => \not_strict_mode.app_rd_data_reg[139]\,
      \not_strict_mode.app_rd_data_reg[13]\ => \not_strict_mode.app_rd_data_reg[13]\,
      \not_strict_mode.app_rd_data_reg[140]\ => \not_strict_mode.app_rd_data_reg[140]\,
      \not_strict_mode.app_rd_data_reg[141]\ => \not_strict_mode.app_rd_data_reg[141]\,
      \not_strict_mode.app_rd_data_reg[142]\ => \not_strict_mode.app_rd_data_reg[142]\,
      \not_strict_mode.app_rd_data_reg[143]\ => \not_strict_mode.app_rd_data_reg[143]\,
      \not_strict_mode.app_rd_data_reg[144]\ => \not_strict_mode.app_rd_data_reg[144]\,
      \not_strict_mode.app_rd_data_reg[145]\ => \not_strict_mode.app_rd_data_reg[145]\,
      \not_strict_mode.app_rd_data_reg[146]\ => \not_strict_mode.app_rd_data_reg[146]\,
      \not_strict_mode.app_rd_data_reg[147]\ => \not_strict_mode.app_rd_data_reg[147]\,
      \not_strict_mode.app_rd_data_reg[148]\ => \not_strict_mode.app_rd_data_reg[148]\,
      \not_strict_mode.app_rd_data_reg[149]\ => \not_strict_mode.app_rd_data_reg[149]\,
      \not_strict_mode.app_rd_data_reg[14]\ => \not_strict_mode.app_rd_data_reg[14]\,
      \not_strict_mode.app_rd_data_reg[150]\ => \not_strict_mode.app_rd_data_reg[150]\,
      \not_strict_mode.app_rd_data_reg[151]\ => \not_strict_mode.app_rd_data_reg[151]\,
      \not_strict_mode.app_rd_data_reg[152]\ => \not_strict_mode.app_rd_data_reg[152]\,
      \not_strict_mode.app_rd_data_reg[153]\ => \not_strict_mode.app_rd_data_reg[153]\,
      \not_strict_mode.app_rd_data_reg[154]\ => \not_strict_mode.app_rd_data_reg[154]\,
      \not_strict_mode.app_rd_data_reg[155]\ => \not_strict_mode.app_rd_data_reg[155]\,
      \not_strict_mode.app_rd_data_reg[156]\ => \not_strict_mode.app_rd_data_reg[156]\,
      \not_strict_mode.app_rd_data_reg[157]\ => \not_strict_mode.app_rd_data_reg[157]\,
      \not_strict_mode.app_rd_data_reg[158]\ => \not_strict_mode.app_rd_data_reg[158]\,
      \not_strict_mode.app_rd_data_reg[159]\ => \not_strict_mode.app_rd_data_reg[159]\,
      \not_strict_mode.app_rd_data_reg[15]\ => \not_strict_mode.app_rd_data_reg[15]\,
      \not_strict_mode.app_rd_data_reg[160]\ => \not_strict_mode.app_rd_data_reg[160]\,
      \not_strict_mode.app_rd_data_reg[161]\ => \not_strict_mode.app_rd_data_reg[161]\,
      \not_strict_mode.app_rd_data_reg[162]\ => \not_strict_mode.app_rd_data_reg[162]\,
      \not_strict_mode.app_rd_data_reg[163]\ => \not_strict_mode.app_rd_data_reg[163]\,
      \not_strict_mode.app_rd_data_reg[164]\ => \not_strict_mode.app_rd_data_reg[164]\,
      \not_strict_mode.app_rd_data_reg[165]\ => \not_strict_mode.app_rd_data_reg[165]\,
      \not_strict_mode.app_rd_data_reg[166]\ => \not_strict_mode.app_rd_data_reg[166]\,
      \not_strict_mode.app_rd_data_reg[167]\ => \not_strict_mode.app_rd_data_reg[167]\,
      \not_strict_mode.app_rd_data_reg[168]\ => \not_strict_mode.app_rd_data_reg[168]\,
      \not_strict_mode.app_rd_data_reg[169]\ => \not_strict_mode.app_rd_data_reg[169]\,
      \not_strict_mode.app_rd_data_reg[16]\ => \not_strict_mode.app_rd_data_reg[16]\,
      \not_strict_mode.app_rd_data_reg[170]\ => \not_strict_mode.app_rd_data_reg[170]\,
      \not_strict_mode.app_rd_data_reg[171]\ => \not_strict_mode.app_rd_data_reg[171]\,
      \not_strict_mode.app_rd_data_reg[172]\ => \not_strict_mode.app_rd_data_reg[172]\,
      \not_strict_mode.app_rd_data_reg[173]\ => \not_strict_mode.app_rd_data_reg[173]\,
      \not_strict_mode.app_rd_data_reg[174]\ => \not_strict_mode.app_rd_data_reg[174]\,
      \not_strict_mode.app_rd_data_reg[175]\ => \not_strict_mode.app_rd_data_reg[175]\,
      \not_strict_mode.app_rd_data_reg[176]\ => \not_strict_mode.app_rd_data_reg[176]\,
      \not_strict_mode.app_rd_data_reg[177]\ => \not_strict_mode.app_rd_data_reg[177]\,
      \not_strict_mode.app_rd_data_reg[178]\ => \not_strict_mode.app_rd_data_reg[178]\,
      \not_strict_mode.app_rd_data_reg[179]\ => \not_strict_mode.app_rd_data_reg[179]\,
      \not_strict_mode.app_rd_data_reg[17]\ => \not_strict_mode.app_rd_data_reg[17]\,
      \not_strict_mode.app_rd_data_reg[180]\ => \not_strict_mode.app_rd_data_reg[180]\,
      \not_strict_mode.app_rd_data_reg[181]\ => \not_strict_mode.app_rd_data_reg[181]\,
      \not_strict_mode.app_rd_data_reg[182]\ => \not_strict_mode.app_rd_data_reg[182]\,
      \not_strict_mode.app_rd_data_reg[183]\ => \not_strict_mode.app_rd_data_reg[183]\,
      \not_strict_mode.app_rd_data_reg[184]\ => \not_strict_mode.app_rd_data_reg[184]\,
      \not_strict_mode.app_rd_data_reg[185]\ => \not_strict_mode.app_rd_data_reg[185]\,
      \not_strict_mode.app_rd_data_reg[186]\ => \not_strict_mode.app_rd_data_reg[186]\,
      \not_strict_mode.app_rd_data_reg[187]\ => \not_strict_mode.app_rd_data_reg[187]\,
      \not_strict_mode.app_rd_data_reg[188]\ => \not_strict_mode.app_rd_data_reg[188]\,
      \not_strict_mode.app_rd_data_reg[189]\ => \not_strict_mode.app_rd_data_reg[189]\,
      \not_strict_mode.app_rd_data_reg[18]\ => \not_strict_mode.app_rd_data_reg[18]\,
      \not_strict_mode.app_rd_data_reg[190]\ => \not_strict_mode.app_rd_data_reg[190]\,
      \not_strict_mode.app_rd_data_reg[191]\ => \not_strict_mode.app_rd_data_reg[191]\,
      \not_strict_mode.app_rd_data_reg[192]\ => \not_strict_mode.app_rd_data_reg[192]\,
      \not_strict_mode.app_rd_data_reg[193]\ => \not_strict_mode.app_rd_data_reg[193]\,
      \not_strict_mode.app_rd_data_reg[194]\ => \not_strict_mode.app_rd_data_reg[194]\,
      \not_strict_mode.app_rd_data_reg[195]\ => \not_strict_mode.app_rd_data_reg[195]\,
      \not_strict_mode.app_rd_data_reg[196]\ => \not_strict_mode.app_rd_data_reg[196]\,
      \not_strict_mode.app_rd_data_reg[197]\ => \not_strict_mode.app_rd_data_reg[197]\,
      \not_strict_mode.app_rd_data_reg[198]\ => \not_strict_mode.app_rd_data_reg[198]\,
      \not_strict_mode.app_rd_data_reg[199]\ => \not_strict_mode.app_rd_data_reg[199]\,
      \not_strict_mode.app_rd_data_reg[19]\ => \not_strict_mode.app_rd_data_reg[19]\,
      \not_strict_mode.app_rd_data_reg[1]\ => \not_strict_mode.app_rd_data_reg[1]\,
      \not_strict_mode.app_rd_data_reg[200]\ => \not_strict_mode.app_rd_data_reg[200]\,
      \not_strict_mode.app_rd_data_reg[201]\ => \not_strict_mode.app_rd_data_reg[201]\,
      \not_strict_mode.app_rd_data_reg[202]\ => \not_strict_mode.app_rd_data_reg[202]\,
      \not_strict_mode.app_rd_data_reg[203]\ => \not_strict_mode.app_rd_data_reg[203]\,
      \not_strict_mode.app_rd_data_reg[204]\ => \not_strict_mode.app_rd_data_reg[204]\,
      \not_strict_mode.app_rd_data_reg[205]\ => \not_strict_mode.app_rd_data_reg[205]\,
      \not_strict_mode.app_rd_data_reg[206]\ => \not_strict_mode.app_rd_data_reg[206]\,
      \not_strict_mode.app_rd_data_reg[207]\ => \not_strict_mode.app_rd_data_reg[207]\,
      \not_strict_mode.app_rd_data_reg[208]\ => \not_strict_mode.app_rd_data_reg[208]\,
      \not_strict_mode.app_rd_data_reg[209]\ => \not_strict_mode.app_rd_data_reg[209]\,
      \not_strict_mode.app_rd_data_reg[20]\ => \not_strict_mode.app_rd_data_reg[20]\,
      \not_strict_mode.app_rd_data_reg[210]\ => \not_strict_mode.app_rd_data_reg[210]\,
      \not_strict_mode.app_rd_data_reg[211]\ => \not_strict_mode.app_rd_data_reg[211]\,
      \not_strict_mode.app_rd_data_reg[212]\ => \not_strict_mode.app_rd_data_reg[212]\,
      \not_strict_mode.app_rd_data_reg[213]\ => \not_strict_mode.app_rd_data_reg[213]\,
      \not_strict_mode.app_rd_data_reg[214]\ => \not_strict_mode.app_rd_data_reg[214]\,
      \not_strict_mode.app_rd_data_reg[215]\ => \not_strict_mode.app_rd_data_reg[215]\,
      \not_strict_mode.app_rd_data_reg[216]\ => \not_strict_mode.app_rd_data_reg[216]\,
      \not_strict_mode.app_rd_data_reg[217]\ => \not_strict_mode.app_rd_data_reg[217]\,
      \not_strict_mode.app_rd_data_reg[218]\ => \not_strict_mode.app_rd_data_reg[218]\,
      \not_strict_mode.app_rd_data_reg[219]\ => \not_strict_mode.app_rd_data_reg[219]\,
      \not_strict_mode.app_rd_data_reg[21]\ => \not_strict_mode.app_rd_data_reg[21]\,
      \not_strict_mode.app_rd_data_reg[220]\ => \not_strict_mode.app_rd_data_reg[220]\,
      \not_strict_mode.app_rd_data_reg[221]\ => \not_strict_mode.app_rd_data_reg[221]\,
      \not_strict_mode.app_rd_data_reg[222]\ => \not_strict_mode.app_rd_data_reg[222]\,
      \not_strict_mode.app_rd_data_reg[223]\ => \not_strict_mode.app_rd_data_reg[223]\,
      \not_strict_mode.app_rd_data_reg[224]\ => \not_strict_mode.app_rd_data_reg[224]\,
      \not_strict_mode.app_rd_data_reg[225]\ => \not_strict_mode.app_rd_data_reg[225]\,
      \not_strict_mode.app_rd_data_reg[226]\ => \not_strict_mode.app_rd_data_reg[226]\,
      \not_strict_mode.app_rd_data_reg[227]\ => \not_strict_mode.app_rd_data_reg[227]\,
      \not_strict_mode.app_rd_data_reg[228]\ => \not_strict_mode.app_rd_data_reg[228]\,
      \not_strict_mode.app_rd_data_reg[229]\ => \not_strict_mode.app_rd_data_reg[229]\,
      \not_strict_mode.app_rd_data_reg[22]\ => \not_strict_mode.app_rd_data_reg[22]\,
      \not_strict_mode.app_rd_data_reg[230]\ => \not_strict_mode.app_rd_data_reg[230]\,
      \not_strict_mode.app_rd_data_reg[231]\ => \not_strict_mode.app_rd_data_reg[231]\,
      \not_strict_mode.app_rd_data_reg[232]\ => \not_strict_mode.app_rd_data_reg[232]\,
      \not_strict_mode.app_rd_data_reg[233]\ => \not_strict_mode.app_rd_data_reg[233]\,
      \not_strict_mode.app_rd_data_reg[234]\ => \not_strict_mode.app_rd_data_reg[234]\,
      \not_strict_mode.app_rd_data_reg[235]\ => \not_strict_mode.app_rd_data_reg[235]\,
      \not_strict_mode.app_rd_data_reg[236]\ => \not_strict_mode.app_rd_data_reg[236]\,
      \not_strict_mode.app_rd_data_reg[237]\ => \not_strict_mode.app_rd_data_reg[237]\,
      \not_strict_mode.app_rd_data_reg[238]\ => \not_strict_mode.app_rd_data_reg[238]\,
      \not_strict_mode.app_rd_data_reg[239]\ => \not_strict_mode.app_rd_data_reg[239]\,
      \not_strict_mode.app_rd_data_reg[23]\ => \not_strict_mode.app_rd_data_reg[23]\,
      \not_strict_mode.app_rd_data_reg[240]\ => \not_strict_mode.app_rd_data_reg[240]\,
      \not_strict_mode.app_rd_data_reg[241]\ => \not_strict_mode.app_rd_data_reg[241]\,
      \not_strict_mode.app_rd_data_reg[242]\ => \not_strict_mode.app_rd_data_reg[242]\,
      \not_strict_mode.app_rd_data_reg[243]\ => \not_strict_mode.app_rd_data_reg[243]\,
      \not_strict_mode.app_rd_data_reg[244]\ => \not_strict_mode.app_rd_data_reg[244]\,
      \not_strict_mode.app_rd_data_reg[245]\ => \not_strict_mode.app_rd_data_reg[245]\,
      \not_strict_mode.app_rd_data_reg[246]\ => \not_strict_mode.app_rd_data_reg[246]\,
      \not_strict_mode.app_rd_data_reg[247]\ => \not_strict_mode.app_rd_data_reg[247]\,
      \not_strict_mode.app_rd_data_reg[248]\ => \not_strict_mode.app_rd_data_reg[248]\,
      \not_strict_mode.app_rd_data_reg[249]\ => \not_strict_mode.app_rd_data_reg[249]\,
      \not_strict_mode.app_rd_data_reg[24]\ => \not_strict_mode.app_rd_data_reg[24]\,
      \not_strict_mode.app_rd_data_reg[250]\ => \not_strict_mode.app_rd_data_reg[250]\,
      \not_strict_mode.app_rd_data_reg[251]\ => \not_strict_mode.app_rd_data_reg[251]\,
      \not_strict_mode.app_rd_data_reg[252]\ => \not_strict_mode.app_rd_data_reg[252]\,
      \not_strict_mode.app_rd_data_reg[253]\ => \not_strict_mode.app_rd_data_reg[253]\,
      \not_strict_mode.app_rd_data_reg[254]\ => \not_strict_mode.app_rd_data_reg[254]\,
      \not_strict_mode.app_rd_data_reg[255]\ => \not_strict_mode.app_rd_data_reg[255]\,
      \not_strict_mode.app_rd_data_reg[256]\ => \not_strict_mode.app_rd_data_reg[256]\,
      \not_strict_mode.app_rd_data_reg[257]\ => \not_strict_mode.app_rd_data_reg[257]\,
      \not_strict_mode.app_rd_data_reg[258]\ => \not_strict_mode.app_rd_data_reg[258]\,
      \not_strict_mode.app_rd_data_reg[259]\ => \not_strict_mode.app_rd_data_reg[259]\,
      \not_strict_mode.app_rd_data_reg[25]\ => \not_strict_mode.app_rd_data_reg[25]\,
      \not_strict_mode.app_rd_data_reg[260]\ => \not_strict_mode.app_rd_data_reg[260]\,
      \not_strict_mode.app_rd_data_reg[261]\ => \not_strict_mode.app_rd_data_reg[261]\,
      \not_strict_mode.app_rd_data_reg[262]\ => \not_strict_mode.app_rd_data_reg[262]\,
      \not_strict_mode.app_rd_data_reg[263]\ => \not_strict_mode.app_rd_data_reg[263]\,
      \not_strict_mode.app_rd_data_reg[264]\ => \not_strict_mode.app_rd_data_reg[264]\,
      \not_strict_mode.app_rd_data_reg[265]\ => \not_strict_mode.app_rd_data_reg[265]\,
      \not_strict_mode.app_rd_data_reg[266]\ => \not_strict_mode.app_rd_data_reg[266]\,
      \not_strict_mode.app_rd_data_reg[267]\ => \not_strict_mode.app_rd_data_reg[267]\,
      \not_strict_mode.app_rd_data_reg[268]\ => \not_strict_mode.app_rd_data_reg[268]\,
      \not_strict_mode.app_rd_data_reg[269]\ => \not_strict_mode.app_rd_data_reg[269]\,
      \not_strict_mode.app_rd_data_reg[26]\ => \not_strict_mode.app_rd_data_reg[26]\,
      \not_strict_mode.app_rd_data_reg[270]\ => \not_strict_mode.app_rd_data_reg[270]\,
      \not_strict_mode.app_rd_data_reg[271]\ => \not_strict_mode.app_rd_data_reg[271]\,
      \not_strict_mode.app_rd_data_reg[272]\ => \not_strict_mode.app_rd_data_reg[272]\,
      \not_strict_mode.app_rd_data_reg[273]\ => \not_strict_mode.app_rd_data_reg[273]\,
      \not_strict_mode.app_rd_data_reg[274]\ => \not_strict_mode.app_rd_data_reg[274]\,
      \not_strict_mode.app_rd_data_reg[275]\ => \not_strict_mode.app_rd_data_reg[275]\,
      \not_strict_mode.app_rd_data_reg[276]\ => \not_strict_mode.app_rd_data_reg[276]\,
      \not_strict_mode.app_rd_data_reg[277]\ => \not_strict_mode.app_rd_data_reg[277]\,
      \not_strict_mode.app_rd_data_reg[278]\ => \not_strict_mode.app_rd_data_reg[278]\,
      \not_strict_mode.app_rd_data_reg[279]\ => \not_strict_mode.app_rd_data_reg[279]\,
      \not_strict_mode.app_rd_data_reg[27]\ => \not_strict_mode.app_rd_data_reg[27]\,
      \not_strict_mode.app_rd_data_reg[280]\ => \not_strict_mode.app_rd_data_reg[280]\,
      \not_strict_mode.app_rd_data_reg[281]\ => \not_strict_mode.app_rd_data_reg[281]\,
      \not_strict_mode.app_rd_data_reg[282]\ => \not_strict_mode.app_rd_data_reg[282]\,
      \not_strict_mode.app_rd_data_reg[283]\ => \not_strict_mode.app_rd_data_reg[283]\,
      \not_strict_mode.app_rd_data_reg[284]\ => \not_strict_mode.app_rd_data_reg[284]\,
      \not_strict_mode.app_rd_data_reg[285]\ => \not_strict_mode.app_rd_data_reg[285]\,
      \not_strict_mode.app_rd_data_reg[286]\ => \not_strict_mode.app_rd_data_reg[286]\,
      \not_strict_mode.app_rd_data_reg[287]\ => \not_strict_mode.app_rd_data_reg[287]\,
      \not_strict_mode.app_rd_data_reg[288]\ => \not_strict_mode.app_rd_data_reg[288]\,
      \not_strict_mode.app_rd_data_reg[289]\ => \not_strict_mode.app_rd_data_reg[289]\,
      \not_strict_mode.app_rd_data_reg[28]\ => \not_strict_mode.app_rd_data_reg[28]\,
      \not_strict_mode.app_rd_data_reg[290]\ => \not_strict_mode.app_rd_data_reg[290]\,
      \not_strict_mode.app_rd_data_reg[291]\ => \not_strict_mode.app_rd_data_reg[291]\,
      \not_strict_mode.app_rd_data_reg[292]\ => \not_strict_mode.app_rd_data_reg[292]\,
      \not_strict_mode.app_rd_data_reg[293]\ => \not_strict_mode.app_rd_data_reg[293]\,
      \not_strict_mode.app_rd_data_reg[294]\ => \not_strict_mode.app_rd_data_reg[294]\,
      \not_strict_mode.app_rd_data_reg[295]\ => \not_strict_mode.app_rd_data_reg[295]\,
      \not_strict_mode.app_rd_data_reg[296]\ => \not_strict_mode.app_rd_data_reg[296]\,
      \not_strict_mode.app_rd_data_reg[297]\ => \not_strict_mode.app_rd_data_reg[297]\,
      \not_strict_mode.app_rd_data_reg[298]\ => \not_strict_mode.app_rd_data_reg[298]\,
      \not_strict_mode.app_rd_data_reg[299]\ => \not_strict_mode.app_rd_data_reg[299]\,
      \not_strict_mode.app_rd_data_reg[29]\ => \not_strict_mode.app_rd_data_reg[29]\,
      \not_strict_mode.app_rd_data_reg[2]\ => \not_strict_mode.app_rd_data_reg[2]\,
      \not_strict_mode.app_rd_data_reg[300]\ => \not_strict_mode.app_rd_data_reg[300]\,
      \not_strict_mode.app_rd_data_reg[301]\ => \not_strict_mode.app_rd_data_reg[301]\,
      \not_strict_mode.app_rd_data_reg[302]\ => \not_strict_mode.app_rd_data_reg[302]\,
      \not_strict_mode.app_rd_data_reg[303]\ => \not_strict_mode.app_rd_data_reg[303]\,
      \not_strict_mode.app_rd_data_reg[304]\ => \not_strict_mode.app_rd_data_reg[304]\,
      \not_strict_mode.app_rd_data_reg[305]\ => \not_strict_mode.app_rd_data_reg[305]\,
      \not_strict_mode.app_rd_data_reg[306]\ => \not_strict_mode.app_rd_data_reg[306]\,
      \not_strict_mode.app_rd_data_reg[307]\ => \not_strict_mode.app_rd_data_reg[307]\,
      \not_strict_mode.app_rd_data_reg[308]\ => \not_strict_mode.app_rd_data_reg[308]\,
      \not_strict_mode.app_rd_data_reg[309]\ => \not_strict_mode.app_rd_data_reg[309]\,
      \not_strict_mode.app_rd_data_reg[30]\ => \not_strict_mode.app_rd_data_reg[30]\,
      \not_strict_mode.app_rd_data_reg[310]\ => \not_strict_mode.app_rd_data_reg[310]\,
      \not_strict_mode.app_rd_data_reg[311]\ => \not_strict_mode.app_rd_data_reg[311]\,
      \not_strict_mode.app_rd_data_reg[312]\ => \not_strict_mode.app_rd_data_reg[312]\,
      \not_strict_mode.app_rd_data_reg[313]\ => \not_strict_mode.app_rd_data_reg[313]\,
      \not_strict_mode.app_rd_data_reg[314]\ => \not_strict_mode.app_rd_data_reg[314]\,
      \not_strict_mode.app_rd_data_reg[315]\ => \not_strict_mode.app_rd_data_reg[315]\,
      \not_strict_mode.app_rd_data_reg[316]\ => \not_strict_mode.app_rd_data_reg[316]\,
      \not_strict_mode.app_rd_data_reg[317]\ => \not_strict_mode.app_rd_data_reg[317]\,
      \not_strict_mode.app_rd_data_reg[318]\ => \not_strict_mode.app_rd_data_reg[318]\,
      \not_strict_mode.app_rd_data_reg[319]\ => \not_strict_mode.app_rd_data_reg[319]\,
      \not_strict_mode.app_rd_data_reg[31]\ => \not_strict_mode.app_rd_data_reg[31]\,
      \not_strict_mode.app_rd_data_reg[320]\ => \not_strict_mode.app_rd_data_reg[320]\,
      \not_strict_mode.app_rd_data_reg[321]\ => \not_strict_mode.app_rd_data_reg[321]\,
      \not_strict_mode.app_rd_data_reg[322]\ => \not_strict_mode.app_rd_data_reg[322]\,
      \not_strict_mode.app_rd_data_reg[323]\ => \not_strict_mode.app_rd_data_reg[323]\,
      \not_strict_mode.app_rd_data_reg[324]\ => \not_strict_mode.app_rd_data_reg[324]\,
      \not_strict_mode.app_rd_data_reg[325]\ => \not_strict_mode.app_rd_data_reg[325]\,
      \not_strict_mode.app_rd_data_reg[326]\ => \not_strict_mode.app_rd_data_reg[326]\,
      \not_strict_mode.app_rd_data_reg[327]\ => \not_strict_mode.app_rd_data_reg[327]\,
      \not_strict_mode.app_rd_data_reg[328]\ => \not_strict_mode.app_rd_data_reg[328]\,
      \not_strict_mode.app_rd_data_reg[329]\ => \not_strict_mode.app_rd_data_reg[329]\,
      \not_strict_mode.app_rd_data_reg[32]\ => \not_strict_mode.app_rd_data_reg[32]\,
      \not_strict_mode.app_rd_data_reg[330]\ => \not_strict_mode.app_rd_data_reg[330]\,
      \not_strict_mode.app_rd_data_reg[331]\ => \not_strict_mode.app_rd_data_reg[331]\,
      \not_strict_mode.app_rd_data_reg[332]\ => \not_strict_mode.app_rd_data_reg[332]\,
      \not_strict_mode.app_rd_data_reg[333]\ => \not_strict_mode.app_rd_data_reg[333]\,
      \not_strict_mode.app_rd_data_reg[334]\ => \not_strict_mode.app_rd_data_reg[334]\,
      \not_strict_mode.app_rd_data_reg[335]\ => \not_strict_mode.app_rd_data_reg[335]\,
      \not_strict_mode.app_rd_data_reg[336]\ => \not_strict_mode.app_rd_data_reg[336]\,
      \not_strict_mode.app_rd_data_reg[337]\ => \not_strict_mode.app_rd_data_reg[337]\,
      \not_strict_mode.app_rd_data_reg[338]\ => \not_strict_mode.app_rd_data_reg[338]\,
      \not_strict_mode.app_rd_data_reg[339]\ => \not_strict_mode.app_rd_data_reg[339]\,
      \not_strict_mode.app_rd_data_reg[33]\ => \not_strict_mode.app_rd_data_reg[33]\,
      \not_strict_mode.app_rd_data_reg[340]\ => \not_strict_mode.app_rd_data_reg[340]\,
      \not_strict_mode.app_rd_data_reg[341]\ => \not_strict_mode.app_rd_data_reg[341]\,
      \not_strict_mode.app_rd_data_reg[342]\ => \not_strict_mode.app_rd_data_reg[342]\,
      \not_strict_mode.app_rd_data_reg[343]\ => \not_strict_mode.app_rd_data_reg[343]\,
      \not_strict_mode.app_rd_data_reg[344]\ => \not_strict_mode.app_rd_data_reg[344]\,
      \not_strict_mode.app_rd_data_reg[345]\ => \not_strict_mode.app_rd_data_reg[345]\,
      \not_strict_mode.app_rd_data_reg[346]\ => \not_strict_mode.app_rd_data_reg[346]\,
      \not_strict_mode.app_rd_data_reg[347]\ => \not_strict_mode.app_rd_data_reg[347]\,
      \not_strict_mode.app_rd_data_reg[348]\ => \not_strict_mode.app_rd_data_reg[348]\,
      \not_strict_mode.app_rd_data_reg[349]\ => \not_strict_mode.app_rd_data_reg[349]\,
      \not_strict_mode.app_rd_data_reg[34]\ => \not_strict_mode.app_rd_data_reg[34]\,
      \not_strict_mode.app_rd_data_reg[350]\ => \not_strict_mode.app_rd_data_reg[350]\,
      \not_strict_mode.app_rd_data_reg[351]\ => \not_strict_mode.app_rd_data_reg[351]\,
      \not_strict_mode.app_rd_data_reg[352]\ => \not_strict_mode.app_rd_data_reg[352]\,
      \not_strict_mode.app_rd_data_reg[353]\ => \not_strict_mode.app_rd_data_reg[353]\,
      \not_strict_mode.app_rd_data_reg[354]\ => \not_strict_mode.app_rd_data_reg[354]\,
      \not_strict_mode.app_rd_data_reg[355]\ => \not_strict_mode.app_rd_data_reg[355]\,
      \not_strict_mode.app_rd_data_reg[356]\ => \not_strict_mode.app_rd_data_reg[356]\,
      \not_strict_mode.app_rd_data_reg[357]\ => \not_strict_mode.app_rd_data_reg[357]\,
      \not_strict_mode.app_rd_data_reg[358]\ => \not_strict_mode.app_rd_data_reg[358]\,
      \not_strict_mode.app_rd_data_reg[359]\ => \not_strict_mode.app_rd_data_reg[359]\,
      \not_strict_mode.app_rd_data_reg[35]\ => \not_strict_mode.app_rd_data_reg[35]\,
      \not_strict_mode.app_rd_data_reg[360]\ => \not_strict_mode.app_rd_data_reg[360]\,
      \not_strict_mode.app_rd_data_reg[361]\ => \not_strict_mode.app_rd_data_reg[361]\,
      \not_strict_mode.app_rd_data_reg[362]\ => \not_strict_mode.app_rd_data_reg[362]\,
      \not_strict_mode.app_rd_data_reg[363]\ => \not_strict_mode.app_rd_data_reg[363]\,
      \not_strict_mode.app_rd_data_reg[364]\ => \not_strict_mode.app_rd_data_reg[364]\,
      \not_strict_mode.app_rd_data_reg[365]\ => \not_strict_mode.app_rd_data_reg[365]\,
      \not_strict_mode.app_rd_data_reg[366]\ => \not_strict_mode.app_rd_data_reg[366]\,
      \not_strict_mode.app_rd_data_reg[367]\ => \not_strict_mode.app_rd_data_reg[367]\,
      \not_strict_mode.app_rd_data_reg[368]\ => \not_strict_mode.app_rd_data_reg[368]\,
      \not_strict_mode.app_rd_data_reg[369]\ => \not_strict_mode.app_rd_data_reg[369]\,
      \not_strict_mode.app_rd_data_reg[36]\ => \not_strict_mode.app_rd_data_reg[36]\,
      \not_strict_mode.app_rd_data_reg[370]\ => \not_strict_mode.app_rd_data_reg[370]\,
      \not_strict_mode.app_rd_data_reg[371]\ => \not_strict_mode.app_rd_data_reg[371]\,
      \not_strict_mode.app_rd_data_reg[372]\ => \not_strict_mode.app_rd_data_reg[372]\,
      \not_strict_mode.app_rd_data_reg[373]\ => \not_strict_mode.app_rd_data_reg[373]\,
      \not_strict_mode.app_rd_data_reg[374]\ => \not_strict_mode.app_rd_data_reg[374]\,
      \not_strict_mode.app_rd_data_reg[375]\ => \not_strict_mode.app_rd_data_reg[375]\,
      \not_strict_mode.app_rd_data_reg[376]\ => \not_strict_mode.app_rd_data_reg[376]\,
      \not_strict_mode.app_rd_data_reg[377]\ => \not_strict_mode.app_rd_data_reg[377]\,
      \not_strict_mode.app_rd_data_reg[378]\ => \not_strict_mode.app_rd_data_reg[378]\,
      \not_strict_mode.app_rd_data_reg[379]\ => \not_strict_mode.app_rd_data_reg[379]\,
      \not_strict_mode.app_rd_data_reg[37]\ => \not_strict_mode.app_rd_data_reg[37]\,
      \not_strict_mode.app_rd_data_reg[380]\ => \not_strict_mode.app_rd_data_reg[380]\,
      \not_strict_mode.app_rd_data_reg[381]\ => \not_strict_mode.app_rd_data_reg[381]\,
      \not_strict_mode.app_rd_data_reg[382]\ => \not_strict_mode.app_rd_data_reg[382]\,
      \not_strict_mode.app_rd_data_reg[383]\ => \not_strict_mode.app_rd_data_reg[383]\,
      \not_strict_mode.app_rd_data_reg[384]\ => \not_strict_mode.app_rd_data_reg[384]\,
      \not_strict_mode.app_rd_data_reg[385]\ => \not_strict_mode.app_rd_data_reg[385]\,
      \not_strict_mode.app_rd_data_reg[386]\ => \not_strict_mode.app_rd_data_reg[386]\,
      \not_strict_mode.app_rd_data_reg[387]\ => \not_strict_mode.app_rd_data_reg[387]\,
      \not_strict_mode.app_rd_data_reg[388]\ => \not_strict_mode.app_rd_data_reg[388]\,
      \not_strict_mode.app_rd_data_reg[389]\ => \not_strict_mode.app_rd_data_reg[389]\,
      \not_strict_mode.app_rd_data_reg[38]\ => \not_strict_mode.app_rd_data_reg[38]\,
      \not_strict_mode.app_rd_data_reg[390]\ => \not_strict_mode.app_rd_data_reg[390]\,
      \not_strict_mode.app_rd_data_reg[391]\ => \not_strict_mode.app_rd_data_reg[391]\,
      \not_strict_mode.app_rd_data_reg[392]\ => \not_strict_mode.app_rd_data_reg[392]\,
      \not_strict_mode.app_rd_data_reg[393]\ => \not_strict_mode.app_rd_data_reg[393]\,
      \not_strict_mode.app_rd_data_reg[394]\ => \not_strict_mode.app_rd_data_reg[394]\,
      \not_strict_mode.app_rd_data_reg[395]\ => \not_strict_mode.app_rd_data_reg[395]\,
      \not_strict_mode.app_rd_data_reg[396]\ => \not_strict_mode.app_rd_data_reg[396]\,
      \not_strict_mode.app_rd_data_reg[397]\ => \not_strict_mode.app_rd_data_reg[397]\,
      \not_strict_mode.app_rd_data_reg[398]\ => \not_strict_mode.app_rd_data_reg[398]\,
      \not_strict_mode.app_rd_data_reg[399]\ => \not_strict_mode.app_rd_data_reg[399]\,
      \not_strict_mode.app_rd_data_reg[39]\ => \not_strict_mode.app_rd_data_reg[39]\,
      \not_strict_mode.app_rd_data_reg[3]\ => \not_strict_mode.app_rd_data_reg[3]\,
      \not_strict_mode.app_rd_data_reg[400]\ => \not_strict_mode.app_rd_data_reg[400]\,
      \not_strict_mode.app_rd_data_reg[401]\ => \not_strict_mode.app_rd_data_reg[401]\,
      \not_strict_mode.app_rd_data_reg[402]\ => \not_strict_mode.app_rd_data_reg[402]\,
      \not_strict_mode.app_rd_data_reg[403]\ => \not_strict_mode.app_rd_data_reg[403]\,
      \not_strict_mode.app_rd_data_reg[404]\ => \not_strict_mode.app_rd_data_reg[404]\,
      \not_strict_mode.app_rd_data_reg[405]\ => \not_strict_mode.app_rd_data_reg[405]\,
      \not_strict_mode.app_rd_data_reg[406]\ => \not_strict_mode.app_rd_data_reg[406]\,
      \not_strict_mode.app_rd_data_reg[407]\ => \not_strict_mode.app_rd_data_reg[407]\,
      \not_strict_mode.app_rd_data_reg[408]\ => \not_strict_mode.app_rd_data_reg[408]\,
      \not_strict_mode.app_rd_data_reg[409]\ => \not_strict_mode.app_rd_data_reg[409]\,
      \not_strict_mode.app_rd_data_reg[40]\ => \not_strict_mode.app_rd_data_reg[40]\,
      \not_strict_mode.app_rd_data_reg[410]\ => \not_strict_mode.app_rd_data_reg[410]\,
      \not_strict_mode.app_rd_data_reg[411]\ => \not_strict_mode.app_rd_data_reg[411]\,
      \not_strict_mode.app_rd_data_reg[412]\ => \not_strict_mode.app_rd_data_reg[412]\,
      \not_strict_mode.app_rd_data_reg[413]\ => \not_strict_mode.app_rd_data_reg[413]\,
      \not_strict_mode.app_rd_data_reg[414]\ => \not_strict_mode.app_rd_data_reg[414]\,
      \not_strict_mode.app_rd_data_reg[415]\ => \not_strict_mode.app_rd_data_reg[415]\,
      \not_strict_mode.app_rd_data_reg[416]\ => \not_strict_mode.app_rd_data_reg[416]\,
      \not_strict_mode.app_rd_data_reg[417]\ => \not_strict_mode.app_rd_data_reg[417]\,
      \not_strict_mode.app_rd_data_reg[418]\ => \not_strict_mode.app_rd_data_reg[418]\,
      \not_strict_mode.app_rd_data_reg[419]\ => \not_strict_mode.app_rd_data_reg[419]\,
      \not_strict_mode.app_rd_data_reg[41]\ => \not_strict_mode.app_rd_data_reg[41]\,
      \not_strict_mode.app_rd_data_reg[420]\ => \not_strict_mode.app_rd_data_reg[420]\,
      \not_strict_mode.app_rd_data_reg[421]\ => \not_strict_mode.app_rd_data_reg[421]\,
      \not_strict_mode.app_rd_data_reg[422]\ => \not_strict_mode.app_rd_data_reg[422]\,
      \not_strict_mode.app_rd_data_reg[423]\ => \not_strict_mode.app_rd_data_reg[423]\,
      \not_strict_mode.app_rd_data_reg[424]\ => \not_strict_mode.app_rd_data_reg[424]\,
      \not_strict_mode.app_rd_data_reg[425]\ => \not_strict_mode.app_rd_data_reg[425]\,
      \not_strict_mode.app_rd_data_reg[426]\ => \not_strict_mode.app_rd_data_reg[426]\,
      \not_strict_mode.app_rd_data_reg[427]\ => \not_strict_mode.app_rd_data_reg[427]\,
      \not_strict_mode.app_rd_data_reg[428]\ => \not_strict_mode.app_rd_data_reg[428]\,
      \not_strict_mode.app_rd_data_reg[429]\ => \not_strict_mode.app_rd_data_reg[429]\,
      \not_strict_mode.app_rd_data_reg[42]\ => \not_strict_mode.app_rd_data_reg[42]\,
      \not_strict_mode.app_rd_data_reg[430]\ => \not_strict_mode.app_rd_data_reg[430]\,
      \not_strict_mode.app_rd_data_reg[431]\ => \not_strict_mode.app_rd_data_reg[431]\,
      \not_strict_mode.app_rd_data_reg[432]\ => \not_strict_mode.app_rd_data_reg[432]\,
      \not_strict_mode.app_rd_data_reg[433]\ => \not_strict_mode.app_rd_data_reg[433]\,
      \not_strict_mode.app_rd_data_reg[434]\ => \not_strict_mode.app_rd_data_reg[434]\,
      \not_strict_mode.app_rd_data_reg[435]\ => \not_strict_mode.app_rd_data_reg[435]\,
      \not_strict_mode.app_rd_data_reg[436]\ => \not_strict_mode.app_rd_data_reg[436]\,
      \not_strict_mode.app_rd_data_reg[437]\ => \not_strict_mode.app_rd_data_reg[437]\,
      \not_strict_mode.app_rd_data_reg[438]\ => \not_strict_mode.app_rd_data_reg[438]\,
      \not_strict_mode.app_rd_data_reg[439]\ => \not_strict_mode.app_rd_data_reg[439]\,
      \not_strict_mode.app_rd_data_reg[43]\ => \not_strict_mode.app_rd_data_reg[43]\,
      \not_strict_mode.app_rd_data_reg[440]\ => \not_strict_mode.app_rd_data_reg[440]\,
      \not_strict_mode.app_rd_data_reg[441]\ => \not_strict_mode.app_rd_data_reg[441]\,
      \not_strict_mode.app_rd_data_reg[442]\ => \not_strict_mode.app_rd_data_reg[442]\,
      \not_strict_mode.app_rd_data_reg[443]\ => \not_strict_mode.app_rd_data_reg[443]\,
      \not_strict_mode.app_rd_data_reg[444]\ => \not_strict_mode.app_rd_data_reg[444]\,
      \not_strict_mode.app_rd_data_reg[445]\ => \not_strict_mode.app_rd_data_reg[445]\,
      \not_strict_mode.app_rd_data_reg[446]\ => \not_strict_mode.app_rd_data_reg[446]\,
      \not_strict_mode.app_rd_data_reg[447]\ => \not_strict_mode.app_rd_data_reg[447]\,
      \not_strict_mode.app_rd_data_reg[448]\ => \not_strict_mode.app_rd_data_reg[448]\,
      \not_strict_mode.app_rd_data_reg[449]\ => \not_strict_mode.app_rd_data_reg[449]\,
      \not_strict_mode.app_rd_data_reg[44]\ => \not_strict_mode.app_rd_data_reg[44]\,
      \not_strict_mode.app_rd_data_reg[450]\ => \not_strict_mode.app_rd_data_reg[450]\,
      \not_strict_mode.app_rd_data_reg[451]\ => \not_strict_mode.app_rd_data_reg[451]\,
      \not_strict_mode.app_rd_data_reg[452]\ => \not_strict_mode.app_rd_data_reg[452]\,
      \not_strict_mode.app_rd_data_reg[453]\ => \not_strict_mode.app_rd_data_reg[453]\,
      \not_strict_mode.app_rd_data_reg[454]\ => \not_strict_mode.app_rd_data_reg[454]\,
      \not_strict_mode.app_rd_data_reg[455]\ => \not_strict_mode.app_rd_data_reg[455]\,
      \not_strict_mode.app_rd_data_reg[456]\ => \not_strict_mode.app_rd_data_reg[456]\,
      \not_strict_mode.app_rd_data_reg[457]\ => \not_strict_mode.app_rd_data_reg[457]\,
      \not_strict_mode.app_rd_data_reg[458]\ => \not_strict_mode.app_rd_data_reg[458]\,
      \not_strict_mode.app_rd_data_reg[459]\ => \not_strict_mode.app_rd_data_reg[459]\,
      \not_strict_mode.app_rd_data_reg[45]\ => \not_strict_mode.app_rd_data_reg[45]\,
      \not_strict_mode.app_rd_data_reg[460]\ => \not_strict_mode.app_rd_data_reg[460]\,
      \not_strict_mode.app_rd_data_reg[461]\ => \not_strict_mode.app_rd_data_reg[461]\,
      \not_strict_mode.app_rd_data_reg[462]\ => \not_strict_mode.app_rd_data_reg[462]\,
      \not_strict_mode.app_rd_data_reg[463]\ => \not_strict_mode.app_rd_data_reg[463]\,
      \not_strict_mode.app_rd_data_reg[464]\ => \not_strict_mode.app_rd_data_reg[464]\,
      \not_strict_mode.app_rd_data_reg[465]\ => \not_strict_mode.app_rd_data_reg[465]\,
      \not_strict_mode.app_rd_data_reg[466]\ => \not_strict_mode.app_rd_data_reg[466]\,
      \not_strict_mode.app_rd_data_reg[467]\ => \not_strict_mode.app_rd_data_reg[467]\,
      \not_strict_mode.app_rd_data_reg[468]\ => \not_strict_mode.app_rd_data_reg[468]\,
      \not_strict_mode.app_rd_data_reg[469]\ => \not_strict_mode.app_rd_data_reg[469]\,
      \not_strict_mode.app_rd_data_reg[46]\ => \not_strict_mode.app_rd_data_reg[46]\,
      \not_strict_mode.app_rd_data_reg[470]\ => \not_strict_mode.app_rd_data_reg[470]\,
      \not_strict_mode.app_rd_data_reg[471]\ => \not_strict_mode.app_rd_data_reg[471]\,
      \not_strict_mode.app_rd_data_reg[472]\ => \not_strict_mode.app_rd_data_reg[472]\,
      \not_strict_mode.app_rd_data_reg[473]\ => \not_strict_mode.app_rd_data_reg[473]\,
      \not_strict_mode.app_rd_data_reg[474]\ => \not_strict_mode.app_rd_data_reg[474]\,
      \not_strict_mode.app_rd_data_reg[475]\ => \not_strict_mode.app_rd_data_reg[475]\,
      \not_strict_mode.app_rd_data_reg[476]\ => \not_strict_mode.app_rd_data_reg[476]\,
      \not_strict_mode.app_rd_data_reg[477]\ => \not_strict_mode.app_rd_data_reg[477]\,
      \not_strict_mode.app_rd_data_reg[478]\ => \not_strict_mode.app_rd_data_reg[478]\,
      \not_strict_mode.app_rd_data_reg[479]\ => \not_strict_mode.app_rd_data_reg[479]\,
      \not_strict_mode.app_rd_data_reg[47]\ => \not_strict_mode.app_rd_data_reg[47]\,
      \not_strict_mode.app_rd_data_reg[480]\ => \not_strict_mode.app_rd_data_reg[480]\,
      \not_strict_mode.app_rd_data_reg[481]\ => \not_strict_mode.app_rd_data_reg[481]\,
      \not_strict_mode.app_rd_data_reg[482]\ => \not_strict_mode.app_rd_data_reg[482]\,
      \not_strict_mode.app_rd_data_reg[483]\ => \not_strict_mode.app_rd_data_reg[483]\,
      \not_strict_mode.app_rd_data_reg[484]\ => \not_strict_mode.app_rd_data_reg[484]\,
      \not_strict_mode.app_rd_data_reg[485]\ => \not_strict_mode.app_rd_data_reg[485]\,
      \not_strict_mode.app_rd_data_reg[486]\ => \not_strict_mode.app_rd_data_reg[486]\,
      \not_strict_mode.app_rd_data_reg[487]\ => \not_strict_mode.app_rd_data_reg[487]\,
      \not_strict_mode.app_rd_data_reg[488]\ => \not_strict_mode.app_rd_data_reg[488]\,
      \not_strict_mode.app_rd_data_reg[489]\ => \not_strict_mode.app_rd_data_reg[489]\,
      \not_strict_mode.app_rd_data_reg[48]\ => \not_strict_mode.app_rd_data_reg[48]\,
      \not_strict_mode.app_rd_data_reg[490]\ => \not_strict_mode.app_rd_data_reg[490]\,
      \not_strict_mode.app_rd_data_reg[491]\ => \not_strict_mode.app_rd_data_reg[491]\,
      \not_strict_mode.app_rd_data_reg[492]\ => \not_strict_mode.app_rd_data_reg[492]\,
      \not_strict_mode.app_rd_data_reg[493]\ => \not_strict_mode.app_rd_data_reg[493]\,
      \not_strict_mode.app_rd_data_reg[494]\ => \not_strict_mode.app_rd_data_reg[494]\,
      \not_strict_mode.app_rd_data_reg[495]\ => \not_strict_mode.app_rd_data_reg[495]\,
      \not_strict_mode.app_rd_data_reg[496]\ => \not_strict_mode.app_rd_data_reg[496]\,
      \not_strict_mode.app_rd_data_reg[497]\ => \not_strict_mode.app_rd_data_reg[497]\,
      \not_strict_mode.app_rd_data_reg[498]\ => \not_strict_mode.app_rd_data_reg[498]\,
      \not_strict_mode.app_rd_data_reg[499]\ => \not_strict_mode.app_rd_data_reg[499]\,
      \not_strict_mode.app_rd_data_reg[49]\ => \not_strict_mode.app_rd_data_reg[49]\,
      \not_strict_mode.app_rd_data_reg[4]\ => \not_strict_mode.app_rd_data_reg[4]\,
      \not_strict_mode.app_rd_data_reg[500]\ => \not_strict_mode.app_rd_data_reg[500]\,
      \not_strict_mode.app_rd_data_reg[501]\ => \not_strict_mode.app_rd_data_reg[501]\,
      \not_strict_mode.app_rd_data_reg[502]\ => \not_strict_mode.app_rd_data_reg[502]\,
      \not_strict_mode.app_rd_data_reg[503]\ => \not_strict_mode.app_rd_data_reg[503]\,
      \not_strict_mode.app_rd_data_reg[504]\ => \not_strict_mode.app_rd_data_reg[504]\,
      \not_strict_mode.app_rd_data_reg[505]\ => \not_strict_mode.app_rd_data_reg[505]\,
      \not_strict_mode.app_rd_data_reg[506]\ => \not_strict_mode.app_rd_data_reg[506]\,
      \not_strict_mode.app_rd_data_reg[507]\ => \not_strict_mode.app_rd_data_reg[507]\,
      \not_strict_mode.app_rd_data_reg[508]\ => \not_strict_mode.app_rd_data_reg[508]\,
      \not_strict_mode.app_rd_data_reg[509]\ => \not_strict_mode.app_rd_data_reg[509]\,
      \not_strict_mode.app_rd_data_reg[50]\ => \not_strict_mode.app_rd_data_reg[50]\,
      \not_strict_mode.app_rd_data_reg[510]\ => \not_strict_mode.app_rd_data_reg[510]\,
      \not_strict_mode.app_rd_data_reg[511]\ => \not_strict_mode.app_rd_data_reg[511]\,
      \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 0) => \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 0),
      \not_strict_mode.app_rd_data_reg[51]\ => \not_strict_mode.app_rd_data_reg[51]\,
      \not_strict_mode.app_rd_data_reg[52]\ => \not_strict_mode.app_rd_data_reg[52]\,
      \not_strict_mode.app_rd_data_reg[53]\ => \not_strict_mode.app_rd_data_reg[53]\,
      \not_strict_mode.app_rd_data_reg[54]\ => \not_strict_mode.app_rd_data_reg[54]\,
      \not_strict_mode.app_rd_data_reg[55]\ => \not_strict_mode.app_rd_data_reg[55]\,
      \not_strict_mode.app_rd_data_reg[56]\ => \not_strict_mode.app_rd_data_reg[56]\,
      \not_strict_mode.app_rd_data_reg[57]\ => \not_strict_mode.app_rd_data_reg[57]\,
      \not_strict_mode.app_rd_data_reg[58]\ => \not_strict_mode.app_rd_data_reg[58]\,
      \not_strict_mode.app_rd_data_reg[59]\ => \not_strict_mode.app_rd_data_reg[59]\,
      \not_strict_mode.app_rd_data_reg[5]\ => \not_strict_mode.app_rd_data_reg[5]\,
      \not_strict_mode.app_rd_data_reg[60]\ => \not_strict_mode.app_rd_data_reg[60]\,
      \not_strict_mode.app_rd_data_reg[61]\ => \not_strict_mode.app_rd_data_reg[61]\,
      \not_strict_mode.app_rd_data_reg[62]\ => \not_strict_mode.app_rd_data_reg[62]\,
      \not_strict_mode.app_rd_data_reg[63]\ => \not_strict_mode.app_rd_data_reg[63]\,
      \not_strict_mode.app_rd_data_reg[64]\ => \not_strict_mode.app_rd_data_reg[64]\,
      \not_strict_mode.app_rd_data_reg[65]\ => \not_strict_mode.app_rd_data_reg[65]\,
      \not_strict_mode.app_rd_data_reg[66]\ => \not_strict_mode.app_rd_data_reg[66]\,
      \not_strict_mode.app_rd_data_reg[67]\ => \not_strict_mode.app_rd_data_reg[67]\,
      \not_strict_mode.app_rd_data_reg[68]\ => \not_strict_mode.app_rd_data_reg[68]\,
      \not_strict_mode.app_rd_data_reg[69]\ => \not_strict_mode.app_rd_data_reg[69]\,
      \not_strict_mode.app_rd_data_reg[6]\ => \not_strict_mode.app_rd_data_reg[6]\,
      \not_strict_mode.app_rd_data_reg[70]\ => \not_strict_mode.app_rd_data_reg[70]\,
      \not_strict_mode.app_rd_data_reg[71]\ => \not_strict_mode.app_rd_data_reg[71]\,
      \not_strict_mode.app_rd_data_reg[72]\ => \not_strict_mode.app_rd_data_reg[72]\,
      \not_strict_mode.app_rd_data_reg[73]\ => \not_strict_mode.app_rd_data_reg[73]\,
      \not_strict_mode.app_rd_data_reg[74]\ => \not_strict_mode.app_rd_data_reg[74]\,
      \not_strict_mode.app_rd_data_reg[75]\ => \not_strict_mode.app_rd_data_reg[75]\,
      \not_strict_mode.app_rd_data_reg[76]\ => \not_strict_mode.app_rd_data_reg[76]\,
      \not_strict_mode.app_rd_data_reg[77]\ => \not_strict_mode.app_rd_data_reg[77]\,
      \not_strict_mode.app_rd_data_reg[78]\ => \not_strict_mode.app_rd_data_reg[78]\,
      \not_strict_mode.app_rd_data_reg[79]\ => \not_strict_mode.app_rd_data_reg[79]\,
      \not_strict_mode.app_rd_data_reg[7]\ => \not_strict_mode.app_rd_data_reg[7]\,
      \not_strict_mode.app_rd_data_reg[80]\ => \not_strict_mode.app_rd_data_reg[80]\,
      \not_strict_mode.app_rd_data_reg[81]\ => \not_strict_mode.app_rd_data_reg[81]\,
      \not_strict_mode.app_rd_data_reg[82]\ => \not_strict_mode.app_rd_data_reg[82]\,
      \not_strict_mode.app_rd_data_reg[83]\ => \not_strict_mode.app_rd_data_reg[83]\,
      \not_strict_mode.app_rd_data_reg[84]\ => \not_strict_mode.app_rd_data_reg[84]\,
      \not_strict_mode.app_rd_data_reg[85]\ => \not_strict_mode.app_rd_data_reg[85]\,
      \not_strict_mode.app_rd_data_reg[86]\ => \not_strict_mode.app_rd_data_reg[86]\,
      \not_strict_mode.app_rd_data_reg[87]\ => \not_strict_mode.app_rd_data_reg[87]\,
      \not_strict_mode.app_rd_data_reg[88]\ => \not_strict_mode.app_rd_data_reg[88]\,
      \not_strict_mode.app_rd_data_reg[89]\ => \not_strict_mode.app_rd_data_reg[89]\,
      \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\,
      \not_strict_mode.app_rd_data_reg[90]\ => \not_strict_mode.app_rd_data_reg[90]\,
      \not_strict_mode.app_rd_data_reg[91]\ => \not_strict_mode.app_rd_data_reg[91]\,
      \not_strict_mode.app_rd_data_reg[92]\ => \not_strict_mode.app_rd_data_reg[92]\,
      \not_strict_mode.app_rd_data_reg[93]\ => \not_strict_mode.app_rd_data_reg[93]\,
      \not_strict_mode.app_rd_data_reg[94]\ => \not_strict_mode.app_rd_data_reg[94]\,
      \not_strict_mode.app_rd_data_reg[95]\ => \not_strict_mode.app_rd_data_reg[95]\,
      \not_strict_mode.app_rd_data_reg[96]\ => \not_strict_mode.app_rd_data_reg[96]\,
      \not_strict_mode.app_rd_data_reg[97]\ => \not_strict_mode.app_rd_data_reg[97]\,
      \not_strict_mode.app_rd_data_reg[98]\ => \not_strict_mode.app_rd_data_reg[98]\,
      \not_strict_mode.app_rd_data_reg[99]\ => \not_strict_mode.app_rd_data_reg[99]\,
      \not_strict_mode.app_rd_data_reg[9]\ => \not_strict_mode.app_rd_data_reg[9]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \not_strict_mode.rd_buf_we\,
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\ => \not_strict_mode.status_ram.rd_buf_we_r1_reg\,
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofifo_rst_reg => A_rst_primitives,
      ofifo_rst_reg0 => ofifo_rst_reg0,
      ofifo_rst_reg0_11 => ofifo_rst_reg0_11,
      ofifo_rst_reg0_13 => ofifo_rst_reg0_13,
      ofifo_rst_reg0_15 => ofifo_rst_reg0_15,
      \out\ => \out\,
      out_dqs_0 => out_dqs_0,
      out_dqs_1 => out_dqs_1,
      out_dqs_2 => out_dqs_2,
      out_dqs_3 => out_dqs_3,
      out_dqs_4 => out_dqs_4,
      out_dqs_5 => out_dqs_5,
      out_dqs_6 => out_dqs_6,
      out_dqs_7 => out_dqs_7,
      p_0_out => p_0_out,
      p_110_in => p_110_in,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_ctl_wr_i2 => phy_ctl_wr_i2,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(10 downto 0) => phy_dout(10 downto 0),
      phy_if_reset => phy_if_reset,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      phy_mc_go => phy_mc_go,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_dqs_found_lanes(7 downto 0) => pi_dqs_found_lanes(7 downto 0),
      \pi_dqs_found_lanes_r1_reg[10]\ => A_rst_primitives_4,
      pi_phase_locked_all_r1_reg => pi_phase_locked_all_r1_reg,
      \pi_rdval_cnt_reg[0]\ => \pi_rdval_cnt_reg[0]\,
      \pi_rdval_cnt_reg[1]\ => \pi_rdval_cnt_reg[1]\,
      \pi_rdval_cnt_reg[2]\ => \pi_rdval_cnt_reg[2]\,
      \pi_rdval_cnt_reg[3]\ => \pi_rdval_cnt_reg[3]\,
      \pi_rdval_cnt_reg[4]\ => \pi_rdval_cnt_reg[4]\,
      \pi_rdval_cnt_reg[5]\ => \pi_rdval_cnt_reg[5]\,
      \pi_rst_stg1_cal_reg[0]\ => \pi_rst_stg1_cal_reg[0]\,
      \pi_rst_stg1_cal_reg[2]\ => \pi_rst_stg1_cal_reg[2]\,
      pi_stg2_load_reg => pi_stg2_load_reg,
      pi_stg2_load_reg_0 => pi_stg2_load_reg_0,
      \pi_stg2_reg_l_reg[5]\(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0),
      \pi_stg2_reg_l_reg[5]_0\(5 downto 0) => \pi_stg2_reg_l_reg[5]_0\(5 downto 0),
      pll_locked => pll_locked,
      \po_rdval_cnt_reg[0]\ => \po_rdval_cnt_reg[0]\,
      \po_rdval_cnt_reg[1]\ => \po_rdval_cnt_reg[1]\,
      \po_rdval_cnt_reg[2]\ => \po_rdval_cnt_reg[2]\,
      \po_rdval_cnt_reg[3]\ => \po_rdval_cnt_reg[3]\,
      \po_rdval_cnt_reg[4]\ => \po_rdval_cnt_reg[4]\,
      \po_rdval_cnt_reg[5]\ => \po_rdval_cnt_reg[5]\,
      \po_rdval_cnt_reg[6]\ => \po_rdval_cnt_reg[6]\,
      \po_rdval_cnt_reg[7]\ => \po_rdval_cnt_reg[7]\,
      \po_rdval_cnt_reg[8]\ => \po_rdval_cnt_reg[8]\,
      \po_stg2_wrcal_cnt_reg[2]\(2 downto 0) => \po_stg2_wrcal_cnt_reg[2]\(2 downto 0),
      ram_init_done_r => ram_init_done_r,
      \rd_mux_sel_r_reg[1]\(1 downto 0) => \rd_mux_sel_r_reg[1]\(1 downto 0),
      \rd_mux_sel_r_reg[2]\ => \rd_mux_sel_r_reg[2]\,
      \rd_ptr_timing_reg[0]\(44 downto 0) => \rd_ptr_timing_reg[0]\(44 downto 0),
      \rd_ptr_timing_reg[0]_0\(15 downto 0) => \rd_ptr_timing_reg[0]_0\(15 downto 0),
      \read_fifo.fifo_out_data_r_reg[6]\(0) => Q(0),
      \read_fifo.fifo_out_data_r_reg[6]_0\ => \read_fifo.fifo_out_data_r_reg[6]\,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\,
      rst_sync_r1_reg => rst_sync_r1_reg,
      store_sr_req_r_reg => store_sr_req_r_reg,
      sync_pulse => sync_pulse,
      sys_rst => sys_rst,
      sys_rst_0 => sys_rst_0,
      tempmon_pi_f_en_r_reg => tempmon_pi_f_en_r_reg,
      tempmon_pi_f_en_r_reg_0 => tempmon_pi_f_en_r_reg_0,
      tempmon_pi_f_en_r_reg_1 => tempmon_pi_f_en_r_reg_1,
      tempmon_pi_f_en_r_reg_2 => tempmon_pi_f_en_r_reg_2,
      tempmon_pi_f_en_r_reg_3 => tempmon_pi_f_en_r_reg_3,
      tempmon_pi_f_en_r_reg_4 => tempmon_pi_f_en_r_reg_4,
      tempmon_pi_f_en_r_reg_5 => tempmon_pi_f_en_r_reg_5,
      tempmon_pi_f_en_r_reg_6 => tempmon_pi_f_en_r_reg_6,
      tempmon_pi_f_inc_r_reg => tempmon_pi_f_inc_r_reg,
      tempmon_pi_f_inc_r_reg_0 => tempmon_pi_f_inc_r_reg_0,
      tempmon_pi_f_inc_r_reg_1 => tempmon_pi_f_inc_r_reg_1,
      tempmon_pi_f_inc_r_reg_2 => tempmon_pi_f_inc_r_reg_2,
      tempmon_pi_f_inc_r_reg_3 => tempmon_pi_f_inc_r_reg_3,
      tempmon_pi_f_inc_r_reg_4 => tempmon_pi_f_inc_r_reg_4,
      tempmon_pi_f_inc_r_reg_5 => tempmon_pi_f_inc_r_reg_5,
      tempmon_pi_f_inc_r_reg_6 => tempmon_pi_f_inc_r_reg_6,
      ts_dqs_0 => ts_dqs_0,
      ts_dqs_1 => ts_dqs_1,
      ts_dqs_2 => ts_dqs_2,
      ts_dqs_3 => ts_dqs_3,
      ts_dqs_4 => ts_dqs_4,
      ts_dqs_5 => ts_dqs_5,
      ts_dqs_6 => ts_dqs_6,
      ts_dqs_7 => ts_dqs_7,
      \write_buffer.wr_buf_out_data_reg[383]\(95 downto 0) => \write_buffer.wr_buf_out_data_reg[383]\(95 downto 0),
      \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[449]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[449]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[450]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[450]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[451]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[451]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[453]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[453]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[454]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[454]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[455]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[455]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[457]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[457]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[458]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[458]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[459]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[459]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[461]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[461]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[462]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[462]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[463]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[463]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[465]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[465]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[466]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[466]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[467]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[467]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[469]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[469]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[470]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[470]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[471]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[471]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[473]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[473]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[474]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[474]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[475]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[475]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[477]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[477]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[478]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[478]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[479]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[479]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[481]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[481]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[482]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[482]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[483]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[483]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[485]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[485]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[486]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[486]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[487]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[487]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[489]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[489]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[490]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[490]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[491]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[491]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[493]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[493]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[494]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[494]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[495]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[495]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[497]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[497]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[498]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[498]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[499]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[499]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[501]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[501]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[502]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[502]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[503]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[503]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[505]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[505]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[506]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[506]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[507]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[507]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[509]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[509]\(5 downto 0),
      \write_buffer.wr_buf_out_data_reg[510]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[510]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[511]\(4 downto 0) => \write_buffer.wr_buf_out_data_reg[511]\(4 downto 0),
      \write_buffer.wr_buf_out_data_reg[575]\(223 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(223 downto 0)
    );
u_ras_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(72),
      O => ddr3_ras_n
    );
u_we_n_obuf: unisim.vcomponents.OBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => mem_dq_out(70),
      O => ddr3_we_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_mc is
  port (
    accept_ns : out STD_LOGIC;
    sent_col : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    mc_cmd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    tempmon_sample_en : out STD_LOGIC;
    mc_ras_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    mc_wrdata_en : out STD_LOGIC;
    mc_cas_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    idle : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    \cmd_pipe_plus.mc_odt_reg[0]_0\ : out STD_LOGIC;
    \read_fifo.tail_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \not_strict_mode.bypass__0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_address_reg[41]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[8]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cmd_pipe_plus.mc_bank_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rd_ptr_timing_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_ptr_timing_reg[0]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pointer_ram.pointer_we\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_end_ns\ : out STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mc_address : out STD_LOGIC_VECTOR ( 38 downto 0 );
    mc_bank : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \phy_ctl_wd_i1_reg[20]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \phy_ctl_wd_i1_reg[22]\ : out STD_LOGIC;
    \phy_ctl_wd_i1_reg[21]\ : out STD_LOGIC;
    \phy_ctl_wd_i1_reg[19]\ : out STD_LOGIC;
    \phy_ctl_wd_i1_reg[18]\ : out STD_LOGIC;
    \phy_ctl_wd_i1_reg[17]\ : out STD_LOGIC;
    \data_offset_1_i1_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_1_i1_reg[5]\ : out STD_LOGIC;
    \data_offset_1_i1_reg[4]\ : out STD_LOGIC;
    \data_offset_1_i1_reg[2]\ : out STD_LOGIC;
    \data_offset_1_i1_reg[1]\ : out STD_LOGIC;
    \data_offset_1_i1_reg[0]\ : out STD_LOGIC;
    \data_offset_2_i1_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \data_offset_2_i1_reg[5]\ : out STD_LOGIC;
    \data_offset_2_i1_reg[4]\ : out STD_LOGIC;
    \data_offset_2_i1_reg[2]\ : out STD_LOGIC;
    \data_offset_2_i1_reg[1]\ : out STD_LOGIC;
    \data_offset_2_i1_reg[0]\ : out STD_LOGIC;
    CLK : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    of_ctl_full_v : in STD_LOGIC_VECTOR ( 0 to 0 );
    phy_mc_ctl_full : in STD_LOGIC;
    in0 : in STD_LOGIC;
    \maint_prescaler.maint_prescaler_r1\ : in STD_LOGIC;
    \init_calib_complete_reg_rep__12\ : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_sr_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_bank_r_lcl_reg[0]\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[0]_0\ : in STD_LOGIC;
    ram_init_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bm_end_r1_reg : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_mc_data_full : in STD_LOGIC;
    \init_calib_complete_reg_rep__26\ : in STD_LOGIC;
    ram_init_done_r : in STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_buf_indx.rd_buf_indx_r_reg[4]\ : in STD_LOGIC;
    app_rdy_r_reg : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \read_fifo.tail_r_reg[0]\ : in STD_LOGIC;
    granted_col_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4]\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\ : in STD_LOGIC;
    granted_col_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10]\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0\ : in STD_LOGIC;
    granted_col_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16]\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\ : in STD_LOGIC;
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_mc : entity is "mig_7series_v2_3_mc";
end mig_7series_0_mig_7series_v2_3_mc;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_mc is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal accept_internal_r : STD_LOGIC;
  signal \^app_sr_active\ : STD_LOGIC;
  signal \arb_mux0/arb_row_col0/col_arb0/last_master_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \arb_mux0/arb_select0/cke_r\ : STD_LOGIC;
  signal \arb_mux0/cs_en2\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/q_has_priority\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[0].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/pass_open_bank_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/q_has_priority\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[1].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/bank_state0/override_demand_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/q_has_priority\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[2].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_state0/col_wait_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_state0/demand_priority_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/bank_state0/demanded_prior_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/q_has_priority\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/q_has_rd\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/tail_r\ : STD_LOGIC;
  signal \bank_cntrl[3].bank0/wait_for_maint_r\ : STD_LOGIC;
  signal \bank_common0/maint_controller.maint_hit_busies_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \bank_common0/periodic_rd_cntr_r\ : STD_LOGIC;
  signal \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal bank_mach0_n_100 : STD_LOGIC;
  signal bank_mach0_n_101 : STD_LOGIC;
  signal bank_mach0_n_102 : STD_LOGIC;
  signal bank_mach0_n_103 : STD_LOGIC;
  signal bank_mach0_n_104 : STD_LOGIC;
  signal bank_mach0_n_105 : STD_LOGIC;
  signal bank_mach0_n_106 : STD_LOGIC;
  signal bank_mach0_n_107 : STD_LOGIC;
  signal bank_mach0_n_108 : STD_LOGIC;
  signal bank_mach0_n_109 : STD_LOGIC;
  signal bank_mach0_n_110 : STD_LOGIC;
  signal bank_mach0_n_111 : STD_LOGIC;
  signal bank_mach0_n_112 : STD_LOGIC;
  signal bank_mach0_n_113 : STD_LOGIC;
  signal bank_mach0_n_115 : STD_LOGIC;
  signal bank_mach0_n_116 : STD_LOGIC;
  signal bank_mach0_n_117 : STD_LOGIC;
  signal bank_mach0_n_118 : STD_LOGIC;
  signal bank_mach0_n_119 : STD_LOGIC;
  signal bank_mach0_n_120 : STD_LOGIC;
  signal bank_mach0_n_121 : STD_LOGIC;
  signal bank_mach0_n_122 : STD_LOGIC;
  signal bank_mach0_n_123 : STD_LOGIC;
  signal bank_mach0_n_124 : STD_LOGIC;
  signal bank_mach0_n_125 : STD_LOGIC;
  signal bank_mach0_n_126 : STD_LOGIC;
  signal bank_mach0_n_127 : STD_LOGIC;
  signal bank_mach0_n_128 : STD_LOGIC;
  signal bank_mach0_n_129 : STD_LOGIC;
  signal bank_mach0_n_130 : STD_LOGIC;
  signal bank_mach0_n_131 : STD_LOGIC;
  signal bank_mach0_n_132 : STD_LOGIC;
  signal bank_mach0_n_133 : STD_LOGIC;
  signal bank_mach0_n_134 : STD_LOGIC;
  signal bank_mach0_n_135 : STD_LOGIC;
  signal bank_mach0_n_136 : STD_LOGIC;
  signal bank_mach0_n_137 : STD_LOGIC;
  signal bank_mach0_n_197 : STD_LOGIC;
  signal bank_mach0_n_198 : STD_LOGIC;
  signal bank_mach0_n_199 : STD_LOGIC;
  signal bank_mach0_n_2 : STD_LOGIC;
  signal bank_mach0_n_200 : STD_LOGIC;
  signal bank_mach0_n_201 : STD_LOGIC;
  signal bank_mach0_n_203 : STD_LOGIC;
  signal bank_mach0_n_204 : STD_LOGIC;
  signal bank_mach0_n_205 : STD_LOGIC;
  signal bank_mach0_n_206 : STD_LOGIC;
  signal bank_mach0_n_207 : STD_LOGIC;
  signal bank_mach0_n_209 : STD_LOGIC;
  signal bank_mach0_n_214 : STD_LOGIC;
  signal bank_mach0_n_224 : STD_LOGIC;
  signal bank_mach0_n_225 : STD_LOGIC;
  signal bank_mach0_n_226 : STD_LOGIC;
  signal bank_mach0_n_227 : STD_LOGIC;
  signal bank_mach0_n_228 : STD_LOGIC;
  signal bank_mach0_n_229 : STD_LOGIC;
  signal bank_mach0_n_230 : STD_LOGIC;
  signal bank_mach0_n_231 : STD_LOGIC;
  signal bank_mach0_n_232 : STD_LOGIC;
  signal bank_mach0_n_233 : STD_LOGIC;
  signal bank_mach0_n_234 : STD_LOGIC;
  signal bank_mach0_n_235 : STD_LOGIC;
  signal bank_mach0_n_81 : STD_LOGIC;
  signal bank_mach0_n_83 : STD_LOGIC;
  signal bank_mach0_n_84 : STD_LOGIC;
  signal bank_mach0_n_85 : STD_LOGIC;
  signal bank_mach0_n_86 : STD_LOGIC;
  signal bank_mach0_n_87 : STD_LOGIC;
  signal bank_mach0_n_88 : STD_LOGIC;
  signal bank_mach0_n_95 : STD_LOGIC;
  signal bank_mach0_n_96 : STD_LOGIC;
  signal \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\ : STD_LOGIC;
  signal \^cmd_pipe_plus.mc_odt_reg[0]_0\ : STD_LOGIC;
  signal col_data_buf_addr : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal col_mach0_n_17 : STD_LOGIC;
  signal col_mach0_n_22 : STD_LOGIC;
  signal col_periodic_rd : STD_LOGIC;
  signal col_rd_wr : STD_LOGIC;
  signal col_rd_wr_r1 : STD_LOGIC;
  signal col_rd_wr_r2 : STD_LOGIC;
  signal \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal head_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \i___0_n_0\ : STD_LOGIC;
  signal \i___10_n_0\ : STD_LOGIC;
  signal \i___11_n_0\ : STD_LOGIC;
  signal \i___12_n_0\ : STD_LOGIC;
  signal \i___13_n_0\ : STD_LOGIC;
  signal \i___14_n_0\ : STD_LOGIC;
  signal \i___15_n_0\ : STD_LOGIC;
  signal \i___16_n_0\ : STD_LOGIC;
  signal \i___17_n_0\ : STD_LOGIC;
  signal \i___18_n_0\ : STD_LOGIC;
  signal \i___19_n_0\ : STD_LOGIC;
  signal \i___1_n_0\ : STD_LOGIC;
  signal \i___20_n_0\ : STD_LOGIC;
  signal \i___21_n_0\ : STD_LOGIC;
  signal \i___22_n_0\ : STD_LOGIC;
  signal \i___23_n_0\ : STD_LOGIC;
  signal \i___24_n_0\ : STD_LOGIC;
  signal \i___25_n_0\ : STD_LOGIC;
  signal \i___26_n_0\ : STD_LOGIC;
  signal \i___27_n_0\ : STD_LOGIC;
  signal \i___28_n_0\ : STD_LOGIC;
  signal \i___29_n_0\ : STD_LOGIC;
  signal \i___2_n_0\ : STD_LOGIC;
  signal \i___30_n_0\ : STD_LOGIC;
  signal \i___31_n_0\ : STD_LOGIC;
  signal \i___32_n_0\ : STD_LOGIC;
  signal \i___33_n_0\ : STD_LOGIC;
  signal \i___34_n_0\ : STD_LOGIC;
  signal \i___35_n_0\ : STD_LOGIC;
  signal \i___36_n_0\ : STD_LOGIC;
  signal \i___37_n_0\ : STD_LOGIC;
  signal \i___38_n_0\ : STD_LOGIC;
  signal \i___39_n_0\ : STD_LOGIC;
  signal \i___3_n_0\ : STD_LOGIC;
  signal \i___40_n_0\ : STD_LOGIC;
  signal \i___41_n_0\ : STD_LOGIC;
  signal \i___42_n_0\ : STD_LOGIC;
  signal \i___43_n_0\ : STD_LOGIC;
  signal \i___44_n_0\ : STD_LOGIC;
  signal \i___45_n_0\ : STD_LOGIC;
  signal \i___46_n_0\ : STD_LOGIC;
  signal \i___47_n_0\ : STD_LOGIC;
  signal \i___48_n_0\ : STD_LOGIC;
  signal \i___49_n_0\ : STD_LOGIC;
  signal \i___4_n_0\ : STD_LOGIC;
  signal \i___50_n_0\ : STD_LOGIC;
  signal \i___51_n_0\ : STD_LOGIC;
  signal \i___52_n_0\ : STD_LOGIC;
  signal \i___53_n_0\ : STD_LOGIC;
  signal \i___54_n_0\ : STD_LOGIC;
  signal \i___55_n_0\ : STD_LOGIC;
  signal \i___56_n_0\ : STD_LOGIC;
  signal \i___57_n_0\ : STD_LOGIC;
  signal \i___58_n_0\ : STD_LOGIC;
  signal \i___59_n_0\ : STD_LOGIC;
  signal \i___5_n_0\ : STD_LOGIC;
  signal \i___60_n_0\ : STD_LOGIC;
  signal \i___61_n_0\ : STD_LOGIC;
  signal \i___62_n_0\ : STD_LOGIC;
  signal \i___63_n_0\ : STD_LOGIC;
  signal \i___64_n_0\ : STD_LOGIC;
  signal \i___65_n_0\ : STD_LOGIC;
  signal \i___66_n_0\ : STD_LOGIC;
  signal \i___67_n_0\ : STD_LOGIC;
  signal \i___68_n_0\ : STD_LOGIC;
  signal \i___69_n_0\ : STD_LOGIC;
  signal \i___6_n_0\ : STD_LOGIC;
  signal \i___70_n_0\ : STD_LOGIC;
  signal \i___71_n_0\ : STD_LOGIC;
  signal \i___72_n_0\ : STD_LOGIC;
  signal \i___73_n_0\ : STD_LOGIC;
  signal \i___74_n_0\ : STD_LOGIC;
  signal \i___75_n_0\ : STD_LOGIC;
  signal \i___76_n_0\ : STD_LOGIC;
  signal \i___77_n_0\ : STD_LOGIC;
  signal \i___78_n_0\ : STD_LOGIC;
  signal \i___79_n_0\ : STD_LOGIC;
  signal \i___7_n_0\ : STD_LOGIC;
  signal \i___80_n_0\ : STD_LOGIC;
  signal \i___81_n_0\ : STD_LOGIC;
  signal \i___82_n_0\ : STD_LOGIC;
  signal \i___83_n_0\ : STD_LOGIC;
  signal \i___84_n_0\ : STD_LOGIC;
  signal \i___85_n_0\ : STD_LOGIC;
  signal \i___86_n_0\ : STD_LOGIC;
  signal \i___87_n_0\ : STD_LOGIC;
  signal \i___88_n_0\ : STD_LOGIC;
  signal \i___89_n_0\ : STD_LOGIC;
  signal \i___8_n_0\ : STD_LOGIC;
  signal \i___90_n_0\ : STD_LOGIC;
  signal \i___91_n_0\ : STD_LOGIC;
  signal \i___92_n_0\ : STD_LOGIC;
  signal \i___93_n_0\ : STD_LOGIC;
  signal \i___94_n_0\ : STD_LOGIC;
  signal \i___95_n_0\ : STD_LOGIC;
  signal \i___96_n_0\ : STD_LOGIC;
  signal \i___9_n_0\ : STD_LOGIC;
  signal idle_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \inhbt_act_faw.faw_cnt_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal inhbt_act_faw_r : STD_LOGIC;
  signal insert_maint_r : STD_LOGIC;
  signal insert_maint_r1 : STD_LOGIC;
  signal maint_prescaler_tick_r : STD_LOGIC;
  signal maint_ref_zq_wip : STD_LOGIC;
  signal maint_req_r : STD_LOGIC;
  signal maint_sre_r : STD_LOGIC;
  signal maint_srx_r : STD_LOGIC;
  signal maint_wip_r : STD_LOGIC;
  signal maint_zq_r : STD_LOGIC;
  signal mc_address_ns : STD_LOGIC_VECTOR ( 41 downto 0 );
  signal mc_bank_ns : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^mc_cas_n\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cas_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cke_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^mc_cmd\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal mc_cmd_ns : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^mc_cs_n\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_cs_n_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_odt_ns : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^mc_ras_n\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_ras_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_ref_zq_wip_ns : STD_LOGIC;
  signal mc_we_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal p_13_out : STD_LOGIC;
  signal p_52_out : STD_LOGIC;
  signal periodic_rd_ack_r : STD_LOGIC;
  signal periodic_rd_r : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/act_this_rank\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.int_read_this_rank\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\ : STD_LOGIC;
  signal \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\ : STD_LOGIC;
  signal \rank_common0/app_ref_r\ : STD_LOGIC;
  signal \rank_common0/app_zq_r\ : STD_LOGIC;
  signal \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \rank_common0/maintenance_request.maint_arb0/last_master_r\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \rank_common0/maintenance_request.maint_grant_r\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \rank_common0/maintenance_request.upd_last_master_r\ : STD_LOGIC;
  signal \rank_common0/periodic_read_request.periodic_rd_grant_r\ : STD_LOGIC;
  signal \rank_common0/periodic_read_request.periodic_rd_r_cnt\ : STD_LOGIC;
  signal \rank_common0/periodic_read_request.upd_last_master_r\ : STD_LOGIC;
  signal \rank_common0/refresh_timer.refresh_timer_r_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rank_common0/sr_cntrl.sre_request_logic.sre_request_r\ : STD_LOGIC;
  signal \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\ : STD_LOGIC;
  signal rank_mach0_n_32 : STD_LOGIC;
  signal rank_mach0_n_35 : STD_LOGIC;
  signal rank_mach0_n_38 : STD_LOGIC;
  signal rank_mach0_n_39 : STD_LOGIC;
  signal rank_mach0_n_40 : STD_LOGIC;
  signal rank_mach0_n_41 : STD_LOGIC;
  signal rank_mach0_n_42 : STD_LOGIC;
  signal rank_mach0_n_43 : STD_LOGIC;
  signal rank_mach0_n_44 : STD_LOGIC;
  signal rank_mach0_n_45 : STD_LOGIC;
  signal rank_mach0_n_46 : STD_LOGIC;
  signal rank_mach0_n_47 : STD_LOGIC;
  signal rank_mach0_n_48 : STD_LOGIC;
  signal rank_mach0_n_49 : STD_LOGIC;
  signal rank_mach0_n_50 : STD_LOGIC;
  signal rank_mach0_n_51 : STD_LOGIC;
  signal rank_mach0_n_52 : STD_LOGIC;
  signal rank_mach0_n_53 : STD_LOGIC;
  signal rank_mach0_n_54 : STD_LOGIC;
  signal rank_mach0_n_55 : STD_LOGIC;
  signal rank_mach0_n_56 : STD_LOGIC;
  signal rank_mach0_n_57 : STD_LOGIC;
  signal rank_mach0_n_59 : STD_LOGIC;
  signal rb_hit_busy_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rd_ptr_timing_reg[0]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rd_wr_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \^read_fifo.tail_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal req_wr_r : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rnk_config_valid_r : STD_LOGIC;
  signal row_cmd_wr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_col : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sending_pre : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sending_row : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^sent_col\ : STD_LOGIC;
  signal sent_col_r2 : STD_LOGIC;
  signal sent_row : STD_LOGIC;
  signal was_priority : STD_LOGIC;
  signal was_wr : STD_LOGIC;
  signal \wtr_timer.wtr_cnt_r\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute syn_maxfan : string;
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[0]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[1]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[2]\ : label is "30";
  attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[3]\ : label is "30";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i___11\ : label is "soft_lutpair1026";
  attribute SOFT_HLUTNM of \i___19\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \i___20\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \i___26\ : label is "soft_lutpair1021";
  attribute SOFT_HLUTNM of \i___27\ : label is "soft_lutpair1021";
  attribute SOFT_HLUTNM of \i___53\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \i___54\ : label is "soft_lutpair1024";
  attribute SOFT_HLUTNM of \i___55\ : label is "soft_lutpair1024";
  attribute SOFT_HLUTNM of \i___56\ : label is "soft_lutpair1018";
  attribute SOFT_HLUTNM of \i___57\ : label is "soft_lutpair1018";
  attribute SOFT_HLUTNM of \i___62\ : label is "soft_lutpair1022";
  attribute SOFT_HLUTNM of \i___63\ : label is "soft_lutpair1022";
  attribute SOFT_HLUTNM of \i___65\ : label is "soft_lutpair1026";
  attribute SOFT_HLUTNM of \i___67\ : label is "soft_lutpair1019";
  attribute SOFT_HLUTNM of \i___68\ : label is "soft_lutpair1019";
  attribute SOFT_HLUTNM of \i___72\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \i___76\ : label is "soft_lutpair1017";
  attribute SOFT_HLUTNM of \i___77\ : label is "soft_lutpair1017";
  attribute SOFT_HLUTNM of \i___79\ : label is "soft_lutpair1025";
  attribute SOFT_HLUTNM of \i___8\ : label is "soft_lutpair1020";
  attribute SOFT_HLUTNM of \i___80\ : label is "soft_lutpair1025";
  attribute SOFT_HLUTNM of \i___9\ : label is "soft_lutpair1020";
begin
  E(0) <= \^e\(0);
  app_sr_active <= \^app_sr_active\;
  \cmd_pipe_plus.mc_odt_reg[0]_0\ <= \^cmd_pipe_plus.mc_odt_reg[0]_0\;
  mc_cas_n(2 downto 0) <= \^mc_cas_n\(2 downto 0);
  mc_cmd(1 downto 0) <= \^mc_cmd\(1 downto 0);
  mc_cs_n(0) <= \^mc_cs_n\(0);
  mc_ras_n(2 downto 0) <= \^mc_ras_n\(2 downto 0);
  \rd_ptr_timing_reg[0]_0\(2 downto 0) <= \^rd_ptr_timing_reg[0]_0\(2 downto 0);
  \read_fifo.tail_r_reg[1]\(0) <= \^read_fifo.tail_r_reg[1]\(0);
  sent_col <= \^sent_col\;
bank_mach0: entity work.mig_7series_0_mig_7series_v2_3_bank_mach
     port map (
      CLK => CLK,
      D(0) => bank_mach0_n_96,
      DIC(0) => col_periodic_rd,
      E(0) => mc_cmd_ns(1),
      Q(3 downto 0) => sending_col(3 downto 0),
      S(0) => S(0),
      SR(0) => SR(0),
      accept_internal_r => accept_internal_r,
      accept_internal_r_reg => bank_mach0_n_87,
      accept_ns => accept_ns,
      accept_r_reg => \i___62_n_0\,
      accept_r_reg_0 => \i___63_n_0\,
      act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      act_wait_r_lcl_reg => bank_mach0_n_88,
      act_wait_r_lcl_reg_0 => bank_mach0_n_104,
      act_wait_r_lcl_reg_1 => bank_mach0_n_105,
      act_wait_r_lcl_reg_2 => bank_mach0_n_106,
      act_wait_r_lcl_reg_3 => bank_mach0_n_131,
      act_wait_r_lcl_reg_4 => bank_mach0_n_132,
      act_wait_r_lcl_reg_5 => bank_mach0_n_133,
      act_wait_r_lcl_reg_6 => \i___59_n_0\,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]\(0),
      \app_addr_r1_reg[23]_0\(0) => \app_addr_r1_reg[23]_0\(0),
      \app_addr_r1_reg[23]_1\(0) => \app_addr_r1_reg[23]_1\(0),
      \app_addr_r1_reg[23]_2\(13 downto 0) => D(13 downto 0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      app_rdy_r_reg => app_rdy_r_reg,
      auto_pre_r_lcl_reg => bank_mach0_n_115,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_1 => bm_end_r1_1,
      bm_end_r1_reg => bm_end_r1_reg,
      bm_end_r1_reg_0 => bm_end_r1_reg_0,
      bm_end_r1_reg_1 => bm_end_r1_reg_1,
      bm_end_r1_reg_2 => bm_end_r1_reg_2,
      cke_r => \arb_mux0/arb_select0/cke_r\,
      cmd(1 downto 0) => cmd(1 downto 0),
      \cmd_pipe_plus.mc_address_reg[28]\(0) => sending_pre(3),
      \cmd_pipe_plus.mc_address_reg[28]_0\ => bank_mach0_n_235,
      \cmd_pipe_plus.mc_address_reg[29]\ => bank_mach0_n_234,
      \cmd_pipe_plus.mc_address_reg[30]\ => bank_mach0_n_233,
      \cmd_pipe_plus.mc_address_reg[32]\ => bank_mach0_n_232,
      \cmd_pipe_plus.mc_address_reg[34]\ => bank_mach0_n_231,
      \cmd_pipe_plus.mc_address_reg[35]\ => bank_mach0_n_230,
      \cmd_pipe_plus.mc_address_reg[36]\ => bank_mach0_n_229,
      \cmd_pipe_plus.mc_address_reg[39]\ => bank_mach0_n_228,
      \cmd_pipe_plus.mc_address_reg[40]\ => bank_mach0_n_227,
      \cmd_pipe_plus.mc_address_reg[41]\(29) => mc_address_ns(41),
      \cmd_pipe_plus.mc_address_reg[41]\(28 downto 27) => mc_address_ns(38 downto 37),
      \cmd_pipe_plus.mc_address_reg[41]\(26) => mc_address_ns(33),
      \cmd_pipe_plus.mc_address_reg[41]\(25) => mc_address_ns(31),
      \cmd_pipe_plus.mc_address_reg[41]\(24 downto 0) => mc_address_ns(24 downto 0),
      \cmd_pipe_plus.mc_address_reg[41]_0\(10 downto 0) => \cmd_pipe_plus.mc_address_reg[41]_0\(10 downto 0),
      \cmd_pipe_plus.mc_aux_out0_reg[1]\ => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\,
      \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[5]\(5 downto 0) => mc_bank_ns(5 downto 0),
      \cmd_pipe_plus.mc_bank_reg[6]\ => bank_mach0_n_226,
      \cmd_pipe_plus.mc_bank_reg[7]\ => bank_mach0_n_225,
      \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[8]_0\ => bank_mach0_n_224,
      \cmd_pipe_plus.mc_cmd_reg[0]\ => \^sent_col\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => bank_mach0_n_81,
      \cmd_pipe_plus.mc_odt_reg[0]\ => \^cmd_pipe_plus.mc_odt_reg[0]_0\,
      \cmd_pipe_plus.mc_we_n_reg[1]\ => bank_mach0_n_100,
      \cmd_pipe_plus.mc_we_n_reg[2]\(1) => mc_we_n_ns(2),
      \cmd_pipe_plus.mc_we_n_reg[2]\(0) => mc_we_n_ns(0),
      col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0),
      col_rd_wr => col_rd_wr,
      col_wait_r => \bank_cntrl[0].bank0/bank_state0/col_wait_r\,
      col_wait_r_0 => \bank_cntrl[1].bank0/bank_state0/col_wait_r\,
      col_wait_r_11 => \bank_cntrl[3].bank0/bank_state0/col_wait_r\,
      col_wait_r_6 => \bank_cntrl[2].bank0/bank_state0/col_wait_r\,
      col_wait_r_reg => \i___22_n_0\,
      col_wait_r_reg_0 => \i___43_n_0\,
      col_wait_r_reg_1 => \i___25_n_0\,
      col_wait_r_reg_2 => \i___24_n_0\,
      col_wait_r_reg_3 => \i___42_n_0\,
      col_wait_r_reg_4 => \i___23_n_0\,
      \compute_tail.tail_r_lcl_reg\ => bank_mach0_n_122,
      cs_en2 => \arb_mux0/cs_en2\,
      \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(3 downto 0),
      demand_priority_r => \bank_cntrl[0].bank0/bank_state0/demand_priority_r\,
      demand_priority_r_1 => \bank_cntrl[1].bank0/bank_state0/demand_priority_r\,
      demand_priority_r_12 => \bank_cntrl[3].bank0/bank_state0/demand_priority_r\,
      demand_priority_r_7 => \bank_cntrl[2].bank0/bank_state0/demand_priority_r\,
      demanded_prior_r => \bank_cntrl[1].bank0/bank_state0/demanded_prior_r\,
      demanded_prior_r_13 => \bank_cntrl[3].bank0/bank_state0/demanded_prior_r\,
      demanded_prior_r_8 => \bank_cntrl[2].bank0/bank_state0/demanded_prior_r\,
      demanded_prior_r_reg => bank_mach0_n_204,
      demanded_prior_r_reg_0 => bank_mach0_n_205,
      \generate_maint_cmds.insert_maint_r_lcl_reg\(1) => \i___66_n_0\,
      \generate_maint_cmds.insert_maint_r_lcl_reg\(0) => \i___78_n_0\,
      \grant_r_reg[0]\ => bank_mach0_n_198,
      \grant_r_reg[1]\ => bank_mach0_n_135,
      \grant_r_reg[1]_0\ => \i___69_n_0\,
      \grant_r_reg[3]\ => bank_mach0_n_134,
      \grant_r_reg[3]_0\ => bank_mach0_n_203,
      \grant_r_reg[3]_1\ => \i___83_n_0\,
      granted_row_r_reg => \i___57_n_0\,
      granted_row_r_reg_0 => \i___56_n_0\,
      head_r(3 downto 0) => head_r(3 downto 0),
      head_r_lcl_reg => bank_mach0_n_110,
      head_r_lcl_reg_0 => bank_mach0_n_111,
      head_r_lcl_reg_1 => bank_mach0_n_116,
      head_r_lcl_reg_10 => \i___7_n_0\,
      head_r_lcl_reg_2 => bank_mach0_n_119,
      head_r_lcl_reg_3 => bank_mach0_n_120,
      head_r_lcl_reg_4 => bank_mach0_n_123,
      head_r_lcl_reg_5 => bank_mach0_n_126,
      head_r_lcl_reg_6 => bank_mach0_n_201,
      head_r_lcl_reg_7 => \i___1_n_0\,
      head_r_lcl_reg_8 => \i___3_n_0\,
      head_r_lcl_reg_9 => \i___5_n_0\,
      idle_r(3 downto 0) => idle_r(3 downto 0),
      idle_r_lcl_reg => \i___0_n_0\,
      idle_r_lcl_reg_0 => \i___2_n_0\,
      idle_r_lcl_reg_1 => \i___4_n_0\,
      idle_r_lcl_reg_2 => \i___6_n_0\,
      idle_r_lcl_reg_3 => \i___33_n_0\,
      idle_r_lcl_reg_4 => \i___61_n_0\,
      idle_r_lcl_reg_5 => \i___28_n_0\,
      idle_r_lcl_reg_6 => \i___45_n_0\,
      idle_r_lcl_reg_7 => \i___38_n_0\,
      inhbt_act_faw_r => inhbt_act_faw_r,
      \init_calib_complete_reg_rep__12\ => \init_calib_complete_reg_rep__12\,
      insert_maint_r => insert_maint_r,
      insert_maint_r1 => insert_maint_r1,
      \last_master_r_reg[0]\ => bank_mach0_n_95,
      \last_master_r_reg[1]\(0) => \arb_mux0/arb_row_col0/col_arb0/last_master_r\(1),
      \last_master_r_reg[3]\(3 downto 0) => sending_row(3 downto 0),
      \last_master_r_reg[3]_0\(0) => \arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r\(3),
      \last_master_r_reg[3]_1\ => \i___70_n_0\,
      \maint_controller.maint_hit_busies_r_reg[3]\(3 downto 0) => \bank_common0/maint_controller.maint_hit_busies_r\(3 downto 0),
      \maint_controller.maint_hit_busies_r_reg[3]_0\(3) => \i___39_n_0\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(2) => \i___36_n_0\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(1) => \i___29_n_0\,
      \maint_controller.maint_hit_busies_r_reg[3]_0\(0) => \i___41_n_0\,
      maint_req_r => maint_req_r,
      maint_sre_r => maint_sre_r,
      maint_srx_r => maint_srx_r,
      maint_wip_r => maint_wip_r,
      maint_zq_r => maint_zq_r,
      \maintenance_request.maint_req_r_lcl_reg\ => \i___64_n_0\,
      \maintenance_request.maint_srx_r_lcl_reg\ => \i___65_n_0\,
      mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0),
      mc_cke_ns(0) => mc_cke_ns(1),
      mc_cs_n_ns(0) => mc_cs_n_ns(0),
      mc_odt_ns(0) => mc_odt_ns(0),
      mc_ras_n_ns(1) => mc_ras_n_ns(2),
      mc_ras_n_ns(0) => mc_ras_n_ns(0),
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ordered_r_lcl_reg(2) => req_wr_r(3),
      ordered_r_lcl_reg(1 downto 0) => req_wr_r(1 downto 0),
      ordered_r_lcl_reg_0 => bank_mach0_n_108,
      ordered_r_lcl_reg_1 => bank_mach0_n_117,
      ordered_r_lcl_reg_2 => bank_mach0_n_125,
      override_demand_r => \bank_cntrl[2].bank0/bank_state0/override_demand_r\,
      override_demand_r_reg => \i___81_n_0\,
      override_demand_r_reg_0 => \i___82_n_0\,
      p_13_out => p_13_out,
      p_52_out => p_52_out,
      pass_open_bank_r => \bank_cntrl[0].bank0/pass_open_bank_r\,
      pass_open_bank_r_2 => \bank_cntrl[1].bank0/pass_open_bank_r\,
      pass_open_bank_r_lcl_reg => bank_mach0_n_127,
      pass_open_bank_r_lcl_reg_0 => bank_mach0_n_128,
      pass_open_bank_r_lcl_reg_1 => bank_mach0_n_136,
      pass_open_bank_r_lcl_reg_2 => bank_mach0_n_137,
      periodic_rd_ack_r => periodic_rd_ack_r,
      periodic_rd_ack_r_lcl_reg => \i___55_n_0\,
      periodic_rd_cntr_r => \bank_common0/periodic_rd_cntr_r\,
      \periodic_rd_generation.int_read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.int_read_this_rank\,
      \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_r_lcl_reg\ => \i___54_n_0\,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      pre_bm_end_r => \bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r\,
      pre_bm_end_r_3 => \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r\,
      pre_bm_end_r_reg => \i___26_n_0\,
      \q_entry_r_reg[0]\ => bank_mach0_n_85,
      \q_entry_r_reg[0]_0\ => bank_mach0_n_121,
      \q_entry_r_reg[0]_1\ => bank_mach0_n_124,
      \q_entry_r_reg[1]\ => bank_mach0_n_2,
      \q_entry_r_reg[1]_0\ => bank_mach0_n_109,
      \q_entry_r_reg[1]_1\ => bank_mach0_n_112,
      \q_entry_r_reg[1]_2\ => bank_mach0_n_113,
      \q_entry_r_reg[1]_3\ => bank_mach0_n_118,
      q_has_priority => \bank_cntrl[0].bank0/q_has_priority\,
      q_has_priority_10 => \bank_cntrl[2].bank0/q_has_priority\,
      q_has_priority_15 => \bank_cntrl[3].bank0/q_has_priority\,
      q_has_priority_5 => \bank_cntrl[1].bank0/q_has_priority\,
      q_has_priority_r_reg => \i___47_n_0\,
      q_has_priority_r_reg_0 => \i___31_n_0\,
      q_has_priority_r_reg_1 => \i___52_n_0\,
      q_has_priority_r_reg_2 => \i___50_n_0\,
      q_has_rd => \bank_cntrl[0].bank0/q_has_rd\,
      q_has_rd_14 => \bank_cntrl[3].bank0/q_has_rd\,
      q_has_rd_4 => \bank_cntrl[1].bank0/q_has_rd\,
      q_has_rd_9 => \bank_cntrl[2].bank0/q_has_rd\,
      q_has_rd_r_reg => \i___46_n_0\,
      q_has_rd_r_reg_0 => \i___30_n_0\,
      q_has_rd_r_reg_1 => \i___51_n_0\,
      q_has_rd_r_reg_2 => \i___49_n_0\,
      \ras_timer_r_reg[0]\ => bank_mach0_n_101,
      \ras_timer_r_reg[0]_0\ => bank_mach0_n_102,
      \ras_timer_r_reg[0]_1\ => bank_mach0_n_107,
      \ras_timer_r_reg[0]_2\ => bank_mach0_n_129,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      ras_timer_zero_r_reg_1 => bank_mach0_n_103,
      ras_timer_zero_r_reg_2 => bank_mach0_n_130,
      rb_hit_busy_r(3 downto 0) => rb_hit_busy_r(3 downto 0),
      rb_hit_busy_r_reg => bank_mach0_n_83,
      rb_hit_busy_r_reg_0 => bank_mach0_n_84,
      rb_hit_busy_r_reg_1 => bank_mach0_n_86,
      \rd_this_rank_r_reg[0]\(1 downto 0) => rd_wr_r(1 downto 0),
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]\,
      \req_bank_r_lcl_reg[0]_0\ => \req_bank_r_lcl_reg[0]_0\,
      \req_bank_r_lcl_reg[2]\ => \req_bank_r_lcl_reg[2]\,
      \req_row_r_lcl_reg[3]\(0) => \req_row_r_lcl_reg[3]\(0),
      req_wr_r_lcl_reg => \i___32_n_0\,
      req_wr_r_lcl_reg_0 => \i___48_n_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ => bank_mach0_n_209,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ => \i___80_n_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\(3 downto 0) => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3 downto 0),
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0\ => \i___79_n_0\,
      \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => bank_mach0_n_214,
      \rnk_config_strobe_r_reg[0]\ => bank_mach0_n_199,
      rnk_config_valid_r => rnk_config_valid_r,
      rnk_config_valid_r_lcl_reg => bank_mach0_n_200,
      rnk_config_valid_r_lcl_reg_0 => \i___60_n_0\,
      row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      sent_row => sent_row,
      \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\ => bank_mach0_n_197,
      tail_r => \bank_cntrl[0].bank0/tail_r\,
      tail_r_19 => \bank_cntrl[1].bank0/tail_r\,
      tail_r_20 => \bank_cntrl[2].bank0/tail_r\,
      tail_r_21 => \bank_cntrl[3].bank0/tail_r\,
      use_addr => use_addr,
      wait_for_maint_r => \bank_cntrl[0].bank0/wait_for_maint_r\,
      wait_for_maint_r_16 => \bank_cntrl[1].bank0/wait_for_maint_r\,
      wait_for_maint_r_17 => \bank_cntrl[2].bank0/wait_for_maint_r\,
      wait_for_maint_r_18 => \bank_cntrl[3].bank0/wait_for_maint_r\,
      wait_for_maint_r_lcl_reg => \i___40_n_0\,
      wait_for_maint_r_lcl_reg_0 => \i___34_n_0\,
      wait_for_maint_r_lcl_reg_1 => \i___35_n_0\,
      wait_for_maint_r_lcl_reg_2 => \i___37_n_0\,
      was_priority => was_priority,
      was_wr => was_wr,
      \wtr_timer.wtr_cnt_r_reg[0]\ => bank_mach0_n_206,
      \wtr_timer.wtr_cnt_r_reg[0]_0\ => bank_mach0_n_207,
      \wtr_timer.wtr_cnt_r_reg[1]\(0) => \wtr_timer.wtr_cnt_r\(1)
    );
\cmd_pipe_plus.mc_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(0),
      Q => mc_address(0),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(10),
      Q => mc_address(10),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(11),
      Q => mc_address(11),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(12),
      Q => mc_address(12),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(13),
      Q => mc_address(13),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(14),
      Q => mc_address(14),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(15),
      Q => mc_address(15),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(16),
      Q => mc_address(16),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(17),
      Q => mc_address(17),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(18),
      Q => mc_address(18),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(19),
      Q => mc_address(19),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(1),
      Q => mc_address(1),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(20),
      Q => mc_address(20),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(21),
      Q => mc_address(21),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(22),
      Q => mc_address(22),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(23),
      Q => mc_address(23),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(24),
      Q => mc_address(24),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[28]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_235,
      Q => mc_address(25),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[29]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_234,
      Q => mc_address(26),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(2),
      Q => mc_address(2),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[30]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_233,
      Q => mc_address(27),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(31),
      Q => mc_address(28),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[32]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_232,
      Q => mc_address(29),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(33),
      Q => mc_address(30),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[34]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_231,
      Q => mc_address(31),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[35]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_230,
      Q => mc_address(32),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[36]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_229,
      Q => mc_address(33),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(37),
      Q => mc_address(34),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(38),
      Q => mc_address(35),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[39]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_228,
      Q => mc_address(36),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(3),
      Q => mc_address(3),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[40]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_227,
      Q => mc_address(37),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_address_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(41),
      Q => mc_address(38),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(4),
      Q => mc_address(4),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(5),
      Q => mc_address(5),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(6),
      Q => mc_address(6),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(7),
      Q => mc_address(7),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(8),
      Q => mc_address(8),
      R => '0'
    );
\cmd_pipe_plus.mc_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_address_ns(9),
      Q => mc_address(9),
      R => '0'
    );
\cmd_pipe_plus.mc_aux_out0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___20_n_0\,
      Q => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\,
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(0),
      Q => mc_bank(0),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(1),
      Q => mc_bank(1),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(2),
      Q => mc_bank(2),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(3),
      Q => mc_bank(3),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(4),
      Q => mc_bank(4),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_bank_ns(5),
      Q => mc_bank(5),
      R => '0'
    );
\cmd_pipe_plus.mc_bank_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_226,
      Q => mc_bank(6),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_bank_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_225,
      Q => mc_bank(7),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_bank_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => bank_mach0_n_224,
      Q => mc_bank(8),
      S => mc_ras_n_ns(2)
    );
\cmd_pipe_plus.mc_cas_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cas_n_ns(0),
      Q => \^mc_cas_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cas_n_ns(1),
      Q => \^mc_cas_n\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_cas_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cas_n_ns(2),
      Q => \^mc_cas_n\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_cke_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cke_ns(1),
      Q => mc_cke(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cmd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \^sent_col\,
      Q => \^mc_cmd\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_cmd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cmd_ns(1),
      Q => \^mc_cmd\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_cs_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_cs_n_ns(0),
      Q => \^mc_cs_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0\,
      Q => \data_offset_1_i1_reg[0]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\,
      Q => \data_offset_1_i1_reg[1]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___89_n_0\,
      Q => \data_offset_1_i1_reg[2]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => granted_col_r_reg_0(0),
      Q => \data_offset_1_i1_reg[3]\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10]\,
      Q => \data_offset_1_i1_reg[4]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___90_n_0\,
      Q => \data_offset_1_i1_reg[5]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0\,
      Q => \data_offset_2_i1_reg[0]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\,
      Q => \data_offset_2_i1_reg[1]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___91_n_0\,
      Q => \data_offset_2_i1_reg[2]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => granted_col_r_reg_1(0),
      Q => \data_offset_2_i1_reg[3]\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16]\,
      Q => \data_offset_2_i1_reg[4]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___92_n_0\,
      Q => \data_offset_2_i1_reg[5]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\,
      Q => \phy_ctl_wd_i1_reg[17]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\,
      Q => \phy_ctl_wd_i1_reg[18]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___87_n_0\,
      Q => \phy_ctl_wd_i1_reg[19]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => granted_col_r_reg(0),
      Q => \phy_ctl_wd_i1_reg[20]\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_data_offset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4]\,
      Q => \phy_ctl_wd_i1_reg[21]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_data_offset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___88_n_0\,
      Q => \phy_ctl_wd_i1_reg[22]\,
      R => bank_mach0_n_81
    );
\cmd_pipe_plus.mc_odt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_odt_ns(0),
      Q => mc_odt(0),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_ras_n_ns(0),
      Q => \^mc_ras_n\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___21_n_0\,
      Q => \^mc_ras_n\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_ras_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_ras_n_ns(2),
      Q => \^mc_ras_n\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_we_n_ns(0),
      Q => \^rd_ptr_timing_reg[0]_0\(0),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___19_n_0\,
      Q => \^rd_ptr_timing_reg[0]_0\(1),
      R => '0'
    );
\cmd_pipe_plus.mc_we_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_we_n_ns(2),
      Q => \^rd_ptr_timing_reg[0]_0\(2),
      R => '0'
    );
\cmd_pipe_plus.mc_wrdata_en_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___93_n_0\,
      Q => mc_wrdata_en,
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(0),
      Q => \write_buffer.wr_buf_out_data_reg[575]\(0),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(1),
      Q => \write_buffer.wr_buf_out_data_reg[575]\(1),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(2),
      Q => \write_buffer.wr_buf_out_data_reg[575]\(2),
      R => '0'
    );
\cmd_pipe_plus.wr_data_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(3),
      Q => \write_buffer.wr_buf_out_data_reg[575]\(3),
      R => '0'
    );
\cmd_pipe_plus.wr_data_en_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \i___94_n_0\,
      Q => \^e\(0),
      R => '0'
    );
col_mach0: entity work.mig_7series_0_mig_7series_v2_3_col_mach
     port map (
      ADDRA(2) => \i___85_n_0\,
      ADDRA(1) => \i___84_n_0\,
      ADDRA(0) => \i___86_n_0\,
      CLK => CLK,
      D(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r\(3 downto 0),
      DIC(0) => col_periodic_rd,
      E(0) => mc_cmd_ns(1),
      Q(7 downto 0) => Q(7 downto 0),
      SR(0) => SR(0),
      col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0),
      col_rd_wr => col_rd_wr,
      col_rd_wr_r1 => col_rd_wr_r1,
      col_rd_wr_r2 => col_rd_wr_r2,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      maint_ref_zq_wip => maint_ref_zq_wip,
      mc_cmd(0) => \^mc_cmd\(0),
      mc_read_idle_r_reg => col_mach0_n_17,
      mc_ref_zq_wip_ns => mc_ref_zq_wip_ns,
      \not_strict_mode.app_rd_data_end_ns\ => \not_strict_mode.app_rd_data_end_ns\,
      \not_strict_mode.app_rd_data_reg[40]\ => \not_strict_mode.app_rd_data_reg[40]\,
      \not_strict_mode.bypass__0\ => \not_strict_mode.bypass__0\,
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0) => \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0),
      ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0),
      \rd_buf_indx.rd_buf_indx_r_reg[4]\ => \rd_buf_indx.rd_buf_indx_r_reg[4]\,
      \read_fifo.fifo_out_data_r_reg[7]_0\ => col_mach0_n_22,
      \read_fifo.tail_r_reg[0]_0\ => \read_fifo.tail_r_reg[0]\,
      \read_fifo.tail_r_reg[1]_0\ => \^read_fifo.tail_r_reg[1]\(0),
      \read_fifo.tail_r_reg[2]_0\(1 downto 0) => \read_fifo.tail_r\(2 downto 1),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      sent_col_r2 => sent_col_r2
    );
\i___0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFDCDCDCDCDCDC"
    )
        port map (
      I0 => bank_mach0_n_88,
      I1 => bank_mach0_n_121,
      I2 => \i___27_n_0\,
      I3 => idle_r(0),
      I4 => \i___63_n_0\,
      I5 => \bank_cntrl[0].bank0/tail_r\,
      O => \i___0_n_0\
    );
\i___1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => bank_mach0_n_119,
      I1 => bank_mach0_n_88,
      I2 => bank_mach0_n_201,
      I3 => \i___33_n_0\,
      I4 => head_r(0),
      O => \i___1_n_0\
    );
\i___10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0008"
    )
        port map (
      I0 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r\,
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => \rank_common0/periodic_read_request.upd_last_master_r\,
      I3 => periodic_rd_r,
      I4 => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      O => \i___10_n_0\
    );
\i___11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => maint_sre_r,
      I1 => maint_srx_r,
      I2 => insert_maint_r1,
      I3 => \^app_sr_active\,
      O => \i___11_n_0\
    );
\i___12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC400C400C400"
    )
        port map (
      I0 => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      I3 => insert_maint_r1,
      I4 => maint_wip_r,
      I5 => maint_ref_zq_wip,
      O => \i___12_n_0\
    );
\i___13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000100FFFFFFFF"
    )
        port map (
      I0 => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(3),
      I1 => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(4),
      I2 => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(1),
      I3 => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(0),
      I4 => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(2),
      I5 => \init_calib_complete_reg_rep__12\,
      O => \i___13_n_0\
    );
\i___14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88870008"
    )
        port map (
      I0 => \i___65_n_0\,
      I1 => insert_maint_r1,
      I2 => rank_mach0_n_32,
      I3 => app_ref_req,
      I4 => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      O => \i___14_n_0\
    );
\i___15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rank_mach0_n_32,
      I1 => \init_calib_complete_reg_rep__12\,
      O => \i___15_n_0\
    );
\i___16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF2AFFFF"
    )
        port map (
      I0 => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      I1 => insert_maint_r1,
      I2 => maint_zq_r,
      I3 => app_zq_req,
      I4 => rank_mach0_n_35,
      O => \i___16_n_0\
    );
\i___17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01111111FFFFFFFF"
    )
        port map (
      I0 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.int_read_this_rank\,
      I1 => rank_mach0_n_59,
      I2 => periodic_rd_ack_r,
      I3 => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      I4 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\,
      I5 => \init_calib_complete_reg_rep__12\,
      O => \i___17_n_0\
    );
\i___18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      I1 => periodic_rd_ack_r,
      I2 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\,
      O => \i___18_n_0\
    );
\i___19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => bank_mach0_n_100,
      I1 => \^sent_col\,
      O => \i___19_n_0\
    );
\i___2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFDCDCDCDCDCDC"
    )
        port map (
      I0 => bank_mach0_n_85,
      I1 => bank_mach0_n_125,
      I2 => \i___44_n_0\,
      I3 => idle_r(1),
      I4 => \i___62_n_0\,
      I5 => \bank_cntrl[1].bank0/tail_r\,
      O => \i___2_n_0\
    );
\i___20\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^cmd_pipe_plus.mc_odt_reg[0]_0\,
      I1 => \^sent_col\,
      O => \i___20_n_0\
    );
\i___21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => sending_col(2),
      I1 => sending_col(1),
      I2 => sending_col(0),
      I3 => sending_col(3),
      I4 => \^sent_col\,
      O => \i___21_n_0\
    );
\i___22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \bank_cntrl[0].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(0),
      I3 => sending_row(0),
      I4 => row_cmd_wr(0),
      I5 => bank_mach0_n_101,
      O => \i___22_n_0\
    );
\i___23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550001"
    )
        port map (
      I0 => \bank_cntrl[3].bank0/bank_state0/col_wait_r\,
      I1 => bank_mach0_n_106,
      I2 => bank_mach0_n_105,
      I3 => bank_mach0_n_134,
      I4 => bank_mach0_n_104,
      I5 => bank_mach0_n_103,
      O => \i___23_n_0\
    );
\i___24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \bank_cntrl[3].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(3),
      I3 => sending_row(3),
      I4 => row_cmd_wr(3),
      I5 => bank_mach0_n_102,
      O => \i___24_n_0\
    );
\i___25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => \bank_cntrl[2].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(2),
      I3 => sending_row(2),
      I4 => row_cmd_wr(2),
      I5 => bank_mach0_n_107,
      O => \i___25_n_0\
    );
\i___26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_52_out,
      I1 => bank_mach0_n_85,
      I2 => bank_mach0_n_88,
      I3 => bank_mach0_n_109,
      O => \i___26_n_0\
    );
\i___27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_13_out,
      I1 => bank_mach0_n_85,
      I2 => p_52_out,
      O => \i___27_n_0\
    );
\i___28\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CDFDFFFF"
    )
        port map (
      I0 => bank_mach0_n_124,
      I1 => bank_mach0_n_125,
      I2 => idle_r(1),
      I3 => bank_mach0_n_113,
      I4 => bank_mach0_n_85,
      O => \i___28_n_0\
    );
\i___29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202220202020"
    )
        port map (
      I0 => bank_mach0_n_85,
      I1 => \rstdiv0_sync_r1_reg_rep__21\,
      I2 => \bank_common0/maint_controller.maint_hit_busies_r\(1),
      I3 => maint_req_r,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_83,
      O => \i___29_n_0\
    );
\i___3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888FFFFB8880000"
    )
        port map (
      I0 => bank_mach0_n_126,
      I1 => bank_mach0_n_85,
      I2 => bank_mach0_n_201,
      I3 => bank_mach0_n_88,
      I4 => \i___28_n_0\,
      I5 => head_r(1),
      O => \i___3_n_0\
    );
\i___30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4454445444545555"
    )
        port map (
      I0 => \i___32_n_0\,
      I1 => \bank_cntrl[1].bank0/q_has_rd\,
      I2 => maint_req_r,
      I3 => idle_r(1),
      I4 => was_wr,
      I5 => \i___62_n_0\,
      O => \i___30_n_0\
    );
\i___31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020222020202020"
    )
        port map (
      I0 => bank_mach0_n_85,
      I1 => \rstdiv0_sync_r1_reg_rep__21\,
      I2 => \bank_cntrl[1].bank0/q_has_priority\,
      I3 => rb_hit_busy_r(1),
      I4 => bank_mach0_n_113,
      I5 => was_priority,
      O => \i___31_n_0\
    );
\i___32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFAAAAAA"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__21\,
      I1 => req_wr_r(1),
      I2 => rd_wr_r(1),
      I3 => \bank_cntrl[1].bank0/pass_open_bank_r\,
      I4 => sending_col(1),
      I5 => \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r\,
      O => \i___32_n_0\
    );
\i___33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CDFDFFFF"
    )
        port map (
      I0 => bank_mach0_n_120,
      I1 => bank_mach0_n_121,
      I2 => idle_r(0),
      I3 => bank_mach0_n_113,
      I4 => bank_mach0_n_88,
      O => \i___33_n_0\
    );
\i___34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[1].bank0/wait_for_maint_r\,
      I1 => idle_r(1),
      I2 => head_r(1),
      I3 => accept_internal_r,
      I4 => use_addr,
      I5 => periodic_rd_ack_r,
      O => \i___34_n_0\
    );
\i___35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/wait_for_maint_r\,
      I1 => idle_r(2),
      I2 => head_r(2),
      I3 => accept_internal_r,
      I4 => use_addr,
      I5 => periodic_rd_ack_r,
      O => \i___35_n_0\
    );
\i___36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010101110101010"
    )
        port map (
      I0 => p_52_out,
      I1 => \rstdiv0_sync_r1_reg_rep__21\,
      I2 => \bank_common0/maint_controller.maint_hit_busies_r\(2),
      I3 => maint_req_r,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_86,
      O => \i___36_n_0\
    );
\i___37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[3].bank0/wait_for_maint_r\,
      I1 => idle_r(3),
      I2 => head_r(3),
      I3 => accept_internal_r,
      I4 => use_addr,
      I5 => periodic_rd_ack_r,
      O => \i___37_n_0\
    );
\i___38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080800000000000"
    )
        port map (
      I0 => idle_r(3),
      I1 => head_r(3),
      I2 => accept_internal_r,
      I3 => use_addr,
      I4 => periodic_rd_ack_r,
      I5 => req_wr_r(3),
      O => \i___38_n_0\
    );
\i___39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010101110101010"
    )
        port map (
      I0 => p_13_out,
      I1 => \rstdiv0_sync_r1_reg_rep__21\,
      I2 => \bank_common0/maint_controller.maint_hit_busies_r\(3),
      I3 => maint_req_r,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_84,
      O => \i___39_n_0\
    );
\i___4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFECECECECECEC"
    )
        port map (
      I0 => p_52_out,
      I1 => bank_mach0_n_117,
      I2 => bank_mach0_n_122,
      I3 => idle_r(2),
      I4 => bank_mach0_n_137,
      I5 => \bank_cntrl[2].bank0/tail_r\,
      O => \i___4_n_0\
    );
\i___40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAEAAAAAAA"
    )
        port map (
      I0 => \bank_cntrl[0].bank0/wait_for_maint_r\,
      I1 => idle_r(0),
      I2 => head_r(0),
      I3 => accept_internal_r,
      I4 => use_addr,
      I5 => periodic_rd_ack_r,
      O => \i___40_n_0\
    );
\i___41\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202220202020"
    )
        port map (
      I0 => bank_mach0_n_88,
      I1 => \rstdiv0_sync_r1_reg_rep__21\,
      I2 => \bank_common0/maint_controller.maint_hit_busies_r\(0),
      I3 => maint_req_r,
      I4 => maint_wip_r,
      I5 => bank_mach0_n_87,
      O => \i___41_n_0\
    );
\i___42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550001"
    )
        port map (
      I0 => \bank_cntrl[1].bank0/bank_state0/col_wait_r\,
      I1 => bank_mach0_n_133,
      I2 => bank_mach0_n_132,
      I3 => bank_mach0_n_135,
      I4 => bank_mach0_n_131,
      I5 => bank_mach0_n_130,
      O => \i___42_n_0\
    );
\i___43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555040404"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \bank_cntrl[1].bank0/bank_state0/col_wait_r\,
      I2 => sending_col(1),
      I3 => sending_row(1),
      I4 => row_cmd_wr(1),
      I5 => bank_mach0_n_129,
      O => \i___43_n_0\
    );
\i___44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => p_52_out,
      I1 => bank_mach0_n_88,
      I2 => p_13_out,
      O => \i___44_n_0\
    );
\i___45\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => bank_mach0_n_88,
      I1 => idle_r(3),
      I2 => idle_r(2),
      I3 => idle_r(1),
      I4 => idle_r(0),
      O => \i___45_n_0\
    );
\i___46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4454445444545555"
    )
        port map (
      I0 => \i___48_n_0\,
      I1 => \bank_cntrl[0].bank0/q_has_rd\,
      I2 => maint_req_r,
      I3 => idle_r(0),
      I4 => was_wr,
      I5 => \i___63_n_0\,
      O => \i___46_n_0\
    );
\i___47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020222020202020"
    )
        port map (
      I0 => bank_mach0_n_88,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => \bank_cntrl[0].bank0/q_has_priority\,
      I3 => rb_hit_busy_r(0),
      I4 => bank_mach0_n_113,
      I5 => was_priority,
      O => \i___47_n_0\
    );
\i___48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFAAAAAA"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => req_wr_r(0),
      I2 => rd_wr_r(0),
      I3 => \bank_cntrl[0].bank0/pass_open_bank_r\,
      I4 => sending_col(0),
      I5 => \bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r\,
      O => \i___48_n_0\
    );
\i___49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4454445444545555"
    )
        port map (
      I0 => bank_mach0_n_128,
      I1 => \bank_cntrl[3].bank0/q_has_rd\,
      I2 => maint_req_r,
      I3 => idle_r(3),
      I4 => was_wr,
      I5 => bank_mach0_n_136,
      O => \i___49_n_0\
    );
\i___5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F80FFFF8F800000"
    )
        port map (
      I0 => bank_mach0_n_123,
      I1 => bank_mach0_n_201,
      I2 => p_52_out,
      I3 => bank_mach0_n_116,
      I4 => bank_mach0_n_118,
      I5 => head_r(2),
      O => \i___5_n_0\
    );
\i___50\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010111010101010"
    )
        port map (
      I0 => p_13_out,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => \bank_cntrl[3].bank0/q_has_priority\,
      I3 => rb_hit_busy_r(3),
      I4 => bank_mach0_n_113,
      I5 => was_priority,
      O => \i___50_n_0\
    );
\i___51\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4454445444545555"
    )
        port map (
      I0 => bank_mach0_n_127,
      I1 => \bank_cntrl[2].bank0/q_has_rd\,
      I2 => maint_req_r,
      I3 => idle_r(2),
      I4 => was_wr,
      I5 => bank_mach0_n_137,
      O => \i___51_n_0\
    );
\i___52\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010111010101010"
    )
        port map (
      I0 => p_52_out,
      I1 => \rstdiv0_sync_r1_reg_rep__20\,
      I2 => \bank_cntrl[2].bank0/q_has_priority\,
      I3 => rb_hit_busy_r(2),
      I4 => bank_mach0_n_113,
      I5 => was_priority,
      O => \i___52_n_0\
    );
\i___53\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => periodic_rd_ack_r,
      I2 => \rank_common0/periodic_read_request.periodic_rd_r_cnt\,
      O => \i___53_n_0\
    );
\i___54\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => periodic_rd_r,
      I1 => periodic_rd_ack_r,
      I2 => \bank_common0/periodic_rd_cntr_r\,
      O => \i___54_n_0\
    );
\i___55\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFAA"
    )
        port map (
      I0 => cmd(0),
      I1 => periodic_rd_ack_r,
      I2 => \bank_common0/periodic_rd_cntr_r\,
      I3 => periodic_rd_r,
      O => \i___55_n_0\
    );
\i___56\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => sent_row,
      I1 => insert_maint_r1,
      I2 => sending_row(1),
      I3 => sending_row(2),
      I4 => sending_row(3),
      O => \i___56_n_0\
    );
\i___57\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF1"
    )
        port map (
      I0 => sent_row,
      I1 => insert_maint_r1,
      I2 => sending_row(1),
      I3 => sending_row(2),
      I4 => sending_row(3),
      O => \i___57_n_0\
    );
\i___58\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00F0F8F8"
    )
        port map (
      I0 => app_sr_req,
      I1 => \init_calib_complete_reg_rep__12\,
      I2 => \rank_common0/sr_cntrl.sre_request_logic.sre_request_r\,
      I3 => insert_maint_r1,
      I4 => maint_sre_r,
      O => \i___58_n_0\
    );
\i___59\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000015"
    )
        port map (
      I0 => bank_mach0_n_198,
      I1 => row_cmd_wr(3),
      I2 => sending_row(3),
      I3 => sending_row(0),
      I4 => bank_mach0_n_203,
      O => \i___59_n_0\
    );
\i___6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFECECECECECEC"
    )
        port map (
      I0 => p_13_out,
      I1 => bank_mach0_n_108,
      I2 => bank_mach0_n_110,
      I3 => idle_r(3),
      I4 => bank_mach0_n_136,
      I5 => \bank_cntrl[3].bank0/tail_r\,
      O => \i___6_n_0\
    );
\i___60\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => rnk_config_valid_r,
      I1 => bank_mach0_n_199,
      I2 => bank_mach0_n_200,
      O => \i___60_n_0\
    );
\i___61\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => bank_mach0_n_113,
      I1 => idle_r(3),
      I2 => idle_r(2),
      I3 => idle_r(1),
      I4 => idle_r(0),
      O => \i___61_n_0\
    );
\i___62\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"07FF"
    )
        port map (
      I0 => use_addr,
      I1 => bank_mach0_n_2,
      I2 => periodic_rd_ack_r,
      I3 => rb_hit_busy_r(1),
      O => \i___62_n_0\
    );
\i___63\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"07FF"
    )
        port map (
      I0 => use_addr,
      I1 => bank_mach0_n_2,
      I2 => periodic_rd_ack_r,
      I3 => rb_hit_busy_r(0),
      O => \i___63_n_0\
    );
\i___64\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AB"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => maint_req_r,
      I2 => maint_wip_r,
      O => \i___64_n_0\
    );
\i___65\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => maint_srx_r,
      I1 => maint_sre_r,
      I2 => maint_zq_r,
      O => \i___65_n_0\
    );
\i___66\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101010101015101"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => bank_mach0_n_214,
      I2 => insert_maint_r,
      I3 => maint_srx_r,
      I4 => maint_zq_r,
      I5 => maint_sre_r,
      O => \i___66_n_0\
    );
\i___67\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55554055"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \wtr_timer.wtr_cnt_r\(0),
      I2 => \wtr_timer.wtr_cnt_r\(1),
      I3 => bank_mach0_n_207,
      I4 => bank_mach0_n_206,
      O => \i___67_n_0\
    );
\i___68\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55550455"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => \wtr_timer.wtr_cnt_r\(1),
      I2 => \wtr_timer.wtr_cnt_r\(0),
      I3 => bank_mach0_n_207,
      I4 => bank_mach0_n_206,
      O => \i___68_n_0\
    );
\i___69\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000BABF"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__20\,
      I1 => sending_col(1),
      I2 => \^sent_col\,
      I3 => \arb_mux0/arb_row_col0/col_arb0/last_master_r\(1),
      I4 => bank_mach0_n_96,
      I5 => bank_mach0_n_95,
      O => \i___69_n_0\
    );
\i___7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F80FFFF8F800000"
    )
        port map (
      I0 => bank_mach0_n_110,
      I1 => bank_mach0_n_201,
      I2 => p_13_out,
      I3 => bank_mach0_n_111,
      I4 => bank_mach0_n_112,
      I5 => head_r(3),
      O => \i___7_n_0\
    );
\i___70\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r\(3),
      I2 => \arb_mux0/cs_en2\,
      I3 => sending_pre(3),
      O => \i___70_n_0\
    );
\i___71\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0151"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \rank_common0/maintenance_request.maint_arb0/last_master_r\(2),
      I2 => \rank_common0/maintenance_request.upd_last_master_r\,
      I3 => \rank_common0/maintenance_request.maint_grant_r\(2),
      O => \i___71_n_0\
    );
\i___72\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF4C"
    )
        port map (
      I0 => periodic_rd_ack_r,
      I1 => periodic_rd_r,
      I2 => \rank_common0/periodic_read_request.periodic_rd_r_cnt\,
      I3 => \rank_common0/periodic_read_request.upd_last_master_r\,
      O => \i___72_n_0\
    );
\i___73\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => app_ref_req,
      I1 => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      I2 => \rank_common0/app_ref_r\,
      O => \i___73_n_0\
    );
\i___74\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => app_zq_req,
      I1 => \rank_common0/app_zq_r\,
      I2 => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      O => \i___74_n_0\
    );
\i___75\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5155554504000010"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \inhbt_act_faw.faw_cnt_r\(0),
      I2 => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      I3 => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      I4 => \inhbt_act_faw.faw_cnt_r\(1),
      I5 => \inhbt_act_faw.faw_cnt_r\(2),
      O => \i___75_n_0\
    );
\i___76\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"41444414"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \inhbt_act_faw.faw_cnt_r\(1),
      I2 => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      I3 => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      I4 => \inhbt_act_faw.faw_cnt_r\(0),
      O => \i___76_n_0\
    );
\i___77\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4114"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      I2 => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      I3 => \inhbt_act_faw.faw_cnt_r\(0),
      O => \i___77_n_0\
    );
\i___78\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E1"
    )
        port map (
      I0 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I1 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I2 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I3 => \rstdiv0_sync_r1_reg_rep__19\,
      I4 => insert_maint_r,
      O => \i___78_n_0\
    );
\i___79\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3),
      I1 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I2 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I3 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      O => \i___79_n_0\
    );
\i___8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0F0"
    )
        port map (
      I0 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\(1),
      I1 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\(0),
      I2 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => maint_prescaler_tick_r,
      I4 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.int_read_this_rank\,
      O => \i___8_n_0\
    );
\i___80\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0),
      I1 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1),
      I2 => \bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2),
      I3 => bank_mach0_n_209,
      O => \i___80_n_0\
    );
\i___81\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055550010"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/bank_state0/override_demand_r\,
      I1 => \bank_cntrl[2].bank0/bank_state0/demanded_prior_r\,
      I2 => \bank_cntrl[2].bank0/bank_state0/demand_priority_r\,
      I3 => sending_col(2),
      I4 => bank_mach0_n_204,
      I5 => \bank_cntrl[0].bank0/bank_state0/demand_priority_r\,
      O => \i___81_n_0\
    );
\i___82\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011111511"
    )
        port map (
      I0 => \bank_cntrl[2].bank0/bank_state0/override_demand_r\,
      I1 => bank_mach0_n_205,
      I2 => \bank_cntrl[1].bank0/bank_state0/demanded_prior_r\,
      I3 => \bank_cntrl[1].bank0/bank_state0/demand_priority_r\,
      I4 => sending_col(1),
      I5 => \bank_cntrl[3].bank0/bank_state0/demand_priority_r\,
      O => \i___82_n_0\
    );
\i___83\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => sending_col(3),
      I1 => \bank_cntrl[3].bank0/bank_state0/demand_priority_r\,
      I2 => \bank_cntrl[3].bank0/bank_state0/demanded_prior_r\,
      O => \i___83_n_0\
    );
\i___84\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \^read_fifo.tail_r_reg[1]\(0),
      I2 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I3 => \read_fifo.tail_r\(1),
      I4 => \read_fifo.tail_r\(2),
      O => \i___84_n_0\
    );
\i___85\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => col_mach0_n_22,
      O => \i___85_n_0\
    );
\i___86\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1540"
    )
        port map (
      I0 => \rstdiv0_sync_r1_reg_rep__19\,
      I1 => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      I2 => \^read_fifo.tail_r_reg[1]\(0),
      I3 => \read_fifo.tail_r\(1),
      O => \i___86_n_0\
    );
\i___87\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2),
      I1 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1),
      I2 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(0),
      O => \i___87_n_0\
    );
\i___88\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5),
      I1 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3),
      I2 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2),
      I3 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(0),
      I4 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1),
      I5 => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(4),
      O => \i___88_n_0\
    );
\i___89\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(2),
      I1 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(1),
      I2 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(0),
      O => \i___89_n_0\
    );
\i___9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF32CC"
    )
        port map (
      I0 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\(1),
      I1 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\(0),
      I2 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\(2),
      I3 => maint_prescaler_tick_r,
      I4 => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.int_read_this_rank\,
      O => \i___9_n_0\
    );
\i___90\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(5),
      I1 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3),
      I2 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(2),
      I3 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(0),
      I4 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(1),
      I5 => \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(4),
      O => \i___90_n_0\
    );
\i___91\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(2),
      I1 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(1),
      I2 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(0),
      O => \i___91_n_0\
    );
\i___92\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(5),
      I1 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3),
      I2 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(2),
      I3 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(0),
      I4 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(1),
      I5 => \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(4),
      O => \i___92_n_0\
    );
\i___93\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sent_col_r2,
      I1 => col_rd_wr_r2,
      O => \i___93_n_0\
    );
\i___94\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^mc_cmd\(0),
      I1 => col_rd_wr_r1,
      O => \i___94_n_0\
    );
\i___95\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(0),
      I1 => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(1),
      O => \i___95_n_0\
    );
\i___96\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rank_common0/refresh_timer.refresh_timer_r_reg__0\(0),
      I1 => \rank_common0/refresh_timer.refresh_timer_r_reg__0\(1),
      O => \i___96_n_0\
    );
mc_read_idle_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => col_mach0_n_17,
      Q => idle,
      R => \maint_prescaler.maint_prescaler_r1\
    );
mc_ref_zq_wip_r_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mc_ref_zq_wip_ns,
      Q => tempmon_sample_en,
      R => '0'
    );
mem_reg_0_15_0_5_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_ras_n\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      O => \rd_ptr_timing_reg[0]\(0)
    );
mem_reg_0_15_36_41_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cs_n\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      O => phy_dout(0)
    );
mem_reg_0_15_42_47_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_ras_n\(2),
      I1 => \init_calib_complete_reg_rep__26\,
      O => phy_dout(1)
    );
mem_reg_0_15_42_47_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rd_ptr_timing_reg[0]_0\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      O => phy_dout(2)
    );
mem_reg_0_15_42_47_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rd_ptr_timing_reg[0]_0\(2),
      I1 => \init_calib_complete_reg_rep__26\,
      O => phy_dout(3)
    );
mem_reg_0_15_48_53_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cas_n\(0),
      I1 => \init_calib_complete_reg_rep__26\,
      O => phy_dout(4)
    );
mem_reg_0_15_54_59_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^mc_cas_n\(2),
      I1 => \init_calib_complete_reg_rep__26\,
      O => phy_dout(5)
    );
\pointer_ram.rams[0].RAM32M0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^e\(0),
      I1 => ram_init_done_r,
      O => \pointer_ram.pointer_we\
    );
rank_mach0: entity work.mig_7series_0_mig_7series_v2_3_rank_mach
     port map (
      CLK => CLK,
      D(2) => \i___75_n_0\,
      D(1) => \i___76_n_0\,
      D(0) => \i___77_n_0\,
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\,
      Q(4 downto 0) => \rank_common0/maint_prescaler.maint_prescaler_r_reg__0\(4 downto 0),
      S(3) => rank_mach0_n_38,
      S(2) => rank_mach0_n_39,
      S(1) => rank_mach0_n_40,
      S(0) => rank_mach0_n_41,
      SR(0) => SR(0),
      SS(0) => \i___13_n_0\,
      act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\,
      app_ref_ack => app_ref_ack,
      app_ref_r => \rank_common0/app_ref_r\,
      app_sr_active => \^app_sr_active\,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_r => \rank_common0/app_zq_r\,
      app_zq_r_reg => \i___74_n_0\,
      cke_r => \arb_mux0/arb_select0/cke_r\,
      in0 => in0,
      \inhbt_act_faw.act_delayed\ => \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed\,
      \inhbt_act_faw.inhbt_act_faw_r_reg\(2 downto 0) => \inhbt_act_faw.faw_cnt_r\(2 downto 0),
      inhbt_act_faw_r => inhbt_act_faw_r,
      \init_calib_complete_reg_rep__12\ => \i___58_n_0\,
      \init_calib_complete_reg_rep__12_0\ => \init_calib_complete_reg_rep__12\,
      \init_calib_complete_reg_rep__12_1\(0) => \i___15_n_0\,
      insert_maint_r1 => insert_maint_r1,
      insert_maint_r1_lcl_reg => bank_mach0_n_197,
      insert_maint_r1_lcl_reg_0 => \i___14_n_0\,
      \last_master_r_reg[2]\(0) => \rank_common0/maintenance_request.maint_arb0/last_master_r\(2),
      \last_master_r_reg[2]_0\ => \i___71_n_0\,
      \maint_controller.maint_wip_r_lcl_reg\ => bank_mach0_n_115,
      \maint_prescaler.maint_prescaler_r1\ => \maint_prescaler.maint_prescaler_r1\,
      \maint_prescaler.maint_prescaler_r_reg[0]\(0) => \i___95_n_0\,
      maint_prescaler_tick_r => maint_prescaler_tick_r,
      maint_ref_zq_wip => maint_ref_zq_wip,
      maint_req_r => maint_req_r,
      maint_sre_r => maint_sre_r,
      maint_srx_r => maint_srx_r,
      maint_zq_r => maint_zq_r,
      \maintenance_request.maint_sre_r_lcl_reg\(0) => \rank_common0/maintenance_request.maint_grant_r\(2),
      \maintenance_request.maint_sre_r_lcl_reg_0\ => \i___11_n_0\,
      \maintenance_request.upd_last_master_r\ => \rank_common0/maintenance_request.upd_last_master_r\,
      mc_cke_ns(0) => mc_cke_ns(1),
      periodic_rd_ack_r_lcl_reg => \i___17_n_0\,
      periodic_rd_ack_r_lcl_reg_0 => \i___72_n_0\,
      \periodic_rd_generation.int_read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.int_read_this_rank\,
      \periodic_rd_generation.periodic_rd_cntr1_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r\,
      \periodic_rd_generation.periodic_rd_request_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r\,
      \periodic_rd_generation.periodic_rd_request_r_reg\ => rank_mach0_n_59,
      \periodic_rd_generation.periodic_rd_request_r_reg_0\ => \i___10_n_0\,
      \periodic_rd_generation.periodic_rd_timer_r\(2 downto 0) => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r\(2 downto 0),
      \periodic_rd_generation.periodic_rd_timer_r_reg[1]\ => \i___8_n_0\,
      \periodic_rd_generation.periodic_rd_timer_r_reg[1]_0\ => \i___9_n_0\,
      \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\,
      \periodic_rd_generation.read_this_rank_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\,
      periodic_rd_r => periodic_rd_r,
      \periodic_read_request.periodic_rd_grant_r\ => \rank_common0/periodic_read_request.periodic_rd_grant_r\,
      \periodic_read_request.periodic_rd_grant_r_reg[0]\ => \i___18_n_0\,
      \periodic_read_request.periodic_rd_r_cnt\ => \rank_common0/periodic_read_request.periodic_rd_r_cnt\,
      \periodic_read_request.periodic_rd_r_lcl_reg\ => \i___53_n_0\,
      \periodic_read_request.upd_last_master_r\ => \rank_common0/periodic_read_request.upd_last_master_r\,
      \refresh_generation.refresh_bank_r\ => \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r\,
      \refresh_generation.refresh_bank_r_reg[0]\ => \i___73_n_0\,
      \refresh_generation.refresh_bank_r_reg[0]_0\ => \i___12_n_0\,
      \refresh_timer.refresh_timer_r_reg[0]\(0) => \i___96_n_0\,
      \refresh_timer.refresh_timer_r_reg[4]\(1 downto 0) => \rank_common0/refresh_timer.refresh_timer_r_reg__0\(1 downto 0),
      \refresh_timer.refresh_timer_r_reg[5]\ => rank_mach0_n_32,
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \sr_cntrl.sre_request_logic.sre_request_r\ => \rank_common0/sr_cntrl.sre_request_logic.sre_request_r\,
      \wtr_timer.wtr_cnt_r_reg[0]\(1 downto 0) => \wtr_timer.wtr_cnt_r\(1 downto 0),
      \wtr_timer.wtr_cnt_r_reg[0]_0\(1) => \i___67_n_0\,
      \wtr_timer.wtr_cnt_r_reg[0]_0\(0) => \i___68_n_0\,
      \zq_cntrl.zq_request_logic.zq_request_r\ => \rank_common0/zq_cntrl.zq_request_logic.zq_request_r\,
      \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \i___16_n_0\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[0]\ => rank_mach0_n_35,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(3) => rank_mach0_n_46,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(2) => rank_mach0_n_47,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(1) => rank_mach0_n_48,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(0) => rank_mach0_n_49,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(3) => rank_mach0_n_50,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(2) => rank_mach0_n_51,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(1) => rank_mach0_n_52,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(0) => rank_mach0_n_53,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(3) => rank_mach0_n_54,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(2) => rank_mach0_n_55,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(1) => rank_mach0_n_56,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(0) => rank_mach0_n_57,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(3) => rank_mach0_n_42,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(2) => rank_mach0_n_43,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(1) => rank_mach0_n_44,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(0) => rank_mach0_n_45,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\,
      \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\,
      S(3) => rank_mach0_n_38,
      S(2) => rank_mach0_n_39,
      S(1) => rank_mach0_n_40,
      S(0) => rank_mach0_n_41
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\,
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\,
      S(3) => rank_mach0_n_50,
      S(2) => rank_mach0_n_51,
      S(1) => rank_mach0_n_52,
      S(0) => rank_mach0_n_53
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\,
      CO(3) => \NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\,
      S(3) => rank_mach0_n_54,
      S(2) => rank_mach0_n_55,
      S(1) => rank_mach0_n_56,
      S(0) => rank_mach0_n_57
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\,
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\,
      S(3) => rank_mach0_n_42,
      S(2) => rank_mach0_n_43,
      S(1) => rank_mach0_n_44,
      S(0) => rank_mach0_n_45
    );
\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\,
      CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\,
      CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1\,
      CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2\,
      CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\,
      O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\,
      O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\,
      O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\,
      S(3) => rank_mach0_n_46,
      S(2) => rank_mach0_n_47,
      S(1) => rank_mach0_n_48,
      S(0) => rank_mach0_n_49
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_ddr_phy_top is
  port (
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dqs_po_en_stg2_f_reg : out STD_LOGIC;
    \complex_row1_rd_cnt_reg[1]\ : out STD_LOGIC;
    rdlvl_stg1_start_r_reg : out STD_LOGIC;
    idelay_tap_limit_r_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    fine_dly_dec_done_r1_reg : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    app_zq_r_reg : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC;
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[7]_1\ : out STD_LOGIC;
    \my_empty_reg[7]_2\ : out STD_LOGIC;
    \my_empty_reg[7]_3\ : out STD_LOGIC;
    \my_empty_reg[7]_4\ : out STD_LOGIC;
    \my_empty_reg[7]_5\ : out STD_LOGIC;
    \my_empty_reg[7]_6\ : out STD_LOGIC;
    \my_empty_reg[7]_7\ : out STD_LOGIC;
    \phy_ctl_wd_i1_reg[0]\ : out STD_LOGIC;
    phy_mc_ctl_full : out STD_LOGIC;
    \not_strict_mode.rd_buf_we\ : out STD_LOGIC;
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : out STD_LOGIC;
    rst_sync_r1_reg : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[8]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[16]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[56]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[48]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[24]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[32]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[42]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[50]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[26]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[34]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[10]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[18]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[58]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[44]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[52]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[28]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[36]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[12]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[20]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[60]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[46]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[54]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[30]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[38]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[14]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[22]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[62]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[104]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[112]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[88]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[96]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[72]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[80]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[120]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[64]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[106]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[114]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[90]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[98]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[74]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[82]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[122]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[66]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[108]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[116]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[92]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[100]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[76]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[84]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[124]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[68]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[110]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[118]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[94]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[102]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[78]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[86]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[126]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[70]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[168]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[176]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[152]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[160]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[136]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[144]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[184]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[128]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[170]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[178]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[154]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[162]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[138]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[146]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[186]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[130]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[172]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[180]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[156]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[164]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[140]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[148]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[188]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[132]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[142]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[150]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[190]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[134]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[174]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[182]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[158]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[166]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[232]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[240]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[216]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[224]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[200]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[208]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[248]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[192]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[234]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[242]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[218]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[226]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[202]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[210]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[250]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[194]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[236]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[244]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[220]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[228]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[204]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[212]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[252]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[196]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[238]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[246]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[222]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[230]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[206]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[214]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[254]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[198]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[296]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[304]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[280]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[288]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[264]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[272]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[312]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[256]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[298]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[306]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[282]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[290]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[266]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[274]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[314]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[258]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[300]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[308]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[284]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[292]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[268]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[276]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[316]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[260]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[270]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[278]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[318]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[262]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[302]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[310]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[286]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[294]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[360]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[368]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[344]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[352]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[328]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[336]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[376]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[320]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[362]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[370]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[346]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[354]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[330]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[338]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[378]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[322]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[364]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[372]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[348]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[356]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[332]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[340]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[380]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[324]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[366]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[374]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[350]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[358]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[334]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[342]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[382]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[326]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[392]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[400]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[440]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[384]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[424]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[432]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[408]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[416]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[426]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[434]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[410]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[418]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[394]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[402]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[442]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[386]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[428]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[436]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[412]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[420]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[396]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[404]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[444]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[388]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[430]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[438]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[414]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[422]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[398]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[406]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[446]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[390]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[488]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[496]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[472]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[480]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[456]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[464]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[504]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[448]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[458]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[466]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[506]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[450]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[490]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[498]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[474]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[482]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[492]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[500]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[476]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[484]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[460]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[468]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[508]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[452]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[494]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[502]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[478]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[486]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[462]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[470]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[510]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[454]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC;
    \maint_prescaler.maint_prescaler_r1\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \read_fifo.tail_r_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[4]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[1]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]\ : out STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC_VECTOR ( 511 downto 0 );
    of_ctl_full_v : out STD_LOGIC_VECTOR ( 0 to 0 );
    phy_mc_data_full : out STD_LOGIC;
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    CLK : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    in0 : in STD_LOGIC;
    RST0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 1 downto 0 );
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    idle : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__4\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__5\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tempmon_sample_en : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__15\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__17\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__22\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_init_done_r : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_rst_0 : in STD_LOGIC;
    mc_ras_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_cs_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 );
    mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_we_n_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mc_address : in STD_LOGIC_VECTOR ( 38 downto 0 );
    mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \write_buffer.wr_buf_out_data_reg[575]\ : in STD_LOGIC_VECTOR ( 575 downto 0 );
    sent_col : in STD_LOGIC;
    \grant_r_reg[3]\ : in STD_LOGIC;
    \read_fifo.tail_r\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    mc_wrdata_en : in STD_LOGIC;
    phy_dout : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_1_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_2_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_ras_n_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[5]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[4]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \cmd_pipe_plus.mc_data_offset_reg[2]\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[1]_0\ : in STD_LOGIC;
    \cmd_pipe_plus.mc_data_offset_reg[0]_0\ : in STD_LOGIC;
    mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \read_fifo.fifo_out_data_r_reg[6]\ : in STD_LOGIC;
    DOC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \write_buffer.wr_buf_out_data_reg[383]\ : in STD_LOGIC_VECTOR ( 95 downto 0 );
    \rstdiv0_sync_r1_reg_rep__10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_rdlvl_done_pulse_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__22_0\ : in STD_LOGIC;
    new_cnt_cpt_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_start_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    clear : in STD_LOGIC;
    pi_cnt_dec_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \device_temp_r_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_ddr_phy_top : entity is "mig_7series_v2_3_ddr_phy_top";
end mig_7series_0_mig_7series_v2_3_ddr_phy_top;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_ddr_phy_top is
  signal \^app_zq_r_reg\ : STD_LOGIC;
  signal calib_sel : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal data_offset_1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal data_offset_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal idelay_inc : STD_LOGIC;
  signal \^init_calib_complete\ : STD_LOGIC;
  signal mux_address : STD_LOGIC_VECTOR ( 54 downto 0 );
  signal mux_bank : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal mux_cas_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_cke : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mux_cs_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_ras_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_reset_n : STD_LOGIC;
  signal mux_we_n : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mux_wrdata : STD_LOGIC_VECTOR ( 511 downto 1 );
  signal mux_wrdata_mask : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \^not_strict_mode.app_rd_data_reg[0]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[10]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[11]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[12]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[13]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[14]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[15]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[16]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[17]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[18]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[19]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[1]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[20]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[21]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[22]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[23]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[24]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[25]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[26]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[27]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[28]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[29]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[2]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[30]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[31]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[32]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[33]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[34]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[35]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[36]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[37]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[38]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[39]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[3]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[40]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[41]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[42]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[43]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[44]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[45]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[46]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[47]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[48]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[49]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[4]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[50]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[51]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[52]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[53]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[54]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[55]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[56]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[57]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[58]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[59]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[5]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[60]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[61]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[62]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[63]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[6]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[7]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[8]\ : STD_LOGIC;
  signal \^not_strict_mode.app_rd_data_reg[9]\ : STD_LOGIC;
  signal phy_cmd_wr_en : STD_LOGIC;
  signal phy_ctl_wd : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal phy_data_wr_en : STD_LOGIC;
  signal phy_if_reset : STD_LOGIC;
  signal phy_mc_go : STD_LOGIC;
  signal phy_rddata_en : STD_LOGIC;
  signal phy_read_calib : STD_LOGIC;
  signal phy_write_calib : STD_LOGIC;
  signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal u_ddr_calib_top_n_1 : STD_LOGIC;
  signal u_ddr_calib_top_n_100 : STD_LOGIC;
  signal u_ddr_calib_top_n_101 : STD_LOGIC;
  signal u_ddr_calib_top_n_102 : STD_LOGIC;
  signal u_ddr_calib_top_n_103 : STD_LOGIC;
  signal u_ddr_calib_top_n_104 : STD_LOGIC;
  signal u_ddr_calib_top_n_105 : STD_LOGIC;
  signal u_ddr_calib_top_n_106 : STD_LOGIC;
  signal u_ddr_calib_top_n_107 : STD_LOGIC;
  signal u_ddr_calib_top_n_108 : STD_LOGIC;
  signal u_ddr_calib_top_n_109 : STD_LOGIC;
  signal u_ddr_calib_top_n_110 : STD_LOGIC;
  signal u_ddr_calib_top_n_111 : STD_LOGIC;
  signal u_ddr_calib_top_n_112 : STD_LOGIC;
  signal u_ddr_calib_top_n_113 : STD_LOGIC;
  signal u_ddr_calib_top_n_114 : STD_LOGIC;
  signal u_ddr_calib_top_n_115 : STD_LOGIC;
  signal u_ddr_calib_top_n_116 : STD_LOGIC;
  signal u_ddr_calib_top_n_117 : STD_LOGIC;
  signal u_ddr_calib_top_n_118 : STD_LOGIC;
  signal u_ddr_calib_top_n_119 : STD_LOGIC;
  signal u_ddr_calib_top_n_120 : STD_LOGIC;
  signal u_ddr_calib_top_n_121 : STD_LOGIC;
  signal u_ddr_calib_top_n_1219 : STD_LOGIC;
  signal u_ddr_calib_top_n_122 : STD_LOGIC;
  signal u_ddr_calib_top_n_1220 : STD_LOGIC;
  signal u_ddr_calib_top_n_1221 : STD_LOGIC;
  signal u_ddr_calib_top_n_1222 : STD_LOGIC;
  signal u_ddr_calib_top_n_1223 : STD_LOGIC;
  signal u_ddr_calib_top_n_1224 : STD_LOGIC;
  signal u_ddr_calib_top_n_123 : STD_LOGIC;
  signal u_ddr_calib_top_n_124 : STD_LOGIC;
  signal u_ddr_calib_top_n_125 : STD_LOGIC;
  signal u_ddr_calib_top_n_126 : STD_LOGIC;
  signal u_ddr_calib_top_n_127 : STD_LOGIC;
  signal u_ddr_calib_top_n_128 : STD_LOGIC;
  signal u_ddr_calib_top_n_129 : STD_LOGIC;
  signal u_ddr_calib_top_n_130 : STD_LOGIC;
  signal u_ddr_calib_top_n_131 : STD_LOGIC;
  signal u_ddr_calib_top_n_132 : STD_LOGIC;
  signal u_ddr_calib_top_n_133 : STD_LOGIC;
  signal u_ddr_calib_top_n_134 : STD_LOGIC;
  signal u_ddr_calib_top_n_135 : STD_LOGIC;
  signal u_ddr_calib_top_n_136 : STD_LOGIC;
  signal u_ddr_calib_top_n_137 : STD_LOGIC;
  signal u_ddr_calib_top_n_138 : STD_LOGIC;
  signal u_ddr_calib_top_n_139 : STD_LOGIC;
  signal u_ddr_calib_top_n_140 : STD_LOGIC;
  signal u_ddr_calib_top_n_141 : STD_LOGIC;
  signal u_ddr_calib_top_n_142 : STD_LOGIC;
  signal u_ddr_calib_top_n_143 : STD_LOGIC;
  signal u_ddr_calib_top_n_144 : STD_LOGIC;
  signal u_ddr_calib_top_n_145 : STD_LOGIC;
  signal u_ddr_calib_top_n_146 : STD_LOGIC;
  signal u_ddr_calib_top_n_147 : STD_LOGIC;
  signal u_ddr_calib_top_n_148 : STD_LOGIC;
  signal u_ddr_calib_top_n_149 : STD_LOGIC;
  signal u_ddr_calib_top_n_150 : STD_LOGIC;
  signal u_ddr_calib_top_n_151 : STD_LOGIC;
  signal u_ddr_calib_top_n_152 : STD_LOGIC;
  signal u_ddr_calib_top_n_153 : STD_LOGIC;
  signal u_ddr_calib_top_n_154 : STD_LOGIC;
  signal u_ddr_calib_top_n_155 : STD_LOGIC;
  signal u_ddr_calib_top_n_156 : STD_LOGIC;
  signal u_ddr_calib_top_n_157 : STD_LOGIC;
  signal u_ddr_calib_top_n_158 : STD_LOGIC;
  signal u_ddr_calib_top_n_159 : STD_LOGIC;
  signal u_ddr_calib_top_n_160 : STD_LOGIC;
  signal u_ddr_calib_top_n_161 : STD_LOGIC;
  signal u_ddr_calib_top_n_162 : STD_LOGIC;
  signal u_ddr_calib_top_n_163 : STD_LOGIC;
  signal u_ddr_calib_top_n_164 : STD_LOGIC;
  signal u_ddr_calib_top_n_165 : STD_LOGIC;
  signal u_ddr_calib_top_n_166 : STD_LOGIC;
  signal u_ddr_calib_top_n_167 : STD_LOGIC;
  signal u_ddr_calib_top_n_168 : STD_LOGIC;
  signal u_ddr_calib_top_n_169 : STD_LOGIC;
  signal u_ddr_calib_top_n_170 : STD_LOGIC;
  signal u_ddr_calib_top_n_174 : STD_LOGIC;
  signal u_ddr_calib_top_n_175 : STD_LOGIC;
  signal u_ddr_calib_top_n_176 : STD_LOGIC;
  signal u_ddr_calib_top_n_177 : STD_LOGIC;
  signal u_ddr_calib_top_n_178 : STD_LOGIC;
  signal u_ddr_calib_top_n_179 : STD_LOGIC;
  signal u_ddr_calib_top_n_180 : STD_LOGIC;
  signal u_ddr_calib_top_n_181 : STD_LOGIC;
  signal u_ddr_calib_top_n_182 : STD_LOGIC;
  signal u_ddr_calib_top_n_183 : STD_LOGIC;
  signal u_ddr_calib_top_n_184 : STD_LOGIC;
  signal u_ddr_calib_top_n_185 : STD_LOGIC;
  signal u_ddr_calib_top_n_186 : STD_LOGIC;
  signal u_ddr_calib_top_n_187 : STD_LOGIC;
  signal u_ddr_calib_top_n_188 : STD_LOGIC;
  signal u_ddr_calib_top_n_189 : STD_LOGIC;
  signal u_ddr_calib_top_n_190 : STD_LOGIC;
  signal u_ddr_calib_top_n_191 : STD_LOGIC;
  signal u_ddr_calib_top_n_192 : STD_LOGIC;
  signal u_ddr_calib_top_n_193 : STD_LOGIC;
  signal u_ddr_calib_top_n_194 : STD_LOGIC;
  signal u_ddr_calib_top_n_195 : STD_LOGIC;
  signal u_ddr_calib_top_n_196 : STD_LOGIC;
  signal u_ddr_calib_top_n_197 : STD_LOGIC;
  signal u_ddr_calib_top_n_198 : STD_LOGIC;
  signal u_ddr_calib_top_n_199 : STD_LOGIC;
  signal u_ddr_calib_top_n_200 : STD_LOGIC;
  signal u_ddr_calib_top_n_201 : STD_LOGIC;
  signal u_ddr_calib_top_n_202 : STD_LOGIC;
  signal u_ddr_calib_top_n_34 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of u_ddr_calib_top_n_34 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_34 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of u_ddr_calib_top_n_34 : signal is "10";
  signal u_ddr_calib_top_n_35 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_35 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_35 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_35 : signal is "10";
  signal u_ddr_calib_top_n_36 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_36 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_36 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_36 : signal is "10";
  signal u_ddr_calib_top_n_37 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_37 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_37 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_37 : signal is "10";
  signal u_ddr_calib_top_n_38 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_38 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_38 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_38 : signal is "10";
  signal u_ddr_calib_top_n_39 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_39 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_39 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_39 : signal is "10";
  signal u_ddr_calib_top_n_40 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_40 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_40 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_40 : signal is "10";
  signal u_ddr_calib_top_n_41 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_41 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_41 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_41 : signal is "10";
  signal u_ddr_calib_top_n_42 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_42 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_42 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_42 : signal is "10";
  signal u_ddr_calib_top_n_43 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_43 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_43 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_43 : signal is "10";
  signal u_ddr_calib_top_n_44 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_44 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_44 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_44 : signal is "10";
  signal u_ddr_calib_top_n_45 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_45 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_45 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_45 : signal is "10";
  signal u_ddr_calib_top_n_46 : STD_LOGIC;
  attribute MAX_FANOUT of u_ddr_calib_top_n_46 : signal is "50";
  attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_46 : signal is "found";
  attribute syn_maxfan of u_ddr_calib_top_n_46 : signal is "10";
  signal u_ddr_calib_top_n_58 : STD_LOGIC;
  signal u_ddr_calib_top_n_64 : STD_LOGIC;
  signal u_ddr_calib_top_n_65 : STD_LOGIC;
  signal u_ddr_calib_top_n_66 : STD_LOGIC;
  signal u_ddr_calib_top_n_67 : STD_LOGIC;
  signal u_ddr_calib_top_n_68 : STD_LOGIC;
  signal u_ddr_calib_top_n_69 : STD_LOGIC;
  signal u_ddr_calib_top_n_70 : STD_LOGIC;
  signal u_ddr_calib_top_n_71 : STD_LOGIC;
  signal u_ddr_calib_top_n_72 : STD_LOGIC;
  signal u_ddr_calib_top_n_73 : STD_LOGIC;
  signal u_ddr_calib_top_n_74 : STD_LOGIC;
  signal u_ddr_calib_top_n_75 : STD_LOGIC;
  signal u_ddr_calib_top_n_76 : STD_LOGIC;
  signal u_ddr_calib_top_n_77 : STD_LOGIC;
  signal u_ddr_calib_top_n_78 : STD_LOGIC;
  signal u_ddr_calib_top_n_81 : STD_LOGIC;
  signal u_ddr_calib_top_n_82 : STD_LOGIC;
  signal u_ddr_calib_top_n_87 : STD_LOGIC;
  signal u_ddr_calib_top_n_88 : STD_LOGIC;
  signal u_ddr_calib_top_n_89 : STD_LOGIC;
  signal u_ddr_calib_top_n_90 : STD_LOGIC;
  signal u_ddr_calib_top_n_91 : STD_LOGIC;
  signal u_ddr_calib_top_n_92 : STD_LOGIC;
  signal u_ddr_calib_top_n_93 : STD_LOGIC;
  signal u_ddr_calib_top_n_94 : STD_LOGIC;
  signal u_ddr_calib_top_n_95 : STD_LOGIC;
  signal u_ddr_calib_top_n_96 : STD_LOGIC;
  signal u_ddr_calib_top_n_97 : STD_LOGIC;
  signal u_ddr_calib_top_n_98 : STD_LOGIC;
  signal u_ddr_calib_top_n_99 : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_read_val\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_rst_primitives\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable105_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en117_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable102_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc108_out\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ififo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\ : STD_LOGIC_VECTOR ( 53 downto 8 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\ : STD_LOGIC_VECTOR ( 75 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\ : STD_LOGIC_VECTOR ( 43 downto 8 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_rst_primitives\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ofifo_rst_reg0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\ : STD_LOGIC;
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\ : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_120 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_121 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_123 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_124 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1248 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1249 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_125 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1250 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1251 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1252 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1253 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1254 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1255 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1256 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1257 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1258 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1259 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_126 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1260 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1261 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1262 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1263 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1264 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1265 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1266 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1267 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1268 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1269 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_127 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1270 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1271 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1272 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1273 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1274 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1275 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1276 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1277 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1278 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1279 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_128 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1280 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1281 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1282 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1283 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1284 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1285 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1286 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1287 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1288 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1289 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_129 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1290 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1291 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1292 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1293 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1294 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1295 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1296 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1297 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1298 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1299 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1300 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1301 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1302 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1303 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1304 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1305 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1306 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1307 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1308 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1309 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1310 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1311 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1312 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1313 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1314 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1315 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1316 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1317 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1318 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1319 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1320 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1321 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1322 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1323 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1324 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1325 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1326 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1327 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1328 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1329 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1330 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1331 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1332 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1333 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1334 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1335 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1336 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1337 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1338 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1339 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1340 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1341 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1342 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1343 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1344 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1345 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1346 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1347 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1348 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1349 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1350 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1351 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1352 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1353 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1354 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1355 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1356 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1357 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1358 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1359 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1360 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1361 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1362 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1363 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1364 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1365 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1366 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1367 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1368 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1369 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1370 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1371 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1372 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1373 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1374 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1375 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1376 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1377 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1378 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1379 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1380 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1381 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1382 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1383 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1384 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1385 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1386 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1387 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1388 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1389 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1390 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1391 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1392 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1393 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1394 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1395 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1396 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1397 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1398 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1399 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1400 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1401 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1402 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1403 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1404 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1405 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1406 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1407 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1408 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1409 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1410 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1411 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1412 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1413 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1414 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1415 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1416 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1417 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1418 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1419 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1420 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1421 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1422 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1423 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1424 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1425 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1426 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1427 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1428 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1429 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1430 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1431 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1432 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1433 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1434 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1435 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1436 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1437 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1438 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1439 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1440 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1441 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1442 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1443 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1444 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1445 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1446 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1447 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1448 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1449 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1450 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1451 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1452 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1453 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1454 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1455 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1456 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1457 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1458 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1459 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1460 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1461 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1462 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1463 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1464 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1465 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1466 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1467 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1468 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1469 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1470 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1471 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1472 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1473 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1474 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1475 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1476 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1477 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1478 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1479 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1480 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1481 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1482 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1483 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1484 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1485 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1486 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1487 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1488 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1489 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1490 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1491 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1492 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1493 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1494 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1495 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1496 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1497 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1498 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1499 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1500 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1501 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1502 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1503 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1504 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1505 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1506 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1507 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1508 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1509 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1510 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1511 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1512 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1513 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1514 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1515 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1516 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1517 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1518 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1519 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1520 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1521 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1522 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1523 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1524 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1525 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1526 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1527 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1528 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1529 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1530 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1531 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1532 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1533 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1534 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1535 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1536 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1537 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1538 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1539 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1540 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1541 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1542 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1543 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1544 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1545 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1546 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1547 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1548 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1549 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1550 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1551 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1552 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1553 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1554 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1555 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1556 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1557 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1558 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1559 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1560 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1561 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1562 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1563 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1564 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1565 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1566 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1567 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1568 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1569 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1570 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1571 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1572 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1573 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1574 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1575 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1576 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1577 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1578 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1579 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1580 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1581 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1582 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1583 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1584 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1585 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1586 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1587 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1588 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1589 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1590 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1591 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1592 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1593 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1594 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1595 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1596 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1597 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1598 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1599 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1600 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1602 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1603 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1604 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1605 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1606 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1607 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1608 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1609 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1610 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1612 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1613 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1614 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1615 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1616 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1617 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1618 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1619 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1620 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1621 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1622 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1623 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1624 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1625 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1626 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1627 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1628 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1629 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1630 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1631 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1632 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1633 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1634 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1635 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1636 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1637 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1638 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1639 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1640 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1641 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1642 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1643 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1644 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1645 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1646 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1647 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1648 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1649 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1650 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1651 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1652 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1653 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1654 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1655 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1656 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1657 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1658 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1659 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1660 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1661 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1662 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1663 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1664 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1665 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1666 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1667 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1668 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1669 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1670 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1671 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1672 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1673 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_1674 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_2 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_3 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_4 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_5 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_6 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_661 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_665 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_666 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_667 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_668 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_669 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_670 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_671 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_672 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_673 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_674 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_675 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_676 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_677 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_678 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_679 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_680 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_681 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_682 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_683 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_684 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_685 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_686 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_687 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_688 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_689 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_690 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_691 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_692 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_693 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_694 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_695 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_696 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_697 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_698 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_699 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_7 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_700 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_701 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_702 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_703 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_704 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_705 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_706 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_707 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_708 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_709 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_710 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_711 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_712 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_713 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_714 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_715 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_716 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_717 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_718 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_719 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_720 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_721 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_722 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_723 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_724 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_725 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_726 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_727 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_728 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_729 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_730 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_731 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_732 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_733 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_734 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_735 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_74 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_8 : STD_LOGIC;
  signal u_ddr_mc_phy_wrapper_n_9 : STD_LOGIC;
  signal \u_ddr_phy_init/cnt_pwron_cke_done_r\ : STD_LOGIC;
  signal \u_ddr_phy_init/p_110_in\ : STD_LOGIC;
  signal \u_ddr_phy_wrcal/p_0_out\ : STD_LOGIC;
begin
  app_zq_r_reg <= \^app_zq_r_reg\;
  init_calib_complete <= \^init_calib_complete\;
  \not_strict_mode.app_rd_data_reg[0]\ <= \^not_strict_mode.app_rd_data_reg[0]\;
  \not_strict_mode.app_rd_data_reg[10]\ <= \^not_strict_mode.app_rd_data_reg[10]\;
  \not_strict_mode.app_rd_data_reg[11]\ <= \^not_strict_mode.app_rd_data_reg[11]\;
  \not_strict_mode.app_rd_data_reg[12]\ <= \^not_strict_mode.app_rd_data_reg[12]\;
  \not_strict_mode.app_rd_data_reg[13]\ <= \^not_strict_mode.app_rd_data_reg[13]\;
  \not_strict_mode.app_rd_data_reg[14]\ <= \^not_strict_mode.app_rd_data_reg[14]\;
  \not_strict_mode.app_rd_data_reg[15]\ <= \^not_strict_mode.app_rd_data_reg[15]\;
  \not_strict_mode.app_rd_data_reg[16]\ <= \^not_strict_mode.app_rd_data_reg[16]\;
  \not_strict_mode.app_rd_data_reg[17]\ <= \^not_strict_mode.app_rd_data_reg[17]\;
  \not_strict_mode.app_rd_data_reg[18]\ <= \^not_strict_mode.app_rd_data_reg[18]\;
  \not_strict_mode.app_rd_data_reg[19]\ <= \^not_strict_mode.app_rd_data_reg[19]\;
  \not_strict_mode.app_rd_data_reg[1]\ <= \^not_strict_mode.app_rd_data_reg[1]\;
  \not_strict_mode.app_rd_data_reg[20]\ <= \^not_strict_mode.app_rd_data_reg[20]\;
  \not_strict_mode.app_rd_data_reg[21]\ <= \^not_strict_mode.app_rd_data_reg[21]\;
  \not_strict_mode.app_rd_data_reg[22]\ <= \^not_strict_mode.app_rd_data_reg[22]\;
  \not_strict_mode.app_rd_data_reg[23]\ <= \^not_strict_mode.app_rd_data_reg[23]\;
  \not_strict_mode.app_rd_data_reg[24]\ <= \^not_strict_mode.app_rd_data_reg[24]\;
  \not_strict_mode.app_rd_data_reg[25]\ <= \^not_strict_mode.app_rd_data_reg[25]\;
  \not_strict_mode.app_rd_data_reg[26]\ <= \^not_strict_mode.app_rd_data_reg[26]\;
  \not_strict_mode.app_rd_data_reg[27]\ <= \^not_strict_mode.app_rd_data_reg[27]\;
  \not_strict_mode.app_rd_data_reg[28]\ <= \^not_strict_mode.app_rd_data_reg[28]\;
  \not_strict_mode.app_rd_data_reg[29]\ <= \^not_strict_mode.app_rd_data_reg[29]\;
  \not_strict_mode.app_rd_data_reg[2]\ <= \^not_strict_mode.app_rd_data_reg[2]\;
  \not_strict_mode.app_rd_data_reg[30]\ <= \^not_strict_mode.app_rd_data_reg[30]\;
  \not_strict_mode.app_rd_data_reg[31]\ <= \^not_strict_mode.app_rd_data_reg[31]\;
  \not_strict_mode.app_rd_data_reg[32]\ <= \^not_strict_mode.app_rd_data_reg[32]\;
  \not_strict_mode.app_rd_data_reg[33]\ <= \^not_strict_mode.app_rd_data_reg[33]\;
  \not_strict_mode.app_rd_data_reg[34]\ <= \^not_strict_mode.app_rd_data_reg[34]\;
  \not_strict_mode.app_rd_data_reg[35]\ <= \^not_strict_mode.app_rd_data_reg[35]\;
  \not_strict_mode.app_rd_data_reg[36]\ <= \^not_strict_mode.app_rd_data_reg[36]\;
  \not_strict_mode.app_rd_data_reg[37]\ <= \^not_strict_mode.app_rd_data_reg[37]\;
  \not_strict_mode.app_rd_data_reg[38]\ <= \^not_strict_mode.app_rd_data_reg[38]\;
  \not_strict_mode.app_rd_data_reg[39]\ <= \^not_strict_mode.app_rd_data_reg[39]\;
  \not_strict_mode.app_rd_data_reg[3]\ <= \^not_strict_mode.app_rd_data_reg[3]\;
  \not_strict_mode.app_rd_data_reg[40]\ <= \^not_strict_mode.app_rd_data_reg[40]\;
  \not_strict_mode.app_rd_data_reg[41]\ <= \^not_strict_mode.app_rd_data_reg[41]\;
  \not_strict_mode.app_rd_data_reg[42]\ <= \^not_strict_mode.app_rd_data_reg[42]\;
  \not_strict_mode.app_rd_data_reg[43]\ <= \^not_strict_mode.app_rd_data_reg[43]\;
  \not_strict_mode.app_rd_data_reg[44]\ <= \^not_strict_mode.app_rd_data_reg[44]\;
  \not_strict_mode.app_rd_data_reg[45]\ <= \^not_strict_mode.app_rd_data_reg[45]\;
  \not_strict_mode.app_rd_data_reg[46]\ <= \^not_strict_mode.app_rd_data_reg[46]\;
  \not_strict_mode.app_rd_data_reg[47]\ <= \^not_strict_mode.app_rd_data_reg[47]\;
  \not_strict_mode.app_rd_data_reg[48]\ <= \^not_strict_mode.app_rd_data_reg[48]\;
  \not_strict_mode.app_rd_data_reg[49]\ <= \^not_strict_mode.app_rd_data_reg[49]\;
  \not_strict_mode.app_rd_data_reg[4]\ <= \^not_strict_mode.app_rd_data_reg[4]\;
  \not_strict_mode.app_rd_data_reg[50]\ <= \^not_strict_mode.app_rd_data_reg[50]\;
  \not_strict_mode.app_rd_data_reg[51]\ <= \^not_strict_mode.app_rd_data_reg[51]\;
  \not_strict_mode.app_rd_data_reg[52]\ <= \^not_strict_mode.app_rd_data_reg[52]\;
  \not_strict_mode.app_rd_data_reg[53]\ <= \^not_strict_mode.app_rd_data_reg[53]\;
  \not_strict_mode.app_rd_data_reg[54]\ <= \^not_strict_mode.app_rd_data_reg[54]\;
  \not_strict_mode.app_rd_data_reg[55]\ <= \^not_strict_mode.app_rd_data_reg[55]\;
  \not_strict_mode.app_rd_data_reg[56]\ <= \^not_strict_mode.app_rd_data_reg[56]\;
  \not_strict_mode.app_rd_data_reg[57]\ <= \^not_strict_mode.app_rd_data_reg[57]\;
  \not_strict_mode.app_rd_data_reg[58]\ <= \^not_strict_mode.app_rd_data_reg[58]\;
  \not_strict_mode.app_rd_data_reg[59]\ <= \^not_strict_mode.app_rd_data_reg[59]\;
  \not_strict_mode.app_rd_data_reg[5]\ <= \^not_strict_mode.app_rd_data_reg[5]\;
  \not_strict_mode.app_rd_data_reg[60]\ <= \^not_strict_mode.app_rd_data_reg[60]\;
  \not_strict_mode.app_rd_data_reg[61]\ <= \^not_strict_mode.app_rd_data_reg[61]\;
  \not_strict_mode.app_rd_data_reg[62]\ <= \^not_strict_mode.app_rd_data_reg[62]\;
  \not_strict_mode.app_rd_data_reg[63]\ <= \^not_strict_mode.app_rd_data_reg[63]\;
  \not_strict_mode.app_rd_data_reg[6]\ <= \^not_strict_mode.app_rd_data_reg[6]\;
  \not_strict_mode.app_rd_data_reg[7]\ <= \^not_strict_mode.app_rd_data_reg[7]\;
  \not_strict_mode.app_rd_data_reg[8]\ <= \^not_strict_mode.app_rd_data_reg[8]\;
  \not_strict_mode.app_rd_data_reg[9]\ <= \^not_strict_mode.app_rd_data_reg[9]\;
u_ddr_calib_top: entity work.mig_7series_0_mig_7series_v2_3_ddr_calib_top
     port map (
      A_rst_primitives => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_rst_primitives\,
      A_rst_primitives_15 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_rst_primitives\,
      CLK => CLK,
      COUNTERLOADVAL(5) => u_ddr_calib_top_n_65,
      COUNTERLOADVAL(4) => u_ddr_calib_top_n_66,
      COUNTERLOADVAL(3) => u_ddr_calib_top_n_67,
      COUNTERLOADVAL(2) => u_ddr_calib_top_n_68,
      COUNTERLOADVAL(1) => u_ddr_calib_top_n_69,
      COUNTERLOADVAL(0) => u_ddr_calib_top_n_70,
      COUNTERREADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_read_val\(5 downto 0),
      D(0) => D(0),
      D0(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0\(1),
      D1(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(3 downto 0),
      D2(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(3 downto 0),
      D3(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3 downto 0),
      D4(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(3 downto 0),
      D5(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(5),
      D5(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(1),
      D6(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(5),
      D7(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(3 downto 0),
      D8(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(3 downto 0),
      D9(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(3 downto 0),
      D_po_coarse_enable105_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable105_out\,
      D_po_counter_read_en117_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en117_out\,
      D_po_fine_enable102_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable102_out\,
      D_po_fine_inc108_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc108_out\,
      LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      LD0_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\,
      LD0_3 => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_4 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_6 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_8 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      Q(3 downto 2) => calib_sel(4 downto 3),
      Q(1 downto 0) => calib_sel(1 downto 0),
      SR(1 downto 0) => SR(1 downto 0),
      SS(0) => SS(0),
      app_zq_r_reg => \^app_zq_r_reg\,
      clear => clear,
      \cmd_pipe_plus.mc_data_offset_1_reg[0]\ => \cmd_pipe_plus.mc_data_offset_1_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\ => \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_1_reg[1]\ => \cmd_pipe_plus.mc_data_offset_1_reg[1]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\ => \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\,
      \cmd_pipe_plus.mc_data_offset_1_reg[2]\ => \cmd_pipe_plus.mc_data_offset_1_reg[2]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0),
      \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\(0) => \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\(0),
      \cmd_pipe_plus.mc_data_offset_1_reg[4]\ => \cmd_pipe_plus.mc_data_offset_1_reg[4]\,
      \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\ => \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\ => \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ => \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[1]\ => \cmd_pipe_plus.mc_data_offset_2_reg[1]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\ => \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[2]\ => \cmd_pipe_plus.mc_data_offset_2_reg[2]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0),
      \cmd_pipe_plus.mc_data_offset_2_reg[4]\ => \cmd_pipe_plus.mc_data_offset_2_reg[4]\,
      \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\ => \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\ => \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[0]\ => \cmd_pipe_plus.mc_data_offset_reg[0]\,
      \cmd_pipe_plus.mc_data_offset_reg[0]_0\ => \cmd_pipe_plus.mc_data_offset_reg[0]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[1]\ => \cmd_pipe_plus.mc_data_offset_reg[1]\,
      \cmd_pipe_plus.mc_data_offset_reg[1]_0\ => \cmd_pipe_plus.mc_data_offset_reg[1]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[2]\ => \cmd_pipe_plus.mc_data_offset_reg[2]\,
      \cmd_pipe_plus.mc_data_offset_reg[3]\(0) => \cmd_pipe_plus.mc_data_offset_reg[3]\(0),
      \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0) => \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0),
      \cmd_pipe_plus.mc_data_offset_reg[4]\ => \cmd_pipe_plus.mc_data_offset_reg[4]\,
      \cmd_pipe_plus.mc_data_offset_reg[4]_0\ => \cmd_pipe_plus.mc_data_offset_reg[4]_0\,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_reg[5]_0\ => \cmd_pipe_plus.mc_data_offset_reg[5]_0\,
      \cmd_pipe_plus.mc_we_n_reg[1]\(0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1),
      cnt_pwron_cke_done_r => \u_ddr_phy_init/cnt_pwron_cke_done_r\,
      \complex_row1_rd_cnt_reg[1]\ => \complex_row1_rd_cnt_reg[1]\,
      \data_offset_1_i1_reg[5]\(5 downto 0) => data_offset_1(5 downto 0),
      \data_offset_2_i1_reg[5]\(5 downto 0) => data_offset_2(5 downto 0),
      \device_temp_r_reg[11]\(11 downto 0) => \device_temp_r_reg[11]\(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => u_ddr_calib_top_n_72,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => u_ddr_calib_top_n_95,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => u_ddr_calib_top_n_105,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => u_ddr_calib_top_n_109,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => u_ddr_calib_top_n_113,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => u_ddr_calib_top_n_143,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ => u_ddr_calib_top_n_151,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ => u_ddr_calib_top_n_155,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\ => \^not_strict_mode.app_rd_data_reg[31]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\ => \^not_strict_mode.app_rd_data_reg[39]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\ => \^not_strict_mode.app_rd_data_reg[63]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\ => \^not_strict_mode.app_rd_data_reg[6]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\ => \^not_strict_mode.app_rd_data_reg[14]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\ => \^not_strict_mode.app_rd_data_reg[22]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2\ => \^not_strict_mode.app_rd_data_reg[29]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3\ => \^not_strict_mode.app_rd_data_reg[37]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4\ => \^not_strict_mode.app_rd_data_reg[46]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5\ => \^not_strict_mode.app_rd_data_reg[54]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6\ => \^not_strict_mode.app_rd_data_reg[61]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\ => \^not_strict_mode.app_rd_data_reg[5]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\ => \^not_strict_mode.app_rd_data_reg[13]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\ => \^not_strict_mode.app_rd_data_reg[21]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\ => \^not_strict_mode.app_rd_data_reg[28]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3\ => \^not_strict_mode.app_rd_data_reg[36]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4\ => \^not_strict_mode.app_rd_data_reg[45]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5\ => \^not_strict_mode.app_rd_data_reg[53]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6\ => \^not_strict_mode.app_rd_data_reg[60]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ => \^not_strict_mode.app_rd_data_reg[4]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ => \^not_strict_mode.app_rd_data_reg[12]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\ => \^not_strict_mode.app_rd_data_reg[20]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2\ => \^not_strict_mode.app_rd_data_reg[27]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3\ => \^not_strict_mode.app_rd_data_reg[35]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4\ => \^not_strict_mode.app_rd_data_reg[44]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5\ => \^not_strict_mode.app_rd_data_reg[52]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6\ => \^not_strict_mode.app_rd_data_reg[59]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ => \^not_strict_mode.app_rd_data_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ => \^not_strict_mode.app_rd_data_reg[11]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1\ => \^not_strict_mode.app_rd_data_reg[26]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2\ => \^not_strict_mode.app_rd_data_reg[34]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3\ => \^not_strict_mode.app_rd_data_reg[43]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4\ => \^not_strict_mode.app_rd_data_reg[58]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\ => \^not_strict_mode.app_rd_data_reg[2]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\ => \^not_strict_mode.app_rd_data_reg[10]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\ => \^not_strict_mode.app_rd_data_reg[19]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\ => \^not_strict_mode.app_rd_data_reg[25]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\ => \^not_strict_mode.app_rd_data_reg[33]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4\ => \^not_strict_mode.app_rd_data_reg[42]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5\ => \^not_strict_mode.app_rd_data_reg[51]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6\ => \^not_strict_mode.app_rd_data_reg[57]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ => \^not_strict_mode.app_rd_data_reg[1]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ => \^not_strict_mode.app_rd_data_reg[9]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1\ => \^not_strict_mode.app_rd_data_reg[18]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2\ => \^not_strict_mode.app_rd_data_reg[24]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3\ => \^not_strict_mode.app_rd_data_reg[32]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4\ => \^not_strict_mode.app_rd_data_reg[41]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5\ => \^not_strict_mode.app_rd_data_reg[50]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6\ => \^not_strict_mode.app_rd_data_reg[56]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ => \^not_strict_mode.app_rd_data_reg[0]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ => \^not_strict_mode.app_rd_data_reg[8]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1\ => \^not_strict_mode.app_rd_data_reg[17]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2\ => \^not_strict_mode.app_rd_data_reg[40]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3\ => \^not_strict_mode.app_rd_data_reg[49]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ => \^not_strict_mode.app_rd_data_reg[16]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ => \^not_strict_mode.app_rd_data_reg[48]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\ => \^not_strict_mode.app_rd_data_reg[7]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\ => \^not_strict_mode.app_rd_data_reg[15]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\ => \^not_strict_mode.app_rd_data_reg[23]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\ => \^not_strict_mode.app_rd_data_reg[30]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\ => \^not_strict_mode.app_rd_data_reg[38]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_4\ => \^not_strict_mode.app_rd_data_reg[47]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_5\ => \^not_strict_mode.app_rd_data_reg[55]\,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_6\ => \^not_strict_mode.app_rd_data_reg[62]\,
      dqs_po_en_stg2_f_reg => dqs_po_en_stg2_f_reg,
      \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[3]\,
      fine_dly_dec_done_r1_reg => fine_dly_dec_done_r1_reg,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => u_ddr_calib_top_n_174,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(2 downto 0) => po_stg2_wrcal_cnt(2 downto 0),
      \grant_r_reg[3]\ => \grant_r_reg[3]\,
      idelay_inc => idelay_inc,
      idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_10 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_11 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_12 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_13 => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_14 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_tap_limit_r_reg => idelay_tap_limit_r_reg,
      ififo_rst_reg => u_ddr_calib_top_n_97,
      ififo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ififo_rst_reg0\,
      ififo_rst_reg_0 => u_ddr_calib_top_n_107,
      ififo_rst_reg_1 => u_ddr_calib_top_n_111,
      ififo_rst_reg_2 => u_ddr_calib_top_n_115,
      ififo_rst_reg_3 => u_ddr_calib_top_n_145,
      ififo_rst_reg_4 => u_ddr_calib_top_n_153,
      ififo_rst_reg_5 => u_ddr_calib_top_n_157,
      in0 => u_ddr_mc_phy_wrapper_n_1248,
      init_calib_complete_reg_0(15 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(43 downto 40),
      init_calib_complete_reg_0(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(27 downto 24),
      init_calib_complete_reg_0(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(19 downto 16),
      init_calib_complete_reg_0(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(11 downto 8),
      \maint_prescaler.maint_prescaler_r1\ => \maint_prescaler.maint_prescaler_r1\,
      mc_address(38 downto 0) => mc_address(38 downto 0),
      mc_bank(8 downto 0) => mc_bank(8 downto 0),
      mc_cas_n(0) => mc_cas_n(1),
      mc_cke(0) => mc_cke(0),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(0) => mc_ras_n(1),
      mc_wrdata_en => mc_wrdata_en,
      mem_out(10) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(53),
      mem_out(9) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(45),
      mem_out(8) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(41),
      mem_out(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(27 downto 24),
      mem_out(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(11 downto 8),
      mux_reset_n => mux_reset_n,
      mux_wrdata(415 downto 288) => mux_wrdata(511 downto 384),
      mux_wrdata(287 downto 285) => mux_wrdata(382 downto 380),
      mux_wrdata(284 downto 282) => mux_wrdata(378 downto 376),
      mux_wrdata(281 downto 279) => mux_wrdata(374 downto 372),
      mux_wrdata(278 downto 276) => mux_wrdata(370 downto 368),
      mux_wrdata(275 downto 273) => mux_wrdata(366 downto 364),
      mux_wrdata(272 downto 270) => mux_wrdata(362 downto 360),
      mux_wrdata(269 downto 267) => mux_wrdata(358 downto 356),
      mux_wrdata(266 downto 264) => mux_wrdata(354 downto 352),
      mux_wrdata(263 downto 261) => mux_wrdata(350 downto 348),
      mux_wrdata(260 downto 258) => mux_wrdata(346 downto 344),
      mux_wrdata(257 downto 255) => mux_wrdata(342 downto 340),
      mux_wrdata(254 downto 252) => mux_wrdata(338 downto 336),
      mux_wrdata(251 downto 249) => mux_wrdata(334 downto 332),
      mux_wrdata(248 downto 246) => mux_wrdata(330 downto 328),
      mux_wrdata(245 downto 243) => mux_wrdata(326 downto 324),
      mux_wrdata(242 downto 239) => mux_wrdata(322 downto 319),
      mux_wrdata(238 downto 236) => mux_wrdata(317 downto 315),
      mux_wrdata(235 downto 233) => mux_wrdata(313 downto 311),
      mux_wrdata(232 downto 230) => mux_wrdata(309 downto 307),
      mux_wrdata(229 downto 227) => mux_wrdata(305 downto 303),
      mux_wrdata(226 downto 224) => mux_wrdata(301 downto 299),
      mux_wrdata(223 downto 221) => mux_wrdata(297 downto 295),
      mux_wrdata(220 downto 218) => mux_wrdata(293 downto 291),
      mux_wrdata(217 downto 215) => mux_wrdata(289 downto 287),
      mux_wrdata(214 downto 212) => mux_wrdata(285 downto 283),
      mux_wrdata(211 downto 209) => mux_wrdata(281 downto 279),
      mux_wrdata(208 downto 206) => mux_wrdata(277 downto 275),
      mux_wrdata(205 downto 203) => mux_wrdata(273 downto 271),
      mux_wrdata(202 downto 200) => mux_wrdata(269 downto 267),
      mux_wrdata(199 downto 197) => mux_wrdata(265 downto 263),
      mux_wrdata(196 downto 194) => mux_wrdata(261 downto 259),
      mux_wrdata(193 downto 191) => mux_wrdata(257 downto 255),
      mux_wrdata(190 downto 188) => mux_wrdata(253 downto 251),
      mux_wrdata(187 downto 185) => mux_wrdata(249 downto 247),
      mux_wrdata(184 downto 182) => mux_wrdata(245 downto 243),
      mux_wrdata(181 downto 179) => mux_wrdata(241 downto 239),
      mux_wrdata(178 downto 176) => mux_wrdata(237 downto 235),
      mux_wrdata(175 downto 173) => mux_wrdata(233 downto 231),
      mux_wrdata(172 downto 170) => mux_wrdata(229 downto 227),
      mux_wrdata(169 downto 167) => mux_wrdata(225 downto 223),
      mux_wrdata(166 downto 164) => mux_wrdata(221 downto 219),
      mux_wrdata(163 downto 161) => mux_wrdata(217 downto 215),
      mux_wrdata(160 downto 158) => mux_wrdata(213 downto 211),
      mux_wrdata(157 downto 155) => mux_wrdata(209 downto 207),
      mux_wrdata(154 downto 152) => mux_wrdata(205 downto 203),
      mux_wrdata(151 downto 149) => mux_wrdata(201 downto 199),
      mux_wrdata(148 downto 146) => mux_wrdata(197 downto 195),
      mux_wrdata(145 downto 142) => mux_wrdata(193 downto 190),
      mux_wrdata(141 downto 139) => mux_wrdata(188 downto 186),
      mux_wrdata(138 downto 136) => mux_wrdata(184 downto 182),
      mux_wrdata(135 downto 133) => mux_wrdata(180 downto 178),
      mux_wrdata(132 downto 130) => mux_wrdata(176 downto 174),
      mux_wrdata(129 downto 127) => mux_wrdata(172 downto 170),
      mux_wrdata(126 downto 124) => mux_wrdata(168 downto 166),
      mux_wrdata(123 downto 121) => mux_wrdata(164 downto 162),
      mux_wrdata(120 downto 118) => mux_wrdata(160 downto 158),
      mux_wrdata(117 downto 115) => mux_wrdata(156 downto 154),
      mux_wrdata(114 downto 112) => mux_wrdata(152 downto 150),
      mux_wrdata(111 downto 109) => mux_wrdata(148 downto 146),
      mux_wrdata(108 downto 106) => mux_wrdata(144 downto 142),
      mux_wrdata(105 downto 103) => mux_wrdata(140 downto 138),
      mux_wrdata(102 downto 100) => mux_wrdata(136 downto 134),
      mux_wrdata(99 downto 97) => mux_wrdata(132 downto 130),
      mux_wrdata(96 downto 32) => mux_wrdata(128 downto 64),
      mux_wrdata(31 downto 30) => mux_wrdata(62 downto 61),
      mux_wrdata(29 downto 28) => mux_wrdata(58 downto 57),
      mux_wrdata(27 downto 26) => mux_wrdata(54 downto 53),
      mux_wrdata(25 downto 24) => mux_wrdata(50 downto 49),
      mux_wrdata(23 downto 22) => mux_wrdata(46 downto 45),
      mux_wrdata(21 downto 20) => mux_wrdata(42 downto 41),
      mux_wrdata(19 downto 18) => mux_wrdata(38 downto 37),
      mux_wrdata(17 downto 16) => mux_wrdata(34 downto 33),
      mux_wrdata(15 downto 14) => mux_wrdata(30 downto 29),
      mux_wrdata(13 downto 12) => mux_wrdata(26 downto 25),
      mux_wrdata(11 downto 10) => mux_wrdata(22 downto 21),
      mux_wrdata(9 downto 8) => mux_wrdata(18 downto 17),
      mux_wrdata(7 downto 6) => mux_wrdata(14 downto 13),
      mux_wrdata(5 downto 4) => mux_wrdata(10 downto 9),
      mux_wrdata(3 downto 2) => mux_wrdata(6 downto 5),
      mux_wrdata(1 downto 0) => mux_wrdata(2 downto 1),
      mux_wrdata_mask(63 downto 0) => mux_wrdata_mask(63 downto 0),
      \my_empty_reg[1]\ => u_ddr_mc_phy_wrapper_n_74,
      \my_empty_reg[1]_0\ => u_ddr_mc_phy_wrapper_n_120,
      \my_empty_reg[1]_1\ => u_ddr_mc_phy_wrapper_n_661,
      \my_empty_reg[1]_2\ => u_ddr_mc_phy_wrapper_n_127,
      \my_empty_reg[1]_3\ => u_ddr_mc_phy_wrapper_n_128,
      \my_empty_reg[1]_4\ => u_ddr_mc_phy_wrapper_n_129,
      \my_empty_reg[1]_5\ => u_ddr_mc_phy_wrapper_n_121,
      \my_empty_reg[1]_6\ => u_ddr_mc_phy_wrapper_n_123,
      \my_empty_reg[1]_7\ => u_ddr_mc_phy_wrapper_n_124,
      \my_empty_reg[1]_8\ => u_ddr_mc_phy_wrapper_n_125,
      \my_empty_reg[1]_9\ => u_ddr_mc_phy_wrapper_n_126,
      \my_empty_reg[7]\ => u_ddr_calib_top_n_34,
      \my_empty_reg[7]_0\ => u_ddr_calib_top_n_35,
      \my_empty_reg[7]_1\ => u_ddr_calib_top_n_36,
      \my_empty_reg[7]_10\ => \my_empty_reg[7]\,
      \my_empty_reg[7]_11\ => \my_empty_reg[7]_0\,
      \my_empty_reg[7]_12\ => \my_empty_reg[7]_1\,
      \my_empty_reg[7]_13\ => \my_empty_reg[7]_2\,
      \my_empty_reg[7]_14\ => \my_empty_reg[7]_3\,
      \my_empty_reg[7]_15\ => \my_empty_reg[7]_4\,
      \my_empty_reg[7]_16\ => \my_empty_reg[7]_5\,
      \my_empty_reg[7]_17\ => \my_empty_reg[7]_6\,
      \my_empty_reg[7]_18\ => \my_empty_reg[7]_7\,
      \my_empty_reg[7]_19\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(7 downto 6),
      \my_empty_reg[7]_19\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(4 downto 2),
      \my_empty_reg[7]_2\ => u_ddr_calib_top_n_37,
      \my_empty_reg[7]_20\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 5),
      \my_empty_reg[7]_20\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(2),
      \my_empty_reg[7]_20\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(0),
      \my_empty_reg[7]_21\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 5),
      \my_empty_reg[7]_21\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3),
      \my_empty_reg[7]_21\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(1 downto 0),
      \my_empty_reg[7]_22\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 6),
      \my_empty_reg[7]_22\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(4 downto 2),
      \my_empty_reg[7]_23\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 5),
      \my_empty_reg[7]_23\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(2),
      \my_empty_reg[7]_23\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(0),
      \my_empty_reg[7]_24\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 5),
      \my_empty_reg[7]_24\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3),
      \my_empty_reg[7]_24\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(1 downto 0),
      \my_empty_reg[7]_25\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(7 downto 6),
      \my_empty_reg[7]_25\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(4 downto 2),
      \my_empty_reg[7]_26\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 5),
      \my_empty_reg[7]_26\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(2),
      \my_empty_reg[7]_26\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(0),
      \my_empty_reg[7]_27\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 5),
      \my_empty_reg[7]_27\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3),
      \my_empty_reg[7]_27\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(1 downto 0),
      \my_empty_reg[7]_28\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 6),
      \my_empty_reg[7]_28\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(4 downto 2),
      \my_empty_reg[7]_29\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 5),
      \my_empty_reg[7]_29\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(2),
      \my_empty_reg[7]_29\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(0),
      \my_empty_reg[7]_3\ => u_ddr_calib_top_n_38,
      \my_empty_reg[7]_30\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 5),
      \my_empty_reg[7]_30\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3),
      \my_empty_reg[7]_30\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(1 downto 0),
      \my_empty_reg[7]_31\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 6),
      \my_empty_reg[7]_31\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(4 downto 2),
      \my_empty_reg[7]_32\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 5),
      \my_empty_reg[7]_32\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(2),
      \my_empty_reg[7]_32\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(0),
      \my_empty_reg[7]_33\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 5),
      \my_empty_reg[7]_33\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(3),
      \my_empty_reg[7]_33\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(1 downto 0),
      \my_empty_reg[7]_34\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 6),
      \my_empty_reg[7]_34\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(4 downto 2),
      \my_empty_reg[7]_35\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 5),
      \my_empty_reg[7]_35\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(2),
      \my_empty_reg[7]_35\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(0),
      \my_empty_reg[7]_36\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 5),
      \my_empty_reg[7]_36\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(3),
      \my_empty_reg[7]_36\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(1 downto 0),
      \my_empty_reg[7]_37\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(7 downto 6),
      \my_empty_reg[7]_37\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(4 downto 2),
      \my_empty_reg[7]_38\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 5),
      \my_empty_reg[7]_38\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(2),
      \my_empty_reg[7]_38\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(0),
      \my_empty_reg[7]_39\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 5),
      \my_empty_reg[7]_39\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3),
      \my_empty_reg[7]_39\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(1 downto 0),
      \my_empty_reg[7]_4\ => u_ddr_calib_top_n_39,
      \my_empty_reg[7]_40\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 6),
      \my_empty_reg[7]_40\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(4 downto 2),
      \my_empty_reg[7]_41\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 5),
      \my_empty_reg[7]_41\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(2),
      \my_empty_reg[7]_41\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(0),
      \my_empty_reg[7]_42\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 5),
      \my_empty_reg[7]_42\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3),
      \my_empty_reg[7]_42\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(1 downto 0),
      \my_empty_reg[7]_43\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(7 downto 6),
      \my_empty_reg[7]_43\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(4 downto 2),
      \my_empty_reg[7]_44\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 5),
      \my_empty_reg[7]_44\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(2),
      \my_empty_reg[7]_44\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(0),
      \my_empty_reg[7]_45\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 5),
      \my_empty_reg[7]_45\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3),
      \my_empty_reg[7]_45\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(1 downto 0),
      \my_empty_reg[7]_46\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 6),
      \my_empty_reg[7]_46\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(4 downto 2),
      \my_empty_reg[7]_47\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 5),
      \my_empty_reg[7]_47\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(2),
      \my_empty_reg[7]_47\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(0),
      \my_empty_reg[7]_48\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 5),
      \my_empty_reg[7]_48\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3),
      \my_empty_reg[7]_48\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(1 downto 0),
      \my_empty_reg[7]_49\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(7 downto 6),
      \my_empty_reg[7]_49\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(4 downto 2),
      \my_empty_reg[7]_5\ => u_ddr_calib_top_n_40,
      \my_empty_reg[7]_50\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 5),
      \my_empty_reg[7]_50\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(2),
      \my_empty_reg[7]_50\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(0),
      \my_empty_reg[7]_51\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 5),
      \my_empty_reg[7]_51\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3),
      \my_empty_reg[7]_51\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(1 downto 0),
      \my_empty_reg[7]_52\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 6),
      \my_empty_reg[7]_52\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(4 downto 2),
      \my_empty_reg[7]_53\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 5),
      \my_empty_reg[7]_53\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(2),
      \my_empty_reg[7]_53\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(0),
      \my_empty_reg[7]_54\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 5),
      \my_empty_reg[7]_54\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3),
      \my_empty_reg[7]_54\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(1 downto 0),
      \my_empty_reg[7]_55\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 6),
      \my_empty_reg[7]_55\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(4 downto 2),
      \my_empty_reg[7]_56\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 5),
      \my_empty_reg[7]_56\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(2),
      \my_empty_reg[7]_56\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(0),
      \my_empty_reg[7]_57\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 5),
      \my_empty_reg[7]_57\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(3),
      \my_empty_reg[7]_57\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(1 downto 0),
      \my_empty_reg[7]_58\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 6),
      \my_empty_reg[7]_58\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(4 downto 2),
      \my_empty_reg[7]_59\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 5),
      \my_empty_reg[7]_59\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(2),
      \my_empty_reg[7]_59\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(0),
      \my_empty_reg[7]_6\ => u_ddr_calib_top_n_41,
      \my_empty_reg[7]_60\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 5),
      \my_empty_reg[7]_60\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(3),
      \my_empty_reg[7]_60\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(1 downto 0),
      \my_empty_reg[7]_61\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(7 downto 6),
      \my_empty_reg[7]_61\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(4 downto 2),
      \my_empty_reg[7]_62\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 5),
      \my_empty_reg[7]_62\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(2),
      \my_empty_reg[7]_62\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(0),
      \my_empty_reg[7]_63\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(7 downto 5),
      \my_empty_reg[7]_63\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3),
      \my_empty_reg[7]_63\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(1 downto 0),
      \my_empty_reg[7]_64\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 6),
      \my_empty_reg[7]_64\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(4 downto 2),
      \my_empty_reg[7]_65\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 5),
      \my_empty_reg[7]_65\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(2),
      \my_empty_reg[7]_65\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(0),
      \my_empty_reg[7]_66\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 5),
      \my_empty_reg[7]_66\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(3),
      \my_empty_reg[7]_66\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(1 downto 0),
      \my_empty_reg[7]_67\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(6 downto 1),
      \my_empty_reg[7]_68\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(6 downto 1),
      \my_empty_reg[7]_69\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(6 downto 1),
      \my_empty_reg[7]_7\ => u_ddr_calib_top_n_42,
      \my_empty_reg[7]_70\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(6 downto 1),
      \my_empty_reg[7]_71\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(6 downto 1),
      \my_empty_reg[7]_72\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(6 downto 1),
      \my_empty_reg[7]_73\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(6 downto 1),
      \my_empty_reg[7]_74\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(6 downto 1),
      \my_empty_reg[7]_75\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(6 downto 1),
      \my_empty_reg[7]_76\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(6 downto 1),
      \my_empty_reg[7]_77\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(6 downto 1),
      \my_empty_reg[7]_78\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(6 downto 1),
      \my_empty_reg[7]_79\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(6 downto 1),
      \my_empty_reg[7]_8\ => u_ddr_calib_top_n_43,
      \my_empty_reg[7]_80\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(6 downto 1),
      \my_empty_reg[7]_81\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(6 downto 1),
      \my_empty_reg[7]_82\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(6 downto 1),
      \my_empty_reg[7]_9\ => u_ddr_calib_top_n_44,
      new_cnt_cpt_r_reg(0) => new_cnt_cpt_r_reg(0),
      ofifo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\,
      ofifo_rst_reg0_5 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\,
      ofifo_rst_reg0_7 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ofifo_rst_reg0\,
      ofifo_rst_reg0_9 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\,
      \out\ => u_ddr_calib_top_n_1,
      p_0_out => \u_ddr_phy_wrcal/p_0_out\,
      p_110_in => \u_ddr_phy_init/p_110_in\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      \phy_ctl_wd_i1_reg[0]\ => \phy_ctl_wd_i1_reg[0]\,
      \phy_ctl_wd_i1_reg[24]\(10 downto 3) => phy_ctl_wd(24 downto 17),
      \phy_ctl_wd_i1_reg[24]\(2 downto 0) => phy_ctl_wd(2 downto 0),
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(21) => \^init_calib_complete\,
      phy_dout(20) => mux_address(41),
      phy_dout(19) => mux_address(27),
      phy_dout(18) => mux_address(13),
      phy_dout(17) => mux_address(54),
      phy_dout(16) => mux_address(40),
      phy_dout(15) => mux_address(26),
      phy_dout(14) => mux_address(12),
      phy_dout(13) => mux_address(39),
      phy_dout(12) => mux_address(11),
      phy_dout(11) => mux_address(52),
      phy_dout(10) => mux_address(38),
      phy_dout(9) => mux_address(24),
      phy_dout(8) => mux_address(10),
      phy_dout(7) => mux_address(51),
      phy_dout(6) => mux_address(37),
      phy_dout(5) => mux_address(23),
      phy_dout(4) => mux_address(9),
      phy_dout(3) => mux_address(50),
      phy_dout(2) => mux_address(36),
      phy_dout(1) => mux_address(22),
      phy_dout(0) => mux_address(8),
      phy_if_reset => phy_if_reset,
      phy_mc_go => phy_mc_go,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_cnt_dec_reg(0) => pi_cnt_dec_reg(0),
      \pi_counter_read_val_reg[0]\ => u_ddr_mc_phy_wrapper_n_669,
      \pi_counter_read_val_reg[1]\ => u_ddr_mc_phy_wrapper_n_668,
      \pi_counter_read_val_reg[2]\ => u_ddr_mc_phy_wrapper_n_666,
      \pi_counter_read_val_reg[2]_0\ => u_ddr_mc_phy_wrapper_n_665,
      \pi_counter_read_val_reg[3]\ => u_ddr_mc_phy_wrapper_n_667,
      \pi_counter_read_val_reg[4]\ => u_ddr_mc_phy_wrapper_n_671,
      \pi_counter_read_val_reg[5]\(5) => u_ddr_calib_top_n_1219,
      \pi_counter_read_val_reg[5]\(4) => u_ddr_calib_top_n_1220,
      \pi_counter_read_val_reg[5]\(3) => u_ddr_calib_top_n_1221,
      \pi_counter_read_val_reg[5]\(2) => u_ddr_calib_top_n_1222,
      \pi_counter_read_val_reg[5]\(1) => u_ddr_calib_top_n_1223,
      \pi_counter_read_val_reg[5]\(0) => u_ddr_calib_top_n_1224,
      \pi_counter_read_val_reg[5]_0\ => u_ddr_mc_phy_wrapper_n_670,
      pi_dqs_found_lanes(7) => u_ddr_mc_phy_wrapper_n_2,
      pi_dqs_found_lanes(6) => u_ddr_mc_phy_wrapper_n_3,
      pi_dqs_found_lanes(5) => u_ddr_mc_phy_wrapper_n_4,
      pi_dqs_found_lanes(4) => u_ddr_mc_phy_wrapper_n_5,
      pi_dqs_found_lanes(3) => u_ddr_mc_phy_wrapper_n_6,
      pi_dqs_found_lanes(2) => u_ddr_mc_phy_wrapper_n_7,
      pi_dqs_found_lanes(1) => u_ddr_mc_phy_wrapper_n_8,
      pi_dqs_found_lanes(0) => u_ddr_mc_phy_wrapper_n_9,
      \pi_dqs_found_lanes_r1_reg[0]\ => u_ddr_calib_top_n_87,
      \pi_dqs_found_lanes_r1_reg[0]_0\(5) => u_ddr_calib_top_n_88,
      \pi_dqs_found_lanes_r1_reg[0]_0\(4) => u_ddr_calib_top_n_89,
      \pi_dqs_found_lanes_r1_reg[0]_0\(3) => u_ddr_calib_top_n_90,
      \pi_dqs_found_lanes_r1_reg[0]_0\(2) => u_ddr_calib_top_n_91,
      \pi_dqs_found_lanes_r1_reg[0]_0\(1) => u_ddr_calib_top_n_92,
      \pi_dqs_found_lanes_r1_reg[0]_0\(0) => u_ddr_calib_top_n_93,
      \pi_dqs_found_lanes_r1_reg[0]_1\ => u_ddr_calib_top_n_98,
      \pi_dqs_found_lanes_r1_reg[0]_2\ => u_ddr_calib_top_n_177,
      \pi_dqs_found_lanes_r1_reg[0]_3\ => u_ddr_calib_top_n_185,
      \pi_dqs_found_lanes_r1_reg[10]\ => u_ddr_calib_top_n_148,
      \pi_dqs_found_lanes_r1_reg[10]_0\ => u_ddr_calib_top_n_158,
      \pi_dqs_found_lanes_r1_reg[10]_1\(5) => u_ddr_calib_top_n_165,
      \pi_dqs_found_lanes_r1_reg[10]_1\(4) => u_ddr_calib_top_n_166,
      \pi_dqs_found_lanes_r1_reg[10]_1\(3) => u_ddr_calib_top_n_167,
      \pi_dqs_found_lanes_r1_reg[10]_1\(2) => u_ddr_calib_top_n_168,
      \pi_dqs_found_lanes_r1_reg[10]_1\(1) => u_ddr_calib_top_n_169,
      \pi_dqs_found_lanes_r1_reg[10]_1\(0) => u_ddr_calib_top_n_170,
      \pi_dqs_found_lanes_r1_reg[10]_2\ => u_ddr_calib_top_n_183,
      \pi_dqs_found_lanes_r1_reg[10]_3\ => u_ddr_calib_top_n_191,
      \pi_dqs_found_lanes_r1_reg[1]\ => u_ddr_calib_top_n_104,
      \pi_dqs_found_lanes_r1_reg[1]_0\ => u_ddr_calib_top_n_108,
      \pi_dqs_found_lanes_r1_reg[1]_1\(5) => u_ddr_calib_top_n_117,
      \pi_dqs_found_lanes_r1_reg[1]_1\(4) => u_ddr_calib_top_n_118,
      \pi_dqs_found_lanes_r1_reg[1]_1\(3) => u_ddr_calib_top_n_119,
      \pi_dqs_found_lanes_r1_reg[1]_1\(2) => u_ddr_calib_top_n_120,
      \pi_dqs_found_lanes_r1_reg[1]_1\(1) => u_ddr_calib_top_n_121,
      \pi_dqs_found_lanes_r1_reg[1]_1\(0) => u_ddr_calib_top_n_122,
      \pi_dqs_found_lanes_r1_reg[1]_2\ => u_ddr_calib_top_n_178,
      \pi_dqs_found_lanes_r1_reg[1]_3\ => u_ddr_calib_top_n_186,
      \pi_dqs_found_lanes_r1_reg[2]\ => u_ddr_calib_top_n_103,
      \pi_dqs_found_lanes_r1_reg[2]_0\ => u_ddr_calib_top_n_112,
      \pi_dqs_found_lanes_r1_reg[2]_1\(5) => u_ddr_calib_top_n_123,
      \pi_dqs_found_lanes_r1_reg[2]_1\(4) => u_ddr_calib_top_n_124,
      \pi_dqs_found_lanes_r1_reg[2]_1\(3) => u_ddr_calib_top_n_125,
      \pi_dqs_found_lanes_r1_reg[2]_1\(2) => u_ddr_calib_top_n_126,
      \pi_dqs_found_lanes_r1_reg[2]_1\(1) => u_ddr_calib_top_n_127,
      \pi_dqs_found_lanes_r1_reg[2]_1\(0) => u_ddr_calib_top_n_128,
      \pi_dqs_found_lanes_r1_reg[2]_2\ => u_ddr_calib_top_n_179,
      \pi_dqs_found_lanes_r1_reg[2]_3\ => u_ddr_calib_top_n_187,
      \pi_dqs_found_lanes_r1_reg[3]\ => u_ddr_calib_top_n_101,
      \pi_dqs_found_lanes_r1_reg[3]_0\ => u_ddr_calib_top_n_116,
      \pi_dqs_found_lanes_r1_reg[3]_1\(5) => u_ddr_calib_top_n_129,
      \pi_dqs_found_lanes_r1_reg[3]_1\(4) => u_ddr_calib_top_n_130,
      \pi_dqs_found_lanes_r1_reg[3]_1\(3) => u_ddr_calib_top_n_131,
      \pi_dqs_found_lanes_r1_reg[3]_1\(2) => u_ddr_calib_top_n_132,
      \pi_dqs_found_lanes_r1_reg[3]_1\(1) => u_ddr_calib_top_n_133,
      \pi_dqs_found_lanes_r1_reg[3]_1\(0) => u_ddr_calib_top_n_134,
      \pi_dqs_found_lanes_r1_reg[3]_2\ => u_ddr_calib_top_n_180,
      \pi_dqs_found_lanes_r1_reg[3]_3\ => u_ddr_calib_top_n_188,
      \pi_dqs_found_lanes_r1_reg[4]\ => u_ddr_calib_top_n_64,
      \pi_dqs_found_lanes_r1_reg[4]_0\ => u_ddr_calib_top_n_74,
      \pi_dqs_found_lanes_r1_reg[4]_1\ => u_ddr_calib_top_n_75,
      \pi_dqs_found_lanes_r1_reg[4]_2\ => u_ddr_calib_top_n_184,
      \pi_dqs_found_lanes_r1_reg[4]_3\ => u_ddr_calib_top_n_192,
      \pi_dqs_found_lanes_r1_reg[8]\ => u_ddr_calib_top_n_135,
      \pi_dqs_found_lanes_r1_reg[8]_0\(5) => u_ddr_calib_top_n_136,
      \pi_dqs_found_lanes_r1_reg[8]_0\(4) => u_ddr_calib_top_n_137,
      \pi_dqs_found_lanes_r1_reg[8]_0\(3) => u_ddr_calib_top_n_138,
      \pi_dqs_found_lanes_r1_reg[8]_0\(2) => u_ddr_calib_top_n_139,
      \pi_dqs_found_lanes_r1_reg[8]_0\(1) => u_ddr_calib_top_n_140,
      \pi_dqs_found_lanes_r1_reg[8]_0\(0) => u_ddr_calib_top_n_141,
      \pi_dqs_found_lanes_r1_reg[8]_1\ => u_ddr_calib_top_n_146,
      \pi_dqs_found_lanes_r1_reg[8]_2\ => u_ddr_calib_top_n_181,
      \pi_dqs_found_lanes_r1_reg[8]_3\ => u_ddr_calib_top_n_189,
      \pi_dqs_found_lanes_r1_reg[9]\ => u_ddr_calib_top_n_150,
      \pi_dqs_found_lanes_r1_reg[9]_0\ => u_ddr_calib_top_n_154,
      \pi_dqs_found_lanes_r1_reg[9]_1\(5) => u_ddr_calib_top_n_159,
      \pi_dqs_found_lanes_r1_reg[9]_1\(4) => u_ddr_calib_top_n_160,
      \pi_dqs_found_lanes_r1_reg[9]_1\(3) => u_ddr_calib_top_n_161,
      \pi_dqs_found_lanes_r1_reg[9]_1\(2) => u_ddr_calib_top_n_162,
      \pi_dqs_found_lanes_r1_reg[9]_1\(1) => u_ddr_calib_top_n_163,
      \pi_dqs_found_lanes_r1_reg[9]_1\(0) => u_ddr_calib_top_n_164,
      \pi_dqs_found_lanes_r1_reg[9]_2\ => u_ddr_calib_top_n_182,
      \pi_dqs_found_lanes_r1_reg[9]_3\ => u_ddr_calib_top_n_190,
      \po_counter_read_val_reg[0]\ => u_ddr_mc_phy_wrapper_n_1602,
      \po_counter_read_val_reg[1]\ => u_ddr_mc_phy_wrapper_n_1603,
      \po_counter_read_val_reg[2]\ => u_ddr_mc_phy_wrapper_n_1604,
      \po_counter_read_val_reg[3]\ => u_ddr_mc_phy_wrapper_n_1605,
      \po_counter_read_val_reg[4]\ => u_ddr_mc_phy_wrapper_n_1606,
      \po_counter_read_val_reg[5]\ => u_ddr_mc_phy_wrapper_n_1607,
      \po_counter_read_val_reg[6]\ => u_ddr_mc_phy_wrapper_n_1608,
      \po_counter_read_val_reg[7]\ => u_ddr_mc_phy_wrapper_n_1609,
      \po_counter_read_val_reg[8]\ => u_ddr_calib_top_n_58,
      \po_counter_read_val_reg[8]_0\ => u_ddr_calib_top_n_71,
      \po_counter_read_val_reg[8]_1\ => u_ddr_calib_top_n_73,
      \po_counter_read_val_reg[8]_10\ => u_ddr_calib_top_n_100,
      \po_counter_read_val_reg[8]_11\ => u_ddr_calib_top_n_102,
      \po_counter_read_val_reg[8]_12\ => u_ddr_calib_top_n_106,
      \po_counter_read_val_reg[8]_13\ => u_ddr_calib_top_n_110,
      \po_counter_read_val_reg[8]_14\ => u_ddr_calib_top_n_114,
      \po_counter_read_val_reg[8]_15\ => u_ddr_calib_top_n_142,
      \po_counter_read_val_reg[8]_16\ => u_ddr_calib_top_n_144,
      \po_counter_read_val_reg[8]_17\ => u_ddr_calib_top_n_147,
      \po_counter_read_val_reg[8]_18\ => u_ddr_calib_top_n_149,
      \po_counter_read_val_reg[8]_19\ => u_ddr_calib_top_n_152,
      \po_counter_read_val_reg[8]_2\ => u_ddr_calib_top_n_76,
      \po_counter_read_val_reg[8]_20\ => u_ddr_calib_top_n_156,
      \po_counter_read_val_reg[8]_21\ => u_ddr_calib_top_n_193,
      \po_counter_read_val_reg[8]_22\ => u_ddr_calib_top_n_194,
      \po_counter_read_val_reg[8]_23\ => u_ddr_calib_top_n_195,
      \po_counter_read_val_reg[8]_24\ => u_ddr_calib_top_n_196,
      \po_counter_read_val_reg[8]_25\ => u_ddr_calib_top_n_197,
      \po_counter_read_val_reg[8]_26\ => u_ddr_calib_top_n_198,
      \po_counter_read_val_reg[8]_27\ => u_ddr_calib_top_n_199,
      \po_counter_read_val_reg[8]_28\ => u_ddr_calib_top_n_200,
      \po_counter_read_val_reg[8]_29\ => u_ddr_calib_top_n_201,
      \po_counter_read_val_reg[8]_3\ => u_ddr_calib_top_n_77,
      \po_counter_read_val_reg[8]_30\ => u_ddr_calib_top_n_202,
      \po_counter_read_val_reg[8]_31\ => u_ddr_mc_phy_wrapper_n_1610,
      \po_counter_read_val_reg[8]_4\ => u_ddr_calib_top_n_78,
      \po_counter_read_val_reg[8]_5\ => u_ddr_calib_top_n_81,
      \po_counter_read_val_reg[8]_6\ => u_ddr_calib_top_n_82,
      \po_counter_read_val_reg[8]_7\ => u_ddr_calib_top_n_94,
      \po_counter_read_val_reg[8]_8\ => u_ddr_calib_top_n_96,
      \po_counter_read_val_reg[8]_9\ => u_ddr_calib_top_n_99,
      \po_stg2_wrcal_cnt_reg[2]\ => u_ddr_mc_phy_wrapper_n_1612,
      \po_stg2_wrcal_cnt_reg[2]_0\ => u_ddr_mc_phy_wrapper_n_1613,
      \po_stg2_wrcal_cnt_reg[2]_1\ => u_ddr_mc_phy_wrapper_n_1614,
      \po_stg2_wrcal_cnt_reg[2]_10\ => u_ddr_mc_phy_wrapper_n_1623,
      \po_stg2_wrcal_cnt_reg[2]_11\ => u_ddr_mc_phy_wrapper_n_1624,
      \po_stg2_wrcal_cnt_reg[2]_12\ => u_ddr_mc_phy_wrapper_n_1625,
      \po_stg2_wrcal_cnt_reg[2]_13\ => u_ddr_mc_phy_wrapper_n_1626,
      \po_stg2_wrcal_cnt_reg[2]_14\ => u_ddr_mc_phy_wrapper_n_1627,
      \po_stg2_wrcal_cnt_reg[2]_15\ => u_ddr_mc_phy_wrapper_n_1628,
      \po_stg2_wrcal_cnt_reg[2]_16\ => u_ddr_mc_phy_wrapper_n_1629,
      \po_stg2_wrcal_cnt_reg[2]_17\ => u_ddr_mc_phy_wrapper_n_1630,
      \po_stg2_wrcal_cnt_reg[2]_18\ => u_ddr_mc_phy_wrapper_n_1631,
      \po_stg2_wrcal_cnt_reg[2]_19\ => u_ddr_mc_phy_wrapper_n_1632,
      \po_stg2_wrcal_cnt_reg[2]_2\ => u_ddr_mc_phy_wrapper_n_1615,
      \po_stg2_wrcal_cnt_reg[2]_20\ => u_ddr_mc_phy_wrapper_n_1633,
      \po_stg2_wrcal_cnt_reg[2]_21\ => u_ddr_mc_phy_wrapper_n_1634,
      \po_stg2_wrcal_cnt_reg[2]_22\ => u_ddr_mc_phy_wrapper_n_1635,
      \po_stg2_wrcal_cnt_reg[2]_23\ => u_ddr_mc_phy_wrapper_n_1636,
      \po_stg2_wrcal_cnt_reg[2]_24\ => u_ddr_mc_phy_wrapper_n_1637,
      \po_stg2_wrcal_cnt_reg[2]_25\ => u_ddr_mc_phy_wrapper_n_1638,
      \po_stg2_wrcal_cnt_reg[2]_26\ => u_ddr_mc_phy_wrapper_n_1639,
      \po_stg2_wrcal_cnt_reg[2]_27\ => u_ddr_mc_phy_wrapper_n_1640,
      \po_stg2_wrcal_cnt_reg[2]_28\ => u_ddr_mc_phy_wrapper_n_1641,
      \po_stg2_wrcal_cnt_reg[2]_29\ => u_ddr_mc_phy_wrapper_n_1642,
      \po_stg2_wrcal_cnt_reg[2]_3\ => u_ddr_mc_phy_wrapper_n_1616,
      \po_stg2_wrcal_cnt_reg[2]_30\ => u_ddr_mc_phy_wrapper_n_1643,
      \po_stg2_wrcal_cnt_reg[2]_31\ => u_ddr_mc_phy_wrapper_n_1644,
      \po_stg2_wrcal_cnt_reg[2]_32\ => u_ddr_mc_phy_wrapper_n_1645,
      \po_stg2_wrcal_cnt_reg[2]_33\ => u_ddr_mc_phy_wrapper_n_1646,
      \po_stg2_wrcal_cnt_reg[2]_34\ => u_ddr_mc_phy_wrapper_n_1647,
      \po_stg2_wrcal_cnt_reg[2]_35\ => u_ddr_mc_phy_wrapper_n_1648,
      \po_stg2_wrcal_cnt_reg[2]_36\ => u_ddr_mc_phy_wrapper_n_1649,
      \po_stg2_wrcal_cnt_reg[2]_37\ => u_ddr_mc_phy_wrapper_n_1650,
      \po_stg2_wrcal_cnt_reg[2]_38\ => u_ddr_mc_phy_wrapper_n_1651,
      \po_stg2_wrcal_cnt_reg[2]_39\ => u_ddr_mc_phy_wrapper_n_1652,
      \po_stg2_wrcal_cnt_reg[2]_4\ => u_ddr_mc_phy_wrapper_n_1617,
      \po_stg2_wrcal_cnt_reg[2]_40\ => u_ddr_mc_phy_wrapper_n_1653,
      \po_stg2_wrcal_cnt_reg[2]_41\ => u_ddr_mc_phy_wrapper_n_1654,
      \po_stg2_wrcal_cnt_reg[2]_42\ => u_ddr_mc_phy_wrapper_n_1655,
      \po_stg2_wrcal_cnt_reg[2]_43\ => u_ddr_mc_phy_wrapper_n_1656,
      \po_stg2_wrcal_cnt_reg[2]_44\ => u_ddr_mc_phy_wrapper_n_1657,
      \po_stg2_wrcal_cnt_reg[2]_45\ => u_ddr_mc_phy_wrapper_n_1658,
      \po_stg2_wrcal_cnt_reg[2]_46\ => u_ddr_mc_phy_wrapper_n_1659,
      \po_stg2_wrcal_cnt_reg[2]_47\ => u_ddr_mc_phy_wrapper_n_1660,
      \po_stg2_wrcal_cnt_reg[2]_48\ => u_ddr_mc_phy_wrapper_n_1661,
      \po_stg2_wrcal_cnt_reg[2]_49\ => u_ddr_mc_phy_wrapper_n_1662,
      \po_stg2_wrcal_cnt_reg[2]_5\ => u_ddr_mc_phy_wrapper_n_1618,
      \po_stg2_wrcal_cnt_reg[2]_50\ => u_ddr_mc_phy_wrapper_n_1663,
      \po_stg2_wrcal_cnt_reg[2]_51\ => u_ddr_mc_phy_wrapper_n_1664,
      \po_stg2_wrcal_cnt_reg[2]_52\ => u_ddr_mc_phy_wrapper_n_1665,
      \po_stg2_wrcal_cnt_reg[2]_53\ => u_ddr_mc_phy_wrapper_n_1666,
      \po_stg2_wrcal_cnt_reg[2]_54\ => u_ddr_mc_phy_wrapper_n_1667,
      \po_stg2_wrcal_cnt_reg[2]_55\ => u_ddr_mc_phy_wrapper_n_1668,
      \po_stg2_wrcal_cnt_reg[2]_56\ => u_ddr_mc_phy_wrapper_n_1669,
      \po_stg2_wrcal_cnt_reg[2]_57\ => u_ddr_mc_phy_wrapper_n_1670,
      \po_stg2_wrcal_cnt_reg[2]_58\ => u_ddr_mc_phy_wrapper_n_1671,
      \po_stg2_wrcal_cnt_reg[2]_59\ => u_ddr_mc_phy_wrapper_n_1672,
      \po_stg2_wrcal_cnt_reg[2]_6\ => u_ddr_mc_phy_wrapper_n_1619,
      \po_stg2_wrcal_cnt_reg[2]_60\ => u_ddr_mc_phy_wrapper_n_1673,
      \po_stg2_wrcal_cnt_reg[2]_61\ => u_ddr_mc_phy_wrapper_n_1674,
      \po_stg2_wrcal_cnt_reg[2]_7\ => u_ddr_mc_phy_wrapper_n_1620,
      \po_stg2_wrcal_cnt_reg[2]_8\ => u_ddr_mc_phy_wrapper_n_1621,
      \po_stg2_wrcal_cnt_reg[2]_9\ => u_ddr_mc_phy_wrapper_n_1622,
      prbs_rdlvl_done_pulse_reg(0) => prbs_rdlvl_done_pulse_reg(0),
      \rd_mux_sel_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_672,
      \rd_mux_sel_r_reg[2]_0\ => u_ddr_mc_phy_wrapper_n_673,
      \rd_mux_sel_r_reg[2]_1\ => u_ddr_mc_phy_wrapper_n_689,
      \rd_mux_sel_r_reg[2]_10\ => u_ddr_mc_phy_wrapper_n_674,
      \rd_mux_sel_r_reg[2]_11\ => u_ddr_mc_phy_wrapper_n_698,
      \rd_mux_sel_r_reg[2]_12\ => u_ddr_mc_phy_wrapper_n_699,
      \rd_mux_sel_r_reg[2]_13\ => u_ddr_mc_phy_wrapper_n_700,
      \rd_mux_sel_r_reg[2]_14\ => u_ddr_mc_phy_wrapper_n_701,
      \rd_mux_sel_r_reg[2]_15\ => u_ddr_mc_phy_wrapper_n_702,
      \rd_mux_sel_r_reg[2]_16\ => u_ddr_mc_phy_wrapper_n_703,
      \rd_mux_sel_r_reg[2]_17\ => u_ddr_mc_phy_wrapper_n_704,
      \rd_mux_sel_r_reg[2]_18\ => u_ddr_mc_phy_wrapper_n_705,
      \rd_mux_sel_r_reg[2]_19\ => u_ddr_mc_phy_wrapper_n_706,
      \rd_mux_sel_r_reg[2]_2\ => u_ddr_mc_phy_wrapper_n_690,
      \rd_mux_sel_r_reg[2]_20\ => u_ddr_mc_phy_wrapper_n_675,
      \rd_mux_sel_r_reg[2]_21\ => u_ddr_mc_phy_wrapper_n_676,
      \rd_mux_sel_r_reg[2]_22\ => u_ddr_mc_phy_wrapper_n_677,
      \rd_mux_sel_r_reg[2]_23\ => u_ddr_mc_phy_wrapper_n_707,
      \rd_mux_sel_r_reg[2]_24\ => u_ddr_mc_phy_wrapper_n_708,
      \rd_mux_sel_r_reg[2]_25\ => u_ddr_mc_phy_wrapper_n_709,
      \rd_mux_sel_r_reg[2]_26\ => u_ddr_mc_phy_wrapper_n_678,
      \rd_mux_sel_r_reg[2]_27\ => u_ddr_mc_phy_wrapper_n_710,
      \rd_mux_sel_r_reg[2]_28\ => u_ddr_mc_phy_wrapper_n_711,
      \rd_mux_sel_r_reg[2]_29\ => u_ddr_mc_phy_wrapper_n_712,
      \rd_mux_sel_r_reg[2]_3\ => u_ddr_mc_phy_wrapper_n_691,
      \rd_mux_sel_r_reg[2]_30\ => u_ddr_mc_phy_wrapper_n_679,
      \rd_mux_sel_r_reg[2]_31\ => u_ddr_mc_phy_wrapper_n_713,
      \rd_mux_sel_r_reg[2]_32\ => u_ddr_mc_phy_wrapper_n_680,
      \rd_mux_sel_r_reg[2]_33\ => u_ddr_mc_phy_wrapper_n_714,
      \rd_mux_sel_r_reg[2]_34\ => u_ddr_mc_phy_wrapper_n_715,
      \rd_mux_sel_r_reg[2]_35\ => u_ddr_mc_phy_wrapper_n_716,
      \rd_mux_sel_r_reg[2]_36\ => u_ddr_mc_phy_wrapper_n_717,
      \rd_mux_sel_r_reg[2]_37\ => u_ddr_mc_phy_wrapper_n_681,
      \rd_mux_sel_r_reg[2]_38\ => u_ddr_mc_phy_wrapper_n_718,
      \rd_mux_sel_r_reg[2]_39\ => u_ddr_mc_phy_wrapper_n_719,
      \rd_mux_sel_r_reg[2]_4\ => u_ddr_mc_phy_wrapper_n_692,
      \rd_mux_sel_r_reg[2]_40\ => u_ddr_mc_phy_wrapper_n_720,
      \rd_mux_sel_r_reg[2]_41\ => u_ddr_mc_phy_wrapper_n_721,
      \rd_mux_sel_r_reg[2]_42\ => u_ddr_mc_phy_wrapper_n_682,
      \rd_mux_sel_r_reg[2]_43\ => u_ddr_mc_phy_wrapper_n_722,
      \rd_mux_sel_r_reg[2]_44\ => u_ddr_mc_phy_wrapper_n_683,
      \rd_mux_sel_r_reg[2]_45\ => u_ddr_mc_phy_wrapper_n_723,
      \rd_mux_sel_r_reg[2]_46\ => u_ddr_mc_phy_wrapper_n_684,
      \rd_mux_sel_r_reg[2]_47\ => u_ddr_mc_phy_wrapper_n_685,
      \rd_mux_sel_r_reg[2]_48\ => u_ddr_mc_phy_wrapper_n_686,
      \rd_mux_sel_r_reg[2]_49\ => u_ddr_mc_phy_wrapper_n_724,
      \rd_mux_sel_r_reg[2]_5\ => u_ddr_mc_phy_wrapper_n_693,
      \rd_mux_sel_r_reg[2]_50\ => u_ddr_mc_phy_wrapper_n_725,
      \rd_mux_sel_r_reg[2]_51\ => u_ddr_mc_phy_wrapper_n_726,
      \rd_mux_sel_r_reg[2]_52\ => u_ddr_mc_phy_wrapper_n_727,
      \rd_mux_sel_r_reg[2]_53\ => u_ddr_mc_phy_wrapper_n_728,
      \rd_mux_sel_r_reg[2]_54\ => u_ddr_mc_phy_wrapper_n_729,
      \rd_mux_sel_r_reg[2]_55\ => u_ddr_mc_phy_wrapper_n_730,
      \rd_mux_sel_r_reg[2]_56\ => u_ddr_mc_phy_wrapper_n_731,
      \rd_mux_sel_r_reg[2]_57\ => u_ddr_mc_phy_wrapper_n_687,
      \rd_mux_sel_r_reg[2]_58\ => u_ddr_mc_phy_wrapper_n_732,
      \rd_mux_sel_r_reg[2]_59\ => u_ddr_mc_phy_wrapper_n_733,
      \rd_mux_sel_r_reg[2]_6\ => u_ddr_mc_phy_wrapper_n_694,
      \rd_mux_sel_r_reg[2]_60\ => u_ddr_mc_phy_wrapper_n_734,
      \rd_mux_sel_r_reg[2]_61\ => u_ddr_mc_phy_wrapper_n_735,
      \rd_mux_sel_r_reg[2]_62\ => u_ddr_mc_phy_wrapper_n_688,
      \rd_mux_sel_r_reg[2]_7\ => u_ddr_mc_phy_wrapper_n_695,
      \rd_mux_sel_r_reg[2]_8\ => u_ddr_mc_phy_wrapper_n_696,
      \rd_mux_sel_r_reg[2]_9\ => u_ddr_mc_phy_wrapper_n_697,
      \rd_ptr_reg[3]\(44 downto 41) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(75 downto 72),
      \rd_ptr_reg[3]\(40 downto 37) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(67 downto 64),
      \rd_ptr_reg[3]\(36 downto 17) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(59 downto 40),
      \rd_ptr_reg[3]\(16 downto 13) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(35 downto 32),
      \rd_ptr_reg[3]\(12 downto 9) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(27 downto 24),
      \rd_ptr_reg[3]\(8 downto 5) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(19 downto 16),
      \rd_ptr_reg[3]\(4 downto 1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(11 downto 8),
      \rd_ptr_reg[3]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(1),
      \rd_ptr_reg[3]_0\(43) => u_ddr_mc_phy_wrapper_n_1469,
      \rd_ptr_reg[3]_0\(42) => u_ddr_mc_phy_wrapper_n_1470,
      \rd_ptr_reg[3]_0\(41) => u_ddr_mc_phy_wrapper_n_1471,
      \rd_ptr_reg[3]_0\(40) => u_ddr_mc_phy_wrapper_n_1472,
      \rd_ptr_reg[3]_0\(39) => u_ddr_mc_phy_wrapper_n_1473,
      \rd_ptr_reg[3]_0\(38) => u_ddr_mc_phy_wrapper_n_1474,
      \rd_ptr_reg[3]_0\(37) => u_ddr_mc_phy_wrapper_n_1475,
      \rd_ptr_reg[3]_0\(36) => u_ddr_mc_phy_wrapper_n_1476,
      \rd_ptr_reg[3]_0\(35) => u_ddr_mc_phy_wrapper_n_1477,
      \rd_ptr_reg[3]_0\(34) => u_ddr_mc_phy_wrapper_n_1478,
      \rd_ptr_reg[3]_0\(33) => u_ddr_mc_phy_wrapper_n_1479,
      \rd_ptr_reg[3]_0\(32) => u_ddr_mc_phy_wrapper_n_1480,
      \rd_ptr_reg[3]_0\(31) => u_ddr_mc_phy_wrapper_n_1481,
      \rd_ptr_reg[3]_0\(30) => u_ddr_mc_phy_wrapper_n_1482,
      \rd_ptr_reg[3]_0\(29) => u_ddr_mc_phy_wrapper_n_1483,
      \rd_ptr_reg[3]_0\(28) => u_ddr_mc_phy_wrapper_n_1484,
      \rd_ptr_reg[3]_0\(27) => u_ddr_mc_phy_wrapper_n_1485,
      \rd_ptr_reg[3]_0\(26) => u_ddr_mc_phy_wrapper_n_1486,
      \rd_ptr_reg[3]_0\(25) => u_ddr_mc_phy_wrapper_n_1487,
      \rd_ptr_reg[3]_0\(24) => u_ddr_mc_phy_wrapper_n_1488,
      \rd_ptr_reg[3]_0\(23) => u_ddr_mc_phy_wrapper_n_1489,
      \rd_ptr_reg[3]_0\(22) => u_ddr_mc_phy_wrapper_n_1490,
      \rd_ptr_reg[3]_0\(21) => u_ddr_mc_phy_wrapper_n_1491,
      \rd_ptr_reg[3]_0\(20) => u_ddr_mc_phy_wrapper_n_1492,
      \rd_ptr_reg[3]_0\(19) => u_ddr_mc_phy_wrapper_n_1493,
      \rd_ptr_reg[3]_0\(18) => u_ddr_mc_phy_wrapper_n_1494,
      \rd_ptr_reg[3]_0\(17) => u_ddr_mc_phy_wrapper_n_1495,
      \rd_ptr_reg[3]_0\(16) => u_ddr_mc_phy_wrapper_n_1496,
      \rd_ptr_reg[3]_0\(15) => u_ddr_mc_phy_wrapper_n_1497,
      \rd_ptr_reg[3]_0\(14) => u_ddr_mc_phy_wrapper_n_1498,
      \rd_ptr_reg[3]_0\(13) => u_ddr_mc_phy_wrapper_n_1499,
      \rd_ptr_reg[3]_0\(12) => u_ddr_mc_phy_wrapper_n_1500,
      \rd_ptr_reg[3]_0\(11) => u_ddr_mc_phy_wrapper_n_1501,
      \rd_ptr_reg[3]_0\(10) => u_ddr_mc_phy_wrapper_n_1502,
      \rd_ptr_reg[3]_0\(9) => u_ddr_mc_phy_wrapper_n_1503,
      \rd_ptr_reg[3]_0\(8) => u_ddr_mc_phy_wrapper_n_1504,
      \rd_ptr_reg[3]_0\(7) => u_ddr_mc_phy_wrapper_n_1505,
      \rd_ptr_reg[3]_0\(6) => u_ddr_mc_phy_wrapper_n_1506,
      \rd_ptr_reg[3]_0\(5) => u_ddr_mc_phy_wrapper_n_1507,
      \rd_ptr_reg[3]_0\(4) => u_ddr_mc_phy_wrapper_n_1508,
      \rd_ptr_reg[3]_0\(3) => u_ddr_mc_phy_wrapper_n_1509,
      \rd_ptr_reg[3]_0\(2) => u_ddr_mc_phy_wrapper_n_1510,
      \rd_ptr_reg[3]_0\(1) => u_ddr_mc_phy_wrapper_n_1511,
      \rd_ptr_reg[3]_0\(0) => u_ddr_mc_phy_wrapper_n_1512,
      \rd_ptr_reg[3]_1\(43) => u_ddr_mc_phy_wrapper_n_1513,
      \rd_ptr_reg[3]_1\(42) => u_ddr_mc_phy_wrapper_n_1514,
      \rd_ptr_reg[3]_1\(41) => u_ddr_mc_phy_wrapper_n_1515,
      \rd_ptr_reg[3]_1\(40) => u_ddr_mc_phy_wrapper_n_1516,
      \rd_ptr_reg[3]_1\(39) => u_ddr_mc_phy_wrapper_n_1517,
      \rd_ptr_reg[3]_1\(38) => u_ddr_mc_phy_wrapper_n_1518,
      \rd_ptr_reg[3]_1\(37) => u_ddr_mc_phy_wrapper_n_1519,
      \rd_ptr_reg[3]_1\(36) => u_ddr_mc_phy_wrapper_n_1520,
      \rd_ptr_reg[3]_1\(35) => u_ddr_mc_phy_wrapper_n_1521,
      \rd_ptr_reg[3]_1\(34) => u_ddr_mc_phy_wrapper_n_1522,
      \rd_ptr_reg[3]_1\(33) => u_ddr_mc_phy_wrapper_n_1523,
      \rd_ptr_reg[3]_1\(32) => u_ddr_mc_phy_wrapper_n_1524,
      \rd_ptr_reg[3]_1\(31) => u_ddr_mc_phy_wrapper_n_1525,
      \rd_ptr_reg[3]_1\(30) => u_ddr_mc_phy_wrapper_n_1526,
      \rd_ptr_reg[3]_1\(29) => u_ddr_mc_phy_wrapper_n_1527,
      \rd_ptr_reg[3]_1\(28) => u_ddr_mc_phy_wrapper_n_1528,
      \rd_ptr_reg[3]_1\(27) => u_ddr_mc_phy_wrapper_n_1529,
      \rd_ptr_reg[3]_1\(26) => u_ddr_mc_phy_wrapper_n_1530,
      \rd_ptr_reg[3]_1\(25) => u_ddr_mc_phy_wrapper_n_1531,
      \rd_ptr_reg[3]_1\(24) => u_ddr_mc_phy_wrapper_n_1532,
      \rd_ptr_reg[3]_1\(23) => u_ddr_mc_phy_wrapper_n_1533,
      \rd_ptr_reg[3]_1\(22) => u_ddr_mc_phy_wrapper_n_1534,
      \rd_ptr_reg[3]_1\(21) => u_ddr_mc_phy_wrapper_n_1535,
      \rd_ptr_reg[3]_1\(20) => u_ddr_mc_phy_wrapper_n_1536,
      \rd_ptr_reg[3]_1\(19) => u_ddr_mc_phy_wrapper_n_1537,
      \rd_ptr_reg[3]_1\(18) => u_ddr_mc_phy_wrapper_n_1538,
      \rd_ptr_reg[3]_1\(17) => u_ddr_mc_phy_wrapper_n_1539,
      \rd_ptr_reg[3]_1\(16) => u_ddr_mc_phy_wrapper_n_1540,
      \rd_ptr_reg[3]_1\(15) => u_ddr_mc_phy_wrapper_n_1541,
      \rd_ptr_reg[3]_1\(14) => u_ddr_mc_phy_wrapper_n_1542,
      \rd_ptr_reg[3]_1\(13) => u_ddr_mc_phy_wrapper_n_1543,
      \rd_ptr_reg[3]_1\(12) => u_ddr_mc_phy_wrapper_n_1544,
      \rd_ptr_reg[3]_1\(11) => u_ddr_mc_phy_wrapper_n_1545,
      \rd_ptr_reg[3]_1\(10) => u_ddr_mc_phy_wrapper_n_1546,
      \rd_ptr_reg[3]_1\(9) => u_ddr_mc_phy_wrapper_n_1547,
      \rd_ptr_reg[3]_1\(8) => u_ddr_mc_phy_wrapper_n_1548,
      \rd_ptr_reg[3]_1\(7) => u_ddr_mc_phy_wrapper_n_1549,
      \rd_ptr_reg[3]_1\(6) => u_ddr_mc_phy_wrapper_n_1550,
      \rd_ptr_reg[3]_1\(5) => u_ddr_mc_phy_wrapper_n_1551,
      \rd_ptr_reg[3]_1\(4) => u_ddr_mc_phy_wrapper_n_1552,
      \rd_ptr_reg[3]_1\(3) => u_ddr_mc_phy_wrapper_n_1553,
      \rd_ptr_reg[3]_1\(2) => u_ddr_mc_phy_wrapper_n_1554,
      \rd_ptr_reg[3]_1\(1) => u_ddr_mc_phy_wrapper_n_1555,
      \rd_ptr_reg[3]_1\(0) => u_ddr_mc_phy_wrapper_n_1556,
      \rd_ptr_reg[3]_2\(43) => u_ddr_mc_phy_wrapper_n_1557,
      \rd_ptr_reg[3]_2\(42) => u_ddr_mc_phy_wrapper_n_1558,
      \rd_ptr_reg[3]_2\(41) => u_ddr_mc_phy_wrapper_n_1559,
      \rd_ptr_reg[3]_2\(40) => u_ddr_mc_phy_wrapper_n_1560,
      \rd_ptr_reg[3]_2\(39) => u_ddr_mc_phy_wrapper_n_1561,
      \rd_ptr_reg[3]_2\(38) => u_ddr_mc_phy_wrapper_n_1562,
      \rd_ptr_reg[3]_2\(37) => u_ddr_mc_phy_wrapper_n_1563,
      \rd_ptr_reg[3]_2\(36) => u_ddr_mc_phy_wrapper_n_1564,
      \rd_ptr_reg[3]_2\(35) => u_ddr_mc_phy_wrapper_n_1565,
      \rd_ptr_reg[3]_2\(34) => u_ddr_mc_phy_wrapper_n_1566,
      \rd_ptr_reg[3]_2\(33) => u_ddr_mc_phy_wrapper_n_1567,
      \rd_ptr_reg[3]_2\(32) => u_ddr_mc_phy_wrapper_n_1568,
      \rd_ptr_reg[3]_2\(31) => u_ddr_mc_phy_wrapper_n_1569,
      \rd_ptr_reg[3]_2\(30) => u_ddr_mc_phy_wrapper_n_1570,
      \rd_ptr_reg[3]_2\(29) => u_ddr_mc_phy_wrapper_n_1571,
      \rd_ptr_reg[3]_2\(28) => u_ddr_mc_phy_wrapper_n_1572,
      \rd_ptr_reg[3]_2\(27) => u_ddr_mc_phy_wrapper_n_1573,
      \rd_ptr_reg[3]_2\(26) => u_ddr_mc_phy_wrapper_n_1574,
      \rd_ptr_reg[3]_2\(25) => u_ddr_mc_phy_wrapper_n_1575,
      \rd_ptr_reg[3]_2\(24) => u_ddr_mc_phy_wrapper_n_1576,
      \rd_ptr_reg[3]_2\(23) => u_ddr_mc_phy_wrapper_n_1577,
      \rd_ptr_reg[3]_2\(22) => u_ddr_mc_phy_wrapper_n_1578,
      \rd_ptr_reg[3]_2\(21) => u_ddr_mc_phy_wrapper_n_1579,
      \rd_ptr_reg[3]_2\(20) => u_ddr_mc_phy_wrapper_n_1580,
      \rd_ptr_reg[3]_2\(19) => u_ddr_mc_phy_wrapper_n_1581,
      \rd_ptr_reg[3]_2\(18) => u_ddr_mc_phy_wrapper_n_1582,
      \rd_ptr_reg[3]_2\(17) => u_ddr_mc_phy_wrapper_n_1583,
      \rd_ptr_reg[3]_2\(16) => u_ddr_mc_phy_wrapper_n_1584,
      \rd_ptr_reg[3]_2\(15) => u_ddr_mc_phy_wrapper_n_1585,
      \rd_ptr_reg[3]_2\(14) => u_ddr_mc_phy_wrapper_n_1586,
      \rd_ptr_reg[3]_2\(13) => u_ddr_mc_phy_wrapper_n_1587,
      \rd_ptr_reg[3]_2\(12) => u_ddr_mc_phy_wrapper_n_1588,
      \rd_ptr_reg[3]_2\(11) => u_ddr_mc_phy_wrapper_n_1589,
      \rd_ptr_reg[3]_2\(10) => u_ddr_mc_phy_wrapper_n_1590,
      \rd_ptr_reg[3]_2\(9) => u_ddr_mc_phy_wrapper_n_1591,
      \rd_ptr_reg[3]_2\(8) => u_ddr_mc_phy_wrapper_n_1592,
      \rd_ptr_reg[3]_2\(7) => u_ddr_mc_phy_wrapper_n_1593,
      \rd_ptr_reg[3]_2\(6) => u_ddr_mc_phy_wrapper_n_1594,
      \rd_ptr_reg[3]_2\(5) => u_ddr_mc_phy_wrapper_n_1595,
      \rd_ptr_reg[3]_2\(4) => u_ddr_mc_phy_wrapper_n_1596,
      \rd_ptr_reg[3]_2\(3) => u_ddr_mc_phy_wrapper_n_1597,
      \rd_ptr_reg[3]_2\(2) => u_ddr_mc_phy_wrapper_n_1598,
      \rd_ptr_reg[3]_2\(1) => u_ddr_mc_phy_wrapper_n_1599,
      \rd_ptr_reg[3]_2\(0) => u_ddr_mc_phy_wrapper_n_1600,
      \rd_ptr_reg[3]_3\(43) => u_ddr_mc_phy_wrapper_n_1249,
      \rd_ptr_reg[3]_3\(42) => u_ddr_mc_phy_wrapper_n_1250,
      \rd_ptr_reg[3]_3\(41) => u_ddr_mc_phy_wrapper_n_1251,
      \rd_ptr_reg[3]_3\(40) => u_ddr_mc_phy_wrapper_n_1252,
      \rd_ptr_reg[3]_3\(39) => u_ddr_mc_phy_wrapper_n_1253,
      \rd_ptr_reg[3]_3\(38) => u_ddr_mc_phy_wrapper_n_1254,
      \rd_ptr_reg[3]_3\(37) => u_ddr_mc_phy_wrapper_n_1255,
      \rd_ptr_reg[3]_3\(36) => u_ddr_mc_phy_wrapper_n_1256,
      \rd_ptr_reg[3]_3\(35) => u_ddr_mc_phy_wrapper_n_1257,
      \rd_ptr_reg[3]_3\(34) => u_ddr_mc_phy_wrapper_n_1258,
      \rd_ptr_reg[3]_3\(33) => u_ddr_mc_phy_wrapper_n_1259,
      \rd_ptr_reg[3]_3\(32) => u_ddr_mc_phy_wrapper_n_1260,
      \rd_ptr_reg[3]_3\(31) => u_ddr_mc_phy_wrapper_n_1261,
      \rd_ptr_reg[3]_3\(30) => u_ddr_mc_phy_wrapper_n_1262,
      \rd_ptr_reg[3]_3\(29) => u_ddr_mc_phy_wrapper_n_1263,
      \rd_ptr_reg[3]_3\(28) => u_ddr_mc_phy_wrapper_n_1264,
      \rd_ptr_reg[3]_3\(27) => u_ddr_mc_phy_wrapper_n_1265,
      \rd_ptr_reg[3]_3\(26) => u_ddr_mc_phy_wrapper_n_1266,
      \rd_ptr_reg[3]_3\(25) => u_ddr_mc_phy_wrapper_n_1267,
      \rd_ptr_reg[3]_3\(24) => u_ddr_mc_phy_wrapper_n_1268,
      \rd_ptr_reg[3]_3\(23) => u_ddr_mc_phy_wrapper_n_1269,
      \rd_ptr_reg[3]_3\(22) => u_ddr_mc_phy_wrapper_n_1270,
      \rd_ptr_reg[3]_3\(21) => u_ddr_mc_phy_wrapper_n_1271,
      \rd_ptr_reg[3]_3\(20) => u_ddr_mc_phy_wrapper_n_1272,
      \rd_ptr_reg[3]_3\(19) => u_ddr_mc_phy_wrapper_n_1273,
      \rd_ptr_reg[3]_3\(18) => u_ddr_mc_phy_wrapper_n_1274,
      \rd_ptr_reg[3]_3\(17) => u_ddr_mc_phy_wrapper_n_1275,
      \rd_ptr_reg[3]_3\(16) => u_ddr_mc_phy_wrapper_n_1276,
      \rd_ptr_reg[3]_3\(15) => u_ddr_mc_phy_wrapper_n_1277,
      \rd_ptr_reg[3]_3\(14) => u_ddr_mc_phy_wrapper_n_1278,
      \rd_ptr_reg[3]_3\(13) => u_ddr_mc_phy_wrapper_n_1279,
      \rd_ptr_reg[3]_3\(12) => u_ddr_mc_phy_wrapper_n_1280,
      \rd_ptr_reg[3]_3\(11) => u_ddr_mc_phy_wrapper_n_1281,
      \rd_ptr_reg[3]_3\(10) => u_ddr_mc_phy_wrapper_n_1282,
      \rd_ptr_reg[3]_3\(9) => u_ddr_mc_phy_wrapper_n_1283,
      \rd_ptr_reg[3]_3\(8) => u_ddr_mc_phy_wrapper_n_1284,
      \rd_ptr_reg[3]_3\(7) => u_ddr_mc_phy_wrapper_n_1285,
      \rd_ptr_reg[3]_3\(6) => u_ddr_mc_phy_wrapper_n_1286,
      \rd_ptr_reg[3]_3\(5) => u_ddr_mc_phy_wrapper_n_1287,
      \rd_ptr_reg[3]_3\(4) => u_ddr_mc_phy_wrapper_n_1288,
      \rd_ptr_reg[3]_3\(3) => u_ddr_mc_phy_wrapper_n_1289,
      \rd_ptr_reg[3]_3\(2) => u_ddr_mc_phy_wrapper_n_1290,
      \rd_ptr_reg[3]_3\(1) => u_ddr_mc_phy_wrapper_n_1291,
      \rd_ptr_reg[3]_3\(0) => u_ddr_mc_phy_wrapper_n_1292,
      \rd_ptr_reg[3]_4\(43) => u_ddr_mc_phy_wrapper_n_1293,
      \rd_ptr_reg[3]_4\(42) => u_ddr_mc_phy_wrapper_n_1294,
      \rd_ptr_reg[3]_4\(41) => u_ddr_mc_phy_wrapper_n_1295,
      \rd_ptr_reg[3]_4\(40) => u_ddr_mc_phy_wrapper_n_1296,
      \rd_ptr_reg[3]_4\(39) => u_ddr_mc_phy_wrapper_n_1297,
      \rd_ptr_reg[3]_4\(38) => u_ddr_mc_phy_wrapper_n_1298,
      \rd_ptr_reg[3]_4\(37) => u_ddr_mc_phy_wrapper_n_1299,
      \rd_ptr_reg[3]_4\(36) => u_ddr_mc_phy_wrapper_n_1300,
      \rd_ptr_reg[3]_4\(35) => u_ddr_mc_phy_wrapper_n_1301,
      \rd_ptr_reg[3]_4\(34) => u_ddr_mc_phy_wrapper_n_1302,
      \rd_ptr_reg[3]_4\(33) => u_ddr_mc_phy_wrapper_n_1303,
      \rd_ptr_reg[3]_4\(32) => u_ddr_mc_phy_wrapper_n_1304,
      \rd_ptr_reg[3]_4\(31) => u_ddr_mc_phy_wrapper_n_1305,
      \rd_ptr_reg[3]_4\(30) => u_ddr_mc_phy_wrapper_n_1306,
      \rd_ptr_reg[3]_4\(29) => u_ddr_mc_phy_wrapper_n_1307,
      \rd_ptr_reg[3]_4\(28) => u_ddr_mc_phy_wrapper_n_1308,
      \rd_ptr_reg[3]_4\(27) => u_ddr_mc_phy_wrapper_n_1309,
      \rd_ptr_reg[3]_4\(26) => u_ddr_mc_phy_wrapper_n_1310,
      \rd_ptr_reg[3]_4\(25) => u_ddr_mc_phy_wrapper_n_1311,
      \rd_ptr_reg[3]_4\(24) => u_ddr_mc_phy_wrapper_n_1312,
      \rd_ptr_reg[3]_4\(23) => u_ddr_mc_phy_wrapper_n_1313,
      \rd_ptr_reg[3]_4\(22) => u_ddr_mc_phy_wrapper_n_1314,
      \rd_ptr_reg[3]_4\(21) => u_ddr_mc_phy_wrapper_n_1315,
      \rd_ptr_reg[3]_4\(20) => u_ddr_mc_phy_wrapper_n_1316,
      \rd_ptr_reg[3]_4\(19) => u_ddr_mc_phy_wrapper_n_1317,
      \rd_ptr_reg[3]_4\(18) => u_ddr_mc_phy_wrapper_n_1318,
      \rd_ptr_reg[3]_4\(17) => u_ddr_mc_phy_wrapper_n_1319,
      \rd_ptr_reg[3]_4\(16) => u_ddr_mc_phy_wrapper_n_1320,
      \rd_ptr_reg[3]_4\(15) => u_ddr_mc_phy_wrapper_n_1321,
      \rd_ptr_reg[3]_4\(14) => u_ddr_mc_phy_wrapper_n_1322,
      \rd_ptr_reg[3]_4\(13) => u_ddr_mc_phy_wrapper_n_1323,
      \rd_ptr_reg[3]_4\(12) => u_ddr_mc_phy_wrapper_n_1324,
      \rd_ptr_reg[3]_4\(11) => u_ddr_mc_phy_wrapper_n_1325,
      \rd_ptr_reg[3]_4\(10) => u_ddr_mc_phy_wrapper_n_1326,
      \rd_ptr_reg[3]_4\(9) => u_ddr_mc_phy_wrapper_n_1327,
      \rd_ptr_reg[3]_4\(8) => u_ddr_mc_phy_wrapper_n_1328,
      \rd_ptr_reg[3]_4\(7) => u_ddr_mc_phy_wrapper_n_1329,
      \rd_ptr_reg[3]_4\(6) => u_ddr_mc_phy_wrapper_n_1330,
      \rd_ptr_reg[3]_4\(5) => u_ddr_mc_phy_wrapper_n_1331,
      \rd_ptr_reg[3]_4\(4) => u_ddr_mc_phy_wrapper_n_1332,
      \rd_ptr_reg[3]_4\(3) => u_ddr_mc_phy_wrapper_n_1333,
      \rd_ptr_reg[3]_4\(2) => u_ddr_mc_phy_wrapper_n_1334,
      \rd_ptr_reg[3]_4\(1) => u_ddr_mc_phy_wrapper_n_1335,
      \rd_ptr_reg[3]_4\(0) => u_ddr_mc_phy_wrapper_n_1336,
      \rd_ptr_reg[3]_5\(43) => u_ddr_mc_phy_wrapper_n_1337,
      \rd_ptr_reg[3]_5\(42) => u_ddr_mc_phy_wrapper_n_1338,
      \rd_ptr_reg[3]_5\(41) => u_ddr_mc_phy_wrapper_n_1339,
      \rd_ptr_reg[3]_5\(40) => u_ddr_mc_phy_wrapper_n_1340,
      \rd_ptr_reg[3]_5\(39) => u_ddr_mc_phy_wrapper_n_1341,
      \rd_ptr_reg[3]_5\(38) => u_ddr_mc_phy_wrapper_n_1342,
      \rd_ptr_reg[3]_5\(37) => u_ddr_mc_phy_wrapper_n_1343,
      \rd_ptr_reg[3]_5\(36) => u_ddr_mc_phy_wrapper_n_1344,
      \rd_ptr_reg[3]_5\(35) => u_ddr_mc_phy_wrapper_n_1345,
      \rd_ptr_reg[3]_5\(34) => u_ddr_mc_phy_wrapper_n_1346,
      \rd_ptr_reg[3]_5\(33) => u_ddr_mc_phy_wrapper_n_1347,
      \rd_ptr_reg[3]_5\(32) => u_ddr_mc_phy_wrapper_n_1348,
      \rd_ptr_reg[3]_5\(31) => u_ddr_mc_phy_wrapper_n_1349,
      \rd_ptr_reg[3]_5\(30) => u_ddr_mc_phy_wrapper_n_1350,
      \rd_ptr_reg[3]_5\(29) => u_ddr_mc_phy_wrapper_n_1351,
      \rd_ptr_reg[3]_5\(28) => u_ddr_mc_phy_wrapper_n_1352,
      \rd_ptr_reg[3]_5\(27) => u_ddr_mc_phy_wrapper_n_1353,
      \rd_ptr_reg[3]_5\(26) => u_ddr_mc_phy_wrapper_n_1354,
      \rd_ptr_reg[3]_5\(25) => u_ddr_mc_phy_wrapper_n_1355,
      \rd_ptr_reg[3]_5\(24) => u_ddr_mc_phy_wrapper_n_1356,
      \rd_ptr_reg[3]_5\(23) => u_ddr_mc_phy_wrapper_n_1357,
      \rd_ptr_reg[3]_5\(22) => u_ddr_mc_phy_wrapper_n_1358,
      \rd_ptr_reg[3]_5\(21) => u_ddr_mc_phy_wrapper_n_1359,
      \rd_ptr_reg[3]_5\(20) => u_ddr_mc_phy_wrapper_n_1360,
      \rd_ptr_reg[3]_5\(19) => u_ddr_mc_phy_wrapper_n_1361,
      \rd_ptr_reg[3]_5\(18) => u_ddr_mc_phy_wrapper_n_1362,
      \rd_ptr_reg[3]_5\(17) => u_ddr_mc_phy_wrapper_n_1363,
      \rd_ptr_reg[3]_5\(16) => u_ddr_mc_phy_wrapper_n_1364,
      \rd_ptr_reg[3]_5\(15) => u_ddr_mc_phy_wrapper_n_1365,
      \rd_ptr_reg[3]_5\(14) => u_ddr_mc_phy_wrapper_n_1366,
      \rd_ptr_reg[3]_5\(13) => u_ddr_mc_phy_wrapper_n_1367,
      \rd_ptr_reg[3]_5\(12) => u_ddr_mc_phy_wrapper_n_1368,
      \rd_ptr_reg[3]_5\(11) => u_ddr_mc_phy_wrapper_n_1369,
      \rd_ptr_reg[3]_5\(10) => u_ddr_mc_phy_wrapper_n_1370,
      \rd_ptr_reg[3]_5\(9) => u_ddr_mc_phy_wrapper_n_1371,
      \rd_ptr_reg[3]_5\(8) => u_ddr_mc_phy_wrapper_n_1372,
      \rd_ptr_reg[3]_5\(7) => u_ddr_mc_phy_wrapper_n_1373,
      \rd_ptr_reg[3]_5\(6) => u_ddr_mc_phy_wrapper_n_1374,
      \rd_ptr_reg[3]_5\(5) => u_ddr_mc_phy_wrapper_n_1375,
      \rd_ptr_reg[3]_5\(4) => u_ddr_mc_phy_wrapper_n_1376,
      \rd_ptr_reg[3]_5\(3) => u_ddr_mc_phy_wrapper_n_1377,
      \rd_ptr_reg[3]_5\(2) => u_ddr_mc_phy_wrapper_n_1378,
      \rd_ptr_reg[3]_5\(1) => u_ddr_mc_phy_wrapper_n_1379,
      \rd_ptr_reg[3]_5\(0) => u_ddr_mc_phy_wrapper_n_1380,
      \rd_ptr_reg[3]_6\(43) => u_ddr_mc_phy_wrapper_n_1381,
      \rd_ptr_reg[3]_6\(42) => u_ddr_mc_phy_wrapper_n_1382,
      \rd_ptr_reg[3]_6\(41) => u_ddr_mc_phy_wrapper_n_1383,
      \rd_ptr_reg[3]_6\(40) => u_ddr_mc_phy_wrapper_n_1384,
      \rd_ptr_reg[3]_6\(39) => u_ddr_mc_phy_wrapper_n_1385,
      \rd_ptr_reg[3]_6\(38) => u_ddr_mc_phy_wrapper_n_1386,
      \rd_ptr_reg[3]_6\(37) => u_ddr_mc_phy_wrapper_n_1387,
      \rd_ptr_reg[3]_6\(36) => u_ddr_mc_phy_wrapper_n_1388,
      \rd_ptr_reg[3]_6\(35) => u_ddr_mc_phy_wrapper_n_1389,
      \rd_ptr_reg[3]_6\(34) => u_ddr_mc_phy_wrapper_n_1390,
      \rd_ptr_reg[3]_6\(33) => u_ddr_mc_phy_wrapper_n_1391,
      \rd_ptr_reg[3]_6\(32) => u_ddr_mc_phy_wrapper_n_1392,
      \rd_ptr_reg[3]_6\(31) => u_ddr_mc_phy_wrapper_n_1393,
      \rd_ptr_reg[3]_6\(30) => u_ddr_mc_phy_wrapper_n_1394,
      \rd_ptr_reg[3]_6\(29) => u_ddr_mc_phy_wrapper_n_1395,
      \rd_ptr_reg[3]_6\(28) => u_ddr_mc_phy_wrapper_n_1396,
      \rd_ptr_reg[3]_6\(27) => u_ddr_mc_phy_wrapper_n_1397,
      \rd_ptr_reg[3]_6\(26) => u_ddr_mc_phy_wrapper_n_1398,
      \rd_ptr_reg[3]_6\(25) => u_ddr_mc_phy_wrapper_n_1399,
      \rd_ptr_reg[3]_6\(24) => u_ddr_mc_phy_wrapper_n_1400,
      \rd_ptr_reg[3]_6\(23) => u_ddr_mc_phy_wrapper_n_1401,
      \rd_ptr_reg[3]_6\(22) => u_ddr_mc_phy_wrapper_n_1402,
      \rd_ptr_reg[3]_6\(21) => u_ddr_mc_phy_wrapper_n_1403,
      \rd_ptr_reg[3]_6\(20) => u_ddr_mc_phy_wrapper_n_1404,
      \rd_ptr_reg[3]_6\(19) => u_ddr_mc_phy_wrapper_n_1405,
      \rd_ptr_reg[3]_6\(18) => u_ddr_mc_phy_wrapper_n_1406,
      \rd_ptr_reg[3]_6\(17) => u_ddr_mc_phy_wrapper_n_1407,
      \rd_ptr_reg[3]_6\(16) => u_ddr_mc_phy_wrapper_n_1408,
      \rd_ptr_reg[3]_6\(15) => u_ddr_mc_phy_wrapper_n_1409,
      \rd_ptr_reg[3]_6\(14) => u_ddr_mc_phy_wrapper_n_1410,
      \rd_ptr_reg[3]_6\(13) => u_ddr_mc_phy_wrapper_n_1411,
      \rd_ptr_reg[3]_6\(12) => u_ddr_mc_phy_wrapper_n_1412,
      \rd_ptr_reg[3]_6\(11) => u_ddr_mc_phy_wrapper_n_1413,
      \rd_ptr_reg[3]_6\(10) => u_ddr_mc_phy_wrapper_n_1414,
      \rd_ptr_reg[3]_6\(9) => u_ddr_mc_phy_wrapper_n_1415,
      \rd_ptr_reg[3]_6\(8) => u_ddr_mc_phy_wrapper_n_1416,
      \rd_ptr_reg[3]_6\(7) => u_ddr_mc_phy_wrapper_n_1417,
      \rd_ptr_reg[3]_6\(6) => u_ddr_mc_phy_wrapper_n_1418,
      \rd_ptr_reg[3]_6\(5) => u_ddr_mc_phy_wrapper_n_1419,
      \rd_ptr_reg[3]_6\(4) => u_ddr_mc_phy_wrapper_n_1420,
      \rd_ptr_reg[3]_6\(3) => u_ddr_mc_phy_wrapper_n_1421,
      \rd_ptr_reg[3]_6\(2) => u_ddr_mc_phy_wrapper_n_1422,
      \rd_ptr_reg[3]_6\(1) => u_ddr_mc_phy_wrapper_n_1423,
      \rd_ptr_reg[3]_6\(0) => u_ddr_mc_phy_wrapper_n_1424,
      \rd_ptr_reg[3]_7\(43) => u_ddr_mc_phy_wrapper_n_1425,
      \rd_ptr_reg[3]_7\(42) => u_ddr_mc_phy_wrapper_n_1426,
      \rd_ptr_reg[3]_7\(41) => u_ddr_mc_phy_wrapper_n_1427,
      \rd_ptr_reg[3]_7\(40) => u_ddr_mc_phy_wrapper_n_1428,
      \rd_ptr_reg[3]_7\(39) => u_ddr_mc_phy_wrapper_n_1429,
      \rd_ptr_reg[3]_7\(38) => u_ddr_mc_phy_wrapper_n_1430,
      \rd_ptr_reg[3]_7\(37) => u_ddr_mc_phy_wrapper_n_1431,
      \rd_ptr_reg[3]_7\(36) => u_ddr_mc_phy_wrapper_n_1432,
      \rd_ptr_reg[3]_7\(35) => u_ddr_mc_phy_wrapper_n_1433,
      \rd_ptr_reg[3]_7\(34) => u_ddr_mc_phy_wrapper_n_1434,
      \rd_ptr_reg[3]_7\(33) => u_ddr_mc_phy_wrapper_n_1435,
      \rd_ptr_reg[3]_7\(32) => u_ddr_mc_phy_wrapper_n_1436,
      \rd_ptr_reg[3]_7\(31) => u_ddr_mc_phy_wrapper_n_1437,
      \rd_ptr_reg[3]_7\(30) => u_ddr_mc_phy_wrapper_n_1438,
      \rd_ptr_reg[3]_7\(29) => u_ddr_mc_phy_wrapper_n_1439,
      \rd_ptr_reg[3]_7\(28) => u_ddr_mc_phy_wrapper_n_1440,
      \rd_ptr_reg[3]_7\(27) => u_ddr_mc_phy_wrapper_n_1441,
      \rd_ptr_reg[3]_7\(26) => u_ddr_mc_phy_wrapper_n_1442,
      \rd_ptr_reg[3]_7\(25) => u_ddr_mc_phy_wrapper_n_1443,
      \rd_ptr_reg[3]_7\(24) => u_ddr_mc_phy_wrapper_n_1444,
      \rd_ptr_reg[3]_7\(23) => u_ddr_mc_phy_wrapper_n_1445,
      \rd_ptr_reg[3]_7\(22) => u_ddr_mc_phy_wrapper_n_1446,
      \rd_ptr_reg[3]_7\(21) => u_ddr_mc_phy_wrapper_n_1447,
      \rd_ptr_reg[3]_7\(20) => u_ddr_mc_phy_wrapper_n_1448,
      \rd_ptr_reg[3]_7\(19) => u_ddr_mc_phy_wrapper_n_1449,
      \rd_ptr_reg[3]_7\(18) => u_ddr_mc_phy_wrapper_n_1450,
      \rd_ptr_reg[3]_7\(17) => u_ddr_mc_phy_wrapper_n_1451,
      \rd_ptr_reg[3]_7\(16) => u_ddr_mc_phy_wrapper_n_1452,
      \rd_ptr_reg[3]_7\(15) => u_ddr_mc_phy_wrapper_n_1453,
      \rd_ptr_reg[3]_7\(14) => u_ddr_mc_phy_wrapper_n_1454,
      \rd_ptr_reg[3]_7\(13) => u_ddr_mc_phy_wrapper_n_1455,
      \rd_ptr_reg[3]_7\(12) => u_ddr_mc_phy_wrapper_n_1456,
      \rd_ptr_reg[3]_7\(11) => u_ddr_mc_phy_wrapper_n_1457,
      \rd_ptr_reg[3]_7\(10) => u_ddr_mc_phy_wrapper_n_1458,
      \rd_ptr_reg[3]_7\(9) => u_ddr_mc_phy_wrapper_n_1459,
      \rd_ptr_reg[3]_7\(8) => u_ddr_mc_phy_wrapper_n_1460,
      \rd_ptr_reg[3]_7\(7) => u_ddr_mc_phy_wrapper_n_1461,
      \rd_ptr_reg[3]_7\(6) => u_ddr_mc_phy_wrapper_n_1462,
      \rd_ptr_reg[3]_7\(5) => u_ddr_mc_phy_wrapper_n_1463,
      \rd_ptr_reg[3]_7\(4) => u_ddr_mc_phy_wrapper_n_1464,
      \rd_ptr_reg[3]_7\(3) => u_ddr_mc_phy_wrapper_n_1465,
      \rd_ptr_reg[3]_7\(2) => u_ddr_mc_phy_wrapper_n_1466,
      \rd_ptr_reg[3]_7\(1) => u_ddr_mc_phy_wrapper_n_1467,
      \rd_ptr_reg[3]_7\(0) => u_ddr_mc_phy_wrapper_n_1468,
      \rd_ptr_timing_reg[0]\ => u_ddr_calib_top_n_45,
      \rd_ptr_timing_reg[0]_0\ => u_ddr_calib_top_n_46,
      \rd_ptr_timing_reg[0]_1\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(3 downto 0),
      \rd_ptr_timing_reg[0]_10\(44) => mux_address(49),
      \rd_ptr_timing_reg[0]_10\(43) => mux_address(35),
      \rd_ptr_timing_reg[0]_10\(42) => mux_address(21),
      \rd_ptr_timing_reg[0]_10\(41) => mux_address(7),
      \rd_ptr_timing_reg[0]_10\(40) => mux_address(48),
      \rd_ptr_timing_reg[0]_10\(39) => mux_address(34),
      \rd_ptr_timing_reg[0]_10\(38) => mux_address(20),
      \rd_ptr_timing_reg[0]_10\(37) => mux_address(6),
      \rd_ptr_timing_reg[0]_10\(36) => mux_address(47),
      \rd_ptr_timing_reg[0]_10\(35) => mux_address(33),
      \rd_ptr_timing_reg[0]_10\(34) => mux_address(19),
      \rd_ptr_timing_reg[0]_10\(33) => mux_address(5),
      \rd_ptr_timing_reg[0]_10\(32) => mux_address(45),
      \rd_ptr_timing_reg[0]_10\(31) => mux_address(31),
      \rd_ptr_timing_reg[0]_10\(30) => mux_address(17),
      \rd_ptr_timing_reg[0]_10\(29) => mux_address(3),
      \rd_ptr_timing_reg[0]_10\(28) => mux_address(46),
      \rd_ptr_timing_reg[0]_10\(27) => mux_address(32),
      \rd_ptr_timing_reg[0]_10\(26) => mux_address(18),
      \rd_ptr_timing_reg[0]_10\(25) => mux_address(4),
      \rd_ptr_timing_reg[0]_10\(24) => mux_address(44),
      \rd_ptr_timing_reg[0]_10\(23) => mux_address(30),
      \rd_ptr_timing_reg[0]_10\(22) => mux_address(16),
      \rd_ptr_timing_reg[0]_10\(21) => mux_address(2),
      \rd_ptr_timing_reg[0]_10\(20) => mux_address(43),
      \rd_ptr_timing_reg[0]_10\(19) => mux_address(29),
      \rd_ptr_timing_reg[0]_10\(18) => mux_address(15),
      \rd_ptr_timing_reg[0]_10\(17) => mux_address(1),
      \rd_ptr_timing_reg[0]_10\(16) => mux_address(42),
      \rd_ptr_timing_reg[0]_10\(15) => mux_address(28),
      \rd_ptr_timing_reg[0]_10\(14) => mux_address(14),
      \rd_ptr_timing_reg[0]_10\(13) => mux_address(0),
      \rd_ptr_timing_reg[0]_10\(12) => mux_bank(11),
      \rd_ptr_timing_reg[0]_10\(11) => mux_bank(8),
      \rd_ptr_timing_reg[0]_10\(10) => mux_bank(5),
      \rd_ptr_timing_reg[0]_10\(9) => mux_bank(2),
      \rd_ptr_timing_reg[0]_10\(8) => mux_bank(10),
      \rd_ptr_timing_reg[0]_10\(7) => mux_bank(7),
      \rd_ptr_timing_reg[0]_10\(6) => mux_bank(4),
      \rd_ptr_timing_reg[0]_10\(5) => mux_bank(1),
      \rd_ptr_timing_reg[0]_10\(4) => mux_bank(9),
      \rd_ptr_timing_reg[0]_10\(3) => mux_bank(6),
      \rd_ptr_timing_reg[0]_10\(2) => mux_bank(3),
      \rd_ptr_timing_reg[0]_10\(1) => mux_bank(0),
      \rd_ptr_timing_reg[0]_10\(0) => mux_ras_n(1),
      \rd_ptr_timing_reg[0]_2\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3 downto 0),
      \rd_ptr_timing_reg[0]_3\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(3 downto 0),
      \rd_ptr_timing_reg[0]_4\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \rd_ptr_timing_reg[0]_5\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \rd_ptr_timing_reg[0]_6\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(3 downto 0),
      \rd_ptr_timing_reg[0]_7\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(3 downto 0),
      \rd_ptr_timing_reg[0]_8\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(3 downto 0),
      \rd_ptr_timing_reg[0]_9\(4) => mux_cas_n(1),
      \rd_ptr_timing_reg[0]_9\(3) => mux_we_n(1),
      \rd_ptr_timing_reg[0]_9\(2) => mux_cs_n(1),
      \rd_ptr_timing_reg[0]_9\(1) => mux_cke(3),
      \rd_ptr_timing_reg[0]_9\(0) => mux_odt(0),
      \rdlvl_dqs_tap_cnt_r_reg[0][4][0]\(1) => u_ddr_calib_top_n_175,
      \rdlvl_dqs_tap_cnt_r_reg[0][4][0]\(0) => u_ddr_calib_top_n_176,
      rdlvl_stg1_start_r_reg => rdlvl_stg1_start_r_reg,
      rdlvl_stg1_start_reg(0) => rdlvl_stg1_start_reg(0),
      rstdiv0_sync_r1_reg_rep => in0,
      \rstdiv0_sync_r1_reg_rep__10\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__10\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__12\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__12\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__13\(3 downto 0) => \rstdiv0_sync_r1_reg_rep__13\(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__15\(0) => \rstdiv0_sync_r1_reg_rep__15\(0),
      \rstdiv0_sync_r1_reg_rep__17\(0) => \rstdiv0_sync_r1_reg_rep__17\(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__2\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__2\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \rstdiv0_sync_r1_reg_rep__22\ => \rstdiv0_sync_r1_reg_rep__22\,
      \rstdiv0_sync_r1_reg_rep__22_0\ => \rstdiv0_sync_r1_reg_rep__22_0\,
      \rstdiv0_sync_r1_reg_rep__23\ => \rstdiv0_sync_r1_reg_rep__23\,
      \rstdiv0_sync_r1_reg_rep__4\ => \rstdiv0_sync_r1_reg_rep__4\,
      \rstdiv0_sync_r1_reg_rep__5\ => \rstdiv0_sync_r1_reg_rep__5\,
      \rstdiv0_sync_r1_reg_rep__6\(0) => \rstdiv0_sync_r1_reg_rep__6\(0),
      \rstdiv0_sync_r1_reg_rep__8\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__8\(1 downto 0),
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      sent_col => sent_col,
      tempmon_sample_en => tempmon_sample_en,
      \write_buffer.wr_buf_out_data_reg[575]\(479 downto 288) => \write_buffer.wr_buf_out_data_reg[575]\(575 downto 384),
      \write_buffer.wr_buf_out_data_reg[575]\(287 downto 285) => \write_buffer.wr_buf_out_data_reg[575]\(382 downto 380),
      \write_buffer.wr_buf_out_data_reg[575]\(284 downto 282) => \write_buffer.wr_buf_out_data_reg[575]\(378 downto 376),
      \write_buffer.wr_buf_out_data_reg[575]\(281 downto 279) => \write_buffer.wr_buf_out_data_reg[575]\(374 downto 372),
      \write_buffer.wr_buf_out_data_reg[575]\(278 downto 276) => \write_buffer.wr_buf_out_data_reg[575]\(370 downto 368),
      \write_buffer.wr_buf_out_data_reg[575]\(275 downto 273) => \write_buffer.wr_buf_out_data_reg[575]\(366 downto 364),
      \write_buffer.wr_buf_out_data_reg[575]\(272 downto 270) => \write_buffer.wr_buf_out_data_reg[575]\(362 downto 360),
      \write_buffer.wr_buf_out_data_reg[575]\(269 downto 267) => \write_buffer.wr_buf_out_data_reg[575]\(358 downto 356),
      \write_buffer.wr_buf_out_data_reg[575]\(266 downto 264) => \write_buffer.wr_buf_out_data_reg[575]\(354 downto 352),
      \write_buffer.wr_buf_out_data_reg[575]\(263 downto 261) => \write_buffer.wr_buf_out_data_reg[575]\(350 downto 348),
      \write_buffer.wr_buf_out_data_reg[575]\(260 downto 258) => \write_buffer.wr_buf_out_data_reg[575]\(346 downto 344),
      \write_buffer.wr_buf_out_data_reg[575]\(257 downto 255) => \write_buffer.wr_buf_out_data_reg[575]\(342 downto 340),
      \write_buffer.wr_buf_out_data_reg[575]\(254 downto 252) => \write_buffer.wr_buf_out_data_reg[575]\(338 downto 336),
      \write_buffer.wr_buf_out_data_reg[575]\(251 downto 249) => \write_buffer.wr_buf_out_data_reg[575]\(334 downto 332),
      \write_buffer.wr_buf_out_data_reg[575]\(248 downto 246) => \write_buffer.wr_buf_out_data_reg[575]\(330 downto 328),
      \write_buffer.wr_buf_out_data_reg[575]\(245 downto 243) => \write_buffer.wr_buf_out_data_reg[575]\(326 downto 324),
      \write_buffer.wr_buf_out_data_reg[575]\(242 downto 239) => \write_buffer.wr_buf_out_data_reg[575]\(322 downto 319),
      \write_buffer.wr_buf_out_data_reg[575]\(238 downto 236) => \write_buffer.wr_buf_out_data_reg[575]\(317 downto 315),
      \write_buffer.wr_buf_out_data_reg[575]\(235 downto 233) => \write_buffer.wr_buf_out_data_reg[575]\(313 downto 311),
      \write_buffer.wr_buf_out_data_reg[575]\(232 downto 230) => \write_buffer.wr_buf_out_data_reg[575]\(309 downto 307),
      \write_buffer.wr_buf_out_data_reg[575]\(229 downto 227) => \write_buffer.wr_buf_out_data_reg[575]\(305 downto 303),
      \write_buffer.wr_buf_out_data_reg[575]\(226 downto 224) => \write_buffer.wr_buf_out_data_reg[575]\(301 downto 299),
      \write_buffer.wr_buf_out_data_reg[575]\(223 downto 221) => \write_buffer.wr_buf_out_data_reg[575]\(297 downto 295),
      \write_buffer.wr_buf_out_data_reg[575]\(220 downto 218) => \write_buffer.wr_buf_out_data_reg[575]\(293 downto 291),
      \write_buffer.wr_buf_out_data_reg[575]\(217 downto 215) => \write_buffer.wr_buf_out_data_reg[575]\(289 downto 287),
      \write_buffer.wr_buf_out_data_reg[575]\(214 downto 212) => \write_buffer.wr_buf_out_data_reg[575]\(285 downto 283),
      \write_buffer.wr_buf_out_data_reg[575]\(211 downto 209) => \write_buffer.wr_buf_out_data_reg[575]\(281 downto 279),
      \write_buffer.wr_buf_out_data_reg[575]\(208 downto 206) => \write_buffer.wr_buf_out_data_reg[575]\(277 downto 275),
      \write_buffer.wr_buf_out_data_reg[575]\(205 downto 203) => \write_buffer.wr_buf_out_data_reg[575]\(273 downto 271),
      \write_buffer.wr_buf_out_data_reg[575]\(202 downto 200) => \write_buffer.wr_buf_out_data_reg[575]\(269 downto 267),
      \write_buffer.wr_buf_out_data_reg[575]\(199 downto 197) => \write_buffer.wr_buf_out_data_reg[575]\(265 downto 263),
      \write_buffer.wr_buf_out_data_reg[575]\(196 downto 194) => \write_buffer.wr_buf_out_data_reg[575]\(261 downto 259),
      \write_buffer.wr_buf_out_data_reg[575]\(193 downto 191) => \write_buffer.wr_buf_out_data_reg[575]\(257 downto 255),
      \write_buffer.wr_buf_out_data_reg[575]\(190 downto 188) => \write_buffer.wr_buf_out_data_reg[575]\(253 downto 251),
      \write_buffer.wr_buf_out_data_reg[575]\(187 downto 185) => \write_buffer.wr_buf_out_data_reg[575]\(249 downto 247),
      \write_buffer.wr_buf_out_data_reg[575]\(184 downto 182) => \write_buffer.wr_buf_out_data_reg[575]\(245 downto 243),
      \write_buffer.wr_buf_out_data_reg[575]\(181 downto 179) => \write_buffer.wr_buf_out_data_reg[575]\(241 downto 239),
      \write_buffer.wr_buf_out_data_reg[575]\(178 downto 176) => \write_buffer.wr_buf_out_data_reg[575]\(237 downto 235),
      \write_buffer.wr_buf_out_data_reg[575]\(175 downto 173) => \write_buffer.wr_buf_out_data_reg[575]\(233 downto 231),
      \write_buffer.wr_buf_out_data_reg[575]\(172 downto 170) => \write_buffer.wr_buf_out_data_reg[575]\(229 downto 227),
      \write_buffer.wr_buf_out_data_reg[575]\(169 downto 167) => \write_buffer.wr_buf_out_data_reg[575]\(225 downto 223),
      \write_buffer.wr_buf_out_data_reg[575]\(166 downto 164) => \write_buffer.wr_buf_out_data_reg[575]\(221 downto 219),
      \write_buffer.wr_buf_out_data_reg[575]\(163 downto 161) => \write_buffer.wr_buf_out_data_reg[575]\(217 downto 215),
      \write_buffer.wr_buf_out_data_reg[575]\(160 downto 158) => \write_buffer.wr_buf_out_data_reg[575]\(213 downto 211),
      \write_buffer.wr_buf_out_data_reg[575]\(157 downto 155) => \write_buffer.wr_buf_out_data_reg[575]\(209 downto 207),
      \write_buffer.wr_buf_out_data_reg[575]\(154 downto 152) => \write_buffer.wr_buf_out_data_reg[575]\(205 downto 203),
      \write_buffer.wr_buf_out_data_reg[575]\(151 downto 149) => \write_buffer.wr_buf_out_data_reg[575]\(201 downto 199),
      \write_buffer.wr_buf_out_data_reg[575]\(148 downto 146) => \write_buffer.wr_buf_out_data_reg[575]\(197 downto 195),
      \write_buffer.wr_buf_out_data_reg[575]\(145 downto 142) => \write_buffer.wr_buf_out_data_reg[575]\(193 downto 190),
      \write_buffer.wr_buf_out_data_reg[575]\(141 downto 139) => \write_buffer.wr_buf_out_data_reg[575]\(188 downto 186),
      \write_buffer.wr_buf_out_data_reg[575]\(138 downto 136) => \write_buffer.wr_buf_out_data_reg[575]\(184 downto 182),
      \write_buffer.wr_buf_out_data_reg[575]\(135 downto 133) => \write_buffer.wr_buf_out_data_reg[575]\(180 downto 178),
      \write_buffer.wr_buf_out_data_reg[575]\(132 downto 130) => \write_buffer.wr_buf_out_data_reg[575]\(176 downto 174),
      \write_buffer.wr_buf_out_data_reg[575]\(129 downto 127) => \write_buffer.wr_buf_out_data_reg[575]\(172 downto 170),
      \write_buffer.wr_buf_out_data_reg[575]\(126 downto 124) => \write_buffer.wr_buf_out_data_reg[575]\(168 downto 166),
      \write_buffer.wr_buf_out_data_reg[575]\(123 downto 121) => \write_buffer.wr_buf_out_data_reg[575]\(164 downto 162),
      \write_buffer.wr_buf_out_data_reg[575]\(120 downto 118) => \write_buffer.wr_buf_out_data_reg[575]\(160 downto 158),
      \write_buffer.wr_buf_out_data_reg[575]\(117 downto 115) => \write_buffer.wr_buf_out_data_reg[575]\(156 downto 154),
      \write_buffer.wr_buf_out_data_reg[575]\(114 downto 112) => \write_buffer.wr_buf_out_data_reg[575]\(152 downto 150),
      \write_buffer.wr_buf_out_data_reg[575]\(111 downto 109) => \write_buffer.wr_buf_out_data_reg[575]\(148 downto 146),
      \write_buffer.wr_buf_out_data_reg[575]\(108 downto 106) => \write_buffer.wr_buf_out_data_reg[575]\(144 downto 142),
      \write_buffer.wr_buf_out_data_reg[575]\(105 downto 103) => \write_buffer.wr_buf_out_data_reg[575]\(140 downto 138),
      \write_buffer.wr_buf_out_data_reg[575]\(102 downto 100) => \write_buffer.wr_buf_out_data_reg[575]\(136 downto 134),
      \write_buffer.wr_buf_out_data_reg[575]\(99 downto 97) => \write_buffer.wr_buf_out_data_reg[575]\(132 downto 130),
      \write_buffer.wr_buf_out_data_reg[575]\(96 downto 32) => \write_buffer.wr_buf_out_data_reg[575]\(128 downto 64),
      \write_buffer.wr_buf_out_data_reg[575]\(31 downto 30) => \write_buffer.wr_buf_out_data_reg[575]\(62 downto 61),
      \write_buffer.wr_buf_out_data_reg[575]\(29 downto 28) => \write_buffer.wr_buf_out_data_reg[575]\(58 downto 57),
      \write_buffer.wr_buf_out_data_reg[575]\(27 downto 26) => \write_buffer.wr_buf_out_data_reg[575]\(54 downto 53),
      \write_buffer.wr_buf_out_data_reg[575]\(25 downto 24) => \write_buffer.wr_buf_out_data_reg[575]\(50 downto 49),
      \write_buffer.wr_buf_out_data_reg[575]\(23 downto 22) => \write_buffer.wr_buf_out_data_reg[575]\(46 downto 45),
      \write_buffer.wr_buf_out_data_reg[575]\(21 downto 20) => \write_buffer.wr_buf_out_data_reg[575]\(42 downto 41),
      \write_buffer.wr_buf_out_data_reg[575]\(19 downto 18) => \write_buffer.wr_buf_out_data_reg[575]\(38 downto 37),
      \write_buffer.wr_buf_out_data_reg[575]\(17 downto 16) => \write_buffer.wr_buf_out_data_reg[575]\(34 downto 33),
      \write_buffer.wr_buf_out_data_reg[575]\(15 downto 14) => \write_buffer.wr_buf_out_data_reg[575]\(30 downto 29),
      \write_buffer.wr_buf_out_data_reg[575]\(13 downto 12) => \write_buffer.wr_buf_out_data_reg[575]\(26 downto 25),
      \write_buffer.wr_buf_out_data_reg[575]\(11 downto 10) => \write_buffer.wr_buf_out_data_reg[575]\(22 downto 21),
      \write_buffer.wr_buf_out_data_reg[575]\(9 downto 8) => \write_buffer.wr_buf_out_data_reg[575]\(18 downto 17),
      \write_buffer.wr_buf_out_data_reg[575]\(7 downto 6) => \write_buffer.wr_buf_out_data_reg[575]\(14 downto 13),
      \write_buffer.wr_buf_out_data_reg[575]\(5 downto 4) => \write_buffer.wr_buf_out_data_reg[575]\(10 downto 9),
      \write_buffer.wr_buf_out_data_reg[575]\(3 downto 2) => \write_buffer.wr_buf_out_data_reg[575]\(6 downto 5),
      \write_buffer.wr_buf_out_data_reg[575]\(1 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(2 downto 1)
    );
u_ddr_mc_phy_wrapper: entity work.mig_7series_0_mig_7series_v2_3_ddr_mc_phy_wrapper
     port map (
      A_rst_primitives => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_rst_primitives\,
      A_rst_primitives_4 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_rst_primitives\,
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      COUNTERLOADVAL(5) => u_ddr_calib_top_n_65,
      COUNTERLOADVAL(4) => u_ddr_calib_top_n_66,
      COUNTERLOADVAL(3) => u_ddr_calib_top_n_67,
      COUNTERLOADVAL(2) => u_ddr_calib_top_n_68,
      COUNTERLOADVAL(1) => u_ddr_calib_top_n_69,
      COUNTERLOADVAL(0) => u_ddr_calib_top_n_70,
      COUNTERREADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/A_pi_counter_read_val\(5 downto 0),
      D(5) => u_ddr_calib_top_n_1219,
      D(4) => u_ddr_calib_top_n_1220,
      D(3) => u_ddr_calib_top_n_1221,
      D(2) => u_ddr_calib_top_n_1222,
      D(1) => u_ddr_calib_top_n_1223,
      D(0) => u_ddr_calib_top_n_1224,
      D0(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0\(1),
      D1(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(3 downto 0),
      D2(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(3 downto 0),
      D3(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3 downto 0),
      D4(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(3 downto 0),
      D5(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(5),
      D5(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(1),
      D6(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(5),
      D7(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(3 downto 0),
      D8(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(3 downto 0),
      D9(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(3 downto 0),
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      D_po_coarse_enable105_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable105_out\,
      D_po_counter_read_en117_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en117_out\,
      D_po_fine_enable102_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable102_out\,
      D_po_fine_inc108_out => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc108_out\,
      LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_10 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_12 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_14 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      LD0_6 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0\,
      LD0_7 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0\,
      LD0_8 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\,
      LD0_9 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\,
      Q(0) => Q(0),
      RST0 => RST0,
      SR(0) => SR(0),
      \calib_sel_reg[0]\ => u_ddr_calib_top_n_104,
      \calib_sel_reg[0]_0\ => u_ddr_calib_top_n_114,
      \calib_sel_reg[0]_1\ => u_ddr_calib_top_n_150,
      \calib_sel_reg[0]_2\ => u_ddr_calib_top_n_152,
      \calib_sel_reg[1]\ => u_ddr_calib_top_n_72,
      \calib_sel_reg[1]_0\ => u_ddr_calib_top_n_75,
      \calib_sel_reg[1]_1\ => u_ddr_calib_top_n_64,
      \calib_sel_reg[1]_10\ => u_ddr_calib_top_n_96,
      \calib_sel_reg[1]_11\ => u_ddr_calib_top_n_94,
      \calib_sel_reg[1]_12\ => u_ddr_calib_top_n_105,
      \calib_sel_reg[1]_13\ => u_ddr_calib_top_n_108,
      \calib_sel_reg[1]_14\ => u_ddr_calib_top_n_107,
      \calib_sel_reg[1]_15\(5) => u_ddr_calib_top_n_117,
      \calib_sel_reg[1]_15\(4) => u_ddr_calib_top_n_118,
      \calib_sel_reg[1]_15\(3) => u_ddr_calib_top_n_119,
      \calib_sel_reg[1]_15\(2) => u_ddr_calib_top_n_120,
      \calib_sel_reg[1]_15\(1) => u_ddr_calib_top_n_121,
      \calib_sel_reg[1]_15\(0) => u_ddr_calib_top_n_122,
      \calib_sel_reg[1]_16\ => u_ddr_calib_top_n_99,
      \calib_sel_reg[1]_17\ => u_ddr_calib_top_n_106,
      \calib_sel_reg[1]_18\ => u_ddr_calib_top_n_109,
      \calib_sel_reg[1]_19\ => u_ddr_calib_top_n_112,
      \calib_sel_reg[1]_2\ => u_ddr_calib_top_n_74,
      \calib_sel_reg[1]_20\ => u_ddr_calib_top_n_103,
      \calib_sel_reg[1]_21\ => u_ddr_calib_top_n_111,
      \calib_sel_reg[1]_22\(5) => u_ddr_calib_top_n_123,
      \calib_sel_reg[1]_22\(4) => u_ddr_calib_top_n_124,
      \calib_sel_reg[1]_22\(3) => u_ddr_calib_top_n_125,
      \calib_sel_reg[1]_22\(2) => u_ddr_calib_top_n_126,
      \calib_sel_reg[1]_22\(1) => u_ddr_calib_top_n_127,
      \calib_sel_reg[1]_22\(0) => u_ddr_calib_top_n_128,
      \calib_sel_reg[1]_23\ => u_ddr_calib_top_n_102,
      \calib_sel_reg[1]_24\ => u_ddr_calib_top_n_110,
      \calib_sel_reg[1]_25\ => u_ddr_calib_top_n_101,
      \calib_sel_reg[1]_26\ => u_ddr_calib_top_n_143,
      \calib_sel_reg[1]_27\ => u_ddr_calib_top_n_146,
      \calib_sel_reg[1]_28\ => u_ddr_calib_top_n_135,
      \calib_sel_reg[1]_29\ => u_ddr_calib_top_n_145,
      \calib_sel_reg[1]_3\ => u_ddr_calib_top_n_73,
      \calib_sel_reg[1]_30\(5) => u_ddr_calib_top_n_136,
      \calib_sel_reg[1]_30\(4) => u_ddr_calib_top_n_137,
      \calib_sel_reg[1]_30\(3) => u_ddr_calib_top_n_138,
      \calib_sel_reg[1]_30\(2) => u_ddr_calib_top_n_139,
      \calib_sel_reg[1]_30\(1) => u_ddr_calib_top_n_140,
      \calib_sel_reg[1]_30\(0) => u_ddr_calib_top_n_141,
      \calib_sel_reg[1]_31\ => u_ddr_calib_top_n_144,
      \calib_sel_reg[1]_32\ => u_ddr_calib_top_n_142,
      \calib_sel_reg[1]_33\ => u_ddr_calib_top_n_155,
      \calib_sel_reg[1]_34\ => u_ddr_calib_top_n_158,
      \calib_sel_reg[1]_35\ => u_ddr_calib_top_n_148,
      \calib_sel_reg[1]_36\ => u_ddr_calib_top_n_157,
      \calib_sel_reg[1]_37\(5) => u_ddr_calib_top_n_165,
      \calib_sel_reg[1]_37\(4) => u_ddr_calib_top_n_166,
      \calib_sel_reg[1]_37\(3) => u_ddr_calib_top_n_167,
      \calib_sel_reg[1]_37\(2) => u_ddr_calib_top_n_168,
      \calib_sel_reg[1]_37\(1) => u_ddr_calib_top_n_169,
      \calib_sel_reg[1]_37\(0) => u_ddr_calib_top_n_170,
      \calib_sel_reg[1]_38\ => u_ddr_calib_top_n_147,
      \calib_sel_reg[1]_39\ => u_ddr_calib_top_n_156,
      \calib_sel_reg[1]_4\ => u_ddr_calib_top_n_71,
      \calib_sel_reg[1]_5\ => u_ddr_calib_top_n_95,
      \calib_sel_reg[1]_6\ => u_ddr_calib_top_n_98,
      \calib_sel_reg[1]_7\ => u_ddr_calib_top_n_87,
      \calib_sel_reg[1]_8\ => u_ddr_calib_top_n_97,
      \calib_sel_reg[1]_9\(5) => u_ddr_calib_top_n_88,
      \calib_sel_reg[1]_9\(4) => u_ddr_calib_top_n_89,
      \calib_sel_reg[1]_9\(3) => u_ddr_calib_top_n_90,
      \calib_sel_reg[1]_9\(2) => u_ddr_calib_top_n_91,
      \calib_sel_reg[1]_9\(1) => u_ddr_calib_top_n_92,
      \calib_sel_reg[1]_9\(0) => u_ddr_calib_top_n_93,
      \calib_sel_reg[4]\(3 downto 2) => calib_sel(4 downto 3),
      \calib_sel_reg[4]\(1 downto 0) => calib_sel(1 downto 0),
      \calib_seq_reg[1]\(10 downto 3) => phy_ctl_wd(24 downto 17),
      \calib_seq_reg[1]\(2 downto 0) => phy_ctl_wd(2 downto 0),
      ck_po_stg2_f_indec_reg => u_ddr_calib_top_n_200,
      ck_po_stg2_f_indec_reg_0 => u_ddr_calib_top_n_202,
      ck_po_stg2_f_indec_reg_1 => u_ddr_calib_top_n_201,
      ck_po_stg2_f_indec_reg_2 => u_ddr_calib_top_n_193,
      ck_po_stg2_f_indec_reg_3 => u_ddr_calib_top_n_194,
      ck_po_stg2_f_indec_reg_4 => u_ddr_calib_top_n_195,
      ck_po_stg2_f_indec_reg_5 => u_ddr_calib_top_n_196,
      ck_po_stg2_f_indec_reg_6 => u_ddr_calib_top_n_197,
      ck_po_stg2_f_indec_reg_7 => u_ddr_calib_top_n_198,
      ck_po_stg2_f_indec_reg_8 => u_ddr_calib_top_n_199,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5 downto 0) => data_offset_1(5 downto 0),
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5 downto 0) => data_offset_2(5 downto 0),
      \cmd_pipe_plus.mc_we_n_reg[2]\(1) => \cmd_pipe_plus.mc_we_n_reg[2]\(2),
      \cmd_pipe_plus.mc_we_n_reg[2]\(0) => \cmd_pipe_plus.mc_we_n_reg[2]\(0),
      cnt_pwron_cke_done_r => \u_ddr_phy_init/cnt_pwron_cke_done_r\,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\,
      dqs_wl_po_stg2_c_incdec_reg => u_ddr_calib_top_n_100,
      dqs_wl_po_stg2_c_incdec_reg_0 => u_ddr_calib_top_n_149,
      freq_refclk => freq_refclk,
      \gen_byte_sel_div2.calib_in_common_reg\ => u_ddr_calib_top_n_58,
      \gen_byte_sel_div2.calib_in_common_reg_0\ => u_ddr_calib_top_n_82,
      \gen_byte_sel_div2.calib_in_common_reg_1\ => u_ddr_calib_top_n_78,
      \gen_byte_sel_div2.calib_in_common_reg_2\ => u_ddr_calib_top_n_76,
      \gen_byte_sel_div2.calib_in_common_reg_3\ => u_ddr_calib_top_n_81,
      \gen_byte_sel_div2.calib_in_common_reg_4\ => u_ddr_calib_top_n_77,
      \gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_695,
      \gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_707,
      \gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_719,
      \gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_730,
      \gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_672,
      \gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_702,
      \gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_713,
      \gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_685,
      \gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_696,
      \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_708,
      \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_720,
      \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_731,
      \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_673,
      \gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_703,
      \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_680,
      \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_686,
      \gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_697,
      \gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_709,
      \gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_721,
      \gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_687,
      \gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_689,
      \gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_704,
      \gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_714,
      \gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_724,
      \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_674,
      \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_678,
      \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_682,
      \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_732,
      \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_690,
      \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_705,
      \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_715,
      \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_725,
      \gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_698,
      \gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_710,
      \gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_722,
      \gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_733,
      \gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_691,
      \gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_706,
      \gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_716,
      \gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_726,
      \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_699,
      \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_711,
      \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_683,
      \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_734,
      \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_692,
      \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_675,
      \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_717,
      \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_727,
      \gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_700,
      \gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_712,
      \gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_723,
      \gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_735,
      \gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_693,
      \gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_676,
      \gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_681,
      \gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_728,
      \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_701,
      \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_679,
      \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_684,
      \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_688,
      \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_694,
      \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_677,
      \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_718,
      \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_729,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1627,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1667,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1643,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1619,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1659,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1635,
      \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\ => u_ddr_mc_phy_wrapper_n_1651,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1628,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1668,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1644,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1620,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1660,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1612,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1636,
      \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ => u_ddr_mc_phy_wrapper_n_1652,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1629,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1669,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1645,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1621,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1661,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1613,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1637,
      \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\ => u_ddr_mc_phy_wrapper_n_1653,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1630,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1670,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1646,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1622,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1662,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1614,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1638,
      \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ => u_ddr_mc_phy_wrapper_n_1654,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1631,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1671,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1647,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1623,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1663,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1615,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1639,
      \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\ => u_ddr_mc_phy_wrapper_n_1655,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1632,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1672,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1648,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1624,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1664,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1616,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1640,
      \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ => u_ddr_mc_phy_wrapper_n_1656,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1633,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1673,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1649,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1625,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1665,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1617,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1641,
      \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\ => u_ddr_mc_phy_wrapper_n_1657,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1634,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1674,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1650,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1626,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1666,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1618,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1642,
      \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ => u_ddr_mc_phy_wrapper_n_1658,
      idelay_ce_r2_reg => u_ddr_calib_top_n_113,
      idelay_ce_r2_reg_0 => u_ddr_calib_top_n_151,
      idelay_inc => idelay_inc,
      idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_3 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst\,
      idelay_ld_rst_5 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst\,
      idle => idle,
      ififo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ififo_rst_reg0\,
      in0 => in0,
      init_calib_complete_reg(21) => \^init_calib_complete\,
      init_calib_complete_reg(20) => mux_address(41),
      init_calib_complete_reg(19) => mux_address(27),
      init_calib_complete_reg(18) => mux_address(13),
      init_calib_complete_reg(17) => mux_address(54),
      init_calib_complete_reg(16) => mux_address(40),
      init_calib_complete_reg(15) => mux_address(26),
      init_calib_complete_reg(14) => mux_address(12),
      init_calib_complete_reg(13) => mux_address(39),
      init_calib_complete_reg(12) => mux_address(11),
      init_calib_complete_reg(11) => mux_address(52),
      init_calib_complete_reg(10) => mux_address(38),
      init_calib_complete_reg(9) => mux_address(24),
      init_calib_complete_reg(8) => mux_address(10),
      init_calib_complete_reg(7) => mux_address(51),
      init_calib_complete_reg(6) => mux_address(37),
      init_calib_complete_reg(5) => mux_address(23),
      init_calib_complete_reg(4) => mux_address(9),
      init_calib_complete_reg(3) => mux_address(50),
      init_calib_complete_reg(2) => mux_address(36),
      init_calib_complete_reg(1) => mux_address(22),
      init_calib_complete_reg(0) => mux_address(8),
      init_calib_complete_reg_rep => u_ddr_calib_top_n_34,
      \init_calib_complete_reg_rep__0\ => u_ddr_calib_top_n_35,
      \init_calib_complete_reg_rep__1\ => u_ddr_calib_top_n_36,
      \init_calib_complete_reg_rep__10\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(3 downto 0),
      \init_calib_complete_reg_rep__10_0\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(3 downto 0),
      \init_calib_complete_reg_rep__10_1\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(3 downto 0),
      \init_calib_complete_reg_rep__10_2\ => u_ddr_calib_top_n_45,
      \init_calib_complete_reg_rep__11\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0),
      \init_calib_complete_reg_rep__11_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0),
      \init_calib_complete_reg_rep__11_1\ => u_ddr_calib_top_n_46,
      \init_calib_complete_reg_rep__12\ => \^app_zq_r_reg\,
      \init_calib_complete_reg_rep__12_0\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(3 downto 0),
      \init_calib_complete_reg_rep__12_1\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(3 downto 0),
      \init_calib_complete_reg_rep__12_2\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3 downto 0),
      \init_calib_complete_reg_rep__2\ => u_ddr_calib_top_n_37,
      \init_calib_complete_reg_rep__25\(45) => mux_address(49),
      \init_calib_complete_reg_rep__25\(44) => mux_address(35),
      \init_calib_complete_reg_rep__25\(43) => mux_address(21),
      \init_calib_complete_reg_rep__25\(42) => mux_address(7),
      \init_calib_complete_reg_rep__25\(41) => mux_address(48),
      \init_calib_complete_reg_rep__25\(40) => mux_address(34),
      \init_calib_complete_reg_rep__25\(39) => mux_address(20),
      \init_calib_complete_reg_rep__25\(38) => mux_address(6),
      \init_calib_complete_reg_rep__25\(37) => mux_address(47),
      \init_calib_complete_reg_rep__25\(36) => mux_address(33),
      \init_calib_complete_reg_rep__25\(35) => mux_address(19),
      \init_calib_complete_reg_rep__25\(34) => mux_address(5),
      \init_calib_complete_reg_rep__25\(33) => mux_address(45),
      \init_calib_complete_reg_rep__25\(32) => mux_address(31),
      \init_calib_complete_reg_rep__25\(31) => mux_address(17),
      \init_calib_complete_reg_rep__25\(30) => mux_address(3),
      \init_calib_complete_reg_rep__25\(29) => mux_address(46),
      \init_calib_complete_reg_rep__25\(28) => mux_address(32),
      \init_calib_complete_reg_rep__25\(27) => mux_address(18),
      \init_calib_complete_reg_rep__25\(26) => mux_address(4),
      \init_calib_complete_reg_rep__25\(25) => mux_address(44),
      \init_calib_complete_reg_rep__25\(24) => mux_address(30),
      \init_calib_complete_reg_rep__25\(23) => mux_address(16),
      \init_calib_complete_reg_rep__25\(22) => mux_address(2),
      \init_calib_complete_reg_rep__25\(21) => mux_address(43),
      \init_calib_complete_reg_rep__25\(20) => mux_address(29),
      \init_calib_complete_reg_rep__25\(19) => mux_address(15),
      \init_calib_complete_reg_rep__25\(18) => mux_address(1),
      \init_calib_complete_reg_rep__25\(17) => mux_address(42),
      \init_calib_complete_reg_rep__25\(16) => mux_address(28),
      \init_calib_complete_reg_rep__25\(15) => mux_address(14),
      \init_calib_complete_reg_rep__25\(14) => mux_address(0),
      \init_calib_complete_reg_rep__25\(13) => mux_bank(11),
      \init_calib_complete_reg_rep__25\(12) => mux_bank(8),
      \init_calib_complete_reg_rep__25\(11) => mux_bank(5),
      \init_calib_complete_reg_rep__25\(10) => mux_bank(2),
      \init_calib_complete_reg_rep__25\(9) => mux_bank(10),
      \init_calib_complete_reg_rep__25\(8) => mux_bank(7),
      \init_calib_complete_reg_rep__25\(7) => mux_bank(4),
      \init_calib_complete_reg_rep__25\(6) => mux_bank(1),
      \init_calib_complete_reg_rep__25\(5) => mux_bank(9),
      \init_calib_complete_reg_rep__25\(4) => mux_bank(6),
      \init_calib_complete_reg_rep__25\(3) => mux_bank(3),
      \init_calib_complete_reg_rep__25\(2) => mux_bank(0),
      \init_calib_complete_reg_rep__25\(1) => mux_ras_n(1),
      \init_calib_complete_reg_rep__25\(0) => \cmd_pipe_plus.mc_ras_n_reg[0]\(0),
      \init_calib_complete_reg_rep__3\ => u_ddr_calib_top_n_38,
      \init_calib_complete_reg_rep__4\ => u_ddr_calib_top_n_39,
      \init_calib_complete_reg_rep__5\ => u_ddr_calib_top_n_40,
      \init_calib_complete_reg_rep__6\ => u_ddr_calib_top_n_41,
      \init_calib_complete_reg_rep__7\ => u_ddr_calib_top_n_42,
      \init_calib_complete_reg_rep__8\ => u_ddr_calib_top_n_43,
      \init_calib_complete_reg_rep__9\ => u_ddr_calib_top_n_44,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      mc_address(3) => mc_address(38),
      mc_address(2) => mc_address(36),
      mc_address(1) => mc_address(13),
      mc_address(0) => mc_address(11),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_ras_n(1) => mc_ras_n(2),
      mc_ras_n(0) => mc_ras_n(0),
      mem_out(10) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(53),
      mem_out(9) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(45),
      mem_out(8) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(41),
      mem_out(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(27 downto 24),
      mem_out(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(11 downto 8),
      mem_refclk => mem_refclk,
      mux_reset_n => mux_reset_n,
      mux_wrdata(415 downto 288) => mux_wrdata(511 downto 384),
      mux_wrdata(287 downto 285) => mux_wrdata(382 downto 380),
      mux_wrdata(284 downto 282) => mux_wrdata(378 downto 376),
      mux_wrdata(281 downto 279) => mux_wrdata(374 downto 372),
      mux_wrdata(278 downto 276) => mux_wrdata(370 downto 368),
      mux_wrdata(275 downto 273) => mux_wrdata(366 downto 364),
      mux_wrdata(272 downto 270) => mux_wrdata(362 downto 360),
      mux_wrdata(269 downto 267) => mux_wrdata(358 downto 356),
      mux_wrdata(266 downto 264) => mux_wrdata(354 downto 352),
      mux_wrdata(263 downto 261) => mux_wrdata(350 downto 348),
      mux_wrdata(260 downto 258) => mux_wrdata(346 downto 344),
      mux_wrdata(257 downto 255) => mux_wrdata(342 downto 340),
      mux_wrdata(254 downto 252) => mux_wrdata(338 downto 336),
      mux_wrdata(251 downto 249) => mux_wrdata(334 downto 332),
      mux_wrdata(248 downto 246) => mux_wrdata(330 downto 328),
      mux_wrdata(245 downto 243) => mux_wrdata(326 downto 324),
      mux_wrdata(242 downto 239) => mux_wrdata(322 downto 319),
      mux_wrdata(238 downto 236) => mux_wrdata(317 downto 315),
      mux_wrdata(235 downto 233) => mux_wrdata(313 downto 311),
      mux_wrdata(232 downto 230) => mux_wrdata(309 downto 307),
      mux_wrdata(229 downto 227) => mux_wrdata(305 downto 303),
      mux_wrdata(226 downto 224) => mux_wrdata(301 downto 299),
      mux_wrdata(223 downto 221) => mux_wrdata(297 downto 295),
      mux_wrdata(220 downto 218) => mux_wrdata(293 downto 291),
      mux_wrdata(217 downto 215) => mux_wrdata(289 downto 287),
      mux_wrdata(214 downto 212) => mux_wrdata(285 downto 283),
      mux_wrdata(211 downto 209) => mux_wrdata(281 downto 279),
      mux_wrdata(208 downto 206) => mux_wrdata(277 downto 275),
      mux_wrdata(205 downto 203) => mux_wrdata(273 downto 271),
      mux_wrdata(202 downto 200) => mux_wrdata(269 downto 267),
      mux_wrdata(199 downto 197) => mux_wrdata(265 downto 263),
      mux_wrdata(196 downto 194) => mux_wrdata(261 downto 259),
      mux_wrdata(193 downto 191) => mux_wrdata(257 downto 255),
      mux_wrdata(190 downto 188) => mux_wrdata(253 downto 251),
      mux_wrdata(187 downto 185) => mux_wrdata(249 downto 247),
      mux_wrdata(184 downto 182) => mux_wrdata(245 downto 243),
      mux_wrdata(181 downto 179) => mux_wrdata(241 downto 239),
      mux_wrdata(178 downto 176) => mux_wrdata(237 downto 235),
      mux_wrdata(175 downto 173) => mux_wrdata(233 downto 231),
      mux_wrdata(172 downto 170) => mux_wrdata(229 downto 227),
      mux_wrdata(169 downto 167) => mux_wrdata(225 downto 223),
      mux_wrdata(166 downto 164) => mux_wrdata(221 downto 219),
      mux_wrdata(163 downto 161) => mux_wrdata(217 downto 215),
      mux_wrdata(160 downto 158) => mux_wrdata(213 downto 211),
      mux_wrdata(157 downto 155) => mux_wrdata(209 downto 207),
      mux_wrdata(154 downto 152) => mux_wrdata(205 downto 203),
      mux_wrdata(151 downto 149) => mux_wrdata(201 downto 199),
      mux_wrdata(148 downto 146) => mux_wrdata(197 downto 195),
      mux_wrdata(145 downto 142) => mux_wrdata(193 downto 190),
      mux_wrdata(141 downto 139) => mux_wrdata(188 downto 186),
      mux_wrdata(138 downto 136) => mux_wrdata(184 downto 182),
      mux_wrdata(135 downto 133) => mux_wrdata(180 downto 178),
      mux_wrdata(132 downto 130) => mux_wrdata(176 downto 174),
      mux_wrdata(129 downto 127) => mux_wrdata(172 downto 170),
      mux_wrdata(126 downto 124) => mux_wrdata(168 downto 166),
      mux_wrdata(123 downto 121) => mux_wrdata(164 downto 162),
      mux_wrdata(120 downto 118) => mux_wrdata(160 downto 158),
      mux_wrdata(117 downto 115) => mux_wrdata(156 downto 154),
      mux_wrdata(114 downto 112) => mux_wrdata(152 downto 150),
      mux_wrdata(111 downto 109) => mux_wrdata(148 downto 146),
      mux_wrdata(108 downto 106) => mux_wrdata(144 downto 142),
      mux_wrdata(105 downto 103) => mux_wrdata(140 downto 138),
      mux_wrdata(102 downto 100) => mux_wrdata(136 downto 134),
      mux_wrdata(99 downto 97) => mux_wrdata(132 downto 130),
      mux_wrdata(96 downto 32) => mux_wrdata(128 downto 64),
      mux_wrdata(31 downto 30) => mux_wrdata(62 downto 61),
      mux_wrdata(29 downto 28) => mux_wrdata(58 downto 57),
      mux_wrdata(27 downto 26) => mux_wrdata(54 downto 53),
      mux_wrdata(25 downto 24) => mux_wrdata(50 downto 49),
      mux_wrdata(23 downto 22) => mux_wrdata(46 downto 45),
      mux_wrdata(21 downto 20) => mux_wrdata(42 downto 41),
      mux_wrdata(19 downto 18) => mux_wrdata(38 downto 37),
      mux_wrdata(17 downto 16) => mux_wrdata(34 downto 33),
      mux_wrdata(15 downto 14) => mux_wrdata(30 downto 29),
      mux_wrdata(13 downto 12) => mux_wrdata(26 downto 25),
      mux_wrdata(11 downto 10) => mux_wrdata(22 downto 21),
      mux_wrdata(9 downto 8) => mux_wrdata(18 downto 17),
      mux_wrdata(7 downto 6) => mux_wrdata(14 downto 13),
      mux_wrdata(5 downto 4) => mux_wrdata(10 downto 9),
      mux_wrdata(3 downto 2) => mux_wrdata(6 downto 5),
      mux_wrdata(1 downto 0) => mux_wrdata(2 downto 1),
      mux_wrdata_mask(63 downto 0) => mux_wrdata_mask(63 downto 0),
      \my_empty_reg[1]\ => u_ddr_mc_phy_wrapper_n_74,
      \my_empty_reg[1]_0\ => u_ddr_mc_phy_wrapper_n_120,
      \my_empty_reg[1]_1\ => u_ddr_mc_phy_wrapper_n_121,
      \my_empty_reg[1]_2\ => u_ddr_mc_phy_wrapper_n_123,
      \my_empty_reg[1]_3\ => u_ddr_mc_phy_wrapper_n_124,
      \my_empty_reg[1]_4\ => u_ddr_mc_phy_wrapper_n_125,
      \my_empty_reg[1]_5\ => u_ddr_mc_phy_wrapper_n_126,
      \my_empty_reg[1]_6\ => u_ddr_mc_phy_wrapper_n_127,
      \my_empty_reg[1]_7\ => u_ddr_mc_phy_wrapper_n_128,
      \my_empty_reg[1]_8\ => u_ddr_mc_phy_wrapper_n_129,
      \my_empty_reg[1]_9\ => u_ddr_mc_phy_wrapper_n_661,
      \my_empty_reg[7]\(43) => u_ddr_mc_phy_wrapper_n_1249,
      \my_empty_reg[7]\(42) => u_ddr_mc_phy_wrapper_n_1250,
      \my_empty_reg[7]\(41) => u_ddr_mc_phy_wrapper_n_1251,
      \my_empty_reg[7]\(40) => u_ddr_mc_phy_wrapper_n_1252,
      \my_empty_reg[7]\(39) => u_ddr_mc_phy_wrapper_n_1253,
      \my_empty_reg[7]\(38) => u_ddr_mc_phy_wrapper_n_1254,
      \my_empty_reg[7]\(37) => u_ddr_mc_phy_wrapper_n_1255,
      \my_empty_reg[7]\(36) => u_ddr_mc_phy_wrapper_n_1256,
      \my_empty_reg[7]\(35) => u_ddr_mc_phy_wrapper_n_1257,
      \my_empty_reg[7]\(34) => u_ddr_mc_phy_wrapper_n_1258,
      \my_empty_reg[7]\(33) => u_ddr_mc_phy_wrapper_n_1259,
      \my_empty_reg[7]\(32) => u_ddr_mc_phy_wrapper_n_1260,
      \my_empty_reg[7]\(31) => u_ddr_mc_phy_wrapper_n_1261,
      \my_empty_reg[7]\(30) => u_ddr_mc_phy_wrapper_n_1262,
      \my_empty_reg[7]\(29) => u_ddr_mc_phy_wrapper_n_1263,
      \my_empty_reg[7]\(28) => u_ddr_mc_phy_wrapper_n_1264,
      \my_empty_reg[7]\(27) => u_ddr_mc_phy_wrapper_n_1265,
      \my_empty_reg[7]\(26) => u_ddr_mc_phy_wrapper_n_1266,
      \my_empty_reg[7]\(25) => u_ddr_mc_phy_wrapper_n_1267,
      \my_empty_reg[7]\(24) => u_ddr_mc_phy_wrapper_n_1268,
      \my_empty_reg[7]\(23) => u_ddr_mc_phy_wrapper_n_1269,
      \my_empty_reg[7]\(22) => u_ddr_mc_phy_wrapper_n_1270,
      \my_empty_reg[7]\(21) => u_ddr_mc_phy_wrapper_n_1271,
      \my_empty_reg[7]\(20) => u_ddr_mc_phy_wrapper_n_1272,
      \my_empty_reg[7]\(19) => u_ddr_mc_phy_wrapper_n_1273,
      \my_empty_reg[7]\(18) => u_ddr_mc_phy_wrapper_n_1274,
      \my_empty_reg[7]\(17) => u_ddr_mc_phy_wrapper_n_1275,
      \my_empty_reg[7]\(16) => u_ddr_mc_phy_wrapper_n_1276,
      \my_empty_reg[7]\(15) => u_ddr_mc_phy_wrapper_n_1277,
      \my_empty_reg[7]\(14) => u_ddr_mc_phy_wrapper_n_1278,
      \my_empty_reg[7]\(13) => u_ddr_mc_phy_wrapper_n_1279,
      \my_empty_reg[7]\(12) => u_ddr_mc_phy_wrapper_n_1280,
      \my_empty_reg[7]\(11) => u_ddr_mc_phy_wrapper_n_1281,
      \my_empty_reg[7]\(10) => u_ddr_mc_phy_wrapper_n_1282,
      \my_empty_reg[7]\(9) => u_ddr_mc_phy_wrapper_n_1283,
      \my_empty_reg[7]\(8) => u_ddr_mc_phy_wrapper_n_1284,
      \my_empty_reg[7]\(7) => u_ddr_mc_phy_wrapper_n_1285,
      \my_empty_reg[7]\(6) => u_ddr_mc_phy_wrapper_n_1286,
      \my_empty_reg[7]\(5) => u_ddr_mc_phy_wrapper_n_1287,
      \my_empty_reg[7]\(4) => u_ddr_mc_phy_wrapper_n_1288,
      \my_empty_reg[7]\(3) => u_ddr_mc_phy_wrapper_n_1289,
      \my_empty_reg[7]\(2) => u_ddr_mc_phy_wrapper_n_1290,
      \my_empty_reg[7]\(1) => u_ddr_mc_phy_wrapper_n_1291,
      \my_empty_reg[7]\(0) => u_ddr_mc_phy_wrapper_n_1292,
      \my_empty_reg[7]_0\(43) => u_ddr_mc_phy_wrapper_n_1293,
      \my_empty_reg[7]_0\(42) => u_ddr_mc_phy_wrapper_n_1294,
      \my_empty_reg[7]_0\(41) => u_ddr_mc_phy_wrapper_n_1295,
      \my_empty_reg[7]_0\(40) => u_ddr_mc_phy_wrapper_n_1296,
      \my_empty_reg[7]_0\(39) => u_ddr_mc_phy_wrapper_n_1297,
      \my_empty_reg[7]_0\(38) => u_ddr_mc_phy_wrapper_n_1298,
      \my_empty_reg[7]_0\(37) => u_ddr_mc_phy_wrapper_n_1299,
      \my_empty_reg[7]_0\(36) => u_ddr_mc_phy_wrapper_n_1300,
      \my_empty_reg[7]_0\(35) => u_ddr_mc_phy_wrapper_n_1301,
      \my_empty_reg[7]_0\(34) => u_ddr_mc_phy_wrapper_n_1302,
      \my_empty_reg[7]_0\(33) => u_ddr_mc_phy_wrapper_n_1303,
      \my_empty_reg[7]_0\(32) => u_ddr_mc_phy_wrapper_n_1304,
      \my_empty_reg[7]_0\(31) => u_ddr_mc_phy_wrapper_n_1305,
      \my_empty_reg[7]_0\(30) => u_ddr_mc_phy_wrapper_n_1306,
      \my_empty_reg[7]_0\(29) => u_ddr_mc_phy_wrapper_n_1307,
      \my_empty_reg[7]_0\(28) => u_ddr_mc_phy_wrapper_n_1308,
      \my_empty_reg[7]_0\(27) => u_ddr_mc_phy_wrapper_n_1309,
      \my_empty_reg[7]_0\(26) => u_ddr_mc_phy_wrapper_n_1310,
      \my_empty_reg[7]_0\(25) => u_ddr_mc_phy_wrapper_n_1311,
      \my_empty_reg[7]_0\(24) => u_ddr_mc_phy_wrapper_n_1312,
      \my_empty_reg[7]_0\(23) => u_ddr_mc_phy_wrapper_n_1313,
      \my_empty_reg[7]_0\(22) => u_ddr_mc_phy_wrapper_n_1314,
      \my_empty_reg[7]_0\(21) => u_ddr_mc_phy_wrapper_n_1315,
      \my_empty_reg[7]_0\(20) => u_ddr_mc_phy_wrapper_n_1316,
      \my_empty_reg[7]_0\(19) => u_ddr_mc_phy_wrapper_n_1317,
      \my_empty_reg[7]_0\(18) => u_ddr_mc_phy_wrapper_n_1318,
      \my_empty_reg[7]_0\(17) => u_ddr_mc_phy_wrapper_n_1319,
      \my_empty_reg[7]_0\(16) => u_ddr_mc_phy_wrapper_n_1320,
      \my_empty_reg[7]_0\(15) => u_ddr_mc_phy_wrapper_n_1321,
      \my_empty_reg[7]_0\(14) => u_ddr_mc_phy_wrapper_n_1322,
      \my_empty_reg[7]_0\(13) => u_ddr_mc_phy_wrapper_n_1323,
      \my_empty_reg[7]_0\(12) => u_ddr_mc_phy_wrapper_n_1324,
      \my_empty_reg[7]_0\(11) => u_ddr_mc_phy_wrapper_n_1325,
      \my_empty_reg[7]_0\(10) => u_ddr_mc_phy_wrapper_n_1326,
      \my_empty_reg[7]_0\(9) => u_ddr_mc_phy_wrapper_n_1327,
      \my_empty_reg[7]_0\(8) => u_ddr_mc_phy_wrapper_n_1328,
      \my_empty_reg[7]_0\(7) => u_ddr_mc_phy_wrapper_n_1329,
      \my_empty_reg[7]_0\(6) => u_ddr_mc_phy_wrapper_n_1330,
      \my_empty_reg[7]_0\(5) => u_ddr_mc_phy_wrapper_n_1331,
      \my_empty_reg[7]_0\(4) => u_ddr_mc_phy_wrapper_n_1332,
      \my_empty_reg[7]_0\(3) => u_ddr_mc_phy_wrapper_n_1333,
      \my_empty_reg[7]_0\(2) => u_ddr_mc_phy_wrapper_n_1334,
      \my_empty_reg[7]_0\(1) => u_ddr_mc_phy_wrapper_n_1335,
      \my_empty_reg[7]_0\(0) => u_ddr_mc_phy_wrapper_n_1336,
      \my_empty_reg[7]_1\(43) => u_ddr_mc_phy_wrapper_n_1337,
      \my_empty_reg[7]_1\(42) => u_ddr_mc_phy_wrapper_n_1338,
      \my_empty_reg[7]_1\(41) => u_ddr_mc_phy_wrapper_n_1339,
      \my_empty_reg[7]_1\(40) => u_ddr_mc_phy_wrapper_n_1340,
      \my_empty_reg[7]_1\(39) => u_ddr_mc_phy_wrapper_n_1341,
      \my_empty_reg[7]_1\(38) => u_ddr_mc_phy_wrapper_n_1342,
      \my_empty_reg[7]_1\(37) => u_ddr_mc_phy_wrapper_n_1343,
      \my_empty_reg[7]_1\(36) => u_ddr_mc_phy_wrapper_n_1344,
      \my_empty_reg[7]_1\(35) => u_ddr_mc_phy_wrapper_n_1345,
      \my_empty_reg[7]_1\(34) => u_ddr_mc_phy_wrapper_n_1346,
      \my_empty_reg[7]_1\(33) => u_ddr_mc_phy_wrapper_n_1347,
      \my_empty_reg[7]_1\(32) => u_ddr_mc_phy_wrapper_n_1348,
      \my_empty_reg[7]_1\(31) => u_ddr_mc_phy_wrapper_n_1349,
      \my_empty_reg[7]_1\(30) => u_ddr_mc_phy_wrapper_n_1350,
      \my_empty_reg[7]_1\(29) => u_ddr_mc_phy_wrapper_n_1351,
      \my_empty_reg[7]_1\(28) => u_ddr_mc_phy_wrapper_n_1352,
      \my_empty_reg[7]_1\(27) => u_ddr_mc_phy_wrapper_n_1353,
      \my_empty_reg[7]_1\(26) => u_ddr_mc_phy_wrapper_n_1354,
      \my_empty_reg[7]_1\(25) => u_ddr_mc_phy_wrapper_n_1355,
      \my_empty_reg[7]_1\(24) => u_ddr_mc_phy_wrapper_n_1356,
      \my_empty_reg[7]_1\(23) => u_ddr_mc_phy_wrapper_n_1357,
      \my_empty_reg[7]_1\(22) => u_ddr_mc_phy_wrapper_n_1358,
      \my_empty_reg[7]_1\(21) => u_ddr_mc_phy_wrapper_n_1359,
      \my_empty_reg[7]_1\(20) => u_ddr_mc_phy_wrapper_n_1360,
      \my_empty_reg[7]_1\(19) => u_ddr_mc_phy_wrapper_n_1361,
      \my_empty_reg[7]_1\(18) => u_ddr_mc_phy_wrapper_n_1362,
      \my_empty_reg[7]_1\(17) => u_ddr_mc_phy_wrapper_n_1363,
      \my_empty_reg[7]_1\(16) => u_ddr_mc_phy_wrapper_n_1364,
      \my_empty_reg[7]_1\(15) => u_ddr_mc_phy_wrapper_n_1365,
      \my_empty_reg[7]_1\(14) => u_ddr_mc_phy_wrapper_n_1366,
      \my_empty_reg[7]_1\(13) => u_ddr_mc_phy_wrapper_n_1367,
      \my_empty_reg[7]_1\(12) => u_ddr_mc_phy_wrapper_n_1368,
      \my_empty_reg[7]_1\(11) => u_ddr_mc_phy_wrapper_n_1369,
      \my_empty_reg[7]_1\(10) => u_ddr_mc_phy_wrapper_n_1370,
      \my_empty_reg[7]_1\(9) => u_ddr_mc_phy_wrapper_n_1371,
      \my_empty_reg[7]_1\(8) => u_ddr_mc_phy_wrapper_n_1372,
      \my_empty_reg[7]_1\(7) => u_ddr_mc_phy_wrapper_n_1373,
      \my_empty_reg[7]_1\(6) => u_ddr_mc_phy_wrapper_n_1374,
      \my_empty_reg[7]_1\(5) => u_ddr_mc_phy_wrapper_n_1375,
      \my_empty_reg[7]_1\(4) => u_ddr_mc_phy_wrapper_n_1376,
      \my_empty_reg[7]_1\(3) => u_ddr_mc_phy_wrapper_n_1377,
      \my_empty_reg[7]_1\(2) => u_ddr_mc_phy_wrapper_n_1378,
      \my_empty_reg[7]_1\(1) => u_ddr_mc_phy_wrapper_n_1379,
      \my_empty_reg[7]_1\(0) => u_ddr_mc_phy_wrapper_n_1380,
      \my_empty_reg[7]_2\(43) => u_ddr_mc_phy_wrapper_n_1381,
      \my_empty_reg[7]_2\(42) => u_ddr_mc_phy_wrapper_n_1382,
      \my_empty_reg[7]_2\(41) => u_ddr_mc_phy_wrapper_n_1383,
      \my_empty_reg[7]_2\(40) => u_ddr_mc_phy_wrapper_n_1384,
      \my_empty_reg[7]_2\(39) => u_ddr_mc_phy_wrapper_n_1385,
      \my_empty_reg[7]_2\(38) => u_ddr_mc_phy_wrapper_n_1386,
      \my_empty_reg[7]_2\(37) => u_ddr_mc_phy_wrapper_n_1387,
      \my_empty_reg[7]_2\(36) => u_ddr_mc_phy_wrapper_n_1388,
      \my_empty_reg[7]_2\(35) => u_ddr_mc_phy_wrapper_n_1389,
      \my_empty_reg[7]_2\(34) => u_ddr_mc_phy_wrapper_n_1390,
      \my_empty_reg[7]_2\(33) => u_ddr_mc_phy_wrapper_n_1391,
      \my_empty_reg[7]_2\(32) => u_ddr_mc_phy_wrapper_n_1392,
      \my_empty_reg[7]_2\(31) => u_ddr_mc_phy_wrapper_n_1393,
      \my_empty_reg[7]_2\(30) => u_ddr_mc_phy_wrapper_n_1394,
      \my_empty_reg[7]_2\(29) => u_ddr_mc_phy_wrapper_n_1395,
      \my_empty_reg[7]_2\(28) => u_ddr_mc_phy_wrapper_n_1396,
      \my_empty_reg[7]_2\(27) => u_ddr_mc_phy_wrapper_n_1397,
      \my_empty_reg[7]_2\(26) => u_ddr_mc_phy_wrapper_n_1398,
      \my_empty_reg[7]_2\(25) => u_ddr_mc_phy_wrapper_n_1399,
      \my_empty_reg[7]_2\(24) => u_ddr_mc_phy_wrapper_n_1400,
      \my_empty_reg[7]_2\(23) => u_ddr_mc_phy_wrapper_n_1401,
      \my_empty_reg[7]_2\(22) => u_ddr_mc_phy_wrapper_n_1402,
      \my_empty_reg[7]_2\(21) => u_ddr_mc_phy_wrapper_n_1403,
      \my_empty_reg[7]_2\(20) => u_ddr_mc_phy_wrapper_n_1404,
      \my_empty_reg[7]_2\(19) => u_ddr_mc_phy_wrapper_n_1405,
      \my_empty_reg[7]_2\(18) => u_ddr_mc_phy_wrapper_n_1406,
      \my_empty_reg[7]_2\(17) => u_ddr_mc_phy_wrapper_n_1407,
      \my_empty_reg[7]_2\(16) => u_ddr_mc_phy_wrapper_n_1408,
      \my_empty_reg[7]_2\(15) => u_ddr_mc_phy_wrapper_n_1409,
      \my_empty_reg[7]_2\(14) => u_ddr_mc_phy_wrapper_n_1410,
      \my_empty_reg[7]_2\(13) => u_ddr_mc_phy_wrapper_n_1411,
      \my_empty_reg[7]_2\(12) => u_ddr_mc_phy_wrapper_n_1412,
      \my_empty_reg[7]_2\(11) => u_ddr_mc_phy_wrapper_n_1413,
      \my_empty_reg[7]_2\(10) => u_ddr_mc_phy_wrapper_n_1414,
      \my_empty_reg[7]_2\(9) => u_ddr_mc_phy_wrapper_n_1415,
      \my_empty_reg[7]_2\(8) => u_ddr_mc_phy_wrapper_n_1416,
      \my_empty_reg[7]_2\(7) => u_ddr_mc_phy_wrapper_n_1417,
      \my_empty_reg[7]_2\(6) => u_ddr_mc_phy_wrapper_n_1418,
      \my_empty_reg[7]_2\(5) => u_ddr_mc_phy_wrapper_n_1419,
      \my_empty_reg[7]_2\(4) => u_ddr_mc_phy_wrapper_n_1420,
      \my_empty_reg[7]_2\(3) => u_ddr_mc_phy_wrapper_n_1421,
      \my_empty_reg[7]_2\(2) => u_ddr_mc_phy_wrapper_n_1422,
      \my_empty_reg[7]_2\(1) => u_ddr_mc_phy_wrapper_n_1423,
      \my_empty_reg[7]_2\(0) => u_ddr_mc_phy_wrapper_n_1424,
      \my_empty_reg[7]_3\(43) => u_ddr_mc_phy_wrapper_n_1425,
      \my_empty_reg[7]_3\(42) => u_ddr_mc_phy_wrapper_n_1426,
      \my_empty_reg[7]_3\(41) => u_ddr_mc_phy_wrapper_n_1427,
      \my_empty_reg[7]_3\(40) => u_ddr_mc_phy_wrapper_n_1428,
      \my_empty_reg[7]_3\(39) => u_ddr_mc_phy_wrapper_n_1429,
      \my_empty_reg[7]_3\(38) => u_ddr_mc_phy_wrapper_n_1430,
      \my_empty_reg[7]_3\(37) => u_ddr_mc_phy_wrapper_n_1431,
      \my_empty_reg[7]_3\(36) => u_ddr_mc_phy_wrapper_n_1432,
      \my_empty_reg[7]_3\(35) => u_ddr_mc_phy_wrapper_n_1433,
      \my_empty_reg[7]_3\(34) => u_ddr_mc_phy_wrapper_n_1434,
      \my_empty_reg[7]_3\(33) => u_ddr_mc_phy_wrapper_n_1435,
      \my_empty_reg[7]_3\(32) => u_ddr_mc_phy_wrapper_n_1436,
      \my_empty_reg[7]_3\(31) => u_ddr_mc_phy_wrapper_n_1437,
      \my_empty_reg[7]_3\(30) => u_ddr_mc_phy_wrapper_n_1438,
      \my_empty_reg[7]_3\(29) => u_ddr_mc_phy_wrapper_n_1439,
      \my_empty_reg[7]_3\(28) => u_ddr_mc_phy_wrapper_n_1440,
      \my_empty_reg[7]_3\(27) => u_ddr_mc_phy_wrapper_n_1441,
      \my_empty_reg[7]_3\(26) => u_ddr_mc_phy_wrapper_n_1442,
      \my_empty_reg[7]_3\(25) => u_ddr_mc_phy_wrapper_n_1443,
      \my_empty_reg[7]_3\(24) => u_ddr_mc_phy_wrapper_n_1444,
      \my_empty_reg[7]_3\(23) => u_ddr_mc_phy_wrapper_n_1445,
      \my_empty_reg[7]_3\(22) => u_ddr_mc_phy_wrapper_n_1446,
      \my_empty_reg[7]_3\(21) => u_ddr_mc_phy_wrapper_n_1447,
      \my_empty_reg[7]_3\(20) => u_ddr_mc_phy_wrapper_n_1448,
      \my_empty_reg[7]_3\(19) => u_ddr_mc_phy_wrapper_n_1449,
      \my_empty_reg[7]_3\(18) => u_ddr_mc_phy_wrapper_n_1450,
      \my_empty_reg[7]_3\(17) => u_ddr_mc_phy_wrapper_n_1451,
      \my_empty_reg[7]_3\(16) => u_ddr_mc_phy_wrapper_n_1452,
      \my_empty_reg[7]_3\(15) => u_ddr_mc_phy_wrapper_n_1453,
      \my_empty_reg[7]_3\(14) => u_ddr_mc_phy_wrapper_n_1454,
      \my_empty_reg[7]_3\(13) => u_ddr_mc_phy_wrapper_n_1455,
      \my_empty_reg[7]_3\(12) => u_ddr_mc_phy_wrapper_n_1456,
      \my_empty_reg[7]_3\(11) => u_ddr_mc_phy_wrapper_n_1457,
      \my_empty_reg[7]_3\(10) => u_ddr_mc_phy_wrapper_n_1458,
      \my_empty_reg[7]_3\(9) => u_ddr_mc_phy_wrapper_n_1459,
      \my_empty_reg[7]_3\(8) => u_ddr_mc_phy_wrapper_n_1460,
      \my_empty_reg[7]_3\(7) => u_ddr_mc_phy_wrapper_n_1461,
      \my_empty_reg[7]_3\(6) => u_ddr_mc_phy_wrapper_n_1462,
      \my_empty_reg[7]_3\(5) => u_ddr_mc_phy_wrapper_n_1463,
      \my_empty_reg[7]_3\(4) => u_ddr_mc_phy_wrapper_n_1464,
      \my_empty_reg[7]_3\(3) => u_ddr_mc_phy_wrapper_n_1465,
      \my_empty_reg[7]_3\(2) => u_ddr_mc_phy_wrapper_n_1466,
      \my_empty_reg[7]_3\(1) => u_ddr_mc_phy_wrapper_n_1467,
      \my_empty_reg[7]_3\(0) => u_ddr_mc_phy_wrapper_n_1468,
      \my_empty_reg[7]_4\(43) => u_ddr_mc_phy_wrapper_n_1469,
      \my_empty_reg[7]_4\(42) => u_ddr_mc_phy_wrapper_n_1470,
      \my_empty_reg[7]_4\(41) => u_ddr_mc_phy_wrapper_n_1471,
      \my_empty_reg[7]_4\(40) => u_ddr_mc_phy_wrapper_n_1472,
      \my_empty_reg[7]_4\(39) => u_ddr_mc_phy_wrapper_n_1473,
      \my_empty_reg[7]_4\(38) => u_ddr_mc_phy_wrapper_n_1474,
      \my_empty_reg[7]_4\(37) => u_ddr_mc_phy_wrapper_n_1475,
      \my_empty_reg[7]_4\(36) => u_ddr_mc_phy_wrapper_n_1476,
      \my_empty_reg[7]_4\(35) => u_ddr_mc_phy_wrapper_n_1477,
      \my_empty_reg[7]_4\(34) => u_ddr_mc_phy_wrapper_n_1478,
      \my_empty_reg[7]_4\(33) => u_ddr_mc_phy_wrapper_n_1479,
      \my_empty_reg[7]_4\(32) => u_ddr_mc_phy_wrapper_n_1480,
      \my_empty_reg[7]_4\(31) => u_ddr_mc_phy_wrapper_n_1481,
      \my_empty_reg[7]_4\(30) => u_ddr_mc_phy_wrapper_n_1482,
      \my_empty_reg[7]_4\(29) => u_ddr_mc_phy_wrapper_n_1483,
      \my_empty_reg[7]_4\(28) => u_ddr_mc_phy_wrapper_n_1484,
      \my_empty_reg[7]_4\(27) => u_ddr_mc_phy_wrapper_n_1485,
      \my_empty_reg[7]_4\(26) => u_ddr_mc_phy_wrapper_n_1486,
      \my_empty_reg[7]_4\(25) => u_ddr_mc_phy_wrapper_n_1487,
      \my_empty_reg[7]_4\(24) => u_ddr_mc_phy_wrapper_n_1488,
      \my_empty_reg[7]_4\(23) => u_ddr_mc_phy_wrapper_n_1489,
      \my_empty_reg[7]_4\(22) => u_ddr_mc_phy_wrapper_n_1490,
      \my_empty_reg[7]_4\(21) => u_ddr_mc_phy_wrapper_n_1491,
      \my_empty_reg[7]_4\(20) => u_ddr_mc_phy_wrapper_n_1492,
      \my_empty_reg[7]_4\(19) => u_ddr_mc_phy_wrapper_n_1493,
      \my_empty_reg[7]_4\(18) => u_ddr_mc_phy_wrapper_n_1494,
      \my_empty_reg[7]_4\(17) => u_ddr_mc_phy_wrapper_n_1495,
      \my_empty_reg[7]_4\(16) => u_ddr_mc_phy_wrapper_n_1496,
      \my_empty_reg[7]_4\(15) => u_ddr_mc_phy_wrapper_n_1497,
      \my_empty_reg[7]_4\(14) => u_ddr_mc_phy_wrapper_n_1498,
      \my_empty_reg[7]_4\(13) => u_ddr_mc_phy_wrapper_n_1499,
      \my_empty_reg[7]_4\(12) => u_ddr_mc_phy_wrapper_n_1500,
      \my_empty_reg[7]_4\(11) => u_ddr_mc_phy_wrapper_n_1501,
      \my_empty_reg[7]_4\(10) => u_ddr_mc_phy_wrapper_n_1502,
      \my_empty_reg[7]_4\(9) => u_ddr_mc_phy_wrapper_n_1503,
      \my_empty_reg[7]_4\(8) => u_ddr_mc_phy_wrapper_n_1504,
      \my_empty_reg[7]_4\(7) => u_ddr_mc_phy_wrapper_n_1505,
      \my_empty_reg[7]_4\(6) => u_ddr_mc_phy_wrapper_n_1506,
      \my_empty_reg[7]_4\(5) => u_ddr_mc_phy_wrapper_n_1507,
      \my_empty_reg[7]_4\(4) => u_ddr_mc_phy_wrapper_n_1508,
      \my_empty_reg[7]_4\(3) => u_ddr_mc_phy_wrapper_n_1509,
      \my_empty_reg[7]_4\(2) => u_ddr_mc_phy_wrapper_n_1510,
      \my_empty_reg[7]_4\(1) => u_ddr_mc_phy_wrapper_n_1511,
      \my_empty_reg[7]_4\(0) => u_ddr_mc_phy_wrapper_n_1512,
      \my_empty_reg[7]_5\(43) => u_ddr_mc_phy_wrapper_n_1513,
      \my_empty_reg[7]_5\(42) => u_ddr_mc_phy_wrapper_n_1514,
      \my_empty_reg[7]_5\(41) => u_ddr_mc_phy_wrapper_n_1515,
      \my_empty_reg[7]_5\(40) => u_ddr_mc_phy_wrapper_n_1516,
      \my_empty_reg[7]_5\(39) => u_ddr_mc_phy_wrapper_n_1517,
      \my_empty_reg[7]_5\(38) => u_ddr_mc_phy_wrapper_n_1518,
      \my_empty_reg[7]_5\(37) => u_ddr_mc_phy_wrapper_n_1519,
      \my_empty_reg[7]_5\(36) => u_ddr_mc_phy_wrapper_n_1520,
      \my_empty_reg[7]_5\(35) => u_ddr_mc_phy_wrapper_n_1521,
      \my_empty_reg[7]_5\(34) => u_ddr_mc_phy_wrapper_n_1522,
      \my_empty_reg[7]_5\(33) => u_ddr_mc_phy_wrapper_n_1523,
      \my_empty_reg[7]_5\(32) => u_ddr_mc_phy_wrapper_n_1524,
      \my_empty_reg[7]_5\(31) => u_ddr_mc_phy_wrapper_n_1525,
      \my_empty_reg[7]_5\(30) => u_ddr_mc_phy_wrapper_n_1526,
      \my_empty_reg[7]_5\(29) => u_ddr_mc_phy_wrapper_n_1527,
      \my_empty_reg[7]_5\(28) => u_ddr_mc_phy_wrapper_n_1528,
      \my_empty_reg[7]_5\(27) => u_ddr_mc_phy_wrapper_n_1529,
      \my_empty_reg[7]_5\(26) => u_ddr_mc_phy_wrapper_n_1530,
      \my_empty_reg[7]_5\(25) => u_ddr_mc_phy_wrapper_n_1531,
      \my_empty_reg[7]_5\(24) => u_ddr_mc_phy_wrapper_n_1532,
      \my_empty_reg[7]_5\(23) => u_ddr_mc_phy_wrapper_n_1533,
      \my_empty_reg[7]_5\(22) => u_ddr_mc_phy_wrapper_n_1534,
      \my_empty_reg[7]_5\(21) => u_ddr_mc_phy_wrapper_n_1535,
      \my_empty_reg[7]_5\(20) => u_ddr_mc_phy_wrapper_n_1536,
      \my_empty_reg[7]_5\(19) => u_ddr_mc_phy_wrapper_n_1537,
      \my_empty_reg[7]_5\(18) => u_ddr_mc_phy_wrapper_n_1538,
      \my_empty_reg[7]_5\(17) => u_ddr_mc_phy_wrapper_n_1539,
      \my_empty_reg[7]_5\(16) => u_ddr_mc_phy_wrapper_n_1540,
      \my_empty_reg[7]_5\(15) => u_ddr_mc_phy_wrapper_n_1541,
      \my_empty_reg[7]_5\(14) => u_ddr_mc_phy_wrapper_n_1542,
      \my_empty_reg[7]_5\(13) => u_ddr_mc_phy_wrapper_n_1543,
      \my_empty_reg[7]_5\(12) => u_ddr_mc_phy_wrapper_n_1544,
      \my_empty_reg[7]_5\(11) => u_ddr_mc_phy_wrapper_n_1545,
      \my_empty_reg[7]_5\(10) => u_ddr_mc_phy_wrapper_n_1546,
      \my_empty_reg[7]_5\(9) => u_ddr_mc_phy_wrapper_n_1547,
      \my_empty_reg[7]_5\(8) => u_ddr_mc_phy_wrapper_n_1548,
      \my_empty_reg[7]_5\(7) => u_ddr_mc_phy_wrapper_n_1549,
      \my_empty_reg[7]_5\(6) => u_ddr_mc_phy_wrapper_n_1550,
      \my_empty_reg[7]_5\(5) => u_ddr_mc_phy_wrapper_n_1551,
      \my_empty_reg[7]_5\(4) => u_ddr_mc_phy_wrapper_n_1552,
      \my_empty_reg[7]_5\(3) => u_ddr_mc_phy_wrapper_n_1553,
      \my_empty_reg[7]_5\(2) => u_ddr_mc_phy_wrapper_n_1554,
      \my_empty_reg[7]_5\(1) => u_ddr_mc_phy_wrapper_n_1555,
      \my_empty_reg[7]_5\(0) => u_ddr_mc_phy_wrapper_n_1556,
      \my_empty_reg[7]_6\(43) => u_ddr_mc_phy_wrapper_n_1557,
      \my_empty_reg[7]_6\(42) => u_ddr_mc_phy_wrapper_n_1558,
      \my_empty_reg[7]_6\(41) => u_ddr_mc_phy_wrapper_n_1559,
      \my_empty_reg[7]_6\(40) => u_ddr_mc_phy_wrapper_n_1560,
      \my_empty_reg[7]_6\(39) => u_ddr_mc_phy_wrapper_n_1561,
      \my_empty_reg[7]_6\(38) => u_ddr_mc_phy_wrapper_n_1562,
      \my_empty_reg[7]_6\(37) => u_ddr_mc_phy_wrapper_n_1563,
      \my_empty_reg[7]_6\(36) => u_ddr_mc_phy_wrapper_n_1564,
      \my_empty_reg[7]_6\(35) => u_ddr_mc_phy_wrapper_n_1565,
      \my_empty_reg[7]_6\(34) => u_ddr_mc_phy_wrapper_n_1566,
      \my_empty_reg[7]_6\(33) => u_ddr_mc_phy_wrapper_n_1567,
      \my_empty_reg[7]_6\(32) => u_ddr_mc_phy_wrapper_n_1568,
      \my_empty_reg[7]_6\(31) => u_ddr_mc_phy_wrapper_n_1569,
      \my_empty_reg[7]_6\(30) => u_ddr_mc_phy_wrapper_n_1570,
      \my_empty_reg[7]_6\(29) => u_ddr_mc_phy_wrapper_n_1571,
      \my_empty_reg[7]_6\(28) => u_ddr_mc_phy_wrapper_n_1572,
      \my_empty_reg[7]_6\(27) => u_ddr_mc_phy_wrapper_n_1573,
      \my_empty_reg[7]_6\(26) => u_ddr_mc_phy_wrapper_n_1574,
      \my_empty_reg[7]_6\(25) => u_ddr_mc_phy_wrapper_n_1575,
      \my_empty_reg[7]_6\(24) => u_ddr_mc_phy_wrapper_n_1576,
      \my_empty_reg[7]_6\(23) => u_ddr_mc_phy_wrapper_n_1577,
      \my_empty_reg[7]_6\(22) => u_ddr_mc_phy_wrapper_n_1578,
      \my_empty_reg[7]_6\(21) => u_ddr_mc_phy_wrapper_n_1579,
      \my_empty_reg[7]_6\(20) => u_ddr_mc_phy_wrapper_n_1580,
      \my_empty_reg[7]_6\(19) => u_ddr_mc_phy_wrapper_n_1581,
      \my_empty_reg[7]_6\(18) => u_ddr_mc_phy_wrapper_n_1582,
      \my_empty_reg[7]_6\(17) => u_ddr_mc_phy_wrapper_n_1583,
      \my_empty_reg[7]_6\(16) => u_ddr_mc_phy_wrapper_n_1584,
      \my_empty_reg[7]_6\(15) => u_ddr_mc_phy_wrapper_n_1585,
      \my_empty_reg[7]_6\(14) => u_ddr_mc_phy_wrapper_n_1586,
      \my_empty_reg[7]_6\(13) => u_ddr_mc_phy_wrapper_n_1587,
      \my_empty_reg[7]_6\(12) => u_ddr_mc_phy_wrapper_n_1588,
      \my_empty_reg[7]_6\(11) => u_ddr_mc_phy_wrapper_n_1589,
      \my_empty_reg[7]_6\(10) => u_ddr_mc_phy_wrapper_n_1590,
      \my_empty_reg[7]_6\(9) => u_ddr_mc_phy_wrapper_n_1591,
      \my_empty_reg[7]_6\(8) => u_ddr_mc_phy_wrapper_n_1592,
      \my_empty_reg[7]_6\(7) => u_ddr_mc_phy_wrapper_n_1593,
      \my_empty_reg[7]_6\(6) => u_ddr_mc_phy_wrapper_n_1594,
      \my_empty_reg[7]_6\(5) => u_ddr_mc_phy_wrapper_n_1595,
      \my_empty_reg[7]_6\(4) => u_ddr_mc_phy_wrapper_n_1596,
      \my_empty_reg[7]_6\(3) => u_ddr_mc_phy_wrapper_n_1597,
      \my_empty_reg[7]_6\(2) => u_ddr_mc_phy_wrapper_n_1598,
      \my_empty_reg[7]_6\(1) => u_ddr_mc_phy_wrapper_n_1599,
      \my_empty_reg[7]_6\(0) => u_ddr_mc_phy_wrapper_n_1600,
      \not_strict_mode.app_rd_data_reg[0]\ => \^not_strict_mode.app_rd_data_reg[0]\,
      \not_strict_mode.app_rd_data_reg[100]\ => \not_strict_mode.app_rd_data_reg[100]\,
      \not_strict_mode.app_rd_data_reg[101]\ => \not_strict_mode.app_rd_data_reg[101]\,
      \not_strict_mode.app_rd_data_reg[102]\ => \not_strict_mode.app_rd_data_reg[102]\,
      \not_strict_mode.app_rd_data_reg[103]\ => \not_strict_mode.app_rd_data_reg[103]\,
      \not_strict_mode.app_rd_data_reg[104]\ => \not_strict_mode.app_rd_data_reg[104]\,
      \not_strict_mode.app_rd_data_reg[105]\ => \not_strict_mode.app_rd_data_reg[105]\,
      \not_strict_mode.app_rd_data_reg[106]\ => \not_strict_mode.app_rd_data_reg[106]\,
      \not_strict_mode.app_rd_data_reg[107]\ => \not_strict_mode.app_rd_data_reg[107]\,
      \not_strict_mode.app_rd_data_reg[108]\ => \not_strict_mode.app_rd_data_reg[108]\,
      \not_strict_mode.app_rd_data_reg[109]\ => \not_strict_mode.app_rd_data_reg[109]\,
      \not_strict_mode.app_rd_data_reg[10]\ => \^not_strict_mode.app_rd_data_reg[10]\,
      \not_strict_mode.app_rd_data_reg[110]\ => \not_strict_mode.app_rd_data_reg[110]\,
      \not_strict_mode.app_rd_data_reg[111]\ => \not_strict_mode.app_rd_data_reg[111]\,
      \not_strict_mode.app_rd_data_reg[112]\ => \not_strict_mode.app_rd_data_reg[112]\,
      \not_strict_mode.app_rd_data_reg[113]\ => \not_strict_mode.app_rd_data_reg[113]\,
      \not_strict_mode.app_rd_data_reg[114]\ => \not_strict_mode.app_rd_data_reg[114]\,
      \not_strict_mode.app_rd_data_reg[115]\ => \not_strict_mode.app_rd_data_reg[115]\,
      \not_strict_mode.app_rd_data_reg[116]\ => \not_strict_mode.app_rd_data_reg[116]\,
      \not_strict_mode.app_rd_data_reg[117]\ => \not_strict_mode.app_rd_data_reg[117]\,
      \not_strict_mode.app_rd_data_reg[118]\ => \not_strict_mode.app_rd_data_reg[118]\,
      \not_strict_mode.app_rd_data_reg[119]\ => \not_strict_mode.app_rd_data_reg[119]\,
      \not_strict_mode.app_rd_data_reg[11]\ => \^not_strict_mode.app_rd_data_reg[11]\,
      \not_strict_mode.app_rd_data_reg[120]\ => \not_strict_mode.app_rd_data_reg[120]\,
      \not_strict_mode.app_rd_data_reg[121]\ => \not_strict_mode.app_rd_data_reg[121]\,
      \not_strict_mode.app_rd_data_reg[122]\ => \not_strict_mode.app_rd_data_reg[122]\,
      \not_strict_mode.app_rd_data_reg[123]\ => \not_strict_mode.app_rd_data_reg[123]\,
      \not_strict_mode.app_rd_data_reg[124]\ => \not_strict_mode.app_rd_data_reg[124]\,
      \not_strict_mode.app_rd_data_reg[125]\ => \not_strict_mode.app_rd_data_reg[125]\,
      \not_strict_mode.app_rd_data_reg[126]\ => \not_strict_mode.app_rd_data_reg[126]\,
      \not_strict_mode.app_rd_data_reg[127]\ => \not_strict_mode.app_rd_data_reg[127]\,
      \not_strict_mode.app_rd_data_reg[128]\ => \not_strict_mode.app_rd_data_reg[128]\,
      \not_strict_mode.app_rd_data_reg[129]\ => \not_strict_mode.app_rd_data_reg[129]\,
      \not_strict_mode.app_rd_data_reg[12]\ => \^not_strict_mode.app_rd_data_reg[12]\,
      \not_strict_mode.app_rd_data_reg[130]\ => \not_strict_mode.app_rd_data_reg[130]\,
      \not_strict_mode.app_rd_data_reg[131]\ => \not_strict_mode.app_rd_data_reg[131]\,
      \not_strict_mode.app_rd_data_reg[132]\ => \not_strict_mode.app_rd_data_reg[132]\,
      \not_strict_mode.app_rd_data_reg[133]\ => \not_strict_mode.app_rd_data_reg[133]\,
      \not_strict_mode.app_rd_data_reg[134]\ => \not_strict_mode.app_rd_data_reg[134]\,
      \not_strict_mode.app_rd_data_reg[135]\ => \not_strict_mode.app_rd_data_reg[135]\,
      \not_strict_mode.app_rd_data_reg[136]\ => \not_strict_mode.app_rd_data_reg[136]\,
      \not_strict_mode.app_rd_data_reg[137]\ => \not_strict_mode.app_rd_data_reg[137]\,
      \not_strict_mode.app_rd_data_reg[138]\ => \not_strict_mode.app_rd_data_reg[138]\,
      \not_strict_mode.app_rd_data_reg[139]\ => \not_strict_mode.app_rd_data_reg[139]\,
      \not_strict_mode.app_rd_data_reg[13]\ => \^not_strict_mode.app_rd_data_reg[13]\,
      \not_strict_mode.app_rd_data_reg[140]\ => \not_strict_mode.app_rd_data_reg[140]\,
      \not_strict_mode.app_rd_data_reg[141]\ => \not_strict_mode.app_rd_data_reg[141]\,
      \not_strict_mode.app_rd_data_reg[142]\ => \not_strict_mode.app_rd_data_reg[142]\,
      \not_strict_mode.app_rd_data_reg[143]\ => \not_strict_mode.app_rd_data_reg[143]\,
      \not_strict_mode.app_rd_data_reg[144]\ => \not_strict_mode.app_rd_data_reg[144]\,
      \not_strict_mode.app_rd_data_reg[145]\ => \not_strict_mode.app_rd_data_reg[145]\,
      \not_strict_mode.app_rd_data_reg[146]\ => \not_strict_mode.app_rd_data_reg[146]\,
      \not_strict_mode.app_rd_data_reg[147]\ => \not_strict_mode.app_rd_data_reg[147]\,
      \not_strict_mode.app_rd_data_reg[148]\ => \not_strict_mode.app_rd_data_reg[148]\,
      \not_strict_mode.app_rd_data_reg[149]\ => \not_strict_mode.app_rd_data_reg[149]\,
      \not_strict_mode.app_rd_data_reg[14]\ => \^not_strict_mode.app_rd_data_reg[14]\,
      \not_strict_mode.app_rd_data_reg[150]\ => \not_strict_mode.app_rd_data_reg[150]\,
      \not_strict_mode.app_rd_data_reg[151]\ => \not_strict_mode.app_rd_data_reg[151]\,
      \not_strict_mode.app_rd_data_reg[152]\ => \not_strict_mode.app_rd_data_reg[152]\,
      \not_strict_mode.app_rd_data_reg[153]\ => \not_strict_mode.app_rd_data_reg[153]\,
      \not_strict_mode.app_rd_data_reg[154]\ => \not_strict_mode.app_rd_data_reg[154]\,
      \not_strict_mode.app_rd_data_reg[155]\ => \not_strict_mode.app_rd_data_reg[155]\,
      \not_strict_mode.app_rd_data_reg[156]\ => \not_strict_mode.app_rd_data_reg[156]\,
      \not_strict_mode.app_rd_data_reg[157]\ => \not_strict_mode.app_rd_data_reg[157]\,
      \not_strict_mode.app_rd_data_reg[158]\ => \not_strict_mode.app_rd_data_reg[158]\,
      \not_strict_mode.app_rd_data_reg[159]\ => \not_strict_mode.app_rd_data_reg[159]\,
      \not_strict_mode.app_rd_data_reg[15]\ => \^not_strict_mode.app_rd_data_reg[15]\,
      \not_strict_mode.app_rd_data_reg[160]\ => \not_strict_mode.app_rd_data_reg[160]\,
      \not_strict_mode.app_rd_data_reg[161]\ => \not_strict_mode.app_rd_data_reg[161]\,
      \not_strict_mode.app_rd_data_reg[162]\ => \not_strict_mode.app_rd_data_reg[162]\,
      \not_strict_mode.app_rd_data_reg[163]\ => \not_strict_mode.app_rd_data_reg[163]\,
      \not_strict_mode.app_rd_data_reg[164]\ => \not_strict_mode.app_rd_data_reg[164]\,
      \not_strict_mode.app_rd_data_reg[165]\ => \not_strict_mode.app_rd_data_reg[165]\,
      \not_strict_mode.app_rd_data_reg[166]\ => \not_strict_mode.app_rd_data_reg[166]\,
      \not_strict_mode.app_rd_data_reg[167]\ => \not_strict_mode.app_rd_data_reg[167]\,
      \not_strict_mode.app_rd_data_reg[168]\ => \not_strict_mode.app_rd_data_reg[168]\,
      \not_strict_mode.app_rd_data_reg[169]\ => \not_strict_mode.app_rd_data_reg[169]\,
      \not_strict_mode.app_rd_data_reg[16]\ => \^not_strict_mode.app_rd_data_reg[16]\,
      \not_strict_mode.app_rd_data_reg[170]\ => \not_strict_mode.app_rd_data_reg[170]\,
      \not_strict_mode.app_rd_data_reg[171]\ => \not_strict_mode.app_rd_data_reg[171]\,
      \not_strict_mode.app_rd_data_reg[172]\ => \not_strict_mode.app_rd_data_reg[172]\,
      \not_strict_mode.app_rd_data_reg[173]\ => \not_strict_mode.app_rd_data_reg[173]\,
      \not_strict_mode.app_rd_data_reg[174]\ => \not_strict_mode.app_rd_data_reg[174]\,
      \not_strict_mode.app_rd_data_reg[175]\ => \not_strict_mode.app_rd_data_reg[175]\,
      \not_strict_mode.app_rd_data_reg[176]\ => \not_strict_mode.app_rd_data_reg[176]\,
      \not_strict_mode.app_rd_data_reg[177]\ => \not_strict_mode.app_rd_data_reg[177]\,
      \not_strict_mode.app_rd_data_reg[178]\ => \not_strict_mode.app_rd_data_reg[178]\,
      \not_strict_mode.app_rd_data_reg[179]\ => \not_strict_mode.app_rd_data_reg[179]\,
      \not_strict_mode.app_rd_data_reg[17]\ => \^not_strict_mode.app_rd_data_reg[17]\,
      \not_strict_mode.app_rd_data_reg[180]\ => \not_strict_mode.app_rd_data_reg[180]\,
      \not_strict_mode.app_rd_data_reg[181]\ => \not_strict_mode.app_rd_data_reg[181]\,
      \not_strict_mode.app_rd_data_reg[182]\ => \not_strict_mode.app_rd_data_reg[182]\,
      \not_strict_mode.app_rd_data_reg[183]\ => \not_strict_mode.app_rd_data_reg[183]\,
      \not_strict_mode.app_rd_data_reg[184]\ => \not_strict_mode.app_rd_data_reg[184]\,
      \not_strict_mode.app_rd_data_reg[185]\ => \not_strict_mode.app_rd_data_reg[185]\,
      \not_strict_mode.app_rd_data_reg[186]\ => \not_strict_mode.app_rd_data_reg[186]\,
      \not_strict_mode.app_rd_data_reg[187]\ => \not_strict_mode.app_rd_data_reg[187]\,
      \not_strict_mode.app_rd_data_reg[188]\ => \not_strict_mode.app_rd_data_reg[188]\,
      \not_strict_mode.app_rd_data_reg[189]\ => \not_strict_mode.app_rd_data_reg[189]\,
      \not_strict_mode.app_rd_data_reg[18]\ => \^not_strict_mode.app_rd_data_reg[18]\,
      \not_strict_mode.app_rd_data_reg[190]\ => \not_strict_mode.app_rd_data_reg[190]\,
      \not_strict_mode.app_rd_data_reg[191]\ => \not_strict_mode.app_rd_data_reg[191]\,
      \not_strict_mode.app_rd_data_reg[192]\ => \not_strict_mode.app_rd_data_reg[192]\,
      \not_strict_mode.app_rd_data_reg[193]\ => \not_strict_mode.app_rd_data_reg[193]\,
      \not_strict_mode.app_rd_data_reg[194]\ => \not_strict_mode.app_rd_data_reg[194]\,
      \not_strict_mode.app_rd_data_reg[195]\ => \not_strict_mode.app_rd_data_reg[195]\,
      \not_strict_mode.app_rd_data_reg[196]\ => \not_strict_mode.app_rd_data_reg[196]\,
      \not_strict_mode.app_rd_data_reg[197]\ => \not_strict_mode.app_rd_data_reg[197]\,
      \not_strict_mode.app_rd_data_reg[198]\ => \not_strict_mode.app_rd_data_reg[198]\,
      \not_strict_mode.app_rd_data_reg[199]\ => \not_strict_mode.app_rd_data_reg[199]\,
      \not_strict_mode.app_rd_data_reg[19]\ => \^not_strict_mode.app_rd_data_reg[19]\,
      \not_strict_mode.app_rd_data_reg[1]\ => \^not_strict_mode.app_rd_data_reg[1]\,
      \not_strict_mode.app_rd_data_reg[200]\ => \not_strict_mode.app_rd_data_reg[200]\,
      \not_strict_mode.app_rd_data_reg[201]\ => \not_strict_mode.app_rd_data_reg[201]\,
      \not_strict_mode.app_rd_data_reg[202]\ => \not_strict_mode.app_rd_data_reg[202]\,
      \not_strict_mode.app_rd_data_reg[203]\ => \not_strict_mode.app_rd_data_reg[203]\,
      \not_strict_mode.app_rd_data_reg[204]\ => \not_strict_mode.app_rd_data_reg[204]\,
      \not_strict_mode.app_rd_data_reg[205]\ => \not_strict_mode.app_rd_data_reg[205]\,
      \not_strict_mode.app_rd_data_reg[206]\ => \not_strict_mode.app_rd_data_reg[206]\,
      \not_strict_mode.app_rd_data_reg[207]\ => \not_strict_mode.app_rd_data_reg[207]\,
      \not_strict_mode.app_rd_data_reg[208]\ => \not_strict_mode.app_rd_data_reg[208]\,
      \not_strict_mode.app_rd_data_reg[209]\ => \not_strict_mode.app_rd_data_reg[209]\,
      \not_strict_mode.app_rd_data_reg[20]\ => \^not_strict_mode.app_rd_data_reg[20]\,
      \not_strict_mode.app_rd_data_reg[210]\ => \not_strict_mode.app_rd_data_reg[210]\,
      \not_strict_mode.app_rd_data_reg[211]\ => \not_strict_mode.app_rd_data_reg[211]\,
      \not_strict_mode.app_rd_data_reg[212]\ => \not_strict_mode.app_rd_data_reg[212]\,
      \not_strict_mode.app_rd_data_reg[213]\ => \not_strict_mode.app_rd_data_reg[213]\,
      \not_strict_mode.app_rd_data_reg[214]\ => \not_strict_mode.app_rd_data_reg[214]\,
      \not_strict_mode.app_rd_data_reg[215]\ => \not_strict_mode.app_rd_data_reg[215]\,
      \not_strict_mode.app_rd_data_reg[216]\ => \not_strict_mode.app_rd_data_reg[216]\,
      \not_strict_mode.app_rd_data_reg[217]\ => \not_strict_mode.app_rd_data_reg[217]\,
      \not_strict_mode.app_rd_data_reg[218]\ => \not_strict_mode.app_rd_data_reg[218]\,
      \not_strict_mode.app_rd_data_reg[219]\ => \not_strict_mode.app_rd_data_reg[219]\,
      \not_strict_mode.app_rd_data_reg[21]\ => \^not_strict_mode.app_rd_data_reg[21]\,
      \not_strict_mode.app_rd_data_reg[220]\ => \not_strict_mode.app_rd_data_reg[220]\,
      \not_strict_mode.app_rd_data_reg[221]\ => \not_strict_mode.app_rd_data_reg[221]\,
      \not_strict_mode.app_rd_data_reg[222]\ => \not_strict_mode.app_rd_data_reg[222]\,
      \not_strict_mode.app_rd_data_reg[223]\ => \not_strict_mode.app_rd_data_reg[223]\,
      \not_strict_mode.app_rd_data_reg[224]\ => \not_strict_mode.app_rd_data_reg[224]\,
      \not_strict_mode.app_rd_data_reg[225]\ => \not_strict_mode.app_rd_data_reg[225]\,
      \not_strict_mode.app_rd_data_reg[226]\ => \not_strict_mode.app_rd_data_reg[226]\,
      \not_strict_mode.app_rd_data_reg[227]\ => \not_strict_mode.app_rd_data_reg[227]\,
      \not_strict_mode.app_rd_data_reg[228]\ => \not_strict_mode.app_rd_data_reg[228]\,
      \not_strict_mode.app_rd_data_reg[229]\ => \not_strict_mode.app_rd_data_reg[229]\,
      \not_strict_mode.app_rd_data_reg[22]\ => \^not_strict_mode.app_rd_data_reg[22]\,
      \not_strict_mode.app_rd_data_reg[230]\ => \not_strict_mode.app_rd_data_reg[230]\,
      \not_strict_mode.app_rd_data_reg[231]\ => \not_strict_mode.app_rd_data_reg[231]\,
      \not_strict_mode.app_rd_data_reg[232]\ => \not_strict_mode.app_rd_data_reg[232]\,
      \not_strict_mode.app_rd_data_reg[233]\ => \not_strict_mode.app_rd_data_reg[233]\,
      \not_strict_mode.app_rd_data_reg[234]\ => \not_strict_mode.app_rd_data_reg[234]\,
      \not_strict_mode.app_rd_data_reg[235]\ => \not_strict_mode.app_rd_data_reg[235]\,
      \not_strict_mode.app_rd_data_reg[236]\ => \not_strict_mode.app_rd_data_reg[236]\,
      \not_strict_mode.app_rd_data_reg[237]\ => \not_strict_mode.app_rd_data_reg[237]\,
      \not_strict_mode.app_rd_data_reg[238]\ => \not_strict_mode.app_rd_data_reg[238]\,
      \not_strict_mode.app_rd_data_reg[239]\ => \not_strict_mode.app_rd_data_reg[239]\,
      \not_strict_mode.app_rd_data_reg[23]\ => \^not_strict_mode.app_rd_data_reg[23]\,
      \not_strict_mode.app_rd_data_reg[240]\ => \not_strict_mode.app_rd_data_reg[240]\,
      \not_strict_mode.app_rd_data_reg[241]\ => \not_strict_mode.app_rd_data_reg[241]\,
      \not_strict_mode.app_rd_data_reg[242]\ => \not_strict_mode.app_rd_data_reg[242]\,
      \not_strict_mode.app_rd_data_reg[243]\ => \not_strict_mode.app_rd_data_reg[243]\,
      \not_strict_mode.app_rd_data_reg[244]\ => \not_strict_mode.app_rd_data_reg[244]\,
      \not_strict_mode.app_rd_data_reg[245]\ => \not_strict_mode.app_rd_data_reg[245]\,
      \not_strict_mode.app_rd_data_reg[246]\ => \not_strict_mode.app_rd_data_reg[246]\,
      \not_strict_mode.app_rd_data_reg[247]\ => \not_strict_mode.app_rd_data_reg[247]\,
      \not_strict_mode.app_rd_data_reg[248]\ => \not_strict_mode.app_rd_data_reg[248]\,
      \not_strict_mode.app_rd_data_reg[249]\ => \not_strict_mode.app_rd_data_reg[249]\,
      \not_strict_mode.app_rd_data_reg[24]\ => \^not_strict_mode.app_rd_data_reg[24]\,
      \not_strict_mode.app_rd_data_reg[250]\ => \not_strict_mode.app_rd_data_reg[250]\,
      \not_strict_mode.app_rd_data_reg[251]\ => \not_strict_mode.app_rd_data_reg[251]\,
      \not_strict_mode.app_rd_data_reg[252]\ => \not_strict_mode.app_rd_data_reg[252]\,
      \not_strict_mode.app_rd_data_reg[253]\ => \not_strict_mode.app_rd_data_reg[253]\,
      \not_strict_mode.app_rd_data_reg[254]\ => \not_strict_mode.app_rd_data_reg[254]\,
      \not_strict_mode.app_rd_data_reg[255]\ => \not_strict_mode.app_rd_data_reg[255]\,
      \not_strict_mode.app_rd_data_reg[256]\ => \not_strict_mode.app_rd_data_reg[256]\,
      \not_strict_mode.app_rd_data_reg[257]\ => \not_strict_mode.app_rd_data_reg[257]\,
      \not_strict_mode.app_rd_data_reg[258]\ => \not_strict_mode.app_rd_data_reg[258]\,
      \not_strict_mode.app_rd_data_reg[259]\ => \not_strict_mode.app_rd_data_reg[259]\,
      \not_strict_mode.app_rd_data_reg[25]\ => \^not_strict_mode.app_rd_data_reg[25]\,
      \not_strict_mode.app_rd_data_reg[260]\ => \not_strict_mode.app_rd_data_reg[260]\,
      \not_strict_mode.app_rd_data_reg[261]\ => \not_strict_mode.app_rd_data_reg[261]\,
      \not_strict_mode.app_rd_data_reg[262]\ => \not_strict_mode.app_rd_data_reg[262]\,
      \not_strict_mode.app_rd_data_reg[263]\ => \not_strict_mode.app_rd_data_reg[263]\,
      \not_strict_mode.app_rd_data_reg[264]\ => \not_strict_mode.app_rd_data_reg[264]\,
      \not_strict_mode.app_rd_data_reg[265]\ => \not_strict_mode.app_rd_data_reg[265]\,
      \not_strict_mode.app_rd_data_reg[266]\ => \not_strict_mode.app_rd_data_reg[266]\,
      \not_strict_mode.app_rd_data_reg[267]\ => \not_strict_mode.app_rd_data_reg[267]\,
      \not_strict_mode.app_rd_data_reg[268]\ => \not_strict_mode.app_rd_data_reg[268]\,
      \not_strict_mode.app_rd_data_reg[269]\ => \not_strict_mode.app_rd_data_reg[269]\,
      \not_strict_mode.app_rd_data_reg[26]\ => \^not_strict_mode.app_rd_data_reg[26]\,
      \not_strict_mode.app_rd_data_reg[270]\ => \not_strict_mode.app_rd_data_reg[270]\,
      \not_strict_mode.app_rd_data_reg[271]\ => \not_strict_mode.app_rd_data_reg[271]\,
      \not_strict_mode.app_rd_data_reg[272]\ => \not_strict_mode.app_rd_data_reg[272]\,
      \not_strict_mode.app_rd_data_reg[273]\ => \not_strict_mode.app_rd_data_reg[273]\,
      \not_strict_mode.app_rd_data_reg[274]\ => \not_strict_mode.app_rd_data_reg[274]\,
      \not_strict_mode.app_rd_data_reg[275]\ => \not_strict_mode.app_rd_data_reg[275]\,
      \not_strict_mode.app_rd_data_reg[276]\ => \not_strict_mode.app_rd_data_reg[276]\,
      \not_strict_mode.app_rd_data_reg[277]\ => \not_strict_mode.app_rd_data_reg[277]\,
      \not_strict_mode.app_rd_data_reg[278]\ => \not_strict_mode.app_rd_data_reg[278]\,
      \not_strict_mode.app_rd_data_reg[279]\ => \not_strict_mode.app_rd_data_reg[279]\,
      \not_strict_mode.app_rd_data_reg[27]\ => \^not_strict_mode.app_rd_data_reg[27]\,
      \not_strict_mode.app_rd_data_reg[280]\ => \not_strict_mode.app_rd_data_reg[280]\,
      \not_strict_mode.app_rd_data_reg[281]\ => \not_strict_mode.app_rd_data_reg[281]\,
      \not_strict_mode.app_rd_data_reg[282]\ => \not_strict_mode.app_rd_data_reg[282]\,
      \not_strict_mode.app_rd_data_reg[283]\ => \not_strict_mode.app_rd_data_reg[283]\,
      \not_strict_mode.app_rd_data_reg[284]\ => \not_strict_mode.app_rd_data_reg[284]\,
      \not_strict_mode.app_rd_data_reg[285]\ => \not_strict_mode.app_rd_data_reg[285]\,
      \not_strict_mode.app_rd_data_reg[286]\ => \not_strict_mode.app_rd_data_reg[286]\,
      \not_strict_mode.app_rd_data_reg[287]\ => \not_strict_mode.app_rd_data_reg[287]\,
      \not_strict_mode.app_rd_data_reg[288]\ => \not_strict_mode.app_rd_data_reg[288]\,
      \not_strict_mode.app_rd_data_reg[289]\ => \not_strict_mode.app_rd_data_reg[289]\,
      \not_strict_mode.app_rd_data_reg[28]\ => \^not_strict_mode.app_rd_data_reg[28]\,
      \not_strict_mode.app_rd_data_reg[290]\ => \not_strict_mode.app_rd_data_reg[290]\,
      \not_strict_mode.app_rd_data_reg[291]\ => \not_strict_mode.app_rd_data_reg[291]\,
      \not_strict_mode.app_rd_data_reg[292]\ => \not_strict_mode.app_rd_data_reg[292]\,
      \not_strict_mode.app_rd_data_reg[293]\ => \not_strict_mode.app_rd_data_reg[293]\,
      \not_strict_mode.app_rd_data_reg[294]\ => \not_strict_mode.app_rd_data_reg[294]\,
      \not_strict_mode.app_rd_data_reg[295]\ => \not_strict_mode.app_rd_data_reg[295]\,
      \not_strict_mode.app_rd_data_reg[296]\ => \not_strict_mode.app_rd_data_reg[296]\,
      \not_strict_mode.app_rd_data_reg[297]\ => \not_strict_mode.app_rd_data_reg[297]\,
      \not_strict_mode.app_rd_data_reg[298]\ => \not_strict_mode.app_rd_data_reg[298]\,
      \not_strict_mode.app_rd_data_reg[299]\ => \not_strict_mode.app_rd_data_reg[299]\,
      \not_strict_mode.app_rd_data_reg[29]\ => \^not_strict_mode.app_rd_data_reg[29]\,
      \not_strict_mode.app_rd_data_reg[2]\ => \^not_strict_mode.app_rd_data_reg[2]\,
      \not_strict_mode.app_rd_data_reg[300]\ => \not_strict_mode.app_rd_data_reg[300]\,
      \not_strict_mode.app_rd_data_reg[301]\ => \not_strict_mode.app_rd_data_reg[301]\,
      \not_strict_mode.app_rd_data_reg[302]\ => \not_strict_mode.app_rd_data_reg[302]\,
      \not_strict_mode.app_rd_data_reg[303]\ => \not_strict_mode.app_rd_data_reg[303]\,
      \not_strict_mode.app_rd_data_reg[304]\ => \not_strict_mode.app_rd_data_reg[304]\,
      \not_strict_mode.app_rd_data_reg[305]\ => \not_strict_mode.app_rd_data_reg[305]\,
      \not_strict_mode.app_rd_data_reg[306]\ => \not_strict_mode.app_rd_data_reg[306]\,
      \not_strict_mode.app_rd_data_reg[307]\ => \not_strict_mode.app_rd_data_reg[307]\,
      \not_strict_mode.app_rd_data_reg[308]\ => \not_strict_mode.app_rd_data_reg[308]\,
      \not_strict_mode.app_rd_data_reg[309]\ => \not_strict_mode.app_rd_data_reg[309]\,
      \not_strict_mode.app_rd_data_reg[30]\ => \^not_strict_mode.app_rd_data_reg[30]\,
      \not_strict_mode.app_rd_data_reg[310]\ => \not_strict_mode.app_rd_data_reg[310]\,
      \not_strict_mode.app_rd_data_reg[311]\ => \not_strict_mode.app_rd_data_reg[311]\,
      \not_strict_mode.app_rd_data_reg[312]\ => \not_strict_mode.app_rd_data_reg[312]\,
      \not_strict_mode.app_rd_data_reg[313]\ => \not_strict_mode.app_rd_data_reg[313]\,
      \not_strict_mode.app_rd_data_reg[314]\ => \not_strict_mode.app_rd_data_reg[314]\,
      \not_strict_mode.app_rd_data_reg[315]\ => \not_strict_mode.app_rd_data_reg[315]\,
      \not_strict_mode.app_rd_data_reg[316]\ => \not_strict_mode.app_rd_data_reg[316]\,
      \not_strict_mode.app_rd_data_reg[317]\ => \not_strict_mode.app_rd_data_reg[317]\,
      \not_strict_mode.app_rd_data_reg[318]\ => \not_strict_mode.app_rd_data_reg[318]\,
      \not_strict_mode.app_rd_data_reg[319]\ => \not_strict_mode.app_rd_data_reg[319]\,
      \not_strict_mode.app_rd_data_reg[31]\ => \^not_strict_mode.app_rd_data_reg[31]\,
      \not_strict_mode.app_rd_data_reg[320]\ => \not_strict_mode.app_rd_data_reg[320]\,
      \not_strict_mode.app_rd_data_reg[321]\ => \not_strict_mode.app_rd_data_reg[321]\,
      \not_strict_mode.app_rd_data_reg[322]\ => \not_strict_mode.app_rd_data_reg[322]\,
      \not_strict_mode.app_rd_data_reg[323]\ => \not_strict_mode.app_rd_data_reg[323]\,
      \not_strict_mode.app_rd_data_reg[324]\ => \not_strict_mode.app_rd_data_reg[324]\,
      \not_strict_mode.app_rd_data_reg[325]\ => \not_strict_mode.app_rd_data_reg[325]\,
      \not_strict_mode.app_rd_data_reg[326]\ => \not_strict_mode.app_rd_data_reg[326]\,
      \not_strict_mode.app_rd_data_reg[327]\ => \not_strict_mode.app_rd_data_reg[327]\,
      \not_strict_mode.app_rd_data_reg[328]\ => \not_strict_mode.app_rd_data_reg[328]\,
      \not_strict_mode.app_rd_data_reg[329]\ => \not_strict_mode.app_rd_data_reg[329]\,
      \not_strict_mode.app_rd_data_reg[32]\ => \^not_strict_mode.app_rd_data_reg[32]\,
      \not_strict_mode.app_rd_data_reg[330]\ => \not_strict_mode.app_rd_data_reg[330]\,
      \not_strict_mode.app_rd_data_reg[331]\ => \not_strict_mode.app_rd_data_reg[331]\,
      \not_strict_mode.app_rd_data_reg[332]\ => \not_strict_mode.app_rd_data_reg[332]\,
      \not_strict_mode.app_rd_data_reg[333]\ => \not_strict_mode.app_rd_data_reg[333]\,
      \not_strict_mode.app_rd_data_reg[334]\ => \not_strict_mode.app_rd_data_reg[334]\,
      \not_strict_mode.app_rd_data_reg[335]\ => \not_strict_mode.app_rd_data_reg[335]\,
      \not_strict_mode.app_rd_data_reg[336]\ => \not_strict_mode.app_rd_data_reg[336]\,
      \not_strict_mode.app_rd_data_reg[337]\ => \not_strict_mode.app_rd_data_reg[337]\,
      \not_strict_mode.app_rd_data_reg[338]\ => \not_strict_mode.app_rd_data_reg[338]\,
      \not_strict_mode.app_rd_data_reg[339]\ => \not_strict_mode.app_rd_data_reg[339]\,
      \not_strict_mode.app_rd_data_reg[33]\ => \^not_strict_mode.app_rd_data_reg[33]\,
      \not_strict_mode.app_rd_data_reg[340]\ => \not_strict_mode.app_rd_data_reg[340]\,
      \not_strict_mode.app_rd_data_reg[341]\ => \not_strict_mode.app_rd_data_reg[341]\,
      \not_strict_mode.app_rd_data_reg[342]\ => \not_strict_mode.app_rd_data_reg[342]\,
      \not_strict_mode.app_rd_data_reg[343]\ => \not_strict_mode.app_rd_data_reg[343]\,
      \not_strict_mode.app_rd_data_reg[344]\ => \not_strict_mode.app_rd_data_reg[344]\,
      \not_strict_mode.app_rd_data_reg[345]\ => \not_strict_mode.app_rd_data_reg[345]\,
      \not_strict_mode.app_rd_data_reg[346]\ => \not_strict_mode.app_rd_data_reg[346]\,
      \not_strict_mode.app_rd_data_reg[347]\ => \not_strict_mode.app_rd_data_reg[347]\,
      \not_strict_mode.app_rd_data_reg[348]\ => \not_strict_mode.app_rd_data_reg[348]\,
      \not_strict_mode.app_rd_data_reg[349]\ => \not_strict_mode.app_rd_data_reg[349]\,
      \not_strict_mode.app_rd_data_reg[34]\ => \^not_strict_mode.app_rd_data_reg[34]\,
      \not_strict_mode.app_rd_data_reg[350]\ => \not_strict_mode.app_rd_data_reg[350]\,
      \not_strict_mode.app_rd_data_reg[351]\ => \not_strict_mode.app_rd_data_reg[351]\,
      \not_strict_mode.app_rd_data_reg[352]\ => \not_strict_mode.app_rd_data_reg[352]\,
      \not_strict_mode.app_rd_data_reg[353]\ => \not_strict_mode.app_rd_data_reg[353]\,
      \not_strict_mode.app_rd_data_reg[354]\ => \not_strict_mode.app_rd_data_reg[354]\,
      \not_strict_mode.app_rd_data_reg[355]\ => \not_strict_mode.app_rd_data_reg[355]\,
      \not_strict_mode.app_rd_data_reg[356]\ => \not_strict_mode.app_rd_data_reg[356]\,
      \not_strict_mode.app_rd_data_reg[357]\ => \not_strict_mode.app_rd_data_reg[357]\,
      \not_strict_mode.app_rd_data_reg[358]\ => \not_strict_mode.app_rd_data_reg[358]\,
      \not_strict_mode.app_rd_data_reg[359]\ => \not_strict_mode.app_rd_data_reg[359]\,
      \not_strict_mode.app_rd_data_reg[35]\ => \^not_strict_mode.app_rd_data_reg[35]\,
      \not_strict_mode.app_rd_data_reg[360]\ => \not_strict_mode.app_rd_data_reg[360]\,
      \not_strict_mode.app_rd_data_reg[361]\ => \not_strict_mode.app_rd_data_reg[361]\,
      \not_strict_mode.app_rd_data_reg[362]\ => \not_strict_mode.app_rd_data_reg[362]\,
      \not_strict_mode.app_rd_data_reg[363]\ => \not_strict_mode.app_rd_data_reg[363]\,
      \not_strict_mode.app_rd_data_reg[364]\ => \not_strict_mode.app_rd_data_reg[364]\,
      \not_strict_mode.app_rd_data_reg[365]\ => \not_strict_mode.app_rd_data_reg[365]\,
      \not_strict_mode.app_rd_data_reg[366]\ => \not_strict_mode.app_rd_data_reg[366]\,
      \not_strict_mode.app_rd_data_reg[367]\ => \not_strict_mode.app_rd_data_reg[367]\,
      \not_strict_mode.app_rd_data_reg[368]\ => \not_strict_mode.app_rd_data_reg[368]\,
      \not_strict_mode.app_rd_data_reg[369]\ => \not_strict_mode.app_rd_data_reg[369]\,
      \not_strict_mode.app_rd_data_reg[36]\ => \^not_strict_mode.app_rd_data_reg[36]\,
      \not_strict_mode.app_rd_data_reg[370]\ => \not_strict_mode.app_rd_data_reg[370]\,
      \not_strict_mode.app_rd_data_reg[371]\ => \not_strict_mode.app_rd_data_reg[371]\,
      \not_strict_mode.app_rd_data_reg[372]\ => \not_strict_mode.app_rd_data_reg[372]\,
      \not_strict_mode.app_rd_data_reg[373]\ => \not_strict_mode.app_rd_data_reg[373]\,
      \not_strict_mode.app_rd_data_reg[374]\ => \not_strict_mode.app_rd_data_reg[374]\,
      \not_strict_mode.app_rd_data_reg[375]\ => \not_strict_mode.app_rd_data_reg[375]\,
      \not_strict_mode.app_rd_data_reg[376]\ => \not_strict_mode.app_rd_data_reg[376]\,
      \not_strict_mode.app_rd_data_reg[377]\ => \not_strict_mode.app_rd_data_reg[377]\,
      \not_strict_mode.app_rd_data_reg[378]\ => \not_strict_mode.app_rd_data_reg[378]\,
      \not_strict_mode.app_rd_data_reg[379]\ => \not_strict_mode.app_rd_data_reg[379]\,
      \not_strict_mode.app_rd_data_reg[37]\ => \^not_strict_mode.app_rd_data_reg[37]\,
      \not_strict_mode.app_rd_data_reg[380]\ => \not_strict_mode.app_rd_data_reg[380]\,
      \not_strict_mode.app_rd_data_reg[381]\ => \not_strict_mode.app_rd_data_reg[381]\,
      \not_strict_mode.app_rd_data_reg[382]\ => \not_strict_mode.app_rd_data_reg[382]\,
      \not_strict_mode.app_rd_data_reg[383]\ => \not_strict_mode.app_rd_data_reg[383]\,
      \not_strict_mode.app_rd_data_reg[384]\ => \not_strict_mode.app_rd_data_reg[384]\,
      \not_strict_mode.app_rd_data_reg[385]\ => \not_strict_mode.app_rd_data_reg[385]\,
      \not_strict_mode.app_rd_data_reg[386]\ => \not_strict_mode.app_rd_data_reg[386]\,
      \not_strict_mode.app_rd_data_reg[387]\ => \not_strict_mode.app_rd_data_reg[387]\,
      \not_strict_mode.app_rd_data_reg[388]\ => \not_strict_mode.app_rd_data_reg[388]\,
      \not_strict_mode.app_rd_data_reg[389]\ => \not_strict_mode.app_rd_data_reg[389]\,
      \not_strict_mode.app_rd_data_reg[38]\ => \^not_strict_mode.app_rd_data_reg[38]\,
      \not_strict_mode.app_rd_data_reg[390]\ => \not_strict_mode.app_rd_data_reg[390]\,
      \not_strict_mode.app_rd_data_reg[391]\ => \not_strict_mode.app_rd_data_reg[391]\,
      \not_strict_mode.app_rd_data_reg[392]\ => \not_strict_mode.app_rd_data_reg[392]\,
      \not_strict_mode.app_rd_data_reg[393]\ => \not_strict_mode.app_rd_data_reg[393]\,
      \not_strict_mode.app_rd_data_reg[394]\ => \not_strict_mode.app_rd_data_reg[394]\,
      \not_strict_mode.app_rd_data_reg[395]\ => \not_strict_mode.app_rd_data_reg[395]\,
      \not_strict_mode.app_rd_data_reg[396]\ => \not_strict_mode.app_rd_data_reg[396]\,
      \not_strict_mode.app_rd_data_reg[397]\ => \not_strict_mode.app_rd_data_reg[397]\,
      \not_strict_mode.app_rd_data_reg[398]\ => \not_strict_mode.app_rd_data_reg[398]\,
      \not_strict_mode.app_rd_data_reg[399]\ => \not_strict_mode.app_rd_data_reg[399]\,
      \not_strict_mode.app_rd_data_reg[39]\ => \^not_strict_mode.app_rd_data_reg[39]\,
      \not_strict_mode.app_rd_data_reg[3]\ => \^not_strict_mode.app_rd_data_reg[3]\,
      \not_strict_mode.app_rd_data_reg[400]\ => \not_strict_mode.app_rd_data_reg[400]\,
      \not_strict_mode.app_rd_data_reg[401]\ => \not_strict_mode.app_rd_data_reg[401]\,
      \not_strict_mode.app_rd_data_reg[402]\ => \not_strict_mode.app_rd_data_reg[402]\,
      \not_strict_mode.app_rd_data_reg[403]\ => \not_strict_mode.app_rd_data_reg[403]\,
      \not_strict_mode.app_rd_data_reg[404]\ => \not_strict_mode.app_rd_data_reg[404]\,
      \not_strict_mode.app_rd_data_reg[405]\ => \not_strict_mode.app_rd_data_reg[405]\,
      \not_strict_mode.app_rd_data_reg[406]\ => \not_strict_mode.app_rd_data_reg[406]\,
      \not_strict_mode.app_rd_data_reg[407]\ => \not_strict_mode.app_rd_data_reg[407]\,
      \not_strict_mode.app_rd_data_reg[408]\ => \not_strict_mode.app_rd_data_reg[408]\,
      \not_strict_mode.app_rd_data_reg[409]\ => \not_strict_mode.app_rd_data_reg[409]\,
      \not_strict_mode.app_rd_data_reg[40]\ => \^not_strict_mode.app_rd_data_reg[40]\,
      \not_strict_mode.app_rd_data_reg[410]\ => \not_strict_mode.app_rd_data_reg[410]\,
      \not_strict_mode.app_rd_data_reg[411]\ => \not_strict_mode.app_rd_data_reg[411]\,
      \not_strict_mode.app_rd_data_reg[412]\ => \not_strict_mode.app_rd_data_reg[412]\,
      \not_strict_mode.app_rd_data_reg[413]\ => \not_strict_mode.app_rd_data_reg[413]\,
      \not_strict_mode.app_rd_data_reg[414]\ => \not_strict_mode.app_rd_data_reg[414]\,
      \not_strict_mode.app_rd_data_reg[415]\ => \not_strict_mode.app_rd_data_reg[415]\,
      \not_strict_mode.app_rd_data_reg[416]\ => \not_strict_mode.app_rd_data_reg[416]\,
      \not_strict_mode.app_rd_data_reg[417]\ => \not_strict_mode.app_rd_data_reg[417]\,
      \not_strict_mode.app_rd_data_reg[418]\ => \not_strict_mode.app_rd_data_reg[418]\,
      \not_strict_mode.app_rd_data_reg[419]\ => \not_strict_mode.app_rd_data_reg[419]\,
      \not_strict_mode.app_rd_data_reg[41]\ => \^not_strict_mode.app_rd_data_reg[41]\,
      \not_strict_mode.app_rd_data_reg[420]\ => \not_strict_mode.app_rd_data_reg[420]\,
      \not_strict_mode.app_rd_data_reg[421]\ => \not_strict_mode.app_rd_data_reg[421]\,
      \not_strict_mode.app_rd_data_reg[422]\ => \not_strict_mode.app_rd_data_reg[422]\,
      \not_strict_mode.app_rd_data_reg[423]\ => \not_strict_mode.app_rd_data_reg[423]\,
      \not_strict_mode.app_rd_data_reg[424]\ => \not_strict_mode.app_rd_data_reg[424]\,
      \not_strict_mode.app_rd_data_reg[425]\ => \not_strict_mode.app_rd_data_reg[425]\,
      \not_strict_mode.app_rd_data_reg[426]\ => \not_strict_mode.app_rd_data_reg[426]\,
      \not_strict_mode.app_rd_data_reg[427]\ => \not_strict_mode.app_rd_data_reg[427]\,
      \not_strict_mode.app_rd_data_reg[428]\ => \not_strict_mode.app_rd_data_reg[428]\,
      \not_strict_mode.app_rd_data_reg[429]\ => \not_strict_mode.app_rd_data_reg[429]\,
      \not_strict_mode.app_rd_data_reg[42]\ => \^not_strict_mode.app_rd_data_reg[42]\,
      \not_strict_mode.app_rd_data_reg[430]\ => \not_strict_mode.app_rd_data_reg[430]\,
      \not_strict_mode.app_rd_data_reg[431]\ => \not_strict_mode.app_rd_data_reg[431]\,
      \not_strict_mode.app_rd_data_reg[432]\ => \not_strict_mode.app_rd_data_reg[432]\,
      \not_strict_mode.app_rd_data_reg[433]\ => \not_strict_mode.app_rd_data_reg[433]\,
      \not_strict_mode.app_rd_data_reg[434]\ => \not_strict_mode.app_rd_data_reg[434]\,
      \not_strict_mode.app_rd_data_reg[435]\ => \not_strict_mode.app_rd_data_reg[435]\,
      \not_strict_mode.app_rd_data_reg[436]\ => \not_strict_mode.app_rd_data_reg[436]\,
      \not_strict_mode.app_rd_data_reg[437]\ => \not_strict_mode.app_rd_data_reg[437]\,
      \not_strict_mode.app_rd_data_reg[438]\ => \not_strict_mode.app_rd_data_reg[438]\,
      \not_strict_mode.app_rd_data_reg[439]\ => \not_strict_mode.app_rd_data_reg[439]\,
      \not_strict_mode.app_rd_data_reg[43]\ => \^not_strict_mode.app_rd_data_reg[43]\,
      \not_strict_mode.app_rd_data_reg[440]\ => \not_strict_mode.app_rd_data_reg[440]\,
      \not_strict_mode.app_rd_data_reg[441]\ => \not_strict_mode.app_rd_data_reg[441]\,
      \not_strict_mode.app_rd_data_reg[442]\ => \not_strict_mode.app_rd_data_reg[442]\,
      \not_strict_mode.app_rd_data_reg[443]\ => \not_strict_mode.app_rd_data_reg[443]\,
      \not_strict_mode.app_rd_data_reg[444]\ => \not_strict_mode.app_rd_data_reg[444]\,
      \not_strict_mode.app_rd_data_reg[445]\ => \not_strict_mode.app_rd_data_reg[445]\,
      \not_strict_mode.app_rd_data_reg[446]\ => \not_strict_mode.app_rd_data_reg[446]\,
      \not_strict_mode.app_rd_data_reg[447]\ => \not_strict_mode.app_rd_data_reg[447]\,
      \not_strict_mode.app_rd_data_reg[448]\ => \not_strict_mode.app_rd_data_reg[448]\,
      \not_strict_mode.app_rd_data_reg[449]\ => \not_strict_mode.app_rd_data_reg[449]\,
      \not_strict_mode.app_rd_data_reg[44]\ => \^not_strict_mode.app_rd_data_reg[44]\,
      \not_strict_mode.app_rd_data_reg[450]\ => \not_strict_mode.app_rd_data_reg[450]\,
      \not_strict_mode.app_rd_data_reg[451]\ => \not_strict_mode.app_rd_data_reg[451]\,
      \not_strict_mode.app_rd_data_reg[452]\ => \not_strict_mode.app_rd_data_reg[452]\,
      \not_strict_mode.app_rd_data_reg[453]\ => \not_strict_mode.app_rd_data_reg[453]\,
      \not_strict_mode.app_rd_data_reg[454]\ => \not_strict_mode.app_rd_data_reg[454]\,
      \not_strict_mode.app_rd_data_reg[455]\ => \not_strict_mode.app_rd_data_reg[455]\,
      \not_strict_mode.app_rd_data_reg[456]\ => \not_strict_mode.app_rd_data_reg[456]\,
      \not_strict_mode.app_rd_data_reg[457]\ => \not_strict_mode.app_rd_data_reg[457]\,
      \not_strict_mode.app_rd_data_reg[458]\ => \not_strict_mode.app_rd_data_reg[458]\,
      \not_strict_mode.app_rd_data_reg[459]\ => \not_strict_mode.app_rd_data_reg[459]\,
      \not_strict_mode.app_rd_data_reg[45]\ => \^not_strict_mode.app_rd_data_reg[45]\,
      \not_strict_mode.app_rd_data_reg[460]\ => \not_strict_mode.app_rd_data_reg[460]\,
      \not_strict_mode.app_rd_data_reg[461]\ => \not_strict_mode.app_rd_data_reg[461]\,
      \not_strict_mode.app_rd_data_reg[462]\ => \not_strict_mode.app_rd_data_reg[462]\,
      \not_strict_mode.app_rd_data_reg[463]\ => \not_strict_mode.app_rd_data_reg[463]\,
      \not_strict_mode.app_rd_data_reg[464]\ => \not_strict_mode.app_rd_data_reg[464]\,
      \not_strict_mode.app_rd_data_reg[465]\ => \not_strict_mode.app_rd_data_reg[465]\,
      \not_strict_mode.app_rd_data_reg[466]\ => \not_strict_mode.app_rd_data_reg[466]\,
      \not_strict_mode.app_rd_data_reg[467]\ => \not_strict_mode.app_rd_data_reg[467]\,
      \not_strict_mode.app_rd_data_reg[468]\ => \not_strict_mode.app_rd_data_reg[468]\,
      \not_strict_mode.app_rd_data_reg[469]\ => \not_strict_mode.app_rd_data_reg[469]\,
      \not_strict_mode.app_rd_data_reg[46]\ => \^not_strict_mode.app_rd_data_reg[46]\,
      \not_strict_mode.app_rd_data_reg[470]\ => \not_strict_mode.app_rd_data_reg[470]\,
      \not_strict_mode.app_rd_data_reg[471]\ => \not_strict_mode.app_rd_data_reg[471]\,
      \not_strict_mode.app_rd_data_reg[472]\ => \not_strict_mode.app_rd_data_reg[472]\,
      \not_strict_mode.app_rd_data_reg[473]\ => \not_strict_mode.app_rd_data_reg[473]\,
      \not_strict_mode.app_rd_data_reg[474]\ => \not_strict_mode.app_rd_data_reg[474]\,
      \not_strict_mode.app_rd_data_reg[475]\ => \not_strict_mode.app_rd_data_reg[475]\,
      \not_strict_mode.app_rd_data_reg[476]\ => \not_strict_mode.app_rd_data_reg[476]\,
      \not_strict_mode.app_rd_data_reg[477]\ => \not_strict_mode.app_rd_data_reg[477]\,
      \not_strict_mode.app_rd_data_reg[478]\ => \not_strict_mode.app_rd_data_reg[478]\,
      \not_strict_mode.app_rd_data_reg[479]\ => \not_strict_mode.app_rd_data_reg[479]\,
      \not_strict_mode.app_rd_data_reg[47]\ => \^not_strict_mode.app_rd_data_reg[47]\,
      \not_strict_mode.app_rd_data_reg[480]\ => \not_strict_mode.app_rd_data_reg[480]\,
      \not_strict_mode.app_rd_data_reg[481]\ => \not_strict_mode.app_rd_data_reg[481]\,
      \not_strict_mode.app_rd_data_reg[482]\ => \not_strict_mode.app_rd_data_reg[482]\,
      \not_strict_mode.app_rd_data_reg[483]\ => \not_strict_mode.app_rd_data_reg[483]\,
      \not_strict_mode.app_rd_data_reg[484]\ => \not_strict_mode.app_rd_data_reg[484]\,
      \not_strict_mode.app_rd_data_reg[485]\ => \not_strict_mode.app_rd_data_reg[485]\,
      \not_strict_mode.app_rd_data_reg[486]\ => \not_strict_mode.app_rd_data_reg[486]\,
      \not_strict_mode.app_rd_data_reg[487]\ => \not_strict_mode.app_rd_data_reg[487]\,
      \not_strict_mode.app_rd_data_reg[488]\ => \not_strict_mode.app_rd_data_reg[488]\,
      \not_strict_mode.app_rd_data_reg[489]\ => \not_strict_mode.app_rd_data_reg[489]\,
      \not_strict_mode.app_rd_data_reg[48]\ => \^not_strict_mode.app_rd_data_reg[48]\,
      \not_strict_mode.app_rd_data_reg[490]\ => \not_strict_mode.app_rd_data_reg[490]\,
      \not_strict_mode.app_rd_data_reg[491]\ => \not_strict_mode.app_rd_data_reg[491]\,
      \not_strict_mode.app_rd_data_reg[492]\ => \not_strict_mode.app_rd_data_reg[492]\,
      \not_strict_mode.app_rd_data_reg[493]\ => \not_strict_mode.app_rd_data_reg[493]\,
      \not_strict_mode.app_rd_data_reg[494]\ => \not_strict_mode.app_rd_data_reg[494]\,
      \not_strict_mode.app_rd_data_reg[495]\ => \not_strict_mode.app_rd_data_reg[495]\,
      \not_strict_mode.app_rd_data_reg[496]\ => \not_strict_mode.app_rd_data_reg[496]\,
      \not_strict_mode.app_rd_data_reg[497]\ => \not_strict_mode.app_rd_data_reg[497]\,
      \not_strict_mode.app_rd_data_reg[498]\ => \not_strict_mode.app_rd_data_reg[498]\,
      \not_strict_mode.app_rd_data_reg[499]\ => \not_strict_mode.app_rd_data_reg[499]\,
      \not_strict_mode.app_rd_data_reg[49]\ => \^not_strict_mode.app_rd_data_reg[49]\,
      \not_strict_mode.app_rd_data_reg[4]\ => \^not_strict_mode.app_rd_data_reg[4]\,
      \not_strict_mode.app_rd_data_reg[500]\ => \not_strict_mode.app_rd_data_reg[500]\,
      \not_strict_mode.app_rd_data_reg[501]\ => \not_strict_mode.app_rd_data_reg[501]\,
      \not_strict_mode.app_rd_data_reg[502]\ => \not_strict_mode.app_rd_data_reg[502]\,
      \not_strict_mode.app_rd_data_reg[503]\ => \not_strict_mode.app_rd_data_reg[503]\,
      \not_strict_mode.app_rd_data_reg[504]\ => \not_strict_mode.app_rd_data_reg[504]\,
      \not_strict_mode.app_rd_data_reg[505]\ => \not_strict_mode.app_rd_data_reg[505]\,
      \not_strict_mode.app_rd_data_reg[506]\ => \not_strict_mode.app_rd_data_reg[506]\,
      \not_strict_mode.app_rd_data_reg[507]\ => \not_strict_mode.app_rd_data_reg[507]\,
      \not_strict_mode.app_rd_data_reg[508]\ => \not_strict_mode.app_rd_data_reg[508]\,
      \not_strict_mode.app_rd_data_reg[509]\ => \not_strict_mode.app_rd_data_reg[509]\,
      \not_strict_mode.app_rd_data_reg[50]\ => \^not_strict_mode.app_rd_data_reg[50]\,
      \not_strict_mode.app_rd_data_reg[510]\ => \not_strict_mode.app_rd_data_reg[510]\,
      \not_strict_mode.app_rd_data_reg[511]\ => \not_strict_mode.app_rd_data_reg[511]\,
      \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 0) => \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 0),
      \not_strict_mode.app_rd_data_reg[51]\ => \^not_strict_mode.app_rd_data_reg[51]\,
      \not_strict_mode.app_rd_data_reg[52]\ => \^not_strict_mode.app_rd_data_reg[52]\,
      \not_strict_mode.app_rd_data_reg[53]\ => \^not_strict_mode.app_rd_data_reg[53]\,
      \not_strict_mode.app_rd_data_reg[54]\ => \^not_strict_mode.app_rd_data_reg[54]\,
      \not_strict_mode.app_rd_data_reg[55]\ => \^not_strict_mode.app_rd_data_reg[55]\,
      \not_strict_mode.app_rd_data_reg[56]\ => \^not_strict_mode.app_rd_data_reg[56]\,
      \not_strict_mode.app_rd_data_reg[57]\ => \^not_strict_mode.app_rd_data_reg[57]\,
      \not_strict_mode.app_rd_data_reg[58]\ => \^not_strict_mode.app_rd_data_reg[58]\,
      \not_strict_mode.app_rd_data_reg[59]\ => \^not_strict_mode.app_rd_data_reg[59]\,
      \not_strict_mode.app_rd_data_reg[5]\ => \^not_strict_mode.app_rd_data_reg[5]\,
      \not_strict_mode.app_rd_data_reg[60]\ => \^not_strict_mode.app_rd_data_reg[60]\,
      \not_strict_mode.app_rd_data_reg[61]\ => \^not_strict_mode.app_rd_data_reg[61]\,
      \not_strict_mode.app_rd_data_reg[62]\ => \^not_strict_mode.app_rd_data_reg[62]\,
      \not_strict_mode.app_rd_data_reg[63]\ => \^not_strict_mode.app_rd_data_reg[63]\,
      \not_strict_mode.app_rd_data_reg[64]\ => \not_strict_mode.app_rd_data_reg[64]\,
      \not_strict_mode.app_rd_data_reg[65]\ => \not_strict_mode.app_rd_data_reg[65]\,
      \not_strict_mode.app_rd_data_reg[66]\ => \not_strict_mode.app_rd_data_reg[66]\,
      \not_strict_mode.app_rd_data_reg[67]\ => \not_strict_mode.app_rd_data_reg[67]\,
      \not_strict_mode.app_rd_data_reg[68]\ => \not_strict_mode.app_rd_data_reg[68]\,
      \not_strict_mode.app_rd_data_reg[69]\ => \not_strict_mode.app_rd_data_reg[69]\,
      \not_strict_mode.app_rd_data_reg[6]\ => \^not_strict_mode.app_rd_data_reg[6]\,
      \not_strict_mode.app_rd_data_reg[70]\ => \not_strict_mode.app_rd_data_reg[70]\,
      \not_strict_mode.app_rd_data_reg[71]\ => \not_strict_mode.app_rd_data_reg[71]\,
      \not_strict_mode.app_rd_data_reg[72]\ => \not_strict_mode.app_rd_data_reg[72]\,
      \not_strict_mode.app_rd_data_reg[73]\ => \not_strict_mode.app_rd_data_reg[73]\,
      \not_strict_mode.app_rd_data_reg[74]\ => \not_strict_mode.app_rd_data_reg[74]\,
      \not_strict_mode.app_rd_data_reg[75]\ => \not_strict_mode.app_rd_data_reg[75]\,
      \not_strict_mode.app_rd_data_reg[76]\ => \not_strict_mode.app_rd_data_reg[76]\,
      \not_strict_mode.app_rd_data_reg[77]\ => \not_strict_mode.app_rd_data_reg[77]\,
      \not_strict_mode.app_rd_data_reg[78]\ => \not_strict_mode.app_rd_data_reg[78]\,
      \not_strict_mode.app_rd_data_reg[79]\ => \not_strict_mode.app_rd_data_reg[79]\,
      \not_strict_mode.app_rd_data_reg[7]\ => \^not_strict_mode.app_rd_data_reg[7]\,
      \not_strict_mode.app_rd_data_reg[80]\ => \not_strict_mode.app_rd_data_reg[80]\,
      \not_strict_mode.app_rd_data_reg[81]\ => \not_strict_mode.app_rd_data_reg[81]\,
      \not_strict_mode.app_rd_data_reg[82]\ => \not_strict_mode.app_rd_data_reg[82]\,
      \not_strict_mode.app_rd_data_reg[83]\ => \not_strict_mode.app_rd_data_reg[83]\,
      \not_strict_mode.app_rd_data_reg[84]\ => \not_strict_mode.app_rd_data_reg[84]\,
      \not_strict_mode.app_rd_data_reg[85]\ => \not_strict_mode.app_rd_data_reg[85]\,
      \not_strict_mode.app_rd_data_reg[86]\ => \not_strict_mode.app_rd_data_reg[86]\,
      \not_strict_mode.app_rd_data_reg[87]\ => \not_strict_mode.app_rd_data_reg[87]\,
      \not_strict_mode.app_rd_data_reg[88]\ => \not_strict_mode.app_rd_data_reg[88]\,
      \not_strict_mode.app_rd_data_reg[89]\ => \not_strict_mode.app_rd_data_reg[89]\,
      \not_strict_mode.app_rd_data_reg[8]\ => \^not_strict_mode.app_rd_data_reg[8]\,
      \not_strict_mode.app_rd_data_reg[90]\ => \not_strict_mode.app_rd_data_reg[90]\,
      \not_strict_mode.app_rd_data_reg[91]\ => \not_strict_mode.app_rd_data_reg[91]\,
      \not_strict_mode.app_rd_data_reg[92]\ => \not_strict_mode.app_rd_data_reg[92]\,
      \not_strict_mode.app_rd_data_reg[93]\ => \not_strict_mode.app_rd_data_reg[93]\,
      \not_strict_mode.app_rd_data_reg[94]\ => \not_strict_mode.app_rd_data_reg[94]\,
      \not_strict_mode.app_rd_data_reg[95]\ => \not_strict_mode.app_rd_data_reg[95]\,
      \not_strict_mode.app_rd_data_reg[96]\ => \not_strict_mode.app_rd_data_reg[96]\,
      \not_strict_mode.app_rd_data_reg[97]\ => \not_strict_mode.app_rd_data_reg[97]\,
      \not_strict_mode.app_rd_data_reg[98]\ => \not_strict_mode.app_rd_data_reg[98]\,
      \not_strict_mode.app_rd_data_reg[99]\ => \not_strict_mode.app_rd_data_reg[99]\,
      \not_strict_mode.app_rd_data_reg[9]\ => \^not_strict_mode.app_rd_data_reg[9]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \not_strict_mode.rd_buf_we\,
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\ => \not_strict_mode.status_ram.rd_buf_we_r1_reg\,
      of_ctl_full_v(0) => of_ctl_full_v(0),
      ofifo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\,
      ofifo_rst_reg0_11 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst_reg0\,
      ofifo_rst_reg0_13 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ofifo_rst_reg0\,
      ofifo_rst_reg0_15 => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\,
      \out\ => u_ddr_calib_top_n_1,
      p_0_out => \u_ddr_phy_wrcal/p_0_out\,
      p_110_in => \u_ddr_phy_init/p_110_in\,
      phy_cmd_wr_en => phy_cmd_wr_en,
      phy_data_wr_en => phy_data_wr_en,
      phy_dout(10) => phy_dout(5),
      phy_dout(9) => mux_cas_n(1),
      phy_dout(8 downto 7) => phy_dout(4 downto 3),
      phy_dout(6) => mux_we_n(1),
      phy_dout(5 downto 4) => phy_dout(2 downto 1),
      phy_dout(3) => mux_cs_n(1),
      phy_dout(2) => phy_dout(0),
      phy_dout(1) => mux_cke(3),
      phy_dout(0) => mux_odt(0),
      phy_if_reset => phy_if_reset,
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      phy_mc_go => phy_mc_go,
      phy_rddata_en => phy_rddata_en,
      phy_read_calib => phy_read_calib,
      phy_write_calib => phy_write_calib,
      pi_dqs_found_lanes(7) => u_ddr_mc_phy_wrapper_n_2,
      pi_dqs_found_lanes(6) => u_ddr_mc_phy_wrapper_n_3,
      pi_dqs_found_lanes(5) => u_ddr_mc_phy_wrapper_n_4,
      pi_dqs_found_lanes(4) => u_ddr_mc_phy_wrapper_n_5,
      pi_dqs_found_lanes(3) => u_ddr_mc_phy_wrapper_n_6,
      pi_dqs_found_lanes(2) => u_ddr_mc_phy_wrapper_n_7,
      pi_dqs_found_lanes(1) => u_ddr_mc_phy_wrapper_n_8,
      pi_dqs_found_lanes(0) => u_ddr_mc_phy_wrapper_n_9,
      pi_phase_locked_all_r1_reg => u_ddr_mc_phy_wrapper_n_1248,
      \pi_rdval_cnt_reg[0]\ => u_ddr_mc_phy_wrapper_n_669,
      \pi_rdval_cnt_reg[1]\ => u_ddr_mc_phy_wrapper_n_668,
      \pi_rdval_cnt_reg[2]\ => u_ddr_mc_phy_wrapper_n_666,
      \pi_rdval_cnt_reg[3]\ => u_ddr_mc_phy_wrapper_n_667,
      \pi_rdval_cnt_reg[4]\ => u_ddr_mc_phy_wrapper_n_671,
      \pi_rdval_cnt_reg[5]\ => u_ddr_mc_phy_wrapper_n_670,
      \pi_rst_stg1_cal_reg[0]\ => u_ddr_calib_top_n_115,
      \pi_rst_stg1_cal_reg[2]\ => u_ddr_calib_top_n_153,
      pi_stg2_load_reg => u_ddr_calib_top_n_116,
      pi_stg2_load_reg_0 => u_ddr_calib_top_n_154,
      \pi_stg2_reg_l_reg[5]\(5) => u_ddr_calib_top_n_129,
      \pi_stg2_reg_l_reg[5]\(4) => u_ddr_calib_top_n_130,
      \pi_stg2_reg_l_reg[5]\(3) => u_ddr_calib_top_n_131,
      \pi_stg2_reg_l_reg[5]\(2) => u_ddr_calib_top_n_132,
      \pi_stg2_reg_l_reg[5]\(1) => u_ddr_calib_top_n_133,
      \pi_stg2_reg_l_reg[5]\(0) => u_ddr_calib_top_n_134,
      \pi_stg2_reg_l_reg[5]_0\(5) => u_ddr_calib_top_n_159,
      \pi_stg2_reg_l_reg[5]_0\(4) => u_ddr_calib_top_n_160,
      \pi_stg2_reg_l_reg[5]_0\(3) => u_ddr_calib_top_n_161,
      \pi_stg2_reg_l_reg[5]_0\(2) => u_ddr_calib_top_n_162,
      \pi_stg2_reg_l_reg[5]_0\(1) => u_ddr_calib_top_n_163,
      \pi_stg2_reg_l_reg[5]_0\(0) => u_ddr_calib_top_n_164,
      pll_locked => pll_locked,
      \po_rdval_cnt_reg[0]\ => u_ddr_mc_phy_wrapper_n_1602,
      \po_rdval_cnt_reg[1]\ => u_ddr_mc_phy_wrapper_n_1603,
      \po_rdval_cnt_reg[2]\ => u_ddr_mc_phy_wrapper_n_1604,
      \po_rdval_cnt_reg[3]\ => u_ddr_mc_phy_wrapper_n_1605,
      \po_rdval_cnt_reg[4]\ => u_ddr_mc_phy_wrapper_n_1606,
      \po_rdval_cnt_reg[5]\ => u_ddr_mc_phy_wrapper_n_1607,
      \po_rdval_cnt_reg[6]\ => u_ddr_mc_phy_wrapper_n_1608,
      \po_rdval_cnt_reg[7]\ => u_ddr_mc_phy_wrapper_n_1609,
      \po_rdval_cnt_reg[8]\ => u_ddr_mc_phy_wrapper_n_1610,
      \po_stg2_wrcal_cnt_reg[2]\(2 downto 0) => po_stg2_wrcal_cnt(2 downto 0),
      ram_init_done_r => ram_init_done_r,
      \rd_mux_sel_r_reg[1]\(1) => u_ddr_calib_top_n_175,
      \rd_mux_sel_r_reg[1]\(0) => u_ddr_calib_top_n_176,
      \rd_mux_sel_r_reg[2]\ => u_ddr_calib_top_n_174,
      \rd_ptr_timing_reg[0]\(44 downto 41) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(75 downto 72),
      \rd_ptr_timing_reg[0]\(40 downto 37) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(67 downto 64),
      \rd_ptr_timing_reg[0]\(36 downto 17) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(59 downto 40),
      \rd_ptr_timing_reg[0]\(16 downto 13) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(35 downto 32),
      \rd_ptr_timing_reg[0]\(12 downto 9) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(27 downto 24),
      \rd_ptr_timing_reg[0]\(8 downto 5) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(19 downto 16),
      \rd_ptr_timing_reg[0]\(4 downto 1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(11 downto 8),
      \rd_ptr_timing_reg[0]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(1),
      \rd_ptr_timing_reg[0]_0\(15 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(43 downto 40),
      \rd_ptr_timing_reg[0]_0\(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(27 downto 24),
      \rd_ptr_timing_reg[0]_0\(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(19 downto 16),
      \rd_ptr_timing_reg[0]_0\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(11 downto 8),
      \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => \read_fifo.tail_r_reg[0]\,
      rst_sync_r1_reg => rst_sync_r1_reg,
      store_sr_req_r_reg => u_ddr_mc_phy_wrapper_n_665,
      sync_pulse => sync_pulse,
      sys_rst => sys_rst,
      sys_rst_0 => sys_rst_0,
      tempmon_pi_f_en_r_reg => u_ddr_calib_top_n_184,
      tempmon_pi_f_en_r_reg_0 => u_ddr_calib_top_n_177,
      tempmon_pi_f_en_r_reg_1 => u_ddr_calib_top_n_178,
      tempmon_pi_f_en_r_reg_2 => u_ddr_calib_top_n_179,
      tempmon_pi_f_en_r_reg_3 => u_ddr_calib_top_n_180,
      tempmon_pi_f_en_r_reg_4 => u_ddr_calib_top_n_181,
      tempmon_pi_f_en_r_reg_5 => u_ddr_calib_top_n_182,
      tempmon_pi_f_en_r_reg_6 => u_ddr_calib_top_n_183,
      tempmon_pi_f_inc_r_reg => u_ddr_calib_top_n_192,
      tempmon_pi_f_inc_r_reg_0 => u_ddr_calib_top_n_185,
      tempmon_pi_f_inc_r_reg_1 => u_ddr_calib_top_n_186,
      tempmon_pi_f_inc_r_reg_2 => u_ddr_calib_top_n_187,
      tempmon_pi_f_inc_r_reg_3 => u_ddr_calib_top_n_188,
      tempmon_pi_f_inc_r_reg_4 => u_ddr_calib_top_n_189,
      tempmon_pi_f_inc_r_reg_5 => u_ddr_calib_top_n_190,
      tempmon_pi_f_inc_r_reg_6 => u_ddr_calib_top_n_191,
      \write_buffer.wr_buf_out_data_reg[383]\(95 downto 0) => \write_buffer.wr_buf_out_data_reg[383]\(95 downto 0),
      \write_buffer.wr_buf_out_data_reg[384]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[388]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[392]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[396]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[400]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[404]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[408]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[412]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[416]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[420]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[424]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[428]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[432]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[436]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[440]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[444]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(6 downto 1),
      \write_buffer.wr_buf_out_data_reg[449]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[449]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(3),
      \write_buffer.wr_buf_out_data_reg[449]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[450]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[450]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(2),
      \write_buffer.wr_buf_out_data_reg[450]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(0),
      \write_buffer.wr_buf_out_data_reg[451]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[451]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[453]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[453]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(3),
      \write_buffer.wr_buf_out_data_reg[453]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[454]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[454]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(2),
      \write_buffer.wr_buf_out_data_reg[454]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(0),
      \write_buffer.wr_buf_out_data_reg[455]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[455]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[457]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[457]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(3),
      \write_buffer.wr_buf_out_data_reg[457]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[458]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[458]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(2),
      \write_buffer.wr_buf_out_data_reg[458]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(0),
      \write_buffer.wr_buf_out_data_reg[459]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[459]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[461]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[461]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(3),
      \write_buffer.wr_buf_out_data_reg[461]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[462]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[462]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(2),
      \write_buffer.wr_buf_out_data_reg[462]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(0),
      \write_buffer.wr_buf_out_data_reg[463]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[463]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[465]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[465]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3),
      \write_buffer.wr_buf_out_data_reg[465]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[466]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[466]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(2),
      \write_buffer.wr_buf_out_data_reg[466]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(0),
      \write_buffer.wr_buf_out_data_reg[467]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[467]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[469]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[469]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3),
      \write_buffer.wr_buf_out_data_reg[469]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[470]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[470]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(2),
      \write_buffer.wr_buf_out_data_reg[470]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(0),
      \write_buffer.wr_buf_out_data_reg[471]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[471]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[473]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[473]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3),
      \write_buffer.wr_buf_out_data_reg[473]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[474]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[474]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(2),
      \write_buffer.wr_buf_out_data_reg[474]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(0),
      \write_buffer.wr_buf_out_data_reg[475]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[475]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[477]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[477]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3),
      \write_buffer.wr_buf_out_data_reg[477]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[478]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[478]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(2),
      \write_buffer.wr_buf_out_data_reg[478]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(0),
      \write_buffer.wr_buf_out_data_reg[479]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[479]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[481]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[481]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3),
      \write_buffer.wr_buf_out_data_reg[481]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[482]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[482]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(2),
      \write_buffer.wr_buf_out_data_reg[482]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(0),
      \write_buffer.wr_buf_out_data_reg[483]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[483]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[485]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[485]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3),
      \write_buffer.wr_buf_out_data_reg[485]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[486]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[486]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(2),
      \write_buffer.wr_buf_out_data_reg[486]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(0),
      \write_buffer.wr_buf_out_data_reg[487]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[487]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[489]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[489]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(3),
      \write_buffer.wr_buf_out_data_reg[489]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[490]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[490]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(2),
      \write_buffer.wr_buf_out_data_reg[490]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(0),
      \write_buffer.wr_buf_out_data_reg[491]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[491]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[493]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[493]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(3),
      \write_buffer.wr_buf_out_data_reg[493]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[494]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[494]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(2),
      \write_buffer.wr_buf_out_data_reg[494]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(0),
      \write_buffer.wr_buf_out_data_reg[495]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[495]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[497]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[497]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3),
      \write_buffer.wr_buf_out_data_reg[497]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[498]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[498]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(2),
      \write_buffer.wr_buf_out_data_reg[498]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(0),
      \write_buffer.wr_buf_out_data_reg[499]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[499]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[501]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[501]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3),
      \write_buffer.wr_buf_out_data_reg[501]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[502]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[502]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(2),
      \write_buffer.wr_buf_out_data_reg[502]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(0),
      \write_buffer.wr_buf_out_data_reg[503]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[503]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[505]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[505]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3),
      \write_buffer.wr_buf_out_data_reg[505]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[506]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[506]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(2),
      \write_buffer.wr_buf_out_data_reg[506]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(0),
      \write_buffer.wr_buf_out_data_reg[507]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[507]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[509]\(5 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[509]\(2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3),
      \write_buffer.wr_buf_out_data_reg[509]\(1 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(1 downto 0),
      \write_buffer.wr_buf_out_data_reg[510]\(4 downto 2) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(7 downto 5),
      \write_buffer.wr_buf_out_data_reg[510]\(1) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(2),
      \write_buffer.wr_buf_out_data_reg[510]\(0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(0),
      \write_buffer.wr_buf_out_data_reg[511]\(4 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(7 downto 6),
      \write_buffer.wr_buf_out_data_reg[511]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0\(4 downto 2),
      \write_buffer.wr_buf_out_data_reg[575]\(223 downto 160) => \write_buffer.wr_buf_out_data_reg[575]\(575 downto 512),
      \write_buffer.wr_buf_out_data_reg[575]\(159) => \write_buffer.wr_buf_out_data_reg[575]\(508),
      \write_buffer.wr_buf_out_data_reg[575]\(158) => \write_buffer.wr_buf_out_data_reg[575]\(504),
      \write_buffer.wr_buf_out_data_reg[575]\(157) => \write_buffer.wr_buf_out_data_reg[575]\(500),
      \write_buffer.wr_buf_out_data_reg[575]\(156) => \write_buffer.wr_buf_out_data_reg[575]\(496),
      \write_buffer.wr_buf_out_data_reg[575]\(155) => \write_buffer.wr_buf_out_data_reg[575]\(492),
      \write_buffer.wr_buf_out_data_reg[575]\(154) => \write_buffer.wr_buf_out_data_reg[575]\(488),
      \write_buffer.wr_buf_out_data_reg[575]\(153) => \write_buffer.wr_buf_out_data_reg[575]\(484),
      \write_buffer.wr_buf_out_data_reg[575]\(152) => \write_buffer.wr_buf_out_data_reg[575]\(480),
      \write_buffer.wr_buf_out_data_reg[575]\(151) => \write_buffer.wr_buf_out_data_reg[575]\(476),
      \write_buffer.wr_buf_out_data_reg[575]\(150) => \write_buffer.wr_buf_out_data_reg[575]\(472),
      \write_buffer.wr_buf_out_data_reg[575]\(149) => \write_buffer.wr_buf_out_data_reg[575]\(468),
      \write_buffer.wr_buf_out_data_reg[575]\(148) => \write_buffer.wr_buf_out_data_reg[575]\(464),
      \write_buffer.wr_buf_out_data_reg[575]\(147) => \write_buffer.wr_buf_out_data_reg[575]\(460),
      \write_buffer.wr_buf_out_data_reg[575]\(146) => \write_buffer.wr_buf_out_data_reg[575]\(456),
      \write_buffer.wr_buf_out_data_reg[575]\(145) => \write_buffer.wr_buf_out_data_reg[575]\(452),
      \write_buffer.wr_buf_out_data_reg[575]\(144) => \write_buffer.wr_buf_out_data_reg[575]\(448),
      \write_buffer.wr_buf_out_data_reg[575]\(143) => \write_buffer.wr_buf_out_data_reg[575]\(383),
      \write_buffer.wr_buf_out_data_reg[575]\(142) => \write_buffer.wr_buf_out_data_reg[575]\(379),
      \write_buffer.wr_buf_out_data_reg[575]\(141) => \write_buffer.wr_buf_out_data_reg[575]\(375),
      \write_buffer.wr_buf_out_data_reg[575]\(140) => \write_buffer.wr_buf_out_data_reg[575]\(371),
      \write_buffer.wr_buf_out_data_reg[575]\(139) => \write_buffer.wr_buf_out_data_reg[575]\(367),
      \write_buffer.wr_buf_out_data_reg[575]\(138) => \write_buffer.wr_buf_out_data_reg[575]\(363),
      \write_buffer.wr_buf_out_data_reg[575]\(137) => \write_buffer.wr_buf_out_data_reg[575]\(359),
      \write_buffer.wr_buf_out_data_reg[575]\(136) => \write_buffer.wr_buf_out_data_reg[575]\(355),
      \write_buffer.wr_buf_out_data_reg[575]\(135) => \write_buffer.wr_buf_out_data_reg[575]\(351),
      \write_buffer.wr_buf_out_data_reg[575]\(134) => \write_buffer.wr_buf_out_data_reg[575]\(347),
      \write_buffer.wr_buf_out_data_reg[575]\(133) => \write_buffer.wr_buf_out_data_reg[575]\(343),
      \write_buffer.wr_buf_out_data_reg[575]\(132) => \write_buffer.wr_buf_out_data_reg[575]\(339),
      \write_buffer.wr_buf_out_data_reg[575]\(131) => \write_buffer.wr_buf_out_data_reg[575]\(335),
      \write_buffer.wr_buf_out_data_reg[575]\(130) => \write_buffer.wr_buf_out_data_reg[575]\(331),
      \write_buffer.wr_buf_out_data_reg[575]\(129) => \write_buffer.wr_buf_out_data_reg[575]\(327),
      \write_buffer.wr_buf_out_data_reg[575]\(128) => \write_buffer.wr_buf_out_data_reg[575]\(323),
      \write_buffer.wr_buf_out_data_reg[575]\(127 downto 126) => \write_buffer.wr_buf_out_data_reg[575]\(318 downto 317),
      \write_buffer.wr_buf_out_data_reg[575]\(125 downto 124) => \write_buffer.wr_buf_out_data_reg[575]\(314 downto 313),
      \write_buffer.wr_buf_out_data_reg[575]\(123 downto 122) => \write_buffer.wr_buf_out_data_reg[575]\(310 downto 309),
      \write_buffer.wr_buf_out_data_reg[575]\(121 downto 120) => \write_buffer.wr_buf_out_data_reg[575]\(306 downto 305),
      \write_buffer.wr_buf_out_data_reg[575]\(119 downto 118) => \write_buffer.wr_buf_out_data_reg[575]\(302 downto 301),
      \write_buffer.wr_buf_out_data_reg[575]\(117 downto 116) => \write_buffer.wr_buf_out_data_reg[575]\(298 downto 297),
      \write_buffer.wr_buf_out_data_reg[575]\(115 downto 114) => \write_buffer.wr_buf_out_data_reg[575]\(294 downto 293),
      \write_buffer.wr_buf_out_data_reg[575]\(113 downto 112) => \write_buffer.wr_buf_out_data_reg[575]\(290 downto 289),
      \write_buffer.wr_buf_out_data_reg[575]\(111 downto 110) => \write_buffer.wr_buf_out_data_reg[575]\(286 downto 285),
      \write_buffer.wr_buf_out_data_reg[575]\(109 downto 108) => \write_buffer.wr_buf_out_data_reg[575]\(282 downto 281),
      \write_buffer.wr_buf_out_data_reg[575]\(107 downto 106) => \write_buffer.wr_buf_out_data_reg[575]\(278 downto 277),
      \write_buffer.wr_buf_out_data_reg[575]\(105 downto 104) => \write_buffer.wr_buf_out_data_reg[575]\(274 downto 273),
      \write_buffer.wr_buf_out_data_reg[575]\(103 downto 102) => \write_buffer.wr_buf_out_data_reg[575]\(270 downto 269),
      \write_buffer.wr_buf_out_data_reg[575]\(101 downto 100) => \write_buffer.wr_buf_out_data_reg[575]\(266 downto 265),
      \write_buffer.wr_buf_out_data_reg[575]\(99 downto 98) => \write_buffer.wr_buf_out_data_reg[575]\(262 downto 261),
      \write_buffer.wr_buf_out_data_reg[575]\(97 downto 96) => \write_buffer.wr_buf_out_data_reg[575]\(258 downto 257),
      \write_buffer.wr_buf_out_data_reg[575]\(95) => \write_buffer.wr_buf_out_data_reg[575]\(254),
      \write_buffer.wr_buf_out_data_reg[575]\(94) => \write_buffer.wr_buf_out_data_reg[575]\(250),
      \write_buffer.wr_buf_out_data_reg[575]\(93) => \write_buffer.wr_buf_out_data_reg[575]\(246),
      \write_buffer.wr_buf_out_data_reg[575]\(92) => \write_buffer.wr_buf_out_data_reg[575]\(242),
      \write_buffer.wr_buf_out_data_reg[575]\(91) => \write_buffer.wr_buf_out_data_reg[575]\(238),
      \write_buffer.wr_buf_out_data_reg[575]\(90) => \write_buffer.wr_buf_out_data_reg[575]\(234),
      \write_buffer.wr_buf_out_data_reg[575]\(89) => \write_buffer.wr_buf_out_data_reg[575]\(230),
      \write_buffer.wr_buf_out_data_reg[575]\(88) => \write_buffer.wr_buf_out_data_reg[575]\(226),
      \write_buffer.wr_buf_out_data_reg[575]\(87) => \write_buffer.wr_buf_out_data_reg[575]\(222),
      \write_buffer.wr_buf_out_data_reg[575]\(86) => \write_buffer.wr_buf_out_data_reg[575]\(218),
      \write_buffer.wr_buf_out_data_reg[575]\(85) => \write_buffer.wr_buf_out_data_reg[575]\(214),
      \write_buffer.wr_buf_out_data_reg[575]\(84) => \write_buffer.wr_buf_out_data_reg[575]\(210),
      \write_buffer.wr_buf_out_data_reg[575]\(83) => \write_buffer.wr_buf_out_data_reg[575]\(206),
      \write_buffer.wr_buf_out_data_reg[575]\(82) => \write_buffer.wr_buf_out_data_reg[575]\(202),
      \write_buffer.wr_buf_out_data_reg[575]\(81) => \write_buffer.wr_buf_out_data_reg[575]\(198),
      \write_buffer.wr_buf_out_data_reg[575]\(80) => \write_buffer.wr_buf_out_data_reg[575]\(194),
      \write_buffer.wr_buf_out_data_reg[575]\(79) => \write_buffer.wr_buf_out_data_reg[575]\(189),
      \write_buffer.wr_buf_out_data_reg[575]\(78) => \write_buffer.wr_buf_out_data_reg[575]\(185),
      \write_buffer.wr_buf_out_data_reg[575]\(77) => \write_buffer.wr_buf_out_data_reg[575]\(181),
      \write_buffer.wr_buf_out_data_reg[575]\(76) => \write_buffer.wr_buf_out_data_reg[575]\(177),
      \write_buffer.wr_buf_out_data_reg[575]\(75) => \write_buffer.wr_buf_out_data_reg[575]\(173),
      \write_buffer.wr_buf_out_data_reg[575]\(74) => \write_buffer.wr_buf_out_data_reg[575]\(169),
      \write_buffer.wr_buf_out_data_reg[575]\(73) => \write_buffer.wr_buf_out_data_reg[575]\(165),
      \write_buffer.wr_buf_out_data_reg[575]\(72) => \write_buffer.wr_buf_out_data_reg[575]\(161),
      \write_buffer.wr_buf_out_data_reg[575]\(71) => \write_buffer.wr_buf_out_data_reg[575]\(157),
      \write_buffer.wr_buf_out_data_reg[575]\(70) => \write_buffer.wr_buf_out_data_reg[575]\(153),
      \write_buffer.wr_buf_out_data_reg[575]\(69) => \write_buffer.wr_buf_out_data_reg[575]\(149),
      \write_buffer.wr_buf_out_data_reg[575]\(68) => \write_buffer.wr_buf_out_data_reg[575]\(145),
      \write_buffer.wr_buf_out_data_reg[575]\(67) => \write_buffer.wr_buf_out_data_reg[575]\(141),
      \write_buffer.wr_buf_out_data_reg[575]\(66) => \write_buffer.wr_buf_out_data_reg[575]\(137),
      \write_buffer.wr_buf_out_data_reg[575]\(65) => \write_buffer.wr_buf_out_data_reg[575]\(133),
      \write_buffer.wr_buf_out_data_reg[575]\(64) => \write_buffer.wr_buf_out_data_reg[575]\(129),
      \write_buffer.wr_buf_out_data_reg[575]\(63 downto 62) => \write_buffer.wr_buf_out_data_reg[575]\(127 downto 126),
      \write_buffer.wr_buf_out_data_reg[575]\(61 downto 60) => \write_buffer.wr_buf_out_data_reg[575]\(123 downto 122),
      \write_buffer.wr_buf_out_data_reg[575]\(59 downto 58) => \write_buffer.wr_buf_out_data_reg[575]\(119 downto 118),
      \write_buffer.wr_buf_out_data_reg[575]\(57 downto 56) => \write_buffer.wr_buf_out_data_reg[575]\(115 downto 114),
      \write_buffer.wr_buf_out_data_reg[575]\(55 downto 54) => \write_buffer.wr_buf_out_data_reg[575]\(111 downto 110),
      \write_buffer.wr_buf_out_data_reg[575]\(53 downto 52) => \write_buffer.wr_buf_out_data_reg[575]\(107 downto 106),
      \write_buffer.wr_buf_out_data_reg[575]\(51 downto 50) => \write_buffer.wr_buf_out_data_reg[575]\(103 downto 102),
      \write_buffer.wr_buf_out_data_reg[575]\(49 downto 48) => \write_buffer.wr_buf_out_data_reg[575]\(99 downto 98),
      \write_buffer.wr_buf_out_data_reg[575]\(47 downto 46) => \write_buffer.wr_buf_out_data_reg[575]\(95 downto 94),
      \write_buffer.wr_buf_out_data_reg[575]\(45 downto 44) => \write_buffer.wr_buf_out_data_reg[575]\(91 downto 90),
      \write_buffer.wr_buf_out_data_reg[575]\(43 downto 42) => \write_buffer.wr_buf_out_data_reg[575]\(87 downto 86),
      \write_buffer.wr_buf_out_data_reg[575]\(41 downto 40) => \write_buffer.wr_buf_out_data_reg[575]\(83 downto 82),
      \write_buffer.wr_buf_out_data_reg[575]\(39 downto 38) => \write_buffer.wr_buf_out_data_reg[575]\(79 downto 78),
      \write_buffer.wr_buf_out_data_reg[575]\(37 downto 36) => \write_buffer.wr_buf_out_data_reg[575]\(75 downto 74),
      \write_buffer.wr_buf_out_data_reg[575]\(35 downto 34) => \write_buffer.wr_buf_out_data_reg[575]\(71 downto 70),
      \write_buffer.wr_buf_out_data_reg[575]\(33 downto 32) => \write_buffer.wr_buf_out_data_reg[575]\(67 downto 66),
      \write_buffer.wr_buf_out_data_reg[575]\(31) => \write_buffer.wr_buf_out_data_reg[575]\(63),
      \write_buffer.wr_buf_out_data_reg[575]\(30 downto 29) => \write_buffer.wr_buf_out_data_reg[575]\(60 downto 59),
      \write_buffer.wr_buf_out_data_reg[575]\(28 downto 27) => \write_buffer.wr_buf_out_data_reg[575]\(56 downto 55),
      \write_buffer.wr_buf_out_data_reg[575]\(26 downto 25) => \write_buffer.wr_buf_out_data_reg[575]\(52 downto 51),
      \write_buffer.wr_buf_out_data_reg[575]\(24 downto 23) => \write_buffer.wr_buf_out_data_reg[575]\(48 downto 47),
      \write_buffer.wr_buf_out_data_reg[575]\(22 downto 21) => \write_buffer.wr_buf_out_data_reg[575]\(44 downto 43),
      \write_buffer.wr_buf_out_data_reg[575]\(20 downto 19) => \write_buffer.wr_buf_out_data_reg[575]\(40 downto 39),
      \write_buffer.wr_buf_out_data_reg[575]\(18 downto 17) => \write_buffer.wr_buf_out_data_reg[575]\(36 downto 35),
      \write_buffer.wr_buf_out_data_reg[575]\(16 downto 15) => \write_buffer.wr_buf_out_data_reg[575]\(32 downto 31),
      \write_buffer.wr_buf_out_data_reg[575]\(14 downto 13) => \write_buffer.wr_buf_out_data_reg[575]\(28 downto 27),
      \write_buffer.wr_buf_out_data_reg[575]\(12 downto 11) => \write_buffer.wr_buf_out_data_reg[575]\(24 downto 23),
      \write_buffer.wr_buf_out_data_reg[575]\(10 downto 9) => \write_buffer.wr_buf_out_data_reg[575]\(20 downto 19),
      \write_buffer.wr_buf_out_data_reg[575]\(8 downto 7) => \write_buffer.wr_buf_out_data_reg[575]\(16 downto 15),
      \write_buffer.wr_buf_out_data_reg[575]\(6 downto 5) => \write_buffer.wr_buf_out_data_reg[575]\(12 downto 11),
      \write_buffer.wr_buf_out_data_reg[575]\(4 downto 3) => \write_buffer.wr_buf_out_data_reg[575]\(8 downto 7),
      \write_buffer.wr_buf_out_data_reg[575]\(2 downto 1) => \write_buffer.wr_buf_out_data_reg[575]\(4 downto 3),
      \write_buffer.wr_buf_out_data_reg[575]\(0) => \write_buffer.wr_buf_out_data_reg[575]\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_mem_intfc is
  port (
    accept_ns : out STD_LOGIC;
    ras_timer_zero_r_reg : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    ras_timer_zero_r_reg_0 : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_sr_active : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dqs_po_en_stg2_f_reg : out STD_LOGIC;
    \complex_row1_rd_cnt_reg[1]\ : out STD_LOGIC;
    rdlvl_stg1_start_r_reg : out STD_LOGIC;
    idelay_tap_limit_r_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    fine_dly_dec_done_r1_reg : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    \my_empty_reg[7]\ : out STD_LOGIC;
    \my_empty_reg[7]_0\ : out STD_LOGIC;
    \my_empty_reg[7]_1\ : out STD_LOGIC;
    \my_empty_reg[7]_2\ : out STD_LOGIC;
    \my_empty_reg[7]_3\ : out STD_LOGIC;
    \my_empty_reg[7]_4\ : out STD_LOGIC;
    \my_empty_reg[7]_5\ : out STD_LOGIC;
    \my_empty_reg[7]_6\ : out STD_LOGIC;
    \my_empty_reg[7]_7\ : out STD_LOGIC;
    \not_strict_mode.bypass__0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \not_strict_mode.rd_buf_we\ : out STD_LOGIC;
    rst_sync_r1_reg : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[8]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[16]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[56]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[0]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[40]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[48]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[24]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[32]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[9]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[17]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[57]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[1]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[41]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[49]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[25]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[33]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[42]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[50]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[26]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[34]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[10]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[18]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[58]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[2]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[43]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[51]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[27]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[35]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[11]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[19]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[59]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[3]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[44]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[52]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[28]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[36]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[12]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[20]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[60]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[4]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[45]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[53]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[29]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[37]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[13]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[21]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[61]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[5]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[46]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[54]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[30]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[38]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[14]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[22]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[62]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[6]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[47]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[55]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[31]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[39]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[15]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[23]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[63]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[7]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[104]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[112]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[88]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[96]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[72]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[80]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[120]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[64]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[105]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[113]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[89]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[97]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[73]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[81]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[121]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[65]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[106]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[114]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[90]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[98]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[74]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[82]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[122]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[66]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[75]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[83]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[123]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[67]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[107]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[115]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[91]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[99]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[108]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[116]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[92]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[100]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[76]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[84]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[124]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[68]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[109]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[117]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[93]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[101]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[77]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[85]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[125]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[69]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[110]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[118]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[94]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[102]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[78]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[86]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[126]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[70]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[111]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[119]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[95]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[103]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[79]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[87]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[127]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[71]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[168]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[176]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[152]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[160]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[136]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[144]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[184]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[128]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[169]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[177]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[153]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[161]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[137]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[145]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[185]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[129]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[170]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[178]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[154]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[162]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[138]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[146]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[186]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[130]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[171]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[179]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[155]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[163]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[139]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[147]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[187]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[131]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[172]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[180]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[156]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[164]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[140]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[148]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[188]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[132]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[141]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[149]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[189]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[133]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[173]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[181]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[157]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[165]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[142]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[150]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[190]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[134]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[174]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[182]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[158]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[166]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[143]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[151]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[191]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[135]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[175]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[183]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[159]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[167]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[232]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[240]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[216]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[224]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[200]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[208]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[248]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[192]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[233]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[241]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[217]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[225]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[201]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[209]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[249]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[193]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[234]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[242]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[218]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[226]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[202]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[210]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[250]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[194]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[203]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[211]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[251]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[195]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[235]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[243]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[219]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[227]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[236]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[244]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[220]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[228]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[204]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[212]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[252]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[196]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[237]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[245]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[221]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[229]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[205]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[213]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[253]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[197]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[238]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[246]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[222]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[230]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[206]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[214]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[254]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[198]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[207]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[215]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[255]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[199]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[239]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[247]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[223]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[231]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[296]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[304]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[280]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[288]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[264]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[272]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[312]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[256]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[265]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[273]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[313]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[257]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[297]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[305]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[281]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[289]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[298]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[306]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[282]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[290]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[266]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[274]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[314]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[258]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[299]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[307]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[283]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[291]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[267]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[275]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[315]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[259]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[300]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[308]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[284]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[292]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[268]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[276]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[316]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[260]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[301]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[309]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[285]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[293]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[269]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[277]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[317]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[261]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[270]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[278]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[318]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[262]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[302]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[310]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[286]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[294]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[303]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[311]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[287]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[295]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[271]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[279]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[319]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[263]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[360]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[368]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[344]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[352]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[328]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[336]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[376]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[320]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[361]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[369]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[345]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[353]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[329]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[337]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[377]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[321]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[362]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[370]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[346]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[354]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[330]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[338]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[378]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[322]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[331]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[339]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[379]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[323]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[363]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[371]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[347]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[355]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[364]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[372]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[348]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[356]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[332]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[340]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[380]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[324]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[333]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[341]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[381]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[325]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[365]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[373]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[349]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[357]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[366]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[374]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[350]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[358]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[334]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[342]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[382]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[326]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[335]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[343]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[383]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[327]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[367]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[375]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[351]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[359]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[392]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[400]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[440]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[384]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[424]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[432]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[408]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[416]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[393]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[401]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[441]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[385]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[425]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[433]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[409]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[417]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[426]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[434]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[410]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[418]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[394]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[402]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[442]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[386]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[427]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[435]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[411]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[419]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[395]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[403]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[443]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[387]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[428]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[436]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[412]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[420]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[396]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[404]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[444]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[388]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[429]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[437]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[413]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[421]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[397]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[405]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[445]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[389]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[430]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[438]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[414]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[422]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[398]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[406]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[446]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[390]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[431]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[439]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[415]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[423]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[399]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[407]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[447]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[391]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[488]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[496]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[472]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[480]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[456]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[464]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[504]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[448]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[489]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[497]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[473]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[481]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[457]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[465]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[505]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[449]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[458]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[466]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[506]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[450]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[490]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[498]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[474]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[482]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[491]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[499]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[475]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[483]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[459]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[467]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[507]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[451]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[492]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[500]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[476]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[484]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[460]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[468]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[508]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[452]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[493]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[501]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[477]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[485]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[461]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[469]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[509]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[453]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[494]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[502]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[478]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[486]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[462]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[470]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[510]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[454]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[463]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[471]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[455]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[495]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[503]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[479]\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[487]\ : out STD_LOGIC;
    \cmd_pipe_plus.mc_bank_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cmd_pipe_plus.mc_address_reg[41]\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ : out STD_LOGIC;
    \pointer_ram.pointer_we\ : out STD_LOGIC;
    \not_strict_mode.app_rd_data_reg[511]_0\ : out STD_LOGIC_VECTOR ( 511 downto 0 );
    \not_strict_mode.app_rd_data_end_ns\ : out STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    CLK : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 1 downto 0 );
    in0 : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    use_addr : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_sr_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    RST0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \req_row_r_lcl_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \app_addr_r1_reg[23]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__4\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__5\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__15\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__17\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__22\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[0]\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[2]\ : in STD_LOGIC;
    \req_bank_r_lcl_reg[0]_0\ : in STD_LOGIC;
    ram_init_addr : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ram_init_done_r : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_rst_0 : in STD_LOGIC;
    \write_buffer.wr_buf_out_data_reg[575]_0\ : in STD_LOGIC_VECTOR ( 575 downto 0 );
    bm_end_r1_reg : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \app_addr_r1_reg[26]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \write_buffer.wr_buf_out_data_reg[383]\ : in STD_LOGIC_VECTOR ( 95 downto 0 );
    DOC : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOB : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DOA : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rd_buf_indx.rd_buf_indx_r_reg[4]\ : in STD_LOGIC;
    app_rdy_r_reg : in STD_LOGIC;
    \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \app_addr_r1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rstdiv0_sync_r1_reg_rep__10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_rdlvl_done_pulse_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__22_0\ : in STD_LOGIC;
    new_cnt_cpt_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_start_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    clear : in STD_LOGIC;
    pi_cnt_dec_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \device_temp_r_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_mem_intfc : entity is "mig_7series_v2_3_mem_intfc";
end mig_7series_0_mig_7series_v2_3_mem_intfc;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_mem_intfc is
  signal \col_mach0/p_0_in\ : STD_LOGIC;
  signal ddr_phy_top0_n_47 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of ddr_phy_top0_n_47 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_47 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of ddr_phy_top0_n_47 : signal is "10";
  signal ddr_phy_top0_n_57 : STD_LOGIC;
  attribute MAX_FANOUT of ddr_phy_top0_n_57 : signal is "50";
  attribute RTL_MAX_FANOUT of ddr_phy_top0_n_57 : signal is "found";
  attribute syn_maxfan of ddr_phy_top0_n_57 : signal is "10";
  signal ddr_phy_top0_n_576 : STD_LOGIC;
  signal ddr_phy_top0_n_577 : STD_LOGIC;
  signal ddr_phy_top0_n_578 : STD_LOGIC;
  signal ddr_phy_top0_n_579 : STD_LOGIC;
  signal ddr_phy_top0_n_580 : STD_LOGIC;
  signal ddr_phy_top0_n_581 : STD_LOGIC;
  signal ddr_phy_top0_n_583 : STD_LOGIC;
  signal ddr_phy_top0_n_584 : STD_LOGIC;
  signal ddr_phy_top0_n_585 : STD_LOGIC;
  signal ddr_phy_top0_n_586 : STD_LOGIC;
  signal ddr_phy_top0_n_587 : STD_LOGIC;
  signal ddr_phy_top0_n_588 : STD_LOGIC;
  signal ddr_phy_top0_n_590 : STD_LOGIC;
  signal ddr_phy_top0_n_591 : STD_LOGIC;
  signal ddr_phy_top0_n_592 : STD_LOGIC;
  signal ddr_phy_top0_n_593 : STD_LOGIC;
  signal ddr_phy_top0_n_594 : STD_LOGIC;
  signal ddr_phy_top0_n_595 : STD_LOGIC;
  signal ddr_phy_top0_n_596 : STD_LOGIC;
  signal ddr_phy_top0_n_597 : STD_LOGIC;
  signal ddr_phy_top0_n_598 : STD_LOGIC;
  signal ddr_phy_top0_n_599 : STD_LOGIC;
  signal ddr_phy_top0_n_60 : STD_LOGIC;
  signal ddr_phy_top0_n_600 : STD_LOGIC;
  signal ddr_phy_top0_n_601 : STD_LOGIC;
  signal ddr_phy_top0_n_602 : STD_LOGIC;
  signal ddr_phy_top0_n_603 : STD_LOGIC;
  signal ddr_phy_top0_n_604 : STD_LOGIC;
  signal ddr_phy_top0_n_605 : STD_LOGIC;
  signal idle : STD_LOGIC;
  signal mc0_n_120 : STD_LOGIC;
  signal mc0_n_121 : STD_LOGIC;
  signal mc0_n_122 : STD_LOGIC;
  signal mc0_n_123 : STD_LOGIC;
  signal mc0_n_124 : STD_LOGIC;
  signal mc0_n_125 : STD_LOGIC;
  signal mc0_n_126 : STD_LOGIC;
  signal mc0_n_127 : STD_LOGIC;
  signal mc0_n_128 : STD_LOGIC;
  signal mc0_n_129 : STD_LOGIC;
  signal mc0_n_130 : STD_LOGIC;
  signal mc0_n_131 : STD_LOGIC;
  signal mc0_n_132 : STD_LOGIC;
  signal mc0_n_133 : STD_LOGIC;
  signal mc0_n_134 : STD_LOGIC;
  signal mc0_n_135 : STD_LOGIC;
  signal mc0_n_136 : STD_LOGIC;
  signal mc0_n_137 : STD_LOGIC;
  signal mc0_n_24 : STD_LOGIC;
  signal mc0_n_35 : STD_LOGIC;
  signal mc_address : STD_LOGIC_VECTOR ( 41 downto 0 );
  signal mc_bank : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal mc_cas_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_cke : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_cmd : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal mc_cs_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_data_offset_1_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_data_offset_2_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_data_offset_ns : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mc_odt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mc_ras_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_we_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mc_wrdata_en : STD_LOGIC;
  signal mux_cas_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mux_cs_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal mux_ras_n : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mux_we_n : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal phy_mc_ctl_full : STD_LOGIC;
  signal phy_mc_data_full : STD_LOGIC;
  signal \rank_mach0/rank_common0/maint_prescaler.maint_prescaler_r1\ : STD_LOGIC;
  signal \read_fifo.tail_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal sent_col : STD_LOGIC;
  signal tempmon_sample_en : STD_LOGIC;
  signal \u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v\ : STD_LOGIC_VECTOR ( 1 to 1 );
begin
ddr_phy_top0: entity work.mig_7series_0_mig_7series_v2_3_ddr_phy_top
     port map (
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      D(0) => mc_data_offset_2_ns(3),
      DOA(1 downto 0) => DOA(1 downto 0),
      DOB(1 downto 0) => DOB(1 downto 0),
      DOC(1 downto 0) => DOC(1 downto 0),
      Q(0) => \col_mach0/p_0_in\,
      RST0 => RST0,
      SR(1 downto 0) => SR(1 downto 0),
      SS(0) => SS(0),
      app_zq_r_reg => ddr_phy_top0_n_47,
      clear => clear,
      \cmd_pipe_plus.mc_data_offset_1_reg[0]\ => ddr_phy_top0_n_604,
      \cmd_pipe_plus.mc_data_offset_1_reg[0]_0\ => mc0_n_131,
      \cmd_pipe_plus.mc_data_offset_1_reg[1]\ => ddr_phy_top0_n_600,
      \cmd_pipe_plus.mc_data_offset_1_reg[1]_0\ => mc0_n_130,
      \cmd_pipe_plus.mc_data_offset_1_reg[2]\ => mc0_n_129,
      \cmd_pipe_plus.mc_data_offset_1_reg[3]\(0) => mc_data_offset_1_ns(3),
      \cmd_pipe_plus.mc_data_offset_1_reg[3]_0\(0) => mc0_n_126,
      \cmd_pipe_plus.mc_data_offset_1_reg[4]\ => ddr_phy_top0_n_599,
      \cmd_pipe_plus.mc_data_offset_1_reg[4]_0\ => mc0_n_128,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(5) => ddr_phy_top0_n_583,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(4) => ddr_phy_top0_n_584,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(3) => ddr_phy_top0_n_585,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(2) => ddr_phy_top0_n_586,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(1) => ddr_phy_top0_n_587,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]\(0) => ddr_phy_top0_n_588,
      \cmd_pipe_plus.mc_data_offset_1_reg[5]_0\ => mc0_n_127,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]\ => ddr_phy_top0_n_605,
      \cmd_pipe_plus.mc_data_offset_2_reg[0]_0\ => mc0_n_137,
      \cmd_pipe_plus.mc_data_offset_2_reg[1]\ => ddr_phy_top0_n_602,
      \cmd_pipe_plus.mc_data_offset_2_reg[1]_0\ => mc0_n_136,
      \cmd_pipe_plus.mc_data_offset_2_reg[2]\ => mc0_n_135,
      \cmd_pipe_plus.mc_data_offset_2_reg[3]\(0) => mc0_n_132,
      \cmd_pipe_plus.mc_data_offset_2_reg[4]\ => ddr_phy_top0_n_601,
      \cmd_pipe_plus.mc_data_offset_2_reg[4]_0\ => mc0_n_134,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(5) => ddr_phy_top0_n_576,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(4) => ddr_phy_top0_n_577,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(3) => ddr_phy_top0_n_578,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(2) => ddr_phy_top0_n_579,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(1) => ddr_phy_top0_n_580,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]\(0) => ddr_phy_top0_n_581,
      \cmd_pipe_plus.mc_data_offset_2_reg[5]_0\ => mc0_n_133,
      \cmd_pipe_plus.mc_data_offset_reg[0]\ => ddr_phy_top0_n_603,
      \cmd_pipe_plus.mc_data_offset_reg[0]_0\ => mc0_n_125,
      \cmd_pipe_plus.mc_data_offset_reg[1]\ => ddr_phy_top0_n_598,
      \cmd_pipe_plus.mc_data_offset_reg[1]_0\ => mc0_n_124,
      \cmd_pipe_plus.mc_data_offset_reg[2]\ => mc0_n_123,
      \cmd_pipe_plus.mc_data_offset_reg[3]\(0) => mc_data_offset_ns(3),
      \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0) => mc0_n_120,
      \cmd_pipe_plus.mc_data_offset_reg[4]\ => ddr_phy_top0_n_597,
      \cmd_pipe_plus.mc_data_offset_reg[4]_0\ => mc0_n_122,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(5) => ddr_phy_top0_n_590,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(4) => ddr_phy_top0_n_591,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(3) => ddr_phy_top0_n_592,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(2) => ddr_phy_top0_n_593,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(1) => ddr_phy_top0_n_594,
      \cmd_pipe_plus.mc_data_offset_reg[5]\(0) => ddr_phy_top0_n_595,
      \cmd_pipe_plus.mc_data_offset_reg[5]_0\ => mc0_n_121,
      \cmd_pipe_plus.mc_ras_n_reg[0]\(0) => mux_ras_n(0),
      \cmd_pipe_plus.mc_we_n_reg[2]\(2 downto 0) => mc_we_n(2 downto 0),
      \complex_row1_rd_cnt_reg[1]\ => \complex_row1_rd_cnt_reg[1]\,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \device_temp_r_reg[11]\(11 downto 0) => \device_temp_r_reg[11]\(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\,
      dqs_po_en_stg2_f_reg => dqs_po_en_stg2_f_reg,
      \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[3]\,
      fine_dly_dec_done_r1_reg => fine_dly_dec_done_r1_reg,
      freq_refclk => freq_refclk,
      \grant_r_reg[3]\ => mc0_n_24,
      idelay_tap_limit_r_reg => idelay_tap_limit_r_reg,
      idle => idle,
      in0 => in0,
      init_calib_complete => init_calib_complete,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      \maint_prescaler.maint_prescaler_r1\ => \rank_mach0/rank_common0/maint_prescaler.maint_prescaler_r1\,
      mc_address(38 downto 25) => mc_address(41 downto 28),
      mc_address(24 downto 0) => mc_address(24 downto 0),
      mc_bank(8 downto 0) => mc_bank(8 downto 0),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cke(0) => mc_cke(3),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0),
      mc_wrdata_en => mc_wrdata_en,
      mem_refclk => mem_refclk,
      \my_empty_reg[7]\ => \my_empty_reg[7]\,
      \my_empty_reg[7]_0\ => \my_empty_reg[7]_0\,
      \my_empty_reg[7]_1\ => \my_empty_reg[7]_1\,
      \my_empty_reg[7]_2\ => \my_empty_reg[7]_2\,
      \my_empty_reg[7]_3\ => \my_empty_reg[7]_3\,
      \my_empty_reg[7]_4\ => \my_empty_reg[7]_4\,
      \my_empty_reg[7]_5\ => \my_empty_reg[7]_5\,
      \my_empty_reg[7]_6\ => \my_empty_reg[7]_6\,
      \my_empty_reg[7]_7\ => \my_empty_reg[7]_7\,
      new_cnt_cpt_r_reg(0) => new_cnt_cpt_r_reg(0),
      \not_strict_mode.app_rd_data_reg[0]\ => \not_strict_mode.app_rd_data_reg[0]\,
      \not_strict_mode.app_rd_data_reg[100]\ => \not_strict_mode.app_rd_data_reg[100]\,
      \not_strict_mode.app_rd_data_reg[101]\ => \not_strict_mode.app_rd_data_reg[101]\,
      \not_strict_mode.app_rd_data_reg[102]\ => \not_strict_mode.app_rd_data_reg[102]\,
      \not_strict_mode.app_rd_data_reg[103]\ => \not_strict_mode.app_rd_data_reg[103]\,
      \not_strict_mode.app_rd_data_reg[104]\ => \not_strict_mode.app_rd_data_reg[104]\,
      \not_strict_mode.app_rd_data_reg[105]\ => \not_strict_mode.app_rd_data_reg[105]\,
      \not_strict_mode.app_rd_data_reg[106]\ => \not_strict_mode.app_rd_data_reg[106]\,
      \not_strict_mode.app_rd_data_reg[107]\ => \not_strict_mode.app_rd_data_reg[107]\,
      \not_strict_mode.app_rd_data_reg[108]\ => \not_strict_mode.app_rd_data_reg[108]\,
      \not_strict_mode.app_rd_data_reg[109]\ => \not_strict_mode.app_rd_data_reg[109]\,
      \not_strict_mode.app_rd_data_reg[10]\ => \not_strict_mode.app_rd_data_reg[10]\,
      \not_strict_mode.app_rd_data_reg[110]\ => \not_strict_mode.app_rd_data_reg[110]\,
      \not_strict_mode.app_rd_data_reg[111]\ => \not_strict_mode.app_rd_data_reg[111]\,
      \not_strict_mode.app_rd_data_reg[112]\ => \not_strict_mode.app_rd_data_reg[112]\,
      \not_strict_mode.app_rd_data_reg[113]\ => \not_strict_mode.app_rd_data_reg[113]\,
      \not_strict_mode.app_rd_data_reg[114]\ => \not_strict_mode.app_rd_data_reg[114]\,
      \not_strict_mode.app_rd_data_reg[115]\ => \not_strict_mode.app_rd_data_reg[115]\,
      \not_strict_mode.app_rd_data_reg[116]\ => \not_strict_mode.app_rd_data_reg[116]\,
      \not_strict_mode.app_rd_data_reg[117]\ => \not_strict_mode.app_rd_data_reg[117]\,
      \not_strict_mode.app_rd_data_reg[118]\ => \not_strict_mode.app_rd_data_reg[118]\,
      \not_strict_mode.app_rd_data_reg[119]\ => \not_strict_mode.app_rd_data_reg[119]\,
      \not_strict_mode.app_rd_data_reg[11]\ => \not_strict_mode.app_rd_data_reg[11]\,
      \not_strict_mode.app_rd_data_reg[120]\ => \not_strict_mode.app_rd_data_reg[120]\,
      \not_strict_mode.app_rd_data_reg[121]\ => \not_strict_mode.app_rd_data_reg[121]\,
      \not_strict_mode.app_rd_data_reg[122]\ => \not_strict_mode.app_rd_data_reg[122]\,
      \not_strict_mode.app_rd_data_reg[123]\ => \not_strict_mode.app_rd_data_reg[123]\,
      \not_strict_mode.app_rd_data_reg[124]\ => \not_strict_mode.app_rd_data_reg[124]\,
      \not_strict_mode.app_rd_data_reg[125]\ => \not_strict_mode.app_rd_data_reg[125]\,
      \not_strict_mode.app_rd_data_reg[126]\ => \not_strict_mode.app_rd_data_reg[126]\,
      \not_strict_mode.app_rd_data_reg[127]\ => \not_strict_mode.app_rd_data_reg[127]\,
      \not_strict_mode.app_rd_data_reg[128]\ => \not_strict_mode.app_rd_data_reg[128]\,
      \not_strict_mode.app_rd_data_reg[129]\ => \not_strict_mode.app_rd_data_reg[129]\,
      \not_strict_mode.app_rd_data_reg[12]\ => \not_strict_mode.app_rd_data_reg[12]\,
      \not_strict_mode.app_rd_data_reg[130]\ => \not_strict_mode.app_rd_data_reg[130]\,
      \not_strict_mode.app_rd_data_reg[131]\ => \not_strict_mode.app_rd_data_reg[131]\,
      \not_strict_mode.app_rd_data_reg[132]\ => \not_strict_mode.app_rd_data_reg[132]\,
      \not_strict_mode.app_rd_data_reg[133]\ => \not_strict_mode.app_rd_data_reg[133]\,
      \not_strict_mode.app_rd_data_reg[134]\ => \not_strict_mode.app_rd_data_reg[134]\,
      \not_strict_mode.app_rd_data_reg[135]\ => \not_strict_mode.app_rd_data_reg[135]\,
      \not_strict_mode.app_rd_data_reg[136]\ => \not_strict_mode.app_rd_data_reg[136]\,
      \not_strict_mode.app_rd_data_reg[137]\ => \not_strict_mode.app_rd_data_reg[137]\,
      \not_strict_mode.app_rd_data_reg[138]\ => \not_strict_mode.app_rd_data_reg[138]\,
      \not_strict_mode.app_rd_data_reg[139]\ => \not_strict_mode.app_rd_data_reg[139]\,
      \not_strict_mode.app_rd_data_reg[13]\ => \not_strict_mode.app_rd_data_reg[13]\,
      \not_strict_mode.app_rd_data_reg[140]\ => \not_strict_mode.app_rd_data_reg[140]\,
      \not_strict_mode.app_rd_data_reg[141]\ => \not_strict_mode.app_rd_data_reg[141]\,
      \not_strict_mode.app_rd_data_reg[142]\ => \not_strict_mode.app_rd_data_reg[142]\,
      \not_strict_mode.app_rd_data_reg[143]\ => \not_strict_mode.app_rd_data_reg[143]\,
      \not_strict_mode.app_rd_data_reg[144]\ => \not_strict_mode.app_rd_data_reg[144]\,
      \not_strict_mode.app_rd_data_reg[145]\ => \not_strict_mode.app_rd_data_reg[145]\,
      \not_strict_mode.app_rd_data_reg[146]\ => \not_strict_mode.app_rd_data_reg[146]\,
      \not_strict_mode.app_rd_data_reg[147]\ => \not_strict_mode.app_rd_data_reg[147]\,
      \not_strict_mode.app_rd_data_reg[148]\ => \not_strict_mode.app_rd_data_reg[148]\,
      \not_strict_mode.app_rd_data_reg[149]\ => \not_strict_mode.app_rd_data_reg[149]\,
      \not_strict_mode.app_rd_data_reg[14]\ => \not_strict_mode.app_rd_data_reg[14]\,
      \not_strict_mode.app_rd_data_reg[150]\ => \not_strict_mode.app_rd_data_reg[150]\,
      \not_strict_mode.app_rd_data_reg[151]\ => \not_strict_mode.app_rd_data_reg[151]\,
      \not_strict_mode.app_rd_data_reg[152]\ => \not_strict_mode.app_rd_data_reg[152]\,
      \not_strict_mode.app_rd_data_reg[153]\ => \not_strict_mode.app_rd_data_reg[153]\,
      \not_strict_mode.app_rd_data_reg[154]\ => \not_strict_mode.app_rd_data_reg[154]\,
      \not_strict_mode.app_rd_data_reg[155]\ => \not_strict_mode.app_rd_data_reg[155]\,
      \not_strict_mode.app_rd_data_reg[156]\ => \not_strict_mode.app_rd_data_reg[156]\,
      \not_strict_mode.app_rd_data_reg[157]\ => \not_strict_mode.app_rd_data_reg[157]\,
      \not_strict_mode.app_rd_data_reg[158]\ => \not_strict_mode.app_rd_data_reg[158]\,
      \not_strict_mode.app_rd_data_reg[159]\ => \not_strict_mode.app_rd_data_reg[159]\,
      \not_strict_mode.app_rd_data_reg[15]\ => \not_strict_mode.app_rd_data_reg[15]\,
      \not_strict_mode.app_rd_data_reg[160]\ => \not_strict_mode.app_rd_data_reg[160]\,
      \not_strict_mode.app_rd_data_reg[161]\ => \not_strict_mode.app_rd_data_reg[161]\,
      \not_strict_mode.app_rd_data_reg[162]\ => \not_strict_mode.app_rd_data_reg[162]\,
      \not_strict_mode.app_rd_data_reg[163]\ => \not_strict_mode.app_rd_data_reg[163]\,
      \not_strict_mode.app_rd_data_reg[164]\ => \not_strict_mode.app_rd_data_reg[164]\,
      \not_strict_mode.app_rd_data_reg[165]\ => \not_strict_mode.app_rd_data_reg[165]\,
      \not_strict_mode.app_rd_data_reg[166]\ => \not_strict_mode.app_rd_data_reg[166]\,
      \not_strict_mode.app_rd_data_reg[167]\ => \not_strict_mode.app_rd_data_reg[167]\,
      \not_strict_mode.app_rd_data_reg[168]\ => \not_strict_mode.app_rd_data_reg[168]\,
      \not_strict_mode.app_rd_data_reg[169]\ => \not_strict_mode.app_rd_data_reg[169]\,
      \not_strict_mode.app_rd_data_reg[16]\ => \not_strict_mode.app_rd_data_reg[16]\,
      \not_strict_mode.app_rd_data_reg[170]\ => \not_strict_mode.app_rd_data_reg[170]\,
      \not_strict_mode.app_rd_data_reg[171]\ => \not_strict_mode.app_rd_data_reg[171]\,
      \not_strict_mode.app_rd_data_reg[172]\ => \not_strict_mode.app_rd_data_reg[172]\,
      \not_strict_mode.app_rd_data_reg[173]\ => \not_strict_mode.app_rd_data_reg[173]\,
      \not_strict_mode.app_rd_data_reg[174]\ => \not_strict_mode.app_rd_data_reg[174]\,
      \not_strict_mode.app_rd_data_reg[175]\ => \not_strict_mode.app_rd_data_reg[175]\,
      \not_strict_mode.app_rd_data_reg[176]\ => \not_strict_mode.app_rd_data_reg[176]\,
      \not_strict_mode.app_rd_data_reg[177]\ => \not_strict_mode.app_rd_data_reg[177]\,
      \not_strict_mode.app_rd_data_reg[178]\ => \not_strict_mode.app_rd_data_reg[178]\,
      \not_strict_mode.app_rd_data_reg[179]\ => \not_strict_mode.app_rd_data_reg[179]\,
      \not_strict_mode.app_rd_data_reg[17]\ => \not_strict_mode.app_rd_data_reg[17]\,
      \not_strict_mode.app_rd_data_reg[180]\ => \not_strict_mode.app_rd_data_reg[180]\,
      \not_strict_mode.app_rd_data_reg[181]\ => \not_strict_mode.app_rd_data_reg[181]\,
      \not_strict_mode.app_rd_data_reg[182]\ => \not_strict_mode.app_rd_data_reg[182]\,
      \not_strict_mode.app_rd_data_reg[183]\ => \not_strict_mode.app_rd_data_reg[183]\,
      \not_strict_mode.app_rd_data_reg[184]\ => \not_strict_mode.app_rd_data_reg[184]\,
      \not_strict_mode.app_rd_data_reg[185]\ => \not_strict_mode.app_rd_data_reg[185]\,
      \not_strict_mode.app_rd_data_reg[186]\ => \not_strict_mode.app_rd_data_reg[186]\,
      \not_strict_mode.app_rd_data_reg[187]\ => \not_strict_mode.app_rd_data_reg[187]\,
      \not_strict_mode.app_rd_data_reg[188]\ => \not_strict_mode.app_rd_data_reg[188]\,
      \not_strict_mode.app_rd_data_reg[189]\ => \not_strict_mode.app_rd_data_reg[189]\,
      \not_strict_mode.app_rd_data_reg[18]\ => \not_strict_mode.app_rd_data_reg[18]\,
      \not_strict_mode.app_rd_data_reg[190]\ => \not_strict_mode.app_rd_data_reg[190]\,
      \not_strict_mode.app_rd_data_reg[191]\ => \not_strict_mode.app_rd_data_reg[191]\,
      \not_strict_mode.app_rd_data_reg[192]\ => \not_strict_mode.app_rd_data_reg[192]\,
      \not_strict_mode.app_rd_data_reg[193]\ => \not_strict_mode.app_rd_data_reg[193]\,
      \not_strict_mode.app_rd_data_reg[194]\ => \not_strict_mode.app_rd_data_reg[194]\,
      \not_strict_mode.app_rd_data_reg[195]\ => \not_strict_mode.app_rd_data_reg[195]\,
      \not_strict_mode.app_rd_data_reg[196]\ => \not_strict_mode.app_rd_data_reg[196]\,
      \not_strict_mode.app_rd_data_reg[197]\ => \not_strict_mode.app_rd_data_reg[197]\,
      \not_strict_mode.app_rd_data_reg[198]\ => \not_strict_mode.app_rd_data_reg[198]\,
      \not_strict_mode.app_rd_data_reg[199]\ => \not_strict_mode.app_rd_data_reg[199]\,
      \not_strict_mode.app_rd_data_reg[19]\ => \not_strict_mode.app_rd_data_reg[19]\,
      \not_strict_mode.app_rd_data_reg[1]\ => \not_strict_mode.app_rd_data_reg[1]\,
      \not_strict_mode.app_rd_data_reg[200]\ => \not_strict_mode.app_rd_data_reg[200]\,
      \not_strict_mode.app_rd_data_reg[201]\ => \not_strict_mode.app_rd_data_reg[201]\,
      \not_strict_mode.app_rd_data_reg[202]\ => \not_strict_mode.app_rd_data_reg[202]\,
      \not_strict_mode.app_rd_data_reg[203]\ => \not_strict_mode.app_rd_data_reg[203]\,
      \not_strict_mode.app_rd_data_reg[204]\ => \not_strict_mode.app_rd_data_reg[204]\,
      \not_strict_mode.app_rd_data_reg[205]\ => \not_strict_mode.app_rd_data_reg[205]\,
      \not_strict_mode.app_rd_data_reg[206]\ => \not_strict_mode.app_rd_data_reg[206]\,
      \not_strict_mode.app_rd_data_reg[207]\ => \not_strict_mode.app_rd_data_reg[207]\,
      \not_strict_mode.app_rd_data_reg[208]\ => \not_strict_mode.app_rd_data_reg[208]\,
      \not_strict_mode.app_rd_data_reg[209]\ => \not_strict_mode.app_rd_data_reg[209]\,
      \not_strict_mode.app_rd_data_reg[20]\ => \not_strict_mode.app_rd_data_reg[20]\,
      \not_strict_mode.app_rd_data_reg[210]\ => \not_strict_mode.app_rd_data_reg[210]\,
      \not_strict_mode.app_rd_data_reg[211]\ => \not_strict_mode.app_rd_data_reg[211]\,
      \not_strict_mode.app_rd_data_reg[212]\ => \not_strict_mode.app_rd_data_reg[212]\,
      \not_strict_mode.app_rd_data_reg[213]\ => \not_strict_mode.app_rd_data_reg[213]\,
      \not_strict_mode.app_rd_data_reg[214]\ => \not_strict_mode.app_rd_data_reg[214]\,
      \not_strict_mode.app_rd_data_reg[215]\ => \not_strict_mode.app_rd_data_reg[215]\,
      \not_strict_mode.app_rd_data_reg[216]\ => \not_strict_mode.app_rd_data_reg[216]\,
      \not_strict_mode.app_rd_data_reg[217]\ => \not_strict_mode.app_rd_data_reg[217]\,
      \not_strict_mode.app_rd_data_reg[218]\ => \not_strict_mode.app_rd_data_reg[218]\,
      \not_strict_mode.app_rd_data_reg[219]\ => \not_strict_mode.app_rd_data_reg[219]\,
      \not_strict_mode.app_rd_data_reg[21]\ => \not_strict_mode.app_rd_data_reg[21]\,
      \not_strict_mode.app_rd_data_reg[220]\ => \not_strict_mode.app_rd_data_reg[220]\,
      \not_strict_mode.app_rd_data_reg[221]\ => \not_strict_mode.app_rd_data_reg[221]\,
      \not_strict_mode.app_rd_data_reg[222]\ => \not_strict_mode.app_rd_data_reg[222]\,
      \not_strict_mode.app_rd_data_reg[223]\ => \not_strict_mode.app_rd_data_reg[223]\,
      \not_strict_mode.app_rd_data_reg[224]\ => \not_strict_mode.app_rd_data_reg[224]\,
      \not_strict_mode.app_rd_data_reg[225]\ => \not_strict_mode.app_rd_data_reg[225]\,
      \not_strict_mode.app_rd_data_reg[226]\ => \not_strict_mode.app_rd_data_reg[226]\,
      \not_strict_mode.app_rd_data_reg[227]\ => \not_strict_mode.app_rd_data_reg[227]\,
      \not_strict_mode.app_rd_data_reg[228]\ => \not_strict_mode.app_rd_data_reg[228]\,
      \not_strict_mode.app_rd_data_reg[229]\ => \not_strict_mode.app_rd_data_reg[229]\,
      \not_strict_mode.app_rd_data_reg[22]\ => \not_strict_mode.app_rd_data_reg[22]\,
      \not_strict_mode.app_rd_data_reg[230]\ => \not_strict_mode.app_rd_data_reg[230]\,
      \not_strict_mode.app_rd_data_reg[231]\ => \not_strict_mode.app_rd_data_reg[231]\,
      \not_strict_mode.app_rd_data_reg[232]\ => \not_strict_mode.app_rd_data_reg[232]\,
      \not_strict_mode.app_rd_data_reg[233]\ => \not_strict_mode.app_rd_data_reg[233]\,
      \not_strict_mode.app_rd_data_reg[234]\ => \not_strict_mode.app_rd_data_reg[234]\,
      \not_strict_mode.app_rd_data_reg[235]\ => \not_strict_mode.app_rd_data_reg[235]\,
      \not_strict_mode.app_rd_data_reg[236]\ => \not_strict_mode.app_rd_data_reg[236]\,
      \not_strict_mode.app_rd_data_reg[237]\ => \not_strict_mode.app_rd_data_reg[237]\,
      \not_strict_mode.app_rd_data_reg[238]\ => \not_strict_mode.app_rd_data_reg[238]\,
      \not_strict_mode.app_rd_data_reg[239]\ => \not_strict_mode.app_rd_data_reg[239]\,
      \not_strict_mode.app_rd_data_reg[23]\ => \not_strict_mode.app_rd_data_reg[23]\,
      \not_strict_mode.app_rd_data_reg[240]\ => \not_strict_mode.app_rd_data_reg[240]\,
      \not_strict_mode.app_rd_data_reg[241]\ => \not_strict_mode.app_rd_data_reg[241]\,
      \not_strict_mode.app_rd_data_reg[242]\ => \not_strict_mode.app_rd_data_reg[242]\,
      \not_strict_mode.app_rd_data_reg[243]\ => \not_strict_mode.app_rd_data_reg[243]\,
      \not_strict_mode.app_rd_data_reg[244]\ => \not_strict_mode.app_rd_data_reg[244]\,
      \not_strict_mode.app_rd_data_reg[245]\ => \not_strict_mode.app_rd_data_reg[245]\,
      \not_strict_mode.app_rd_data_reg[246]\ => \not_strict_mode.app_rd_data_reg[246]\,
      \not_strict_mode.app_rd_data_reg[247]\ => \not_strict_mode.app_rd_data_reg[247]\,
      \not_strict_mode.app_rd_data_reg[248]\ => \not_strict_mode.app_rd_data_reg[248]\,
      \not_strict_mode.app_rd_data_reg[249]\ => \not_strict_mode.app_rd_data_reg[249]\,
      \not_strict_mode.app_rd_data_reg[24]\ => \not_strict_mode.app_rd_data_reg[24]\,
      \not_strict_mode.app_rd_data_reg[250]\ => \not_strict_mode.app_rd_data_reg[250]\,
      \not_strict_mode.app_rd_data_reg[251]\ => \not_strict_mode.app_rd_data_reg[251]\,
      \not_strict_mode.app_rd_data_reg[252]\ => \not_strict_mode.app_rd_data_reg[252]\,
      \not_strict_mode.app_rd_data_reg[253]\ => \not_strict_mode.app_rd_data_reg[253]\,
      \not_strict_mode.app_rd_data_reg[254]\ => \not_strict_mode.app_rd_data_reg[254]\,
      \not_strict_mode.app_rd_data_reg[255]\ => \not_strict_mode.app_rd_data_reg[255]\,
      \not_strict_mode.app_rd_data_reg[256]\ => \not_strict_mode.app_rd_data_reg[256]\,
      \not_strict_mode.app_rd_data_reg[257]\ => \not_strict_mode.app_rd_data_reg[257]\,
      \not_strict_mode.app_rd_data_reg[258]\ => \not_strict_mode.app_rd_data_reg[258]\,
      \not_strict_mode.app_rd_data_reg[259]\ => \not_strict_mode.app_rd_data_reg[259]\,
      \not_strict_mode.app_rd_data_reg[25]\ => \not_strict_mode.app_rd_data_reg[25]\,
      \not_strict_mode.app_rd_data_reg[260]\ => \not_strict_mode.app_rd_data_reg[260]\,
      \not_strict_mode.app_rd_data_reg[261]\ => \not_strict_mode.app_rd_data_reg[261]\,
      \not_strict_mode.app_rd_data_reg[262]\ => \not_strict_mode.app_rd_data_reg[262]\,
      \not_strict_mode.app_rd_data_reg[263]\ => \not_strict_mode.app_rd_data_reg[263]\,
      \not_strict_mode.app_rd_data_reg[264]\ => \not_strict_mode.app_rd_data_reg[264]\,
      \not_strict_mode.app_rd_data_reg[265]\ => \not_strict_mode.app_rd_data_reg[265]\,
      \not_strict_mode.app_rd_data_reg[266]\ => \not_strict_mode.app_rd_data_reg[266]\,
      \not_strict_mode.app_rd_data_reg[267]\ => \not_strict_mode.app_rd_data_reg[267]\,
      \not_strict_mode.app_rd_data_reg[268]\ => \not_strict_mode.app_rd_data_reg[268]\,
      \not_strict_mode.app_rd_data_reg[269]\ => \not_strict_mode.app_rd_data_reg[269]\,
      \not_strict_mode.app_rd_data_reg[26]\ => \not_strict_mode.app_rd_data_reg[26]\,
      \not_strict_mode.app_rd_data_reg[270]\ => \not_strict_mode.app_rd_data_reg[270]\,
      \not_strict_mode.app_rd_data_reg[271]\ => \not_strict_mode.app_rd_data_reg[271]\,
      \not_strict_mode.app_rd_data_reg[272]\ => \not_strict_mode.app_rd_data_reg[272]\,
      \not_strict_mode.app_rd_data_reg[273]\ => \not_strict_mode.app_rd_data_reg[273]\,
      \not_strict_mode.app_rd_data_reg[274]\ => \not_strict_mode.app_rd_data_reg[274]\,
      \not_strict_mode.app_rd_data_reg[275]\ => \not_strict_mode.app_rd_data_reg[275]\,
      \not_strict_mode.app_rd_data_reg[276]\ => \not_strict_mode.app_rd_data_reg[276]\,
      \not_strict_mode.app_rd_data_reg[277]\ => \not_strict_mode.app_rd_data_reg[277]\,
      \not_strict_mode.app_rd_data_reg[278]\ => \not_strict_mode.app_rd_data_reg[278]\,
      \not_strict_mode.app_rd_data_reg[279]\ => \not_strict_mode.app_rd_data_reg[279]\,
      \not_strict_mode.app_rd_data_reg[27]\ => \not_strict_mode.app_rd_data_reg[27]\,
      \not_strict_mode.app_rd_data_reg[280]\ => \not_strict_mode.app_rd_data_reg[280]\,
      \not_strict_mode.app_rd_data_reg[281]\ => \not_strict_mode.app_rd_data_reg[281]\,
      \not_strict_mode.app_rd_data_reg[282]\ => \not_strict_mode.app_rd_data_reg[282]\,
      \not_strict_mode.app_rd_data_reg[283]\ => \not_strict_mode.app_rd_data_reg[283]\,
      \not_strict_mode.app_rd_data_reg[284]\ => \not_strict_mode.app_rd_data_reg[284]\,
      \not_strict_mode.app_rd_data_reg[285]\ => \not_strict_mode.app_rd_data_reg[285]\,
      \not_strict_mode.app_rd_data_reg[286]\ => \not_strict_mode.app_rd_data_reg[286]\,
      \not_strict_mode.app_rd_data_reg[287]\ => \not_strict_mode.app_rd_data_reg[287]\,
      \not_strict_mode.app_rd_data_reg[288]\ => \not_strict_mode.app_rd_data_reg[288]\,
      \not_strict_mode.app_rd_data_reg[289]\ => \not_strict_mode.app_rd_data_reg[289]\,
      \not_strict_mode.app_rd_data_reg[28]\ => \not_strict_mode.app_rd_data_reg[28]\,
      \not_strict_mode.app_rd_data_reg[290]\ => \not_strict_mode.app_rd_data_reg[290]\,
      \not_strict_mode.app_rd_data_reg[291]\ => \not_strict_mode.app_rd_data_reg[291]\,
      \not_strict_mode.app_rd_data_reg[292]\ => \not_strict_mode.app_rd_data_reg[292]\,
      \not_strict_mode.app_rd_data_reg[293]\ => \not_strict_mode.app_rd_data_reg[293]\,
      \not_strict_mode.app_rd_data_reg[294]\ => \not_strict_mode.app_rd_data_reg[294]\,
      \not_strict_mode.app_rd_data_reg[295]\ => \not_strict_mode.app_rd_data_reg[295]\,
      \not_strict_mode.app_rd_data_reg[296]\ => \not_strict_mode.app_rd_data_reg[296]\,
      \not_strict_mode.app_rd_data_reg[297]\ => \not_strict_mode.app_rd_data_reg[297]\,
      \not_strict_mode.app_rd_data_reg[298]\ => \not_strict_mode.app_rd_data_reg[298]\,
      \not_strict_mode.app_rd_data_reg[299]\ => \not_strict_mode.app_rd_data_reg[299]\,
      \not_strict_mode.app_rd_data_reg[29]\ => \not_strict_mode.app_rd_data_reg[29]\,
      \not_strict_mode.app_rd_data_reg[2]\ => \not_strict_mode.app_rd_data_reg[2]\,
      \not_strict_mode.app_rd_data_reg[300]\ => \not_strict_mode.app_rd_data_reg[300]\,
      \not_strict_mode.app_rd_data_reg[301]\ => \not_strict_mode.app_rd_data_reg[301]\,
      \not_strict_mode.app_rd_data_reg[302]\ => \not_strict_mode.app_rd_data_reg[302]\,
      \not_strict_mode.app_rd_data_reg[303]\ => \not_strict_mode.app_rd_data_reg[303]\,
      \not_strict_mode.app_rd_data_reg[304]\ => \not_strict_mode.app_rd_data_reg[304]\,
      \not_strict_mode.app_rd_data_reg[305]\ => \not_strict_mode.app_rd_data_reg[305]\,
      \not_strict_mode.app_rd_data_reg[306]\ => \not_strict_mode.app_rd_data_reg[306]\,
      \not_strict_mode.app_rd_data_reg[307]\ => \not_strict_mode.app_rd_data_reg[307]\,
      \not_strict_mode.app_rd_data_reg[308]\ => \not_strict_mode.app_rd_data_reg[308]\,
      \not_strict_mode.app_rd_data_reg[309]\ => \not_strict_mode.app_rd_data_reg[309]\,
      \not_strict_mode.app_rd_data_reg[30]\ => \not_strict_mode.app_rd_data_reg[30]\,
      \not_strict_mode.app_rd_data_reg[310]\ => \not_strict_mode.app_rd_data_reg[310]\,
      \not_strict_mode.app_rd_data_reg[311]\ => \not_strict_mode.app_rd_data_reg[311]\,
      \not_strict_mode.app_rd_data_reg[312]\ => \not_strict_mode.app_rd_data_reg[312]\,
      \not_strict_mode.app_rd_data_reg[313]\ => \not_strict_mode.app_rd_data_reg[313]\,
      \not_strict_mode.app_rd_data_reg[314]\ => \not_strict_mode.app_rd_data_reg[314]\,
      \not_strict_mode.app_rd_data_reg[315]\ => \not_strict_mode.app_rd_data_reg[315]\,
      \not_strict_mode.app_rd_data_reg[316]\ => \not_strict_mode.app_rd_data_reg[316]\,
      \not_strict_mode.app_rd_data_reg[317]\ => \not_strict_mode.app_rd_data_reg[317]\,
      \not_strict_mode.app_rd_data_reg[318]\ => \not_strict_mode.app_rd_data_reg[318]\,
      \not_strict_mode.app_rd_data_reg[319]\ => \not_strict_mode.app_rd_data_reg[319]\,
      \not_strict_mode.app_rd_data_reg[31]\ => \not_strict_mode.app_rd_data_reg[31]\,
      \not_strict_mode.app_rd_data_reg[320]\ => \not_strict_mode.app_rd_data_reg[320]\,
      \not_strict_mode.app_rd_data_reg[321]\ => \not_strict_mode.app_rd_data_reg[321]\,
      \not_strict_mode.app_rd_data_reg[322]\ => \not_strict_mode.app_rd_data_reg[322]\,
      \not_strict_mode.app_rd_data_reg[323]\ => \not_strict_mode.app_rd_data_reg[323]\,
      \not_strict_mode.app_rd_data_reg[324]\ => \not_strict_mode.app_rd_data_reg[324]\,
      \not_strict_mode.app_rd_data_reg[325]\ => \not_strict_mode.app_rd_data_reg[325]\,
      \not_strict_mode.app_rd_data_reg[326]\ => \not_strict_mode.app_rd_data_reg[326]\,
      \not_strict_mode.app_rd_data_reg[327]\ => \not_strict_mode.app_rd_data_reg[327]\,
      \not_strict_mode.app_rd_data_reg[328]\ => \not_strict_mode.app_rd_data_reg[328]\,
      \not_strict_mode.app_rd_data_reg[329]\ => \not_strict_mode.app_rd_data_reg[329]\,
      \not_strict_mode.app_rd_data_reg[32]\ => \not_strict_mode.app_rd_data_reg[32]\,
      \not_strict_mode.app_rd_data_reg[330]\ => \not_strict_mode.app_rd_data_reg[330]\,
      \not_strict_mode.app_rd_data_reg[331]\ => \not_strict_mode.app_rd_data_reg[331]\,
      \not_strict_mode.app_rd_data_reg[332]\ => \not_strict_mode.app_rd_data_reg[332]\,
      \not_strict_mode.app_rd_data_reg[333]\ => \not_strict_mode.app_rd_data_reg[333]\,
      \not_strict_mode.app_rd_data_reg[334]\ => \not_strict_mode.app_rd_data_reg[334]\,
      \not_strict_mode.app_rd_data_reg[335]\ => \not_strict_mode.app_rd_data_reg[335]\,
      \not_strict_mode.app_rd_data_reg[336]\ => \not_strict_mode.app_rd_data_reg[336]\,
      \not_strict_mode.app_rd_data_reg[337]\ => \not_strict_mode.app_rd_data_reg[337]\,
      \not_strict_mode.app_rd_data_reg[338]\ => \not_strict_mode.app_rd_data_reg[338]\,
      \not_strict_mode.app_rd_data_reg[339]\ => \not_strict_mode.app_rd_data_reg[339]\,
      \not_strict_mode.app_rd_data_reg[33]\ => \not_strict_mode.app_rd_data_reg[33]\,
      \not_strict_mode.app_rd_data_reg[340]\ => \not_strict_mode.app_rd_data_reg[340]\,
      \not_strict_mode.app_rd_data_reg[341]\ => \not_strict_mode.app_rd_data_reg[341]\,
      \not_strict_mode.app_rd_data_reg[342]\ => \not_strict_mode.app_rd_data_reg[342]\,
      \not_strict_mode.app_rd_data_reg[343]\ => \not_strict_mode.app_rd_data_reg[343]\,
      \not_strict_mode.app_rd_data_reg[344]\ => \not_strict_mode.app_rd_data_reg[344]\,
      \not_strict_mode.app_rd_data_reg[345]\ => \not_strict_mode.app_rd_data_reg[345]\,
      \not_strict_mode.app_rd_data_reg[346]\ => \not_strict_mode.app_rd_data_reg[346]\,
      \not_strict_mode.app_rd_data_reg[347]\ => \not_strict_mode.app_rd_data_reg[347]\,
      \not_strict_mode.app_rd_data_reg[348]\ => \not_strict_mode.app_rd_data_reg[348]\,
      \not_strict_mode.app_rd_data_reg[349]\ => \not_strict_mode.app_rd_data_reg[349]\,
      \not_strict_mode.app_rd_data_reg[34]\ => \not_strict_mode.app_rd_data_reg[34]\,
      \not_strict_mode.app_rd_data_reg[350]\ => \not_strict_mode.app_rd_data_reg[350]\,
      \not_strict_mode.app_rd_data_reg[351]\ => \not_strict_mode.app_rd_data_reg[351]\,
      \not_strict_mode.app_rd_data_reg[352]\ => \not_strict_mode.app_rd_data_reg[352]\,
      \not_strict_mode.app_rd_data_reg[353]\ => \not_strict_mode.app_rd_data_reg[353]\,
      \not_strict_mode.app_rd_data_reg[354]\ => \not_strict_mode.app_rd_data_reg[354]\,
      \not_strict_mode.app_rd_data_reg[355]\ => \not_strict_mode.app_rd_data_reg[355]\,
      \not_strict_mode.app_rd_data_reg[356]\ => \not_strict_mode.app_rd_data_reg[356]\,
      \not_strict_mode.app_rd_data_reg[357]\ => \not_strict_mode.app_rd_data_reg[357]\,
      \not_strict_mode.app_rd_data_reg[358]\ => \not_strict_mode.app_rd_data_reg[358]\,
      \not_strict_mode.app_rd_data_reg[359]\ => \not_strict_mode.app_rd_data_reg[359]\,
      \not_strict_mode.app_rd_data_reg[35]\ => \not_strict_mode.app_rd_data_reg[35]\,
      \not_strict_mode.app_rd_data_reg[360]\ => \not_strict_mode.app_rd_data_reg[360]\,
      \not_strict_mode.app_rd_data_reg[361]\ => \not_strict_mode.app_rd_data_reg[361]\,
      \not_strict_mode.app_rd_data_reg[362]\ => \not_strict_mode.app_rd_data_reg[362]\,
      \not_strict_mode.app_rd_data_reg[363]\ => \not_strict_mode.app_rd_data_reg[363]\,
      \not_strict_mode.app_rd_data_reg[364]\ => \not_strict_mode.app_rd_data_reg[364]\,
      \not_strict_mode.app_rd_data_reg[365]\ => \not_strict_mode.app_rd_data_reg[365]\,
      \not_strict_mode.app_rd_data_reg[366]\ => \not_strict_mode.app_rd_data_reg[366]\,
      \not_strict_mode.app_rd_data_reg[367]\ => \not_strict_mode.app_rd_data_reg[367]\,
      \not_strict_mode.app_rd_data_reg[368]\ => \not_strict_mode.app_rd_data_reg[368]\,
      \not_strict_mode.app_rd_data_reg[369]\ => \not_strict_mode.app_rd_data_reg[369]\,
      \not_strict_mode.app_rd_data_reg[36]\ => \not_strict_mode.app_rd_data_reg[36]\,
      \not_strict_mode.app_rd_data_reg[370]\ => \not_strict_mode.app_rd_data_reg[370]\,
      \not_strict_mode.app_rd_data_reg[371]\ => \not_strict_mode.app_rd_data_reg[371]\,
      \not_strict_mode.app_rd_data_reg[372]\ => \not_strict_mode.app_rd_data_reg[372]\,
      \not_strict_mode.app_rd_data_reg[373]\ => \not_strict_mode.app_rd_data_reg[373]\,
      \not_strict_mode.app_rd_data_reg[374]\ => \not_strict_mode.app_rd_data_reg[374]\,
      \not_strict_mode.app_rd_data_reg[375]\ => \not_strict_mode.app_rd_data_reg[375]\,
      \not_strict_mode.app_rd_data_reg[376]\ => \not_strict_mode.app_rd_data_reg[376]\,
      \not_strict_mode.app_rd_data_reg[377]\ => \not_strict_mode.app_rd_data_reg[377]\,
      \not_strict_mode.app_rd_data_reg[378]\ => \not_strict_mode.app_rd_data_reg[378]\,
      \not_strict_mode.app_rd_data_reg[379]\ => \not_strict_mode.app_rd_data_reg[379]\,
      \not_strict_mode.app_rd_data_reg[37]\ => \not_strict_mode.app_rd_data_reg[37]\,
      \not_strict_mode.app_rd_data_reg[380]\ => \not_strict_mode.app_rd_data_reg[380]\,
      \not_strict_mode.app_rd_data_reg[381]\ => \not_strict_mode.app_rd_data_reg[381]\,
      \not_strict_mode.app_rd_data_reg[382]\ => \not_strict_mode.app_rd_data_reg[382]\,
      \not_strict_mode.app_rd_data_reg[383]\ => \not_strict_mode.app_rd_data_reg[383]\,
      \not_strict_mode.app_rd_data_reg[384]\ => \not_strict_mode.app_rd_data_reg[384]\,
      \not_strict_mode.app_rd_data_reg[385]\ => \not_strict_mode.app_rd_data_reg[385]\,
      \not_strict_mode.app_rd_data_reg[386]\ => \not_strict_mode.app_rd_data_reg[386]\,
      \not_strict_mode.app_rd_data_reg[387]\ => \not_strict_mode.app_rd_data_reg[387]\,
      \not_strict_mode.app_rd_data_reg[388]\ => \not_strict_mode.app_rd_data_reg[388]\,
      \not_strict_mode.app_rd_data_reg[389]\ => \not_strict_mode.app_rd_data_reg[389]\,
      \not_strict_mode.app_rd_data_reg[38]\ => \not_strict_mode.app_rd_data_reg[38]\,
      \not_strict_mode.app_rd_data_reg[390]\ => \not_strict_mode.app_rd_data_reg[390]\,
      \not_strict_mode.app_rd_data_reg[391]\ => \not_strict_mode.app_rd_data_reg[391]\,
      \not_strict_mode.app_rd_data_reg[392]\ => \not_strict_mode.app_rd_data_reg[392]\,
      \not_strict_mode.app_rd_data_reg[393]\ => \not_strict_mode.app_rd_data_reg[393]\,
      \not_strict_mode.app_rd_data_reg[394]\ => \not_strict_mode.app_rd_data_reg[394]\,
      \not_strict_mode.app_rd_data_reg[395]\ => \not_strict_mode.app_rd_data_reg[395]\,
      \not_strict_mode.app_rd_data_reg[396]\ => \not_strict_mode.app_rd_data_reg[396]\,
      \not_strict_mode.app_rd_data_reg[397]\ => \not_strict_mode.app_rd_data_reg[397]\,
      \not_strict_mode.app_rd_data_reg[398]\ => \not_strict_mode.app_rd_data_reg[398]\,
      \not_strict_mode.app_rd_data_reg[399]\ => \not_strict_mode.app_rd_data_reg[399]\,
      \not_strict_mode.app_rd_data_reg[39]\ => \not_strict_mode.app_rd_data_reg[39]\,
      \not_strict_mode.app_rd_data_reg[3]\ => \not_strict_mode.app_rd_data_reg[3]\,
      \not_strict_mode.app_rd_data_reg[400]\ => \not_strict_mode.app_rd_data_reg[400]\,
      \not_strict_mode.app_rd_data_reg[401]\ => \not_strict_mode.app_rd_data_reg[401]\,
      \not_strict_mode.app_rd_data_reg[402]\ => \not_strict_mode.app_rd_data_reg[402]\,
      \not_strict_mode.app_rd_data_reg[403]\ => \not_strict_mode.app_rd_data_reg[403]\,
      \not_strict_mode.app_rd_data_reg[404]\ => \not_strict_mode.app_rd_data_reg[404]\,
      \not_strict_mode.app_rd_data_reg[405]\ => \not_strict_mode.app_rd_data_reg[405]\,
      \not_strict_mode.app_rd_data_reg[406]\ => \not_strict_mode.app_rd_data_reg[406]\,
      \not_strict_mode.app_rd_data_reg[407]\ => \not_strict_mode.app_rd_data_reg[407]\,
      \not_strict_mode.app_rd_data_reg[408]\ => \not_strict_mode.app_rd_data_reg[408]\,
      \not_strict_mode.app_rd_data_reg[409]\ => \not_strict_mode.app_rd_data_reg[409]\,
      \not_strict_mode.app_rd_data_reg[40]\ => \not_strict_mode.app_rd_data_reg[40]\,
      \not_strict_mode.app_rd_data_reg[410]\ => \not_strict_mode.app_rd_data_reg[410]\,
      \not_strict_mode.app_rd_data_reg[411]\ => \not_strict_mode.app_rd_data_reg[411]\,
      \not_strict_mode.app_rd_data_reg[412]\ => \not_strict_mode.app_rd_data_reg[412]\,
      \not_strict_mode.app_rd_data_reg[413]\ => \not_strict_mode.app_rd_data_reg[413]\,
      \not_strict_mode.app_rd_data_reg[414]\ => \not_strict_mode.app_rd_data_reg[414]\,
      \not_strict_mode.app_rd_data_reg[415]\ => \not_strict_mode.app_rd_data_reg[415]\,
      \not_strict_mode.app_rd_data_reg[416]\ => \not_strict_mode.app_rd_data_reg[416]\,
      \not_strict_mode.app_rd_data_reg[417]\ => \not_strict_mode.app_rd_data_reg[417]\,
      \not_strict_mode.app_rd_data_reg[418]\ => \not_strict_mode.app_rd_data_reg[418]\,
      \not_strict_mode.app_rd_data_reg[419]\ => \not_strict_mode.app_rd_data_reg[419]\,
      \not_strict_mode.app_rd_data_reg[41]\ => \not_strict_mode.app_rd_data_reg[41]\,
      \not_strict_mode.app_rd_data_reg[420]\ => \not_strict_mode.app_rd_data_reg[420]\,
      \not_strict_mode.app_rd_data_reg[421]\ => \not_strict_mode.app_rd_data_reg[421]\,
      \not_strict_mode.app_rd_data_reg[422]\ => \not_strict_mode.app_rd_data_reg[422]\,
      \not_strict_mode.app_rd_data_reg[423]\ => \not_strict_mode.app_rd_data_reg[423]\,
      \not_strict_mode.app_rd_data_reg[424]\ => \not_strict_mode.app_rd_data_reg[424]\,
      \not_strict_mode.app_rd_data_reg[425]\ => \not_strict_mode.app_rd_data_reg[425]\,
      \not_strict_mode.app_rd_data_reg[426]\ => \not_strict_mode.app_rd_data_reg[426]\,
      \not_strict_mode.app_rd_data_reg[427]\ => \not_strict_mode.app_rd_data_reg[427]\,
      \not_strict_mode.app_rd_data_reg[428]\ => \not_strict_mode.app_rd_data_reg[428]\,
      \not_strict_mode.app_rd_data_reg[429]\ => \not_strict_mode.app_rd_data_reg[429]\,
      \not_strict_mode.app_rd_data_reg[42]\ => \not_strict_mode.app_rd_data_reg[42]\,
      \not_strict_mode.app_rd_data_reg[430]\ => \not_strict_mode.app_rd_data_reg[430]\,
      \not_strict_mode.app_rd_data_reg[431]\ => \not_strict_mode.app_rd_data_reg[431]\,
      \not_strict_mode.app_rd_data_reg[432]\ => \not_strict_mode.app_rd_data_reg[432]\,
      \not_strict_mode.app_rd_data_reg[433]\ => \not_strict_mode.app_rd_data_reg[433]\,
      \not_strict_mode.app_rd_data_reg[434]\ => \not_strict_mode.app_rd_data_reg[434]\,
      \not_strict_mode.app_rd_data_reg[435]\ => \not_strict_mode.app_rd_data_reg[435]\,
      \not_strict_mode.app_rd_data_reg[436]\ => \not_strict_mode.app_rd_data_reg[436]\,
      \not_strict_mode.app_rd_data_reg[437]\ => \not_strict_mode.app_rd_data_reg[437]\,
      \not_strict_mode.app_rd_data_reg[438]\ => \not_strict_mode.app_rd_data_reg[438]\,
      \not_strict_mode.app_rd_data_reg[439]\ => \not_strict_mode.app_rd_data_reg[439]\,
      \not_strict_mode.app_rd_data_reg[43]\ => \not_strict_mode.app_rd_data_reg[43]\,
      \not_strict_mode.app_rd_data_reg[440]\ => \not_strict_mode.app_rd_data_reg[440]\,
      \not_strict_mode.app_rd_data_reg[441]\ => \not_strict_mode.app_rd_data_reg[441]\,
      \not_strict_mode.app_rd_data_reg[442]\ => \not_strict_mode.app_rd_data_reg[442]\,
      \not_strict_mode.app_rd_data_reg[443]\ => \not_strict_mode.app_rd_data_reg[443]\,
      \not_strict_mode.app_rd_data_reg[444]\ => \not_strict_mode.app_rd_data_reg[444]\,
      \not_strict_mode.app_rd_data_reg[445]\ => \not_strict_mode.app_rd_data_reg[445]\,
      \not_strict_mode.app_rd_data_reg[446]\ => \not_strict_mode.app_rd_data_reg[446]\,
      \not_strict_mode.app_rd_data_reg[447]\ => \not_strict_mode.app_rd_data_reg[447]\,
      \not_strict_mode.app_rd_data_reg[448]\ => \not_strict_mode.app_rd_data_reg[448]\,
      \not_strict_mode.app_rd_data_reg[449]\ => \not_strict_mode.app_rd_data_reg[449]\,
      \not_strict_mode.app_rd_data_reg[44]\ => \not_strict_mode.app_rd_data_reg[44]\,
      \not_strict_mode.app_rd_data_reg[450]\ => \not_strict_mode.app_rd_data_reg[450]\,
      \not_strict_mode.app_rd_data_reg[451]\ => \not_strict_mode.app_rd_data_reg[451]\,
      \not_strict_mode.app_rd_data_reg[452]\ => \not_strict_mode.app_rd_data_reg[452]\,
      \not_strict_mode.app_rd_data_reg[453]\ => \not_strict_mode.app_rd_data_reg[453]\,
      \not_strict_mode.app_rd_data_reg[454]\ => \not_strict_mode.app_rd_data_reg[454]\,
      \not_strict_mode.app_rd_data_reg[455]\ => \not_strict_mode.app_rd_data_reg[455]\,
      \not_strict_mode.app_rd_data_reg[456]\ => \not_strict_mode.app_rd_data_reg[456]\,
      \not_strict_mode.app_rd_data_reg[457]\ => \not_strict_mode.app_rd_data_reg[457]\,
      \not_strict_mode.app_rd_data_reg[458]\ => \not_strict_mode.app_rd_data_reg[458]\,
      \not_strict_mode.app_rd_data_reg[459]\ => \not_strict_mode.app_rd_data_reg[459]\,
      \not_strict_mode.app_rd_data_reg[45]\ => \not_strict_mode.app_rd_data_reg[45]\,
      \not_strict_mode.app_rd_data_reg[460]\ => \not_strict_mode.app_rd_data_reg[460]\,
      \not_strict_mode.app_rd_data_reg[461]\ => \not_strict_mode.app_rd_data_reg[461]\,
      \not_strict_mode.app_rd_data_reg[462]\ => \not_strict_mode.app_rd_data_reg[462]\,
      \not_strict_mode.app_rd_data_reg[463]\ => \not_strict_mode.app_rd_data_reg[463]\,
      \not_strict_mode.app_rd_data_reg[464]\ => \not_strict_mode.app_rd_data_reg[464]\,
      \not_strict_mode.app_rd_data_reg[465]\ => \not_strict_mode.app_rd_data_reg[465]\,
      \not_strict_mode.app_rd_data_reg[466]\ => \not_strict_mode.app_rd_data_reg[466]\,
      \not_strict_mode.app_rd_data_reg[467]\ => \not_strict_mode.app_rd_data_reg[467]\,
      \not_strict_mode.app_rd_data_reg[468]\ => \not_strict_mode.app_rd_data_reg[468]\,
      \not_strict_mode.app_rd_data_reg[469]\ => \not_strict_mode.app_rd_data_reg[469]\,
      \not_strict_mode.app_rd_data_reg[46]\ => \not_strict_mode.app_rd_data_reg[46]\,
      \not_strict_mode.app_rd_data_reg[470]\ => \not_strict_mode.app_rd_data_reg[470]\,
      \not_strict_mode.app_rd_data_reg[471]\ => \not_strict_mode.app_rd_data_reg[471]\,
      \not_strict_mode.app_rd_data_reg[472]\ => \not_strict_mode.app_rd_data_reg[472]\,
      \not_strict_mode.app_rd_data_reg[473]\ => \not_strict_mode.app_rd_data_reg[473]\,
      \not_strict_mode.app_rd_data_reg[474]\ => \not_strict_mode.app_rd_data_reg[474]\,
      \not_strict_mode.app_rd_data_reg[475]\ => \not_strict_mode.app_rd_data_reg[475]\,
      \not_strict_mode.app_rd_data_reg[476]\ => \not_strict_mode.app_rd_data_reg[476]\,
      \not_strict_mode.app_rd_data_reg[477]\ => \not_strict_mode.app_rd_data_reg[477]\,
      \not_strict_mode.app_rd_data_reg[478]\ => \not_strict_mode.app_rd_data_reg[478]\,
      \not_strict_mode.app_rd_data_reg[479]\ => \not_strict_mode.app_rd_data_reg[479]\,
      \not_strict_mode.app_rd_data_reg[47]\ => \not_strict_mode.app_rd_data_reg[47]\,
      \not_strict_mode.app_rd_data_reg[480]\ => \not_strict_mode.app_rd_data_reg[480]\,
      \not_strict_mode.app_rd_data_reg[481]\ => \not_strict_mode.app_rd_data_reg[481]\,
      \not_strict_mode.app_rd_data_reg[482]\ => \not_strict_mode.app_rd_data_reg[482]\,
      \not_strict_mode.app_rd_data_reg[483]\ => \not_strict_mode.app_rd_data_reg[483]\,
      \not_strict_mode.app_rd_data_reg[484]\ => \not_strict_mode.app_rd_data_reg[484]\,
      \not_strict_mode.app_rd_data_reg[485]\ => \not_strict_mode.app_rd_data_reg[485]\,
      \not_strict_mode.app_rd_data_reg[486]\ => \not_strict_mode.app_rd_data_reg[486]\,
      \not_strict_mode.app_rd_data_reg[487]\ => \not_strict_mode.app_rd_data_reg[487]\,
      \not_strict_mode.app_rd_data_reg[488]\ => \not_strict_mode.app_rd_data_reg[488]\,
      \not_strict_mode.app_rd_data_reg[489]\ => \not_strict_mode.app_rd_data_reg[489]\,
      \not_strict_mode.app_rd_data_reg[48]\ => \not_strict_mode.app_rd_data_reg[48]\,
      \not_strict_mode.app_rd_data_reg[490]\ => \not_strict_mode.app_rd_data_reg[490]\,
      \not_strict_mode.app_rd_data_reg[491]\ => \not_strict_mode.app_rd_data_reg[491]\,
      \not_strict_mode.app_rd_data_reg[492]\ => \not_strict_mode.app_rd_data_reg[492]\,
      \not_strict_mode.app_rd_data_reg[493]\ => \not_strict_mode.app_rd_data_reg[493]\,
      \not_strict_mode.app_rd_data_reg[494]\ => \not_strict_mode.app_rd_data_reg[494]\,
      \not_strict_mode.app_rd_data_reg[495]\ => \not_strict_mode.app_rd_data_reg[495]\,
      \not_strict_mode.app_rd_data_reg[496]\ => \not_strict_mode.app_rd_data_reg[496]\,
      \not_strict_mode.app_rd_data_reg[497]\ => \not_strict_mode.app_rd_data_reg[497]\,
      \not_strict_mode.app_rd_data_reg[498]\ => \not_strict_mode.app_rd_data_reg[498]\,
      \not_strict_mode.app_rd_data_reg[499]\ => \not_strict_mode.app_rd_data_reg[499]\,
      \not_strict_mode.app_rd_data_reg[49]\ => \not_strict_mode.app_rd_data_reg[49]\,
      \not_strict_mode.app_rd_data_reg[4]\ => \not_strict_mode.app_rd_data_reg[4]\,
      \not_strict_mode.app_rd_data_reg[500]\ => \not_strict_mode.app_rd_data_reg[500]\,
      \not_strict_mode.app_rd_data_reg[501]\ => \not_strict_mode.app_rd_data_reg[501]\,
      \not_strict_mode.app_rd_data_reg[502]\ => \not_strict_mode.app_rd_data_reg[502]\,
      \not_strict_mode.app_rd_data_reg[503]\ => \not_strict_mode.app_rd_data_reg[503]\,
      \not_strict_mode.app_rd_data_reg[504]\ => \not_strict_mode.app_rd_data_reg[504]\,
      \not_strict_mode.app_rd_data_reg[505]\ => \not_strict_mode.app_rd_data_reg[505]\,
      \not_strict_mode.app_rd_data_reg[506]\ => \not_strict_mode.app_rd_data_reg[506]\,
      \not_strict_mode.app_rd_data_reg[507]\ => \not_strict_mode.app_rd_data_reg[507]\,
      \not_strict_mode.app_rd_data_reg[508]\ => \not_strict_mode.app_rd_data_reg[508]\,
      \not_strict_mode.app_rd_data_reg[509]\ => \not_strict_mode.app_rd_data_reg[509]\,
      \not_strict_mode.app_rd_data_reg[50]\ => \not_strict_mode.app_rd_data_reg[50]\,
      \not_strict_mode.app_rd_data_reg[510]\ => \not_strict_mode.app_rd_data_reg[510]\,
      \not_strict_mode.app_rd_data_reg[511]\ => \not_strict_mode.app_rd_data_reg[511]\,
      \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 0) => \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 0),
      \not_strict_mode.app_rd_data_reg[51]\ => \not_strict_mode.app_rd_data_reg[51]\,
      \not_strict_mode.app_rd_data_reg[52]\ => \not_strict_mode.app_rd_data_reg[52]\,
      \not_strict_mode.app_rd_data_reg[53]\ => \not_strict_mode.app_rd_data_reg[53]\,
      \not_strict_mode.app_rd_data_reg[54]\ => \not_strict_mode.app_rd_data_reg[54]\,
      \not_strict_mode.app_rd_data_reg[55]\ => \not_strict_mode.app_rd_data_reg[55]\,
      \not_strict_mode.app_rd_data_reg[56]\ => \not_strict_mode.app_rd_data_reg[56]\,
      \not_strict_mode.app_rd_data_reg[57]\ => \not_strict_mode.app_rd_data_reg[57]\,
      \not_strict_mode.app_rd_data_reg[58]\ => \not_strict_mode.app_rd_data_reg[58]\,
      \not_strict_mode.app_rd_data_reg[59]\ => \not_strict_mode.app_rd_data_reg[59]\,
      \not_strict_mode.app_rd_data_reg[5]\ => \not_strict_mode.app_rd_data_reg[5]\,
      \not_strict_mode.app_rd_data_reg[60]\ => \not_strict_mode.app_rd_data_reg[60]\,
      \not_strict_mode.app_rd_data_reg[61]\ => \not_strict_mode.app_rd_data_reg[61]\,
      \not_strict_mode.app_rd_data_reg[62]\ => \not_strict_mode.app_rd_data_reg[62]\,
      \not_strict_mode.app_rd_data_reg[63]\ => \not_strict_mode.app_rd_data_reg[63]\,
      \not_strict_mode.app_rd_data_reg[64]\ => \not_strict_mode.app_rd_data_reg[64]\,
      \not_strict_mode.app_rd_data_reg[65]\ => \not_strict_mode.app_rd_data_reg[65]\,
      \not_strict_mode.app_rd_data_reg[66]\ => \not_strict_mode.app_rd_data_reg[66]\,
      \not_strict_mode.app_rd_data_reg[67]\ => \not_strict_mode.app_rd_data_reg[67]\,
      \not_strict_mode.app_rd_data_reg[68]\ => \not_strict_mode.app_rd_data_reg[68]\,
      \not_strict_mode.app_rd_data_reg[69]\ => \not_strict_mode.app_rd_data_reg[69]\,
      \not_strict_mode.app_rd_data_reg[6]\ => \not_strict_mode.app_rd_data_reg[6]\,
      \not_strict_mode.app_rd_data_reg[70]\ => \not_strict_mode.app_rd_data_reg[70]\,
      \not_strict_mode.app_rd_data_reg[71]\ => \not_strict_mode.app_rd_data_reg[71]\,
      \not_strict_mode.app_rd_data_reg[72]\ => \not_strict_mode.app_rd_data_reg[72]\,
      \not_strict_mode.app_rd_data_reg[73]\ => \not_strict_mode.app_rd_data_reg[73]\,
      \not_strict_mode.app_rd_data_reg[74]\ => \not_strict_mode.app_rd_data_reg[74]\,
      \not_strict_mode.app_rd_data_reg[75]\ => \not_strict_mode.app_rd_data_reg[75]\,
      \not_strict_mode.app_rd_data_reg[76]\ => \not_strict_mode.app_rd_data_reg[76]\,
      \not_strict_mode.app_rd_data_reg[77]\ => \not_strict_mode.app_rd_data_reg[77]\,
      \not_strict_mode.app_rd_data_reg[78]\ => \not_strict_mode.app_rd_data_reg[78]\,
      \not_strict_mode.app_rd_data_reg[79]\ => \not_strict_mode.app_rd_data_reg[79]\,
      \not_strict_mode.app_rd_data_reg[7]\ => \not_strict_mode.app_rd_data_reg[7]\,
      \not_strict_mode.app_rd_data_reg[80]\ => \not_strict_mode.app_rd_data_reg[80]\,
      \not_strict_mode.app_rd_data_reg[81]\ => \not_strict_mode.app_rd_data_reg[81]\,
      \not_strict_mode.app_rd_data_reg[82]\ => \not_strict_mode.app_rd_data_reg[82]\,
      \not_strict_mode.app_rd_data_reg[83]\ => \not_strict_mode.app_rd_data_reg[83]\,
      \not_strict_mode.app_rd_data_reg[84]\ => \not_strict_mode.app_rd_data_reg[84]\,
      \not_strict_mode.app_rd_data_reg[85]\ => \not_strict_mode.app_rd_data_reg[85]\,
      \not_strict_mode.app_rd_data_reg[86]\ => \not_strict_mode.app_rd_data_reg[86]\,
      \not_strict_mode.app_rd_data_reg[87]\ => \not_strict_mode.app_rd_data_reg[87]\,
      \not_strict_mode.app_rd_data_reg[88]\ => \not_strict_mode.app_rd_data_reg[88]\,
      \not_strict_mode.app_rd_data_reg[89]\ => \not_strict_mode.app_rd_data_reg[89]\,
      \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\,
      \not_strict_mode.app_rd_data_reg[90]\ => \not_strict_mode.app_rd_data_reg[90]\,
      \not_strict_mode.app_rd_data_reg[91]\ => \not_strict_mode.app_rd_data_reg[91]\,
      \not_strict_mode.app_rd_data_reg[92]\ => \not_strict_mode.app_rd_data_reg[92]\,
      \not_strict_mode.app_rd_data_reg[93]\ => \not_strict_mode.app_rd_data_reg[93]\,
      \not_strict_mode.app_rd_data_reg[94]\ => \not_strict_mode.app_rd_data_reg[94]\,
      \not_strict_mode.app_rd_data_reg[95]\ => \not_strict_mode.app_rd_data_reg[95]\,
      \not_strict_mode.app_rd_data_reg[96]\ => \not_strict_mode.app_rd_data_reg[96]\,
      \not_strict_mode.app_rd_data_reg[97]\ => \not_strict_mode.app_rd_data_reg[97]\,
      \not_strict_mode.app_rd_data_reg[98]\ => \not_strict_mode.app_rd_data_reg[98]\,
      \not_strict_mode.app_rd_data_reg[99]\ => \not_strict_mode.app_rd_data_reg[99]\,
      \not_strict_mode.app_rd_data_reg[9]\ => \not_strict_mode.app_rd_data_reg[9]\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \not_strict_mode.rd_buf_we\,
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\ => ddr_phy_top0_n_60,
      of_ctl_full_v(0) => \u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v\(1),
      \phy_ctl_wd_i1_reg[0]\ => ddr_phy_top0_n_57,
      phy_dout(5) => mux_cas_n(2),
      phy_dout(4) => mux_cas_n(0),
      phy_dout(3) => mux_we_n(2),
      phy_dout(2) => mux_we_n(0),
      phy_dout(1) => mux_cs_n(2),
      phy_dout(0) => mux_cs_n(0),
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      pi_cnt_dec_reg(0) => pi_cnt_dec_reg(0),
      pll_locked => pll_locked,
      prbs_rdlvl_done_pulse_reg(0) => prbs_rdlvl_done_pulse_reg(0),
      ram_init_done_r => ram_init_done_r,
      rdlvl_stg1_start_r_reg => rdlvl_stg1_start_r_reg,
      rdlvl_stg1_start_reg(0) => rdlvl_stg1_start_reg(0),
      \read_fifo.fifo_out_data_r_reg[6]\ => mc0_n_35,
      \read_fifo.tail_r\(0) => \read_fifo.tail_r\(0),
      \read_fifo.tail_r_reg[0]\ => ddr_phy_top0_n_596,
      rst_sync_r1_reg => rst_sync_r1_reg,
      \rstdiv0_sync_r1_reg_rep__10\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__10\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__12\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__12\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__13\(3 downto 0) => \rstdiv0_sync_r1_reg_rep__13\(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__15\(0) => \rstdiv0_sync_r1_reg_rep__15\(0),
      \rstdiv0_sync_r1_reg_rep__17\(0) => \rstdiv0_sync_r1_reg_rep__17\(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__2\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__2\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \rstdiv0_sync_r1_reg_rep__22\ => \rstdiv0_sync_r1_reg_rep__22\,
      \rstdiv0_sync_r1_reg_rep__22_0\ => \rstdiv0_sync_r1_reg_rep__22_0\,
      \rstdiv0_sync_r1_reg_rep__23\ => \rstdiv0_sync_r1_reg_rep__23\,
      \rstdiv0_sync_r1_reg_rep__4\ => \rstdiv0_sync_r1_reg_rep__4\,
      \rstdiv0_sync_r1_reg_rep__5\ => \rstdiv0_sync_r1_reg_rep__5\,
      \rstdiv0_sync_r1_reg_rep__6\(0) => \rstdiv0_sync_r1_reg_rep__6\(0),
      \rstdiv0_sync_r1_reg_rep__8\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__8\(1 downto 0),
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      sent_col => sent_col,
      sync_pulse => sync_pulse,
      sys_rst => sys_rst,
      sys_rst_0 => sys_rst_0,
      tempmon_sample_en => tempmon_sample_en,
      \write_buffer.wr_buf_out_data_reg[383]\(95 downto 0) => \write_buffer.wr_buf_out_data_reg[383]\(95 downto 0),
      \write_buffer.wr_buf_out_data_reg[575]\(575 downto 0) => \write_buffer.wr_buf_out_data_reg[575]_0\(575 downto 0)
    );
mc0: entity work.mig_7series_0_mig_7series_v2_3_mc
     port map (
      CLK => CLK,
      D(13 downto 0) => D(13 downto 0),
      E(0) => E(0),
      Q(7) => Q(6),
      Q(6) => \col_mach0/p_0_in\,
      Q(5 downto 0) => Q(5 downto 0),
      S(0) => S(0),
      SR(0) => SR(0),
      accept_ns => accept_ns,
      \app_addr_r1_reg[23]\(0) => \app_addr_r1_reg[23]\(0),
      \app_addr_r1_reg[23]_0\(0) => \app_addr_r1_reg[23]_0\(0),
      \app_addr_r1_reg[23]_1\(0) => \app_addr_r1_reg[23]_1\(0),
      \app_addr_r1_reg[26]\(2 downto 0) => \app_addr_r1_reg[26]\(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0),
      app_rdy_r_reg => app_rdy_r_reg,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_1 => bm_end_r1_1,
      bm_end_r1_reg => bm_end_r1_reg,
      bm_end_r1_reg_0 => bm_end_r1_reg_0,
      bm_end_r1_reg_1 => bm_end_r1_reg_1,
      bm_end_r1_reg_2 => bm_end_r1_reg_2,
      cmd(1 downto 0) => cmd(1 downto 0),
      \cmd_pipe_plus.mc_address_reg[41]_0\(10 downto 0) => \cmd_pipe_plus.mc_address_reg[41]\(10 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0),
      \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(5 downto 3),
      \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(8 downto 6),
      \cmd_pipe_plus.mc_odt_reg[0]_0\ => mc0_n_24,
      \data_offset_1_i1_reg[0]\ => mc0_n_131,
      \data_offset_1_i1_reg[1]\ => mc0_n_130,
      \data_offset_1_i1_reg[2]\ => mc0_n_129,
      \data_offset_1_i1_reg[3]\(0) => mc0_n_126,
      \data_offset_1_i1_reg[4]\ => mc0_n_128,
      \data_offset_1_i1_reg[5]\ => mc0_n_127,
      \data_offset_2_i1_reg[0]\ => mc0_n_137,
      \data_offset_2_i1_reg[1]\ => mc0_n_136,
      \data_offset_2_i1_reg[2]\ => mc0_n_135,
      \data_offset_2_i1_reg[3]\(0) => mc0_n_132,
      \data_offset_2_i1_reg[4]\ => mc0_n_134,
      \data_offset_2_i1_reg[5]\ => mc0_n_133,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => ddr_phy_top0_n_60,
      granted_col_r_reg(0) => mc_data_offset_ns(3),
      granted_col_r_reg_0(0) => mc_data_offset_1_ns(3),
      granted_col_r_reg_1(0) => mc_data_offset_2_ns(3),
      idle => idle,
      in0 => in0,
      \init_calib_complete_reg_rep__12\ => ddr_phy_top0_n_47,
      \init_calib_complete_reg_rep__26\ => ddr_phy_top0_n_57,
      \maint_prescaler.maint_prescaler_r1\ => \rank_mach0/rank_common0/maint_prescaler.maint_prescaler_r1\,
      mc_address(38 downto 25) => mc_address(41 downto 28),
      mc_address(24 downto 0) => mc_address(24 downto 0),
      mc_bank(8 downto 0) => mc_bank(8 downto 0),
      mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0),
      mc_cke(0) => mc_cke(3),
      mc_cmd(1 downto 0) => mc_cmd(1 downto 0),
      mc_cs_n(0) => mc_cs_n(0),
      mc_odt(0) => mc_odt(0),
      mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0),
      mc_wrdata_en => mc_wrdata_en,
      \not_strict_mode.app_rd_data_end_ns\ => \not_strict_mode.app_rd_data_end_ns\,
      \not_strict_mode.app_rd_data_reg[40]\ => mc0_n_35,
      \not_strict_mode.bypass__0\ => \not_strict_mode.bypass__0\,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0),
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0) => \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0),
      of_ctl_full_v(0) => \u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v\(1),
      \phy_ctl_wd_i1_reg[17]\ => mc0_n_125,
      \phy_ctl_wd_i1_reg[18]\ => mc0_n_124,
      \phy_ctl_wd_i1_reg[19]\ => mc0_n_123,
      \phy_ctl_wd_i1_reg[20]\(0) => mc0_n_120,
      \phy_ctl_wd_i1_reg[21]\ => mc0_n_122,
      \phy_ctl_wd_i1_reg[22]\ => mc0_n_121,
      phy_dout(5) => mux_cas_n(2),
      phy_dout(4) => mux_cas_n(0),
      phy_dout(3) => mux_we_n(2),
      phy_dout(2) => mux_we_n(0),
      phy_dout(1) => mux_cs_n(2),
      phy_dout(0) => mux_cs_n(0),
      phy_mc_ctl_full => phy_mc_ctl_full,
      phy_mc_data_full => phy_mc_data_full,
      \pointer_ram.pointer_we\ => \pointer_ram.pointer_we\,
      ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0),
      ram_init_done_r => ram_init_done_r,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ => ddr_phy_top0_n_598,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\ => ddr_phy_top0_n_603,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4]\ => ddr_phy_top0_n_597,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5) => ddr_phy_top0_n_590,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(4) => ddr_phy_top0_n_591,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3) => ddr_phy_top0_n_592,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2) => ddr_phy_top0_n_593,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1) => ddr_phy_top0_n_594,
      \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(0) => ddr_phy_top0_n_595,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10]\ => ddr_phy_top0_n_599,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(5) => ddr_phy_top0_n_583,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(4) => ddr_phy_top0_n_584,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(3) => ddr_phy_top0_n_585,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(2) => ddr_phy_top0_n_586,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(1) => ddr_phy_top0_n_587,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]\(0) => ddr_phy_top0_n_588,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]\ => ddr_phy_top0_n_600,
      \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0\ => ddr_phy_top0_n_604,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]\ => ddr_phy_top0_n_602,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0\ => ddr_phy_top0_n_605,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16]\ => ddr_phy_top0_n_601,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(5) => ddr_phy_top0_n_576,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(4) => ddr_phy_top0_n_577,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(3) => ddr_phy_top0_n_578,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(2) => ddr_phy_top0_n_579,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(1) => ddr_phy_top0_n_580,
      \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]\(0) => ddr_phy_top0_n_581,
      ras_timer_zero_r_reg => ras_timer_zero_r_reg,
      ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg_0,
      \rd_buf_indx.rd_buf_indx_r_reg[4]\ => \rd_buf_indx.rd_buf_indx_r_reg[4]\,
      \rd_ptr_timing_reg[0]\(0) => mux_ras_n(0),
      \rd_ptr_timing_reg[0]_0\(2 downto 0) => mc_we_n(2 downto 0),
      \read_fifo.tail_r_reg[0]\ => ddr_phy_top0_n_596,
      \read_fifo.tail_r_reg[1]\(0) => \read_fifo.tail_r\(0),
      \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]\,
      \req_bank_r_lcl_reg[0]_0\ => \req_bank_r_lcl_reg[0]_0\,
      \req_bank_r_lcl_reg[2]\ => \req_bank_r_lcl_reg[2]\,
      \req_row_r_lcl_reg[3]\(0) => \req_row_r_lcl_reg[3]\(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      sent_col => sent_col,
      tempmon_sample_en => tempmon_sample_en,
      use_addr => use_addr,
      \write_buffer.wr_buf_out_data_reg[575]\(3 downto 0) => \write_buffer.wr_buf_out_data_reg[575]\(3 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_v2_3_memc_ui_top_std is
  port (
    bm_end_r1 : out STD_LOGIC;
    bm_end_r1_0 : out STD_LOGIC;
    bm_end_r1_1 : out STD_LOGIC;
    bm_end_r1_2 : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ : out STD_LOGIC;
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    po_cnt_dec : out STD_LOGIC;
    prbs_rdlvl_done_pulse : out STD_LOGIC;
    rdlvl_stg1_start_r_reg : out STD_LOGIC;
    idelay_tap_limit_r_reg : out STD_LOGIC;
    samp_edge_cnt0_en_r : out STD_LOGIC;
    pi_cnt_dec : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    rst_sync_r1_reg : out STD_LOGIC;
    app_rdy : out STD_LOGIC;
    \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    app_rd_data : out STD_LOGIC_VECTOR ( 511 downto 0 );
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    CLK : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 1 downto 0 );
    in0 : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__21\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__20\ : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__19\ : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    freq_refclk : in STD_LOGIC;
    mem_refclk : in STD_LOGIC;
    sync_pulse : in STD_LOGIC;
    pll_locked : in STD_LOGIC;
    RST0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__23\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__12\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__4\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__5\ : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rstdiv0_sync_r1_reg_rep__13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rstdiv0_sync_r1_reg_rep__15\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__17\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__22\ : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    iodelay_ctrl_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_rst_0 : in STD_LOGIC;
    bm_end_r1_reg : in STD_LOGIC;
    bm_end_r1_reg_0 : in STD_LOGIC;
    bm_end_r1_reg_1 : in STD_LOGIC;
    bm_end_r1_reg_2 : in STD_LOGIC;
    \rstdiv0_sync_r1_reg_rep__10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    prbs_rdlvl_done_pulse_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rstdiv0_sync_r1_reg_rep__22_0\ : in STD_LOGIC;
    new_cnt_cpt_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdlvl_stg1_start_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    clear : in STD_LOGIC;
    pi_cnt_dec_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 11 downto 0 );
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_v2_3_memc_ui_top_std : entity is "mig_7series_v2_3_memc_ui_top_std";
end mig_7series_0_mig_7series_v2_3_memc_ui_top_std;

architecture STRUCTURE of mig_7series_0_mig_7series_v2_3_memc_ui_top_std is
  signal accept_ns : STD_LOGIC;
  signal \^app_rdy\ : STD_LOGIC;
  signal bank : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cmd : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal col : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal data_buf_addr : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \ddr_phy_top0/mux_wrdata\ : STD_LOGIC_VECTOR ( 383 downto 0 );
  signal \mc0/bank_mach0/req_bank_r\ : STD_LOGIC_VECTOR ( 11 downto 3 );
  signal \mc0/bank_mach0/req_row_r\ : STD_LOGIC_VECTOR ( 55 downto 12 );
  signal mem_intfc0_n_100 : STD_LOGIC;
  signal mem_intfc0_n_101 : STD_LOGIC;
  signal mem_intfc0_n_102 : STD_LOGIC;
  signal mem_intfc0_n_103 : STD_LOGIC;
  signal mem_intfc0_n_104 : STD_LOGIC;
  signal mem_intfc0_n_105 : STD_LOGIC;
  signal mem_intfc0_n_106 : STD_LOGIC;
  signal mem_intfc0_n_107 : STD_LOGIC;
  signal mem_intfc0_n_108 : STD_LOGIC;
  signal mem_intfc0_n_109 : STD_LOGIC;
  signal mem_intfc0_n_110 : STD_LOGIC;
  signal mem_intfc0_n_111 : STD_LOGIC;
  signal mem_intfc0_n_112 : STD_LOGIC;
  signal mem_intfc0_n_113 : STD_LOGIC;
  signal mem_intfc0_n_114 : STD_LOGIC;
  signal mem_intfc0_n_115 : STD_LOGIC;
  signal mem_intfc0_n_116 : STD_LOGIC;
  signal mem_intfc0_n_117 : STD_LOGIC;
  signal mem_intfc0_n_118 : STD_LOGIC;
  signal mem_intfc0_n_119 : STD_LOGIC;
  signal mem_intfc0_n_120 : STD_LOGIC;
  signal mem_intfc0_n_121 : STD_LOGIC;
  signal mem_intfc0_n_122 : STD_LOGIC;
  signal mem_intfc0_n_123 : STD_LOGIC;
  signal mem_intfc0_n_124 : STD_LOGIC;
  signal mem_intfc0_n_125 : STD_LOGIC;
  signal mem_intfc0_n_126 : STD_LOGIC;
  signal mem_intfc0_n_127 : STD_LOGIC;
  signal mem_intfc0_n_128 : STD_LOGIC;
  signal mem_intfc0_n_129 : STD_LOGIC;
  signal mem_intfc0_n_130 : STD_LOGIC;
  signal mem_intfc0_n_131 : STD_LOGIC;
  signal mem_intfc0_n_132 : STD_LOGIC;
  signal mem_intfc0_n_133 : STD_LOGIC;
  signal mem_intfc0_n_134 : STD_LOGIC;
  signal mem_intfc0_n_135 : STD_LOGIC;
  signal mem_intfc0_n_136 : STD_LOGIC;
  signal mem_intfc0_n_137 : STD_LOGIC;
  signal mem_intfc0_n_138 : STD_LOGIC;
  signal mem_intfc0_n_139 : STD_LOGIC;
  signal mem_intfc0_n_140 : STD_LOGIC;
  signal mem_intfc0_n_141 : STD_LOGIC;
  signal mem_intfc0_n_142 : STD_LOGIC;
  signal mem_intfc0_n_143 : STD_LOGIC;
  signal mem_intfc0_n_144 : STD_LOGIC;
  signal mem_intfc0_n_145 : STD_LOGIC;
  signal mem_intfc0_n_146 : STD_LOGIC;
  signal mem_intfc0_n_147 : STD_LOGIC;
  signal mem_intfc0_n_148 : STD_LOGIC;
  signal mem_intfc0_n_149 : STD_LOGIC;
  signal mem_intfc0_n_150 : STD_LOGIC;
  signal mem_intfc0_n_151 : STD_LOGIC;
  signal mem_intfc0_n_152 : STD_LOGIC;
  signal mem_intfc0_n_153 : STD_LOGIC;
  signal mem_intfc0_n_154 : STD_LOGIC;
  signal mem_intfc0_n_155 : STD_LOGIC;
  signal mem_intfc0_n_156 : STD_LOGIC;
  signal mem_intfc0_n_157 : STD_LOGIC;
  signal mem_intfc0_n_158 : STD_LOGIC;
  signal mem_intfc0_n_159 : STD_LOGIC;
  signal mem_intfc0_n_160 : STD_LOGIC;
  signal mem_intfc0_n_161 : STD_LOGIC;
  signal mem_intfc0_n_162 : STD_LOGIC;
  signal mem_intfc0_n_163 : STD_LOGIC;
  signal mem_intfc0_n_164 : STD_LOGIC;
  signal mem_intfc0_n_165 : STD_LOGIC;
  signal mem_intfc0_n_166 : STD_LOGIC;
  signal mem_intfc0_n_167 : STD_LOGIC;
  signal mem_intfc0_n_168 : STD_LOGIC;
  signal mem_intfc0_n_169 : STD_LOGIC;
  signal mem_intfc0_n_170 : STD_LOGIC;
  signal mem_intfc0_n_171 : STD_LOGIC;
  signal mem_intfc0_n_172 : STD_LOGIC;
  signal mem_intfc0_n_173 : STD_LOGIC;
  signal mem_intfc0_n_174 : STD_LOGIC;
  signal mem_intfc0_n_175 : STD_LOGIC;
  signal mem_intfc0_n_176 : STD_LOGIC;
  signal mem_intfc0_n_177 : STD_LOGIC;
  signal mem_intfc0_n_178 : STD_LOGIC;
  signal mem_intfc0_n_179 : STD_LOGIC;
  signal mem_intfc0_n_180 : STD_LOGIC;
  signal mem_intfc0_n_181 : STD_LOGIC;
  signal mem_intfc0_n_182 : STD_LOGIC;
  signal mem_intfc0_n_183 : STD_LOGIC;
  signal mem_intfc0_n_184 : STD_LOGIC;
  signal mem_intfc0_n_185 : STD_LOGIC;
  signal mem_intfc0_n_186 : STD_LOGIC;
  signal mem_intfc0_n_187 : STD_LOGIC;
  signal mem_intfc0_n_188 : STD_LOGIC;
  signal mem_intfc0_n_189 : STD_LOGIC;
  signal mem_intfc0_n_190 : STD_LOGIC;
  signal mem_intfc0_n_191 : STD_LOGIC;
  signal mem_intfc0_n_192 : STD_LOGIC;
  signal mem_intfc0_n_193 : STD_LOGIC;
  signal mem_intfc0_n_194 : STD_LOGIC;
  signal mem_intfc0_n_195 : STD_LOGIC;
  signal mem_intfc0_n_196 : STD_LOGIC;
  signal mem_intfc0_n_197 : STD_LOGIC;
  signal mem_intfc0_n_198 : STD_LOGIC;
  signal mem_intfc0_n_199 : STD_LOGIC;
  signal mem_intfc0_n_200 : STD_LOGIC;
  signal mem_intfc0_n_201 : STD_LOGIC;
  signal mem_intfc0_n_202 : STD_LOGIC;
  signal mem_intfc0_n_203 : STD_LOGIC;
  signal mem_intfc0_n_204 : STD_LOGIC;
  signal mem_intfc0_n_205 : STD_LOGIC;
  signal mem_intfc0_n_206 : STD_LOGIC;
  signal mem_intfc0_n_207 : STD_LOGIC;
  signal mem_intfc0_n_208 : STD_LOGIC;
  signal mem_intfc0_n_209 : STD_LOGIC;
  signal mem_intfc0_n_210 : STD_LOGIC;
  signal mem_intfc0_n_211 : STD_LOGIC;
  signal mem_intfc0_n_212 : STD_LOGIC;
  signal mem_intfc0_n_213 : STD_LOGIC;
  signal mem_intfc0_n_214 : STD_LOGIC;
  signal mem_intfc0_n_215 : STD_LOGIC;
  signal mem_intfc0_n_216 : STD_LOGIC;
  signal mem_intfc0_n_217 : STD_LOGIC;
  signal mem_intfc0_n_218 : STD_LOGIC;
  signal mem_intfc0_n_219 : STD_LOGIC;
  signal mem_intfc0_n_220 : STD_LOGIC;
  signal mem_intfc0_n_221 : STD_LOGIC;
  signal mem_intfc0_n_222 : STD_LOGIC;
  signal mem_intfc0_n_223 : STD_LOGIC;
  signal mem_intfc0_n_224 : STD_LOGIC;
  signal mem_intfc0_n_225 : STD_LOGIC;
  signal mem_intfc0_n_226 : STD_LOGIC;
  signal mem_intfc0_n_227 : STD_LOGIC;
  signal mem_intfc0_n_228 : STD_LOGIC;
  signal mem_intfc0_n_229 : STD_LOGIC;
  signal mem_intfc0_n_230 : STD_LOGIC;
  signal mem_intfc0_n_231 : STD_LOGIC;
  signal mem_intfc0_n_232 : STD_LOGIC;
  signal mem_intfc0_n_233 : STD_LOGIC;
  signal mem_intfc0_n_234 : STD_LOGIC;
  signal mem_intfc0_n_235 : STD_LOGIC;
  signal mem_intfc0_n_236 : STD_LOGIC;
  signal mem_intfc0_n_237 : STD_LOGIC;
  signal mem_intfc0_n_238 : STD_LOGIC;
  signal mem_intfc0_n_239 : STD_LOGIC;
  signal mem_intfc0_n_240 : STD_LOGIC;
  signal mem_intfc0_n_241 : STD_LOGIC;
  signal mem_intfc0_n_242 : STD_LOGIC;
  signal mem_intfc0_n_243 : STD_LOGIC;
  signal mem_intfc0_n_244 : STD_LOGIC;
  signal mem_intfc0_n_245 : STD_LOGIC;
  signal mem_intfc0_n_246 : STD_LOGIC;
  signal mem_intfc0_n_247 : STD_LOGIC;
  signal mem_intfc0_n_248 : STD_LOGIC;
  signal mem_intfc0_n_249 : STD_LOGIC;
  signal mem_intfc0_n_250 : STD_LOGIC;
  signal mem_intfc0_n_251 : STD_LOGIC;
  signal mem_intfc0_n_252 : STD_LOGIC;
  signal mem_intfc0_n_253 : STD_LOGIC;
  signal mem_intfc0_n_254 : STD_LOGIC;
  signal mem_intfc0_n_255 : STD_LOGIC;
  signal mem_intfc0_n_256 : STD_LOGIC;
  signal mem_intfc0_n_257 : STD_LOGIC;
  signal mem_intfc0_n_258 : STD_LOGIC;
  signal mem_intfc0_n_259 : STD_LOGIC;
  signal mem_intfc0_n_260 : STD_LOGIC;
  signal mem_intfc0_n_261 : STD_LOGIC;
  signal mem_intfc0_n_262 : STD_LOGIC;
  signal mem_intfc0_n_263 : STD_LOGIC;
  signal mem_intfc0_n_264 : STD_LOGIC;
  signal mem_intfc0_n_265 : STD_LOGIC;
  signal mem_intfc0_n_266 : STD_LOGIC;
  signal mem_intfc0_n_267 : STD_LOGIC;
  signal mem_intfc0_n_268 : STD_LOGIC;
  signal mem_intfc0_n_269 : STD_LOGIC;
  signal mem_intfc0_n_270 : STD_LOGIC;
  signal mem_intfc0_n_271 : STD_LOGIC;
  signal mem_intfc0_n_272 : STD_LOGIC;
  signal mem_intfc0_n_273 : STD_LOGIC;
  signal mem_intfc0_n_274 : STD_LOGIC;
  signal mem_intfc0_n_275 : STD_LOGIC;
  signal mem_intfc0_n_276 : STD_LOGIC;
  signal mem_intfc0_n_277 : STD_LOGIC;
  signal mem_intfc0_n_278 : STD_LOGIC;
  signal mem_intfc0_n_279 : STD_LOGIC;
  signal mem_intfc0_n_280 : STD_LOGIC;
  signal mem_intfc0_n_281 : STD_LOGIC;
  signal mem_intfc0_n_282 : STD_LOGIC;
  signal mem_intfc0_n_283 : STD_LOGIC;
  signal mem_intfc0_n_284 : STD_LOGIC;
  signal mem_intfc0_n_285 : STD_LOGIC;
  signal mem_intfc0_n_286 : STD_LOGIC;
  signal mem_intfc0_n_287 : STD_LOGIC;
  signal mem_intfc0_n_288 : STD_LOGIC;
  signal mem_intfc0_n_289 : STD_LOGIC;
  signal mem_intfc0_n_290 : STD_LOGIC;
  signal mem_intfc0_n_291 : STD_LOGIC;
  signal mem_intfc0_n_292 : STD_LOGIC;
  signal mem_intfc0_n_293 : STD_LOGIC;
  signal mem_intfc0_n_294 : STD_LOGIC;
  signal mem_intfc0_n_295 : STD_LOGIC;
  signal mem_intfc0_n_296 : STD_LOGIC;
  signal mem_intfc0_n_297 : STD_LOGIC;
  signal mem_intfc0_n_298 : STD_LOGIC;
  signal mem_intfc0_n_299 : STD_LOGIC;
  signal mem_intfc0_n_300 : STD_LOGIC;
  signal mem_intfc0_n_301 : STD_LOGIC;
  signal mem_intfc0_n_302 : STD_LOGIC;
  signal mem_intfc0_n_303 : STD_LOGIC;
  signal mem_intfc0_n_304 : STD_LOGIC;
  signal mem_intfc0_n_305 : STD_LOGIC;
  signal mem_intfc0_n_306 : STD_LOGIC;
  signal mem_intfc0_n_307 : STD_LOGIC;
  signal mem_intfc0_n_308 : STD_LOGIC;
  signal mem_intfc0_n_309 : STD_LOGIC;
  signal mem_intfc0_n_310 : STD_LOGIC;
  signal mem_intfc0_n_311 : STD_LOGIC;
  signal mem_intfc0_n_312 : STD_LOGIC;
  signal mem_intfc0_n_313 : STD_LOGIC;
  signal mem_intfc0_n_314 : STD_LOGIC;
  signal mem_intfc0_n_315 : STD_LOGIC;
  signal mem_intfc0_n_316 : STD_LOGIC;
  signal mem_intfc0_n_317 : STD_LOGIC;
  signal mem_intfc0_n_318 : STD_LOGIC;
  signal mem_intfc0_n_319 : STD_LOGIC;
  signal mem_intfc0_n_320 : STD_LOGIC;
  signal mem_intfc0_n_321 : STD_LOGIC;
  signal mem_intfc0_n_322 : STD_LOGIC;
  signal mem_intfc0_n_323 : STD_LOGIC;
  signal mem_intfc0_n_324 : STD_LOGIC;
  signal mem_intfc0_n_325 : STD_LOGIC;
  signal mem_intfc0_n_326 : STD_LOGIC;
  signal mem_intfc0_n_327 : STD_LOGIC;
  signal mem_intfc0_n_328 : STD_LOGIC;
  signal mem_intfc0_n_329 : STD_LOGIC;
  signal mem_intfc0_n_330 : STD_LOGIC;
  signal mem_intfc0_n_331 : STD_LOGIC;
  signal mem_intfc0_n_332 : STD_LOGIC;
  signal mem_intfc0_n_333 : STD_LOGIC;
  signal mem_intfc0_n_334 : STD_LOGIC;
  signal mem_intfc0_n_335 : STD_LOGIC;
  signal mem_intfc0_n_336 : STD_LOGIC;
  signal mem_intfc0_n_337 : STD_LOGIC;
  signal mem_intfc0_n_338 : STD_LOGIC;
  signal mem_intfc0_n_339 : STD_LOGIC;
  signal mem_intfc0_n_340 : STD_LOGIC;
  signal mem_intfc0_n_341 : STD_LOGIC;
  signal mem_intfc0_n_342 : STD_LOGIC;
  signal mem_intfc0_n_343 : STD_LOGIC;
  signal mem_intfc0_n_344 : STD_LOGIC;
  signal mem_intfc0_n_345 : STD_LOGIC;
  signal mem_intfc0_n_346 : STD_LOGIC;
  signal mem_intfc0_n_347 : STD_LOGIC;
  signal mem_intfc0_n_348 : STD_LOGIC;
  signal mem_intfc0_n_349 : STD_LOGIC;
  signal mem_intfc0_n_350 : STD_LOGIC;
  signal mem_intfc0_n_351 : STD_LOGIC;
  signal mem_intfc0_n_352 : STD_LOGIC;
  signal mem_intfc0_n_353 : STD_LOGIC;
  signal mem_intfc0_n_354 : STD_LOGIC;
  signal mem_intfc0_n_355 : STD_LOGIC;
  signal mem_intfc0_n_356 : STD_LOGIC;
  signal mem_intfc0_n_357 : STD_LOGIC;
  signal mem_intfc0_n_358 : STD_LOGIC;
  signal mem_intfc0_n_359 : STD_LOGIC;
  signal mem_intfc0_n_360 : STD_LOGIC;
  signal mem_intfc0_n_361 : STD_LOGIC;
  signal mem_intfc0_n_362 : STD_LOGIC;
  signal mem_intfc0_n_363 : STD_LOGIC;
  signal mem_intfc0_n_364 : STD_LOGIC;
  signal mem_intfc0_n_365 : STD_LOGIC;
  signal mem_intfc0_n_366 : STD_LOGIC;
  signal mem_intfc0_n_367 : STD_LOGIC;
  signal mem_intfc0_n_368 : STD_LOGIC;
  signal mem_intfc0_n_369 : STD_LOGIC;
  signal mem_intfc0_n_370 : STD_LOGIC;
  signal mem_intfc0_n_371 : STD_LOGIC;
  signal mem_intfc0_n_372 : STD_LOGIC;
  signal mem_intfc0_n_373 : STD_LOGIC;
  signal mem_intfc0_n_374 : STD_LOGIC;
  signal mem_intfc0_n_375 : STD_LOGIC;
  signal mem_intfc0_n_376 : STD_LOGIC;
  signal mem_intfc0_n_377 : STD_LOGIC;
  signal mem_intfc0_n_378 : STD_LOGIC;
  signal mem_intfc0_n_379 : STD_LOGIC;
  signal mem_intfc0_n_380 : STD_LOGIC;
  signal mem_intfc0_n_381 : STD_LOGIC;
  signal mem_intfc0_n_382 : STD_LOGIC;
  signal mem_intfc0_n_383 : STD_LOGIC;
  signal mem_intfc0_n_384 : STD_LOGIC;
  signal mem_intfc0_n_385 : STD_LOGIC;
  signal mem_intfc0_n_386 : STD_LOGIC;
  signal mem_intfc0_n_387 : STD_LOGIC;
  signal mem_intfc0_n_388 : STD_LOGIC;
  signal mem_intfc0_n_389 : STD_LOGIC;
  signal mem_intfc0_n_390 : STD_LOGIC;
  signal mem_intfc0_n_391 : STD_LOGIC;
  signal mem_intfc0_n_392 : STD_LOGIC;
  signal mem_intfc0_n_393 : STD_LOGIC;
  signal mem_intfc0_n_394 : STD_LOGIC;
  signal mem_intfc0_n_395 : STD_LOGIC;
  signal mem_intfc0_n_396 : STD_LOGIC;
  signal mem_intfc0_n_397 : STD_LOGIC;
  signal mem_intfc0_n_398 : STD_LOGIC;
  signal mem_intfc0_n_399 : STD_LOGIC;
  signal mem_intfc0_n_400 : STD_LOGIC;
  signal mem_intfc0_n_401 : STD_LOGIC;
  signal mem_intfc0_n_402 : STD_LOGIC;
  signal mem_intfc0_n_403 : STD_LOGIC;
  signal mem_intfc0_n_404 : STD_LOGIC;
  signal mem_intfc0_n_405 : STD_LOGIC;
  signal mem_intfc0_n_406 : STD_LOGIC;
  signal mem_intfc0_n_407 : STD_LOGIC;
  signal mem_intfc0_n_408 : STD_LOGIC;
  signal mem_intfc0_n_409 : STD_LOGIC;
  signal mem_intfc0_n_410 : STD_LOGIC;
  signal mem_intfc0_n_411 : STD_LOGIC;
  signal mem_intfc0_n_412 : STD_LOGIC;
  signal mem_intfc0_n_413 : STD_LOGIC;
  signal mem_intfc0_n_414 : STD_LOGIC;
  signal mem_intfc0_n_415 : STD_LOGIC;
  signal mem_intfc0_n_416 : STD_LOGIC;
  signal mem_intfc0_n_417 : STD_LOGIC;
  signal mem_intfc0_n_418 : STD_LOGIC;
  signal mem_intfc0_n_419 : STD_LOGIC;
  signal mem_intfc0_n_420 : STD_LOGIC;
  signal mem_intfc0_n_421 : STD_LOGIC;
  signal mem_intfc0_n_422 : STD_LOGIC;
  signal mem_intfc0_n_423 : STD_LOGIC;
  signal mem_intfc0_n_424 : STD_LOGIC;
  signal mem_intfc0_n_425 : STD_LOGIC;
  signal mem_intfc0_n_426 : STD_LOGIC;
  signal mem_intfc0_n_427 : STD_LOGIC;
  signal mem_intfc0_n_428 : STD_LOGIC;
  signal mem_intfc0_n_429 : STD_LOGIC;
  signal mem_intfc0_n_430 : STD_LOGIC;
  signal mem_intfc0_n_431 : STD_LOGIC;
  signal mem_intfc0_n_432 : STD_LOGIC;
  signal mem_intfc0_n_433 : STD_LOGIC;
  signal mem_intfc0_n_434 : STD_LOGIC;
  signal mem_intfc0_n_435 : STD_LOGIC;
  signal mem_intfc0_n_436 : STD_LOGIC;
  signal mem_intfc0_n_437 : STD_LOGIC;
  signal mem_intfc0_n_438 : STD_LOGIC;
  signal mem_intfc0_n_439 : STD_LOGIC;
  signal mem_intfc0_n_440 : STD_LOGIC;
  signal mem_intfc0_n_441 : STD_LOGIC;
  signal mem_intfc0_n_442 : STD_LOGIC;
  signal mem_intfc0_n_443 : STD_LOGIC;
  signal mem_intfc0_n_444 : STD_LOGIC;
  signal mem_intfc0_n_445 : STD_LOGIC;
  signal mem_intfc0_n_446 : STD_LOGIC;
  signal mem_intfc0_n_447 : STD_LOGIC;
  signal mem_intfc0_n_448 : STD_LOGIC;
  signal mem_intfc0_n_449 : STD_LOGIC;
  signal mem_intfc0_n_450 : STD_LOGIC;
  signal mem_intfc0_n_451 : STD_LOGIC;
  signal mem_intfc0_n_452 : STD_LOGIC;
  signal mem_intfc0_n_453 : STD_LOGIC;
  signal mem_intfc0_n_454 : STD_LOGIC;
  signal mem_intfc0_n_455 : STD_LOGIC;
  signal mem_intfc0_n_456 : STD_LOGIC;
  signal mem_intfc0_n_457 : STD_LOGIC;
  signal mem_intfc0_n_458 : STD_LOGIC;
  signal mem_intfc0_n_459 : STD_LOGIC;
  signal mem_intfc0_n_460 : STD_LOGIC;
  signal mem_intfc0_n_461 : STD_LOGIC;
  signal mem_intfc0_n_462 : STD_LOGIC;
  signal mem_intfc0_n_463 : STD_LOGIC;
  signal mem_intfc0_n_464 : STD_LOGIC;
  signal mem_intfc0_n_465 : STD_LOGIC;
  signal mem_intfc0_n_466 : STD_LOGIC;
  signal mem_intfc0_n_467 : STD_LOGIC;
  signal mem_intfc0_n_468 : STD_LOGIC;
  signal mem_intfc0_n_469 : STD_LOGIC;
  signal mem_intfc0_n_470 : STD_LOGIC;
  signal mem_intfc0_n_471 : STD_LOGIC;
  signal mem_intfc0_n_472 : STD_LOGIC;
  signal mem_intfc0_n_473 : STD_LOGIC;
  signal mem_intfc0_n_474 : STD_LOGIC;
  signal mem_intfc0_n_475 : STD_LOGIC;
  signal mem_intfc0_n_476 : STD_LOGIC;
  signal mem_intfc0_n_477 : STD_LOGIC;
  signal mem_intfc0_n_478 : STD_LOGIC;
  signal mem_intfc0_n_479 : STD_LOGIC;
  signal mem_intfc0_n_480 : STD_LOGIC;
  signal mem_intfc0_n_481 : STD_LOGIC;
  signal mem_intfc0_n_482 : STD_LOGIC;
  signal mem_intfc0_n_483 : STD_LOGIC;
  signal mem_intfc0_n_484 : STD_LOGIC;
  signal mem_intfc0_n_485 : STD_LOGIC;
  signal mem_intfc0_n_486 : STD_LOGIC;
  signal mem_intfc0_n_487 : STD_LOGIC;
  signal mem_intfc0_n_488 : STD_LOGIC;
  signal mem_intfc0_n_489 : STD_LOGIC;
  signal mem_intfc0_n_490 : STD_LOGIC;
  signal mem_intfc0_n_491 : STD_LOGIC;
  signal mem_intfc0_n_492 : STD_LOGIC;
  signal mem_intfc0_n_493 : STD_LOGIC;
  signal mem_intfc0_n_494 : STD_LOGIC;
  signal mem_intfc0_n_495 : STD_LOGIC;
  signal mem_intfc0_n_496 : STD_LOGIC;
  signal mem_intfc0_n_497 : STD_LOGIC;
  signal mem_intfc0_n_498 : STD_LOGIC;
  signal mem_intfc0_n_499 : STD_LOGIC;
  signal mem_intfc0_n_500 : STD_LOGIC;
  signal mem_intfc0_n_501 : STD_LOGIC;
  signal mem_intfc0_n_502 : STD_LOGIC;
  signal mem_intfc0_n_503 : STD_LOGIC;
  signal mem_intfc0_n_504 : STD_LOGIC;
  signal mem_intfc0_n_505 : STD_LOGIC;
  signal mem_intfc0_n_506 : STD_LOGIC;
  signal mem_intfc0_n_507 : STD_LOGIC;
  signal mem_intfc0_n_508 : STD_LOGIC;
  signal mem_intfc0_n_509 : STD_LOGIC;
  signal mem_intfc0_n_510 : STD_LOGIC;
  signal mem_intfc0_n_511 : STD_LOGIC;
  signal mem_intfc0_n_512 : STD_LOGIC;
  signal mem_intfc0_n_513 : STD_LOGIC;
  signal mem_intfc0_n_514 : STD_LOGIC;
  signal mem_intfc0_n_515 : STD_LOGIC;
  signal mem_intfc0_n_516 : STD_LOGIC;
  signal mem_intfc0_n_517 : STD_LOGIC;
  signal mem_intfc0_n_518 : STD_LOGIC;
  signal mem_intfc0_n_519 : STD_LOGIC;
  signal mem_intfc0_n_520 : STD_LOGIC;
  signal mem_intfc0_n_521 : STD_LOGIC;
  signal mem_intfc0_n_522 : STD_LOGIC;
  signal mem_intfc0_n_523 : STD_LOGIC;
  signal mem_intfc0_n_524 : STD_LOGIC;
  signal mem_intfc0_n_525 : STD_LOGIC;
  signal mem_intfc0_n_526 : STD_LOGIC;
  signal mem_intfc0_n_527 : STD_LOGIC;
  signal mem_intfc0_n_528 : STD_LOGIC;
  signal mem_intfc0_n_529 : STD_LOGIC;
  signal mem_intfc0_n_530 : STD_LOGIC;
  signal mem_intfc0_n_531 : STD_LOGIC;
  signal mem_intfc0_n_532 : STD_LOGIC;
  signal mem_intfc0_n_533 : STD_LOGIC;
  signal mem_intfc0_n_534 : STD_LOGIC;
  signal mem_intfc0_n_535 : STD_LOGIC;
  signal mem_intfc0_n_536 : STD_LOGIC;
  signal mem_intfc0_n_537 : STD_LOGIC;
  signal mem_intfc0_n_538 : STD_LOGIC;
  signal mem_intfc0_n_539 : STD_LOGIC;
  signal mem_intfc0_n_540 : STD_LOGIC;
  signal mem_intfc0_n_541 : STD_LOGIC;
  signal mem_intfc0_n_542 : STD_LOGIC;
  signal mem_intfc0_n_543 : STD_LOGIC;
  signal mem_intfc0_n_544 : STD_LOGIC;
  signal mem_intfc0_n_545 : STD_LOGIC;
  signal mem_intfc0_n_546 : STD_LOGIC;
  signal mem_intfc0_n_547 : STD_LOGIC;
  signal mem_intfc0_n_548 : STD_LOGIC;
  signal mem_intfc0_n_549 : STD_LOGIC;
  signal mem_intfc0_n_550 : STD_LOGIC;
  signal mem_intfc0_n_551 : STD_LOGIC;
  signal mem_intfc0_n_552 : STD_LOGIC;
  signal mem_intfc0_n_553 : STD_LOGIC;
  signal mem_intfc0_n_554 : STD_LOGIC;
  signal mem_intfc0_n_555 : STD_LOGIC;
  signal mem_intfc0_n_556 : STD_LOGIC;
  signal mem_intfc0_n_557 : STD_LOGIC;
  signal mem_intfc0_n_558 : STD_LOGIC;
  signal mem_intfc0_n_559 : STD_LOGIC;
  signal mem_intfc0_n_56 : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of mem_intfc0_n_56 : signal is "50";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of mem_intfc0_n_56 : signal is "found";
  attribute syn_maxfan : string;
  attribute syn_maxfan of mem_intfc0_n_56 : signal is "10";
  signal mem_intfc0_n_560 : STD_LOGIC;
  signal mem_intfc0_n_561 : STD_LOGIC;
  signal mem_intfc0_n_562 : STD_LOGIC;
  signal mem_intfc0_n_563 : STD_LOGIC;
  signal mem_intfc0_n_564 : STD_LOGIC;
  signal mem_intfc0_n_565 : STD_LOGIC;
  signal mem_intfc0_n_566 : STD_LOGIC;
  signal mem_intfc0_n_567 : STD_LOGIC;
  signal mem_intfc0_n_568 : STD_LOGIC;
  signal mem_intfc0_n_569 : STD_LOGIC;
  signal mem_intfc0_n_57 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_57 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_57 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_57 : signal is "10";
  signal mem_intfc0_n_570 : STD_LOGIC;
  signal mem_intfc0_n_571 : STD_LOGIC;
  signal mem_intfc0_n_572 : STD_LOGIC;
  signal mem_intfc0_n_573 : STD_LOGIC;
  signal mem_intfc0_n_574 : STD_LOGIC;
  signal mem_intfc0_n_575 : STD_LOGIC;
  signal mem_intfc0_n_576 : STD_LOGIC;
  signal mem_intfc0_n_577 : STD_LOGIC;
  signal mem_intfc0_n_578 : STD_LOGIC;
  signal mem_intfc0_n_579 : STD_LOGIC;
  signal mem_intfc0_n_58 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_58 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_58 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_58 : signal is "10";
  signal mem_intfc0_n_580 : STD_LOGIC;
  signal mem_intfc0_n_581 : STD_LOGIC;
  signal mem_intfc0_n_582 : STD_LOGIC;
  signal mem_intfc0_n_583 : STD_LOGIC;
  signal mem_intfc0_n_584 : STD_LOGIC;
  signal mem_intfc0_n_585 : STD_LOGIC;
  signal mem_intfc0_n_586 : STD_LOGIC;
  signal mem_intfc0_n_59 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_59 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_59 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_59 : signal is "10";
  signal mem_intfc0_n_60 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_60 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_60 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_60 : signal is "10";
  signal mem_intfc0_n_61 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_61 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_61 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_61 : signal is "10";
  signal mem_intfc0_n_62 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_62 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_62 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_62 : signal is "10";
  signal mem_intfc0_n_63 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_63 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_63 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_63 : signal is "10";
  signal mem_intfc0_n_64 : STD_LOGIC;
  attribute MAX_FANOUT of mem_intfc0_n_64 : signal is "50";
  attribute RTL_MAX_FANOUT of mem_intfc0_n_64 : signal is "found";
  attribute syn_maxfan of mem_intfc0_n_64 : signal is "10";
  signal mem_intfc0_n_75 : STD_LOGIC;
  signal mem_intfc0_n_76 : STD_LOGIC;
  signal mem_intfc0_n_77 : STD_LOGIC;
  signal mem_intfc0_n_78 : STD_LOGIC;
  signal mem_intfc0_n_79 : STD_LOGIC;
  signal mem_intfc0_n_80 : STD_LOGIC;
  signal mem_intfc0_n_81 : STD_LOGIC;
  signal mem_intfc0_n_82 : STD_LOGIC;
  signal mem_intfc0_n_83 : STD_LOGIC;
  signal mem_intfc0_n_84 : STD_LOGIC;
  signal mem_intfc0_n_85 : STD_LOGIC;
  signal mem_intfc0_n_86 : STD_LOGIC;
  signal mem_intfc0_n_87 : STD_LOGIC;
  signal mem_intfc0_n_88 : STD_LOGIC;
  signal mem_intfc0_n_89 : STD_LOGIC;
  signal mem_intfc0_n_90 : STD_LOGIC;
  signal mem_intfc0_n_91 : STD_LOGIC;
  signal mem_intfc0_n_92 : STD_LOGIC;
  signal mem_intfc0_n_93 : STD_LOGIC;
  signal mem_intfc0_n_94 : STD_LOGIC;
  signal mem_intfc0_n_95 : STD_LOGIC;
  signal mem_intfc0_n_96 : STD_LOGIC;
  signal mem_intfc0_n_97 : STD_LOGIC;
  signal mem_intfc0_n_98 : STD_LOGIC;
  signal mem_intfc0_n_99 : STD_LOGIC;
  signal ram_init_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ram_init_done_r : STD_LOGIC;
  signal rd_data_addr : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rd_data_end : STD_LOGIC;
  signal rd_data_offset : STD_LOGIC;
  signal reset_reg_n_0 : STD_LOGIC;
  signal row : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal u_ui_top_n_3 : STD_LOGIC;
  signal u_ui_top_n_518 : STD_LOGIC;
  signal u_ui_top_n_519 : STD_LOGIC;
  signal u_ui_top_n_523 : STD_LOGIC;
  signal u_ui_top_n_538 : STD_LOGIC;
  signal u_ui_top_n_539 : STD_LOGIC;
  signal u_ui_top_n_540 : STD_LOGIC;
  signal u_ui_top_n_541 : STD_LOGIC;
  signal u_ui_top_n_542 : STD_LOGIC;
  signal u_ui_top_n_546 : STD_LOGIC;
  signal u_ui_top_n_547 : STD_LOGIC;
  signal \ui_rd_data0/not_strict_mode.app_rd_data_end_ns\ : STD_LOGIC;
  signal \ui_rd_data0/not_strict_mode.app_rd_data_ns\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \ui_rd_data0/not_strict_mode.bypass__0\ : STD_LOGIC;
  signal \ui_rd_data0/not_strict_mode.rd_buf_we\ : STD_LOGIC;
  signal \ui_rd_data0/not_strict_mode.rd_status\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \ui_rd_data0/p_100_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_101_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_102_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_103_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_104_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_105_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_106_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_107_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_108_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_109_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_10_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_110_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_111_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_112_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_113_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_114_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_115_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_116_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_117_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_118_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_119_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_11_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_120_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_121_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_122_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_123_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_124_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_125_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_126_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_127_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_128_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_129_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_12_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_130_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_131_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_132_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_133_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_134_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_135_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_136_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_137_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_138_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_139_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_13_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_140_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_141_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_142_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_143_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_144_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_145_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_146_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_147_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_148_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_149_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_14_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_150_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_151_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_152_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_153_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_154_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_155_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_156_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_157_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_158_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_159_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_15_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_160_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_161_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_162_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_163_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_164_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_165_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_166_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_167_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_168_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_169_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_16_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_170_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_171_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_172_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_173_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_174_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_175_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_176_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_177_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_178_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_179_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_17_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_180_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_181_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_182_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_183_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_184_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_185_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_186_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_187_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_188_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_189_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_18_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_190_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_191_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_192_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_193_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_194_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_195_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_196_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_197_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_198_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_199_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_19_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_200_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_201_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_202_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_203_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_204_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_205_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_206_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_207_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_208_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_209_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_20_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_210_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_211_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_212_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_213_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_214_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_215_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_216_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_217_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_218_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_219_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_21_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_220_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_221_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_222_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_223_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_224_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_225_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_226_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_227_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_228_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_229_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_22_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_230_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_231_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_232_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_233_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_234_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_235_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_236_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_237_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_238_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_239_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_23_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_240_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_241_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_242_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_243_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_244_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_245_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_246_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_247_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_248_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_249_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_24_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_250_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_251_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_252_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_253_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_254_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_256_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_257_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_258_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_25_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_26_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_27_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_28_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_29_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_30_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_31_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_32_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_33_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_34_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_35_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_36_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_37_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_38_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_39_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_3_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_40_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_41_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_42_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_43_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_44_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_45_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_46_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_47_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_48_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_49_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_4_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_50_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_51_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_52_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_53_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_54_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_55_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_56_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_57_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_58_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_59_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_5_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_60_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_61_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_62_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_63_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_64_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_65_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_66_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_67_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_68_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_69_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_6_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_70_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_71_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_72_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_73_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_74_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_75_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_76_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_77_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_78_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_79_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_7_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_80_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_81_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_82_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_83_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_84_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_85_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_86_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_87_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_88_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_89_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_8_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_90_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_91_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_92_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_93_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_94_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_95_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_96_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_97_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_98_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_99_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_rd_data0/p_9_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ui_wr_data0/pointer_ram.pointer_we\ : STD_LOGIC;
  signal use_addr : STD_LOGIC;
  signal wr_data : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal wr_data_addr : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wr_data_en : STD_LOGIC;
  signal wr_data_mask : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute syn_maxfan of reset_reg : label is "10";
begin
  app_rdy <= \^app_rdy\;
mem_intfc0: entity work.mig_7series_0_mig_7series_v2_3_mem_intfc
     port map (
      CLK => CLK,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      D(13 downto 0) => row(13 downto 0),
      DOA(1 downto 0) => \ui_rd_data0/p_258_out\(1 downto 0),
      DOB(1 downto 0) => \ui_rd_data0/p_257_out\(1 downto 0),
      DOC(1 downto 0) => \ui_rd_data0/p_256_out\(1 downto 0),
      E(0) => wr_data_en,
      Q(6) => rd_data_end,
      Q(5 downto 1) => rd_data_addr(4 downto 0),
      Q(0) => rd_data_offset,
      RST0 => RST0,
      S(0) => u_ui_top_n_523,
      SR(1 downto 0) => SR(1 downto 0),
      SS(0) => SS(0),
      accept_ns => accept_ns,
      \app_addr_r1_reg[23]\(0) => u_ui_top_n_538,
      \app_addr_r1_reg[23]_0\(0) => u_ui_top_n_539,
      \app_addr_r1_reg[23]_1\(0) => u_ui_top_n_540,
      \app_addr_r1_reg[26]\(2 downto 0) => bank(2 downto 0),
      \app_addr_r1_reg[9]\(9 downto 0) => col(9 downto 0),
      app_rdy_r_reg => \^app_rdy\,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1_0 => bm_end_r1_0,
      bm_end_r1_1 => bm_end_r1_1,
      bm_end_r1_reg => bm_end_r1_reg,
      bm_end_r1_reg_0 => bm_end_r1_reg_0,
      bm_end_r1_reg_1 => bm_end_r1_reg_1,
      bm_end_r1_reg_2 => bm_end_r1_reg_2,
      clear => clear,
      cmd(1 downto 0) => cmd(1 downto 0),
      \cmd_pipe_plus.mc_address_reg[41]\(10 downto 9) => \mc0/bank_mach0/req_row_r\(55 downto 54),
      \cmd_pipe_plus.mc_address_reg[41]\(8 downto 7) => \mc0/bank_mach0/req_row_r\(41 downto 40),
      \cmd_pipe_plus.mc_address_reg[41]\(6 downto 5) => \mc0/bank_mach0/req_row_r\(27 downto 26),
      \cmd_pipe_plus.mc_address_reg[41]\(4 downto 2) => \mc0/bank_mach0/req_row_r\(19 downto 17),
      \cmd_pipe_plus.mc_address_reg[41]\(1 downto 0) => \mc0/bank_mach0/req_row_r\(13 downto 12),
      \cmd_pipe_plus.mc_bank_reg[8]\(8 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 3),
      \complex_row1_rd_cnt_reg[1]\ => prbs_rdlvl_done_pulse,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \device_temp_r_reg[11]\(11 downto 0) => D(11 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\,
      dqs_po_en_stg2_f_reg => po_cnt_dec,
      \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ => \en_cnt_div4.enable_wrlvl_cnt_reg[3]\,
      fine_dly_dec_done_r1_reg => pi_cnt_dec,
      freq_refclk => freq_refclk,
      idelay_tap_limit_r_reg => idelay_tap_limit_r_reg,
      in0 => in0,
      init_calib_complete => init_calib_complete,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      mem_refclk => mem_refclk,
      \my_empty_reg[7]\ => mem_intfc0_n_56,
      \my_empty_reg[7]_0\ => mem_intfc0_n_57,
      \my_empty_reg[7]_1\ => mem_intfc0_n_58,
      \my_empty_reg[7]_2\ => mem_intfc0_n_59,
      \my_empty_reg[7]_3\ => mem_intfc0_n_60,
      \my_empty_reg[7]_4\ => mem_intfc0_n_61,
      \my_empty_reg[7]_5\ => mem_intfc0_n_62,
      \my_empty_reg[7]_6\ => mem_intfc0_n_63,
      \my_empty_reg[7]_7\ => mem_intfc0_n_64,
      new_cnt_cpt_r_reg(0) => new_cnt_cpt_r_reg(0),
      \not_strict_mode.app_rd_data_end_ns\ => \ui_rd_data0/not_strict_mode.app_rd_data_end_ns\,
      \not_strict_mode.app_rd_data_reg[0]\ => mem_intfc0_n_78,
      \not_strict_mode.app_rd_data_reg[100]\ => mem_intfc0_n_174,
      \not_strict_mode.app_rd_data_reg[101]\ => mem_intfc0_n_182,
      \not_strict_mode.app_rd_data_reg[102]\ => mem_intfc0_n_190,
      \not_strict_mode.app_rd_data_reg[103]\ => mem_intfc0_n_198,
      \not_strict_mode.app_rd_data_reg[104]\ => mem_intfc0_n_139,
      \not_strict_mode.app_rd_data_reg[105]\ => mem_intfc0_n_147,
      \not_strict_mode.app_rd_data_reg[106]\ => mem_intfc0_n_155,
      \not_strict_mode.app_rd_data_reg[107]\ => mem_intfc0_n_167,
      \not_strict_mode.app_rd_data_reg[108]\ => mem_intfc0_n_171,
      \not_strict_mode.app_rd_data_reg[109]\ => mem_intfc0_n_179,
      \not_strict_mode.app_rd_data_reg[10]\ => mem_intfc0_n_95,
      \not_strict_mode.app_rd_data_reg[110]\ => mem_intfc0_n_187,
      \not_strict_mode.app_rd_data_reg[111]\ => mem_intfc0_n_195,
      \not_strict_mode.app_rd_data_reg[112]\ => mem_intfc0_n_140,
      \not_strict_mode.app_rd_data_reg[113]\ => mem_intfc0_n_148,
      \not_strict_mode.app_rd_data_reg[114]\ => mem_intfc0_n_156,
      \not_strict_mode.app_rd_data_reg[115]\ => mem_intfc0_n_168,
      \not_strict_mode.app_rd_data_reg[116]\ => mem_intfc0_n_172,
      \not_strict_mode.app_rd_data_reg[117]\ => mem_intfc0_n_180,
      \not_strict_mode.app_rd_data_reg[118]\ => mem_intfc0_n_188,
      \not_strict_mode.app_rd_data_reg[119]\ => mem_intfc0_n_196,
      \not_strict_mode.app_rd_data_reg[11]\ => mem_intfc0_n_103,
      \not_strict_mode.app_rd_data_reg[120]\ => mem_intfc0_n_145,
      \not_strict_mode.app_rd_data_reg[121]\ => mem_intfc0_n_153,
      \not_strict_mode.app_rd_data_reg[122]\ => mem_intfc0_n_161,
      \not_strict_mode.app_rd_data_reg[123]\ => mem_intfc0_n_165,
      \not_strict_mode.app_rd_data_reg[124]\ => mem_intfc0_n_177,
      \not_strict_mode.app_rd_data_reg[125]\ => mem_intfc0_n_185,
      \not_strict_mode.app_rd_data_reg[126]\ => mem_intfc0_n_193,
      \not_strict_mode.app_rd_data_reg[127]\ => mem_intfc0_n_201,
      \not_strict_mode.app_rd_data_reg[128]\ => mem_intfc0_n_210,
      \not_strict_mode.app_rd_data_reg[129]\ => mem_intfc0_n_218,
      \not_strict_mode.app_rd_data_reg[12]\ => mem_intfc0_n_111,
      \not_strict_mode.app_rd_data_reg[130]\ => mem_intfc0_n_226,
      \not_strict_mode.app_rd_data_reg[131]\ => mem_intfc0_n_234,
      \not_strict_mode.app_rd_data_reg[132]\ => mem_intfc0_n_242,
      \not_strict_mode.app_rd_data_reg[133]\ => mem_intfc0_n_246,
      \not_strict_mode.app_rd_data_reg[134]\ => mem_intfc0_n_254,
      \not_strict_mode.app_rd_data_reg[135]\ => mem_intfc0_n_262,
      \not_strict_mode.app_rd_data_reg[136]\ => mem_intfc0_n_207,
      \not_strict_mode.app_rd_data_reg[137]\ => mem_intfc0_n_215,
      \not_strict_mode.app_rd_data_reg[138]\ => mem_intfc0_n_223,
      \not_strict_mode.app_rd_data_reg[139]\ => mem_intfc0_n_231,
      \not_strict_mode.app_rd_data_reg[13]\ => mem_intfc0_n_119,
      \not_strict_mode.app_rd_data_reg[140]\ => mem_intfc0_n_239,
      \not_strict_mode.app_rd_data_reg[141]\ => mem_intfc0_n_243,
      \not_strict_mode.app_rd_data_reg[142]\ => mem_intfc0_n_251,
      \not_strict_mode.app_rd_data_reg[143]\ => mem_intfc0_n_259,
      \not_strict_mode.app_rd_data_reg[144]\ => mem_intfc0_n_208,
      \not_strict_mode.app_rd_data_reg[145]\ => mem_intfc0_n_216,
      \not_strict_mode.app_rd_data_reg[146]\ => mem_intfc0_n_224,
      \not_strict_mode.app_rd_data_reg[147]\ => mem_intfc0_n_232,
      \not_strict_mode.app_rd_data_reg[148]\ => mem_intfc0_n_240,
      \not_strict_mode.app_rd_data_reg[149]\ => mem_intfc0_n_244,
      \not_strict_mode.app_rd_data_reg[14]\ => mem_intfc0_n_127,
      \not_strict_mode.app_rd_data_reg[150]\ => mem_intfc0_n_252,
      \not_strict_mode.app_rd_data_reg[151]\ => mem_intfc0_n_260,
      \not_strict_mode.app_rd_data_reg[152]\ => mem_intfc0_n_205,
      \not_strict_mode.app_rd_data_reg[153]\ => mem_intfc0_n_213,
      \not_strict_mode.app_rd_data_reg[154]\ => mem_intfc0_n_221,
      \not_strict_mode.app_rd_data_reg[155]\ => mem_intfc0_n_229,
      \not_strict_mode.app_rd_data_reg[156]\ => mem_intfc0_n_237,
      \not_strict_mode.app_rd_data_reg[157]\ => mem_intfc0_n_249,
      \not_strict_mode.app_rd_data_reg[158]\ => mem_intfc0_n_257,
      \not_strict_mode.app_rd_data_reg[159]\ => mem_intfc0_n_265,
      \not_strict_mode.app_rd_data_reg[15]\ => mem_intfc0_n_135,
      \not_strict_mode.app_rd_data_reg[160]\ => mem_intfc0_n_206,
      \not_strict_mode.app_rd_data_reg[161]\ => mem_intfc0_n_214,
      \not_strict_mode.app_rd_data_reg[162]\ => mem_intfc0_n_222,
      \not_strict_mode.app_rd_data_reg[163]\ => mem_intfc0_n_230,
      \not_strict_mode.app_rd_data_reg[164]\ => mem_intfc0_n_238,
      \not_strict_mode.app_rd_data_reg[165]\ => mem_intfc0_n_250,
      \not_strict_mode.app_rd_data_reg[166]\ => mem_intfc0_n_258,
      \not_strict_mode.app_rd_data_reg[167]\ => mem_intfc0_n_266,
      \not_strict_mode.app_rd_data_reg[168]\ => mem_intfc0_n_203,
      \not_strict_mode.app_rd_data_reg[169]\ => mem_intfc0_n_211,
      \not_strict_mode.app_rd_data_reg[16]\ => mem_intfc0_n_76,
      \not_strict_mode.app_rd_data_reg[170]\ => mem_intfc0_n_219,
      \not_strict_mode.app_rd_data_reg[171]\ => mem_intfc0_n_227,
      \not_strict_mode.app_rd_data_reg[172]\ => mem_intfc0_n_235,
      \not_strict_mode.app_rd_data_reg[173]\ => mem_intfc0_n_247,
      \not_strict_mode.app_rd_data_reg[174]\ => mem_intfc0_n_255,
      \not_strict_mode.app_rd_data_reg[175]\ => mem_intfc0_n_263,
      \not_strict_mode.app_rd_data_reg[176]\ => mem_intfc0_n_204,
      \not_strict_mode.app_rd_data_reg[177]\ => mem_intfc0_n_212,
      \not_strict_mode.app_rd_data_reg[178]\ => mem_intfc0_n_220,
      \not_strict_mode.app_rd_data_reg[179]\ => mem_intfc0_n_228,
      \not_strict_mode.app_rd_data_reg[17]\ => mem_intfc0_n_84,
      \not_strict_mode.app_rd_data_reg[180]\ => mem_intfc0_n_236,
      \not_strict_mode.app_rd_data_reg[181]\ => mem_intfc0_n_248,
      \not_strict_mode.app_rd_data_reg[182]\ => mem_intfc0_n_256,
      \not_strict_mode.app_rd_data_reg[183]\ => mem_intfc0_n_264,
      \not_strict_mode.app_rd_data_reg[184]\ => mem_intfc0_n_209,
      \not_strict_mode.app_rd_data_reg[185]\ => mem_intfc0_n_217,
      \not_strict_mode.app_rd_data_reg[186]\ => mem_intfc0_n_225,
      \not_strict_mode.app_rd_data_reg[187]\ => mem_intfc0_n_233,
      \not_strict_mode.app_rd_data_reg[188]\ => mem_intfc0_n_241,
      \not_strict_mode.app_rd_data_reg[189]\ => mem_intfc0_n_245,
      \not_strict_mode.app_rd_data_reg[18]\ => mem_intfc0_n_96,
      \not_strict_mode.app_rd_data_reg[190]\ => mem_intfc0_n_253,
      \not_strict_mode.app_rd_data_reg[191]\ => mem_intfc0_n_261,
      \not_strict_mode.app_rd_data_reg[192]\ => mem_intfc0_n_274,
      \not_strict_mode.app_rd_data_reg[193]\ => mem_intfc0_n_282,
      \not_strict_mode.app_rd_data_reg[194]\ => mem_intfc0_n_290,
      \not_strict_mode.app_rd_data_reg[195]\ => mem_intfc0_n_294,
      \not_strict_mode.app_rd_data_reg[196]\ => mem_intfc0_n_306,
      \not_strict_mode.app_rd_data_reg[197]\ => mem_intfc0_n_314,
      \not_strict_mode.app_rd_data_reg[198]\ => mem_intfc0_n_322,
      \not_strict_mode.app_rd_data_reg[199]\ => mem_intfc0_n_326,
      \not_strict_mode.app_rd_data_reg[19]\ => mem_intfc0_n_104,
      \not_strict_mode.app_rd_data_reg[1]\ => mem_intfc0_n_86,
      \not_strict_mode.app_rd_data_reg[200]\ => mem_intfc0_n_271,
      \not_strict_mode.app_rd_data_reg[201]\ => mem_intfc0_n_279,
      \not_strict_mode.app_rd_data_reg[202]\ => mem_intfc0_n_287,
      \not_strict_mode.app_rd_data_reg[203]\ => mem_intfc0_n_291,
      \not_strict_mode.app_rd_data_reg[204]\ => mem_intfc0_n_303,
      \not_strict_mode.app_rd_data_reg[205]\ => mem_intfc0_n_311,
      \not_strict_mode.app_rd_data_reg[206]\ => mem_intfc0_n_319,
      \not_strict_mode.app_rd_data_reg[207]\ => mem_intfc0_n_323,
      \not_strict_mode.app_rd_data_reg[208]\ => mem_intfc0_n_272,
      \not_strict_mode.app_rd_data_reg[209]\ => mem_intfc0_n_280,
      \not_strict_mode.app_rd_data_reg[20]\ => mem_intfc0_n_112,
      \not_strict_mode.app_rd_data_reg[210]\ => mem_intfc0_n_288,
      \not_strict_mode.app_rd_data_reg[211]\ => mem_intfc0_n_292,
      \not_strict_mode.app_rd_data_reg[212]\ => mem_intfc0_n_304,
      \not_strict_mode.app_rd_data_reg[213]\ => mem_intfc0_n_312,
      \not_strict_mode.app_rd_data_reg[214]\ => mem_intfc0_n_320,
      \not_strict_mode.app_rd_data_reg[215]\ => mem_intfc0_n_324,
      \not_strict_mode.app_rd_data_reg[216]\ => mem_intfc0_n_269,
      \not_strict_mode.app_rd_data_reg[217]\ => mem_intfc0_n_277,
      \not_strict_mode.app_rd_data_reg[218]\ => mem_intfc0_n_285,
      \not_strict_mode.app_rd_data_reg[219]\ => mem_intfc0_n_297,
      \not_strict_mode.app_rd_data_reg[21]\ => mem_intfc0_n_120,
      \not_strict_mode.app_rd_data_reg[220]\ => mem_intfc0_n_301,
      \not_strict_mode.app_rd_data_reg[221]\ => mem_intfc0_n_309,
      \not_strict_mode.app_rd_data_reg[222]\ => mem_intfc0_n_317,
      \not_strict_mode.app_rd_data_reg[223]\ => mem_intfc0_n_329,
      \not_strict_mode.app_rd_data_reg[224]\ => mem_intfc0_n_270,
      \not_strict_mode.app_rd_data_reg[225]\ => mem_intfc0_n_278,
      \not_strict_mode.app_rd_data_reg[226]\ => mem_intfc0_n_286,
      \not_strict_mode.app_rd_data_reg[227]\ => mem_intfc0_n_298,
      \not_strict_mode.app_rd_data_reg[228]\ => mem_intfc0_n_302,
      \not_strict_mode.app_rd_data_reg[229]\ => mem_intfc0_n_310,
      \not_strict_mode.app_rd_data_reg[22]\ => mem_intfc0_n_128,
      \not_strict_mode.app_rd_data_reg[230]\ => mem_intfc0_n_318,
      \not_strict_mode.app_rd_data_reg[231]\ => mem_intfc0_n_330,
      \not_strict_mode.app_rd_data_reg[232]\ => mem_intfc0_n_267,
      \not_strict_mode.app_rd_data_reg[233]\ => mem_intfc0_n_275,
      \not_strict_mode.app_rd_data_reg[234]\ => mem_intfc0_n_283,
      \not_strict_mode.app_rd_data_reg[235]\ => mem_intfc0_n_295,
      \not_strict_mode.app_rd_data_reg[236]\ => mem_intfc0_n_299,
      \not_strict_mode.app_rd_data_reg[237]\ => mem_intfc0_n_307,
      \not_strict_mode.app_rd_data_reg[238]\ => mem_intfc0_n_315,
      \not_strict_mode.app_rd_data_reg[239]\ => mem_intfc0_n_327,
      \not_strict_mode.app_rd_data_reg[23]\ => mem_intfc0_n_136,
      \not_strict_mode.app_rd_data_reg[240]\ => mem_intfc0_n_268,
      \not_strict_mode.app_rd_data_reg[241]\ => mem_intfc0_n_276,
      \not_strict_mode.app_rd_data_reg[242]\ => mem_intfc0_n_284,
      \not_strict_mode.app_rd_data_reg[243]\ => mem_intfc0_n_296,
      \not_strict_mode.app_rd_data_reg[244]\ => mem_intfc0_n_300,
      \not_strict_mode.app_rd_data_reg[245]\ => mem_intfc0_n_308,
      \not_strict_mode.app_rd_data_reg[246]\ => mem_intfc0_n_316,
      \not_strict_mode.app_rd_data_reg[247]\ => mem_intfc0_n_328,
      \not_strict_mode.app_rd_data_reg[248]\ => mem_intfc0_n_273,
      \not_strict_mode.app_rd_data_reg[249]\ => mem_intfc0_n_281,
      \not_strict_mode.app_rd_data_reg[24]\ => mem_intfc0_n_81,
      \not_strict_mode.app_rd_data_reg[250]\ => mem_intfc0_n_289,
      \not_strict_mode.app_rd_data_reg[251]\ => mem_intfc0_n_293,
      \not_strict_mode.app_rd_data_reg[252]\ => mem_intfc0_n_305,
      \not_strict_mode.app_rd_data_reg[253]\ => mem_intfc0_n_313,
      \not_strict_mode.app_rd_data_reg[254]\ => mem_intfc0_n_321,
      \not_strict_mode.app_rd_data_reg[255]\ => mem_intfc0_n_325,
      \not_strict_mode.app_rd_data_reg[256]\ => mem_intfc0_n_338,
      \not_strict_mode.app_rd_data_reg[257]\ => mem_intfc0_n_342,
      \not_strict_mode.app_rd_data_reg[258]\ => mem_intfc0_n_354,
      \not_strict_mode.app_rd_data_reg[259]\ => mem_intfc0_n_362,
      \not_strict_mode.app_rd_data_reg[25]\ => mem_intfc0_n_89,
      \not_strict_mode.app_rd_data_reg[260]\ => mem_intfc0_n_370,
      \not_strict_mode.app_rd_data_reg[261]\ => mem_intfc0_n_378,
      \not_strict_mode.app_rd_data_reg[262]\ => mem_intfc0_n_382,
      \not_strict_mode.app_rd_data_reg[263]\ => mem_intfc0_n_394,
      \not_strict_mode.app_rd_data_reg[264]\ => mem_intfc0_n_335,
      \not_strict_mode.app_rd_data_reg[265]\ => mem_intfc0_n_339,
      \not_strict_mode.app_rd_data_reg[266]\ => mem_intfc0_n_351,
      \not_strict_mode.app_rd_data_reg[267]\ => mem_intfc0_n_359,
      \not_strict_mode.app_rd_data_reg[268]\ => mem_intfc0_n_367,
      \not_strict_mode.app_rd_data_reg[269]\ => mem_intfc0_n_375,
      \not_strict_mode.app_rd_data_reg[26]\ => mem_intfc0_n_93,
      \not_strict_mode.app_rd_data_reg[270]\ => mem_intfc0_n_379,
      \not_strict_mode.app_rd_data_reg[271]\ => mem_intfc0_n_391,
      \not_strict_mode.app_rd_data_reg[272]\ => mem_intfc0_n_336,
      \not_strict_mode.app_rd_data_reg[273]\ => mem_intfc0_n_340,
      \not_strict_mode.app_rd_data_reg[274]\ => mem_intfc0_n_352,
      \not_strict_mode.app_rd_data_reg[275]\ => mem_intfc0_n_360,
      \not_strict_mode.app_rd_data_reg[276]\ => mem_intfc0_n_368,
      \not_strict_mode.app_rd_data_reg[277]\ => mem_intfc0_n_376,
      \not_strict_mode.app_rd_data_reg[278]\ => mem_intfc0_n_380,
      \not_strict_mode.app_rd_data_reg[279]\ => mem_intfc0_n_392,
      \not_strict_mode.app_rd_data_reg[27]\ => mem_intfc0_n_101,
      \not_strict_mode.app_rd_data_reg[280]\ => mem_intfc0_n_333,
      \not_strict_mode.app_rd_data_reg[281]\ => mem_intfc0_n_345,
      \not_strict_mode.app_rd_data_reg[282]\ => mem_intfc0_n_349,
      \not_strict_mode.app_rd_data_reg[283]\ => mem_intfc0_n_357,
      \not_strict_mode.app_rd_data_reg[284]\ => mem_intfc0_n_365,
      \not_strict_mode.app_rd_data_reg[285]\ => mem_intfc0_n_373,
      \not_strict_mode.app_rd_data_reg[286]\ => mem_intfc0_n_385,
      \not_strict_mode.app_rd_data_reg[287]\ => mem_intfc0_n_389,
      \not_strict_mode.app_rd_data_reg[288]\ => mem_intfc0_n_334,
      \not_strict_mode.app_rd_data_reg[289]\ => mem_intfc0_n_346,
      \not_strict_mode.app_rd_data_reg[28]\ => mem_intfc0_n_109,
      \not_strict_mode.app_rd_data_reg[290]\ => mem_intfc0_n_350,
      \not_strict_mode.app_rd_data_reg[291]\ => mem_intfc0_n_358,
      \not_strict_mode.app_rd_data_reg[292]\ => mem_intfc0_n_366,
      \not_strict_mode.app_rd_data_reg[293]\ => mem_intfc0_n_374,
      \not_strict_mode.app_rd_data_reg[294]\ => mem_intfc0_n_386,
      \not_strict_mode.app_rd_data_reg[295]\ => mem_intfc0_n_390,
      \not_strict_mode.app_rd_data_reg[296]\ => mem_intfc0_n_331,
      \not_strict_mode.app_rd_data_reg[297]\ => mem_intfc0_n_343,
      \not_strict_mode.app_rd_data_reg[298]\ => mem_intfc0_n_347,
      \not_strict_mode.app_rd_data_reg[299]\ => mem_intfc0_n_355,
      \not_strict_mode.app_rd_data_reg[29]\ => mem_intfc0_n_117,
      \not_strict_mode.app_rd_data_reg[2]\ => mem_intfc0_n_98,
      \not_strict_mode.app_rd_data_reg[300]\ => mem_intfc0_n_363,
      \not_strict_mode.app_rd_data_reg[301]\ => mem_intfc0_n_371,
      \not_strict_mode.app_rd_data_reg[302]\ => mem_intfc0_n_383,
      \not_strict_mode.app_rd_data_reg[303]\ => mem_intfc0_n_387,
      \not_strict_mode.app_rd_data_reg[304]\ => mem_intfc0_n_332,
      \not_strict_mode.app_rd_data_reg[305]\ => mem_intfc0_n_344,
      \not_strict_mode.app_rd_data_reg[306]\ => mem_intfc0_n_348,
      \not_strict_mode.app_rd_data_reg[307]\ => mem_intfc0_n_356,
      \not_strict_mode.app_rd_data_reg[308]\ => mem_intfc0_n_364,
      \not_strict_mode.app_rd_data_reg[309]\ => mem_intfc0_n_372,
      \not_strict_mode.app_rd_data_reg[30]\ => mem_intfc0_n_125,
      \not_strict_mode.app_rd_data_reg[310]\ => mem_intfc0_n_384,
      \not_strict_mode.app_rd_data_reg[311]\ => mem_intfc0_n_388,
      \not_strict_mode.app_rd_data_reg[312]\ => mem_intfc0_n_337,
      \not_strict_mode.app_rd_data_reg[313]\ => mem_intfc0_n_341,
      \not_strict_mode.app_rd_data_reg[314]\ => mem_intfc0_n_353,
      \not_strict_mode.app_rd_data_reg[315]\ => mem_intfc0_n_361,
      \not_strict_mode.app_rd_data_reg[316]\ => mem_intfc0_n_369,
      \not_strict_mode.app_rd_data_reg[317]\ => mem_intfc0_n_377,
      \not_strict_mode.app_rd_data_reg[318]\ => mem_intfc0_n_381,
      \not_strict_mode.app_rd_data_reg[319]\ => mem_intfc0_n_393,
      \not_strict_mode.app_rd_data_reg[31]\ => mem_intfc0_n_133,
      \not_strict_mode.app_rd_data_reg[320]\ => mem_intfc0_n_402,
      \not_strict_mode.app_rd_data_reg[321]\ => mem_intfc0_n_410,
      \not_strict_mode.app_rd_data_reg[322]\ => mem_intfc0_n_418,
      \not_strict_mode.app_rd_data_reg[323]\ => mem_intfc0_n_422,
      \not_strict_mode.app_rd_data_reg[324]\ => mem_intfc0_n_434,
      \not_strict_mode.app_rd_data_reg[325]\ => mem_intfc0_n_438,
      \not_strict_mode.app_rd_data_reg[326]\ => mem_intfc0_n_450,
      \not_strict_mode.app_rd_data_reg[327]\ => mem_intfc0_n_454,
      \not_strict_mode.app_rd_data_reg[328]\ => mem_intfc0_n_399,
      \not_strict_mode.app_rd_data_reg[329]\ => mem_intfc0_n_407,
      \not_strict_mode.app_rd_data_reg[32]\ => mem_intfc0_n_82,
      \not_strict_mode.app_rd_data_reg[330]\ => mem_intfc0_n_415,
      \not_strict_mode.app_rd_data_reg[331]\ => mem_intfc0_n_419,
      \not_strict_mode.app_rd_data_reg[332]\ => mem_intfc0_n_431,
      \not_strict_mode.app_rd_data_reg[333]\ => mem_intfc0_n_435,
      \not_strict_mode.app_rd_data_reg[334]\ => mem_intfc0_n_447,
      \not_strict_mode.app_rd_data_reg[335]\ => mem_intfc0_n_451,
      \not_strict_mode.app_rd_data_reg[336]\ => mem_intfc0_n_400,
      \not_strict_mode.app_rd_data_reg[337]\ => mem_intfc0_n_408,
      \not_strict_mode.app_rd_data_reg[338]\ => mem_intfc0_n_416,
      \not_strict_mode.app_rd_data_reg[339]\ => mem_intfc0_n_420,
      \not_strict_mode.app_rd_data_reg[33]\ => mem_intfc0_n_90,
      \not_strict_mode.app_rd_data_reg[340]\ => mem_intfc0_n_432,
      \not_strict_mode.app_rd_data_reg[341]\ => mem_intfc0_n_436,
      \not_strict_mode.app_rd_data_reg[342]\ => mem_intfc0_n_448,
      \not_strict_mode.app_rd_data_reg[343]\ => mem_intfc0_n_452,
      \not_strict_mode.app_rd_data_reg[344]\ => mem_intfc0_n_397,
      \not_strict_mode.app_rd_data_reg[345]\ => mem_intfc0_n_405,
      \not_strict_mode.app_rd_data_reg[346]\ => mem_intfc0_n_413,
      \not_strict_mode.app_rd_data_reg[347]\ => mem_intfc0_n_425,
      \not_strict_mode.app_rd_data_reg[348]\ => mem_intfc0_n_429,
      \not_strict_mode.app_rd_data_reg[349]\ => mem_intfc0_n_441,
      \not_strict_mode.app_rd_data_reg[34]\ => mem_intfc0_n_94,
      \not_strict_mode.app_rd_data_reg[350]\ => mem_intfc0_n_445,
      \not_strict_mode.app_rd_data_reg[351]\ => mem_intfc0_n_457,
      \not_strict_mode.app_rd_data_reg[352]\ => mem_intfc0_n_398,
      \not_strict_mode.app_rd_data_reg[353]\ => mem_intfc0_n_406,
      \not_strict_mode.app_rd_data_reg[354]\ => mem_intfc0_n_414,
      \not_strict_mode.app_rd_data_reg[355]\ => mem_intfc0_n_426,
      \not_strict_mode.app_rd_data_reg[356]\ => mem_intfc0_n_430,
      \not_strict_mode.app_rd_data_reg[357]\ => mem_intfc0_n_442,
      \not_strict_mode.app_rd_data_reg[358]\ => mem_intfc0_n_446,
      \not_strict_mode.app_rd_data_reg[359]\ => mem_intfc0_n_458,
      \not_strict_mode.app_rd_data_reg[35]\ => mem_intfc0_n_102,
      \not_strict_mode.app_rd_data_reg[360]\ => mem_intfc0_n_395,
      \not_strict_mode.app_rd_data_reg[361]\ => mem_intfc0_n_403,
      \not_strict_mode.app_rd_data_reg[362]\ => mem_intfc0_n_411,
      \not_strict_mode.app_rd_data_reg[363]\ => mem_intfc0_n_423,
      \not_strict_mode.app_rd_data_reg[364]\ => mem_intfc0_n_427,
      \not_strict_mode.app_rd_data_reg[365]\ => mem_intfc0_n_439,
      \not_strict_mode.app_rd_data_reg[366]\ => mem_intfc0_n_443,
      \not_strict_mode.app_rd_data_reg[367]\ => mem_intfc0_n_455,
      \not_strict_mode.app_rd_data_reg[368]\ => mem_intfc0_n_396,
      \not_strict_mode.app_rd_data_reg[369]\ => mem_intfc0_n_404,
      \not_strict_mode.app_rd_data_reg[36]\ => mem_intfc0_n_110,
      \not_strict_mode.app_rd_data_reg[370]\ => mem_intfc0_n_412,
      \not_strict_mode.app_rd_data_reg[371]\ => mem_intfc0_n_424,
      \not_strict_mode.app_rd_data_reg[372]\ => mem_intfc0_n_428,
      \not_strict_mode.app_rd_data_reg[373]\ => mem_intfc0_n_440,
      \not_strict_mode.app_rd_data_reg[374]\ => mem_intfc0_n_444,
      \not_strict_mode.app_rd_data_reg[375]\ => mem_intfc0_n_456,
      \not_strict_mode.app_rd_data_reg[376]\ => mem_intfc0_n_401,
      \not_strict_mode.app_rd_data_reg[377]\ => mem_intfc0_n_409,
      \not_strict_mode.app_rd_data_reg[378]\ => mem_intfc0_n_417,
      \not_strict_mode.app_rd_data_reg[379]\ => mem_intfc0_n_421,
      \not_strict_mode.app_rd_data_reg[37]\ => mem_intfc0_n_118,
      \not_strict_mode.app_rd_data_reg[380]\ => mem_intfc0_n_433,
      \not_strict_mode.app_rd_data_reg[381]\ => mem_intfc0_n_437,
      \not_strict_mode.app_rd_data_reg[382]\ => mem_intfc0_n_449,
      \not_strict_mode.app_rd_data_reg[383]\ => mem_intfc0_n_453,
      \not_strict_mode.app_rd_data_reg[384]\ => mem_intfc0_n_462,
      \not_strict_mode.app_rd_data_reg[385]\ => mem_intfc0_n_470,
      \not_strict_mode.app_rd_data_reg[386]\ => mem_intfc0_n_482,
      \not_strict_mode.app_rd_data_reg[387]\ => mem_intfc0_n_490,
      \not_strict_mode.app_rd_data_reg[388]\ => mem_intfc0_n_498,
      \not_strict_mode.app_rd_data_reg[389]\ => mem_intfc0_n_506,
      \not_strict_mode.app_rd_data_reg[38]\ => mem_intfc0_n_126,
      \not_strict_mode.app_rd_data_reg[390]\ => mem_intfc0_n_514,
      \not_strict_mode.app_rd_data_reg[391]\ => mem_intfc0_n_522,
      \not_strict_mode.app_rd_data_reg[392]\ => mem_intfc0_n_459,
      \not_strict_mode.app_rd_data_reg[393]\ => mem_intfc0_n_467,
      \not_strict_mode.app_rd_data_reg[394]\ => mem_intfc0_n_479,
      \not_strict_mode.app_rd_data_reg[395]\ => mem_intfc0_n_487,
      \not_strict_mode.app_rd_data_reg[396]\ => mem_intfc0_n_495,
      \not_strict_mode.app_rd_data_reg[397]\ => mem_intfc0_n_503,
      \not_strict_mode.app_rd_data_reg[398]\ => mem_intfc0_n_511,
      \not_strict_mode.app_rd_data_reg[399]\ => mem_intfc0_n_519,
      \not_strict_mode.app_rd_data_reg[39]\ => mem_intfc0_n_134,
      \not_strict_mode.app_rd_data_reg[3]\ => mem_intfc0_n_106,
      \not_strict_mode.app_rd_data_reg[400]\ => mem_intfc0_n_460,
      \not_strict_mode.app_rd_data_reg[401]\ => mem_intfc0_n_468,
      \not_strict_mode.app_rd_data_reg[402]\ => mem_intfc0_n_480,
      \not_strict_mode.app_rd_data_reg[403]\ => mem_intfc0_n_488,
      \not_strict_mode.app_rd_data_reg[404]\ => mem_intfc0_n_496,
      \not_strict_mode.app_rd_data_reg[405]\ => mem_intfc0_n_504,
      \not_strict_mode.app_rd_data_reg[406]\ => mem_intfc0_n_512,
      \not_strict_mode.app_rd_data_reg[407]\ => mem_intfc0_n_520,
      \not_strict_mode.app_rd_data_reg[408]\ => mem_intfc0_n_465,
      \not_strict_mode.app_rd_data_reg[409]\ => mem_intfc0_n_473,
      \not_strict_mode.app_rd_data_reg[40]\ => mem_intfc0_n_79,
      \not_strict_mode.app_rd_data_reg[410]\ => mem_intfc0_n_477,
      \not_strict_mode.app_rd_data_reg[411]\ => mem_intfc0_n_485,
      \not_strict_mode.app_rd_data_reg[412]\ => mem_intfc0_n_493,
      \not_strict_mode.app_rd_data_reg[413]\ => mem_intfc0_n_501,
      \not_strict_mode.app_rd_data_reg[414]\ => mem_intfc0_n_509,
      \not_strict_mode.app_rd_data_reg[415]\ => mem_intfc0_n_517,
      \not_strict_mode.app_rd_data_reg[416]\ => mem_intfc0_n_466,
      \not_strict_mode.app_rd_data_reg[417]\ => mem_intfc0_n_474,
      \not_strict_mode.app_rd_data_reg[418]\ => mem_intfc0_n_478,
      \not_strict_mode.app_rd_data_reg[419]\ => mem_intfc0_n_486,
      \not_strict_mode.app_rd_data_reg[41]\ => mem_intfc0_n_87,
      \not_strict_mode.app_rd_data_reg[420]\ => mem_intfc0_n_494,
      \not_strict_mode.app_rd_data_reg[421]\ => mem_intfc0_n_502,
      \not_strict_mode.app_rd_data_reg[422]\ => mem_intfc0_n_510,
      \not_strict_mode.app_rd_data_reg[423]\ => mem_intfc0_n_518,
      \not_strict_mode.app_rd_data_reg[424]\ => mem_intfc0_n_463,
      \not_strict_mode.app_rd_data_reg[425]\ => mem_intfc0_n_471,
      \not_strict_mode.app_rd_data_reg[426]\ => mem_intfc0_n_475,
      \not_strict_mode.app_rd_data_reg[427]\ => mem_intfc0_n_483,
      \not_strict_mode.app_rd_data_reg[428]\ => mem_intfc0_n_491,
      \not_strict_mode.app_rd_data_reg[429]\ => mem_intfc0_n_499,
      \not_strict_mode.app_rd_data_reg[42]\ => mem_intfc0_n_91,
      \not_strict_mode.app_rd_data_reg[430]\ => mem_intfc0_n_507,
      \not_strict_mode.app_rd_data_reg[431]\ => mem_intfc0_n_515,
      \not_strict_mode.app_rd_data_reg[432]\ => mem_intfc0_n_464,
      \not_strict_mode.app_rd_data_reg[433]\ => mem_intfc0_n_472,
      \not_strict_mode.app_rd_data_reg[434]\ => mem_intfc0_n_476,
      \not_strict_mode.app_rd_data_reg[435]\ => mem_intfc0_n_484,
      \not_strict_mode.app_rd_data_reg[436]\ => mem_intfc0_n_492,
      \not_strict_mode.app_rd_data_reg[437]\ => mem_intfc0_n_500,
      \not_strict_mode.app_rd_data_reg[438]\ => mem_intfc0_n_508,
      \not_strict_mode.app_rd_data_reg[439]\ => mem_intfc0_n_516,
      \not_strict_mode.app_rd_data_reg[43]\ => mem_intfc0_n_99,
      \not_strict_mode.app_rd_data_reg[440]\ => mem_intfc0_n_461,
      \not_strict_mode.app_rd_data_reg[441]\ => mem_intfc0_n_469,
      \not_strict_mode.app_rd_data_reg[442]\ => mem_intfc0_n_481,
      \not_strict_mode.app_rd_data_reg[443]\ => mem_intfc0_n_489,
      \not_strict_mode.app_rd_data_reg[444]\ => mem_intfc0_n_497,
      \not_strict_mode.app_rd_data_reg[445]\ => mem_intfc0_n_505,
      \not_strict_mode.app_rd_data_reg[446]\ => mem_intfc0_n_513,
      \not_strict_mode.app_rd_data_reg[447]\ => mem_intfc0_n_521,
      \not_strict_mode.app_rd_data_reg[448]\ => mem_intfc0_n_530,
      \not_strict_mode.app_rd_data_reg[449]\ => mem_intfc0_n_538,
      \not_strict_mode.app_rd_data_reg[44]\ => mem_intfc0_n_107,
      \not_strict_mode.app_rd_data_reg[450]\ => mem_intfc0_n_542,
      \not_strict_mode.app_rd_data_reg[451]\ => mem_intfc0_n_554,
      \not_strict_mode.app_rd_data_reg[452]\ => mem_intfc0_n_562,
      \not_strict_mode.app_rd_data_reg[453]\ => mem_intfc0_n_570,
      \not_strict_mode.app_rd_data_reg[454]\ => mem_intfc0_n_578,
      \not_strict_mode.app_rd_data_reg[455]\ => mem_intfc0_n_582,
      \not_strict_mode.app_rd_data_reg[456]\ => mem_intfc0_n_527,
      \not_strict_mode.app_rd_data_reg[457]\ => mem_intfc0_n_535,
      \not_strict_mode.app_rd_data_reg[458]\ => mem_intfc0_n_539,
      \not_strict_mode.app_rd_data_reg[459]\ => mem_intfc0_n_551,
      \not_strict_mode.app_rd_data_reg[45]\ => mem_intfc0_n_115,
      \not_strict_mode.app_rd_data_reg[460]\ => mem_intfc0_n_559,
      \not_strict_mode.app_rd_data_reg[461]\ => mem_intfc0_n_567,
      \not_strict_mode.app_rd_data_reg[462]\ => mem_intfc0_n_575,
      \not_strict_mode.app_rd_data_reg[463]\ => mem_intfc0_n_579,
      \not_strict_mode.app_rd_data_reg[464]\ => mem_intfc0_n_528,
      \not_strict_mode.app_rd_data_reg[465]\ => mem_intfc0_n_536,
      \not_strict_mode.app_rd_data_reg[466]\ => mem_intfc0_n_540,
      \not_strict_mode.app_rd_data_reg[467]\ => mem_intfc0_n_552,
      \not_strict_mode.app_rd_data_reg[468]\ => mem_intfc0_n_560,
      \not_strict_mode.app_rd_data_reg[469]\ => mem_intfc0_n_568,
      \not_strict_mode.app_rd_data_reg[46]\ => mem_intfc0_n_123,
      \not_strict_mode.app_rd_data_reg[470]\ => mem_intfc0_n_576,
      \not_strict_mode.app_rd_data_reg[471]\ => mem_intfc0_n_580,
      \not_strict_mode.app_rd_data_reg[472]\ => mem_intfc0_n_525,
      \not_strict_mode.app_rd_data_reg[473]\ => mem_intfc0_n_533,
      \not_strict_mode.app_rd_data_reg[474]\ => mem_intfc0_n_545,
      \not_strict_mode.app_rd_data_reg[475]\ => mem_intfc0_n_549,
      \not_strict_mode.app_rd_data_reg[476]\ => mem_intfc0_n_557,
      \not_strict_mode.app_rd_data_reg[477]\ => mem_intfc0_n_565,
      \not_strict_mode.app_rd_data_reg[478]\ => mem_intfc0_n_573,
      \not_strict_mode.app_rd_data_reg[479]\ => mem_intfc0_n_585,
      \not_strict_mode.app_rd_data_reg[47]\ => mem_intfc0_n_131,
      \not_strict_mode.app_rd_data_reg[480]\ => mem_intfc0_n_526,
      \not_strict_mode.app_rd_data_reg[481]\ => mem_intfc0_n_534,
      \not_strict_mode.app_rd_data_reg[482]\ => mem_intfc0_n_546,
      \not_strict_mode.app_rd_data_reg[483]\ => mem_intfc0_n_550,
      \not_strict_mode.app_rd_data_reg[484]\ => mem_intfc0_n_558,
      \not_strict_mode.app_rd_data_reg[485]\ => mem_intfc0_n_566,
      \not_strict_mode.app_rd_data_reg[486]\ => mem_intfc0_n_574,
      \not_strict_mode.app_rd_data_reg[487]\ => mem_intfc0_n_586,
      \not_strict_mode.app_rd_data_reg[488]\ => mem_intfc0_n_523,
      \not_strict_mode.app_rd_data_reg[489]\ => mem_intfc0_n_531,
      \not_strict_mode.app_rd_data_reg[48]\ => mem_intfc0_n_80,
      \not_strict_mode.app_rd_data_reg[490]\ => mem_intfc0_n_543,
      \not_strict_mode.app_rd_data_reg[491]\ => mem_intfc0_n_547,
      \not_strict_mode.app_rd_data_reg[492]\ => mem_intfc0_n_555,
      \not_strict_mode.app_rd_data_reg[493]\ => mem_intfc0_n_563,
      \not_strict_mode.app_rd_data_reg[494]\ => mem_intfc0_n_571,
      \not_strict_mode.app_rd_data_reg[495]\ => mem_intfc0_n_583,
      \not_strict_mode.app_rd_data_reg[496]\ => mem_intfc0_n_524,
      \not_strict_mode.app_rd_data_reg[497]\ => mem_intfc0_n_532,
      \not_strict_mode.app_rd_data_reg[498]\ => mem_intfc0_n_544,
      \not_strict_mode.app_rd_data_reg[499]\ => mem_intfc0_n_548,
      \not_strict_mode.app_rd_data_reg[49]\ => mem_intfc0_n_88,
      \not_strict_mode.app_rd_data_reg[4]\ => mem_intfc0_n_114,
      \not_strict_mode.app_rd_data_reg[500]\ => mem_intfc0_n_556,
      \not_strict_mode.app_rd_data_reg[501]\ => mem_intfc0_n_564,
      \not_strict_mode.app_rd_data_reg[502]\ => mem_intfc0_n_572,
      \not_strict_mode.app_rd_data_reg[503]\ => mem_intfc0_n_584,
      \not_strict_mode.app_rd_data_reg[504]\ => mem_intfc0_n_529,
      \not_strict_mode.app_rd_data_reg[505]\ => mem_intfc0_n_537,
      \not_strict_mode.app_rd_data_reg[506]\ => mem_intfc0_n_541,
      \not_strict_mode.app_rd_data_reg[507]\ => mem_intfc0_n_553,
      \not_strict_mode.app_rd_data_reg[508]\ => mem_intfc0_n_561,
      \not_strict_mode.app_rd_data_reg[509]\ => mem_intfc0_n_569,
      \not_strict_mode.app_rd_data_reg[50]\ => mem_intfc0_n_92,
      \not_strict_mode.app_rd_data_reg[510]\ => mem_intfc0_n_577,
      \not_strict_mode.app_rd_data_reg[511]\ => mem_intfc0_n_581,
      \not_strict_mode.app_rd_data_reg[511]_0\(511 downto 0) => \ui_rd_data0/not_strict_mode.app_rd_data_ns\(511 downto 0),
      \not_strict_mode.app_rd_data_reg[51]\ => mem_intfc0_n_100,
      \not_strict_mode.app_rd_data_reg[52]\ => mem_intfc0_n_108,
      \not_strict_mode.app_rd_data_reg[53]\ => mem_intfc0_n_116,
      \not_strict_mode.app_rd_data_reg[54]\ => mem_intfc0_n_124,
      \not_strict_mode.app_rd_data_reg[55]\ => mem_intfc0_n_132,
      \not_strict_mode.app_rd_data_reg[56]\ => mem_intfc0_n_77,
      \not_strict_mode.app_rd_data_reg[57]\ => mem_intfc0_n_85,
      \not_strict_mode.app_rd_data_reg[58]\ => mem_intfc0_n_97,
      \not_strict_mode.app_rd_data_reg[59]\ => mem_intfc0_n_105,
      \not_strict_mode.app_rd_data_reg[5]\ => mem_intfc0_n_122,
      \not_strict_mode.app_rd_data_reg[60]\ => mem_intfc0_n_113,
      \not_strict_mode.app_rd_data_reg[61]\ => mem_intfc0_n_121,
      \not_strict_mode.app_rd_data_reg[62]\ => mem_intfc0_n_129,
      \not_strict_mode.app_rd_data_reg[63]\ => mem_intfc0_n_137,
      \not_strict_mode.app_rd_data_reg[64]\ => mem_intfc0_n_146,
      \not_strict_mode.app_rd_data_reg[65]\ => mem_intfc0_n_154,
      \not_strict_mode.app_rd_data_reg[66]\ => mem_intfc0_n_162,
      \not_strict_mode.app_rd_data_reg[67]\ => mem_intfc0_n_166,
      \not_strict_mode.app_rd_data_reg[68]\ => mem_intfc0_n_178,
      \not_strict_mode.app_rd_data_reg[69]\ => mem_intfc0_n_186,
      \not_strict_mode.app_rd_data_reg[6]\ => mem_intfc0_n_130,
      \not_strict_mode.app_rd_data_reg[70]\ => mem_intfc0_n_194,
      \not_strict_mode.app_rd_data_reg[71]\ => mem_intfc0_n_202,
      \not_strict_mode.app_rd_data_reg[72]\ => mem_intfc0_n_143,
      \not_strict_mode.app_rd_data_reg[73]\ => mem_intfc0_n_151,
      \not_strict_mode.app_rd_data_reg[74]\ => mem_intfc0_n_159,
      \not_strict_mode.app_rd_data_reg[75]\ => mem_intfc0_n_163,
      \not_strict_mode.app_rd_data_reg[76]\ => mem_intfc0_n_175,
      \not_strict_mode.app_rd_data_reg[77]\ => mem_intfc0_n_183,
      \not_strict_mode.app_rd_data_reg[78]\ => mem_intfc0_n_191,
      \not_strict_mode.app_rd_data_reg[79]\ => mem_intfc0_n_199,
      \not_strict_mode.app_rd_data_reg[7]\ => mem_intfc0_n_138,
      \not_strict_mode.app_rd_data_reg[80]\ => mem_intfc0_n_144,
      \not_strict_mode.app_rd_data_reg[81]\ => mem_intfc0_n_152,
      \not_strict_mode.app_rd_data_reg[82]\ => mem_intfc0_n_160,
      \not_strict_mode.app_rd_data_reg[83]\ => mem_intfc0_n_164,
      \not_strict_mode.app_rd_data_reg[84]\ => mem_intfc0_n_176,
      \not_strict_mode.app_rd_data_reg[85]\ => mem_intfc0_n_184,
      \not_strict_mode.app_rd_data_reg[86]\ => mem_intfc0_n_192,
      \not_strict_mode.app_rd_data_reg[87]\ => mem_intfc0_n_200,
      \not_strict_mode.app_rd_data_reg[88]\ => mem_intfc0_n_141,
      \not_strict_mode.app_rd_data_reg[89]\ => mem_intfc0_n_149,
      \not_strict_mode.app_rd_data_reg[8]\ => mem_intfc0_n_75,
      \not_strict_mode.app_rd_data_reg[90]\ => mem_intfc0_n_157,
      \not_strict_mode.app_rd_data_reg[91]\ => mem_intfc0_n_169,
      \not_strict_mode.app_rd_data_reg[92]\ => mem_intfc0_n_173,
      \not_strict_mode.app_rd_data_reg[93]\ => mem_intfc0_n_181,
      \not_strict_mode.app_rd_data_reg[94]\ => mem_intfc0_n_189,
      \not_strict_mode.app_rd_data_reg[95]\ => mem_intfc0_n_197,
      \not_strict_mode.app_rd_data_reg[96]\ => mem_intfc0_n_142,
      \not_strict_mode.app_rd_data_reg[97]\ => mem_intfc0_n_150,
      \not_strict_mode.app_rd_data_reg[98]\ => mem_intfc0_n_158,
      \not_strict_mode.app_rd_data_reg[99]\ => mem_intfc0_n_170,
      \not_strict_mode.app_rd_data_reg[9]\ => mem_intfc0_n_83,
      \not_strict_mode.bypass__0\ => \ui_rd_data0/not_strict_mode.bypass__0\,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0) => \ui_rd_data0/p_252_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \ui_rd_data0/p_253_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \ui_rd_data0/p_254_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \ui_rd_data0/p_245_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100\(1 downto 0) => \ui_rd_data0/p_155_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101\(1 downto 0) => \ui_rd_data0/p_150_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102\(1 downto 0) => \ui_rd_data0/p_151_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103\(1 downto 0) => \ui_rd_data0/p_152_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104\(1 downto 0) => \ui_rd_data0/p_147_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105\(1 downto 0) => \ui_rd_data0/p_148_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106\(1 downto 0) => \ui_rd_data0/p_149_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107\(1 downto 0) => \ui_rd_data0/p_144_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108\(1 downto 0) => \ui_rd_data0/p_145_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109\(1 downto 0) => \ui_rd_data0/p_146_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \ui_rd_data0/p_240_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110\(1 downto 0) => \ui_rd_data0/p_141_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111\(1 downto 0) => \ui_rd_data0/p_142_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112\(1 downto 0) => \ui_rd_data0/p_143_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113\(1 downto 0) => \ui_rd_data0/p_138_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114\(1 downto 0) => \ui_rd_data0/p_139_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115\(1 downto 0) => \ui_rd_data0/p_140_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116\(1 downto 0) => \ui_rd_data0/p_135_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117\(1 downto 0) => \ui_rd_data0/p_136_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118\(1 downto 0) => \ui_rd_data0/p_137_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119\(1 downto 0) => \ui_rd_data0/p_132_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \ui_rd_data0/p_241_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120\(1 downto 0) => \ui_rd_data0/p_133_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121\(1 downto 0) => \ui_rd_data0/p_134_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122\(1 downto 0) => \ui_rd_data0/p_129_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123\(1 downto 0) => \ui_rd_data0/p_130_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_124\(1 downto 0) => \ui_rd_data0/p_131_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_125\(1 downto 0) => \ui_rd_data0/p_126_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_126\(1 downto 0) => \ui_rd_data0/p_127_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_127\(1 downto 0) => \ui_rd_data0/p_128_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_128\(1 downto 0) => \ui_rd_data0/p_123_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_129\(1 downto 0) => \ui_rd_data0/p_124_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \ui_rd_data0/p_242_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_130\(1 downto 0) => \ui_rd_data0/p_125_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_131\(1 downto 0) => \ui_rd_data0/p_120_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_132\(1 downto 0) => \ui_rd_data0/p_121_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_133\(1 downto 0) => \ui_rd_data0/p_122_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_134\(1 downto 0) => \ui_rd_data0/p_117_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_135\(1 downto 0) => \ui_rd_data0/p_118_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_136\(1 downto 0) => \ui_rd_data0/p_119_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_137\(1 downto 0) => \ui_rd_data0/p_114_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_138\(1 downto 0) => \ui_rd_data0/p_115_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_139\(1 downto 0) => \ui_rd_data0/p_116_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \ui_rd_data0/p_237_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_140\(1 downto 0) => \ui_rd_data0/p_111_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_141\(1 downto 0) => \ui_rd_data0/p_112_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_142\(1 downto 0) => \ui_rd_data0/p_113_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_143\(1 downto 0) => \ui_rd_data0/p_108_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_144\(1 downto 0) => \ui_rd_data0/p_109_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_145\(1 downto 0) => \ui_rd_data0/p_110_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_146\(1 downto 0) => \ui_rd_data0/p_105_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_147\(1 downto 0) => \ui_rd_data0/p_106_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_148\(1 downto 0) => \ui_rd_data0/p_107_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_149\(1 downto 0) => \ui_rd_data0/p_102_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \ui_rd_data0/p_238_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_150\(1 downto 0) => \ui_rd_data0/p_103_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_151\(1 downto 0) => \ui_rd_data0/p_104_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_152\(1 downto 0) => \ui_rd_data0/p_99_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_153\(1 downto 0) => \ui_rd_data0/p_100_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_154\(1 downto 0) => \ui_rd_data0/p_101_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_155\(1 downto 0) => \ui_rd_data0/p_96_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_156\(1 downto 0) => \ui_rd_data0/p_97_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_157\(1 downto 0) => \ui_rd_data0/p_98_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_158\(1 downto 0) => \ui_rd_data0/p_93_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_159\(1 downto 0) => \ui_rd_data0/p_94_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \ui_rd_data0/p_239_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_160\(1 downto 0) => \ui_rd_data0/p_95_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_161\(1 downto 0) => \ui_rd_data0/p_90_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_162\(1 downto 0) => \ui_rd_data0/p_91_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_163\(1 downto 0) => \ui_rd_data0/p_92_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_164\(1 downto 0) => \ui_rd_data0/p_87_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_165\(1 downto 0) => \ui_rd_data0/p_88_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_166\(1 downto 0) => \ui_rd_data0/p_89_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_167\(1 downto 0) => \ui_rd_data0/p_84_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_168\(1 downto 0) => \ui_rd_data0/p_85_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_169\(1 downto 0) => \ui_rd_data0/p_86_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \ui_rd_data0/p_234_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_170\(1 downto 0) => \ui_rd_data0/p_81_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_171\(1 downto 0) => \ui_rd_data0/p_82_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_172\(1 downto 0) => \ui_rd_data0/p_83_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_173\(1 downto 0) => \ui_rd_data0/p_78_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_174\(1 downto 0) => \ui_rd_data0/p_79_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_175\(1 downto 0) => \ui_rd_data0/p_80_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_176\(1 downto 0) => \ui_rd_data0/p_75_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_177\(1 downto 0) => \ui_rd_data0/p_76_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_178\(1 downto 0) => \ui_rd_data0/p_77_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_179\(1 downto 0) => \ui_rd_data0/p_72_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \ui_rd_data0/p_235_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_180\(1 downto 0) => \ui_rd_data0/p_73_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_181\(1 downto 0) => \ui_rd_data0/p_74_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_182\(1 downto 0) => \ui_rd_data0/p_69_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_183\(1 downto 0) => \ui_rd_data0/p_70_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_184\(1 downto 0) => \ui_rd_data0/p_71_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_185\(1 downto 0) => \ui_rd_data0/p_66_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_186\(1 downto 0) => \ui_rd_data0/p_67_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_187\(1 downto 0) => \ui_rd_data0/p_68_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_188\(1 downto 0) => \ui_rd_data0/p_63_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_189\(1 downto 0) => \ui_rd_data0/p_64_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \ui_rd_data0/p_236_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_190\(1 downto 0) => \ui_rd_data0/p_65_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_191\(1 downto 0) => \ui_rd_data0/p_60_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_192\(1 downto 0) => \ui_rd_data0/p_61_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_193\(1 downto 0) => \ui_rd_data0/p_62_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_194\(1 downto 0) => \ui_rd_data0/p_57_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_195\(1 downto 0) => \ui_rd_data0/p_58_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_196\(1 downto 0) => \ui_rd_data0/p_59_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_197\(1 downto 0) => \ui_rd_data0/p_54_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_198\(1 downto 0) => \ui_rd_data0/p_55_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_199\(1 downto 0) => \ui_rd_data0/p_56_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \ui_rd_data0/p_249_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \ui_rd_data0/p_231_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_200\(1 downto 0) => \ui_rd_data0/p_51_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_201\(1 downto 0) => \ui_rd_data0/p_52_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_202\(1 downto 0) => \ui_rd_data0/p_53_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_203\(1 downto 0) => \ui_rd_data0/p_48_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_204\(1 downto 0) => \ui_rd_data0/p_49_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_205\(1 downto 0) => \ui_rd_data0/p_50_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_206\(1 downto 0) => \ui_rd_data0/p_45_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_207\(1 downto 0) => \ui_rd_data0/p_46_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_208\(1 downto 0) => \ui_rd_data0/p_47_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_209\(1 downto 0) => \ui_rd_data0/p_42_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \ui_rd_data0/p_232_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_210\(1 downto 0) => \ui_rd_data0/p_43_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_211\(1 downto 0) => \ui_rd_data0/p_44_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_212\(1 downto 0) => \ui_rd_data0/p_39_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_213\(1 downto 0) => \ui_rd_data0/p_40_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_214\(1 downto 0) => \ui_rd_data0/p_41_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_215\(1 downto 0) => \ui_rd_data0/p_36_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_216\(1 downto 0) => \ui_rd_data0/p_37_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_217\(1 downto 0) => \ui_rd_data0/p_38_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_218\(1 downto 0) => \ui_rd_data0/p_33_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_219\(1 downto 0) => \ui_rd_data0/p_34_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \ui_rd_data0/p_233_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_220\(1 downto 0) => \ui_rd_data0/p_35_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_221\(1 downto 0) => \ui_rd_data0/p_30_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_222\(1 downto 0) => \ui_rd_data0/p_31_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_223\(1 downto 0) => \ui_rd_data0/p_32_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_224\(1 downto 0) => \ui_rd_data0/p_27_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_225\(1 downto 0) => \ui_rd_data0/p_28_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_226\(1 downto 0) => \ui_rd_data0/p_29_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_227\(1 downto 0) => \ui_rd_data0/p_24_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_228\(1 downto 0) => \ui_rd_data0/p_25_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_229\(1 downto 0) => \ui_rd_data0/p_26_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \ui_rd_data0/p_228_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_230\(1 downto 0) => \ui_rd_data0/p_21_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_231\(1 downto 0) => \ui_rd_data0/p_22_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_232\(1 downto 0) => \ui_rd_data0/p_23_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_233\(1 downto 0) => \ui_rd_data0/p_18_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_234\(1 downto 0) => \ui_rd_data0/p_19_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_235\(1 downto 0) => \ui_rd_data0/p_20_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_236\(1 downto 0) => \ui_rd_data0/p_15_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_237\(1 downto 0) => \ui_rd_data0/p_16_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_238\(1 downto 0) => \ui_rd_data0/p_17_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_239\(1 downto 0) => \ui_rd_data0/p_12_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \ui_rd_data0/p_229_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_240\(1 downto 0) => \ui_rd_data0/p_13_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_241\(1 downto 0) => \ui_rd_data0/p_14_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_242\(1 downto 0) => \ui_rd_data0/p_9_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_243\(1 downto 0) => \ui_rd_data0/p_10_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_244\(1 downto 0) => \ui_rd_data0/p_11_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_245\(1 downto 0) => \ui_rd_data0/p_6_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_246\(1 downto 0) => \ui_rd_data0/p_7_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_247\(1 downto 0) => \ui_rd_data0/p_8_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_248\(1 downto 0) => \ui_rd_data0/p_3_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_249\(1 downto 0) => \ui_rd_data0/p_4_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \ui_rd_data0/p_230_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_250\(1 downto 0) => \ui_rd_data0/p_5_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(1) => u_ui_top_n_518,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_251\(0) => u_ui_top_n_519,
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \ui_rd_data0/p_225_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \ui_rd_data0/p_226_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \ui_rd_data0/p_227_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \ui_rd_data0/p_222_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \ui_rd_data0/p_250_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \ui_rd_data0/p_223_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0) => \ui_rd_data0/p_224_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0) => \ui_rd_data0/p_219_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0) => \ui_rd_data0/p_220_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0) => \ui_rd_data0/p_221_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0) => \ui_rd_data0/p_216_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0) => \ui_rd_data0/p_217_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0) => \ui_rd_data0/p_218_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0) => \ui_rd_data0/p_213_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0) => \ui_rd_data0/p_214_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \ui_rd_data0/p_251_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0) => \ui_rd_data0/p_215_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0) => \ui_rd_data0/p_210_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0) => \ui_rd_data0/p_211_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0) => \ui_rd_data0/p_212_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0) => \ui_rd_data0/p_207_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0) => \ui_rd_data0/p_208_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0) => \ui_rd_data0/p_209_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0) => \ui_rd_data0/p_204_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0) => \ui_rd_data0/p_205_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0) => \ui_rd_data0/p_206_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \ui_rd_data0/p_246_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0) => \ui_rd_data0/p_201_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0) => \ui_rd_data0/p_202_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0) => \ui_rd_data0/p_203_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0) => \ui_rd_data0/p_198_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0) => \ui_rd_data0/p_199_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0) => \ui_rd_data0/p_200_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0) => \ui_rd_data0/p_195_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0) => \ui_rd_data0/p_196_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0) => \ui_rd_data0/p_197_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0) => \ui_rd_data0/p_192_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \ui_rd_data0/p_247_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0) => \ui_rd_data0/p_193_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61\(1 downto 0) => \ui_rd_data0/p_194_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62\(1 downto 0) => \ui_rd_data0/p_189_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63\(1 downto 0) => \ui_rd_data0/p_190_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64\(1 downto 0) => \ui_rd_data0/p_191_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65\(1 downto 0) => \ui_rd_data0/p_186_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66\(1 downto 0) => \ui_rd_data0/p_187_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67\(1 downto 0) => \ui_rd_data0/p_188_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68\(1 downto 0) => \ui_rd_data0/p_183_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69\(1 downto 0) => \ui_rd_data0/p_184_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \ui_rd_data0/p_248_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70\(1 downto 0) => \ui_rd_data0/p_185_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71\(1 downto 0) => \ui_rd_data0/p_180_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72\(1 downto 0) => \ui_rd_data0/p_181_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73\(1 downto 0) => \ui_rd_data0/p_182_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74\(1 downto 0) => \ui_rd_data0/p_177_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75\(1 downto 0) => \ui_rd_data0/p_178_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76\(1 downto 0) => \ui_rd_data0/p_179_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77\(1 downto 0) => \ui_rd_data0/p_174_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78\(1 downto 0) => \ui_rd_data0/p_175_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79\(1 downto 0) => \ui_rd_data0/p_176_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \ui_rd_data0/p_243_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80\(1 downto 0) => \ui_rd_data0/p_171_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81\(1 downto 0) => \ui_rd_data0/p_172_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82\(1 downto 0) => \ui_rd_data0/p_173_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83\(1 downto 0) => \ui_rd_data0/p_168_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84\(1 downto 0) => \ui_rd_data0/p_169_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85\(1 downto 0) => \ui_rd_data0/p_170_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86\(1 downto 0) => \ui_rd_data0/p_165_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87\(1 downto 0) => \ui_rd_data0/p_166_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88\(1 downto 0) => \ui_rd_data0/p_167_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89\(1 downto 0) => \ui_rd_data0/p_162_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \ui_rd_data0/p_244_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90\(1 downto 0) => \ui_rd_data0/p_163_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91\(1 downto 0) => \ui_rd_data0/p_164_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92\(1 downto 0) => \ui_rd_data0/p_159_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93\(1 downto 0) => \ui_rd_data0/p_160_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94\(1 downto 0) => \ui_rd_data0/p_161_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95\(1 downto 0) => \ui_rd_data0/p_156_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96\(1 downto 0) => \ui_rd_data0/p_157_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97\(1 downto 0) => \ui_rd_data0/p_158_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98\(1 downto 0) => \ui_rd_data0/p_153_out\(1 downto 0),
      \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99\(1 downto 0) => \ui_rd_data0/p_154_out\(1 downto 0),
      \not_strict_mode.rd_buf_we\ => \ui_rd_data0/not_strict_mode.rd_buf_we\,
      \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => data_buf_addr(4 downto 0),
      \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0) => \ui_rd_data0/not_strict_mode.rd_status\(1),
      pi_cnt_dec_reg(0) => pi_cnt_dec_reg(0),
      pll_locked => pll_locked,
      \pointer_ram.pointer_we\ => \ui_wr_data0/pointer_ram.pointer_we\,
      prbs_rdlvl_done_pulse_reg(0) => prbs_rdlvl_done_pulse_reg(0),
      ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0),
      ram_init_done_r => ram_init_done_r,
      ras_timer_zero_r_reg => bm_end_r1,
      ras_timer_zero_r_reg_0 => bm_end_r1_2,
      \rd_buf_indx.rd_buf_indx_r_reg[4]\ => u_ui_top_n_3,
      rdlvl_stg1_start_r_reg => rdlvl_stg1_start_r_reg,
      rdlvl_stg1_start_reg(0) => rdlvl_stg1_start_reg(0),
      \req_bank_r_lcl_reg[0]\ => u_ui_top_n_542,
      \req_bank_r_lcl_reg[0]_0\ => u_ui_top_n_547,
      \req_bank_r_lcl_reg[2]\ => u_ui_top_n_546,
      \req_row_r_lcl_reg[3]\(0) => u_ui_top_n_541,
      rst_sync_r1_reg => rst_sync_r1_reg,
      \rstdiv0_sync_r1_reg_rep__10\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__10\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__12\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__12\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__13\(3 downto 0) => \rstdiv0_sync_r1_reg_rep__13\(3 downto 0),
      \rstdiv0_sync_r1_reg_rep__15\(0) => \rstdiv0_sync_r1_reg_rep__15\(0),
      \rstdiv0_sync_r1_reg_rep__17\(0) => \rstdiv0_sync_r1_reg_rep__17\(0),
      \rstdiv0_sync_r1_reg_rep__19\ => \rstdiv0_sync_r1_reg_rep__19\,
      \rstdiv0_sync_r1_reg_rep__2\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__2\(1 downto 0),
      \rstdiv0_sync_r1_reg_rep__20\ => \rstdiv0_sync_r1_reg_rep__20\,
      \rstdiv0_sync_r1_reg_rep__21\ => \rstdiv0_sync_r1_reg_rep__21\,
      \rstdiv0_sync_r1_reg_rep__22\ => \rstdiv0_sync_r1_reg_rep__22\,
      \rstdiv0_sync_r1_reg_rep__22_0\ => \rstdiv0_sync_r1_reg_rep__22_0\,
      \rstdiv0_sync_r1_reg_rep__23\ => \rstdiv0_sync_r1_reg_rep__23\,
      \rstdiv0_sync_r1_reg_rep__4\ => \rstdiv0_sync_r1_reg_rep__4\,
      \rstdiv0_sync_r1_reg_rep__5\ => \rstdiv0_sync_r1_reg_rep__5\,
      \rstdiv0_sync_r1_reg_rep__6\(0) => \rstdiv0_sync_r1_reg_rep__6\(0),
      \rstdiv0_sync_r1_reg_rep__8\(1 downto 0) => \rstdiv0_sync_r1_reg_rep__8\(1 downto 0),
      samp_edge_cnt0_en_r => samp_edge_cnt0_en_r,
      sync_pulse => sync_pulse,
      sys_rst => sys_rst,
      sys_rst_0 => sys_rst_0,
      use_addr => use_addr,
      \write_buffer.wr_buf_out_data_reg[383]\(95) => \ddr_phy_top0/mux_wrdata\(383),
      \write_buffer.wr_buf_out_data_reg[383]\(94) => \ddr_phy_top0/mux_wrdata\(379),
      \write_buffer.wr_buf_out_data_reg[383]\(93) => \ddr_phy_top0/mux_wrdata\(375),
      \write_buffer.wr_buf_out_data_reg[383]\(92) => \ddr_phy_top0/mux_wrdata\(371),
      \write_buffer.wr_buf_out_data_reg[383]\(91) => \ddr_phy_top0/mux_wrdata\(367),
      \write_buffer.wr_buf_out_data_reg[383]\(90) => \ddr_phy_top0/mux_wrdata\(363),
      \write_buffer.wr_buf_out_data_reg[383]\(89) => \ddr_phy_top0/mux_wrdata\(359),
      \write_buffer.wr_buf_out_data_reg[383]\(88) => \ddr_phy_top0/mux_wrdata\(355),
      \write_buffer.wr_buf_out_data_reg[383]\(87) => \ddr_phy_top0/mux_wrdata\(351),
      \write_buffer.wr_buf_out_data_reg[383]\(86) => \ddr_phy_top0/mux_wrdata\(347),
      \write_buffer.wr_buf_out_data_reg[383]\(85) => \ddr_phy_top0/mux_wrdata\(343),
      \write_buffer.wr_buf_out_data_reg[383]\(84) => \ddr_phy_top0/mux_wrdata\(339),
      \write_buffer.wr_buf_out_data_reg[383]\(83) => \ddr_phy_top0/mux_wrdata\(335),
      \write_buffer.wr_buf_out_data_reg[383]\(82) => \ddr_phy_top0/mux_wrdata\(331),
      \write_buffer.wr_buf_out_data_reg[383]\(81) => \ddr_phy_top0/mux_wrdata\(327),
      \write_buffer.wr_buf_out_data_reg[383]\(80) => \ddr_phy_top0/mux_wrdata\(323),
      \write_buffer.wr_buf_out_data_reg[383]\(79) => \ddr_phy_top0/mux_wrdata\(318),
      \write_buffer.wr_buf_out_data_reg[383]\(78) => \ddr_phy_top0/mux_wrdata\(314),
      \write_buffer.wr_buf_out_data_reg[383]\(77) => \ddr_phy_top0/mux_wrdata\(310),
      \write_buffer.wr_buf_out_data_reg[383]\(76) => \ddr_phy_top0/mux_wrdata\(306),
      \write_buffer.wr_buf_out_data_reg[383]\(75) => \ddr_phy_top0/mux_wrdata\(302),
      \write_buffer.wr_buf_out_data_reg[383]\(74) => \ddr_phy_top0/mux_wrdata\(298),
      \write_buffer.wr_buf_out_data_reg[383]\(73) => \ddr_phy_top0/mux_wrdata\(294),
      \write_buffer.wr_buf_out_data_reg[383]\(72) => \ddr_phy_top0/mux_wrdata\(290),
      \write_buffer.wr_buf_out_data_reg[383]\(71) => \ddr_phy_top0/mux_wrdata\(286),
      \write_buffer.wr_buf_out_data_reg[383]\(70) => \ddr_phy_top0/mux_wrdata\(282),
      \write_buffer.wr_buf_out_data_reg[383]\(69) => \ddr_phy_top0/mux_wrdata\(278),
      \write_buffer.wr_buf_out_data_reg[383]\(68) => \ddr_phy_top0/mux_wrdata\(274),
      \write_buffer.wr_buf_out_data_reg[383]\(67) => \ddr_phy_top0/mux_wrdata\(270),
      \write_buffer.wr_buf_out_data_reg[383]\(66) => \ddr_phy_top0/mux_wrdata\(266),
      \write_buffer.wr_buf_out_data_reg[383]\(65) => \ddr_phy_top0/mux_wrdata\(262),
      \write_buffer.wr_buf_out_data_reg[383]\(64) => \ddr_phy_top0/mux_wrdata\(258),
      \write_buffer.wr_buf_out_data_reg[383]\(63) => \ddr_phy_top0/mux_wrdata\(254),
      \write_buffer.wr_buf_out_data_reg[383]\(62) => \ddr_phy_top0/mux_wrdata\(250),
      \write_buffer.wr_buf_out_data_reg[383]\(61) => \ddr_phy_top0/mux_wrdata\(246),
      \write_buffer.wr_buf_out_data_reg[383]\(60) => \ddr_phy_top0/mux_wrdata\(242),
      \write_buffer.wr_buf_out_data_reg[383]\(59) => \ddr_phy_top0/mux_wrdata\(238),
      \write_buffer.wr_buf_out_data_reg[383]\(58) => \ddr_phy_top0/mux_wrdata\(234),
      \write_buffer.wr_buf_out_data_reg[383]\(57) => \ddr_phy_top0/mux_wrdata\(230),
      \write_buffer.wr_buf_out_data_reg[383]\(56) => \ddr_phy_top0/mux_wrdata\(226),
      \write_buffer.wr_buf_out_data_reg[383]\(55) => \ddr_phy_top0/mux_wrdata\(222),
      \write_buffer.wr_buf_out_data_reg[383]\(54) => \ddr_phy_top0/mux_wrdata\(218),
      \write_buffer.wr_buf_out_data_reg[383]\(53) => \ddr_phy_top0/mux_wrdata\(214),
      \write_buffer.wr_buf_out_data_reg[383]\(52) => \ddr_phy_top0/mux_wrdata\(210),
      \write_buffer.wr_buf_out_data_reg[383]\(51) => \ddr_phy_top0/mux_wrdata\(206),
      \write_buffer.wr_buf_out_data_reg[383]\(50) => \ddr_phy_top0/mux_wrdata\(202),
      \write_buffer.wr_buf_out_data_reg[383]\(49) => \ddr_phy_top0/mux_wrdata\(198),
      \write_buffer.wr_buf_out_data_reg[383]\(48) => \ddr_phy_top0/mux_wrdata\(194),
      \write_buffer.wr_buf_out_data_reg[383]\(47) => \ddr_phy_top0/mux_wrdata\(189),
      \write_buffer.wr_buf_out_data_reg[383]\(46) => \ddr_phy_top0/mux_wrdata\(185),
      \write_buffer.wr_buf_out_data_reg[383]\(45) => \ddr_phy_top0/mux_wrdata\(181),
      \write_buffer.wr_buf_out_data_reg[383]\(44) => \ddr_phy_top0/mux_wrdata\(177),
      \write_buffer.wr_buf_out_data_reg[383]\(43) => \ddr_phy_top0/mux_wrdata\(173),
      \write_buffer.wr_buf_out_data_reg[383]\(42) => \ddr_phy_top0/mux_wrdata\(169),
      \write_buffer.wr_buf_out_data_reg[383]\(41) => \ddr_phy_top0/mux_wrdata\(165),
      \write_buffer.wr_buf_out_data_reg[383]\(40) => \ddr_phy_top0/mux_wrdata\(161),
      \write_buffer.wr_buf_out_data_reg[383]\(39) => \ddr_phy_top0/mux_wrdata\(157),
      \write_buffer.wr_buf_out_data_reg[383]\(38) => \ddr_phy_top0/mux_wrdata\(153),
      \write_buffer.wr_buf_out_data_reg[383]\(37) => \ddr_phy_top0/mux_wrdata\(149),
      \write_buffer.wr_buf_out_data_reg[383]\(36) => \ddr_phy_top0/mux_wrdata\(145),
      \write_buffer.wr_buf_out_data_reg[383]\(35) => \ddr_phy_top0/mux_wrdata\(141),
      \write_buffer.wr_buf_out_data_reg[383]\(34) => \ddr_phy_top0/mux_wrdata\(137),
      \write_buffer.wr_buf_out_data_reg[383]\(33) => \ddr_phy_top0/mux_wrdata\(133),
      \write_buffer.wr_buf_out_data_reg[383]\(32) => \ddr_phy_top0/mux_wrdata\(129),
      \write_buffer.wr_buf_out_data_reg[383]\(31) => \ddr_phy_top0/mux_wrdata\(63),
      \write_buffer.wr_buf_out_data_reg[383]\(30 downto 29) => \ddr_phy_top0/mux_wrdata\(60 downto 59),
      \write_buffer.wr_buf_out_data_reg[383]\(28 downto 27) => \ddr_phy_top0/mux_wrdata\(56 downto 55),
      \write_buffer.wr_buf_out_data_reg[383]\(26 downto 25) => \ddr_phy_top0/mux_wrdata\(52 downto 51),
      \write_buffer.wr_buf_out_data_reg[383]\(24 downto 23) => \ddr_phy_top0/mux_wrdata\(48 downto 47),
      \write_buffer.wr_buf_out_data_reg[383]\(22 downto 21) => \ddr_phy_top0/mux_wrdata\(44 downto 43),
      \write_buffer.wr_buf_out_data_reg[383]\(20 downto 19) => \ddr_phy_top0/mux_wrdata\(40 downto 39),
      \write_buffer.wr_buf_out_data_reg[383]\(18 downto 17) => \ddr_phy_top0/mux_wrdata\(36 downto 35),
      \write_buffer.wr_buf_out_data_reg[383]\(16 downto 15) => \ddr_phy_top0/mux_wrdata\(32 downto 31),
      \write_buffer.wr_buf_out_data_reg[383]\(14 downto 13) => \ddr_phy_top0/mux_wrdata\(28 downto 27),
      \write_buffer.wr_buf_out_data_reg[383]\(12 downto 11) => \ddr_phy_top0/mux_wrdata\(24 downto 23),
      \write_buffer.wr_buf_out_data_reg[383]\(10 downto 9) => \ddr_phy_top0/mux_wrdata\(20 downto 19),
      \write_buffer.wr_buf_out_data_reg[383]\(8 downto 7) => \ddr_phy_top0/mux_wrdata\(16 downto 15),
      \write_buffer.wr_buf_out_data_reg[383]\(6 downto 5) => \ddr_phy_top0/mux_wrdata\(12 downto 11),
      \write_buffer.wr_buf_out_data_reg[383]\(4 downto 3) => \ddr_phy_top0/mux_wrdata\(8 downto 7),
      \write_buffer.wr_buf_out_data_reg[383]\(2 downto 1) => \ddr_phy_top0/mux_wrdata\(4 downto 3),
      \write_buffer.wr_buf_out_data_reg[383]\(0) => \ddr_phy_top0/mux_wrdata\(0),
      \write_buffer.wr_buf_out_data_reg[575]\(3 downto 0) => wr_data_addr(3 downto 0),
      \write_buffer.wr_buf_out_data_reg[575]_0\(575 downto 512) => wr_data_mask(63 downto 0),
      \write_buffer.wr_buf_out_data_reg[575]_0\(511 downto 0) => wr_data(511 downto 0)
    );
reset_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rstdiv0_sync_r1_reg_rep__23\,
      Q => reset_reg_n_0,
      R => '0'
    );
u_ui_top: entity work.mig_7series_0_mig_7series_v2_3_ui_top
     port map (
      CLK => CLK,
      D(13 downto 0) => row(13 downto 0),
      DIA(1) => mem_intfc0_n_122,
      DIA(0) => mem_intfc0_n_114,
      DIB(1) => mem_intfc0_n_106,
      DIB(0) => mem_intfc0_n_98,
      DIC(1) => mem_intfc0_n_86,
      DIC(0) => mem_intfc0_n_78,
      DOA(1 downto 0) => \ui_rd_data0/p_258_out\(1 downto 0),
      DOB(1 downto 0) => \ui_rd_data0/p_257_out\(1 downto 0),
      DOC(1 downto 0) => \ui_rd_data0/p_256_out\(1 downto 0),
      E(0) => wr_data_en,
      Q(6) => rd_data_end,
      Q(5 downto 1) => rd_data_addr(4 downto 0),
      Q(0) => rd_data_offset,
      S(0) => u_ui_top_n_523,
      accept_ns => accept_ns,
      app_addr(26 downto 0) => app_addr(26 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rd_data(511 downto 0) => app_rd_data(511 downto 0),
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_rdy => \^app_rdy\,
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      cmd(1 downto 0) => cmd(1 downto 0),
      \cmd_pipe_plus.wr_data_addr_reg[3]\(3 downto 0) => wr_data_addr(3 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\(1) => mem_intfc0_n_133,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\(0) => mem_intfc0_n_125,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\(1) => mem_intfc0_n_134,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_0\(0) => mem_intfc0_n_126,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\(1) => mem_intfc0_n_137,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]_1\(0) => mem_intfc0_n_129,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\(1) => mem_intfc0_n_262,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\(0) => mem_intfc0_n_254,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\(1) => mem_intfc0_n_259,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0\(0) => mem_intfc0_n_251,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\(1) => mem_intfc0_n_260,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1\(0) => mem_intfc0_n_252,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\(1) => mem_intfc0_n_263,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2\(0) => mem_intfc0_n_255,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3\(1) => mem_intfc0_n_264,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_3\(0) => mem_intfc0_n_256,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1) => mem_intfc0_n_326,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(0) => mem_intfc0_n_322,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\(1) => mem_intfc0_n_323,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\(0) => mem_intfc0_n_319,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\(1) => mem_intfc0_n_324,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1\(0) => mem_intfc0_n_320,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\(1) => mem_intfc0_n_327,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2\(0) => mem_intfc0_n_315,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3\(1) => mem_intfc0_n_328,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_3\(0) => mem_intfc0_n_316,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1) => mem_intfc0_n_394,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(0) => mem_intfc0_n_382,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\(1) => mem_intfc0_n_391,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\(0) => mem_intfc0_n_379,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\(1) => mem_intfc0_n_392,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1\(0) => mem_intfc0_n_380,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\(1) => mem_intfc0_n_387,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2\(0) => mem_intfc0_n_383,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3\(1) => mem_intfc0_n_388,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_3\(0) => mem_intfc0_n_384,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1) => mem_intfc0_n_454,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(0) => mem_intfc0_n_450,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\(1) => mem_intfc0_n_451,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\(0) => mem_intfc0_n_447,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\(1) => mem_intfc0_n_452,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1\(0) => mem_intfc0_n_448,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\(1) => mem_intfc0_n_455,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2\(0) => mem_intfc0_n_443,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3\(1) => mem_intfc0_n_456,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_3\(0) => mem_intfc0_n_444,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1) => mem_intfc0_n_522,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(0) => mem_intfc0_n_514,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\(1) => mem_intfc0_n_519,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\(0) => mem_intfc0_n_511,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\(1) => mem_intfc0_n_520,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1\(0) => mem_intfc0_n_512,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\(1) => mem_intfc0_n_515,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2\(0) => mem_intfc0_n_507,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3\(1) => mem_intfc0_n_516,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_3\(0) => mem_intfc0_n_508,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1) => mem_intfc0_n_582,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(0) => mem_intfc0_n_578,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\(1) => mem_intfc0_n_579,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\(0) => mem_intfc0_n_575,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\(1) => mem_intfc0_n_580,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1\(0) => mem_intfc0_n_576,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\(1) => mem_intfc0_n_583,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2\(0) => mem_intfc0_n_571,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3\(1) => mem_intfc0_n_584,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_3\(0) => mem_intfc0_n_572,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\(1) => mem_intfc0_n_117,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\(0) => mem_intfc0_n_109,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\(1) => mem_intfc0_n_118,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0\(0) => mem_intfc0_n_110,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\(1) => mem_intfc0_n_121,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1\(0) => mem_intfc0_n_113,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\(1) => mem_intfc0_n_181,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\(0) => mem_intfc0_n_173,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\(1) => mem_intfc0_n_182,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0\(0) => mem_intfc0_n_174,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\(1) => mem_intfc0_n_185,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1\(0) => mem_intfc0_n_177,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\(1) => mem_intfc0_n_249,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\(0) => mem_intfc0_n_237,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\(1) => mem_intfc0_n_250,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0\(0) => mem_intfc0_n_238,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\(1) => mem_intfc0_n_245,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1\(0) => mem_intfc0_n_241,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\(1) => mem_intfc0_n_309,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\(0) => mem_intfc0_n_301,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\(1) => mem_intfc0_n_310,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0\(0) => mem_intfc0_n_302,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\(1) => mem_intfc0_n_313,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1\(0) => mem_intfc0_n_305,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\(1) => mem_intfc0_n_197,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\(0) => mem_intfc0_n_189,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\(1) => mem_intfc0_n_198,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_0\(0) => mem_intfc0_n_190,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1\(1) => mem_intfc0_n_201,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]_1\(0) => mem_intfc0_n_193,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\(1) => mem_intfc0_n_373,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\(0) => mem_intfc0_n_365,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\(1) => mem_intfc0_n_374,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0\(0) => mem_intfc0_n_366,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\(1) => mem_intfc0_n_377,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1\(0) => mem_intfc0_n_369,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\(1) => mem_intfc0_n_441,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\(0) => mem_intfc0_n_429,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\(1) => mem_intfc0_n_442,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0\(0) => mem_intfc0_n_430,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\(1) => mem_intfc0_n_437,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1\(0) => mem_intfc0_n_433,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\(1) => mem_intfc0_n_501,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\(0) => mem_intfc0_n_493,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\(1) => mem_intfc0_n_502,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0\(0) => mem_intfc0_n_494,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\(1) => mem_intfc0_n_505,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1\(0) => mem_intfc0_n_497,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\(1) => mem_intfc0_n_565,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\(0) => mem_intfc0_n_557,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(1) => mem_intfc0_n_566,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0\(0) => mem_intfc0_n_558,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(1) => mem_intfc0_n_569,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1\(0) => mem_intfc0_n_561,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\(1) => mem_intfc0_n_119,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\(0) => mem_intfc0_n_111,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\(1) => mem_intfc0_n_120,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0\(0) => mem_intfc0_n_112,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\(1) => mem_intfc0_n_115,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1\(0) => mem_intfc0_n_107,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\(1) => mem_intfc0_n_116,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2\(0) => mem_intfc0_n_108,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\(1) => mem_intfc0_n_186,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\(0) => mem_intfc0_n_178,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\(1) => mem_intfc0_n_183,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0\(0) => mem_intfc0_n_175,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\(1) => mem_intfc0_n_184,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1\(0) => mem_intfc0_n_176,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\(1) => mem_intfc0_n_179,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2\(0) => mem_intfc0_n_171,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\(1) => mem_intfc0_n_180,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3\(0) => mem_intfc0_n_172,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\(1) => mem_intfc0_n_246,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\(0) => mem_intfc0_n_242,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\(1) => mem_intfc0_n_243,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0\(0) => mem_intfc0_n_239,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\(1) => mem_intfc0_n_244,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1\(0) => mem_intfc0_n_240,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\(1) => mem_intfc0_n_247,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2\(0) => mem_intfc0_n_235,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\(1) => mem_intfc0_n_248,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3\(0) => mem_intfc0_n_236,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\(1) => mem_intfc0_n_314,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\(0) => mem_intfc0_n_306,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\(1) => mem_intfc0_n_311,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0\(0) => mem_intfc0_n_303,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\(1) => mem_intfc0_n_312,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1\(0) => mem_intfc0_n_304,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\(1) => mem_intfc0_n_307,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2\(0) => mem_intfc0_n_299,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\(1) => mem_intfc0_n_308,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3\(0) => mem_intfc0_n_300,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\(1) => mem_intfc0_n_378,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\(0) => mem_intfc0_n_370,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\(1) => mem_intfc0_n_375,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0\(0) => mem_intfc0_n_367,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\(1) => mem_intfc0_n_376,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1\(0) => mem_intfc0_n_368,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\(1) => mem_intfc0_n_371,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2\(0) => mem_intfc0_n_363,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\(1) => mem_intfc0_n_372,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3\(0) => mem_intfc0_n_364,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\(1) => mem_intfc0_n_438,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\(0) => mem_intfc0_n_434,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\(1) => mem_intfc0_n_435,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0\(0) => mem_intfc0_n_431,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\(1) => mem_intfc0_n_436,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1\(0) => mem_intfc0_n_432,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\(1) => mem_intfc0_n_439,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2\(0) => mem_intfc0_n_427,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\(1) => mem_intfc0_n_440,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3\(0) => mem_intfc0_n_428,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\(1) => mem_intfc0_n_265,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\(0) => mem_intfc0_n_257,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\(1) => mem_intfc0_n_266,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_0\(0) => mem_intfc0_n_258,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1\(1) => mem_intfc0_n_261,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]_1\(0) => mem_intfc0_n_253,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\(1) => mem_intfc0_n_506,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\(0) => mem_intfc0_n_498,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\(1) => mem_intfc0_n_503,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0\(0) => mem_intfc0_n_495,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\(1) => mem_intfc0_n_504,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1\(0) => mem_intfc0_n_496,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\(1) => mem_intfc0_n_499,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2\(0) => mem_intfc0_n_491,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\(1) => mem_intfc0_n_500,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3\(0) => mem_intfc0_n_492,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\(1) => mem_intfc0_n_570,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\(0) => mem_intfc0_n_562,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\(1) => mem_intfc0_n_567,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0\(0) => mem_intfc0_n_559,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\(1) => mem_intfc0_n_568,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1\(0) => mem_intfc0_n_560,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\(1) => mem_intfc0_n_563,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2\(0) => mem_intfc0_n_555,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\(1) => mem_intfc0_n_564,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3\(0) => mem_intfc0_n_556,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1) => mem_intfc0_n_101,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(0) => mem_intfc0_n_93,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\(1) => mem_intfc0_n_102,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\(0) => mem_intfc0_n_94,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\(1) => mem_intfc0_n_105,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1\(0) => mem_intfc0_n_97,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1) => mem_intfc0_n_169,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(0) => mem_intfc0_n_157,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\(1) => mem_intfc0_n_170,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\(0) => mem_intfc0_n_158,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\(1) => mem_intfc0_n_165,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1\(0) => mem_intfc0_n_161,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1) => mem_intfc0_n_229,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(0) => mem_intfc0_n_221,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\(1) => mem_intfc0_n_230,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\(0) => mem_intfc0_n_222,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\(1) => mem_intfc0_n_233,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1\(0) => mem_intfc0_n_225,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1) => mem_intfc0_n_297,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(0) => mem_intfc0_n_285,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\(1) => mem_intfc0_n_298,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\(0) => mem_intfc0_n_286,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\(1) => mem_intfc0_n_293,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1\(0) => mem_intfc0_n_289,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1) => mem_intfc0_n_357,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(0) => mem_intfc0_n_349,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\(1) => mem_intfc0_n_358,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\(0) => mem_intfc0_n_350,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\(1) => mem_intfc0_n_361,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1\(0) => mem_intfc0_n_353,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1) => mem_intfc0_n_425,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(0) => mem_intfc0_n_413,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\(1) => mem_intfc0_n_426,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\(0) => mem_intfc0_n_414,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\(1) => mem_intfc0_n_421,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1\(0) => mem_intfc0_n_417,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1) => mem_intfc0_n_485,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(0) => mem_intfc0_n_477,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\(1) => mem_intfc0_n_486,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\(0) => mem_intfc0_n_478,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\(1) => mem_intfc0_n_489,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1\(0) => mem_intfc0_n_481,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1) => mem_intfc0_n_549,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(0) => mem_intfc0_n_545,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\(1) => mem_intfc0_n_550,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\(0) => mem_intfc0_n_546,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\(1) => mem_intfc0_n_553,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1\(0) => mem_intfc0_n_541,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\(1) => mem_intfc0_n_329,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\(0) => mem_intfc0_n_317,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\(1) => mem_intfc0_n_330,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_0\(0) => mem_intfc0_n_318,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1\(1) => mem_intfc0_n_325,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]_1\(0) => mem_intfc0_n_321,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1) => mem_intfc0_n_103,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(0) => mem_intfc0_n_95,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\(1) => mem_intfc0_n_99,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\(0) => mem_intfc0_n_91,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1) => mem_intfc0_n_166,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(0) => mem_intfc0_n_162,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\(1) => mem_intfc0_n_163,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\(0) => mem_intfc0_n_159,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\(1) => mem_intfc0_n_167,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1\(0) => mem_intfc0_n_155,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1) => mem_intfc0_n_234,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(0) => mem_intfc0_n_226,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\(1) => mem_intfc0_n_231,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\(0) => mem_intfc0_n_223,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\(1) => mem_intfc0_n_227,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1\(0) => mem_intfc0_n_219,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1) => mem_intfc0_n_294,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(0) => mem_intfc0_n_290,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\(1) => mem_intfc0_n_291,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\(0) => mem_intfc0_n_287,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\(1) => mem_intfc0_n_295,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1\(0) => mem_intfc0_n_283,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1) => mem_intfc0_n_362,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(0) => mem_intfc0_n_354,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\(1) => mem_intfc0_n_359,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\(0) => mem_intfc0_n_351,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\(1) => mem_intfc0_n_355,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1\(0) => mem_intfc0_n_347,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1) => mem_intfc0_n_422,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(0) => mem_intfc0_n_418,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\(1) => mem_intfc0_n_419,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\(0) => mem_intfc0_n_415,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\(1) => mem_intfc0_n_423,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1\(0) => mem_intfc0_n_411,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1) => mem_intfc0_n_490,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(0) => mem_intfc0_n_482,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\(1) => mem_intfc0_n_487,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\(0) => mem_intfc0_n_479,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\(1) => mem_intfc0_n_483,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1\(0) => mem_intfc0_n_475,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1) => mem_intfc0_n_554,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(0) => mem_intfc0_n_542,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(1) => mem_intfc0_n_551,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(0) => mem_intfc0_n_539,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\(1) => mem_intfc0_n_547,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\(0) => mem_intfc0_n_543,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\(1) => mem_intfc0_n_104,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\(0) => mem_intfc0_n_96,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\(1) => mem_intfc0_n_89,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0\(0) => mem_intfc0_n_81,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\(1) => mem_intfc0_n_90,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1\(0) => mem_intfc0_n_82,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\(1) => mem_intfc0_n_100,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2\(0) => mem_intfc0_n_92,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\(1) => mem_intfc0_n_85,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3\(0) => mem_intfc0_n_77,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\(1) => mem_intfc0_n_164,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\(0) => mem_intfc0_n_160,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\(1) => mem_intfc0_n_149,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0\(0) => mem_intfc0_n_141,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\(1) => mem_intfc0_n_150,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1\(0) => mem_intfc0_n_142,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\(1) => mem_intfc0_n_168,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2\(0) => mem_intfc0_n_156,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\(1) => mem_intfc0_n_153,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3\(0) => mem_intfc0_n_145,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\(1) => mem_intfc0_n_389,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\(0) => mem_intfc0_n_385,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\(1) => mem_intfc0_n_390,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_0\(0) => mem_intfc0_n_386,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1\(1) => mem_intfc0_n_393,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]_1\(0) => mem_intfc0_n_381,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\(1) => mem_intfc0_n_232,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\(0) => mem_intfc0_n_224,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\(1) => mem_intfc0_n_213,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0\(0) => mem_intfc0_n_205,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\(1) => mem_intfc0_n_214,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1\(0) => mem_intfc0_n_206,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\(1) => mem_intfc0_n_228,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2\(0) => mem_intfc0_n_220,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\(1) => mem_intfc0_n_217,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3\(0) => mem_intfc0_n_209,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\(1) => mem_intfc0_n_292,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\(0) => mem_intfc0_n_288,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\(1) => mem_intfc0_n_277,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0\(0) => mem_intfc0_n_269,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\(1) => mem_intfc0_n_278,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1\(0) => mem_intfc0_n_270,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\(1) => mem_intfc0_n_296,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2\(0) => mem_intfc0_n_284,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\(1) => mem_intfc0_n_281,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3\(0) => mem_intfc0_n_273,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\(1) => mem_intfc0_n_360,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\(0) => mem_intfc0_n_352,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\(1) => mem_intfc0_n_345,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0\(0) => mem_intfc0_n_333,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\(1) => mem_intfc0_n_346,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1\(0) => mem_intfc0_n_334,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\(1) => mem_intfc0_n_356,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2\(0) => mem_intfc0_n_348,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\(1) => mem_intfc0_n_341,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3\(0) => mem_intfc0_n_337,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\(1) => mem_intfc0_n_420,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\(0) => mem_intfc0_n_416,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\(1) => mem_intfc0_n_405,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0\(0) => mem_intfc0_n_397,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\(1) => mem_intfc0_n_406,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1\(0) => mem_intfc0_n_398,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\(1) => mem_intfc0_n_424,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2\(0) => mem_intfc0_n_412,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\(1) => mem_intfc0_n_409,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3\(0) => mem_intfc0_n_401,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\(1) => mem_intfc0_n_488,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\(0) => mem_intfc0_n_480,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\(1) => mem_intfc0_n_473,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0\(0) => mem_intfc0_n_465,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\(1) => mem_intfc0_n_474,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1\(0) => mem_intfc0_n_466,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\(1) => mem_intfc0_n_484,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2\(0) => mem_intfc0_n_476,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\(1) => mem_intfc0_n_469,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3\(0) => mem_intfc0_n_461,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\(1) => mem_intfc0_n_552,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\(0) => mem_intfc0_n_540,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\(1) => mem_intfc0_n_533,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0\(0) => mem_intfc0_n_525,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\(1) => mem_intfc0_n_534,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1\(0) => mem_intfc0_n_526,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\(1) => mem_intfc0_n_548,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2\(0) => mem_intfc0_n_544,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\(1) => mem_intfc0_n_537,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3\(0) => mem_intfc0_n_529,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1) => mem_intfc0_n_83,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(0) => mem_intfc0_n_75,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\(1) => mem_intfc0_n_87,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\(0) => mem_intfc0_n_79,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1) => mem_intfc0_n_154,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(0) => mem_intfc0_n_146,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\(1) => mem_intfc0_n_151,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\(0) => mem_intfc0_n_143,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\(1) => mem_intfc0_n_147,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1\(0) => mem_intfc0_n_139,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1) => mem_intfc0_n_218,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(0) => mem_intfc0_n_210,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\(1) => mem_intfc0_n_215,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\(0) => mem_intfc0_n_207,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\(1) => mem_intfc0_n_211,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1\(0) => mem_intfc0_n_203,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1) => mem_intfc0_n_282,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(0) => mem_intfc0_n_274,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\(1) => mem_intfc0_n_279,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\(0) => mem_intfc0_n_271,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\(1) => mem_intfc0_n_275,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1\(0) => mem_intfc0_n_267,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\(1) => mem_intfc0_n_457,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\(0) => mem_intfc0_n_445,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\(1) => mem_intfc0_n_458,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_0\(0) => mem_intfc0_n_446,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1\(1) => mem_intfc0_n_453,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]_1\(0) => mem_intfc0_n_449,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1) => mem_intfc0_n_342,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(0) => mem_intfc0_n_338,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\(1) => mem_intfc0_n_339,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\(0) => mem_intfc0_n_335,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\(1) => mem_intfc0_n_343,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1\(0) => mem_intfc0_n_331,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1) => mem_intfc0_n_410,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(0) => mem_intfc0_n_402,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\(1) => mem_intfc0_n_407,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\(0) => mem_intfc0_n_399,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\(1) => mem_intfc0_n_403,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1\(0) => mem_intfc0_n_395,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1) => mem_intfc0_n_470,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(0) => mem_intfc0_n_462,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\(1) => mem_intfc0_n_467,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\(0) => mem_intfc0_n_459,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\(1) => mem_intfc0_n_471,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1\(0) => mem_intfc0_n_463,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1) => mem_intfc0_n_538,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(0) => mem_intfc0_n_530,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\(1) => mem_intfc0_n_535,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\(0) => mem_intfc0_n_527,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\(1) => mem_intfc0_n_531,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1\(0) => mem_intfc0_n_523,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1) => mem_intfc0_n_84,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(0) => mem_intfc0_n_76,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1) => mem_intfc0_n_88,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(0) => mem_intfc0_n_80,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1) => mem_intfc0_n_152,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(0) => mem_intfc0_n_144,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1) => mem_intfc0_n_148,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(0) => mem_intfc0_n_140,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1) => mem_intfc0_n_216,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(0) => mem_intfc0_n_208,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1) => mem_intfc0_n_212,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(0) => mem_intfc0_n_204,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1) => mem_intfc0_n_280,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(0) => mem_intfc0_n_272,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1) => mem_intfc0_n_276,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(0) => mem_intfc0_n_268,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1) => mem_intfc0_n_340,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(0) => mem_intfc0_n_336,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1) => mem_intfc0_n_344,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(0) => mem_intfc0_n_332,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1) => mem_intfc0_n_408,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(0) => mem_intfc0_n_400,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1) => mem_intfc0_n_404,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(0) => mem_intfc0_n_396,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\(1) => mem_intfc0_n_517,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\(0) => mem_intfc0_n_509,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\(1) => mem_intfc0_n_518,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_0\(0) => mem_intfc0_n_510,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\(1) => mem_intfc0_n_521,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]_1\(0) => mem_intfc0_n_513,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1) => mem_intfc0_n_468,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(0) => mem_intfc0_n_460,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1) => mem_intfc0_n_472,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(0) => mem_intfc0_n_464,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1) => mem_intfc0_n_536,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(0) => mem_intfc0_n_528,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1) => mem_intfc0_n_532,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(0) => mem_intfc0_n_524,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\(1) => mem_intfc0_n_585,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\(0) => mem_intfc0_n_573,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\(1) => mem_intfc0_n_586,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0\(0) => mem_intfc0_n_574,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\(1) => mem_intfc0_n_581,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1\(0) => mem_intfc0_n_577,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_2\(511 downto 0) => \ui_rd_data0/not_strict_mode.app_rd_data_ns\(511 downto 0),
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\(1) => mem_intfc0_n_138,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\(0) => mem_intfc0_n_130,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\(1) => mem_intfc0_n_135,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0\(0) => mem_intfc0_n_127,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\(1) => mem_intfc0_n_136,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1\(0) => mem_intfc0_n_128,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\(1) => mem_intfc0_n_131,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2\(0) => mem_intfc0_n_123,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\(1) => mem_intfc0_n_132,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_3\(0) => mem_intfc0_n_124,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\(1) => mem_intfc0_n_202,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\(0) => mem_intfc0_n_194,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\(1) => mem_intfc0_n_199,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0\(0) => mem_intfc0_n_191,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\(1) => mem_intfc0_n_200,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1\(0) => mem_intfc0_n_192,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\(1) => mem_intfc0_n_195,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2\(0) => mem_intfc0_n_187,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3\(1) => mem_intfc0_n_196,
      \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_3\(0) => mem_intfc0_n_188,
      \init_calib_complete_reg_rep__14\ => mem_intfc0_n_56,
      \init_calib_complete_reg_rep__15\ => mem_intfc0_n_57,
      \init_calib_complete_reg_rep__16\ => mem_intfc0_n_58,
      \init_calib_complete_reg_rep__17\ => mem_intfc0_n_59,
      \init_calib_complete_reg_rep__18\ => mem_intfc0_n_60,
      \init_calib_complete_reg_rep__19\ => mem_intfc0_n_61,
      \init_calib_complete_reg_rep__20\ => mem_intfc0_n_62,
      \init_calib_complete_reg_rep__21\ => mem_intfc0_n_63,
      \init_calib_complete_reg_rep__22\ => mem_intfc0_n_64,
      \my_empty_reg[7]\(95) => \ddr_phy_top0/mux_wrdata\(383),
      \my_empty_reg[7]\(94) => \ddr_phy_top0/mux_wrdata\(379),
      \my_empty_reg[7]\(93) => \ddr_phy_top0/mux_wrdata\(375),
      \my_empty_reg[7]\(92) => \ddr_phy_top0/mux_wrdata\(371),
      \my_empty_reg[7]\(91) => \ddr_phy_top0/mux_wrdata\(367),
      \my_empty_reg[7]\(90) => \ddr_phy_top0/mux_wrdata\(363),
      \my_empty_reg[7]\(89) => \ddr_phy_top0/mux_wrdata\(359),
      \my_empty_reg[7]\(88) => \ddr_phy_top0/mux_wrdata\(355),
      \my_empty_reg[7]\(87) => \ddr_phy_top0/mux_wrdata\(351),
      \my_empty_reg[7]\(86) => \ddr_phy_top0/mux_wrdata\(347),
      \my_empty_reg[7]\(85) => \ddr_phy_top0/mux_wrdata\(343),
      \my_empty_reg[7]\(84) => \ddr_phy_top0/mux_wrdata\(339),
      \my_empty_reg[7]\(83) => \ddr_phy_top0/mux_wrdata\(335),
      \my_empty_reg[7]\(82) => \ddr_phy_top0/mux_wrdata\(331),
      \my_empty_reg[7]\(81) => \ddr_phy_top0/mux_wrdata\(327),
      \my_empty_reg[7]\(80) => \ddr_phy_top0/mux_wrdata\(323),
      \my_empty_reg[7]\(79) => \ddr_phy_top0/mux_wrdata\(318),
      \my_empty_reg[7]\(78) => \ddr_phy_top0/mux_wrdata\(314),
      \my_empty_reg[7]\(77) => \ddr_phy_top0/mux_wrdata\(310),
      \my_empty_reg[7]\(76) => \ddr_phy_top0/mux_wrdata\(306),
      \my_empty_reg[7]\(75) => \ddr_phy_top0/mux_wrdata\(302),
      \my_empty_reg[7]\(74) => \ddr_phy_top0/mux_wrdata\(298),
      \my_empty_reg[7]\(73) => \ddr_phy_top0/mux_wrdata\(294),
      \my_empty_reg[7]\(72) => \ddr_phy_top0/mux_wrdata\(290),
      \my_empty_reg[7]\(71) => \ddr_phy_top0/mux_wrdata\(286),
      \my_empty_reg[7]\(70) => \ddr_phy_top0/mux_wrdata\(282),
      \my_empty_reg[7]\(69) => \ddr_phy_top0/mux_wrdata\(278),
      \my_empty_reg[7]\(68) => \ddr_phy_top0/mux_wrdata\(274),
      \my_empty_reg[7]\(67) => \ddr_phy_top0/mux_wrdata\(270),
      \my_empty_reg[7]\(66) => \ddr_phy_top0/mux_wrdata\(266),
      \my_empty_reg[7]\(65) => \ddr_phy_top0/mux_wrdata\(262),
      \my_empty_reg[7]\(64) => \ddr_phy_top0/mux_wrdata\(258),
      \my_empty_reg[7]\(63) => \ddr_phy_top0/mux_wrdata\(254),
      \my_empty_reg[7]\(62) => \ddr_phy_top0/mux_wrdata\(250),
      \my_empty_reg[7]\(61) => \ddr_phy_top0/mux_wrdata\(246),
      \my_empty_reg[7]\(60) => \ddr_phy_top0/mux_wrdata\(242),
      \my_empty_reg[7]\(59) => \ddr_phy_top0/mux_wrdata\(238),
      \my_empty_reg[7]\(58) => \ddr_phy_top0/mux_wrdata\(234),
      \my_empty_reg[7]\(57) => \ddr_phy_top0/mux_wrdata\(230),
      \my_empty_reg[7]\(56) => \ddr_phy_top0/mux_wrdata\(226),
      \my_empty_reg[7]\(55) => \ddr_phy_top0/mux_wrdata\(222),
      \my_empty_reg[7]\(54) => \ddr_phy_top0/mux_wrdata\(218),
      \my_empty_reg[7]\(53) => \ddr_phy_top0/mux_wrdata\(214),
      \my_empty_reg[7]\(52) => \ddr_phy_top0/mux_wrdata\(210),
      \my_empty_reg[7]\(51) => \ddr_phy_top0/mux_wrdata\(206),
      \my_empty_reg[7]\(50) => \ddr_phy_top0/mux_wrdata\(202),
      \my_empty_reg[7]\(49) => \ddr_phy_top0/mux_wrdata\(198),
      \my_empty_reg[7]\(48) => \ddr_phy_top0/mux_wrdata\(194),
      \my_empty_reg[7]\(47) => \ddr_phy_top0/mux_wrdata\(189),
      \my_empty_reg[7]\(46) => \ddr_phy_top0/mux_wrdata\(185),
      \my_empty_reg[7]\(45) => \ddr_phy_top0/mux_wrdata\(181),
      \my_empty_reg[7]\(44) => \ddr_phy_top0/mux_wrdata\(177),
      \my_empty_reg[7]\(43) => \ddr_phy_top0/mux_wrdata\(173),
      \my_empty_reg[7]\(42) => \ddr_phy_top0/mux_wrdata\(169),
      \my_empty_reg[7]\(41) => \ddr_phy_top0/mux_wrdata\(165),
      \my_empty_reg[7]\(40) => \ddr_phy_top0/mux_wrdata\(161),
      \my_empty_reg[7]\(39) => \ddr_phy_top0/mux_wrdata\(157),
      \my_empty_reg[7]\(38) => \ddr_phy_top0/mux_wrdata\(153),
      \my_empty_reg[7]\(37) => \ddr_phy_top0/mux_wrdata\(149),
      \my_empty_reg[7]\(36) => \ddr_phy_top0/mux_wrdata\(145),
      \my_empty_reg[7]\(35) => \ddr_phy_top0/mux_wrdata\(141),
      \my_empty_reg[7]\(34) => \ddr_phy_top0/mux_wrdata\(137),
      \my_empty_reg[7]\(33) => \ddr_phy_top0/mux_wrdata\(133),
      \my_empty_reg[7]\(32) => \ddr_phy_top0/mux_wrdata\(129),
      \my_empty_reg[7]\(31) => \ddr_phy_top0/mux_wrdata\(63),
      \my_empty_reg[7]\(30 downto 29) => \ddr_phy_top0/mux_wrdata\(60 downto 59),
      \my_empty_reg[7]\(28 downto 27) => \ddr_phy_top0/mux_wrdata\(56 downto 55),
      \my_empty_reg[7]\(26 downto 25) => \ddr_phy_top0/mux_wrdata\(52 downto 51),
      \my_empty_reg[7]\(24 downto 23) => \ddr_phy_top0/mux_wrdata\(48 downto 47),
      \my_empty_reg[7]\(22 downto 21) => \ddr_phy_top0/mux_wrdata\(44 downto 43),
      \my_empty_reg[7]\(20 downto 19) => \ddr_phy_top0/mux_wrdata\(40 downto 39),
      \my_empty_reg[7]\(18 downto 17) => \ddr_phy_top0/mux_wrdata\(36 downto 35),
      \my_empty_reg[7]\(16 downto 15) => \ddr_phy_top0/mux_wrdata\(32 downto 31),
      \my_empty_reg[7]\(14 downto 13) => \ddr_phy_top0/mux_wrdata\(28 downto 27),
      \my_empty_reg[7]\(12 downto 11) => \ddr_phy_top0/mux_wrdata\(24 downto 23),
      \my_empty_reg[7]\(10 downto 9) => \ddr_phy_top0/mux_wrdata\(20 downto 19),
      \my_empty_reg[7]\(8 downto 7) => \ddr_phy_top0/mux_wrdata\(16 downto 15),
      \my_empty_reg[7]\(6 downto 5) => \ddr_phy_top0/mux_wrdata\(12 downto 11),
      \my_empty_reg[7]\(4 downto 3) => \ddr_phy_top0/mux_wrdata\(8 downto 7),
      \my_empty_reg[7]\(2 downto 1) => \ddr_phy_top0/mux_wrdata\(4 downto 3),
      \my_empty_reg[7]\(0) => \ddr_phy_top0/mux_wrdata\(0),
      \my_empty_reg[7]_0\(575 downto 512) => wr_data_mask(63 downto 0),
      \my_empty_reg[7]_0\(511 downto 0) => wr_data(511 downto 0),
      \not_strict_mode.app_rd_data_end_ns\ => \ui_rd_data0/not_strict_mode.app_rd_data_end_ns\,
      \not_strict_mode.app_rd_data_end_reg\(0) => \ui_rd_data0/not_strict_mode.rd_status\(1),
      \not_strict_mode.app_rd_data_reg[101]\(1 downto 0) => \ui_rd_data0/p_209_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[103]\(1 downto 0) => \ui_rd_data0/p_204_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[105]\(1 downto 0) => \ui_rd_data0/p_205_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[107]\(1 downto 0) => \ui_rd_data0/p_206_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[109]\(1 downto 0) => \ui_rd_data0/p_201_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[111]\(1 downto 0) => \ui_rd_data0/p_202_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[113]\(1 downto 0) => \ui_rd_data0/p_203_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[115]\(1 downto 0) => \ui_rd_data0/p_198_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[117]\(1 downto 0) => \ui_rd_data0/p_199_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[119]\(1 downto 0) => \ui_rd_data0/p_200_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[11]\(1 downto 0) => \ui_rd_data0/p_254_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[121]\(1 downto 0) => \ui_rd_data0/p_195_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[123]\(1 downto 0) => \ui_rd_data0/p_196_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[125]\(1 downto 0) => \ui_rd_data0/p_197_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[127]\(1 downto 0) => \ui_rd_data0/p_192_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[129]\(1 downto 0) => \ui_rd_data0/p_193_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[131]\(1 downto 0) => \ui_rd_data0/p_194_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[133]\(1 downto 0) => \ui_rd_data0/p_189_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[135]\(1 downto 0) => \ui_rd_data0/p_190_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[137]\(1 downto 0) => \ui_rd_data0/p_191_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[139]\(1 downto 0) => \ui_rd_data0/p_186_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[13]\(1 downto 0) => \ui_rd_data0/p_249_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[141]\(1 downto 0) => \ui_rd_data0/p_187_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[143]\(1 downto 0) => \ui_rd_data0/p_188_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[145]\(1 downto 0) => \ui_rd_data0/p_183_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[147]\(1 downto 0) => \ui_rd_data0/p_184_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[149]\(1 downto 0) => \ui_rd_data0/p_185_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[151]\(1 downto 0) => \ui_rd_data0/p_180_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[153]\(1 downto 0) => \ui_rd_data0/p_181_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[155]\(1 downto 0) => \ui_rd_data0/p_182_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[157]\(1 downto 0) => \ui_rd_data0/p_177_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[159]\(1 downto 0) => \ui_rd_data0/p_178_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[15]\(1 downto 0) => \ui_rd_data0/p_250_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[161]\(1 downto 0) => \ui_rd_data0/p_179_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[163]\(1 downto 0) => \ui_rd_data0/p_174_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[165]\(1 downto 0) => \ui_rd_data0/p_175_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[167]\(1 downto 0) => \ui_rd_data0/p_176_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[169]\(1 downto 0) => \ui_rd_data0/p_171_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[171]\(1 downto 0) => \ui_rd_data0/p_172_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[173]\(1 downto 0) => \ui_rd_data0/p_173_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[175]\(1 downto 0) => \ui_rd_data0/p_168_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[177]\(1 downto 0) => \ui_rd_data0/p_169_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[179]\(1 downto 0) => \ui_rd_data0/p_170_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[17]\(1 downto 0) => \ui_rd_data0/p_251_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[181]\(1 downto 0) => \ui_rd_data0/p_165_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[183]\(1 downto 0) => \ui_rd_data0/p_166_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[185]\(1 downto 0) => \ui_rd_data0/p_167_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[187]\(1 downto 0) => \ui_rd_data0/p_162_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[189]\(1 downto 0) => \ui_rd_data0/p_163_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[191]\(1 downto 0) => \ui_rd_data0/p_164_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[193]\(1 downto 0) => \ui_rd_data0/p_159_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[195]\(1 downto 0) => \ui_rd_data0/p_160_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[197]\(1 downto 0) => \ui_rd_data0/p_161_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[199]\(1 downto 0) => \ui_rd_data0/p_156_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[19]\(1 downto 0) => \ui_rd_data0/p_246_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[201]\(1 downto 0) => \ui_rd_data0/p_157_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[203]\(1 downto 0) => \ui_rd_data0/p_158_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[205]\(1 downto 0) => \ui_rd_data0/p_153_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[207]\(1 downto 0) => \ui_rd_data0/p_154_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[209]\(1 downto 0) => \ui_rd_data0/p_155_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[211]\(1 downto 0) => \ui_rd_data0/p_150_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[213]\(1 downto 0) => \ui_rd_data0/p_151_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[215]\(1 downto 0) => \ui_rd_data0/p_152_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[217]\(1 downto 0) => \ui_rd_data0/p_147_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[219]\(1 downto 0) => \ui_rd_data0/p_148_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[21]\(1 downto 0) => \ui_rd_data0/p_247_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[221]\(1 downto 0) => \ui_rd_data0/p_149_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[223]\(1 downto 0) => \ui_rd_data0/p_144_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[225]\(1 downto 0) => \ui_rd_data0/p_145_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[227]\(1 downto 0) => \ui_rd_data0/p_146_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[229]\(1 downto 0) => \ui_rd_data0/p_141_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[231]\(1 downto 0) => \ui_rd_data0/p_142_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[233]\(1 downto 0) => \ui_rd_data0/p_143_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[235]\(1 downto 0) => \ui_rd_data0/p_138_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[237]\(1 downto 0) => \ui_rd_data0/p_139_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[239]\(1 downto 0) => \ui_rd_data0/p_140_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[23]\(1 downto 0) => \ui_rd_data0/p_248_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[241]\(1 downto 0) => \ui_rd_data0/p_135_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[243]\(1 downto 0) => \ui_rd_data0/p_136_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[245]\(1 downto 0) => \ui_rd_data0/p_137_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[247]\(1 downto 0) => \ui_rd_data0/p_132_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[249]\(1 downto 0) => \ui_rd_data0/p_133_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[251]\(1 downto 0) => \ui_rd_data0/p_134_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[253]\(1 downto 0) => \ui_rd_data0/p_129_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[255]\(1 downto 0) => \ui_rd_data0/p_130_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[257]\(1 downto 0) => \ui_rd_data0/p_131_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[259]\(1 downto 0) => \ui_rd_data0/p_126_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[25]\(1 downto 0) => \ui_rd_data0/p_243_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[261]\(1 downto 0) => \ui_rd_data0/p_127_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[263]\(1 downto 0) => \ui_rd_data0/p_128_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[265]\(1 downto 0) => \ui_rd_data0/p_123_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[267]\(1 downto 0) => \ui_rd_data0/p_124_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[269]\(1 downto 0) => \ui_rd_data0/p_125_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[271]\(1 downto 0) => \ui_rd_data0/p_120_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[273]\(1 downto 0) => \ui_rd_data0/p_121_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[275]\(1 downto 0) => \ui_rd_data0/p_122_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[277]\(1 downto 0) => \ui_rd_data0/p_117_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[279]\(1 downto 0) => \ui_rd_data0/p_118_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[27]\(1 downto 0) => \ui_rd_data0/p_244_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[281]\(1 downto 0) => \ui_rd_data0/p_119_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[283]\(1 downto 0) => \ui_rd_data0/p_114_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[285]\(1 downto 0) => \ui_rd_data0/p_115_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[287]\(1 downto 0) => \ui_rd_data0/p_116_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[289]\(1 downto 0) => \ui_rd_data0/p_111_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[291]\(1 downto 0) => \ui_rd_data0/p_112_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[293]\(1 downto 0) => \ui_rd_data0/p_113_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[295]\(1 downto 0) => \ui_rd_data0/p_108_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[297]\(1 downto 0) => \ui_rd_data0/p_109_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[299]\(1 downto 0) => \ui_rd_data0/p_110_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[29]\(1 downto 0) => \ui_rd_data0/p_245_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[301]\(1 downto 0) => \ui_rd_data0/p_105_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[303]\(1 downto 0) => \ui_rd_data0/p_106_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[305]\(1 downto 0) => \ui_rd_data0/p_107_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[307]\(1 downto 0) => \ui_rd_data0/p_102_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[309]\(1 downto 0) => \ui_rd_data0/p_103_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[311]\(1 downto 0) => \ui_rd_data0/p_104_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[313]\(1 downto 0) => \ui_rd_data0/p_99_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[315]\(1 downto 0) => \ui_rd_data0/p_100_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[317]\(1 downto 0) => \ui_rd_data0/p_101_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[319]\(1 downto 0) => \ui_rd_data0/p_96_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[31]\(1 downto 0) => \ui_rd_data0/p_240_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[321]\(1 downto 0) => \ui_rd_data0/p_97_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[323]\(1 downto 0) => \ui_rd_data0/p_98_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[325]\(1 downto 0) => \ui_rd_data0/p_93_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[327]\(1 downto 0) => \ui_rd_data0/p_94_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[329]\(1 downto 0) => \ui_rd_data0/p_95_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[331]\(1 downto 0) => \ui_rd_data0/p_90_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[333]\(1 downto 0) => \ui_rd_data0/p_91_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[335]\(1 downto 0) => \ui_rd_data0/p_92_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[337]\(1 downto 0) => \ui_rd_data0/p_87_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[339]\(1 downto 0) => \ui_rd_data0/p_88_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[33]\(1 downto 0) => \ui_rd_data0/p_241_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[341]\(1 downto 0) => \ui_rd_data0/p_89_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[343]\(1 downto 0) => \ui_rd_data0/p_84_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[345]\(1 downto 0) => \ui_rd_data0/p_85_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[347]\(1 downto 0) => \ui_rd_data0/p_86_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[349]\(1 downto 0) => \ui_rd_data0/p_81_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[351]\(1 downto 0) => \ui_rd_data0/p_82_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[353]\(1 downto 0) => \ui_rd_data0/p_83_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[355]\(1 downto 0) => \ui_rd_data0/p_78_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[357]\(1 downto 0) => \ui_rd_data0/p_79_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[359]\(1 downto 0) => \ui_rd_data0/p_80_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[35]\(1 downto 0) => \ui_rd_data0/p_242_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[361]\(1 downto 0) => \ui_rd_data0/p_75_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[363]\(1 downto 0) => \ui_rd_data0/p_76_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[365]\(1 downto 0) => \ui_rd_data0/p_77_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[367]\(1 downto 0) => \ui_rd_data0/p_72_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[369]\(1 downto 0) => \ui_rd_data0/p_73_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[371]\(1 downto 0) => \ui_rd_data0/p_74_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[373]\(1 downto 0) => \ui_rd_data0/p_69_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[375]\(1 downto 0) => \ui_rd_data0/p_70_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[377]\(1 downto 0) => \ui_rd_data0/p_71_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[379]\(1 downto 0) => \ui_rd_data0/p_66_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[37]\(1 downto 0) => \ui_rd_data0/p_237_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[381]\(1 downto 0) => \ui_rd_data0/p_67_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[383]\(1 downto 0) => \ui_rd_data0/p_68_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[385]\(1 downto 0) => \ui_rd_data0/p_63_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[387]\(1 downto 0) => \ui_rd_data0/p_64_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[389]\(1 downto 0) => \ui_rd_data0/p_65_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[391]\(1 downto 0) => \ui_rd_data0/p_60_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[393]\(1 downto 0) => \ui_rd_data0/p_61_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[395]\(1 downto 0) => \ui_rd_data0/p_62_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[397]\(1 downto 0) => \ui_rd_data0/p_57_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[399]\(1 downto 0) => \ui_rd_data0/p_58_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[39]\(1 downto 0) => \ui_rd_data0/p_238_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[401]\(1 downto 0) => \ui_rd_data0/p_59_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[403]\(1 downto 0) => \ui_rd_data0/p_54_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[405]\(1 downto 0) => \ui_rd_data0/p_55_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[407]\(1 downto 0) => \ui_rd_data0/p_56_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[409]\(1 downto 0) => \ui_rd_data0/p_51_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[411]\(1 downto 0) => \ui_rd_data0/p_52_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[413]\(1 downto 0) => \ui_rd_data0/p_53_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[415]\(1 downto 0) => \ui_rd_data0/p_48_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[417]\(1 downto 0) => \ui_rd_data0/p_49_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[419]\(1 downto 0) => \ui_rd_data0/p_50_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[41]\(1 downto 0) => \ui_rd_data0/p_239_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[421]\(1 downto 0) => \ui_rd_data0/p_45_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[423]\(1 downto 0) => \ui_rd_data0/p_46_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[425]\(1 downto 0) => \ui_rd_data0/p_47_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[427]\(1 downto 0) => \ui_rd_data0/p_42_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[429]\(1 downto 0) => \ui_rd_data0/p_43_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[431]\(1 downto 0) => \ui_rd_data0/p_44_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[433]\(1 downto 0) => \ui_rd_data0/p_39_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[435]\(1 downto 0) => \ui_rd_data0/p_40_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[437]\(1 downto 0) => \ui_rd_data0/p_41_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[439]\(1 downto 0) => \ui_rd_data0/p_36_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[43]\(1 downto 0) => \ui_rd_data0/p_234_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[441]\(1 downto 0) => \ui_rd_data0/p_37_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[443]\(1 downto 0) => \ui_rd_data0/p_38_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[445]\(1 downto 0) => \ui_rd_data0/p_33_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[447]\(1 downto 0) => \ui_rd_data0/p_34_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[449]\(1 downto 0) => \ui_rd_data0/p_35_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[451]\(1 downto 0) => \ui_rd_data0/p_30_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[453]\(1 downto 0) => \ui_rd_data0/p_31_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[455]\(1 downto 0) => \ui_rd_data0/p_32_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[457]\(1 downto 0) => \ui_rd_data0/p_27_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[459]\(1 downto 0) => \ui_rd_data0/p_28_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[45]\(1 downto 0) => \ui_rd_data0/p_235_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[461]\(1 downto 0) => \ui_rd_data0/p_29_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[463]\(1 downto 0) => \ui_rd_data0/p_24_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[465]\(1 downto 0) => \ui_rd_data0/p_25_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[467]\(1 downto 0) => \ui_rd_data0/p_26_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[469]\(1 downto 0) => \ui_rd_data0/p_21_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[471]\(1 downto 0) => \ui_rd_data0/p_22_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[473]\(1 downto 0) => \ui_rd_data0/p_23_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[475]\(1 downto 0) => \ui_rd_data0/p_18_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[477]\(1 downto 0) => \ui_rd_data0/p_19_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[479]\(1 downto 0) => \ui_rd_data0/p_20_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[47]\(1 downto 0) => \ui_rd_data0/p_236_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[481]\(1 downto 0) => \ui_rd_data0/p_15_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[483]\(1 downto 0) => \ui_rd_data0/p_16_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[485]\(1 downto 0) => \ui_rd_data0/p_17_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[487]\(1 downto 0) => \ui_rd_data0/p_12_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[489]\(1 downto 0) => \ui_rd_data0/p_13_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[491]\(1 downto 0) => \ui_rd_data0/p_14_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[493]\(1 downto 0) => \ui_rd_data0/p_9_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[495]\(1 downto 0) => \ui_rd_data0/p_10_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[497]\(1 downto 0) => \ui_rd_data0/p_11_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[499]\(1 downto 0) => \ui_rd_data0/p_6_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[49]\(1 downto 0) => \ui_rd_data0/p_231_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[501]\(1 downto 0) => \ui_rd_data0/p_7_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[503]\(1 downto 0) => \ui_rd_data0/p_8_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[505]\(1 downto 0) => \ui_rd_data0/p_3_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[507]\(1 downto 0) => \ui_rd_data0/p_4_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[509]\(1 downto 0) => \ui_rd_data0/p_5_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[511]\(1) => u_ui_top_n_518,
      \not_strict_mode.app_rd_data_reg[511]\(0) => u_ui_top_n_519,
      \not_strict_mode.app_rd_data_reg[51]\(1 downto 0) => \ui_rd_data0/p_232_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[53]\(1 downto 0) => \ui_rd_data0/p_233_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[55]\(1 downto 0) => \ui_rd_data0/p_228_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[57]\(1 downto 0) => \ui_rd_data0/p_229_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[59]\(1 downto 0) => \ui_rd_data0/p_230_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[61]\(1 downto 0) => \ui_rd_data0/p_225_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[63]\(1 downto 0) => \ui_rd_data0/p_226_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[65]\(1 downto 0) => \ui_rd_data0/p_227_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[67]\(1 downto 0) => \ui_rd_data0/p_222_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[69]\(1 downto 0) => \ui_rd_data0/p_223_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[71]\(1 downto 0) => \ui_rd_data0/p_224_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[73]\(1 downto 0) => \ui_rd_data0/p_219_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[75]\(1 downto 0) => \ui_rd_data0/p_220_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[77]\(1 downto 0) => \ui_rd_data0/p_221_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[79]\(1 downto 0) => \ui_rd_data0/p_216_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[7]\(1 downto 0) => \ui_rd_data0/p_252_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[81]\(1 downto 0) => \ui_rd_data0/p_217_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[83]\(1 downto 0) => \ui_rd_data0/p_218_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[85]\(1 downto 0) => \ui_rd_data0/p_213_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[87]\(1 downto 0) => \ui_rd_data0/p_214_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[89]\(1 downto 0) => \ui_rd_data0/p_215_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[91]\(1 downto 0) => \ui_rd_data0/p_210_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[93]\(1 downto 0) => \ui_rd_data0/p_211_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[95]\(1 downto 0) => \ui_rd_data0/p_212_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[97]\(1 downto 0) => \ui_rd_data0/p_207_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[99]\(1 downto 0) => \ui_rd_data0/p_208_out\(1 downto 0),
      \not_strict_mode.app_rd_data_reg[9]\(1 downto 0) => \ui_rd_data0/p_253_out\(1 downto 0),
      \not_strict_mode.bypass__0\ => \ui_rd_data0/not_strict_mode.bypass__0\,
      \not_strict_mode.rd_buf_we\ => \ui_rd_data0/not_strict_mode.rd_buf_we\,
      \not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4]\ => u_ui_top_n_3,
      \pointer_ram.pointer_we\ => \ui_wr_data0/pointer_ram.pointer_we\,
      ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0),
      ram_init_done_r => ram_init_done_r,
      rb_hit_busy_r_reg => u_ui_top_n_542,
      rb_hit_busy_r_reg_0 => u_ui_top_n_546,
      rb_hit_busy_r_reg_1 => u_ui_top_n_547,
      \req_bank_r_lcl_reg[2]\(2 downto 0) => bank(2 downto 0),
      \req_bank_r_lcl_reg[2]_0\(8 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 3),
      \req_col_r_reg[9]\(9 downto 0) => col(9 downto 0),
      \req_data_buf_addr_r_reg[4]\(4 downto 0) => data_buf_addr(4 downto 0),
      \req_row_r_lcl_reg[13]\(10 downto 9) => \mc0/bank_mach0/req_row_r\(55 downto 54),
      \req_row_r_lcl_reg[13]\(8 downto 7) => \mc0/bank_mach0/req_row_r\(41 downto 40),
      \req_row_r_lcl_reg[13]\(6 downto 5) => \mc0/bank_mach0/req_row_r\(27 downto 26),
      \req_row_r_lcl_reg[13]\(4 downto 2) => \mc0/bank_mach0/req_row_r\(19 downto 17),
      \req_row_r_lcl_reg[13]\(1 downto 0) => \mc0/bank_mach0/req_row_r\(13 downto 12),
      reset_reg => reset_reg_n_0,
      row_hit_r_reg(0) => u_ui_top_n_538,
      row_hit_r_reg_0(0) => u_ui_top_n_539,
      row_hit_r_reg_1(0) => u_ui_top_n_540,
      row_hit_r_reg_2(0) => u_ui_top_n_541,
      use_addr => use_addr
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0_mig_7series_0_mig is
  port (
    ui_clk : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    ui_clk_sync_rst : out STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    iserdes_clk : out STD_LOGIC;
    iserdes_clk_0 : out STD_LOGIC;
    iserdes_clk_1 : out STD_LOGIC;
    iserdes_clk_2 : out STD_LOGIC;
    iserdes_clk_3 : out STD_LOGIC;
    iserdes_clk_4 : out STD_LOGIC;
    iserdes_clk_5 : out STD_LOGIC;
    iserdes_clk_6 : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_ras_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    app_rdy : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    app_rd_data_end : out STD_LOGIC;
    app_rd_data : out STD_LOGIC_VECTOR ( 511 downto 0 );
    ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    init_calib_complete : out STD_LOGIC;
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    CLKB0 : in STD_LOGIC;
    CLKB0_7 : in STD_LOGIC;
    CLKB0_8 : in STD_LOGIC;
    CLKB0_9 : in STD_LOGIC;
    CLKB0_10 : in STD_LOGIC;
    CLKB0_11 : in STD_LOGIC;
    CLKB0_12 : in STD_LOGIC;
    CLKB0_13 : in STD_LOGIC;
    clk_ref_i : in STD_LOGIC;
    sys_rst : in STD_LOGIC;
    sys_clk_i : in STD_LOGIC;
    app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_wren : in STD_LOGIC;
    app_wdf_end : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of mig_7series_0_mig_7series_0_mig : entity is "mig_7series_0_mig";
end mig_7series_0_mig_7series_0_mig;

architecture STRUCTURE of mig_7series_0_mig_7series_0_mig is
  signal freq_refclk : STD_LOGIC;
  signal iodelay_ctrl_rdy : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row0_rd_done1\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cnt_shift_r0\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/idelay_tap_limit_r0\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pi_cnt_dec\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\ : STD_LOGIC;
  signal \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/RST0\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\ : STD_LOGIC;
  signal mem_refclk : STD_LOGIC;
  signal mmcm_clk : STD_LOGIC;
  signal pll_locked : STD_LOGIC;
  signal sync_pulse : STD_LOGIC;
  signal sys_rst_act_hi : STD_LOGIC;
  signal u_ddr3_infrastructure_n_0 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_10 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_11 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_12 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_13 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_14 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_15 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_16 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_17 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_18 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_19 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_20 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_21 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_22 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_23 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_24 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_25 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_26 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_27 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_28 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_29 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_32 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_33 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_34 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_35 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_36 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_38 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_40 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_41 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_6 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_7 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_8 : STD_LOGIC;
  signal u_ddr3_infrastructure_n_9 : STD_LOGIC;
  signal u_memc_ui_top_std_n_49 : STD_LOGIC;
  signal u_memc_ui_top_std_n_50 : STD_LOGIC;
  signal u_memc_ui_top_std_n_54 : STD_LOGIC;
  signal u_memc_ui_top_std_n_56 : STD_LOGIC;
  signal \^ui_clk\ : STD_LOGIC;
  signal \^ui_clk_sync_rst\ : STD_LOGIC;
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of u_memc_ui_top_std : label is "mig_7series_v2_3_ddr3_7Series, 2013.4";
begin
  ui_clk <= \^ui_clk\;
  ui_clk_sync_rst <= \^ui_clk_sync_rst\;
\temp_mon_enabled.u_tempmon\: entity work.mig_7series_0_mig_7series_v2_3_tempmon
     port map (
      CLK => \^ui_clk\,
      D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0),
      clk_ref_i => clk_ref_i,
      in0 => \^ui_clk_sync_rst\
    );
u_ddr3_clk_ibuf: entity work.mig_7series_0_mig_7series_v2_3_clk_ibuf
     port map (
      mmcm_clk => mmcm_clk,
      sys_clk_i => sys_clk_i
    );
u_ddr3_infrastructure: entity work.mig_7series_0_mig_7series_v2_3_infrastructure
     port map (
      AS(0) => sys_rst_act_hi,
      CLK => \^ui_clk\,
      \FSM_sequential_fine_adj_state_r_reg[3]\(0) => u_ddr3_infrastructure_n_24,
      RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/RST0\,
      SR(1) => u_ddr3_infrastructure_n_6,
      SR(0) => u_ddr3_infrastructure_n_7,
      SS(0) => u_ddr3_infrastructure_n_36,
      bm_end_r1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_0 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_2 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\,
      clear => u_ddr3_infrastructure_n_40,
      \cnt_shift_r_reg[0]\ => u_ddr3_infrastructure_n_27,
      \cnt_shift_r_reg[0]_0\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cnt_shift_r0\,
      \complex_num_writes_dec_reg[0]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row0_rd_done1\,
      complex_oclkdelay_calib_start_int_reg => u_ddr3_infrastructure_n_10,
      \en_cnt_div4.enable_wrlvl_cnt_reg[4]\ => u_ddr3_infrastructure_n_38,
      \fine_inc_reg[6][5]\(1) => u_ddr3_infrastructure_n_15,
      \fine_inc_reg[6][5]\(0) => u_ddr3_infrastructure_n_16,
      freq_refclk => freq_refclk,
      in0 => \^ui_clk_sync_rst\,
      \init_state_r_reg[5]\ => u_memc_ui_top_std_n_56,
      \last_master_r_reg[2]\ => u_ddr3_infrastructure_n_25,
      mem_refclk => mem_refclk,
      mmcm_clk => mmcm_clk,
      new_cnt_cpt_r_reg => u_memc_ui_top_std_n_50,
      pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pi_cnt_dec\,
      \pi_rdval_cnt_reg[0]\(1) => u_ddr3_infrastructure_n_8,
      \pi_rdval_cnt_reg[0]\(0) => u_ddr3_infrastructure_n_9,
      pll_locked => pll_locked,
      po_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\,
      \po_rdval_cnt_reg[0]\ => u_ddr3_infrastructure_n_11,
      prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\,
      pre_wait_r_reg => u_ddr3_infrastructure_n_26,
      \ras_timer_r_reg[0]\ => u_ddr3_infrastructure_n_32,
      \ras_timer_r_reg[0]_0\ => u_ddr3_infrastructure_n_35,
      ras_timer_zero_r_reg => u_ddr3_infrastructure_n_33,
      ras_timer_zero_r_reg_0 => u_ddr3_infrastructure_n_34,
      rdlvl_stg1_start_reg => u_memc_ui_top_std_n_49,
      reset_reg => u_ddr3_infrastructure_n_29,
      \rst_ref_sync_r_reg[0][14]\ => u_memc_ui_top_std_n_54,
      rst_sync_r1_reg_0 => u_ddr3_infrastructure_n_0,
      samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\,
      \smallest_reg[7][3]\ => u_ddr3_infrastructure_n_14,
      sync_pulse => sync_pulse,
      \tap_cnt_cpt_r_reg[5]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/idelay_tap_limit_r0\,
      \two_inc_max_limit_reg[1]\(0) => u_ddr3_infrastructure_n_23,
      \wait_cnt_r_reg[0]\ => u_ddr3_infrastructure_n_28,
      \wait_cnt_r_reg[0]_0\(0) => u_ddr3_infrastructure_n_41,
      \wl_dqs_tap_count_r_reg[0][3][1]\(1) => u_ddr3_infrastructure_n_12,
      \wl_dqs_tap_count_r_reg[0][3][1]\(0) => u_ddr3_infrastructure_n_13,
      wrcal_pat_resume_r_reg(1) => u_ddr3_infrastructure_n_17,
      wrcal_pat_resume_r_reg(0) => u_ddr3_infrastructure_n_18,
      wrlvl_byte_redo_reg(3) => u_ddr3_infrastructure_n_19,
      wrlvl_byte_redo_reg(2) => u_ddr3_infrastructure_n_20,
      wrlvl_byte_redo_reg(1) => u_ddr3_infrastructure_n_21,
      wrlvl_byte_redo_reg(0) => u_ddr3_infrastructure_n_22
    );
u_iodelay_ctrl: entity work.mig_7series_0_mig_7series_v2_3_iodelay_ctrl
     port map (
      AS(0) => sys_rst_act_hi,
      clk_ref_i => clk_ref_i,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      sys_rst => sys_rst
    );
u_memc_ui_top_std: entity work.mig_7series_0_mig_7series_v2_3_memc_ui_top_std
     port map (
      CLK => \^ui_clk\,
      CLKB0 => CLKB0,
      CLKB0_10 => CLKB0_10,
      CLKB0_11 => CLKB0_11,
      CLKB0_12 => CLKB0_12,
      CLKB0_13 => CLKB0_13,
      CLKB0_7 => CLKB0_7,
      CLKB0_8 => CLKB0_8,
      CLKB0_9 => CLKB0_9,
      D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0),
      RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/RST0\,
      SR(1) => u_ddr3_infrastructure_n_6,
      SR(0) => u_ddr3_infrastructure_n_7,
      SS(0) => u_ddr3_infrastructure_n_36,
      app_addr(26 downto 0) => app_addr(26 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rd_data(511 downto 0) => app_rd_data(511 downto 0),
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_rdy => app_rdy,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      bm_end_r1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_0 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_1 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_2 => \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1\,
      bm_end_r1_reg => u_ddr3_infrastructure_n_32,
      bm_end_r1_reg_0 => u_ddr3_infrastructure_n_33,
      bm_end_r1_reg_1 => u_ddr3_infrastructure_n_34,
      bm_end_r1_reg_2 => u_ddr3_infrastructure_n_35,
      clear => u_ddr3_infrastructure_n_40,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0),
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => iserdes_clk,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => iserdes_clk_0,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1\ => iserdes_clk_1,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2\ => iserdes_clk_2,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3\ => iserdes_clk_3,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4\ => iserdes_clk_4,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_5\ => iserdes_clk_5,
      \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_6\ => iserdes_clk_6,
      \en_cnt_div4.enable_wrlvl_cnt_reg[3]\ => u_memc_ui_top_std_n_56,
      freq_refclk => freq_refclk,
      idelay_tap_limit_r_reg => u_memc_ui_top_std_n_50,
      in0 => \^ui_clk_sync_rst\,
      init_calib_complete => init_calib_complete,
      iodelay_ctrl_rdy(0) => iodelay_ctrl_rdy(0),
      mem_refclk => mem_refclk,
      new_cnt_cpt_r_reg(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/idelay_tap_limit_r0\,
      pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pi_cnt_dec\,
      pi_cnt_dec_reg(0) => u_ddr3_infrastructure_n_41,
      pll_locked => pll_locked,
      po_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\,
      prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\,
      prbs_rdlvl_done_pulse_reg(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row0_rd_done1\,
      rdlvl_stg1_start_r_reg => u_memc_ui_top_std_n_49,
      rdlvl_stg1_start_reg(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cnt_shift_r0\,
      rst_sync_r1_reg => u_memc_ui_top_std_n_54,
      \rstdiv0_sync_r1_reg_rep__10\(1) => u_ddr3_infrastructure_n_15,
      \rstdiv0_sync_r1_reg_rep__10\(0) => u_ddr3_infrastructure_n_16,
      \rstdiv0_sync_r1_reg_rep__12\(1) => u_ddr3_infrastructure_n_17,
      \rstdiv0_sync_r1_reg_rep__12\(0) => u_ddr3_infrastructure_n_18,
      \rstdiv0_sync_r1_reg_rep__13\(3) => u_ddr3_infrastructure_n_19,
      \rstdiv0_sync_r1_reg_rep__13\(2) => u_ddr3_infrastructure_n_20,
      \rstdiv0_sync_r1_reg_rep__13\(1) => u_ddr3_infrastructure_n_21,
      \rstdiv0_sync_r1_reg_rep__13\(0) => u_ddr3_infrastructure_n_22,
      \rstdiv0_sync_r1_reg_rep__15\(0) => u_ddr3_infrastructure_n_23,
      \rstdiv0_sync_r1_reg_rep__17\(0) => u_ddr3_infrastructure_n_24,
      \rstdiv0_sync_r1_reg_rep__19\ => u_ddr3_infrastructure_n_25,
      \rstdiv0_sync_r1_reg_rep__2\(1) => u_ddr3_infrastructure_n_8,
      \rstdiv0_sync_r1_reg_rep__2\(0) => u_ddr3_infrastructure_n_9,
      \rstdiv0_sync_r1_reg_rep__20\ => u_ddr3_infrastructure_n_26,
      \rstdiv0_sync_r1_reg_rep__21\ => u_ddr3_infrastructure_n_27,
      \rstdiv0_sync_r1_reg_rep__22\ => u_ddr3_infrastructure_n_28,
      \rstdiv0_sync_r1_reg_rep__22_0\ => u_ddr3_infrastructure_n_38,
      \rstdiv0_sync_r1_reg_rep__23\ => u_ddr3_infrastructure_n_29,
      \rstdiv0_sync_r1_reg_rep__4\ => u_ddr3_infrastructure_n_10,
      \rstdiv0_sync_r1_reg_rep__5\ => u_ddr3_infrastructure_n_11,
      \rstdiv0_sync_r1_reg_rep__6\(0) => u_ddr3_infrastructure_n_13,
      \rstdiv0_sync_r1_reg_rep__8\(1) => u_ddr3_infrastructure_n_14,
      \rstdiv0_sync_r1_reg_rep__8\(0) => u_ddr3_infrastructure_n_12,
      samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\,
      sync_pulse => sync_pulse,
      sys_rst => sys_rst,
      sys_rst_0 => u_ddr3_infrastructure_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_7series_0 is
  port (
    ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
    ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddr3_ras_n : out STD_LOGIC;
    ddr3_cas_n : out STD_LOGIC;
    ddr3_we_n : out STD_LOGIC;
    ddr3_reset_n : out STD_LOGIC;
    ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    app_addr : in STD_LOGIC_VECTOR ( 27 downto 0 );
    app_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 );
    app_en : in STD_LOGIC;
    app_wdf_data : in STD_LOGIC_VECTOR ( 511 downto 0 );
    app_wdf_end : in STD_LOGIC;
    app_wdf_mask : in STD_LOGIC_VECTOR ( 63 downto 0 );
    app_wdf_wren : in STD_LOGIC;
    app_rd_data : out STD_LOGIC_VECTOR ( 511 downto 0 );
    app_rd_data_end : out STD_LOGIC;
    app_rd_data_valid : out STD_LOGIC;
    app_rdy : out STD_LOGIC;
    app_wdf_rdy : out STD_LOGIC;
    app_sr_req : in STD_LOGIC;
    app_ref_req : in STD_LOGIC;
    app_zq_req : in STD_LOGIC;
    app_sr_active : out STD_LOGIC;
    app_ref_ack : out STD_LOGIC;
    app_zq_ack : out STD_LOGIC;
    ui_clk : out STD_LOGIC;
    ui_clk_sync_rst : out STD_LOGIC;
    init_calib_complete : out STD_LOGIC;
    sys_clk_i : in STD_LOGIC;
    clk_ref_i : in STD_LOGIC;
    sys_rst : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of mig_7series_0 : entity is true;
end mig_7series_0;

architecture STRUCTURE of mig_7series_0 is
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\ : STD_LOGIC;
  signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\ : STD_LOGIC;
begin
u_mig_7series_0_mig: entity work.mig_7series_0_mig_7series_0_mig
     port map (
      CLKB0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      CLKB0_10 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\,
      CLKB0_11 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      CLKB0_12 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      CLKB0_13 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      CLKB0_7 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      CLKB0_8 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      CLKB0_9 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      app_addr(26 downto 0) => app_addr(26 downto 0),
      app_cmd(1 downto 0) => app_cmd(1 downto 0),
      app_en => app_en,
      app_rd_data(511 downto 0) => app_rd_data(511 downto 0),
      app_rd_data_end => app_rd_data_end,
      app_rd_data_valid => app_rd_data_valid,
      app_rdy => app_rdy,
      app_ref_ack => app_ref_ack,
      app_ref_req => app_ref_req,
      app_sr_active => app_sr_active,
      app_sr_req => app_sr_req,
      app_wdf_data(511 downto 0) => app_wdf_data(511 downto 0),
      app_wdf_end => app_wdf_end,
      app_wdf_mask(63 downto 0) => app_wdf_mask(63 downto 0),
      app_wdf_rdy => app_wdf_rdy,
      app_wdf_wren => app_wdf_wren,
      app_zq_ack => app_zq_ack,
      app_zq_req => app_zq_req,
      clk_ref_i => clk_ref_i,
      ddr3_addr(13 downto 0) => ddr3_addr(13 downto 0),
      ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0),
      ddr3_cas_n => ddr3_cas_n,
      ddr3_cke(0) => ddr3_cke(0),
      ddr3_cs_n(0) => ddr3_cs_n(0),
      ddr3_dm(7 downto 0) => ddr3_dm(7 downto 0),
      ddr3_dq(63 downto 0) => ddr3_dq(63 downto 0),
      ddr3_dqs_n(7 downto 0) => ddr3_dqs_n(7 downto 0),
      ddr3_dqs_p(7 downto 0) => ddr3_dqs_p(7 downto 0),
      ddr3_odt(0) => ddr3_odt(0),
      ddr3_ras_n => ddr3_ras_n,
      ddr3_reset_n => ddr3_reset_n,
      ddr3_we_n => ddr3_we_n,
      ddr_ck_out(1) => ddr3_ck_n(0),
      ddr_ck_out(0) => ddr3_ck_p(0),
      init_calib_complete => init_calib_complete,
      iserdes_clk => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      iserdes_clk_0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      iserdes_clk_1 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      iserdes_clk_2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      iserdes_clk_3 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\,
      iserdes_clk_4 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk\,
      iserdes_clk_5 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk\,
      iserdes_clk_6 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\,
      sys_clk_i => sys_clk_i,
      sys_rst => sys_rst,
      ui_clk => ui_clk,
      ui_clk_sync_rst => ui_clk_sync_rst
    );
end STRUCTURE;
