                                                          Log file                                                       

Generated by MIG MIG Version 2.3
Coregen 14.7 - Build Number P_INT.20150528 on Mon Jan 8 13:12:53 2018


Creating the directory c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_designCreated the SDC file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/constraints/mig_7series_0.xdc Successfully
Created the OOC XDC file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/constraints/mig_7series_0_ooc.xdc SuccessfullyCreated the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_clk_ibuf.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_infrastructure.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_iodelay_ctrl.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/clocking/mig_7series_v2_3_tempmon.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_arb_mux.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_arb_row_col.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_arb_select.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_cntrl.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_common.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_compare.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_mach.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_queue.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_bank_state.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_col_mach.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_mc.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_rank_cntrl.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_rank_common.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_rank_mach.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/controller/mig_7series_v2_3_round_robin_arb.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_buf.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_dec_fix.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_gen.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_ecc_merge_enc.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ecc/mig_7series_v2_3_fi_xor.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ip_top/mig_7series_v2_3_mem_intfc.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ip_top/mig_7series_v2_3_memc_ui_top_std.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_group_io.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_lane.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_tempmon.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_calib_top.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_if_post_fifo.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy_wrapper.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_of_pre_fifo.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_4lanes.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_init.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal_hr.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_oclkdelay_cal.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_prbs_rdlvl.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_rdlvl.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_top.vhd Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrcal.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl_off_delay.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_prbs_gen.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_lim.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_top.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_mux.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_data.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_samp.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_edge.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_cntlr.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_pd.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_tap_base.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_meta.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_edge_store.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/phy/mig_7series_v2_3_poc_cc.v Successfully
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Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_cmd.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_rd_data.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_top.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/ui/mig_7series_v2_3_ui_wr_data.v Successfully
 ..Successful
Created the file - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/../docs/phy_only_support_readme.txt Successfully
 ..SuccessfulCreated the Top Level File - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/mig_7series_0_temp.vhdCreated the Top Level File - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl/mig_7series_0_temp.vhdCreated the Top Level File - c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0_temp.vhoThe design output files are located in c:/Users/Alain/Documents/1VHDL/com-1824 channel emulator/project_1GB/project_1GB.srcs/sources_1/ip/mig_7series_0/_tmp/mig_7series_0/user_design/rtl and ..user_design/constraints for rtl & ucf files respectively.